From 5263b2bdb0d573a4c001556822b082c0fc80f8af Mon Sep 17 00:00:00 2001
From: Jim Knowler <jim.knowler2@gmail.com>
Date: Tue, 29 Dec 2020 14:37:08 +0000
Subject: [PATCH] TestBench: rename 'nextStep' as 'step'

---
 gtestverilog/lib/TestBench.h             | 12 +++++-------
 gtestverilog/test/TestBench.test.cpp     | 22 +++++++++++-----------
 gtestverilog/tools/generate_testbench.py |  4 ++--
 3 files changed, 18 insertions(+), 20 deletions(-)

diff --git a/gtestverilog/lib/TestBench.h b/gtestverilog/lib/TestBench.h
index 121a3b9..bb8ff5e 100644
--- a/gtestverilog/lib/TestBench.h
+++ b/gtestverilog/lib/TestBench.h
@@ -39,23 +39,23 @@ namespace gtestverilog {
 			for (size_t i=0; i<numTicks; i++) {
 				// rising edge
 				assert(m_core->i_clk == m_clockPolarity);
-				nextStep();
+				step();
 
 				// falling edge
 				assert(m_core->i_clk != m_clockPolarity);
-				nextStep();
+				step();
 			}
 		}
 
 		/// @brief simulate a single half clock step
 		/// @note This will invert the current value on port 'i_clk'
-		void nextStep() {
+		void step() {
 			m_core->i_clk = (m_core->i_clk) ? 0 : 1;
 			m_core->eval();
 
 			m_stepCount += 1;
 
-			onNextStep();
+			onStep();
 		}
 
 		MODULE& core() {
@@ -77,9 +77,7 @@ namespace gtestverilog {
 		}
 
 	protected:
-		virtual void onNextStep() {
-
-		}
+		virtual void onStep() {}
 
 	private:
 		std::unique_ptr<MODULE>		m_core;
diff --git a/gtestverilog/test/TestBench.test.cpp b/gtestverilog/test/TestBench.test.cpp
index 69a5bf0..dda4822 100644
--- a/gtestverilog/test/TestBench.test.cpp
+++ b/gtestverilog/test/TestBench.test.cpp
@@ -37,9 +37,9 @@ TEST(TestBench, ShouldTickMultipleTimes) {
     testBench.tick(10);
 }
 
-TEST(TestBench, ShouldNextStep) {
+TEST(TestBench, ShouldStep) {
     TestBench<TestCore> testBench;
-    testBench.nextStep();
+    testBench.step();
 }
 
 TEST(TestBench, ShouldInvokeOnStep) {
@@ -47,17 +47,17 @@ TEST(TestBench, ShouldInvokeOnStep) {
     public:
         int counter = 0;
 
-        virtual void onNextStep() {
+        virtual void onStep() {
             counter += 1;
         }
     };
 
     MyTestBench testBench;
 
-    testBench.nextStep();
+    testBench.step();
     ASSERT_EQ(1, testBench.counter);
 
-    testBench.nextStep();
+    testBench.step();
     ASSERT_EQ(2, testBench.counter);
 }
 
@@ -71,10 +71,10 @@ TEST(TestBench, ShouldGetStepCount) {
     TestBench<TestCore> testBench;
     ASSERT_EQ(0, testBench.stepCount());
 
-    testBench.nextStep();
+    testBench.step();
     ASSERT_EQ(1, testBench.stepCount());
 
-    testBench.nextStep();
+    testBench.step();
     ASSERT_EQ(2, testBench.stepCount());
 
     testBench.tick(3);
@@ -88,10 +88,10 @@ TEST(TestBench, ShouldSetClockPolarity0) {
     testBench.setClockPolarity(0);
     ASSERT_EQ(0, core.i_clk);
 
-    testBench.nextStep();
+    testBench.step();
     ASSERT_EQ(1, core.i_clk);
 
-    testBench.nextStep();
+    testBench.step();
     ASSERT_EQ(0, core.i_clk);
 
     testBench.tick();
@@ -105,10 +105,10 @@ TEST(TestBench, ShouldSetClockPolarity1) {
     testBench.setClockPolarity(1);
     ASSERT_EQ(1, core.i_clk);
 
-    testBench.nextStep();
+    testBench.step();
     ASSERT_EQ(0, core.i_clk);
 
-    testBench.nextStep();
+    testBench.step();
     ASSERT_EQ(1, core.i_clk);
 
     testBench.tick();
diff --git a/gtestverilog/tools/generate_testbench.py b/gtestverilog/tools/generate_testbench.py
index 936a60f..290df26 100644
--- a/gtestverilog/tools/generate_testbench.py
+++ b/gtestverilog/tools/generate_testbench.py
@@ -60,7 +60,7 @@ def write_source_file():
 
     source_middle = """
     
-    void {name}::onNextStep() {{
+    void {name}::onStep() {{
         using namespace gtestverilog;
 
         Step step;
@@ -127,7 +127,7 @@ def write_header_file():
     class {name} : public ::gtestverilog::TestBench<{verilated_name}> {{
     public:
 
-        virtual void onNextStep() override;
+        virtual void onStep() override;
 
         ::gtestverilog::Trace trace;