From c8df5ae055631baa4cf4dbf48c3b1a8d9f780d3f Mon Sep 17 00:00:00 2001
From: Jim Knowler <jim.knowler2@gmail.com>
Date: Tue, 29 Dec 2020 14:34:13 +0000
Subject: [PATCH] TestBench: add support for clock polarity

---
 gtestverilog/lib/TestBench.h         | 23 +++++++++++++-----
 gtestverilog/test/TestBench.test.cpp | 35 ++++++++++++++++++++++++++++
 2 files changed, 52 insertions(+), 6 deletions(-)

diff --git a/gtestverilog/lib/TestBench.h b/gtestverilog/lib/TestBench.h
index 578e56f..121a3b9 100644
--- a/gtestverilog/lib/TestBench.h
+++ b/gtestverilog/lib/TestBench.h
@@ -15,11 +15,11 @@ namespace gtestverilog {
 		TestBench(void) {
 			m_core = std::make_unique<MODULE>();
 			
-			m_stepCount = 0;
+			m_stepCount = 0;	
 			
 			m_core->i_reset_n = 1;
-			m_core->i_clk = 0;
-			m_core->eval();
+			
+			setClockPolarity(0);
 		}
 
 		~TestBench(void) {
@@ -38,11 +38,11 @@ namespace gtestverilog {
 		void tick(size_t numTicks = 1) {
 			for (size_t i=0; i<numTicks; i++) {
 				// rising edge
-				assert(m_core->i_clk == 0);
+				assert(m_core->i_clk == m_clockPolarity);
 				nextStep();
 
 				// falling edge
-				assert(m_core->i_clk == 1);
+				assert(m_core->i_clk != m_clockPolarity);
 				nextStep();
 			}
 		}
@@ -66,15 +66,26 @@ namespace gtestverilog {
 			return m_stepCount;
 		}
 
+		/// @brief set the polarity of i_clk
+		/// @value polarity the value of i_clk in IDLE state (either 0 or 1)
+		void setClockPolarity(int polarity) {
+			assert((polarity==1) || (polarity==0));
+			m_clockPolarity = polarity;
+
+			m_core->i_clk = m_clockPolarity;
+			m_core->eval();
+		}
+
 	protected:
 		virtual void onNextStep() {
 
 		}
 
 	private:
-		uint64_t    m_stepCount;
 		std::unique_ptr<MODULE>		m_core;
 
+		uint64_t    m_stepCount;
+		int 		m_clockPolarity;
 	};
 
 }
\ No newline at end of file
diff --git a/gtestverilog/test/TestBench.test.cpp b/gtestverilog/test/TestBench.test.cpp
index 7e2651a..69a5bf0 100644
--- a/gtestverilog/test/TestBench.test.cpp
+++ b/gtestverilog/test/TestBench.test.cpp
@@ -79,4 +79,39 @@ TEST(TestBench, ShouldGetStepCount) {
 
     testBench.tick(3);
     ASSERT_EQ(8, testBench.stepCount());
+}
+
+TEST(TestBench, ShouldSetClockPolarity0) {
+    TestBench<TestCore> testBench;
+    auto& core = testBench.core();
+
+    testBench.setClockPolarity(0);
+    ASSERT_EQ(0, core.i_clk);
+
+    testBench.nextStep();
+    ASSERT_EQ(1, core.i_clk);
+
+    testBench.nextStep();
+    ASSERT_EQ(0, core.i_clk);
+
+    testBench.tick();
+    ASSERT_EQ(0, core.i_clk);
+}
+
+TEST(TestBench, ShouldSetClockPolarity1) {
+    TestBench<TestCore> testBench;
+    auto& core = testBench.core();
+
+    testBench.setClockPolarity(1);
+    ASSERT_EQ(1, core.i_clk);
+
+    testBench.nextStep();
+    ASSERT_EQ(0, core.i_clk);
+
+    testBench.nextStep();
+    ASSERT_EQ(1, core.i_clk);
+
+    testBench.tick();
+    ASSERT_EQ(1, core.i_clk);
+
 }
\ No newline at end of file