From fa33866012db604274dbb74e1075051a79d55cc7 Mon Sep 17 00:00:00 2001
From: Jim Knowler <jim.knowler2@gmail.com>
Date: Tue, 16 Mar 2021 10:55:13 +0000
Subject: [PATCH] TraceBuilder: signal() - add support for vector<uint32_t>

---
 gtestverilog/lib/TraceBuilder.cpp       | 16 ++++++++++++++++
 gtestverilog/lib/TraceBuilder.h         |  4 ++++
 gtestverilog/test/TraceBuilder.test.cpp | 17 +++++++++++++++++
 3 files changed, 37 insertions(+)

diff --git a/gtestverilog/lib/TraceBuilder.cpp b/gtestverilog/lib/TraceBuilder.cpp
index beebda6..a498bf1 100644
--- a/gtestverilog/lib/TraceBuilder.cpp
+++ b/gtestverilog/lib/TraceBuilder.cpp
@@ -107,6 +107,22 @@ namespace gtestverilog {
         return *this;
     }
 
+    TraceBuilder& TraceBuilder::signal(const std::vector<uint32_t>& stepValues) {
+        if (!currentPort) {
+            throw std::logic_error("unable to add signal without current port");
+        }
+
+        if (stepValues.size() == 0) {
+            throw std::logic_error("unable to add zero-length signal");
+        }
+
+        concat();
+
+        currentSignal.insert(currentSignal.end(), stepValues.begin(), stepValues.end());
+
+        return *this;
+    }
+
     TraceBuilder& TraceBuilder::repeat(size_t repetitions) {
         applyModifier([=](std::vector<PortValue>& signal) {
             std::vector<PortValue> newSignal;
diff --git a/gtestverilog/lib/TraceBuilder.h b/gtestverilog/lib/TraceBuilder.h
index 9362a0a..457f65a 100644
--- a/gtestverilog/lib/TraceBuilder.h
+++ b/gtestverilog/lib/TraceBuilder.h
@@ -28,6 +28,10 @@ namespace gtestverilog {
         /// @note subsequent modifiers will be applied only to this signal, until concat() or allPorts() are called
         TraceBuilder& signal(const std::initializer_list<uint32_t>& stepValues);
 
+        /// @brief append a new signal to the current port
+        /// @note subsequent modifiers will be applied only to this signal, until concat() or allPorts() are called
+        TraceBuilder& signal(const std::vector<uint32_t>& stepValues);
+
         /// @brief repeat the current signal being added to the current port
         /// @example TraceBuilder().port(myPort).signal("abcd").repeat(2) => "abcdabcd" 
         TraceBuilder& repeat(size_t repetitions);
diff --git a/gtestverilog/test/TraceBuilder.test.cpp b/gtestverilog/test/TraceBuilder.test.cpp
index 3c719de..ae80cba 100644
--- a/gtestverilog/test/TraceBuilder.test.cpp
+++ b/gtestverilog/test/TraceBuilder.test.cpp
@@ -282,3 +282,20 @@ TEST(TraceBuilder, ShouldFailToAddEmptyPortValueSignal) {
              .port(test_port_0).signal({})
     );
 }
+
+TEST(TraceBuilder, ShouldAddSignalFromVectorAndInitialiserList) {
+    std::vector<uint32_t> steps1 = {3, 1};
+    Trace trace = TraceBuilder()
+        .port(test_port_1).signal(steps1).repeatEachStep(2).signal({2, 4}).repeatEachStep(2);
+    
+    const std::vector<Step>& steps = trace.getSteps();
+    ASSERT_EQ(steps.size(), 8);
+    ASSERT_EQ(std::get<uint32_t>(steps[0].port(test_port_1)), 3);
+    ASSERT_EQ(std::get<uint32_t>(steps[1].port(test_port_1)), 3);
+    ASSERT_EQ(std::get<uint32_t>(steps[2].port(test_port_1)), 1);
+    ASSERT_EQ(std::get<uint32_t>(steps[3].port(test_port_1)), 1);
+    ASSERT_EQ(std::get<uint32_t>(steps[4].port(test_port_1)), 2);
+    ASSERT_EQ(std::get<uint32_t>(steps[5].port(test_port_1)), 2);
+    ASSERT_EQ(std::get<uint32_t>(steps[6].port(test_port_1)), 4);
+    ASSERT_EQ(std::get<uint32_t>(steps[7].port(test_port_1)), 4);
+}
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