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cpu_m68k.asm
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cpu_m68k.asm
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; cpu_m68k.asm - 6502 CPU emulation for Atari Falcon port
;
; Copyright (C) 2001 Karel Rous (empty head)
; Copyright (C) 2001-2003 Atari800 development team (see DOC/CREDITS)
;
; This file is part of the Atari800 emulator project which emulates
; the Atari 400, 800, 800XL, 130XE, and 5200 8-bit computers.
;
; Atari800 is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation; either version 2 of the License, or
; (at your option) any later version.
;
; Atari800 is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with Atari800; if not, write to the Free Software
; Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
;
; Last changes : 30th March 2003, gerhard.janka
; P65C02 ; we emulate this version of processor (6502 has a bug in jump code,
; you can emulate this bug by commenting out this line :)
; PROFILE ; fills the 'instruction_count' array for instruction profiling
; MONITOR_BREAK ; jump to monitor at break
; CRASH_MENU ; enable crash menu output
; CYCLE_EXACT ; !NO_CYCLE_EXACT :)
; NEW_CYCLE_EXACT ; !NO_NEW_CYCLE_EXACT :)
OPT P=68040,L1,O+,W-
output cpu_m68k.o
xref _CART_BountyBob2
xref _CART_BountyBob1
xref _GTIA_GetByte
xref _POKEY_GetByte
xref _PIA_GetByte
xref _ANTIC_GetByte
xref _CART_GetByte
xref _GTIA_PutByte
xref _POKEY_PutByte
xref _PIA_PutByte
xref _ANTIC_PutByte
xref _CART_PutByte
xref _Atari800_RunEsc
xref _Atari800_Exit
xref _exit
xref _wsync_halt ;CPU is stopped
ifd NEW_CYCLE_EXACT
xref _delayed_wsync
xref _antic2cpu_ptr
xref _cur_screen_pos
endc
xref _xpos
xref _xpos_limit
xdef _regPC
xdef _regA
xdef _regP ;/* Processor Status Byte (Partial) */
xdef _regS
xdef _regX
xdef _regY
xref _memory
xref _attrib
ifd PROFILE
xref _instruction_count
endc
ifd MONITOR_BREAK
xdef _remember_PC
xdef _remember_PC_curpos
ifd NEW_CYCLE_EXACT
xdef _remember_xpos
xdef _remember_xpos_curpos
endc
xdef _remember_JMP
xdef _remember_jmp_curpos
xref _ypos_break_addr
xref _ypos
xref _break_addr
xref _break_step
xref _break_ret
xref _break_cim
xref _break_here
xref _brkhere
xref _ret_nesting
endc
ifd CRASH_MENU
xref _crash_code
xref _crash_address
xref _crash_afterCIM
endc
xdef _IRQ
xdef _NMI
xdef _RTI
xdef _GO
xdef _CPUGET
xdef _CPUPUT
xdef _CPU_INIT
xdef _cycles ;temporarily needed outside :)
xdef _cim_encountered
xdef _rts_handler
ifd MONITOR_BREAK
rem_pc_steps equ 64 ; has to be equal to REMEMBER_PC_STEPS
rem_jmp_steps equ 16 ; has to be equal to REMEMBER_JMP_STEPS
remember_PC
_remember_PC
ds.w rem_pc_steps ;REMEMBER_PC_STEPS
remember_PC_curpos
_remember_PC_curpos
ds.l 1
remember_xpos
_remember_xpos
ds.l rem_pc_steps ;REMEMBER_PC_STEPS
remember_xpos_curpos
_remember_xpos_curpos
ds.l 1
remember_JMP
_remember_JMP
ds.w rem_jmp_steps ;REMEMBER_JMP_STEPS
remember_jmp_curpos
_remember_jmp_curpos
ds.l 1
endc
even
cnop 0,4 ; doubleword alignment
regP
ds.b 1 ;
_regP ds.b 1 ; CCR
regA
ds.b 1
_regA ds.b 1 ; A
regX
ds.b 1
_regX ds.b 1 ; X
regY
ds.b 1
_regY ds.b 1 ; Y
regPC
_regPC ds.w 1 ; PC
regS
ds.b 1
_regS ds.b 1 ; stack
IRQ
_IRQ ds.b 1
ds.b 1 ; dummy
_cim_encountered
ds.b 1
_rts_handler
ds.l 1
even
memory_pointer equr a5
attrib_pointer equr a4
PC6502 equr a2
CD equr a6 ; cycles counter up
ZFLAG equr d1 ; Bit 0..7
NFLAG equr d1 ; Bit 8..15
VFLAG equr d6 ; Bit 7
DFLAG equr d6 ; Bit 15
CFLAG equr d5 ; Bit 0..7, ( 1 = ff )
A equr d2
X equr d3
Y equr d4
;d0 contains usually adress where we are working or temporary value
;d7 contains is a working register or adress
LoHi macro ;change order of lo and hi byte (address)
ror.w #8,\1
endm
; ==========================================================
; Emulated Registers and Flags are kept local to this module
; ==========================================================
; regP=processor flags; regPC=PC; regA=A; regX=X; regY=Y
UPDATE_GLOBAL_REGS macro
sub.l memory_pointer,PC6502
movem.w d0/d2-d4/a2,regP ; d0->regP, d2-d4 (A,X,Y) a2 (regPC)
endm
; PC=regPC; A=regA; X=regX; Y=regY
UPDATE_LOCAL_REGS macro
moveq #0,d7
move.w regP,d0
move.w regA,d2
move.w regX,d3
move.w regY,d4
move.w regPC,d7
move.l memory_pointer,PC6502
add.l d7,PC6502
lea OPMODE_TABLE,a3
btst #D_FLAGB,_regP
beq.s .upd_end
lea OPMODE_TABLE_D,a3
.upd_end:
endm
_Local_GetByte:
move.l d7,d1
moveq #0,d0
move.b d1,d0
lsr.w #8,d1
move.b (HIxTable,d1.l),d1
; jmp ([GetTable,PC,d1.l*4])
move.w (GetTable,PC,d1.l*2),d1
jmp (GetTable,d1.w)
GetTable:
dc.w GetNone-GetTable,GetGTIA-GetTable
dc.w GetPOKEY-GetTable,GetPIA-GetTable
dc.w GetANTIC-GetTable,GetCART-GetTable
dc.w ItsBob1-GetTable,ItsBob2-GetTable
GetNone:
st d0 ; higher bytes are 0 from before
rts
GetGTIA:
move.l d0,-(a7)
jsr _GTIA_GetByte
addq.l #4,a7
rts
GetPOKEY:
move.l d0,-(a7)
jsr _POKEY_GetByte
addq.l #4,a7
rts
GetPIA:
move.l d0,-(a7)
jsr _PIA_GetByte
addq.l #4,a7
rts
GetANTIC:
move.l d0,-(a7)
jsr _ANTIC_GetByte
addq.l #4,a7
rts
GetCART:
move.l d0,-(a7)
jsr _CART_GetByte
addq.l #4,a7
rts
ItsBob2:
move.w d7,-(a7)
clr.w -(a7)
jsr _CART_BountyBob2
addq.l #4,a7
moveq #0,d0
rts
ItsBob1:
move.w d7,-(a7)
clr.w -(a7)
jsr _CART_BountyBob1
addq.l #4,a7
moveq #0,d0
rts
_Local_PutByte:
moveq #0,d1
move.w d7,d1
lsr.w #8,d1
move.b (HIxTable,d1.l),d1
jmp ([PutTable,PC,d1.l*4])
PutTable:
dc.l PutNone,PutGTIA,PutPOKEY,PutPIA
dc.l PutANTIC,PutCART,ItsBob1,ItsBob2
PutNone:
moveq #0,d0
rts
PutGTIA:
move.b d0,d1
move.l d1,-(a7)
move.b d7,d1
move.l d1,-(a7)
ifd CYCLE_EXACT
move.l CD,_xpos
endc
jsr _GTIA_PutByte
addq.l #8,a7
rts
PutPOKEY:
move.b d0,d1
move.l d1,-(a7)
move.b d7,d1
move.l d1,-(a7)
ifd CYCLE_EXACT
move.l CD,_xpos
endc
jsr _POKEY_PutByte
addq.l #8,a7
rts
PutPIA:
move.b d0,d1
move.l d1,-(a7)
move.b d7,d1
move.l d1,-(a7)
jsr _PIA_PutByte
addq.l #8,a7
rts
PutANTIC:
move.b d0,d1
move.l d1,-(a7)
move.b d7,d1
move.l d1,-(a7)
move.l CD,_xpos
jsr _ANTIC_PutByte
move.l _xpos,CD
addq.l #8,a7
rts
PutCART:
move.b d0,d1
move.l d1,-(a7)
move.b d7,d1
move.l d1,-(a7)
jsr _CART_PutByte
addq.l #8,a7
rts
HIxNone equ 0
HIxGTIA8 equ 1
HIxGTIA5 equ 1
HIxPOKEY8 equ 2
HIxPOKEY5 equ 2
HIxPIA8 equ 3
HIxANTIC8 equ 4
HIxCART equ 5
HIxBob1 equ 6
HIxBob2 equ 7
HIxTable:
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; 00..7
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; 04..7
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; 08..b
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; 0c..f
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; 10..7
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; 14..7
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; 18..b
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; 1c..f
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; 20..7
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; 24..7
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; 28..b
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; 2c..f
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; 30..7
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; 34..7
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; 38..b
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; 3c..f
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; 40..7
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; 44..7
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; 48..b
dc.b HIxNone,HIxNone,HIxNone,HIxBob1 ; 4c..f
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; 50..7
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; 54..7
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; 58..b
dc.b HIxNone,HIxNone,HIxNone,HIxBob2 ; 5c..f
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; 60..7
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; 64..7
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; 68..b
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; 6c..f
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; 70..7
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; 74..7
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; 78..b
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; 7c..f
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; 80..7
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; 84..7
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; 88..b
dc.b HIxNone,HIxNone,HIxNone,HIxBob1 ; 8c..f
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; 90..7
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; 94..7
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; 98..b
dc.b HIxNone,HIxNone,HIxNone,HIxBob2 ; 9c..f
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; a0..7
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; a4..7
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; a8..b
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; ac..f
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; b0..7
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; b4..7
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; b8..b
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; bc..f
dc.b HIxGTIA5,HIxNone,HIxNone,HIxNone ; c0..3
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; c4..7
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; c8..b
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; cc..f
dc.b HIxGTIA8,HIxNone,HIxPOKEY8,HIxPIA8 ; d0..3
dc.b HIxANTIC8,HIxCART,HIxNone,HIxNone ; d4..7
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; d8..b
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; dc..f
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; e0..3
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; e4..7
dc.b HIxPOKEY5,HIxNone,HIxNone,HIxPOKEY5 ; e8..b
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; ec..f
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; f0..3
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; f4..7
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; f8..b
dc.b HIxNone,HIxNone,HIxNone,HIxNone ; fc..f
EXE_GETBYTE macro
; move.l d7,-(a7)
jsr _Local_GetByte
; addq.l #4,a7 ;put stack onto right place
endm
EXE_PUTBYTE macro
; clr.l -(a7)
; move.b \1,3(a7) ;byte
jsr _Local_PutByte
; addq.l #8,a7
endm
RMW_GETBYTE macro
ifd CYCLE_EXACT
move.w d7,d0
and.w #$ef1f,d0
cmp.w #$c01a,d0
bne.s .normal_get
EXE_GETBYTE
subq.l #1,CD
move.l d0,-(a7)
EXE_PUTBYTE d0
move.l (a7)+,d0
addq.l #1,CD
bra.s .end_rmw_get
.normal_get:
EXE_GETBYTE
.end_rmw_get:
elseif
EXE_GETBYTE
endc
endm
_CPU_INIT:
ifd MONITOR_BREAK
moveq #0,d0
move.l d0,_remember_PC_curpos
move.l d0,_remember_xpos_curpos
move.l d0,_remember_jmp_curpos
endc
moveq #1,d0 ; set regS to page 1
move.b d0,regS
rts
;these are bit in MC68000 CCR register
NB68 equ 3
EB68 equ 4 ;X
ZB68 equ 2
OB68 equ 1
CB68 equ 0
WSYNC_C equ 106
N_FLAG equ $80
N_FLAGN equ $7f
N_FLAGB equ 7
V_FLAG equ $40
V_FLAGN equ $bf
V_FLAGB equ 6
G_FLAG equ $20
G_FLAGB equ 5
B_FLAG equ $10
B_FLAGN equ $ef
B_FLAGB equ 4
D_FLAG equ $08
D_FLAGN equ $f7
D_FLAGB equ 3
I_FLAG equ $04
I_FLAGN equ $fb
I_FLAGB equ 2
Z_FLAG equ $02
Z_FLAGN equ $fd
Z_FLAGB equ 1
C_FLAG equ $01
C_FLAGN equ $fe
C_FLAGB equ 0
VCZN_FLAGS equ $c3
VCZN_FLAGSN equ $3c
SetI macro
ori.b #I_FLAG,_regP
endm
ClrI macro
andi.b #I_FLAGN,_regP
endm
SetB macro
ori.b #B_FLAG,_regP
endm
SetD macro
ori.b #D_FLAG,_regP
lea OPMODE_TABLE_D,a3
endm
ClrD macro
andi.b #D_FLAGN,_regP
lea OPMODE_TABLE,a3
endm
;static UBYTE N; /* bit7 zero (0) or bit 7 non-zero (1) */
;static UBYTE Z; /* zero (0) or non-zero (1) */
;static UBYTE V;
;static UBYTE C; /* zero (0) or one(1) */
isRAM equ 0
isROM equ 1
isHARDWARE equ 2
;/*
; * The following array is used for 6502 instruction profiling
; */
;int instruction_count[256];
;UBYTE memory[65536];
;UBYTE attrib[65536];
;/*
; ===============================================================
; Z flag: This actually contains the result of an operation which
; would modify the Z flag. The value is tested for
; equality by the BEQ and BNE instruction.
; ===============================================================
;*/
; Bit : 76543210
; 68000 : ***XNZVC
; _RegP : NV*BDIZC
ConvertSTATUS_RegP macro
move.b _regP,\1 ;put flag BDI into d0
andi.b #VCZN_FLAGSN,\1 ; clear overflow, carry, zero & negative flag
tst.b CFLAG
beq.s .SETC\@
addq.b #1,\1
.SETC\@
tst.w NFLAG
bpl.s .SETN\@
; ori.b #N_FLAG,\1
tas \1
.SETN\@
tst.b ZFLAG
bne.s .SETZ\@ ; beware! reverse compare is ok
addq.b #2,\1
.SETZ\@
tst.b VFLAG
bpl.s .SETV\@ ; !!!
ori.b #V_FLAG,\1
.SETV\@
endm
ConvertSTATUS_RegP_destroy macro
move.b _regP,\1 ;put flag BDI into d0
andi.b #VCZN_FLAGSN,\1 ; clear overflow, carry, zero & negative flag
lsr.b #7,CFLAG
or.b CFLAG,\1
tst.w NFLAG
bpl.s .SETN\@
; ori.b #N_FLAG,\1
tas \1
.SETN\@
tst.b ZFLAG
bne.s .SETZ\@ ; beware! reverse compare is ok
addq.b #2,\1
.SETZ\@
tst.b VFLAG
bpl.s .SETV\@ ; !!!
ori.b #V_FLAG,\1
.SETV\@
endm
ConvertRegP_STATUS macro
btst #V_FLAGB,\1
sne VFLAG
btst #C_FLAGB,\1
sne CFLAG
move.b \1,NFLAG
lsl.w #8,NFLAG ; sets NFLAG and clears ZFLAG
btst #Z_FLAGB,\1
seq ZFLAG
endm
Call_Atari800_RunEsc macro
; move.l d7,-(a7) !!!TEST!!!
clr.l -(a7) ;!!!TEST!!!
move.b d7,(3,a7) ;!!!TEST!!!
ConvertSTATUS_RegP_destroy d0
UPDATE_GLOBAL_REGS
jsr _Atari800_RunEsc
addq.l #4,a7
UPDATE_LOCAL_REGS
ConvertRegP_STATUS d0
endm
Call_Atari800_Exit_true macro
pea $1.W
jsr _Atari800_Exit
addq.l #4,a7
tst.l d0
bne.s .GOON\@
clr.l -(a7)
jsr _exit
.GOON\@
endm
PLW macro
moveq #0,\2
move.w regS,\2
addq.b #2,\2 ; wrong way around
move.b (memory_pointer,\2.l),\1
asl.w #8,\1
subq.b #1,\2
or.b (memory_pointer,\2.l),\1
addq.b #1,\2
move.b \2,_regS
endm
SetVFLAG macro
st VFLAG
endm
ClrVFLAG macro
clr.b VFLAG
endm
SetCFLAG macro
st CFLAG
endm
ClrCFLAG macro
clr.b CFLAG
endm
CPUGET:
_CPUGET:
ConvertSTATUS_RegP d0
move.b d0,_regP
rts
CPUPUT:
_CPUPUT:
move.b _regP,d0
ConvertRegP_STATUS d0
rts
NMI:
_NMI:
lea _memory,a0
moveq #0,d1
move.w regS,d1
move.b _regPC,(a0,d1.l)
subq.b #1,d1
move.b _regPC+1,(a0,d1.l)
subq.b #1,d1
; move.b _regP,(a0,d1.l) ;put P onto stack
move.b _regP,d0 ; Test
andi.b #B_FLAGN,d0 ; Test
move.b d0,(a0,d1.l) ; Test
subq.b #1,d1
move.b d1,_regS
SetI
;put regPC & Stack pointer adress on its place
move.w (a0,$fffa.l),d1
LoHi d1
move.w d1,_regPC
addq.l #7,_xpos
ifd MONITOR_BREAK
addq.l #1,_ret_nesting
endc
rts
_GO: ;cycles (d0)
; UWORD PC;
; UBYTE S;
; UBYTE A;
; UBYTE X;
; UBYTE Y;
;
; UWORD addr;
; UBYTE data;
;/*
; This used to be in the main loop but has been removed to improve
; execution speed. It does not seem to have any adverse effect on
; the emulation for two reasons:-
;
; 1. NMI's can only be raised in atari_custom.c - there is
; no way an NMI can be generated whilst in this routine.
;
; 2. The timing of the IRQs are not that critical.
;*/
move.l 4(a7),d0
ifd NEW_CYCLE_EXACT
tst.b _wsync_halt
beq.s NO_WS_HALT
moveq.l #WSYNC_C-1,d1 ; TEST : no -1 if bpl.s
cmp.l #-999,_cur_screen_pos
beq.s .now_cmp
move.l _antic2cpu_ptr,a0
move.l (a0,d1*4),d1
.now_cmp:
add.l _delayed_wsync,d1
cmp.l d0,d1
; bpl.s TERM_GO ; TEST
bge TERM_GO ; TEST
addq.l #1,d1 ; TEST : not necessary if bpl.s
move.l d1,_xpos
clr.b _wsync_halt
clr.l _delayed_wsync
elseif
tst.b _wsync_halt
beq.s NO_WS_HALT
moveq.l #WSYNC_C-1,d1 ; TEST : no -1 if bpl.s
cmp.l d0,d1
; bpl.s TERM_GO ; TEST
bge TERM_GO ; TEST
addq.l #1,d1 ; TEST : not necessary if bpl.s
move.l d1,_xpos
clr.b _wsync_halt
endc
NO_WS_HALT:
move.l d0,_xpos_limit ; needed for WSYNC store inside ANTIC
movem.l d2-d7/a2-a6,-(a7)
move.l _xpos,CD
lea _memory,memory_pointer
UPDATE_LOCAL_REGS
ConvertRegP_STATUS d0
lea _attrib,attrib_pointer
tst.b _IRQ ; CPUCHECKIRQ
beq NEXTCHANGE_WITHOUT
move.b d0,d7
; and.b #I_FLAG,d0 ;is interrupt active
btst #I_FLAG,d0
bne NEXTCHANGE_WITHOUT ;yes, no other interrupt
moveq #0,d0
move.w regS,d0 ; push PC and P to stack ( PHW + PHB ) start
move.b _regPC,(memory_pointer,d0.l)
subq.b #1,d0
move.b _regPC+1,(memory_pointer,d0.l)
subq.b #1,d0
; move.b d7,(memory_pointer,d0.l) ;put P onto stack
andi.b #B_FLAGN,d7 ; TEST
move.b d7,(memory_pointer,d0.l) ; TEST
subq.b #1,d0
move.b d0,_regS ; push PC and P to stack ( PHW + PHB ) end
SetI
move.w (memory_pointer,$fffe.l),d0 ; d0 already cleared from before
LoHi d0
move.l d0,PC6502
add.l memory_pointer,PC6502
addq.l #7,CD
clr.b _IRQ ;clear interrupt.....
ifd MONITOR_BREAK
addq.l #1,_ret_nesting
endc
bra NEXTCHANGE_WITHOUT
;/*
; =====================================
; Extract Address if Required by Opcode
; =====================================
;*/
;d0 contains final value for use in program
; addressing macros
NCYCLES_XY macro
cmp.b \1,d7 ; if ( (UBYTE) addr < X,Y ) ncycles++;
; bpl.s .NCY_XY_NC\@
bcc.s .NCY_XY_NC\@ ; !!!
addq.l #1,CD
.NCY_XY_NC\@:
endm
ABSOLUTE macro
move.w (PC6502)+,d7
LoHi d7 ;d7 contains reversed value
endm
ABSOLUTE_X macro
ABSOLUTE
add.w X,d7
endm
ABSOLUTE_X_NCY macro
ABSOLUTE_X \1
NCYCLES_XY X
endm
ABSOLUTE_Y macro
ABSOLUTE
add.w Y,d7
endm
ABSOLUTE_Y_NCY macro
ABSOLUTE_Y \1
NCYCLES_XY Y
endm
IMMEDIATE macro
move.b (PC6502)+,\1
endm
INDIRECT_X macro
move.b (PC6502)+,d7
add.b X,d7
move.w (memory_pointer,d7.l),d7
LoHi d7
endm
INDIRECT_Y macro
move.b (PC6502)+,d7
move.w (memory_pointer,d7.l),d7
LoHi d7 ;swap bytes
add.w Y,d7
endm
INDIRECT_Y_NCY macro
INDIRECT_Y
NCYCLES_XY Y
endm
ZPAGE macro
move.b (PC6502)+,d7
endm
ZPAGE_X macro
move.b (PC6502)+,d7
add.b X,d7
endm
ZPAGE_Y macro
move.b (PC6502)+,d7
add.b Y,d7
endm
; miscellaneous macros
NEXTCHANGE_REG macro
move.b \1,ZFLAG
bra.w NEXTCHANGE_N
endm
; command macros
ROL_C macro
add.b CFLAG,CFLAG
addx.b \1,\1 ;left
scs CFLAG
endm
ROR_C macro
add.b CFLAG,CFLAG
roxr.b #1,\1
scs CFLAG
endm
ASL_C macro
add.b \1,\1 ;left
scs CFLAG
endm
LSR_C macro
lsr.b #1,\1
scs CFLAG
endm
; opcodes
; inofficial opcodes
; unstable inofficial opcodes
opcode_93: ;/* SHA (ab),y [unofficial, UNSTABLE - Store A AND X AND (H+1) ?] */
; /* It seems previous memory value is important - also in 9f */;
addq.l #cy_IndY2,CD
move.b (PC6502)+,d7
addq.b #1,d7
move.b (memory_pointer,d7.l),d0
addq.b #1,d0
and.b A,d0
and.b X,d0
move.w (memory_pointer,d7.l),d7
LoHi d7 ;swap bytes
add.w Y,d7
tst.b (attrib_pointer,d7.l) ; PUTANYBYTE
bne.w A800PUTB
move.b d0,(memory_pointer,d7.l)
bra.w NEXTCHANGE_WITHOUT
opcode_9f: ;/* SHA abcd,y [unofficial, UNSTABLE - Store A AND X AND (H+1) ?] */
addq.l #cy_IndY2,CD
move.w (PC6502)+,d7
move.b d7,d0
LoHi d7 ;d7 contains reversed value
addq.b #1,d0
and.b A,d0
and.b X,d0
add.w Y,d7
tst.b (attrib_pointer,d7.l) ; PUTANYBYTE
bne.w A800PUTB
move.b d0,(memory_pointer,d7.l)
bra.w NEXTCHANGE_WITHOUT
opcode_9e: ;/* SHX abcd,y [unofficial - Store X and (H+1)] (Fox) */
; /* Seems to be stable */
addq.l #cy_IndY2,CD
move.w (PC6502)+,d7
move.b d7,d0
LoHi d7 ;d7 contains reversed value
addq.b #1,d0
and.b X,d0
add.w Y,d7
tst.b (attrib_pointer,d7.l) ; PUTANYBYTE
bne.w A800PUTB
move.b d0,(memory_pointer,d7.l)
bra.w NEXTCHANGE_WITHOUT
opcode_9c: ;/* SHY abcd,x [unofficial - Store Y and (H+1)] (Fox) */
; /* Seems to be stable */
addq.l #cy_AbsX2,CD
move.w (PC6502)+,d7
move.b d7,d0
LoHi d7 ;d7 contains reversed value
addq.b #1,d0
and.b A,d0
and.b Y,d0
add.w X,d7
tst.b (attrib_pointer,d7.l) ; PUTANYBYTE
bne.w A800PUTB
move.b d0,(memory_pointer,d7.l)
bra.w NEXTCHANGE_WITHOUT
opcode_9b: ;/* SHS abcd,y [unofficial, UNSTABLE] (Fox) */
; /* Transfer A AND X to S, then store S AND (H+1)] */
; /* S seems to be stable, only memory values vary */
addq.l #cy_IndY2,CD
move.w (PC6502)+,d7
move.b d7,d0
LoHi d7 ;d7 contains reversed value
move.b A,_regS
and.b X,_regS
addq.b #1,d0
and.b _regS,d0
add.w Y,d7
tst.b (attrib_pointer,d7.l) ; PUTANYBYTE
bne.w A800PUTB
move.b d0,(memory_pointer,d7.l)
bra.w NEXTCHANGE_WITHOUT
; stable inofficial opcodes
opcode_6b: ;/* ARR #ab [unofficial - Acc AND Data, ROR result] */
; not optimized because I think it will never be executed anyway
addq.l #cy_Imm,CD
IMMEDIATE ZFLAG
and.b A,ZFLAG
btst #D_FLAGB,_regP
beq.s .6b_noBCD
; 'BCD fixup'
move.b ZFLAG,d7
ROR_C ZFLAG
move.b ZFLAG,A
move.b d7,VFLAG ;VFLAG
eor.b ZFLAG,VFLAG
and.b #$40,VFLAG
sne VFLAG
move.b A,d7
move.b A,d7
move.b d7,d0
andi.b #15,d0
move.b d7,CFLAG
andi.b #1,CFLAG
add.b CFLAG,d0
cmpi.b #6,d0 ; check for >5
bmi.s .6b_bcd1 ; <=5
move.b A,CFLAG