vitec_cpld_xc9536.ucf

#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "A_CLK"  LOC = "P23"  ;
NET "B_DIR"  LOC = "P6"  ; 
NET "B_OE"  LOC = "P7"  ; 
NET "C_F_in<1>"  LOC = "P8"  ; 
NET "C_F_in<2>"  LOC = "P12"  ; 
NET "C_F_in<3>"  LOC = "P13"  ; 
# C_F<6> does not reach the FPGA at all?
# C_F<4:5>, C_F<7> seem to be ok (but note the swapping in FPGA UCF!)
NET "C_F_out<4>"  LOC = "P14"  ; 
NET "C_F_out<5>"  LOC = "P16"  ;  
NET "C_F_out<6>"  LOC = "P27"  ;
NET "C_F_out<7>"  LOC = "P22"  ; 
NET "DTACK"  LOC = "P40"  ;
NET "I_A<11>"  LOC = "P29"  ;
NET "I_A<12>"  LOC = "P30"  ;
NET "I_A<13>"  LOC = "P31"  ;
NET "I_A<14>"  LOC = "P32"  ;
NET "I_A<15>"  LOC = "P33"  ;
NET "I_AM<0>"  LOC = "P39"  ;
NET "I_AM<1>"  LOC = "P38"  ;
NET "I_AM<2>"  LOC = "P37"  ;
NET "I_AM<3>"  LOC = "P36"  ;
NET "I_AM<4>"  LOC = "P28"  ;
NET "I_AM<5>"  LOC = "P34"  ;
NET "PORT_CLK"  LOC = "P3"  ;
NET "PORT_READ"  LOC = "P5"  ;
NET "SWITCH1<0>"  LOC = "P18"  ;
NET "SWITCH1<1>"  LOC = "P19"  ;
NET "SWITCH1<2>"  LOC = "P20"  ;
NET "SWITCH1<3>"  LOC = "P21"  ;
NET "V_AS"  LOC = "P1"  ;
NET "V_DS<0>"  LOC = "P42"  ;
NET "V_DS<1>"  LOC = "P43"  ;
NET "V_LWORD"  LOC = "P2"  ; 
NET "V_SYSCLK"  LOC = "P44"  ;
NET "V_WRITE"  LOC = "P41"  ;

#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE
#Created by Constraints Editor (xc9536xl-vq44-5) - 2013/07/15
NET "V_SYSCLK" TNM_NET = V_SYSCLK;
TIMESPEC TS_V_SYSCLK = PERIOD "V_SYSCLK" 16 MHz HIGH 50%;