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請問如果用modelsim compile,makefile該怎麼修改,或是matmul.py要怎麼執行,才能運作,感謝!
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合成的部分可以先稍安勿躁 QQ 助教在想辦法 主要是希望合成的環境和 target 要一樣
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基本上 makefile 每一個 rule 只做兩行指令: 你可以先到有 python 的環境執行 matmul.py 把 *.bin 產生出來就好 cd tb/ && python3 matmul.py inputs1 然後再用自己的 verilog compiler 執行但記得把這些資料夾 build/ src/ tb/ 路徑餵給它 不然的話 src code 的路勁建議全部用絕對路徑
cd tb/ && python3 matmul.py inputs1
build/
src/
tb/
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請問如果用modelsim compile,makefile該怎麼修改,或是matmul.py要怎麼執行,才能運作,感謝!
The text was updated successfully, but these errors were encountered: