diff --git a/.github/workflows/runtest.yaml b/.github/workflows/runtest.yaml
index 6fefbc3c4..2ffa1df24 100644
--- a/.github/workflows/runtest.yaml
+++ b/.github/workflows/runtest.yaml
@@ -12,6 +12,10 @@ permissions:
 
 jobs:
    CI_test_run: 
+    strategy:
+      fail-fast: false
+      matrix:
+        compiler: [AC6, CLANG, GCC]
     runs-on: ubuntu-latest    
 
     steps:
@@ -30,6 +34,8 @@ jobs:
 
       - name: Activate vcpkg
         uses: ARM-software/cmsis-actions/vcpkg@v1
+        with:
+          cache: "-${{ matrix.compiler }}"
 
       - name: Activate Arm tool license
         uses: ARM-software/cmsis-actions/armlm@v1
@@ -59,7 +65,7 @@ jobs:
           cd cmsis_build
 
           echo "Load missing pack"
-          csolution list packs -s  test_ac6.csolution.yml -m > required_packs.txt
+          csolution list packs -s  test.csolution.yml -m > required_packs.txt
           
           cat required_packs.txt
           cpackget add -a -f required_packs.txt
@@ -69,13 +75,13 @@ jobs:
           cd Testing/cmsis_build
           echo "Running tests"
 
-          python runall.py -avh $AVH_FVP_PLUGINS/../bin
+          python runall.py -s -g ${{ matrix.compiler }} -avh $AVH_FVP_PLUGINS/../bin
 
       - name: Upload test report
         uses: actions/upload-artifact@v4
         with:
-          name: test-report
-          path: Testing/cmsis_build/summary.html
+          name: test-report_${{ matrix.compiler }}
+          path: Testing/cmsis_build/summary_${{ matrix.compiler }}.html
 
       
       - name: Check error
@@ -83,4 +89,4 @@ jobs:
           cd Testing/cmsis_build
           
           echo "Checking output..."
-          test "$(grep "Error" summary.html | wc -l)" -eq 0
+          test "$(grep "Error" summary_${{ matrix.compiler }}.html | wc -l)" -eq 0
diff --git a/Include/arm_math_types.h b/Include/arm_math_types.h
index 785d2ed16..c10329220 100755
--- a/Include/arm_math_types.h
+++ b/Include/arm_math_types.h
@@ -40,11 +40,19 @@ extern "C"
 #elif defined ( __APPLE_CC__ )
   #pragma GCC diagnostic ignored "-Wold-style-cast"
 
+#elif defined(__clang__)
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wsign-conversion"
+  #pragma GCC diagnostic ignored "-Wconversion"
+  #pragma GCC diagnostic ignored "-Wunused-parameter"
+
 #elif defined ( __GNUC__ )
   #pragma GCC diagnostic push
   #pragma GCC diagnostic ignored "-Wsign-conversion"
   #pragma GCC diagnostic ignored "-Wconversion"
   #pragma GCC diagnostic ignored "-Wunused-parameter"
+  // Disable some code having issue with GCC
+  #define __CMSIS_GCC_H 
 
 #elif defined ( __ICCARM__ )
 
diff --git a/Testing/FrameworkInclude/Timing.h b/Testing/FrameworkInclude/Timing.h
index 86201202c..4ba2b6fd9 100644
--- a/Testing/FrameworkInclude/Timing.h
+++ b/Testing/FrameworkInclude/Timing.h
@@ -1,6 +1,9 @@
 #ifndef _TIMING_H_
 #define _TIMING_H_
 
+#include "RTE_Components.h"
+#include  CMSIS_device_header
+
 #include "Test.h"
 #include "arm_math_types.h"
 #include "arm_math_types_f16.h"
diff --git a/Testing/FrameworkSource/Error.cpp b/Testing/FrameworkSource/Error.cpp
index d18c06202..5e8a79605 100644
--- a/Testing/FrameworkSource/Error.cpp
+++ b/Testing/FrameworkSource/Error.cpp
@@ -30,7 +30,7 @@
 #include "arm_math_types.h"
 #include "arm_math_types_f16.h"
 #include "Error.h"
-
+#include <cinttypes>
 
 namespace Client {
 
diff --git a/Testing/FrameworkSource/Timing.cpp b/Testing/FrameworkSource/Timing.cpp
index c178aac34..9d107b9c1 100644
--- a/Testing/FrameworkSource/Timing.cpp
+++ b/Testing/FrameworkSource/Timing.cpp
@@ -4,63 +4,7 @@
 
 #define SYSTICK_INITIAL_VALUE       0x0FFFFFF
 static uint32_t startCycles=0;
-
-#if   defined ARMCM0
-  #include "ARMCM0.h"
-#elif defined ARMCM0P
-  #include "ARMCM0plus.h"
-#elif defined ARMCM0P_MPU
-  #include "ARMCM0plus_MPU.h"
-#elif defined ARMCM3
-  #include "ARMCM3.h"
-#elif defined ARMCM4
-  #include "ARMCM4.h"
-#elif defined ARMCM4_FP
-  #include "ARMCM4_FP.h"
-#elif defined ARMCM7
-  #include "ARMCM7.h" 
-#elif defined ARMCM7_SP
-  #include "ARMCM7_SP.h"
-#elif defined ARMCM7_DP
-  #include "ARMCM7_DP.h"
-#elif defined (ARMCM33)
-  #include "ARMCM33.h"
-#elif defined (ARMCM33_DSP_FP)
-  #include "ARMCM33_DSP_FP.h"
-#elif defined (ARMCM33_DSP_FP_TZ)
-  #include "ARMCM33_DSP_FP_TZ.h"
-#elif defined ARMSC000
-  #include "ARMSC000.h"
-#elif defined ARMSC300
-  #include "ARMSC300.h"
-#elif defined ARMv8MBL
-  #include "ARMv8MBL.h"
-#elif defined ARMv8MML
-  #include "ARMv8MML.h"
-#elif defined ARMv8MML_DSP
-  #include "ARMv8MML_DSP.h"
-#elif defined ARMv8MML_SP
-  #include "ARMv8MML_SP.h"
-#elif defined ARMv8MML_DSP_SP
-  #include "ARMv8MML_DSP_SP.h"
-#elif defined ARMv8MML_DP
-  #include "ARMv8MML_DP.h"
-#elif defined ARMv8MML_DSP_DP
-  #include "ARMv8MML_DSP_DP.h"
-#elif defined ARMv81MML_DSP_DP_MVE_FP
-  #include "ARMv81MML_DSP_DP_MVE_FP.h"
-#elif defined ARMCM55
-  #include "ARMCM55.h"
-#elif defined ARMCM85
-  #include "ARMCM85.h"
-#elif defined SSE300MPS3
-  #include "SSE300MPS3.h"
-#elif defined ARMv7A
-  /* TODO */
-#else
-  #define NOTIMING
 #endif
-#endif /* CORTEXM*/
 
 #if defined(CORTEXA) || defined(CORTEXR)
 #if !defined(__GNUC_PYTHON__)
diff --git a/Testing/cmsis_build/.gitignore b/Testing/cmsis_build/.gitignore
index 8bc2f7a1c..ae132e74a 100644
--- a/Testing/cmsis_build/.gitignore
+++ b/Testing/cmsis_build/.gitignore
@@ -4,3 +4,4 @@ results*.txt
 *.cbuild.yml
 *.cbuild-idx.yml
 disasm.s
+cprj/
diff --git a/Testing/cmsis_build/RTE/Device/ARMCM0P/ARMCM0plus_gcc.ld b/Testing/cmsis_build/RTE/Device/ARMCM0P/ARMCM0plus_gcc.ld
new file mode 100644
index 000000000..93ed813c8
--- /dev/null
+++ b/Testing/cmsis_build/RTE/Device/ARMCM0P/ARMCM0plus_gcc.ld
@@ -0,0 +1,263 @@
+/*
+ *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+ */
+
+/*---------------------- Flash Configuration ----------------------------------
+  <h> Flash Configuration
+    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+  </h>
+  -----------------------------------------------------------------------------*/
+__ROM_BASE = 0x00000000;
+__ROM_SIZE = 0x00040000;
+
+/*--------------------- Embedded RAM Configuration ----------------------------
+  <h> RAM Configuration
+    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>
+    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+  </h>
+ -----------------------------------------------------------------------------*/
+__RAM_BASE = 0x20000000;
+__RAM_SIZE = 0x00020000;
+
+/*--------------------- Stack / Heap Configuration ----------------------------
+  <h> Stack / Heap Configuration
+    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+  </h>
+  -----------------------------------------------------------------------------*/
+__STACK_SIZE = 0x00000400;
+__HEAP_SIZE  = 0x00000C00;
+
+/*
+ *-------------------- <<< end of configuration section >>> -------------------
+ */
+
+MEMORY
+{
+  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
+  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext          (deprecated)
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+  .text :
+  {
+    KEEP(*(.vectors))
+    *(.text*)
+
+    KEEP(*(.init))
+    KEEP(*(.fini))
+
+    /* .ctors */
+    *crtbegin.o(.ctors)
+    *crtbegin?.o(.ctors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+    *(SORT(.ctors.*))
+    *(.ctors)
+
+    /* .dtors */
+    *crtbegin.o(.dtors)
+    *crtbegin?.o(.dtors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+    *(SORT(.dtors.*))
+    *(.dtors)
+
+    *(.rodata*)
+
+    KEEP(*(.eh_frame*))
+  } > FLASH
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > FLASH
+
+  __exidx_start = .;
+  .ARM.exidx :
+  {
+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+  } > FLASH
+  __exidx_end = .;
+
+  .copy.table :
+  {
+    . = ALIGN(4);
+    __copy_table_start__ = .;
+
+    LONG (LOADADDR(.data))
+    LONG (ADDR(.data))
+    LONG (SIZEOF(.data) / 4)
+
+    /* Add each additional data section here */
+/*
+    LONG (LOADADDR(.data2))
+    LONG (ADDR(.data2))
+    LONG (SIZEOF(.data2) / 4)
+*/
+    __copy_table_end__ = .;
+  } > FLASH
+
+  .zero.table :
+  {
+    . = ALIGN(4);
+    __zero_table_start__ = .;
+
+/*  .bss initialization to zero is already done during C Run-Time Startup.
+    LONG (ADDR(.bss))
+    LONG (SIZEOF(.bss) / 4)
+*/
+
+    /* Add each additional bss section here */
+/*
+    LONG (ADDR(.bss2))
+    LONG (SIZEOF(.bss2) / 4)
+*/
+    __zero_table_end__ = .;
+  } > FLASH
+
+  /*
+   * This __etext variable is kept for backward compatibility with older,
+   * ASM based startup files.
+   */
+  PROVIDE(__etext = LOADADDR(.data));
+
+  .data : ALIGN(4)
+  {
+    __data_start__ = .;
+    *(vtable)
+    *(.data)
+    *(.data.*)
+
+    . = ALIGN(4);
+    /* preinit data */
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP(*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+
+    . = ALIGN(4);
+    /* init data */
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP(*(SORT(.init_array.*)))
+    KEEP(*(.init_array))
+    PROVIDE_HIDDEN (__init_array_end = .);
+
+    . = ALIGN(4);
+    /* finit data */
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP(*(SORT(.fini_array.*)))
+    KEEP(*(.fini_array))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    /* All data end */
+    __data_end__ = .;
+
+  } > RAM AT > FLASH
+
+  /*
+   * Secondary data section, optional
+   *
+   * Remember to add each additional data section
+   * to the .copy.table above to assure proper
+   * initialization during startup.
+   */
+/*
+  .data2 : ALIGN(4)
+  {
+    . = ALIGN(4);
+    __data2_start__ = .;
+    *(.data2)
+    *(.data2.*)
+    . = ALIGN(4);
+    __data2_end__ = .;
+
+  } > RAM2 AT > FLASH
+*/
+
+  .bss :
+  {
+    . = ALIGN(4);
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss.*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+  } > RAM AT > RAM
+
+  /*
+   * Secondary bss section, optional
+   *
+   * Remember to add each additional bss section
+   * to the .zero.table above to assure proper
+   * initialization during startup.
+   */
+/*
+  .bss2 :
+  {
+    . = ALIGN(4);
+    __bss2_start__ = .;
+    *(.bss2)
+    *(.bss2.*)
+    . = ALIGN(4);
+    __bss2_end__ = .;
+  } > RAM2 AT > RAM2
+*/
+
+  .heap (NOLOAD) :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    . = . + __HEAP_SIZE;
+    . = ALIGN(8);
+    __HeapLimit = .;
+  } > RAM
+
+  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (NOLOAD) :
+  {
+    . = ALIGN(8);
+    __StackLimit = .;
+    . = . + __STACK_SIZE;
+    . = ALIGN(8);
+    __StackTop = .;
+  } > RAM
+  PROVIDE(__stack = __StackTop);
+
+  /* Check if data + heap + stack exceeds RAM limit */
+  ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/Testing/cmsis_build/RTE/Device/ARMCM33/ARMCM33_ac6.sct b/Testing/cmsis_build/RTE/Device/ARMCM33/ARMCM33_ac6.sct
new file mode 100644
index 000000000..e0f60de18
--- /dev/null
+++ b/Testing/cmsis_build/RTE/Device/ARMCM33/ARMCM33_ac6.sct
@@ -0,0 +1,123 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc
+; command above MUST be in first line (no comment above!)
+
+;Note: Add '-mcmse' to first line if your software model is "Secure Mode".
+;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse
+
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE      0x00000000
+#define __ROM_SIZE      0x00080000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>
+;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE      0x20000000
+#define __RAM_SIZE      0x00040000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE    0x00000200
+#define __HEAP_SIZE     0x00000C00
+
+/*--------------------- CMSE Veneer Configuration ---------------------------
+; <h> CMSE Veneer Configuration
+;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __CMSEVENEER_SIZE    0x200
+
+/*
+;------------- <<< end of configuration section >>> ---------------------------
+*/
+
+
+/*----------------------------------------------------------------------------
+  User Stack & Heap boundary definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */
+#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */
+
+/* ----------------------------------------------------------------------------
+  Stack seal size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __STACKSEAL_SIZE   ( 8 )
+#else
+#define __STACKSEAL_SIZE   ( 0 )
+#endif
+
+
+/*----------------------------------------------------------------------------
+  Region base & size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )
+#define __CV_SIZE          ( __CMSEVENEER_SIZE )
+#else
+#define __CV_SIZE          ( 0 )
+#endif
+
+#define __RO_BASE          ( __ROM_BASE )
+#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )
+
+#define __RW_BASE          ( __RAM_BASE )
+#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE )
+
+
+/*----------------------------------------------------------------------------
+  Scatter Region definition
+ *----------------------------------------------------------------------------*/
+LR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region
+  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+
+  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {
+    *(.bss.noinit)
+  }
+
+  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
+    *(+RW +ZI)
+  }
+
+#if __HEAP_SIZE > 0
+  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap
+  }
+#endif
+
+  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack
+  }
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack
+  }
+#endif
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers
+  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {
+   *(Veneer$$CMSE)
+  }
+}
+#endif
diff --git a/Testing/cmsis_build/RTE/Device/ARMCM33/ARMCM33_gcc.ld b/Testing/cmsis_build/RTE/Device/ARMCM33/ARMCM33_gcc.ld
new file mode 100644
index 000000000..d275cb755
--- /dev/null
+++ b/Testing/cmsis_build/RTE/Device/ARMCM33/ARMCM33_gcc.ld
@@ -0,0 +1,295 @@
+/*
+ *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+ */
+
+/*---------------------- Flash Configuration ----------------------------------
+  <h> Flash Configuration
+    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+  </h>
+  -----------------------------------------------------------------------------*/
+__ROM_BASE = 0x00000000;
+__ROM_SIZE = 0x00040000;
+
+/*--------------------- Embedded RAM Configuration ----------------------------
+  <h> RAM Configuration
+    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>
+    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+  </h>
+ -----------------------------------------------------------------------------*/
+__RAM_BASE = 0x20000000;
+__RAM_SIZE = 0x00020000;
+
+/*--------------------- Stack / Heap Configuration ----------------------------
+  <h> Stack / Heap Configuration
+    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+  </h>
+  -----------------------------------------------------------------------------*/
+__STACK_SIZE = 0x00000400;
+__HEAP_SIZE  = 0x00000C00;
+
+/*
+ *-------------------- <<< end of configuration section >>> -------------------
+ */
+
+/* ARMv8-M stack sealing:
+   to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0
+ */
+__STACKSEAL_SIZE = 0;
+
+
+MEMORY
+{
+  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
+  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext          (deprecated)
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __StackSeal      (only if ARMv8-M stack sealing is used)
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+  .text :
+  {
+    KEEP(*(.vectors))
+    *(.text*)
+
+    KEEP(*(.init))
+    KEEP(*(.fini))
+
+    /* .ctors */
+    *crtbegin.o(.ctors)
+    *crtbegin?.o(.ctors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+    *(SORT(.ctors.*))
+    *(.ctors)
+
+    /* .dtors */
+    *crtbegin.o(.dtors)
+    *crtbegin?.o(.dtors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+    *(SORT(.dtors.*))
+    *(.dtors)
+
+    *(.rodata*)
+
+    KEEP(*(.eh_frame*))
+  } > FLASH
+
+  /*
+   * SG veneers:
+   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address
+   * must be set, either with the command line option '--section-start' or in a linker script,
+   * to indicate where to place these veneers in memory.
+   */
+/*
+  .gnu.sgstubs :
+  {
+    . = ALIGN(32);
+  } > FLASH
+*/
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > FLASH
+
+  __exidx_start = .;
+  .ARM.exidx :
+  {
+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+  } > FLASH
+  __exidx_end = .;
+
+  .copy.table :
+  {
+    . = ALIGN(4);
+    __copy_table_start__ = .;
+
+    LONG (LOADADDR(.data))
+    LONG (ADDR(.data))
+    LONG (SIZEOF(.data) / 4)
+
+    /* Add each additional data section here */
+/*
+    LONG (LOADADDR(.data2))
+    LONG (ADDR(.data2))
+    LONG (SIZEOF(.data2) / 4)
+*/
+    __copy_table_end__ = .;
+  } > FLASH
+
+  .zero.table :
+  {
+    . = ALIGN(4);
+    __zero_table_start__ = .;
+
+/*  .bss initialization to zero is already done during C Run-Time Startup.
+    LONG (ADDR(.bss))
+    LONG (SIZEOF(.bss) / 4)
+*/
+
+    /* Add each additional bss section here */
+/*
+    LONG (ADDR(.bss2))
+    LONG (SIZEOF(.bss2) / 4)
+*/
+    __zero_table_end__ = .;
+  } > FLASH
+
+  /*
+   * This __etext variable is kept for backward compatibility with older,
+   * ASM based startup files.
+   */
+  PROVIDE(__etext = LOADADDR(.data));
+
+  .data : ALIGN(4)
+  {
+    __data_start__ = .;
+    *(vtable)
+    *(.data)
+    *(.data.*)
+
+    . = ALIGN(4);
+    /* preinit data */
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP(*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+
+    . = ALIGN(4);
+    /* init data */
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP(*(SORT(.init_array.*)))
+    KEEP(*(.init_array))
+    PROVIDE_HIDDEN (__init_array_end = .);
+
+    . = ALIGN(4);
+    /* finit data */
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP(*(SORT(.fini_array.*)))
+    KEEP(*(.fini_array))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    /* All data end */
+    __data_end__ = .;
+
+  } > RAM AT > FLASH
+
+  /*
+   * Secondary data section, optional
+   *
+   * Remember to add each additional data section
+   * to the .copy.table above to assure proper
+   * initialization during startup.
+   */
+/*
+  .data2 : ALIGN(4)
+  {
+    . = ALIGN(4);
+    __data2_start__ = .;
+    *(.data2)
+    *(.data2.*)
+    . = ALIGN(4);
+    __data2_end__ = .;
+
+  } > RAM2 AT > FLASH
+*/
+
+  .bss :
+  {
+    . = ALIGN(4);
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss.*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+  } > RAM AT > RAM
+
+  /*
+   * Secondary bss section, optional
+   *
+   * Remember to add each additional bss section
+   * to the .zero.table above to assure proper
+   * initialization during startup.
+   */
+/*
+  .bss2 :
+  {
+    . = ALIGN(4);
+    __bss2_start__ = .;
+    *(.bss2)
+    *(.bss2.*)
+    . = ALIGN(4);
+    __bss2_end__ = .;
+  } > RAM2 AT > RAM2
+*/
+
+  .heap (NOLOAD) :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    . = . + __HEAP_SIZE;
+    . = ALIGN(8);
+    __HeapLimit = .;
+  } > RAM
+
+  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (NOLOAD) :
+  {
+    . = ALIGN(8);
+    __StackLimit = .;
+    . = . + __STACK_SIZE;
+    . = ALIGN(8);
+    __StackTop = .;
+  } > RAM
+  PROVIDE(__stack = __StackTop);
+
+  /* ARMv8-M stack sealing:
+     to use ARMv8-M stack sealing uncomment '.stackseal' section
+   */
+/*
+  .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (NOLOAD) :
+  {
+    . = ALIGN(8);
+    __StackSeal = .;
+    . = . + 8;
+    . = ALIGN(8);
+  } > RAM
+*/
+
+  /* Check if data + heap + stack exceeds RAM limit */
+  ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/Testing/cmsis_build/RTE/Device/ARMCM33/partition_ARMCM33.h b/Testing/cmsis_build/RTE/Device/ARMCM33/partition_ARMCM33.h
new file mode 100644
index 000000000..a7cb0d73d
--- /dev/null
+++ b/Testing/cmsis_build/RTE/Device/ARMCM33/partition_ARMCM33.h
@@ -0,0 +1,1260 @@
+/**************************************************************************//**
+ * @file     partition_ARMCM33.h
+ * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33
+ * @version  V1.1.1
+ * @date     12. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef PARTITION_ARMCM33_H
+#define PARTITION_ARMCM33_H
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+*/
+
+/*
+// <e>Initialize Security Attribution Unit (SAU) CTRL register
+*/
+#define SAU_INIT_CTRL          1
+
+/*
+//   <q> Enable SAU
+//   <i> Value for SAU->CTRL register bit ENABLE
+*/
+#define SAU_INIT_CTRL_ENABLE   1
+
+/*
+//   <o> When SAU is disabled
+//     <0=> All Memory is Secure
+//     <1=> All Memory is Non-Secure
+//   <i> Value for SAU->CTRL register bit ALLNS
+//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
+*/
+#define SAU_INIT_CTRL_ALLNS  0
+
+/*
+// </e>
+*/
+
+/*
+// <h>Initialize Security Attribution Unit (SAU) Address Regions
+// <i>SAU configuration specifies regions to be one of:
+// <i> - Secure and Non-Secure Callable
+// <i> - Non-Secure
+// <i>Note: All memory regions not configured by SAU are Secure
+*/
+#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */
+
+/*
+//   <e>Initialize SAU Region 0
+//   <i> Setup SAU Region 0 memory attributes
+*/
+#define SAU_INIT_REGION0    1
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END0       0x001FFFFF      /* end address of SAU region 0 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC0       1
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 1
+//   <i> Setup SAU Region 1 memory attributes
+*/
+#define SAU_INIT_REGION1    1
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START1     0x00200000
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END1       0x003FFFFF
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC1       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 2
+//   <i> Setup SAU Region 2 memory attributes
+*/
+#define SAU_INIT_REGION2    1
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START2     0x20200000
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END2       0x203FFFFF
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC2       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 3
+//   <i> Setup SAU Region 3 memory attributes
+*/
+#define SAU_INIT_REGION3    1
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START3     0x40000000
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END3       0x40040000
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC3       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 4
+//   <i> Setup SAU Region 4 memory attributes
+*/
+#define SAU_INIT_REGION4    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START4     0x00000000      /* start address of SAU region 4 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END4       0x00000000      /* end address of SAU region 4 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC4       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 5
+//   <i> Setup SAU Region 5 memory attributes
+*/
+#define SAU_INIT_REGION5    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START5     0x00000000
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END5       0x00000000
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC5       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 6
+//   <i> Setup SAU Region 6 memory attributes
+*/
+#define SAU_INIT_REGION6    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START6     0x00000000
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END6       0x00000000
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC6       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 7
+//   <i> Setup SAU Region 7 memory attributes
+*/
+#define SAU_INIT_REGION7    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START7     0x00000000
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END7       0x00000000
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC7       0
+/*
+//   </e>
+*/
+
+/*
+// </h>
+*/
+
+/*
+// <e>Setup behaviour of Sleep and Exception Handling
+*/
+#define SCB_CSR_AIRCR_INIT  1
+
+/*
+//   <o> Deep Sleep can be enabled by
+//     <0=>Secure and Non-Secure state
+//     <1=>Secure state only
+//   <i> Value for SCB->CSR register bit DEEPSLEEPS
+*/
+#define SCB_CSR_DEEPSLEEPS_VAL  1
+
+/*
+//   <o>System reset request accessible from
+//     <0=> Secure and Non-Secure state
+//     <1=> Secure state only
+//   <i> Value for SCB->AIRCR register bit SYSRESETREQS
+*/
+#define SCB_AIRCR_SYSRESETREQS_VAL  1
+
+/*
+//   <o>Priority of Non-Secure exceptions is
+//     <0=> Not altered
+//     <1=> Lowered to 0x80-0xFF
+//   <i> Value for SCB->AIRCR register bit PRIS
+*/
+#define SCB_AIRCR_PRIS_VAL      1
+
+/*
+//   <o>BusFault, HardFault, and NMI target
+//     <0=> Secure state
+//     <1=> Non-Secure state
+//   <i> Value for SCB->AIRCR register bit BFHFNMINS
+*/
+#define SCB_AIRCR_BFHFNMINS_VAL 0
+
+/*
+// </e>
+*/
+
+/*
+// <e>Setup behaviour of Floating Point Unit
+*/
+#define TZ_FPU_NS_USAGE 1
+
+/*
+// <o>Floating Point Unit usage
+//     <0=> Secure state only
+//     <3=> Secure and Non-Secure state
+//   <i> Value for SCB->NSACR register bits CP10, CP11
+*/
+#define SCB_NSACR_CP10_11_VAL       3
+
+/*
+// <o>Treat floating-point registers as Secure
+//     <0=> Disabled
+//     <1=> Enabled
+//   <i> Value for FPU->FPCCR register bit TS
+*/
+#define FPU_FPCCR_TS_VAL            0
+
+/*
+// <o>Clear on return (CLRONRET) accessibility
+//     <0=> Secure and Non-Secure state
+//     <1=> Secure state only
+//   <i> Value for FPU->FPCCR register bit CLRONRETS
+*/
+#define FPU_FPCCR_CLRONRETS_VAL     0
+
+/*
+// <o>Clear floating-point caller saved registers on exception return
+//     <0=> Disabled
+//     <1=> Enabled
+//   <i> Value for FPU->FPCCR register bit CLRONRET
+*/
+#define FPU_FPCCR_CLRONRET_VAL      1
+
+/*
+// </e>
+*/
+
+/*
+// <h>Setup Interrupt Target
+*/
+
+/*
+//   <e>Initialize ITNS 0 (Interrupts 0..31)
+*/
+#define NVIC_INIT_ITNS0    1
+
+/*
+// Interrupts 0..31
+//   <o.0>  Interrupt 0   <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 1   <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 2   <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 3   <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 4   <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 5   <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 6   <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 7   <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 8   <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 9   <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 10  <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 11  <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 12  <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 13  <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 14  <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 15  <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 16  <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 17  <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 18  <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 19  <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 20  <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 21  <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 22  <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 23  <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 24  <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 25  <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 26  <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 27  <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 28  <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 29  <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 30  <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 31  <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS0_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 1 (Interrupts 32..63)
+*/
+#define NVIC_INIT_ITNS1    1
+
+/*
+// Interrupts 32..63
+//   <o.0>  Interrupt 32  <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 33  <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 34  <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 35  <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 36  <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 37  <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 38  <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 39  <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 40  <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 41  <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 42  <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 43  <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 44  <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 45  <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 46  <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 47  <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 48  <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 49  <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 50  <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 51  <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 52  <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 53  <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 54  <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 55  <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 56  <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 57  <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 58  <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 59  <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 60  <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 61  <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 62  <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 63  <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS1_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 2 (Interrupts 64..95)
+*/
+#define NVIC_INIT_ITNS2    0
+
+/*
+// Interrupts 64..95
+//   <o.0>  Interrupt 64  <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 65  <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 66  <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 67  <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 68  <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 69  <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 70  <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 71  <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 72  <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 73  <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 74  <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 75  <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 76  <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 77  <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 78  <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 79  <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 80  <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 81  <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 82  <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 83  <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 84  <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 85  <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 86  <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 87  <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 88  <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 89  <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 90  <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 91  <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 92  <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 93  <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 94  <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 95  <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS2_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 3 (Interrupts 96..127)
+*/
+#define NVIC_INIT_ITNS3    0
+
+/*
+// Interrupts 96..127
+//   <o.0>  Interrupt 96  <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 97  <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 98  <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 99  <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 100 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 101 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 102 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 103 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 104 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 105 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS3_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 4 (Interrupts 128..159)
+*/
+#define NVIC_INIT_ITNS4    0
+
+/*
+// Interrupts 128..159
+//   <o.0>  Interrupt 128 <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 129 <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 130 <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 131 <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 132 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 133 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 134 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 135 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 136 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 137 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS4_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 5 (Interrupts 160..191)
+*/
+#define NVIC_INIT_ITNS5    0
+
+/*
+// Interrupts 160..191
+//   <o.0>  Interrupt 160 <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 161 <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 162 <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 163 <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 164 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 165 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 166 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 167 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 168 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 169 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS5_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 6 (Interrupts 192..223)
+*/
+#define NVIC_INIT_ITNS6    0
+
+/*
+// Interrupts 192..223
+//   <o.0>  Interrupt 192 <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 193 <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 194 <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 195 <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 196 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 197 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 198 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 199 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 200 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 201 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS6_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 7 (Interrupts 224..255)
+*/
+#define NVIC_INIT_ITNS7    0
+
+/*
+// Interrupts 224..255
+//   <o.0>  Interrupt 224 <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 225 <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 226 <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 227 <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 228 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 229 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 230 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 231 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 232 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 233 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS7_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 8 (Interrupts 256..287)
+*/
+#define NVIC_INIT_ITNS8    0
+
+/*
+// Interrupts 256..287
+//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS8_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 9 (Interrupts 288..319)
+*/
+#define NVIC_INIT_ITNS9    0
+
+/*
+// Interrupts 288..319
+//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS9_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 10 (Interrupts 320..351)
+*/
+#define NVIC_INIT_ITNS10   0
+
+/*
+// Interrupts 320..351
+//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS10_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 11 (Interrupts 352..383)
+*/
+#define NVIC_INIT_ITNS11   0
+
+/*
+// Interrupts 352..383
+//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS11_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 12 (Interrupts 384..415)
+*/
+#define NVIC_INIT_ITNS12   0
+
+/*
+// Interrupts 384..415
+//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS12_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 13 (Interrupts 416..447)
+*/
+#define NVIC_INIT_ITNS13   0
+
+/*
+// Interrupts 416..447
+//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS13_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 14 (Interrupts 448..479)
+*/
+#define NVIC_INIT_ITNS14   0
+
+/*
+// Interrupts 448..479
+//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS14_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 15 (Interrupts 480..511)
+*/
+#define NVIC_INIT_ITNS15   0
+
+/*
+// Interrupts 480..511
+//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state
+//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state
+//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state
+//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state
+//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state
+//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state
+//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state
+//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state
+//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state
+//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state
+//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state
+//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state
+//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state
+//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state
+//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state
+//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state
+//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state
+//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state
+//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state
+//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state
+//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state
+//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state
+//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state
+//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state
+//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state
+//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state
+//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state
+//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS15_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+// </h>
+*/
+
+
+
+/*
+    max 128 SAU regions.
+    SAU regions are defined in partition.h
+ */
+
+#define SAU_INIT_REGION(n) \
+    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \
+    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \
+    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \
+                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U
+
+/**
+  \brief   Setup a SAU Region
+  \details Writes the region information contained in SAU_Region to the
+           registers SAU_RNR, SAU_RBAR, and SAU_RLAR
+ */
+__STATIC_INLINE void TZ_SAU_Setup (void)
+{
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+
+  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
+    SAU_INIT_REGION(0);
+  #endif
+
+  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
+    SAU_INIT_REGION(1);
+  #endif
+
+  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
+    SAU_INIT_REGION(2);
+  #endif
+
+  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
+    SAU_INIT_REGION(3);
+  #endif
+
+  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
+    SAU_INIT_REGION(4);
+  #endif
+
+  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
+    SAU_INIT_REGION(5);
+  #endif
+
+  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
+    SAU_INIT_REGION(6);
+  #endif
+
+  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
+    SAU_INIT_REGION(7);
+  #endif
+
+  /* repeat this for all possible SAU regions */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+
+  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
+    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
+                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;
+  #endif
+
+  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
+    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |
+                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);
+
+    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |
+                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk          ))                    |
+                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |
+                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
+                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |
+                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);
+  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
+
+  #if defined (__FPU_USED) && (__FPU_USED == 1U) && \
+      defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
+
+    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
+                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
+
+    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
+                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |
+                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
+                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
+  #endif
+
+  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
+    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
+    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
+    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
+    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
+    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
+    NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
+    NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)
+    NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)
+    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)
+    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)
+    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)
+    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)
+    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)
+    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)
+    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)
+    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;
+  #endif
+
+  /* repeat this for all possible ITNS elements */
+
+}
+
+#endif  /* PARTITION_ARMCM33_H */
diff --git a/Testing/cmsis_build/RTE/Device/ARMCM33/startup_ARMCM33.c b/Testing/cmsis_build/RTE/Device/ARMCM33/startup_ARMCM33.c
new file mode 100644
index 000000000..a9432a170
--- /dev/null
+++ b/Testing/cmsis_build/RTE/Device/ARMCM33/startup_ARMCM33.c
@@ -0,0 +1,164 @@
+/******************************************************************************
+ * @file     startup_ARMCM33.c
+ * @brief    CMSIS-Core Device Startup File for Cortex-M33 Device
+ * @version  V3.0.0
+ * @date     06. April 2023
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2023 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM33)
+  #include "ARMCM33.h"
+#else
+  #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+  External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+extern uint32_t __STACK_LIMIT;
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+extern uint32_t __STACK_SEAL;
+#endif
+
+extern __NO_RETURN void __PROGRAM_START(void);
+
+/*----------------------------------------------------------------------------
+  Internal References
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler  (void);
+            void Default_Handler(void);
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler      (void) __attribute__ ((weak));
+void MemManage_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler       (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void SecureFault_Handler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler       (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler        (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
+       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
+  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */
+  Reset_Handler,                            /*     Reset Handler */
+  NMI_Handler,                              /* -14 NMI Handler */
+  HardFault_Handler,                        /* -13 Hard Fault Handler */
+  MemManage_Handler,                        /* -12 MPU Fault Handler */
+  BusFault_Handler,                         /* -11 Bus Fault Handler */
+  UsageFault_Handler,                       /* -10 Usage Fault Handler */
+  SecureFault_Handler,                      /*  -9 Secure Fault Handler */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  SVC_Handler,                              /*  -5 SVCall Handler */
+  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */
+  0,                                        /*     Reserved */
+  PendSV_Handler,                           /*  -2 PendSV Handler */
+  SysTick_Handler,                          /*  -1 SysTick Handler */
+
+  /* Interrupts */
+  Interrupt0_Handler,                       /*   0 Interrupt 0 */
+  Interrupt1_Handler,                       /*   1 Interrupt 1 */
+  Interrupt2_Handler,                       /*   2 Interrupt 2 */
+  Interrupt3_Handler,                       /*   3 Interrupt 3 */
+  Interrupt4_Handler,                       /*   4 Interrupt 4 */
+  Interrupt5_Handler,                       /*   5 Interrupt 5 */
+  Interrupt6_Handler,                       /*   6 Interrupt 6 */
+  Interrupt7_Handler,                       /*   7 Interrupt 7 */
+  Interrupt8_Handler,                       /*   8 Interrupt 8 */
+  Interrupt9_Handler                        /*   9 Interrupt 9 */
+                                            /* Interrupts 10 .. 480 are left out */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler(void)
+{
+  __set_PSP((uint32_t)(&__INITIAL_SP));
+
+  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
+  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));
+#endif
+
+  SystemInit();                             /* CMSIS System Initialization */
+  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */
+}
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wmissing-noreturn"
+#endif
+
+/*----------------------------------------------------------------------------
+  Hard Fault Handler
+ *----------------------------------------------------------------------------*/
+void HardFault_Handler(void)
+{
+  while(1);
+}
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+  while(1);
+}
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang diagnostic pop
+#endif
+
diff --git a/Testing/cmsis_build/RTE/Device/ARMCM33/system_ARMCM33.c b/Testing/cmsis_build/RTE/Device/ARMCM33/system_ARMCM33.c
new file mode 100644
index 000000000..c1cbc8b4b
--- /dev/null
+++ b/Testing/cmsis_build/RTE/Device/ARMCM33/system_ARMCM33.c
@@ -0,0 +1,86 @@
+/**************************************************************************//**
+ * @file     system_ARMCM33.c
+ * @brief    CMSIS Device System Source File for
+ *           ARMCM33 Device
+ * @version  V2.0.0
+ * @date     06. Aril 2023
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2023 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM33)
+  #include "ARMCM33.h"
+  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)
+    #include "partition_ARMCM33.h"
+  #endif
+#else
+  #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
+
+#define  SYSTEM_CLOCK    (XTAL / 2U)
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);
+#endif
+
+#if defined (__FPU_USED) && (__FPU_USED == 1U)
+  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */
+                 (3U << 11U*2U)  );         /* enable CP11 Full Access */
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  TZ_SAU_Setup();
+#endif
+
+  SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/Testing/cmsis_build/RTE/Device/ARMCM4/ARMCM4_ac6.sct b/Testing/cmsis_build/RTE/Device/ARMCM4/ARMCM4_ac6.sct
new file mode 100644
index 000000000..eb67b5fe6
--- /dev/null
+++ b/Testing/cmsis_build/RTE/Device/ARMCM4/ARMCM4_ac6.sct
@@ -0,0 +1,80 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m4 -xc
+; command above MUST be in first line (no comment above!)
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE      0x00000000
+#define __ROM_SIZE      0x00080000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>
+;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE      0x20000000
+#define __RAM_SIZE      0x00040000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE    0x00000200
+#define __HEAP_SIZE     0x00000C00
+
+/*
+;------------- <<< end of configuration section >>> ---------------------------
+*/
+
+
+/*----------------------------------------------------------------------------
+  User Stack & Heap boundary definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE)    /* starts at end of RAM */
+#define __HEAP_BASE    (AlignExpr(+0, 8))           /* starts after RW_RAM section, 8 byte aligned */
+
+
+/*----------------------------------------------------------------------------
+  Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+#define __RO_BASE       __ROM_BASE
+#define __RO_SIZE       __ROM_SIZE
+
+#define __RW_BASE       __RAM_BASE
+#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+LR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region
+  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+
+  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {
+    *(.bss.noinit)
+  }
+
+  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
+    *(+RW +ZI)
+  }
+
+#if __HEAP_SIZE > 0
+  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap
+  }
+#endif
+
+  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack
+  }
+}
diff --git a/Testing/cmsis_build/RTE/Device/ARMCM4/ARMCM4_gcc.ld b/Testing/cmsis_build/RTE/Device/ARMCM4/ARMCM4_gcc.ld
new file mode 100644
index 000000000..93ed813c8
--- /dev/null
+++ b/Testing/cmsis_build/RTE/Device/ARMCM4/ARMCM4_gcc.ld
@@ -0,0 +1,263 @@
+/*
+ *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+ */
+
+/*---------------------- Flash Configuration ----------------------------------
+  <h> Flash Configuration
+    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+  </h>
+  -----------------------------------------------------------------------------*/
+__ROM_BASE = 0x00000000;
+__ROM_SIZE = 0x00040000;
+
+/*--------------------- Embedded RAM Configuration ----------------------------
+  <h> RAM Configuration
+    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>
+    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+  </h>
+ -----------------------------------------------------------------------------*/
+__RAM_BASE = 0x20000000;
+__RAM_SIZE = 0x00020000;
+
+/*--------------------- Stack / Heap Configuration ----------------------------
+  <h> Stack / Heap Configuration
+    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+  </h>
+  -----------------------------------------------------------------------------*/
+__STACK_SIZE = 0x00000400;
+__HEAP_SIZE  = 0x00000C00;
+
+/*
+ *-------------------- <<< end of configuration section >>> -------------------
+ */
+
+MEMORY
+{
+  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
+  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext          (deprecated)
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+  .text :
+  {
+    KEEP(*(.vectors))
+    *(.text*)
+
+    KEEP(*(.init))
+    KEEP(*(.fini))
+
+    /* .ctors */
+    *crtbegin.o(.ctors)
+    *crtbegin?.o(.ctors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+    *(SORT(.ctors.*))
+    *(.ctors)
+
+    /* .dtors */
+    *crtbegin.o(.dtors)
+    *crtbegin?.o(.dtors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+    *(SORT(.dtors.*))
+    *(.dtors)
+
+    *(.rodata*)
+
+    KEEP(*(.eh_frame*))
+  } > FLASH
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > FLASH
+
+  __exidx_start = .;
+  .ARM.exidx :
+  {
+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+  } > FLASH
+  __exidx_end = .;
+
+  .copy.table :
+  {
+    . = ALIGN(4);
+    __copy_table_start__ = .;
+
+    LONG (LOADADDR(.data))
+    LONG (ADDR(.data))
+    LONG (SIZEOF(.data) / 4)
+
+    /* Add each additional data section here */
+/*
+    LONG (LOADADDR(.data2))
+    LONG (ADDR(.data2))
+    LONG (SIZEOF(.data2) / 4)
+*/
+    __copy_table_end__ = .;
+  } > FLASH
+
+  .zero.table :
+  {
+    . = ALIGN(4);
+    __zero_table_start__ = .;
+
+/*  .bss initialization to zero is already done during C Run-Time Startup.
+    LONG (ADDR(.bss))
+    LONG (SIZEOF(.bss) / 4)
+*/
+
+    /* Add each additional bss section here */
+/*
+    LONG (ADDR(.bss2))
+    LONG (SIZEOF(.bss2) / 4)
+*/
+    __zero_table_end__ = .;
+  } > FLASH
+
+  /*
+   * This __etext variable is kept for backward compatibility with older,
+   * ASM based startup files.
+   */
+  PROVIDE(__etext = LOADADDR(.data));
+
+  .data : ALIGN(4)
+  {
+    __data_start__ = .;
+    *(vtable)
+    *(.data)
+    *(.data.*)
+
+    . = ALIGN(4);
+    /* preinit data */
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP(*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+
+    . = ALIGN(4);
+    /* init data */
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP(*(SORT(.init_array.*)))
+    KEEP(*(.init_array))
+    PROVIDE_HIDDEN (__init_array_end = .);
+
+    . = ALIGN(4);
+    /* finit data */
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP(*(SORT(.fini_array.*)))
+    KEEP(*(.fini_array))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    /* All data end */
+    __data_end__ = .;
+
+  } > RAM AT > FLASH
+
+  /*
+   * Secondary data section, optional
+   *
+   * Remember to add each additional data section
+   * to the .copy.table above to assure proper
+   * initialization during startup.
+   */
+/*
+  .data2 : ALIGN(4)
+  {
+    . = ALIGN(4);
+    __data2_start__ = .;
+    *(.data2)
+    *(.data2.*)
+    . = ALIGN(4);
+    __data2_end__ = .;
+
+  } > RAM2 AT > FLASH
+*/
+
+  .bss :
+  {
+    . = ALIGN(4);
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss.*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+  } > RAM AT > RAM
+
+  /*
+   * Secondary bss section, optional
+   *
+   * Remember to add each additional bss section
+   * to the .zero.table above to assure proper
+   * initialization during startup.
+   */
+/*
+  .bss2 :
+  {
+    . = ALIGN(4);
+    __bss2_start__ = .;
+    *(.bss2)
+    *(.bss2.*)
+    . = ALIGN(4);
+    __bss2_end__ = .;
+  } > RAM2 AT > RAM2
+*/
+
+  .heap (NOLOAD) :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    . = . + __HEAP_SIZE;
+    . = ALIGN(8);
+    __HeapLimit = .;
+  } > RAM
+
+  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (NOLOAD) :
+  {
+    . = ALIGN(8);
+    __StackLimit = .;
+    . = . + __STACK_SIZE;
+    . = ALIGN(8);
+    __StackTop = .;
+  } > RAM
+  PROVIDE(__stack = __StackTop);
+
+  /* Check if data + heap + stack exceeds RAM limit */
+  ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/Testing/cmsis_build/RTE/Device/ARMCM4/startup_ARMCM4.c b/Testing/cmsis_build/RTE/Device/ARMCM4/startup_ARMCM4.c
new file mode 100644
index 000000000..9d5777366
--- /dev/null
+++ b/Testing/cmsis_build/RTE/Device/ARMCM4/startup_ARMCM4.c
@@ -0,0 +1,150 @@
+/******************************************************************************
+ * @file     startup_ARMCM4.c
+ * @brief    CMSIS-Core(M) Device Startup File for a Cortex-M4 Device
+ * @version  V3.0.0
+ * @date     06. April 2023
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2023 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM4)
+  #include "ARMCM4.h"
+#else
+  #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+  External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+
+extern __NO_RETURN void __PROGRAM_START(void);
+
+/*----------------------------------------------------------------------------
+  Internal References
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler  (void);
+            void Default_Handler(void);
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler      (void) __attribute__ ((weak));
+void MemManage_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler       (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler       (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler        (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
+       const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
+  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */
+  Reset_Handler,                            /*     Reset Handler */
+  NMI_Handler,                              /* -14 NMI Handler */
+  HardFault_Handler,                        /* -13 Hard Fault Handler */
+  MemManage_Handler,                        /* -12 MPU Fault Handler */
+  BusFault_Handler,                         /* -11 Bus Fault Handler */
+  UsageFault_Handler,                       /* -10 Usage Fault Handler */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  SVC_Handler,                              /*  -5 SVC Handler */
+  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */
+  0,                                        /*     Reserved */
+  PendSV_Handler,                           /*  -2 PendSV Handler */
+  SysTick_Handler,                          /*  -1 SysTick Handler */
+
+  /* Interrupts */
+  Interrupt0_Handler,                       /*   0 Interrupt 0 */
+  Interrupt1_Handler,                       /*   1 Interrupt 1 */
+  Interrupt2_Handler,                       /*   2 Interrupt 2 */
+  Interrupt3_Handler,                       /*   3 Interrupt 3 */
+  Interrupt4_Handler,                       /*   4 Interrupt 4 */
+  Interrupt5_Handler,                       /*   5 Interrupt 5 */
+  Interrupt6_Handler,                       /*   6 Interrupt 6 */
+  Interrupt7_Handler,                       /*   7 Interrupt 7 */
+  Interrupt8_Handler,                       /*   8 Interrupt 8 */
+  Interrupt9_Handler                        /*   9 Interrupt 9 */
+                                            /* Interrupts 10 .. 223 are left out */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler(void)
+{
+  SystemInit();                             /* CMSIS System Initialization */
+  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */
+}
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wmissing-noreturn"
+#endif
+
+/*----------------------------------------------------------------------------
+  Hard Fault Handler
+ *----------------------------------------------------------------------------*/
+void HardFault_Handler(void)
+{
+  while(1);
+}
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+  while(1);
+}
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang diagnostic pop
+#endif
+
diff --git a/Testing/cmsis_build/RTE/Device/ARMCM4/system_ARMCM4.c b/Testing/cmsis_build/RTE/Device/ARMCM4/system_ARMCM4.c
new file mode 100644
index 000000000..803d4fc3e
--- /dev/null
+++ b/Testing/cmsis_build/RTE/Device/ARMCM4/system_ARMCM4.c
@@ -0,0 +1,79 @@
+/**************************************************************************//**
+ * @file     system_ARMCM4.c
+ * @brief    CMSIS Device System Source File for
+ *           ARMCM4 Device
+ * @version  V2.0.0
+ * @date     06. April 2023
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2023 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM4)
+  #include "ARMCM4.h"
+#else
+  #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
+
+#define  SYSTEM_CLOCK    (XTAL / 2U)
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);
+#endif
+
+#if defined (__FPU_USED) && (__FPU_USED == 1U)
+  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */
+                 (3U << 11U*2U)  );         /* enable CP11 Full Access */
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+  SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/Testing/cmsis_build/RTE/Device/ARMCM7/ARMCM7_ac6.sct b/Testing/cmsis_build/RTE/Device/ARMCM7/ARMCM7_ac6.sct
new file mode 100644
index 000000000..3cba29e72
--- /dev/null
+++ b/Testing/cmsis_build/RTE/Device/ARMCM7/ARMCM7_ac6.sct
@@ -0,0 +1,80 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m7 -xc
+; command above MUST be in first line (no comment above!)
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE      0x00000000
+#define __ROM_SIZE      0x00080000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>
+;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE      0x20000000
+#define __RAM_SIZE      0x00040000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE    0x00000200
+#define __HEAP_SIZE     0x00000C00
+
+/*
+;------------- <<< end of configuration section >>> ---------------------------
+*/
+
+
+/*----------------------------------------------------------------------------
+  User Stack & Heap boundary definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE)    /* starts at end of RAM */
+#define __HEAP_BASE    (AlignExpr(+0, 8))           /* starts after RW_RAM section, 8 byte aligned */
+
+
+/*----------------------------------------------------------------------------
+  Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+#define __RO_BASE       __ROM_BASE
+#define __RO_SIZE       __ROM_SIZE
+
+#define __RW_BASE       __RAM_BASE
+#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+LR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region
+  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+
+  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {
+    *(.bss.noinit)
+  }
+
+  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
+    *(+RW +ZI)
+  }
+
+#if __HEAP_SIZE > 0
+  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap
+  }
+#endif
+
+  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack
+  }
+}
diff --git a/Testing/cmsis_build/RTE/Device/ARMCM7/ARMCM7_gcc.ld b/Testing/cmsis_build/RTE/Device/ARMCM7/ARMCM7_gcc.ld
new file mode 100644
index 000000000..93ed813c8
--- /dev/null
+++ b/Testing/cmsis_build/RTE/Device/ARMCM7/ARMCM7_gcc.ld
@@ -0,0 +1,263 @@
+/*
+ *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+ */
+
+/*---------------------- Flash Configuration ----------------------------------
+  <h> Flash Configuration
+    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+  </h>
+  -----------------------------------------------------------------------------*/
+__ROM_BASE = 0x00000000;
+__ROM_SIZE = 0x00040000;
+
+/*--------------------- Embedded RAM Configuration ----------------------------
+  <h> RAM Configuration
+    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>
+    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+  </h>
+ -----------------------------------------------------------------------------*/
+__RAM_BASE = 0x20000000;
+__RAM_SIZE = 0x00020000;
+
+/*--------------------- Stack / Heap Configuration ----------------------------
+  <h> Stack / Heap Configuration
+    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+  </h>
+  -----------------------------------------------------------------------------*/
+__STACK_SIZE = 0x00000400;
+__HEAP_SIZE  = 0x00000C00;
+
+/*
+ *-------------------- <<< end of configuration section >>> -------------------
+ */
+
+MEMORY
+{
+  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
+  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext          (deprecated)
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+  .text :
+  {
+    KEEP(*(.vectors))
+    *(.text*)
+
+    KEEP(*(.init))
+    KEEP(*(.fini))
+
+    /* .ctors */
+    *crtbegin.o(.ctors)
+    *crtbegin?.o(.ctors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+    *(SORT(.ctors.*))
+    *(.ctors)
+
+    /* .dtors */
+    *crtbegin.o(.dtors)
+    *crtbegin?.o(.dtors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+    *(SORT(.dtors.*))
+    *(.dtors)
+
+    *(.rodata*)
+
+    KEEP(*(.eh_frame*))
+  } > FLASH
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > FLASH
+
+  __exidx_start = .;
+  .ARM.exidx :
+  {
+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+  } > FLASH
+  __exidx_end = .;
+
+  .copy.table :
+  {
+    . = ALIGN(4);
+    __copy_table_start__ = .;
+
+    LONG (LOADADDR(.data))
+    LONG (ADDR(.data))
+    LONG (SIZEOF(.data) / 4)
+
+    /* Add each additional data section here */
+/*
+    LONG (LOADADDR(.data2))
+    LONG (ADDR(.data2))
+    LONG (SIZEOF(.data2) / 4)
+*/
+    __copy_table_end__ = .;
+  } > FLASH
+
+  .zero.table :
+  {
+    . = ALIGN(4);
+    __zero_table_start__ = .;
+
+/*  .bss initialization to zero is already done during C Run-Time Startup.
+    LONG (ADDR(.bss))
+    LONG (SIZEOF(.bss) / 4)
+*/
+
+    /* Add each additional bss section here */
+/*
+    LONG (ADDR(.bss2))
+    LONG (SIZEOF(.bss2) / 4)
+*/
+    __zero_table_end__ = .;
+  } > FLASH
+
+  /*
+   * This __etext variable is kept for backward compatibility with older,
+   * ASM based startup files.
+   */
+  PROVIDE(__etext = LOADADDR(.data));
+
+  .data : ALIGN(4)
+  {
+    __data_start__ = .;
+    *(vtable)
+    *(.data)
+    *(.data.*)
+
+    . = ALIGN(4);
+    /* preinit data */
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP(*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+
+    . = ALIGN(4);
+    /* init data */
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP(*(SORT(.init_array.*)))
+    KEEP(*(.init_array))
+    PROVIDE_HIDDEN (__init_array_end = .);
+
+    . = ALIGN(4);
+    /* finit data */
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP(*(SORT(.fini_array.*)))
+    KEEP(*(.fini_array))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    /* All data end */
+    __data_end__ = .;
+
+  } > RAM AT > FLASH
+
+  /*
+   * Secondary data section, optional
+   *
+   * Remember to add each additional data section
+   * to the .copy.table above to assure proper
+   * initialization during startup.
+   */
+/*
+  .data2 : ALIGN(4)
+  {
+    . = ALIGN(4);
+    __data2_start__ = .;
+    *(.data2)
+    *(.data2.*)
+    . = ALIGN(4);
+    __data2_end__ = .;
+
+  } > RAM2 AT > FLASH
+*/
+
+  .bss :
+  {
+    . = ALIGN(4);
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss.*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+  } > RAM AT > RAM
+
+  /*
+   * Secondary bss section, optional
+   *
+   * Remember to add each additional bss section
+   * to the .zero.table above to assure proper
+   * initialization during startup.
+   */
+/*
+  .bss2 :
+  {
+    . = ALIGN(4);
+    __bss2_start__ = .;
+    *(.bss2)
+    *(.bss2.*)
+    . = ALIGN(4);
+    __bss2_end__ = .;
+  } > RAM2 AT > RAM2
+*/
+
+  .heap (NOLOAD) :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    . = . + __HEAP_SIZE;
+    . = ALIGN(8);
+    __HeapLimit = .;
+  } > RAM
+
+  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (NOLOAD) :
+  {
+    . = ALIGN(8);
+    __StackLimit = .;
+    . = . + __STACK_SIZE;
+    . = ALIGN(8);
+    __StackTop = .;
+  } > RAM
+  PROVIDE(__stack = __StackTop);
+
+  /* Check if data + heap + stack exceeds RAM limit */
+  ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/Testing/cmsis_build/RTE/Device/ARMCM7/startup_ARMCM7.c b/Testing/cmsis_build/RTE/Device/ARMCM7/startup_ARMCM7.c
new file mode 100644
index 000000000..96a18eb58
--- /dev/null
+++ b/Testing/cmsis_build/RTE/Device/ARMCM7/startup_ARMCM7.c
@@ -0,0 +1,150 @@
+/******************************************************************************
+ * @file     startup_ARMCM7.c
+ * @brief    CMSIS-Core(M) Device Startup File for a Cortex-M7 Device
+ * @version  V3.0.0
+ * @date     06. April 2023
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2023 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM7)
+  #include "ARMCM7.h"
+#else
+  #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+  External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+
+extern __NO_RETURN void __PROGRAM_START(void);
+
+/*----------------------------------------------------------------------------
+  Internal References
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler  (void);
+            void Default_Handler(void);
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler      (void) __attribute__ ((weak));
+void MemManage_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler       (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler       (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler        (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
+       const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
+  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */
+  Reset_Handler,                            /*     Reset Handler */
+  NMI_Handler,                              /* -14 NMI Handler */
+  HardFault_Handler,                        /* -13 Hard Fault Handler */
+  MemManage_Handler,                        /* -12 MPU Fault Handler */
+  BusFault_Handler,                         /* -11 Bus Fault Handler */
+  UsageFault_Handler,                       /* -10 Usage Fault Handler */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  SVC_Handler,                              /*  -5 SVC Handler */
+  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */
+  0,                                        /*     Reserved */
+  PendSV_Handler,                           /*  -2 PendSV Handler */
+  SysTick_Handler,                          /*  -1 SysTick Handler */
+
+  /* Interrupts */
+  Interrupt0_Handler,                       /*   0 Interrupt 0 */
+  Interrupt1_Handler,                       /*   1 Interrupt 1 */
+  Interrupt2_Handler,                       /*   2 Interrupt 2 */
+  Interrupt3_Handler,                       /*   3 Interrupt 3 */
+  Interrupt4_Handler,                       /*   4 Interrupt 4 */
+  Interrupt5_Handler,                       /*   5 Interrupt 5 */
+  Interrupt6_Handler,                       /*   6 Interrupt 6 */
+  Interrupt7_Handler,                       /*   7 Interrupt 7 */
+  Interrupt8_Handler,                       /*   8 Interrupt 8 */
+  Interrupt9_Handler                        /*   9 Interrupt 9 */
+                                            /* Interrupts 10 .. 223 are left out */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler(void)
+{
+  SystemInit();                             /* CMSIS System Initialization */
+  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */
+}
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wmissing-noreturn"
+#endif
+
+/*----------------------------------------------------------------------------
+  Hard Fault Handler
+ *----------------------------------------------------------------------------*/
+void HardFault_Handler(void)
+{
+  while(1);
+}
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+  while(1);
+}
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang diagnostic pop
+#endif
+
diff --git a/Testing/cmsis_build/RTE/Device/ARMCM7/system_ARMCM7.c b/Testing/cmsis_build/RTE/Device/ARMCM7/system_ARMCM7.c
new file mode 100644
index 000000000..0a95be03f
--- /dev/null
+++ b/Testing/cmsis_build/RTE/Device/ARMCM7/system_ARMCM7.c
@@ -0,0 +1,79 @@
+/**************************************************************************//**
+ * @file     system_ARMCM7.c
+ * @brief    CMSIS Device System Source File for
+ *           ARMCM7 Device
+ * @version  V2.0.0
+ * @date     06. April 2023
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2023 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM7)
+  #include "ARMCM7.h"
+#else
+  #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
+
+#define  SYSTEM_CLOCK    (XTAL / 2U)
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);
+#endif
+
+#if defined (__FPU_USED) && (__FPU_USED == 1U)
+  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */
+                 (3U << 11U*2U)  );         /* enable CP11 Full Access */
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+  SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/Testing/cmsis_build/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.ld b/Testing/cmsis_build/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.ld
new file mode 100644
index 000000000..ff09e8e31
--- /dev/null
+++ b/Testing/cmsis_build/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.ld
@@ -0,0 +1,242 @@
+;/*
+; * Copyright (c) 2009-2023 Arm Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; *     http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+/* Linker script to configure memory regions. */
+/* This file will be run trough the pre-processor. */
+
+#include "region_defs.h"
+
+MEMORY
+{
+  FLASH (rx)  : ORIGIN = S_CODE_START, LENGTH = S_CODE_SIZE
+  RAM   (rwx) : ORIGIN = S_DATA_START, LENGTH = S_DATA_SIZE
+}
+
+__heap_size__  = HEAP_SIZE;
+__stack_size__ = STACK_SIZE;
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapBase
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.vectors))
+        __Vectors_End = .;
+        __Vectors_Size = __Vectors_End - __Vectors;
+        __end__ = .;
+
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+         *crtbegin.o(.dtors)
+         *crtbegin?.o(.dtors)
+         *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+         *(SORT(.dtors.*))
+         *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    /*
+     * Place the CMSE Veneers (containing the SG instruction) after the code, in a
+     * separate 32 bytes aligned region so that the SAU can programmed to just set
+     * this region as Non-Secure Callable. The maximum size of this executable
+     * region makes it only used the space left over by the ER_CODE region
+     * so that you can rely on code+veneer size combined will not exceed the
+     * S_CODE_SIZE value. We also substract from the available space the
+     * area used to align this section on 32 bytes boundary (for SAU conf).
+     */
+    .gnu.sgstubs : ALIGN(32)
+    {
+        *(.gnu.sgstubs*)
+    } > FLASH
+    . = ALIGN(32);
+    Image$$ER_CODE_CMSE_VENEER$$Base = ADDR(.gnu.sgstubs);
+    Image$$ER_CODE_CMSE_VENEER$$Limit = .;
+    Image$$ER_CODE_CMSE_VENEER$$Length = Image$$ER_CODE_CMSE_VENEER$$Limit - Image$$ER_CODE_CMSE_VENEER$$Base;
+
+    /* Make sure veneers fit into code memory */
+    ASSERT(((S_CODE_START + S_CODE_SIZE) > Image$$ER_CODE_CMSE_VENEER$$Limit), "Veneer region does not fit into code memory")
+
+    .ARM.extab : ALIGN(32)
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    /* To copy multiple ROM to RAM sections,
+     * define etext2/data2_start/data2_end and
+     * define __STARTUP_COPY_MULTIPLE in startup_cmsdk_mps2_sse_200.S */
+    .copy.table : ALIGN(4)
+    {
+        __copy_table_start__ = .;
+        LONG (__etext)
+        LONG (__data_start__)
+        LONG ((__data_end__ - __data_start__) / 4)
+        LONG (DEFINED(__etext2) ? __etext2 : 0)
+        LONG (DEFINED(__data2_start__) ? __data2_start__ : 0)
+        LONG (DEFINED(__data2_start__) ? ((__data2_end__ - __data2_start__) / 4) : 0)
+        __copy_table_end__ = .;
+    } > FLASH
+
+    /* To clear multiple BSS sections,
+     * uncomment .zero.table section and,
+     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+    .zero.table : ALIGN(4)
+    {
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG ((__bss_end__ - __bss_start__) / 4)
+        LONG (DEFINED(__bss2_start__) ? __bss2_start__ : 0)
+        LONG (DEFINED(__bss2_start__) ? ((__bss2_end__ - __bss2_start__) / 4) : 0)
+        __zero_table_end__ = .;
+    } > FLASH
+
+    __etext = ALIGN(4);
+
+    .data : ALIGN(4)
+    {
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM AT> FLASH
+
+    .bss : ALIGN(4)
+    {
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > RAM
+
+    bss_size = __bss_end__ - __bss_start__;
+
+    .stack : ALIGN(8)
+    {
+        __StackLimit = .;
+        KEEP(*(.stack*))
+        . += __stack_size__ - 0x8;
+        __StackTop = .;
+    } > RAM
+
+    .msp_stack_seal_res :
+    {
+        . += 0x8;
+    } > RAM
+    __StackSeal = ADDR(.msp_stack_seal_res);
+
+    .heap : ALIGN(8)
+    {
+        __end__ = .;
+        PROVIDE(end = .);
+        __HeapBase = .;
+        . += __heap_size__;
+        __HeapLimit = .;
+        __heap_limit = .; /* Add for _sbrk */
+    } > RAM
+
+    /* Set stack top to end of the used RAM section, and stack limit move down by
+     * size of stack_dummy section */
+    PROVIDE(__stack = __StackTop);
+
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackTop <= (S_DATA_START + S_DATA_SIZE), "Secure RAM region overflowed")
+}
diff --git a/Testing/cmsis_build/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct b/Testing/cmsis_build/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct
new file mode 100644
index 000000000..8b95c189d
--- /dev/null
+++ b/Testing/cmsis_build/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct
@@ -0,0 +1,62 @@
+#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc
+
+;/*
+; * Copyright (c) 2018-2023 Arm Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; *     http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; */
+
+#include "region_defs.h"
+
+LR_CODE S_CODE_START {
+    ER_CODE S_CODE_START {
+        *.o (RESET +First)
+        .ANY (+RO)
+    }
+
+    /* This empty, zero long execution region is here to mark the limit address
+     * of the last execution region that is allocated in SRAM.
+     */
+    CODE_WATERMARK +0 EMPTY 0x0 {
+    }
+    /* Make sure that the sections allocated in the SRAM does not exceed the
+     * size of the SRAM available.
+     */
+    ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE)
+
+    ER_DATA S_DATA_START {
+        .ANY (+ZI +RW)
+    }
+
+    #if HEAP_SIZE > 0
+    ARM_LIB_HEAP +0 ALIGN 8 EMPTY  HEAP_SIZE  {   ; Reserve empty region for heap
+    }
+    #endif
+
+    ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE - 0x8 {   ; Reserve empty region for stack
+    }
+
+    STACKSEAL +0 EMPTY 0x8 {
+    }
+
+    /* This empty, zero long execution region is here to mark the limit address
+     * of the last execution region that is allocated in SRAM.
+     */
+    SRAM_WATERMARK +0 EMPTY 0x0 {
+    }
+    /* Make sure that the sections allocated in the SRAM does not exceed the
+     * size of the SRAM available.
+     */
+    ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE)
+}
diff --git a/Testing/cmsis_build/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c b/Testing/cmsis_build/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c
new file mode 100644
index 000000000..72b39ca55
--- /dev/null
+++ b/Testing/cmsis_build/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c
@@ -0,0 +1,375 @@
+/*
+ * Copyright (c) 2022-2023 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * This file is derivative of CMSIS V5.9.0 startup_ARMCM55.c
+ * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c
+ */
+
+#include "SSE300MPS3.h"
+
+/*----------------------------------------------------------------------------
+  External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+extern uint32_t __STACK_LIMIT;
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+extern uint64_t __STACK_SEAL;
+#endif
+
+extern void __PROGRAM_START(void) __NO_RETURN;
+
+/*----------------------------------------------------------------------------
+  Internal References
+ *----------------------------------------------------------------------------*/
+void Reset_Handler  (void) __NO_RETURN;
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+#define DEFAULT_IRQ_HANDLER(handler_name)  \
+void __WEAK handler_name(void) __NO_RETURN; \
+void handler_name(void) { \
+    while(1); \
+}
+
+/* Exceptions */
+DEFAULT_IRQ_HANDLER(NMI_Handler)
+DEFAULT_IRQ_HANDLER(HardFault_Handler)
+DEFAULT_IRQ_HANDLER(MemManage_Handler)
+DEFAULT_IRQ_HANDLER(BusFault_Handler)
+DEFAULT_IRQ_HANDLER(UsageFault_Handler)
+DEFAULT_IRQ_HANDLER(SecureFault_Handler)
+DEFAULT_IRQ_HANDLER(SVC_Handler)
+DEFAULT_IRQ_HANDLER(DebugMon_Handler)
+DEFAULT_IRQ_HANDLER(PendSV_Handler)
+DEFAULT_IRQ_HANDLER(SysTick_Handler)
+
+DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler)
+DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler)
+DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler)
+DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler)
+DEFAULT_IRQ_HANDLER(TIMER1_Handler)
+DEFAULT_IRQ_HANDLER(TIMER2_Handler)
+DEFAULT_IRQ_HANDLER(MPC_Handler)
+DEFAULT_IRQ_HANDLER(PPC_Handler)
+DEFAULT_IRQ_HANDLER(MSC_Handler)
+DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler)
+DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler)
+DEFAULT_IRQ_HANDLER(SYS_PPU_Handler)
+DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler)
+DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler)
+DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler)
+DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler)
+DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler)
+
+DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler)
+DEFAULT_IRQ_HANDLER(UARTRX0_Handler)
+DEFAULT_IRQ_HANDLER(UARTTX0_Handler)
+DEFAULT_IRQ_HANDLER(UARTRX1_Handler)
+DEFAULT_IRQ_HANDLER(UARTTX1_Handler)
+DEFAULT_IRQ_HANDLER(UARTRX2_Handler)
+DEFAULT_IRQ_HANDLER(UARTTX2_Handler)
+DEFAULT_IRQ_HANDLER(UARTRX3_Handler)
+DEFAULT_IRQ_HANDLER(UARTTX3_Handler)
+DEFAULT_IRQ_HANDLER(UARTRX4_Handler)
+DEFAULT_IRQ_HANDLER(UARTTX4_Handler)
+DEFAULT_IRQ_HANDLER(UART0_Combined_Handler)
+DEFAULT_IRQ_HANDLER(UART1_Combined_Handler)
+DEFAULT_IRQ_HANDLER(UART2_Combined_Handler)
+DEFAULT_IRQ_HANDLER(UART3_Combined_Handler)
+DEFAULT_IRQ_HANDLER(UART4_Combined_Handler)
+DEFAULT_IRQ_HANDLER(UARTOVF_Handler)
+DEFAULT_IRQ_HANDLER(ETHERNET_Handler)
+DEFAULT_IRQ_HANDLER(I2S_Handler)
+DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler)
+DEFAULT_IRQ_HANDLER(USB_Handler)
+DEFAULT_IRQ_HANDLER(SPI_ADC_Handler)
+DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler)
+DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler)
+DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler)
+#ifdef CORSTONE300_AN547
+DEFAULT_IRQ_HANDLER(DMA_Ch_1_Error_Handler)
+DEFAULT_IRQ_HANDLER(DMA_Ch_1_Terminal_Count_Handler)
+DEFAULT_IRQ_HANDLER(DMA_Ch_1_Combined_Handler)
+DEFAULT_IRQ_HANDLER(DMA_Ch_2_Error_Handler)
+DEFAULT_IRQ_HANDLER(DMA_Ch_2_Terminal_Count_Handler)
+DEFAULT_IRQ_HANDLER(DMA_Ch_2_Combined_Handler)
+DEFAULT_IRQ_HANDLER(DMA_Ch_3_Error_Handler)
+DEFAULT_IRQ_HANDLER(DMA_Ch_3_Terminal_Count_Handler)
+DEFAULT_IRQ_HANDLER(DMA_Ch_3_Combined_Handler)
+#endif
+DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler)
+DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_0_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_1_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_2_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_3_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_4_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_5_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_6_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_7_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_8_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_9_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_10_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_11_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_12_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_13_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_14_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_15_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_0_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_1_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_2_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_3_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_4_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_5_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_6_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_7_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_8_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_9_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_10_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_11_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_12_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_13_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_14_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_15_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_0_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_1_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_2_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_3_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_4_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_5_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_6_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_7_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_8_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_9_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_10_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_11_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_12_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_13_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_14_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_15_Handler)
+DEFAULT_IRQ_HANDLER(GPIO3_0_Handler)
+DEFAULT_IRQ_HANDLER(GPIO3_1_Handler)
+DEFAULT_IRQ_HANDLER(GPIO3_2_Handler)
+DEFAULT_IRQ_HANDLER(GPIO3_3_Handler)
+DEFAULT_IRQ_HANDLER(UARTRX5_Handler)
+DEFAULT_IRQ_HANDLER(UARTTX5_Handler)
+DEFAULT_IRQ_HANDLER(UART5_Handler)
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[];
+       const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = {
+  (VECTOR_TABLE_Type)(&__INITIAL_SP),            /*      Initial Stack Pointer */
+  Reset_Handler,                     /*      Reset Handler */
+  NMI_Handler,                       /* -14: NMI Handler */
+  HardFault_Handler,                 /* -13: Hard Fault Handler */
+  MemManage_Handler,                 /* -12: MPU Fault Handler */
+  BusFault_Handler,                  /* -11: Bus Fault Handler */
+  UsageFault_Handler,                /* -10: Usage Fault Handler */
+  SecureFault_Handler,               /*  -9: Secure Fault Handler */
+  0,                                 /*      Reserved */
+  0,                                 /*      Reserved */
+  0,                                 /*      Reserved */
+  SVC_Handler,                       /*  -5: SVCall Handler */
+  DebugMon_Handler,                  /*  -4: Debug Monitor Handler */
+  0,                                 /*      Reserved */
+  PendSV_Handler,                    /*  -2: PendSV Handler */
+  SysTick_Handler,                   /*  -1: SysTick Handler */
+
+  NONSEC_WATCHDOG_RESET_REQ_Handler, /*   0: Non-Secure Watchdog Reset Request Handler */
+  NONSEC_WATCHDOG_Handler,           /*   1: Non-Secure Watchdog Handler */
+  SLOWCLK_Timer_Handler,             /*   2: SLOWCLK Timer Handler */
+  TFM_TIMER0_IRQ_Handler,            /*   3: TIMER 0 Handler */
+  TIMER1_Handler,                    /*   4: TIMER 1 Handler */
+  TIMER2_Handler,                    /*   5: TIMER 2 Handler */
+  0,                                 /*   6: Reserved */
+  0,                                 /*   7: Reserved */
+  0,                                 /*   8: Reserved */
+  MPC_Handler,                       /*   9: MPC Combined (Secure) Handler */
+  PPC_Handler,                       /*  10: PPC Combined (Secure) Handler */
+  MSC_Handler,                       /*  11: MSC Combined (Secure) Handler */
+  BRIDGE_ERROR_Handler,              /*  12: Bridge Error (Secure) Handler */
+  0,                                 /*  13: Reserved */
+  MGMT_PPU_Handler,                  /*  14: MGMT PPU Handler */
+  SYS_PPU_Handler,                   /*  15: SYS PPU Handler */
+  CPU0_PPU_Handler,                  /*  16: CPU0 PPU Handler */
+  0,                                 /*  17: Reserved */
+  0,                                 /*  18: Reserved */
+  0,                                 /*  19: Reserved */
+  0,                                 /*  20: Reserved */
+  0,                                 /*  21: Reserved */
+  0,                                 /*  22: Reserved */
+  0,                                 /*  23: Reserved */
+  0,                                 /*  24: Reserved */
+  0,                                 /*  25: Reserved */
+  DEBUG_PPU_Handler,                 /*  26: DEBUG PPU Handler */
+  TIMER3_AON_Handler,                /*  27: TIMER 3 AON Handler */
+  CPU0_CTI_0_Handler,                /*  28: CPU0 CTI IRQ 0 Handler */
+  CPU0_CTI_1_Handler,                /*  29: CPU0 CTI IRQ 1 Handler */
+  0,                                 /*  30: Reserved */
+  0,                                 /*  31: Reserved */
+
+  /* External interrupts */
+  System_Timestamp_Counter_Handler,  /*  32: System timestamp counter Handler */
+  UARTRX0_Handler,                   /*  33: UART 0 RX Handler */
+  UARTTX0_Handler,                   /*  34: UART 0 TX Handler */
+  UARTRX1_Handler,                   /*  35: UART 1 RX Handler */
+  UARTTX1_Handler,                   /*  36: UART 1 TX Handler */
+  UARTRX2_Handler,                   /*  37: UART 2 RX Handler */
+  UARTTX2_Handler,                   /*  38: UART 2 TX Handler */
+  UARTRX3_Handler,                   /*  39: UART 3 RX Handler */
+  UARTTX3_Handler,                   /*  40: UART 3 TX Handler */
+  UARTRX4_Handler,                   /*  41: UART 4 RX Handler */
+  UARTTX4_Handler,                   /*  42: UART 4 TX Handler */
+  UART0_Combined_Handler,            /*  43: UART 0 Combined Handler */
+  UART1_Combined_Handler,            /*  44: UART 1 Combined Handler */
+  UART2_Combined_Handler,            /*  45: UART 2 Combined Handler */
+  UART3_Combined_Handler,            /*  46: UART 3 Combined Handler */
+  UART4_Combined_Handler,            /*  47: UART 4 Combined Handler */
+  UARTOVF_Handler,                   /*  48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */
+  ETHERNET_Handler,                  /*  49: Ethernet Handler */
+  I2S_Handler,                       /*  50: Audio I2S Handler */
+  TOUCH_SCREEN_Handler,              /*  51: Touch Screen Handler */
+  USB_Handler,                       /*  52: USB Handler */
+  SPI_ADC_Handler,                   /*  53: SPI ADC Handler */
+  SPI_SHIELD0_Handler,               /*  54: SPI (Shield 0) Handler */
+  SPI_SHIELD1_Handler,               /*  55: SPI (Shield 0) Handler */
+  ETHOS_U55_Handler,                 /*  56: Ethos-U55 Handler */
+#ifdef CORSTONE300_AN547
+  0,                                 /*  57: Reserved */
+  0,                                 /*  58: Reserved */
+  0,                                 /*  59: Reserved */
+  DMA_Ch_1_Error_Handler,            /*  60: DMA Ch1 Error Handler */
+  DMA_Ch_1_Terminal_Count_Handler,   /*  61: DMA Ch1 Terminal Count Handler */
+  DMA_Ch_1_Combined_Handler,         /*  62: DMA Ch1 Combined Handler */
+  DMA_Ch_2_Error_Handler,            /*  63: DMA Ch2 Error Handler */
+  DMA_Ch_2_Terminal_Count_Handler,   /*  64: DMA Ch2 Terminal Count Handler */
+  DMA_Ch_2_Combined_Handler,         /*  65: DMA Ch2 Combined Handler */
+  DMA_Ch_3_Error_Handler,            /*  66: DMA Ch3 Error Handler */
+  DMA_Ch_3_Terminal_Count_Handler,   /*  67: DMA Ch3 Terminal Count Handler */
+  DMA_Ch_3_Combined_Handler,         /*  68: DMA Ch3 Combined Handler */
+#else
+  0,                                 /*  57: Reserved */
+  0,                                 /*  58: Reserved */
+  0,                                 /*  59: Reserved */
+  0,                                 /*  60: Reserved */
+  0,                                 /*  61: Reserved */
+  0,                                 /*  62: Reserved */
+  0,                                 /*  63: Reserved */
+  0,                                 /*  64: Reserved */
+  0,                                 /*  65: Reserved */
+  0,                                 /*  66: Reserved */
+  0,                                 /*  67: Reserved */
+  0,                                 /*  68: Reserved */
+#endif
+  GPIO0_Combined_Handler,            /*  69: GPIO 0 Combined Handler */
+  GPIO1_Combined_Handler,            /*  70: GPIO 1 Combined Handler */
+  GPIO2_Combined_Handler,            /*  71: GPIO 2 Combined Handler */
+  GPIO3_Combined_Handler,            /*  72: GPIO 3 Combined Handler */
+  GPIO0_0_Handler,                   /*  73: GPIO0 Pin 0 Handler */
+  GPIO0_1_Handler,                   /*  74: GPIO0 Pin 1 Handler */
+  GPIO0_2_Handler,                   /*  75: GPIO0 Pin 2 Handler */
+  GPIO0_3_Handler,                   /*  76: GPIO0 Pin 3 Handler */
+  GPIO0_4_Handler,                   /*  77: GPIO0 Pin 4 Handler */
+  GPIO0_5_Handler,                   /*  78: GPIO0 Pin 5 Handler */
+  GPIO0_6_Handler,                   /*  79: GPIO0 Pin 6 Handler */
+  GPIO0_7_Handler,                   /*  80: GPIO0 Pin 7 Handler */
+  GPIO0_8_Handler,                   /*  81: GPIO0 Pin 8 Handler */
+  GPIO0_9_Handler,                   /*  82: GPIO0 Pin 9 Handler */
+  GPIO0_10_Handler,                  /*  83: GPIO0 Pin 10 Handler */
+  GPIO0_11_Handler,                  /*  84: GPIO0 Pin 11 Handler */
+  GPIO0_12_Handler,                  /*  85: GPIO0 Pin 12 Handler */
+  GPIO0_13_Handler,                  /*  86: GPIO0 Pin 13 Handler */
+  GPIO0_14_Handler,                  /*  87: GPIO0 Pin 14 Handler */
+  GPIO0_15_Handler,                  /*  88: GPIO0 Pin 15 Handler */
+  GPIO1_0_Handler,                   /*  89: GPIO1 Pin 0 Handler */
+  GPIO1_1_Handler,                   /*  90: GPIO1 Pin 1 Handler */
+  GPIO1_2_Handler,                   /*  91: GPIO1 Pin 2 Handler */
+  GPIO1_3_Handler,                   /*  92: GPIO1 Pin 3 Handler */
+  GPIO1_4_Handler,                   /*  93: GPIO1 Pin 4 Handler */
+  GPIO1_5_Handler,                   /*  94: GPIO1 Pin 5 Handler */
+  GPIO1_6_Handler,                   /*  95: GPIO1 Pin 6 Handler */
+  GPIO1_7_Handler,                   /*  96: GPIO1 Pin 7 Handler */
+  GPIO1_8_Handler,                   /*  97: GPIO1 Pin 8 Handler */
+  GPIO1_9_Handler,                   /*  98: GPIO1 Pin 9 Handler */
+  GPIO1_10_Handler,                  /*  99: GPIO1 Pin 10 Handler */
+  GPIO1_11_Handler,                  /*  100: GPIO1 Pin 11 Handler */
+  GPIO1_12_Handler,                  /*  101: GPIO1 Pin 12 Handler */
+  GPIO1_13_Handler,                  /*  102: GPIO1 Pin 13 Handler */
+  GPIO1_14_Handler,                  /*  103: GPIO1 Pin 14 Handler */
+  GPIO1_15_Handler,                  /*  104: GPIO1 Pin 15 Handler */
+  GPIO2_0_Handler,                   /*  105: GPIO2 Pin 0 Handler */
+  GPIO2_1_Handler,                   /*  106: GPIO2 Pin 1 Handler */
+  GPIO2_2_Handler,                   /*  107: GPIO2 Pin 2 Handler */
+  GPIO2_3_Handler,                   /*  108: GPIO2 Pin 3 Handler */
+  GPIO2_4_Handler,                   /*  109: GPIO2 Pin 4 Handler */
+  GPIO2_5_Handler,                   /*  110: GPIO2 Pin 5 Handler */
+  GPIO2_6_Handler,                   /*  111: GPIO2 Pin 6 Handler */
+  GPIO2_7_Handler,                   /*  112: GPIO2 Pin 7 Handler */
+  GPIO2_8_Handler,                   /*  113: GPIO2 Pin 8 Handler */
+  GPIO2_9_Handler,                   /*  114: GPIO2 Pin 9 Handler */
+  GPIO2_10_Handler,                  /*  115: GPIO2 Pin 10 Handler */
+  GPIO2_11_Handler,                  /*  116: GPIO2 Pin 11 Handler */
+  GPIO2_12_Handler,                  /*  117: GPIO2 Pin 12 Handler */
+  GPIO2_13_Handler,                  /*  118: GPIO2 Pin 13 Handler */
+  GPIO2_14_Handler,                  /*  119: GPIO2 Pin 14 Handler */
+  GPIO2_15_Handler,                  /*  120: GPIO2 Pin 15 Handler */
+  GPIO3_0_Handler,                   /*  121: GPIO3 Pin 0 Handler */
+  GPIO3_1_Handler,                   /*  122: GPIO3 Pin 1 Handler */
+  GPIO3_2_Handler,                   /*  123: GPIO3 Pin 2 Handler */
+  GPIO3_3_Handler,                   /*  124: GPIO3 Pin 3 Handler */
+  UARTRX5_Handler,                   /*  125: UART 5 RX Interrupt */
+  UARTTX5_Handler,                   /*  126: UART 5 TX Interrupt */
+  UART5_Handler,                     /*  127: UART 5 combined Interrupt */
+  0,                                 /*  128: Reserved */
+  0,                                 /*  129: Reserved */
+  0,                                 /*  130: Reserved */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void)
+{
+    __set_PSP((uint32_t)(&__INITIAL_SP));
+
+    __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
+    __set_PSPLIM((uint32_t)(&__STACK_LIMIT));
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));
+#endif
+
+    SystemInit();                             /* CMSIS System Initialization */
+    __PROGRAM_START();                        /* Enter PreMain (C library entry point) */
+}
diff --git a/Testing/cmsis_build/cdefault.yml b/Testing/cmsis_build/cdefault.yml
new file mode 100644
index 000000000..81eb557c2
--- /dev/null
+++ b/Testing/cmsis_build/cdefault.yml
@@ -0,0 +1,133 @@
+default:
+
+  compiler: AC6
+  
+  misc:
+    - for-compiler: AC6
+      C:
+        - -Wsign-compare 
+        - -Wdouble-promotion 
+        - -DNDEBUG 
+        - -Wall 
+        - -Wextra  
+        - -Werror
+        - -std=c11 
+        - -Ofast 
+        - -ffast-math
+        - -Wno-packed 
+        - -Wno-missing-variable-declarations 
+        - -Wno-missing-prototypes 
+        - -Wno-missing-noreturn 
+        - -Wno-sign-conversion 
+        - -Wno-nonportable-include-path 
+        - -Wno-reserved-id-macro 
+        - -Wno-unused-macros 
+        - -Wno-documentation-unknown-command 
+        - -Wno-documentation 
+        - -Wno-license-management 
+        - -Wno-parentheses-equality 
+        - -Wno-reserved-identifier
+        - -ffunction-sections
+      CPP:
+        - -fno-rtti 
+        - -DNDEBUG 
+        - -Wall 
+        - -Wextra  
+        - -std=c++17
+        - -Ofast 
+        - -ffast-math
+        - -Wno-unused-function
+        - -ffunction-sections
+      ASM:
+        - -masm=auto
+      Link:
+        - --entry=Reset_Handler
+        - --info=summarysizes
+        - --info=sizes
+        - --info=totals
+        - --info=unused
+        - --info=veneers
+
+    - for-compiler: GCC
+      C:
+        - -Wsign-compare 
+        - -Wdouble-promotion 
+        - -DNDEBUG 
+        - -Wall 
+        - -Wextra  
+        - -std=c11 
+        - -Ofast 
+        - -ffast-math
+        - -Wno-packed 
+        - -Wno-missing-prototypes 
+        - -Wno-missing-noreturn 
+        - -Wno-sign-conversion 
+        - -Wno-unused-macros 
+        - -ffunction-sections
+        - -flax-vector-conversions
+        - -Wno-maybe-uninitialized
+        - -fdata-sections
+        - -mfp16-format=ieee
+      CPP:
+        - -fno-rtti 
+        - -DNDEBUG 
+        - -Wall 
+        - -Wextra  
+        - -std=c++17
+        - -Ofast 
+        - -ffast-math
+        - -Wno-unused-function
+        - -ffunction-sections
+        - -fdata-sections
+        - -Wno-psabi
+        - -mfp16-format=ieee
+      ASM:
+        - -masm=auto
+      Link:
+        - --specs=nano.specs
+        - -Wl,-Map=$elf()$.map
+        - -lm
+        - -Wl,--wrap=SysTick_Handler
+        - -Wl,--gc-sections
+      Library:
+        - -lm
+
+    - for-compiler: CLANG
+      C:
+         - -Wsign-compare 
+         - -Wdouble-promotion 
+         - -DNDEBUG 
+         - -Wall 
+         - -Wextra  
+         - -Werror
+         - -std=c11 
+         - -Ofast 
+         - -ffast-math
+         - -Wno-packed 
+         - -Wno-missing-variable-declarations 
+         - -Wno-missing-prototypes 
+         - -Wno-missing-noreturn 
+         - -Wno-sign-conversion 
+         - -Wno-nonportable-include-path 
+         - -Wno-reserved-id-macro 
+         - -Wno-unused-macros 
+         - -Wno-documentation-unknown-command 
+         - -Wno-documentation 
+         - -Wno-parentheses-equality 
+         - -Wno-reserved-identifier
+         - -ffunction-sections
+      CPP:
+        - -fno-rtti 
+        - -DNDEBUG 
+        - -Wall 
+        - -Wextra  
+        - -std=c++17
+        - -Ofast 
+        - -ffast-math
+        - -Wno-unused-function
+        - -ffunction-sections
+      ASM:
+        - -masm=auto
+      Link:
+        - -Wl,-Map=$elf()$.map
+        - -Wl,--gc-sections
diff --git a/Testing/cmsis_build/configs/ARM_VHT_Corstone_300_config.txt b/Testing/cmsis_build/configs/ARM_VHT_Corstone_300_config.txt
index 6a2600493..8d5fe96e8 100644
--- a/Testing/cmsis_build/configs/ARM_VHT_Corstone_300_config.txt
+++ b/Testing/cmsis_build/configs/ARM_VHT_Corstone_300_config.txt
@@ -1,32 +1,15 @@
-# Parameters:
-# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]
-#----------------------------------------------------------------------------------------------
-cpu0.CFGITCMSZ=11
-cpu0.CFGDTCMSZ=11
 mps3_board.visualisation.disable-visualisation=1
-# (bool  , init-time) default = '0'      : Enable/disable visualisation
-cpu0.FPU=1                                            # (bool  , init-time) default = '1'      : Set whether the model has VFP support
-cpu0.MVE=2                                            # (int   , init-time) default = '0x1'    : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included
-cpu0.semihosting-enable=1                             # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
-cpu0.semihosting-Thumb_SVC=0xAB                       # (int   , init-time) default = '0xAB'   : T32 SVC number for semihosting : [0x0..0xFF]
-cpu0.semihosting-cmd_line=""                          # (string, init-time) default = ''       : Command line available to semihosting SVC calls
-cpu0.semihosting-heap_base=0x0                        # (int   , init-time) default = '0x0'    : Virtual address of heap base : [0x0..0xFFFFFFFF]
-cpu0.semihosting-heap_limit=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]
-cpu0.semihosting-stack_base=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]
-cpu0.semihosting-stack_limit=0x0                      # (int   , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]
-cpu0.semihosting-cwd=""                               # (string, init-time) default = ''       : Base directory for semihosting file access.
-cpu0.MPU_S=0x8                                        # (int   , init-time) default = '0x8'    : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10]
-cpu0.MPU_NS=0x8                                       # (int   , init-time) default = '0x8'    : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10]
-cpu0.ITM=0                                            # (bool  , init-time) default = '1'      : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included
-cpu0.IRQLVL=0x3                                       # (int   , init-time) default = '0x3'    : Number of bits of interrupt priority : [0x3..0x8]
-cpu0.INITSVTOR=0x70000000                             # (int   , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80]
-cpu0.INITNSVTOR=0x70000000                                   # (int   , init-time) default = '0x0'    : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80]
-cpu0.SAU=0x0                                          # (int   , init-time) default = '0x4'    : Number of SAU regions (0 => no SAU) : [0x0..0x8]
-idau.NUM_IDAU_REGION=0x0                              # (int   , init-time) default = '0xA'    : 
-cpu0.LOCK_SAU=0                                       # (bool  , init-time) default = '0'      : Lock down of SAU registers write
-cpu0.LOCK_S_MPU=0                                     # (bool  , init-time) default = '0'      : Lock down of Secure MPU registers write
-cpu0.LOCK_NS_MPU=0                                    # (bool  , init-time) default = '0'      : Lock down of Non-Secure MPU registers write
-cpu0.CPIF=1                                           # (bool  , init-time) default = '1'      : Specifies whether the external coprocessor interface is included
-cpu0.SECEXT=0                                         # (bool  , init-time) default = '1'      : Whether the ARMv8-M Security Extensions are included
-mps3_board.DISABLE_GATING=1                             # (bool  , init-time) default = '0'      : Disable Memory gating logic
-#----------------------------------------------------------------------------------------------
+cpu0.FPU=1
+cpu0.MVE=2
+cpu0.semihosting-enable=1
+cpu0.semihosting-Thumb_SVC=0xAB
+cpu0.semihosting-cmd_line=""
+cpu0.semihosting-heap_base=0x0
+cpu0.semihosting-heap_limit=0x0
+cpu0.semihosting-stack_base=0x0
+cpu0.semihosting-stack_limit=0x0
+cpu0.semihosting-cwd=""
+#cpu0.INITSVTOR=0x70000000 # remove for gcc and clang
+#cpu0.INITNSVTOR=0x70000000 # remove for gcc and clang
+#cpu0.SECEXT=0 # remove for gcc and clang
+#mps3_board.DISABLE_GATING=1 # remove for gcc and clang
diff --git a/Testing/cmsis_build/configs/ARM_VHT_Corstone_300_config_ext.txt b/Testing/cmsis_build/configs/ARM_VHT_Corstone_300_config_ext.txt
new file mode 100644
index 000000000..3a19044f8
--- /dev/null
+++ b/Testing/cmsis_build/configs/ARM_VHT_Corstone_300_config_ext.txt
@@ -0,0 +1,15 @@
+mps3_board.visualisation.disable-visualisation=1
+cpu0.FPU=1
+cpu0.MVE=2
+cpu0.semihosting-enable=1
+cpu0.semihosting-Thumb_SVC=0xAB
+cpu0.semihosting-cmd_line=""
+cpu0.semihosting-heap_base=0x0
+cpu0.semihosting-heap_limit=0x0
+cpu0.semihosting-stack_base=0x0
+cpu0.semihosting-stack_limit=0x0
+cpu0.semihosting-cwd=""
+cpu0.INITSVTOR=0x70000000 # remove for gcc and clang
+cpu0.INITNSVTOR=0x70000000 # remove for gcc and clang
+cpu0.SECEXT=0 # remove for gcc and clang
+mps3_board.DISABLE_GATING=1 # remove for gcc and clang
diff --git a/Testing/cmsis_build/linker_scripts/ARMCM0P/region_defs.h b/Testing/cmsis_build/linker_scripts/ARMCM0P/region_defs.h
new file mode 100644
index 000000000..7d523c01e
--- /dev/null
+++ b/Testing/cmsis_build/linker_scripts/ARMCM0P/region_defs.h
@@ -0,0 +1,60 @@
+#ifndef REGIONS_ARMCM0P_H
+#define REGIONS_ARMCM0P_H
+
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <n>Device pack:   ARM::Cortex_DFP@1.0.0
+// <i>Device pack used to generate this file
+
+// <h>ROM Configuration
+// =======================
+// <h> ROM=<__ROM0>
+//   <o> Base address <0x0-0xFFFFFFFF:8>
+//   <i> Defines base address of memory region.
+//   <i> Default: 0x00000000
+#define __ROM0_BASE 0x00000000
+//   <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
+//   <i> Defines size of memory region.
+//   <i> Default: 0x00040000
+#define __ROM0_SIZE 0x00200000
+//   <q>Default region
+//   <i> Enables memory region globally for the application.
+#define __ROM0_DEFAULT 1
+//   <q>Startup
+//   <i> Selects region to be used for startup code.
+#define __ROM0_STARTUP 1
+// </h>
+
+// </h>
+
+// <h>RAM Configuration
+// =======================
+// <h> RAM=<__RAM0>
+//   <o> Base address <0x0-0xFFFFFFFF:8>
+//   <i> Defines base address of memory region.
+//   <i> Default: 0x20000000
+#define __RAM0_BASE 0x20000000
+//   <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
+//   <i> Defines size of memory region.
+//   <i> Default: 0x00020000
+#define __RAM0_SIZE 0x00200000
+//   <q>Default region
+//   <i> Enables memory region globally for the application.
+#define __RAM0_DEFAULT 1
+//   <q>No zero initialize
+//   <i> Excludes region from zero initialization.
+#define __RAM0_NOINIT 0
+// </h>
+
+// </h>
+
+// <h>Stack / Heap Configuration
+//   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+#define __STACK_SIZE 0x00002000
+#define __HEAP_SIZE 0x00100000
+// </h>
+
+
+#endif /* REGIONS_ARMCM0P_H */
diff --git a/Testing/cmsis_build/linker_scripts/ARMCM3/region_defs.h b/Testing/cmsis_build/linker_scripts/ARMCM3/region_defs.h
new file mode 100644
index 000000000..8b2ab0cac
--- /dev/null
+++ b/Testing/cmsis_build/linker_scripts/ARMCM3/region_defs.h
@@ -0,0 +1,60 @@
+#ifndef REGIONS_ARMCM4_H
+#define REGIONS_ARMCM4_H
+
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <n>Device pack:   ARM::Cortex_DFP@1.0.0
+// <i>Device pack used to generate this file
+
+// <h>ROM Configuration
+// =======================
+// <h> ROM=<__ROM0>
+//   <o> Base address <0x0-0xFFFFFFFF:8>
+//   <i> Defines base address of memory region.
+//   <i> Default: 0x00000000
+#define __ROM0_BASE 0x00000000
+//   <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
+//   <i> Defines size of memory region.
+//   <i> Default: 0x00040000
+#define __ROM0_SIZE 0x00200000
+//   <q>Default region
+//   <i> Enables memory region globally for the application.
+#define __ROM0_DEFAULT 1
+//   <q>Startup
+//   <i> Selects region to be used for startup code.
+#define __ROM0_STARTUP 1
+// </h>
+
+// </h>
+
+// <h>RAM Configuration
+// =======================
+// <h> RAM=<__RAM0>
+//   <o> Base address <0x0-0xFFFFFFFF:8>
+//   <i> Defines base address of memory region.
+//   <i> Default: 0x20000000
+#define __RAM0_BASE 0x20000000
+//   <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
+//   <i> Defines size of memory region.
+//   <i> Default: 0x00020000
+#define __RAM0_SIZE 0x00200000
+//   <q>Default region
+//   <i> Enables memory region globally for the application.
+#define __RAM0_DEFAULT 1
+//   <q>No zero initialize
+//   <i> Excludes region from zero initialization.
+#define __RAM0_NOINIT 0
+// </h>
+
+// </h>
+
+// <h>Stack / Heap Configuration
+//   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+#define __STACK_SIZE 0x00002000
+#define __HEAP_SIZE 0x00100000
+// </h>
+
+
+#endif /* REGIONS_ARMCM4_H */
diff --git a/Testing/cmsis_build/linker_scripts/ARMCM33_DSP_FP/region_defs.h b/Testing/cmsis_build/linker_scripts/ARMCM33_DSP_FP/region_defs.h
new file mode 100644
index 000000000..8b2ab0cac
--- /dev/null
+++ b/Testing/cmsis_build/linker_scripts/ARMCM33_DSP_FP/region_defs.h
@@ -0,0 +1,60 @@
+#ifndef REGIONS_ARMCM4_H
+#define REGIONS_ARMCM4_H
+
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <n>Device pack:   ARM::Cortex_DFP@1.0.0
+// <i>Device pack used to generate this file
+
+// <h>ROM Configuration
+// =======================
+// <h> ROM=<__ROM0>
+//   <o> Base address <0x0-0xFFFFFFFF:8>
+//   <i> Defines base address of memory region.
+//   <i> Default: 0x00000000
+#define __ROM0_BASE 0x00000000
+//   <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
+//   <i> Defines size of memory region.
+//   <i> Default: 0x00040000
+#define __ROM0_SIZE 0x00200000
+//   <q>Default region
+//   <i> Enables memory region globally for the application.
+#define __ROM0_DEFAULT 1
+//   <q>Startup
+//   <i> Selects region to be used for startup code.
+#define __ROM0_STARTUP 1
+// </h>
+
+// </h>
+
+// <h>RAM Configuration
+// =======================
+// <h> RAM=<__RAM0>
+//   <o> Base address <0x0-0xFFFFFFFF:8>
+//   <i> Defines base address of memory region.
+//   <i> Default: 0x20000000
+#define __RAM0_BASE 0x20000000
+//   <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
+//   <i> Defines size of memory region.
+//   <i> Default: 0x00020000
+#define __RAM0_SIZE 0x00200000
+//   <q>Default region
+//   <i> Enables memory region globally for the application.
+#define __RAM0_DEFAULT 1
+//   <q>No zero initialize
+//   <i> Excludes region from zero initialization.
+#define __RAM0_NOINIT 0
+// </h>
+
+// </h>
+
+// <h>Stack / Heap Configuration
+//   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+#define __STACK_SIZE 0x00002000
+#define __HEAP_SIZE 0x00100000
+// </h>
+
+
+#endif /* REGIONS_ARMCM4_H */
diff --git a/Testing/cmsis_build/linker_scripts/ARMCM4/region_defs.h b/Testing/cmsis_build/linker_scripts/ARMCM4/region_defs.h
new file mode 100644
index 000000000..8b2ab0cac
--- /dev/null
+++ b/Testing/cmsis_build/linker_scripts/ARMCM4/region_defs.h
@@ -0,0 +1,60 @@
+#ifndef REGIONS_ARMCM4_H
+#define REGIONS_ARMCM4_H
+
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <n>Device pack:   ARM::Cortex_DFP@1.0.0
+// <i>Device pack used to generate this file
+
+// <h>ROM Configuration
+// =======================
+// <h> ROM=<__ROM0>
+//   <o> Base address <0x0-0xFFFFFFFF:8>
+//   <i> Defines base address of memory region.
+//   <i> Default: 0x00000000
+#define __ROM0_BASE 0x00000000
+//   <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
+//   <i> Defines size of memory region.
+//   <i> Default: 0x00040000
+#define __ROM0_SIZE 0x00200000
+//   <q>Default region
+//   <i> Enables memory region globally for the application.
+#define __ROM0_DEFAULT 1
+//   <q>Startup
+//   <i> Selects region to be used for startup code.
+#define __ROM0_STARTUP 1
+// </h>
+
+// </h>
+
+// <h>RAM Configuration
+// =======================
+// <h> RAM=<__RAM0>
+//   <o> Base address <0x0-0xFFFFFFFF:8>
+//   <i> Defines base address of memory region.
+//   <i> Default: 0x20000000
+#define __RAM0_BASE 0x20000000
+//   <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
+//   <i> Defines size of memory region.
+//   <i> Default: 0x00020000
+#define __RAM0_SIZE 0x00200000
+//   <q>Default region
+//   <i> Enables memory region globally for the application.
+#define __RAM0_DEFAULT 1
+//   <q>No zero initialize
+//   <i> Excludes region from zero initialization.
+#define __RAM0_NOINIT 0
+// </h>
+
+// </h>
+
+// <h>Stack / Heap Configuration
+//   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+#define __STACK_SIZE 0x00002000
+#define __HEAP_SIZE 0x00100000
+// </h>
+
+
+#endif /* REGIONS_ARMCM4_H */
diff --git a/Testing/cmsis_build/linker_scripts/ARMCM7_DP/region_defs.h b/Testing/cmsis_build/linker_scripts/ARMCM7_DP/region_defs.h
new file mode 100644
index 000000000..8b2ab0cac
--- /dev/null
+++ b/Testing/cmsis_build/linker_scripts/ARMCM7_DP/region_defs.h
@@ -0,0 +1,60 @@
+#ifndef REGIONS_ARMCM4_H
+#define REGIONS_ARMCM4_H
+
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <n>Device pack:   ARM::Cortex_DFP@1.0.0
+// <i>Device pack used to generate this file
+
+// <h>ROM Configuration
+// =======================
+// <h> ROM=<__ROM0>
+//   <o> Base address <0x0-0xFFFFFFFF:8>
+//   <i> Defines base address of memory region.
+//   <i> Default: 0x00000000
+#define __ROM0_BASE 0x00000000
+//   <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
+//   <i> Defines size of memory region.
+//   <i> Default: 0x00040000
+#define __ROM0_SIZE 0x00200000
+//   <q>Default region
+//   <i> Enables memory region globally for the application.
+#define __ROM0_DEFAULT 1
+//   <q>Startup
+//   <i> Selects region to be used for startup code.
+#define __ROM0_STARTUP 1
+// </h>
+
+// </h>
+
+// <h>RAM Configuration
+// =======================
+// <h> RAM=<__RAM0>
+//   <o> Base address <0x0-0xFFFFFFFF:8>
+//   <i> Defines base address of memory region.
+//   <i> Default: 0x20000000
+#define __RAM0_BASE 0x20000000
+//   <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
+//   <i> Defines size of memory region.
+//   <i> Default: 0x00020000
+#define __RAM0_SIZE 0x00200000
+//   <q>Default region
+//   <i> Enables memory region globally for the application.
+#define __RAM0_DEFAULT 1
+//   <q>No zero initialize
+//   <i> Excludes region from zero initialization.
+#define __RAM0_NOINIT 0
+// </h>
+
+// </h>
+
+// <h>Stack / Heap Configuration
+//   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+#define __STACK_SIZE 0x00002000
+#define __HEAP_SIZE 0x00100000
+// </h>
+
+
+#endif /* REGIONS_ARMCM4_H */
diff --git a/Testing/cmsis_build/linker_scripts/SSE-300-MPS3/region_defs.h b/Testing/cmsis_build/linker_scripts/SSE-300-MPS3/region_defs.h
new file mode 100644
index 000000000..32ac16b37
--- /dev/null
+++ b/Testing/cmsis_build/linker_scripts/SSE-300-MPS3/region_defs.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2016-2022 Arm Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __REGION_DEFS_H__
+#define __REGION_DEFS_H__
+
+#include "region_limits.h"
+
+/* **************************************************************
+ * WARNING: this file is parsed both by the C/C++ compiler
+ * and the linker. As a result the syntax must be valid not only
+ * for C/C++ but for the linker scripts too.
+ * Beware of the following limitations:
+ *   - LD (GCC linker) requires white space around operators.
+ *   - UL postfix for macros is not suported by the linker script
+ ****************************************************************/
+
+/* Secure regions */
+#define S_CODE_START     ( S_ROM_ALIAS )
+#define S_CODE_SIZE      ( TOTAL_S_ROM_SIZE )
+#define S_CODE_LIMIT     ( S_CODE_START + S_CODE_SIZE )
+
+#define S_DATA_START     ( S_RAM_ALIAS )
+#define S_DATA_SIZE      ( TOTAL_S_RAM_SIZE )
+#define S_DATA_LIMIT     ( S_DATA_START + S_DATA_SIZE )
+
+#define S_DDR4_START     ( S_DDR4_ALIAS )
+#define S_DDR4_SIZE      ( TOTAL_S_DDR4_SIZE )
+#define S_DDR4_LIMIT     ( S_DDR4_START + S_DDR4_SIZE )
+
+#endif /* __REGION_DEFS_H__ */
diff --git a/Testing/cmsis_build/linker_scripts/SSE-300-MPS3/region_limits.h b/Testing/cmsis_build/linker_scripts/SSE-300-MPS3/region_limits.h
new file mode 100644
index 000000000..dfe88b34f
--- /dev/null
+++ b/Testing/cmsis_build/linker_scripts/SSE-300-MPS3/region_limits.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2018-2022 Arm Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __REGION_LIMITS_H__
+#define __REGION_LIMITS_H__
+
+/* **************************************************************
+ * WARNING: this file is parsed both by the C/C++ compiler
+ * and the linker. As a result the syntax must be valid not only
+ * for C/C++ but for the linker scripts too.
+ * Beware of the following limitations:
+ *   - LD (GCC linker) requires white space around operators.
+ *   - UL postfix for macros is not suported by the linker script
+ ****************************************************************/
+
+/* Secure Code */
+#define S_ROM_ALIAS               (0x10000000) /* ITCM_BASE_S */
+#define TOTAL_S_ROM_SIZE          (0x00080000) /* 512 kB */
+
+/* Secure Data */
+#define S_RAM_ALIAS               (0x30000000) /* DTCM_BASE_S */
+#define TOTAL_S_RAM_SIZE          (0x00080000) /* 512 kB */
+
+/* Secure DDR4 */
+#define S_DDR4_ALIAS              (0x70000000) /* DDR4_BLK1_BASE_S */
+#define TOTAL_S_DDR4_SIZE         (0x10000000) /* 256 MB */
+
+/* Heap and Stack sizes for secure and nonsecure applications */
+#define HEAP_SIZE                 (0x00100000) /* 1 KiB */
+#define STACK_SIZE                (0x00002000) /* 1 KiB */
+
+#endif /* __REGION_LIMITS_H__ */
diff --git a/Testing/cmsis_build/linker_scripts/ac6_m0p_mps3_s.sct b/Testing/cmsis_build/linker_scripts/ac6_m0p_mps3_s.sct
new file mode 100644
index 000000000..4d6e579d0
--- /dev/null
+++ b/Testing/cmsis_build/linker_scripts/ac6_m0p_mps3_s.sct
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2023 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------------
+  Stack seal size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __STACKSEAL_SIZE   ( 8 )
+#else
+#define __STACKSEAL_SIZE   ( 0 )
+#endif
+
+/*----------------------------------------------------------------------------
+  Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+
+LR_ROM0 __ROM0_BASE __ROM0_SIZE  {
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  ER_CMSE_VENEER __ROM0_BASE+__ROM0_SIZE -__ROM0_SIZE {
+   *(Veneer$$CMSE)
+  }
+  #define ER_CMSE_VENEER_SIZE AlignExpr(ImageLength(ER_CMSE_VENEER), 8)
+#else
+  #define ER_CMSE_VENEER_SIZE 0
+#endif
+
+  ER_ROM0 __ROM0_BASE (__ROM0_SIZE - ER_CMSE_VENEER_SIZE) {
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   *(+RO +XO)
+  }
+
+  RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE) {
+    *(.bss.noinit)
+  }
+
+  RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
+    *(+RW +ZI)
+  }
+
+#if __HEAP_SIZE > 0
+  ARM_LIB_HEAP  (AlignExpr(+0, 8)) EMPTY __HEAP_SIZE  {   ; Reserve empty region for heap
+  }
+#endif
+
+  ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE {   ; Reserve empty region for stack
+  }
+
+#if __STACKSEAL_SIZE > 0
+  STACKSEAL +0 EMPTY 8 {             ; Reserve empty region for stack seal immediately after stack
+  }
+#endif
+
+#if __RAM1_SIZE > 0
+  RW_RAM1 __RAM1_BASE __RAM1_SIZE  {
+   .ANY (+RW +ZI)
+  }
+#endif
+
+#if __RAM2_SIZE > 0
+  RW_RAM2 __RAM2_BASE __RAM2_SIZE  {
+   .ANY (+RW +ZI)
+  }
+#endif
+
+#if __RAM3_SIZE > 0
+  RW_RAM3 __RAM3_BASE __RAM3_SIZE  {
+   .ANY (+RW +ZI)
+  }
+#endif
+}
+
+#if __ROM1_SIZE > 0
+LR_ROM1 __ROM1_BASE __ROM1_SIZE  {
+  ER_ROM1 +0 __ROM1_SIZE {
+   .ANY (+RO +XO)
+  }
+}
+#endif
+
+#if __ROM2_SIZE > 0
+LR_ROM2 __ROM2_BASE __ROM2_SIZE  {
+  ER_ROM2 +0 __ROM2_SIZE {
+   .ANY (+RO +XO)
+  }
+}
+#endif
+
+#if __ROM3_SIZE > 0
+LR_ROM3 __ROM3_BASE __ROM3_SIZE  {
+  ER_ROM3 +0 __ROM3_SIZE {
+   .ANY (+RO +XO)
+  }
+}
+#endif
diff --git a/Testing/cmsis_build/linker_scripts/ac6_m33_mps3_s.sct b/Testing/cmsis_build/linker_scripts/ac6_m33_mps3_s.sct
new file mode 100644
index 000000000..4d6e579d0
--- /dev/null
+++ b/Testing/cmsis_build/linker_scripts/ac6_m33_mps3_s.sct
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2023 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------------
+  Stack seal size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __STACKSEAL_SIZE   ( 8 )
+#else
+#define __STACKSEAL_SIZE   ( 0 )
+#endif
+
+/*----------------------------------------------------------------------------
+  Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+
+LR_ROM0 __ROM0_BASE __ROM0_SIZE  {
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  ER_CMSE_VENEER __ROM0_BASE+__ROM0_SIZE -__ROM0_SIZE {
+   *(Veneer$$CMSE)
+  }
+  #define ER_CMSE_VENEER_SIZE AlignExpr(ImageLength(ER_CMSE_VENEER), 8)
+#else
+  #define ER_CMSE_VENEER_SIZE 0
+#endif
+
+  ER_ROM0 __ROM0_BASE (__ROM0_SIZE - ER_CMSE_VENEER_SIZE) {
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   *(+RO +XO)
+  }
+
+  RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE) {
+    *(.bss.noinit)
+  }
+
+  RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
+    *(+RW +ZI)
+  }
+
+#if __HEAP_SIZE > 0
+  ARM_LIB_HEAP  (AlignExpr(+0, 8)) EMPTY __HEAP_SIZE  {   ; Reserve empty region for heap
+  }
+#endif
+
+  ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE {   ; Reserve empty region for stack
+  }
+
+#if __STACKSEAL_SIZE > 0
+  STACKSEAL +0 EMPTY 8 {             ; Reserve empty region for stack seal immediately after stack
+  }
+#endif
+
+#if __RAM1_SIZE > 0
+  RW_RAM1 __RAM1_BASE __RAM1_SIZE  {
+   .ANY (+RW +ZI)
+  }
+#endif
+
+#if __RAM2_SIZE > 0
+  RW_RAM2 __RAM2_BASE __RAM2_SIZE  {
+   .ANY (+RW +ZI)
+  }
+#endif
+
+#if __RAM3_SIZE > 0
+  RW_RAM3 __RAM3_BASE __RAM3_SIZE  {
+   .ANY (+RW +ZI)
+  }
+#endif
+}
+
+#if __ROM1_SIZE > 0
+LR_ROM1 __ROM1_BASE __ROM1_SIZE  {
+  ER_ROM1 +0 __ROM1_SIZE {
+   .ANY (+RO +XO)
+  }
+}
+#endif
+
+#if __ROM2_SIZE > 0
+LR_ROM2 __ROM2_BASE __ROM2_SIZE  {
+  ER_ROM2 +0 __ROM2_SIZE {
+   .ANY (+RO +XO)
+  }
+}
+#endif
+
+#if __ROM3_SIZE > 0
+LR_ROM3 __ROM3_BASE __ROM3_SIZE  {
+  ER_ROM3 +0 __ROM3_SIZE {
+   .ANY (+RO +XO)
+  }
+}
+#endif
diff --git a/Testing/cmsis_build/linker_scripts/ac6_m3_mps3_s.sct b/Testing/cmsis_build/linker_scripts/ac6_m3_mps3_s.sct
new file mode 100644
index 000000000..4d6e579d0
--- /dev/null
+++ b/Testing/cmsis_build/linker_scripts/ac6_m3_mps3_s.sct
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2023 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------------
+  Stack seal size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __STACKSEAL_SIZE   ( 8 )
+#else
+#define __STACKSEAL_SIZE   ( 0 )
+#endif
+
+/*----------------------------------------------------------------------------
+  Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+
+LR_ROM0 __ROM0_BASE __ROM0_SIZE  {
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  ER_CMSE_VENEER __ROM0_BASE+__ROM0_SIZE -__ROM0_SIZE {
+   *(Veneer$$CMSE)
+  }
+  #define ER_CMSE_VENEER_SIZE AlignExpr(ImageLength(ER_CMSE_VENEER), 8)
+#else
+  #define ER_CMSE_VENEER_SIZE 0
+#endif
+
+  ER_ROM0 __ROM0_BASE (__ROM0_SIZE - ER_CMSE_VENEER_SIZE) {
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   *(+RO +XO)
+  }
+
+  RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE) {
+    *(.bss.noinit)
+  }
+
+  RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
+    *(+RW +ZI)
+  }
+
+#if __HEAP_SIZE > 0
+  ARM_LIB_HEAP  (AlignExpr(+0, 8)) EMPTY __HEAP_SIZE  {   ; Reserve empty region for heap
+  }
+#endif
+
+  ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE {   ; Reserve empty region for stack
+  }
+
+#if __STACKSEAL_SIZE > 0
+  STACKSEAL +0 EMPTY 8 {             ; Reserve empty region for stack seal immediately after stack
+  }
+#endif
+
+#if __RAM1_SIZE > 0
+  RW_RAM1 __RAM1_BASE __RAM1_SIZE  {
+   .ANY (+RW +ZI)
+  }
+#endif
+
+#if __RAM2_SIZE > 0
+  RW_RAM2 __RAM2_BASE __RAM2_SIZE  {
+   .ANY (+RW +ZI)
+  }
+#endif
+
+#if __RAM3_SIZE > 0
+  RW_RAM3 __RAM3_BASE __RAM3_SIZE  {
+   .ANY (+RW +ZI)
+  }
+#endif
+}
+
+#if __ROM1_SIZE > 0
+LR_ROM1 __ROM1_BASE __ROM1_SIZE  {
+  ER_ROM1 +0 __ROM1_SIZE {
+   .ANY (+RO +XO)
+  }
+}
+#endif
+
+#if __ROM2_SIZE > 0
+LR_ROM2 __ROM2_BASE __ROM2_SIZE  {
+  ER_ROM2 +0 __ROM2_SIZE {
+   .ANY (+RO +XO)
+  }
+}
+#endif
+
+#if __ROM3_SIZE > 0
+LR_ROM3 __ROM3_BASE __ROM3_SIZE  {
+  ER_ROM3 +0 __ROM3_SIZE {
+   .ANY (+RO +XO)
+  }
+}
+#endif
diff --git a/Testing/cmsis_build/linker_scripts/ac6_m4_mps3_s.sct b/Testing/cmsis_build/linker_scripts/ac6_m4_mps3_s.sct
new file mode 100644
index 000000000..4d6e579d0
--- /dev/null
+++ b/Testing/cmsis_build/linker_scripts/ac6_m4_mps3_s.sct
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2023 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------------
+  Stack seal size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __STACKSEAL_SIZE   ( 8 )
+#else
+#define __STACKSEAL_SIZE   ( 0 )
+#endif
+
+/*----------------------------------------------------------------------------
+  Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+
+LR_ROM0 __ROM0_BASE __ROM0_SIZE  {
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  ER_CMSE_VENEER __ROM0_BASE+__ROM0_SIZE -__ROM0_SIZE {
+   *(Veneer$$CMSE)
+  }
+  #define ER_CMSE_VENEER_SIZE AlignExpr(ImageLength(ER_CMSE_VENEER), 8)
+#else
+  #define ER_CMSE_VENEER_SIZE 0
+#endif
+
+  ER_ROM0 __ROM0_BASE (__ROM0_SIZE - ER_CMSE_VENEER_SIZE) {
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   *(+RO +XO)
+  }
+
+  RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE) {
+    *(.bss.noinit)
+  }
+
+  RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
+    *(+RW +ZI)
+  }
+
+#if __HEAP_SIZE > 0
+  ARM_LIB_HEAP  (AlignExpr(+0, 8)) EMPTY __HEAP_SIZE  {   ; Reserve empty region for heap
+  }
+#endif
+
+  ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE {   ; Reserve empty region for stack
+  }
+
+#if __STACKSEAL_SIZE > 0
+  STACKSEAL +0 EMPTY 8 {             ; Reserve empty region for stack seal immediately after stack
+  }
+#endif
+
+#if __RAM1_SIZE > 0
+  RW_RAM1 __RAM1_BASE __RAM1_SIZE  {
+   .ANY (+RW +ZI)
+  }
+#endif
+
+#if __RAM2_SIZE > 0
+  RW_RAM2 __RAM2_BASE __RAM2_SIZE  {
+   .ANY (+RW +ZI)
+  }
+#endif
+
+#if __RAM3_SIZE > 0
+  RW_RAM3 __RAM3_BASE __RAM3_SIZE  {
+   .ANY (+RW +ZI)
+  }
+#endif
+}
+
+#if __ROM1_SIZE > 0
+LR_ROM1 __ROM1_BASE __ROM1_SIZE  {
+  ER_ROM1 +0 __ROM1_SIZE {
+   .ANY (+RO +XO)
+  }
+}
+#endif
+
+#if __ROM2_SIZE > 0
+LR_ROM2 __ROM2_BASE __ROM2_SIZE  {
+  ER_ROM2 +0 __ROM2_SIZE {
+   .ANY (+RO +XO)
+  }
+}
+#endif
+
+#if __ROM3_SIZE > 0
+LR_ROM3 __ROM3_BASE __ROM3_SIZE  {
+  ER_ROM3 +0 __ROM3_SIZE {
+   .ANY (+RO +XO)
+  }
+}
+#endif
diff --git a/Testing/cmsis_build/linker_scripts/ac6_m7_mps3_s.sct b/Testing/cmsis_build/linker_scripts/ac6_m7_mps3_s.sct
new file mode 100644
index 000000000..4d6e579d0
--- /dev/null
+++ b/Testing/cmsis_build/linker_scripts/ac6_m7_mps3_s.sct
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2023 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------------
+  Stack seal size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __STACKSEAL_SIZE   ( 8 )
+#else
+#define __STACKSEAL_SIZE   ( 0 )
+#endif
+
+/*----------------------------------------------------------------------------
+  Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+
+LR_ROM0 __ROM0_BASE __ROM0_SIZE  {
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  ER_CMSE_VENEER __ROM0_BASE+__ROM0_SIZE -__ROM0_SIZE {
+   *(Veneer$$CMSE)
+  }
+  #define ER_CMSE_VENEER_SIZE AlignExpr(ImageLength(ER_CMSE_VENEER), 8)
+#else
+  #define ER_CMSE_VENEER_SIZE 0
+#endif
+
+  ER_ROM0 __ROM0_BASE (__ROM0_SIZE - ER_CMSE_VENEER_SIZE) {
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   *(+RO +XO)
+  }
+
+  RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE) {
+    *(.bss.noinit)
+  }
+
+  RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
+    *(+RW +ZI)
+  }
+
+#if __HEAP_SIZE > 0
+  ARM_LIB_HEAP  (AlignExpr(+0, 8)) EMPTY __HEAP_SIZE  {   ; Reserve empty region for heap
+  }
+#endif
+
+  ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE {   ; Reserve empty region for stack
+  }
+
+#if __STACKSEAL_SIZE > 0
+  STACKSEAL +0 EMPTY 8 {             ; Reserve empty region for stack seal immediately after stack
+  }
+#endif
+
+#if __RAM1_SIZE > 0
+  RW_RAM1 __RAM1_BASE __RAM1_SIZE  {
+   .ANY (+RW +ZI)
+  }
+#endif
+
+#if __RAM2_SIZE > 0
+  RW_RAM2 __RAM2_BASE __RAM2_SIZE  {
+   .ANY (+RW +ZI)
+  }
+#endif
+
+#if __RAM3_SIZE > 0
+  RW_RAM3 __RAM3_BASE __RAM3_SIZE  {
+   .ANY (+RW +ZI)
+  }
+#endif
+}
+
+#if __ROM1_SIZE > 0
+LR_ROM1 __ROM1_BASE __ROM1_SIZE  {
+  ER_ROM1 +0 __ROM1_SIZE {
+   .ANY (+RO +XO)
+  }
+}
+#endif
+
+#if __ROM2_SIZE > 0
+LR_ROM2 __ROM2_BASE __ROM2_SIZE  {
+  ER_ROM2 +0 __ROM2_SIZE {
+   .ANY (+RO +XO)
+  }
+}
+#endif
+
+#if __ROM3_SIZE > 0
+LR_ROM3 __ROM3_BASE __ROM3_SIZE  {
+  ER_ROM3 +0 __ROM3_SIZE {
+   .ANY (+RO +XO)
+  }
+}
+#endif
diff --git a/Testing/cmsis_build/linker_scripts/ac6_sse300_mps3_s.sct b/Testing/cmsis_build/linker_scripts/ac6_sse300_mps3_s.sct
new file mode 100644
index 000000000..f7cedacaa
--- /dev/null
+++ b/Testing/cmsis_build/linker_scripts/ac6_sse300_mps3_s.sct
@@ -0,0 +1,79 @@
+
+;/*
+; * Copyright (c) 2018-2021 Arm Limited. All rights reserved.
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; *     http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; */
+
+;#include "region_defs.h"
+
+LR_CODE S_DDR4_START {
+    ER_CODE S_DDR4_START {
+        *.o (RESET +First)
+        .ANY (+RO)
+        /* different test vectors */
+        * (InRoot$$Sections)
+    }
+
+    /*
+     * Place the CMSE Veneers (containing the SG instruction) after the code, in
+     * a separate 32 bytes aligned region so that the SAU can programmed to just
+     * set this region as Non-Secure Callable. The maximum size of this
+     * executable region makes it only used the space left over by the ER_CODE
+     * region so that you can rely on code+veneer size combined will not exceed
+     * the S_CODE_SIZE value. We also substract from the available space the
+     * area used to align this section on 32 bytes boundary (for SAU conf).
+     */
+    ER_CODE_CMSE_VENEER +0 ALIGN 32 {
+        *(Veneer$$CMSE)
+    }
+    /*
+     * This dummy region ensures that the next one will be aligned on a 32 bytes
+     * boundary, so that the following region will not be mistakenly configured
+     * as Non-Secure Callable by the SAU.
+     */
+    ER_CODE_CMSE_VENEER_DUMMY +0 ALIGN 32 EMPTY 0 {}
+
+    /* This empty, zero long execution region is here to mark the limit address
+     * of the last execution region that is allocated in SRAM.
+     */
+    CODE_WATERMARK +0 EMPTY 0x0 {
+    }
+    /* Make sure that the sections allocated in the SRAM does not exceed the
+     * size of the SRAM available.
+     */
+    ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_DDR4_START + S_DDR4_SIZE)
+
+    ER_DATA +0 ALIGN 32  {
+        .ANY (+ZI +RW)
+    }
+
+    #if HEAP_SIZE > 0
+    ARM_LIB_HEAP +0 ALIGN 8 EMPTY  HEAP_SIZE  {   ; Reserve empty region for heap
+    }
+    #endif
+
+    ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE {   ; Reserve empty region for stack
+    }
+
+    /* This empty, zero long execution region is here to mark the limit address
+     * of the last execution region that is allocated in SRAM.
+     */
+    SRAM_WATERMARK +0 EMPTY 0x0 {
+    }
+    /* Make sure that the sections allocated in the SRAM does not exceed the
+     * size of the SRAM available.
+     */
+    ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DDR4_START + S_DDR4_SIZE)
+}
diff --git a/Testing/cmsis_build/linker_scripts/ac6_sse310_mps3_s.sct b/Testing/cmsis_build/linker_scripts/ac6_sse310_mps3_s.sct
new file mode 100644
index 000000000..0650639f8
--- /dev/null
+++ b/Testing/cmsis_build/linker_scripts/ac6_sse310_mps3_s.sct
@@ -0,0 +1,60 @@
+
+;/*
+; * Copyright (c) 2018-2021 Arm Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; *     http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; */
+
+
+
+LR_CODE S_CODE_START {
+    ER_CODE S_CODE_START {
+        *.o (RESET +First)
+        .ANY (+RO)
+        /* different test vectors */
+        * (InRoot$$Sections)
+    }
+
+    /* This empty, zero long execution region is here to mark the limit address
+     * of the last execution region that is allocated in SRAM.
+     */
+    CODE_WATERMARK +0 EMPTY 0x0 {
+    }
+    /* Make sure that the sections allocated in the SRAM does not exceed the
+     * size of the SRAM available.
+     */
+    ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE)
+
+    ER_DATA S_DATA_START {
+        .ANY (+ZI +RW +RO-DATA)
+    }
+
+    #if HEAP_SIZE > 0
+    ARM_LIB_HEAP +0 ALIGN 8 EMPTY  HEAP_SIZE  {   ; Reserve empty region for heap
+    }
+    #endif
+
+    ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE {   ; Reserve empty region for stack
+    }
+
+    /* This empty, zero long execution region is here to mark the limit address
+     * of the last execution region that is allocated in SRAM.
+     */
+    SRAM_WATERMARK +0 EMPTY 0x0 {
+    }
+    /* Make sure that the sections allocated in the SRAM does not exceed the
+     * size of the SRAM available.
+     */
+    ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE)
+}
diff --git a/Testing/cmsis_build/linker_scripts/clang_m0p_mps3.ld b/Testing/cmsis_build/linker_scripts/clang_m0p_mps3.ld
new file mode 100644
index 000000000..40f955c16
--- /dev/null
+++ b/Testing/cmsis_build/linker_scripts/clang_m0p_mps3.ld
@@ -0,0 +1,353 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright © 2019 Keith Packard
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above
+ *    copyright notice, this list of conditions and the following
+ *    disclaimer in the documentation and/or other materials provided
+ *    with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* ----------------------------------------------------------------------------
+  Stack seal size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __STACKSEAL_SIZE   ( 8 )
+#else
+#define __STACKSEAL_SIZE   ( 0 )
+#endif
+
+/* ----------------------------------------------------------------------------
+  Memory definition
+ *----------------------------------------------------------------------------*/
+MEMORY
+{
+  ROM0  (rx!w)  : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE
+#if __ROM1_SIZE > 0
+  ROM1  (rx!w)  : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE
+#endif
+#if __ROM2_SIZE > 0
+  ROM2  (rx!w)  : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE
+#endif
+#if __ROM3_SIZE > 0
+  ROM3  (rx!w)  : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE
+#endif
+
+  RAM0  (w!rx) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE
+#if __RAM1_SIZE > 0
+  RAM1  (w!rx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE
+#endif
+#if __RAM2_SIZE > 0
+  RAM2  (w!rx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE
+#endif
+#if __RAM3_SIZE > 0
+  RAM3  (w!rx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE
+#endif
+}
+
+ENTRY(Reset_Handler)
+
+PHDRS
+{
+	text PT_LOAD;
+	ram PT_LOAD;
+	ram_init PT_LOAD;
+	tls PT_TLS;
+}
+
+SECTIONS
+{
+	.init : {
+		KEEP (*(.vectors))
+		KEEP (*(.text.init.enter))
+		KEEP (*(.data.init.enter))
+		KEEP (*(SORT_BY_NAME(.init) SORT_BY_NAME(.init.*)))
+	} >ROM0 AT>ROM0 :text
+
+	.text : {
+
+		/* code */
+		*(.text.unlikely .text.unlikely.*)
+		*(.text.startup .text.startup.*)
+		*(.text .text.* .opd .opd.*)
+		*(.gnu.linkonce.t.*)
+		KEEP (*(.fini .fini.*))
+		__text_end = .;
+
+		PROVIDE (__etext = __text_end);
+		PROVIDE (_etext = __text_end);
+		PROVIDE (etext = __text_end);
+
+		/* read-only data */
+		*(.rdata)
+		*(.rodata .rodata.*)
+		*(.gnu.linkonce.r.*)
+
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
+		*(.data.rel.ro .data.rel.ro.*)
+		*(.got .got.*)
+
+		/* Need to pre-align so that the symbols come after padding */
+		. = ALIGN(8);
+
+		/* lists of constructors and destructors */
+		PROVIDE_HIDDEN ( __preinit_array_start = . );
+		KEEP (*(.preinit_array))
+		PROVIDE_HIDDEN ( __preinit_array_end = . );
+
+		PROVIDE_HIDDEN ( __init_array_start = . );
+		KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+		KEEP (*(.init_array .ctors))
+		PROVIDE_HIDDEN ( __init_array_end = . );
+
+		PROVIDE_HIDDEN ( __fini_array_start = . );
+		KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+		KEEP (*(.fini_array .dtors))
+		PROVIDE_HIDDEN ( __fini_array_end = . );
+
+	} >ROM0 AT>ROM0 :text
+
+	.toc : {
+		*(.toc .toc.*)
+	} >ROM0 AT>ROM0 :text
+
+	/* additional sections when compiling with C++ exception support */
+	
+	.except_ordered : {
+		*(.gcc_except_table *.gcc_except_table.*)
+		KEEP (*(.eh_frame .eh_frame.*))
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} >ROM0 AT>ROM0 :text
+
+	.except_unordered : {
+		. = ALIGN(8);
+
+		PROVIDE(__exidx_start = .);
+		*(.ARM.exidx*)
+		PROVIDE(__exidx_end = .);
+	} >ROM0 AT>ROM0 :text
+	
+
+	/*
+	 * Data values which are preserved across reset
+	 */
+	.preserve (NOLOAD) : {
+		PROVIDE(__preserve_start__ = .);
+		KEEP(*(SORT_BY_NAME(.preserve.*)))
+		KEEP(*(.preserve))
+		PROVIDE(__preserve_end__ = .);
+	} >RAM0 AT>RAM0 :ram
+
+	.data :  {
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+
+		/* Need to pre-align so that the symbols come after padding */
+		. = ALIGN(8);
+
+		PROVIDE( __global_pointer$ = . + 0x800 );
+		*(.sdata .sdata.* .sdata2.*)
+		*(.gnu.linkonce.s.*)
+	} >RAM0 AT>ROM0 :ram_init
+	PROVIDE(__data_start = ADDR(.data));
+	PROVIDE(__data_source = LOADADDR(.data));
+
+	/* Thread local initialized data. This gets
+	 * space allocated as it is expected to be placed
+	 * in ram to be used as a template for TLS data blocks
+	 * allocated at runtime. We're slightly abusing that
+	 * by placing the data in flash where it will be copied
+	 * into the allocate ram addresses by the existing
+	 * data initialization code in crt0
+	 */
+	.tdata :  {
+		*(.tdata .tdata.* .gnu.linkonce.td.*)
+		PROVIDE(__data_end = .);
+		PROVIDE(__tdata_end = .);
+	} >RAM0 AT>ROM0 :tls :ram_init
+	PROVIDE( __tls_base = ADDR(.tdata));
+	PROVIDE( __tdata_start = ADDR(.tdata));
+	PROVIDE( __tdata_source = LOADADDR(.tdata) );
+	PROVIDE( __tdata_source_end = LOADADDR(.tdata) + SIZEOF(.tdata) );
+	PROVIDE( __data_source_end = __tdata_source_end );
+	PROVIDE( __tdata_size = SIZEOF(.tdata) );
+	PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) );
+
+	PROVIDE( __edata = __data_end );
+	PROVIDE( _edata = __data_end );
+	PROVIDE( edata = __data_end );
+	PROVIDE( __data_size = __data_end - __data_start );
+	PROVIDE( __data_source_size = __data_source_end - __data_source );
+
+	.tbss (NOLOAD) : {
+		*(.tbss .tbss.* .gnu.linkonce.tb.*)
+		*(.tcommon)
+		PROVIDE( __tls_end = . );
+		PROVIDE( __tbss_end = . );
+	} >RAM0 AT>RAM0 :tls :ram
+	PROVIDE( __bss_start = ADDR(.tbss));
+	PROVIDE( __tbss_start = ADDR(.tbss));
+	PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) );
+	PROVIDE( __tbss_size = SIZEOF(.tbss) );
+	PROVIDE( __tls_size = __tls_end - __tls_base );
+	PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) );
+	PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) );
+	PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) );
+
+	/*
+	 * The linker special cases .tbss segments which are
+	 * identified as segments which are not loaded and are
+	 * thread_local.
+	 *
+	 * For these segments, the linker does not advance 'dot'
+	 * across them.  We actually need memory allocated for tbss,
+	 * so we create a special segment here just to make room
+	 */
+	/*
+	.tbss_space (NOLOAD) : {
+		. = ADDR(.tbss);
+		. = . + SIZEOF(.tbss);
+	} >RAM0 AT>RAM0 :ram
+	*/
+
+	.bss (NOLOAD) : {
+		*(.sbss*)
+		*(.gnu.linkonce.sb.*)
+		*(.bss .bss.*)
+		*(.gnu.linkonce.b.*)
+		*(COMMON)
+
+		/* Align the heap */
+		. = ALIGN(8);
+		__bss_end = .;
+	} >RAM0 AT>RAM0 :ram
+	PROVIDE( __non_tls_bss_start = ADDR(.bss) );
+	PROVIDE( __end = __bss_end );
+	PROVIDE( _end = __bss_end );
+	PROVIDE( end = __bss_end );
+	PROVIDE( __bss_size = __bss_end - __bss_start );
+
+	/* Make the rest of memory available for heap storage */
+	PROVIDE (__heap_start = __end);
+#ifdef __HEAP_SIZE
+	PROVIDE (__heap_end = __heap_start + __HEAP_SIZE);
+	PROVIDE (__heap_size = __HEAP_SIZE);
+#else
+	PROVIDE (__heap_end = __stack - __STACK_SIZE);
+	PROVIDE (__heap_size = __heap_end - __heap_start);
+#endif
+	.heap (NOLOAD) : {
+		. += __heap_size;
+	} >RAM0 :ram
+
+	/* Define a stack region to make sure it fits in memory */
+	PROVIDE(__stack = ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE);
+	PROVIDE(__stack_limit = __stack - __STACK_SIZE);
+	.stack (__stack_limit) (NOLOAD) : {
+		. += __STACK_SIZE;
+	} >RAM0 :ram
+
+#if __STACKSEAL_SIZE > 0
+	PROVIDE(__stack_seal = __stack)
+  	.stackseal (__stack) (NOLOAD) :
+  	{
+    	. += __STACKSEAL_SIZE;
+  	} >RAM0 :ram
+#endif
+
+	/* Throw away C++ exception handling information */
+
+	/*
+
+	/DISCARD/ : {
+		*(.note .note.*)
+		*(.eh_frame .eh_frame.*)
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+		*(.ARM.exidx*)
+	}
+
+	*/
+
+	/* Stabs debugging sections.  */
+	.stab          0 : { *(.stab) }
+	.stabstr       0 : { *(.stabstr) }
+	.stab.excl     0 : { *(.stab.excl) }
+	.stab.exclstr  0 : { *(.stab.exclstr) }
+	.stab.index    0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment       0 : { *(.comment) }
+	.gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) }
+	/* DWARF debug sections.
+	   Symbols in the DWARF debugging sections are relative to the beginning
+	   of the section so we begin them at 0.  */
+	/* DWARF 1.  */
+	.debug          0 : { *(.debug) }
+	.line           0 : { *(.line) }
+	/* GNU DWARF 1 extensions.  */
+	.debug_srcinfo  0 : { *(.debug_srcinfo) }
+	.debug_sfnames  0 : { *(.debug_sfnames) }
+	/* DWARF 1.1 and DWARF 2.  */
+	.debug_aranges  0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	/* DWARF 2.  */
+	.debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+	.debug_abbrev   0 : { *(.debug_abbrev) }
+	.debug_line     0 : { *(.debug_line .debug_line.* .debug_line_end) }
+	.debug_frame    0 : { *(.debug_frame) }
+	.debug_str      0 : { *(.debug_str) }
+	.debug_loc      0 : { *(.debug_loc) }
+	.debug_macinfo  0 : { *(.debug_macinfo) }
+	/* SGI/MIPS DWARF 2 extensions.  */
+	.debug_weaknames 0 : { *(.debug_weaknames) }
+	.debug_funcnames 0 : { *(.debug_funcnames) }
+	.debug_typenames 0 : { *(.debug_typenames) }
+	.debug_varnames  0 : { *(.debug_varnames) }
+	/* DWARF 3.  */
+	.debug_pubtypes 0 : { *(.debug_pubtypes) }
+	.debug_ranges   0 : { *(.debug_ranges) }
+	/* DWARF 5.  */
+	.debug_addr     0 : { *(.debug_addr) }
+	.debug_line_str 0 : { *(.debug_line_str) }
+	.debug_loclists 0 : { *(.debug_loclists) }
+	.debug_macro    0 : { *(.debug_macro) }
+	.debug_names    0 : { *(.debug_names) }
+	.debug_rnglists 0 : { *(.debug_rnglists) }
+	.debug_str_offsets 0 : { *(.debug_str_offsets) }
+	.debug_sup      0 : { *(.debug_sup) }
+	.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
+}
+/*
+ * Check that sections that are copied from flash to RAM have matching
+ * padding, so that a single memcpy() of __data_size copies the correct bytes.
+ */
+ASSERT( __data_size == __data_source_size,
+	"ERROR: .data/.tdata flash size does not match RAM size");
diff --git a/Testing/cmsis_build/linker_scripts/clang_m33_mps3.ld b/Testing/cmsis_build/linker_scripts/clang_m33_mps3.ld
new file mode 100644
index 000000000..40f955c16
--- /dev/null
+++ b/Testing/cmsis_build/linker_scripts/clang_m33_mps3.ld
@@ -0,0 +1,353 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright © 2019 Keith Packard
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above
+ *    copyright notice, this list of conditions and the following
+ *    disclaimer in the documentation and/or other materials provided
+ *    with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* ----------------------------------------------------------------------------
+  Stack seal size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __STACKSEAL_SIZE   ( 8 )
+#else
+#define __STACKSEAL_SIZE   ( 0 )
+#endif
+
+/* ----------------------------------------------------------------------------
+  Memory definition
+ *----------------------------------------------------------------------------*/
+MEMORY
+{
+  ROM0  (rx!w)  : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE
+#if __ROM1_SIZE > 0
+  ROM1  (rx!w)  : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE
+#endif
+#if __ROM2_SIZE > 0
+  ROM2  (rx!w)  : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE
+#endif
+#if __ROM3_SIZE > 0
+  ROM3  (rx!w)  : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE
+#endif
+
+  RAM0  (w!rx) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE
+#if __RAM1_SIZE > 0
+  RAM1  (w!rx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE
+#endif
+#if __RAM2_SIZE > 0
+  RAM2  (w!rx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE
+#endif
+#if __RAM3_SIZE > 0
+  RAM3  (w!rx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE
+#endif
+}
+
+ENTRY(Reset_Handler)
+
+PHDRS
+{
+	text PT_LOAD;
+	ram PT_LOAD;
+	ram_init PT_LOAD;
+	tls PT_TLS;
+}
+
+SECTIONS
+{
+	.init : {
+		KEEP (*(.vectors))
+		KEEP (*(.text.init.enter))
+		KEEP (*(.data.init.enter))
+		KEEP (*(SORT_BY_NAME(.init) SORT_BY_NAME(.init.*)))
+	} >ROM0 AT>ROM0 :text
+
+	.text : {
+
+		/* code */
+		*(.text.unlikely .text.unlikely.*)
+		*(.text.startup .text.startup.*)
+		*(.text .text.* .opd .opd.*)
+		*(.gnu.linkonce.t.*)
+		KEEP (*(.fini .fini.*))
+		__text_end = .;
+
+		PROVIDE (__etext = __text_end);
+		PROVIDE (_etext = __text_end);
+		PROVIDE (etext = __text_end);
+
+		/* read-only data */
+		*(.rdata)
+		*(.rodata .rodata.*)
+		*(.gnu.linkonce.r.*)
+
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
+		*(.data.rel.ro .data.rel.ro.*)
+		*(.got .got.*)
+
+		/* Need to pre-align so that the symbols come after padding */
+		. = ALIGN(8);
+
+		/* lists of constructors and destructors */
+		PROVIDE_HIDDEN ( __preinit_array_start = . );
+		KEEP (*(.preinit_array))
+		PROVIDE_HIDDEN ( __preinit_array_end = . );
+
+		PROVIDE_HIDDEN ( __init_array_start = . );
+		KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+		KEEP (*(.init_array .ctors))
+		PROVIDE_HIDDEN ( __init_array_end = . );
+
+		PROVIDE_HIDDEN ( __fini_array_start = . );
+		KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+		KEEP (*(.fini_array .dtors))
+		PROVIDE_HIDDEN ( __fini_array_end = . );
+
+	} >ROM0 AT>ROM0 :text
+
+	.toc : {
+		*(.toc .toc.*)
+	} >ROM0 AT>ROM0 :text
+
+	/* additional sections when compiling with C++ exception support */
+	
+	.except_ordered : {
+		*(.gcc_except_table *.gcc_except_table.*)
+		KEEP (*(.eh_frame .eh_frame.*))
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} >ROM0 AT>ROM0 :text
+
+	.except_unordered : {
+		. = ALIGN(8);
+
+		PROVIDE(__exidx_start = .);
+		*(.ARM.exidx*)
+		PROVIDE(__exidx_end = .);
+	} >ROM0 AT>ROM0 :text
+	
+
+	/*
+	 * Data values which are preserved across reset
+	 */
+	.preserve (NOLOAD) : {
+		PROVIDE(__preserve_start__ = .);
+		KEEP(*(SORT_BY_NAME(.preserve.*)))
+		KEEP(*(.preserve))
+		PROVIDE(__preserve_end__ = .);
+	} >RAM0 AT>RAM0 :ram
+
+	.data :  {
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+
+		/* Need to pre-align so that the symbols come after padding */
+		. = ALIGN(8);
+
+		PROVIDE( __global_pointer$ = . + 0x800 );
+		*(.sdata .sdata.* .sdata2.*)
+		*(.gnu.linkonce.s.*)
+	} >RAM0 AT>ROM0 :ram_init
+	PROVIDE(__data_start = ADDR(.data));
+	PROVIDE(__data_source = LOADADDR(.data));
+
+	/* Thread local initialized data. This gets
+	 * space allocated as it is expected to be placed
+	 * in ram to be used as a template for TLS data blocks
+	 * allocated at runtime. We're slightly abusing that
+	 * by placing the data in flash where it will be copied
+	 * into the allocate ram addresses by the existing
+	 * data initialization code in crt0
+	 */
+	.tdata :  {
+		*(.tdata .tdata.* .gnu.linkonce.td.*)
+		PROVIDE(__data_end = .);
+		PROVIDE(__tdata_end = .);
+	} >RAM0 AT>ROM0 :tls :ram_init
+	PROVIDE( __tls_base = ADDR(.tdata));
+	PROVIDE( __tdata_start = ADDR(.tdata));
+	PROVIDE( __tdata_source = LOADADDR(.tdata) );
+	PROVIDE( __tdata_source_end = LOADADDR(.tdata) + SIZEOF(.tdata) );
+	PROVIDE( __data_source_end = __tdata_source_end );
+	PROVIDE( __tdata_size = SIZEOF(.tdata) );
+	PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) );
+
+	PROVIDE( __edata = __data_end );
+	PROVIDE( _edata = __data_end );
+	PROVIDE( edata = __data_end );
+	PROVIDE( __data_size = __data_end - __data_start );
+	PROVIDE( __data_source_size = __data_source_end - __data_source );
+
+	.tbss (NOLOAD) : {
+		*(.tbss .tbss.* .gnu.linkonce.tb.*)
+		*(.tcommon)
+		PROVIDE( __tls_end = . );
+		PROVIDE( __tbss_end = . );
+	} >RAM0 AT>RAM0 :tls :ram
+	PROVIDE( __bss_start = ADDR(.tbss));
+	PROVIDE( __tbss_start = ADDR(.tbss));
+	PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) );
+	PROVIDE( __tbss_size = SIZEOF(.tbss) );
+	PROVIDE( __tls_size = __tls_end - __tls_base );
+	PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) );
+	PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) );
+	PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) );
+
+	/*
+	 * The linker special cases .tbss segments which are
+	 * identified as segments which are not loaded and are
+	 * thread_local.
+	 *
+	 * For these segments, the linker does not advance 'dot'
+	 * across them.  We actually need memory allocated for tbss,
+	 * so we create a special segment here just to make room
+	 */
+	/*
+	.tbss_space (NOLOAD) : {
+		. = ADDR(.tbss);
+		. = . + SIZEOF(.tbss);
+	} >RAM0 AT>RAM0 :ram
+	*/
+
+	.bss (NOLOAD) : {
+		*(.sbss*)
+		*(.gnu.linkonce.sb.*)
+		*(.bss .bss.*)
+		*(.gnu.linkonce.b.*)
+		*(COMMON)
+
+		/* Align the heap */
+		. = ALIGN(8);
+		__bss_end = .;
+	} >RAM0 AT>RAM0 :ram
+	PROVIDE( __non_tls_bss_start = ADDR(.bss) );
+	PROVIDE( __end = __bss_end );
+	PROVIDE( _end = __bss_end );
+	PROVIDE( end = __bss_end );
+	PROVIDE( __bss_size = __bss_end - __bss_start );
+
+	/* Make the rest of memory available for heap storage */
+	PROVIDE (__heap_start = __end);
+#ifdef __HEAP_SIZE
+	PROVIDE (__heap_end = __heap_start + __HEAP_SIZE);
+	PROVIDE (__heap_size = __HEAP_SIZE);
+#else
+	PROVIDE (__heap_end = __stack - __STACK_SIZE);
+	PROVIDE (__heap_size = __heap_end - __heap_start);
+#endif
+	.heap (NOLOAD) : {
+		. += __heap_size;
+	} >RAM0 :ram
+
+	/* Define a stack region to make sure it fits in memory */
+	PROVIDE(__stack = ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE);
+	PROVIDE(__stack_limit = __stack - __STACK_SIZE);
+	.stack (__stack_limit) (NOLOAD) : {
+		. += __STACK_SIZE;
+	} >RAM0 :ram
+
+#if __STACKSEAL_SIZE > 0
+	PROVIDE(__stack_seal = __stack)
+  	.stackseal (__stack) (NOLOAD) :
+  	{
+    	. += __STACKSEAL_SIZE;
+  	} >RAM0 :ram
+#endif
+
+	/* Throw away C++ exception handling information */
+
+	/*
+
+	/DISCARD/ : {
+		*(.note .note.*)
+		*(.eh_frame .eh_frame.*)
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+		*(.ARM.exidx*)
+	}
+
+	*/
+
+	/* Stabs debugging sections.  */
+	.stab          0 : { *(.stab) }
+	.stabstr       0 : { *(.stabstr) }
+	.stab.excl     0 : { *(.stab.excl) }
+	.stab.exclstr  0 : { *(.stab.exclstr) }
+	.stab.index    0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment       0 : { *(.comment) }
+	.gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) }
+	/* DWARF debug sections.
+	   Symbols in the DWARF debugging sections are relative to the beginning
+	   of the section so we begin them at 0.  */
+	/* DWARF 1.  */
+	.debug          0 : { *(.debug) }
+	.line           0 : { *(.line) }
+	/* GNU DWARF 1 extensions.  */
+	.debug_srcinfo  0 : { *(.debug_srcinfo) }
+	.debug_sfnames  0 : { *(.debug_sfnames) }
+	/* DWARF 1.1 and DWARF 2.  */
+	.debug_aranges  0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	/* DWARF 2.  */
+	.debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+	.debug_abbrev   0 : { *(.debug_abbrev) }
+	.debug_line     0 : { *(.debug_line .debug_line.* .debug_line_end) }
+	.debug_frame    0 : { *(.debug_frame) }
+	.debug_str      0 : { *(.debug_str) }
+	.debug_loc      0 : { *(.debug_loc) }
+	.debug_macinfo  0 : { *(.debug_macinfo) }
+	/* SGI/MIPS DWARF 2 extensions.  */
+	.debug_weaknames 0 : { *(.debug_weaknames) }
+	.debug_funcnames 0 : { *(.debug_funcnames) }
+	.debug_typenames 0 : { *(.debug_typenames) }
+	.debug_varnames  0 : { *(.debug_varnames) }
+	/* DWARF 3.  */
+	.debug_pubtypes 0 : { *(.debug_pubtypes) }
+	.debug_ranges   0 : { *(.debug_ranges) }
+	/* DWARF 5.  */
+	.debug_addr     0 : { *(.debug_addr) }
+	.debug_line_str 0 : { *(.debug_line_str) }
+	.debug_loclists 0 : { *(.debug_loclists) }
+	.debug_macro    0 : { *(.debug_macro) }
+	.debug_names    0 : { *(.debug_names) }
+	.debug_rnglists 0 : { *(.debug_rnglists) }
+	.debug_str_offsets 0 : { *(.debug_str_offsets) }
+	.debug_sup      0 : { *(.debug_sup) }
+	.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
+}
+/*
+ * Check that sections that are copied from flash to RAM have matching
+ * padding, so that a single memcpy() of __data_size copies the correct bytes.
+ */
+ASSERT( __data_size == __data_source_size,
+	"ERROR: .data/.tdata flash size does not match RAM size");
diff --git a/Testing/cmsis_build/linker_scripts/clang_m3_mps3.ld b/Testing/cmsis_build/linker_scripts/clang_m3_mps3.ld
new file mode 100644
index 000000000..40f955c16
--- /dev/null
+++ b/Testing/cmsis_build/linker_scripts/clang_m3_mps3.ld
@@ -0,0 +1,353 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright © 2019 Keith Packard
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above
+ *    copyright notice, this list of conditions and the following
+ *    disclaimer in the documentation and/or other materials provided
+ *    with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* ----------------------------------------------------------------------------
+  Stack seal size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __STACKSEAL_SIZE   ( 8 )
+#else
+#define __STACKSEAL_SIZE   ( 0 )
+#endif
+
+/* ----------------------------------------------------------------------------
+  Memory definition
+ *----------------------------------------------------------------------------*/
+MEMORY
+{
+  ROM0  (rx!w)  : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE
+#if __ROM1_SIZE > 0
+  ROM1  (rx!w)  : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE
+#endif
+#if __ROM2_SIZE > 0
+  ROM2  (rx!w)  : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE
+#endif
+#if __ROM3_SIZE > 0
+  ROM3  (rx!w)  : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE
+#endif
+
+  RAM0  (w!rx) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE
+#if __RAM1_SIZE > 0
+  RAM1  (w!rx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE
+#endif
+#if __RAM2_SIZE > 0
+  RAM2  (w!rx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE
+#endif
+#if __RAM3_SIZE > 0
+  RAM3  (w!rx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE
+#endif
+}
+
+ENTRY(Reset_Handler)
+
+PHDRS
+{
+	text PT_LOAD;
+	ram PT_LOAD;
+	ram_init PT_LOAD;
+	tls PT_TLS;
+}
+
+SECTIONS
+{
+	.init : {
+		KEEP (*(.vectors))
+		KEEP (*(.text.init.enter))
+		KEEP (*(.data.init.enter))
+		KEEP (*(SORT_BY_NAME(.init) SORT_BY_NAME(.init.*)))
+	} >ROM0 AT>ROM0 :text
+
+	.text : {
+
+		/* code */
+		*(.text.unlikely .text.unlikely.*)
+		*(.text.startup .text.startup.*)
+		*(.text .text.* .opd .opd.*)
+		*(.gnu.linkonce.t.*)
+		KEEP (*(.fini .fini.*))
+		__text_end = .;
+
+		PROVIDE (__etext = __text_end);
+		PROVIDE (_etext = __text_end);
+		PROVIDE (etext = __text_end);
+
+		/* read-only data */
+		*(.rdata)
+		*(.rodata .rodata.*)
+		*(.gnu.linkonce.r.*)
+
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
+		*(.data.rel.ro .data.rel.ro.*)
+		*(.got .got.*)
+
+		/* Need to pre-align so that the symbols come after padding */
+		. = ALIGN(8);
+
+		/* lists of constructors and destructors */
+		PROVIDE_HIDDEN ( __preinit_array_start = . );
+		KEEP (*(.preinit_array))
+		PROVIDE_HIDDEN ( __preinit_array_end = . );
+
+		PROVIDE_HIDDEN ( __init_array_start = . );
+		KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+		KEEP (*(.init_array .ctors))
+		PROVIDE_HIDDEN ( __init_array_end = . );
+
+		PROVIDE_HIDDEN ( __fini_array_start = . );
+		KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+		KEEP (*(.fini_array .dtors))
+		PROVIDE_HIDDEN ( __fini_array_end = . );
+
+	} >ROM0 AT>ROM0 :text
+
+	.toc : {
+		*(.toc .toc.*)
+	} >ROM0 AT>ROM0 :text
+
+	/* additional sections when compiling with C++ exception support */
+	
+	.except_ordered : {
+		*(.gcc_except_table *.gcc_except_table.*)
+		KEEP (*(.eh_frame .eh_frame.*))
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} >ROM0 AT>ROM0 :text
+
+	.except_unordered : {
+		. = ALIGN(8);
+
+		PROVIDE(__exidx_start = .);
+		*(.ARM.exidx*)
+		PROVIDE(__exidx_end = .);
+	} >ROM0 AT>ROM0 :text
+	
+
+	/*
+	 * Data values which are preserved across reset
+	 */
+	.preserve (NOLOAD) : {
+		PROVIDE(__preserve_start__ = .);
+		KEEP(*(SORT_BY_NAME(.preserve.*)))
+		KEEP(*(.preserve))
+		PROVIDE(__preserve_end__ = .);
+	} >RAM0 AT>RAM0 :ram
+
+	.data :  {
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+
+		/* Need to pre-align so that the symbols come after padding */
+		. = ALIGN(8);
+
+		PROVIDE( __global_pointer$ = . + 0x800 );
+		*(.sdata .sdata.* .sdata2.*)
+		*(.gnu.linkonce.s.*)
+	} >RAM0 AT>ROM0 :ram_init
+	PROVIDE(__data_start = ADDR(.data));
+	PROVIDE(__data_source = LOADADDR(.data));
+
+	/* Thread local initialized data. This gets
+	 * space allocated as it is expected to be placed
+	 * in ram to be used as a template for TLS data blocks
+	 * allocated at runtime. We're slightly abusing that
+	 * by placing the data in flash where it will be copied
+	 * into the allocate ram addresses by the existing
+	 * data initialization code in crt0
+	 */
+	.tdata :  {
+		*(.tdata .tdata.* .gnu.linkonce.td.*)
+		PROVIDE(__data_end = .);
+		PROVIDE(__tdata_end = .);
+	} >RAM0 AT>ROM0 :tls :ram_init
+	PROVIDE( __tls_base = ADDR(.tdata));
+	PROVIDE( __tdata_start = ADDR(.tdata));
+	PROVIDE( __tdata_source = LOADADDR(.tdata) );
+	PROVIDE( __tdata_source_end = LOADADDR(.tdata) + SIZEOF(.tdata) );
+	PROVIDE( __data_source_end = __tdata_source_end );
+	PROVIDE( __tdata_size = SIZEOF(.tdata) );
+	PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) );
+
+	PROVIDE( __edata = __data_end );
+	PROVIDE( _edata = __data_end );
+	PROVIDE( edata = __data_end );
+	PROVIDE( __data_size = __data_end - __data_start );
+	PROVIDE( __data_source_size = __data_source_end - __data_source );
+
+	.tbss (NOLOAD) : {
+		*(.tbss .tbss.* .gnu.linkonce.tb.*)
+		*(.tcommon)
+		PROVIDE( __tls_end = . );
+		PROVIDE( __tbss_end = . );
+	} >RAM0 AT>RAM0 :tls :ram
+	PROVIDE( __bss_start = ADDR(.tbss));
+	PROVIDE( __tbss_start = ADDR(.tbss));
+	PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) );
+	PROVIDE( __tbss_size = SIZEOF(.tbss) );
+	PROVIDE( __tls_size = __tls_end - __tls_base );
+	PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) );
+	PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) );
+	PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) );
+
+	/*
+	 * The linker special cases .tbss segments which are
+	 * identified as segments which are not loaded and are
+	 * thread_local.
+	 *
+	 * For these segments, the linker does not advance 'dot'
+	 * across them.  We actually need memory allocated for tbss,
+	 * so we create a special segment here just to make room
+	 */
+	/*
+	.tbss_space (NOLOAD) : {
+		. = ADDR(.tbss);
+		. = . + SIZEOF(.tbss);
+	} >RAM0 AT>RAM0 :ram
+	*/
+
+	.bss (NOLOAD) : {
+		*(.sbss*)
+		*(.gnu.linkonce.sb.*)
+		*(.bss .bss.*)
+		*(.gnu.linkonce.b.*)
+		*(COMMON)
+
+		/* Align the heap */
+		. = ALIGN(8);
+		__bss_end = .;
+	} >RAM0 AT>RAM0 :ram
+	PROVIDE( __non_tls_bss_start = ADDR(.bss) );
+	PROVIDE( __end = __bss_end );
+	PROVIDE( _end = __bss_end );
+	PROVIDE( end = __bss_end );
+	PROVIDE( __bss_size = __bss_end - __bss_start );
+
+	/* Make the rest of memory available for heap storage */
+	PROVIDE (__heap_start = __end);
+#ifdef __HEAP_SIZE
+	PROVIDE (__heap_end = __heap_start + __HEAP_SIZE);
+	PROVIDE (__heap_size = __HEAP_SIZE);
+#else
+	PROVIDE (__heap_end = __stack - __STACK_SIZE);
+	PROVIDE (__heap_size = __heap_end - __heap_start);
+#endif
+	.heap (NOLOAD) : {
+		. += __heap_size;
+	} >RAM0 :ram
+
+	/* Define a stack region to make sure it fits in memory */
+	PROVIDE(__stack = ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE);
+	PROVIDE(__stack_limit = __stack - __STACK_SIZE);
+	.stack (__stack_limit) (NOLOAD) : {
+		. += __STACK_SIZE;
+	} >RAM0 :ram
+
+#if __STACKSEAL_SIZE > 0
+	PROVIDE(__stack_seal = __stack)
+  	.stackseal (__stack) (NOLOAD) :
+  	{
+    	. += __STACKSEAL_SIZE;
+  	} >RAM0 :ram
+#endif
+
+	/* Throw away C++ exception handling information */
+
+	/*
+
+	/DISCARD/ : {
+		*(.note .note.*)
+		*(.eh_frame .eh_frame.*)
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+		*(.ARM.exidx*)
+	}
+
+	*/
+
+	/* Stabs debugging sections.  */
+	.stab          0 : { *(.stab) }
+	.stabstr       0 : { *(.stabstr) }
+	.stab.excl     0 : { *(.stab.excl) }
+	.stab.exclstr  0 : { *(.stab.exclstr) }
+	.stab.index    0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment       0 : { *(.comment) }
+	.gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) }
+	/* DWARF debug sections.
+	   Symbols in the DWARF debugging sections are relative to the beginning
+	   of the section so we begin them at 0.  */
+	/* DWARF 1.  */
+	.debug          0 : { *(.debug) }
+	.line           0 : { *(.line) }
+	/* GNU DWARF 1 extensions.  */
+	.debug_srcinfo  0 : { *(.debug_srcinfo) }
+	.debug_sfnames  0 : { *(.debug_sfnames) }
+	/* DWARF 1.1 and DWARF 2.  */
+	.debug_aranges  0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	/* DWARF 2.  */
+	.debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+	.debug_abbrev   0 : { *(.debug_abbrev) }
+	.debug_line     0 : { *(.debug_line .debug_line.* .debug_line_end) }
+	.debug_frame    0 : { *(.debug_frame) }
+	.debug_str      0 : { *(.debug_str) }
+	.debug_loc      0 : { *(.debug_loc) }
+	.debug_macinfo  0 : { *(.debug_macinfo) }
+	/* SGI/MIPS DWARF 2 extensions.  */
+	.debug_weaknames 0 : { *(.debug_weaknames) }
+	.debug_funcnames 0 : { *(.debug_funcnames) }
+	.debug_typenames 0 : { *(.debug_typenames) }
+	.debug_varnames  0 : { *(.debug_varnames) }
+	/* DWARF 3.  */
+	.debug_pubtypes 0 : { *(.debug_pubtypes) }
+	.debug_ranges   0 : { *(.debug_ranges) }
+	/* DWARF 5.  */
+	.debug_addr     0 : { *(.debug_addr) }
+	.debug_line_str 0 : { *(.debug_line_str) }
+	.debug_loclists 0 : { *(.debug_loclists) }
+	.debug_macro    0 : { *(.debug_macro) }
+	.debug_names    0 : { *(.debug_names) }
+	.debug_rnglists 0 : { *(.debug_rnglists) }
+	.debug_str_offsets 0 : { *(.debug_str_offsets) }
+	.debug_sup      0 : { *(.debug_sup) }
+	.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
+}
+/*
+ * Check that sections that are copied from flash to RAM have matching
+ * padding, so that a single memcpy() of __data_size copies the correct bytes.
+ */
+ASSERT( __data_size == __data_source_size,
+	"ERROR: .data/.tdata flash size does not match RAM size");
diff --git a/Testing/cmsis_build/linker_scripts/clang_m4_mps3.ld b/Testing/cmsis_build/linker_scripts/clang_m4_mps3.ld
new file mode 100644
index 000000000..40f955c16
--- /dev/null
+++ b/Testing/cmsis_build/linker_scripts/clang_m4_mps3.ld
@@ -0,0 +1,353 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright © 2019 Keith Packard
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above
+ *    copyright notice, this list of conditions and the following
+ *    disclaimer in the documentation and/or other materials provided
+ *    with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* ----------------------------------------------------------------------------
+  Stack seal size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __STACKSEAL_SIZE   ( 8 )
+#else
+#define __STACKSEAL_SIZE   ( 0 )
+#endif
+
+/* ----------------------------------------------------------------------------
+  Memory definition
+ *----------------------------------------------------------------------------*/
+MEMORY
+{
+  ROM0  (rx!w)  : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE
+#if __ROM1_SIZE > 0
+  ROM1  (rx!w)  : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE
+#endif
+#if __ROM2_SIZE > 0
+  ROM2  (rx!w)  : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE
+#endif
+#if __ROM3_SIZE > 0
+  ROM3  (rx!w)  : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE
+#endif
+
+  RAM0  (w!rx) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE
+#if __RAM1_SIZE > 0
+  RAM1  (w!rx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE
+#endif
+#if __RAM2_SIZE > 0
+  RAM2  (w!rx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE
+#endif
+#if __RAM3_SIZE > 0
+  RAM3  (w!rx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE
+#endif
+}
+
+ENTRY(Reset_Handler)
+
+PHDRS
+{
+	text PT_LOAD;
+	ram PT_LOAD;
+	ram_init PT_LOAD;
+	tls PT_TLS;
+}
+
+SECTIONS
+{
+	.init : {
+		KEEP (*(.vectors))
+		KEEP (*(.text.init.enter))
+		KEEP (*(.data.init.enter))
+		KEEP (*(SORT_BY_NAME(.init) SORT_BY_NAME(.init.*)))
+	} >ROM0 AT>ROM0 :text
+
+	.text : {
+
+		/* code */
+		*(.text.unlikely .text.unlikely.*)
+		*(.text.startup .text.startup.*)
+		*(.text .text.* .opd .opd.*)
+		*(.gnu.linkonce.t.*)
+		KEEP (*(.fini .fini.*))
+		__text_end = .;
+
+		PROVIDE (__etext = __text_end);
+		PROVIDE (_etext = __text_end);
+		PROVIDE (etext = __text_end);
+
+		/* read-only data */
+		*(.rdata)
+		*(.rodata .rodata.*)
+		*(.gnu.linkonce.r.*)
+
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
+		*(.data.rel.ro .data.rel.ro.*)
+		*(.got .got.*)
+
+		/* Need to pre-align so that the symbols come after padding */
+		. = ALIGN(8);
+
+		/* lists of constructors and destructors */
+		PROVIDE_HIDDEN ( __preinit_array_start = . );
+		KEEP (*(.preinit_array))
+		PROVIDE_HIDDEN ( __preinit_array_end = . );
+
+		PROVIDE_HIDDEN ( __init_array_start = . );
+		KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+		KEEP (*(.init_array .ctors))
+		PROVIDE_HIDDEN ( __init_array_end = . );
+
+		PROVIDE_HIDDEN ( __fini_array_start = . );
+		KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+		KEEP (*(.fini_array .dtors))
+		PROVIDE_HIDDEN ( __fini_array_end = . );
+
+	} >ROM0 AT>ROM0 :text
+
+	.toc : {
+		*(.toc .toc.*)
+	} >ROM0 AT>ROM0 :text
+
+	/* additional sections when compiling with C++ exception support */
+	
+	.except_ordered : {
+		*(.gcc_except_table *.gcc_except_table.*)
+		KEEP (*(.eh_frame .eh_frame.*))
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} >ROM0 AT>ROM0 :text
+
+	.except_unordered : {
+		. = ALIGN(8);
+
+		PROVIDE(__exidx_start = .);
+		*(.ARM.exidx*)
+		PROVIDE(__exidx_end = .);
+	} >ROM0 AT>ROM0 :text
+	
+
+	/*
+	 * Data values which are preserved across reset
+	 */
+	.preserve (NOLOAD) : {
+		PROVIDE(__preserve_start__ = .);
+		KEEP(*(SORT_BY_NAME(.preserve.*)))
+		KEEP(*(.preserve))
+		PROVIDE(__preserve_end__ = .);
+	} >RAM0 AT>RAM0 :ram
+
+	.data :  {
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+
+		/* Need to pre-align so that the symbols come after padding */
+		. = ALIGN(8);
+
+		PROVIDE( __global_pointer$ = . + 0x800 );
+		*(.sdata .sdata.* .sdata2.*)
+		*(.gnu.linkonce.s.*)
+	} >RAM0 AT>ROM0 :ram_init
+	PROVIDE(__data_start = ADDR(.data));
+	PROVIDE(__data_source = LOADADDR(.data));
+
+	/* Thread local initialized data. This gets
+	 * space allocated as it is expected to be placed
+	 * in ram to be used as a template for TLS data blocks
+	 * allocated at runtime. We're slightly abusing that
+	 * by placing the data in flash where it will be copied
+	 * into the allocate ram addresses by the existing
+	 * data initialization code in crt0
+	 */
+	.tdata :  {
+		*(.tdata .tdata.* .gnu.linkonce.td.*)
+		PROVIDE(__data_end = .);
+		PROVIDE(__tdata_end = .);
+	} >RAM0 AT>ROM0 :tls :ram_init
+	PROVIDE( __tls_base = ADDR(.tdata));
+	PROVIDE( __tdata_start = ADDR(.tdata));
+	PROVIDE( __tdata_source = LOADADDR(.tdata) );
+	PROVIDE( __tdata_source_end = LOADADDR(.tdata) + SIZEOF(.tdata) );
+	PROVIDE( __data_source_end = __tdata_source_end );
+	PROVIDE( __tdata_size = SIZEOF(.tdata) );
+	PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) );
+
+	PROVIDE( __edata = __data_end );
+	PROVIDE( _edata = __data_end );
+	PROVIDE( edata = __data_end );
+	PROVIDE( __data_size = __data_end - __data_start );
+	PROVIDE( __data_source_size = __data_source_end - __data_source );
+
+	.tbss (NOLOAD) : {
+		*(.tbss .tbss.* .gnu.linkonce.tb.*)
+		*(.tcommon)
+		PROVIDE( __tls_end = . );
+		PROVIDE( __tbss_end = . );
+	} >RAM0 AT>RAM0 :tls :ram
+	PROVIDE( __bss_start = ADDR(.tbss));
+	PROVIDE( __tbss_start = ADDR(.tbss));
+	PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) );
+	PROVIDE( __tbss_size = SIZEOF(.tbss) );
+	PROVIDE( __tls_size = __tls_end - __tls_base );
+	PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) );
+	PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) );
+	PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) );
+
+	/*
+	 * The linker special cases .tbss segments which are
+	 * identified as segments which are not loaded and are
+	 * thread_local.
+	 *
+	 * For these segments, the linker does not advance 'dot'
+	 * across them.  We actually need memory allocated for tbss,
+	 * so we create a special segment here just to make room
+	 */
+	/*
+	.tbss_space (NOLOAD) : {
+		. = ADDR(.tbss);
+		. = . + SIZEOF(.tbss);
+	} >RAM0 AT>RAM0 :ram
+	*/
+
+	.bss (NOLOAD) : {
+		*(.sbss*)
+		*(.gnu.linkonce.sb.*)
+		*(.bss .bss.*)
+		*(.gnu.linkonce.b.*)
+		*(COMMON)
+
+		/* Align the heap */
+		. = ALIGN(8);
+		__bss_end = .;
+	} >RAM0 AT>RAM0 :ram
+	PROVIDE( __non_tls_bss_start = ADDR(.bss) );
+	PROVIDE( __end = __bss_end );
+	PROVIDE( _end = __bss_end );
+	PROVIDE( end = __bss_end );
+	PROVIDE( __bss_size = __bss_end - __bss_start );
+
+	/* Make the rest of memory available for heap storage */
+	PROVIDE (__heap_start = __end);
+#ifdef __HEAP_SIZE
+	PROVIDE (__heap_end = __heap_start + __HEAP_SIZE);
+	PROVIDE (__heap_size = __HEAP_SIZE);
+#else
+	PROVIDE (__heap_end = __stack - __STACK_SIZE);
+	PROVIDE (__heap_size = __heap_end - __heap_start);
+#endif
+	.heap (NOLOAD) : {
+		. += __heap_size;
+	} >RAM0 :ram
+
+	/* Define a stack region to make sure it fits in memory */
+	PROVIDE(__stack = ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE);
+	PROVIDE(__stack_limit = __stack - __STACK_SIZE);
+	.stack (__stack_limit) (NOLOAD) : {
+		. += __STACK_SIZE;
+	} >RAM0 :ram
+
+#if __STACKSEAL_SIZE > 0
+	PROVIDE(__stack_seal = __stack)
+  	.stackseal (__stack) (NOLOAD) :
+  	{
+    	. += __STACKSEAL_SIZE;
+  	} >RAM0 :ram
+#endif
+
+	/* Throw away C++ exception handling information */
+
+	/*
+
+	/DISCARD/ : {
+		*(.note .note.*)
+		*(.eh_frame .eh_frame.*)
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+		*(.ARM.exidx*)
+	}
+
+	*/
+
+	/* Stabs debugging sections.  */
+	.stab          0 : { *(.stab) }
+	.stabstr       0 : { *(.stabstr) }
+	.stab.excl     0 : { *(.stab.excl) }
+	.stab.exclstr  0 : { *(.stab.exclstr) }
+	.stab.index    0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment       0 : { *(.comment) }
+	.gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) }
+	/* DWARF debug sections.
+	   Symbols in the DWARF debugging sections are relative to the beginning
+	   of the section so we begin them at 0.  */
+	/* DWARF 1.  */
+	.debug          0 : { *(.debug) }
+	.line           0 : { *(.line) }
+	/* GNU DWARF 1 extensions.  */
+	.debug_srcinfo  0 : { *(.debug_srcinfo) }
+	.debug_sfnames  0 : { *(.debug_sfnames) }
+	/* DWARF 1.1 and DWARF 2.  */
+	.debug_aranges  0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	/* DWARF 2.  */
+	.debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+	.debug_abbrev   0 : { *(.debug_abbrev) }
+	.debug_line     0 : { *(.debug_line .debug_line.* .debug_line_end) }
+	.debug_frame    0 : { *(.debug_frame) }
+	.debug_str      0 : { *(.debug_str) }
+	.debug_loc      0 : { *(.debug_loc) }
+	.debug_macinfo  0 : { *(.debug_macinfo) }
+	/* SGI/MIPS DWARF 2 extensions.  */
+	.debug_weaknames 0 : { *(.debug_weaknames) }
+	.debug_funcnames 0 : { *(.debug_funcnames) }
+	.debug_typenames 0 : { *(.debug_typenames) }
+	.debug_varnames  0 : { *(.debug_varnames) }
+	/* DWARF 3.  */
+	.debug_pubtypes 0 : { *(.debug_pubtypes) }
+	.debug_ranges   0 : { *(.debug_ranges) }
+	/* DWARF 5.  */
+	.debug_addr     0 : { *(.debug_addr) }
+	.debug_line_str 0 : { *(.debug_line_str) }
+	.debug_loclists 0 : { *(.debug_loclists) }
+	.debug_macro    0 : { *(.debug_macro) }
+	.debug_names    0 : { *(.debug_names) }
+	.debug_rnglists 0 : { *(.debug_rnglists) }
+	.debug_str_offsets 0 : { *(.debug_str_offsets) }
+	.debug_sup      0 : { *(.debug_sup) }
+	.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
+}
+/*
+ * Check that sections that are copied from flash to RAM have matching
+ * padding, so that a single memcpy() of __data_size copies the correct bytes.
+ */
+ASSERT( __data_size == __data_source_size,
+	"ERROR: .data/.tdata flash size does not match RAM size");
diff --git a/Testing/cmsis_build/linker_scripts/clang_m7_mps3.ld b/Testing/cmsis_build/linker_scripts/clang_m7_mps3.ld
new file mode 100644
index 000000000..40f955c16
--- /dev/null
+++ b/Testing/cmsis_build/linker_scripts/clang_m7_mps3.ld
@@ -0,0 +1,353 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright © 2019 Keith Packard
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above
+ *    copyright notice, this list of conditions and the following
+ *    disclaimer in the documentation and/or other materials provided
+ *    with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* ----------------------------------------------------------------------------
+  Stack seal size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __STACKSEAL_SIZE   ( 8 )
+#else
+#define __STACKSEAL_SIZE   ( 0 )
+#endif
+
+/* ----------------------------------------------------------------------------
+  Memory definition
+ *----------------------------------------------------------------------------*/
+MEMORY
+{
+  ROM0  (rx!w)  : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE
+#if __ROM1_SIZE > 0
+  ROM1  (rx!w)  : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE
+#endif
+#if __ROM2_SIZE > 0
+  ROM2  (rx!w)  : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE
+#endif
+#if __ROM3_SIZE > 0
+  ROM3  (rx!w)  : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE
+#endif
+
+  RAM0  (w!rx) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE
+#if __RAM1_SIZE > 0
+  RAM1  (w!rx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE
+#endif
+#if __RAM2_SIZE > 0
+  RAM2  (w!rx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE
+#endif
+#if __RAM3_SIZE > 0
+  RAM3  (w!rx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE
+#endif
+}
+
+ENTRY(Reset_Handler)
+
+PHDRS
+{
+	text PT_LOAD;
+	ram PT_LOAD;
+	ram_init PT_LOAD;
+	tls PT_TLS;
+}
+
+SECTIONS
+{
+	.init : {
+		KEEP (*(.vectors))
+		KEEP (*(.text.init.enter))
+		KEEP (*(.data.init.enter))
+		KEEP (*(SORT_BY_NAME(.init) SORT_BY_NAME(.init.*)))
+	} >ROM0 AT>ROM0 :text
+
+	.text : {
+
+		/* code */
+		*(.text.unlikely .text.unlikely.*)
+		*(.text.startup .text.startup.*)
+		*(.text .text.* .opd .opd.*)
+		*(.gnu.linkonce.t.*)
+		KEEP (*(.fini .fini.*))
+		__text_end = .;
+
+		PROVIDE (__etext = __text_end);
+		PROVIDE (_etext = __text_end);
+		PROVIDE (etext = __text_end);
+
+		/* read-only data */
+		*(.rdata)
+		*(.rodata .rodata.*)
+		*(.gnu.linkonce.r.*)
+
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
+		*(.data.rel.ro .data.rel.ro.*)
+		*(.got .got.*)
+
+		/* Need to pre-align so that the symbols come after padding */
+		. = ALIGN(8);
+
+		/* lists of constructors and destructors */
+		PROVIDE_HIDDEN ( __preinit_array_start = . );
+		KEEP (*(.preinit_array))
+		PROVIDE_HIDDEN ( __preinit_array_end = . );
+
+		PROVIDE_HIDDEN ( __init_array_start = . );
+		KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+		KEEP (*(.init_array .ctors))
+		PROVIDE_HIDDEN ( __init_array_end = . );
+
+		PROVIDE_HIDDEN ( __fini_array_start = . );
+		KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+		KEEP (*(.fini_array .dtors))
+		PROVIDE_HIDDEN ( __fini_array_end = . );
+
+	} >ROM0 AT>ROM0 :text
+
+	.toc : {
+		*(.toc .toc.*)
+	} >ROM0 AT>ROM0 :text
+
+	/* additional sections when compiling with C++ exception support */
+	
+	.except_ordered : {
+		*(.gcc_except_table *.gcc_except_table.*)
+		KEEP (*(.eh_frame .eh_frame.*))
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} >ROM0 AT>ROM0 :text
+
+	.except_unordered : {
+		. = ALIGN(8);
+
+		PROVIDE(__exidx_start = .);
+		*(.ARM.exidx*)
+		PROVIDE(__exidx_end = .);
+	} >ROM0 AT>ROM0 :text
+	
+
+	/*
+	 * Data values which are preserved across reset
+	 */
+	.preserve (NOLOAD) : {
+		PROVIDE(__preserve_start__ = .);
+		KEEP(*(SORT_BY_NAME(.preserve.*)))
+		KEEP(*(.preserve))
+		PROVIDE(__preserve_end__ = .);
+	} >RAM0 AT>RAM0 :ram
+
+	.data :  {
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+
+		/* Need to pre-align so that the symbols come after padding */
+		. = ALIGN(8);
+
+		PROVIDE( __global_pointer$ = . + 0x800 );
+		*(.sdata .sdata.* .sdata2.*)
+		*(.gnu.linkonce.s.*)
+	} >RAM0 AT>ROM0 :ram_init
+	PROVIDE(__data_start = ADDR(.data));
+	PROVIDE(__data_source = LOADADDR(.data));
+
+	/* Thread local initialized data. This gets
+	 * space allocated as it is expected to be placed
+	 * in ram to be used as a template for TLS data blocks
+	 * allocated at runtime. We're slightly abusing that
+	 * by placing the data in flash where it will be copied
+	 * into the allocate ram addresses by the existing
+	 * data initialization code in crt0
+	 */
+	.tdata :  {
+		*(.tdata .tdata.* .gnu.linkonce.td.*)
+		PROVIDE(__data_end = .);
+		PROVIDE(__tdata_end = .);
+	} >RAM0 AT>ROM0 :tls :ram_init
+	PROVIDE( __tls_base = ADDR(.tdata));
+	PROVIDE( __tdata_start = ADDR(.tdata));
+	PROVIDE( __tdata_source = LOADADDR(.tdata) );
+	PROVIDE( __tdata_source_end = LOADADDR(.tdata) + SIZEOF(.tdata) );
+	PROVIDE( __data_source_end = __tdata_source_end );
+	PROVIDE( __tdata_size = SIZEOF(.tdata) );
+	PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) );
+
+	PROVIDE( __edata = __data_end );
+	PROVIDE( _edata = __data_end );
+	PROVIDE( edata = __data_end );
+	PROVIDE( __data_size = __data_end - __data_start );
+	PROVIDE( __data_source_size = __data_source_end - __data_source );
+
+	.tbss (NOLOAD) : {
+		*(.tbss .tbss.* .gnu.linkonce.tb.*)
+		*(.tcommon)
+		PROVIDE( __tls_end = . );
+		PROVIDE( __tbss_end = . );
+	} >RAM0 AT>RAM0 :tls :ram
+	PROVIDE( __bss_start = ADDR(.tbss));
+	PROVIDE( __tbss_start = ADDR(.tbss));
+	PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) );
+	PROVIDE( __tbss_size = SIZEOF(.tbss) );
+	PROVIDE( __tls_size = __tls_end - __tls_base );
+	PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) );
+	PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) );
+	PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) );
+
+	/*
+	 * The linker special cases .tbss segments which are
+	 * identified as segments which are not loaded and are
+	 * thread_local.
+	 *
+	 * For these segments, the linker does not advance 'dot'
+	 * across them.  We actually need memory allocated for tbss,
+	 * so we create a special segment here just to make room
+	 */
+	/*
+	.tbss_space (NOLOAD) : {
+		. = ADDR(.tbss);
+		. = . + SIZEOF(.tbss);
+	} >RAM0 AT>RAM0 :ram
+	*/
+
+	.bss (NOLOAD) : {
+		*(.sbss*)
+		*(.gnu.linkonce.sb.*)
+		*(.bss .bss.*)
+		*(.gnu.linkonce.b.*)
+		*(COMMON)
+
+		/* Align the heap */
+		. = ALIGN(8);
+		__bss_end = .;
+	} >RAM0 AT>RAM0 :ram
+	PROVIDE( __non_tls_bss_start = ADDR(.bss) );
+	PROVIDE( __end = __bss_end );
+	PROVIDE( _end = __bss_end );
+	PROVIDE( end = __bss_end );
+	PROVIDE( __bss_size = __bss_end - __bss_start );
+
+	/* Make the rest of memory available for heap storage */
+	PROVIDE (__heap_start = __end);
+#ifdef __HEAP_SIZE
+	PROVIDE (__heap_end = __heap_start + __HEAP_SIZE);
+	PROVIDE (__heap_size = __HEAP_SIZE);
+#else
+	PROVIDE (__heap_end = __stack - __STACK_SIZE);
+	PROVIDE (__heap_size = __heap_end - __heap_start);
+#endif
+	.heap (NOLOAD) : {
+		. += __heap_size;
+	} >RAM0 :ram
+
+	/* Define a stack region to make sure it fits in memory */
+	PROVIDE(__stack = ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE);
+	PROVIDE(__stack_limit = __stack - __STACK_SIZE);
+	.stack (__stack_limit) (NOLOAD) : {
+		. += __STACK_SIZE;
+	} >RAM0 :ram
+
+#if __STACKSEAL_SIZE > 0
+	PROVIDE(__stack_seal = __stack)
+  	.stackseal (__stack) (NOLOAD) :
+  	{
+    	. += __STACKSEAL_SIZE;
+  	} >RAM0 :ram
+#endif
+
+	/* Throw away C++ exception handling information */
+
+	/*
+
+	/DISCARD/ : {
+		*(.note .note.*)
+		*(.eh_frame .eh_frame.*)
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+		*(.ARM.exidx*)
+	}
+
+	*/
+
+	/* Stabs debugging sections.  */
+	.stab          0 : { *(.stab) }
+	.stabstr       0 : { *(.stabstr) }
+	.stab.excl     0 : { *(.stab.excl) }
+	.stab.exclstr  0 : { *(.stab.exclstr) }
+	.stab.index    0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment       0 : { *(.comment) }
+	.gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) }
+	/* DWARF debug sections.
+	   Symbols in the DWARF debugging sections are relative to the beginning
+	   of the section so we begin them at 0.  */
+	/* DWARF 1.  */
+	.debug          0 : { *(.debug) }
+	.line           0 : { *(.line) }
+	/* GNU DWARF 1 extensions.  */
+	.debug_srcinfo  0 : { *(.debug_srcinfo) }
+	.debug_sfnames  0 : { *(.debug_sfnames) }
+	/* DWARF 1.1 and DWARF 2.  */
+	.debug_aranges  0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	/* DWARF 2.  */
+	.debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+	.debug_abbrev   0 : { *(.debug_abbrev) }
+	.debug_line     0 : { *(.debug_line .debug_line.* .debug_line_end) }
+	.debug_frame    0 : { *(.debug_frame) }
+	.debug_str      0 : { *(.debug_str) }
+	.debug_loc      0 : { *(.debug_loc) }
+	.debug_macinfo  0 : { *(.debug_macinfo) }
+	/* SGI/MIPS DWARF 2 extensions.  */
+	.debug_weaknames 0 : { *(.debug_weaknames) }
+	.debug_funcnames 0 : { *(.debug_funcnames) }
+	.debug_typenames 0 : { *(.debug_typenames) }
+	.debug_varnames  0 : { *(.debug_varnames) }
+	/* DWARF 3.  */
+	.debug_pubtypes 0 : { *(.debug_pubtypes) }
+	.debug_ranges   0 : { *(.debug_ranges) }
+	/* DWARF 5.  */
+	.debug_addr     0 : { *(.debug_addr) }
+	.debug_line_str 0 : { *(.debug_line_str) }
+	.debug_loclists 0 : { *(.debug_loclists) }
+	.debug_macro    0 : { *(.debug_macro) }
+	.debug_names    0 : { *(.debug_names) }
+	.debug_rnglists 0 : { *(.debug_rnglists) }
+	.debug_str_offsets 0 : { *(.debug_str_offsets) }
+	.debug_sup      0 : { *(.debug_sup) }
+	.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
+}
+/*
+ * Check that sections that are copied from flash to RAM have matching
+ * padding, so that a single memcpy() of __data_size copies the correct bytes.
+ */
+ASSERT( __data_size == __data_source_size,
+	"ERROR: .data/.tdata flash size does not match RAM size");
diff --git a/Testing/cmsis_build/linker_scripts/clang_sse300_mps3.sct b/Testing/cmsis_build/linker_scripts/clang_sse300_mps3.sct
new file mode 100644
index 000000000..9c10fb1e4
--- /dev/null
+++ b/Testing/cmsis_build/linker_scripts/clang_sse300_mps3.sct
@@ -0,0 +1,364 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright © 2019 Keith Packard
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above
+ *    copyright notice, this list of conditions and the following
+ *    disclaimer in the documentation and/or other materials provided
+ *    with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* ----------------------------------------------------------------------------
+  Stack seal size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __STACKSEAL_SIZE   ( 8 )
+#else
+#define __STACKSEAL_SIZE   ( 0 )
+#endif
+
+/* ----------------------------------------------------------------------------
+  Memory definition
+ *----------------------------------------------------------------------------*/
+MEMORY
+{
+  ROM0  (rx!w)  : ORIGIN = S_CODE_START, LENGTH = S_CODE_SIZE + 0x000000
+#if __ROM1_SIZE > 0
+  ROM1  (rx!w)  : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE
+#endif
+#if __ROM2_SIZE > 0
+  ROM2  (rx!w)  : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE
+#endif
+#if __ROM3_SIZE > 0
+  ROM3  (rx!w)  : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE
+#endif
+
+  RAM0  (w!rx) : ORIGIN = S_DDR4_START, LENGTH = S_DDR4_SIZE + 0x000000
+#if __RAM1_SIZE > 0
+  RAM1  (rw) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE + 0x000000
+#endif
+#if __RAM2_SIZE > 0
+  RAM2  (w!rx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE
+#endif
+#if __RAM3_SIZE > 0
+  RAM3  (w!rx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE
+#endif
+}
+
+ENTRY(Reset_Handler)
+
+PHDRS
+{
+	text PT_LOAD;
+	ram PT_LOAD;
+	ram_init PT_LOAD;
+	tls PT_TLS;
+}
+
+SECTIONS
+{
+	.init : {
+		KEEP (*(.vectors))
+		KEEP (*(.text.init.enter))
+		KEEP (*(.data.init.enter))
+		KEEP (*(SORT_BY_NAME(.init) SORT_BY_NAME(.init.*)))
+	} >RAM0 AT>RAM0 :text
+
+	.text : {
+
+		/* code */
+		*(.text.unlikely .text.unlikely.*)
+		*(.text.startup .text.startup.*)
+		*(.text .text.* .opd .opd.*)
+		*(.gnu.linkonce.t.*)
+		KEEP (*(.fini .fini.*))
+		__text_end = .;
+
+		PROVIDE (__etext = __text_end);
+		PROVIDE (_etext = __text_end);
+		PROVIDE (etext = __text_end);
+
+		*(.gnu.linkonce.r.*)
+
+
+
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
+		*(.data.rel.ro .data.rel.ro.*)
+		*(.got .got.*)
+
+		/* Need to pre-align so that the symbols come after padding */
+		. = ALIGN(8);
+
+		/* lists of constructors and destructors */
+		PROVIDE_HIDDEN ( __preinit_array_start = . );
+		KEEP (*(.preinit_array))
+		PROVIDE_HIDDEN ( __preinit_array_end = . );
+
+		PROVIDE_HIDDEN ( __init_array_start = . );
+		KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+		KEEP (*(.init_array .ctors))
+		PROVIDE_HIDDEN ( __init_array_end = . );
+
+		PROVIDE_HIDDEN ( __fini_array_start = . );
+		KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+		KEEP (*(.fini_array .dtors))
+		PROVIDE_HIDDEN ( __fini_array_end = . );
+
+	} >RAM0 AT>RAM0 :text
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+	.veneers :
+	{
+		. = ALIGN(32);
+		KEEP(*(.gnu.sgstubs))
+	} > RAM0 AT>RAM0 :text
+#endif
+
+	.toc : {
+		*(.toc .toc.*)
+	} >RAM0 AT>RAM0 :text
+
+	/* additional sections when compiling with C++ exception support */
+
+	.except_ordered : {
+		*(.gcc_except_table *.gcc_except_table.*)
+		KEEP (*(.eh_frame .eh_frame.*))
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} >RAM0 AT>RAM0 :text
+
+	.except_unordered : {
+		. = ALIGN(8);
+
+		PROVIDE(__exidx_start = .);
+		*(.ARM.exidx*)
+		PROVIDE(__exidx_end = .);
+	} >RAM0 AT>RAM0 :text
+
+
+	/*
+	 * Data values which are preserved across reset
+	 */
+	.preserve (NOLOAD) : {
+		PROVIDE(__preserve_start__ = .);
+		KEEP(*(SORT_BY_NAME(.preserve.*)))
+		KEEP(*(.preserve))
+		PROVIDE(__preserve_end__ = .);
+	} >RAM0 AT>RAM0 :ram
+
+	.data :  {
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+
+		/* read-only data */
+		*(.rdata)
+		*(.rodata .rodata.*)
+
+		/* Need to pre-align so that the symbols come after padding */
+		. = ALIGN(8);
+
+		PROVIDE( __global_pointer$ = . + 0x800 );
+		*(.sdata .sdata.* .sdata2.*)
+		*(.gnu.linkonce.s.*)
+	} >RAM0 AT>RAM0 :ram_init
+	PROVIDE(__data_start = ADDR(.data));
+	PROVIDE(__data_source = LOADADDR(.data));
+
+	/* Thread local initialized data. This gets
+	 * space allocated as it is expected to be placed
+	 * in ram to be used as a template for TLS data blocks
+	 * allocated at runtime. We're slightly abusing that
+	 * by placing the data in flash where it will be copied
+	 * into the allocate ram addresses by the existing
+	 * data initialization code in crt0
+	 */
+	.tdata :  {
+		*(.tdata .tdata.* .gnu.linkonce.td.*)
+		PROVIDE(__data_end = .);
+		PROVIDE(__tdata_end = .);
+	} >RAM0 AT>RAM0 :tls :ram_init
+	PROVIDE( __tls_base = ADDR(.tdata));
+	PROVIDE( __tdata_start = ADDR(.tdata));
+	PROVIDE( __tdata_source = LOADADDR(.tdata) );
+	PROVIDE( __tdata_source_end = LOADADDR(.tdata) + SIZEOF(.tdata) );
+	PROVIDE( __data_source_end = __tdata_source_end );
+	PROVIDE( __tdata_size = SIZEOF(.tdata) );
+	PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) );
+
+	PROVIDE( __edata = __data_end );
+	PROVIDE( _edata = __data_end );
+	PROVIDE( edata = __data_end );
+	PROVIDE( __data_size = __data_end - __data_start );
+	PROVIDE( __data_source_size = __data_source_end - __data_source );
+
+	.tbss (NOLOAD) : {
+		*(.tbss .tbss.* .gnu.linkonce.tb.*)
+		*(.tcommon)
+		PROVIDE( __tls_end = . );
+		PROVIDE( __tbss_end = . );
+	} >RAM0 AT>RAM0 :tls :ram
+	PROVIDE( __bss_start = ADDR(.tbss));
+	PROVIDE( __tbss_start = ADDR(.tbss));
+	PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) );
+	PROVIDE( __tbss_size = SIZEOF(.tbss) );
+	PROVIDE( __tls_size = __tls_end - __tls_base );
+	PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) );
+	PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) );
+	PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) );
+
+	/*
+	 * The linker special cases .tbss segments which are
+	 * identified as segments which are not loaded and are
+	 * thread_local.
+	 *
+	 * For these segments, the linker does not advance 'dot'
+	 * across them.  We actually need memory allocated for tbss,
+	 * so we create a special segment here just to make room
+	 */
+	/*
+	.tbss_space (NOLOAD) : {
+		. = ADDR(.tbss);
+		. = . + SIZEOF(.tbss);
+	} >RAM0 AT>RAM0 :ram
+	*/
+
+	.bss (NOLOAD) : {
+		*(.sbss*)
+		*(.gnu.linkonce.sb.*)
+		*(.bss .bss.*)
+		*(.gnu.linkonce.b.*)
+		*(COMMON)
+
+		/* Align the heap */
+		. = ALIGN(8);
+		__bss_end = .;
+	} >RAM0 AT>RAM0 :ram
+	PROVIDE( __non_tls_bss_start = ADDR(.bss) );
+	PROVIDE( __end = __bss_end );
+	PROVIDE( _end = __bss_end );
+	PROVIDE( end = __bss_end );
+	PROVIDE( __bss_size = __bss_end - __bss_start );
+
+	/* Make the rest of memory available for heap storage */
+	PROVIDE (__heap_start = __end);
+#ifdef HEAP_SIZE
+	PROVIDE (__heap_end = __heap_start + HEAP_SIZE);
+	PROVIDE (__heap_size = HEAP_SIZE);
+#else
+	PROVIDE (__heap_end = __stack - STACK_SIZE);
+	PROVIDE (__heap_size = __heap_end - __heap_start);
+#endif
+	.heap (NOLOAD) : {
+		. += __heap_size;
+	} >RAM0 :ram
+
+	/* Define a stack region to make sure it fits in memory */
+	PROVIDE(__stack = ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE);
+	PROVIDE(__stack_limit = __stack - STACK_SIZE);
+	.stack (__stack_limit) (NOLOAD) : {
+		. += STACK_SIZE;
+	} >RAM0 :ram
+
+#if __STACKSEAL_SIZE > 0
+	PROVIDE(__stack_seal = __stack);
+  	.stackseal (__stack) (NOLOAD) :
+  	{
+    	. += __STACKSEAL_SIZE;
+  	} >RAM0 :ram
+#endif
+
+	/* Throw away C++ exception handling information */
+
+	/*
+
+	/DISCARD/ : {
+		*(.note .note.*)
+		*(.eh_frame .eh_frame.*)
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+		*(.ARM.exidx*)
+	}
+
+	*/
+
+	/* Stabs debugging sections.  */
+	.stab          0 : { *(.stab) }
+	.stabstr       0 : { *(.stabstr) }
+	.stab.excl     0 : { *(.stab.excl) }
+	.stab.exclstr  0 : { *(.stab.exclstr) }
+	.stab.index    0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment       0 : { *(.comment) }
+	.gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) }
+	/* DWARF debug sections.
+	   Symbols in the DWARF debugging sections are relative to the beginning
+	   of the section so we begin them at 0.  */
+	/* DWARF 1.  */
+	.debug          0 : { *(.debug) }
+	.line           0 : { *(.line) }
+	/* GNU DWARF 1 extensions.  */
+	.debug_srcinfo  0 : { *(.debug_srcinfo) }
+	.debug_sfnames  0 : { *(.debug_sfnames) }
+	/* DWARF 1.1 and DWARF 2.  */
+	.debug_aranges  0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	/* DWARF 2.  */
+	.debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+	.debug_abbrev   0 : { *(.debug_abbrev) }
+	.debug_line     0 : { *(.debug_line .debug_line.* .debug_line_end) }
+	.debug_frame    0 : { *(.debug_frame) }
+	.debug_str      0 : { *(.debug_str) }
+	.debug_loc      0 : { *(.debug_loc) }
+	.debug_macinfo  0 : { *(.debug_macinfo) }
+	/* SGI/MIPS DWARF 2 extensions.  */
+	.debug_weaknames 0 : { *(.debug_weaknames) }
+	.debug_funcnames 0 : { *(.debug_funcnames) }
+	.debug_typenames 0 : { *(.debug_typenames) }
+	.debug_varnames  0 : { *(.debug_varnames) }
+	/* DWARF 3.  */
+	.debug_pubtypes 0 : { *(.debug_pubtypes) }
+	.debug_ranges   0 : { *(.debug_ranges) }
+	/* DWARF 5.  */
+	.debug_addr     0 : { *(.debug_addr) }
+	.debug_line_str 0 : { *(.debug_line_str) }
+	.debug_loclists 0 : { *(.debug_loclists) }
+	.debug_macro    0 : { *(.debug_macro) }
+	.debug_names    0 : { *(.debug_names) }
+	.debug_rnglists 0 : { *(.debug_rnglists) }
+	.debug_str_offsets 0 : { *(.debug_str_offsets) }
+	.debug_sup      0 : { *(.debug_sup) }
+	.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
+}
+/*
+ * Check that sections that are copied from flash to RAM have matching
+ * padding, so that a single memcpy() of __data_size copies the correct bytes.
+ */
+ASSERT( __data_size == __data_source_size,
+	"ERROR: .data/.tdata flash size does not match RAM size");
diff --git a/Testing/cmsis_build/linker_scripts/clang_sse310_mps3.sct b/Testing/cmsis_build/linker_scripts/clang_sse310_mps3.sct
new file mode 100644
index 000000000..3f4877162
--- /dev/null
+++ b/Testing/cmsis_build/linker_scripts/clang_sse310_mps3.sct
@@ -0,0 +1,363 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright © 2019 Keith Packard
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above
+ *    copyright notice, this list of conditions and the following
+ *    disclaimer in the documentation and/or other materials provided
+ *    with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* ----------------------------------------------------------------------------
+  Stack seal size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __STACKSEAL_SIZE   ( 8 )
+#else
+#define __STACKSEAL_SIZE   ( 0 )
+#endif
+
+/* ----------------------------------------------------------------------------
+  Memory definition
+ *----------------------------------------------------------------------------*/
+MEMORY
+{
+  ROM0  (rx!w)  : ORIGIN = S_CODE_START, LENGTH = S_CODE_SIZE + 0x000000
+#if __ROM1_SIZE > 0
+  ROM1  (rx!w)  : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE
+#endif
+#if __ROM2_SIZE > 0
+  ROM2  (rx!w)  : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE
+#endif
+#if __ROM3_SIZE > 0
+  ROM3  (rx!w)  : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE
+#endif
+
+  RAM0  (w!rx) : ORIGIN = S_DATA_START, LENGTH = S_DATA_SIZE + 0x000000
+#if __RAM1_SIZE > 0
+  RAM1  (w!rx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE
+#endif
+#if __RAM2_SIZE > 0
+  RAM2  (w!rx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE
+#endif
+#if __RAM3_SIZE > 0
+  RAM3  (w!rx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE
+#endif
+}
+
+ENTRY(Reset_Handler)
+
+PHDRS
+{
+	text PT_LOAD;
+	ram PT_LOAD;
+	ram_init PT_LOAD;
+	tls PT_TLS;
+}
+
+SECTIONS
+{
+	.init : {
+		KEEP (*(.vectors))
+		KEEP (*(.text.init.enter))
+		KEEP (*(.data.init.enter))
+		KEEP (*(SORT_BY_NAME(.init) SORT_BY_NAME(.init.*)))
+	} >ROM0 AT>ROM0 :text
+
+	.text : {
+
+		/* code */
+		*(.text.unlikely .text.unlikely.*)
+		*(.text.startup .text.startup.*)
+		*(.text .text.* .opd .opd.*)
+		*(.gnu.linkonce.t.*)
+		KEEP (*(.fini .fini.*))
+		__text_end = .;
+
+		PROVIDE (__etext = __text_end);
+		PROVIDE (_etext = __text_end);
+		PROVIDE (etext = __text_end);
+
+		*(.gnu.linkonce.r.*)
+
+
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
+		*(.data.rel.ro .data.rel.ro.*)
+		*(.got .got.*)
+
+		/* Need to pre-align so that the symbols come after padding */
+		. = ALIGN(8);
+
+		/* lists of constructors and destructors */
+		PROVIDE_HIDDEN ( __preinit_array_start = . );
+		KEEP (*(.preinit_array))
+		PROVIDE_HIDDEN ( __preinit_array_end = . );
+
+		PROVIDE_HIDDEN ( __init_array_start = . );
+		KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+		KEEP (*(.init_array .ctors))
+		PROVIDE_HIDDEN ( __init_array_end = . );
+
+		PROVIDE_HIDDEN ( __fini_array_start = . );
+		KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+		KEEP (*(.fini_array .dtors))
+		PROVIDE_HIDDEN ( __fini_array_end = . );
+
+	} >ROM0 AT>ROM0 :text
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+	.veneers :
+	{
+		. = ALIGN(32);
+		KEEP(*(.gnu.sgstubs))
+	} > ROM0 AT>ROM0 :text
+#endif
+
+	.toc : {
+		*(.toc .toc.*)
+	} >ROM0 AT>ROM0 :text
+
+	/* additional sections when compiling with C++ exception support */
+
+	.except_ordered : {
+		*(.gcc_except_table *.gcc_except_table.*)
+		KEEP (*(.eh_frame .eh_frame.*))
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} >ROM0 AT>ROM0 :text
+
+	.except_unordered : {
+		. = ALIGN(8);
+
+		PROVIDE(__exidx_start = .);
+		*(.ARM.exidx*)
+		PROVIDE(__exidx_end = .);
+	} >ROM0 AT>ROM0 :text
+
+
+	/*
+	 * Data values which are preserved across reset
+	 */
+	.preserve (NOLOAD) : {
+		PROVIDE(__preserve_start__ = .);
+		KEEP(*(SORT_BY_NAME(.preserve.*)))
+		KEEP(*(.preserve))
+		PROVIDE(__preserve_end__ = .);
+	} >RAM0 AT>RAM0 :ram
+
+	.data :  {
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+
+		/* read-only data */
+		*(.rdata)
+		*(.rodata .rodata.*)
+
+		/* Need to pre-align so that the symbols come after padding */
+		. = ALIGN(8);
+
+		PROVIDE( __global_pointer$ = . + 0x800 );
+		*(.sdata .sdata.* .sdata2.*)
+		*(.gnu.linkonce.s.*)
+	} >RAM0 AT>ROM0 :ram_init
+	PROVIDE(__data_start = ADDR(.data));
+	PROVIDE(__data_source = LOADADDR(.data));
+
+	/* Thread local initialized data. This gets
+	 * space allocated as it is expected to be placed
+	 * in ram to be used as a template for TLS data blocks
+	 * allocated at runtime. We're slightly abusing that
+	 * by placing the data in flash where it will be copied
+	 * into the allocate ram addresses by the existing
+	 * data initialization code in crt0
+	 */
+	.tdata :  {
+		*(.tdata .tdata.* .gnu.linkonce.td.*)
+		PROVIDE(__data_end = .);
+		PROVIDE(__tdata_end = .);
+	} >RAM0 AT>ROM0 :tls :ram_init
+	PROVIDE( __tls_base = ADDR(.tdata));
+	PROVIDE( __tdata_start = ADDR(.tdata));
+	PROVIDE( __tdata_source = LOADADDR(.tdata) );
+	PROVIDE( __tdata_source_end = LOADADDR(.tdata) + SIZEOF(.tdata) );
+	PROVIDE( __data_source_end = __tdata_source_end );
+	PROVIDE( __tdata_size = SIZEOF(.tdata) );
+	PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) );
+
+	PROVIDE( __edata = __data_end );
+	PROVIDE( _edata = __data_end );
+	PROVIDE( edata = __data_end );
+	PROVIDE( __data_size = __data_end - __data_start );
+	PROVIDE( __data_source_size = __data_source_end - __data_source );
+
+	.tbss (NOLOAD) : {
+		*(.tbss .tbss.* .gnu.linkonce.tb.*)
+		*(.tcommon)
+		PROVIDE( __tls_end = . );
+		PROVIDE( __tbss_end = . );
+	} >RAM0 AT>RAM0 :tls :ram
+	PROVIDE( __bss_start = ADDR(.tbss));
+	PROVIDE( __tbss_start = ADDR(.tbss));
+	PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) );
+	PROVIDE( __tbss_size = SIZEOF(.tbss) );
+	PROVIDE( __tls_size = __tls_end - __tls_base );
+	PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) );
+	PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) );
+	PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) );
+
+	/*
+	 * The linker special cases .tbss segments which are
+	 * identified as segments which are not loaded and are
+	 * thread_local.
+	 *
+	 * For these segments, the linker does not advance 'dot'
+	 * across them.  We actually need memory allocated for tbss,
+	 * so we create a special segment here just to make room
+	 */
+	/*
+	.tbss_space (NOLOAD) : {
+		. = ADDR(.tbss);
+		. = . + SIZEOF(.tbss);
+	} >RAM0 AT>RAM0 :ram
+	*/
+
+	.bss (NOLOAD) : {
+		*(.sbss*)
+		*(.gnu.linkonce.sb.*)
+		*(.bss .bss.*)
+		*(.gnu.linkonce.b.*)
+		*(COMMON)
+
+		/* Align the heap */
+		. = ALIGN(8);
+		__bss_end = .;
+	} >RAM0 AT>RAM0 :ram
+	PROVIDE( __non_tls_bss_start = ADDR(.bss) );
+	PROVIDE( __end = __bss_end );
+	PROVIDE( _end = __bss_end );
+	PROVIDE( end = __bss_end );
+	PROVIDE( __bss_size = __bss_end - __bss_start );
+
+	/* Make the rest of memory available for heap storage */
+	PROVIDE (__heap_start = __end);
+#ifdef HEAP_SIZE
+	PROVIDE (__heap_end = __heap_start + HEAP_SIZE);
+	PROVIDE (__heap_size = HEAP_SIZE);
+#else
+	PROVIDE (__heap_end = __stack - STACK_SIZE);
+	PROVIDE (__heap_size = __heap_end - __heap_start);
+#endif
+	.heap (NOLOAD) : {
+		. += __heap_size;
+	} >RAM0 :ram
+
+	/* Define a stack region to make sure it fits in memory */
+	PROVIDE(__stack = ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE);
+	PROVIDE(__stack_limit = __stack - STACK_SIZE);
+	.stack (__stack_limit) (NOLOAD) : {
+		. += STACK_SIZE;
+	} >RAM0 :ram
+
+#if __STACKSEAL_SIZE > 0
+	PROVIDE(__stack_seal = __stack);
+  	.stackseal (__stack) (NOLOAD) :
+  	{
+    	. += __STACKSEAL_SIZE;
+  	} >RAM0 :ram
+#endif
+
+	/* Throw away C++ exception handling information */
+
+	/*
+
+	/DISCARD/ : {
+		*(.note .note.*)
+		*(.eh_frame .eh_frame.*)
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+		*(.ARM.exidx*)
+	}
+
+	*/
+
+	/* Stabs debugging sections.  */
+	.stab          0 : { *(.stab) }
+	.stabstr       0 : { *(.stabstr) }
+	.stab.excl     0 : { *(.stab.excl) }
+	.stab.exclstr  0 : { *(.stab.exclstr) }
+	.stab.index    0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment       0 : { *(.comment) }
+	.gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) }
+	/* DWARF debug sections.
+	   Symbols in the DWARF debugging sections are relative to the beginning
+	   of the section so we begin them at 0.  */
+	/* DWARF 1.  */
+	.debug          0 : { *(.debug) }
+	.line           0 : { *(.line) }
+	/* GNU DWARF 1 extensions.  */
+	.debug_srcinfo  0 : { *(.debug_srcinfo) }
+	.debug_sfnames  0 : { *(.debug_sfnames) }
+	/* DWARF 1.1 and DWARF 2.  */
+	.debug_aranges  0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	/* DWARF 2.  */
+	.debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+	.debug_abbrev   0 : { *(.debug_abbrev) }
+	.debug_line     0 : { *(.debug_line .debug_line.* .debug_line_end) }
+	.debug_frame    0 : { *(.debug_frame) }
+	.debug_str      0 : { *(.debug_str) }
+	.debug_loc      0 : { *(.debug_loc) }
+	.debug_macinfo  0 : { *(.debug_macinfo) }
+	/* SGI/MIPS DWARF 2 extensions.  */
+	.debug_weaknames 0 : { *(.debug_weaknames) }
+	.debug_funcnames 0 : { *(.debug_funcnames) }
+	.debug_typenames 0 : { *(.debug_typenames) }
+	.debug_varnames  0 : { *(.debug_varnames) }
+	/* DWARF 3.  */
+	.debug_pubtypes 0 : { *(.debug_pubtypes) }
+	.debug_ranges   0 : { *(.debug_ranges) }
+	/* DWARF 5.  */
+	.debug_addr     0 : { *(.debug_addr) }
+	.debug_line_str 0 : { *(.debug_line_str) }
+	.debug_loclists 0 : { *(.debug_loclists) }
+	.debug_macro    0 : { *(.debug_macro) }
+	.debug_names    0 : { *(.debug_names) }
+	.debug_rnglists 0 : { *(.debug_rnglists) }
+	.debug_str_offsets 0 : { *(.debug_str_offsets) }
+	.debug_sup      0 : { *(.debug_sup) }
+	.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
+}
+/*
+ * Check that sections that are copied from flash to RAM have matching
+ * padding, so that a single memcpy() of __data_size copies the correct bytes.
+ */
+ASSERT( __data_size == __data_source_size,
+	"ERROR: .data/.tdata flash size does not match RAM size");
diff --git a/Testing/cmsis_build/linker_scripts/gcc_m0p_mps3.ld b/Testing/cmsis_build/linker_scripts/gcc_m0p_mps3.ld
new file mode 100644
index 000000000..a018e5d4e
--- /dev/null
+++ b/Testing/cmsis_build/linker_scripts/gcc_m0p_mps3.ld
@@ -0,0 +1,294 @@
+/*
+ * Copyright (c) 2023 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------------
+  Stack seal size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __STACKSEAL_SIZE   ( 8 )
+#else
+#define __STACKSEAL_SIZE   ( 0 )
+#endif
+
+/* ----------------------------------------------------------------------------
+  Memory definition
+ *----------------------------------------------------------------------------*/
+MEMORY
+{
+  ROM0  (rx)  : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE
+#if __ROM1_SIZE > 0
+  ROM1  (rx)  : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE
+#endif
+#if __ROM2_SIZE > 0
+  ROM2  (rx)  : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE
+#endif
+#if __ROM3_SIZE > 0
+  ROM3  (rx)  : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE
+#endif
+
+  RAM0  (rwx) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE
+#if __RAM1_SIZE > 0
+  RAM1  (rwx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE
+#endif
+#if __RAM2_SIZE > 0
+  RAM2  (rwx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE
+#endif
+#if __RAM3_SIZE > 0
+  RAM3  (rwx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE
+#endif
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext          (deprecated)
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+  .text :
+  {
+    KEEP(*(.vectors))
+    *(.text*)
+
+    KEEP(*(.init))
+    KEEP(*(.fini))
+
+    /* .ctors */
+    *crtbegin.o(.ctors)
+    *crtbegin?.o(.ctors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+    *(SORT(.ctors.*))
+    *(.ctors)
+
+    /* .dtors */
+    *crtbegin.o(.dtors)
+    *crtbegin?.o(.dtors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+    *(SORT(.dtors.*))
+    *(.dtors)
+
+    *(.rodata*)
+
+    KEEP(*(.eh_frame*))
+  } > ROM0
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  .gnu.sgstubs :
+  {
+    . = ALIGN(32);
+  } > ROM0
+#endif
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > ROM0
+
+  __exidx_start = .;
+  .ARM.exidx :
+  {
+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+  } > ROM0
+  __exidx_end = .;
+
+  .copy.table :
+  {
+    . = ALIGN(4);
+    __copy_table_start__ = .;
+
+    LONG (LOADADDR(.data))
+    LONG (ADDR(.data))
+    LONG (SIZEOF(.data) / 4)
+
+    /* Add each additional data section here */
+/*
+    LONG (LOADADDR(.data2))
+    LONG (ADDR(.data2))
+    LONG (SIZEOF(.data2) / 4)
+*/
+    __copy_table_end__ = .;
+  } > ROM0
+
+  .zero.table :
+  {
+    . = ALIGN(4);
+    __zero_table_start__ = .;
+
+/*  .bss initialization to zero is already done during C Run-Time Startup.
+    LONG (ADDR(.bss))
+    LONG (SIZEOF(.bss) / 4)
+*/
+
+    /* Add each additional bss section here */
+/*
+    LONG (ADDR(.bss2))
+    LONG (SIZEOF(.bss2) / 4)
+*/
+    __zero_table_end__ = .;
+  } > ROM0
+
+  /*
+   * This __etext variable is kept for backward compatibility with older,
+   * ASM based startup files.
+   */
+  PROVIDE(__etext = LOADADDR(.data));
+
+  .data : ALIGN(4)
+  {
+    __data_start__ = .;
+    *(vtable)
+    *(.data)
+    *(.data.*)
+
+    . = ALIGN(4);
+    /* preinit data */
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP(*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+
+    . = ALIGN(4);
+    /* init data */
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP(*(SORT(.init_array.*)))
+    KEEP(*(.init_array))
+    PROVIDE_HIDDEN (__init_array_end = .);
+
+    . = ALIGN(4);
+    /* finit data */
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP(*(SORT(.fini_array.*)))
+    KEEP(*(.fini_array))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    /* All data end */
+    __data_end__ = .;
+
+  } > RAM0 AT > ROM0
+
+  /*
+   * Secondary data section, optional
+   *
+   * Remember to add each additional data section
+   * to the .copy.table above to assure proper
+   * initialization during startup.
+   */
+/*
+  .data2 : ALIGN(4)
+  {
+    . = ALIGN(4);
+    __data2_start__ = .;
+    *(.data2)
+    *(.data2.*)
+    . = ALIGN(4);
+    __data2_end__ = .;
+
+  } > RAM1 AT > ROM0 
+*/
+
+  .bss :
+  {
+    . = ALIGN(4);
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss.*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+  } > RAM0 AT > RAM0
+
+  /*
+   * Secondary bss section, optional
+   *
+   * Remember to add each additional bss section
+   * to the .zero.table above to assure proper
+   * initialization during startup.
+   */
+/*
+  .bss2 :
+  {
+    . = ALIGN(4);
+    __bss2_start__ = .;
+    *(.bss2)
+    *(.bss2.*)
+    . = ALIGN(4);
+    __bss2_end__ = .;
+  } > RAM1 AT > RAM1
+*/
+
+  .heap (NOLOAD) :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    . = . + __HEAP_SIZE;
+    . = ALIGN(8);
+    __HeapLimit = .;
+  } > RAM0
+
+  .stack (ORIGIN(RAM0) + LENGTH(RAM0) - __STACK_SIZE - __STACKSEAL_SIZE) (NOLOAD) :
+  {
+    . = ALIGN(8);
+    __StackLimit = .;
+    . = . + __STACK_SIZE;
+    . = ALIGN(8);
+    __StackTop = .;
+  } > RAM0
+  PROVIDE(__stack = __StackTop);
+
+#if __STACKSEAL_SIZE > 0
+  .stackseal (ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE) (NOLOAD) :
+  {
+    . = ALIGN(8);
+    __StackSeal = .;
+    . = . + 8;
+    . = ALIGN(8);
+  } > RAM0
+#endif
+
+  /* Check if data + heap + stack exceeds RAM limit */
+  ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/Testing/cmsis_build/linker_scripts/gcc_m33_mps3.ld b/Testing/cmsis_build/linker_scripts/gcc_m33_mps3.ld
new file mode 100644
index 000000000..a018e5d4e
--- /dev/null
+++ b/Testing/cmsis_build/linker_scripts/gcc_m33_mps3.ld
@@ -0,0 +1,294 @@
+/*
+ * Copyright (c) 2023 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------------
+  Stack seal size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __STACKSEAL_SIZE   ( 8 )
+#else
+#define __STACKSEAL_SIZE   ( 0 )
+#endif
+
+/* ----------------------------------------------------------------------------
+  Memory definition
+ *----------------------------------------------------------------------------*/
+MEMORY
+{
+  ROM0  (rx)  : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE
+#if __ROM1_SIZE > 0
+  ROM1  (rx)  : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE
+#endif
+#if __ROM2_SIZE > 0
+  ROM2  (rx)  : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE
+#endif
+#if __ROM3_SIZE > 0
+  ROM3  (rx)  : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE
+#endif
+
+  RAM0  (rwx) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE
+#if __RAM1_SIZE > 0
+  RAM1  (rwx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE
+#endif
+#if __RAM2_SIZE > 0
+  RAM2  (rwx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE
+#endif
+#if __RAM3_SIZE > 0
+  RAM3  (rwx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE
+#endif
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext          (deprecated)
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+  .text :
+  {
+    KEEP(*(.vectors))
+    *(.text*)
+
+    KEEP(*(.init))
+    KEEP(*(.fini))
+
+    /* .ctors */
+    *crtbegin.o(.ctors)
+    *crtbegin?.o(.ctors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+    *(SORT(.ctors.*))
+    *(.ctors)
+
+    /* .dtors */
+    *crtbegin.o(.dtors)
+    *crtbegin?.o(.dtors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+    *(SORT(.dtors.*))
+    *(.dtors)
+
+    *(.rodata*)
+
+    KEEP(*(.eh_frame*))
+  } > ROM0
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  .gnu.sgstubs :
+  {
+    . = ALIGN(32);
+  } > ROM0
+#endif
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > ROM0
+
+  __exidx_start = .;
+  .ARM.exidx :
+  {
+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+  } > ROM0
+  __exidx_end = .;
+
+  .copy.table :
+  {
+    . = ALIGN(4);
+    __copy_table_start__ = .;
+
+    LONG (LOADADDR(.data))
+    LONG (ADDR(.data))
+    LONG (SIZEOF(.data) / 4)
+
+    /* Add each additional data section here */
+/*
+    LONG (LOADADDR(.data2))
+    LONG (ADDR(.data2))
+    LONG (SIZEOF(.data2) / 4)
+*/
+    __copy_table_end__ = .;
+  } > ROM0
+
+  .zero.table :
+  {
+    . = ALIGN(4);
+    __zero_table_start__ = .;
+
+/*  .bss initialization to zero is already done during C Run-Time Startup.
+    LONG (ADDR(.bss))
+    LONG (SIZEOF(.bss) / 4)
+*/
+
+    /* Add each additional bss section here */
+/*
+    LONG (ADDR(.bss2))
+    LONG (SIZEOF(.bss2) / 4)
+*/
+    __zero_table_end__ = .;
+  } > ROM0
+
+  /*
+   * This __etext variable is kept for backward compatibility with older,
+   * ASM based startup files.
+   */
+  PROVIDE(__etext = LOADADDR(.data));
+
+  .data : ALIGN(4)
+  {
+    __data_start__ = .;
+    *(vtable)
+    *(.data)
+    *(.data.*)
+
+    . = ALIGN(4);
+    /* preinit data */
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP(*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+
+    . = ALIGN(4);
+    /* init data */
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP(*(SORT(.init_array.*)))
+    KEEP(*(.init_array))
+    PROVIDE_HIDDEN (__init_array_end = .);
+
+    . = ALIGN(4);
+    /* finit data */
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP(*(SORT(.fini_array.*)))
+    KEEP(*(.fini_array))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    /* All data end */
+    __data_end__ = .;
+
+  } > RAM0 AT > ROM0
+
+  /*
+   * Secondary data section, optional
+   *
+   * Remember to add each additional data section
+   * to the .copy.table above to assure proper
+   * initialization during startup.
+   */
+/*
+  .data2 : ALIGN(4)
+  {
+    . = ALIGN(4);
+    __data2_start__ = .;
+    *(.data2)
+    *(.data2.*)
+    . = ALIGN(4);
+    __data2_end__ = .;
+
+  } > RAM1 AT > ROM0 
+*/
+
+  .bss :
+  {
+    . = ALIGN(4);
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss.*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+  } > RAM0 AT > RAM0
+
+  /*
+   * Secondary bss section, optional
+   *
+   * Remember to add each additional bss section
+   * to the .zero.table above to assure proper
+   * initialization during startup.
+   */
+/*
+  .bss2 :
+  {
+    . = ALIGN(4);
+    __bss2_start__ = .;
+    *(.bss2)
+    *(.bss2.*)
+    . = ALIGN(4);
+    __bss2_end__ = .;
+  } > RAM1 AT > RAM1
+*/
+
+  .heap (NOLOAD) :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    . = . + __HEAP_SIZE;
+    . = ALIGN(8);
+    __HeapLimit = .;
+  } > RAM0
+
+  .stack (ORIGIN(RAM0) + LENGTH(RAM0) - __STACK_SIZE - __STACKSEAL_SIZE) (NOLOAD) :
+  {
+    . = ALIGN(8);
+    __StackLimit = .;
+    . = . + __STACK_SIZE;
+    . = ALIGN(8);
+    __StackTop = .;
+  } > RAM0
+  PROVIDE(__stack = __StackTop);
+
+#if __STACKSEAL_SIZE > 0
+  .stackseal (ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE) (NOLOAD) :
+  {
+    . = ALIGN(8);
+    __StackSeal = .;
+    . = . + 8;
+    . = ALIGN(8);
+  } > RAM0
+#endif
+
+  /* Check if data + heap + stack exceeds RAM limit */
+  ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/Testing/cmsis_build/linker_scripts/gcc_m3_mps3.ld b/Testing/cmsis_build/linker_scripts/gcc_m3_mps3.ld
new file mode 100644
index 000000000..a018e5d4e
--- /dev/null
+++ b/Testing/cmsis_build/linker_scripts/gcc_m3_mps3.ld
@@ -0,0 +1,294 @@
+/*
+ * Copyright (c) 2023 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------------
+  Stack seal size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __STACKSEAL_SIZE   ( 8 )
+#else
+#define __STACKSEAL_SIZE   ( 0 )
+#endif
+
+/* ----------------------------------------------------------------------------
+  Memory definition
+ *----------------------------------------------------------------------------*/
+MEMORY
+{
+  ROM0  (rx)  : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE
+#if __ROM1_SIZE > 0
+  ROM1  (rx)  : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE
+#endif
+#if __ROM2_SIZE > 0
+  ROM2  (rx)  : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE
+#endif
+#if __ROM3_SIZE > 0
+  ROM3  (rx)  : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE
+#endif
+
+  RAM0  (rwx) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE
+#if __RAM1_SIZE > 0
+  RAM1  (rwx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE
+#endif
+#if __RAM2_SIZE > 0
+  RAM2  (rwx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE
+#endif
+#if __RAM3_SIZE > 0
+  RAM3  (rwx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE
+#endif
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext          (deprecated)
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+  .text :
+  {
+    KEEP(*(.vectors))
+    *(.text*)
+
+    KEEP(*(.init))
+    KEEP(*(.fini))
+
+    /* .ctors */
+    *crtbegin.o(.ctors)
+    *crtbegin?.o(.ctors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+    *(SORT(.ctors.*))
+    *(.ctors)
+
+    /* .dtors */
+    *crtbegin.o(.dtors)
+    *crtbegin?.o(.dtors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+    *(SORT(.dtors.*))
+    *(.dtors)
+
+    *(.rodata*)
+
+    KEEP(*(.eh_frame*))
+  } > ROM0
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  .gnu.sgstubs :
+  {
+    . = ALIGN(32);
+  } > ROM0
+#endif
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > ROM0
+
+  __exidx_start = .;
+  .ARM.exidx :
+  {
+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+  } > ROM0
+  __exidx_end = .;
+
+  .copy.table :
+  {
+    . = ALIGN(4);
+    __copy_table_start__ = .;
+
+    LONG (LOADADDR(.data))
+    LONG (ADDR(.data))
+    LONG (SIZEOF(.data) / 4)
+
+    /* Add each additional data section here */
+/*
+    LONG (LOADADDR(.data2))
+    LONG (ADDR(.data2))
+    LONG (SIZEOF(.data2) / 4)
+*/
+    __copy_table_end__ = .;
+  } > ROM0
+
+  .zero.table :
+  {
+    . = ALIGN(4);
+    __zero_table_start__ = .;
+
+/*  .bss initialization to zero is already done during C Run-Time Startup.
+    LONG (ADDR(.bss))
+    LONG (SIZEOF(.bss) / 4)
+*/
+
+    /* Add each additional bss section here */
+/*
+    LONG (ADDR(.bss2))
+    LONG (SIZEOF(.bss2) / 4)
+*/
+    __zero_table_end__ = .;
+  } > ROM0
+
+  /*
+   * This __etext variable is kept for backward compatibility with older,
+   * ASM based startup files.
+   */
+  PROVIDE(__etext = LOADADDR(.data));
+
+  .data : ALIGN(4)
+  {
+    __data_start__ = .;
+    *(vtable)
+    *(.data)
+    *(.data.*)
+
+    . = ALIGN(4);
+    /* preinit data */
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP(*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+
+    . = ALIGN(4);
+    /* init data */
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP(*(SORT(.init_array.*)))
+    KEEP(*(.init_array))
+    PROVIDE_HIDDEN (__init_array_end = .);
+
+    . = ALIGN(4);
+    /* finit data */
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP(*(SORT(.fini_array.*)))
+    KEEP(*(.fini_array))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    /* All data end */
+    __data_end__ = .;
+
+  } > RAM0 AT > ROM0
+
+  /*
+   * Secondary data section, optional
+   *
+   * Remember to add each additional data section
+   * to the .copy.table above to assure proper
+   * initialization during startup.
+   */
+/*
+  .data2 : ALIGN(4)
+  {
+    . = ALIGN(4);
+    __data2_start__ = .;
+    *(.data2)
+    *(.data2.*)
+    . = ALIGN(4);
+    __data2_end__ = .;
+
+  } > RAM1 AT > ROM0 
+*/
+
+  .bss :
+  {
+    . = ALIGN(4);
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss.*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+  } > RAM0 AT > RAM0
+
+  /*
+   * Secondary bss section, optional
+   *
+   * Remember to add each additional bss section
+   * to the .zero.table above to assure proper
+   * initialization during startup.
+   */
+/*
+  .bss2 :
+  {
+    . = ALIGN(4);
+    __bss2_start__ = .;
+    *(.bss2)
+    *(.bss2.*)
+    . = ALIGN(4);
+    __bss2_end__ = .;
+  } > RAM1 AT > RAM1
+*/
+
+  .heap (NOLOAD) :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    . = . + __HEAP_SIZE;
+    . = ALIGN(8);
+    __HeapLimit = .;
+  } > RAM0
+
+  .stack (ORIGIN(RAM0) + LENGTH(RAM0) - __STACK_SIZE - __STACKSEAL_SIZE) (NOLOAD) :
+  {
+    . = ALIGN(8);
+    __StackLimit = .;
+    . = . + __STACK_SIZE;
+    . = ALIGN(8);
+    __StackTop = .;
+  } > RAM0
+  PROVIDE(__stack = __StackTop);
+
+#if __STACKSEAL_SIZE > 0
+  .stackseal (ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE) (NOLOAD) :
+  {
+    . = ALIGN(8);
+    __StackSeal = .;
+    . = . + 8;
+    . = ALIGN(8);
+  } > RAM0
+#endif
+
+  /* Check if data + heap + stack exceeds RAM limit */
+  ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/Testing/cmsis_build/linker_scripts/gcc_m4_mps3.ld b/Testing/cmsis_build/linker_scripts/gcc_m4_mps3.ld
new file mode 100644
index 000000000..a018e5d4e
--- /dev/null
+++ b/Testing/cmsis_build/linker_scripts/gcc_m4_mps3.ld
@@ -0,0 +1,294 @@
+/*
+ * Copyright (c) 2023 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------------
+  Stack seal size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __STACKSEAL_SIZE   ( 8 )
+#else
+#define __STACKSEAL_SIZE   ( 0 )
+#endif
+
+/* ----------------------------------------------------------------------------
+  Memory definition
+ *----------------------------------------------------------------------------*/
+MEMORY
+{
+  ROM0  (rx)  : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE
+#if __ROM1_SIZE > 0
+  ROM1  (rx)  : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE
+#endif
+#if __ROM2_SIZE > 0
+  ROM2  (rx)  : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE
+#endif
+#if __ROM3_SIZE > 0
+  ROM3  (rx)  : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE
+#endif
+
+  RAM0  (rwx) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE
+#if __RAM1_SIZE > 0
+  RAM1  (rwx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE
+#endif
+#if __RAM2_SIZE > 0
+  RAM2  (rwx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE
+#endif
+#if __RAM3_SIZE > 0
+  RAM3  (rwx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE
+#endif
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext          (deprecated)
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+  .text :
+  {
+    KEEP(*(.vectors))
+    *(.text*)
+
+    KEEP(*(.init))
+    KEEP(*(.fini))
+
+    /* .ctors */
+    *crtbegin.o(.ctors)
+    *crtbegin?.o(.ctors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+    *(SORT(.ctors.*))
+    *(.ctors)
+
+    /* .dtors */
+    *crtbegin.o(.dtors)
+    *crtbegin?.o(.dtors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+    *(SORT(.dtors.*))
+    *(.dtors)
+
+    *(.rodata*)
+
+    KEEP(*(.eh_frame*))
+  } > ROM0
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  .gnu.sgstubs :
+  {
+    . = ALIGN(32);
+  } > ROM0
+#endif
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > ROM0
+
+  __exidx_start = .;
+  .ARM.exidx :
+  {
+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+  } > ROM0
+  __exidx_end = .;
+
+  .copy.table :
+  {
+    . = ALIGN(4);
+    __copy_table_start__ = .;
+
+    LONG (LOADADDR(.data))
+    LONG (ADDR(.data))
+    LONG (SIZEOF(.data) / 4)
+
+    /* Add each additional data section here */
+/*
+    LONG (LOADADDR(.data2))
+    LONG (ADDR(.data2))
+    LONG (SIZEOF(.data2) / 4)
+*/
+    __copy_table_end__ = .;
+  } > ROM0
+
+  .zero.table :
+  {
+    . = ALIGN(4);
+    __zero_table_start__ = .;
+
+/*  .bss initialization to zero is already done during C Run-Time Startup.
+    LONG (ADDR(.bss))
+    LONG (SIZEOF(.bss) / 4)
+*/
+
+    /* Add each additional bss section here */
+/*
+    LONG (ADDR(.bss2))
+    LONG (SIZEOF(.bss2) / 4)
+*/
+    __zero_table_end__ = .;
+  } > ROM0
+
+  /*
+   * This __etext variable is kept for backward compatibility with older,
+   * ASM based startup files.
+   */
+  PROVIDE(__etext = LOADADDR(.data));
+
+  .data : ALIGN(4)
+  {
+    __data_start__ = .;
+    *(vtable)
+    *(.data)
+    *(.data.*)
+
+    . = ALIGN(4);
+    /* preinit data */
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP(*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+
+    . = ALIGN(4);
+    /* init data */
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP(*(SORT(.init_array.*)))
+    KEEP(*(.init_array))
+    PROVIDE_HIDDEN (__init_array_end = .);
+
+    . = ALIGN(4);
+    /* finit data */
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP(*(SORT(.fini_array.*)))
+    KEEP(*(.fini_array))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    /* All data end */
+    __data_end__ = .;
+
+  } > RAM0 AT > ROM0
+
+  /*
+   * Secondary data section, optional
+   *
+   * Remember to add each additional data section
+   * to the .copy.table above to assure proper
+   * initialization during startup.
+   */
+/*
+  .data2 : ALIGN(4)
+  {
+    . = ALIGN(4);
+    __data2_start__ = .;
+    *(.data2)
+    *(.data2.*)
+    . = ALIGN(4);
+    __data2_end__ = .;
+
+  } > RAM1 AT > ROM0 
+*/
+
+  .bss :
+  {
+    . = ALIGN(4);
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss.*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+  } > RAM0 AT > RAM0
+
+  /*
+   * Secondary bss section, optional
+   *
+   * Remember to add each additional bss section
+   * to the .zero.table above to assure proper
+   * initialization during startup.
+   */
+/*
+  .bss2 :
+  {
+    . = ALIGN(4);
+    __bss2_start__ = .;
+    *(.bss2)
+    *(.bss2.*)
+    . = ALIGN(4);
+    __bss2_end__ = .;
+  } > RAM1 AT > RAM1
+*/
+
+  .heap (NOLOAD) :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    . = . + __HEAP_SIZE;
+    . = ALIGN(8);
+    __HeapLimit = .;
+  } > RAM0
+
+  .stack (ORIGIN(RAM0) + LENGTH(RAM0) - __STACK_SIZE - __STACKSEAL_SIZE) (NOLOAD) :
+  {
+    . = ALIGN(8);
+    __StackLimit = .;
+    . = . + __STACK_SIZE;
+    . = ALIGN(8);
+    __StackTop = .;
+  } > RAM0
+  PROVIDE(__stack = __StackTop);
+
+#if __STACKSEAL_SIZE > 0
+  .stackseal (ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE) (NOLOAD) :
+  {
+    . = ALIGN(8);
+    __StackSeal = .;
+    . = . + 8;
+    . = ALIGN(8);
+  } > RAM0
+#endif
+
+  /* Check if data + heap + stack exceeds RAM limit */
+  ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/Testing/cmsis_build/linker_scripts/gcc_m7_mps3.ld b/Testing/cmsis_build/linker_scripts/gcc_m7_mps3.ld
new file mode 100644
index 000000000..a018e5d4e
--- /dev/null
+++ b/Testing/cmsis_build/linker_scripts/gcc_m7_mps3.ld
@@ -0,0 +1,294 @@
+/*
+ * Copyright (c) 2023 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------------
+  Stack seal size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __STACKSEAL_SIZE   ( 8 )
+#else
+#define __STACKSEAL_SIZE   ( 0 )
+#endif
+
+/* ----------------------------------------------------------------------------
+  Memory definition
+ *----------------------------------------------------------------------------*/
+MEMORY
+{
+  ROM0  (rx)  : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE
+#if __ROM1_SIZE > 0
+  ROM1  (rx)  : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE
+#endif
+#if __ROM2_SIZE > 0
+  ROM2  (rx)  : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE
+#endif
+#if __ROM3_SIZE > 0
+  ROM3  (rx)  : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE
+#endif
+
+  RAM0  (rwx) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE
+#if __RAM1_SIZE > 0
+  RAM1  (rwx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE
+#endif
+#if __RAM2_SIZE > 0
+  RAM2  (rwx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE
+#endif
+#if __RAM3_SIZE > 0
+  RAM3  (rwx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE
+#endif
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext          (deprecated)
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+  .text :
+  {
+    KEEP(*(.vectors))
+    *(.text*)
+
+    KEEP(*(.init))
+    KEEP(*(.fini))
+
+    /* .ctors */
+    *crtbegin.o(.ctors)
+    *crtbegin?.o(.ctors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+    *(SORT(.ctors.*))
+    *(.ctors)
+
+    /* .dtors */
+    *crtbegin.o(.dtors)
+    *crtbegin?.o(.dtors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+    *(SORT(.dtors.*))
+    *(.dtors)
+
+    *(.rodata*)
+
+    KEEP(*(.eh_frame*))
+  } > ROM0
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  .gnu.sgstubs :
+  {
+    . = ALIGN(32);
+  } > ROM0
+#endif
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > ROM0
+
+  __exidx_start = .;
+  .ARM.exidx :
+  {
+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+  } > ROM0
+  __exidx_end = .;
+
+  .copy.table :
+  {
+    . = ALIGN(4);
+    __copy_table_start__ = .;
+
+    LONG (LOADADDR(.data))
+    LONG (ADDR(.data))
+    LONG (SIZEOF(.data) / 4)
+
+    /* Add each additional data section here */
+/*
+    LONG (LOADADDR(.data2))
+    LONG (ADDR(.data2))
+    LONG (SIZEOF(.data2) / 4)
+*/
+    __copy_table_end__ = .;
+  } > ROM0
+
+  .zero.table :
+  {
+    . = ALIGN(4);
+    __zero_table_start__ = .;
+
+/*  .bss initialization to zero is already done during C Run-Time Startup.
+    LONG (ADDR(.bss))
+    LONG (SIZEOF(.bss) / 4)
+*/
+
+    /* Add each additional bss section here */
+/*
+    LONG (ADDR(.bss2))
+    LONG (SIZEOF(.bss2) / 4)
+*/
+    __zero_table_end__ = .;
+  } > ROM0
+
+  /*
+   * This __etext variable is kept for backward compatibility with older,
+   * ASM based startup files.
+   */
+  PROVIDE(__etext = LOADADDR(.data));
+
+  .data : ALIGN(4)
+  {
+    __data_start__ = .;
+    *(vtable)
+    *(.data)
+    *(.data.*)
+
+    . = ALIGN(4);
+    /* preinit data */
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP(*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+
+    . = ALIGN(4);
+    /* init data */
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP(*(SORT(.init_array.*)))
+    KEEP(*(.init_array))
+    PROVIDE_HIDDEN (__init_array_end = .);
+
+    . = ALIGN(4);
+    /* finit data */
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP(*(SORT(.fini_array.*)))
+    KEEP(*(.fini_array))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    /* All data end */
+    __data_end__ = .;
+
+  } > RAM0 AT > ROM0
+
+  /*
+   * Secondary data section, optional
+   *
+   * Remember to add each additional data section
+   * to the .copy.table above to assure proper
+   * initialization during startup.
+   */
+/*
+  .data2 : ALIGN(4)
+  {
+    . = ALIGN(4);
+    __data2_start__ = .;
+    *(.data2)
+    *(.data2.*)
+    . = ALIGN(4);
+    __data2_end__ = .;
+
+  } > RAM1 AT > ROM0 
+*/
+
+  .bss :
+  {
+    . = ALIGN(4);
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss.*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+  } > RAM0 AT > RAM0
+
+  /*
+   * Secondary bss section, optional
+   *
+   * Remember to add each additional bss section
+   * to the .zero.table above to assure proper
+   * initialization during startup.
+   */
+/*
+  .bss2 :
+  {
+    . = ALIGN(4);
+    __bss2_start__ = .;
+    *(.bss2)
+    *(.bss2.*)
+    . = ALIGN(4);
+    __bss2_end__ = .;
+  } > RAM1 AT > RAM1
+*/
+
+  .heap (NOLOAD) :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    . = . + __HEAP_SIZE;
+    . = ALIGN(8);
+    __HeapLimit = .;
+  } > RAM0
+
+  .stack (ORIGIN(RAM0) + LENGTH(RAM0) - __STACK_SIZE - __STACKSEAL_SIZE) (NOLOAD) :
+  {
+    . = ALIGN(8);
+    __StackLimit = .;
+    . = . + __STACK_SIZE;
+    . = ALIGN(8);
+    __StackTop = .;
+  } > RAM0
+  PROVIDE(__stack = __StackTop);
+
+#if __STACKSEAL_SIZE > 0
+  .stackseal (ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE) (NOLOAD) :
+  {
+    . = ALIGN(8);
+    __StackSeal = .;
+    . = . + 8;
+    . = ALIGN(8);
+  } > RAM0
+#endif
+
+  /* Check if data + heap + stack exceeds RAM limit */
+  ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/Testing/cmsis_build/linker_scripts/gcc_sse300_mps3.ld b/Testing/cmsis_build/linker_scripts/gcc_sse300_mps3.ld
new file mode 100644
index 000000000..691e6685d
--- /dev/null
+++ b/Testing/cmsis_build/linker_scripts/gcc_sse300_mps3.ld
@@ -0,0 +1,295 @@
+/*
+ * Copyright (c) 2023 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------------
+  Stack seal size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __STACKSEAL_SIZE   ( 8 )
+#else
+#define __STACKSEAL_SIZE   ( 0 )
+#endif
+
+/* ----------------------------------------------------------------------------
+  Memory definition
+ *----------------------------------------------------------------------------*/
+MEMORY
+{
+  ROM0  (rx)  : ORIGIN = S_CODE_START, LENGTH = S_CODE_SIZE
+#if __ROM1_SIZE > 0
+  ROM1  (rx)  : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE
+#endif
+#if __ROM2_SIZE > 0
+  ROM2  (rx)  : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE
+#endif
+#if __ROM3_SIZE > 0
+  ROM3  (rx)  : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE
+#endif
+
+  RAM0  (rw) : ORIGIN = S_DDR4_START, LENGTH = S_DDR4_SIZE
+#if __RAM1_SIZE > 0
+  RAM1  (rw) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE
+#endif
+#if __RAM2_SIZE > 0
+  RAM2  (rw) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE
+#endif
+#if __RAM3_SIZE > 0
+  RAM3  (rw) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE
+#endif
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext          (deprecated)
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+  .text :
+  {
+    KEEP(*(.vectors))
+    *(.text*)
+
+    KEEP(*(.init))
+    KEEP(*(.fini))
+
+    /* .ctors */
+    *crtbegin.o(.ctors)
+    *crtbegin?.o(.ctors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+    *(SORT(.ctors.*))
+    *(.ctors)
+
+    /* .dtors */
+    *crtbegin.o(.dtors)
+    *crtbegin?.o(.dtors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+    *(SORT(.dtors.*))
+    *(.dtors)
+
+    /* *(.rodata*) */
+
+    KEEP(*(.eh_frame*))
+  } > RAM0
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  .gnu.sgstubs :
+  {
+    . = ALIGN(32);
+  } > RAM0
+#endif
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > RAM0
+
+  __exidx_start = .;
+  .ARM.exidx :
+  {
+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+  } > RAM0
+  __exidx_end = .;
+
+  .copy.table :
+  {
+    . = ALIGN(4);
+    __copy_table_start__ = .;
+
+    LONG (LOADADDR(.data))
+    LONG (ADDR(.data))
+    LONG (SIZEOF(.data) / 4)
+
+    /* Add each additional data section here */
+/*
+    LONG (LOADADDR(.data2))
+    LONG (ADDR(.data2))
+    LONG (SIZEOF(.data2) / 4)
+*/
+    __copy_table_end__ = .;
+  } > RAM0
+
+  .zero.table :
+  {
+    . = ALIGN(4);
+    __zero_table_start__ = .;
+
+/*  .bss initialization to zero is already done during C Run-Time Startup.
+    LONG (ADDR(.bss))
+    LONG (SIZEOF(.bss) / 4)
+*/
+
+    /* Add each additional bss section here */
+/*
+    LONG (ADDR(.bss2))
+    LONG (SIZEOF(.bss2) / 4)
+*/
+    __zero_table_end__ = .;
+  } > RAM0
+
+  /*
+   * This __etext variable is kept for backward compatibility with older,
+   * ASM based startup files.
+   */
+  PROVIDE(__etext = LOADADDR(.data));
+
+  .data : ALIGN(4)
+  {
+    __data_start__ = .;
+    *(vtable)
+    *(.data)
+    *(.data.*)
+    *(.rodata*)
+
+    . = ALIGN(4);
+    /* preinit data */
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP(*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+
+    . = ALIGN(4);
+    /* init data */
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP(*(SORT(.init_array.*)))
+    KEEP(*(.init_array))
+    PROVIDE_HIDDEN (__init_array_end = .);
+
+    . = ALIGN(4);
+    /* finit data */
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP(*(SORT(.fini_array.*)))
+    KEEP(*(.fini_array))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    /* All data end */
+    __data_end__ = .;
+
+  } > RAM0
+
+  /*
+   * Secondary data section, optional
+   *
+   * Remember to add each additional data section
+   * to the .copy.table above to assure proper
+   * initialization during startup.
+   */
+/*
+  .data2 : ALIGN(4)
+  {
+    . = ALIGN(4);
+    __data2_start__ = .;
+    *(.data2)
+    *(.data2.*)
+    . = ALIGN(4);
+    __data2_end__ = .;
+
+  } > RAM1 AT > ROM0
+*/
+
+  .bss :
+  {
+    . = ALIGN(4);
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss.*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+  } > RAM0
+
+  /*
+   * Secondary bss section, optional
+   *
+   * Remember to add each additional bss section
+   * to the .zero.table above to assure proper
+   * initialization during startup.
+   */
+/*
+  .bss2 :
+  {
+    . = ALIGN(4);
+    __bss2_start__ = .;
+    *(.bss2)
+    *(.bss2.*)
+    . = ALIGN(4);
+    __bss2_end__ = .;
+  } > RAM1 AT > RAM1
+*/
+
+  .heap (NOLOAD) :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    . = . + HEAP_SIZE;
+    . = ALIGN(8);
+    __HeapLimit = .;
+  } > RAM0
+
+  .stack (ORIGIN(RAM0) + LENGTH(RAM0) - STACK_SIZE - __STACKSEAL_SIZE) (NOLOAD) :
+  {
+    . = ALIGN(8);
+    __StackLimit = .;
+    . = . + STACK_SIZE;
+    . = ALIGN(8);
+    __StackTop = .;
+  } > RAM0
+  PROVIDE(__stack = __StackTop);
+
+#if __STACKSEAL_SIZE > 0
+  .stackseal (ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE) (NOLOAD) :
+  {
+    . = ALIGN(8);
+    __StackSeal = .;
+    . = . + 8;
+    . = ALIGN(8);
+  } > RAM0
+#endif
+
+  /* Check if data + heap + stack exceeds RAM limit */
+  ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/Testing/cmsis_build/linker_scripts/gcc_sse310_mps3_s.ld b/Testing/cmsis_build/linker_scripts/gcc_sse310_mps3_s.ld
new file mode 100644
index 000000000..7bea37e1a
--- /dev/null
+++ b/Testing/cmsis_build/linker_scripts/gcc_sse310_mps3_s.ld
@@ -0,0 +1,295 @@
+/*
+ * Copyright (c) 2023 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------------
+  Stack seal size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __STACKSEAL_SIZE   ( 8 )
+#else
+#define __STACKSEAL_SIZE   ( 0 )
+#endif
+
+/* ----------------------------------------------------------------------------
+  Memory definition
+ *----------------------------------------------------------------------------*/
+MEMORY
+{
+  ROM0  (rx)  : ORIGIN = S_CODE_START, LENGTH = S_CODE_SIZE
+#if __ROM1_SIZE > 0
+  ROM1  (rx)  : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE
+#endif
+#if __ROM2_SIZE > 0
+  ROM2  (rx)  : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE
+#endif
+#if __ROM3_SIZE > 0
+  ROM3  (rx)  : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE
+#endif
+
+  RAM0  (rwx) : ORIGIN = S_DATA_START, LENGTH = S_DATA_SIZE
+#if __RAM1_SIZE > 0
+  RAM1  (rwx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE
+#endif
+#if __RAM2_SIZE > 0
+  RAM2  (rwx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE
+#endif
+#if __RAM3_SIZE > 0
+  RAM3  (rwx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE
+#endif
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext          (deprecated)
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+  .text :
+  {
+    KEEP(*(.vectors))
+    *(.text*)
+
+    KEEP(*(.init))
+    KEEP(*(.fini))
+
+    /* .ctors */
+    *crtbegin.o(.ctors)
+    *crtbegin?.o(.ctors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+    *(SORT(.ctors.*))
+    *(.ctors)
+
+    /* .dtors */
+    *crtbegin.o(.dtors)
+    *crtbegin?.o(.dtors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+    *(SORT(.dtors.*))
+    *(.dtors)
+
+    /* *(.rodata*) */
+
+    KEEP(*(.eh_frame*))
+  } > ROM0
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  .gnu.sgstubs :
+  {
+    . = ALIGN(32);
+  } > ROM0
+#endif
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > ROM0
+
+  __exidx_start = .;
+  .ARM.exidx :
+  {
+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+  } > ROM0
+  __exidx_end = .;
+
+  .copy.table :
+  {
+    . = ALIGN(4);
+    __copy_table_start__ = .;
+
+    LONG (LOADADDR(.data))
+    LONG (ADDR(.data))
+    LONG (SIZEOF(.data) / 4)
+
+    /* Add each additional data section here */
+/*
+    LONG (LOADADDR(.data2))
+    LONG (ADDR(.data2))
+    LONG (SIZEOF(.data2) / 4)
+*/
+    __copy_table_end__ = .;
+  } > ROM0
+
+  .zero.table :
+  {
+    . = ALIGN(4);
+    __zero_table_start__ = .;
+
+/*  .bss initialization to zero is already done during C Run-Time Startup.
+    LONG (ADDR(.bss))
+    LONG (SIZEOF(.bss) / 4)
+*/
+
+    /* Add each additional bss section here */
+/*
+    LONG (ADDR(.bss2))
+    LONG (SIZEOF(.bss2) / 4)
+*/
+    __zero_table_end__ = .;
+  } > ROM0
+
+  /*
+   * This __etext variable is kept for backward compatibility with older,
+   * ASM based startup files.
+   */
+  PROVIDE(__etext = LOADADDR(.data));
+
+  .data : ALIGN(4)
+  {
+    __data_start__ = .;
+    *(vtable)
+    *(.data)
+    *(.data.*)
+    *(.rodata*)
+
+    . = ALIGN(4);
+    /* preinit data */
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP(*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+
+    . = ALIGN(4);
+    /* init data */
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP(*(SORT(.init_array.*)))
+    KEEP(*(.init_array))
+    PROVIDE_HIDDEN (__init_array_end = .);
+
+    . = ALIGN(4);
+    /* finit data */
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP(*(SORT(.fini_array.*)))
+    KEEP(*(.fini_array))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    /* All data end */
+    __data_end__ = .;
+
+  } > RAM0 AT > ROM0
+
+  /*
+   * Secondary data section, optional
+   *
+   * Remember to add each additional data section
+   * to the .copy.table above to assure proper
+   * initialization during startup.
+   */
+/*
+  .data2 : ALIGN(4)
+  {
+    . = ALIGN(4);
+    __data2_start__ = .;
+    *(.data2)
+    *(.data2.*)
+    . = ALIGN(4);
+    __data2_end__ = .;
+
+  } > RAM1 AT > ROM0
+*/
+
+  .bss :
+  {
+    . = ALIGN(4);
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss.*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+  } > RAM0 AT > RAM0
+
+  /*
+   * Secondary bss section, optional
+   *
+   * Remember to add each additional bss section
+   * to the .zero.table above to assure proper
+   * initialization during startup.
+   */
+/*
+  .bss2 :
+  {
+    . = ALIGN(4);
+    __bss2_start__ = .;
+    *(.bss2)
+    *(.bss2.*)
+    . = ALIGN(4);
+    __bss2_end__ = .;
+  } > RAM1 AT > RAM1
+*/
+
+  .heap (NOLOAD) :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    . = . + HEAP_SIZE;
+    . = ALIGN(8);
+    __HeapLimit = .;
+  } > RAM0
+
+  .stack (ORIGIN(RAM0) + LENGTH(RAM0) - STACK_SIZE - __STACKSEAL_SIZE) (NOLOAD) :
+  {
+    . = ALIGN(8);
+    __StackLimit = .;
+    . = . + STACK_SIZE;
+    . = ALIGN(8);
+    __StackTop = .;
+  } > RAM0
+  PROVIDE(__stack = __StackTop);
+
+#if __STACKSEAL_SIZE > 0
+  .stackseal (ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE) (NOLOAD) :
+  {
+    . = ALIGN(8);
+    __StackSeal = .;
+    . = . + 8;
+    . = ALIGN(8);
+  } > RAM0
+#endif
+
+  /* Check if data + heap + stack exceeds RAM limit */
+  ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/Testing/cmsis_build/runall.py b/Testing/cmsis_build/runall.py
index 8f7678461..902e51fde 100644
--- a/Testing/cmsis_build/runall.py
+++ b/Testing/cmsis_build/runall.py
@@ -8,11 +8,13 @@
 from os import environ
 
 parser = argparse.ArgumentParser(description='Parse test description')
-parser.add_argument('-avh', nargs='?',type = str, default="C:/Keil_v5/ARM/VHT", help="AVH folder")
+parser.add_argument('-avh', nargs='?',type = str, default="C:/Keil_v5/ARM/avh-fvp/bin/models", help="AVH folder")
 parser.add_argument('-d', action='store_true', help="Debug log")
 parser.add_argument('-n', action='store_true', help="No force rebuild")
 parser.add_argument('-r', action='store_true', help="Raw results only")
 parser.add_argument('-c', action='store_true', help="Display cycles (so passing test are displayed)")
+parser.add_argument('-g', nargs='?',type = str,help="AC6 / CLANG / GCC")
+parser.add_argument('-s', action='store_true', help="Take into account AVH error code")
 
 args = parser.parse_args()
 
@@ -79,17 +81,17 @@ def msg(self):
 # in case of error since the test report is giving
 # all the details. So, there is an option to
 # disable the dump of stderr
-def run(*args,mustPrint=False,dumpStdErr=True):
+def run(*args,mustPrint=False,dumpStdErr=True,withExitCodeCheck=True):
     global ERROR_OCCURED
     global DEBUG
     try:
         if DEBUG:
             print(" ".join(args))
         result=subprocess.run(args,text=True,capture_output=True,timeout=600)
-        if result.returncode !=0 :
+        if withExitCodeCheck and (result.returncode !=0) :
              ERROR_OCCURED = True
              if dumpStdErr:
-                return(Result(result.stderr + "\n\nSTDOUT:\n\n" + result.stdout,error=True))
+                return(Result(result.stderr + f"\n\nSTDOUT (error code = {result.returncode}):\n\n" + result.stdout,error=True))
              else:
                 return(Result(result.stdout,error=True))
 
@@ -108,7 +110,11 @@ def run(*args,mustPrint=False,dumpStdErr=True):
 # Configuration file for AVH core
 configFiles={
     "CS310":"ARM_VHT_Corstone_310_config.txt",
-    "CS300":"ARM_VHT_Corstone_300_config.txt",
+    "CS300":{
+       "AC6":"ARM_VHT_Corstone_300_config_ext.txt",
+       "GCC":"ARM_VHT_Corstone_300_config_ext.txt",
+       "CLANG":"ARM_VHT_Corstone_300_config_ext.txt"
+    },
     "M55":"ARM_VHT_MPS2_M55_config.txt",
     "M33_DSP_FP":"ARM_VHT_MPS2_M33_DSP_FP_config.txt",
     "M7DP":"ARM_VHT_MPS2_M7DP_config.txt",
@@ -132,29 +138,32 @@ def run(*args,mustPrint=False,dumpStdErr=True):
 }
 
 avhWindowsExe={
-    "CS310":"VHT_Corstone_SSE-310.exe",
-    "CS300":"VHT_Corstone_SSE-300_Ethos-U55.exe",
-    "M55":"VHT_MPS2_Cortex-M55.exe",
-    "M33_DSP_FP":"VHT_MPS2_Cortex-M33.exe",
-    "M7DP":"VHT_MPS2_Cortex-M7.exe",
-    "M4FP":"VHT_MPS2_Cortex-M4.exe",
-    "M3":"VHT_MPS2_Cortex-M3.exe",
-    "M23":"VHT_MPS2_Cortex-M23.exe",
-    "M0plus":"VHT_MPS2_Cortex-M0plus.exe",
+    "CS310":"FVP_Corstone_SSE-310_Ethos-U65.exe",
+    "CS300":"FVP_Corstone_SSE-300_Ethos-U55.exe",
+    "M55":"FVP_MPS2_Cortex-M55.exe",
+    "M33_DSP_FP":"FVP_MPS2_Cortex-M33.exe",
+    "M7DP":"FVP_MPS2_Cortex-M7.exe",
+    "M4FP":"FVP_MPS2_Cortex-M4.exe",
+    "M3":"FVP_MPS2_Cortex-M3.exe",
+    "M23":"FVP_MPS2_Cortex-M23.exe",
+    "M0plus":"FVP_MPS2_Cortex-M0plus.exe",
 }
 
 AVHROOT = args.avh
 
 # Run AVH
-def runAVH(build,core):
-    axf="out/test/%s/Release/test.axf" % (build,)
-    elf="out/test/%s/Release/test.elf" % (build,)
+def runAVH(build,core,compiler):
+    axf="cprj/out/test/%s/Release/test.axf" % (build,)
+    elf="cprj/out/test/%s/Release/test.elf" % (build,)
     app = axf 
     if os.path.exists(axf):
         app = axf 
     if os.path.exists(elf):
         app = elf
-    config = os.path.join("configs",configFiles[core])
+    if isinstance(configFiles[core],str):
+       config = os.path.join("configs",configFiles[core])
+    else:
+       config = os.path.join("configs",configFiles[core][compiler])
     
     if AVHROOT:
        avhAttempt = os.path.join(AVHROOT,avhWindowsExe[core])
@@ -169,7 +178,7 @@ def runAVH(build,core):
 
 
     
-    res=run(avh,"-f",config,app)
+    res=run(avh,"-f",config,app,withExitCodeCheck=args.s)
     return(res)
    
 ####################
@@ -193,9 +202,11 @@ def runAVH(build,core):
 
 
 #allSuites=[
-#("DECIMF64","../Output.pickle"),
-#("UnaryTestsF32","../Output.pickle"),
-#("UnaryTestsF16","../Output_f16.pickle"),
+#("MISCF32","../Output.pickle"),
+#("MISCQ31","../Output.pickle"),
+#("SupportTestsF16","../Output_f16.pickle"),
+###("BasicTestsF32","../Output.pickle"),
+##("BasicTestsF16","../Output_f16.pickle"),
 #]
 
 # Solution and build file for all
@@ -203,47 +214,54 @@ def runAVH(build,core):
 # It is a pair : csolution target type and AVH identification
 # AVH identification is used to find the executable
 # and the configuration file
-solutions={
-    'test_ac6.csolution.yml':[
-    #  ("VHT-Corstone-310","CS310"),
+compil_config={
+    'AC6':[
+      ("VHT-Corstone-300","CS300"),
+      ("VHT-Corstone-300-NOMVE","CS300"),
+      ("VHT_M33","M33_DSP_FP"),
+      ("VHT_M7","M7DP"),
+      ("VHT_M7_UNROLLED","M7DP"),
+      ("VHT_M4","M4FP"),
+      ("VHT_M0P","M0plus")
+    ],
+    'GCC':[
+      ("VHT-Corstone-300","CS300"),
+      #("VHT-Corstone-300-NOMVE","CS300"),
+      ("VHT_M33","M33_DSP_FP"),
+      ("VHT_M7","M7DP"),
+      ("VHT_M7_UNROLLED","M7DP"),
+      ("VHT_M4","M4FP"),
+      ("VHT_M0P","M0plus")
+    ],
+    'CLANG':[
       ("VHT-Corstone-300","CS300"),
       ("VHT-Corstone-300-NOMVE","CS300"),
       ("VHT_M33","M33_DSP_FP"),
       ("VHT_M7","M7DP"),
       ("VHT_M7_UNROLLED","M7DP"),
       ("VHT_M4","M4FP"),
-    #  #("VHT_M3","M3"),
-    #  #("VHT_M23","M23"),
       ("VHT_M0P","M0plus")
     ],
-    #'test_gcc.csolution.yml':[
-    #  ("VHT-Corstone-300","CS300"),
-      #("VHT_M55","M55"),
-      ##("VHT_M33","M33_DSP_FP"),
-    #  ("VHT_M7","M7DP"),
-    #  ("VHT_M7_UNROLLED","M7DP"),
-    #  ("VHT_M4","M4FP"),
-      ##("VHT_M3","M3"),
-      ##("VHT_M23","M23"),
-    #  ("VHT_M0P","M0plus")
-    #]
 }
 
-# Override previous solutions for more restricted testing.
-#solutions={
-#    'test_ac6.csolution.yml':[
+#Override previous solutions for more restricted testing.
+#compil_config={
+#    'AC6':[
 #      ("VHT-Corstone-300","CS300"),
-#      #("VHT_M7_UNROLLED","M7DP"),
-#    ]
-#}
-#
-#solutions={
-#    'test_gcc.csolution.yml':[
+#      ("VHT_M33","M33_DSP_FP"),
+#    ],
+#    'GCC':[
 #      ("VHT-Corstone-300","CS300"),
-#      #("VHT_M7_UNROLLED","M7DP"),
+#      ("VHT_M33","M33_DSP_FP"),
+#    ],
+#    'CLANG':[
+#      ("VHT-Corstone-300","CS300"),
+#      ("VHT_M33","M33_DSP_FP"),
 #    ]
 #}
 
+
+
 HTMLHEADER="""<html>
 <header>
 <title>CMSIS-DSP Test summary</title>
@@ -255,86 +273,93 @@ def runAVH(build,core):
 </body></html>
 """
 
+compilers = ["AC6", "CLANG", "GCC"]
+
+if args.g:
+    compilers=[args.g]
+
+
 # Run the tests and log the result
 # in a summary.html file
-with open("summary.html","w") as f:
+
+if len(compilers)>1:
+   results_file = "summary.html" 
+else:
+   results_file = f"summary_{compilers[0]}.html" 
+
+with open(results_file,"w") as f:
     print(HTMLHEADER,file=f)
-    for s in solutions:
-        printTitle("Process solution %s" % s)
-        res=run("csolution","convert","-s",s)
-        if res.error:
-            printError("Error csolution")
-            print("<p><font color=\"red\">Error converting csolution %s</font></p><PRE>" % s,file=f)
-            print(res.msg,file=f)
-            print("</PRE>",file=f)
-            continue
-        print("<h1>Solution %s</h1>" % s,file=f)
-        maxNbBuilds=len(solutions[s])
-        buildNb=0
-        for build,core in solutions[s]:
-            buildNb = buildNb + 1
-            print("<h2>Core %s</h2>" % build,file=f)
-            printTitle("Process core %s (%d/%d)" % (build,buildNb,maxNbBuilds))
-            buildFile="test.Release+%s.cprj" % build
-            nb = 0 
-            maxNb = len(allSuites)
-            for s,pickle in allSuites:
-                nb = nb + 1
-                printSubTitle("Process suite %s (%d/%d)" % (s,nb,maxNb))
-                res=run(sys.executable,"../processTests.py","-gen","..","-p","../Patterns","-d","../Parameters","-f",pickle,"-e",s,mustPrint=True)
-                if res.error:
-                    printError("Error processTests")
-                    print("<p><font color=\"red\">Error generating %s</font></p><PRE>" % s,file=f)
-                    print(res.msg,file=f)
-                    print("</PRE>",file=f)
-                    continue
-                if nb==1:
-                   # -r is needed for first
-                   # build when we switch
-                   # between different solutions
-                   # (Like one using AC6 and the other
-                   # using gcc)
-                   if args.n:
-                      res=run("cbuild",buildFile)
-                   else:
-                      res=run("cbuild","-r",buildFile)
-                else:
-                   res=run("cbuild",buildFile)
-                if res.error:
-                    printError("Error cbuild")
-                    print("<p><font color=\"red\">Error building %s</font></p><PRE>" % s,file=f)
-                    print(res.msg,file=f)
-                    print("</PRE>",file=f)
-                    continue
-                printSubTitle("Run AVH")
-                res=runAVH(build,core)
-                if res.error:
-                    printError("Error running AVH")
-                    print("<p><font color=\"red\">Error running %s</font></p><PRE>" % s,file=f)
-                    print(res.msg,file=f)
-                    print("</PRE>",file=f)
-                    continue
-                else:
-                    with open("results.txt","w") as o:
-                        print(res.msg,file=o)
-                    # Dump raw result
-                    if args.r:
-                        print(res.msg)
-                # If raw result, no post processing
-                if not args.r:
-                    res=run(sys.executable,"../processResult.py","-f",pickle,"-e","-ahtml","-r","results.txt",dumpStdErr=False)
+    for comp_nb,compiler in enumerate(compilers):
+        if compiler in compil_config:
+            solutions = compil_config[compiler]
+            printTitle("Process compiler %s (%d / %d)" % (compiler,comp_nb+1,len(compilers)))
+            print("<h1>Compiler %s</h1>" % compiler,file=f)
+            maxNbBuilds=len(solutions)
+            buildNb=0
+            for build,core in solutions:
+                buildNb = buildNb + 1
+                print("<h2>Core %s</h2>" % build,file=f)
+                printTitle("Process core %s (%d/%d)" % (build,buildNb,maxNbBuilds))
+                buildFile="test.Release+%s" % build
+                nb = 0 
+                maxNb = len(allSuites)
+                for s,pickle in allSuites:
+                    nb = nb + 1
+                    printSubTitle("Process suite %s (%d/%d)" % (s,nb,maxNb))
+                    res=run(sys.executable,"../processTests.py","-gen","..","-p","../Patterns","-d","../Parameters","-f",pickle,"-e",s,mustPrint=True)
+                    if res.error:
+                        printError("Error processTests")
+                        print("<p><font color=\"red\">Error generating %s</font></p><PRE>" % s,file=f)
+                        print(res.msg,file=f)
+                        print("</PRE>",file=f)
+                        continue
+                    if nb==1:
+                       # -r is needed for first
+                       # build when we switch
+                       # between different solutions
+                       # (Like one using AC6 and the other
+                       # using gcc)
+                       if args.n:
+                          res=run("cbuild","-O", "cprj","test.csolution.yml","-c",buildFile,"--toolchain",compiler)
+                       else:
+                          res=run("cbuild","-O", "cprj","test.csolution.yml","-r","--update-rte","-c",buildFile,"--toolchain",compiler)
+                    else:
+                       res=run("cbuild","-O", "cprj","test.csolution.yml","-c",buildFile,"--toolchain",compiler)
+                    if res.error:
+                        printError("Error cbuild")
+                        print("<p><font color=\"red\">Error building %s</font></p><PRE>" % s,file=f)
+                        print(res.msg,file=f)
+                        print("</PRE>",file=f)
+                        continue
+                    printSubTitle("Run AVH")
+                    res=runAVH(build,core,compiler)
                     if res.error:
-                        printError("Error processResult")
-                        print("<p><font color=\"red\">Error processing %s result</font></p><PRE>" % s,file=f)
+                        printError("Error running AVH")
+                        print("<p><font color=\"red\">Error running %s</font></p><PRE>" % s,file=f)
                         print(res.msg,file=f)
                         print("</PRE>",file=f)
                         continue
                     else:
-                        # When no error the section is 
-                        # included in final file on when 
-                        # cycles are requested
-                        if args.c:
-                           print(res.msg,file=f)
+                        with open("results.txt","w") as o:
+                            print(res.msg,file=o)
+                        # Dump raw result
+                        if args.r:
+                            print(res.msg)
+                    # If raw result, no post processing
+                    if not args.r:
+                        res=run(sys.executable,"../processResult.py","-f",pickle,"-e","-ahtml","-r","results.txt",dumpStdErr=False)
+                        if res.error:
+                            printError("Error processResult")
+                            print("<p><font color=\"red\">Error processing %s result</font></p><PRE>" % s,file=f)
+                            print(res.msg,file=f)
+                            print("</PRE>",file=f)
+                            continue
+                        else:
+                            # When no error the section is 
+                            # included in final file on when 
+                            # cycles are requested
+                            if args.c:
+                               print(res.msg,file=f)
     print(HTMLFOOTER,file=f)
 
 if not GHACTION:
diff --git a/Testing/cmsis_build/test.Release+FVP_A5Neon.cprj b/Testing/cmsis_build/test.Release+FVP_A5Neon.cprj
deleted file mode 100644
index d06c123f5..000000000
--- a/Testing/cmsis_build/test.Release+FVP_A5Neon.cprj
+++ /dev/null
@@ -1,194 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<cprj schemaVersion="1.0.1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="CPRJ.xsd">
-  <created timestamp="2022-11-08T10:36:33" tool="csolution 1.1.0"/>
-
-  <info isLayer="false">
-    <description>Automatically generated project</description>
-  </info>
-
-  <packages>
-    <package name="CMSIS" vendor="ARM" version="5.9.0:5.9.0"/>
-  </packages>
-
-  <compilers>
-    <compiler name="GCC" version="11.2.1"/>
-  </compilers>
-
-  <target Dfpu="DP_FPU" Dname="ARMCA5" Dsecure="Non-secure" Dvendor="ARM:82">
-    <output intdir="tmp/test/FVP_A5Neon/Release" name="test.Release+FVP_A5Neon" outdir="out/test/FVP_A5Neon/Release" rtedir="RTE" type="exe"/>
-    <asflags add="-masm=auto" compiler="GCC"/>
-    <cflags add="-ffunction-sections -mfp16-format=ieee -fdata-sections -std=c11 -Ofast -ffast-math  -flax-vector-conversions" compiler="GCC"/>
-    <cxxflags add="-ffunction-sections -mfp16-format=ieee -fdata-sections  -std=c++11 -Ofast -ffast-math  -flax-vector-conversions -Wno-unused-parameter" compiler="GCC"/>
-    <ldflags add="--specs=nano.specs --specs=rdimon.specs --entry=Reset_Handler -Wl,--gc-sections" compiler="GCC"/>
-    <defines>EMBEDDED;NORMALFVP;CORTEXA</defines>
-    <includes>../../Include;../../PrivateInclude;../FrameworkInclude;../GeneratedInclude;../Include/Tests</includes>
-  </target>
-
-  <components>
-    <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="1.2.1"/>
-    <component Cclass="Device" Cgroup="IRQ Controller" Csub="GIC" Cvendor="ARM" Cversion="1.0.1"/>
-    <component Cclass="Device" Cgroup="OS Tick" Csub="Private Timer" Cvendor="ARM" Cversion="1.0.2"/>
-    <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1">
-      <file attr="config" category="header" name="Device/ARM/ARMCA5/Config/mem_ARMCA5.h" version="1.1.0"/>
-      <file attr="config" category="header" name="Device/ARM/ARMCA5/Config/system_ARMCA5.h" version="1.0.0"/>
-      <file attr="config" category="other" name="Device/ARM/ARMCA5/Source/GCC/ARMCA5.ld" version="1.0.0"/>
-      <file attr="config" category="sourceC" name="Device/ARM/ARMCA5/Source/GCC/startup_ARMCA5.c" version="1.0.1"/>
-      <file attr="config" category="sourceC" name="Device/ARM/ARMCA5/Source/mmu_ARMCA5.c" version="1.2.0"/>
-      <file attr="config" category="sourceC" name="Device/ARM/ARMCA5/Source/system_ARMCA5.c" version="1.0.1"/>
-    </component>
-  </components>
-
-  <files>
-    <group name="App">
-      <file category="sourceCpp" name="../main.cpp"/>
-      <file category="sourceC" name="../patterndata.c"/>
-      <file category="sourceCpp" name="../testmain.cpp"/>
-    </group>
-    <group name="TestFramework">
-      <file category="sourceCpp" name="../FrameworkSource/ArrayMemory.cpp"/>
-      <file category="sourceCpp" name="../FrameworkSource/Calibrate.cpp"/>
-      <file category="sourceCpp" name="../FrameworkSource/Error.cpp"/>
-      <file category="sourceCpp" name="../FrameworkSource/FPGA.cpp"/>
-      <file category="sourceCpp" name="../FrameworkSource/Generators.cpp"/>
-      <file category="sourceCpp" name="../FrameworkSource/IORunner.cpp"/>
-      <file category="sourceCpp" name="../FrameworkSource/Pattern.cpp"/>
-      <file category="sourceCpp" name="../FrameworkSource/PatternMgr.cpp"/>
-      <file category="sourceCpp" name="../FrameworkSource/Test.cpp"/>
-      <file category="sourceCpp" name="../FrameworkSource/Timing.cpp"/>
-    </group>
-    <group name="GeneratedConfig">
-      <file category="sourceCpp" name="../GeneratedSource/TestDesc.cpp"/>
-    </group>
-    <group name="Tests">
-      <file category="sourceCpp" name="../Source/Tests/BasicTestsF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BasicTestsF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BasicTestsF64.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BasicTestsQ7.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BasicTestsQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BasicTestsQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BayesF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BayesF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BinaryTestsF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BinaryTestsF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BinaryTestsF64.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BinaryTestsQ7.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BinaryTestsQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BinaryTestsQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BIQUADF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BIQUADF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BIQUADF64.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BIQUADQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BIQUADQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/ComplexTestsF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/ComplexTestsF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/ComplexTestsF64.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/ComplexTestsQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/ComplexTestsQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/DECIMF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/DECIMQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/DECIMQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/DistanceTestsF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/DistanceTestsF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/DistanceTestsF64.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/DistanceTestsU32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/ExampleCategoryF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/ExampleCategoryQ7.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/ExampleCategoryQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/ExampleCategoryQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/FastMathF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/FastMathF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/FastMathF64.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/FastMathQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/FastMathQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/FastMathQ63.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/FIRF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/FIRF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/FIRF64.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/FIRQ7.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/FIRQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/FIRQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/InterpolationTestsF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/InterpolationTestsF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/InterpolationTestsQ7.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/InterpolationTestsQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/InterpolationTestsQ31.cpp"/>
-      <file category="sourceC" name="../Source/Tests/mfccdata.c"/>
-      <file category="sourceC" name="../Source/Tests/mfccdata_f16.c"/>
-      <file category="sourceCpp" name="../Source/Tests/MFCCF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/MFCCF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/MFCCQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/MFCCQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/MISCF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/MISCF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/MISCF64.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/MISCQ7.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/MISCQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/MISCQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/QuaternionTestsF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/StatsTestsF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/StatsTestsF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/StatsTestsF64.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/StatsTestsQ7.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/StatsTestsQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/StatsTestsQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/SupportBarTestsF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/SupportBarTestsF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/SupportTestsF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/SupportTestsF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/SupportTestsF64.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/SupportTestsQ7.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/SupportTestsQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/SupportTestsQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/SVMF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/SVMF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/TransformCF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/TransformCF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/TransformCF64.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/TransformCQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/TransformCQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/TransformRF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/TransformRF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/TransformRF64.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/TransformRQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/TransformRQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/UnaryTestsF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/UnaryTestsF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/UnaryTestsF64.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/UnaryTestsQ7.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/UnaryTestsQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/UnaryTestsQ31.cpp"/>
-    </group>
-    <group name="CMSIS-DSP">
-      <defines>ARM_MATH_ROUNDING</defines>
-      <file category="sourceC" name="../../Source/BasicMathFunctions/BasicMathFunctions.c"/>
-      <file category="sourceC" name="../../Source/BasicMathFunctions/BasicMathFunctionsF16.c"/>
-      <file category="sourceC" name="../../Source/DistanceFunctions/DistanceFunctions.c"/>
-      <file category="sourceC" name="../../Source/DistanceFunctions/DistanceFunctionsF16.c"/>
-      <file category="sourceC" name="../../Source/MatrixFunctions/MatrixFunctions.c"/>
-      <file category="sourceC" name="../../Source/MatrixFunctions/MatrixFunctionsF16.c"/>
-      <file category="sourceC" name="../../Source/BayesFunctions/BayesFunctions.c"/>
-      <file category="sourceC" name="../../Source/BayesFunctions/BayesFunctionsF16.c"/>
-      <file category="sourceC" name="../../Source/FastMathFunctions/FastMathFunctions.c"/>
-      <file category="sourceC" name="../../Source/FastMathFunctions/FastMathFunctionsF16.c"/>
-      <file category="sourceC" name="../../Source/QuaternionMathFunctions/QuaternionMathFunctions.c"/>
-      <file category="sourceC" name="../../Source/StatisticsFunctions/StatisticsFunctions.c"/>
-      <file category="sourceC" name="../../Source/StatisticsFunctions/StatisticsFunctionsF16.c"/>
-      <file category="sourceC" name="../../Source/CommonTables/CommonTables.c"/>
-      <file category="sourceC" name="../../Source/CommonTables/CommonTablesF16.c"/>
-      <file category="sourceC" name="../../Source/FilteringFunctions/FilteringFunctions.c"/>
-      <file category="sourceC" name="../../Source/FilteringFunctions/FilteringFunctionsF16.c"/>
-      <file category="sourceC" name="../../Source/SupportFunctions/SupportFunctions.c"/>
-      <file category="sourceC" name="../../Source/SupportFunctions/SupportFunctionsF16.c"/>
-      <file category="sourceC" name="../../Source/ComplexMathFunctions/ComplexMathFunctions.c"/>
-      <file category="sourceC" name="../../Source/ComplexMathFunctions/ComplexMathFunctionsF16.c"/>
-      <file category="sourceC" name="../../Source/SVMFunctions/SVMFunctions.c"/>
-      <file category="sourceC" name="../../Source/SVMFunctions/SVMFunctionsF16.c"/>
-      <file category="sourceC" name="../../Source/InterpolationFunctions/InterpolationFunctions.c"/>
-      <file category="sourceC" name="../../Source/InterpolationFunctions/InterpolationFunctionsF16.c"/>
-      <file category="sourceC" name="../../Source/TransformFunctions/TransformFunctions.c"/>
-      <file category="sourceC" name="../../Source/TransformFunctions/TransformFunctionsF16.c"/>
-      <file category="sourceC" name="../../Source/ControllerFunctions/ControllerFunctions.c"/>
-    </group>
-  </files>
-</cprj>
-
diff --git a/Testing/cmsis_build/test.Release+FVP_A7Neon.cprj b/Testing/cmsis_build/test.Release+FVP_A7Neon.cprj
deleted file mode 100644
index 2ce051c01..000000000
--- a/Testing/cmsis_build/test.Release+FVP_A7Neon.cprj
+++ /dev/null
@@ -1,194 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<cprj schemaVersion="1.0.1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="CPRJ.xsd">
-  <created timestamp="2022-11-08T10:36:33" tool="csolution 1.1.0"/>
-
-  <info isLayer="false">
-    <description>Automatically generated project</description>
-  </info>
-
-  <packages>
-    <package name="CMSIS" vendor="ARM" version="5.9.0:5.9.0"/>
-  </packages>
-
-  <compilers>
-    <compiler name="GCC" version="11.2.1"/>
-  </compilers>
-
-  <target Dfpu="DP_FPU" Dname="ARMCA7" Dsecure="Non-secure" Dvendor="ARM:82">
-    <output intdir="tmp/test/FVP_A7Neon/Release" name="test.Release+FVP_A7Neon" outdir="out/test/FVP_A7Neon/Release" rtedir="RTE" type="exe"/>
-    <asflags add="-masm=auto" compiler="GCC"/>
-    <cflags add="-ffunction-sections -mfp16-format=ieee -fdata-sections -std=c11 -Ofast -ffast-math  -flax-vector-conversions" compiler="GCC"/>
-    <cxxflags add="-ffunction-sections -mfp16-format=ieee -fdata-sections  -std=c++11 -Ofast -ffast-math  -flax-vector-conversions -Wno-unused-parameter" compiler="GCC"/>
-    <ldflags add="--specs=nano.specs --specs=rdimon.specs --entry=Reset_Handler -Wl,--gc-sections" compiler="GCC"/>
-    <defines>EMBEDDED;NORMALFVP;CORTEXA</defines>
-    <includes>../../Include;../../PrivateInclude;../FrameworkInclude;../GeneratedInclude;../Include/Tests</includes>
-  </target>
-
-  <components>
-    <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="1.2.1"/>
-    <component Cclass="Device" Cgroup="IRQ Controller" Csub="GIC" Cvendor="ARM" Cversion="1.0.1"/>
-    <component Cclass="Device" Cgroup="OS Tick" Csub="Generic Physical Timer" Cvendor="ARM" Cversion="1.0.1"/>
-    <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1">
-      <file attr="config" category="header" name="Device/ARM/ARMCA7/Config/mem_ARMCA7.h" version="1.1.0"/>
-      <file attr="config" category="header" name="Device/ARM/ARMCA7/Config/system_ARMCA7.h" version="1.0.0"/>
-      <file attr="config" category="other" name="Device/ARM/ARMCA7/Source/GCC/ARMCA7.ld" version="1.0.0"/>
-      <file attr="config" category="sourceC" name="Device/ARM/ARMCA7/Source/GCC/startup_ARMCA7.c" version="1.0.1"/>
-      <file attr="config" category="sourceC" name="Device/ARM/ARMCA7/Source/mmu_ARMCA7.c" version="1.2.0"/>
-      <file attr="config" category="sourceC" name="Device/ARM/ARMCA7/Source/system_ARMCA7.c" version="1.0.1"/>
-    </component>
-  </components>
-
-  <files>
-    <group name="App">
-      <file category="sourceCpp" name="../main.cpp"/>
-      <file category="sourceC" name="../patterndata.c"/>
-      <file category="sourceCpp" name="../testmain.cpp"/>
-    </group>
-    <group name="TestFramework">
-      <file category="sourceCpp" name="../FrameworkSource/ArrayMemory.cpp"/>
-      <file category="sourceCpp" name="../FrameworkSource/Calibrate.cpp"/>
-      <file category="sourceCpp" name="../FrameworkSource/Error.cpp"/>
-      <file category="sourceCpp" name="../FrameworkSource/FPGA.cpp"/>
-      <file category="sourceCpp" name="../FrameworkSource/Generators.cpp"/>
-      <file category="sourceCpp" name="../FrameworkSource/IORunner.cpp"/>
-      <file category="sourceCpp" name="../FrameworkSource/Pattern.cpp"/>
-      <file category="sourceCpp" name="../FrameworkSource/PatternMgr.cpp"/>
-      <file category="sourceCpp" name="../FrameworkSource/Test.cpp"/>
-      <file category="sourceCpp" name="../FrameworkSource/Timing.cpp"/>
-    </group>
-    <group name="GeneratedConfig">
-      <file category="sourceCpp" name="../GeneratedSource/TestDesc.cpp"/>
-    </group>
-    <group name="Tests">
-      <file category="sourceCpp" name="../Source/Tests/BasicTestsF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BasicTestsF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BasicTestsF64.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BasicTestsQ7.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BasicTestsQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BasicTestsQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BayesF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BayesF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BinaryTestsF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BinaryTestsF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BinaryTestsF64.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BinaryTestsQ7.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BinaryTestsQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BinaryTestsQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BIQUADF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BIQUADF32.cpp"/>
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-      <file category="sourceCpp" name="../Source/Tests/FIRQ7.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/FIRQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/FIRQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/InterpolationTestsF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/InterpolationTestsF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/InterpolationTestsQ7.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/InterpolationTestsQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/InterpolationTestsQ31.cpp"/>
-      <file category="sourceC" name="../Source/Tests/mfccdata.c"/>
-      <file category="sourceC" name="../Source/Tests/mfccdata_f16.c"/>
-      <file category="sourceCpp" name="../Source/Tests/MFCCF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/MFCCF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/MFCCQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/MFCCQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/MISCF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/MISCF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/MISCF64.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/MISCQ7.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/MISCQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/MISCQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/QuaternionTestsF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/StatsTestsF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/StatsTestsF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/StatsTestsF64.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/StatsTestsQ7.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/StatsTestsQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/StatsTestsQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/SupportBarTestsF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/SupportBarTestsF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/SupportTestsF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/SupportTestsF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/SupportTestsF64.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/SupportTestsQ7.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/SupportTestsQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/SupportTestsQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/SVMF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/SVMF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/TransformCF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/TransformCF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/TransformCF64.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/TransformCQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/TransformCQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/TransformRF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/TransformRF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/TransformRF64.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/TransformRQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/TransformRQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/UnaryTestsF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/UnaryTestsF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/UnaryTestsF64.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/UnaryTestsQ7.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/UnaryTestsQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/UnaryTestsQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/WindowTestsF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/WindowTestsF64.cpp"/>
-    </group>
-    <group name="CMSIS-DSP">
-      <defines>ARM_MATH_ROUNDING</defines>
-      <file category="sourceC" name="../../Source/BasicMathFunctions/BasicMathFunctions.c"/>
-      <file category="sourceC" name="../../Source/BasicMathFunctions/BasicMathFunctionsF16.c"/>
-      <file category="sourceC" name="../../Source/DistanceFunctions/DistanceFunctions.c"/>
-      <file category="sourceC" name="../../Source/DistanceFunctions/DistanceFunctionsF16.c"/>
-      <file category="sourceC" name="../../Source/MatrixFunctions/MatrixFunctions.c"/>
-      <file category="sourceC" name="../../Source/MatrixFunctions/MatrixFunctionsF16.c"/>
-      <file category="sourceC" name="../../Source/BayesFunctions/BayesFunctions.c"/>
-      <file category="sourceC" name="../../Source/BayesFunctions/BayesFunctionsF16.c"/>
-      <file category="sourceC" name="../../Source/FastMathFunctions/FastMathFunctions.c"/>
-      <file category="sourceC" name="../../Source/FastMathFunctions/FastMathFunctionsF16.c"/>
-      <file category="sourceC" name="../../Source/QuaternionMathFunctions/QuaternionMathFunctions.c"/>
-      <file category="sourceC" name="../../Source/StatisticsFunctions/StatisticsFunctions.c"/>
-      <file category="sourceC" name="../../Source/StatisticsFunctions/StatisticsFunctionsF16.c"/>
-      <file category="sourceC" name="../../Source/CommonTables/CommonTables.c"/>
-      <file category="sourceC" name="../../Source/CommonTables/CommonTablesF16.c"/>
-      <file category="sourceC" name="../../Source/FilteringFunctions/FilteringFunctions.c"/>
-      <file category="sourceC" name="../../Source/FilteringFunctions/FilteringFunctionsF16.c"/>
-      <file category="sourceC" name="../../Source/SupportFunctions/SupportFunctions.c"/>
-      <file category="sourceC" name="../../Source/SupportFunctions/SupportFunctionsF16.c"/>
-      <file category="sourceC" name="../../Source/ComplexMathFunctions/ComplexMathFunctions.c"/>
-      <file category="sourceC" name="../../Source/ComplexMathFunctions/ComplexMathFunctionsF16.c"/>
-      <file category="sourceC" name="../../Source/SVMFunctions/SVMFunctions.c"/>
-      <file category="sourceC" name="../../Source/SVMFunctions/SVMFunctionsF16.c"/>
-      <file category="sourceC" name="../../Source/InterpolationFunctions/InterpolationFunctions.c"/>
-      <file category="sourceC" name="../../Source/InterpolationFunctions/InterpolationFunctionsF16.c"/>
-      <file category="sourceC" name="../../Source/TransformFunctions/TransformFunctions.c"/>
-      <file category="sourceC" name="../../Source/TransformFunctions/TransformFunctionsF16.c"/>
-      <file category="sourceC" name="../../Source/ControllerFunctions/ControllerFunctions.c"/>
-      <file category="sourceC" name="../../Source/WindowFunctions/WindowFunctions.c"/>
-    </group>
-  </files>
-</cprj>
-
diff --git a/Testing/cmsis_build/test.Release+VHT_M7_UNROLLED.cprj b/Testing/cmsis_build/test.Release+VHT_M7_UNROLLED.cprj
deleted file mode 100644
index e3549869c..000000000
--- a/Testing/cmsis_build/test.Release+VHT_M7_UNROLLED.cprj
+++ /dev/null
@@ -1,193 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<cprj schemaVersion="2.0.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="CPRJ.xsd">
-  <created timestamp="2024-06-11T16:26:20" tool="csolution 2.4.0"/>
-
-  <info isLayer="false">
-    <description>Automatically generated project</description>
-  </info>
-
-  <packages>
-    <package name="CMSIS" vendor="ARM" version="5.9.0:5.9.0"/>
-  </packages>
-
-  <compilers>
-    <compiler name="AC6" version="6.22.0:6.22.0"/>
-  </compilers>
-
-  <target Dfpu="DP_FPU" Dname="ARMCM7_DP" Dvendor="ARM:82">
-    <output elf="test.axf" intdir="tmp/test/VHT_M7_UNROLLED/Release" name="test" outdir="out/test/VHT_M7_UNROLLED/Release" rtedir="RTE" type="exe"/>
-    <options debug="on"/>
-    <asflags add="-masm=auto" compiler="AC6"/>
-    <cflags add="-Wsign-compare -Wdouble-promotion -DNDEBUG -Wall -Wextra -Werror -std=c11 -Ofast -ffast-math -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier" compiler="AC6"/>
-    <cxxflags add="-fno-rtti -DNDEBUG -Wall -Wextra -std=c++11 -Ofast -ffast-math" compiler="AC6"/>
-    <ldflags add="--entry=Reset_Handler --info=summarysizes --info=sizes --info=totals --info=unused --info=veneers" compiler="AC6" file="RTE/Device/ARMCM7_DP/ARMCM7_ac6.sct"/>
-    <defines>EMBEDDED;CORTEXM;ARM_MATH_LOOPUNROLL;ARMCM7_DP</defines>
-    <includes>../../Include;../../PrivateInclude;../FrameworkInclude;../GeneratedInclude;../Include/Tests</includes>
-  </target>
-
-  <components>
-    <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.6.0"/>
-    <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.0.3" rtedir="RTE">
-      <file attr="config" category="linkerScript" name="Device/ARM/ARMCM7/Source/ARM/ARMCM7_ac6.sct" version="1.0.0"/>
-      <file attr="config" category="sourceC" name="Device/ARM/ARMCM7/Source/startup_ARMCM7.c" version="2.0.3"/>
-      <file attr="config" category="sourceC" name="Device/ARM/ARMCM7/Source/system_ARMCM7.c" version="1.0.1"/>
-    </component>
-  </components>
-
-  <files>
-    <group name="App">
-      <file category="sourceCpp" name="../main.cpp"/>
-      <file category="sourceC" name="../patterndata.c"/>
-      <file category="sourceCpp" name="../testmain.cpp"/>
-    </group>
-    <group name="TestFramework">
-      <file category="sourceCpp" name="../FrameworkSource/ArrayMemory.cpp"/>
-      <file category="sourceCpp" name="../FrameworkSource/Calibrate.cpp"/>
-      <file category="sourceCpp" name="../FrameworkSource/Error.cpp"/>
-      <file category="sourceCpp" name="../FrameworkSource/FPGA.cpp"/>
-      <file category="sourceCpp" name="../FrameworkSource/Generators.cpp"/>
-      <file category="sourceCpp" name="../FrameworkSource/IORunner.cpp"/>
-      <file category="sourceCpp" name="../FrameworkSource/Pattern.cpp"/>
-      <file category="sourceCpp" name="../FrameworkSource/PatternMgr.cpp"/>
-      <file category="sourceCpp" name="../FrameworkSource/Test.cpp"/>
-      <file category="sourceCpp" name="../FrameworkSource/Timing.cpp"/>
-    </group>
-    <group name="GeneratedConfig">
-      <file category="sourceCpp" name="../GeneratedSource/TestDesc.cpp"/>
-    </group>
-    <group name="Tests">
-      <file category="sourceCpp" name="../Source/Tests/BasicTestsF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BasicTestsF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BasicTestsF64.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BasicTestsQ7.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BasicTestsQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BasicTestsQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BayesF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BayesF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BinaryTestsF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BinaryTestsF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BinaryTestsF64.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BinaryTestsQ7.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BinaryTestsQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BinaryTestsQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BIQUADF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BIQUADF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BIQUADF64.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BIQUADQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/BIQUADQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/ComplexTestsF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/ComplexTestsF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/ComplexTestsF64.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/ComplexTestsQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/ComplexTestsQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/DECIMF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/DECIMQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/DECIMQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/DistanceTestsF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/DistanceTestsF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/DistanceTestsF64.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/DistanceTestsU32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/ExampleCategoryF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/ExampleCategoryQ7.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/ExampleCategoryQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/ExampleCategoryQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/FastMathF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/FastMathF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/FastMathF64.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/FastMathQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/FastMathQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/FastMathQ63.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/FIRF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/FIRF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/FIRF64.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/FIRQ7.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/FIRQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/FIRQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/InterpolationTestsF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/InterpolationTestsF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/InterpolationTestsQ7.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/InterpolationTestsQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/InterpolationTestsQ31.cpp"/>
-      <file category="sourceC" name="../Source/Tests/mfccdata.c"/>
-      <file category="sourceC" name="../Source/Tests/mfccdata_f16.c"/>
-      <file category="sourceCpp" name="../Source/Tests/MFCCF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/MFCCF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/MFCCQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/MFCCQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/MISCF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/MISCF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/MISCF64.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/MISCQ7.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/MISCQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/MISCQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/QuaternionTestsF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/StatsTestsF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/StatsTestsF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/StatsTestsF64.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/StatsTestsQ7.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/StatsTestsQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/StatsTestsQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/SupportBarTestsF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/SupportBarTestsF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/SupportTestsF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/SupportTestsF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/SupportTestsF64.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/SupportTestsQ7.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/SupportTestsQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/SupportTestsQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/SVMF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/SVMF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/TransformCF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/TransformCF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/TransformCF64.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/TransformCQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/TransformCQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/TransformRF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/TransformRF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/TransformRF64.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/TransformRQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/TransformRQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/UnaryTestsF16.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/UnaryTestsF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/UnaryTestsF64.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/UnaryTestsQ7.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/UnaryTestsQ15.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/UnaryTestsQ31.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/WindowTestsF32.cpp"/>
-      <file category="sourceCpp" name="../Source/Tests/WindowTestsF64.cpp"/>
-    </group>
-    <group name="CMSIS-DSP">
-      <defines>ARM_MATH_ROUNDING</defines>
-      <file category="sourceC" name="../../Source/BasicMathFunctions/BasicMathFunctions.c"/>
-      <file category="sourceC" name="../../Source/BasicMathFunctions/BasicMathFunctionsF16.c"/>
-      <file category="sourceC" name="../../Source/DistanceFunctions/DistanceFunctions.c"/>
-      <file category="sourceC" name="../../Source/DistanceFunctions/DistanceFunctionsF16.c"/>
-      <file category="sourceC" name="../../Source/MatrixFunctions/MatrixFunctions.c"/>
-      <file category="sourceC" name="../../Source/MatrixFunctions/MatrixFunctionsF16.c"/>
-      <file category="sourceC" name="../../Source/BayesFunctions/BayesFunctions.c"/>
-      <file category="sourceC" name="../../Source/BayesFunctions/BayesFunctionsF16.c"/>
-      <file category="sourceC" name="../../Source/FastMathFunctions/FastMathFunctions.c"/>
-      <file category="sourceC" name="../../Source/FastMathFunctions/FastMathFunctionsF16.c"/>
-      <file category="sourceC" name="../../Source/QuaternionMathFunctions/QuaternionMathFunctions.c"/>
-      <file category="sourceC" name="../../Source/StatisticsFunctions/StatisticsFunctions.c"/>
-      <file category="sourceC" name="../../Source/StatisticsFunctions/StatisticsFunctionsF16.c"/>
-      <file category="sourceC" name="../../Source/CommonTables/CommonTables.c"/>
-      <file category="sourceC" name="../../Source/CommonTables/CommonTablesF16.c"/>
-      <file category="sourceC" name="../../Source/FilteringFunctions/FilteringFunctions.c"/>
-      <file category="sourceC" name="../../Source/FilteringFunctions/FilteringFunctionsF16.c"/>
-      <file category="sourceC" name="../../Source/SupportFunctions/SupportFunctions.c"/>
-      <file category="sourceC" name="../../Source/SupportFunctions/SupportFunctionsF16.c"/>
-      <file category="sourceC" name="../../Source/ComplexMathFunctions/ComplexMathFunctions.c"/>
-      <file category="sourceC" name="../../Source/ComplexMathFunctions/ComplexMathFunctionsF16.c"/>
-      <file category="sourceC" name="../../Source/SVMFunctions/SVMFunctions.c"/>
-      <file category="sourceC" name="../../Source/SVMFunctions/SVMFunctionsF16.c"/>
-      <file category="sourceC" name="../../Source/InterpolationFunctions/InterpolationFunctions.c"/>
-      <file category="sourceC" name="../../Source/InterpolationFunctions/InterpolationFunctionsF16.c"/>
-      <file category="sourceC" name="../../Source/TransformFunctions/TransformFunctions.c"/>
-      <file category="sourceC" name="../../Source/TransformFunctions/TransformFunctionsF16.c"/>
-      <file category="sourceC" name="../../Source/ControllerFunctions/ControllerFunctions.c"/>
-      <file category="sourceC" name="../../Source/WindowFunctions/WindowFunctions.c"/>
-    </group>
-  </files>
-</cprj>
-
diff --git a/Testing/cmsis_build/test.cbuild-pack.yml b/Testing/cmsis_build/test.cbuild-pack.yml
new file mode 100644
index 000000000..1f7743e36
--- /dev/null
+++ b/Testing/cmsis_build/test.cbuild-pack.yml
@@ -0,0 +1,14 @@
+cbuild-pack:
+  resolved-packs:
+    - resolved-pack: ARM::CMSIS@6.0.0
+      selected-by-pack:
+        - ARM::CMSIS@6.0.0
+    - resolved-pack: ARM::CMSIS-Compiler@2.0.0
+      selected-by-pack:
+        - ARM::CMSIS-Compiler@2.0.0
+    - resolved-pack: ARM::Cortex_DFP@1.0.0
+      selected-by-pack:
+        - ARM::Cortex_DFP@1.0.0
+    - resolved-pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0
+      selected-by-pack:
+        - ARM::V2M_MPS3_SSE_300_BSP@1.4.0
diff --git a/Testing/cmsis_build/test.cproject.yml b/Testing/cmsis_build/test.cproject.yml
index 8cec783d5..cde475bdd 100644
--- a/Testing/cmsis_build/test.cproject.yml
+++ b/Testing/cmsis_build/test.cproject.yml
@@ -1,26 +1,4 @@
 project:
-  setups:
-    - setup: Cortex-A9
-      define:
-        - ARM_MATH_AUTOVECTORIZE
-        - DISABLEFLOAT16
-      for-context: 
-        - +FVP_A9Neon
-
-    - setup: Cortex-A5 or A7
-      define:
-        - ARM_MATH_NEON
-        - DISABLEFLOAT16
-      for-context: 
-        - +FVP_A5Neon
-        - +FVP_A7Neon
-
-    - setup: Any Cortex-M
-      not-for-context: 
-        - +FVP_A5Neon
-        - +FVP_A7Neon
-        - +FVP_A9Neon
-
   groups:
     - group: App
       files:
@@ -144,15 +122,191 @@ project:
         - file: ../Source/Tests/UnaryTestsQ31.cpp
         - file: ../Source/Tests/WindowTestsF32.cpp
         - file: ../Source/Tests/WindowTestsF64.cpp
+  define:
+      - EMBEDDED
+  add-path:
+      - ../FrameworkInclude
+      - ../GeneratedInclude
+      - ../Include/Tests
 
   # A CMSIS-DSP Layer is used to be able to build
   # and test with the current source version
   # without requring to install a CMSIS Pack
   layers:
-    - layer: boot.clayer.yml 
     - layer: dsp.clayer.yml 
     
-
   components:
     - component: ARM::CMSIS:CORE
-    
+    - component: ARM::Device:Startup&C Startup
+    - component: ARM::Device:Definition
+      for-context: 
+          - +VHT-Corstone-300
+          - +MPS3-Corstone-300
+          - +VHT-Corstone-300-NOMVE
+    - component: CMSIS-Compiler:CORE
+      for-context: 
+          - +MPS3-Corstone-300
+    - component: CMSIS-Compiler:STDOUT:Custom@1.0.0
+      for-context: 
+          - +MPS3-Corstone-300
+    - component: ARM::Device:USART STDOUT
+      for-context: 
+          - +MPS3-Corstone-300
+    - component: ARM::CMSIS Driver:USART
+      for-context: 
+          - +MPS3-Corstone-300
+    - component: ARM::Device:Native Driver:SysCounter
+      for-context: 
+          - +VHT-Corstone-300
+          - +MPS3-Corstone-300
+          - +VHT-Corstone-300-NOMVE
+    - component: ARM::Device:Native Driver:SysTimer
+      for-context: 
+          - +VHT-Corstone-300
+          - +MPS3-Corstone-300
+          - +VHT-Corstone-300-NOMVE
+    - component: ARM::Device:Native Driver:Timeout
+      for-context: 
+          - +VHT-Corstone-300
+          - +MPS3-Corstone-300
+          - +VHT-Corstone-300-NOMVE
+    - component: ARM::Device:Native Driver:UART
+      for-context: 
+          - +MPS3-Corstone-300
+  
+  linker:
+  ######################## SSE300
+    - script: linker_scripts/gcc_sse300_mps3.ld
+      for-context:
+        - +MPS3-Corstone-300
+        - +VHT-Corstone-300
+        - +VHT-Corstone-300-NOMVE
+      for-compiler: GCC
+
+    - script: linker_scripts/clang_sse300_mps3.sct
+      for-context:
+        - +MPS3-Corstone-300
+        - +VHT-Corstone-300
+        - +VHT-Corstone-300-NOMVE
+      for-compiler: CLANG
+
+    - script: linker_scripts/ac6_sse300_mps3_s.sct
+      for-context:
+        - +MPS3-Corstone-300
+        - +VHT-Corstone-300
+        - +VHT-Corstone-300-NOMVE
+      for-compiler: AC6
+
+    - regions: linker_scripts/SSE-300-MPS3/region_defs.h
+      for-context:
+        - +MPS3-Corstone-300
+        - +VHT-Corstone-300
+        - +VHT-Corstone-300-NOMVE
+
+  ######################## M33
+    - script: linker_scripts/gcc_m33_mps3.ld
+      for-context:
+        - +VHT_M33
+      for-compiler: GCC
+
+    - script: linker_scripts/clang_m33_mps3.ld
+      for-context:
+        - +VHT_M33
+      for-compiler: CLANG
+
+    - script: linker_scripts/ac6_m33_mps3_s.sct
+      for-context:
+        - +VHT_M33
+      for-compiler: AC6
+
+    - regions: linker_scripts/ARMCM33_DSP_FP/region_defs.h
+      for-context:
+        - +VHT_M33
+
+  ######################## M7
+    - script: linker_scripts/gcc_m7_mps3.ld
+      for-context:
+        - +VHT_M7_UNROLLED
+        - +VHT_M7
+      for-compiler: GCC
+
+    - script: linker_scripts/clang_m7_mps3.ld
+      for-context:
+        - +VHT_M7_UNROLLED
+        - +VHT_M7
+      for-compiler: CLANG
+
+    - script: linker_scripts/ac6_m7_mps3_s.sct
+      for-context:
+        - +VHT_M7_UNROLLED
+        - +VHT_M7
+      for-compiler: AC6
+
+    - regions: linker_scripts/ARMCM7_DP/region_defs.h
+      for-context:
+        - +VHT_M7_UNROLLED
+        - +VHT_M7
+
+  ######################## M4
+    - script: linker_scripts/gcc_m4_mps3.ld
+      for-context:
+        - +VHT_M4
+      for-compiler: GCC
+
+    - script: linker_scripts/clang_m4_mps3.ld
+      for-context:
+        - +VHT_M4
+      for-compiler: CLANG
+
+    - script: linker_scripts/ac6_m4_mps3_s.sct
+      for-context:
+        - +VHT_M4
+      for-compiler: AC6
+
+    - regions: linker_scripts/ARMCM4/region_defs.h
+      for-context:
+        - +VHT_M4
+
+
+
+  ######################## M3
+    - script: linker_scripts/gcc_m3_mps3.ld
+      for-context:
+        - +VHT_M3
+      for-compiler: GCC
+
+    - script: linker_scripts/clang_m3_mps3.ld
+      for-context:
+        - +VHT_M3
+      for-compiler: CLANG
+
+    - script: linker_scripts/ac6_m3_mps3_s.sct
+      for-context:
+        - +VHT_M3
+      for-compiler: AC6
+
+    - regions: linker_scripts/ARMCM3/region_defs.h
+      for-context:
+        - +VHT_M3
+
+
+  ######################## M0P
+    - script: linker_scripts/gcc_m0p_mps3.ld
+      for-context:
+        - +VHT_M0P
+      for-compiler: GCC
+
+    - script: linker_scripts/clang_m0p_mps3.ld
+      for-context:
+        - +VHT_M0P
+      for-compiler: CLANG
+
+    - script: linker_scripts/ac6_m0p_mps3_s.sct
+      for-context:
+        - +VHT_M0P
+      for-compiler: AC6
+
+    - regions: linker_scripts/ARMCM0P/region_defs.h
+      for-context:
+        - +VHT_M0P
+
diff --git a/Testing/cmsis_build/test.csolution.yml b/Testing/cmsis_build/test.csolution.yml
new file mode 100644
index 000000000..9e0dedfc7
--- /dev/null
+++ b/Testing/cmsis_build/test.csolution.yml
@@ -0,0 +1,202 @@
+solution:
+  compiler: AC6
+
+  language-C: c11
+  language-CPP: c++17
+  cdefault:
+
+  packs:
+    - pack: ARM::CMSIS@6.0.0
+    - pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0
+    - pack: ARM::CMSIS-Compiler@2.0.0
+    - pack: ARM::Cortex_DFP@1.0.0
+
+  target-types:
+    - type: MPS3-Corstone-300
+      device: ARM::SSE-300-MPS3
+      board: ARM::V2M-MPS3-SSE-300-FVP
+      define:
+        - CORTEXM
+        - SSE300MPS3
+        - MPS3
+        - ARMCM55
+      misc:
+        - for-compiler: GCC
+          C:
+            - -Wno-sign-compare
+            - -Wno-unused-parameter
+          CPP:
+            - -Wno-sign-compare
+            - -Wno-unused-parameter
+          Link:
+            - --specs=nosys.specs            
+        - for-compiler: CLANG
+          C:
+            - -Wno-sign-compare
+            - -Wno-unused-parameter
+          CPP:
+            - -Wno-sign-compare
+            - -Wno-unused-parameter
+          Link:
+            - -lcrt0
+
+    - type: VHT-Corstone-300
+      device: ARM::SSE-300-MPS3
+      board: ARM::V2M-MPS3-SSE-300-FVP
+      define:
+        - CORTEXM
+        - ARMCM55
+        - SSE300MPS3
+        - VHT
+      misc:
+        - for-compiler: GCC
+          Link:
+            - --specs=rdimon.specs
+          Library:
+            - -lrdimon
+        - for-compiler: CLANG
+          Link:
+            - -lcrt0-semihost
+            - -lsemihost
+
+    - type: VHT-Corstone-300-NOMVE
+      device: ARM::SSE-300-MPS3
+      board: ARM::V2M-MPS3-SSE-300-FVP
+      define:
+        - CORTEXM
+        - ARMCM55
+        - SSE300MPS3
+        - VHT
+        - ARM_MATH_AUTOVECTORIZE # The pack force MVE so 
+        # we have to disable but autovectorization still generating MVE
+      misc:
+        - for-compiler: AC6
+          C: 
+            - -mcpu=cortex-m55+nomve
+        - for-compiler: GCC
+          C: 
+            - -mcpu=cortex-m55+nomve
+          Link:
+            - --specs=rdimon.specs
+          Library:
+            - -lrdimon
+        - for-compiler: CLANG
+          C: 
+            - -mcpu=cortex-m55+nomve
+          Link:
+            - -lcrt0-semihost
+            - -lsemihost
+
+    - type: VHT_M33
+      device: ARMCM33
+      define:
+        - CORTEXM
+        - ARMCM33
+        - VHT
+      misc:
+        - for-compiler: GCC
+          Link:
+            - --specs=rdimon.specs
+          Library:
+            - -lrdimon
+        - for-compiler: CLANG
+          Link:
+            - -lcrt0-semihost
+            - -lsemihost
+
+    - type: VHT_M7
+      device: ARMCM7
+      define:
+        - CORTEXM
+        - ARMCM7
+        - VHT
+      misc:
+        - for-compiler: GCC
+          Link:
+            - --specs=rdimon.specs
+          Library:
+            - -lrdimon
+        - for-compiler: CLANG
+          Link:
+            - -lcrt0-semihost
+            - -lsemihost
+
+    - type: VHT_M7_UNROLLED
+      device: ARMCM7
+      define:
+        - CORTEXM
+        - ARM_MATH_LOOPUNROLL
+        - ARMCM7_DP
+        - VHT
+      misc:
+        - for-compiler: GCC
+          Link:
+            - --specs=rdimon.specs
+          Library:
+            - -lrdimon
+        - for-compiler: CLANG
+          Link:
+            - -lcrt0-semihost
+            - -lsemihost
+
+    - type: VHT_M4
+      device: ARMCM4
+      define:
+        - CORTEXM
+        - ARMCM4
+        - VHT 
+      misc:
+        - for-compiler: GCC
+          Link:
+            - --specs=rdimon.specs
+          Library:
+            - -lrdimon
+        - for-compiler: CLANG
+          Link:
+            - -lcrt0-semihost
+            - -lsemihost
+
+    - type: VHT_M3
+      device: ARMCM3
+      define:
+        - CORTEXM
+        - ARMCM3
+        - VHT 
+      misc:
+        - for-compiler: GCC
+          Link:
+            - --specs=rdimon.specs
+          Library:
+            - -lrdimon
+        - for-compiler: CLANG
+          Link:
+            - -lcrt0-semihost
+            - -lsemihost
+
+    - type: VHT_M0P
+      device: ARMCM0P
+      define:
+        - CORTEXM
+        - ARMCM0P
+        - VHT
+      misc:
+        - for-compiler: GCC
+          Link:
+            - --specs=rdimon.specs
+          Library:
+            - -lrdimon
+        - for-compiler: CLANG
+          Link:
+            - -lcrt0-semihost
+            - -lsemihost
+
+
+
+  build-types:
+    - type: Release
+      debug: on
+
+
+  projects:
+    - project: ./test.cproject.yml
+    
\ No newline at end of file
diff --git a/Testing/cmsis_build/test_ac6.cbuild-pack.yml b/Testing/cmsis_build/test_ac6.cbuild-pack.yml
deleted file mode 100644
index 208d9ee7c..000000000
--- a/Testing/cmsis_build/test_ac6.cbuild-pack.yml
+++ /dev/null
@@ -1,17 +0,0 @@
-cbuild-pack:
-  resolved-packs:
-    - resolved-pack: ARM::CMSIS@5.9.0
-      selected-by-pack:
-        - ARM::CMSIS@5.9.0
-    - resolved-pack: ARM::DMA350@1.0.0
-      selected-by-pack:
-        - ARM::DMA350@1.0.0
-    - resolved-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
-      selected-by-pack:
-        - ARM::V2M_MPS3_SSE_300_BSP@1.3.0
-    - resolved-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0
-      selected-by-pack:
-        - ARM::V2M_MPS3_SSE_310_BSP@1.3.0
-    - resolved-pack: Keil::ARM_Compiler@1.7.2
-      selected-by-pack:
-        - Keil::ARM_Compiler@1.7.2
diff --git a/Testing/cmsis_build/test_ac6.csolution.yml b/Testing/cmsis_build/test_ac6.csolution.yml
deleted file mode 100644
index a90df4ecc..000000000
--- a/Testing/cmsis_build/test_ac6.csolution.yml
+++ /dev/null
@@ -1,131 +0,0 @@
-solution:
-  compiler: AC6@6.22.0
-  misc:
-    - C:
-      - -Wsign-compare 
-      - -Wdouble-promotion 
-      - -DNDEBUG 
-      - -Wall 
-      - -Wextra  
-      - -Werror
-      - -std=c11 
-      - -Ofast 
-      - -ffast-math
-      - -Wno-packed 
-      - -Wno-missing-variable-declarations 
-      - -Wno-missing-prototypes 
-      - -Wno-missing-noreturn 
-      - -Wno-sign-conversion 
-      - -Wno-nonportable-include-path 
-      - -Wno-reserved-id-macro 
-      - -Wno-unused-macros 
-      - -Wno-documentation-unknown-command 
-      - -Wno-documentation 
-      - -Wno-license-management 
-      - -Wno-parentheses-equality 
-      - -Wno-reserved-identifier
-    - CPP:
-      - -fno-rtti 
-      - -DNDEBUG 
-      - -Wall 
-      - -Wextra  
-      - -std=c++11 
-      - -Ofast 
-      - -ffast-math
-    - ASM:
-      - -masm=auto
-    - Link:
-      - --entry=Reset_Handler
-      - --info=summarysizes
-      - --info=sizes
-      - --info=totals
-      - --info=unused
-      - --info=veneers
-  add-path:
-      - ../FrameworkInclude
-      - ../GeneratedInclude
-      - ../Include/Tests
-  define:
-      - EMBEDDED
-
-  packs:
-    - pack: ARM::CMSIS@5.9.0
-    - pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
-    - pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0
-    - pack: Keil::ARM_Compiler@1.7.2
-    - pack: ARM::DMA350@1.0.0
-
-  target-types:
-    #- type: VHT-Corstone-310
-    #  device: ARM::SSE-310-MPS3_FVP
-    #  board: ARM::V2M-MPS3-SSE-310
-    #  define:
-    #    - CORTEXM
-    #    - SSE310MPS3
-
-    - type: VHT-Corstone-300
-      device: ARM::SSE-300-MPS3
-      board: ARM::V2M-MPS3-SSE-300-FVP 
-      define:
-        - CORTEXM
-        - SSE300MPS3
-
-    - type: VHT-Corstone-300-NOMVE
-      device: ARM::SSE-300-MPS3
-      board: ARM::V2M-MPS3-SSE-300-FVP 
-      misc:
-        - C: 
-          - -mcpu=cortex-m55+nomve
-      define:
-        - CORTEXM
-        - SSE300MPS3
-        - ARM_MATH_AUTOVECTORIZE
-
-    - type: VHT_M33
-      device: ARMCM33_DSP_FP
-      define:
-        - CORTEXM
-        - ARMCM33_DSP_FP
-
-    - type: VHT_M7
-      device: ARMCM7_DP
-      define:
-        - CORTEXM
-        - ARMCM7_DP
-
-    - type: VHT_M7_UNROLLED
-      device: ARMCM7_DP
-      define:
-        - CORTEXM
-        - ARM_MATH_LOOPUNROLL
-        - ARMCM7_DP
-
-    - type: VHT_M4
-      device: ARMCM4_FP
-      define:
-        - CORTEXM
-        - ARMCM4_FP
-
-    - type: VHT_M3
-      device: ARMCM3
-      define:
-        - CORTEXM
-        - ARMCM3
-
-    - type: VHT_M23
-      device: ARMCM23
-      define:
-        - CORTEXM
-
-    - type: VHT_M0P
-      device: ARMCM0P
-      define:
-        - CORTEXM
-        - ARMCM0P
-
-  build-types:
-    - type: Release
-      debug: on
-
-  projects:
-    - project: ./test.cproject.yml
\ No newline at end of file
diff --git a/Testing/cmsis_build/test_gcc.cbuild-pack.yml b/Testing/cmsis_build/test_gcc.cbuild-pack.yml
deleted file mode 100644
index 208d9ee7c..000000000
--- a/Testing/cmsis_build/test_gcc.cbuild-pack.yml
+++ /dev/null
@@ -1,17 +0,0 @@
-cbuild-pack:
-  resolved-packs:
-    - resolved-pack: ARM::CMSIS@5.9.0
-      selected-by-pack:
-        - ARM::CMSIS@5.9.0
-    - resolved-pack: ARM::DMA350@1.0.0
-      selected-by-pack:
-        - ARM::DMA350@1.0.0
-    - resolved-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
-      selected-by-pack:
-        - ARM::V2M_MPS3_SSE_300_BSP@1.3.0
-    - resolved-pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0
-      selected-by-pack:
-        - ARM::V2M_MPS3_SSE_310_BSP@1.3.0
-    - resolved-pack: Keil::ARM_Compiler@1.7.2
-      selected-by-pack:
-        - Keil::ARM_Compiler@1.7.2
diff --git a/Testing/cmsis_build/test_gcc.csolution.yml b/Testing/cmsis_build/test_gcc.csolution.yml
deleted file mode 100644
index 8980c77ae..000000000
--- a/Testing/cmsis_build/test_gcc.csolution.yml
+++ /dev/null
@@ -1,97 +0,0 @@
-solution:
-  compiler: GCC@13.2.1
-  misc:
-    - C:
-      - -ffunction-sections 
-      - -mfp16-format=ieee 
-      - -fdata-sections 
-      - -std=c11 
-      - -Ofast 
-      - -ffast-math  
-      - -flax-vector-conversions
-    - CPP:
-      - -ffunction-sections 
-      - -mfp16-format=ieee 
-      - -fdata-sections  
-      - -std=c++11 
-      - -Ofast 
-      - -ffast-math  
-      - -flax-vector-conversions 
-      - -Wno-unused-parameter
-    - ASM:
-      - -masm=auto
-    - Link:
-      - --specs=nano.specs
-      - --specs=rdimon.specs
-      - --entry=Reset_Handler 
-      - -Wl,--gc-sections
-     
-  add-path:
-      - ../FrameworkInclude
-      - ../GeneratedInclude
-      - ../Include/Tests
-  define:
-      - EMBEDDED
-      - NORMALFVP
-
-  packs:
-    - pack: ARM::CMSIS@5.9.0
-    - pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
-    - pack: ARM::V2M_MPS3_SSE_310_BSP@1.3.0
-    - pack: Keil::ARM_Compiler@1.7.2
-    - pack: ARM::DMA350@1.0.0
-
-  target-types:
-# There is no   gcc support in the pack
-# for Corstone CS300.
-
-    - type: VHT-Corstone-300
-      device: ARM::SSE-300-MPS3
-      board: ARM::V2M-MPS3-SSE-300-FVP 
-      define:
-        - CORTEXM
-        - SSE300MPS3
-
-        
-    - type: VHT_M55
-      device: ARMCM55
-      define:
-        - CORTEXM
-
-    - type: VHT_M33
-      device: ARMCM33_DSP_FP
-      define:
-        - CORTEXM
-    
-    - type: VHT_M7
-      device: ARMCM7_DP
-      define:
-        - CORTEXM
-      
-    - type: VHT_M4
-      device: ARMCM4_FP
-      define:
-        - CORTEXM
-      
-    - type: VHT_M3
-      device: ARMCM3
-      define:
-        - CORTEXM
-      
-    - type: VHT_M23
-      device: ARMCM23
-      define:
-        - CORTEXM
-      
-    - type: VHT_M0P
-      device: ARMCM0P
-      define:
-        - CORTEXM
-      
-  build-types:
-    - type: Release
-      debug: off
-      
-
-  projects:
-    - project: ./test.cproject.yml
\ No newline at end of file
diff --git a/Testing/main.cpp b/Testing/main.cpp
index 0a5476745..c6b50883a 100644
--- a/Testing/main.cpp
+++ b/Testing/main.cpp
@@ -4,55 +4,6 @@ extern int testmain(const char *);
 
 extern "C" const char *patternData;
 
-//! \note for IAR
-#ifdef __IS_COMPILER_IAR__
-#   undef __IS_COMPILER_IAR__
-#endif
-#if defined(__IAR_SYSTEMS_ICC__)
-#   define __IS_COMPILER_IAR__                 1
-#endif
-
-
-
-
-//! \note for arm compiler 5
-#ifdef __IS_COMPILER_ARM_COMPILER_5__
-#   undef __IS_COMPILER_ARM_COMPILER_5__
-#endif
-#if ((__ARMCC_VERSION >= 5000000) && (__ARMCC_VERSION < 6000000))
-#   define __IS_COMPILER_ARM_COMPILER_5__      1
-#endif
-//! @}
-
-//! \note for arm compiler 6
-#ifdef __IS_COMPILER_ARM_COMPILER_6__
-#   undef __IS_COMPILER_ARM_COMPILER_6__
-#endif
-#if ((__ARMCC_VERSION >= 6000000) && (__ARMCC_VERSION < 7000000))
-#   define __IS_COMPILER_ARM_COMPILER_6__      1
-#endif
-
-#ifdef __IS_COMPILER_LLVM__
-#   undef  __IS_COMPILER_LLVM__
-#endif
-#if defined(__clang__) && !__IS_COMPILER_ARM_COMPILER_6__
-#   define __IS_COMPILER_LLVM__                1
-#else
-//! \note for gcc
-#ifdef __IS_COMPILER_GCC__
-#   undef __IS_COMPILER_GCC__
-#endif
-#if defined(__GNUC__) && !(__IS_COMPILER_ARM_COMPILER_6__ || __IS_COMPILER_LLVM__)
-#   define __IS_COMPILER_GCC__                 1
-#endif
-//! @}
-#endif
-//! @}
-
-#if defined(ARMCM33_DSP_FP) && defined(__IS_COMPILER_GCC__)
-extern "C" void _exit(int return_code);
-#endif
-
 
 int main()
 {
@@ -60,15 +11,5 @@ int main()
 
     r=testmain(patternData);
 
-    /* 
-
-    Temporary solution to solve problems with IPSS support for M33.
-
-    */
-
-    #if defined(ARMCM33_DSP_FP) && defined(__IS_COMPILER_GCC__)
-    _exit(r);
-    #endif
-
-    return(r);
+    exit(r);
 }
diff --git a/Testing/testmain.cpp b/Testing/testmain.cpp
index e41f6afc5..493959e07 100644
--- a/Testing/testmain.cpp
+++ b/Testing/testmain.cpp
@@ -5,6 +5,7 @@
 #if defined(EMBEDDED)
 #include "FPGA.h"
 #else
+#error("Only EMBEDDED mode is supported. Other modes are deprecated")
 #include "Semihosting.h"
 #endif
 #include "IORunner.h"
diff --git a/vcpkg-configuration.json b/vcpkg-configuration.json
index efd106f4e..d4ca1c816 100644
--- a/vcpkg-configuration.json
+++ b/vcpkg-configuration.json
@@ -12,6 +12,7 @@
   "arm:tools/ninja-build/ninja": "1.12.0",
   "arm:compilers/arm/armclang": "6.22.0",
   "arm:compilers/arm/arm-none-eabi-gcc": "^13.2.1",
+  "arm:compilers/arm/llvm-embedded": "^18.1.3",
   "arm:models/arm/avh-fvp": "^11.22.39",
   "arm:debuggers/arm/armdbg": "6.1.2"
  }