diff --git a/Source/TransformFunctions/arm_mfcc_q15.c b/Source/TransformFunctions/arm_mfcc_q15.c
index ba7acd0bc..e9e31b22f 100755
--- a/Source/TransformFunctions/arm_mfcc_q15.c
+++ b/Source/TransformFunctions/arm_mfcc_q15.c
@@ -95,7 +95,7 @@ arm_status arm_mfcc_q15(
// q15
arm_absmax_q15(pSrc,S->fftLen,&m,&index);
- if (m !=0)
+ if ((m != 0) && (m != 0x7FFF))
{
q15_t quotient;
int16_t shift;
@@ -162,7 +162,7 @@ arm_status arm_mfcc_q15(
}
- if (m != 0)
+ if ((m != 0) && (m != 0x7FFF))
{
arm_scale_q31(pTmp,m<<16,0,pTmp,S->nbMelFilters);
}
diff --git a/Source/TransformFunctions/arm_mfcc_q31.c b/Source/TransformFunctions/arm_mfcc_q31.c
index 5acd61e1b..b1adaaba3 100755
--- a/Source/TransformFunctions/arm_mfcc_q31.c
+++ b/Source/TransformFunctions/arm_mfcc_q31.c
@@ -96,7 +96,7 @@ arm_status arm_mfcc_q31(
// q31
arm_absmax_q31(pSrc,S->fftLen,&m,&index);
- if (m !=0)
+ if ((m != 0) && (m != 0x7FFFFFFF))
{
q31_t quotient;
int16_t shift;
@@ -165,7 +165,7 @@ arm_status arm_mfcc_q31(
}
- if (m != 0)
+ if ((m != 0) && (m != 0x7FFFFFFF))
{
arm_scale_q31(pTmp,m,0,pTmp,S->nbMelFilters);
}
diff --git a/Testing/FrameworkSource/IORunner.cpp b/Testing/FrameworkSource/IORunner.cpp
index 6abf16294..5538352ad 100644
--- a/Testing/FrameworkSource/IORunner.cpp
+++ b/Testing/FrameworkSource/IORunner.cpp
@@ -198,7 +198,7 @@ fast models.
{
Testing::TestStatus finalResult = Testing::kTestPassed;
int nbTests = s->getNbTests();
- int failedTests=0;
+ //int failedTests=0;
Testing::errorID_t error=0;
unsigned long line = 0;
char details[200];
@@ -378,7 +378,7 @@ fast models.
if (result == Testing::kTestFailed)
{
- failedTests ++;
+ //failedTests ++;
finalResult = Testing::kTestFailed;
}
}
@@ -392,7 +392,7 @@ fast models.
Testing::TestStatus IORunner::run(Group *g)
{
int nbTests = g->getNbContainer();
- int failedTests=0;
+ //int failedTests=0;
// Read Node identification
@@ -411,7 +411,7 @@ fast models.
if (result == Testing::kTestFailed)
{
- failedTests ++;
+ //failedTests ++;
finalResult = Testing::kTestFailed;
}
}
diff --git a/Testing/cmsis_build/RTE/Device/ARMCM55/partition_ARMCM55.h b/Testing/cmsis_build/RTE/Device/ARMCM55/partition_ARMCM55.h
new file mode 100644
index 000000000..eabaf300f
--- /dev/null
+++ b/Testing/cmsis_build/RTE/Device/ARMCM55/partition_ARMCM55.h
@@ -0,0 +1,1261 @@
+/**************************************************************************//**
+ * @file partition_ARMCM55.h
+ * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline
+ * @version V1.0.0
+ * @date 20. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef PARTITION_ARMCM55_H
+#define PARTITION_ARMCM55_H
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+*/
+
+/*
+// Initialize Security Attribution Unit (SAU) CTRL register
+*/
+#define SAU_INIT_CTRL 1
+
+/*
+// Enable SAU
+// Value for SAU->CTRL register bit ENABLE
+*/
+#define SAU_INIT_CTRL_ENABLE 1
+
+/*
+// When SAU is disabled
+// <0=> All Memory is Secure
+// <1=> All Memory is Non-Secure
+// Value for SAU->CTRL register bit ALLNS
+// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
+*/
+#define SAU_INIT_CTRL_ALLNS 0
+
+/*
+//
+*/
+
+/*
+// Initialize Security Attribution Unit (SAU) Address Regions
+// SAU configuration specifies regions to be one of:
+// - Secure and Non-Secure Callable
+// - Non-Secure
+// Note: All memory regions not configured by SAU are Secure
+*/
+#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
+
+/*
+// Initialize SAU Region 0
+// Setup SAU Region 0 memory attributes
+*/
+#define SAU_INIT_REGION0 1
+
+/*
+// Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */
+
+/*
+// End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */
+
+/*
+// Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC0 1
+/*
+//
+*/
+
+/*
+// Initialize SAU Region 1
+// Setup SAU Region 1 memory attributes
+*/
+#define SAU_INIT_REGION1 1
+
+/*
+// Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START1 0x00200000
+
+/*
+// End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END1 0x003FFFFF
+
+/*
+// Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC1 0
+/*
+//
+*/
+
+/*
+// Initialize SAU Region 2
+// Setup SAU Region 2 memory attributes
+*/
+#define SAU_INIT_REGION2 1
+
+/*
+// Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START2 0x20200000
+
+/*
+// End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END2 0x203FFFFF
+
+/*
+// Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC2 0
+/*
+//
+*/
+
+/*
+// Initialize SAU Region 3
+// Setup SAU Region 3 memory attributes
+*/
+#define SAU_INIT_REGION3 1
+
+/*
+// Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START3 0x40000000
+
+/*
+// End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END3 0x40040000
+
+/*
+// Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC3 0
+/*
+//
+*/
+
+/*
+// Initialize SAU Region 4
+// Setup SAU Region 4 memory attributes
+*/
+#define SAU_INIT_REGION4 0
+
+/*
+// Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */
+
+/*
+// End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */
+
+/*
+// Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC4 0
+/*
+//
+*/
+
+/*
+// Initialize SAU Region 5
+// Setup SAU Region 5 memory attributes
+*/
+#define SAU_INIT_REGION5 0
+
+/*
+// Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START5 0x00000000
+
+/*
+// End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END5 0x00000000
+
+/*
+// Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC5 0
+/*
+//
+*/
+
+/*
+// Initialize SAU Region 6
+// Setup SAU Region 6 memory attributes
+*/
+#define SAU_INIT_REGION6 0
+
+/*
+// Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START6 0x00000000
+
+/*
+// End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END6 0x00000000
+
+/*
+// Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC6 0
+/*
+//
+*/
+
+/*
+// Initialize SAU Region 7
+// Setup SAU Region 7 memory attributes
+*/
+#define SAU_INIT_REGION7 0
+
+/*
+// Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START7 0x00000000
+
+/*
+// End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END7 0x00000000
+
+/*
+// Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC7 0
+/*
+//
+*/
+
+/*
+//
+*/
+
+/*
+// Setup behaviour of Sleep and Exception Handling
+*/
+#define SCB_CSR_AIRCR_INIT 1
+
+/*
+// Deep Sleep can be enabled by
+// <0=>Secure and Non-Secure state
+// <1=>Secure state only
+// Value for SCB->CSR register bit DEEPSLEEPS
+*/
+#define SCB_CSR_DEEPSLEEPS_VAL 1
+
+/*
+// System reset request accessible from
+// <0=> Secure and Non-Secure state
+// <1=> Secure state only
+// Value for SCB->AIRCR register bit SYSRESETREQS
+*/
+#define SCB_AIRCR_SYSRESETREQS_VAL 1
+
+/*
+// Priority of Non-Secure exceptions is
+// <0=> Not altered
+// <1=> Lowered to 0x80-0xFF
+// Value for SCB->AIRCR register bit PRIS
+*/
+#define SCB_AIRCR_PRIS_VAL 1
+
+/*
+// BusFault, HardFault, and NMI target
+// <0=> Secure state
+// <1=> Non-Secure state
+// Value for SCB->AIRCR register bit BFHFNMINS
+*/
+#define SCB_AIRCR_BFHFNMINS_VAL 0
+
+/*
+//
+*/
+
+/*
+// Setup behaviour of Floating Point and Vector Unit (FPU/MVE)
+*/
+#define TZ_FPU_NS_USAGE 1
+
+/*
+// Floating Point and Vector Unit usage
+// <0=> Secure state only
+// <3=> Secure and Non-Secure state
+// Value for SCB->NSACR register bits CP10, CP11
+*/
+#define SCB_NSACR_CP10_11_VAL 3
+
+/*
+// Treat floating-point registers as Secure
+// <0=> Disabled
+// <1=> Enabled
+// Value for FPU->FPCCR register bit TS
+*/
+#define FPU_FPCCR_TS_VAL 0
+
+/*
+// Clear on return (CLRONRET) accessibility
+// <0=> Secure and Non-Secure state
+// <1=> Secure state only
+// Value for FPU->FPCCR register bit CLRONRETS
+*/
+#define FPU_FPCCR_CLRONRETS_VAL 0
+
+/*
+// Clear floating-point caller saved registers on exception return
+// <0=> Disabled
+// <1=> Enabled
+// Value for FPU->FPCCR register bit CLRONRET
+*/
+#define FPU_FPCCR_CLRONRET_VAL 1
+
+/*
+//
+*/
+
+/*
+// Setup Interrupt Target
+*/
+
+/*
+// Initialize ITNS 0 (Interrupts 0..31)
+*/
+#define NVIC_INIT_ITNS0 1
+
+/*
+// Interrupts 0..31
+// Interrupt 0 <0=> Secure state <1=> Non-Secure state
+// Interrupt 1 <0=> Secure state <1=> Non-Secure state
+// Interrupt 2 <0=> Secure state <1=> Non-Secure state
+// Interrupt 3 <0=> Secure state <1=> Non-Secure state
+// Interrupt 4 <0=> Secure state <1=> Non-Secure state
+// Interrupt 5 <0=> Secure state <1=> Non-Secure state
+// Interrupt 6 <0=> Secure state <1=> Non-Secure state
+// Interrupt 7 <0=> Secure state <1=> Non-Secure state
+// Interrupt 8 <0=> Secure state <1=> Non-Secure state
+// Interrupt 9 <0=> Secure state <1=> Non-Secure state
+// Interrupt 10 <0=> Secure state <1=> Non-Secure state
+// Interrupt 11 <0=> Secure state <1=> Non-Secure state
+// Interrupt 12 <0=> Secure state <1=> Non-Secure state
+// Interrupt 13 <0=> Secure state <1=> Non-Secure state
+// Interrupt 14 <0=> Secure state <1=> Non-Secure state
+// Interrupt 15 <0=> Secure state <1=> Non-Secure state
+// Interrupt 16 <0=> Secure state <1=> Non-Secure state
+// Interrupt 17 <0=> Secure state <1=> Non-Secure state
+// Interrupt 18 <0=> Secure state <1=> Non-Secure state
+// Interrupt 19 <0=> Secure state <1=> Non-Secure state
+// Interrupt 20 <0=> Secure state <1=> Non-Secure state
+// Interrupt 21 <0=> Secure state <1=> Non-Secure state
+// Interrupt 22 <0=> Secure state <1=> Non-Secure state
+// Interrupt 23 <0=> Secure state <1=> Non-Secure state
+// Interrupt 24 <0=> Secure state <1=> Non-Secure state
+// Interrupt 25 <0=> Secure state <1=> Non-Secure state
+// Interrupt 26 <0=> Secure state <1=> Non-Secure state
+// Interrupt 27 <0=> Secure state <1=> Non-Secure state
+// Interrupt 28 <0=> Secure state <1=> Non-Secure state
+// Interrupt 29 <0=> Secure state <1=> Non-Secure state
+// Interrupt 30 <0=> Secure state <1=> Non-Secure state
+// Interrupt 31 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS0_VAL 0x00000000
+
+/*
+//
+*/
+
+/*
+// Initialize ITNS 1 (Interrupts 32..63)
+*/
+#define NVIC_INIT_ITNS1 1
+
+/*
+// Interrupts 32..63
+// Interrupt 32 <0=> Secure state <1=> Non-Secure state
+// Interrupt 33 <0=> Secure state <1=> Non-Secure state
+// Interrupt 34 <0=> Secure state <1=> Non-Secure state
+// Interrupt 35 <0=> Secure state <1=> Non-Secure state
+// Interrupt 36 <0=> Secure state <1=> Non-Secure state
+// Interrupt 37 <0=> Secure state <1=> Non-Secure state
+// Interrupt 38 <0=> Secure state <1=> Non-Secure state
+// Interrupt 39 <0=> Secure state <1=> Non-Secure state
+// Interrupt 40 <0=> Secure state <1=> Non-Secure state
+// Interrupt 41 <0=> Secure state <1=> Non-Secure state
+// Interrupt 42 <0=> Secure state <1=> Non-Secure state
+// Interrupt 43 <0=> Secure state <1=> Non-Secure state
+// Interrupt 44 <0=> Secure state <1=> Non-Secure state
+// Interrupt 45 <0=> Secure state <1=> Non-Secure state
+// Interrupt 46 <0=> Secure state <1=> Non-Secure state
+// Interrupt 47 <0=> Secure state <1=> Non-Secure state
+// Interrupt 48 <0=> Secure state <1=> Non-Secure state
+// Interrupt 49 <0=> Secure state <1=> Non-Secure state
+// Interrupt 50 <0=> Secure state <1=> Non-Secure state
+// Interrupt 51 <0=> Secure state <1=> Non-Secure state
+// Interrupt 52 <0=> Secure state <1=> Non-Secure state
+// Interrupt 53 <0=> Secure state <1=> Non-Secure state
+// Interrupt 54 <0=> Secure state <1=> Non-Secure state
+// Interrupt 55 <0=> Secure state <1=> Non-Secure state
+// Interrupt 56 <0=> Secure state <1=> Non-Secure state
+// Interrupt 57 <0=> Secure state <1=> Non-Secure state
+// Interrupt 58 <0=> Secure state <1=> Non-Secure state
+// Interrupt 59 <0=> Secure state <1=> Non-Secure state
+// Interrupt 60 <0=> Secure state <1=> Non-Secure state
+// Interrupt 61 <0=> Secure state <1=> Non-Secure state
+// Interrupt 62 <0=> Secure state <1=> Non-Secure state
+// Interrupt 63 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS1_VAL 0x00000000
+
+/*
+//
+*/
+
+/*
+// Initialize ITNS 2 (Interrupts 64..95)
+*/
+#define NVIC_INIT_ITNS2 0
+
+/*
+// Interrupts 64..95
+// Interrupt 64 <0=> Secure state <1=> Non-Secure state
+// Interrupt 65 <0=> Secure state <1=> Non-Secure state
+// Interrupt 66 <0=> Secure state <1=> Non-Secure state
+// Interrupt 67 <0=> Secure state <1=> Non-Secure state
+// Interrupt 68 <0=> Secure state <1=> Non-Secure state
+// Interrupt 69 <0=> Secure state <1=> Non-Secure state
+// Interrupt 70 <0=> Secure state <1=> Non-Secure state
+// Interrupt 71 <0=> Secure state <1=> Non-Secure state
+// Interrupt 72 <0=> Secure state <1=> Non-Secure state
+// Interrupt 73 <0=> Secure state <1=> Non-Secure state
+// Interrupt 74 <0=> Secure state <1=> Non-Secure state
+// Interrupt 75 <0=> Secure state <1=> Non-Secure state
+// Interrupt 76 <0=> Secure state <1=> Non-Secure state
+// Interrupt 77 <0=> Secure state <1=> Non-Secure state
+// Interrupt 78 <0=> Secure state <1=> Non-Secure state
+// Interrupt 79 <0=> Secure state <1=> Non-Secure state
+// Interrupt 80 <0=> Secure state <1=> Non-Secure state
+// Interrupt 81 <0=> Secure state <1=> Non-Secure state
+// Interrupt 82 <0=> Secure state <1=> Non-Secure state
+// Interrupt 83 <0=> Secure state <1=> Non-Secure state
+// Interrupt 84 <0=> Secure state <1=> Non-Secure state
+// Interrupt 85 <0=> Secure state <1=> Non-Secure state
+// Interrupt 86 <0=> Secure state <1=> Non-Secure state
+// Interrupt 87 <0=> Secure state <1=> Non-Secure state
+// Interrupt 88 <0=> Secure state <1=> Non-Secure state
+// Interrupt 89 <0=> Secure state <1=> Non-Secure state
+// Interrupt 90 <0=> Secure state <1=> Non-Secure state
+// Interrupt 91 <0=> Secure state <1=> Non-Secure state
+// Interrupt 92 <0=> Secure state <1=> Non-Secure state
+// Interrupt 93 <0=> Secure state <1=> Non-Secure state
+// Interrupt 94 <0=> Secure state <1=> Non-Secure state
+// Interrupt 95 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS2_VAL 0x00000000
+
+/*
+//
+*/
+
+/*
+// Initialize ITNS 3 (Interrupts 96..127)
+*/
+#define NVIC_INIT_ITNS3 0
+
+/*
+// Interrupts 96..127
+// Interrupt 96 <0=> Secure state <1=> Non-Secure state
+// Interrupt 97 <0=> Secure state <1=> Non-Secure state
+// Interrupt 98 <0=> Secure state <1=> Non-Secure state
+// Interrupt 99 <0=> Secure state <1=> Non-Secure state
+// Interrupt 100 <0=> Secure state <1=> Non-Secure state
+// Interrupt 101 <0=> Secure state <1=> Non-Secure state
+// Interrupt 102 <0=> Secure state <1=> Non-Secure state
+// Interrupt 103 <0=> Secure state <1=> Non-Secure state
+// Interrupt 104 <0=> Secure state <1=> Non-Secure state
+// Interrupt 105 <0=> Secure state <1=> Non-Secure state
+// Interrupt 106 <0=> Secure state <1=> Non-Secure state
+// Interrupt 107 <0=> Secure state <1=> Non-Secure state
+// Interrupt 108 <0=> Secure state <1=> Non-Secure state
+// Interrupt 109 <0=> Secure state <1=> Non-Secure state
+// Interrupt 110 <0=> Secure state <1=> Non-Secure state
+// Interrupt 111 <0=> Secure state <1=> Non-Secure state
+// Interrupt 112 <0=> Secure state <1=> Non-Secure state
+// Interrupt 113 <0=> Secure state <1=> Non-Secure state
+// Interrupt 114 <0=> Secure state <1=> Non-Secure state
+// Interrupt 115 <0=> Secure state <1=> Non-Secure state
+// Interrupt 116 <0=> Secure state <1=> Non-Secure state
+// Interrupt 117 <0=> Secure state <1=> Non-Secure state
+// Interrupt 118 <0=> Secure state <1=> Non-Secure state
+// Interrupt 119 <0=> Secure state <1=> Non-Secure state
+// Interrupt 120 <0=> Secure state <1=> Non-Secure state
+// Interrupt 121 <0=> Secure state <1=> Non-Secure state
+// Interrupt 122 <0=> Secure state <1=> Non-Secure state
+// Interrupt 123 <0=> Secure state <1=> Non-Secure state
+// Interrupt 124 <0=> Secure state <1=> Non-Secure state
+// Interrupt 125 <0=> Secure state <1=> Non-Secure state
+// Interrupt 126 <0=> Secure state <1=> Non-Secure state
+// Interrupt 127 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS3_VAL 0x00000000
+
+/*
+//
+*/
+
+/*
+// Initialize ITNS 4 (Interrupts 128..159)
+*/
+#define NVIC_INIT_ITNS4 0
+
+/*
+// Interrupts 128..159
+// Interrupt 128 <0=> Secure state <1=> Non-Secure state
+// Interrupt 129 <0=> Secure state <1=> Non-Secure state
+// Interrupt 130 <0=> Secure state <1=> Non-Secure state
+// Interrupt 131 <0=> Secure state <1=> Non-Secure state
+// Interrupt 132 <0=> Secure state <1=> Non-Secure state
+// Interrupt 133 <0=> Secure state <1=> Non-Secure state
+// Interrupt 134 <0=> Secure state <1=> Non-Secure state
+// Interrupt 135 <0=> Secure state <1=> Non-Secure state
+// Interrupt 136 <0=> Secure state <1=> Non-Secure state
+// Interrupt 137 <0=> Secure state <1=> Non-Secure state
+// Interrupt 138 <0=> Secure state <1=> Non-Secure state
+// Interrupt 139 <0=> Secure state <1=> Non-Secure state
+// Interrupt 140 <0=> Secure state <1=> Non-Secure state
+// Interrupt 141 <0=> Secure state <1=> Non-Secure state
+// Interrupt 142 <0=> Secure state <1=> Non-Secure state
+// Interrupt 143 <0=> Secure state <1=> Non-Secure state
+// Interrupt 144 <0=> Secure state <1=> Non-Secure state
+// Interrupt 145 <0=> Secure state <1=> Non-Secure state
+// Interrupt 146 <0=> Secure state <1=> Non-Secure state
+// Interrupt 147 <0=> Secure state <1=> Non-Secure state
+// Interrupt 148 <0=> Secure state <1=> Non-Secure state
+// Interrupt 149 <0=> Secure state <1=> Non-Secure state
+// Interrupt 150 <0=> Secure state <1=> Non-Secure state
+// Interrupt 151 <0=> Secure state <1=> Non-Secure state
+// Interrupt 152 <0=> Secure state <1=> Non-Secure state
+// Interrupt 153 <0=> Secure state <1=> Non-Secure state
+// Interrupt 154 <0=> Secure state <1=> Non-Secure state
+// Interrupt 155 <0=> Secure state <1=> Non-Secure state
+// Interrupt 156 <0=> Secure state <1=> Non-Secure state
+// Interrupt 157 <0=> Secure state <1=> Non-Secure state
+// Interrupt 158 <0=> Secure state <1=> Non-Secure state
+// Interrupt 159 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS4_VAL 0x00000000
+
+/*
+//
+*/
+
+/*
+// Initialize ITNS 5 (Interrupts 160..191)
+*/
+#define NVIC_INIT_ITNS5 0
+
+/*
+// Interrupts 160..191
+// Interrupt 160 <0=> Secure state <1=> Non-Secure state
+// Interrupt 161 <0=> Secure state <1=> Non-Secure state
+// Interrupt 162 <0=> Secure state <1=> Non-Secure state
+// Interrupt 163 <0=> Secure state <1=> Non-Secure state
+// Interrupt 164 <0=> Secure state <1=> Non-Secure state
+// Interrupt 165 <0=> Secure state <1=> Non-Secure state
+// Interrupt 166 <0=> Secure state <1=> Non-Secure state
+// Interrupt 167 <0=> Secure state <1=> Non-Secure state
+// Interrupt 168 <0=> Secure state <1=> Non-Secure state
+// Interrupt 169 <0=> Secure state <1=> Non-Secure state
+// Interrupt 170 <0=> Secure state <1=> Non-Secure state
+// Interrupt 171 <0=> Secure state <1=> Non-Secure state
+// Interrupt 172 <0=> Secure state <1=> Non-Secure state
+// Interrupt 173 <0=> Secure state <1=> Non-Secure state
+// Interrupt 174 <0=> Secure state <1=> Non-Secure state
+// Interrupt 175 <0=> Secure state <1=> Non-Secure state
+// Interrupt 176 <0=> Secure state <1=> Non-Secure state
+// Interrupt 177 <0=> Secure state <1=> Non-Secure state
+// Interrupt 178 <0=> Secure state <1=> Non-Secure state
+// Interrupt 179 <0=> Secure state <1=> Non-Secure state
+// Interrupt 180 <0=> Secure state <1=> Non-Secure state
+// Interrupt 181 <0=> Secure state <1=> Non-Secure state
+// Interrupt 182 <0=> Secure state <1=> Non-Secure state
+// Interrupt 183 <0=> Secure state <1=> Non-Secure state
+// Interrupt 184 <0=> Secure state <1=> Non-Secure state
+// Interrupt 185 <0=> Secure state <1=> Non-Secure state
+// Interrupt 186 <0=> Secure state <1=> Non-Secure state
+// Interrupt 187 <0=> Secure state <1=> Non-Secure state
+// Interrupt 188 <0=> Secure state <1=> Non-Secure state
+// Interrupt 189 <0=> Secure state <1=> Non-Secure state
+// Interrupt 190 <0=> Secure state <1=> Non-Secure state
+// Interrupt 191 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS5_VAL 0x00000000
+
+/*
+//
+*/
+
+/*
+// Initialize ITNS 6 (Interrupts 192..223)
+*/
+#define NVIC_INIT_ITNS6 0
+
+/*
+// Interrupts 192..223
+// Interrupt 192 <0=> Secure state <1=> Non-Secure state
+// Interrupt 193 <0=> Secure state <1=> Non-Secure state
+// Interrupt 194 <0=> Secure state <1=> Non-Secure state
+// Interrupt 195 <0=> Secure state <1=> Non-Secure state
+// Interrupt 196 <0=> Secure state <1=> Non-Secure state
+// Interrupt 197 <0=> Secure state <1=> Non-Secure state
+// Interrupt 198 <0=> Secure state <1=> Non-Secure state
+// Interrupt 199 <0=> Secure state <1=> Non-Secure state
+// Interrupt 200 <0=> Secure state <1=> Non-Secure state
+// Interrupt 201 <0=> Secure state <1=> Non-Secure state
+// Interrupt 202 <0=> Secure state <1=> Non-Secure state
+// Interrupt 203 <0=> Secure state <1=> Non-Secure state
+// Interrupt 204 <0=> Secure state <1=> Non-Secure state
+// Interrupt 205 <0=> Secure state <1=> Non-Secure state
+// Interrupt 206 <0=> Secure state <1=> Non-Secure state
+// Interrupt 207 <0=> Secure state <1=> Non-Secure state
+// Interrupt 208 <0=> Secure state <1=> Non-Secure state
+// Interrupt 209 <0=> Secure state <1=> Non-Secure state
+// Interrupt 210 <0=> Secure state <1=> Non-Secure state
+// Interrupt 211 <0=> Secure state <1=> Non-Secure state
+// Interrupt 212 <0=> Secure state <1=> Non-Secure state
+// Interrupt 213 <0=> Secure state <1=> Non-Secure state
+// Interrupt 214 <0=> Secure state <1=> Non-Secure state
+// Interrupt 215 <0=> Secure state <1=> Non-Secure state
+// Interrupt 216 <0=> Secure state <1=> Non-Secure state
+// Interrupt 217 <0=> Secure state <1=> Non-Secure state
+// Interrupt 218 <0=> Secure state <1=> Non-Secure state
+// Interrupt 219 <0=> Secure state <1=> Non-Secure state
+// Interrupt 220 <0=> Secure state <1=> Non-Secure state
+// Interrupt 221 <0=> Secure state <1=> Non-Secure state
+// Interrupt 222 <0=> Secure state <1=> Non-Secure state
+// Interrupt 223 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS6_VAL 0x00000000
+
+/*
+//
+*/
+
+/*
+// Initialize ITNS 7 (Interrupts 224..255)
+*/
+#define NVIC_INIT_ITNS7 0
+
+/*
+// Interrupts 224..255
+// Interrupt 224 <0=> Secure state <1=> Non-Secure state
+// Interrupt 225 <0=> Secure state <1=> Non-Secure state
+// Interrupt 226 <0=> Secure state <1=> Non-Secure state
+// Interrupt 227 <0=> Secure state <1=> Non-Secure state
+// Interrupt 228 <0=> Secure state <1=> Non-Secure state
+// Interrupt 229 <0=> Secure state <1=> Non-Secure state
+// Interrupt 230 <0=> Secure state <1=> Non-Secure state
+// Interrupt 231 <0=> Secure state <1=> Non-Secure state
+// Interrupt 232 <0=> Secure state <1=> Non-Secure state
+// Interrupt 233 <0=> Secure state <1=> Non-Secure state
+// Interrupt 234 <0=> Secure state <1=> Non-Secure state
+// Interrupt 235 <0=> Secure state <1=> Non-Secure state
+// Interrupt 236 <0=> Secure state <1=> Non-Secure state
+// Interrupt 237 <0=> Secure state <1=> Non-Secure state
+// Interrupt 238 <0=> Secure state <1=> Non-Secure state
+// Interrupt 239 <0=> Secure state <1=> Non-Secure state
+// Interrupt 240 <0=> Secure state <1=> Non-Secure state
+// Interrupt 241 <0=> Secure state <1=> Non-Secure state
+// Interrupt 242 <0=> Secure state <1=> Non-Secure state
+// Interrupt 243 <0=> Secure state <1=> Non-Secure state
+// Interrupt 244 <0=> Secure state <1=> Non-Secure state
+// Interrupt 245 <0=> Secure state <1=> Non-Secure state
+// Interrupt 246 <0=> Secure state <1=> Non-Secure state
+// Interrupt 247 <0=> Secure state <1=> Non-Secure state
+// Interrupt 248 <0=> Secure state <1=> Non-Secure state
+// Interrupt 249 <0=> Secure state <1=> Non-Secure state
+// Interrupt 250 <0=> Secure state <1=> Non-Secure state
+// Interrupt 251 <0=> Secure state <1=> Non-Secure state
+// Interrupt 252 <0=> Secure state <1=> Non-Secure state
+// Interrupt 253 <0=> Secure state <1=> Non-Secure state
+// Interrupt 254 <0=> Secure state <1=> Non-Secure state
+// Interrupt 255 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS7_VAL 0x00000000
+
+/*
+//
+*/
+
+/*
+// Initialize ITNS 8 (Interrupts 256..287)
+*/
+#define NVIC_INIT_ITNS8 0
+
+/*
+// Interrupts 256..287
+// Interrupt 256 <0=> Secure state <1=> Non-Secure state
+// Interrupt 257 <0=> Secure state <1=> Non-Secure state
+// Interrupt 258 <0=> Secure state <1=> Non-Secure state
+// Interrupt 259 <0=> Secure state <1=> Non-Secure state
+// Interrupt 260 <0=> Secure state <1=> Non-Secure state
+// Interrupt 261 <0=> Secure state <1=> Non-Secure state
+// Interrupt 262 <0=> Secure state <1=> Non-Secure state
+// Interrupt 263 <0=> Secure state <1=> Non-Secure state
+// Interrupt 264 <0=> Secure state <1=> Non-Secure state
+// Interrupt 265 <0=> Secure state <1=> Non-Secure state
+// Interrupt 266 <0=> Secure state <1=> Non-Secure state
+// Interrupt 267 <0=> Secure state <1=> Non-Secure state
+// Interrupt 268 <0=> Secure state <1=> Non-Secure state
+// Interrupt 269 <0=> Secure state <1=> Non-Secure state
+// Interrupt 270 <0=> Secure state <1=> Non-Secure state
+// Interrupt 271 <0=> Secure state <1=> Non-Secure state
+// Interrupt 272 <0=> Secure state <1=> Non-Secure state
+// Interrupt 273 <0=> Secure state <1=> Non-Secure state
+// Interrupt 274 <0=> Secure state <1=> Non-Secure state
+// Interrupt 275 <0=> Secure state <1=> Non-Secure state
+// Interrupt 276 <0=> Secure state <1=> Non-Secure state
+// Interrupt 277 <0=> Secure state <1=> Non-Secure state
+// Interrupt 278 <0=> Secure state <1=> Non-Secure state
+// Interrupt 279 <0=> Secure state <1=> Non-Secure state
+// Interrupt 280 <0=> Secure state <1=> Non-Secure state
+// Interrupt 281 <0=> Secure state <1=> Non-Secure state
+// Interrupt 282 <0=> Secure state <1=> Non-Secure state
+// Interrupt 283 <0=> Secure state <1=> Non-Secure state
+// Interrupt 284 <0=> Secure state <1=> Non-Secure state
+// Interrupt 285 <0=> Secure state <1=> Non-Secure state
+// Interrupt 286 <0=> Secure state <1=> Non-Secure state
+// Interrupt 287 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS8_VAL 0x00000000
+
+/*
+//
+*/
+
+/*
+// Initialize ITNS 9 (Interrupts 288..319)
+*/
+#define NVIC_INIT_ITNS9 0
+
+/*
+// Interrupts 288..319
+// Interrupt 288 <0=> Secure state <1=> Non-Secure state
+// Interrupt 289 <0=> Secure state <1=> Non-Secure state
+// Interrupt 290 <0=> Secure state <1=> Non-Secure state
+// Interrupt 291 <0=> Secure state <1=> Non-Secure state
+// Interrupt 292 <0=> Secure state <1=> Non-Secure state
+// Interrupt 293 <0=> Secure state <1=> Non-Secure state
+// Interrupt 294 <0=> Secure state <1=> Non-Secure state
+// Interrupt 295 <0=> Secure state <1=> Non-Secure state
+// Interrupt 296 <0=> Secure state <1=> Non-Secure state
+// Interrupt 297 <0=> Secure state <1=> Non-Secure state
+// Interrupt 298 <0=> Secure state <1=> Non-Secure state
+// Interrupt 299 <0=> Secure state <1=> Non-Secure state
+// Interrupt 300 <0=> Secure state <1=> Non-Secure state
+// Interrupt 301 <0=> Secure state <1=> Non-Secure state
+// Interrupt 302 <0=> Secure state <1=> Non-Secure state
+// Interrupt 303 <0=> Secure state <1=> Non-Secure state
+// Interrupt 304 <0=> Secure state <1=> Non-Secure state
+// Interrupt 305 <0=> Secure state <1=> Non-Secure state
+// Interrupt 306 <0=> Secure state <1=> Non-Secure state
+// Interrupt 307 <0=> Secure state <1=> Non-Secure state
+// Interrupt 308 <0=> Secure state <1=> Non-Secure state
+// Interrupt 309 <0=> Secure state <1=> Non-Secure state
+// Interrupt 310 <0=> Secure state <1=> Non-Secure state
+// Interrupt 311 <0=> Secure state <1=> Non-Secure state
+// Interrupt 312 <0=> Secure state <1=> Non-Secure state
+// Interrupt 313 <0=> Secure state <1=> Non-Secure state
+// Interrupt 314 <0=> Secure state <1=> Non-Secure state
+// Interrupt 315 <0=> Secure state <1=> Non-Secure state
+// Interrupt 316 <0=> Secure state <1=> Non-Secure state
+// Interrupt 317 <0=> Secure state <1=> Non-Secure state
+// Interrupt 318 <0=> Secure state <1=> Non-Secure state
+// Interrupt 319 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS9_VAL 0x00000000
+
+/*
+//
+*/
+
+/*
+// Initialize ITNS 10 (Interrupts 320..351)
+*/
+#define NVIC_INIT_ITNS10 0
+
+/*
+// Interrupts 320..351
+// Interrupt 320 <0=> Secure state <1=> Non-Secure state
+// Interrupt 321 <0=> Secure state <1=> Non-Secure state
+// Interrupt 322 <0=> Secure state <1=> Non-Secure state
+// Interrupt 323 <0=> Secure state <1=> Non-Secure state
+// Interrupt 324 <0=> Secure state <1=> Non-Secure state
+// Interrupt 325 <0=> Secure state <1=> Non-Secure state
+// Interrupt 326 <0=> Secure state <1=> Non-Secure state
+// Interrupt 327 <0=> Secure state <1=> Non-Secure state
+// Interrupt 328 <0=> Secure state <1=> Non-Secure state
+// Interrupt 329 <0=> Secure state <1=> Non-Secure state
+// Interrupt 330 <0=> Secure state <1=> Non-Secure state
+// Interrupt 331 <0=> Secure state <1=> Non-Secure state
+// Interrupt 332 <0=> Secure state <1=> Non-Secure state
+// Interrupt 333 <0=> Secure state <1=> Non-Secure state
+// Interrupt 334 <0=> Secure state <1=> Non-Secure state
+// Interrupt 335 <0=> Secure state <1=> Non-Secure state
+// Interrupt 336 <0=> Secure state <1=> Non-Secure state
+// Interrupt 337 <0=> Secure state <1=> Non-Secure state
+// Interrupt 338 <0=> Secure state <1=> Non-Secure state
+// Interrupt 339 <0=> Secure state <1=> Non-Secure state
+// Interrupt 340 <0=> Secure state <1=> Non-Secure state
+// Interrupt 341 <0=> Secure state <1=> Non-Secure state
+// Interrupt 342 <0=> Secure state <1=> Non-Secure state
+// Interrupt 343 <0=> Secure state <1=> Non-Secure state
+// Interrupt 344 <0=> Secure state <1=> Non-Secure state
+// Interrupt 345 <0=> Secure state <1=> Non-Secure state
+// Interrupt 346 <0=> Secure state <1=> Non-Secure state
+// Interrupt 347 <0=> Secure state <1=> Non-Secure state
+// Interrupt 348 <0=> Secure state <1=> Non-Secure state
+// Interrupt 349 <0=> Secure state <1=> Non-Secure state
+// Interrupt 350 <0=> Secure state <1=> Non-Secure state
+// Interrupt 351 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS10_VAL 0x00000000
+
+/*
+//
+*/
+
+/*
+// Initialize ITNS 11 (Interrupts 352..383)
+*/
+#define NVIC_INIT_ITNS11 0
+
+/*
+// Interrupts 352..383
+// Interrupt 352 <0=> Secure state <1=> Non-Secure state
+// Interrupt 353 <0=> Secure state <1=> Non-Secure state
+// Interrupt 354 <0=> Secure state <1=> Non-Secure state
+// Interrupt 355 <0=> Secure state <1=> Non-Secure state
+// Interrupt 356 <0=> Secure state <1=> Non-Secure state
+// Interrupt 357 <0=> Secure state <1=> Non-Secure state
+// Interrupt 358 <0=> Secure state <1=> Non-Secure state
+// Interrupt 359 <0=> Secure state <1=> Non-Secure state
+// Interrupt 360 <0=> Secure state <1=> Non-Secure state
+// Interrupt 361 <0=> Secure state <1=> Non-Secure state
+// Interrupt 362 <0=> Secure state <1=> Non-Secure state
+// Interrupt 363 <0=> Secure state <1=> Non-Secure state
+// Interrupt 364 <0=> Secure state <1=> Non-Secure state
+// Interrupt 365 <0=> Secure state <1=> Non-Secure state
+// Interrupt 366 <0=> Secure state <1=> Non-Secure state
+// Interrupt 367 <0=> Secure state <1=> Non-Secure state
+// Interrupt 368 <0=> Secure state <1=> Non-Secure state
+// Interrupt 369 <0=> Secure state <1=> Non-Secure state
+// Interrupt 370 <0=> Secure state <1=> Non-Secure state
+// Interrupt 371 <0=> Secure state <1=> Non-Secure state
+// Interrupt 372 <0=> Secure state <1=> Non-Secure state
+// Interrupt 373 <0=> Secure state <1=> Non-Secure state
+// Interrupt 374 <0=> Secure state <1=> Non-Secure state
+// Interrupt 375 <0=> Secure state <1=> Non-Secure state
+// Interrupt 376 <0=> Secure state <1=> Non-Secure state
+// Interrupt 377 <0=> Secure state <1=> Non-Secure state
+// Interrupt 378 <0=> Secure state <1=> Non-Secure state
+// Interrupt 379 <0=> Secure state <1=> Non-Secure state
+// Interrupt 380 <0=> Secure state <1=> Non-Secure state
+// Interrupt 381 <0=> Secure state <1=> Non-Secure state
+// Interrupt 382 <0=> Secure state <1=> Non-Secure state
+// Interrupt 383 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS11_VAL 0x00000000
+
+/*
+//
+*/
+
+/*
+// Initialize ITNS 12 (Interrupts 384..415)
+*/
+#define NVIC_INIT_ITNS12 0
+
+/*
+// Interrupts 384..415
+// Interrupt 384 <0=> Secure state <1=> Non-Secure state
+// Interrupt 385 <0=> Secure state <1=> Non-Secure state
+// Interrupt 386 <0=> Secure state <1=> Non-Secure state
+// Interrupt 387 <0=> Secure state <1=> Non-Secure state
+// Interrupt 388 <0=> Secure state <1=> Non-Secure state
+// Interrupt 389 <0=> Secure state <1=> Non-Secure state
+// Interrupt 390 <0=> Secure state <1=> Non-Secure state
+// Interrupt 391 <0=> Secure state <1=> Non-Secure state
+// Interrupt 392 <0=> Secure state <1=> Non-Secure state
+// Interrupt 393 <0=> Secure state <1=> Non-Secure state
+// Interrupt 394 <0=> Secure state <1=> Non-Secure state
+// Interrupt 395 <0=> Secure state <1=> Non-Secure state
+// Interrupt 396 <0=> Secure state <1=> Non-Secure state
+// Interrupt 397 <0=> Secure state <1=> Non-Secure state
+// Interrupt 398 <0=> Secure state <1=> Non-Secure state
+// Interrupt 399 <0=> Secure state <1=> Non-Secure state
+// Interrupt 400 <0=> Secure state <1=> Non-Secure state
+// Interrupt 401 <0=> Secure state <1=> Non-Secure state
+// Interrupt 402 <0=> Secure state <1=> Non-Secure state
+// Interrupt 403 <0=> Secure state <1=> Non-Secure state
+// Interrupt 404 <0=> Secure state <1=> Non-Secure state
+// Interrupt 405 <0=> Secure state <1=> Non-Secure state
+// Interrupt 406 <0=> Secure state <1=> Non-Secure state
+// Interrupt 407 <0=> Secure state <1=> Non-Secure state
+// Interrupt 408 <0=> Secure state <1=> Non-Secure state
+// Interrupt 409 <0=> Secure state <1=> Non-Secure state
+// Interrupt 410 <0=> Secure state <1=> Non-Secure state
+// Interrupt 411 <0=> Secure state <1=> Non-Secure state
+// Interrupt 412 <0=> Secure state <1=> Non-Secure state
+// Interrupt 413 <0=> Secure state <1=> Non-Secure state
+// Interrupt 414 <0=> Secure state <1=> Non-Secure state
+// Interrupt 415 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS12_VAL 0x00000000
+
+/*
+//
+*/
+
+/*
+// Initialize ITNS 13 (Interrupts 416..447)
+*/
+#define NVIC_INIT_ITNS13 0
+
+/*
+// Interrupts 416..447
+// Interrupt 416 <0=> Secure state <1=> Non-Secure state
+// Interrupt 417 <0=> Secure state <1=> Non-Secure state
+// Interrupt 418 <0=> Secure state <1=> Non-Secure state
+// Interrupt 419 <0=> Secure state <1=> Non-Secure state
+// Interrupt 420 <0=> Secure state <1=> Non-Secure state
+// Interrupt 421 <0=> Secure state <1=> Non-Secure state
+// Interrupt 422 <0=> Secure state <1=> Non-Secure state
+// Interrupt 423 <0=> Secure state <1=> Non-Secure state
+// Interrupt 424 <0=> Secure state <1=> Non-Secure state
+// Interrupt 425 <0=> Secure state <1=> Non-Secure state
+// Interrupt 426 <0=> Secure state <1=> Non-Secure state
+// Interrupt 427 <0=> Secure state <1=> Non-Secure state
+// Interrupt 428 <0=> Secure state <1=> Non-Secure state
+// Interrupt 429 <0=> Secure state <1=> Non-Secure state
+// Interrupt 430 <0=> Secure state <1=> Non-Secure state
+// Interrupt 431 <0=> Secure state <1=> Non-Secure state
+// Interrupt 432 <0=> Secure state <1=> Non-Secure state
+// Interrupt 433 <0=> Secure state <1=> Non-Secure state
+// Interrupt 434 <0=> Secure state <1=> Non-Secure state
+// Interrupt 435 <0=> Secure state <1=> Non-Secure state
+// Interrupt 436 <0=> Secure state <1=> Non-Secure state
+// Interrupt 437 <0=> Secure state <1=> Non-Secure state
+// Interrupt 438 <0=> Secure state <1=> Non-Secure state
+// Interrupt 439 <0=> Secure state <1=> Non-Secure state
+// Interrupt 440 <0=> Secure state <1=> Non-Secure state
+// Interrupt 441 <0=> Secure state <1=> Non-Secure state
+// Interrupt 442 <0=> Secure state <1=> Non-Secure state
+// Interrupt 443 <0=> Secure state <1=> Non-Secure state
+// Interrupt 444 <0=> Secure state <1=> Non-Secure state
+// Interrupt 445 <0=> Secure state <1=> Non-Secure state
+// Interrupt 446 <0=> Secure state <1=> Non-Secure state
+// Interrupt 447 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS13_VAL 0x00000000
+
+/*
+//
+*/
+
+/*
+// Initialize ITNS 14 (Interrupts 448..479)
+*/
+#define NVIC_INIT_ITNS14 0
+
+/*
+// Interrupts 448..479
+// Interrupt 448 <0=> Secure state <1=> Non-Secure state
+// Interrupt 449 <0=> Secure state <1=> Non-Secure state
+// Interrupt 450 <0=> Secure state <1=> Non-Secure state
+// Interrupt 451 <0=> Secure state <1=> Non-Secure state
+// Interrupt 452 <0=> Secure state <1=> Non-Secure state
+// Interrupt 453 <0=> Secure state <1=> Non-Secure state
+// Interrupt 454 <0=> Secure state <1=> Non-Secure state
+// Interrupt 455 <0=> Secure state <1=> Non-Secure state
+// Interrupt 456 <0=> Secure state <1=> Non-Secure state
+// Interrupt 457 <0=> Secure state <1=> Non-Secure state
+// Interrupt 458 <0=> Secure state <1=> Non-Secure state
+// Interrupt 459 <0=> Secure state <1=> Non-Secure state
+// Interrupt 460 <0=> Secure state <1=> Non-Secure state
+// Interrupt 461 <0=> Secure state <1=> Non-Secure state
+// Interrupt 462 <0=> Secure state <1=> Non-Secure state
+// Interrupt 463 <0=> Secure state <1=> Non-Secure state
+// Interrupt 464 <0=> Secure state <1=> Non-Secure state
+// Interrupt 465 <0=> Secure state <1=> Non-Secure state
+// Interrupt 466 <0=> Secure state <1=> Non-Secure state
+// Interrupt 467 <0=> Secure state <1=> Non-Secure state
+// Interrupt 468 <0=> Secure state <1=> Non-Secure state
+// Interrupt 469 <0=> Secure state <1=> Non-Secure state
+// Interrupt 470 <0=> Secure state <1=> Non-Secure state
+// Interrupt 471 <0=> Secure state <1=> Non-Secure state
+// Interrupt 472 <0=> Secure state <1=> Non-Secure state
+// Interrupt 473 <0=> Secure state <1=> Non-Secure state
+// Interrupt 474 <0=> Secure state <1=> Non-Secure state
+// Interrupt 475 <0=> Secure state <1=> Non-Secure state
+// Interrupt 476 <0=> Secure state <1=> Non-Secure state
+// Interrupt 477 <0=> Secure state <1=> Non-Secure state
+// Interrupt 478 <0=> Secure state <1=> Non-Secure state
+// Interrupt 479 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS14_VAL 0x00000000
+
+/*
+//
+*/
+
+/*
+// Initialize ITNS 15 (Interrupts 480..511)
+*/
+#define NVIC_INIT_ITNS15 0
+
+/*
+// Interrupts 480..511
+// Interrupt 480 <0=> Secure state <1=> Non-Secure state
+// Interrupt 481 <0=> Secure state <1=> Non-Secure state
+// Interrupt 482 <0=> Secure state <1=> Non-Secure state
+// Interrupt 483 <0=> Secure state <1=> Non-Secure state
+// Interrupt 484 <0=> Secure state <1=> Non-Secure state
+// Interrupt 485 <0=> Secure state <1=> Non-Secure state
+// Interrupt 486 <0=> Secure state <1=> Non-Secure state
+// Interrupt 487 <0=> Secure state <1=> Non-Secure state
+// Interrupt 488 <0=> Secure state <1=> Non-Secure state
+// Interrupt 489 <0=> Secure state <1=> Non-Secure state
+// Interrupt 490 <0=> Secure state <1=> Non-Secure state
+// Interrupt 491 <0=> Secure state <1=> Non-Secure state
+// Interrupt 492 <0=> Secure state <1=> Non-Secure state
+// Interrupt 493 <0=> Secure state <1=> Non-Secure state
+// Interrupt 494 <0=> Secure state <1=> Non-Secure state
+// Interrupt 495 <0=> Secure state <1=> Non-Secure state
+// Interrupt 496 <0=> Secure state <1=> Non-Secure state
+// Interrupt 497 <0=> Secure state <1=> Non-Secure state
+// Interrupt 498 <0=> Secure state <1=> Non-Secure state
+// Interrupt 499 <0=> Secure state <1=> Non-Secure state
+// Interrupt 500 <0=> Secure state <1=> Non-Secure state
+// Interrupt 501 <0=> Secure state <1=> Non-Secure state
+// Interrupt 502 <0=> Secure state <1=> Non-Secure state
+// Interrupt 503 <0=> Secure state <1=> Non-Secure state
+// Interrupt 504 <0=> Secure state <1=> Non-Secure state
+// Interrupt 505 <0=> Secure state <1=> Non-Secure state
+// Interrupt 506 <0=> Secure state <1=> Non-Secure state
+// Interrupt 507 <0=> Secure state <1=> Non-Secure state
+// Interrupt 508 <0=> Secure state <1=> Non-Secure state
+// Interrupt 509 <0=> Secure state <1=> Non-Secure state
+// Interrupt 510 <0=> Secure state <1=> Non-Secure state
+// Interrupt 511 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS15_VAL 0x00000000
+
+/*
+//
+*/
+
+/*
+//
+*/
+
+
+
+/*
+ max 128 SAU regions.
+ SAU regions are defined in partition.h
+ */
+
+#define SAU_INIT_REGION(n) \
+ SAU->RNR = (n & SAU_RNR_REGION_Msk); \
+ SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
+ SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
+ ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
+
+/**
+ \brief Setup a SAU Region
+ \details Writes the region information contained in SAU_Region to the
+ registers SAU_RNR, SAU_RBAR, and SAU_RLAR
+ */
+__STATIC_INLINE void TZ_SAU_Setup (void)
+{
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+
+ #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
+ SAU_INIT_REGION(0);
+ #endif
+
+ #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
+ SAU_INIT_REGION(1);
+ #endif
+
+ #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
+ SAU_INIT_REGION(2);
+ #endif
+
+ #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
+ SAU_INIT_REGION(3);
+ #endif
+
+ #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
+ SAU_INIT_REGION(4);
+ #endif
+
+ #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
+ SAU_INIT_REGION(5);
+ #endif
+
+ #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
+ SAU_INIT_REGION(6);
+ #endif
+
+ #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
+ SAU_INIT_REGION(7);
+ #endif
+
+ /* repeat this for all possible SAU regions */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+
+ #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
+ SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
+ ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
+ #endif
+
+ #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
+ SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
+ ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
+
+ SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
+ SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) |
+ ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
+ ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
+ ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
+ ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
+ #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
+
+ #if (((defined (__FPU_USED) && (__FPU_USED == 1U)) || \
+ (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \
+ (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)))
+
+ SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
+ ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
+
+ FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
+ ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |
+ ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
+ ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
+ #endif
+
+ #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
+ NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
+ NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
+ NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
+ NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
+ NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
+ NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
+ NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)
+ NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)
+ NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)
+ NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)
+ NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)
+ NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)
+ NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)
+ NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)
+ NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)
+ NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;
+ #endif
+
+ /* repeat this for all possible ITNS elements */
+
+}
+
+#endif /* PARTITION_ARMCM55_H */
diff --git a/Testing/cmsis_build/runall.py b/Testing/cmsis_build/runall.py
index 4a7780951..160925b93 100644
--- a/Testing/cmsis_build/runall.py
+++ b/Testing/cmsis_build/runall.py
@@ -160,11 +160,11 @@ def runAVH(build,core):
# Test suite and output pickle needed to decode the result
#print(allSuites)
-allSuites=[("MFCCF32","../Output.pickle"),
-("MFCCQ31","../Output.pickle"),
-("MFCCQ15","../Output.pickle"),
-("MFCCF16","../Output_f16.pickle"),
-]
+#allSuites=[
+#("MFCCQ15","../Output.pickle"),
+#("MFCCQ31","../Output.pickle"),
+#("SupportTestsF16","../Output_f16.pickle"),
+#]
#allSuites=[("ComplexTestsF32","../Output.pickle"),
#("DistanceTestsF32","../Output.pickle"),
@@ -204,10 +204,10 @@ def runAVH(build,core):
'test_ac6.csolution.yml':[
# ("VHT-Corstone-310","CS310"),
("VHT-Corstone-300","CS300"),
- # #("VHT_M33","M33_DSP_FP"),
+ ("VHT_M33","M33_DSP_FP"),
("VHT_M7","M7DP"),
("VHT_M7_UNROLLED","M7DP"),
- # #("VHT_M4","M4FP"),
+ ("VHT_M4","M4FP"),
# #("VHT_M3","M3"),
# #("VHT_M23","M23"),
("VHT_M0P","M0plus")
@@ -218,7 +218,7 @@ def runAVH(build,core):
##("VHT_M33","M33_DSP_FP"),
("VHT_M7","M7DP"),
("VHT_M7_UNROLLED","M7DP"),
- ##("VHT_M4","M4FP"),
+ ("VHT_M4","M4FP"),
##("VHT_M3","M3"),
##("VHT_M23","M23"),
("VHT_M0P","M0plus")
@@ -226,12 +226,14 @@ def runAVH(build,core):
}
# Override previous solutions for more restricted testing.
-solutions={
- 'test_ac6.csolution.yml':[
- # ("VHT-Corstone-310","CS310"),
- ("VHT-Corstone-300","CS300"),
- ]
-}
+#solutions={
+# 'test_ac6.csolution.yml':[
+# # ("VHT-Corstone-310","CS310"),
+# ("VHT_M7","M7DP"),
+# ("VHT_M7_UNROLLED","M7DP"),
+# ("VHT_M0P","M0plus")
+# ]
+#}
HTMLHEADER="""
diff --git a/Testing/cmsis_build/test.Release+VHT-Corstone-300.cprj b/Testing/cmsis_build/test.Release+VHT-Corstone-300.cprj
index 80a90d2fb..f1a0051ca 100644
--- a/Testing/cmsis_build/test.Release+VHT-Corstone-300.cprj
+++ b/Testing/cmsis_build/test.Release+VHT-Corstone-300.cprj
@@ -1,6 +1,6 @@
-
+
Automatically generated project
@@ -12,7 +12,7 @@
-
+
diff --git a/Testing/cmsis_build/test.Release+VHT-Corstone-310.cprj b/Testing/cmsis_build/test.Release+VHT-Corstone-310.cprj
index 4cc5eb641..3fd160489 100644
--- a/Testing/cmsis_build/test.Release+VHT-Corstone-310.cprj
+++ b/Testing/cmsis_build/test.Release+VHT-Corstone-310.cprj
@@ -1,6 +1,6 @@
-
+
Automatically generated project
@@ -13,7 +13,7 @@
-
+
diff --git a/Testing/cmsis_build/test.Release+VHT_M0P.cprj b/Testing/cmsis_build/test.Release+VHT_M0P.cprj
index c810c24af..a9da1994b 100644
--- a/Testing/cmsis_build/test.Release+VHT_M0P.cprj
+++ b/Testing/cmsis_build/test.Release+VHT_M0P.cprj
@@ -1,6 +1,6 @@
-
+
Automatically generated project
@@ -11,7 +11,7 @@
-
+
diff --git a/Testing/cmsis_build/test.Release+VHT_M23.cprj b/Testing/cmsis_build/test.Release+VHT_M23.cprj
index 6257b68a8..7efe783ee 100644
--- a/Testing/cmsis_build/test.Release+VHT_M23.cprj
+++ b/Testing/cmsis_build/test.Release+VHT_M23.cprj
@@ -1,6 +1,6 @@
-
+
Automatically generated project
@@ -11,7 +11,7 @@
-
+
diff --git a/Testing/cmsis_build/test.Release+VHT_M3.cprj b/Testing/cmsis_build/test.Release+VHT_M3.cprj
index b59509fc1..8491f3f17 100644
--- a/Testing/cmsis_build/test.Release+VHT_M3.cprj
+++ b/Testing/cmsis_build/test.Release+VHT_M3.cprj
@@ -1,6 +1,6 @@
-
+
Automatically generated project
@@ -11,7 +11,7 @@
-
+
diff --git a/Testing/cmsis_build/test.Release+VHT_M33.cprj b/Testing/cmsis_build/test.Release+VHT_M33.cprj
index 35d7afc18..f9237c464 100644
--- a/Testing/cmsis_build/test.Release+VHT_M33.cprj
+++ b/Testing/cmsis_build/test.Release+VHT_M33.cprj
@@ -1,6 +1,6 @@
-
+
Automatically generated project
@@ -11,7 +11,7 @@
-
+
diff --git a/Testing/cmsis_build/test.Release+VHT_M4.cprj b/Testing/cmsis_build/test.Release+VHT_M4.cprj
index 938ff7661..7f56a5c73 100644
--- a/Testing/cmsis_build/test.Release+VHT_M4.cprj
+++ b/Testing/cmsis_build/test.Release+VHT_M4.cprj
@@ -1,6 +1,6 @@
-
+
Automatically generated project
@@ -11,7 +11,7 @@
-
+
diff --git a/Testing/cmsis_build/test.Release+VHT_M55.cprj b/Testing/cmsis_build/test.Release+VHT_M55.cprj
index 86f181e4d..3cd873573 100644
--- a/Testing/cmsis_build/test.Release+VHT_M55.cprj
+++ b/Testing/cmsis_build/test.Release+VHT_M55.cprj
@@ -1,6 +1,6 @@
-
-
+
+
Automatically generated project
@@ -14,8 +14,8 @@
-
-
+
+
@@ -28,6 +28,7 @@
+
diff --git a/Testing/cmsis_build/test.Release+VHT_M7.cprj b/Testing/cmsis_build/test.Release+VHT_M7.cprj
index 1a35dead9..dffaa0c9b 100644
--- a/Testing/cmsis_build/test.Release+VHT_M7.cprj
+++ b/Testing/cmsis_build/test.Release+VHT_M7.cprj
@@ -1,6 +1,6 @@
-
+
Automatically generated project
@@ -11,7 +11,7 @@
-
+
diff --git a/Testing/cmsis_build/test.Release+VHT_M7_UNROLLED.cprj b/Testing/cmsis_build/test.Release+VHT_M7_UNROLLED.cprj
index 2de92d347..1baacffa9 100644
--- a/Testing/cmsis_build/test.Release+VHT_M7_UNROLLED.cprj
+++ b/Testing/cmsis_build/test.Release+VHT_M7_UNROLLED.cprj
@@ -1,6 +1,6 @@
-
+
Automatically generated project
@@ -11,7 +11,7 @@
-
+
diff --git a/Testing/cmsis_build/test_ac6.csolution.yml b/Testing/cmsis_build/test_ac6.csolution.yml
index b5493bd27..875349eb8 100644
--- a/Testing/cmsis_build/test_ac6.csolution.yml
+++ b/Testing/cmsis_build/test_ac6.csolution.yml
@@ -1,5 +1,5 @@
solution:
- compiler: AC6@6.18.0
+ compiler: AC6@6.20.100
misc:
- C:
- -Wsign-compare