diff --git a/ARM.CMSIS-DSP.pdsc b/ARM.CMSIS-DSP.pdsc index a09118d0a..a4fbcfdfc 100644 --- a/ARM.CMSIS-DSP.pdsc +++ b/ARM.CMSIS-DSP.pdsc @@ -41,7 +41,7 @@ - + CMSIS-DSP Library for Cortex-M and Cortex-A diff --git a/Examples/ARM/arm_bayes_example/arm_bayes_example.uvprojx b/Examples/ARM/arm_bayes_example/arm_bayes_example.uvprojx index 257385877..f3a049edd 100644 --- a/Examples/ARM/arm_bayes_example/arm_bayes_example.uvprojx +++ b/Examples/ARM/arm_bayes_example/arm_bayes_example.uvprojx @@ -10,7 +10,7 @@ ARMCM0 0x4 ARM-ADS - 6180000::V6.18::..\..\Program Files (x86)\ArmCompilerforEmbedded6.18 + 6220000::V6.22::..\..\Program Files\ArmCompilerforEmbedded6.22 1 @@ -374,7 +374,7 @@ .\RTE\Device\ARMCM0\ARMCM0_ac6.sct - + --entry=Reset_Handler @@ -777,7 +777,7 @@ .\RTE\Device\ARMCM3\ARMCM3_ac6.sct - + --entry=Reset_Handler @@ -939,7 +939,7 @@ 0 0 1 - 0 + 1 4096 1 @@ -1180,7 +1180,7 @@ .\RTE\Device\ARMCM4_FP\ARMCM4_ac6.sct - + --entry=Reset_Handler @@ -1342,7 +1342,7 @@ 0 0 1 - 0 + 1 4096 1 @@ -1583,7 +1583,7 @@ .\RTE\Device\ARMCM7_SP\ARMCM7_ac6.sct - + --entry=Reset_Handler @@ -1986,7 +1986,7 @@ .\RTE\Device\ARMCM55\ARMCM55_ac6.sct - + --entry=Reset_Handler diff --git a/Examples/ARM/arm_class_marks_example/arm_class_marks_example.uvprojx b/Examples/ARM/arm_class_marks_example/arm_class_marks_example.uvprojx index 32bee7c7d..28fc2c6fb 100644 --- a/Examples/ARM/arm_class_marks_example/arm_class_marks_example.uvprojx +++ b/Examples/ARM/arm_class_marks_example/arm_class_marks_example.uvprojx @@ -374,7 +374,7 @@ .\RTE\Device\ARMCM0\ARMCM0_ac6.sct - + --entry=Reset_Handler @@ -777,7 +777,7 @@ .\RTE\Device\ARMCM3\ARMCM3_ac6.sct - + --entry=Reset_Handler @@ -1180,7 +1180,7 @@ .\RTE\Device\ARMCM4_FP\ARMCM4_ac6.sct - + --entry=Reset_Handler @@ -1583,7 +1583,7 @@ .\RTE\Device\ARMCM7_SP\ARMCM7_ac6.sct - + --entry=Reset_Handler @@ -1986,7 +1986,7 @@ .\RTE\Device\ARMCM55\ARMCM55_ac6.sct - + --entry=Reset_Handler diff --git a/Examples/ARM/arm_convolution_example/arm_convolution_example.uvprojx b/Examples/ARM/arm_convolution_example/arm_convolution_example.uvprojx index ad6fcfa04..b66e92bd0 100644 --- a/Examples/ARM/arm_convolution_example/arm_convolution_example.uvprojx +++ b/Examples/ARM/arm_convolution_example/arm_convolution_example.uvprojx @@ -374,7 +374,7 @@ .\RTE\Device\ARMCM0\ARMCM0_ac6.sct - + --entry=Reset_Handler @@ -782,7 +782,7 @@ .\RTE\Device\ARMCM3\ARMCM3_ac6.sct - + --entry=Reset_Handler @@ -1190,7 +1190,7 @@ .\RTE\Device\ARMCM4_FP\ARMCM4_ac6.sct - + --entry=Reset_Handler @@ -1598,7 +1598,7 @@ .\RTE\Device\ARMCM7_SP\ARMCM7_ac6.sct - + --entry=Reset_Handler @@ -2006,7 +2006,7 @@ .\RTE\Device\ARMCM55\ARMCM55_ac6.sct - + --entry=Reset_Handler diff --git a/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example.uvprojx b/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example.uvprojx index 3f1d5ad61..7a593a15c 100644 --- a/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example.uvprojx +++ b/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example.uvprojx @@ -374,7 +374,7 @@ .\RTE\Device\ARMCM0\ARMCM0_ac6.sct - + --entry=Reset_Handler @@ -777,7 +777,7 @@ .\RTE\Device\ARMCM3\ARMCM3_ac6.sct - + --entry=Reset_Handler @@ -1180,7 +1180,7 @@ .\RTE\Device\ARMCM4_FP\ARMCM4_ac6.sct - + --entry=Reset_Handler @@ -1583,7 +1583,7 @@ .\RTE\Device\ARMCM7_SP\ARMCM7_ac6.sct - + --entry=Reset_Handler @@ -1986,7 +1986,7 @@ .\RTE\Device\ARMCM55\ARMCM55_ac6.sct - + --entry=Reset_Handler diff --git a/Examples/ARM/arm_fft_bin_example/arm_fft_bin_example.uvprojx b/Examples/ARM/arm_fft_bin_example/arm_fft_bin_example.uvprojx index e57e720dc..f43b9aa76 100644 --- a/Examples/ARM/arm_fft_bin_example/arm_fft_bin_example.uvprojx +++ b/Examples/ARM/arm_fft_bin_example/arm_fft_bin_example.uvprojx @@ -374,7 +374,7 @@ .\RTE\Device\ARMCM0\ARMCM0_ac6.sct - + --entry=Reset_Handler @@ -782,7 +782,7 @@ .\RTE\Device\ARMCM3\ARMCM3_ac6.sct - + --entry=Reset_Handler @@ -1190,7 +1190,7 @@ .\RTE\Device\ARMCM4_FP\ARMCM4_ac6.sct - + --entry=Reset_Handler @@ -1598,7 +1598,7 @@ .\RTE\Device\ARMCM7_SP\ARMCM7_ac6.sct - + --entry=Reset_Handler @@ -2006,7 +2006,7 @@ .\RTE\Device\ARMCM55\ARMCM55_ac6.sct - + --entry=Reset_Handler diff --git a/Examples/ARM/arm_fir_example/arm_fir_example.uvprojx b/Examples/ARM/arm_fir_example/arm_fir_example.uvprojx index f575b6515..0b68e4ae5 100644 --- a/Examples/ARM/arm_fir_example/arm_fir_example.uvprojx +++ b/Examples/ARM/arm_fir_example/arm_fir_example.uvprojx @@ -374,7 +374,7 @@ .\RTE\Device\ARMCM0\ARMCM0_ac6.sct - + --entry=Reset_Handler @@ -787,7 +787,7 @@ .\RTE\Device\ARMCM3\ARMCM3_ac6.sct - + --entry=Reset_Handler @@ -1200,7 +1200,7 @@ .\RTE\Device\ARMCM4_FP\ARMCM4_ac6.sct - + --entry=Reset_Handler @@ -1613,7 +1613,7 @@ .\RTE\Device\ARMCM7_SP\ARMCM7_ac6.sct - + --entry=Reset_Handler @@ -2026,7 +2026,7 @@ .\RTE\Device\ARMCM55\ARMCM55_ac6.sct - + --entry=Reset_Handler diff --git a/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_example.uvprojx b/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_example.uvprojx index 007931d14..daedc6b01 100644 --- a/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_example.uvprojx +++ b/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_example.uvprojx @@ -374,7 +374,7 @@ .\RTE\Device\ARMCM0\ARMCM0_ac6.sct - + --entry=Reset_Handler @@ -787,7 +787,7 @@ .\RTE\Device\ARMCM3\ARMCM3_ac6.sct - + --entry=Reset_Handler @@ -1200,7 +1200,7 @@ .\RTE\Device\ARMCM4_FP\ARMCM4_ac6.sct - + --entry=Reset_Handler @@ -1613,7 +1613,7 @@ .\RTE\Device\ARMCM7_SP\ARMCM7_ac6.sct - + --entry=Reset_Handler @@ -2026,7 +2026,7 @@ .\RTE\Device\ARMCM55\ARMCM55_ac6.sct - + --entry=Reset_Handler diff --git a/Examples/ARM/arm_linear_interp_example/arm_linear_interp_example.uvprojx b/Examples/ARM/arm_linear_interp_example/arm_linear_interp_example.uvprojx index 0db837c1c..1b478d421 100644 --- a/Examples/ARM/arm_linear_interp_example/arm_linear_interp_example.uvprojx +++ b/Examples/ARM/arm_linear_interp_example/arm_linear_interp_example.uvprojx @@ -374,7 +374,7 @@ .\RTE\Device\ARMCM0\ARMCM0_ac6.sct - + --entry=Reset_Handler @@ -787,7 +787,7 @@ .\RTE\Device\ARMCM3\ARMCM3_ac6.sct - + --entry=Reset_Handler @@ -1200,7 +1200,7 @@ .\RTE\Device\ARMCM4_FP\ARMCM4_ac6.sct - + --entry=Reset_Handler @@ -1613,7 +1613,7 @@ .\RTE\Device\ARMCM7_SP\ARMCM7_ac6.sct - + --entry=Reset_Handler @@ -2026,7 +2026,7 @@ .\RTE\Device\ARMCM55\ARMCM55_ac6.sct - + --entry=Reset_Handler diff --git a/Examples/ARM/arm_matrix_example/arm_matrix_example.uvprojx b/Examples/ARM/arm_matrix_example/arm_matrix_example.uvprojx index 6447efb59..be5c9e9d1 100644 --- a/Examples/ARM/arm_matrix_example/arm_matrix_example.uvprojx +++ b/Examples/ARM/arm_matrix_example/arm_matrix_example.uvprojx @@ -374,7 +374,7 @@ .\RTE\Device\ARMCM0\ARMCM0_ac6.sct - + --entry=Reset_Handler @@ -782,7 +782,7 @@ .\RTE\Device\ARMCM3\ARMCM3_ac6.sct - + --entry=Reset_Handler @@ -1190,7 +1190,7 @@ .\RTE\Device\ARMCM4_FP\ARMCM4_ac6.sct - + --entry=Reset_Handler @@ -1598,7 +1598,7 @@ .\RTE\Device\ARMCM7_SP\ARMCM7_ac6.sct - + --entry=Reset_Handler @@ -2006,7 +2006,7 @@ .\RTE\Device\ARMCM55\ARMCM55_ac6.sct - + --entry=Reset_Handler diff --git a/Examples/ARM/arm_signal_converge_example/arm_signal_converge_example.uvprojx b/Examples/ARM/arm_signal_converge_example/arm_signal_converge_example.uvprojx index f0976d5b1..8bbc65136 100644 --- a/Examples/ARM/arm_signal_converge_example/arm_signal_converge_example.uvprojx +++ b/Examples/ARM/arm_signal_converge_example/arm_signal_converge_example.uvprojx @@ -374,7 +374,7 @@ .\RTE\Device\ARMCM0\ARMCM0_ac6.sct - + --entry=Reset_Handler @@ -787,7 +787,7 @@ .\RTE\Device\ARMCM3\ARMCM3_ac6.sct - + --entry=Reset_Handler @@ -1200,7 +1200,7 @@ .\RTE\Device\ARMCM4_FP\ARMCM4_ac6.sct - + --entry=Reset_Handler @@ -1613,7 +1613,7 @@ .\RTE\Device\ARMCM7_SP\ARMCM7_ac6.sct - + --entry=Reset_Handler @@ -2026,7 +2026,7 @@ .\RTE\Device\ARMCM55\ARMCM55_ac6.sct - + --entry=Reset_Handler diff --git a/Examples/ARM/arm_sin_cos_example/arm_sin_cos_example.uvprojx b/Examples/ARM/arm_sin_cos_example/arm_sin_cos_example.uvprojx index 431e5bdc6..28a6f6e0b 100644 --- a/Examples/ARM/arm_sin_cos_example/arm_sin_cos_example.uvprojx +++ b/Examples/ARM/arm_sin_cos_example/arm_sin_cos_example.uvprojx @@ -374,7 +374,7 @@ .\RTE\Device\ARMCM0\ARMCM0_ac6.sct - + --entry=Reset_Handler @@ -777,7 +777,7 @@ .\RTE\Device\ARMCM3\ARMCM3_ac6.sct - + --entry=Reset_Handler @@ -1180,7 +1180,7 @@ .\RTE\Device\ARMCM4_FP\ARMCM4_ac6.sct - + --entry=Reset_Handler @@ -1583,7 +1583,7 @@ .\RTE\Device\ARMCM7_SP\ARMCM7_ac6.sct - + --entry=Reset_Handler @@ -1986,7 +1986,7 @@ .\RTE\Device\ARMCM55\ARMCM55_ac6.sct - + --entry=Reset_Handler diff --git a/Examples/ARM/arm_svm_example/arm_svm_example.uvprojx b/Examples/ARM/arm_svm_example/arm_svm_example.uvprojx index 027075cdf..b86f3f954 100644 --- a/Examples/ARM/arm_svm_example/arm_svm_example.uvprojx +++ b/Examples/ARM/arm_svm_example/arm_svm_example.uvprojx @@ -374,7 +374,7 @@ .\RTE\Device\ARMCM0\ARMCM0_ac6.sct - + --entry=Reset_Handler @@ -777,7 +777,7 @@ .\RTE\Device\ARMCM3\ARMCM3_ac6.sct - + --entry=Reset_Handler @@ -1180,7 +1180,7 @@ .\RTE\Device\ARMCM4_FP\ARMCM4_ac6.sct - + --entry=Reset_Handler @@ -1583,7 +1583,7 @@ .\RTE\Device\ARMCM7_SP\ARMCM7_ac6.sct - + --entry=Reset_Handler @@ -1986,7 +1986,7 @@ .\RTE\Device\ARMCM55\ARMCM55_ac6.sct - + --entry=Reset_Handler diff --git a/Examples/ARM/arm_variance_example/arm_variance_example.uvprojx b/Examples/ARM/arm_variance_example/arm_variance_example.uvprojx index 28bd2f3fe..57f08d186 100644 --- a/Examples/ARM/arm_variance_example/arm_variance_example.uvprojx +++ b/Examples/ARM/arm_variance_example/arm_variance_example.uvprojx @@ -374,7 +374,7 @@ .\RTE\Device\ARMCM0\ARMCM0_ac6.sct - + --entry=Reset_Handler @@ -777,7 +777,7 @@ .\RTE\Device\ARMCM3\ARMCM3_ac6.sct - + --entry=Reset_Handler @@ -1180,7 +1180,7 @@ .\RTE\Device\ARMCM4_FP\ARMCM4_ac6.sct - + --entry=Reset_Handler @@ -1583,7 +1583,7 @@ .\RTE\Device\ARMCM7_SP\ARMCM7_ac6.sct - + --entry=Reset_Handler @@ -1986,7 +1986,7 @@ .\RTE\Device\ARMCM55\ARMCM55_ac6.sct - + --entry=Reset_Handler diff --git a/Examples/cmsis_build/.gitignore b/Examples/cmsis_build/.gitignore index bbf5bce92..2c0580ec1 100644 --- a/Examples/cmsis_build/.gitignore +++ b/Examples/cmsis_build/.gitignore @@ -4,3 +4,7 @@ .*@* *.cbuild.yml *.bat +*.cbuild-pack.yml +cprj/examples_ac6.cbuild-idx.yml +cprj/out/ +cprj/tmp/ diff --git a/Examples/cmsis_build/RTE/Device/ARMCM0P/ARMCM0plus_ac6.sct b/Examples/cmsis_build/RTE/Device/ARMCM0P/ARMCM0plus_ac6.sct deleted file mode 100644 index 447f91282..000000000 --- a/Examples/cmsis_build/RTE/Device/ARMCM0P/ARMCM0plus_ac6.sct +++ /dev/null @@ -1,76 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m0+ -xc -; command above MUST be in first line (no comment above!) - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - - -/*---------------------------------------------------------------------------- - Scatter File Definitions definition - *----------------------------------------------------------------------------*/ -#define __RO_BASE __ROM_BASE -#define __RO_SIZE __ROM_SIZE - -#define __RW_BASE __RAM_BASE -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) - - -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_RAM __RW_BASE __RW_SIZE { ; RW data - .ANY (+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } -} diff --git a/Examples/cmsis_build/RTE/Device/ARMCM0P/startup_ARMCM0plus.c b/Examples/cmsis_build/RTE/Device/ARMCM0P/startup_ARMCM0plus.c deleted file mode 100644 index 76d1fa885..000000000 --- a/Examples/cmsis_build/RTE/Device/ARMCM0P/startup_ARMCM0plus.c +++ /dev/null @@ -1,148 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM0plus.c - * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0+ Device - * @version V2.0.3 - * @date 31. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM0P) - #include "ARMCM0plus.h" -#elif defined (ARMCM0P_MPU) - #include "ARMCM0plus_MPU.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; - const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVCall Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10..31 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/Examples/cmsis_build/RTE/Device/ARMCM0P/system_ARMCM0plus.c b/Examples/cmsis_build/RTE/Device/ARMCM0P/system_ARMCM0plus.c deleted file mode 100644 index 3bde8e11b..000000000 --- a/Examples/cmsis_build/RTE/Device/ARMCM0P/system_ARMCM0plus.c +++ /dev/null @@ -1,61 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM0plus.c - * @brief CMSIS Device System Source File for - * ARMCM0plus Device - * @version V1.0.0 - * @date 09. July 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "ARMCM0plus.h" - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/Examples/cmsis_build/RTE/Device/ARMCM7_DP/ARMCM7_ac6.sct b/Examples/cmsis_build/RTE/Device/ARMCM7_DP/ARMCM7_ac6.sct deleted file mode 100644 index e1b77e51e..000000000 --- a/Examples/cmsis_build/RTE/Device/ARMCM7_DP/ARMCM7_ac6.sct +++ /dev/null @@ -1,76 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m7 -xc -; command above MUST be in first line (no comment above!) - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - - -/*---------------------------------------------------------------------------- - Scatter File Definitions definition - *----------------------------------------------------------------------------*/ -#define __RO_BASE __ROM_BASE -#define __RO_SIZE __ROM_SIZE - -#define __RW_BASE __RAM_BASE -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) - - -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_RAM __RW_BASE __RW_SIZE { ; RW data - .ANY (+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } -} diff --git a/Examples/cmsis_build/RTE/Device/ARMCM7_DP/startup_ARMCM7.c b/Examples/cmsis_build/RTE/Device/ARMCM7_DP/startup_ARMCM7.c deleted file mode 100644 index 509cd3387..000000000 --- a/Examples/cmsis_build/RTE/Device/ARMCM7_DP/startup_ARMCM7.c +++ /dev/null @@ -1,154 +0,0 @@ -/****************************************************************************** - * @file startup_ARMCM7.c - * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device - * @version V2.0.3 - * @date 31. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM7) - #include "ARMCM7.h" -#elif defined (ARMCM7_SP) - #include "ARMCM7_SP.h" -#elif defined (ARMCM7_DP) - #include "ARMCM7_DP.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - Interrupt0_Handler, /* 0 Interrupt 0 */ - Interrupt1_Handler, /* 1 Interrupt 1 */ - Interrupt2_Handler, /* 2 Interrupt 2 */ - Interrupt3_Handler, /* 3 Interrupt 3 */ - Interrupt4_Handler, /* 4 Interrupt 4 */ - Interrupt5_Handler, /* 5 Interrupt 5 */ - Interrupt6_Handler, /* 6 Interrupt 6 */ - Interrupt7_Handler, /* 7 Interrupt 7 */ - Interrupt8_Handler, /* 8 Interrupt 8 */ - Interrupt9_Handler /* 9 Interrupt 9 */ - /* Interrupts 10 .. 223 are left out */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif - diff --git a/Examples/cmsis_build/RTE/Device/ARMCM7_DP/system_ARMCM7.c b/Examples/cmsis_build/RTE/Device/ARMCM7_DP/system_ARMCM7.c deleted file mode 100644 index 75f9c18eb..000000000 --- a/Examples/cmsis_build/RTE/Device/ARMCM7_DP/system_ARMCM7.c +++ /dev/null @@ -1,83 +0,0 @@ -/**************************************************************************//** - * @file system_ARMCM7.c - * @brief CMSIS Device System Source File for - * ARMCM7 Device - * @version V1.0.1 - * @date 15. November 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined (ARMCM7) - #include "ARMCM7.h" -#elif defined (ARMCM7_SP) - #include "ARMCM7_SP.h" -#elif defined (ARMCM7_DP) - #include "ARMCM7_DP.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; - - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - -#if defined (__FPU_USED) && (__FPU_USED == 1U) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/Examples/cmsis_build/RTE/Device/SSE-300-MPS3/RTE_Device.h b/Examples/cmsis_build/RTE/Device/SSE-300-MPS3/RTE_Device.h index 5bf4c867c..31255472f 100644 --- a/Examples/cmsis_build/RTE/Device/SSE-300-MPS3/RTE_Device.h +++ b/Examples/cmsis_build/RTE/Device/SSE-300-MPS3/RTE_Device.h @@ -27,51 +27,51 @@ // MPC (Memory Protection Controller) [Driver_ISRAM0_MPC] // Configuration settings for Driver_ISRAM0_MPC in component ::Drivers:MPC -#define RTE_ISRAM0_MPC 1 +#define RTE_ISRAM0_MPC 0 // MPC (Memory Protection Controller) [Driver_ISRAM1_MPC] // Configuration settings for Driver_ISRAM1_MPC in component ::Drivers:MPC -#define RTE_ISRAM1_MPC 1 +#define RTE_ISRAM1_MPC 0 // MPC (Memory Protection Controller) [Driver_SRAM_MPC] // Configuration settings for Driver_SRAM_MPC in component ::Drivers:MPC -#define RTE_SRAM_MPC 1 +#define RTE_SRAM_MPC 0 // MPC (Memory Protection Controller) [Driver_QSPI_MPC] // Configuration settings for Driver_QSPI_MPC in component ::Drivers:MPC -#define RTE_QSPI_MPC 1 +#define RTE_QSPI_MPC 0 // PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN0] // Configuration settings for Driver_PPC_SSE300_MAIN0 in component ::Drivers:PPC -#define RTE_PPC_SSE300_MAIN0 1 +#define RTE_PPC_SSE300_MAIN0 0 // PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP0] // Configuration settings for Driver_PPC_SSE300_MAIN_EXP0 in component ::Drivers:PPC -#define RTE_PPC_SSE300_MAIN_EXP0 1 +#define RTE_PPC_SSE300_MAIN_EXP0 0 // PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP1] // Configuration settings for Driver_PPC_SSE300_MAIN_EXP1 in component ::Drivers:PPC -#define RTE_PPC_SSE300_MAIN_EXP1 1 +#define RTE_PPC_SSE300_MAIN_EXP1 0 // PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH0] // Configuration settings for Driver_PPC_SSE300_PERIPH0 in component ::Drivers:PPC -#define RTE_PPC_SSE300_PERIPH0 1 +#define RTE_PPC_SSE300_PERIPH0 0 // PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH1] // Configuration settings for Driver_PPC_SSE300_PERIPH1 in component ::Drivers:PPC -#define RTE_PPC_SSE300_PERIPH1 1 +#define RTE_PPC_SSE300_PERIPH1 0 // PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP0] // Configuration settings for Driver_PPC_SSE300_PERIPH_EXP0 in component ::Drivers:PPC -#define RTE_PPC_SSE300_PERIPH_EXP0 1 +#define RTE_PPC_SSE300_PERIPH_EXP0 0 // PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP1] // Configuration settings for Driver_PPC_SSE300_PERIPH_EXP1 in component ::Drivers:PPC -#define RTE_PPC_SSE300_PERIPH_EXP1 1 +#define RTE_PPC_SSE300_PERIPH_EXP1 0 // PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP2] // Configuration settings for Driver_PPC_SSE300_PERIPH_EXP2 in component ::Drivers:PPC -#define RTE_PPC_SSE300_PERIPH_EXP2 1 +#define RTE_PPC_SSE300_PERIPH_EXP2 0 // Flash device emulated by SRAM [Driver_Flash0] // Configuration settings for Driver_Flash0 in component ::Drivers:Flash diff --git a/Examples/cmsis_build/RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct b/Examples/cmsis_build/RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct deleted file mode 100644 index 343c63d26..000000000 --- a/Examples/cmsis_build/RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct +++ /dev/null @@ -1,78 +0,0 @@ -#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc - -;/* -; * Copyright (c) 2018-2021 Arm Limited. All rights reserved. -; * -; * Licensed under the Apache License, Version 2.0 (the "License"); -; * you may not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * http://www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an "AS IS" BASIS, -; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; * -; */ - -#include "region_defs.h" - -LR_CODE S_CODE_START { - ER_CODE S_CODE_START { - *.o (RESET +First) - .ANY (+RO) - } - - /* - * Place the CMSE Veneers (containing the SG instruction) after the code, in - * a separate 32 bytes aligned region so that the SAU can programmed to just - * set this region as Non-Secure Callable. The maximum size of this - * executable region makes it only used the space left over by the ER_CODE - * region so that you can rely on code+veneer size combined will not exceed - * the S_CODE_SIZE value. We also substract from the available space the - * area used to align this section on 32 bytes boundary (for SAU conf). - */ - ER_CODE_CMSE_VENEER +0 ALIGN 32 { - *(Veneer$$CMSE) - } - /* - * This dummy region ensures that the next one will be aligned on a 32 bytes - * boundary, so that the following region will not be mistakenly configured - * as Non-Secure Callable by the SAU. - */ - ER_CODE_CMSE_VENEER_DUMMY +0 ALIGN 32 EMPTY 0 {} - - /* This empty, zero long execution region is here to mark the limit address - * of the last execution region that is allocated in SRAM. - */ - CODE_WATERMARK +0 EMPTY 0x0 { - } - /* Make sure that the sections allocated in the SRAM does not exceed the - * size of the SRAM available. - */ - ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE) - - ER_DATA S_DATA_START { - .ANY (+ZI +RW) - } - - #if HEAP_SIZE > 0 - ARM_LIB_HEAP +0 ALIGN 8 EMPTY HEAP_SIZE { ; Reserve empty region for heap - } - #endif - - ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE { ; Reserve empty region for stack - } - - /* This empty, zero long execution region is here to mark the limit address - * of the last execution region that is allocated in SRAM. - */ - SRAM_WATERMARK +0 EMPTY 0x0 { - } - /* Make sure that the sections allocated in the SRAM does not exceed the - * size of the SRAM available. - */ - ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE) -} diff --git a/Examples/cmsis_build/RTE/Device/SSE-310-MPS3/corstone310_mps3_s.sct b/Examples/cmsis_build/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct similarity index 91% rename from Examples/cmsis_build/RTE/Device/SSE-310-MPS3/corstone310_mps3_s.sct rename to Examples/cmsis_build/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct index 8a1976b06..8b95c189d 100644 --- a/Examples/cmsis_build/RTE/Device/SSE-310-MPS3/corstone310_mps3_s.sct +++ b/Examples/cmsis_build/RTE/Device/SSE-300-MPS3/linker_SSE300MPS3_secure.sct @@ -1,7 +1,7 @@ #! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc ;/* -; * Copyright (c) 2018-2021 Arm Limited +; * Copyright (c) 2018-2023 Arm Limited ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); ; * you may not use this file except in compliance with the License. @@ -44,7 +44,10 @@ LR_CODE S_CODE_START { } #endif - ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE { ; Reserve empty region for stack + ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE - 0x8 { ; Reserve empty region for stack + } + + STACKSEAL +0 EMPTY 0x8 { } /* This empty, zero long execution region is here to mark the limit address diff --git a/Examples/cmsis_build/RTE/Device/SSE-300-MPS3/platform_base_address.h b/Examples/cmsis_build/RTE/Device/SSE-300-MPS3/platform_base_address.h deleted file mode 100644 index b813097f5..000000000 --- a/Examples/cmsis_build/RTE/Device/SSE-300-MPS3/platform_base_address.h +++ /dev/null @@ -1,271 +0,0 @@ -/* - * Copyright (c) 2019-2021 Arm Limited - * - * Licensed under the Apache License Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing software - * distributed under the License is distributed on an "AS IS" BASIS - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/** - * \file platform_base_address.h - * \brief This file defines all the peripheral base addresses for AN552 MPS3 SSE-300 + - * Ethos-U55 platform. - */ - -#ifndef __PLATFORM_BASE_ADDRESS_H__ -#define __PLATFORM_BASE_ADDRESS_H__ - -/* ======= Defines peripherals memory map addresses ======= */ -/* Non-secure memory map addresses */ -#define ITCM_BASE_NS 0x00000000 /* Instruction TCM Non-Secure base address */ -#define SRAM_BASE_NS 0x01000000 /* CODE SRAM Non-Secure base address */ -#define DTCM0_BASE_NS 0x20000000 /* Data TCM block 0 Non-Secure base address */ -#define DTCM1_BASE_NS 0x20020000 /* Data TCM block 1 Non-Secure base address */ -#define DTCM2_BASE_NS 0x20040000 /* Data TCM block 2 Non-Secure base address */ -#define DTCM3_BASE_NS 0x20060000 /* Data TCM block 3 Non-Secure base address */ -#define ISRAM0_BASE_NS 0x21000000 /* Internal SRAM Area Non-Secure base address */ -#define ISRAM1_BASE_NS 0x21100000 /* Internal SRAM Area Non-Secure base address */ -#define QSPI_SRAM_BASE_NS 0x28000000 /* QSPI SRAM Non-Secure base address */ -/* Non-Secure Subsystem peripheral region */ -#define CPU0_PWRCTRL_BASE_NS 0x40012000 /* CPU 0 Power Control Block Non-Secure base address */ -#define CPU0_IDENTITY_BASE_NS 0x4001F000 /* CPU 0 Identity Block Non-Secure base address */ -#define SSE300_NSACFG_BASE_NS 0x40080000 /* SSE-300 Non-Secure Access Configuration Register Block Non-Secure base address */ -/* Non-Secure MSTEXPPILL Peripheral region */ -#define GPIO0_CMSDK_BASE_NS 0x41100000 /* GPIO 0 Non-Secure base address */ -#define GPIO1_CMSDK_BASE_NS 0x41101000 /* GPIO 1 Non-Secure base address */ -#define GPIO2_CMSDK_BASE_NS 0x41102000 /* GPIO 2 Non-Secure base address */ -#define GPIO3_CMSDK_BASE_NS 0x41103000 /* GPIO 3 Non-Secure base address */ -#define FMC_CMSDK_GPIO_0_BASE_NS 0x41104000 /* FMC CMSDK GPIO 0 Non-Secure base address */ -#define FMC_CMSDK_GPIO_1_BASE_NS 0x41105000 /* FMC CMSDK GPIO 1 Non-Secure base address */ -#define FMC_CMSDK_GPIO_2_BASE_NS 0x41106000 /* FMC CMSDK GPIO 2 Non-Secure base address */ -#define FMC_CMSDK_GPIO_3_BASE_NS 0x41107000 /* FMC CMSDK GPIO 3 Non-Secure base address */ -#define EXTERNAL_MANAGER_0_BASE_NS 0x41200000 /* External manager 0 (Unused) Non-Secure base address */ -#define EXTERNAL_MANAGER_1_BASE_NS 0x41201000 /* External manager 1 (Unused) Non-Secure base address */ -#define EXTERNAL_MANAGER_2_BASE_NS 0x41202000 /* External manager 2 (Unused) Non-Secure base address */ -#define EXTERNAL_MANAGER_3_BASE_NS 0x41203000 /* External manager 3 (Unused) Non-Secure base address */ -#define ETHERNET_BASE_NS 0x41400000 /* Ethernet Non-Secure base address */ -#define USB_BASE_NS 0x41500000 /* USB Non-Secure base address */ -#define USER_APB0_BASE_NS 0x41700000 /* User APB 0 Non-Secure base address */ -#define USER_APB1_BASE_NS 0x41701000 /* User APB 1 Non-Secure base address */ -#define USER_APB2_BASE_NS 0x41702000 /* User APB 2 Non-Secure base address */ -#define USER_APB3_BASE_NS 0x41703000 /* User APB 3 Non-Secure base address */ -#define QSPI_CONFIG_BASE_NS 0x41800000 /* QSPI Config Non-Secure base address */ -#define QSPI_WRITE_BASE_NS 0x41801000 /* QSPI Write Non-Secure base address */ -/* Non-Secure Subsystem peripheral region */ -#define SYSTIMER0_ARMV8_M_BASE_NS 0x48000000 /* System Timer 0 Non-Secure base address */ -#define SYSTIMER1_ARMV8_M_BASE_NS 0x48001000 /* System Timer 1 Non-Secure base address */ -#define SYSTIMER2_ARMV8_M_BASE_NS 0x48002000 /* System Timer 2 Non-Secure base address */ -#define SYSTIMER3_ARMV8_M_BASE_NS 0x48003000 /* System Timer 3 Non-Secure base address */ -#define SSE300_SYSINFO_BASE_NS 0x48020000 /* SSE-300 System info Block Non-Secure base address */ -#define SLOWCLK_TIMER_CMSDK_BASE_NS 0x4802F000 /* CMSDK based SLOWCLK Timer Non-Secure base address */ -#define SYSWDOG_ARMV8_M_CNTRL_BASE_NS 0x48040000 /* Non-Secure Watchdog Timer control frame Non-Secure base address */ -#define SYSWDOG_ARMV8_M_REFRESH_BASE_NS 0x48041000 /* Non-Secure Watchdog Timer refresh frame Non-Secure base address */ -#define SYSCNTR_READ_BASE_NS 0x48101000 /* System Counter Read Secure base address */ -/* Non-Secure MSTEXPPIHL Peripheral region */ -#define ETHOS_U55_APB_BASE_NS 0x48102000 /* Ethos-U55 APB Non-Secure base address */ -#define U55_TIMING_ADAPTER_0_BASE_NS 0x48103000 /* Ethos-U55 Timing Adapter 0 APB registers Non-Secure base address */ -#define U55_TIMING_ADAPTER_1_BASE_NS 0x48103200 /* Ethos-U55 Timing Adapter 1 APB registers Non-Secure base address */ -#define FPGA_SBCon_I2C_TOUCH_BASE_NS 0x49200000 /* FPGA - SBCon I2C (Touch) Non-Secure base address */ -#define FPGA_SBCon_I2C_AUDIO_BASE_NS 0x49201000 /* FPGA - SBCon I2C (Audio Conf) Non-Secure base address */ -#define FPGA_SPI_ADC_BASE_NS 0x49202000 /* FPGA - PL022 (SPI ADC) Non-Secure base address */ -#define FPGA_SPI_SHIELD0_BASE_NS 0x49203000 /* FPGA - PL022 (SPI Shield0) Non-Secure base address */ -#define FPGA_SPI_SHIELD1_BASE_NS 0x49204000 /* FPGA - PL022 (SPI Shield1) Non-Secure base address */ -#define SBCon_I2C_SHIELD0_BASE_NS 0x49205000 /* SBCon (I2C - Shield0) Non-Secure base address */ -#define SBCon_I2C_SHIELD1_BASE_NS 0x49206000 /* SBCon (I2C – Shield1) Non-Secure base address */ -#define USER_APB_BASE_NS 0x49207000 /* USER APB Non-Secure base address */ -#define FPGA_DDR4_EEPROM_BASE_NS 0x49208000 /* FPGA - SBCon I2C (DDR4 EEPROM) Non-Secure base address */ -#define FMC_USER_APB0 0x4920C000 /* FMC User APB0 */ -#define FMC_USER_APB1 0x4920D000 /* FMC User APB1 */ -#define FMC_USER_APB2 0x4920E000 /* FMC User APB2 */ -#define FMC_USER_APB3 0x4920F000 /* FMC User APB3 */ -#define FPGA_SCC_BASE_NS 0x49300000 /* FPGA - SCC registers Non-Secure base address */ -#define FPGA_I2S_BASE_NS 0x49301000 /* FPGA - I2S (Audio) Non-Secure base address */ -#define FPGA_IO_BASE_NS 0x49302000 /* FPGA - IO (System Ctrl + I/O) Non-Secure base address */ -#define UART0_BASE_NS 0x49303000 /* UART 0 Non-Secure base address */ -#define UART1_BASE_NS 0x49304000 /* UART 1 Non-Secure base address */ -#define UART2_BASE_NS 0x49305000 /* UART 2 Non-Secure base address */ -#define UART3_BASE_NS 0x49306000 /* UART 3 Non-Secure base address */ -#define UART4_BASE_NS 0x49307000 /* UART 4 Non-Secure base address */ -#define UART5_BASE_NS 0x49308000 /* UART 5 Non-Secure base address */ -#define CLCD_Config_Reg_BASE_NS 0x4930A000 /* CLCD Config Reg Non-Secure base address */ -#define RTC_BASE_NS 0x4930B000 /* RTC Non-Secure base address */ -#define DDR4_BLK0_BASE_NS 0x60000000 /* DDR4 block 0 Non-Secure base address */ -#define DDR4_BLK2_BASE_NS 0x80000000 /* DDR4 block 2 Non-Secure base address */ -#define DDR4_BLK4_BASE_NS 0xA0000000 /* DDR4 block 4 Non-Secure base address */ -#define DDR4_BLK6_BASE_NS 0xC0000000 /* DDR4 block 6 Non-Secure base address */ - -/* Secure memory map addresses */ -#define ITCM_BASE_S 0x10000000 /* Instruction TCM Secure base address */ -#define SRAM_BASE_S 0x11000000 /* CODE SRAM Secure base address */ -#define DTCM0_BASE_S 0x30000000 /* Data TCM block 0 Secure base address */ -#define DTCM1_BASE_S 0x30020000 /* Data TCM block 1 Secure base address */ -#define DTCM2_BASE_S 0x30040000 /* Data TCM block 2 Secure base address */ -#define DTCM3_BASE_S 0x30060000 /* Data TCM block 3 Secure base address */ -#define ISRAM0_BASE_S 0x31000000 /* Internal SRAM Area Secure base address */ -#define ISRAM1_BASE_S 0x31100000 /* Internal SRAM Area Secure base address */ -#define QSPI_SRAM_BASE_S 0x38000000 /* QSPI SRAM Secure base address */ -/* Secure Subsystem peripheral region */ -#define CPU0_SECCTRL_BASE_S 0x50011000 /* CPU 0 Local Security Control Block Secure base address */ -#define CPU0_PWRCTRL_BASE_S 0x50012000 /* CPU 0 Power Control Block Secure base address */ -#define CPU0_IDENTITY_BASE_S 0x5001F000 /* CPU 0 Identity Block Secure base address */ -#define SSE300_SACFG_BASE_S 0x50080000 /* SSE-300 Secure Access Configuration Register Secure base address */ -#define MPC_ISRAM0_BASE_S 0x50083000 /* Internal SRAM0 Memory Protection Controller Secure base address */ -#define MPC_ISRAM1_BASE_S 0x50084000 /* Internal SRAM1 Memory Protection Controller Secure base address */ -/* Secure MSTEXPPILL Peripheral region */ -#define GPIO0_CMSDK_BASE_S 0x51100000 /* GPIO 0 Secure base address */ -#define GPIO1_CMSDK_BASE_S 0x51101000 /* GPIO 1 Secure base address */ -#define GPIO2_CMSDK_BASE_S 0x51102000 /* GPIO 2 Secure base address */ -#define GPIO3_CMSDK_BASE_S 0x51103000 /* GPIO 3 Secure base address */ -#define FMC_CMSDK_GPIO_0_BASE_S 0x51104000 /* FMC CMSDK GPIO 0 Secure base address */ -#define FMC_CMSDK_GPIO_1_BASE_S 0x51105000 /* FMC CMSDK GPIO 1 Secure base address */ -#define FMC_CMSDK_GPIO_2_BASE_S 0x51106000 /* FMC CMSDK GPIO 2 Secure base address */ -#define FMC_CMSDK_GPIO_3_BASE_S 0x51107000 /* FMC CMSDK GPIO 3 Secure base address */ -#define EXTERNAL_MANAGER0_BASE_S 0x51200000 /* External Manager 0 (Unused) Secure base address */ -#define EXTERNAL_MANAGER1_BASE_S 0x51201000 /* External Manager 1 (Unused) Secure base address */ -#define EXTERNAL_MANAGER2_BASE_S 0x51202000 /* External Manager 2 (Unused) Secure base address */ -#define EXTERNAL_MANAGER3_BASE_S 0x51203000 /* External Manager 3 (Unused) Secure base address */ -#define ETHERNET_BASE_S 0x51400000 /* Ethernet Secure base address */ -#define USB_BASE_S 0x51500000 /* USB Secure base address */ -#define USER_APB0_BASE_S 0x51700000 /* User APB 0 Secure base address */ -#define USER_APB1_BASE_S 0x51701000 /* User APB 1 Secure base address */ -#define USER_APB2_BASE_S 0x51702000 /* User APB 2 Secure base address */ -#define USER_APB3_BASE_S 0x51703000 /* User APB 3 Secure base address */ -#define QSPI_CONFIG_BASE_S 0x51800000 /* QSPI Config Secure base address */ -#define QSPI_WRITE_BASE_S 0x51801000 /* QSPI Write Secure base address */ -#define MPC_SRAM_BASE_S 0x57000000 /* SRAM Memory Protection Controller Secure base address */ -#define MPC_QSPI_BASE_S 0x57001000 /* QSPI Memory Protection Controller Secure base address */ -#define MPC_DDR4_BASE_S 0x57002000 /* DDR4 Memory Protection Controller Secure base address */ -/* Secure Subsystem peripheral region */ -#define SYSTIMER0_ARMV8_M_BASE_S 0x58000000 /* System Timer 0 Secure base address */ -#define SYSTIMER1_ARMV8_M_BASE_S 0x58001000 /* System Timer 1 Secure base address */ -#define SYSTIMER2_ARMV8_M_BASE_S 0x58002000 /* System Timer 0 Secure base address */ -#define SYSTIMER3_ARMV8_M_BASE_S 0x58003000 /* System Timer 1 Secure base address */ -#define SSE300_SYSINFO_BASE_S 0x58020000 /* SSE-300 System info Block Secure base address */ -#define SSE300_SYSCTRL_BASE_S 0x58021000 /* SSE-300 System control Block Secure base address */ -#define SSE300_SYSPPU_BASE_S 0x58022000 /* SSE-300 System Power Policy Unit Secure base address */ -#define SSE300_CPU0PPU_BASE_S 0x58023000 /* SSE-300 CPU 0 Power Policy Unit Secure base address */ -#define SSE300_MGMTPPU_BASE_S 0x58028000 /* SSE-300 Management Power Policy Unit Secure base address */ -#define SSE300_DBGPPU_BASE_S 0x58029000 /* SSE-300 Debug Power Policy Unit Secure base address */ -#define SLOWCLK_WDOG_CMSDK_BASE_S 0x5802E000 /* CMSDK based SLOWCLK Watchdog Secure base address */ -#define SLOWCLK_TIMER_CMSDK_BASE_S 0x5802F000 /* CMSDK based SLOWCLK Timer Secure base address */ -#define SYSWDOG_ARMV8_M_CNTRL_BASE_S 0x58040000 /* Secure Watchdog Timer control frame Secure base address */ -#define SYSWDOG_ARMV8_M_REFRESH_BASE_S 0x58041000 /* Secure Watchdog Timer refresh frame Secure base address */ -#define SYSCNTR_CNTRL_BASE_S 0x58100000 /* System Counter Control Secure base address */ -#define SYSCNTR_READ_BASE_S 0x58101000 /* System Counter Read Secure base address */ -/* Secure MSTEXPPIHL Peripheral region */ -#define ETHOS_U55_APB_BASE_S 0x58102000 /* Ethos-U55 APB Secure base address */ -#define U55_TIMING_ADAPTER_0_BASE_S 0x58103000 /* Ethos-U55 Timing Adapter 0 APB registers Secure base address */ -#define U55_TIMING_ADAPTER_1_BASE_S 0x58103200 /* Ethos-U55 Timing Adapter 1 APB registers Secure base address */ -#define FPGA_SBCon_I2C_TOUCH_BASE_S 0x59200000 /* FPGA - SBCon I2C (Touch) Secure base address */ -#define FPGA_SBCon_I2C_AUDIO_BASE_S 0x59201000 /* FPGA - SBCon I2C (Audio Conf) Secure base address */ -#define FPGA_SPI_ADC_BASE_S 0x59202000 /* FPGA - PL022 (SPI ADC) Secure base address */ -#define FPGA_SPI_SHIELD0_BASE_S 0x59203000 /* FPGA - PL022 (SPI Shield0) Secure base address */ -#define FPGA_SPI_SHIELD1_BASE_S 0x59204000 /* FPGA - PL022 (SPI Shield1) Secure base address */ -#define SBCon_I2C_SHIELD0_BASE_S 0x59205000 /* SBCon (I2C - Shield0) Secure base address */ -#define SBCon_I2C_SHIELD1_BASE_S 0x59206000 /* SBCon (I2C – Shield1) Secure base address */ -#define USER_APB_BASE_S 0x59207000 /* USER APB Secure base address */ -#define FPGA_DDR4_EEPROM_BASE_S 0x59208000 /* FPGA - SBCon I2C (DDR4 EEPROM) Secure base address */ -#define FMC_USER_APB_0_BASE_S 0x5920C000 /* FMC User APB0 registers Secure base address */ -#define FMC_USER_APB_1_BASE_S 0x5920D000 /* FMC User APB1 registers Secure base address */ -#define FMC_USER_APB_2_BASE_S 0x5920E000 /* FMC User APB2 registers Secure base address */ -#define FMC_USER_APB_3_BASE_S 0x5920F000 /* FMC User APB3 registers Secure base address */ -#define FPGA_SCC_BASE_S 0x59300000 /* FPGA - SCC registers Secure base address */ -#define FPGA_I2S_BASE_S 0x59301000 /* FPGA - I2S (Audio) Secure base address */ -#define FPGA_IO_BASE_S 0x59302000 /* FPGA - IO (System Ctrl + I/O) Secure base address */ -#define UART0_BASE_S 0x59303000 /* UART 0 Secure base address */ -#define UART1_BASE_S 0x59304000 /* UART 1 Secure base address */ -#define UART2_BASE_S 0x59305000 /* UART 2 Secure base address */ -#define UART3_BASE_S 0x59306000 /* UART 3 Secure base address */ -#define UART4_BASE_S 0x59307000 /* UART 4 Secure base address */ -#define UART5_BASE_S 0x59308000 /* UART 5 Secure base address */ -#define CLCD_Config_Reg_BASE_S 0x5930A000 /* CLCD Config Reg Secure base address */ -#define RTC_BASE_S 0x5930B000 /* RTC Secure base address */ -#define DDR4_BLK1_BASE_S 0x70000000 /* DDR4 block 1 Secure base address */ -#define DDR4_BLK3_BASE_S 0x90000000 /* DDR4 block 3 Secure base address */ -#define DDR4_BLK5_BASE_S 0xB0000000 /* DDR4 block 5 Secure base address */ -#define DDR4_BLK7_BASE_S 0xD0000000 /* DDR4 block 7 Secure base address */ - -/* Memory map addresses exempt from memory attribution by both the SAU and IDAU */ -#define SSE300_EWIC_BASE 0xE0047000 /* External Wakeup Interrupt Controller - * Access from Non-secure software is only allowed - * if AIRCR.BFHFNMINS is set to 1 */ - -/* Memory size definitions */ -#define ITCM_SIZE (0x00080000) /* 512 kB */ -#define DTCM_BLK_SIZE (0x00020000) /* 128 kB */ -#define DTCM_BLK_NUM (0x4) /* Number of DTCM blocks */ -#define SRAM_SIZE (0x00100000) /* 1 MB */ -#define ISRAM0_SIZE (0x00100000) /* 1 MB */ -#define ISRAM1_SIZE (0x00100000) /* 1 MB */ -#define QSPI_SRAM_SIZE (0x00800000) /* 8 MB */ -#define DDR4_BLK_SIZE (0x10000000) /* 256 MB */ -#define DDR4_BLK_NUM (0x8) /* Number of DDR4 blocks */ - -/* Defines for Driver MPC's */ -/* SRAM -- 2 MB */ -#define MPC_SRAM_RANGE_BASE_NS (SRAM_BASE_NS) -#define MPC_SRAM_RANGE_LIMIT_NS (SRAM_BASE_NS + SRAM_SIZE-1) -#define MPC_SRAM_RANGE_OFFSET_NS (0x0) -#define MPC_SRAM_RANGE_BASE_S (SRAM_BASE_S) -#define MPC_SRAM_RANGE_LIMIT_S (SRAM_BASE_S + SRAM_SIZE-1) -#define MPC_SRAM_RANGE_OFFSET_S (0x0) - -/* QSPI -- 8 MB*/ -#define MPC_QSPI_RANGE_BASE_NS (QSPI_SRAM_BASE_NS) -#define MPC_QSPI_RANGE_LIMIT_NS (QSPI_SRAM_BASE_NS + QSPI_SRAM_SIZE-1) -#define MPC_QSPI_RANGE_OFFSET_NS (0x0) -#define MPC_QSPI_RANGE_BASE_S (QSPI_SRAM_BASE_S) -#define MPC_QSPI_RANGE_LIMIT_S (QSPI_SRAM_BASE_S + QSPI_SRAM_SIZE-1) -#define MPC_QSPI_RANGE_OFFSET_S (0x0) - -/* ISRAM0 -- 2 MB*/ -#define MPC_ISRAM0_RANGE_BASE_NS (ISRAM0_BASE_NS) -#define MPC_ISRAM0_RANGE_LIMIT_NS (ISRAM0_BASE_NS + ISRAM0_SIZE-1) -#define MPC_ISRAM0_RANGE_OFFSET_NS (0x0) -#define MPC_ISRAM0_RANGE_BASE_S (ISRAM0_BASE_S) -#define MPC_ISRAM0_RANGE_LIMIT_S (ISRAM0_BASE_S + ISRAM0_SIZE-1) -#define MPC_ISRAM0_RANGE_OFFSET_S (0x0) - -/* ISRAM1 -- 2 MB*/ -#define MPC_ISRAM1_RANGE_BASE_NS (ISRAM1_BASE_NS) -#define MPC_ISRAM1_RANGE_LIMIT_NS (ISRAM1_BASE_NS + ISRAM1_SIZE-1) -#define MPC_ISRAM1_RANGE_OFFSET_NS (0x0) -#define MPC_ISRAM1_RANGE_BASE_S (ISRAM1_BASE_S) -#define MPC_ISRAM1_RANGE_LIMIT_S (ISRAM1_BASE_S + ISRAM1_SIZE-1) -#define MPC_ISRAM1_RANGE_OFFSET_S (0x0) - -/* DDR4 -- 2GB (8 * 256 MB) */ -#define MPC_DDR4_BLK0_RANGE_BASE_NS (DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK0_RANGE_LIMIT_NS (DDR4_BLK0_BASE_NS + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK0_RANGE_OFFSET_NS (0x0) -#define MPC_DDR4_BLK1_RANGE_BASE_S (DDR4_BLK1_BASE_S) -#define MPC_DDR4_BLK1_RANGE_LIMIT_S (DDR4_BLK1_BASE_S + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK1_RANGE_OFFSET_S (DDR4_BLK1_BASE_S - DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK2_RANGE_BASE_NS (DDR4_BLK2_BASE_NS) -#define MPC_DDR4_BLK2_RANGE_LIMIT_NS (DDR4_BLK2_BASE_NS + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK2_RANGE_OFFSET_NS (DDR4_BLK2_BASE_NS - DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK3_RANGE_BASE_S (DDR4_BLK3_BASE_S) -#define MPC_DDR4_BLK3_RANGE_LIMIT_S (DDR4_BLK3_BASE_S + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK3_RANGE_OFFSET_S (DDR4_BLK3_BASE_S - DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK4_RANGE_BASE_NS (DDR4_BLK4_BASE_NS) -#define MPC_DDR4_BLK4_RANGE_LIMIT_NS (DDR4_BLK4_BASE_NS + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK4_RANGE_OFFSET_NS (DDR4_BLK4_BASE_NS - DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK5_RANGE_BASE_S (DDR4_BLK5_BASE_S) -#define MPC_DDR4_BLK5_RANGE_LIMIT_S (DDR4_BLK5_BASE_S + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK5_RANGE_OFFSET_S (DDR4_BLK5_BASE_S - DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK6_RANGE_BASE_NS (DDR4_BLK6_BASE_NS) -#define MPC_DDR4_BLK6_RANGE_LIMIT_NS (DDR4_BLK6_BASE_NS + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK6_RANGE_OFFSET_NS (DDR4_BLK6_BASE_NS - DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK7_RANGE_BASE_S (DDR4_BLK7_BASE_S) -#define MPC_DDR4_BLK7_RANGE_LIMIT_S (DDR4_BLK7_BASE_S + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK7_RANGE_OFFSET_S (DDR4_BLK7_BASE_S - DDR4_BLK0_BASE_NS) - -#endif /* __PLATFORM_BASE_ADDRESS_H__ */ diff --git a/Examples/cmsis_build/RTE/Device/SSE-310-MPS3/startup_SSE310MPS3.c b/Examples/cmsis_build/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c similarity index 84% rename from Examples/cmsis_build/RTE/Device/SSE-310-MPS3/startup_SSE310MPS3.c rename to Examples/cmsis_build/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c index 26d8b28d1..72b39ca55 100644 --- a/Examples/cmsis_build/RTE/Device/SSE-310-MPS3/startup_SSE310MPS3.c +++ b/Examples/cmsis_build/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2009-2022 Arm Limited. All rights reserved. + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -17,27 +17,20 @@ */ /* - * This file is derivative of CMSIS V5.6.0 startup_ARMv81MML.c - * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b + * This file is derivative of CMSIS V5.9.0 startup_ARMCM55.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c */ -#include "SSE310MPS3.h" -#include "system_SSE310MPS3.h" - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler Function Prototype - *----------------------------------------------------------------------------*/ -typedef void( *pFunc )( void ); +#include "SSE300MPS3.h" /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ - -#define __MSP_INITIAL_SP __INITIAL_SP -#define __MSP_STACK_LIMIT __STACK_LIMIT - -extern uint32_t __MSP_INITIAL_SP; -extern uint32_t __MSP_STACK_LIMIT; +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif extern void __PROGRAM_START(void) __NO_RETURN; @@ -77,7 +70,9 @@ DEFAULT_IRQ_HANDLER(MPC_Handler) DEFAULT_IRQ_HANDLER(PPC_Handler) DEFAULT_IRQ_HANDLER(MSC_Handler) DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) -DEFAULT_IRQ_HANDLER(COMBINED_PPU_Handler) +DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler) +DEFAULT_IRQ_HANDLER(SYS_PPU_Handler) +DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler) DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler) DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler) DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler) @@ -107,9 +102,18 @@ DEFAULT_IRQ_HANDLER(USB_Handler) DEFAULT_IRQ_HANDLER(SPI_ADC_Handler) DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler) DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler) -DEFAULT_IRQ_HANDLER(DMA_Channel_0_Handler) -DEFAULT_IRQ_HANDLER(DMA_Channel_1_Handler) DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler) +#ifdef CORSTONE300_AN547 +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Combined_Handler) +#endif DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) @@ -179,9 +183,9 @@ DEFAULT_IRQ_HANDLER(UART5_Handler) #pragma GCC diagnostic ignored "-Wpedantic" #endif -extern const pFunc __VECTOR_TABLE[]; - const pFunc __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { - (pFunc)(&__MSP_INITIAL_SP), /* Initial Stack Pointer */ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14: NMI Handler */ HardFault_Handler, /* -13: Hard Fault Handler */ @@ -212,9 +216,9 @@ extern const pFunc __VECTOR_TABLE[]; MSC_Handler, /* 11: MSC Combined (Secure) Handler */ BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ 0, /* 13: Reserved */ - COMBINED_PPU_Handler, /* 14: Combined PPU Handler */ - 0, /* 15: Reserved */ - ETHOS_U55_Handler, /* 16: Ethos-U55 Handler */ + MGMT_PPU_Handler, /* 14: MGMT PPU Handler */ + SYS_PPU_Handler, /* 15: SYS PPU Handler */ + CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */ 0, /* 17: Reserved */ 0, /* 18: Reserved */ 0, /* 19: Reserved */ @@ -224,7 +228,7 @@ extern const pFunc __VECTOR_TABLE[]; 0, /* 23: Reserved */ 0, /* 24: Reserved */ 0, /* 25: Reserved */ - 0, /* 26: Reserved */ + DEBUG_PPU_Handler, /* 26: DEBUG PPU Handler */ TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */ CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */ CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */ @@ -256,9 +260,23 @@ extern const pFunc __VECTOR_TABLE[]; SPI_ADC_Handler, /* 53: SPI ADC Handler */ SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */ SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */ - 0, /* 56: Reserved */ - DMA_Channel_0_Handler, /* 57: DMA (DMA350) Channel 0 Handler */ - DMA_Channel_1_Handler, /* 58: DMA (DMA350) Channel 1 Handler */ + ETHOS_U55_Handler, /* 56: Ethos-U55 Handler */ +#ifdef CORSTONE300_AN547 + 0, /* 57: Reserved */ + 0, /* 58: Reserved */ + 0, /* 59: Reserved */ + DMA_Ch_1_Error_Handler, /* 60: DMA Ch1 Error Handler */ + DMA_Ch_1_Terminal_Count_Handler, /* 61: DMA Ch1 Terminal Count Handler */ + DMA_Ch_1_Combined_Handler, /* 62: DMA Ch1 Combined Handler */ + DMA_Ch_2_Error_Handler, /* 63: DMA Ch2 Error Handler */ + DMA_Ch_2_Terminal_Count_Handler, /* 64: DMA Ch2 Terminal Count Handler */ + DMA_Ch_2_Combined_Handler, /* 65: DMA Ch2 Combined Handler */ + DMA_Ch_3_Error_Handler, /* 66: DMA Ch3 Error Handler */ + DMA_Ch_3_Terminal_Count_Handler, /* 67: DMA Ch3 Terminal Count Handler */ + DMA_Ch_3_Combined_Handler, /* 68: DMA Ch3 Combined Handler */ +#else + 0, /* 57: Reserved */ + 0, /* 58: Reserved */ 0, /* 59: Reserved */ 0, /* 60: Reserved */ 0, /* 61: Reserved */ @@ -269,6 +287,7 @@ extern const pFunc __VECTOR_TABLE[]; 0, /* 66: Reserved */ 0, /* 67: Reserved */ 0, /* 68: Reserved */ +#endif GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ @@ -342,9 +361,15 @@ extern const pFunc __VECTOR_TABLE[]; *----------------------------------------------------------------------------*/ void Reset_Handler(void) { - __set_MSPLIM((uint32_t)(&__MSP_STACK_LIMIT)); + __set_PSP((uint32_t)(&__INITIAL_SP)); - SystemInit(); /* CMSIS System Initialization */ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } diff --git a/Examples/cmsis_build/RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c b/Examples/cmsis_build/RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c deleted file mode 100644 index d1e59d74a..000000000 --- a/Examples/cmsis_build/RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c +++ /dev/null @@ -1,344 +0,0 @@ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * This file is derivative of CMSIS V5.6.0 startup_ARMv81MML.c - * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b - */ - -#include "SSE300MPS3.h" - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler Function Prototype - *----------------------------------------------------------------------------*/ -typedef void( *pFunc )( void ); - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; - -extern void __PROGRAM_START(void) __NO_RETURN; - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -void Reset_Handler (void) __NO_RETURN; - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -#define DEFAULT_IRQ_HANDLER(handler_name) \ -void __WEAK __NO_RETURN handler_name(void); \ -void handler_name(void) { \ - while(1); \ -} - -/* Exceptions */ -DEFAULT_IRQ_HANDLER(NMI_Handler) -DEFAULT_IRQ_HANDLER(HardFault_Handler) -DEFAULT_IRQ_HANDLER(MemManage_Handler) -DEFAULT_IRQ_HANDLER(BusFault_Handler) -DEFAULT_IRQ_HANDLER(UsageFault_Handler) -DEFAULT_IRQ_HANDLER(SecureFault_Handler) -DEFAULT_IRQ_HANDLER(SVC_Handler) -DEFAULT_IRQ_HANDLER(DebugMon_Handler) -DEFAULT_IRQ_HANDLER(PendSV_Handler) -DEFAULT_IRQ_HANDLER(SysTick_Handler) - -DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_Handler) -DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) -DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) -DEFAULT_IRQ_HANDLER(TIMER0_Handler) -DEFAULT_IRQ_HANDLER(TIMER1_Handler) -DEFAULT_IRQ_HANDLER(TIMER2_Handler) -DEFAULT_IRQ_HANDLER(MPC_Handler) -DEFAULT_IRQ_HANDLER(PPC_Handler) -DEFAULT_IRQ_HANDLER(MSC_Handler) -DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) -DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler) -DEFAULT_IRQ_HANDLER(SYS_PPU_Handler) -DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler) -DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler) -DEFAULT_IRQ_HANDLER(TIMER3_Handler) -DEFAULT_IRQ_HANDLER(CTI_REQ0_IRQHandler) -DEFAULT_IRQ_HANDLER(CTI_REQ1_IRQHandler) - -DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) -DEFAULT_IRQ_HANDLER(UARTRX0_Handler) -DEFAULT_IRQ_HANDLER(UARTTX0_Handler) -DEFAULT_IRQ_HANDLER(UARTRX1_Handler) -DEFAULT_IRQ_HANDLER(UARTTX1_Handler) -DEFAULT_IRQ_HANDLER(UARTRX2_Handler) -DEFAULT_IRQ_HANDLER(UARTTX2_Handler) -DEFAULT_IRQ_HANDLER(UARTRX3_Handler) -DEFAULT_IRQ_HANDLER(UARTTX3_Handler) -DEFAULT_IRQ_HANDLER(UARTRX4_Handler) -DEFAULT_IRQ_HANDLER(UARTTX4_Handler) -DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) -DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) -DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) -DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) -DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) -DEFAULT_IRQ_HANDLER(UARTOVF_Handler) -DEFAULT_IRQ_HANDLER(ETHERNET_Handler) -DEFAULT_IRQ_HANDLER(I2S_Handler) -DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler) -DEFAULT_IRQ_HANDLER(USB_Handler) -DEFAULT_IRQ_HANDLER(SPI_ADC_Handler) -DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler) -DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler) -DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) -DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_0_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_1_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_2_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_3_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_4_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_5_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_6_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_7_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_8_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_9_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_10_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_11_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_12_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_13_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_14_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_15_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_0_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_1_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_2_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_3_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_4_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_5_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_6_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_7_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_8_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_9_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_10_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_11_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_12_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_13_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_14_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_15_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_0_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_1_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_2_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_3_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_4_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_5_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_6_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_7_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_8_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_9_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_10_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_11_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_12_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_13_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_14_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_15_Handler) -DEFAULT_IRQ_HANDLER(GPIO3_0_Handler) -DEFAULT_IRQ_HANDLER(GPIO3_1_Handler) -DEFAULT_IRQ_HANDLER(GPIO3_2_Handler) -DEFAULT_IRQ_HANDLER(GPIO3_3_Handler) -DEFAULT_IRQ_HANDLER(UARTRX5_Handler) -DEFAULT_IRQ_HANDLER(UARTTX5_Handler) -DEFAULT_IRQ_HANDLER(UART5_Handler) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const pFunc __VECTOR_TABLE[496]; - const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14: NMI Handler */ - HardFault_Handler, /* -13: Hard Fault Handler */ - MemManage_Handler, /* -12: MPU Fault Handler */ - BusFault_Handler, /* -11: Bus Fault Handler */ - UsageFault_Handler, /* -10: Usage Fault Handler */ - SecureFault_Handler, /* -9: Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5: SVCall Handler */ - DebugMon_Handler, /* -4: Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2: PendSV Handler */ - SysTick_Handler, /* -1: SysTick Handler */ - - NONSEC_WATCHDOG_RESET_Handler, /* 0: Non-Secure Watchdog Reset Handler */ - NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ - SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ - TIMER0_Handler, /* 3: TIMER 0 Handler */ - TIMER1_Handler, /* 4: TIMER 1 Handler */ - TIMER2_Handler, /* 5: TIMER 2 Handler */ - 0, /* 6: Reserved */ - 0, /* 7: Reserved */ - 0, /* 8: Reserved */ - MPC_Handler, /* 9: MPC Combined (Secure) Handler */ - PPC_Handler, /* 10: PPC Combined (Secure) Handler */ - MSC_Handler, /* 11: MSC Combined (Secure) Handler */ - BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ - 0, /* 13: Reserved */ - MGMT_PPU_Handler, /* 14: MGMT PPU Handler */ - SYS_PPU_Handler, /* 15: SYS PPU Handler */ - CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */ - 0, /* 17: Reserved */ - 0, /* 18: Reserved */ - 0, /* 19: Reserved */ - 0, /* 20: Reserved */ - 0, /* 21: Reserved */ - 0, /* 22: Reserved */ - 0, /* 23: Reserved */ - 0, /* 24: Reserved */ - 0, /* 25: Reserved */ - DEBUG_PPU_Handler, /* 26: DEBUG PPU Handler */ - TIMER3_Handler, /* 27: TIMER 3 Handler */ - CTI_REQ0_IRQHandler, /* 28: CTI request 0 IRQ Handler */ - CTI_REQ1_IRQHandler, /* 29: CTI request 1 IRQ Handler */ - 0, /* 30: Reserved */ - 0, /* 31: Reserved */ - - /* External interrupts */ - System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */ - UARTRX0_Handler, /* 33: UART 0 RX Handler */ - UARTTX0_Handler, /* 34: UART 0 TX Handler */ - UARTRX1_Handler, /* 35: UART 1 RX Handler */ - UARTTX1_Handler, /* 36: UART 1 TX Handler */ - UARTRX2_Handler, /* 37: UART 2 RX Handler */ - UARTTX2_Handler, /* 38: UART 2 TX Handler */ - UARTRX3_Handler, /* 39: UART 3 RX Handler */ - UARTTX3_Handler, /* 40: UART 3 TX Handler */ - UARTRX4_Handler, /* 41: UART 4 RX Handler */ - UARTTX4_Handler, /* 42: UART 4 TX Handler */ - UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ - UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ - UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ - UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ - UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ - UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ - ETHERNET_Handler, /* 49: Ethernet Handler */ - I2S_Handler, /* 50: Audio I2S Handler */ - TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */ - USB_Handler, /* 52: USB Handler */ - SPI_ADC_Handler, /* 53: SPI ADC Handler */ - SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */ - SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */ - ETHOS_U55_Handler, /* 56: Ethos-U55 Handler */ - 0, /* 57: Reserved */ - 0, /* 58: Reserved */ - 0, /* 59: Reserved */ - 0, /* 60: Reserved */ - 0, /* 61: Reserved */ - 0, /* 62: Reserved */ - 0, /* 63: Reserved */ - 0, /* 64: Reserved */ - 0, /* 65: Reserved */ - 0, /* 66: Reserved */ - 0, /* 67: Reserved */ - 0, /* 68: Reserved */ - GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ - GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ - GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ - GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ - GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */ - GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */ - GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */ - GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */ - GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */ - GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */ - GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */ - GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */ - GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */ - GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */ - GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */ - GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */ - GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */ - GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */ - GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */ - GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */ - GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */ - GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */ - GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */ - GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */ - GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */ - GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */ - GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */ - GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */ - GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */ - GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */ - GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */ - GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */ - GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */ - GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */ - GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */ - GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */ - GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */ - GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */ - GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */ - GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */ - GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */ - GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */ - GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */ - GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */ - GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */ - GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */ - GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */ - GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */ - GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */ - GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */ - GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */ - GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */ - GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */ - GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */ - GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */ - GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */ - UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ - UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ - UART5_Handler, /* 127: UART 5 combined Interrupt */ - 0, /* 128: Reserved */ - 0, /* 129: Reserved */ - 0, /* 130: Reserved */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -void Reset_Handler(void) -{ - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} diff --git a/Examples/cmsis_build/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c b/Examples/cmsis_build/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c index 1d8c3b674..4e67d536d 100644 --- a/Examples/cmsis_build/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c +++ b/Examples/cmsis_build/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c @@ -17,8 +17,8 @@ */ /* - * This file is derivative of CMSIS V5.6.0 system_ARMv81MML.c - * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b + * This file is derivative of CMSIS V5.9.0 system_ARMCM55.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c */ #include "SSE300MPS3.h" @@ -31,11 +31,9 @@ #define PERIPHERAL_CLOCK (25000000UL) /*---------------------------------------------------------------------------- - Externals + Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - extern uint32_t __VECTOR_TABLE; -#endif +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; /*---------------------------------------------------------------------------- System Core Clock Variable @@ -57,21 +55,27 @@ void SystemCoreClockUpdate (void) *----------------------------------------------------------------------------*/ void SystemInit (void) { - #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t)(&__VECTOR_TABLE); + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); #endif #if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE >= 1U)) + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ (3U << 11U*2U) ); /* enable CP11 Full Access */ - /* Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. Set - * CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU - * into retention state - */ - PWRMODCTL->CPDLPSTATE &= 0xFFFFFF00UL; + /* Set low-power state for PDEPU */ + /* 0b00 | ON, PDEPU is not in low-power state */ + /* 0b01 | ON, but the clock is off */ + /* 0b10 | RET(ention) */ + /* 0b11 | OFF */ + + /* Clear ELPSTATE, value is 0b11 on Cold reset */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; #endif #ifdef UNALIGNED_SUPPORT_DISABLE @@ -83,4 +87,7 @@ void SystemInit (void) __DSB(); __ISB(); + + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; } diff --git a/Examples/cmsis_build/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.h b/Examples/cmsis_build/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.h deleted file mode 100644 index feba5e9aa..000000000 --- a/Examples/cmsis_build/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2009-2020 Arm Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * This file is derivative of CMSIS V5.6.0 system_ARMv81MML.h - * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b - */ - -#ifndef __SYSTEM_CORE_INIT_H__ -#define __SYSTEM_CORE_INIT_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ -extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency */ - -/** - * \brief Initializes the system - */ -extern void SystemInit(void); - -/** - * \brief Restores system core clock - */ -extern void SystemCoreClockUpdate(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_CORE_INIT_H__ */ diff --git a/Examples/cmsis_build/RTE/Device/SSE-310-MPS3/RTE_Device.h b/Examples/cmsis_build/RTE/Device/SSE-310-MPS3/RTE_Device.h deleted file mode 100644 index 70b7bf958..000000000 --- a/Examples/cmsis_build/RTE/Device/SSE-310-MPS3/RTE_Device.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (c) 2019-2022 Arm Limited. All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - -// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0] -// Configuration settings for Driver_USART0 in component ::Drivers:USART -#define RTE_USART0 1 - -// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1] -// Configuration settings for Driver_USART1 in component ::Drivers:USART -#define RTE_USART1 1 - -// MPC (Memory Protection Controller) [Driver_ISRAM0_MPC] -// Configuration settings for Driver_ISRAM0_MPC in component ::Drivers:MPC -#define RTE_ISRAM0_MPC 0 - -// MPC (Memory Protection Controller) [Driver_ISRAM1_MPC] -// Configuration settings for Driver_ISRAM1_MPC in component ::Drivers:MPC -#define RTE_ISRAM1_MPC 0 - -// MPC (Memory Protection Controller) [Driver_SRAM_MPC] -// Configuration settings for Driver_SRAM_MPC in component ::Drivers:MPC -#define RTE_SRAM_MPC 0 - -// MPC (Memory Protection Controller) [Driver_QSPI_MPC] -// Configuration settings for Driver_QSPI_MPC in component ::Drivers:MPC -#define RTE_QSPI_MPC 0 - -// PPC (Peripheral Protection Controller) [PPC_CORSTONE310_MAIN0] -// Configuration settings for Driver_PPC_CORSTONE310_MAIN0 in component ::Drivers:PPC -#define RTE_PPC_CORSTONE310_MAIN0 0 - -// PPC (Peripheral Protection Controller) [PPC_CORSTONE310_MAIN_EXP0] -// Configuration settings for Driver_PPC_CORSTONE310_MAIN_EXP0 in component ::Drivers:PPC -#define RTE_PPC_CORSTONE310_MAIN_EXP0 0 - -// PPC (Peripheral Protection Controller) [PPC_CORSTONE310_MAIN_EXP1] -// Configuration settings for Driver_PPC_CORSTONE310_MAIN_EXP1 in component ::Drivers:PPC -#define RTE_PPC_CORSTONE310_MAIN_EXP1 0 - -// PPC (Peripheral Protection Controller) [PPC_CORSTONE310_PERIPH0] -// Configuration settings for Driver_PPC_CORSTONE310_PERIPH0 in component ::Drivers:PPC -#define RTE_PPC_CORSTONE310_PERIPH0 0 - -// PPC (Peripheral Protection Controller) [PPC_CORSTONE310_PERIPH1] -// Configuration settings for Driver_PPC_CORSTONE310_PERIPH1 in component ::Drivers:PPC -#define RTE_PPC_CORSTONE310_PERIPH1 0 - -// PPC (Peripheral Protection Controller) [PPC_CORSTONE310_PERIPH_EXP0] -// Configuration settings for Driver_PPC_CORSTONE310_PERIPH_EXP0 in component ::Drivers:PPC -#define RTE_PPC_CORSTONE310_PERIPH_EXP0 0 - -// PPC (Peripheral Protection Controller) [PPC_CORSTONE310_PERIPH_EXP1] -// Configuration settings for Driver_PPC_CORSTONE310_PERIPH_EXP1 in component ::Drivers:PPC -#define RTE_PPC_CORSTONE310_PERIPH_EXP1 0 - -// PPC (Peripheral Protection Controller) [PPC_CORSTONE310_PERIPH_EXP2] -// Configuration settings for Driver_PPC_CORSTONE310_PERIPH_EXP2 in component ::Drivers:PPC -#define RTE_PPC_CORSTONE310_PERIPH_EXP2 0 - -// Flash device emulated by SRAM [Driver_Flash0] -// Configuration settings for Driver_Flash0 in component ::Drivers:Flash -#define RTE_FLASH0 1 - -// I2C SBCon [Driver_I2C0] -// Configuration settings for Driver_I2C0 in component ::Drivers:I2C -#define RTE_I2C0 1 - -#endif /* __RTE_DEVICE_H */ diff --git a/Examples/cmsis_build/RTE/Device/SSE-310-MPS3/cmsis_driver_config.h b/Examples/cmsis_build/RTE/Device/SSE-310-MPS3/cmsis_driver_config.h deleted file mode 100644 index 35df89ef1..000000000 --- a/Examples/cmsis_build/RTE/Device/SSE-310-MPS3/cmsis_driver_config.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2019-2022 Arm Limited. All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_DRIVER_CONFIG_H__ -#define __CMSIS_DRIVER_CONFIG_H__ - -#include "system_SSE310MPS3.h" -#include "device_cfg.h" -#include "device_definition.h" -#include "platform_base_address.h" - -#endif /* __CMSIS_DRIVER_CONFIG_H__ */ diff --git a/Examples/cmsis_build/RTE/Device/SSE-310-MPS3/device_cfg.h b/Examples/cmsis_build/RTE/Device/SSE-310-MPS3/device_cfg.h deleted file mode 100644 index e34f782c5..000000000 --- a/Examples/cmsis_build/RTE/Device/SSE-310-MPS3/device_cfg.h +++ /dev/null @@ -1,158 +0,0 @@ -/* - * Copyright (c) 2020-2022 Arm Limited. All rights reserved. - * - * Licensed under the Apache License Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing software - * distributed under the License is distributed on an "AS IS" BASIS - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __DEVICE_CFG_H__ -#define __DEVICE_CFG_H__ - -/** - * \file device_cfg.h - * \brief Configuration file native driver re-targeting - * - * \details This file can be used to add native driver specific macro - * definitions to select which peripherals are available in the build. - * - * This is a default device configuration file with all peripherals enabled. - */ - -/* Secure only peripheral configuration */ - -/* ARM MPS3 IO SCC */ -#define MPS3_IO_S -#define MPS3_IO_DEV MPS3_IO_DEV_S - -/* I2C_SBCon */ -#define I2C0_SBCON_S -#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S - -/* I2S */ -#define MPS3_I2S_S -#define MPS3_I2S_DEV MPS3_I2S_DEV_S - -/* ARM UART Controller PL011 */ -#define UART0_CMSDK_S -#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S -#define UART1_CMSDK_S -#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S - -#define DEFAULT_UART_BAUDRATE 115200U - -/* To be used as CODE and DATA sram */ -#define MPC_ISRAM0_S -#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S - -#define MPC_ISRAM1_S -#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S - -#define MPC_SRAM_S -#define MPC_SRAM_DEV MPC_SRAM_DEV_S - -#define MPC_QSPI_S -#define MPC_QSPI_DEV MPC_QSPI_DEV_S - -/** System Counter Armv8-M */ -#define SYSCOUNTER_CNTRL_ARMV8_M_S -#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S - -#define SYSCOUNTER_READ_ARMV8_M_S -#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S -/** - * Arbitrary scaling values for test purposes - */ -#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u -#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u -#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u -#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u - -/* System timer */ -#define SYSTIMER0_ARMV8_M_S -#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S -#define SYSTIMER1_ARMV8_M_S -#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S -#define SYSTIMER2_ARMV8_M_S -#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S -#define SYSTIMER3_ARMV8_M_S -#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S - -#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) -#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) -#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) -#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) - -/* CMSDK GPIO driver structures */ -#define GPIO0_CMSDK_S -#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S -#define GPIO1_CMSDK_S -#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S -#define GPIO2_CMSDK_S -#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S -#define GPIO3_CMSDK_S -#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S - -/* System Watchdogs */ -#define SYSWDOG_ARMV8_M_S -#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S - -/* ARM MPC SIE 310 driver structures */ -#define MPC_VM0_S -#define MPC_VM0_DEV MPC_VM0_DEV_S -#define MPC_VM1_S -#define MPC_VM1_DEV MPC_VM1_DEV_S -#define MPC_SSRAM2_S -#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S -#define MPC_SSRAM3_S -#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S - -/* ARM PPC driver structures */ -#define PPC_CORSTONE310_MAIN0_S -#define PPC_CORSTONE310_MAIN0_DEV PPC_CORSTONE310_MAIN0_DEV_S -#define PPC_CORSTONE310_MAIN_EXP0_S -#define PPC_CORSTONE310_MAIN_EXP0_DEV PPC_CORSTONE310_MAIN_EXP0_DEV_S -#define PPC_CORSTONE310_MAIN_EXP1_S -#define PPC_CORSTONE310_MAIN_EXP1_DEV PPC_CORSTONE310_MAIN_EXP1_DEV_S -#define PPC_CORSTONE310_MAIN_EXP2_S -#define PPC_CORSTONE310_MAIN_EXP2_DEV PPC_CORSTONE310_MAIN_EXP2_DEV_S -#define PPC_CORSTONE310_MAIN_EXP3_S -#define PPC_CORSTONE310_MAIN_EXP3_DEV PPC_CORSTONE310_MAIN_EXP3_DEV_S -#define PPC_CORSTONE310_PERIPH0_S -#define PPC_CORSTONE310_PERIPH0_DEV PPC_CORSTONE310_PERIPH0_DEV_S -#define PPC_CORSTONE310_PERIPH1_S -#define PPC_CORSTONE310_PERIPH1_DEV PPC_CORSTONE310_PERIPH1_DEV_S -#define PPC_CORSTONE310_PERIPH_EXP0_S -#define PPC_CORSTONE310_PERIPH_EXP0_DEV PPC_CORSTONE310_PERIPH_EXP0_DEV_S -#define PPC_CORSTONE310_PERIPH_EXP1_S -#define PPC_CORSTONE310_PERIPH_EXP1_DEV PPC_CORSTONE310_PERIPH_EXP1_DEV_S -#define PPC_CORSTONE310_PERIPH_EXP2_S -#define PPC_CORSTONE310_PERIPH_EXP2_DEV PPC_CORSTONE310_PERIPH_EXP2_DEV_S -#define PPC_CORSTONE310_PERIPH_EXP3_S -#define PPC_CORSTONE310_PERIPH_EXP3_DEV PPC_CORSTONE310_PERIPH_EXP3_DEV_S - -/* DMA350 */ -#define DMA350_DMA0_S -#define DMA350_DMA0_DEV DMA350_DMA0_DEV_S - -#define DMA350_CH0_S -#define DMA350_DMA0_CH0_S -#define DMA350_CH1_S -#define DMA350_DMA0_CH1_S - -/* ARM SPI PL022 */ -/* Invalid device stubs are not defined */ -#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ -#define SPI1_PL022_S -#define SPI1_PL022_DEV SPI1_PL022_DEV_S - - -#endif /* __DEVICE_CFG_H__ */ diff --git a/Examples/cmsis_build/RTE/Device/SSE-310-MPS3/platform_base_address.h b/Examples/cmsis_build/RTE/Device/SSE-310-MPS3/platform_base_address.h deleted file mode 100644 index 04ab7412f..000000000 --- a/Examples/cmsis_build/RTE/Device/SSE-310-MPS3/platform_base_address.h +++ /dev/null @@ -1,257 +0,0 @@ -/* - * Copyright (c) 2019-2022 Arm Limited - * - * Licensed under the Apache License Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing software - * distributed under the License is distributed on an "AS IS" BASIS - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/** - * \file platform_base_address.h - * \brief This file defines all the peripheral base addresses for Corstone-310. - */ - -#ifndef __PLATFORM_BASE_ADDRESS_H__ -#define __PLATFORM_BASE_ADDRESS_H__ - -/* ======= Defines peripherals memory map addresses ======= */ -/* Non-secure memory map addresses */ -#define ITCM_BASE_NS 0x00000000 /* Instruction TCM Non-Secure base address */ -#define SRAM_BASE_NS 0x01000000 /* CODE SRAM Non-Secure base address */ -#define DTCM0_BASE_NS 0x20000000 /* Data TCM block 0 Non-Secure base address */ -#define DTCM1_BASE_NS 0x20002000 /* Data TCM block 1 Non-Secure base address */ -#define DTCM2_BASE_NS 0x20004000 /* Data TCM block 2 Non-Secure base address */ -#define DTCM3_BASE_NS 0x20006000 /* Data TCM block 3 Non-Secure base address */ -#define ISRAM0_BASE_NS 0x21000000 /* Internal SRAM Area Non-Secure base address */ -#define ISRAM1_BASE_NS 0x21200000 /* Internal SRAM Area Non-Secure base address */ -#define QSPI_SRAM_BASE_NS 0x28000000 /* QSPI SRAM Non-Secure base address */ -/* Non-Secure Subsystem peripheral region */ -#define DMA_350_BASE_NS 0x40002000 /* DMA350 register block Non-Secure base address */ -#define ETHOS_U55_APB_BASE_NS 0x40004000 /* Ethos-U55 APB Non-Secure base address */ -#define CPU0_PWRCTRL_BASE_NS 0x40012000 /* CPU 0 Power Control Block Non-Secure base address */ -#define CPU0_IDENTITY_BASE_NS 0x4001F000 /* CPU 0 Identity Block Non-Secure base address */ -#define CORSTONE310_NSACFG_BASE_NS 0x40080000 /* Corstone-310 Non-Secure Access Configuration Register Block Non-Secure base address */ -/* Non-Secure MSTEXPPILL Peripheral region */ -#define GPIO0_CMSDK_BASE_NS 0x41100000 /* GPIO 0 Non-Secure base address */ -#define GPIO1_CMSDK_BASE_NS 0x41101000 /* GPIO 1 Non-Secure base address */ -#define GPIO2_CMSDK_BASE_NS 0x41102000 /* GPIO 2 Non-Secure base address */ -#define GPIO3_CMSDK_BASE_NS 0x41103000 /* GPIO 3 Non-Secure base address */ -#define AHB_USER_0_BASE_NS 0x41104000 /* AHB USER 0 Non-Secure base address */ -#define AHB_USER_1_BASE_NS 0x41105000 /* AHB USER 1 Non-Secure base address */ -#define AHB_USER_2_BASE_NS 0x41106000 /* AHB USER 2 Non-Secure base address */ -#define AHB_USER_3_BASE_NS 0x41107000 /* AHB USER 3 Non-Secure base address */ -#define ETHERNET_BASE_NS 0x41400000 /* Ethernet Non-Secure base address */ -#define USB_BASE_NS 0x41500000 /* USB Non-Secure base address */ -#define USER_APB0_BASE_NS 0x41700000 /* User APB 0 Non-Secure base address */ -#define USER_APB1_BASE_NS 0x41701000 /* User APB 1 Non-Secure base address */ -#define USER_APB2_BASE_NS 0x41702000 /* User APB 2 Non-Secure base address */ -#define USER_APB3_BASE_NS 0x41703000 /* User APB 3 Non-Secure base address */ -#define QSPI_CONFIG_BASE_NS 0x41800000 /* QSPI Config Non-Secure base address */ -#define QSPI_WRITE_BASE_NS 0x41801000 /* QSPI Write Non-Secure base address */ -/* Non-Secure Subsystem peripheral region */ -#define SYSTIMER0_ARMV8_M_BASE_NS 0x48000000 /* System Timer 0 Non-Secure base address */ -#define SYSTIMER1_ARMV8_M_BASE_NS 0x48001000 /* System Timer 1 Non-Secure base address */ -#define SYSTIMER2_ARMV8_M_BASE_NS 0x48002000 /* System Timer 2 Non-Secure base address */ -#define SYSTIMER3_ARMV8_M_BASE_NS 0x48003000 /* System Timer 3 Non-Secure base address */ -#define CORSTONE310_SYSINFO_BASE_NS 0x48020000 /* Corstone-310 System info Block Non-Secure base address */ -#define SLOWCLK_TIMER_CMSDK_BASE_NS 0x4802F000 /* CMSDK based SLOWCLK Timer Non-Secure base address */ -#define SYSWDOG_ARMV8_M_CNTRL_BASE_NS 0x48040000 /* Non-Secure Watchdog Timer control frame Non-Secure base address */ -#define SYSWDOG_ARMV8_M_REFRESH_BASE_NS 0x48041000 /* Non-Secure Watchdog Timer refresh frame Non-Secure base address */ -#define SYSCNTR_READ_BASE_NS 0x48101000 /* System Counter Read Secure base address */ -/* Non-Secure MSTEXPPIHL Peripheral region */ -#define U55_TIMING_ADAPTER_0_BASE_NS 0x48103000 /* Ethos-U55 Timing Adapter 0 APB registers Non-Secure base address */ -#define U55_TIMING_ADAPTER_1_BASE_NS 0x48103200 /* Ethos-U55 Timing Adapter 1 APB registers Non-Secure base address */ -#define FPGA_SBCon_I2C_TOUCH_BASE_NS 0x49200000 /* FPGA - SBCon I2C (Touch) Non-Secure base address */ -#define FPGA_SBCon_I2C_AUDIO_BASE_NS 0x49201000 /* FPGA - SBCon I2C (Audio Conf) Non-Secure base address */ -#define FPGA_SPI_ADC_BASE_NS 0x49202000 /* FPGA - PL022 (SPI ADC) Non-Secure base address */ -#define FPGA_SPI_SHIELD0_BASE_NS 0x49203000 /* FPGA - PL022 (SPI Shield0) Non-Secure base address */ -#define FPGA_SPI_SHIELD1_BASE_NS 0x49204000 /* FPGA - PL022 (SPI Shield1) Non-Secure base address */ -#define SBCon_I2C_SHIELD0_BASE_NS 0x49205000 /* SBCon (I2C - Shield0) Non-Secure base address */ -#define SBCon_I2C_SHIELD1_BASE_NS 0x49206000 /* SBCon (I2C – Shield1) Non-Secure base address */ -#define USER_APB_BASE_NS 0x49207000 /* USER APB Non-Secure base address */ -#define FPGA_DDR4_EEPROM_BASE_NS 0x49208000 /* FPGA - SBCon I2C (DDR4 EEPROM) Non-Secure base address */ -#define FPGA_SCC_BASE_NS 0x49300000 /* FPGA - SCC registers Non-Secure base address */ -#define FPGA_I2S_BASE_NS 0x49301000 /* FPGA - I2S (Audio) Non-Secure base address */ -#define FPGA_IO_BASE_NS 0x49302000 /* FPGA - IO (System Ctrl + I/O) Non-Secure base address */ -#define UART0_BASE_NS 0x49303000 /* UART 0 Non-Secure base address */ -#define UART1_BASE_NS 0x49304000 /* UART 1 Non-Secure base address */ -#define UART2_BASE_NS 0x49305000 /* UART 2 Non-Secure base address */ -#define UART3_BASE_NS 0x49306000 /* UART 3 Non-Secure base address */ -#define UART4_BASE_NS 0x49307000 /* UART 4 Non-Secure base address */ -#define UART5_BASE_NS 0x49308000 /* UART 5 Non-Secure base address */ -#define CLCD_Config_Reg_BASE_NS 0x4930A000 /* CLCD Config Reg Non-Secure base address */ -#define RTC_BASE_NS 0x4930B000 /* RTC Non-Secure base address */ -#define DDR4_BLK0_BASE_NS 0x60000000 /* DDR4 block 0 Non-Secure base address */ -#define DDR4_BLK2_BASE_NS 0x80000000 /* DDR4 block 2 Non-Secure base address */ -#define DDR4_BLK4_BASE_NS 0xA0000000 /* DDR4 block 4 Non-Secure base address */ -#define DDR4_BLK6_BASE_NS 0xC0000000 /* DDR4 block 6 Non-Secure base address */ - -/* Secure memory map addresses */ -#define ITCM_BASE_S 0x10000000 /* Instruction TCM Secure base address */ -#define SRAM_BASE_S 0x11000000 /* CODE SRAM Secure base address */ -#define DTCM0_BASE_S 0x30000000 /* Data TCM block 0 Secure base address */ -#define DTCM1_BASE_S 0x30002000 /* Data TCM block 1 Secure base address */ -#define DTCM2_BASE_S 0x30004000 /* Data TCM block 2 Secure base address */ -#define DTCM3_BASE_S 0x30006000 /* Data TCM block 3 Secure base address */ -#define ISRAM0_BASE_S 0x31000000 /* Internal SRAM Area Secure base address */ -#define ISRAM1_BASE_S 0x31200000 /* Internal SRAM Area Secure base address */ -#define QSPI_SRAM_BASE_S 0x38000000 /* QSPI SRAM Secure base address */ -/* Secure Subsystem peripheral region */ -#define DMA_350_BASE_S 0x50002000 /* DMA350 register block Secure base address */ -#define ETHOS_U55_APB_BASE_S 0x50004000 /* Ethos-U55 APB Secure base address */ -#define CPU0_SECCTRL_BASE_S 0x50011000 /* CPU 0 Local Security Control Block Secure base address */ -#define CPU0_PWRCTRL_BASE_S 0x50012000 /* CPU 0 Power Control Block Secure base address */ -#define CPU0_IDENTITY_BASE_S 0x5001F000 /* CPU 0 Identity Block Secure base address */ -#define CORSTONE310_SACFG_BASE_S 0x50080000 /* Corstone-310 Secure Access Configuration Register Secure base address */ -#define MPC_ISRAM0_BASE_S 0x50083000 /* Internal SRAM0 Memory Protection Controller Secure base address */ -#define MPC_ISRAM1_BASE_S 0x50084000 /* Internal SRAM1 Memory Protection Controller Secure base address */ -/* Secure MSTEXPPILL Peripheral region */ -#define GPIO0_CMSDK_BASE_S 0x51100000 /* GPIO 0 Secure base address */ -#define GPIO1_CMSDK_BASE_S 0x51101000 /* GPIO 1 Secure base address */ -#define GPIO2_CMSDK_BASE_S 0x51102000 /* GPIO 2 Secure base address */ -#define GPIO3_CMSDK_BASE_S 0x51103000 /* GPIO 3 Secure base address */ -#define AHB_USER_0_BASE_S 0x51104000 /* AHB USER 0 Secure base address */ -#define AHB_USER_1_BASE_S 0x51105000 /* AHB USER 1 Secure base address */ -#define AHB_USER_2_BASE_S 0x51106000 /* AHB USER 2 Secure base address */ -#define AHB_USER_3_BASE_S 0x51107000 /* AHB USER 3 Secure base address */ -#define ETHERNET_BASE_S 0x51400000 /* Ethernet Secure base address */ -#define USB_BASE_S 0x51500000 /* USB Secure base address */ -#define USER_APB0_BASE_S 0x51700000 /* User APB 0 Secure base address */ -#define USER_APB1_BASE_S 0x51701000 /* User APB 1 Secure base address */ -#define USER_APB2_BASE_S 0x51702000 /* User APB 2 Secure base address */ -#define USER_APB3_BASE_S 0x51703000 /* User APB 3 Secure base address */ -#define QSPI_CONFIG_BASE_S 0x51800000 /* QSPI Config Secure base address */ -#define QSPI_WRITE_BASE_S 0x51801000 /* QSPI Write Secure base address */ -#define MPC_SRAM_BASE_S 0x57000000 /* SRAM Memory Protection Controller Secure base address */ -#define MPC_QSPI_BASE_S 0x57001000 /* QSPI Memory Protection Controller Secure base address */ -#define MPC_DDR4_BASE_S 0x57002000 /* DDR4 Memory Protection Controller Secure base address */ -/* Secure Subsystem peripheral region */ -#define SYSTIMER0_ARMV8_M_BASE_S 0x58000000 /* System Timer 0 Secure base address */ -#define SYSTIMER1_ARMV8_M_BASE_S 0x58001000 /* System Timer 1 Secure base address */ -#define SYSTIMER2_ARMV8_M_BASE_S 0x58002000 /* System Timer 0 Secure base address */ -#define SYSTIMER3_ARMV8_M_BASE_S 0x58003000 /* System Timer 1 Secure base address */ -#define CORSTONE310_SYSINFO_BASE_S 0x58020000 /* Corstone-310 System info Block Secure base address */ -#define CORSTONE310_SYSCTRL_BASE_S 0x58021000 /* Corstone-310 System control Block Secure base address */ -#define CORSTONE310_SYSPPU_BASE_S 0x58022000 /* Corstone-310 System Power Policy Unit Secure base address */ -#define CORSTONE310_CPU0PPU_BASE_S 0x58023000 /* Corstone-310 CPU 0 Power Policy Unit Secure base address */ -#define CORSTONE310_MGMTPPU_BASE_S 0x58028000 /* Corstone-310 Management Power Policy Unit Secure base address */ -#define CORSTONE310_DBGPPU_BASE_S 0x58029000 /* Corstone-310 Debug Power Policy Unit Secure base address */ -#define CORSTONE310_NPU0PPU_BASE_S 0x5802A000 /* Corstone-310 NPU 0 Power Policy Unit Secure base address */ -#define SLOWCLK_WDOG_CMSDK_BASE_S 0x5802E000 /* CMSDK based SLOWCLK Watchdog Secure base address */ -#define SLOWCLK_TIMER_CMSDK_BASE_S 0x5802F000 /* CMSDK based SLOWCLK Timer Secure base address */ -#define SYSWDOG_ARMV8_M_CNTRL_BASE_S 0x58040000 /* Secure Watchdog Timer control frame Secure base address */ -#define SYSWDOG_ARMV8_M_REFRESH_BASE_S 0x58041000 /* Secure Watchdog Timer refresh frame Secure base address */ -#define SYSCNTR_CNTRL_BASE_S 0x58100000 /* System Counter Control Secure base address */ -#define SYSCNTR_READ_BASE_S 0x58101000 /* System Counter Read Secure base address */ -/* Secure MSTEXPPIHL Peripheral region */ -#define U55_TIMING_ADAPTER_0_BASE_S 0x58103000 /* Ethos-U55 Timing Adapter 0 APB registers Secure base address */ -#define U55_TIMING_ADAPTER_1_BASE_S 0x58103200 /* Ethos-U55 Timing Adapter 1 APB registers Secure base address */ -#define FPGA_SBCon_I2C_TOUCH_BASE_S 0x59200000 /* FPGA - SBCon I2C (Touch) Secure base address */ -#define FPGA_SBCon_I2C_AUDIO_BASE_S 0x59201000 /* FPGA - SBCon I2C (Audio Conf) Secure base address */ -#define FPGA_SPI_ADC_BASE_S 0x59202000 /* FPGA - PL022 (SPI ADC) Secure base address */ -#define FPGA_SPI_SHIELD0_BASE_S 0x59203000 /* FPGA - PL022 (SPI Shield0) Secure base address */ -#define FPGA_SPI_SHIELD1_BASE_S 0x59204000 /* FPGA - PL022 (SPI Shield1) Secure base address */ -#define SBCon_I2C_SHIELD0_BASE_S 0x59205000 /* SBCon (I2C - Shield0) Secure base address */ -#define SBCon_I2C_SHIELD1_BASE_S 0x59206000 /* SBCon (I2C – Shield1) Secure base address */ -#define USER_APB_BASE_S 0x59207000 /* USER APB Secure base address */ -#define FPGA_DDR4_EEPROM_BASE_S 0x59208000 /* FPGA - SBCon I2C (DDR4 EEPROM) Secure base address */ -#define FPGA_SCC_BASE_S 0x59300000 /* FPGA - SCC registers Secure base address */ -#define FPGA_I2S_BASE_S 0x59301000 /* FPGA - I2S (Audio) Secure base address */ -#define FPGA_IO_BASE_S 0x59302000 /* FPGA - IO (System Ctrl + I/O) Secure base address */ -#define UART0_BASE_S 0x59303000 /* UART 0 Secure base address */ -#define UART1_BASE_S 0x59304000 /* UART 1 Secure base address */ -#define UART2_BASE_S 0x59305000 /* UART 2 Secure base address */ -#define UART3_BASE_S 0x59306000 /* UART 3 Secure base address */ -#define UART4_BASE_S 0x59307000 /* UART 4 Secure base address */ -#define UART5_BASE_S 0x59308000 /* UART 5 Secure base address */ -#define CLCD_Config_Reg_BASE_S 0x5930A000 /* CLCD Config Reg Secure base address */ -#define RTC_BASE_S 0x5930B000 /* RTC Secure base address */ -#define DDR4_BLK1_BASE_S 0x70000000 /* DDR4 block 1 Secure base address */ -#define DDR4_BLK3_BASE_S 0x90000000 /* DDR4 block 3 Secure base address */ -#define DDR4_BLK5_BASE_S 0xB0000000 /* DDR4 block 5 Secure base address */ -#define DDR4_BLK7_BASE_S 0xD0000000 /* DDR4 block 7 Secure base address */ - -/* Memory map addresses exempt from memory attribution by both the SAU and IDAU */ -#define CORSTONE310_EWIC_BASE 0xE0047000 /* External Wakeup Interrupt Controller - * Access from Non-secure software is only allowed - * if AIRCR.BFHFNMINS is set to 1 */ - -/* Memory size definitions */ -#define ITCM_SIZE (0x00008000) /* 32 kB */ -#define DTCM_BLK_SIZE (0x00002000) /* 8 kB */ -#define DTCM_BLK_NUM (0x4) /* Number of DTCM blocks */ -#define SRAM_SIZE (0x00200000) /* 2 MB */ -#define ISRAM0_SIZE (0x00200000) /* 2 MB */ -#define ISRAM1_SIZE (0x00200000) /* 2 MB */ -#define QSPI_SRAM_SIZE (0x00800000) /* 8 MB */ -#define DDR4_BLK_SIZE (0x10000000) /* 256 MB */ -#define DDR4_BLK_NUM (0x8) /* Number of DDR4 blocks */ - -/* Defines for Driver MPC's */ -/* SRAM -- 2 MB */ -#define MPC_SRAM_RANGE_BASE_NS (SRAM_BASE_NS) -#define MPC_SRAM_RANGE_LIMIT_NS (SRAM_BASE_NS + SRAM_SIZE-1) -#define MPC_SRAM_RANGE_OFFSET_NS (0x0) -#define MPC_SRAM_RANGE_BASE_S (SRAM_BASE_S) -#define MPC_SRAM_RANGE_LIMIT_S (SRAM_BASE_S + SRAM_SIZE-1) -#define MPC_SRAM_RANGE_OFFSET_S (0x0) - -/* QSPI -- 8 MB */ -#define MPC_QSPI_RANGE_BASE_NS (QSPI_SRAM_BASE_NS) -#define MPC_QSPI_RANGE_LIMIT_NS (QSPI_SRAM_BASE_NS + QSPI_SRAM_SIZE-1) -#define MPC_QSPI_RANGE_OFFSET_NS (0x0) -#define MPC_QSPI_RANGE_BASE_S (QSPI_SRAM_BASE_S) -#define MPC_QSPI_RANGE_LIMIT_S (QSPI_SRAM_BASE_S + QSPI_SRAM_SIZE-1) -#define MPC_QSPI_RANGE_OFFSET_S (0x0) - -/* ISRAM0 -- 2 MB*/ -#define MPC_ISRAM0_RANGE_BASE_NS (ISRAM0_BASE_NS) -#define MPC_ISRAM0_RANGE_LIMIT_NS (ISRAM0_BASE_NS + ISRAM0_SIZE-1) -#define MPC_ISRAM0_RANGE_OFFSET_NS (0x0) -#define MPC_ISRAM0_RANGE_BASE_S (ISRAM0_BASE_S) -#define MPC_ISRAM0_RANGE_LIMIT_S (ISRAM0_BASE_S + ISRAM0_SIZE-1) -#define MPC_ISRAM0_RANGE_OFFSET_S (0x0) - -/* ISRAM1 -- 2 MB */ -#define MPC_ISRAM1_RANGE_BASE_NS (ISRAM1_BASE_NS) -#define MPC_ISRAM1_RANGE_LIMIT_NS (ISRAM1_BASE_NS + ISRAM1_SIZE-1) -#define MPC_ISRAM1_RANGE_OFFSET_NS (0x0) -#define MPC_ISRAM1_RANGE_BASE_S (ISRAM1_BASE_S) -#define MPC_ISRAM1_RANGE_LIMIT_S (ISRAM1_BASE_S + ISRAM1_SIZE-1) -#define MPC_ISRAM1_RANGE_OFFSET_S (0x0) - -/* DDR4 -- 2GB (8 * 256 MB) */ -#define MPC_DDR4_BLK0_RANGE_BASE_NS (DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK0_RANGE_LIMIT_NS (DDR4_BLK0_BASE_NS + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK0_RANGE_OFFSET_NS (0x0) -#define MPC_DDR4_BLK1_RANGE_BASE_S (DDR4_BLK1_BASE_S) -#define MPC_DDR4_BLK1_RANGE_LIMIT_S (DDR4_BLK1_BASE_S + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK1_RANGE_OFFSET_S (DDR4_BLK1_BASE_S - DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK2_RANGE_BASE_NS (DDR4_BLK2_BASE_NS) -#define MPC_DDR4_BLK2_RANGE_LIMIT_NS (DDR4_BLK2_BASE_NS + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK2_RANGE_OFFSET_NS (DDR4_BLK2_BASE_NS - DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK3_RANGE_BASE_S (DDR4_BLK3_BASE_S) -#define MPC_DDR4_BLK3_RANGE_LIMIT_S (DDR4_BLK3_BASE_S + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK3_RANGE_OFFSET_S (DDR4_BLK3_BASE_S - DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK4_RANGE_BASE_NS (DDR4_BLK4_BASE_NS) -#define MPC_DDR4_BLK4_RANGE_LIMIT_NS (DDR4_BLK4_BASE_NS + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK4_RANGE_OFFSET_NS (DDR4_BLK4_BASE_NS - DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK5_RANGE_BASE_S (DDR4_BLK5_BASE_S) -#define MPC_DDR4_BLK5_RANGE_LIMIT_S (DDR4_BLK5_BASE_S + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK5_RANGE_OFFSET_S (DDR4_BLK5_BASE_S - DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK6_RANGE_BASE_NS (DDR4_BLK6_BASE_NS) -#define MPC_DDR4_BLK6_RANGE_LIMIT_NS (DDR4_BLK6_BASE_NS + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK6_RANGE_OFFSET_NS (DDR4_BLK6_BASE_NS - DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK7_RANGE_BASE_S (DDR4_BLK7_BASE_S) -#define MPC_DDR4_BLK7_RANGE_LIMIT_S (DDR4_BLK7_BASE_S + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK7_RANGE_OFFSET_S (DDR4_BLK7_BASE_S - DDR4_BLK0_BASE_NS) - -#endif /* __PLATFORM_BASE_ADDRESS_H__ */ diff --git a/Examples/cmsis_build/RTE/Device/SSE-310-MPS3/region_defs.h b/Examples/cmsis_build/RTE/Device/SSE-310-MPS3/region_defs.h deleted file mode 100644 index c8cd91967..000000000 --- a/Examples/cmsis_build/RTE/Device/SSE-310-MPS3/region_defs.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2016-2020 Arm Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __REGION_DEFS_H__ -#define __REGION_DEFS_H__ - -#include "region_limits.h" - -/* ************************************************************** - * WARNING: this file is parsed both by the C/C++ compiler - * and the linker. As a result the syntax must be valid not only - * for C/C++ but for the linker scripts too. - * Beware of the following limitations: - * - LD (GCC linker) requires white space around operators. - * - UL postfix for macros is not suported by the linker script - ****************************************************************/ - -/* Secure regions */ -#define S_CODE_START ( S_ROM_ALIAS ) -#define S_CODE_SIZE ( TOTAL_S_ROM_SIZE ) -#define S_CODE_LIMIT ( S_CODE_START + S_CODE_SIZE ) - -#define S_DATA_START ( S_RAM_ALIAS ) -#define S_DATA_SIZE ( TOTAL_S_RAM_SIZE ) -#define S_DATA_LIMIT ( S_DATA_START + S_DATA_SIZE ) - -/* Non-Secure regions */ -#define NS_CODE_START ( NS_ROM_ALIAS ) -#define NS_CODE_SIZE ( TOTAL_NS_ROM_SIZE ) -#define NS_CODE_LIMIT ( NS_CODE_START + NS_CODE_SIZE ) - -#define NS_DATA_START ( NS_RAM_ALIAS ) -#define NS_DATA_SIZE ( TOTAL_NS_RAM_SIZE ) -#define NS_DATA_LIMIT ( NS_DATA_START + NS_DATA_SIZE ) - -#endif /* __REGION_DEFS_H__ */ diff --git a/Examples/cmsis_build/RTE/Device/SSE-310-MPS3/region_limits.h b/Examples/cmsis_build/RTE/Device/SSE-310-MPS3/region_limits.h deleted file mode 100644 index 4ca8f9904..000000000 --- a/Examples/cmsis_build/RTE/Device/SSE-310-MPS3/region_limits.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2018-2022 Arm Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __REGION_LIMITS_H__ -#define __REGION_LIMITS_H__ - -/* ************************************************************** - * WARNING: this file is parsed both by the C/C++ compiler - * and the linker. As a result the syntax must be valid not only - * for C/C++ but for the linker scripts too. - * Beware of the following limitations: - * - LD (GCC linker) requires white space around operators. - * - UL postfix for macros is not suported by the linker script - ****************************************************************/ - -/* Secure Code */ -#define S_ROM_ALIAS (0x11000000) /* SRAM_BASE_S */ -#define TOTAL_S_ROM_SIZE (0x00020000) /* 128 kB */ - -/* Secure Data */ -#define S_RAM_ALIAS (0x31000000) /* ISRAM0_BASE_S */ -#define TOTAL_S_RAM_SIZE (0x00040000) /* 256 kB */ - -/* Non-Secure Code */ -#define NS_ROM_ALIAS (0x01000000 + 0x00020000) /* SRAM_BASE_NS */ -#define TOTAL_NS_ROM_SIZE (0x00020000) /* 128 kB */ - -/* Non-Secure Data */ -#define NS_RAM_ALIAS (0x21000000 + 0x00040000) /* ISRAM0_BASE_NS */ -#define TOTAL_NS_RAM_SIZE (0x00040000) /* 256 kB */ - -/* Heap and Stack sizes for secure and nonsecure applications */ -#define HEAP_SIZE (0x00000400) /* 1 KiB */ -#define STACK_SIZE (0x00000400) /* 1 KiB */ - -#endif /* __REGION_LIMITS_H__ */ diff --git a/Examples/cmsis_build/RTE/Device/SSE-310-MPS3/system_SSE310MPS3.c b/Examples/cmsis_build/RTE/Device/SSE-310-MPS3/system_SSE310MPS3.c deleted file mode 100644 index b8d5a2916..000000000 --- a/Examples/cmsis_build/RTE/Device/SSE-310-MPS3/system_SSE310MPS3.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (c) 2009-2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * This file is derivative of CMSIS system_ARMCM85.c - * Git SHA: 61ad1303bc50450130cfb540caa384875a260b91 - */ - -#include "SSE310MPS3.h" - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ - #define XTAL (32000000UL) - #define SYSTEM_CLOCK (XTAL) - #define PERIPHERAL_CLOCK (25000000UL) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; -uint32_t PeripheralClock = PERIPHERAL_CLOCK; - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; - PeripheralClock = PERIPHERAL_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); -#endif - - /* Set CPDLPSTATE.RLPSTATE to 0 - Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state. - Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */ - PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk | - PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk | - PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk ); - -#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ - - /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ - /* PDEPU ON, Clock OFF */ - PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - - /* Enable Loop and branch info cache */ - SCB->CCR |= SCB_CCR_LOB_Msk; - - /* Enable Branch Prediction */ - SCB->CCR |= SCB_CCR_BP_Msk; - - __DSB(); - __ISB(); -} diff --git a/Examples/cmsis_build/RTE/Device/SSE-310-MPS3/system_SSE310MPS3.h b/Examples/cmsis_build/RTE/Device/SSE-310-MPS3/system_SSE310MPS3.h deleted file mode 100644 index b60758421..000000000 --- a/Examples/cmsis_build/RTE/Device/SSE-310-MPS3/system_SSE310MPS3.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2009-2022 Arm Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * This file is derivative of CMSIS system_ARMCM85.h - * Git SHA: 61ad1303bc50450130cfb540caa384875a260b91 - */ - -#ifndef __SYSTEM_CORE_INIT_H__ -#define __SYSTEM_CORE_INIT_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ -extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency */ - -/** - \brief Exception / Interrupt Handler Function Prototype -*/ -typedef void(*VECTOR_TABLE_Type)(void); - -/** - * \brief Initializes the system - */ -extern void SystemInit(void); - -/** - * \brief Restores system core clock - */ -extern void SystemCoreClockUpdate(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_CORE_INIT_H__ */ diff --git a/Examples/cmsis_build/buildall_cs300.bat b/Examples/cmsis_build/buildall_cs300.bat index 6a88b1fbb..64b4dd0e4 100644 --- a/Examples/cmsis_build/buildall_cs300.bat +++ b/Examples/cmsis_build/buildall_cs300.bat @@ -1,13 +1,15 @@ -cbuild "projects/bayes.Release+VHT-Corstone-300.cprj" -cbuild "projects/linearinterp.Release+VHT-Corstone-300.cprj" -cbuild "projects/classmarks.Release+VHT-Corstone-300.cprj" -cbuild "projects/matrix.Release+VHT-Corstone-300.cprj" -cbuild "projects/convolution.Release+VHT-Corstone-300.cprj" -cbuild "projects/signalconverge.Release+VHT-Corstone-300.cprj" -cbuild "projects/dotproduct.Release+VHT-Corstone-300.cprj" -cbuild "projects/sincos.Release+VHT-Corstone-300.cprj" -cbuild "projects/fftbin.Release+VHT-Corstone-300.cprj" -cbuild "projects/svm.Release+VHT-Corstone-300.cprj" -cbuild "projects/fir.Release+VHT-Corstone-300.cprj" -cbuild "projects/variance.Release+VHT-Corstone-300.cprj" -cbuild "projects/graphicequalizer.Release+VHT-Corstone-300.cprj" \ No newline at end of file +cbuild -O cprj examples_ac6.csolution.yml --update-rte -r --toolchain AC6 -c bayes.Release+VHT-Corstone-300 +cbuild -O cprj examples_ac6.csolution.yml --update-rte -r --toolchain AC6 -c linearinterp.Release+VHT-Corstone-300 +cbuild -O cprj examples_ac6.csolution.yml --update-rte -r --toolchain AC6 -c classmarks.Release+VHT-Corstone-300 +cbuild -O cprj examples_ac6.csolution.yml --update-rte -r --toolchain AC6 -c matrix.Release+VHT-Corstone-300 +cbuild -O cprj examples_ac6.csolution.yml --update-rte -r --toolchain AC6 -c convolution.Release+VHT-Corstone-300 +cbuild -O cprj examples_ac6.csolution.yml --update-rte -r --toolchain AC6 -c signalconverge.Release+VHT-Corstone-300 +cbuild -O cprj examples_ac6.csolution.yml --update-rte -r --toolchain AC6 -c dotproduct.Release+VHT-Corstone-300 +cbuild -O cprj examples_ac6.csolution.yml --update-rte -r --toolchain AC6 -c sincos.Release+VHT-Corstone-300 +cbuild -O cprj examples_ac6.csolution.yml --update-rte -r --toolchain AC6 -c fftbin.Release+VHT-Corstone-300 +cbuild -O cprj examples_ac6.csolution.yml --update-rte -r --toolchain AC6 -c svm.Release+VHT-Corstone-300 +cbuild -O cprj examples_ac6.csolution.yml --update-rte -r --toolchain AC6 -c fir.Release+VHT-Corstone-300 +cbuild -O cprj examples_ac6.csolution.yml --update-rte -r --toolchain AC6 -c variance.Release+VHT-Corstone-300 +cbuild -O cprj examples_ac6.csolution.yml --update-rte -r --toolchain AC6 -c graphicequalizer.Release+VHT-Corstone-300 + + diff --git a/Examples/cmsis_build/projects/bayes.Release+VHT-Corstone-300.cprj b/Examples/cmsis_build/cprj/bayes.Release+VHT-Corstone-300.cprj similarity index 80% rename from Examples/cmsis_build/projects/bayes.Release+VHT-Corstone-300.cprj rename to Examples/cmsis_build/cprj/bayes.Release+VHT-Corstone-300.cprj index bfc806d9a..60da6af52 100644 --- a/Examples/cmsis_build/projects/bayes.Release+VHT-Corstone-300.cprj +++ b/Examples/cmsis_build/cprj/bayes.Release+VHT-Corstone-300.cprj @@ -1,49 +1,47 @@ - + Automatically generated project - - + + - + - + - + ../../../Include;../../../PrivateInclude - - - - - - + + - + + + + + + + + - - - + - - - diff --git a/Examples/cmsis_build/projects/classmarks.Release+VHT-Corstone-300.cprj b/Examples/cmsis_build/cprj/classmarks.Release+VHT-Corstone-300.cprj similarity index 80% rename from Examples/cmsis_build/projects/classmarks.Release+VHT-Corstone-300.cprj rename to Examples/cmsis_build/cprj/classmarks.Release+VHT-Corstone-300.cprj index 2fbb46811..30f28af98 100644 --- a/Examples/cmsis_build/projects/classmarks.Release+VHT-Corstone-300.cprj +++ b/Examples/cmsis_build/cprj/classmarks.Release+VHT-Corstone-300.cprj @@ -1,49 +1,47 @@ - + Automatically generated project - - + + - + - + - + ../../../Include;../../../PrivateInclude - - - - - - + + - + + + + + + + + - - - + - - - diff --git a/Examples/cmsis_build/projects/convolution.Release+VHT-Corstone-300.cprj b/Examples/cmsis_build/cprj/convolution.Release+VHT-Corstone-300.cprj similarity index 80% rename from Examples/cmsis_build/projects/convolution.Release+VHT-Corstone-300.cprj rename to Examples/cmsis_build/cprj/convolution.Release+VHT-Corstone-300.cprj index 486e81990..49649c179 100644 --- a/Examples/cmsis_build/projects/convolution.Release+VHT-Corstone-300.cprj +++ b/Examples/cmsis_build/cprj/convolution.Release+VHT-Corstone-300.cprj @@ -1,49 +1,47 @@ - + Automatically generated project - - + + - + - + - + ../../ARM/arm_convolution_example;../../../Include;../../../PrivateInclude - - - - - - + + - + + + + + + + + - - - + - - - diff --git a/Examples/cmsis_build/projects/dotproduct.Release+VHT-Corstone-300.cprj b/Examples/cmsis_build/cprj/dotproduct.Release+VHT-Corstone-300.cprj similarity index 80% rename from Examples/cmsis_build/projects/dotproduct.Release+VHT-Corstone-300.cprj rename to Examples/cmsis_build/cprj/dotproduct.Release+VHT-Corstone-300.cprj index f96f865d5..4923a951e 100644 --- a/Examples/cmsis_build/projects/dotproduct.Release+VHT-Corstone-300.cprj +++ b/Examples/cmsis_build/cprj/dotproduct.Release+VHT-Corstone-300.cprj @@ -1,49 +1,47 @@ - + Automatically generated project - - + + - + - + - + ../../../Include;../../../PrivateInclude - - - - - - + + - + + + + + + + + - - - + - - - diff --git a/Examples/cmsis_build/projects/fftbin.Release+VHT-Corstone-300.cprj b/Examples/cmsis_build/cprj/fftbin.Release+VHT-Corstone-300.cprj similarity index 80% rename from Examples/cmsis_build/projects/fftbin.Release+VHT-Corstone-300.cprj rename to Examples/cmsis_build/cprj/fftbin.Release+VHT-Corstone-300.cprj index 638a90c01..4d8c86363 100644 --- a/Examples/cmsis_build/projects/fftbin.Release+VHT-Corstone-300.cprj +++ b/Examples/cmsis_build/cprj/fftbin.Release+VHT-Corstone-300.cprj @@ -1,49 +1,47 @@ - + Automatically generated project - - + + - + - + - + ../../../Include;../../../PrivateInclude - - - - - - + + - + + + + + + + + - - - + - - - diff --git a/Examples/cmsis_build/projects/fir.Release+VHT-Corstone-300.cprj b/Examples/cmsis_build/cprj/fir.Release+VHT-Corstone-300.cprj similarity index 81% rename from Examples/cmsis_build/projects/fir.Release+VHT-Corstone-300.cprj rename to Examples/cmsis_build/cprj/fir.Release+VHT-Corstone-300.cprj index 500500cd6..ac7b087cc 100644 --- a/Examples/cmsis_build/projects/fir.Release+VHT-Corstone-300.cprj +++ b/Examples/cmsis_build/cprj/fir.Release+VHT-Corstone-300.cprj @@ -1,49 +1,47 @@ - + Automatically generated project - - + + - + - + - + ../../ARM/arm_fir_example;../../../Include;../../../PrivateInclude - - - - - - + + - + + + + + + + + - - - + - - - diff --git a/Examples/cmsis_build/projects/graphicequalizer.Release+VHT-Corstone-300.cprj b/Examples/cmsis_build/cprj/graphicequalizer.Release+VHT-Corstone-300.cprj similarity index 80% rename from Examples/cmsis_build/projects/graphicequalizer.Release+VHT-Corstone-300.cprj rename to Examples/cmsis_build/cprj/graphicequalizer.Release+VHT-Corstone-300.cprj index 9b1d01a33..7a5f18a39 100644 --- a/Examples/cmsis_build/projects/graphicequalizer.Release+VHT-Corstone-300.cprj +++ b/Examples/cmsis_build/cprj/graphicequalizer.Release+VHT-Corstone-300.cprj @@ -1,49 +1,47 @@ - + Automatically generated project - - + + - + - + - + ../../ARM/arm_graphic_equalizer_example;../../../Include;../../../PrivateInclude - - - - - - + + - + + + + + + + + - - - + - - - diff --git a/Examples/cmsis_build/projects/linearinterp.Release+VHT-Corstone-300.cprj b/Examples/cmsis_build/cprj/linearinterp.Release+VHT-Corstone-300.cprj similarity index 80% rename from Examples/cmsis_build/projects/linearinterp.Release+VHT-Corstone-300.cprj rename to Examples/cmsis_build/cprj/linearinterp.Release+VHT-Corstone-300.cprj index e7c73c030..9c0177315 100644 --- a/Examples/cmsis_build/projects/linearinterp.Release+VHT-Corstone-300.cprj +++ b/Examples/cmsis_build/cprj/linearinterp.Release+VHT-Corstone-300.cprj @@ -1,49 +1,47 @@ - + Automatically generated project - - + + - + - + - + ../../ARM/arm_linear_interp_example;../../../Include;../../../PrivateInclude - - - - - - + + - + + + + + + + + - - - + - - - diff --git a/Examples/cmsis_build/projects/matrix.Release+VHT-Corstone-300.cprj b/Examples/cmsis_build/cprj/matrix.Release+VHT-Corstone-300.cprj similarity index 80% rename from Examples/cmsis_build/projects/matrix.Release+VHT-Corstone-300.cprj rename to Examples/cmsis_build/cprj/matrix.Release+VHT-Corstone-300.cprj index 87f7798dd..c7647d1cc 100644 --- a/Examples/cmsis_build/projects/matrix.Release+VHT-Corstone-300.cprj +++ b/Examples/cmsis_build/cprj/matrix.Release+VHT-Corstone-300.cprj @@ -1,49 +1,47 @@ - + Automatically generated project - - + + - + - + - + ../../ARM/arm_matrix_example;../../../Include;../../../PrivateInclude - - - - - - + + - + + + + + + + + - - - + - - - diff --git a/Examples/cmsis_build/projects/signalconverge.Release+VHT-Corstone-300.cprj b/Examples/cmsis_build/cprj/signalconverge.Release+VHT-Corstone-300.cprj similarity index 80% rename from Examples/cmsis_build/projects/signalconverge.Release+VHT-Corstone-300.cprj rename to Examples/cmsis_build/cprj/signalconverge.Release+VHT-Corstone-300.cprj index 8a8805bd8..1fe564bea 100644 --- a/Examples/cmsis_build/projects/signalconverge.Release+VHT-Corstone-300.cprj +++ b/Examples/cmsis_build/cprj/signalconverge.Release+VHT-Corstone-300.cprj @@ -1,49 +1,47 @@ - + Automatically generated project - - + + - + - + - + ../../ARM/arm_signal_converge_example;../../../Include;../../../PrivateInclude - - - - - - + + - + + + + + + + + - - - + - - - diff --git a/Examples/cmsis_build/projects/sincos.Release+VHT-Corstone-300.cprj b/Examples/cmsis_build/cprj/sincos.Release+VHT-Corstone-300.cprj similarity index 80% rename from Examples/cmsis_build/projects/sincos.Release+VHT-Corstone-300.cprj rename to Examples/cmsis_build/cprj/sincos.Release+VHT-Corstone-300.cprj index 3e2927b58..1233b92d3 100644 --- a/Examples/cmsis_build/projects/sincos.Release+VHT-Corstone-300.cprj +++ b/Examples/cmsis_build/cprj/sincos.Release+VHT-Corstone-300.cprj @@ -1,49 +1,47 @@ - + Automatically generated project - - + + - + - + - + ../../../Include;../../../PrivateInclude - - - - - - + + - + + + + + + + + - - - + - - - diff --git a/Examples/cmsis_build/projects/svm.Release+VHT-Corstone-300.cprj b/Examples/cmsis_build/cprj/svm.Release+VHT-Corstone-300.cprj similarity index 80% rename from Examples/cmsis_build/projects/svm.Release+VHT-Corstone-300.cprj rename to Examples/cmsis_build/cprj/svm.Release+VHT-Corstone-300.cprj index aa4ef38df..4c5789d0e 100644 --- a/Examples/cmsis_build/projects/svm.Release+VHT-Corstone-300.cprj +++ b/Examples/cmsis_build/cprj/svm.Release+VHT-Corstone-300.cprj @@ -1,49 +1,47 @@ - + Automatically generated project - - + + - + - + - + ../../../Include;../../../PrivateInclude - - - - - - + + - + + + + + + + + - - - + - - - diff --git a/Examples/cmsis_build/projects/variance.Release+VHT-Corstone-300.cprj b/Examples/cmsis_build/cprj/variance.Release+VHT-Corstone-300.cprj similarity index 80% rename from Examples/cmsis_build/projects/variance.Release+VHT-Corstone-300.cprj rename to Examples/cmsis_build/cprj/variance.Release+VHT-Corstone-300.cprj index c050c7352..e268877e1 100644 --- a/Examples/cmsis_build/projects/variance.Release+VHT-Corstone-300.cprj +++ b/Examples/cmsis_build/cprj/variance.Release+VHT-Corstone-300.cprj @@ -1,49 +1,47 @@ - + Automatically generated project - - + + - + - + - + ../../../Include;../../../PrivateInclude - - - - - - + + - + + + + + + + + - - - + - - - diff --git a/Examples/cmsis_build/examples_ac6.csolution.yml b/Examples/cmsis_build/examples_ac6.csolution.yml index 03d8df703..cf3001f44 100644 --- a/Examples/cmsis_build/examples_ac6.csolution.yml +++ b/Examples/cmsis_build/examples_ac6.csolution.yml @@ -44,11 +44,10 @@ solution: - --info=veneers packs: - - pack: ARM::CMSIS-DSP@1.14.4 - - pack: ARM::CMSIS@5.9.0 - - pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0 - - pack: ARM::V2M_MPS3_SSE_310_BSP@1.1.0 - - pack: Keil::ARM_Compiler@1.7.2 + - pack: ARM::CMSIS@6.0.0 + - pack: ARM::V2M_MPS3_SSE_300_BSP@1.4.0 + - pack: ARM::CMSIS-Compiler@2.0.0 + - pack: ARM::Cortex_DFP@1.0.0 target-types: - type: VHT-Corstone-310 diff --git a/Examples/cmsis_build/projects/RTE/Device/ARMCM0P/regions_ARMCM0P.h b/Examples/cmsis_build/projects/RTE/Device/ARMCM0P/regions_ARMCM0P.h deleted file mode 100644 index 59943ae15..000000000 --- a/Examples/cmsis_build/projects/RTE/Device/ARMCM0P/regions_ARMCM0P.h +++ /dev/null @@ -1,60 +0,0 @@ -#ifndef REGIONS_ARMCM0P_H -#define REGIONS_ARMCM0P_H - - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Device pack: ARM.CMSIS.5.9.0 -// Device pack used to generate this file - -// ROM Configuration -// ======================= -// IROM1=<__ROM0> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x00000000 -#define __ROM0_BASE 0x00000000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00040000 -#define __ROM0_SIZE 0x00040000 -// Default region -// Enables memory region globally for the application. -#define __ROM0_DEFAULT 1 -// Startup -// Selects region to be used for startup code. -#define __ROM0_STARTUP 1 -// - -// - -// RAM Configuration -// ======================= -// IRAM1=<__RAM0> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x20000000 -#define __RAM0_BASE 0x20000000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00020000 -#define __RAM0_SIZE 0x00020000 -// Default region -// Enables memory region globally for the application. -#define __RAM0_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM0_NOINIT 0 -// - -// - -// Stack / Heap Configuration -// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 -// - - -#endif /* REGIONS_ARMCM0P_H */ diff --git a/Examples/cmsis_build/projects/RTE/Device/ARMCM7_DP/regions_ARMCM7_DP.h b/Examples/cmsis_build/projects/RTE/Device/ARMCM7_DP/regions_ARMCM7_DP.h deleted file mode 100644 index 537369568..000000000 --- a/Examples/cmsis_build/projects/RTE/Device/ARMCM7_DP/regions_ARMCM7_DP.h +++ /dev/null @@ -1,60 +0,0 @@ -#ifndef REGIONS_ARMCM7_DP_H -#define REGIONS_ARMCM7_DP_H - - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Device pack: ARM.CMSIS.5.9.0 -// Device pack used to generate this file - -// ROM Configuration -// ======================= -// IROM1=<__ROM0> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x00000000 -#define __ROM0_BASE 0x00000000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00040000 -#define __ROM0_SIZE 0x00040000 -// Default region -// Enables memory region globally for the application. -#define __ROM0_DEFAULT 1 -// Startup -// Selects region to be used for startup code. -#define __ROM0_STARTUP 1 -// - -// - -// RAM Configuration -// ======================= -// IRAM1=<__RAM0> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x20000000 -#define __RAM0_BASE 0x20000000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00020000 -#define __RAM0_SIZE 0x00020000 -// Default region -// Enables memory region globally for the application. -#define __RAM0_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM0_NOINIT 0 -// - -// - -// Stack / Heap Configuration -// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 -// - - -#endif /* REGIONS_ARMCM7_DP_H */ diff --git a/Examples/cmsis_build/projects/RTE/Device/SSE_300_MPS3/regions_SSE_300_MPS3.h b/Examples/cmsis_build/projects/RTE/Device/SSE_300_MPS3/regions_SSE_300_MPS3.h deleted file mode 100644 index eabdf878a..000000000 --- a/Examples/cmsis_build/projects/RTE/Device/SSE_300_MPS3/regions_SSE_300_MPS3.h +++ /dev/null @@ -1,332 +0,0 @@ -#ifndef REGIONS_SSE_300_MPS3_H -#define REGIONS_SSE_300_MPS3_H - - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Device pack: ARM.V2M_MPS3_SSE_300_BSP.1.3.0 -// Device pack used to generate this file - -// ROM Configuration -// ======================= -// - -// RAM Configuration -// ======================= -// ITCM_NS=<__RAM0> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x00000000 -#define __RAM0_BASE 0x00000000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00080000 -#define __RAM0_SIZE 0x00080000 -// Default region -// Enables memory region globally for the application. -#define __RAM0_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM0_NOINIT 0 -// - -// SRAM_NS=<__RAM1> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x01000000 -#define __RAM1_BASE 0x01000000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00100000 -#define __RAM1_SIZE 0x00100000 -// Default region -// Enables memory region globally for the application. -#define __RAM1_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM1_NOINIT 0 -// - -// DTCM0_NS=<__RAM2> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x20000000 -#define __RAM2_BASE 0x20000000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00020000 -#define __RAM2_SIZE 0x00020000 -// Default region -// Enables memory region globally for the application. -#define __RAM2_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM2_NOINIT 0 -// - -// DTCM1_NS=<__RAM3> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x20020000 -#define __RAM3_BASE 0x20020000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00020000 -#define __RAM3_SIZE 0x00020000 -// Default region -// Enables memory region globally for the application. -#define __RAM3_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM3_NOINIT 0 -// - -// DTCM2_NS=<__RAM4> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x20040000 -#define __RAM4_BASE 0x20040000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00020000 -#define __RAM4_SIZE 0x00020000 -// Default region -// Enables memory region globally for the application. -#define __RAM4_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM4_NOINIT 0 -// - -// DTCM3_NS=<__RAM5> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x20060000 -#define __RAM5_BASE 0x20060000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00020000 -#define __RAM5_SIZE 0x00020000 -// Default region -// Enables memory region globally for the application. -#define __RAM5_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM5_NOINIT 0 -// - -// ISRAM0_NS=<__RAM6> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x21000000 -#define __RAM6_BASE 0x21000000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00100000 -#define __RAM6_SIZE 0x00100000 -// Default region -// Enables memory region globally for the application. -#define __RAM6_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM6_NOINIT 0 -// - -// ISRAM1_NS=<__RAM7> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x21100000 -#define __RAM7_BASE 0x21100000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00100000 -#define __RAM7_SIZE 0x00100000 -// Default region -// Enables memory region globally for the application. -#define __RAM7_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM7_NOINIT 0 -// - -// QSPI_SRAM_NS=<__RAM8> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x28000000 -#define __RAM8_BASE 0x28000000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00800000 -#define __RAM8_SIZE 0x00800000 -// Default region -// Enables memory region globally for the application. -#define __RAM8_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM8_NOINIT 0 -// - -// ITCM_S=<__RAM9> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x10000000 -#define __RAM9_BASE 0x10000000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00080000 -#define __RAM9_SIZE 0x00080000 -// Default region -// Enables memory region globally for the application. -#define __RAM9_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM9_NOINIT 0 -// - -// SRAM_S=<__RAM10> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x11000000 -#define __RAM10_BASE 0x11000000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00100000 -#define __RAM10_SIZE 0x00100000 -// Default region -// Enables memory region globally for the application. -#define __RAM10_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM10_NOINIT 0 -// - -// DTCM0_S=<__RAM11> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x30000000 -#define __RAM11_BASE 0x30000000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00020000 -#define __RAM11_SIZE 0x00020000 -// Default region -// Enables memory region globally for the application. -#define __RAM11_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM11_NOINIT 0 -// - -// DTCM1_S=<__RAM12> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x30020000 -#define __RAM12_BASE 0x30020000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00020000 -#define __RAM12_SIZE 0x00020000 -// Default region -// Enables memory region globally for the application. -#define __RAM12_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM12_NOINIT 0 -// - -// DTCM2_S=<__RAM13> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x30040000 -#define __RAM13_BASE 0x30040000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00020000 -#define __RAM13_SIZE 0x00020000 -// Default region -// Enables memory region globally for the application. -#define __RAM13_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM13_NOINIT 0 -// - -// DTCM3_S=<__RAM14> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x30060000 -#define __RAM14_BASE 0x30060000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00020000 -#define __RAM14_SIZE 0x00020000 -// Default region -// Enables memory region globally for the application. -#define __RAM14_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM14_NOINIT 0 -// - -// ISRAM0_S=<__RAM15> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x31000000 -#define __RAM15_BASE 0x31000000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00100000 -#define __RAM15_SIZE 0x00100000 -// Default region -// Enables memory region globally for the application. -#define __RAM15_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM15_NOINIT 0 -// - -// ISRAM1_S=<__RAM16> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x31100000 -#define __RAM16_BASE 0x31100000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00100000 -#define __RAM16_SIZE 0x00100000 -// Default region -// Enables memory region globally for the application. -#define __RAM16_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM16_NOINIT 0 -// - -// QSPI_SRAM_S=<__RAM17> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x38000000 -#define __RAM17_BASE 0x38000000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00800000 -#define __RAM17_SIZE 0x00800000 -// Default region -// Enables memory region globally for the application. -#define __RAM17_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM17_NOINIT 0 -// - -// - -// Stack / Heap Configuration -// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 -// - - -#endif /* REGIONS_SSE_300_MPS3_H */ diff --git a/Examples/cmsis_build/projects/RTE/Device/SSE_310_MPS3/regions_SSE_310_MPS3.h b/Examples/cmsis_build/projects/RTE/Device/SSE_310_MPS3/regions_SSE_310_MPS3.h deleted file mode 100644 index 53cb3bd71..000000000 --- a/Examples/cmsis_build/projects/RTE/Device/SSE_310_MPS3/regions_SSE_310_MPS3.h +++ /dev/null @@ -1,332 +0,0 @@ -#ifndef REGIONS_SSE_310_MPS3_H -#define REGIONS_SSE_310_MPS3_H - - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Device pack: ARM.V2M_MPS3_SSE_310_BSP.1.1.0 -// Device pack used to generate this file - -// ROM Configuration -// ======================= -// - -// RAM Configuration -// ======================= -// ITCM_NS=<__RAM0> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x00000000 -#define __RAM0_BASE 0x00000000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00008000 -#define __RAM0_SIZE 0x00008000 -// Default region -// Enables memory region globally for the application. -#define __RAM0_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM0_NOINIT 0 -// - -// SRAM_NS=<__RAM1> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x01000000 -#define __RAM1_BASE 0x01000000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00200000 -#define __RAM1_SIZE 0x00200000 -// Default region -// Enables memory region globally for the application. -#define __RAM1_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM1_NOINIT 0 -// - -// DTCM0_NS=<__RAM2> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x20000000 -#define __RAM2_BASE 0x20000000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00002000 -#define __RAM2_SIZE 0x00002000 -// Default region -// Enables memory region globally for the application. -#define __RAM2_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM2_NOINIT 0 -// - -// DTCM1_NS=<__RAM3> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x20002000 -#define __RAM3_BASE 0x20002000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00002000 -#define __RAM3_SIZE 0x00002000 -// Default region -// Enables memory region globally for the application. -#define __RAM3_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM3_NOINIT 0 -// - -// DTCM2_NS=<__RAM4> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x20004000 -#define __RAM4_BASE 0x20004000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00002000 -#define __RAM4_SIZE 0x00002000 -// Default region -// Enables memory region globally for the application. -#define __RAM4_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM4_NOINIT 0 -// - -// DTCM3_NS=<__RAM5> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x20006000 -#define __RAM5_BASE 0x20006000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00002000 -#define __RAM5_SIZE 0x00002000 -// Default region -// Enables memory region globally for the application. -#define __RAM5_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM5_NOINIT 0 -// - -// ISRAM0_NS=<__RAM6> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x21000000 -#define __RAM6_BASE 0x21000000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00200000 -#define __RAM6_SIZE 0x00200000 -// Default region -// Enables memory region globally for the application. -#define __RAM6_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM6_NOINIT 0 -// - -// ISRAM1_NS=<__RAM7> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x21200000 -#define __RAM7_BASE 0x21200000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00200000 -#define __RAM7_SIZE 0x00200000 -// Default region -// Enables memory region globally for the application. -#define __RAM7_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM7_NOINIT 0 -// - -// QSPI_SRAM_NS=<__RAM8> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x28000000 -#define __RAM8_BASE 0x28000000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00800000 -#define __RAM8_SIZE 0x00800000 -// Default region -// Enables memory region globally for the application. -#define __RAM8_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM8_NOINIT 0 -// - -// ITCM_S=<__RAM9> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x10000000 -#define __RAM9_BASE 0x10000000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00008000 -#define __RAM9_SIZE 0x00008000 -// Default region -// Enables memory region globally for the application. -#define __RAM9_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM9_NOINIT 0 -// - -// SRAM_S=<__RAM10> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x11000000 -#define __RAM10_BASE 0x11000000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00200000 -#define __RAM10_SIZE 0x00200000 -// Default region -// Enables memory region globally for the application. -#define __RAM10_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM10_NOINIT 0 -// - -// DTCM0_S=<__RAM11> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x30000000 -#define __RAM11_BASE 0x30000000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00002000 -#define __RAM11_SIZE 0x00002000 -// Default region -// Enables memory region globally for the application. -#define __RAM11_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM11_NOINIT 0 -// - -// DTCM1_S=<__RAM12> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x30002000 -#define __RAM12_BASE 0x30002000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00002000 -#define __RAM12_SIZE 0x00002000 -// Default region -// Enables memory region globally for the application. -#define __RAM12_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM12_NOINIT 0 -// - -// DTCM2_S=<__RAM13> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x30004000 -#define __RAM13_BASE 0x30004000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00002000 -#define __RAM13_SIZE 0x00002000 -// Default region -// Enables memory region globally for the application. -#define __RAM13_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM13_NOINIT 0 -// - -// DTCM3_S=<__RAM14> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x30006000 -#define __RAM14_BASE 0x30006000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00002000 -#define __RAM14_SIZE 0x00002000 -// Default region -// Enables memory region globally for the application. -#define __RAM14_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM14_NOINIT 0 -// - -// ISRAM0_S=<__RAM15> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x31000000 -#define __RAM15_BASE 0x31000000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00200000 -#define __RAM15_SIZE 0x00200000 -// Default region -// Enables memory region globally for the application. -#define __RAM15_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM15_NOINIT 0 -// - -// ISRAM1_S=<__RAM16> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x31200000 -#define __RAM16_BASE 0x31200000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00200000 -#define __RAM16_SIZE 0x00200000 -// Default region -// Enables memory region globally for the application. -#define __RAM16_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM16_NOINIT 0 -// - -// QSPI_SRAM_S=<__RAM17> -// Base address <0x0-0xFFFFFFFF:8> -// Defines base address of memory region. -// Default: 0x38000000 -#define __RAM17_BASE 0x38000000 -// Region size [bytes] <0x0-0xFFFFFFFF:8> -// Defines size of memory region. -// Default: 0x00800000 -#define __RAM17_SIZE 0x00800000 -// Default region -// Enables memory region globally for the application. -#define __RAM17_DEFAULT 1 -// No zero initialize -// Excludes region from zero initialization. -#define __RAM17_NOINIT 0 -// - -// - -// Stack / Heap Configuration -// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 -// - - -#endif /* REGIONS_SSE_310_MPS3_H */ diff --git a/Examples/cmsis_build/projects/RTE/_Release_VHT-Corstone-300/RTE_Components.h b/Examples/cmsis_build/projects/RTE/_Release_VHT-Corstone-300/RTE_Components.h index b865dda87..e6d9f8643 100644 --- a/Examples/cmsis_build/projects/RTE/_Release_VHT-Corstone-300/RTE_Components.h +++ b/Examples/cmsis_build/projects/RTE/_Release_VHT-Corstone-300/RTE_Components.h @@ -1,6 +1,6 @@ /* * CSOLUTION generated file: DO NOT EDIT! - * Generated by: csolution version 2.0.0 + * Generated by: csolution version 2.4.0 * * Project: 'bayes.Release+VHT-Corstone-300' * Target: 'Release+VHT-Corstone-300' diff --git a/Examples/cmsis_build/projects/RTE/_Release_VHT-Corstone-310/RTE_Components.h b/Examples/cmsis_build/projects/RTE/_Release_VHT-Corstone-310/RTE_Components.h deleted file mode 100644 index cbccf152a..000000000 --- a/Examples/cmsis_build/projects/RTE/_Release_VHT-Corstone-310/RTE_Components.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * CSOLUTION generated file: DO NOT EDIT! - * Generated by: csolution version 2.0.0 - * - * Project: 'bayes.Release+VHT-Corstone-310' - * Target: 'Release+VHT-Corstone-310' - */ - -#ifndef RTE_COMPONENTS_H -#define RTE_COMPONENTS_H - - -/* - * Define the Device Header File: - */ -#define CMSIS_device_header "SSE310MPS3.h" - - - -#endif /* RTE_COMPONENTS_H */ diff --git a/Examples/cmsis_build/projects/RTE/_Release_VHT_M0P/RTE_Components.h b/Examples/cmsis_build/projects/RTE/_Release_VHT_M0P/RTE_Components.h deleted file mode 100644 index 603cc38cb..000000000 --- a/Examples/cmsis_build/projects/RTE/_Release_VHT_M0P/RTE_Components.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * CSOLUTION generated file: DO NOT EDIT! - * Generated by: csolution version 2.0.0 - * - * Project: 'bayes.Release+VHT_M0P' - * Target: 'Release+VHT_M0P' - */ - -#ifndef RTE_COMPONENTS_H -#define RTE_COMPONENTS_H - - -/* - * Define the Device Header File: - */ -#define CMSIS_device_header "ARMCM0plus.h" - - - -#endif /* RTE_COMPONENTS_H */ diff --git a/Examples/cmsis_build/projects/RTE/_Release_VHT_M7/RTE_Components.h b/Examples/cmsis_build/projects/RTE/_Release_VHT_M7/RTE_Components.h deleted file mode 100644 index b570c5b0b..000000000 --- a/Examples/cmsis_build/projects/RTE/_Release_VHT_M7/RTE_Components.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * CSOLUTION generated file: DO NOT EDIT! - * Generated by: csolution version 2.0.0 - * - * Project: 'bayes.Release+VHT_M7' - * Target: 'Release+VHT_M7' - */ - -#ifndef RTE_COMPONENTS_H -#define RTE_COMPONENTS_H - - -/* - * Define the Device Header File: - */ -#define CMSIS_device_header "ARMCM7_DP.h" - - - -#endif /* RTE_COMPONENTS_H */ diff --git a/Examples/cmsis_build/projects/bayes.Release+VHT-Corstone-310.cprj b/Examples/cmsis_build/projects/bayes.Release+VHT-Corstone-310.cprj deleted file mode 100644 index 04aa47772..000000000 --- a/Examples/cmsis_build/projects/bayes.Release+VHT-Corstone-310.cprj +++ /dev/null @@ -1,87 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - - ../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/bayes.Release+VHT_M0P.cprj b/Examples/cmsis_build/projects/bayes.Release+VHT_M0P.cprj deleted file mode 100644 index d99e2a938..000000000 --- a/Examples/cmsis_build/projects/bayes.Release+VHT_M0P.cprj +++ /dev/null @@ -1,74 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - ../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/bayes.Release+VHT_M7.cprj b/Examples/cmsis_build/projects/bayes.Release+VHT_M7.cprj deleted file mode 100644 index 17f7749a6..000000000 --- a/Examples/cmsis_build/projects/bayes.Release+VHT_M7.cprj +++ /dev/null @@ -1,74 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - ../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/classmarks.Release+VHT-Corstone-310.cprj b/Examples/cmsis_build/projects/classmarks.Release+VHT-Corstone-310.cprj deleted file mode 100644 index acf39e952..000000000 --- a/Examples/cmsis_build/projects/classmarks.Release+VHT-Corstone-310.cprj +++ /dev/null @@ -1,87 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - - ../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/classmarks.Release+VHT_M0P.cprj b/Examples/cmsis_build/projects/classmarks.Release+VHT_M0P.cprj deleted file mode 100644 index 523b566ae..000000000 --- a/Examples/cmsis_build/projects/classmarks.Release+VHT_M0P.cprj +++ /dev/null @@ -1,74 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - ../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/classmarks.Release+VHT_M7.cprj b/Examples/cmsis_build/projects/classmarks.Release+VHT_M7.cprj deleted file mode 100644 index e52a109f0..000000000 --- a/Examples/cmsis_build/projects/classmarks.Release+VHT_M7.cprj +++ /dev/null @@ -1,74 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - ../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/convolution.Release+VHT-Corstone-310.cprj b/Examples/cmsis_build/projects/convolution.Release+VHT-Corstone-310.cprj deleted file mode 100644 index 0e634e55d..000000000 --- a/Examples/cmsis_build/projects/convolution.Release+VHT-Corstone-310.cprj +++ /dev/null @@ -1,88 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - - ../../ARM/arm_convolution_example;../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/convolution.Release+VHT_M0P.cprj b/Examples/cmsis_build/projects/convolution.Release+VHT_M0P.cprj deleted file mode 100644 index 29ac65d03..000000000 --- a/Examples/cmsis_build/projects/convolution.Release+VHT_M0P.cprj +++ /dev/null @@ -1,75 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - ../../ARM/arm_convolution_example;../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/convolution.Release+VHT_M7.cprj b/Examples/cmsis_build/projects/convolution.Release+VHT_M7.cprj deleted file mode 100644 index 09ce31de3..000000000 --- a/Examples/cmsis_build/projects/convolution.Release+VHT_M7.cprj +++ /dev/null @@ -1,75 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - ../../ARM/arm_convolution_example;../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/dotproduct.Release+VHT-Corstone-310.cprj b/Examples/cmsis_build/projects/dotproduct.Release+VHT-Corstone-310.cprj deleted file mode 100644 index d7e515038..000000000 --- a/Examples/cmsis_build/projects/dotproduct.Release+VHT-Corstone-310.cprj +++ /dev/null @@ -1,87 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - - ../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/dotproduct.Release+VHT_M0P.cprj b/Examples/cmsis_build/projects/dotproduct.Release+VHT_M0P.cprj deleted file mode 100644 index 0f888fae1..000000000 --- a/Examples/cmsis_build/projects/dotproduct.Release+VHT_M0P.cprj +++ /dev/null @@ -1,74 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - ../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/dotproduct.Release+VHT_M7.cprj b/Examples/cmsis_build/projects/dotproduct.Release+VHT_M7.cprj deleted file mode 100644 index 50efe2bbe..000000000 --- a/Examples/cmsis_build/projects/dotproduct.Release+VHT_M7.cprj +++ /dev/null @@ -1,74 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - ../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/fftbin.Release+VHT-Corstone-310.cprj b/Examples/cmsis_build/projects/fftbin.Release+VHT-Corstone-310.cprj deleted file mode 100644 index 61384df53..000000000 --- a/Examples/cmsis_build/projects/fftbin.Release+VHT-Corstone-310.cprj +++ /dev/null @@ -1,88 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - - ../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/fftbin.Release+VHT_M0P.cprj b/Examples/cmsis_build/projects/fftbin.Release+VHT_M0P.cprj deleted file mode 100644 index 8856caa33..000000000 --- a/Examples/cmsis_build/projects/fftbin.Release+VHT_M0P.cprj +++ /dev/null @@ -1,75 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - ../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/fftbin.Release+VHT_M7.cprj b/Examples/cmsis_build/projects/fftbin.Release+VHT_M7.cprj deleted file mode 100644 index f19a9da78..000000000 --- a/Examples/cmsis_build/projects/fftbin.Release+VHT_M7.cprj +++ /dev/null @@ -1,75 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - ../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/fir.Release+VHT-Corstone-310.cprj b/Examples/cmsis_build/projects/fir.Release+VHT-Corstone-310.cprj deleted file mode 100644 index a33a3197c..000000000 --- a/Examples/cmsis_build/projects/fir.Release+VHT-Corstone-310.cprj +++ /dev/null @@ -1,89 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - - ../../ARM/arm_fir_example;../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/fir.Release+VHT_M0P.cprj b/Examples/cmsis_build/projects/fir.Release+VHT_M0P.cprj deleted file mode 100644 index 19981d630..000000000 --- a/Examples/cmsis_build/projects/fir.Release+VHT_M0P.cprj +++ /dev/null @@ -1,76 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - ../../ARM/arm_fir_example;../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/fir.Release+VHT_M7.cprj b/Examples/cmsis_build/projects/fir.Release+VHT_M7.cprj deleted file mode 100644 index 62c6d0a94..000000000 --- a/Examples/cmsis_build/projects/fir.Release+VHT_M7.cprj +++ /dev/null @@ -1,76 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - ../../ARM/arm_fir_example;../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/graphicequalizer.Release+VHT-Corstone-310.cprj b/Examples/cmsis_build/projects/graphicequalizer.Release+VHT-Corstone-310.cprj deleted file mode 100644 index e8d9c2206..000000000 --- a/Examples/cmsis_build/projects/graphicequalizer.Release+VHT-Corstone-310.cprj +++ /dev/null @@ -1,89 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - - ../../ARM/arm_graphic_equalizer_example;../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/graphicequalizer.Release+VHT_M0P.cprj b/Examples/cmsis_build/projects/graphicequalizer.Release+VHT_M0P.cprj deleted file mode 100644 index 428a6a19c..000000000 --- a/Examples/cmsis_build/projects/graphicequalizer.Release+VHT_M0P.cprj +++ /dev/null @@ -1,76 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - ../../ARM/arm_graphic_equalizer_example;../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/graphicequalizer.Release+VHT_M7.cprj b/Examples/cmsis_build/projects/graphicequalizer.Release+VHT_M7.cprj deleted file mode 100644 index 304c93c00..000000000 --- a/Examples/cmsis_build/projects/graphicequalizer.Release+VHT_M7.cprj +++ /dev/null @@ -1,76 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - ../../ARM/arm_graphic_equalizer_example;../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/linearinterp.Release+VHT-Corstone-310.cprj b/Examples/cmsis_build/projects/linearinterp.Release+VHT-Corstone-310.cprj deleted file mode 100644 index 30679a533..000000000 --- a/Examples/cmsis_build/projects/linearinterp.Release+VHT-Corstone-310.cprj +++ /dev/null @@ -1,89 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - - ../../ARM/arm_linear_interp_example;../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/linearinterp.Release+VHT_M0P.cprj b/Examples/cmsis_build/projects/linearinterp.Release+VHT_M0P.cprj deleted file mode 100644 index da9345384..000000000 --- a/Examples/cmsis_build/projects/linearinterp.Release+VHT_M0P.cprj +++ /dev/null @@ -1,76 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - ../../ARM/arm_linear_interp_example;../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/linearinterp.Release+VHT_M7.cprj b/Examples/cmsis_build/projects/linearinterp.Release+VHT_M7.cprj deleted file mode 100644 index 3f5e41597..000000000 --- a/Examples/cmsis_build/projects/linearinterp.Release+VHT_M7.cprj +++ /dev/null @@ -1,76 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - ../../ARM/arm_linear_interp_example;../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/matrix.Release+VHT-Corstone-310.cprj b/Examples/cmsis_build/projects/matrix.Release+VHT-Corstone-310.cprj deleted file mode 100644 index ac09668af..000000000 --- a/Examples/cmsis_build/projects/matrix.Release+VHT-Corstone-310.cprj +++ /dev/null @@ -1,88 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - - ../../ARM/arm_matrix_example;../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/matrix.Release+VHT_M0P.cprj b/Examples/cmsis_build/projects/matrix.Release+VHT_M0P.cprj deleted file mode 100644 index 36b7373a5..000000000 --- a/Examples/cmsis_build/projects/matrix.Release+VHT_M0P.cprj +++ /dev/null @@ -1,75 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - ../../ARM/arm_matrix_example;../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/matrix.Release+VHT_M7.cprj b/Examples/cmsis_build/projects/matrix.Release+VHT_M7.cprj deleted file mode 100644 index a8aea48a4..000000000 --- a/Examples/cmsis_build/projects/matrix.Release+VHT_M7.cprj +++ /dev/null @@ -1,75 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - ../../ARM/arm_matrix_example;../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/signalconverge.Release+VHT-Corstone-310.cprj b/Examples/cmsis_build/projects/signalconverge.Release+VHT-Corstone-310.cprj deleted file mode 100644 index 4f718028d..000000000 --- a/Examples/cmsis_build/projects/signalconverge.Release+VHT-Corstone-310.cprj +++ /dev/null @@ -1,89 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - - ../../ARM/arm_signal_converge_example;../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/signalconverge.Release+VHT_M0P.cprj b/Examples/cmsis_build/projects/signalconverge.Release+VHT_M0P.cprj deleted file mode 100644 index f993e4f3a..000000000 --- a/Examples/cmsis_build/projects/signalconverge.Release+VHT_M0P.cprj +++ /dev/null @@ -1,76 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - ../../ARM/arm_signal_converge_example;../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/signalconverge.Release+VHT_M7.cprj b/Examples/cmsis_build/projects/signalconverge.Release+VHT_M7.cprj deleted file mode 100644 index 198b7e229..000000000 --- a/Examples/cmsis_build/projects/signalconverge.Release+VHT_M7.cprj +++ /dev/null @@ -1,76 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - ../../ARM/arm_signal_converge_example;../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/sincos.Release+VHT-Corstone-310.cprj b/Examples/cmsis_build/projects/sincos.Release+VHT-Corstone-310.cprj deleted file mode 100644 index 7bcabfda7..000000000 --- a/Examples/cmsis_build/projects/sincos.Release+VHT-Corstone-310.cprj +++ /dev/null @@ -1,87 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - - ../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/sincos.Release+VHT_M0P.cprj b/Examples/cmsis_build/projects/sincos.Release+VHT_M0P.cprj deleted file mode 100644 index 5ccd0f353..000000000 --- a/Examples/cmsis_build/projects/sincos.Release+VHT_M0P.cprj +++ /dev/null @@ -1,74 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - ../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/sincos.Release+VHT_M7.cprj b/Examples/cmsis_build/projects/sincos.Release+VHT_M7.cprj deleted file mode 100644 index ab04ccc3a..000000000 --- a/Examples/cmsis_build/projects/sincos.Release+VHT_M7.cprj +++ /dev/null @@ -1,74 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - ../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/svm.Release+VHT-Corstone-310.cprj b/Examples/cmsis_build/projects/svm.Release+VHT-Corstone-310.cprj deleted file mode 100644 index e74e590e1..000000000 --- a/Examples/cmsis_build/projects/svm.Release+VHT-Corstone-310.cprj +++ /dev/null @@ -1,87 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - - ../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/svm.Release+VHT_M0P.cprj b/Examples/cmsis_build/projects/svm.Release+VHT_M0P.cprj deleted file mode 100644 index 1f8b972db..000000000 --- a/Examples/cmsis_build/projects/svm.Release+VHT_M0P.cprj +++ /dev/null @@ -1,74 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - ../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/svm.Release+VHT_M7.cprj b/Examples/cmsis_build/projects/svm.Release+VHT_M7.cprj deleted file mode 100644 index 9e7377f5f..000000000 --- a/Examples/cmsis_build/projects/svm.Release+VHT_M7.cprj +++ /dev/null @@ -1,74 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - ../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/variance.Release+VHT-Corstone-310.cprj b/Examples/cmsis_build/projects/variance.Release+VHT-Corstone-310.cprj deleted file mode 100644 index c55975a6d..000000000 --- a/Examples/cmsis_build/projects/variance.Release+VHT-Corstone-310.cprj +++ /dev/null @@ -1,87 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - - ../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/variance.Release+VHT_M0P.cprj b/Examples/cmsis_build/projects/variance.Release+VHT_M0P.cprj deleted file mode 100644 index ff2fb72af..000000000 --- a/Examples/cmsis_build/projects/variance.Release+VHT_M0P.cprj +++ /dev/null @@ -1,74 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - ../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/projects/variance.Release+VHT_M7.cprj b/Examples/cmsis_build/projects/variance.Release+VHT_M7.cprj deleted file mode 100644 index ca1096087..000000000 --- a/Examples/cmsis_build/projects/variance.Release+VHT_M7.cprj +++ /dev/null @@ -1,74 +0,0 @@ - - - - - - Automatically generated project - - - - - - - - - - - - - - - - - - ../../../Include;../../../PrivateInclude - - - - - - - - - - - - - - - - - ARM_MATH_ROUNDING - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Examples/cmsis_build/runall.bat b/Examples/cmsis_build/runall.bat index 6208f3e56..c96bec782 100644 --- a/Examples/cmsis_build/runall.bat +++ b/Examples/cmsis_build/runall.bat @@ -1,91 +1,103 @@ +REM Depending on the version of MDK you have installed, the path to +REM FVP executables may need to be updated. +REM +REM * MDK versions before 5.37: `Keil_v5/ARM/FVP` +REM * MDK versions 5.38, 5.39: `Keil_v5/ARM/VHT` +REM * MDK version 5.40 or later: `Keil_v5/ARM/avh-fvp/bin/models` +REM +REM With MDK >= 5.40, the name of FVP is starting with FVP_ +REM instead of VHT_ +REM +REM Below the paths for MDK >= 5.40 + ECHO "Bayes" -C:\Keil_v5\ARM\VHT\VHT_Corstone_SSE-300_Ethos-U55.exe ^ +C:\Keil_v5\ARM\avh-fvp\bin\models\FVP_Corstone_SSE-300_Ethos-U55.exe ^ -f ..\ARM\arm_bayes_example\ARMCM55_FP_MVE_config.txt ^ -C cpu0.semihosting-enable=1 ^ -C mps3_board.visualisation.disable-visualisation=1 ^ - -a cpu0="out\bayes\VHT-Corstone-300\Release\bayes.axf" + -a cpu0="cprj\out\bayes\VHT-Corstone-300\Release\bayes.axf" ECHO "Class marks" -C:\Keil_v5\ARM\VHT\VHT_Corstone_SSE-300_Ethos-U55.exe ^ +C:\Keil_v5\ARM\avh-fvp\bin\models\FVP_Corstone_SSE-300_Ethos-U55.exe ^ -f ..\ARM\arm_class_marks_example\ARMCM55_FP_MVE_config.txt ^ -C cpu0.semihosting-enable=1 ^ -C mps3_board.visualisation.disable-visualisation=1 ^ - -a cpu0="out\classmarks\VHT-Corstone-300\Release\classmarks.axf" + -a cpu0="cprj\out\classmarks\VHT-Corstone-300\Release\classmarks.axf" ECHO "Convolution" -C:\Keil_v5\ARM\VHT\VHT_Corstone_SSE-300_Ethos-U55.exe ^ +C:\Keil_v5\ARM\avh-fvp\bin\models\FVP_Corstone_SSE-300_Ethos-U55.exe ^ -f ..\ARM\arm_convolution_example\ARMCM55_FP_MVE_config.txt ^ -C cpu0.semihosting-enable=1 ^ -C mps3_board.visualisation.disable-visualisation=1 ^ - -a cpu0="out\convolution\VHT-Corstone-300\Release\convolution.axf" + -a cpu0="cprj\out\convolution\VHT-Corstone-300\Release\convolution.axf" ECHO "Dot product" -C:\Keil_v5\ARM\VHT\VHT_Corstone_SSE-300_Ethos-U55.exe ^ +C:\Keil_v5\ARM\avh-fvp\bin\models\FVP_Corstone_SSE-300_Ethos-U55.exe ^ -f ..\ARM\arm_dotproduct_example\ARMCM55_FP_MVE_config.txt ^ -C cpu0.semihosting-enable=1 ^ -C mps3_board.visualisation.disable-visualisation=1 ^ - -a cpu0="out\dotproduct\VHT-Corstone-300\Release\dotproduct.axf" + -a cpu0="cprj\out\dotproduct\VHT-Corstone-300\Release\dotproduct.axf" ECHO "FFT Bin" -C:\Keil_v5\ARM\VHT\VHT_Corstone_SSE-300_Ethos-U55.exe ^ +C:\Keil_v5\ARM\avh-fvp\bin\models\FVP_Corstone_SSE-300_Ethos-U55.exe ^ -f ..\ARM\arm_fft_bin_example\ARMCM55_FP_MVE_config.txt ^ -C cpu0.semihosting-enable=1 ^ -C mps3_board.visualisation.disable-visualisation=1 ^ - -a cpu0="out\fftbin\VHT-Corstone-300\Release\fftbin.axf" + -a cpu0="cprj\out\fftbin\VHT-Corstone-300\Release\fftbin.axf" ECHO "Fir example" -C:\Keil_v5\ARM\VHT\VHT_Corstone_SSE-300_Ethos-U55.exe ^ +C:\Keil_v5\ARM\avh-fvp\bin\models\FVP_Corstone_SSE-300_Ethos-U55.exe ^ -f ..\ARM\arm_fir_example\ARMCM55_FP_MVE_config.txt ^ -C cpu0.semihosting-enable=1 ^ -C mps3_board.visualisation.disable-visualisation=1 ^ - -a cpu0="out\fir\VHT-Corstone-300\Release\fir.axf" + -a cpu0="cprj\out\fir\VHT-Corstone-300\Release\fir.axf" ECHO "Graphic Equalizer" -C:\Keil_v5\ARM\VHT\VHT_Corstone_SSE-300_Ethos-U55.exe ^ +C:\Keil_v5\ARM\avh-fvp\bin\models\FVP_Corstone_SSE-300_Ethos-U55.exe ^ -f ..\ARM\arm_graphic_equalizer_example\ARMCM55_FP_MVE_config.txt ^ -C cpu0.semihosting-enable=1 ^ -C mps3_board.visualisation.disable-visualisation=1 ^ - -a cpu0="out\graphicequalizer\VHT-Corstone-300\Release\graphicequalizer.axf" + -a cpu0="cprj\out\graphicequalizer\VHT-Corstone-300\Release\graphicequalizer.axf" ECHO "Linear interpolation" -C:\Keil_v5\ARM\VHT\VHT_Corstone_SSE-300_Ethos-U55.exe ^ +C:\Keil_v5\ARM\avh-fvp\bin\models\FVP_Corstone_SSE-300_Ethos-U55.exe ^ -f ..\ARM\arm_linear_interp_example\ARMCM55_FP_MVE_config.txt ^ -C cpu0.semihosting-enable=1 ^ -C mps3_board.visualisation.disable-visualisation=1 ^ - -a cpu0="out\linearinterp\VHT-Corstone-300\Release\linearinterp.axf" + -a cpu0="cprj\out\linearinterp\VHT-Corstone-300\Release\linearinterp.axf" ECHO "Matrix" -C:\Keil_v5\ARM\VHT\VHT_Corstone_SSE-300_Ethos-U55.exe ^ +C:\Keil_v5\ARM\avh-fvp\bin\models\FVP_Corstone_SSE-300_Ethos-U55.exe ^ -f ..\ARM\arm_matrix_example\ARMCM55_FP_MVE_config.txt ^ -C cpu0.semihosting-enable=1 ^ -C mps3_board.visualisation.disable-visualisation=1 ^ - -a cpu0="out\matrix\VHT-Corstone-300\Release\matrix.axf" + -a cpu0="cprj\out\matrix\VHT-Corstone-300\Release\matrix.axf" ECHO "Signal Converge" -C:\Keil_v5\ARM\VHT\VHT_Corstone_SSE-300_Ethos-U55.exe ^ +C:\Keil_v5\ARM\avh-fvp\bin\models\FVP_Corstone_SSE-300_Ethos-U55.exe ^ -f ..\ARM\arm_signal_converge_example\ARMCM55_FP_MVE_config.txt ^ -C cpu0.semihosting-enable=1 ^ -C mps3_board.visualisation.disable-visualisation=1 ^ - -a cpu0="out\signalconverge\VHT-Corstone-300\Release\signalconverge.axf" + -a cpu0="cprj\out\signalconverge\VHT-Corstone-300\Release\signalconverge.axf" ECHO "Sin Cos" -C:\Keil_v5\ARM\VHT\VHT_Corstone_SSE-300_Ethos-U55.exe ^ +C:\Keil_v5\ARM\avh-fvp\bin\models\FVP_Corstone_SSE-300_Ethos-U55.exe ^ -f ..\ARM\arm_sin_cos_example\ARMCM55_FP_MVE_config.txt ^ -C cpu0.semihosting-enable=1 ^ -C mps3_board.visualisation.disable-visualisation=1 ^ - -a cpu0="out\sincos\VHT-Corstone-300\Release\sincos.axf" + -a cpu0="cprj\out\sincos\VHT-Corstone-300\Release\sincos.axf" ECHO "SVM" -C:\Keil_v5\ARM\VHT\VHT_Corstone_SSE-300_Ethos-U55.exe ^ +C:\Keil_v5\ARM\avh-fvp\bin\models\FVP_Corstone_SSE-300_Ethos-U55.exe ^ -f ..\ARM\arm_svm_example\ARMCM55_FP_MVE_config.txt ^ -C cpu0.semihosting-enable=1 ^ -C mps3_board.visualisation.disable-visualisation=1 ^ - -a cpu0="out\svm\VHT-Corstone-300\Release\svm.axf" + -a cpu0="cprj\out\svm\VHT-Corstone-300\Release\svm.axf" ECHO "Variance" -C:\Keil_v5\ARM\VHT\VHT_Corstone_SSE-300_Ethos-U55.exe ^ +C:\Keil_v5\ARM\avh-fvp\bin\models\FVP_Corstone_SSE-300_Ethos-U55.exe ^ -f ..\ARM\arm_variance_example\ARMCM55_FP_MVE_config.txt ^ -C cpu0.semihosting-enable=1 ^ -C mps3_board.visualisation.disable-visualisation=1 ^ - -a cpu0="out\variance\VHT-Corstone-300\Release\variance.axf" + -a cpu0="cprj\out\variance\VHT-Corstone-300\Release\variance.axf" diff --git a/Examples/cmsis_build/vht.clayer.yml b/Examples/cmsis_build/vht.clayer.yml index 83a0160a2..af2802191 100644 --- a/Examples/cmsis_build/vht.clayer.yml +++ b/Examples/cmsis_build/vht.clayer.yml @@ -4,28 +4,20 @@ layer: components: - component: ARM::CMSIS:CORE - #- component: ARM::CMSIS:DSP&Source@1.14.4 - - component: Device:Startup&C Startup - not-for-context: - - +VHT-Corstone-300 - - +VHT-Corstone-310 - - component: ARM::Device:Definition + - component: ARM::Device:Startup&C Startup for-context: - - +VHT-Corstone-300 - - +VHT-Corstone-310 - - component: ARM::Device:Startup&Baremetal + - +VHT-Corstone-300 + - +VHT_M7 + - +VHT_M0P + - component: ARM::Device:Definition for-context: - - +VHT-Corstone-300 - - +VHT-Corstone-310 - - component: ARM::Native Driver:Timeout + - +VHT-Corstone-300 + - component: ARM::Device:Native Driver:SysCounter for-context: - - +VHT-Corstone-300 - - +VHT-Corstone-310 - - component: ARM::Native Driver:SysCounter + - +VHT-Corstone-300 + - component: ARM::Device:Native Driver:SysTimer for-context: - - +VHT-Corstone-300 - - +VHT-Corstone-310 - - component: ARM::Native Driver:SysTimer + - +VHT-Corstone-300 + - component: ARM::Device:Native Driver:Timeout for-context: - - +VHT-Corstone-300 - - +VHT-Corstone-310 + - +VHT-Corstone-300