From 84641af17aa53bf1f4ec63b553eb648ba902aa87 Mon Sep 17 00:00:00 2001 From: Momchil Velikov Date: Wed, 17 Jul 2024 10:08:41 +0100 Subject: [PATCH 01/11] [aapcs64] Describe the FPMR register Change-Id: Ie032d9b6ce01a27170f5ce9acbcea3910709cb1f --- aapcs64/aapcs64.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/aapcs64/aapcs64.rst b/aapcs64/aapcs64.rst index ca3a879..7d78ff4 100644 --- a/aapcs64/aapcs64.rst +++ b/aapcs64/aapcs64.rst @@ -892,6 +892,8 @@ thread-local storage on platforms where multi-threaded code is supported. The exact location of such information is platform specific. +The FPMR is system register that controls behaviors of the FP8 instructions. It is a temporary register. The state of the register must be held in thread-local storage on platforms where multi-threaded code is supported. + Scalable vector registers ^^^^^^^^^^^^^^^^^^^^^^^^^ From 4a6224d5e1c60fcf45961f5109378564ab321c33 Mon Sep 17 00:00:00 2001 From: Momchil Velikov Date: Mon, 22 Jul 2024 11:59:17 +0100 Subject: [PATCH 02/11] [fixup] Added/changed some words Change-Id: Ib924865cd666235863e1a1b53222a7dcebad0f1e --- aapcs64/aapcs64.rst | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/aapcs64/aapcs64.rst b/aapcs64/aapcs64.rst index 7d78ff4..0fa5ea5 100644 --- a/aapcs64/aapcs64.rst +++ b/aapcs64/aapcs64.rst @@ -892,7 +892,10 @@ thread-local storage on platforms where multi-threaded code is supported. The exact location of such information is platform specific. -The FPMR is system register that controls behaviors of the FP8 instructions. It is a temporary register. The state of the register must be held in thread-local storage on platforms where multi-threaded code is supported. +The FPMR is system register that controls behaviors of the FP8 instructions. It +is a temporary register. The state of the register must be held in thread-local +storage on platforms where multi-threaded code is supported. The exact location +of that storage is platform specific. Scalable vector registers ^^^^^^^^^^^^^^^^^^^^^^^^^ From 95be580ae67f82e4872081570ae7ff5480792de6 Mon Sep 17 00:00:00 2001 From: Momchil Velikov Date: Wed, 24 Jul 2024 08:39:42 +0100 Subject: [PATCH 03/11] [fixup] Remove part about keeping FPMR in thread-local storage Change-Id: Ie51735d57f32f21c95f62ae0647344ccbe627ca8 --- aapcs64/aapcs64.rst | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/aapcs64/aapcs64.rst b/aapcs64/aapcs64.rst index 0fa5ea5..378a6a7 100644 --- a/aapcs64/aapcs64.rst +++ b/aapcs64/aapcs64.rst @@ -892,10 +892,8 @@ thread-local storage on platforms where multi-threaded code is supported. The exact location of such information is platform specific. -The FPMR is system register that controls behaviors of the FP8 instructions. It -is a temporary register. The state of the register must be held in thread-local -storage on platforms where multi-threaded code is supported. The exact location -of that storage is platform specific. +The FPMR is a system register that controls behaviors of the FP8 instructions. +It is a temporary register. Scalable vector registers ^^^^^^^^^^^^^^^^^^^^^^^^^ From 510f01082ab8e8d6514533568b01296e6e07e8da Mon Sep 17 00:00:00 2001 From: Momchil Velikov Date: Wed, 24 Jul 2024 08:41:10 +0100 Subject: [PATCH 04/11] [fixup] Remove stray whitespace Change-Id: I3818ad4bc33c5bce98314f1a67b06dc0ba520bdb --- aapcs64/aapcs64.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/aapcs64/aapcs64.rst b/aapcs64/aapcs64.rst index 378a6a7..81f4825 100644 --- a/aapcs64/aapcs64.rst +++ b/aapcs64/aapcs64.rst @@ -893,7 +893,7 @@ supported. The exact location of such information is platform specific. The FPMR is a system register that controls behaviors of the FP8 instructions. -It is a temporary register. +It is a temporary register. Scalable vector registers ^^^^^^^^^^^^^^^^^^^^^^^^^ From 848cc240c0b982bd8fc2850071a9f7ce75aa9753 Mon Sep 17 00:00:00 2001 From: Momchil Velikov Date: Fri, 13 Sep 2024 10:47:25 +0100 Subject: [PATCH 05/11] [fixup] Describe FP8 types and add alpha markers Change-Id: Idd90f08498c2e8b207218bf97e66747e6b61037a --- aapcs64/aapcs64.rst | 179 +++++++++++++++++++++++--------------------- 1 file changed, 95 insertions(+), 84 deletions(-) diff --git a/aapcs64/aapcs64.rst b/aapcs64/aapcs64.rst index 81f4825..a205c28 100644 --- a/aapcs64/aapcs64.rst +++ b/aapcs64/aapcs64.rst @@ -892,6 +892,8 @@ thread-local storage on platforms where multi-threaded code is supported. The exact location of such information is platform specific. +**(Alpha)** + The FPMR is a system register that controls behaviors of the FP8 instructions. It is a temporary register. @@ -2573,6 +2575,9 @@ The mapping of C arithmetic types to Fundamental Data Types is shown in `Table 3 | | | significant bits of the type in a big-endian view. Non-significant | | | | bits within the last quad-word are unspecified. | +--------------------------------+-----------------------------------------+------------------------------------------------------------------------+ + | **(Alpha)** ``__mfp8`` | unsigned byte | Arm extension. Values are intrepreted as either E5M2 or E4M3, | + | | | depending on processor mode. | + +--------------------------------+-----------------------------------------+------------------------------------------------------------------------+ A platform ABI may specify a different combination of primitive variants but we discourage this. @@ -2968,61 +2973,65 @@ The header file ``arm_neon.h`` also defines a number of intrinsic functions that .. table:: Table 7: Short vector extended types - +-----------------+-------------------+---------------------------+----------+ - | Internal type | arm\_neon.h type | Base Type | Elements | - +=================+===================+===========================+==========+ - | __Int8x8\_t | int8x8\_t | signed byte | 8 | - +-----------------+-------------------+---------------------------+----------+ - | __Int16x4\_t | int16x4\_t | signed half-word | 4 | - +-----------------+-------------------+---------------------------+----------+ - | __Int32x2\_t | int32x2\_t | signed word | 2 | - +-----------------+-------------------+---------------------------+----------+ - | __Uint8x8\_t | uint8x8\_t | unsigned byte | 8 | - +-----------------+-------------------+---------------------------+----------+ - | __Uint16x4\_t | uint16x4\_t | unsigned half-word | 4 | - +-----------------+-------------------+---------------------------+----------+ - | __Uint32x2\_t | uint32x2\_t | unsigned word | 2 | - +-----------------+-------------------+---------------------------+----------+ - | __Float16x4\_t | float16x4\_t | half-precision float | 4 | - +-----------------+-------------------+---------------------------+----------+ - | __Float32x2\_t | float32x2\_t | single-precision float | 2 | - +-----------------+-------------------+---------------------------+----------+ - | __Poly8x8\_t | poly8x8\_t | unsigned byte | 8 | - +-----------------+-------------------+---------------------------+----------+ - | __Poly16x4\_t | poly16x4\_t | unsigned half-word | 4 | - +-----------------+-------------------+---------------------------+----------+ - | __Int8x16\_t | int8x16\_t | signed byte | 16 | - +-----------------+-------------------+---------------------------+----------+ - | __Int16x8\_t | int16x8\_t | signed half-word | 8 | - +-----------------+-------------------+---------------------------+----------+ - | __Int32x4\_t | int32x4\_t | signed word | 4 | - +-----------------+-------------------+---------------------------+----------+ - | __Int64x2\_t | int64x2\_t | signed double-word | 2 | - +-----------------+-------------------+---------------------------+----------+ - | __Uint8x16\_t | uint8x16\_t | unsigned byte | 16 | - +-----------------+-------------------+---------------------------+----------+ - | __Uint16x8\_t | uint16x8\_t | unsigned half-word | 8 | - +-----------------+-------------------+---------------------------+----------+ - | __Uint32x4\_t | uint32x4\_t | unsigned word | 4 | - +-----------------+-------------------+---------------------------+----------+ - | __Uint64x2\_t | uint64x2\_t | unsigned double-word | 2 | - +-----------------+-------------------+---------------------------+----------+ - | __Float16x8\_t | float16x8\_t | half-precision float | 8 | - +-----------------+-------------------+---------------------------+----------+ - | __Float32x4\_t | float32x4\_t | single-precision float | 4 | - +-----------------+-------------------+---------------------------+----------+ - | __Float64x2\_t | float64x2\_t | double-precision float | 2 | - +-----------------+-------------------+---------------------------+----------+ - | __Poly8x16\_t | poly8x16\_t | unsigned byte | 16 | - +-----------------+-------------------+---------------------------+----------+ - | __Poly16x8\_t | poly16x8\_t | unsigned half-word | 8 | - +-----------------+-------------------+---------------------------+----------+ - | __Poly64x2\_t | poly64x2\_t | unsigned double-word | 2 | - +-----------------+-------------------+---------------------------+----------+ - | __Bfloat16x4\_t | bfloat16x4\_t | half-precision Brain float| 4 | - +-----------------+-------------------+---------------------------+----------+ - | __Bfloat16x8\_t | bfloat16x8\_t | half-precision Brain float| 8 | - +-----------------+-------------------+---------------------------+----------+ + +-----------------------------+-------------------+--------------------------+-----------+ + | Internal type | arm\_neon.h type | Base Type | Elements | + +=============================+===================+==========================+===========+ + | __Int8x8\_t | int8x8\_t | signed byte | 8 | + +-----------------------------+-------------------+--------------------------+-----------+ + | __Int16x4\_t | int16x4\_t | signed half-word | 4 | + +-----------------------------+-------------------+--------------------------+-----------+ + | __Int32x2\_t | int32x2\_t | signed word | 2 | + +-----------------------------+-------------------+--------------------------+-----------+ + | __Uint8x8\_t | uint8x8\_t | unsigned byte | 8 | + +-----------------------------+-------------------+--------------------------+-----------+ + | __Uint16x4\_t | uint16x4\_t | unsigned half-word | 4 | + +-----------------------------+-------------------+--------------------------+-----------+ + | __Uint32x2\_t | uint32x2\_t | unsigned word | 2 | + +-----------------------------+-------------------+--------------------------+-----------+ + | __Float16x4\_t | float16x4\_t | half-precision float | 4 | + +-----------------------------+-------------------+--------------------------+-----------+ + | __Float32x2\_t | float32x2\_t | single-precision float | 2 | + +-----------------------------+-------------------+--------------------------+-----------+ + | __Poly8x8\_t | poly8x8\_t | unsigned byte | 8 | + +-----------------------------+-------------------+--------------------------+-----------+ + | __Poly16x4\_t | poly16x4\_t | unsigned half-word | 4 | + +-----------------------------+-------------------+--------------------------+-----------+ + | __Int8x16\_t | int8x16\_t | signed byte | 16 | + +-----------------------------+-------------------+--------------------------+-----------+ + | __Int16x8\_t | int16x8\_t | signed half-word | 8 | + +-----------------------------+-------------------+--------------------------+-----------+ + | __Int32x4\_t | int32x4\_t | signed word | 4 | + +-----------------------------+-------------------+--------------------------+-----------+ + | __Int64x2\_t | int64x2\_t | signed double-word | 2 | + +-----------------------------+-------------------+--------------------------+-----------+ + | __Uint8x16\_t | uint8x16\_t | unsigned byte | 16 | + +-----------------------------+-------------------+--------------------------+-----------+ + | __Uint16x8\_t | uint16x8\_t | unsigned half-word | 8 | + +-----------------------------+-------------------+--------------------------+-----------+ + | __Uint32x4\_t | uint32x4\_t | unsigned word | 4 | + +-----------------------------+-------------------+--------------------------+-----------+ + | __Uint64x2\_t | uint64x2\_t | unsigned double-word | 2 | + +-----------------------------+-------------------+--------------------------+-----------+ + | __Float16x8\_t | float16x8\_t | half-precision float | 8 | + +-----------------------------+-------------------+--------------------------+-----------+ + | __Float32x4\_t | float32x4\_t | single-precision float | 4 | + +-----------------------------+-------------------+--------------------------+-----------+ + | __Float64x2\_t | float64x2\_t | double-precision float | 2 | + +-----------------------------+-------------------+--------------------------+-----------+ + | __Poly8x16\_t | poly8x16\_t | unsigned byte | 16 | + +-----------------------------+-------------------+--------------------------+-----------+ + | __Poly16x8\_t | poly16x8\_t | unsigned half-word | 8 | + +-----------------------------+-------------------+--------------------------+-----------+ + | __Poly64x2\_t | poly64x2\_t | unsigned double-word | 2 | + +-----------------------------+-------------------+--------------------------+-----------+ + | __Bfloat16x4\_t | bfloat16x4\_t | half-precison Brain float| 4 | + +-----------------------------+-------------------+--------------------------+-----------+ + | __Bfloat16x8\_t | bfloat16x8\_t | half-precison Brain float| 8 | + +-----------------------------+-------------------+--------------------------+-----------+ + | **(Alpha)** __Mfloat8x8\_t | mfloat8x8\_t | modal 8-bit float | 8 | + +-----------------------------+-------------------+--------------------------+-----------+ + | **(Alpha)** __Mfloat8x16\_t | mfloat8x16\_t | modal 8-bit float | 16 | + +-----------------------------+-------------------+--------------------------+-----------+ APPENDIX Support for Scalable vectors ===================================== @@ -3057,35 +3066,37 @@ document. .. table:: Table 8: Scalable Vector Types and Scalable Predicate Types - +---------------------+-----------------------+-------------------------------------------+----------------+ - | Internal type | ``arm_sve.h`` type | Base type | Elements | - +=====================+=======================+===========================================+================+ - | ``__SVInt8_t`` | ``svint8_t`` | signed byte | VG×8 | - +---------------------+-----------------------+-------------------------------------------+----------------+ - | ``__SVUint8_t`` | ``svuint8_t`` | unsigned byte | VG×8 | - +---------------------+-----------------------+-------------------------------------------+----------------+ - | ``__SVInt16_t`` | ``svint16_t`` | signed half-word | VG×4 | - +---------------------+-----------------------+-------------------------------------------+----------------+ - | ``__SVUint16_t`` | ``svuint16_t`` | unsigned half-word | VG×4 | - +---------------------+-----------------------+-------------------------------------------+----------------+ - | ``__SVFloat16_t`` | ``svfloat16_t`` | half-precision float | VG×4 | - +---------------------+-----------------------+-------------------------------------------+----------------+ - | ``__SVBfloat16_t`` | ``svbfloat16_t`` | half-precision brain float | VG×4 | - +---------------------+-----------------------+-------------------------------------------+----------------+ - | ``__SVInt32_t`` | ``svint32_t`` | signed word | VG×2 | - +---------------------+-----------------------+-------------------------------------------+----------------+ - | ``__SVUint32_t`` | ``svuint32_t`` | unsigned word | VG×2 | - +---------------------+-----------------------+-------------------------------------------+----------------+ - | ``__SVFloat32_t`` | ``svfloat32_t`` | single-precision float | VG×2 | - +---------------------+-----------------------+-------------------------------------------+----------------+ - | ``__SVInt64_t`` | ``svint64_t`` | signed double-word | VG | - +---------------------+-----------------------+-------------------------------------------+----------------+ - | ``__SVUint64_t`` | ``svuint64_t`` | unsigned double-word | VG | - +---------------------+-----------------------+-------------------------------------------+----------------+ - | ``__SVFloat64_t`` | ``svfloat64_t`` | double-precision float | VG | - +---------------------+-----------------------+-------------------------------------------+----------------+ - | ``__SVBool_t`` | ``svbool_t`` | single bit (fully packed into VG bytes) | VG×8 | - +---------------------+-----------------------+-------------------------------------------+----------------+ + +--------------------------------+-----------------------+-------------------------------------------+----------------+ + | Internal type | ``arm_sve.h`` type | Base type | Elements | + +================================+=======================+===========================================+================+ + | ``__SVInt8_t`` | ``svint8_t`` | signed byte | VG×8 | + +--------------------------------+-----------------------+-------------------------------------------+----------------+ + | ``__SVUint8_t`` | ``svuint8_t`` | unsigned byte | VG×8 | + +--------------------------------+-----------------------+-------------------------------------------+----------------+ + | ``__SVInt16_t`` | ``svint16_t`` | signed half-word | VG×4 | + +--------------------------------+-----------------------+-------------------------------------------+----------------+ + | ``__SVUint16_t`` | ``svuint16_t`` | unsigned half-word | VG×4 | + +--------------------------------+-----------------------+-------------------------------------------+----------------+ + | ``__SVFloat16_t`` | ``svfloat16_t`` | half-precision float | VG×4 | + +--------------------------------+-----------------------+-------------------------------------------+----------------+ + | ``__SVBfloat16_t`` | ``svbfloat16_t`` | half-precision brain float | VG×4 | + +--------------------------------+-----------------------+-------------------------------------------+----------------+ + | ``__SVInt32_t`` | ``svint32_t`` | signed word | VG×2 | + +--------------------------------+-----------------------+-------------------------------------------+----------------+ + | ``__SVUint32_t`` | ``svuint32_t`` | unsigned word | VG×2 | + +--------------------------------+-----------------------+-------------------------------------------+----------------+ + | ``__SVFloat32_t`` | ``svfloat32_t`` | single-precision float | VG×2 | + +--------------------------------+-----------------------+-------------------------------------------+----------------+ + | ``__SVInt64_t`` | ``svint64_t`` | signed double-word | VG | + +--------------------------------+-----------------------+-------------------------------------------+----------------+ + | ``__SVUint64_t`` | ``svuint64_t`` | unsigned double-word | VG | + +--------------------------------+-----------------------+-------------------------------------------+----------------+ + | ``__SVFloat64_t`` | ``svfloat64_t`` | double-precision float | VG | + +--------------------------------+-----------------------+-------------------------------------------+----------------+ + | ``__SVBool_t`` | ``svbool_t`` | single bit (fully packed into VG bytes) | VG×8 | + +--------------------------------+-----------------------+-------------------------------------------+----------------+ + | **(Alpha)** ``__SVMfloat8_t`` | ``svmfloat8_t`` | modal 8-bit float | VG×8 | + +--------------------------------+-----------------------+-------------------------------------------+----------------+ APPENDIX C++ mangling From bbadad93dc84f083f340c6943b15ccae9c6f8726 Mon Sep 17 00:00:00 2001 From: Momchil Velikov Date: Wed, 18 Sep 2024 16:53:09 +0100 Subject: [PATCH 06/11] [fixup] Typo Change-Id: I687854ddf3f87e0e7642b8ecf617740721f3bb6c --- aapcs64/aapcs64.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/aapcs64/aapcs64.rst b/aapcs64/aapcs64.rst index a205c28..35e0061 100644 --- a/aapcs64/aapcs64.rst +++ b/aapcs64/aapcs64.rst @@ -2575,7 +2575,7 @@ The mapping of C arithmetic types to Fundamental Data Types is shown in `Table 3 | | | significant bits of the type in a big-endian view. Non-significant | | | | bits within the last quad-word are unspecified. | +--------------------------------+-----------------------------------------+------------------------------------------------------------------------+ - | **(Alpha)** ``__mfp8`` | unsigned byte | Arm extension. Values are intrepreted as either E5M2 or E4M3, | + | **(Alpha)** ``__mfp8`` | unsigned byte | Arm extension. Values are interpreted as either E5M2 or E4M3, | | | | depending on processor mode. | +--------------------------------+-----------------------------------------+------------------------------------------------------------------------+ From e6e60f354e26f712740954a3a7ca65a80ad5969b Mon Sep 17 00:00:00 2001 From: Momchil Velikov Date: Mon, 30 Sep 2024 18:18:28 +0100 Subject: [PATCH 07/11] [fixup] Define the 8-bit float as a machine type Change-Id: I1c3f74cd8adf665b20619aa0e3a6fd4a200f9997 --- aapcs64/aapcs64.rst | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/aapcs64/aapcs64.rst b/aapcs64/aapcs64.rst index 35e0061..a64f414 100644 --- a/aapcs64/aapcs64.rst +++ b/aapcs64/aapcs64.rst @@ -538,7 +538,9 @@ Fundamental Data Types | +---------------------------------------+------------+---------------------------+ | | | Signed quad-word | 16 | 16 | | +------------------------+---------------------------------------+------------+---------------------------+-----------------------------------------------+ - | Floating Point | Half precision | 2 | 2 | See `Half-precision Floating Point`_ | + | Floating Point | 8-bit precision | 1 | 1 | See `Modal 8-bit floating point`_ | + | +---------------------------------------+------------+---------------------------+-----------------------------------------------+ + | | Half precision | 2 | 2 | See `Half-precision Floating Point`_ | | +---------------------------------------+------------+---------------------------+-----------------------------------------------+ | | Single precision | 4 | 4 | IEEE 754-2008 | | +---------------------------------------+------------+---------------------------+ | @@ -576,6 +578,18 @@ Fundamental Data Types +------------------------+---------------------------------------+------------+---------------------------+-----------------------------------------------+ +Modal 8-bit floating-point +------------------------------------ + +The architecture provides hardware support for modal 8-bit floating point types. +Two formats are currently supported: + +1. E4M3, 4-bit exponent and 3-bit significand, with no representation for + infinities and only a single bit-pattern in the significand for NaNs. + +2. E5M2, 5-bit exponent and 2-bit significand, following IEEE 754 conventions + for representation of special values. + Half-precision Floating Point ----------------------------- @@ -894,8 +908,8 @@ specific. **(Alpha)** -The FPMR is a system register that controls behaviors of the FP8 instructions. -It is a temporary register. +The FPMR is a system register that controls behaviors of the instructions +operating on modal 8-bit floating-point values. It is a temporary register. Scalable vector registers ^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2575,7 +2589,7 @@ The mapping of C arithmetic types to Fundamental Data Types is shown in `Table 3 | | | significant bits of the type in a big-endian view. Non-significant | | | | bits within the last quad-word are unspecified. | +--------------------------------+-----------------------------------------+------------------------------------------------------------------------+ - | **(Alpha)** ``__mfp8`` | unsigned byte | Arm extension. Values are interpreted as either E5M2 or E4M3, | + | **(Alpha)** ``__mfp8`` | 8-bit floating point | Arm extension. Values are interpreted as either E5M2 or E4M3, | | | | depending on processor mode. | +--------------------------------+-----------------------------------------+------------------------------------------------------------------------+ From 8bde47ac29c51f7e55692e5eeee9d2bfc0b3cc09 Mon Sep 17 00:00:00 2001 From: Momchil Velikov Date: Mon, 30 Sep 2024 18:34:31 +0100 Subject: [PATCH 08/11] [fixup] Update rule C.1 Change-Id: I4c9210828052471b73a358542752cf3f7ec3405a --- aapcs64/aapcs64.rst | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/aapcs64/aapcs64.rst b/aapcs64/aapcs64.rst index a64f414..c72382d 100644 --- a/aapcs64/aapcs64.rst +++ b/aapcs64/aapcs64.rst @@ -1903,10 +1903,10 @@ For a caller, sufficient stack space to hold stacked argument values is assumed | When an argument is assigned to a register any unused bits in the register have unspecified value. When an | | argument is assigned to a stack slot any unused padding bytes have unspecified value. | +-----------------------+----------------------------------------------------------------------------------------+ - | | If the argument is a Half-, Single-, Double- or Quad- precision Floating-point or | - | | short vector type and the NSRN is less than 8, then the argument is allocated to the | - | C.1 | least significant bits of register v[NSRN]. The NSRN is incremented by one. The | - | | argument has now been allocated. | + | | If the argument is an 8-bit, Half-, Single-, Double- or Quad- precision Floating-point | + | C.1 | or short vector type and the NSRN is less than 8, then the argument is allocated to | + | | the least significant bits of register v[NSRN]. The NSRN is incremented by one. | + | | The argument has now been allocated. | +-----------------------+----------------------------------------------------------------------------------------+ | | If the argument is an HFA or an HVA and there are sufficient unallocated SIMD and | | | Floating-point registers (NSRN + number of members ≤ 8), then the argument is | From 5e2e5a386df93c001f4f46a2ef02ccaf0b6c9b5d Mon Sep 17 00:00:00 2001 From: Momchil Velikov Date: Fri, 4 Oct 2024 10:14:36 +0100 Subject: [PATCH 09/11] [fixup] Delete a word Change-Id: Ib9481fe1a006adf7829493a0e2983b821f299b08 --- aapcs64/aapcs64.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/aapcs64/aapcs64.rst b/aapcs64/aapcs64.rst index c72382d..a57f378 100644 --- a/aapcs64/aapcs64.rst +++ b/aapcs64/aapcs64.rst @@ -582,7 +582,7 @@ Modal 8-bit floating-point ------------------------------------ The architecture provides hardware support for modal 8-bit floating point types. -Two formats are currently supported: +Two formats are supported: 1. E4M3, 4-bit exponent and 3-bit significand, with no representation for infinities and only a single bit-pattern in the significand for NaNs. From 63afe8ee3773acdda31387e00be179d4d8208617 Mon Sep 17 00:00:00 2001 From: Momchil Velikov Date: Tue, 15 Oct 2024 10:30:46 +0100 Subject: [PATCH 10/11] [fixup] Rebase and spelling chnages Change-Id: Ie212dfd9a079b9e263456855da7ff55674b90f22 --- aapcs64/aapcs64.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/aapcs64/aapcs64.rst b/aapcs64/aapcs64.rst index a57f378..ec13b95 100644 --- a/aapcs64/aapcs64.rst +++ b/aapcs64/aapcs64.rst @@ -538,7 +538,7 @@ Fundamental Data Types | +---------------------------------------+------------+---------------------------+ | | | Signed quad-word | 16 | 16 | | +------------------------+---------------------------------------+------------+---------------------------+-----------------------------------------------+ - | Floating Point | 8-bit precision | 1 | 1 | See `Modal 8-bit floating point`_ | + | Floating Point | 8-bit precision | 1 | 1 | See `Modal 8-bit floating-point`_ | | +---------------------------------------+------------+---------------------------+-----------------------------------------------+ | | Half precision | 2 | 2 | See `Half-precision Floating Point`_ | | +---------------------------------------+------------+---------------------------+-----------------------------------------------+ @@ -581,7 +581,7 @@ Fundamental Data Types Modal 8-bit floating-point ------------------------------------ -The architecture provides hardware support for modal 8-bit floating point types. +The architecture provides hardware support for modal 8-bit floating-point types. Two formats are supported: 1. E4M3, 4-bit exponent and 3-bit significand, with no representation for From 45e16baf03c014a0498f429d00b19662c4bf88b4 Mon Sep 17 00:00:00 2001 From: Momchil Velikov Date: Mon, 28 Oct 2024 13:11:05 +0000 Subject: [PATCH 11/11] [fixup] Update the change history Change-Id: Ifa3a90957106b49ae51f07e672ce7f91924e8a9c --- aapcs64/aapcs64.rst | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/aapcs64/aapcs64.rst b/aapcs64/aapcs64.rst index ec13b95..fa90f85 100644 --- a/aapcs64/aapcs64.rst +++ b/aapcs64/aapcs64.rst @@ -257,6 +257,11 @@ changes to the content of the document for that release. | | | - Add the __arm_get_current_vg SME support routine. | | | | - Clarify use of `it` when preserving z and p registers. | +------------+--------------------+------------------------------------------------------------------+ +| | | - Add descriptions of the modal 8-bit floating point types | +| | | - Add a description of the FPMR register | +| | | - Update argument passing rules to include FP8 types | +| | | | ++------------+--------------------+------------------------------------------------------------------+ References ^^^^^^^^^^