diff --git a/linux_app/sbsa-acs-app/include/sbsa_avs_common.h b/linux_app/sbsa-acs-app/include/sbsa_avs_common.h deleted file mode 100644 index 393b97db..00000000 --- a/linux_app/sbsa-acs-app/include/sbsa_avs_common.h +++ /dev/null @@ -1,104 +0,0 @@ -/** @file - * Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - - -/** This file is common to all test cases and Val layer of the Suite */ - - -#ifndef __SBSA_AVS_COMMON_H__ -#define __SBSA_AVS_COMMON_H__ - -#define TEST_NAME_HELPER(x,y) c##x##y -#define TEST_NAME(x,y) TEST_NAME_HELPER(x,y) - -#define AVS_PE_TEST_NUM_BASE 0 -#define AVS_GIC_TEST_NUM_BASE 20 -#define AVS_TIMER_TEST_NUM_BASE 30 -#define AVS_WD_TEST_NUM_BASE 40 -#define AVS_PCIE_TEST_NUM_BASE 50 -#define AVS_WAKEUP_TEST_NUM_BASE 70 -#define AVS_PER_TEST_NUM_BASE 80 -#define AVS_SMMU_TEST_NUM_BASE 90 -#define AVS_SECURE_TEST_NUM_BASE 900 - -#define STATE_BIT 28 -#define STATE_MASK 0xF - //These are the states a test can be in */ - #define TEST_START_VAL 0x1 - #define TEST_END_VAL 0x2 - #define TEST_PASS_VAL 0x4 - #define TEST_FAIL_VAL 0x8 - #define TEST_SKIP_VAL 0x9 - #define TEST_PENDING_VAL 0xA - -#define CPU_NUM_BIT 32 -#define CPU_NUM_MASK 0xFFFFFFFF - -#define LEVEL_BIT 24 -#define LEVEL_MASK 0xF - -#define TEST_NUM_BIT 16 -#define TEST_NUM_MASK 0xFF - - -/* TEST start and Stop defines */ - - - -#define SBSA_AVS_START(level, test_num) (((TEST_START_VAL) << STATE_BIT) | ((level) << LEVEL_BIT) | ((test_num) << TEST_NUM_BIT)) -#define SBSA_AVS_END(level, test_num) (((TEST_END_VAL) << STATE_BIT) | ((level) << LEVEL_BIT) | ((test_num) << TEST_NUM_BIT)) - - - -/* TEST Result defines */ - -#define RESULT_PASS(level, test_num, status) (((TEST_PASS_VAL) << STATE_BIT) | ((level) << LEVEL_BIT) | ((test_num) << TEST_NUM_BIT) | (status)) - -#define RESULT_FAIL(level, test_num, status) (((TEST_FAIL_VAL) << STATE_BIT) | ((level) << LEVEL_BIT) | ((test_num) << TEST_NUM_BIT) | (status)) - -#define RESULT_SKIP(level, test_num, status) (((TEST_SKIP_VAL) << STATE_BIT) | ((level) << LEVEL_BIT) | ((test_num) << TEST_NUM_BIT) | (status)) - -#define RESULT_PENDING(level, test_num) (((TEST_PENDING_VAL) << STATE_BIT) | \ - ((level) << LEVEL_BIT) | ((test_num) << TEST_NUM_BIT)) - -#define IS_TEST_START(value) (((value >> STATE_BIT) & (STATE_MASK)) == TEST_START_VAL) -#define IS_TEST_END(value) (((value >> STATE_BIT) & (STATE_MASK)) == TEST_END_VAL) -#define IS_RESULT_PENDING(value) (((value >> STATE_BIT) & (STATE_MASK)) == TEST_PENDING_VAL) -#define IS_TEST_PASS(value) (((value >> STATE_BIT) & (STATE_MASK)) == TEST_PASS_VAL) -#define IS_TEST_FAIL(value) (((value >> STATE_BIT) & (STATE_MASK)) == TEST_FAIL_VAL) -#define IS_TEST_SKIP(value) (((value >> STATE_BIT) & (STATE_MASK)) == TEST_SKIP_VAL) -#define IS_TEST_FAIL_SKIP(value) ((IS_TEST_FAIL(value)) || (IS_TEST_SKIP(value))) - -uint32_t -val_mmio_read(addr_t addr); - -void -val_mmio_write(addr_t addr, uint32_t data); - -uint32_t -val_initialize_test(uint32_t test_num, char8_t * desc, uint32_t num_pe, uint32_t level); - -uint32_t -val_check_for_error(uint32_t test_num, uint32_t num_pe); - -void -val_run_test_payload(uint32_t test_num, uint32_t num_pe, void (*payload)(void), uint64_t test_input); - -void -val_data_cache_ops_by_va(addr_t addr, uint32_t type); - -#endif diff --git a/linux_app/sbsa-acs-app/sbsa_drv_intf.c b/linux_app/sbsa-acs-app/sbsa_drv_intf.c index 3ebf4cc1..d158ab9a 100644 --- a/linux_app/sbsa-acs-app/sbsa_drv_intf.c +++ b/linux_app/sbsa-acs-app/sbsa_drv_intf.c @@ -44,8 +44,6 @@ call_drv_get_status(unsigned long int *arg0, unsigned long int *arg1, unsigned l fd = fopen("/proc/sbsa", "r"); - fseek(fd, 0, SEEK_SET); - if (NULL == fd) { printf("fopen failed \n"); @@ -200,8 +198,6 @@ int read_from_proc_sbsa_msg() { fd = fopen("/proc/sbsa_msg", "r"); - fseek(fd, 0, SEEK_SET); - if (NULL == fd) { printf("fopen failed \n"); return 1; diff --git a/platform/pal_uefi/include/pal_uefi.h b/platform/pal_uefi/include/pal_uefi.h index 4d548bee..23bae3d3 100644 --- a/platform/pal_uefi/include/pal_uefi.h +++ b/platform/pal_uefi/include/pal_uefi.h @@ -35,6 +35,7 @@ extern UINT32 g_enable_module; #define PCIE_CAP_NOT_FOUND 0x10000010 /* The specified capability was not found */ #define PCIE_UNKNOWN_RESPONSE 0xFFFFFFFF /* Function not found or UR response from completer */ +#define NOT_IMPLEMENTED 0x4B1D /* Feature or API by default unimplemented */ typedef struct { UINT64 Arg0; diff --git a/platform/pal_uefi/src/pal_exerciser.c b/platform/pal_uefi/src/pal_exerciser.c index 4f738d32..01376466 100644 --- a/platform/pal_uefi/src/pal_exerciser.c +++ b/platform/pal_uefi/src/pal_exerciser.c @@ -93,26 +93,6 @@ pal_exerciser_get_pcie_config_offset(UINT32 Bdf) return cfg_addr; } - -/** - @brief This API returns if the device is a exerciser - @param bdf - Bus/Device/Function - @return 1 - true 0 - false -**/ -UINT32 -pal_is_bdf_exerciser(UINT32 bdf) -{ - UINT64 Ecam; - UINT32 vendor_dev_id; - Ecam = pal_pcie_get_mcfg_ecam(); - - vendor_dev_id = pal_mmio_read(Ecam + pal_exerciser_get_pcie_config_offset(bdf)); - if (vendor_dev_id == EXERCISER_ID) - return 1; - else - return 0; -} - /** @brief This function triggers the DMA operation **/ @@ -511,3 +491,23 @@ pal_exerciser_get_data ( return 1; } } + +/** + @brief This API checks if the given Bdf is an exerciser + @param Bdf - Bdf of the device + @return status - 1 if bdf is exerciser + 0 if bdf is not exerciser +**/ +UINT32 +pal_is_bdf_exerciser(UINT32 bdf) +{ + UINT64 Ecam; + UINT32 vendor_dev_id; + Ecam = pal_pcie_get_mcfg_ecam(); + + vendor_dev_id = pal_mmio_read(Ecam + pal_exerciser_get_pcie_config_offset(bdf)); + if (vendor_dev_id == EXERCISER_ID) + return 1; + else + return 0; +} diff --git a/platform/pal_uefi/src/pal_pcie.c b/platform/pal_uefi/src/pal_pcie.c index 0985d631..932459f6 100644 --- a/platform/pal_uefi/src/pal_pcie.c +++ b/platform/pal_uefi/src/pal_pcie.c @@ -213,6 +213,8 @@ pal_pcie_io_write_cfg(UINT32 Bdf, UINT32 offset, UINT32 data) /** @brief This API checks the PCIe Hierarchy Supports P2P + This is platform dependent API.If the system supports peer 2 peer + traffic, return 0 else return 1 1. Caller - Test Suite @return 1 - P2P feature not supported 0 - P2P feature supported **/ @@ -225,7 +227,7 @@ pal_pcie_p2p_support() * transactions is platform implementation specific */ - return 0; + return NOT_IMPLEMENTED; } /** @@ -275,14 +277,16 @@ pal_get_msi_vectors ( /** @brief Get legacy IRQ routing for a PCI device - + This is Platform dependent API and needs to be filled + with legacy IRQ map for a pcie devices. @param bus PCI bus address @param dev PCI device address @param fn PCI function number @param irq_map pointer to IRQ map structure @return irq_map IRQ routing map - @return status code + @return status code If the device legacy irq map information is filled + return 0, else returns NOT_IMPLEMENTED **/ UINT32 pal_pcie_get_legacy_irq_map ( @@ -293,7 +297,7 @@ pal_pcie_get_legacy_irq_map ( PERIPHERAL_IRQ_MAP *IrqMap ) { - return 1; + return NOT_IMPLEMENTED; } /* Place holder function. Need to be @@ -311,8 +315,9 @@ pal_pcie_get_root_port_bdf ( } /** - @brief Platform dependent API checks the Address Translation - Cache Support for BDF + @brief Checks the Address Translation Cache Support for BDF + Platform dependent API. Fill this with system ATC support + information for bdf's 1. Caller - Test Suite @return 0 - ATC not supported 1 - ATC supported **/ @@ -324,7 +329,7 @@ pal_pcie_is_cache_present ( UINT32 Fn ) { - return 1; + return NOT_IMPLEMENTED; } /** diff --git a/platform/pal_uefi/src/pal_pcie_enumeration.c b/platform/pal_uefi/src/pal_pcie_enumeration.c index 5c1539b1..de3ea4a2 100644 --- a/platform/pal_uefi/src/pal_pcie_enumeration.c +++ b/platform/pal_uefi/src/pal_pcie_enumeration.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2019, 2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2019, 2021-2022 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -221,3 +221,22 @@ VOID pal_pcie_enumerate(VOID) * For uefi, enumeration is done during bootup * Hence, not implemented for uefi.*/ } + +/** + @brief This API is used as placeholder to check if the bdf + obtained is valid or not + + @param bdf + @return 0 if bdf is valid else 1 +**/ +UINT32 +pal_pcie_check_device_valid(UINT32 bdf) +{ + + /*Add BDFs to this function if PCIe tests + need to be ignored for a BDF for any reason + */ + + return 0; +} + diff --git a/test_pool/exerciser/test_e006.c b/test_pool/exerciser/test_e006.c index be4598b0..a5736ced 100644 --- a/test_pool/exerciser/test_e006.c +++ b/test_pool/exerciser/test_e006.c @@ -156,8 +156,16 @@ payload (void) val_gic_free_irq(e_intr_line, 0); } } else { - val_print (AVS_PRINT_ERR, "\n Legacy interrupt mapping Read error for bdf: 0x%x", e_bdf); - test_fail++; + if (status == NOT_IMPLEMENTED) { + val_print(AVS_PRINT_DEBUG, + "\n pal_pcie_get_legacy_irq_map unimplemented for bdf: 0x%x", e_bdf); + continue; + } + else { + val_print(AVS_PRINT_ERR, "\n Legacy interrupt mapping Read error for bdf: 0x%x", + e_bdf); + test_fail++; + } } } diff --git a/test_pool/exerciser/test_e009.c b/test_pool/exerciser/test_e009.c index 4a8c359b..c3be7156 100644 --- a/test_pool/exerciser/test_e009.c +++ b/test_pool/exerciser/test_e009.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2019-2020, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019-2021, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -40,6 +40,7 @@ payload(void) uint32_t reg_value; uint32_t instance; uint32_t fail_cnt; + uint32_t status; uint64_t header_type; fail_cnt = 0; @@ -63,9 +64,21 @@ payload(void) * of the exerciser's root port. Exerciser should see this * request as a Type 0 Request. */ - val_exerciser_ops(START_TXN_MONITOR, CFG_READ, instance); + status = val_exerciser_ops(START_TXN_MONITOR, CFG_READ, instance); + if (status == PCIE_CAP_NOT_FOUND) + { + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + val_pcie_read_cfg(e_bdf, TYPE01_VIDR, ®_value); - val_exerciser_ops(STOP_TXN_MONITOR, CFG_READ, instance); + status = val_exerciser_ops(STOP_TXN_MONITOR, CFG_READ, instance); + if (status == PCIE_CAP_NOT_FOUND) + { + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + return; + } + val_exerciser_get_param(CFG_TXN_ATTRIBUTES, (uint64_t *)&header_type, 0, instance); if (header_type != TYPE0) { diff --git a/test_pool/exerciser/test_e010.c b/test_pool/exerciser/test_e010.c index 82802d52..a208a7d2 100644 --- a/test_pool/exerciser/test_e010.c +++ b/test_pool/exerciser/test_e010.c @@ -93,9 +93,12 @@ payload(void) uint32_t erp_rs_reg_value; uint32_t instance; uint32_t fail_cnt; + uint32_t test_skip; + uint32_t status; uint64_t header_type; fail_cnt = 0; + test_skip = 1; pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); @@ -147,9 +150,20 @@ payload(void) * of the exerciser. Exerciser should see this request as a * Type 1 Request. */ - val_exerciser_ops(START_TXN_MONITOR, CFG_READ, instance); + status = val_exerciser_ops(START_TXN_MONITOR, CFG_READ, instance); + if (status == PCIE_CAP_NOT_FOUND) + { + goto restore; + } + val_pcie_read_cfg(e_bdf, TYPE01_VIDR, ®_value); - val_exerciser_ops(STOP_TXN_MONITOR, CFG_READ, instance); + status = val_exerciser_ops(STOP_TXN_MONITOR, CFG_READ, instance); + if (status == PCIE_CAP_NOT_FOUND) + { + goto restore; + } + + test_skip = 0; val_exerciser_get_param(CFG_TXN_ATTRIBUTES, (uint64_t *)&header_type, 0, instance); if (header_type != TYPE1) { @@ -157,13 +171,16 @@ payload(void) fail_cnt++; } +restore: /* Restore Exerciser rootport and it's right sibling subordinate bus registers */ val_pcie_write_cfg(erp_bdf, TYPE1_PBN, erp_reg_value); if (rs_flag) val_pcie_write_cfg(erp_rs_bdf, TYPE1_PBN, erp_rs_reg_value); } - if (fail_cnt) + if (test_skip) + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + else if (fail_cnt) val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, fail_cnt)); else val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); diff --git a/test_pool/exerciser/test_e012.c b/test_pool/exerciser/test_e012.c index 2e6f003c..37739780 100644 --- a/test_pool/exerciser/test_e012.c +++ b/test_pool/exerciser/test_e012.c @@ -221,9 +221,15 @@ payload(void) instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); /* Check If PCIe Hierarchy supports P2P. */ + if (val_pcie_p2p_support() == NOT_IMPLEMENTED) { + val_print(AVS_PRINT_DEBUG, "\n pal_pcie_p2p_support API is unimplemented ", 0); + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + if (val_pcie_p2p_support()) { - val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); return; } @@ -289,7 +295,7 @@ payload(void) } if (test_skip == 1) - val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 03)); else if (fail_cnt) val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, fail_cnt)); else diff --git a/test_pool/exerciser/test_e013.c b/test_pool/exerciser/test_e013.c index b988eb78..7428d9b8 100644 --- a/test_pool/exerciser/test_e013.c +++ b/test_pool/exerciser/test_e013.c @@ -333,9 +333,15 @@ payload(void) bdf_tbl_ptr = val_pcie_bdf_table_ptr(); /* Check If PCIe Hierarchy supports P2P. */ + if (val_pcie_p2p_support() == NOT_IMPLEMENTED) { + val_print(AVS_PRINT_DEBUG, "\n pal_pcie_p2p_support API is unimplemented ", 0); + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + if (val_pcie_p2p_support()) { - val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); return; } @@ -441,7 +447,7 @@ payload(void) } if (test_skip == 1) - val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 03)); else if (fail_cnt) val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, fail_cnt)); else diff --git a/test_pool/pcie/test_p010.c b/test_pool/pcie/test_p010.c index 7344b81a..5ebd2d0d 100644 --- a/test_pool/pcie/test_p010.c +++ b/test_pool/pcie/test_p010.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2019, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2019, 2022 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -51,10 +51,10 @@ payload(void) { /* For each SMMUv3 check for PASID support */ /* If PASID is supported, test the max number of PASIDs supported */ - num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); - for(num_smmu--; num_smmu >= 0; num_smmu--) + num_smmu = val_iovirt_get_smmu_info(SMMU_NUM_CTRL, 0); + for (num_smmu--; num_smmu >= 0; num_smmu--) { - if(val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 3) + if (val_iovirt_get_smmu_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 3) { if((max_pasids = val_smmu_max_pasids(num_smmu)) > 0) { diff --git a/test_pool/pcie/test_p012.c b/test_pool/pcie/test_p012.c index 1660065a..1717f62f 100644 --- a/test_pool/pcie/test_p012.c +++ b/test_pool/pcie/test_p012.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -98,7 +98,10 @@ payload (void) val_print (AVS_PRINT_ERR, "\n Maximum number of interrupts has been reached", 0); break; default: - val_print (AVS_PRINT_ERR, "\n Unknown error", 0); + if (status == NOT_IMPLEMENTED) + val_print (AVS_PRINT_ERR, "\n API not implemented", 0); + else + val_print (AVS_PRINT_ERR, "\n Unknown error", 0); break; } } diff --git a/test_pool/pcie/test_p050.c b/test_pool/pcie/test_p050.c index 08371bbd..1ed9a208 100644 --- a/test_pool/pcie/test_p050.c +++ b/test_pool/pcie/test_p050.c @@ -66,7 +66,14 @@ payload(void) status = val_pci_get_legacy_irq_map(bdf, intr_map); if (status) { - val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + if (status == NOT_IMPLEMENTED) { + val_print (AVS_PRINT_WARN, + "\n pal_pcie_get_legacy_irq_map unimplemented", 0); + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + } + else + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + return; } diff --git a/test_pool/pcie/test_p052.c b/test_pool/pcie/test_p052.c index cf87298d..7a73fd07 100644 --- a/test_pool/pcie/test_p052.c +++ b/test_pool/pcie/test_p052.c @@ -59,8 +59,9 @@ payload(void) if ((dp_type == iEP_EP) || (dp_type == RCiEP)) { /* Check if Address Translation Cache is Present in this device. */ - /* If ATC Not present, skip the test.*/ - if (!val_pcie_is_cache_present(bdf)) + /* If ATC Not present or capabilty not filled, skip the test.*/ + if ((val_pcie_is_cache_present(bdf) == NOT_IMPLEMENTED) || + (val_pcie_is_cache_present(bdf) == 0)) continue; test_skip = 0; diff --git a/test_pool/pcie/test_p053.c b/test_pool/pcie/test_p053.c index 0712e584..70e3400d 100644 --- a/test_pool/pcie/test_p053.c +++ b/test_pool/pcie/test_p053.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020-2021, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -45,9 +45,15 @@ payload(void) pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); /* Check If PCIe Hierarchy supports P2P */ + if (val_pcie_p2p_support() == NOT_IMPLEMENTED) { + val_print(AVS_PRINT_DEBUG, "\n pal_pcie_p2p_support API is unimplemented ", 0); + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + if (val_pcie_p2p_support()) { - val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); return; } @@ -115,7 +121,7 @@ payload(void) } if (test_skip == 1) - val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 03)); else if (test_fails) val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, test_fails)); else diff --git a/test_pool/pcie/test_p054.c b/test_pool/pcie/test_p054.c index 4f5c3840..d87938e3 100644 --- a/test_pool/pcie/test_p054.c +++ b/test_pool/pcie/test_p054.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020-2021, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -42,9 +42,15 @@ payload(void) pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); /* Check If PCIe Hierarchy supports P2P */ + if (val_pcie_p2p_support() == NOT_IMPLEMENTED) { + val_print(AVS_PRINT_DEBUG, "\n pal_pcie_p2p_support API is unimplemented ", 0); + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + if (val_pcie_p2p_support()) { - val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); return; } @@ -79,7 +85,7 @@ payload(void) } if (test_skip == 1) - val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 03)); else if (test_fails) val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, test_fails)); else diff --git a/test_pool/pcie/test_p056.c b/test_pool/pcie/test_p056.c index 286eed9a..566f18fe 100644 --- a/test_pool/pcie/test_p056.c +++ b/test_pool/pcie/test_p056.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020-2021, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,9 +46,15 @@ payload(void) pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); /* Check If PCIe Hierarchy supports P2P */ + if (val_pcie_p2p_support() == NOT_IMPLEMENTED) { + val_print(AVS_PRINT_DEBUG, "\n pal_pcie_p2p_support API is unimplemented ", 0); + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + if (val_pcie_p2p_support()) { - val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); return; } @@ -136,7 +142,7 @@ payload(void) } if (test_skip == 1) - val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 03)); else if (test_fails) val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, test_fails)); else diff --git a/uefi_app/SbsaAvsMain.c b/uefi_app/SbsaAvsMain.c index 21547ce7..172b83fa 100644 --- a/uefi_app/SbsaAvsMain.c +++ b/uefi_app/SbsaAvsMain.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2021, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2022 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -453,10 +453,10 @@ ShellAppMainsbsa ( val_pe_initialize_default_exception_handler(val_pe_default_esr); FlushImage(); - Print(L"\n *** Starting PE tests *** \n"); + Print(L"\n *** Starting PE tests *** \n"); Status = val_pe_execute_tests(g_sbsa_level, val_pe_get_num()); - Print(L"\n *** Starting GIC tests *** \n"); + Print(L"\n *** Starting GIC tests *** \n"); Status |= val_gic_execute_tests(g_sbsa_level, val_pe_get_num()); Print(L"\n *** Starting Timer tests *** \n"); @@ -465,9 +465,6 @@ ShellAppMainsbsa ( Print(L"\n *** Starting Watchdog tests *** \n"); Status |= val_wd_execute_tests(g_sbsa_level, val_pe_get_num()); - Print(L"\n *** Starting PCIe tests *** \n"); - Status |= val_pcie_execute_tests(g_enable_pcie_tests, g_sbsa_level, val_pe_get_num()); - Print(L"\n *** Starting Power and Wakeup semantic tests *** \n"); Status |= val_wakeup_execute_tests(g_sbsa_level, val_pe_get_num()); @@ -477,13 +474,16 @@ ShellAppMainsbsa ( Print(L"\n *** Starting IO Virtualization tests *** \n"); Status |= val_smmu_execute_tests(g_sbsa_level, val_pe_get_num()); + Print(L"\n *** Starting PCIe tests *** \n"); + Status |= val_pcie_execute_tests(g_enable_pcie_tests, g_sbsa_level, val_pe_get_num()); + /* * Configure Gic Redistributor and ITS to support * Generation of LPIs. */ configureGicIts(); - if (g_sbsa_level > 3) { + if (g_sbsa_level > 3) { Print(L"\n *** Starting PCIe Exerciser tests *** \n"); Status |= val_exerciser_execute_tests(g_sbsa_level); } diff --git a/val/include/pal_interface.h b/val/include/pal_interface.h index 09b26f69..263b42f7 100644 --- a/val/include/pal_interface.h +++ b/val/include/pal_interface.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2021, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2022, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -298,6 +298,8 @@ uint32_t pal_pcie_is_cache_present(uint32_t seg, uint32_t bus, uint32_t dev, uin uint32_t pal_pcie_is_onchip_peripheral(uint32_t bdf); void pal_pcie_io_write_cfg(uint32_t bdf, uint32_t offset, uint32_t data); uint32_t pal_pcie_check_device_list(void); +uint32_t pal_pcie_check_device_valid(uint32_t bdf); + /** @brief Instance of SMMU INFO block **/ @@ -750,14 +752,14 @@ typedef enum { EXERCISER_DATA_BAR0_SPACE = 0x2, } EXERCISER_DATA_TYPE; - +uint32_t pal_is_bdf_exerciser(uint32_t bdf); uint32_t pal_exerciser_set_param(EXERCISER_PARAM_TYPE type, uint64_t value1, uint64_t value2, uint32_t bdf); uint32_t pal_exerciser_get_param(EXERCISER_PARAM_TYPE type, uint64_t *value1, uint64_t *value2, uint32_t bdf); uint32_t pal_exerciser_set_state(EXERCISER_STATE state, uint64_t *value, uint32_t bdf); uint32_t pal_exerciser_get_state(EXERCISER_STATE *state, uint32_t bdf); uint32_t pal_exerciser_ops(EXERCISER_OPS ops, uint64_t param, uint32_t instance); uint32_t pal_exerciser_get_data(EXERCISER_DATA_TYPE type, exerciser_data_t *data, uint32_t bdf, uint64_t ecam); -uint32_t pal_is_bdf_exerciser(uint32_t bdf); + uint32_t pal_nist_generate_rng(uint32_t *rng_buffer); #endif diff --git a/val/include/sbsa_avs_pcie.h b/val/include/sbsa_avs_pcie.h index 1d7255c3..7269b0c3 100644 --- a/val/include/sbsa_avs_pcie.h +++ b/val/include/sbsa_avs_pcie.h @@ -72,6 +72,7 @@ #define MEM_SHIFT 20 #define MEM_BASE_SHIFT 16 #define BAR_MASK 0xFFFFFFF0 +#define MSI_BIR_MASK 0xFFFFFFF8 /* Allows storage of 2048 valid BDFs */ #define PCIE_DEVICE_BDF_TABLE_SZ 8192 diff --git a/val/include/val_interface.h b/val/include/val_interface.h index 1cc9ae53..c03edb7c 100644 --- a/val/include/val_interface.h +++ b/val/include/val_interface.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2021, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2022, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -20,7 +20,7 @@ #include "pal_interface.h" -/* set G_PRINT_LEVEL to one of the below values in your application entry +/* set G_PRINT_LEVEL to one of the below values in your application entry to control the verbosity of the prints */ #define AVS_PRINT_ERR 5 /* Only Errors. use this to de-clutter the terminal and focus only on specifics */ #define AVS_PRINT_WARN 4 /* Only warnings & errors. use this to de-clutter the terminal and focus only on specifics */ @@ -36,6 +36,8 @@ #define AVS_STATUS_NIST_PASS 0x1 #define AVS_INVALID_INDEX 0xFFFFFFFF +#define NOT_IMPLEMENTED 0x4B1D /* Feature or API not imeplemented */ + #define VAL_EXTRACT_BITS(data, start, end) ((data >> start) & ((1ul << (end-start+1))-1)) /* GENERIC VAL APIs */ @@ -235,6 +237,7 @@ void val_iovirt_free_info_table(void); uint32_t val_iovirt_get_rc_smmu_index(uint32_t rc_seg_num, uint32_t rid); uint32_t val_smmu_execute_tests(uint32_t level, uint32_t num_pe); uint64_t val_smmu_get_info(SMMU_INFO_e, uint32_t index); +uint64_t val_iovirt_get_smmu_info(SMMU_INFO_e type, uint32_t index); typedef enum { DMA_NUM_CTRL = 1, diff --git a/val/src/avs_exerciser.c b/val/src/avs_exerciser.c index be30fac0..76880391 100644 --- a/val/src/avs_exerciser.c +++ b/val/src/avs_exerciser.c @@ -219,6 +219,11 @@ val_exerciser_execute_tests(uint32_t level) uint32_t status, i; uint32_t num_instances; + if (level == 3) { + val_print(AVS_PRINT_WARN, "Exerciser Sbsa compliance is only from Level %d \n", 4); + return AVS_STATUS_SKIP; + } + for (i = 0; i < MAX_TEST_SKIP_NUM; i++){ if (g_skip_test_num[i] == AVS_EXERCISER_TEST_NUM_BASE) { val_print(AVS_PRINT_TEST, "\n USER Override - Skipping three Exerciser tests \n", 0); diff --git a/val/src/avs_gic_support.c b/val/src/avs_gic_support.c index 46349ef0..c591479d 100644 --- a/val/src/avs_gic_support.c +++ b/val/src/avs_gic_support.c @@ -309,7 +309,8 @@ void clear_msi_x_table(uint32_t bdf, uint32_t msi_index) { uint32_t msi_cap_offset, msi_table_bar_index; - uint32_t table_offset_reg, table_address; + uint32_t table_offset_reg; + uint64_t table_address; uint32_t read_value; /* Get MSI Capability Offset */ @@ -323,7 +324,18 @@ void clear_msi_x_table(uint32_t bdf, uint32_t msi_index) /* Read MSI-X Table Address from the BAR Register */ val_pcie_read_cfg(bdf, msi_cap_offset + MSI_X_TOR_OFFSET, &table_offset_reg); msi_table_bar_index = table_offset_reg & MSI_X_TABLE_BIR_MASK; - val_pcie_read_cfg(bdf, TYPE01_BAR + msi_table_bar_index*4, &table_address); + val_pcie_read_cfg(bdf, TYPE01_BAR + msi_table_bar_index * 4, &read_value); + + /* Masking BAR attributes */ + table_address = read_value & BAR_MASK; + + if (BAR_REG(read_value) == BAR_64_BIT) + { + val_pcie_read_cfg(bdf, TYPE01_BAR + (msi_table_bar_index * 4) + 4, &read_value); + table_address = table_address | ((uint64_t)read_value << 32); + } + + table_address = table_address + (table_offset_reg & MSI_BIR_MASK); /* Clear MSI Table */ val_mmio_write(table_address + msi_index*MSI_X_ENTRY_SIZE + MSI_X_MSG_TBL_ADDR_OFFSET, 0); @@ -345,7 +357,8 @@ uint32_t fill_msi_x_table(uint32_t bdf, uint32_t msi_index, uint32_t msi_addr, u { uint32_t msi_cap_offset, msi_table_bar_index; - uint32_t table_offset_reg, table_address, command_data; + uint32_t table_offset_reg, command_data; + uint64_t table_address; uint32_t read_value; /* Enable Memory Space, Bus Master */ @@ -373,7 +386,7 @@ uint32_t fill_msi_x_table(uint32_t bdf, uint32_t msi_index, uint32_t msi_addr, u val_pcie_read_cfg(bdf, TYPE01_BAR + (msi_table_bar_index*4) + 4, &read_value); table_address = table_address | ((uint64_t)read_value << 32); } - table_address = table_address + (table_offset_reg & 0xfffffff8); + table_address = table_address + (table_offset_reg & MSI_BIR_MASK); /* Fill MSI Table with msi_addr, msi_data */ val_mmio_write(table_address + msi_index*MSI_X_ENTRY_SIZE + MSI_X_MSG_TBL_ADDR_OFFSET, msi_addr); diff --git a/val/src/avs_memory.c b/val/src/avs_memory.c index c1de3752..3187d560 100644 --- a/val/src/avs_memory.c +++ b/val/src/avs_memory.c @@ -124,8 +124,10 @@ val_memory_get_addr(MEMORY_INFO_e mem_type, uint32_t instance, uint64_t *attr) switch(mem_type) { case MEM_TYPE_DEVICE: i = val_memory_get_entry_index(MEMORY_TYPE_DEVICE, instance); + break; case MEM_TYPE_NORMAL: i = val_memory_get_entry_index(MEMORY_TYPE_NORMAL, instance); + break; default: i = 0xFF; break; diff --git a/val/src/avs_pcie.c b/val/src/avs_pcie.c index d120d185..5073b61a 100644 --- a/val/src/avs_pcie.c +++ b/val/src/avs_pcie.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2021, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2022, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -426,7 +426,7 @@ val_pcie_create_info_table(uint64_t *pcie_info_table) /* Create the list of valid Pcie Device Functions */ if (val_pcie_create_device_bdf_table()) { - val_print(AVS_PRINT_ERR, "\n Create Bdf table failed.\n", 0); + val_print(AVS_PRINT_ERR, "Create Bdf table failed.\n", 0); return; } @@ -460,7 +460,7 @@ static uint32_t val_pcie_populate_device_rootport(void) for (tbl_index = 0; tbl_index < bdf_tbl_ptr->num_entries; tbl_index++) { bdf = bdf_tbl_ptr->device[tbl_index].bdf; - val_print(AVS_PRINT_DEBUG, " Dev bdf 0x%x", bdf); + val_print(AVS_PRINT_DEBUG, " Dev bdf 0x%x", bdf); /* Fn returns rp_bdf = 0 and status = 1, if RP not found */ status = val_pcie_get_rootport(bdf, &rp_bdf); @@ -488,6 +488,7 @@ val_pcie_create_device_bdf_table() uint32_t bdf; uint32_t reg_value; uint32_t cid_offset; + uint32_t status; /* if table is already present, return success */ if (g_pcie_bdf_table) @@ -546,6 +547,10 @@ val_pcie_create_device_bdf_table() if (val_pcie_find_capability(bdf, PCIE_CAP, CID_PCIECS, &cid_offset) != PCIE_SUCCESS) continue; + status = pal_pcie_check_device_valid(bdf); + if (status) + continue; + g_pcie_bdf_table->device[g_pcie_bdf_table->num_entries++].bdf = bdf; } @@ -1855,7 +1860,7 @@ val_pcie_get_rootport(uint32_t bdf, uint32_t *rp_bdf) dp_type = val_pcie_device_port_type(bdf); - val_print(AVS_PRINT_DEBUG, " DP type 0x%x", dp_type); + val_print(AVS_PRINT_DEBUG, " DP type 0x%x ", dp_type); /* If the device is RP, set its rootport value to same */ if (dp_type == RP) diff --git a/val/src/avs_peripherals.c b/val/src/avs_peripherals.c index 8e3b1fe2..eaca3792 100644 --- a/val/src/avs_peripherals.c +++ b/val/src/avs_peripherals.c @@ -116,66 +116,82 @@ val_peripheral_get_info(PERIPHERAL_INFO_e info_type, uint32_t instance) i = val_peripheral_get_entry_index(PERIPHERAL_TYPE_USB, instance); if (i != 0xFFFF) return g_peripheral_info_table->info[i].base0; + break; case USB_FLAGS: i = val_peripheral_get_entry_index(PERIPHERAL_TYPE_USB, instance); if (i != 0xFFFF) return g_peripheral_info_table->info[i].flags; + break; case USB_GSIV: i = val_peripheral_get_entry_index(PERIPHERAL_TYPE_USB, instance); if (i != 0xFFFF) return g_peripheral_info_table->info[i].irq; + break; case USB_BDF: i = val_peripheral_get_entry_index(PERIPHERAL_TYPE_USB, instance); if (i != 0xFFFF) return g_peripheral_info_table->info[i].bdf; + break; case SATA_BASE0: i = val_peripheral_get_entry_index(PERIPHERAL_TYPE_SATA, instance); if (i != 0xFFFF) return g_peripheral_info_table->info[i].base0; + break; case SATA_BASE1: i = val_peripheral_get_entry_index(PERIPHERAL_TYPE_SATA, instance); if (i != 0xFFFF) return g_peripheral_info_table->info[i].base1; + break; case SATA_FLAGS: i = val_peripheral_get_entry_index(PERIPHERAL_TYPE_SATA, instance); if (i != 0xFFFF) return g_peripheral_info_table->info[i].flags; + break; case SATA_BDF: i = val_peripheral_get_entry_index(PERIPHERAL_TYPE_SATA, instance); if (i != 0xFFFF) return g_peripheral_info_table->info[i].bdf; + break; case SATA_GSIV: i = val_peripheral_get_entry_index(PERIPHERAL_TYPE_SATA, instance); if (i != 0xFFFF) return g_peripheral_info_table->info[i].irq; + break; case UART_BASE0: i = val_peripheral_get_entry_index(PERIPHERAL_TYPE_UART, instance); if (i != 0xFFFF) return g_peripheral_info_table->info[i].base0; + break; case UART_GSIV: i = val_peripheral_get_entry_index(PERIPHERAL_TYPE_UART, instance); if (i != 0xFFFF) return g_peripheral_info_table->info[i].irq; + break; case UART_FLAGS: i = val_peripheral_get_entry_index(PERIPHERAL_TYPE_UART, instance); if (i != 0xFFFF) return g_peripheral_info_table->info[i].flags; + break; case ANY_FLAGS: i = val_peripheral_get_entry_index (PERIPHERAL_TYPE_NONE, instance); if (i != 0xFFFF) return g_peripheral_info_table->info[i].flags; + break; case ANY_GSIV: i = val_peripheral_get_entry_index (PERIPHERAL_TYPE_NONE, instance); if (i != 0xFFFF) return g_peripheral_info_table->info[i].irq; + break; case ANY_BDF: i = val_peripheral_get_entry_index (PERIPHERAL_TYPE_NONE, instance); if (i != 0xFFFF) return g_peripheral_info_table->info[i].bdf; + break; case MAX_PASIDS: i = val_peripheral_get_entry_index (PERIPHERAL_TYPE_NONE, instance); if (i != 0xFFFF) return g_peripheral_info_table->info[i].max_pasids; + break; default: break; } diff --git a/val/src/avs_smmu.c b/val/src/avs_smmu.c index 1df44d54..3a92353c 100644 --- a/val/src/avs_smmu.c +++ b/val/src/avs_smmu.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2021, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2022, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -194,7 +194,7 @@ val_smmu_max_pasids(uint32_t smmu_index) { uint64_t smmu_base; - smmu_base = val_smmu_get_info(SMMU_CTRL_BASE, smmu_index); + smmu_base = val_iovirt_get_smmu_info(SMMU_CTRL_BASE, smmu_index); return pal_smmu_max_pasids(smmu_base); }