diff --git a/platform/pal_baremetal/FVP/RDN2/include/platform_override_fvp.h b/platform/pal_baremetal/FVP/RDN2/include/platform_override_fvp.h index 4c1ab7e1..e3e92126 100644 --- a/platform/pal_baremetal/FVP/RDN2/include/platform_override_fvp.h +++ b/platform/pal_baremetal/FVP/RDN2/include/platform_override_fvp.h @@ -32,9 +32,9 @@ extern uint32_t g_num_modules; #define PLATFORM_OVERRIDE_PRINT_LEVEL 0x3 //The permissible levels are 1,2,3,4 and 5 /* PCIe BAR config parameters*/ -#define PLATFORM_OVERRIDE_PCIE_BAR64_VAL 0x500000000 -#define PLATFORM_OVERRIDE_PCIE_BAR32NP_VAL 0x60700000 -#define PLATFORM_OVERRIDE_PCIE_BAR32P_VAL 0x60000000 +#define PLATFORM_OVERRIDE_PCIE_BAR64_VAL 0x4000000000 +#define PLATFORM_OVERRIDE_PCIE_BAR32NP_VAL 0x60000000 +#define PLATFORM_OVERRIDE_PCIE_BAR32P_VAL 0x60500000 /* PE platform config paramaters */ #define PLATFORM_OVERRIDE_PE_CNT 16 @@ -120,10 +120,10 @@ extern uint32_t g_num_modules; #define PLATFORM_OVERRIDE_GICITS_TYPE 0x1004 #define PLATFORM_OVERRIDE_GICMSIFRAME_TYPE 0x1005 #define PLATFORM_OVERRIDE_GICH_TYPE 0x1006 -#define PLATFORM_OVERRIDE_GICC_BASE 0x0 +#define PLATFORM_OVERRIDE_GICC_BASE 0x30000000 #define PLATFORM_OVERRIDE_GICD_BASE 0x30000000 #define PLATFORM_OVERRIDE_GICRD_BASE 0x301C0000 -#define PLATFORM_OVERRIDE_GICH_BASE 0x0 +#define PLATFORM_OVERRIDE_GICH_BASE 0x2C010000 #define PLATFORM_OVERRIDE_GICITS0_BASE 0x30040000 #define PLATFORM_OVERRIDE_GICITS0_ID 0 #define PLATFORM_OVERRIDE_GICITS1_BASE 0x30080000 @@ -163,7 +163,7 @@ extern uint32_t g_num_modules; #define PLATFORM_OVERRIDE_NS_EL1_TIMER_GSIV 0x1E #define PLATFORM_OVERRIDE_NS_EL2_TIMER_GSIV 0x1A #define PLATFORM_OVERRIDE_VIRTUAL_TIMER_GSIV 0x1B -#define PLATFORM_OVERRIDE_EL2_VIR_TIMER_GSIV 0 +#define PLATFORM_OVERRIDE_EL2_VIR_TIMER_GSIV 28 #define PLATFORM_OVERRIDE_PLATFORM_TIMER_COUNT 0x2 #define PLATFORM_OVERRIDE_SYS_TIMER_TYPE 0x2001 @@ -192,7 +192,7 @@ extern uint32_t g_num_modules; #define PLATFORM_OVERRIDE_TIMER_FLAGS_1 ((PLATFORM_OVERRIDE_TIMER_CMN_FLAGS_1 << 16) | \ (PLATFORM_OVERRIDE_TIMER_VIRT_FLAGS_1 << 8) | \ (PLATFORM_OVERRIDE_TIMER_PHY_FLAGS_1)) -#define PLATFORM_OVERRIDE_TIMER_CNTFRQ 0x0 +#define PLATFORM_OVERRIDE_TIMER_CNTFRQ 0x5F5E100 #define PLATFORM_OVERRIDE_TIMEOUT 1 /* Define the Timeout values to be used */ #define PLATFORM_OVERRIDE_TIMEOUT_LARGE 0x100000 @@ -218,7 +218,7 @@ extern uint32_t g_num_modules; #define PLATFORM_OVERRIDE_IRQ 1 #define PLATFORM_OVERRIDE_MAX_IRQ_CNT 0xFFFF -#define PLATFORM_OVERRIDE_MAX_SID 20 +#define PLATFORM_OVERRIDE_MAX_SID 24 /* PCIE platform config parameters */ #define PLATFORM_OVERRIDE_NUM_ECAM 1 @@ -232,7 +232,7 @@ extern uint32_t g_num_modules; #define PLATFORM_OVERRIDE_PCIE_ECAM_BASE_ADDR_0 0x1010000000 #define PLATFORM_OVERRIDE_PCIE_SEGMENT_GRP_NUM_0 0x0 #define PLATFORM_OVERRIDE_PCIE_START_BUS_NUM_0 0x0 -#define PLATFORM_OVERRIDE_PCIE_END_BUS_NUM_0 0x3F +#define PLATFORM_OVERRIDE_PCIE_END_BUS_NUM_0 0x8 #define PLATFORM_OVERRIDE_PCIE_ECAM_BASE_ADDR_1 0x1010000000 #define PLATFORM_OVERRIDE_PCIE_SEGMENT_GRP_NUM_1 0x0 @@ -240,7 +240,7 @@ extern uint32_t g_num_modules; #define PLATFORM_OVERRIDE_PCIE_END_BUS_NUM_1 0x7F #define PLATFORM_OVERRIDE_MAX_BDF 1 -#define PLATFORM_OVERRIDE_PCIE_MAX_BUS 0x40 +#define PLATFORM_OVERRIDE_PCIE_MAX_BUS 0x9 #define PLATFORM_OVERRIDE_PCIE_MAX_DEV 32 #define PLATFORM_OVERRIDE_PCIE_MAX_FUNC 8 @@ -588,149 +588,149 @@ extern uint32_t g_num_modules; #define IOVIRT_SMMU_CTX_INT_OFFSET 0x0 #define IOVIRT_SMMU_CTX_INT_CNT 0x0 #define IOVIRT_RC_PCI_SEG_NUM 0x0 -#define IOVIRT_RC_MEMORY_PROPERTIES 0x1 +#define IOVIRT_RC_MEMORY_PROPERTIES 0x0 #define IOVIRT_RC_ATS_ATTRIBUTE 0x1 #define RC_MAP0_INPUT_BASE 0x0 -#define RC_MAP0_ID_COUNT 0x3FFF +#define RC_MAP0_ID_COUNT 0x8FFF #define RC_MAP0_OUTPUT_BASE 0x30000 -#define RC_MAP0_OUTPUT_REF 0x5A4 -#define RC_MAP1_INPUT_BASE 0x4000 -#define RC_MAP1_ID_COUNT 0x3FFF -#define RC_MAP1_OUTPUT_BASE 0x34000 -#define RC_MAP1_OUTPUT_REF 0x6D0 -#define RC_MAP2_INPUT_BASE 0x8000 -#define RC_MAP2_ID_COUNT 0x3FFF -#define RC_MAP2_OUTPUT_BASE 0x38000 -#define RC_MAP2_OUTPUT_REF 0x7FC -#define RC_MAP3_INPUT_BASE 0xC000 -#define RC_MAP3_ID_COUNT 0x3FFF -#define RC_MAP3_OUTPUT_BASE 0x3C000 -#define RC_MAP3_OUTPUT_REF 0x928 - -#define SMMUV3_0_ID_MAP0_INPUT_BASE 0x30000 -#define SMMUV3_0_ID_MAP0_ID_COUNT 0x3FFF -#define SMMUV3_0_ID_MAP0_OUTPUT_BASE 0x30000 +#define RC_MAP0_OUTPUT_REF 0x644 +#define RC_MAP1_INPUT_BASE 0x900 +#define RC_MAP1_ID_COUNT 0xFF +#define RC_MAP1_OUTPUT_BASE 0x30900 +#define RC_MAP1_OUTPUT_REF 0x780 +#define RC_MAP2_INPUT_BASE 0xA00 +#define RC_MAP2_ID_COUNT 0xFF +#define RC_MAP2_OUTPUT_BASE 0x30A00 +#define RC_MAP2_OUTPUT_REF 0x8BC +#define RC_MAP3_INPUT_BASE 0xF00 +#define RC_MAP3_ID_COUNT 0xFF +#define RC_MAP3_OUTPUT_BASE 0x30B00 +#define RC_MAP3_OUTPUT_REF 0x9F8 + +#define SMMUV3_0_ID_MAP0_INPUT_BASE 0x0 +#define SMMUV3_0_ID_MAP0_ID_COUNT 0x0 +#define SMMUV3_0_ID_MAP0_OUTPUT_BASE 0x80000 #define SMMUV3_0_ID_MAP0_OUTPUT_REF 0x18 -#define SMMUV3_0_ID_MAP1_INPUT_BASE 0x0 -#define SMMUV3_0_ID_MAP1_ID_COUNT 0x1 -#define SMMUV3_0_ID_MAP1_OUTPUT_BASE 0x80000 +#define SMMUV3_0_ID_MAP1_INPUT_BASE 0x30000 +#define SMMUV3_0_ID_MAP1_ID_COUNT 0x8FF +#define SMMUV3_0_ID_MAP1_OUTPUT_BASE 0x30000 #define SMMUV3_0_ID_MAP1_OUTPUT_REF 0x18 -#define SMMUV3_1_ID_MAP0_INPUT_BASE 0x34000 -#define SMMUV3_1_ID_MAP0_ID_COUNT 0x3FFF -#define SMMUV3_1_ID_MAP0_OUTPUT_BASE 0x34000 -#define SMMUV3_1_ID_MAP0_OUTPUT_REF 0x134 -#define SMMUV3_1_ID_MAP1_INPUT_BASE 0x0 -#define SMMUV3_1_ID_MAP1_ID_COUNT 0x1 -#define SMMUV3_1_ID_MAP1_OUTPUT_BASE 0x80000 -#define SMMUV3_1_ID_MAP1_OUTPUT_REF 0x134 - -#define SMMUV3_2_ID_MAP0_INPUT_BASE 0x38000 -#define SMMUV3_2_ID_MAP0_ID_COUNT 0x3FFF -#define SMMUV3_2_ID_MAP0_OUTPUT_BASE 0x38000 -#define SMMUV3_2_ID_MAP0_OUTPUT_REF 0x250 -#define SMMUV3_2_ID_MAP1_INPUT_BASE 0x0 -#define SMMUV3_2_ID_MAP1_ID_COUNT 0x1 -#define SMMUV3_2_ID_MAP1_OUTPUT_BASE 0x80000 -#define SMMUV3_2_ID_MAP1_OUTPUT_REF 0x250 - -#define SMMUV3_3_ID_MAP0_INPUT_BASE 0x3C000 -#define SMMUV3_3_ID_MAP0_ID_COUNT 0x3FFF -#define SMMUV3_3_ID_MAP0_OUTPUT_BASE 0x3C000 -#define SMMUV3_3_ID_MAP0_OUTPUT_REF 0x36C -#define SMMUV3_3_ID_MAP1_INPUT_BASE 0x0 -#define SMMUV3_3_ID_MAP1_ID_COUNT 0x1 -#define SMMUV3_3_ID_MAP1_OUTPUT_BASE 0x80000 -#define SMMUV3_3_ID_MAP1_OUTPUT_REF 0x36C - -#define SMMUV3_4_ID_MAP0_INPUT_BASE 0x10000 -#define SMMUV3_4_ID_MAP0_ID_COUNT 0x9 -#define SMMUV3_4_ID_MAP0_OUTPUT_BASE 0x10000 -#define SMMUV3_4_ID_MAP0_OUTPUT_REF 0x488 -#define SMMUV3_4_ID_MAP1_INPUT_BASE 0x30000 +#define SMMUV3_1_ID_MAP0_INPUT_BASE 0x0 +#define SMMUV3_1_ID_MAP0_ID_COUNT 0x0 +#define SMMUV3_1_ID_MAP0_OUTPUT_BASE 0x80000 +#define SMMUV3_1_ID_MAP0_OUTPUT_REF 0x144 +#define SMMUV3_1_ID_MAP1_INPUT_BASE 0x30900 +#define SMMUV3_1_ID_MAP1_ID_COUNT 0xFF +#define SMMUV3_1_ID_MAP1_OUTPUT_BASE 0x30900 +#define SMMUV3_1_ID_MAP1_OUTPUT_REF 0x144 + +#define SMMUV3_2_ID_MAP0_INPUT_BASE 0x0 +#define SMMUV3_2_ID_MAP0_ID_COUNT 0x0 +#define SMMUV3_2_ID_MAP0_OUTPUT_BASE 0x80000 +#define SMMUV3_2_ID_MAP0_OUTPUT_REF 0x270 +#define SMMUV3_2_ID_MAP1_INPUT_BASE 0x30A00 +#define SMMUV3_2_ID_MAP1_ID_COUNT 0xFF +#define SMMUV3_2_ID_MAP1_OUTPUT_BASE 0x30A00 +#define SMMUV3_2_ID_MAP1_OUTPUT_REF 0x270 + +#define SMMUV3_3_ID_MAP0_INPUT_BASE 0x0 +#define SMMUV3_3_ID_MAP0_ID_COUNT 0x0 +#define SMMUV3_3_ID_MAP0_OUTPUT_BASE 0x80000 +#define SMMUV3_3_ID_MAP0_OUTPUT_REF 0x39C +#define SMMUV3_3_ID_MAP1_INPUT_BASE 0x30B00 +#define SMMUV3_3_ID_MAP1_ID_COUNT 0xFF +#define SMMUV3_3_ID_MAP1_OUTPUT_BASE 0x30B00 +#define SMMUV3_3_ID_MAP1_OUTPUT_REF 0x39C + +#define SMMUV3_4_ID_MAP0_INPUT_BASE 0x0 +#define SMMUV3_4_ID_MAP0_ID_COUNT 0x0 +#define SMMUV3_4_ID_MAP0_OUTPUT_BASE 0x80000 +#define SMMUV3_4_ID_MAP0_OUTPUT_REF 0x4C8 +#define SMMUV3_4_ID_MAP1_INPUT_BASE 0x10000 #define SMMUV3_4_ID_MAP1_ID_COUNT 0x9 -#define SMMUV3_4_ID_MAP1_OUTPUT_BASE 0x30000 -#define SMMUV3_4_ID_MAP1_OUTPUT_REF 0x488 -#define SMMUV3_4_ID_MAP2_INPUT_BASE 0x0 -#define SMMUV3_4_ID_MAP2_ID_COUNT 0x1 -#define SMMUV3_4_ID_MAP2_OUTPUT_BASE 0x80000 -#define SMMUV3_4_ID_MAP2_OUTPUT_REF 0x488 +#define SMMUV3_4_ID_MAP1_OUTPUT_BASE 0x10000 +#define SMMUV3_4_ID_MAP1_OUTPUT_REF 0x4C8 +#define SMMUV3_4_ID_MAP2_INPUT_BASE 0x30000 +#define SMMUV3_4_ID_MAP2_ID_COUNT 0x9 +#define SMMUV3_4_ID_MAP2_OUTPUT_BASE 0x30000 +#define SMMUV3_4_ID_MAP2_OUTPUT_REF 0x4C8 #define NAMED_COMP0_MAP0_INPUT_BASE 0x0 -#define NAMED_COMP0_MAP0_ID_COUNT 0x1 +#define NAMED_COMP0_MAP0_ID_COUNT 0x0 #define NAMED_COMP0_MAP0_OUTPUT_BASE 0x10000 -#define NAMED_COMP0_MAP0_OUTPUT_REF 0xA54 +#define NAMED_COMP0_MAP0_OUTPUT_REF 0xAE4 #define NAMED_COMP0_MAP1_INPUT_BASE 0x1 -#define NAMED_COMP0_MAP1_ID_COUNT 0x1 +#define NAMED_COMP0_MAP1_ID_COUNT 0x0 #define NAMED_COMP0_MAP1_OUTPUT_BASE 0x10001 -#define NAMED_COMP0_MAP1_OUTPUT_REF 0xA54 +#define NAMED_COMP0_MAP1_OUTPUT_REF 0xAE4 #define NAMED_COMP0_MAP2_INPUT_BASE 0x2 -#define NAMED_COMP0_MAP2_ID_COUNT 0x1 +#define NAMED_COMP0_MAP2_ID_COUNT 0x0 #define NAMED_COMP0_MAP2_OUTPUT_BASE 0x10002 -#define NAMED_COMP0_MAP2_OUTPUT_REF 0xA54 +#define NAMED_COMP0_MAP2_OUTPUT_REF 0xAE4 #define NAMED_COMP0_MAP3_INPUT_BASE 0x3 -#define NAMED_COMP0_MAP3_ID_COUNT 0x1 +#define NAMED_COMP0_MAP3_ID_COUNT 0x0 #define NAMED_COMP0_MAP3_OUTPUT_BASE 0x10003 -#define NAMED_COMP0_MAP3_OUTPUT_REF 0xA54 +#define NAMED_COMP0_MAP3_OUTPUT_REF 0xAE4 #define NAMED_COMP0_MAP4_INPUT_BASE 0x4 -#define NAMED_COMP0_MAP4_ID_COUNT 0x1 +#define NAMED_COMP0_MAP4_ID_COUNT 0x0 #define NAMED_COMP0_MAP4_OUTPUT_BASE 0x10004 -#define NAMED_COMP0_MAP4_OUTPUT_REF 0xA54 +#define NAMED_COMP0_MAP4_OUTPUT_REF 0xAE4 #define NAMED_COMP0_MAP5_INPUT_BASE 0x5 -#define NAMED_COMP0_MAP5_ID_COUNT 0x1 +#define NAMED_COMP0_MAP5_ID_COUNT 0x0 #define NAMED_COMP0_MAP5_OUTPUT_BASE 0x10005 -#define NAMED_COMP0_MAP5_OUTPUT_REF 0xA54 +#define NAMED_COMP0_MAP5_OUTPUT_REF 0xAE4 #define NAMED_COMP0_MAP6_INPUT_BASE 0x6 -#define NAMED_COMP0_MAP6_ID_COUNT 0x1 +#define NAMED_COMP0_MAP6_ID_COUNT 0x0 #define NAMED_COMP0_MAP6_OUTPUT_BASE 0x10006 -#define NAMED_COMP0_MAP6_OUTPUT_REF 0xA54 +#define NAMED_COMP0_MAP6_OUTPUT_REF 0xAE4 #define NAMED_COMP0_MAP7_INPUT_BASE 0x7 -#define NAMED_COMP0_MAP7_ID_COUNT 0x1 +#define NAMED_COMP0_MAP7_ID_COUNT 0x0 #define NAMED_COMP0_MAP7_OUTPUT_BASE 0x10007 -#define NAMED_COMP0_MAP7_OUTPUT_REF 0xA54 +#define NAMED_COMP0_MAP7_OUTPUT_REF 0xAE4 #define NAMED_COMP0_MAP8_INPUT_BASE 0x8 -#define NAMED_COMP0_MAP8_ID_COUNT 0x1 +#define NAMED_COMP0_MAP8_ID_COUNT 0x0 #define NAMED_COMP0_MAP8_OUTPUT_BASE 0x10008 -#define NAMED_COMP0_MAP8_OUTPUT_REF 0xA54 +#define NAMED_COMP0_MAP8_OUTPUT_REF 0xAE4 #define NAMED_COMP1_MAP0_INPUT_BASE 0x0 -#define NAMED_COMP1_MAP0_ID_COUNT 0x1 +#define NAMED_COMP1_MAP0_ID_COUNT 0x0 #define NAMED_COMP1_MAP0_OUTPUT_BASE 0x30000 -#define NAMED_COMP1_MAP0_OUTPUT_REF 0xA54 +#define NAMED_COMP1_MAP0_OUTPUT_REF 0xAE4 #define NAMED_COMP1_MAP1_INPUT_BASE 0x1 -#define NAMED_COMP1_MAP1_ID_COUNT 0x1 +#define NAMED_COMP1_MAP1_ID_COUNT 0x0 #define NAMED_COMP1_MAP1_OUTPUT_BASE 0x30001 -#define NAMED_COMP1_MAP1_OUTPUT_REF 0xA54 +#define NAMED_COMP1_MAP1_OUTPUT_REF 0xAE4 #define NAMED_COMP1_MAP2_INPUT_BASE 0x2 -#define NAMED_COMP1_MAP2_ID_COUNT 0x1 +#define NAMED_COMP1_MAP2_ID_COUNT 0x0 #define NAMED_COMP1_MAP2_OUTPUT_BASE 0x30002 -#define NAMED_COMP1_MAP2_OUTPUT_REF 0xA54 +#define NAMED_COMP1_MAP2_OUTPUT_REF 0xAE4 #define NAMED_COMP1_MAP3_INPUT_BASE 0x3 -#define NAMED_COMP1_MAP3_ID_COUNT 0x1 +#define NAMED_COMP1_MAP3_ID_COUNT 0x0 #define NAMED_COMP1_MAP3_OUTPUT_BASE 0x30003 -#define NAMED_COMP1_MAP3_OUTPUT_REF 0xA54 +#define NAMED_COMP1_MAP3_OUTPUT_REF 0xAE4 #define NAMED_COMP1_MAP4_INPUT_BASE 0x4 -#define NAMED_COMP1_MAP4_ID_COUNT 0x1 +#define NAMED_COMP1_MAP4_ID_COUNT 0x0 #define NAMED_COMP1_MAP4_OUTPUT_BASE 0x30004 -#define NAMED_COMP1_MAP4_OUTPUT_REF 0xA54 +#define NAMED_COMP1_MAP4_OUTPUT_REF 0xAE4 #define NAMED_COMP1_MAP5_INPUT_BASE 0x5 -#define NAMED_COMP1_MAP5_ID_COUNT 0x1 +#define NAMED_COMP1_MAP5_ID_COUNT 0x0 #define NAMED_COMP1_MAP5_OUTPUT_BASE 0x30005 -#define NAMED_COMP1_MAP5_OUTPUT_REF 0xA54 +#define NAMED_COMP1_MAP5_OUTPUT_REF 0xAE4 #define NAMED_COMP1_MAP6_INPUT_BASE 0x6 -#define NAMED_COMP1_MAP6_ID_COUNT 0x1 +#define NAMED_COMP1_MAP6_ID_COUNT 0x0 #define NAMED_COMP1_MAP6_OUTPUT_BASE 0x30006 -#define NAMED_COMP1_MAP6_OUTPUT_REF 0xA54 +#define NAMED_COMP1_MAP6_OUTPUT_REF 0xAE4 #define NAMED_COMP1_MAP7_INPUT_BASE 0x7 -#define NAMED_COMP1_MAP7_ID_COUNT 0x1 +#define NAMED_COMP1_MAP7_ID_COUNT 0x0 #define NAMED_COMP1_MAP7_OUTPUT_BASE 0x30007 -#define NAMED_COMP1_MAP7_OUTPUT_REF 0xA54 +#define NAMED_COMP1_MAP7_OUTPUT_REF 0xAE4 #define NAMED_COMP1_MAP8_INPUT_BASE 0x8 -#define NAMED_COMP1_MAP8_ID_COUNT 0x1 +#define NAMED_COMP1_MAP8_ID_COUNT 0x0 #define NAMED_COMP1_MAP8_OUTPUT_BASE 0x30008 -#define NAMED_COMP1_MAP8_OUTPUT_REF 0xA54 +#define NAMED_COMP1_MAP8_OUTPUT_REF 0xAE4 #define IOVIRT_PMCG_0_BASE_ADDRESS 0x0 #define IOVIRT_PMCG_0_OVERFLOW_GSIV 0x0 @@ -852,17 +852,17 @@ extern uint32_t g_num_modules; /* Memory config */ #define PLATFORM_OVERRIDE_MEMORY_ENTRY_COUNT 0x3 -#define PLATFORM_OVERRIDE_MEMORY_ENTRY0_PHY_ADDR 0xC000000 -#define PLATFORM_OVERRIDE_MEMORY_ENTRY0_VIRT_ADDR 0xC000000 +#define PLATFORM_OVERRIDE_MEMORY_ENTRY0_PHY_ADDR 0x1050000000 +#define PLATFORM_OVERRIDE_MEMORY_ENTRY0_VIRT_ADDR 0x1050000000 #define PLATFORM_OVERRIDE_MEMORY_ENTRY0_SIZE 0x4000000 #define PLATFORM_OVERRIDE_MEMORY_ENTRY0_TYPE MEMORY_TYPE_DEVICE #define PLATFORM_OVERRIDE_MEMORY_ENTRY1_PHY_ADDR 0xFF600000 -#define PLATFORM_OVERRIDE_MEMORY_ENTRY1_VIRT_ADDR 0xFF600000 +#define PLATFORM_OVERRIDE_MEMORY_ENTRY1_VIRT_ADDR 0x0 #define PLATFORM_OVERRIDE_MEMORY_ENTRY1_SIZE 0x10000 #define PLATFORM_OVERRIDE_MEMORY_ENTRY1_TYPE MEMORY_TYPE_RESERVED #define PLATFORM_OVERRIDE_MEMORY_ENTRY2_PHY_ADDR 0x80000000 #define PLATFORM_OVERRIDE_MEMORY_ENTRY2_VIRT_ADDR 0x80000000 -#define PLATFORM_OVERRIDE_MEMORY_ENTRY2_SIZE 0x7F000000 +#define PLATFORM_OVERRIDE_MEMORY_ENTRY2_SIZE 0x60000000 #define PLATFORM_OVERRIDE_MEMORY_ENTRY2_TYPE MEMORY_TYPE_NORMAL /* Cache config and MASKS*/ @@ -1312,9 +1312,9 @@ extern uint32_t g_num_modules; /* SRAT config */ -#define PLATFORM_OVERRIDE_NUM_SRAT_ENTRIES 17 -#define PLATFORM_OVERRIDE_MEM_AFF_CNT 1 -#define PLATFORM_OVERRIDE_GICC_AFF_CNT 16 +#define PLATFORM_OVERRIDE_NUM_SRAT_ENTRIES 0 +#define PLATFORM_OVERRIDE_MEM_AFF_CNT 0 +#define PLATFORM_OVERRIDE_GICC_AFF_CNT 0 #define PLATFORM_SRAT_MEM0_PROX_DOMAIN 0x0 #define PLATFORM_SRAT_MEM0_FLAGS 0x1 @@ -1401,8 +1401,8 @@ extern uint32_t g_num_modules; #define PLATFORM_SRAT_GICC15_FLAGS 0x1 #define PLATFORM_SRAT_GICC15_CLK_DOMAIN 0x0 -#define PLATFORM_OVERRIDE_NUM_OF_HMAT_PROX_DOMAIN 1 -#define PLATFORM_OVERRIDE_HMAT_MEM_ENTRIES 0x4 +#define PLATFORM_OVERRIDE_NUM_OF_HMAT_PROX_DOMAIN 0 +#define PLATFORM_OVERRIDE_HMAT_MEM_ENTRIES 0x0 #define HMAT_NODE_MEM_SLLBIC 0x1 #define HMAT_NODE_MEM_SLLBIC_DATA_TYPE 0x3 @@ -1428,7 +1428,7 @@ extern uint32_t g_num_modules; /* APMT config */ #define MAX_NUM_OF_PMU_SUPPORTED 512 -#define PLATFORM_OVERRIDE_PMU_NODE_CNT 0x1 +#define PLATFORM_OVERRIDE_PMU_NODE_CNT 0x0 #define PLATFORM_PMU_NODE0_BASE0 0x1010028000 #define PLATFORM_PMU_NODE0_BASE1 0x0 @@ -1441,14 +1441,14 @@ extern uint32_t g_num_modules; #define RAS_MAX_NUM_NODES 140 #define RAS_MAX_INTR_TYPE 0x2 -#define PLATFORM_OVERRIDE_NUM_RAS_NODES 0x1 +#define PLATFORM_OVERRIDE_NUM_RAS_NODES 0x0 -#define PLATFORM_OVERRIDE_NUM_PE_RAS_NODES 0x1 +#define PLATFORM_OVERRIDE_NUM_PE_RAS_NODES 0x0 #define PLATFORM_OVERRIDE_NUM_MC_RAS_NODES 0x0 /* RAS Node Data */ #define PLATFORM_RAS_NODE0_LENGTH 0x0 -#define PLATFORM_RAS_NODE0_NUM_INTR_ENTRY 0x1 +#define PLATFORM_RAS_NODE0_NUM_INTR_ENTRY 0x0 #define PLATFORM_RAS_NODE0_PE_PROCESSOR_ID 0x0 #define PLATFORM_RAS_NODE0_PE_RES_TYPE 0x0 @@ -1470,10 +1470,10 @@ extern uint32_t g_num_modules; #define PLATFORM_RAS_NODE0_INTR0_GSIV 0x11 #define PLATFORM_RAS_NODE0_INTR0_ITS_ID 0x0 -#define RAS2_MAX_NUM_BLOCKS 0x4 +#define RAS2_MAX_NUM_BLOCKS 0x0 -#define PLATFORM_OVERRIDE_NUM_RAS2_BLOCK 0x3 -#define PLATFORM_OVERRIDE_NUM_RAS2_MEM_BLOCK 0x3 +#define PLATFORM_OVERRIDE_NUM_RAS2_BLOCK 0x0 +#define PLATFORM_OVERRIDE_NUM_RAS2_MEM_BLOCK 0x0 #define PLATFORM_OVERRIDE_RAS2_BLOCK0_PROXIMITY 0x0 #define PLATFORM_OVERRIDE_RAS2_BLOCK0_PATROL_SCRUB_SUPPORT 0x1 @@ -1483,9 +1483,9 @@ extern uint32_t g_num_modules; #define PLATFORM_OVERRIDE_RAS2_BLOCK2_PATROL_SCRUB_SUPPORT 0x1 /*MPAM Config*/ -#define MPAM_MAX_MSC_NODE 0x1 -#define MPAM_MAX_RSRC_NODE 0x1 -#define PLATFORM_MPAM_MSC_COUNT 0x1 +#define MPAM_MAX_MSC_NODE 0x0 +#define MPAM_MAX_RSRC_NODE 0x0 +#define PLATFORM_MPAM_MSC_COUNT 0x0 #define PLATFORM_MPAM_MSC0_BASE_ADDR 0x1010028000 #define PLATFORM_MPAM_MSC0_ADDR_LEN 0x2004 diff --git a/platform/pal_baremetal/FVP/RDN2/src/platform_cfg_fvp.c b/platform/pal_baremetal/FVP/RDN2/src/platform_cfg_fvp.c index 8abc7b01..5ceb3a6e 100644 --- a/platform/pal_baremetal/FVP/RDN2/src/platform_cfg_fvp.c +++ b/platform/pal_baremetal/FVP/RDN2/src/platform_cfg_fvp.c @@ -1245,27 +1245,17 @@ SRAT_INFO_TABLE platform_srat_cfg = { .num_of_srat_entries = PLATFORM_OVERRIDE_NUM_SRAT_ENTRIES, + /* Example : SRAT Node type to be filled */ + /* .srat_info[0].node_type = SRAT_NODE_MEM_AFF, .srat_info[1].node_type = SRAT_NODE_GICC_AFF, - .srat_info[2].node_type = SRAT_NODE_GICC_AFF, - .srat_info[3].node_type = SRAT_NODE_GICC_AFF, - .srat_info[4].node_type = SRAT_NODE_GICC_AFF, - .srat_info[5].node_type = SRAT_NODE_GICC_AFF, - .srat_info[6].node_type = SRAT_NODE_GICC_AFF, - .srat_info[7].node_type = SRAT_NODE_GICC_AFF, - .srat_info[8].node_type = SRAT_NODE_GICC_AFF, - .srat_info[9].node_type = SRAT_NODE_GICC_AFF, - .srat_info[10].node_type = SRAT_NODE_GICC_AFF, - .srat_info[11].node_type = SRAT_NODE_GICC_AFF, - .srat_info[12].node_type = SRAT_NODE_GICC_AFF, - .srat_info[13].node_type = SRAT_NODE_GICC_AFF, - .srat_info[14].node_type = SRAT_NODE_GICC_AFF, - .srat_info[15].node_type = SRAT_NODE_GICC_AFF, - .srat_info[16].node_type = SRAT_NODE_GICC_AFF, + */ }; PLATFORM_OVERRIDE_SRAT_NODE_INFO_TABLE platform_srat_node_type = { + /* Example : SRAT Node type details to be filled */ + /* .mem_aff[0].prox_domain = PLATFORM_SRAT_MEM0_PROX_DOMAIN, .mem_aff[0].flags = PLATFORM_SRAT_MEM0_FLAGS, .mem_aff[0].addr_base = PLATFORM_SRAT_MEM0_ADDR_BASE, @@ -1275,98 +1265,27 @@ PLATFORM_OVERRIDE_SRAT_NODE_INFO_TABLE platform_srat_node_type = { .gicc_aff[0].proc_uid = PLATFORM_SRAT_GICC0_PROC_UID, .gicc_aff[0].flags = PLATFORM_SRAT_GICC0_FLAGS, .gicc_aff[0].clk_domain = PLATFORM_SRAT_GICC0_CLK_DOMAIN, - - .gicc_aff[1].prox_domain = PLATFORM_SRAT_GICC1_PROX_DOMAIN, - .gicc_aff[1].proc_uid = PLATFORM_SRAT_GICC1_PROC_UID, - .gicc_aff[1].flags = PLATFORM_SRAT_GICC1_FLAGS, - .gicc_aff[1].clk_domain = PLATFORM_SRAT_GICC1_CLK_DOMAIN, - - .gicc_aff[2].prox_domain = PLATFORM_SRAT_GICC2_PROX_DOMAIN, - .gicc_aff[2].proc_uid = PLATFORM_SRAT_GICC2_PROC_UID, - .gicc_aff[2].flags = PLATFORM_SRAT_GICC2_FLAGS, - .gicc_aff[2].clk_domain = PLATFORM_SRAT_GICC2_CLK_DOMAIN, - - .gicc_aff[3].prox_domain = PLATFORM_SRAT_GICC3_PROX_DOMAIN, - .gicc_aff[3].proc_uid = PLATFORM_SRAT_GICC3_PROC_UID, - .gicc_aff[3].flags = PLATFORM_SRAT_GICC3_FLAGS, - .gicc_aff[3].clk_domain = PLATFORM_SRAT_GICC3_CLK_DOMAIN, - - .gicc_aff[4].prox_domain = PLATFORM_SRAT_GICC4_PROX_DOMAIN, - .gicc_aff[4].proc_uid = PLATFORM_SRAT_GICC4_PROC_UID, - .gicc_aff[4].flags = PLATFORM_SRAT_GICC4_FLAGS, - .gicc_aff[4].clk_domain = PLATFORM_SRAT_GICC4_CLK_DOMAIN, - - .gicc_aff[5].prox_domain = PLATFORM_SRAT_GICC5_PROX_DOMAIN, - .gicc_aff[5].proc_uid = PLATFORM_SRAT_GICC5_PROC_UID, - .gicc_aff[5].flags = PLATFORM_SRAT_GICC5_FLAGS, - .gicc_aff[5].clk_domain = PLATFORM_SRAT_GICC5_CLK_DOMAIN, - - .gicc_aff[6].prox_domain = PLATFORM_SRAT_GICC6_PROX_DOMAIN, - .gicc_aff[6].proc_uid = PLATFORM_SRAT_GICC6_PROC_UID, - .gicc_aff[6].flags = PLATFORM_SRAT_GICC6_FLAGS, - .gicc_aff[6].clk_domain = PLATFORM_SRAT_GICC6_CLK_DOMAIN, - - .gicc_aff[7].prox_domain = PLATFORM_SRAT_GICC7_PROX_DOMAIN, - .gicc_aff[7].proc_uid = PLATFORM_SRAT_GICC7_PROC_UID, - .gicc_aff[7].flags = PLATFORM_SRAT_GICC7_FLAGS, - .gicc_aff[7].clk_domain = PLATFORM_SRAT_GICC7_CLK_DOMAIN, - - .gicc_aff[8].prox_domain = PLATFORM_SRAT_GICC8_PROX_DOMAIN, - .gicc_aff[8].proc_uid = PLATFORM_SRAT_GICC8_PROC_UID, - .gicc_aff[8].flags = PLATFORM_SRAT_GICC8_FLAGS, - .gicc_aff[8].clk_domain = PLATFORM_SRAT_GICC8_CLK_DOMAIN, - - .gicc_aff[9].prox_domain = PLATFORM_SRAT_GICC9_PROX_DOMAIN, - .gicc_aff[9].proc_uid = PLATFORM_SRAT_GICC9_PROC_UID, - .gicc_aff[9].flags = PLATFORM_SRAT_GICC9_FLAGS, - .gicc_aff[9].clk_domain = PLATFORM_SRAT_GICC9_CLK_DOMAIN, - - .gicc_aff[10].prox_domain = PLATFORM_SRAT_GICC10_PROX_DOMAIN, - .gicc_aff[10].proc_uid = PLATFORM_SRAT_GICC10_PROC_UID, - .gicc_aff[10].flags = PLATFORM_SRAT_GICC10_FLAGS, - .gicc_aff[10].clk_domain = PLATFORM_SRAT_GICC10_CLK_DOMAIN, - - .gicc_aff[11].prox_domain = PLATFORM_SRAT_GICC11_PROX_DOMAIN, - .gicc_aff[11].proc_uid = PLATFORM_SRAT_GICC11_PROC_UID, - .gicc_aff[11].flags = PLATFORM_SRAT_GICC11_FLAGS, - .gicc_aff[11].clk_domain = PLATFORM_SRAT_GICC11_CLK_DOMAIN, - - .gicc_aff[12].prox_domain = PLATFORM_SRAT_GICC12_PROX_DOMAIN, - .gicc_aff[12].proc_uid = PLATFORM_SRAT_GICC12_PROC_UID, - .gicc_aff[12].flags = PLATFORM_SRAT_GICC12_FLAGS, - .gicc_aff[12].clk_domain = PLATFORM_SRAT_GICC12_CLK_DOMAIN, - - .gicc_aff[13].prox_domain = PLATFORM_SRAT_GICC13_PROX_DOMAIN, - .gicc_aff[13].proc_uid = PLATFORM_SRAT_GICC13_PROC_UID, - .gicc_aff[13].flags = PLATFORM_SRAT_GICC13_FLAGS, - .gicc_aff[13].clk_domain = PLATFORM_SRAT_GICC13_CLK_DOMAIN, - - .gicc_aff[14].prox_domain = PLATFORM_SRAT_GICC14_PROX_DOMAIN, - .gicc_aff[14].proc_uid = PLATFORM_SRAT_GICC14_PROC_UID, - .gicc_aff[14].flags = PLATFORM_SRAT_GICC14_FLAGS, - .gicc_aff[14].clk_domain = PLATFORM_SRAT_GICC14_CLK_DOMAIN, - - .gicc_aff[15].prox_domain = PLATFORM_SRAT_GICC15_PROX_DOMAIN, - .gicc_aff[15].proc_uid = PLATFORM_SRAT_GICC15_PROC_UID, - .gicc_aff[15].flags = PLATFORM_SRAT_GICC15_FLAGS, - .gicc_aff[15].clk_domain = PLATFORM_SRAT_GICC15_CLK_DOMAIN, - + */ }; PLATFORM_OVERRIDE_HMAT_INFO_TABLE platform_hmat_cfg = { .num_of_prox_domain = PLATFORM_OVERRIDE_NUM_OF_HMAT_PROX_DOMAIN, + /* Example : HMAT Node details to be filled */ + /* .bw_info[0].type = HMAT_NODE_MEM_SLLBIC, .bw_info[0].data_type = HMAT_NODE_MEM_SLLBIC_DATA_TYPE, .bw_info[0].flags = HMAT_NODE_MEM_SLLBIC_FLAGS, .bw_info[0].entry_base_unit = HMAT_NODE_MEM_SLLBIC_ENTRY_BASE_UNIT, - + */ }; PLATFORM_OVERRIDE_HMAT_MEM_TABLE platform_hmat_mem_cfg = { + /* Example : HMAT MEM details to be filled */ + /* .bw_mem_info[0].mem_prox_domain = PLATFORM_HMAT_MEM0_PROX_DOMAIN, .bw_mem_info[0].max_write_bw = PLATFORM_HMAT_MEM0_MAX_WRITE_BW, .bw_mem_info[0].max_read_bw = PLATFORM_HMAT_MEM0_MAX_READ_BW, @@ -1382,20 +1301,22 @@ PLATFORM_OVERRIDE_HMAT_MEM_TABLE platform_hmat_mem_cfg = { .bw_mem_info[3].mem_prox_domain = PLATFORM_HMAT_MEM3_PROX_DOMAIN, .bw_mem_info[3].max_write_bw = PLATFORM_HMAT_MEM3_MAX_WRITE_BW, .bw_mem_info[3].max_read_bw = PLATFORM_HMAT_MEM3_MAX_READ_BW, - + */ }; PLATFORM_OVERRIDE_PMU_INFO_TABLE platform_pmu_cfg = { .pmu_count = PLATFORM_OVERRIDE_PMU_NODE_CNT, + /* Example : PMU Node details to be filled */ + /* .pmu_info[0].base0 = PLATFORM_PMU_NODE0_BASE0, .pmu_info[0].base1 = PLATFORM_PMU_NODE0_BASE1, .pmu_info[0].type = PLATFORM_PMU_NODE0_TYPE, .pmu_info[0].primary_instance = PLATFORM_PMU_NODE0_PRI_INSTANCE, .pmu_info[0].secondary_instance = PLATFORM_PMU_NODE0_SEC_INSTANCE, .pmu_info[0].dual_page_extension = PLATFORM_PMU_NODE0_DUAL_PAGE_EXT, - + */ }; RAS_INFO_TABLE platform_ras_cfg = { @@ -1404,10 +1325,12 @@ RAS_INFO_TABLE platform_ras_cfg = { .num_pe_node = PLATFORM_OVERRIDE_NUM_PE_RAS_NODES, .num_mc_node = PLATFORM_OVERRIDE_NUM_MC_RAS_NODES, + /* Example : PE RAS Node to be filled */ + /* .node[0].type = NODE_TYPE_PE, .node[0].length = 140, .node[0].num_intr_entries = 1, - + */ /* Example : Memory Controller RAS Node to be filled */ //.node[1].type = NODE_TYPE_MC, //.node[1].length = 0, @@ -1417,18 +1340,22 @@ RAS_INFO_TABLE platform_ras_cfg = { PLATFORM_OVERRIDE_RAS_NODE_DATA_INFO platform_ras_node_data = { + /* Example : PE RAS Node data to be filled */ + /* .node_data[0].pe.processor_id = PLATFORM_RAS_NODE0_PE_PROCESSOR_ID, .node_data[0].pe.resource_type = PLATFORM_RAS_NODE0_PE_RES_TYPE, .node_data[0].pe.flags = PLATFORM_RAS_NODE0_PE_FLAGS, .node_data[0].pe.affinity = PLATFORM_RAS_NODE0_PE_AFF, .node_data[0].pe.res_specific_data = PLATFORM_RAS_NODE0_PE_RES_DATA, - + */ /* Example : Memory Controller RAS Node data to be filled */ //.node_data[1].mc.proximity_domain = PLATFORM_RAS_NODE0_MC_PROX_DOMAIN, }; PLATFORM_OVERRIDE_RAS_NODE_INTERFACE_INFO platform_ras_node_interface = { + /* Example : RAS Node interface info to be filled */ + /* .intf_info[0].intf_type = PLATFORM_RAS_NODE0_INTF_TYPE, .intf_info[0].flags = PLATFORM_RAS_NODE0_INTF_FLAGS, .intf_info[0].base_addr = PLATFORM_RAS_NODE0_INTF_BASE, @@ -1437,26 +1364,18 @@ PLATFORM_OVERRIDE_RAS_NODE_INTERFACE_INFO platform_ras_node_interface = { .intf_info[0].err_rec_implement = PLATFORM_RAS_NODE0_INTF_ERR_REC_IMP, .intf_info[0].err_status_reporting = PLATFORM_RAS_NODE0_INTF_ERR_STATUS, .intf_info[0].addressing_mode = PLATFORM_RAS_NODE0_INTF_ADDR_MODE, - - /* Example : RAS Node interface info to be filled */ - /* - .intf_info[1].intf_type = PLATFORM_RAS_NODE1_INTF_TYPE, - .intf_info[1].flags = PLATFORM_RAS_NODE1_INTF_FLAGS, - .intf_info[1].base_addr = PLATFORM_RAS_NODE1_INTF_BASE, - .intf_info[1].start_rec_index = PLATFORM_RAS_NODE1_INTF_START_REC, - .intf_info[1].num_err_rec = PLATFORM_RAS_NODE1_INTF_NUM_REC, - .intf_info[1].err_rec_implement = PLATFORM_RAS_NODE1_INTF_ERR_REC_IMP, - .intf_info[1].err_status_reporting = PLATFORM_RAS_NODE1_INTF_ERR_STATUS, - .intf_info[1].addressing_mode = PLATFORM_RAS_NODE1_INTF_ADDR_MODE, */ }; PLATFORM_OVERRIDE_RAS_NODE_INTERRUPT_INFO platform_ras_node_interrupt = { + /* Example : RAS Node 0 Interrupt 0 details needs to be filled */ + /* .intr_info[0][0].type = PLATFORM_RAS_NODE0_INTR0_TYPE, .intr_info[0][0].flag = PLATFORM_RAS_NODE0_INTR0_FLAG, .intr_info[0][0].gsiv = PLATFORM_RAS_NODE0_INTR0_GSIV, .intr_info[0][0].its_grp_id = PLATFORM_RAS_NODE0_INTR0_ITS_ID, + */ /* Example : RAS Node 0 Interrupt 1 details needs to be filled */ /* @@ -1480,6 +1399,8 @@ PLATFORM_OVERRIDE_RAS2_INFO_TABLE platform_ras2_cfg = { .num_all_block = PLATFORM_OVERRIDE_NUM_RAS2_BLOCK, .num_of_mem_block = PLATFORM_OVERRIDE_NUM_RAS2_MEM_BLOCK, + /* Example : RAS2 Blocks to be filled */ + /* .blocks[0].type = RAS2_TYPE_MEMORY, .blocks[0].proximity_domain = PLATFORM_OVERRIDE_RAS2_BLOCK0_PROXIMITY, .blocks[0].patrol_scrub_support = PLATFORM_OVERRIDE_RAS2_BLOCK0_PATROL_SCRUB_SUPPORT, @@ -1491,12 +1412,6 @@ PLATFORM_OVERRIDE_RAS2_INFO_TABLE platform_ras2_cfg = { .blocks[2].type = RAS2_TYPE_MEMORY, .blocks[2].proximity_domain = PLATFORM_OVERRIDE_RAS2_BLOCK2_PROXIMITY, .blocks[2].patrol_scrub_support = PLATFORM_OVERRIDE_RAS2_BLOCK2_PATROL_SCRUB_SUPPORT, - - /* Example : RAS2 Blocks to be filled */ - /* - .blocks[1].type = RAS2_TYPE_MEMORY, - .blocks[1].proximity_domain = PLATFORM_OVERRIDE_RAS2_BLOCK1_PROXIMITY, - .blocks[1].patrol_scrub_support = PLATFORM_OVERRIDE_RAS2_BLOCK1_PATROL_SCRUB_SUPPORT, */ }; @@ -1504,6 +1419,8 @@ PLATFORM_OVERRIDE_RAS2_INFO_TABLE platform_ras2_cfg = { PLATFORM_OVERRIDE_MPAM_INFO_TABLE platform_mpam_cfg = { .msc_count = PLATFORM_MPAM_MSC_COUNT, + /* Example : MPAM MSC Blocks to be filled */ + /* .msc_node[0].msc_base_addr = PLATFORM_MPAM_MSC0_BASE_ADDR, .msc_node[0].msc_addr_len = PLATFORM_MPAM_MSC0_ADDR_LEN, .msc_node[0].max_nrdy = PLATFORM_MPAM_MSC0_MAX_NRDY, @@ -1513,5 +1430,5 @@ PLATFORM_OVERRIDE_MPAM_INFO_TABLE platform_mpam_cfg = { .msc_node[0].rsrc_node[0].locator_type = PLATFORM_MPAM_MSC0_RSRC0_LOCATOR_TYPE, .msc_node[0].rsrc_node[0].descriptor1 = PLATFORM_MPAM_MSC0_RSRC0_DESCRIPTOR1, .msc_node[0].rsrc_node[0].descriptor2 = PLATFORM_MPAM_MSC0_RSRC0_DESCRIPTOR2, - + */ }; diff --git a/platform/pal_baremetal/src/pal_pcie_enumeration.c b/platform/pal_baremetal/src/pal_pcie_enumeration.c index c81a6854..19532b0b 100644 --- a/platform/pal_baremetal/src/pal_pcie_enumeration.c +++ b/platform/pal_baremetal/src/pal_pcie_enumeration.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020-2023 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -530,7 +530,7 @@ pal_pcie_get_bdf(uint32_t ClassCode, uint32_t StartBdf) InputDev = PCIE_EXTRACT_BDF_DEV(StartBdf); InputFunc = PCIE_EXTRACT_BDF_FUNC(StartBdf); - for (Bus = InputBus; Bus < PCIE_MAX_BUS; Bus++) + for (Bus = InputBus; Bus < PLATFORM_OVERRIDE_PCIE_MAX_BUS; Bus++) { for (Dev = InputDev; Dev < PCIE_MAX_DEV; Dev++) {