This desgin is a sequential design for AES128/AES192/AES256 that is depending on a contoller to switch between the 3 systems by settign nr (number of rounds per operation for the system) . The main module is runnig the whole operation in (2nr+1) round and (2nr) clk . In the round (nr+1) we get our cipher ,in the round (2*nr+1) we decipher it and get out original input . At the final round if the input is as same as the output of the decryption operation the flag turns on ==> the input is successfully encrypted and decrypted ✅✅.
- The main module is (AES) ,this module takes two parameters nr-->number of rounds , nk-->number of bytes.
- It generates the full_key depending on the the parameters,
- Each clock the input state for the encryption or decryption (depending on the counter) is been changed depending on the AES logic.
- By any change on the counter the Display reg is been updated according the AES logic. (Display reg is resposible for storing the least eight significant bits of each state at the begining of the round )
To switch between the the AES systems you have to reset then switch (no parallel output)
for parallel output ,kindly go to design A or B