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bandpass.v
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bandpass.v
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// -------------------------------------------------------------
//
// Module: bandpass_filter
// Generated by MATLAB(R) 9.4 and the Filter Design HDL Coder 3.1.3.
// Generated on: 2020-08-06 17:35:09
// Generated by: Muhammad Abdullah
// -------------------------------------------------------------
// -------------------------------------------------------------
// HDL Code Generation Options:
//
// TargetDirectory: D:\matlab\bin\hdlsrc\bandpass_filter
// Name: bandpass_filter
// SerialPartition: 9
// TargetLanguage: Verilog
// TestBenchStimulus: impulse step ramp chirp noise
// -------------------------------------------------------------
// HDL Implementation : Fully Serial
// Multipliers : 1
// Folding Factor : 9
// -------------------------------------------------------------
// Filter Settings:
//
// Discrete-Time FIR Filter (real)
// -------------------------------
// Filter Structure : Direct-Form FIR
// Filter Length : 11
// Stable : Yes
// Linear Phase : Yes (Type 1)
// Arithmetic : fixed
// Numerator : s6,5 -> [-1 1)
// Input : s18,17 -> [-1 1)
// Filter Internals : Specify Precision
// Output : s33,30 -> [-4 4)
// Product : s26,24 -> [-2 2)
// Accumulator : s26,24 -> [-2 2)
// Round Mode : convergent
// Overflow Mode : wrap
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module bandpass_filter
(
clk,
clk_enable,
reset,
filter_in,
filter_out
);
input clk;
input clk_enable;
input reset;
input signed [17:0] filter_in; //sfix18_En17
output signed [32:0] filter_out; //sfix33_En30
////////////////////////////////////////////////////////////////
//Module Architecture: bandpass_filter
////////////////////////////////////////////////////////////////
// Local Functions
// Type Definitions
// Constants
parameter signed [5:0] coeff1 = 6'b111101; //sfix6_En5
parameter signed [5:0] coeff2 = 6'b111000; //sfix6_En5
parameter signed [5:0] coeff3 = 6'b111000; //sfix6_En5
parameter signed [5:0] coeff4 = 6'b000000; //sfix6_En5
parameter signed [5:0] coeff5 = 6'b001011; //sfix6_En5
parameter signed [5:0] coeff6 = 6'b010000; //sfix6_En5
parameter signed [5:0] coeff7 = 6'b001011; //sfix6_En5
parameter signed [5:0] coeff8 = 6'b000000; //sfix6_En5
parameter signed [5:0] coeff9 = 6'b111000; //sfix6_En5
parameter signed [5:0] coeff10 = 6'b111000; //sfix6_En5
parameter signed [5:0] coeff11 = 6'b111101; //sfix6_En5
// Signals
reg [3:0] cur_count; // ufix4
wire phase_8; // boolean
wire phase_0; // boolean
reg signed [17:0] delay_pipeline [0:10] ; // sfix18_En17
wire signed [17:0] inputmux_1; // sfix18_En17
reg signed [25:0] acc_final; // sfix26_En24
reg signed [25:0] acc_out_1; // sfix26_En24
wire signed [25:0] product_1; // sfix26_En24
wire signed [5:0] product_1_mux; // sfix6_En5
wire signed [23:0] mul_temp; // sfix24_En22
wire signed [25:0] prod_typeconvert_1; // sfix26_En24
wire signed [25:0] acc_sum_1; // sfix26_En24
wire signed [25:0] acc_in_1; // sfix26_En24
wire signed [25:0] add_signext; // sfix26_En24
wire signed [25:0] add_signext_1; // sfix26_En24
wire signed [26:0] add_temp; // sfix27_En24
wire signed [32:0] output_typeconvert; // sfix33_En30
reg signed [32:0] output_register; // sfix33_En30
// Block Statements
always @ (posedge clk or posedge reset)
begin: Counter_process
if (reset == 1'b1) begin
cur_count <= 4'b1000;
end
else begin
if (clk_enable == 1'b1) begin
if (cur_count == 4'b1000) begin
cur_count <= 4'b0000;
end
else begin
cur_count <= cur_count + 1;
end
end
end
end // Counter_process
assign phase_8 = (cur_count == 4'b1000 && clk_enable == 1'b1)? 1 : 0;
assign phase_0 = (cur_count == 4'b0000 && clk_enable == 1'b1)? 1 : 0;
always @( posedge clk or posedge reset)
begin: Delay_Pipeline_process
if (reset == 1'b1) begin
delay_pipeline[0] <= 0;
delay_pipeline[1] <= 0;
delay_pipeline[2] <= 0;
delay_pipeline[3] <= 0;
delay_pipeline[4] <= 0;
delay_pipeline[5] <= 0;
delay_pipeline[6] <= 0;
delay_pipeline[7] <= 0;
delay_pipeline[8] <= 0;
delay_pipeline[9] <= 0;
delay_pipeline[10] <= 0;
end
else begin
if (phase_8 == 1'b1) begin
delay_pipeline[0] <= filter_in;
delay_pipeline[1] <= delay_pipeline[0];
delay_pipeline[2] <= delay_pipeline[1];
delay_pipeline[3] <= delay_pipeline[2];
delay_pipeline[4] <= delay_pipeline[3];
delay_pipeline[5] <= delay_pipeline[4];
delay_pipeline[6] <= delay_pipeline[5];
delay_pipeline[7] <= delay_pipeline[6];
delay_pipeline[8] <= delay_pipeline[7];
delay_pipeline[9] <= delay_pipeline[8];
delay_pipeline[10] <= delay_pipeline[9];
end
end
end // Delay_Pipeline_process
assign inputmux_1 = (cur_count == 4'b0000) ? delay_pipeline[0] :
(cur_count == 4'b0001) ? delay_pipeline[1] :
(cur_count == 4'b0010) ? delay_pipeline[2] :
(cur_count == 4'b0011) ? delay_pipeline[4] :
(cur_count == 4'b0100) ? delay_pipeline[5] :
(cur_count == 4'b0101) ? delay_pipeline[6] :
(cur_count == 4'b0110) ? delay_pipeline[8] :
(cur_count == 4'b0111) ? delay_pipeline[9] :
delay_pipeline[10];
// ------------------ Serial partition # 1 ------------------
assign product_1_mux = (cur_count == 4'b0000) ? coeff1 :
(cur_count == 4'b0001) ? coeff2 :
(cur_count == 4'b0010) ? coeff3 :
(cur_count == 4'b0011) ? coeff5 :
(cur_count == 4'b0100) ? coeff6 :
(cur_count == 4'b0101) ? coeff7 :
(cur_count == 4'b0110) ? coeff9 :
(cur_count == 4'b0111) ? coeff10 :
coeff11;
assign mul_temp = inputmux_1 * product_1_mux;
assign product_1 = $signed({mul_temp[23:0], 2'b00});
assign prod_typeconvert_1 = product_1;
assign add_signext = prod_typeconvert_1;
assign add_signext_1 = acc_out_1;
assign add_temp = add_signext + add_signext_1;
assign acc_sum_1 = add_temp[25:0];
assign acc_in_1 = (phase_0 == 1'b1) ? prod_typeconvert_1 :
acc_sum_1;
always @ (posedge clk or posedge reset)
begin: Acc_reg_1_process
if (reset == 1'b1) begin
acc_out_1 <= 0;
end
else begin
if (clk_enable == 1'b1) begin
acc_out_1 <= acc_in_1;
end
end
end // Acc_reg_1_process
always @ (posedge clk or posedge reset)
begin: Finalsum_reg_process
if (reset == 1'b1) begin
acc_final <= 0;
end
else begin
if (phase_0 == 1'b1) begin
acc_final <= acc_out_1;
end
end
end // Finalsum_reg_process
assign output_typeconvert = $signed({acc_final[25:0], 6'b000000});
always @ (posedge clk or posedge reset)
begin: Output_Register_process
if (reset == 1'b1) begin
output_register <= 0;
end
else begin
if (phase_8 == 1'b1) begin
output_register <= output_typeconvert;
end
end
end // Output_Register_process
// Assignment Statements
assign filter_out = output_register;
endmodule // bandpass_filter