BRWM_tb.vcd

$date
	Thu Apr  8 23:42:39 2021
$end
$version
	Icarus Verilog
$end
$timescale
	1ns
$end
$scope module BRWM_tb $end
$var wire 1 ! done $end
$var wire 8 " data_out [7:0] $end
$var reg 1 # clear $end
$var reg 1 $ clk $end
$var reg 8 % data_in [7:0] $end
$var reg 1 & on_off $end
$var reg 1 ' pause $end
$var reg 1 ( rw $end
$scope module DUT $end
$var wire 1 # clear $end
$var wire 1 $ clk $end
$var wire 8 ) data_in [7:0] $end
$var wire 1 ! done $end
$var wire 1 & on_off $end
$var wire 1 ' pause $end
$var wire 1 ( rw $end
$var wire 8 * data_out [7:0] $end
$var reg 3 + CS [2:0] $end
$var reg 3 , NS [2:0] $end
$var reg 1 - flag $end
$var reg 8 . out [7:0] $end
$var integer 32 / i [31:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
bx /
bx .
x-
b0 ,
b0 +
bz *
b0 )
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0&
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x#
bz "
x!
$end
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#619
1$
#620
0$
#621
1$
#622
0$
#623
1$
#624
0$
#625
1$
#626
0$
#627
1$
#628
0$
#629
1$
#630
0$