-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathatmel_start_config.atstart
1336 lines (1336 loc) · 49.3 KB
/
atmel_start_config.atstart
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
format_version: '2'
name: My Project
versions:
api: '1.0'
backend: 1.9.698
commit: ''
content: unknown
content_pack_name: unknown
format: '2'
frontend: 1.9.698
packs_version_avr8: 1.0.1463
packs_version_qtouch: unknown
packs_version_sam: 1.0.1726
version_backend: 1.9.698
version_frontend: ''
board:
identifier: CustomBoard
device: SAMD51P20A-AF
details: null
application: null
middlewares:
FREERTOS_V1000_0:
user_label: FREERTOS_V1000_0
configuration:
freertos_advanced: true
freertos_check_for_stack_overflow: true
freertos_etaskgetstate: false
freertos_generate_run_time_stats: false
freertos_max_co_routine_priorities: 2
freertos_max_priorities: 5
freertos_minimal_stack_size: 64
freertos_pctaskgettaskname: true
freertos_tick_rate_hz: 1000
freertos_timer_task_priority: 2
freertos_timer_task_stack_depth: 64
freertos_total_heap_size: 2400
freertos_use_16_bit_ticks: false
freertos_use_application_task_tag_functions: false
freertos_use_co_routines: false
freertos_use_counting_semaphores: false
freertos_use_idle_hook: false
freertos_use_malloc_failed_hook: false
freertos_use_mutexes: true
freertos_use_port_optimised_functions: false
freertos_use_preemption: true
freertos_use_recursive_mutexes: false
freertos_use_stats_formatting_functions: true
freertos_use_tick_hook: false
freertos_use_tickless_idle: false
freertos_use_timers: true
freertos_use_trace_facility: true
freertos_uxtaskpriorityget: false
freertos_vtaskcleanupresources: false
freertos_vtaskdelay: true
freertos_vtaskdelayuntil: false
freertos_vtaskdelete: true
freertos_vtaskpriorityset: false
freertos_vtasksuspend: true
freertos_xresumefromisr: false
freertos_xtaskgetcurrenttaskhandle: false
freertos_xtaskgetidletaskhandle: false
freertos_xtimerpendfunctioncall: false
definition: Atmel:RTOS1000:0.0.1::FreeRTOS_v1000_MemMang_1
functionality: FreeRTOS_v10.0.0
api: RTOS:FreeRTOSv1000:MemMang_1
dependencies: {}
drivers:
ADC_0:
user_label: ADC_0
definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51P20A-AF::ADC0::driver_config_definition::ADC::HAL:Driver:ADC.Sync
functionality: ADC
api: HAL:Driver:ADC_Sync
configuration:
adc_advanced_settings: false
adc_arch_adjres: 0
adc_arch_corren: false
adc_arch_dbgrun: false
adc_arch_event_settings: false
adc_arch_flushei: false
adc_arch_flushinv: false
adc_arch_gaincorr: 0
adc_arch_leftadj: false
adc_arch_offcomp: false
adc_arch_offsetcorr: 0
adc_arch_ondemand: false
adc_arch_refcomp: false
adc_arch_resrdyeo: false
adc_arch_runstdby: false
adc_arch_samplen: 0
adc_arch_samplenum: 1 sample
adc_arch_seqen: 0
adc_arch_startei: false
adc_arch_startinv: false
adc_arch_winlt: 0
adc_arch_winmode: No window mode
adc_arch_winmoneo: false
adc_arch_winut: 0
adc_differential_mode: false
adc_freerunning_mode: false
adc_pinmux_negative: ADC AIN0 pin
adc_pinmux_positive: ADC AIN0 pin
adc_prescaler: Peripheral clock divided by 2
adc_reference: Internal bandgap reference
adc_resolution: 12-bit
optional_signals: []
variant: null
clocks:
domain_group:
nodes:
- name: ADC
input: Generic clock generator 1
external: false
external_frequency: 0
configuration:
adc_gclk_selection: Generic clock generator 1
ADC_1:
user_label: ADC_1
definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51P20A-AF::ADC1::driver_config_definition::ADC::HAL:Driver:ADC.Sync
functionality: ADC
api: HAL:Driver:ADC_Sync
configuration:
adc_advanced_settings: false
adc_arch_adjres: 0
adc_arch_corren: false
adc_arch_dbgrun: false
adc_arch_event_settings: false
adc_arch_flushei: false
adc_arch_flushinv: false
adc_arch_gaincorr: 0
adc_arch_leftadj: false
adc_arch_offcomp: false
adc_arch_offsetcorr: 0
adc_arch_ondemand: false
adc_arch_refcomp: false
adc_arch_resrdyeo: false
adc_arch_runstdby: false
adc_arch_samplen: 0
adc_arch_samplenum: 1 sample
adc_arch_seqen: 0
adc_arch_startei: false
adc_arch_startinv: false
adc_arch_winlt: 0
adc_arch_winmode: No window mode
adc_arch_winmoneo: false
adc_arch_winut: 0
adc_differential_mode: false
adc_freerunning_mode: false
adc_pinmux_negative: ADC AIN0 pin
adc_pinmux_positive: ADC AIN0 pin
adc_prescaler: Peripheral clock divided by 2
adc_reference: Internal bandgap reference
adc_resolution: 12-bit
optional_signals: []
variant: null
clocks:
domain_group:
nodes:
- name: ADC
input: Generic clock generator 0
external: false
external_frequency: 0
configuration:
adc_gclk_selection: Generic clock generator 0
CMCC:
user_label: CMCC
definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51P20A-AF::CMCC::driver_config_definition::CMCC::HAL:HPL:CMCC
functionality: System
api: HAL:HPL:CMCC
configuration:
cache_size: 4 KB
cmcc_advanced_configuration: false
cmcc_clock_gating_disable: false
cmcc_data_cache_disable: false
cmcc_enable: true
cmcc_inst_cache_disable: false
optional_signals: []
variant: null
clocks:
domain_group: null
DMAC:
user_label: DMAC
definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51P20A-AF::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC
functionality: System
api: HAL:HPL:DMAC
configuration:
dmac_beatsize_0: 8-bit bus transfer
dmac_beatsize_1: 8-bit bus transfer
dmac_beatsize_10: 8-bit bus transfer
dmac_beatsize_11: 8-bit bus transfer
dmac_beatsize_12: 8-bit bus transfer
dmac_beatsize_13: 8-bit bus transfer
dmac_beatsize_14: 8-bit bus transfer
dmac_beatsize_15: 8-bit bus transfer
dmac_beatsize_16: 8-bit bus transfer
dmac_beatsize_17: 8-bit bus transfer
dmac_beatsize_18: 8-bit bus transfer
dmac_beatsize_19: 8-bit bus transfer
dmac_beatsize_2: 8-bit bus transfer
dmac_beatsize_20: 8-bit bus transfer
dmac_beatsize_21: 8-bit bus transfer
dmac_beatsize_22: 8-bit bus transfer
dmac_beatsize_23: 8-bit bus transfer
dmac_beatsize_24: 8-bit bus transfer
dmac_beatsize_25: 8-bit bus transfer
dmac_beatsize_26: 8-bit bus transfer
dmac_beatsize_27: 8-bit bus transfer
dmac_beatsize_28: 8-bit bus transfer
dmac_beatsize_29: 8-bit bus transfer
dmac_beatsize_3: 8-bit bus transfer
dmac_beatsize_30: 8-bit bus transfer
dmac_beatsize_31: 8-bit bus transfer
dmac_beatsize_4: 8-bit bus transfer
dmac_beatsize_5: 8-bit bus transfer
dmac_beatsize_6: 8-bit bus transfer
dmac_beatsize_7: 8-bit bus transfer
dmac_beatsize_8: 8-bit bus transfer
dmac_beatsize_9: 8-bit bus transfer
dmac_blockact_0: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_1: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_10: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_11: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_12: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_13: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_14: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_15: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_16: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_17: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_18: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_19: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_2: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_20: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_21: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_22: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_23: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_24: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_25: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_26: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_27: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_28: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_29: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_3: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_30: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_31: Channel will be disabled if it is the last block transfer
in the transaction
dmac_blockact_4: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_5: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_6: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_7: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_8: Channel will be disabled if it is the last block transfer in
the transaction
dmac_blockact_9: Channel will be disabled if it is the last block transfer in
the transaction
dmac_channel_0_settings: false
dmac_channel_10_settings: false
dmac_channel_11_settings: false
dmac_channel_12_settings: false
dmac_channel_13_settings: false
dmac_channel_14_settings: false
dmac_channel_15_settings: false
dmac_channel_16_settings: false
dmac_channel_17_settings: false
dmac_channel_18_settings: false
dmac_channel_19_settings: false
dmac_channel_1_settings: false
dmac_channel_20_settings: false
dmac_channel_21_settings: false
dmac_channel_22_settings: false
dmac_channel_23_settings: false
dmac_channel_24_settings: false
dmac_channel_25_settings: false
dmac_channel_26_settings: false
dmac_channel_27_settings: false
dmac_channel_28_settings: false
dmac_channel_29_settings: false
dmac_channel_2_settings: false
dmac_channel_30_settings: false
dmac_channel_31_settings: false
dmac_channel_3_settings: false
dmac_channel_4_settings: false
dmac_channel_5_settings: false
dmac_channel_6_settings: false
dmac_channel_7_settings: false
dmac_channel_8_settings: false
dmac_channel_9_settings: false
dmac_dbgrun: false
dmac_dstinc_0: false
dmac_dstinc_1: false
dmac_dstinc_10: false
dmac_dstinc_11: false
dmac_dstinc_12: false
dmac_dstinc_13: false
dmac_dstinc_14: false
dmac_dstinc_15: false
dmac_dstinc_16: false
dmac_dstinc_17: false
dmac_dstinc_18: false
dmac_dstinc_19: false
dmac_dstinc_2: false
dmac_dstinc_20: false
dmac_dstinc_21: false
dmac_dstinc_22: false
dmac_dstinc_23: false
dmac_dstinc_24: false
dmac_dstinc_25: false
dmac_dstinc_26: false
dmac_dstinc_27: false
dmac_dstinc_28: false
dmac_dstinc_29: false
dmac_dstinc_3: false
dmac_dstinc_30: false
dmac_dstinc_31: false
dmac_dstinc_4: false
dmac_dstinc_5: false
dmac_dstinc_6: false
dmac_dstinc_7: false
dmac_dstinc_8: false
dmac_dstinc_9: false
dmac_enable: false
dmac_evact_0: No action
dmac_evact_1: No action
dmac_evact_10: No action
dmac_evact_11: No action
dmac_evact_12: No action
dmac_evact_13: No action
dmac_evact_14: No action
dmac_evact_15: No action
dmac_evact_16: No action
dmac_evact_17: No action
dmac_evact_18: No action
dmac_evact_19: No action
dmac_evact_2: No action
dmac_evact_20: No action
dmac_evact_21: No action
dmac_evact_22: No action
dmac_evact_23: No action
dmac_evact_24: No action
dmac_evact_25: No action
dmac_evact_26: No action
dmac_evact_27: No action
dmac_evact_28: No action
dmac_evact_29: No action
dmac_evact_3: No action
dmac_evact_30: No action
dmac_evact_31: No action
dmac_evact_4: No action
dmac_evact_5: No action
dmac_evact_6: No action
dmac_evact_7: No action
dmac_evact_8: No action
dmac_evact_9: No action
dmac_evie_0: false
dmac_evie_1: false
dmac_evie_10: false
dmac_evie_11: false
dmac_evie_12: false
dmac_evie_13: false
dmac_evie_14: false
dmac_evie_15: false
dmac_evie_16: false
dmac_evie_17: false
dmac_evie_18: false
dmac_evie_19: false
dmac_evie_2: false
dmac_evie_20: false
dmac_evie_21: false
dmac_evie_22: false
dmac_evie_23: false
dmac_evie_24: false
dmac_evie_25: false
dmac_evie_26: false
dmac_evie_27: false
dmac_evie_28: false
dmac_evie_29: false
dmac_evie_3: false
dmac_evie_30: false
dmac_evie_31: false
dmac_evie_4: false
dmac_evie_5: false
dmac_evie_6: false
dmac_evie_7: false
dmac_evie_8: false
dmac_evie_9: false
dmac_evoe_0: false
dmac_evoe_1: false
dmac_evoe_10: false
dmac_evoe_11: false
dmac_evoe_12: false
dmac_evoe_13: false
dmac_evoe_14: false
dmac_evoe_15: false
dmac_evoe_16: false
dmac_evoe_17: false
dmac_evoe_18: false
dmac_evoe_19: false
dmac_evoe_2: false
dmac_evoe_20: false
dmac_evoe_21: false
dmac_evoe_22: false
dmac_evoe_23: false
dmac_evoe_24: false
dmac_evoe_25: false
dmac_evoe_26: false
dmac_evoe_27: false
dmac_evoe_28: false
dmac_evoe_29: false
dmac_evoe_3: false
dmac_evoe_30: false
dmac_evoe_31: false
dmac_evoe_4: false
dmac_evoe_5: false
dmac_evoe_6: false
dmac_evoe_7: false
dmac_evoe_8: false
dmac_evoe_9: false
dmac_evosel_0: Event generation disabled
dmac_evosel_1: Event generation disabled
dmac_evosel_10: Event generation disabled
dmac_evosel_11: Event generation disabled
dmac_evosel_12: Event generation disabled
dmac_evosel_13: Event generation disabled
dmac_evosel_14: Event generation disabled
dmac_evosel_15: Event generation disabled
dmac_evosel_16: Event generation disabled
dmac_evosel_17: Event generation disabled
dmac_evosel_18: Event generation disabled
dmac_evosel_19: Event generation disabled
dmac_evosel_2: Event generation disabled
dmac_evosel_20: Event generation disabled
dmac_evosel_21: Event generation disabled
dmac_evosel_22: Event generation disabled
dmac_evosel_23: Event generation disabled
dmac_evosel_24: Event generation disabled
dmac_evosel_25: Event generation disabled
dmac_evosel_26: Event generation disabled
dmac_evosel_27: Event generation disabled
dmac_evosel_28: Event generation disabled
dmac_evosel_29: Event generation disabled
dmac_evosel_3: Event generation disabled
dmac_evosel_30: Event generation disabled
dmac_evosel_31: Event generation disabled
dmac_evosel_4: Event generation disabled
dmac_evosel_5: Event generation disabled
dmac_evosel_6: Event generation disabled
dmac_evosel_7: Event generation disabled
dmac_evosel_8: Event generation disabled
dmac_evosel_9: Event generation disabled
dmac_lvl_0: Channel priority 0
dmac_lvl_1: Channel priority 0
dmac_lvl_10: Channel priority 0
dmac_lvl_11: Channel priority 0
dmac_lvl_12: Channel priority 0
dmac_lvl_13: Channel priority 0
dmac_lvl_14: Channel priority 0
dmac_lvl_15: Channel priority 0
dmac_lvl_16: Channel priority 0
dmac_lvl_17: Channel priority 0
dmac_lvl_18: Channel priority 0
dmac_lvl_19: Channel priority 0
dmac_lvl_2: Channel priority 0
dmac_lvl_20: Channel priority 0
dmac_lvl_21: Channel priority 0
dmac_lvl_22: Channel priority 0
dmac_lvl_23: Channel priority 0
dmac_lvl_24: Channel priority 0
dmac_lvl_25: Channel priority 0
dmac_lvl_26: Channel priority 0
dmac_lvl_27: Channel priority 0
dmac_lvl_28: Channel priority 0
dmac_lvl_29: Channel priority 0
dmac_lvl_3: Channel priority 0
dmac_lvl_30: Channel priority 0
dmac_lvl_31: Channel priority 0
dmac_lvl_4: Channel priority 0
dmac_lvl_5: Channel priority 0
dmac_lvl_6: Channel priority 0
dmac_lvl_7: Channel priority 0
dmac_lvl_8: Channel priority 0
dmac_lvl_9: Channel priority 0
dmac_lvlen0: true
dmac_lvlen1: true
dmac_lvlen2: true
dmac_lvlen3: true
dmac_lvlpri0: 0
dmac_lvlpri1: 0
dmac_lvlpri2: 0
dmac_lvlpri3: 0
dmac_rrlvlen0: Static arbitration scheme for channel with priority 0
dmac_rrlvlen1: Static arbitration scheme for channel with priority 1
dmac_rrlvlen2: Static arbitration scheme for channel with priority 2
dmac_rrlvlen3: Static arbitration scheme for channel with priority 3
dmac_runstdby_0: false
dmac_runstdby_1: false
dmac_runstdby_10: false
dmac_runstdby_11: false
dmac_runstdby_12: false
dmac_runstdby_13: false
dmac_runstdby_14: false
dmac_runstdby_15: false
dmac_runstdby_16: false
dmac_runstdby_17: false
dmac_runstdby_18: false
dmac_runstdby_19: false
dmac_runstdby_2: false
dmac_runstdby_20: false
dmac_runstdby_21: false
dmac_runstdby_22: false
dmac_runstdby_23: false
dmac_runstdby_24: false
dmac_runstdby_25: false
dmac_runstdby_26: false
dmac_runstdby_27: false
dmac_runstdby_28: false
dmac_runstdby_29: false
dmac_runstdby_3: false
dmac_runstdby_30: false
dmac_runstdby_31: false
dmac_runstdby_4: false
dmac_runstdby_5: false
dmac_runstdby_6: false
dmac_runstdby_7: false
dmac_runstdby_8: false
dmac_runstdby_9: false
dmac_srcinc_0: false
dmac_srcinc_1: false
dmac_srcinc_10: false
dmac_srcinc_11: false
dmac_srcinc_12: false
dmac_srcinc_13: false
dmac_srcinc_14: false
dmac_srcinc_15: false
dmac_srcinc_16: false
dmac_srcinc_17: false
dmac_srcinc_18: false
dmac_srcinc_19: false
dmac_srcinc_2: false
dmac_srcinc_20: false
dmac_srcinc_21: false
dmac_srcinc_22: false
dmac_srcinc_23: false
dmac_srcinc_24: false
dmac_srcinc_25: false
dmac_srcinc_26: false
dmac_srcinc_27: false
dmac_srcinc_28: false
dmac_srcinc_29: false
dmac_srcinc_3: false
dmac_srcinc_30: false
dmac_srcinc_31: false
dmac_srcinc_4: false
dmac_srcinc_5: false
dmac_srcinc_6: false
dmac_srcinc_7: false
dmac_srcinc_8: false
dmac_srcinc_9: false
dmac_stepsel_0: Step size settings apply to the destination address
dmac_stepsel_1: Step size settings apply to the destination address
dmac_stepsel_10: Step size settings apply to the destination address
dmac_stepsel_11: Step size settings apply to the destination address
dmac_stepsel_12: Step size settings apply to the destination address
dmac_stepsel_13: Step size settings apply to the destination address
dmac_stepsel_14: Step size settings apply to the destination address
dmac_stepsel_15: Step size settings apply to the destination address
dmac_stepsel_16: Step size settings apply to the destination address
dmac_stepsel_17: Step size settings apply to the destination address
dmac_stepsel_18: Step size settings apply to the destination address
dmac_stepsel_19: Step size settings apply to the destination address
dmac_stepsel_2: Step size settings apply to the destination address
dmac_stepsel_20: Step size settings apply to the destination address
dmac_stepsel_21: Step size settings apply to the destination address
dmac_stepsel_22: Step size settings apply to the destination address
dmac_stepsel_23: Step size settings apply to the destination address
dmac_stepsel_24: Step size settings apply to the destination address
dmac_stepsel_25: Step size settings apply to the destination address
dmac_stepsel_26: Step size settings apply to the destination address
dmac_stepsel_27: Step size settings apply to the destination address
dmac_stepsel_28: Step size settings apply to the destination address
dmac_stepsel_29: Step size settings apply to the destination address
dmac_stepsel_3: Step size settings apply to the destination address
dmac_stepsel_30: Step size settings apply to the destination address
dmac_stepsel_31: Step size settings apply to the destination address
dmac_stepsel_4: Step size settings apply to the destination address
dmac_stepsel_5: Step size settings apply to the destination address
dmac_stepsel_6: Step size settings apply to the destination address
dmac_stepsel_7: Step size settings apply to the destination address
dmac_stepsel_8: Step size settings apply to the destination address
dmac_stepsel_9: Step size settings apply to the destination address
dmac_stepsize_0: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_1: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_10: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_11: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_12: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_13: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_14: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_15: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_16: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_17: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_18: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_19: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_2: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_20: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_21: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_22: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_23: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_24: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_25: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_26: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_27: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_28: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_29: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_3: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_30: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_31: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_4: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_5: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_6: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1
dmac_trifsrc_0: Only software/event triggers
dmac_trifsrc_1: Only software/event triggers
dmac_trifsrc_10: Only software/event triggers
dmac_trifsrc_11: Only software/event triggers
dmac_trifsrc_12: Only software/event triggers
dmac_trifsrc_13: Only software/event triggers
dmac_trifsrc_14: Only software/event triggers
dmac_trifsrc_15: Only software/event triggers
dmac_trifsrc_16: Only software/event triggers
dmac_trifsrc_17: Only software/event triggers
dmac_trifsrc_18: Only software/event triggers
dmac_trifsrc_19: Only software/event triggers
dmac_trifsrc_2: Only software/event triggers
dmac_trifsrc_20: Only software/event triggers
dmac_trifsrc_21: Only software/event triggers
dmac_trifsrc_22: Only software/event triggers
dmac_trifsrc_23: Only software/event triggers
dmac_trifsrc_24: Only software/event triggers
dmac_trifsrc_25: Only software/event triggers
dmac_trifsrc_26: Only software/event triggers
dmac_trifsrc_27: Only software/event triggers
dmac_trifsrc_28: Only software/event triggers
dmac_trifsrc_29: Only software/event triggers
dmac_trifsrc_3: Only software/event triggers
dmac_trifsrc_30: Only software/event triggers
dmac_trifsrc_31: Only software/event triggers
dmac_trifsrc_4: Only software/event triggers
dmac_trifsrc_5: Only software/event triggers
dmac_trifsrc_6: Only software/event triggers
dmac_trifsrc_7: Only software/event triggers
dmac_trifsrc_8: Only software/event triggers
dmac_trifsrc_9: Only software/event triggers
dmac_trigact_0: One trigger required for each block transfer
dmac_trigact_1: One trigger required for each block transfer
dmac_trigact_10: One trigger required for each block transfer
dmac_trigact_11: One trigger required for each block transfer
dmac_trigact_12: One trigger required for each block transfer
dmac_trigact_13: One trigger required for each block transfer
dmac_trigact_14: One trigger required for each block transfer
dmac_trigact_15: One trigger required for each block transfer
dmac_trigact_16: One trigger required for each block transfer
dmac_trigact_17: One trigger required for each block transfer
dmac_trigact_18: One trigger required for each block transfer
dmac_trigact_19: One trigger required for each block transfer
dmac_trigact_2: One trigger required for each block transfer
dmac_trigact_20: One trigger required for each block transfer
dmac_trigact_21: One trigger required for each block transfer
dmac_trigact_22: One trigger required for each block transfer
dmac_trigact_23: One trigger required for each block transfer
dmac_trigact_24: One trigger required for each block transfer
dmac_trigact_25: One trigger required for each block transfer
dmac_trigact_26: One trigger required for each block transfer
dmac_trigact_27: One trigger required for each block transfer
dmac_trigact_28: One trigger required for each block transfer
dmac_trigact_29: One trigger required for each block transfer
dmac_trigact_3: One trigger required for each block transfer
dmac_trigact_30: One trigger required for each block transfer
dmac_trigact_31: One trigger required for each block transfer
dmac_trigact_4: One trigger required for each block transfer
dmac_trigact_5: One trigger required for each block transfer
dmac_trigact_6: One trigger required for each block transfer
dmac_trigact_7: One trigger required for each block transfer
dmac_trigact_8: One trigger required for each block transfer
dmac_trigact_9: One trigger required for each block transfer
optional_signals: []
variant: null
clocks:
domain_group: null
GCLK:
user_label: GCLK
definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51P20A-AF::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK
functionality: System
api: HAL:HPL:GCLK
configuration:
$input: 120000512
$input_id: Digital Phase Locked Loop (DPLL1)
RESERVED_InputFreq: 120000512
RESERVED_InputFreq_id: Digital Phase Locked Loop (DPLL1)
_$freq_output_Generic clock generator 0: 12000000
_$freq_output_Generic clock generator 1: 6000000
_$freq_output_Generic clock generator 10: 12000000
_$freq_output_Generic clock generator 11: 12000000
_$freq_output_Generic clock generator 2: 12000000
_$freq_output_Generic clock generator 3: 32768
_$freq_output_Generic clock generator 4: 32768
_$freq_output_Generic clock generator 5: 48000000
_$freq_output_Generic clock generator 6: 120000512
_$freq_output_Generic clock generator 7: 12000000
_$freq_output_Generic clock generator 8: 12000000
_$freq_output_Generic clock generator 9: 12000000
enable_gclk_gen_0: true
enable_gclk_gen_0__externalclock: 1000000
enable_gclk_gen_1: true
enable_gclk_gen_10: false
enable_gclk_gen_10__externalclock: 1000000
enable_gclk_gen_11: false
enable_gclk_gen_11__externalclock: 1000000
enable_gclk_gen_1__externalclock: 1000000
enable_gclk_gen_2: true
enable_gclk_gen_2__externalclock: 1000000
enable_gclk_gen_3: true
enable_gclk_gen_3__externalclock: 1000000
enable_gclk_gen_4: true
enable_gclk_gen_4__externalclock: 1000000
enable_gclk_gen_5: false
enable_gclk_gen_5__externalclock: 1000000
enable_gclk_gen_6: false
enable_gclk_gen_6__externalclock: 1000000
enable_gclk_gen_7: false
enable_gclk_gen_7__externalclock: 1000000
enable_gclk_gen_8: false
enable_gclk_gen_8__externalclock: 1000000
enable_gclk_gen_9: false
enable_gclk_gen_9__externalclock: 1000000
gclk_arch_gen_0_enable: true
gclk_arch_gen_0_idc: false
gclk_arch_gen_0_oe: false
gclk_arch_gen_0_oov: false
gclk_arch_gen_0_runstdby: false
gclk_arch_gen_10_enable: false
gclk_arch_gen_10_idc: false
gclk_arch_gen_10_oe: false
gclk_arch_gen_10_oov: false
gclk_arch_gen_10_runstdby: false
gclk_arch_gen_11_enable: false
gclk_arch_gen_11_idc: false
gclk_arch_gen_11_oe: false
gclk_arch_gen_11_oov: false
gclk_arch_gen_11_runstdby: false
gclk_arch_gen_1_enable: true
gclk_arch_gen_1_idc: false
gclk_arch_gen_1_oe: false
gclk_arch_gen_1_oov: false
gclk_arch_gen_1_runstdby: true
gclk_arch_gen_2_enable: true
gclk_arch_gen_2_idc: false
gclk_arch_gen_2_oe: false
gclk_arch_gen_2_oov: false
gclk_arch_gen_2_runstdby: false
gclk_arch_gen_3_enable: true
gclk_arch_gen_3_idc: false
gclk_arch_gen_3_oe: false
gclk_arch_gen_3_oov: false
gclk_arch_gen_3_runstdby: false
gclk_arch_gen_4_enable: true
gclk_arch_gen_4_idc: false
gclk_arch_gen_4_oe: false
gclk_arch_gen_4_oov: false
gclk_arch_gen_4_runstdby: false
gclk_arch_gen_5_enable: false
gclk_arch_gen_5_idc: false
gclk_arch_gen_5_oe: false
gclk_arch_gen_5_oov: false
gclk_arch_gen_5_runstdby: false
gclk_arch_gen_6_enable: false
gclk_arch_gen_6_idc: false
gclk_arch_gen_6_oe: false
gclk_arch_gen_6_oov: false
gclk_arch_gen_6_runstdby: false
gclk_arch_gen_7_enable: false
gclk_arch_gen_7_idc: false
gclk_arch_gen_7_oe: false
gclk_arch_gen_7_oov: false
gclk_arch_gen_7_runstdby: false
gclk_arch_gen_8_enable: false
gclk_arch_gen_8_idc: false
gclk_arch_gen_8_oe: false
gclk_arch_gen_8_oov: false
gclk_arch_gen_8_runstdby: false
gclk_arch_gen_9_enable: false
gclk_arch_gen_9_idc: false
gclk_arch_gen_9_oe: false
gclk_arch_gen_9_oov: false
gclk_arch_gen_9_runstdby: false
gclk_gen_0_div: 4
gclk_gen_0_div_sel: false
gclk_gen_0_oscillator: Digital Frequency Locked Loop (DFLL48M)
gclk_gen_10_div: 1
gclk_gen_10_div_sel: false
gclk_gen_10_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
gclk_gen_11_div: 1
gclk_gen_11_div_sel: false
gclk_gen_11_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
gclk_gen_1_div: 8
gclk_gen_1_div_sel: false
gclk_gen_1_oscillator: Digital Frequency Locked Loop (DFLL48M)
gclk_gen_2_div: 1
gclk_gen_2_div_sel: true
gclk_gen_2_oscillator: Digital Frequency Locked Loop (DFLL48M)
gclk_gen_3_div: 1
gclk_gen_3_div_sel: false
gclk_gen_3_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
gclk_gen_4_div: 1
gclk_gen_4_div_sel: false
gclk_gen_4_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
gclk_gen_5_div: 1
gclk_gen_5_div_sel: false
gclk_gen_5_oscillator: Digital Frequency Locked Loop (DFLL48M)
gclk_gen_6_div: 1
gclk_gen_6_div_sel: false
gclk_gen_6_oscillator: Digital Phase Locked Loop (DPLL1)
gclk_gen_7_div: 1
gclk_gen_7_div_sel: false
gclk_gen_7_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
gclk_gen_8_div: 1
gclk_gen_8_div_sel: false
gclk_gen_8_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
gclk_gen_9_div: 1
gclk_gen_9_div_sel: false
gclk_gen_9_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
optional_signals: []
variant: null
clocks:
domain_group: null
MCLK:
user_label: MCLK
definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51P20A-AF::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK
functionality: System
api: HAL:HPL:MCLK
configuration:
$input: 12000000
$input_id: Generic clock generator 0
RESERVED_InputFreq: 12000000
RESERVED_InputFreq_id: Generic clock generator 0
_$freq_output_CPU: 12000000
cpu_clock_source: Generic clock generator 0
cpu_div: '1'
enable_cpu_clock: true
mclk_arch_bupdiv: Divide by 8
mclk_arch_hsdiv: Divide by 1
mclk_arch_lpdiv: Divide by 4
nvm_wait_states: '0'
optional_signals: []
variant: null
clocks:
domain_group:
nodes:
- name: CPU
input: CPU
external: false
external_frequency: 0
configuration: {}
OSC32KCTRL:
user_label: OSC32KCTRL
definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51P20A-AF::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL
functionality: System
api: HAL:HPL:OSC32KCTRL
configuration:
$input: 32768
$input_id: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
RESERVED_InputFreq: 32768
RESERVED_InputFreq_id: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
_$freq_output_RTC source: 32768
enable_osculp32k: true
enable_rtc_source: false
enable_xosc32k: false
osculp32k_calib: 0
osculp32k_calib_enable: false
rtc_1khz_selection: false
rtc_source_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
xosc32k_arch_cfden: false
xosc32k_arch_cfdeo: false
xosc32k_arch_cgm: Standard mode
xosc32k_arch_en1k: false
xosc32k_arch_en32k: false
xosc32k_arch_enable: false
xosc32k_arch_ondemand: true
xosc32k_arch_runstdby: false
xosc32k_arch_startup: 62592us
xosc32k_arch_swben: false
xosc32k_arch_xtalen: true
optional_signals: []
variant: null
clocks:
domain_group: null
OSCCTRL:
user_label: OSCCTRL
definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51P20A-AF::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL
functionality: System
api: HAL:HPL:OSCCTRL
configuration:
$input: 32768
$input_id: Generic clock generator 4
RESERVED_InputFreq: 32768
RESERVED_InputFreq_id: Generic clock generator 4
_$freq_output_Digital Frequency Locked Loop (DFLL48M): 48000000
_$freq_output_Digital Phase Locked Loop (DPLL0): 47985664
_$freq_output_Digital Phase Locked Loop (DPLL1): 120000512
_$freq_output_External Crystal Oscillator 8-48MHz (XOSC0): 12000000
_$freq_output_External Crystal Oscillator 8-48MHz (XOSC1): 12000000
dfll_arch_bplckc: false
dfll_arch_calibration: false
dfll_arch_ccdis: false
dfll_arch_coarse: 31
dfll_arch_cstep: 1
dfll_arch_enable: true
dfll_arch_fine: 128
dfll_arch_fstep: 1
dfll_arch_llaw: false
dfll_arch_ondemand: false
dfll_arch_qldis: false
dfll_arch_runstdby: false
dfll_arch_stable: false
dfll_arch_usbcrm: false
dfll_arch_waitlock: true
dfll_mode: Open Loop Mode
dfll_mul: 0
dfll_ref_clock: Generic clock generator 3
enable_dfll: true
enable_fdpll0: false
enable_fdpll1: false
enable_xosc0: false
enable_xosc1: false
fdpll0_arch_dcoen: false
fdpll0_arch_enable: false
fdpll0_arch_filter: 0
fdpll0_arch_lbypass: false
fdpll0_arch_ltime: No time-out, automatic lock
fdpll0_arch_ondemand: false
fdpll0_arch_refclk: XOSC32K clock reference
fdpll0_arch_runstdby: false
fdpll0_arch_wuf: false
fdpll0_clock_dcofilter: 0
fdpll0_clock_div: 0
fdpll0_ldr: 1463
fdpll0_ldrfrac: 13
fdpll0_ref_clock: 32kHz External Crystal Oscillator (XOSC32K)
fdpll1_arch_dcoen: false
fdpll1_arch_enable: false
fdpll1_arch_filter: 0
fdpll1_arch_lbypass: false
fdpll1_arch_ltime: No time-out, automatic lock
fdpll1_arch_ondemand: false
fdpll1_arch_refclk: GCLK clock reference
fdpll1_arch_runstdby: false
fdpll1_arch_wuf: false
fdpll1_clock_dcofilter: 0
fdpll1_clock_div: 10
fdpll1_ldr: 3661
fdpll1_ldrfrac: 4
fdpll1_ref_clock: Generic clock generator 4
xosc0_arch_cfden: false
xosc0_arch_enable: false
xosc0_arch_enalc: false
xosc0_arch_lowbufgain: false
xosc0_arch_ondemand: false
xosc0_arch_runstdby: false
xosc0_arch_startup: 31us
xosc0_arch_swben: false
xosc0_arch_xtalen: false
xosc0_frequency: 12000000
xosc1_arch_cfden: false
xosc1_arch_enable: false