MCAUSE/MTVAL for illegal SCR addresses

[kliuMsft]

When r/w an unimplemented SCR address (e.g., 22), Looks like sail is trapping with MCAUSE = 2 and MTVAL=0. Just want to confirm that's indeed the intention (in the case of PERM_SR violation it returns MCAUSE = 0x1c).

[rmn30]

Yes, the former is a reserved instruction exception (as with a non-existent CSR) and we gave the latter its own CHERI cause with mtval indicating cause = 0x18 reg = PCC. Arguably it would be more RISC-V like to use reserved instruction there as with accessing CSR in the wrong mode.

[marnovandermaas]

Can this issue be closed now or is there an outstanding action here?