Case and assign examples on website don't appear to work

[jaipadmakumar]

When I try to run either the 'case' or 'assign' examples from the dropdown menu on the website, I get an error The Verilog code did not produce a valid netlist.

When I run cello in eclipse using those verilog files, I get an error saying Exception in thread "main" java.lang.IllegalStateException: Error in abstract circuit. Exiting. which traces back to line 236 in the following block:

try {
    abstract_lc = getAbstractCircuit(_options.get_fin_verilog(), ucf);
} catch(Exception e) {
    throw new IllegalStateException("Error in abstract circuit.  Exiting.");
}

I have a couple guesses for why the error arises but neither appear to be correct:

For the case statement, it seems like part of the problem may be that out1 should be declared as output reg out1; since it's in analways block. However, doing so doesn't seem to fix the problem (also other verilog files like the 'Full Demo' would presumably need that line as well but don't so I guess that statement gets automatically written in the parser?).

For the assign statement, one issue that I see is that on this line:
assign out1 = w0 | (a & c);
c is used but is never declared as in input. However, changing that to a b doesn't fix the issue.

[tim-tx]

I've noticed some bugs in the current parser, too. It's not really a proper parser to begin with, i.e. there is no parse tree, I think it just sort of cherry-picks supported cases by line scanning. I'm working on a rewrite of the parser now in Antlr, structural verilog is done, I'm near done with continuous assign statements, haven't started case statements yet. Hopefully issues like this will disappear or be easier to diagnose.

[jaipadmakumar]

Hmm ok. What do you think of using something external to parse the verilog and then parsing the output itself? There must be some sort of standard file format for circuits and it seems like that may solve a lot of headache down the road as Cello moves toward supporting more complex verilog.

I'm not sure if there's anything to do this (which I guess would be why it made sense to write a custom parser in the first place) but on first glance, it looks like ABC can already output a file in BENCH format (https://people.eecs.berkeley.edu/~alanmi/abc/abc.htm). This file looks like it could be parsed pretty straightforwardly?

[tim-tx]

I was definitely hoping that a java verilog parser was already in existence and I poked around looking for parsers before starting the Antlr thing I'm working on, but I didn't find much that looked very promising. I see ABC can output a few formats, but their website says supported input includes only "a very limited set of structural verilog." There's another tool called Icarus verilog, but it's written in C++ and only seems to provide command-line tools, I assumed that would be kinda hacky to intergrate. It seems decent though, if you're desparate you might be able to hook that up to ABC in the meantime. I think ABC is the next step after the parsed verilog anyway, after the and-inverter graph is built from the netlist.

Antlr seems nice, it makes the parsing very modular. It definitely makes adding new functionality less of a headache than adding more to the existing parser.