From c14bb00ebaaf03a12abdd04e0e269b38fed1eef5 Mon Sep 17 00:00:00 2001
From: Alex Richardson <Alexander.Richardson@cl.cam.ac.uk>
Date: Tue, 18 Jun 2024 14:16:04 -0700
Subject: [PATCH] Add Thumb instruction tracing for Arm32

---
 target/arm/helper.c        | 12 ++++++++++--
 target/arm/helper.h        |  2 +-
 target/arm/translate-a64.c |  7 ++-----
 target/arm/translate.c     | 15 ++++++++++++---
 4 files changed, 25 insertions(+), 11 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index b94a8b1ca6..205dd24abd 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -14033,11 +14033,19 @@ void aarch64_sve_change_el(CPUARMState *env, int old_el,
 #endif
 
 #ifdef CONFIG_TCG_LOG_INSTR
-void HELPER(arm_log_instr)(CPUARMState *env, target_ulong pc, uint32_t opcode)
+void HELPER(arm_log_instr)(CPUARMState *env, uint64_t pc, uint32_t opcode,
+                           uint32_t opcode_size)
 {
     if (qemu_log_instr_enabled(env)) {
         qemu_log_instr_asid(env, cpu_get_asid(env, pc));
-        qemu_log_instr(env, pc, (char *)&opcode, sizeof(opcode));
+        if (opcode_size == 2) {
+            uint16_t opcode16 = opcode;
+            qemu_log_instr(env, pc, (char *)&opcode16, opcode_size);
+        } else {
+            tcg_debug_assert(opcode_size == 4);
+            qemu_log_instr(env, pc, (char *)&opcode, opcode_size);
+        }
+
     }
 }
 #endif
diff --git a/target/arm/helper.h b/target/arm/helper.h
index ac5e8438fc..2fee3bd47a 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -938,7 +938,7 @@ DEF_HELPER_FLAGS_5(neon_sqrdmulh_s, TCG_CALL_NO_RWG,
 #endif
 
 #ifdef CONFIG_TCG_LOG_INSTR
-DEF_HELPER_FLAGS_3(arm_log_instr, TCG_CALL_NO_WG, void, env, tl, i32)
+DEF_HELPER_FLAGS_4(arm_log_instr, TCG_CALL_NO_WG, void, env, i64, i32, i32)
 #endif
 
 #ifdef TARGET_CHERI
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index dbc8ace042..40112c321d 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -15304,11 +15304,8 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)
 
 #if defined(CONFIG_TCG_LOG_INSTR)
     if (unlikely(s->base.log_instr_enabled)) {
-        TCGv pc = tcg_const_tl(s->base.pc_next);
-        TCGv_i32 opc = tcg_const_i32(insn);
-        gen_helper_arm_log_instr(cpu_env, pc, opc);
-        tcg_temp_free(pc);
-        tcg_temp_free_i32(opc);
+        gen_helper_arm_log_instr(cpu_env, tcg_constant_i64(s->pc_curr),
+                                 tcg_constant_i32(insn), tcg_constant_i32(4));
     }
 
 #endif
diff --git a/target/arm/translate.c b/target/arm/translate.c
index faed6ead36..290d3d1135 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9110,9 +9110,8 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
 
 #if defined(CONFIG_TCG_LOG_INSTR)
     if (unlikely(dcbase->log_instr_enabled)) {
-        TCGv pc = tcg_const_tl(dc->pc_curr);
-        gen_helper_arm_log_instr(cpu_env, pc, tcg_constant_i32(insn));
-        tcg_temp_free(pc);
+        gen_helper_arm_log_instr(cpu_env, tcg_constant_i64(dc->pc_curr),
+                                 tcg_constant_i32(insn), tcg_constant_i32(4));
     }
 #endif
 
@@ -9193,6 +9192,16 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
     }
     dc->insn = insn;
 
+#if defined(CONFIG_TCG_LOG_INSTR)
+    if (unlikely(dcbase->log_instr_enabled)) {
+        /* For Thumb we have to undo the 16-bit swap above for disassembly. */
+        gen_helper_arm_log_instr(
+            cpu_env, tcg_constant_i64(dc->pc_curr),
+            tcg_constant_i32(is_16bit ? insn : rol32(insn, 16)),
+            tcg_constant_i32(is_16bit ? 2 : 4));
+    }
+#endif
+
     if (dc->condexec_mask && !thumb_insn_is_unconditional(dc, insn)) {
         uint32_t cond = dc->condexec_cond;