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README
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/* *********************************************************************
* Broadcom Common Firmware Environment (CFE)
*
* README
*
* Author: Mitch Lichtenberg
*
*********************************************************************
*
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
* This software is furnished under license and may be used and
* copied only in accordance with the following terms and
* conditions. Subject to these conditions, you may download,
* copy, install, use, modify and distribute modified or unmodified
* copies of this software in source and/or binary form. No title
* or ownership is transferred hereby.
*
* 1) Any source code used, modified or distributed must reproduce
* and retain this copyright notice and list of conditions
* as they appear in the source file.
*
* 2) No right is granted to use any trade name, trademark, or
* logo of Broadcom Corporation. The "Broadcom Corporation"
* name may not be used to endorse or promote products derived
* from this software without the prior written permission of
* Broadcom Corporation.
*
* 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
* PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
* SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
* PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
* TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
********************************************************************* */
RELEASE NOTES FOR: CFE version 1.4.2
------------------------------------------------------------------------------
INTRODUCTION
------------------------------------------------------------------------------
This directory contains Broadcom's Broadband processor division
"Common Firmware Environment," or CFE. (pronounce it 'cafe' if you like)
It is intended to be a flexible toolkit of CPU initialization and
bootstrap code for use on processors like the SB1250 and its derivatives.
CFE contains the following important features:
* Easy to port to new SB1250/BCM1480 designs
* Initializes CPUs, caches, memory controllers, and peripherals
* Built-in device drivers for SB1250 SOC peripherals
* Several console choices, including serial ports, ROM
emulators, JTAG, etc.
* Environment storage in NV EEPROM, flash, etc.
* Supports big or little endian operation
* Supports 32-bit and 64-bit processors
* Support for network bootstrap. Network protocols supported
include IP,ARP,ICMP,UDP,DHCP,TFTP.
* Support for disk bootstrap.
* Provides an external API for boot loaders and startup programs
* Simple user interface. UI is easy to remove for embedded apps.
See the file 'TODO' for a list of things that are being considered
as CFE matures.
There is some documentation in PDF format in the docs/ directory.
------------------------------------------------------------------------
Directory organization
----------------------
CFE is laid out to make it easy to build and maintain versions for
different boards at the same time. The directories at this level
are the build areas for ports of CFE:
cfe/ Main CFE source tree
build/ The "new" build tree location
The 'build' directory contains build areas for various
targets, and the skeletal Makefiles that build them. This
directory has subdirectories by vendor, so you can create
your own directory here and avoid hassles with merging changes.
build/broadcom/bcm91480ht/ BCM1480 evaulation board - "BIG DIPPER"
build/broadcom/bcm91280e/ BCM1480 evaluation board - "CUPERTINO"
build/broadcom/bcm91480b/ BCM1480 evaluation board - "BIG SUR"
build/broadcom/swarm/ BCM1250 evaluation board - "SWARM"
build/broadcom/sentosa/ BCM1250 evaluation board - "SENTOSA"
build/broadcom/rhone/ BCM1125 evaluation board - "RHONE"
build/broadcom/bcm1250cpci BCM1250 evaluation board - "BCM1250CPCI"
build/broadcom/vcs/ Verilog simulator version
build/broadcom/sim/ Functional Simulator
build/broadcom/tiny/ Minimal version of CFE
The 'arch' directory contains architecture-specific stuff:
cfe/arch Top of architecture tree
cfe/arch/mips All MIPS-related subdirectories
cfe/arch/mips/cpu CPU-specfic subdirectories
cfe/arch/mips/board Board-specific subdirectories
cfe/arch/mips/common Common MIPS-related sources
For the SWARM platform, the following directories are of interest:
cfe/arch/mips/cpu/sb1250
cfe/arch/mips/board/swarm
cfe/arch/mips/common
For the SENTOSA platform, the following directories are of interest:
cfe/arch/mips/cpu/sb1250
cfe/arch/mips/board/sentosa
cfe/arch/mips/common
For the RHONE platform, the following directories are of interest:
cfe/arch/mips/cpu/sb1250
cfe/arch/mips/board/rhone
cfe/arch/mips/common
For the BCM91480B platform, the following directories are of interest:
cfe/arch/mips/cpu/bcm1480
cfe/arch/mips/board/bcm91480b
cfe/arch/mips/common
For the BCM91280E platform, the following directories are of interest:
cfe/arch/mips/cpu/bcm1480
cfe/arch/mips/board/bcm91280e
cfe/arch/mips/common
For the BCM91480HT platform, the following directories are of interest:
cfe/arch/mips/cpu/bcm1480
cfe/arch/mips/board/bcm91480ht
cfe/arch/mips/common
Platform-independent sources continue to live in the cfe/
directory and its subdirectories:
cfe/docs/ Documentation in PDF format
cfe/arch/ Platform-specific directories
cfe/dev/ Device drivers for consoles and boot storage
cfe/include/ Common include files
cfe/lib/ Common library routines
cfe/main/ Main program
cfe/net/ Network subsystem (IP, DHCP, TFTP, etc.)
cfe/pci/ PCI and LDT configuration
cfe/ui/ User interface
cfe/applets/ Test "applets" for firmware API
cfe/verif/ Stuff for running chip verification tests
cfe/hosttools/ Tools built on the host
cfe/vendor/ Vendor extensions to CFE
cfe/x86emu/ X86 emulator for VGA initialization
cfe/pccons/ PC console routines
Building CFE
------------
To build the firmware for the swarm (BCM1250 evaluation board)
for example:
cd swarm ; gmake all ; cd ..
This will produce:
swarm/cfe Executable file
swarm/cfe.flash Network flash update file
swarm/cfe.srec Motorola S-records
swarm/cfe.map Linker map file
------------------------------------------------------------------------------
CHANGES SINCE PREVIOUS VERSION (1.4.1)
------------------------------------------------------------------------------
* CAS 6 support for DDR2. Both 32-bit and 64-bit (ganged) channels are supported.
* Large memory (DDR2 >= 4GB) support. Tested on BCM91480B board with 4GB DDR2:
- 64-bit (ganged) channels.
- Zero channel interleave/Zero chip select interleave.
- Full channel interleave/Zero chip select interleave.
- Zero channel interleave/Full chip select interleave.
- Full channel interleave/Full chip select interleave.
* Update of cfe/applets to work with current (410) and older (25x) toolchains.
- Applets are simple programs to test callbacks into CFE.
- These compiled programs can be loaded via the TFTP loader in CFE which will
call APIs in CFE.
* Bug fixes:
- UART C/D now have correct absolute and relative addresses
(change from UM100 to UM101).
- Fused disabled CPUs now are stated as such in startup banner.
(this is the case when system_revision says it's a 4 core part and 2 or more cores
are fused disabled).
- Minor updates of files to work with newer toolchain (410) that were not being
compiled.
------------------------------------------------------------------------------
CHANGES SINCE PREVIOUS VERSION (1.4.0)
------------------------------------------------------------------------------
* Added support for HT1000/HT2000 on Big Dipper.
- HT1000/HT2000 bridge configuration and discovery
- HT1000 PCI-X bus card support
- HT2000 PCI-X and PCI-E bus card support
- HT1000/HT2000 internal device discovery: SATA (Frodo), USB, IDE, Ethernet
Note: USB, IDE, and Ethernet have not been fully tested. They will be
revisited on the next release.
------------------------------------------------------------------------------
CHANGES SINCE PREVIOUS VERSION (1.3.3)
------------------------------------------------------------------------------
* Support for sb1-elf toolchain version 4.1.0 added.
* Add support for boards with no ODT chip selects and has DRAM at cs 0/1, 2/3, etc.
This is for 1480-based boards only.
* Add BCM112x B0 and BCM1250 C3 support. This includes 1Gb DRAM support for
sb1250_draminit.c
* HSP Cleanup. Moved HSP oriented ui command to ui_hspcmds.c (from ui_pmcmds.c)
* HSP Cleanup. All HSP oriented functions moved to new bcm1480_hsp_utils.c/h 3).
Created new HSP ui routines and APIs for error detection on SPI4 and HT 4).
Added PM remote loopback functionality through connected system.
------------------------------------------------------------------------------
CHANGES SINCE PREVIOUS VERSION (1.3.2)
------------------------------------------------------------------------------
* Initial support for the BCM91480HT "Big Dipper" evaluation board has been
added.
This is an ATX-style BCM1480 eval board with 32-bit DDR2 DIMMs.
* BCM1480 DRAM init feature: A new flag option to configure the MC for boards
with no ODT chip selects. The flag is MCFLAG_NO_ODT_CS.
* CFE_CMD_DEV_ENUM API function now supported.
* CFE_CMD_ENV_DEL API now correctly delete variables from the nonvolatile
device as well as CFE's internal structures.
------------------------------------------------------------------------------
CHANGES SINCE PREVIOUS VERSION (1.3.1)
------------------------------------------------------------------------------
* Update bcm1480_pci_machdep.c. HSP buffer allocation updated to be
within hardware spec.
------------------------------------------------------------------------------
CHANGES SINCE PREVIOUS VERSION (1.3.0)
------------------------------------------------------------------------------
* Support for the BCM91280E "CUPERTINO" evaluation board has been added.
* SB1250 DRAM init feature: A new flag option to set Output Drive Strength to
"reduced strength" for DDR.
* BCM1480 DRAM init feature: A new flag option to set Output Drive Strength to
"reduced strength" for DDR and DDR2.
* Boards with non-parallel termination require SSTL_2 class 1 type for address
& data operations and reduced Output Drive Strength at the DRAM.
The Sentosa, Rhone, and Shorty have been updated for the above changes.
* Add a new CPU type BCM1158 (one core, half cache, one HT port) to cpu info
code and banner display.
* HT CSR updates: txN_htio_txphitcnt bits 7:0 (npc_phitcnt) has a range from
10..30. The init code now sets it at minimum of 10.
Since npc_phitcnt = npc_ceiling - npc_floor + 1, npc_floor is now 0xC9
(from 0xC5).
* Packet Manager Diagnostic Updates:
Added random payload test cases for packet manager.
Added additional PM debug functionality.
Added first pass PM Hash & Route loop-back diag.
- HR block initialization.
- Basic framework for HR packet loop-back testing.
- HR path and rule table pass thru tests. Map PMO(0-16) to PMI(0-16).
- HR IVC routing diag test case.
- HR payload word routing diag test case (including offset adjust).
- Path table "one-hot" bitmap routing diag test.
- Support for HR "next destination" hardware debug feature.
------------------------------------------------------------------------------
CHANGES SINCE PREVIOUS VERSION (1.3.0)
------------------------------------------------------------------------------
* Support for the BCM91280E "CUPERTINO" evaluation board has been added.
* SB1250 DRAM init feature: A new flag option to set Output Drive Strength to
"reduced strength" for DDR.
* BCM1480 DRAM init feature: A new flag option to set Output Drive Strength to
"reduced strength" for DDR and DDR2.
* Boards with non-parallel termination require SSTL_2 class 1 type for address
& data operations and reduced Output Drive Strength at the DRAM.
The Sentosa, Rhone, and Shorty have been updated for the above changes.
* Add a new CPU type BCM1158 (one core, half cache, one HT port) to cpu info
code and banner display.
* HT CSR updates: txN_htio_txphitcnt bits 7:0 (npc_phitcnt) has a range from
10..30. The init code now sets it at minimum of 10.
Since npc_phitcnt = npc_ceiling - npc_floor + 1, npc_floor is now 0xC9
(from 0xC5).
* Packet Manager Diagnostic Updates:
Added random payload test cases for packet manager.
Added additional PM debug functionality.
Added first pass PM Hash & Route loop-back diag.
- HR block initialization.
- Basic framework for HR packet loop-back testing.
- HR path and rule table pass thru tests. Map PMO(0-16) to PMI(0-16).
- HR IVC routing diag test case.
- HR payload word routing diag test case (including offset adjust).
- Path table "one-hot" bitmap routing diag test.
- Support for HR "next destination" hardware debug feature.
------------------------------------------------------------------------------
CHANGES SINCE PREVIOUS VERSION (1.2.5)
------------------------------------------------------------------------------
* BCM1480 memory init routine improvements to support new features on the
BCM1480 pass B0. New features include: dynamic ODT, frequency range control
for the DLL, 2T addr/command signaling and DQo/DQSo quarter cycle shift.
* BCM1480 memory init routine improvements to support existing features.
These include: channel interleaving, chip select interleaving, "data capture
window" calculation, and DDR2 registered DIMMs/mini-DIMMs.
* Improve memorytest command to do "walking 1s", "walking 0s", etc..
* Added support for BCM1480-based systems using DIMMs and 4GB of memory.
* Added support to select slowest chip select to configure MC when there are
multiple chip selects of different memory speeds.
------------------------------------------------------------------------------
CHANGES SINCE PREVIOUS VERSION (1.2.4)
------------------------------------------------------------------------------
This is a minor release.
* Set maximum speed of DRAM for the BCM91480B evaluation board to 200MHz.
(the DRAM init table has a "speed limit" flag to prevent the memory system
from running faster than the board is electrically capable of). You
can modify the bcm91480b_init.S to change this speed if you need to.
* Fixed some problems in the flash engine and flash driver that were
introduced in 1.2.4. These problems were mostly related to 5836 designs
and 16-bit flash chips.
* Added some more Broadcom parts to the tables in the PCI scan/display code.
------------------------------------------------------------------------------
CHANGES SINCE PREVIOUS VERSION (1.2.3)
------------------------------------------------------------------------------
* The makefiles have been reworked to allow easy selection of SMbus
devices, similar to the scheme that is used today for PCI devices. You
can now include a SMBDEVS macro in your board file to list the SMbus
devices that should be built for your board.
* Since the conversion to "all 32 bit" versions, a new bug has been
introduced that was preventing the upper halves of 64-bit registers
from being saved when calling into CFE from a 64-bit application.
This can prevent 64-bit SMP Linux from booting properly. This has
been fixed (see the macros in arch/mips/commin/include/mipsmacros.h)
and the API entry and exception files (apientry.S, exception.S).
* New callouts have been added in init_mips.S:
CPUCFG_EARLYINIT can override the default board_earlyinit
CPUCFG_DRAMINFO can override the default board_draminfo
CPUCFG_PREDRAMINIT is new; it is called just before board_draminfo
to give the board package a chance to work around bugs or do
other preparation.
* The CPU packages have been modified to have a single interface for
dealing with cache ops. A new include file, cpu_cache.h, has macros
and prototypes for cache invalidation and flush routines. All the
device drivers that support noncoherent I/O have been modified to use
these macros.
* The BCM1480 boards have had numerous small fixes, including:
- Basic initialization of certain node controller registers
- Better PCI, PCI-X support. Some basic support for BCM1480
parts in device mode has been introduced. The pci_map_window
routines and related calls have been implemented.
* A new environment variable, RESTART, has been added. If you set this
either from a program or permanently, when a program does a soft
restart to CFE, CFE will run the commands in this environment
variable. So, for example, before Linux exits you could set this
to restart Linux.
* The PCI vendor and device tables have been reduced in size considerably
to save memory.
* The USB code has been reworked to be more resilient to devices being
disconnected while they are active.
* The USB Ethernet device driver now expects a "stub" device to
be instantiated similar to the USB Serial device. With this change
you can unplug and re-plug a USB Ethernet device and it will
use the same device name.
* A new CFE "filesystem" supporting XMODEM transfers has been added. If
configured, you can boot or flash from the serial port using
the XMODEM protocol, like this:
CFE> flash -fs=xmodem uart0:
At present, only XMODEM CRC mode is allowed. Non-CRC won't work.
* The Flash engine has been modified to handle more combinations of
endianness and 16 vs 8 bit devices.
* The board packages for the Enterprise Switch group's MPC8240 and MPC8245
boards (BCM98245CPCI "BMW" and "Mousse") have been added. These
versions can be used on the control processors for certain StrataXGS
switch chassis.
------------------------------------------------------------------------------
CHANGES SINCE PREVIOUS VERSION (1.2.2)
------------------------------------------------------------------------------
This is a minor CFE release.
* To work around some issues with the fuses on BCM1480 A2 parts,
support for S0 (the original preproduction samples) has been
disabled completely. If you have a BCM1480 S0 evaluation
board or a board with a BCM1480 S0, you should re-enable
the conditional compile define _BCM1480_S0_WORKAROUNDS_
(see arch/mips/cpu/bcm1480/Makefile). The most important
workaround this enables is the restrictions on available MCLK
clock divisors in the S0 parts.
[Note that "BCM1480" includes BCM1255, BCM1280, BCM1455, BCM1480,
and the other chips in this family.]
* The BCM1480 DRAM init routine has been improved to handle higher
DDR2 DRAM speeds. The changes are also in the BCM91480B evaluation
board init routines.
* The USB ethernet drivers have been separated out into smaller drivers.
* A bug in the multiprocessor initialization of the BCM1480 has been
corrected that can sometimes cause cache line to be evicted to
the flash area. If this line contains a particular sequence
of bytes, it can switch the flash in to erase, CFI, or programming
modes unintentionally.
------------------------------------------------------------------------------
CHANGES SINCE PREVIOUS VERSION (1.2.1)
------------------------------------------------------------------------------
* The test program for the ScanLogic SL11 chip on the BCM1250CPCI
and BCM91125PCIX boards has been rewritten. Eventually, this chip
will have the same support as the OHCI drivers and thus support
booting from USB thumb drives, USB consoles, etc.
* Lots of infrastructure improvements in the USB code, mostly
changes to the device infrastructure and updates to the serial
driver to support more bizarre USB serial ports.
* The USB Ethernet driver has been greatly improved.
* BCM91480A/B board support has been greatly improved. The config
switch settings have been standardized, with new constants
added to map the switches to their functions.
* Both PCMCIA channels are now supported on the BCM91480B board.
* On the BCM91480B, Config switch settings can now be used to selectively
disable extra CPUs, allowing the BCM91480B board to behave as if it
had a BCM1280 CPU stuffed on it.
* Numerous improvements to the BCM5836/BCM4704 support, particularly
in the ara of PCI.
* Header files have been updated for the BCM1480 family. Customers should
use the new header files in their applications.
* CFE was not restoring the KX bit setting in the status register
when the user API was invoked.
* The exception message (crash dump) now includes the CPU number.
* The exception handlers were not being restored properly on a soft
restart to CFE (for example, when you reboot from Linux). This
causes trouble if you want to boot again without a hardware reset.
This problem has been fixed.
* Many, many improvements to the BCM1480 DRAM init routine. Customers
should definitely take the new version if possible. Timing
calculations have been improved, and more interleaving options
are now supported.
* The BCM1480 packet manager now has some test commands and example code
to initialize the high speed ports.
* The BCM1480 HyperTransport interface now supports a new environment
variable, LDT_LINKWIDTH, to configure the width of the interface to
8 or 16 bits. The default is 16 bits.
* The BCM1250 DRAM init routine has been improved to calculate
the tRCw, tRCR, and tCwCr values in a more consistent way.
* The flash drivers have been updated to work properly in 16-bit mode
on the BCM5836/4704 processors, for big or little endian operation.
------------------------------------------------------------------------------
CHANGES SINCE PREVIOUS VERSION (1.1.1)
------------------------------------------------------------------------------
[Note: This ia another MAJOR new CFE release. There have been
source file changes to nearly all of CFE's files to re-enable
64-bit address support while CFE remains a 32-bit app].
* MAJOR NEW FEATURE: 64-bit API, 64-bit ELF
Since CFE can no longer be built as a native 64-bit
application due to toolchain changes, special support
needed to be added throughout CFE for 64-bit support
within the 32-bit version of CFE.
*ALL* external pointers (values who could possibly reference
data beyond CFE's data segment) are declared as the
basic type "hsaddr_t" with access functions and macros
in "lib_hssubr.h".
Unfortunately, this change affected 100+ source files, including
all the device drivers and some API functions. Since CFE's
API allows applications like the Linux kernel to pass 64-bit
pointers (for example, console output or starting the other
CPUs), CFE needs to pass all 64 bits of the pointers around.
There are two new macros, PTR2HSADDR and HSADDR2PTR, that
are used to convert between hsaddr_t and regular pointers
when you know that the pointer is within CFE's data segment.
There are also two variants of memcpy, called
hs_memcpy_to_hs and hs_memcpy_from_hs, to copy data to/from
buffers that might be outside CFE's data segment.
* More BCM1480/1455/1280/1255 support.
The include files and board support packages have been improved
as we continue to test the early samples.
Some typos have been found and fixed, particularly in the
packet manager headers (bcm1480_hr.h, bcm1480_pm.h)
* BCM1480 DRAM init routine improvements.
Support for DDR2 SPD's has been added. In addition, the
timing calculations have been improved for DDR2 memories.
DDR2 memory init tables now require a "distance" parameter
that specifies the relative location of a chip select
along the memory bus. This is used to determine which
chip has on-die termination (ODT) enabled.
Support for channel interleaving (64-bit channels only) has
been added.
* Support for the BCM91480B evaluation board has been added.
This is an ATX-style 1480 eval board with DDR2 memory.
* Bug Fix: The BCM1250/BCM1480 ethernet driver was not
waiting long enough after configuration for the PHY to
settle, particularly at gigabit speed. As a result, it
often took two tries to get an address from the DHCP
server. This has been fixed by starting the PHY earlier.
* The chip type detection code and display routines have
been substantially rewritten. Hopefully they make sense now.
* Lots of old uses of __long64 have been removed. They are
no longer relevant
------------------------------------------------------------------------------
CHANGES SINCE PREVIOUS VERSION (1.0.40)
------------------------------------------------------------------------------
[Note: This is a MAJOR new CFE release. There have been source file
changes to nearly all of CFE's files to accomodate new tools
and a new relocation method. On the whole, the source changes are
minor but there are a lot of them!]
* MAJOR NEW FEATURE: New relocation method
CFE's relocation method has been changed to use System-V PIC format
instead of the old "embedded-pic". The old method is deprecated
in current GCC versions and will be deleted entirely in the future,
so CFE had to be modified to relocate without using embedded-pic.
To make this work, the low-level startup code, many of the macros
in the code, and several other places have been touched or
rewritten. The include file "cfe.h" must now be _before_ other
include files to set up certain macros properly.
* No more 64-bit versions
Since the SVR4 PIC toolchain does not support relocatable 64-bit
libraries, there are now no more 64-bit native versions of CFE.
(pointers and longs are 32 bits, and long longs are 64 bits).
CFE now runs with KX set in the status register all the time.
You can still access 64-bit data with the "d", "e", "u",
and other commands. To make this work, the old "lib_hssubr.S"
(hyperspace subroutines) has been ressurected.
NOTE: This has temporarily broken loading 64-bit ELF files, we will
revisit this in a future release.
* Processor and chipset support for the BCM1480/BCM1455/BCM1280/BCM1255
chips. Look in the arch/mips/chipset/sibyte and arch/mips/cpu/bcm1480
directories for the new files. The include files are believed
to be accurate as of the current user's manual revision and errata.
Notes specific to the 1480 release:
- In general, the 1480 package is very new and subject to
rapid change as we continue to check out the chip.
- The DRAM initialization code is still new and has some
missing features, including SPD support for DDR-II.
- 4-channel 32-bit mode has not been tested.
* Preliminary board support package for the BCM91480A, the
eval platform for the BCM1480 and BCM1280 chips. This
package is for evaluation use only, there will be another
CFE release for this board once the eval platforms are
generally available.
* Processor and chipset support for the BCM5836 low-end MIPS32
processor. Look in the arch/mips/chipset/bcmsb and arch/mips/cpu/bcmcore
directories for the new files.
* Board support package for the BCM91125CPCI
module has been added. This is an 1125-based CPCI card.
* Board support package for the BCM95836CPCI
module has been added. This is an 5836-based CPCI card.
* Board support packe for the BCM91125PCIX has been added. This
is an ATX board with a BCM1125 and an HT-to-PCIX bridge.
* The include files for the BCM1255, BCM1280, BCM1455, BCM1480
are now in the arch/mips/chipset/sibyte/include area. Preliminary
support for these new chips have been added to appropriate
areas in the source tree (dram init, etc.). More updates
in this area for the next version.
* Some preliminary support for compressing CFE has been added. It is
not fully baked yet, but customers can examine it to see if it
will be useful. With this feature, most of CFE is compressed
via gzip and a boot-loader-loader decompresses the firmware
and transfers it to memory. Look for "ZipStart"
* The flashop engine (assembly stub used to batch flash commands)
has been updated to support Intel flash buffered write commands.
This should dramatically improve write speed when using Intel
flash parts.
* The kit generation procedures we use to make the CFE kit files have
been included in the release/ directory of CFE. You can use these
procedures to package your own CFE releases.
* The Algorithmics P5064 and P6064 boards have been removed.
------------------------------------------------------------------------------
CHANGES SINCE PREVIOUS VERSION (1.0.38)
------------------------------------------------------------------------------
[Note: It's been a while since a new CFE release was made, so
customers should also read the 1.0.38 differences in the section
after this one.]
* Support for the new BCM91125F evaluation board has been introduced
* In anticipation of the BCM1x80/BCM1x55 chips, the SiByte-specific
files have been moved into their own "chipset" directory.
The Ethernet controller driver, UARTs, and other common modules that used
to live in arch/mips/cpu/sb1250 are now in arch/mips/chipset/sibyte
* The 'tiny' board target (minimalistic BCM1250 board) has been
fixed so that it builds again.
* The SMBus interface has a new level of abstraction. If your code
uses the BCM1250 SMBus device drivers in CFE, you may need
to make some changes to your board_device_init() routine
(see the code in the SWARM or Sentosa port for an example).
Basically, before devices are instantiated you should be
sure you create SMBus buses as follows:
cfe_add_smbus(&sb1250_smbus,A_SMB_BASE(0),0);
cfe_add_smbus(&sb1250_smbus,A_SMB_BASE(1),0);
Then instantiate your devices "normally." SMBuses get numbered
from zero in the order they are instantiated via cfe_add_smbus.
The new SMBus code moves all the SMBus-device-specific routines
into processor/architecture independent places and leaves
the actual SMBus protocol code in the host chip-specific
area. You can now write bit-bang SMBus host routines
or use other SMBus host controllers and re-use CFE's
pre-existing device drivers for nvram/tod/temperature chips.
* The Sentosa board's memory timing has been increased to run
the memory at 133MHz (max speed depending on core clock)
* M-Systems(tm) DiskOnChip(tm) support. If you have signed the
NDA with M-Systems and have access to their DiskOnChip
boot driver kit (BDK), CFE can access configured M-Systems
flash devices. You need to provide certain files from the
M-Systems BDK and place them in the cfe/msys directory,
then set CFG_MSYS=1 in your Makefile.
* The code in the BCM1250 cache init routines for supporting the
ancient A0..A7 parts with "binned" caches (preproduction parts
with partial caches) has been removed, since the BCM1250 is
in full production now.
* BCM1250 Pass1 support has been disabled.
* The 'mkflashimage' program should now work properly when compiled
under Cygwin.
* New device drivers for the DS1743 RTC/NVRAM, Intel i82559 Ethernet,
RealTek rtl8139 Ethernet, and a "C" version of the flash update engine.
* The PromICE console driver lets you specify whether your PromICE
is connected in direct mode (write line attached) or not,
instead of using a compile-time constant.
* The Ethernet routines have been rearranged to move common packet
manipulation, address parsing, and other non-device routines into
a common place.
* The PCI/HyperTransport init routines for the BCM1250 have been
improved to handle additional topologies and configurations.
------------------------------------------------------------------------------
CHANGES SINCE PREVIOUS VERSION (1.0.37)
------------------------------------------------------------------------------
* The BCM1250 memory initialization routine has been updated to
calculate tRCD and tRCR/tRCW more accurately when the
parameter is not supplied by the SPD. Even if you do not update
all of CFE, you should retrofit this change into your CFE if
you notice any memory timing problems.
* The console F12 key macro should work properly now to either
repeat the previous command or execute the command in the F12
environment variable.
* TFTP's retries and timeouts are now measured in ticks. The TFTP
timeouts are also stored in globals that you can modify
in your board_devs routine.
* A new user command, "reserve", has been added to reserve memory
and not communicate it to the operating system. So, you could
take a chunk of memory, reserve it, and then boot Linux and
Linux would not add that chunk to the boot map.
* The PCI initialization code has been reworked to break out
machine-dependent and machine-independent stuff more clearly.
* New drivers have been included for the BCM4401 PCI fast ethernet
and BCM570x PCI gigabit ethernet controllers.
* The NS16550 serial driver has been enhanced to take the crystal
frequency (NS16550_HZ) as a parameter. Good for boards that use
nonstandard clocks or have multiple different 16550's.
* The various "cpu_config.h" files have CPUCFG_ARCHNAME and
CPUCFG_ELFTYPE defined to break out the processor architecture and
ELF header type into cpu-specific include files.
* The Algorithmics P5064 and P6064 ports now compile again, but are
probably broken. Assume you'll have to make changes if you want to
get these working on your hardware!
------------------------------------------------------------------------------
CHANGES SINCE PREVIOUS VERSION (1.0.36)
------------------------------------------------------------------------------
* The Makefile for the BCM1250CPCI version has been modified
to support building dual-endian versions of CFE.
* Some cleanup has been done in the source files in preparation
for the release to the public (non-NDA) web site.
* The PCI enumeration code has been modified to deal with
more than one host "port". To do this, the tag format has
been changed slightly - routines that include pcivar.h
would probably need some changes.
* A typo in lib_physio.h has been fixed - writing 64-bit values
to 64-bit uncached addresses was being done with a 32-bit store.
* The most recent BCM1250 system include files have been incorporated
into the source tree.
* sbmips.h (MIPS processor stuff) has been enhanced to include a
bunch of macros and inlines for accessing CP0 registers.
* FCRAM support in the DRAM init routines has been improved.
* The startup messages now recognize Rev.C silicon.
* A new include file, endian.h, contains the "truth" about the
endianness (for use by #ifdefs in the code).
* Device drivers for PCI Ethernet controllers and other devices have
been modified to use common macros for address manipulation.
* The makefile now recognizes a new "CHIPSET" directory, to go
along with "CPU" and "BOARD" - future versions of CFE will
show some device driver files moving into this area of
the tree (under arch/mips/chipset) so that, for example,
the BCM14xx and BCM12xx console drivers can live in one place.
* The command processor has been hacked yet again to make it behave
more like a shell. In particular, quoting behaviour should once
again be working.
------------------------------------------------------------------------------
CHANGES SINCE PREVIOUS VERSION (1.0.35)
------------------------------------------------------------------------------
* The license has been modified to be "GPL compatible." This
means that you should be able to incorporate parts of CFE
into a GPL'd program without license hassles.
* The Hypertransport initialization code in CFE now supports both
the LDT 0.17 and the HyperTransport 1.03 styles of fabric
initialization. There is a new flag, ldt_rev_017, that can be
included in the value of the PCI_OPTIONS environment variable. If
that flag is set, the 0.17 initialization procedure will be used.
Otherwise, the 1.03 procedure is followed. There is also a new
configuration option, CFG_LDT_REV_017, that sets the default value
of the ldt_rev_017 attribute. This option is specified in the
Makefile.
You must choose the initialization procedure properly, either by
default or by making a permanent assignment to PCI_OPTIONS, to
match the type of devices present on your HyperTransport chain.
If the choice is incorrect, the system can fail to initialize the
Hypertransport links and may hang at startup while attempting to
do so.
If set to '1', fabric initialization will be appropriate for
the HyperTransport 0.17 specification. The SP1011 HT->PCI bridge
can only operate in 0.17 mode, and standard Makefiles for boards
with SP1011s make this the default.
If set to '0', fabric initalization will be approprate for the 1.01
(and later) specification. The PLX 7520 HT->PCI-X bridge can only
operate in this mode. Standard Makefiles for boards with only HT
expansion connectors make this the default.
Either setting is acceptable when communicating with another
BCM1250 in a double-hosted chain, but both ends must agree.
* CFE now supports initialization of HyperTransport fabrics that
include the PLX 7520 HT->PCI-X chip. For link speeds other than
200 MHz, the 1.03 initialization option (above) must be used.
* The BCM1250CPCI port had incorrectly programmed the GPIO interrupt
mask register, preventing Linux from being able to use the on-board
IDE interface. This has been fixed.
* Some 64-bit/32-bit issues have been fixed in the "flashop engine"
that is used for programming flash devices. In particular, 64-bit
ops are used when manipulating addresses in 64-bit mode.
* The default values for the drive strengths and skews for the
DRAM controllers have been modified to be more reasonable for
currently shipping parts.
* The workarounds for known bugs in the BCM1125's memory controller
have been made a run-time check.
* The command line parser has been substantially rewritten to be more
shell-like in its expansion of environment variables. In particular
you can now set an environment variable to include multiple CFE
commands.
* The command line parser supports "aliases" - if the first word of
a command line matches an environment variable, it will be expanded
even if there is no preceding dollar sign. For example, you can
now do:
CFE> setenv start "ifconfig eth0 -auto; boot -elf server:myprogram"
and later just type "start" to start the program.
PLEASE NOTE: If you define an alias that has the same name as a built-in
command, you will need to quote the command to prevent the expansion
from occuring:
CFE> setenv e "ifconfig eth0 -auto"
CFE> e (this will run the "ifconfig" command)
CFE> 'e' (this will run the "edit memory" command)
* By enabling an option, CFG_URLS in your bsp_config.h file, CFE can
now process file names in URL syntax. This option defaults to OFF
to use the current syntax. When enabled, you can use boot files
in the following format:
CFE> boot -elf tftp://servername/path/to/filename
CFE> boot -elf fat://ide0.0/path/to/filename
CFE> boot -elf rawfs://flash0.os
This syntax works with the "boot", "load", and "flash" commands.
* You can now boot from an HTTP server by enabling "CFG_HTTPFS" in
your bsp_config.h file. This also requires TCP support (define CFG_TCP).
CFE> boot -elf -http servername:path/to/binary (old syntax)
CFE> boot -elf http://servername/path/to/binary (URL syntax)
------------------------------------------------------------------------------
CHANGES SINCE PREVIOUS VERSION (1.0.34)
------------------------------------------------------------------------------
* CFE now builds using the "sb1-elf" toolchain by default.
It will still build using mips64-sb1sim, but it is recommended
that you switch to the new toolchain.
* The BCM1125E port now uses the SPD EEPROM to store memory
parameters. If the EEPROM is not programmed, a default memory
table will be used.
* For versions of the 1250 and 1125 that are step A0 (anything but
pass1) or newer, PCI code now configures HyperTransport
interrupts for level triggered mode. For older versions,
configuration is for edge triggered mode as before.
* If CFE is used to load an operating system such as Linux that
relies on CFE's configuration of interrupts, be sure to use only
versions of that operating system that can deal with level
triggered HyperTransport interrupts (must issue EOIs).
* Exceptions now display the CAUSE field symbolically, displaying
the exception name along with the CAUSE register value.
* A number of fixes have been made to the SB1250 include files,
including the addition of BCM1125 DMA features and some additional
constants for the drive strength registers.
* Some additional test code has been placed in the firmware's
ethernet driver for testing FIFO mode.
* The memory initialization routines have had an off-by-one
error corrected that can cause the memory to be run slower
than the rated maximum.