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CPU.abl
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MODULE CPU
TITLE 'Caltech10 CPU'
" Description: This is the fully connected Caltech10 CPU, implementing the full
" instruction set, with the exception of the Call and RTS
" which require a FSM to implement. The Caltech10 is composed Of
" instantiations of a DAU, a PAU, an ALU, and a CU, as well as
" the logic which connects them together.
"
" Inputs: ProgramDB[15..0] - the 16-bit program data bus
" Reset - system reset signal
" Clock - system clock
"
" I/O: DataDB[7..0] - the 8-bit data data bus
"
" Outputs: ProgramAB[12..0] - the 13-bit program address bus
" DataAB[7..0] - the 8-bit data address bus
" RD - read signal for the data data bus
" WR - write signal for the data data bus
" IO - memory (0) or I/O (1) is being accessed
"
" Status Outputs: Accum[7..0] - the 8-bit accumulator
" Flags[7..0] - the 8-bit flag register
" XReg[7..0] - the 8-bit X register
" SReg[7..0] - the 8-bit S register
" Revision History:
" 02/15/18 Glen George Initial Revision
" 01/05/21 Glen George Updated comments
" 03/09/23 Edward Speer Instantiate modules
" 03/10/23 Edward Speer Add muxes on DataDB and ALU
" 03/10/23 Edward Speer Change resets to active high
" 03/11/23 Edward Speer Add PAU Offset source mux
" 03/11/23 Edward Speer Update Comments
" 03/15/23 Edward Speer Add PC on PAU offset mux
" Pin/Signal Declarations
" Inputs
ProgramDB15..ProgramDB0 pin; "input 16-bit instruction data bus
Reset pin; "input system reset signal
Clock pin; "input system clock
" I/O
DataDB7..DataDB0 pin; "I/O 8-bit Data data bus
" Outputs
ProgramAB12..ProgramAB0 pin; "output the 13-bit Program address bus
DataAB7..DataAB0 pin; "output the 8-bit Data address bus
RD pin; "output read signal for the Data data bus
WR pin; "output write signal for the Data data bus
IO pin; "output accessing memory (0) or I/O (1)
" Debugging/Status Outputs
Accum7..Accum0 pin; "the 8-bit accumulator
Flags7..Flags0 pin; "the flags (8 bits)
XReg7..XReg0 pin; "the 8-bit X register
SReg7..SReg0 pin; "the 8-bit S register
" Internal signals
DBMOut7..DBMOut0 node ISTYPE 'COM'; "Data Databus mux output
ALUMuxIn7..ALUMuxIn0 node ISTYPE 'COM'; "ALU input mux output
PAUMuxIn7..PAUMuxIn0 node ISTYPE 'COM'; "PAU Input Mux output
LOffset12..LOffset0 node ISTYPE 'COM'; "13 bit offset from instruction
PC12..PC0 node ISTYPE 'COM'; "13 bit program counter out from PAU
" declare the used modules
"PAU
ProgramAccess INTERFACE (Offset7..Offset0, Direct12..Direct0,
MuxS2..MuxS0, Load,
Reset, Clock
-> ProgAddr12..ProgAddr0, PC12..PC0);
"ALU
ALU INTERFACE (Data7..Data0,
ZAdd, F3..F0, SZHold, CVHold, CinA, CinB, Popf, AccHold, InvertC,
Reset, Clock
-> Accum7..Accum0, Flags7..Flags0);
"DAU
DataAccess INTERFACE (Accum7..Accum0, Offset7..Offset0,
AS1..AS0, PrePostSelect, OffS,
IDS1..IDS0, UpdateX, UpdateS,
Reset, Clock
-> DataAddr7..DataAddr0, XReg7..XReg0, SReg7..SReg0);
"CU
CU INTERFACE (Flags7..Flags0, ProgramDB15..ProgramDB0, Reset, Clock
-> MuxS2..MuxS0, Load, AS1..AS0, PrePostSelect, OffS,
IDS1..IDS0, UpdateX, UpdateS, ZAdd, F3..F0, SZHold, CVHold, CinA,
CinB, Popf, AccHold, InvertC, PAUOffS, DDBS1..DDBS0, RD, WR, IO,
OffOut12..OffOut0, ALUS1..ALUS0);
" create instances of the modules
PAUnit FUNCTIONAL_BLOCK ProgramAccess;
DAUnit FUNCTIONAL_BLOCK DataAccess;
ALUnit FUNCTIONAL_BLOCK ALU;
Control FUNCTIONAL_BLOCK CU;
" Busses
DBMOut = [DBMOut7..DBMOut0]; "Data Databus mux output
Accum = [Accum7..Accum0]; "8 bit system accumulator
Flags = [Flags7..Flags0]; "ALU Status Register
ProgramAB = [ProgramAB12..ProgramAB0]; "13-bit Program address bus
ProgramDB = [ProgramDB15..ProgramDB0]; "16-bit Program data bus
DataAB = [DataAB7..DataAB0]; "8-bit Data address bus
DataDB = [DataDB7..DataDB0]; "8-bit Data data bus
LOffset = [LOffset12..LOffset0]; "13 bit address from instruction
PC = [PC12..PC0]; "13 bit program counter out from PAU
ALUMuxIn = [ALUMuxIn7..ALUMuxIn0]; "ALU Input mux output
PAUMuxIn = [PAUMuxIn7..PAUMuxIn0]; "PAU offset soure mux output
EQUATIONS
"Control Unit inputs
Control.[Flags7..Flags0] = [Flags7..Flags0];
Control.[ProgramDB15..ProgramDB0] = [ProgramDB15..ProgramDB0];
Control.Reset = Reset;
Control.Clock = Clock;
"Control Unit Outputs
RD = Control.RD & !Clock; "RD/WR signals can't occur on high clock
WR = Control.WR & !Clock;
IO = Control.IO;
LOffset = Control.[OffOut12..OffOut0];
"Offset mux for PAU
PAUMuxIn = (Control.PAUOffS & DataDB) # "1 -> DataDB
(!Control.PAUOffS & Control.[OffOut7..OffOut0]); "0 -> 8 bit instruction address
" PAU Inputs
PAUnit.[Offset7..Offset0] = PAUMuxIn;
PAUnit.[Direct12..Direct0] = LOffset;
PAUnit.[MuxS2..MuxS0] = Control.[MuxS2..MuxS0];
PAUnit.Load = Control.Load;
PAUnit.Reset = Reset;
PAUnit.Clock = Clock;
"PAU Outputs
" ProgramAB = PAUnit.[ProgAddr12..ProgAddr0];
ProgramAB = PAUnit.[PC12..PC0];
PC = PAUnit.[PC12..PC0];
"DAU Inputs
DAUnit.[Accum7..Accum0] = Accum;
DAUnit.[Offset7..Offset0] = Control.[OffOut7..OffOut0];
DAUnit.[AS1..AS0] = Control.[AS1..AS0];
DAUnit.PrePostSelect = Control.PrePostSelect;
DAUnit.OffS = Control.OffS;
DAUnit.[IDS1..IDS0] = Control.[IDS1..IDS0];
DAUnit.UpdateX = Control.UpdateX;
DAUnit.UpdateS = Control.UpdateS;
DAUnit.Reset = !Reset;
DAUnit.Clock = Clock;
[XReg7..XReg0] = DAUnit.[XReg7..XReg0];
[SReg7..SReg0] = DAUnit.[SReg7..SReg0];
"DAU Outputs
DataAB = DAUnit.[DataAddr7..DataAddr0];
"ALU Input mux
ALUMuxIn = (!Control.ALUS1 & !Control.ALUS0 & DataDB) # " 00 -> Data DataBus
(!Control.ALUS1 & Control.ALUS0 & Control.[OffOut7..OffOut0]) # " 01 -> Offset
(Control.ALUS1 & !Control.ALUS0 & " 10 -> X
DAUnit.[XReg7..XReg0]) #
(Control.ALUS1 & Control.ALUS0 & " 11 -> S
DAUnit.[SReg7..SReg0]);
" ALU Inputs
ALUnit.[Data7..Data0] = ALUMuxIn;
ALUnit.ZAdd = Control.ZAdd;
ALUnit.[F3..F0] = Control.[F3..F0];
ALUnit.SZHold = Control.SZHold;
ALUnit.CVHold = Control.CVHold;
ALUnit.CinA = Control.CinA;
ALUnit.CinB = Control.CinB;
ALUnit.Popf = Control.Popf;
ALUnit.AccHold = Control.AccHold;
ALUnit.InvertC = Control.InvertC;
ALUnit.Reset = !Reset;
ALUnit.Clock = Clock;
" ALU Outputs
Accum = ALUnit.[Accum7..Accum0];
Flags = ALUnit.[Flags7..Flags0];
DBMOut = (!Control.DDBS1 & !Control.DDBS0 & Accum) # "00 -> Accumulator
(!Control.DDBS1 & Control.DDBS0 & "01 -> Flags (Flag6, Flag4 always low)
[ALUnit.Flags7, 0, ALUnit.Flags5, 0, ALUnit.Flags3..ALUnit.Flags0]) #
(Control.DDBS1 & !Control.DDBS0 & [0, 0, 0, PC12..PC8]) # "10 -> PC12..8
(Control.DDBS1 & Control.DDBS0 & [PC7..PC0]); "11 -> PC7..0
DataDB = DBMOut;
" output enables
" Data data bus is enabled when writing
DataDB.OE = Control.WR;
" most signals are always enabled
ProgramAB.OE = ^h1FFF;
DataAB.OE = ^hFF;
RD.OE = 1;
WR.OE = 1;
IO.OE = 1;
[Accum7..Accum0].OE = ^hFF;
[Flags7..Flags0].OE = ^hFF;
[XReg7..XReg0].OE = ^hFF;
[SReg7..SReg0].OE = ^hFF;
END CPU