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Mnemonico_ANDWF.asm
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Mnemonico_ANDWF.asm
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#INCLUDE <P18F4550.INC>
; CONFIG1L
CONFIG PLLDIV = 1 ; PLL Prescaler Selection bits (No prescale (4 MHz oscillator input drives PLL directly))
CONFIG CPUDIV = OSC1_PLL2 ; System Clock Postscaler Selection bits ([Primary Oscillator Src: /1][96 MHz PLL Src: /2])
CONFIG USBDIV = 1 ; USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1) (USB clock source comes directly from the primary oscillator block with no postscale)
; CONFIG1H
CONFIG FOSC = HS ; Oscillator Selection bits (HS oscillator (HS))
CONFIG FCMEN = OFF ; Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
CONFIG IESO = OFF ; Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
; CONFIG2L
CONFIG PWRT = OFF ; Power-up Timer Enable bit (PWRT disabled)
CONFIG BOR = ON ; Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
CONFIG BORV = 3 ; Brown-out Reset Voltage bits (Minimum setting 2.05V)
CONFIG VREGEN = OFF ; USB Voltage Regulator Enable bit (USB voltage regulator disabled)
; CONFIG2H
CONFIG WDT = OFF ; Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
CONFIG WDTPS = 32768 ; Watchdog Timer Postscale Select bits (1:32768)
; CONFIG3H
CONFIG CCP2MX = OFF ; CCP2 MUX bit (CCP2 input/output is multiplexed with RB3)
CONFIG PBADEN = OFF ; PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)
CONFIG LPT1OSC = OFF ; Low-Power Timer 1 Oscillator Enable bit (Timer1 configured for higher power operation)
CONFIG MCLRE = ON ; MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)
;***************** USO DE LA MNEMONICO ANDWF F, D, A ****************************
;El empleo de este mnemonico es bastante simple pues realiza la operacion de AND entre el registro W y un FILE F
;Que puede ser un operando, dato o registro de trabajo
;********** EJEMPLO ****************
CBLOCK 0x00
ENDC
ORG 0X000
GOTO MAIN
ORG 0X008
GOTO INT_ALTA_PRIOR
ORG 0X018
GOTO INT_BAJA_PRIOR
ORG 0X020
MAIN:
CLRF TRISD ; Movemos el dato 0x00 hacia el registro TRISD para poner como salida a puerto D
GOTO START ; Vamos a la direccion con el alias de START
START:
CLRF LATD; Limpiamos el registro W
MOVLW B'01010101';Movemos el dato literal binario hacia el registro de trabajo W
MOVWF 0X10;Llevamos el dato hacía la posición 0x10 de la SRAM
MOVLW B'10101010'; Movemos el dato literal binario hacia el registro W
ANDWF 0X10, W;Hacemos un and entre W y el dato de la pos 0x10 de la SRAM
MOVWF LATD ; LATD = W AND pos 0x10
;En este caos en particular el resultado va a ser 0x00
;Explicación: 01010101 AND 10101010 = 00000000
GOTO START; Retornamos a la direccion de memoria con el nombre START
ORG 0X0C0
INT_ALTA_PRIOR:
RETFIE
ORG 0X0F0
INT_BAJA_PRIOR:
RETFIE
END