diff --git a/Config/freertos-config/FreeRTOSConfig.h b/Config/freertos-config/FreeRTOSConfig.h
index 1388a44d..90fd5dfa 100644
--- a/Config/freertos-config/FreeRTOSConfig.h
+++ b/Config/freertos-config/FreeRTOSConfig.h
@@ -57,10 +57,26 @@ extern uint32_t SystemCoreClock;
 #define configENABLE_TRUSTZONE              0
 #define configRUN_FREERTOS_SECURE_ONLY      0
 
-/* somehow 100 tick per second gives similar timing (~85%) as 1000 did on the FPGA, so with this 1 ms to 1 tick can be */
-/* kept... */
-#define configTICK_RATE_HZ    ( ( uint32_t ) 100 ) /* Scheduler polling rate of 1000 Hz */
-
+/* From the "Fast Models Reference Guide" (https://developer.arm.com/documentation/100964/1123/About-the-models),
+ * "Programmer's View (PV) models of processors and devices work at a level
+ * where functional behavior is equivalent to what a programmer would see using
+ * the hardware.
+ *
+ * They sacrifice timing accuracy to achieve fast simulation execution speeds:
+ * you can use the PV models for confirming software functionality, but you
+ * must not rely on the accuracy of cycle counts, low-level component
+ * interactions, or other hardware-specific behavior."
+ *
+ * As described above, FVPs sacrifice timing accuracy to achieve fast
+ * simulation execution speeds. Therefore, we need this work around of setting
+ * `configTICK_RATE_HZ` to `100` to simulate scheduler polling rate of
+ * `1000 Hz` or 1 tick per second.
+ *
+ * In addition, the macro `pdMS_TO_TICKS` is defined here to match the 1 tick
+ * per second instead of using the macro defined in
+ * `FreeRTOS-kernel/include/projdefs.h`
+ */
+#define configTICK_RATE_HZ                  ( ( uint32_t ) 100 )
 #define pdMS_TO_TICKS( xTimeInMs )    ( ( TickType_t ) xTimeInMs )
 #define TICKS_TO_pdMS( xTicks )       ( ( uint32_t ) xTicks )