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Simplify asm in some tests (#631)
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@Dentosal
Dentosal authored Nov 8, 2023
1 parent c419c9b commit 264ca3c
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Showing 3 changed files with 47 additions and 120 deletions.
109 changes: 28 additions & 81 deletions fuel-vm/src/tests/blockchain.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -509,9 +509,8 @@ fn ldc__load_len_of_target_contract<'a>(
let index = i as Immediate12;
let value = *byte as Immediate12;
load_contract.extend([
op::xor(reg_a, reg_a, reg_a), // r[a] := 0
op::ori(reg_a, reg_a, value), // r[a] := r[a] | value
op::sb(RegId::HP, reg_a, index), // m[$hp+index] := r[a] (=value)
op::movi(reg_a, value.try_into().unwrap()), // r[a] := r[a] | value
op::sb(RegId::HP, reg_a, index), // m[$hp+index] := r[a] (=value)
]);
}

Expand Down Expand Up @@ -911,9 +910,7 @@ fn code_copy_a_gt_vmmax_sub_d() {

// test memory offset above reg_hp value
let code_copy = vec![
op::xor(reg_a, reg_a, reg_a),
op::ori(reg_a, reg_a, 1),
op::slli(reg_a, reg_a, MAX_MEM_SHL),
op::slli(reg_a, RegId::ONE, MAX_MEM_SHL),
op::addi(reg_a, reg_a, 1),
op::ccp(reg_a, RegId::ZERO, RegId::ZERO, RegId::ZERO),
];
Expand All @@ -926,8 +923,7 @@ fn code_copy_b_plus_32_overflow() {
let reg_a = 0x20;
// test overflow add
let code_copy = vec![
op::xor(reg_a, reg_a, reg_a),
op::not(reg_a, reg_a),
op::not(reg_a, RegId::ZERO),
op::ccp(RegId::ZERO, reg_a, RegId::ZERO, RegId::ZERO),
];

Expand All @@ -939,9 +935,7 @@ fn code_copy_b_gt_vm_max_ram() {
let reg_a = 0x20;
// test overflow add
let code_copy = vec![
op::xor(reg_a, reg_a, reg_a),
op::ori(reg_a, reg_a, 1),
op::slli(reg_a, reg_a, MAX_MEM_SHL),
op::slli(reg_a, RegId::ONE, MAX_MEM_SHL),
op::subi(reg_a, reg_a, 31),
op::ccp(RegId::ZERO, reg_a, RegId::ZERO, RegId::ZERO),
];
Expand All @@ -954,9 +948,7 @@ fn code_copy_c_gt_vm_max_ram() {
let reg_a = 0x20;
// test overflow add
let code_copy = vec![
op::xor(reg_a, reg_a, reg_a),
op::ori(reg_a, reg_a, 1),
op::slli(reg_a, reg_a, MAX_MEM_SHL),
op::slli(reg_a, RegId::ONE, MAX_MEM_SHL),
op::addi(reg_a, reg_a, 1),
op::ccp(RegId::ZERO, RegId::ZERO, reg_a, RegId::ZERO),
];
Expand All @@ -970,11 +962,7 @@ fn code_root_a_plus_32_overflow() {
let reg_a = 0x20;

// cover contract_id_end beyond max ram
let code_root = vec![
op::xor(reg_a, reg_a, reg_a),
op::not(reg_a, reg_a),
op::croo(reg_a, RegId::ZERO),
];
let code_root = vec![op::not(reg_a, RegId::ZERO), op::croo(reg_a, RegId::ZERO)];

check_expected_reason_for_instructions(code_root, MemoryOverflow);
}
Expand All @@ -985,11 +973,7 @@ fn code_root_b_plus_32_overflow() {
let reg_a = 0x20;

// cover contract_id_end beyond max ram
let code_root = vec![
op::xor(reg_a, reg_a, reg_a),
op::not(reg_a, reg_a),
op::croo(RegId::ZERO, reg_a),
];
let code_root = vec![op::not(reg_a, RegId::ZERO), op::croo(RegId::ZERO, reg_a)];

check_expected_reason_for_instructions(code_root, MemoryOverflow);
}
Expand All @@ -1001,9 +985,7 @@ fn code_root_a_over_max_ram() {

// cover contract_id_end beyond max ram
let code_root = vec![
op::xor(reg_a, reg_a, reg_a),
op::ori(reg_a, reg_a, 1),
op::slli(reg_a, reg_a, MAX_MEM_SHL),
op::slli(reg_a, RegId::ONE, MAX_MEM_SHL),
op::subi(reg_a, reg_a, 31 as Immediate12),
op::croo(reg_a, RegId::ZERO),
];
Expand All @@ -1018,9 +1000,7 @@ fn code_root_b_over_max_ram() {

// cover contract_id_end beyond max ram
let code_root = vec![
op::xor(reg_a, reg_a, reg_a),
op::ori(reg_a, reg_a, 1),
op::slli(reg_a, reg_a, MAX_MEM_SHL),
op::slli(reg_a, RegId::ONE, MAX_MEM_SHL),
op::subi(reg_a, reg_a, 31 as Immediate12),
op::croo(RegId::ZERO, reg_a),
];
Expand All @@ -1034,11 +1014,7 @@ fn code_size_b_plus_32_overflow() {
let reg_a = 0x20;

// cover contract_id_end beyond max ram
let code_root = vec![
op::xor(reg_a, reg_a, reg_a),
op::not(reg_a, reg_a),
op::csiz(reg_a, reg_a),
];
let code_root = vec![op::not(reg_a, RegId::ZERO), op::csiz(reg_a, reg_a)];

check_expected_reason_for_instructions(code_root, MemoryOverflow);
}
Expand All @@ -1050,9 +1026,7 @@ fn code_size_b_over_max_ram() {

// cover contract_id_end beyond max ram
let code_root = vec![
op::xor(reg_a, reg_a, reg_a),
op::ori(reg_a, reg_a, 1),
op::slli(reg_a, reg_a, MAX_MEM_SHL),
op::slli(reg_a, RegId::ONE, MAX_MEM_SHL),
op::subi(reg_a, reg_a, 31 as Immediate12),
op::csiz(reg_a, reg_a),
];
Expand Down Expand Up @@ -1276,8 +1250,7 @@ fn state_r_word_b_plus_32_over() {

// cover contract_id_end beyond max ram
let state_read_word = vec![
op::xor(reg_a, reg_a, reg_a),
op::not(reg_a, reg_a),
op::not(reg_a, RegId::ZERO),
op::subi(reg_a, reg_a, 31 as Immediate12),
op::srw(reg_a, SET_STATUS_REG, reg_a),
];
Expand All @@ -1292,9 +1265,7 @@ fn state_r_word_b_over_max_ram() {

// cover contract_id_end beyond max ram
let state_read_word = vec![
op::xor(reg_a, reg_a, reg_a),
op::ori(reg_a, reg_a, 1),
op::slli(reg_a, reg_a, MAX_MEM_SHL),
op::slli(reg_a, RegId::ONE, MAX_MEM_SHL),
op::subi(reg_a, reg_a, 31 as Immediate12),
op::srw(reg_a, SET_STATUS_REG, reg_a),
];
Expand All @@ -1309,8 +1280,7 @@ fn state_r_qword_a_plus_32_over() {

// cover contract_id_end beyond max ram
let state_read_qword = vec![
op::xor(reg_a, reg_a, reg_a),
op::not(reg_a, reg_a),
op::not(reg_a, RegId::ZERO),
op::subi(reg_a, reg_a, 31 as Immediate12),
op::srwq(reg_a, SET_STATUS_REG, RegId::ZERO, RegId::ONE),
];
Expand All @@ -1327,8 +1297,7 @@ fn state_r_qword_c_plus_32_over() {
let state_read_qword = vec![
op::movi(0x11, 100),
op::aloc(0x11),
op::xor(reg_a, reg_a, reg_a),
op::not(reg_a, reg_a),
op::not(reg_a, RegId::ZERO),
op::subi(reg_a, reg_a, 31 as Immediate12),
op::srwq(RegId::HP, SET_STATUS_REG, reg_a, RegId::ONE),
];
Expand All @@ -1343,9 +1312,7 @@ fn state_r_qword_a_over_max_ram() {

// cover contract_id_end beyond max ram
let state_read_qword = vec![
op::xor(reg_a, reg_a, reg_a),
op::ori(reg_a, reg_a, 1),
op::slli(reg_a, reg_a, MAX_MEM_SHL),
op::slli(reg_a, RegId::ONE, MAX_MEM_SHL),
op::subi(reg_a, reg_a, 31 as Immediate12),
op::srwq(reg_a, SET_STATUS_REG, RegId::ZERO, RegId::ONE),
];
Expand All @@ -1363,9 +1330,7 @@ fn state_r_qword_c_over_max_ram() {
op::movi(0x11, 100),
op::aloc(0x11),
op::move_(0x31, RegId::HP),
op::xor(reg_a, reg_a, reg_a),
op::ori(reg_a, reg_a, 1),
op::slli(reg_a, reg_a, MAX_MEM_SHL),
op::slli(reg_a, RegId::ONE, MAX_MEM_SHL),
op::subi(reg_a, reg_a, 31 as Immediate12),
op::srwq(0x31, SET_STATUS_REG, reg_a, RegId::ONE),
];
Expand All @@ -1380,8 +1345,7 @@ fn state_w_word_a_plus_32_over() {

// cover contract_id_end beyond max ram
let state_write_word = vec![
op::xor(reg_a, reg_a, reg_a),
op::not(reg_a, reg_a),
op::not(reg_a, RegId::ZERO),
op::subi(reg_a, reg_a, 31 as Immediate12),
op::sww(reg_a, SET_STATUS_REG, RegId::ZERO),
];
Expand All @@ -1396,9 +1360,7 @@ fn state_w_word_a_over_max_ram() {

// cover contract_id_end beyond max ram
let state_write_word = vec![
op::xor(reg_a, reg_a, reg_a),
op::ori(reg_a, reg_a, 1),
op::slli(reg_a, reg_a, MAX_MEM_SHL),
op::slli(reg_a, RegId::ONE, MAX_MEM_SHL),
op::subi(reg_a, reg_a, 31 as Immediate12),
op::sww(reg_a, SET_STATUS_REG, RegId::ZERO),
];
Expand All @@ -1413,8 +1375,7 @@ fn state_w_qword_a_plus_32_over() {

// cover contract_id_end beyond max ram
let state_write_qword = vec![
op::xor(reg_a, reg_a, reg_a),
op::not(reg_a, reg_a),
op::not(reg_a, RegId::ZERO),
op::subi(reg_a, reg_a, 31 as Immediate12),
op::swwq(reg_a, SET_STATUS_REG, RegId::ZERO, RegId::ONE),
];
Expand All @@ -1429,8 +1390,7 @@ fn state_w_qword_b_plus_32_over() {

// cover contract_id_end beyond max ram
let state_write_qword = vec![
op::xor(reg_a, reg_a, reg_a),
op::not(reg_a, reg_a),
op::not(reg_a, RegId::ZERO),
op::subi(reg_a, reg_a, 31 as Immediate12),
op::swwq(RegId::ZERO, SET_STATUS_REG, reg_a, RegId::ONE),
];
Expand All @@ -1445,9 +1405,7 @@ fn state_w_qword_a_over_max_ram() {

// cover contract_id_end beyond max ram
let state_write_qword = vec![
op::xor(reg_a, reg_a, reg_a),
op::ori(reg_a, reg_a, 1),
op::slli(reg_a, reg_a, MAX_MEM_SHL),
op::slli(reg_a, RegId::ONE, MAX_MEM_SHL),
op::subi(reg_a, reg_a, 31),
op::swwq(reg_a, SET_STATUS_REG, RegId::ZERO, RegId::ONE),
];
Expand All @@ -1462,9 +1420,7 @@ fn state_w_qword_b_over_max_ram() {

// cover contract_id_end beyond max ram
let state_write_qword = vec![
op::xor(reg_a, reg_a, reg_a),
op::ori(reg_a, reg_a, 1),
op::slli(reg_a, reg_a, MAX_MEM_SHL),
op::slli(reg_a, RegId::ONE, MAX_MEM_SHL),
op::subi(reg_a, reg_a, 31),
op::swwq(RegId::ZERO, SET_STATUS_REG, reg_a, RegId::ONE),
];
Expand All @@ -1491,15 +1447,11 @@ fn message_output_b_gt_msg_len() {
fn message_output_a_b_over() {
// Then deploy another contract that attempts to read the first one
let reg_a = 0x20;
let reg_b = 0x21;

// cover contract_id_end beyond max ram
let message_output = vec![
op::xor(reg_a, reg_a, reg_a), // r[a] = 0
op::xor(reg_b, reg_b, reg_b), // r[b] = 0
op::not(reg_a, reg_a), // r[a] = MAX
op::addi(reg_b, reg_b, 1), // r[b] = 1
op::smo(reg_a, reg_b, RegId::ZERO, RegId::ZERO),
op::not(reg_a, RegId::ZERO), // r[a] = MAX
op::smo(reg_a, RegId::ONE, RegId::ZERO, RegId::ZERO),
];

check_expected_reason_for_instructions(message_output, MemoryOverflow);
Expand All @@ -1509,16 +1461,11 @@ fn message_output_a_b_over() {
fn message_output_a_b_gt_max_mem() {
// Then deploy another contract that attempts to read the first one
let reg_a = 0x20;
let reg_b = 0x21;

// cover contract_id_end beyond max ram
let message_output = vec![
op::xor(reg_a, reg_a, reg_a),
op::xor(reg_b, reg_b, reg_b),
op::ori(reg_a, reg_a, 1),
op::slli(reg_a, reg_a, MAX_MEM_SHL),
op::addi(reg_b, reg_b, 1),
op::smo(reg_a, reg_b, RegId::ZERO, RegId::ZERO),
op::slli(reg_a, RegId::ONE, MAX_MEM_SHL),
op::smo(reg_a, RegId::ONE, RegId::ZERO, RegId::ZERO),
];

check_expected_reason_for_instructions(message_output, MemoryOverflow);
Expand Down
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