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VLSI

Playing with logic gates, find my approach to make decison making cirucits.

  1. 2 to 1 mux
  2. 3 to 8
  3. 4 to 1 MUX
  4. D Flip Flop
  5. Full Adder using 3 to 8
  6. Full Adder using two half adders
  7. Full Adder
  8. 8_to_1_using_4_to_1_and_2_to_1
  9. AND
  10. AND_using_NAND
  11. NAND
  12. NOR
  13. NOT
  14. NOT_using_NAND
  15. NOT_using_NOR
  16. OR
  17. OR_using_NAND
  18. OR_using_NOR
  19. XNOR
  20. XNOR_using_NOR
  21. XOR
  22. XOR_using_NAND
  23. Full_Adder
  24. Full_Adder_using_two_half_adder
  25. Full_Substractor
  26. Half_Adder
  27. Half_Adder_using_NAND
  28. Half_Substractor
  29. Half_Substractor_using_NAND
  30. 3_to_8_Decoder
  31. Full_adder_using_3_to_8_decoder
  32. 2_to_1_MUX
  33. 4_to_1_MUX
  34. Half Adder
  35. Half Substractor using Nand
  36. Half Substractor
  37. J K Flip Flop
  38. S R Flip Flop
  39. Sine_Discrete
  40. T Flip Flop
  41. d Flip flop
  42. fcfs
  43. preemetive_sjfs
  44. preemitive_priority_scheduling
  45. priority_scheduling
  46. reconstructed sine
  47. sjfs
  48. thread