-
Notifications
You must be signed in to change notification settings - Fork 0
/
TB2.vhd
80 lines (62 loc) · 2.14 KB
/
TB2.vhd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use std.textio.all;
ENTITY TB2 IS
END TB2;
ARCHITECTURE behavior OF TB2 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Compressor
PORT(
CLK : in std_logic;
Data : IN string(1 to 64);
Compressed : INOUT string(1 to 192)
);
END COMPONENT;
COMPONENT FileWriter
PORT(
WriteData: in String (1 to 192)
);
END COMPONENT;
COMPONENT FileReader
PORT(
ReadData : OUT String(1 to 64)
);
END COMPONENT;
-------------------------------------------------------------------------
signal writeData : String(1 to 192):= " ";
signal ReadData : String(1 to 64):= " ";
--Inputs
signal Data : string(1 to 64) := " ";
--BiDirs
signal Compressed : string(1 to 192) := " ";
signal clk : std_logic := '1';
constant clk_period : time := 2000 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut1: Compressor PORT MAP (
clk => clk,
Data => Data,
Compressed => Compressed
);
uut2: FileReader PORT MAP (
ReadData => ReadData
);
uut3: FileWriter PORT MAP (
WriteData => WriteData
);
clk_proc: process
begin
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
end process;
stim_proc: process
begin
wait for 300 ns;
Data <= ReadData; --&" ";
wait for 200000 ns;
WriteData <= Compressed;
wait;
end process;
END;