Synchronous Reset Error

[11522514]

Hi, I'm just starting to test out chiffre and I was trying to setup the sample LeChiffre configuration. I ended up having to change the patch file, but now I am getting this error and I don't have an idea how to fix it.
Exception in thread "main" java.lang.AssertionError: assertion failed: Error! Synchronous reset should have been removed! UIntType(IntWidth(1)) AsyncResetType
at scala.Predef$.assert(Predef.scala:219)
at firrtl.VerilogEmitter$VerilogRender.regUpdate(Emitter.scala:494)
at firrtl.VerilogEmitter$VerilogRender.build_streams(Emitter.scala:647)
at firrtl.VerilogEmitter$VerilogRender.$anonfun$build_streams$1(Emitter.scala:638)
at firrtl.VerilogEmitter$VerilogRender.$anonfun$build_streams$1$adapted(Emitter.scala:638)
at scala.collection.mutable.ResizableArray.foreach(ResizableArray.scala:58)
at scala.collection.mutable.ResizableArray.foreach$(ResizableArray.scala:51)
at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:47)
at firrtl.ir.Block.foreachStmt(IR.scala:363)
at firrtl.traversals.Foreachers$StmtForMagnet$$anon$1.foreach(Foreachers.scala:18)
at firrtl.traversals.Foreachers$StmtForeach$.foreach$extension(Foreachers.scala:35)
at firrtl.VerilogEmitter$VerilogRender.build_streams(Emitter.scala:638)
at firrtl.VerilogEmitter$VerilogRender.$anonfun$build_streams$1(Emitter.scala:638)
at firrtl.VerilogEmitter$VerilogRender.$anonfun$build_streams$1$adapted(Emitter.scala:638)
at scala.collection.mutable.ResizableArray.foreach(ResizableArray.scala:58)
at scala.collection.mutable.ResizableArray.foreach$(ResizableArray.scala:51)
at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:47)
at firrtl.ir.Block.foreachStmt(IR.scala:363)
at firrtl.traversals.Foreachers$StmtForMagnet$$anon$1.foreach(Foreachers.scala:18)
at firrtl.traversals.Foreachers$StmtForeach$.foreach$extension(Foreachers.scala:35)
at firrtl.VerilogEmitter$VerilogRender.build_streams(Emitter.scala:638)
at firrtl.VerilogEmitter$VerilogRender.$anonfun$build_streams$1(Emitter.scala:638)
at firrtl.VerilogEmitter$VerilogRender.$anonfun$build_streams$1$adapted(Emitter.scala:638)
at scala.collection.mutable.ResizableArray.foreach(ResizableArray.scala:58)
at scala.collection.mutable.ResizableArray.foreach$(ResizableArray.scala:51)
at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:47)
at firrtl.ir.Block.foreachStmt(IR.scala:363)
at firrtl.traversals.Foreachers$StmtForMagnet$$anon$1.foreach(Foreachers.scala:18)
at firrtl.traversals.Foreachers$StmtForeach$.foreach$extension(Foreachers.scala:35)
at firrtl.VerilogEmitter$VerilogRender.build_streams(Emitter.scala:638)
at firrtl.VerilogEmitter$VerilogRender.emit_verilog(Emitter.scala:838)
at firrtl.VerilogEmitter.$anonfun$emit$3(Emitter.scala:890)
at scala.collection.mutable.ResizableArray.foreach(ResizableArray.scala:58)
at scala.collection.mutable.ResizableArray.foreach$(ResizableArray.scala:51)
at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:47)
at firrtl.VerilogEmitter.emit(Emitter.scala:884)
at firrtl.VerilogEmitter.$anonfun$execute$3(Emitter.scala:899)
at scala.collection.TraversableLike.$anonfun$flatMap$1(TraversableLike.scala:240)
at scala.collection.immutable.List.foreach(List.scala:388)
at scala.collection.TraversableLike.flatMap(TraversableLike.scala:240)
at scala.collection.TraversableLike.flatMap$(TraversableLike.scala:237)
at scala.collection.immutable.List.flatMap(List.scala:351)
at firrtl.VerilogEmitter.execute(Emitter.scala:896)
at firrtl.Transform.$anonfun$runTransform$2(Compiler.scala:199)
at firrtl.Utils$.time(Utils.scala:186)
at firrtl.Transform.runTransform(Compiler.scala:199)
at firrtl.Compiler.$anonfun$compile$2(Compiler.scala:457)
at scala.collection.LinearSeqOptimized.foldLeft(LinearSeqOptimized.scala:122)
at scala.collection.LinearSeqOptimized.foldLeft$(LinearSeqOptimized.scala:118)
at scala.collection.immutable.List.foldLeft(List.scala:85)
at firrtl.Compiler.$anonfun$compile$1(Compiler.scala:455)
at firrtl.Utils$.time(Utils.scala:186)
at firrtl.Compiler.compile(Compiler.scala:455)
at firrtl.Compiler.compile$(Compiler.scala:451)
at firrtl.VerilogCompiler.compile(LoweringCompilers.scala:162)
at firrtl.Driver$.$anonfun$execute$1(Driver.scala:241)
at logger.Logger$.$anonfun$makeScope$2(Logger.scala:138)
at scala.util.DynamicVariable.withValue(DynamicVariable.scala:58)
at logger.Logger$.makeScope(Logger.scala:136)
at firrtl.Driver$.execute(Driver.scala:223)
at firrtl.Driver$.execute(Driver.scala:303)
at firrtl.Driver$.main(Driver.scala:319)
at firrtl.Driver.main(Driver.scala)

[seldridge]

Thanks for checking out Chiffre!

This is actually some bleeding edge stuff that you're hitting, i.e., the new Async Reset stuff. That error text seems to indicate that a synchronous reset was not converted to a UInt. My guess would be that the Chiffre transforms need to have reset inference run to clean things up after they add reset lines. I am, however, surprised to see that showing AsyncResetType in the message.

Regardless, it sounds like the Chiffre transforms need to be cleaned up to work with the async reset work.

I would likely need to dig into this, but I can also ping @jackkoenig. Time is always the issue on my end...

[jackkoenig]

Could be a bug in the Verilog Emitter's check as well, let me know what you find

[11522514]

I don't quite understand the interaction between the firrtl and chiffre libraries or the design parameters I can set. If possible I wouldn't mind setting all resets to be synchronous to avoid this.

[11522514]

The chiffre transform finished this before emitting the error
Time: 871.1 ms
Form: UnknownForm
======== Finished Transform VerilogRename ========

======== Starting Transform VerilogPrep$ ========

Time: 83.8 ms
Form: UnknownForm
======== Finished Transform VerilogPrep$ ========

======== Starting Transform AddDescriptionNodes ========

Time: 2.9 ms
Form: UnknownForm
======== Finished Transform AddDescriptionNodes ========

Exception in thread "main" java.lang.AssertionError: assertion failed: Error! Synchronous reset should have been removed! UIntType(IntWidth(1)) AsyncResetType

[seldridge]

Yes, you're right. This isn't erroring out in the Chiffre transform, but later... Somehow an asynchronous reset is getting introduced and that is propagating all the way to the transforms that run just before Verilog emission.

Also, apologies for my slow responses, here. I've got a deadline coming up and haven't been able to circle back to this. I'm intending to, however.

[game11189]

Hello, I have got the same problem. Do you guys have any idea to fix it? Now, I can only compile a Rocket core with Chiffre by disabling the assert command giving this error (inside VerilogRender class in FIRRTL).