Major bug/problem in the a22oi_1 standard cell

[sergeiandreyev]

Functional inconsistency was found between layout/transistor-level schematic and Liberty/Verilog description of the a22oi_1 cell, if the cell is used in the design this will lead to a chip not functioning as expected (#42). New internal checks were implemented to find such inconsistencies and one issue was found also in sdfbbp_1 cell.
These issues are fixed in latest version of stdcell Liberty/Verilog views.
Please update your version of GitHub repository and rebuild your designs.

P.S. Thanks to ETH Zurich team that found this critical issue!