diff --git a/.github/CODEOWNERS b/.github/CODEOWNERS
new file mode 100644
index 00000000..3c99adce
--- /dev/null
+++ b/.github/CODEOWNERS
@@ -0,0 +1 @@
+*    @KrzysztofHerman @sergeiandreyev
diff --git a/.github/ISSUE_TEMPLATE.md b/.github/ISSUE_TEMPLATE.md
index a9d7ea35..f73a7ba1 100644
--- a/.github/ISSUE_TEMPLATE.md
+++ b/.github/ISSUE_TEMPLATE.md
@@ -1,7 +1,5 @@
 ## Environment
 
-- Klayout Version:
-- OS/Platform:
 
 ## Expected Behavior
 
diff --git a/.gitignore b/.gitignore
index e8c01c08..82f01ff1 100644
--- a/.gitignore
+++ b/.gitignore
@@ -14,7 +14,6 @@ dist/
 downloads/
 eggs/
 .eggs/
-lib/
 lib64/
 parts/
 sdist/
@@ -160,6 +159,7 @@ cython_debug/
 #.idea/
 
 *.raw
+*.la
 *.spice
 *.csv
 *.osdi
@@ -173,4 +173,7 @@ cython_debug/
 unit_tests_*
 lvs_run_*
 *_extracted.cir
-cells_tests_*
\ No newline at end of file
+cells_tests_*
+
+# KLayout LVS options
+lvs_options.yml
diff --git a/.gitmodules b/.gitmodules
new file mode 100644
index 00000000..9aa815d8
--- /dev/null
+++ b/.gitmodules
@@ -0,0 +1,9 @@
+[submodule "ihp-sg13g2/libs.tech/digital"]
+	path = ihp-sg13g2/libs.tech/digital
+	url = https://github.com/hneemann/IHP130.git
+[submodule "ihp-sg13g2/libs.tech/klayout/python/pycell4klayout-api"]
+	path = ihp-sg13g2/libs.tech/klayout/python/pycell4klayout-api
+	url = https://github.com/IHP-GmbH/pycell4klayout-api
+[submodule "ihp-sg13g2/libs.tech/klayout/python/pypreprocessor"]
+	path = ihp-sg13g2/libs.tech/klayout/python/pypreprocessor
+	url = https://github.com/IHP-GmbH/pypreprocessor
diff --git a/CHANGELOG.md b/CHANGELOG.md
new file mode 100644
index 00000000..9e629c5a
--- /dev/null
+++ b/CHANGELOG.md
@@ -0,0 +1,200 @@
+# Changelog
+
+All notable changes to this project will be documented in this file.
+
+The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/).
+
+## [Unreleased] - 2024-10-14
+
+### Added
+- Xschem install script: added Python shebang line
+- Qucs-S install script: added Python shebang line
+- Qucs-s install script: added checking for qucs-s binary
+- Add vbic examples for Xyce/adms
+- Add moshv lib and examples for Xyce
+- Initial list of tool versions
+- Added cross-platform compatibility for logger
+- Added initial version of multiplier check for netlists in stdcells
+- Add CODEOWNERS file
+    - Krzysztof and Sergei are the maintainer of this repository. Add them as CODEOWNER to auto-assign them in Pull Requests.
+- KLayout XSection: added initial README
+- Initial version of KLayout cross-section (XS) settings
+- Added HBT models for Xyce simulator
+- Added smaller SRAM macros
+- KLayout Pycells: added NWell to 'dpantenna' device
+- Added pnpMPA measurements documentation
+- Added 'Digital' IHP130 cells as submodule
+
+### Changed
+- Update ISSUE_TEMPLATE.md
+    - removed explicit env items, user should put his own related settings
+- Updated procedure to avoid constant openning cmd window on Windows to execute task list.
+- Update versions.txt
+    - added OpenVAF
+- Klayout PyCell integration
+    - Added support for or'ed #ifdef defines
+    - Took over windows compatibility work from Andreas Krinke <andreas.krinke@gmx.de>
+    - Fixed pypreprocessor issues
+    - Fixed misleading import
+    - Fixed documentation
+    - Add pypreprocessor IHP clone submodule
+    - Added evalution of names used for conditional compilation against process-chain
+    - Added catching of PyCell static/dynamic compilation errors for correction of file-path stack-dump
+    - Added diagnositc logging of process-chain as well as set defines
+    - Eleminate pre-definition of used defines by pre-scanning cell code
+    - Fixed issue from IHP open source server regarding remove of tmp-file
+    - Implemented 'conditional compilation' for PyCell code, see documentation in ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/__init__.py
+    - Simplified referencing python modules by setting search path
+    - Re-implemented clone() for shapes using deepcopy
+    - Implemented tagging of shapes feature from SKILL Pcell counter-part
+    - Fixed npn13G2L/npn13G2V to be equal to SKILL Pcell counter-part
+    - Introduced library code/documentation as submodule from pycell4klayout-api repo
+    - Added support for fgAnd, fgNot andfgSize
+    - Fixed dbLayerSize
+    - Fixed pin label creation by removing extra text generation
+    - Added missing self-argument in class Box
+    - Fix wrong assignment: re-assign pins, terms and nets from PyCell-instances to cell-instances for multi-cell instances of the same PyCell
+    - Fixed merge-error
+    - Added PyCell parameter type bool
+    - Added partial implementation for PyCell API class Net
+    - Added partial implementation for PyCell API class Path
+    - Added partial implementation for PyCell API class ShapeFilter
+    - Added support for Net's
+    - Added generic registering of IHP PyCell's in Klayout
+    - Added support for inductor2, inductor2_sc, inductor2_sp, inductor3, inductor3_sc and inductor3_sp
+    - Added partial implementation of class Pin from PyCell API
+    - Added partial implementation of class Term from PyCell API
+    - Added support for pins/terminals
+    - Added support for XOR geometric transformation
+    - Added support for text alignment/orientation
+    - Fixed dbLayerXorList from geometry.py
+    - Added support of npn13G2L and npn13G2V
+    - Extended documentation
+- Update KLayout DRC scripts
+    - fixes regression that missed DRC errors, e.g. for M1.b
+    - improves running the DRC on Windows
+    - prints message for each rule during run
+    - new options, increased accuracy of width and overlap checks
+    - fixes bug regarding µm/dbu conversion
+    - new options, increased accuracy of space and separation checks
+    - fixes incorrect DRC errors, e.g. for pSD.d, pSD.d1
+    - maximal DRC script supports ~75% of rules
+    - rename DRC script parameters for OpenROAD compatibility
+        - logfile -> log_file
+        - gdsfile -> in_gds
+        - outfile -> report_file
+    - DRC script parameter "cell" is now optional
+    - output number of DRC errors at the end
+    - DRC script no longer depends on layout dbu
+        - all lengths are given in micrometers
+    - add limits to rule descriptions, e.g., "Min. GatPoly width = 0.13"
+- Improve Windows compatibility of PyCell code
+    - remove dependency on psutil, which is difficult to install on Windows
+- Updated Qucs-S examples, install.py for Qucs
+- Use Xyce vbic build-in model instead Verilog-A model
+- Change example file names
+- Xyce library extension moslv
+- Update README.md
+    - added tool versions part
+    - Aligned file names
+    - added note on XSection in PDK contents
+    - updated year in Apache license header
+    - Added 'Digital' tool in PDK contents
+    - Added LVS in PDK contents section
+- pmosHV Pycell: various updates to align to the implementation in commercial PDK
+- Pycell4klayout-api updated to the latest version
+- Sealring Pycell: area for registration
+- libs.tech: openroad: Add missing SRAMs
+    - A4defa8ab added missing .lib files for recently added SRAMs. Update the export.yml with all files for these RAMs.
+- Xyce HBT models: commented vbe_max, vbc_max, vce_max parameters - these are not used
+- libs.tech: Python tool to generate export.yml
+    - The export.yml file communicates all exportable files, with additional meta data, to OpenROAD. It can automatically check if files changed or new exist and sync those.
+- libs.ref: Don't ignore sub-directories
+    - The .gitignore in the root level ignores directories like lib/. This will prevent checking in new libs as Git would ignore those.
+- Update README.md
+    - added note on current status
+    - screenshot as an example
+- KLayout Pycells: small typo correction in npn13G2* devices
+- Update README.md
+    - Added requirement to set PDK_ROOT
+- Ngspice models: changed '.parameters' to '.param' in corner*.lib files
+- Option list duplication removed
+- Update xschemrc
+    - Adding `append XSCHEM_LIBRARY_PATH :${XSCHEM_SHAREDIR}/xschem_library/devices` line
+- Update path to standard symbols
+- .spiceinit PDK env. variable added + fixes
+- .spiceinit PDK env. variable added
+- Update .gitmodules
+    - Changed SSH to HTTPS mode
+- Updating custom writer for LVS runset
+- Major change in ngspice model referencing, xschem testcases update, qucs-s examples updated
+- Construct full lvs rule deck for SG13G2 tech
+- libs.tech: Klayout: tech: sg13g2.lyt: Use empty lef-files
+    - OpenROAD-flow-scripts will search and replace for <lef-files>.*</lef-files>. Therefore, keep it empty in this syntax.
+- libs.tech: Klayout: tech: Add map file
+    - This file was copied from the OpenROAD-flow-scripts repository and should be maintained and kept here.
+- libs.tech: Klayout: tech: Add layer map
+    - OpenROAD requires the sg13g2.map file to correctly place each layer. Fix this here to not overwrite manually changes in OpenROAD-Flow-Scripts.
+- KLayout Pycells: updated device library name
+- KLayout tech file: setting up technology specific grids, smallest (req) = 5nm
+- IO cells: renamed 'liberty' folder to 'lib' to align across cellsets (stdcell, sram)
+- IO cells: aligned Liberty file names
+- libs.tech: klayout: Add macro to report layer density
+    - This script calculates and reports the density for multiple important layers and can help to see which layers will violatie fill rules. Based-on: Krzystof Herman <herman@ihp-microelectronics.com>
+- libs.tech: klayout: drc: Use correct border
+    - The DRC report had multiple violations included which are relate to unclean calculation of the chip border. Based-on: Andreas Krinke <andreas.krinke@tu-dresden.de>
+- libs.tech: klayout: Add Python script to generate Sealring files
+    - This script can be called in Klayout's batch mode and generates a GDS file with a sealring included. The width and height of the ring are configurable via arguments.
+    - Example call: 
+    ```
+    klayout -n sg13g2 -zz -r sealring.py \
+    -rd width=1300.0 -rd height=1300.0 \
+    -rd output=macros/sealring.gds.gz
+    ```
+- DbCreateRect outside if..else
+- Via stack PCell integration
+- KLayout Pycells: some fixes and cleanup for npn13G2
+- IO cells: renamed CDL file to align
+- Dantenna and dpantenna PCells integration
+- Xschem testcases *.sch files updated to support lower-case w and l
+- Xschemrc res_drc function updated
+- DRC checks for xschem added in xschemrc (mosfets, hbt, diode, res, mim), symbols modified, some testcases modified
+- @spiceprefix added for mos devices and diodes, RF symbols added for HV mosfets
+- Lv symbols modified for lvs, @spiceprofix added
+- Change hv pcells name
+- KLayout Pycells: updated 'Ae' text string in npn13G2* cells to be consistent w/ internal implementation
+- Hv added to init
+- Hv-mos pcell integration
+- Lvs-symbol
+- Some updates on top of #121
+    - Remove labels on ESD diodes so they are now recognized as regular d(p)antenna diodes
+    - Increase width to minimum 0.48µm to account for new rule not yet in DRC check.
+- Layout rule manual updated
+- Update README.md
+    - OpenROAD, OpenROAD flow scripts, Qucs-S added as supported EDA tools.
+
+### Fixed
+- Stdcells LEF: USE ANALOG changed to USE SIGNAL
+- pnpMPA: fixed pin order in model, updated xschem symbol and testbench
+- libs.ref: sg13g2_io: verilog: Fix specify syntax
+    - The input and output definition in the Verilog specify block were positioned in the wrong order (output to input). Change and also implement the tri-state better.
+- LVS rule decks: Fix GF180 remnants in log strings
+- pnpMPA docs: fixed typos in file naming
+- libs.tech: klayout: macros: Fix intentation
+- libs.tech: klayout: Fix Metal density min/max values
+    - Global min./max. Metal(n) density values are 35% and 60%. The previous 25% and 75% are only valid for 800x800 chip areas.
+- Fix class name in hv-pmos pcell
+- Fix hv pcell integration in init file
+
+### Removed
+- Qucs-S symbols: removed .INCLUDE, removed temperature sensing terminal from standard npn13G2* devices
+- Pycells: removed via_stack device, it's obsolete
+- Remove merged.lef from klayout setup
+    - Removing reference to merged.lef which does not exist.
+- Delete ihp-sg13g2/libs.tech/pycell directory
+- KLayout tech JSON: removed all layers definitions, these are taken from .lyp file
+- KLayout DRC: removed obsolete deck file (now we have min and max in separate files)
+
+[unreleased]: https://github.com///compare/v0.1.0..HEAD
+
+<!-- generated by git-cliff -->
diff --git a/README.md b/README.md
index 6ce32e99..59ad95ea 100644
--- a/README.md
+++ b/README.md
@@ -39,10 +39,12 @@ backend option offers 5 thin metal layers, two thick metal layers (2 and 3 μm t
     * SPICE Netlist
     * Verilog
 * IO cellset
+    * CDL
     * GDSII
     * LEF
-    * Liberty (dummy)
+    * Liberty
     * SPICE Netlist
+    * Verilog
 * SRAM cellset
     * CDL
     * GDSII
@@ -53,13 +55,14 @@ backend option offers 5 thin metal layers, two thick metal layers (2 and 3 μm t
     * GDSII
 * KLayout tool data:
     * layer property and tech files
-    * DRC rules (minimal set)
-    * PyCells
-       * initial version of the wrapper API
-       * sample cells
-* Pcells (for reference only) `libs.tech/pycell`
+    * DRC rules (minimal/maximal set)
+    * LVS rules
+    * PyCells (1st priority)
+    * XSection initial settings
 * MOS/HBT/Passive device models for ngspice/Xyce
 * xschem: primitive device symbols, settings and testbenches
+* Qucs-S: primitive device symbols, settings and testbenches
+* Digital: stdcells
 * OpenEMS: tutorials, scripts, documentation
 * SG13G2 Process specification & Layout Rules
 * MOS/HBT Measurements in MDM format
@@ -83,6 +86,13 @@ backend option offers 5 thin metal layers, two thick metal layers (2 and 3 μm t
     * Source: https://github.com/KLayout/klayout
 * OpenEMS
     * Source: https://github.com/thliebig/openEMS-Project
+* OpenROAD
+    * Source: https://github.com/The-OpenROAD-Project/OpenROAD
+* OpenROAD-flow-scripts
+    * Source: https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts
+ 
+## Tool versions (tested with)
+[versions.txt](versions.txt)
 
 ## Contributing
 
@@ -105,7 +115,7 @@ The IHP Open Source PDK is released under the [Apache 2.0 license](LICENSE).
 
 The copyright details are:
     
-    Copyright 2023 IHP PDK Authors
+    Copyright 2024 IHP PDK Authors
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
diff --git a/ihp-sg13g2/libs.doc/doc/SG13G2_os_layout_rules.pdf b/ihp-sg13g2/libs.doc/doc/SG13G2_os_layout_rules.pdf
index 82d83d7b..8bd0fa79 100644
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diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/buttons.htm b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/buttons.htm
new file mode 100644
index 00000000..ade0a86f
--- /dev/null
+++ b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/buttons.htm
@@ -0,0 +1,44 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html>
+<head>
+<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=utf-8">
+<SCRIPT LANGUAGE="JavaScript">
+<!--
+function btZoom()
+{ var actPage;
+  var newPage;
+  actPage = parent.text.location.href;
+  var pos;
+  pos = actPage.indexOf("result_");
+  if ( pos>0 )
+  { newPage = actPage.substr(0,pos)+"reszoom"+actPage.substr(pos+6);
+  open(newPage);
+  }  
+  else alert("For this page is no zoomed page available");
+}
+function btDetach()
+{ var newPage;
+  newPage = parent.text.location.href;
+  open(newPage);
+}
+function btPrint()
+{ parent.text.focus();
+  var checkVar;
+  var BrowserName = navigator.appName;
+  checkVar = parent.text.usePrintZoom;
+  if ( checkVar==1 ) parent.text.setPrintZoom(1);
+  parent.text.window.print();
+  if (BrowserName=="Netscape") alert("Continue ...");
+  if ( checkVar==1 ) parent.text.setPrintZoom(0);
+}
+//-->
+</SCRIPT>
+</head>
+<body bgcolor="#E1E1E1">
+<form>
+<input type="button" value="Zoom" onclick="btZoom()">
+<input type="button" value="Detach" onclick="btDetach()">
+<input type="button" value="Print" onclick="btPrint()">
+</form>
+</body>
+</html>
diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/content.htm b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/content.htm
new file mode 100644
index 00000000..de13d8c7
--- /dev/null
+++ b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/content.htm
@@ -0,0 +1,61 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html>
+
+<head>
+
+<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=utf-8">
+
+<title>Content</title></head>
+
+<body bgcolor="FFFFFF">
+
+<hr>
+
+<h1>pnpMPA (SG13)</h1>
+
+<h2>pnpMPA</h2>
+
+<p>Testfield: T323<br>Technology: SG13<br>Lot: PQA701 (SG13S)<br>Wafer: 01, 15-19, 24<br>Lot: PQA702 (SG13G2)<br>Wafer: 06-10<br>Date: October 2022<br>
+<br>DC and CV Measurements&nbsp; at 27°C</p>
+
+<h3>Devices Info</h3>
+
+<h4>pnpMPA Transistor</h4>
+
+ &nbsp;&nbsp;&nbsp;&nbsp; <a href="setup/dc_new.htm">Geometries and appplications</a><br>
+
+<h3>Measurements Setup</h3>
+
+<h4>DC Setup</h4>
+
+ &nbsp;&nbsp;&nbsp;&nbsp; <a href="setup/meas_pnpMPA_new.htm">Bias Conditions</a><br>
+
+
+
+ <h3>Results</h3>
+
+<h4>Transistor Characteristics</h4>
+
+ &nbsp;&nbsp;&nbsp;&nbsp; <a href="results/result_gummel_transistor_pnpMPA_new.htm">Gummel Plots</a><br>
+
+ &nbsp;&nbsp;&nbsp;&nbsp; <a href="results/result_output_transistor_pnpMPA_new.htm">Output Characteristics</a><br>
+
+<h4>Capacitances</h4>
+
+ &nbsp;&nbsp;&nbsp;&nbsp; <a href="results/result_c_pnpMPA_new.htm">Junction Capacitances</a><br>
+
+<h4>Monte-Carlo Statistical Data</h4>
+
+ &nbsp;&nbsp;&nbsp;&nbsp; <a href="results/result_stats.htm">Best Case, Worst Case, 1-Sigma</a><br>
+
+
+<h3>Model Parameter Set</h3>
+
+ &nbsp;&nbsp;&nbsp;&nbsp; <a href="results/library_transistor_pnpMPA.htm">pnpMPA</a><br>
+
+
+
+<br><hr>
+
+</body></html>
diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/head.htm b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/head.htm
new file mode 100644
index 00000000..26bfab15
--- /dev/null
+++ b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/head.htm
@@ -0,0 +1,10 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<head>
+<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=utf-8">
+</head>
+<body bgcolor="#E1E1E1">
+<FONT FACE="Helvetica, ARIAL, MS SANS SERIF, SANS-SERIF" SIZE="2">
+<b>pnpMPA (SG13_tech)</b>
+</FONT>
+</body>
+</html>
\ No newline at end of file
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diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/imgmenu/join.gif b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/imgmenu/join.gif
new file mode 100644
index 00000000..458076b8
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diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/imgmenu/joinbottom.gif b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/imgmenu/joinbottom.gif
new file mode 100644
index 00000000..664e3957
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diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/imgmenu/jointop.gif b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/imgmenu/jointop.gif
new file mode 100644
index 00000000..2c95aa4e
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diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/imgmenu/line.gif b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/imgmenu/line.gif
new file mode 100644
index 00000000..a2aceafa
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diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/imgmenu/minus.gif b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/imgmenu/minus.gif
new file mode 100644
index 00000000..40c8f20b
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diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/imgmenu/minusbottom.gif b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/imgmenu/minusbottom.gif
new file mode 100644
index 00000000..2c350841
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diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/imgmenu/minusonly.gif b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/imgmenu/minusonly.gif
new file mode 100644
index 00000000..fd6dd506
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diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/imgmenu/minustop.gif b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/imgmenu/minustop.gif
new file mode 100644
index 00000000..4a665a85
Binary files /dev/null and b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/imgmenu/minustop.gif differ
diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/imgmenu/plus.gif b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/imgmenu/plus.gif
new file mode 100644
index 00000000..6aab0430
Binary files /dev/null and b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/imgmenu/plus.gif differ
diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/imgmenu/plusbottom.gif b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/imgmenu/plusbottom.gif
new file mode 100644
index 00000000..d75515a0
Binary files /dev/null and b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/imgmenu/plusbottom.gif differ
diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/imgmenu/plusonly.gif b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/imgmenu/plusonly.gif
new file mode 100644
index 00000000..a5cf04e0
Binary files /dev/null and b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/imgmenu/plusonly.gif differ
diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/imgmenu/plustop.gif b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/imgmenu/plustop.gif
new file mode 100644
index 00000000..087be05d
Binary files /dev/null and b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/imgmenu/plustop.gif differ
diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/index.htm b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/index.htm
new file mode 100644
index 00000000..144d2593
--- /dev/null
+++ b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/index.htm
@@ -0,0 +1,973 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<HTML>
+<HEAD>
+<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=utf-8">
+<!--
+Joust Outliner Version 2.5.4
+(c) Copyright 1996-2001, MITEM (Europe) Ltd. All rights reserved.
+This code may be freely copied and distributed provided that it is accompanied by this 
+header.  For full details of the Joust license, as well as documentation and help, go 
+to http://www.ivanpeters.com/.
+
+Do not modify anything between here and the "End of Joust" marker unless you know what you
+are doing.  
+-->
+<script language="JavaScript">
+<!--
+function getDHTMLObj(docName, objName) {
+	if 	(theBrowser.hasW3CDOM) {
+		//AdMOS Fix Javascript Error
+		if ( eval(docName + '.getElementById("' + objName + '")') != null ){
+			return eval(docName + '.getElementById("' + objName + '").style');
+		}
+		else { return "";}
+	}
+	else { return eval(docName + theBrowser.DHTMLRange + '.' + objName + theBrowser.DHTMLStyleObj);	}
+}
+function getDHTMLObjTop(theObj) {return (theBrowser.code == "MSIE") ? theObj.pixelTop : theObj.top;}
+function getDHTMLObjHeight(docName, objName) {
+	if 	(theBrowser.hasW3CDOM) {
+		//AdMOS Fix Javascript Error
+		if ( eval(docName + '.getElementById("' + objName + '")') != null ){
+			return parseInt(eval(docName + '.getElementById("' + objName + '").offsetHeight'),10);
+		}
+		else { return "";}
+	}
+	else { return eval(docName + theBrowser.DHTMLRange + '.' + objName + theBrowser.DHTMLDivHeight); }
+}
+function getDHTMLImg(docName, objName, imgName) {
+	if 	(document.layers) {
+		return getDHTMLObj(docName, objName).document.images[imgName];
+	} else {
+		return eval(docName + '.images.' + imgName);
+	}
+}
+function simpleArray() {this.item = 0;}
+function imgStoreItem(n, s, w, h) {
+	this.name = n;
+	this.src = s;
+	this.obj = null;
+	this.w = w;
+	this.h = h;
+	if ((theBrowser.canCache) && (s)) {
+		this.obj = new Image(w, h);
+		this.obj.src = s;
+	}
+}
+function imgStoreObject() {
+	this.count = -1;
+	this.img = new imgStoreItem;
+	this.find = imgStoreFind;
+	this.add = imgStoreAdd;
+	this.getSrc = imgStoreGetSrc;
+	this.getTag = imgStoreGetTag;
+}
+function imgStoreFind(theName) {
+	var foundItem = -1;
+	for (var i = 0; i <= this.count; i++) {if (this.img[i].name == theName) {foundItem = i;break;}}
+	return foundItem;
+}
+function imgStoreAdd(n, s, w, h) {
+	var i = this.find(n);
+	if (i == -1) {i = ++this.count;}
+	this.img[i] = new imgStoreItem(n, s, parseInt(w, 10), parseInt(h, 10));
+}
+function imgStoreGetSrc(theName) {
+	var i = this.find(theName);
+	var img = this.img[i];
+	return (i == -1) ? '' : ((img.obj) ? img.obj.src : img.src);
+}
+function imgStoreGetTag(theName, iconID, altText) {
+	var i = this.find(theName);
+	if (i < 0) {return ''}
+	with (this.img[i]) {
+		if (src == '') {return ''}
+		var tag = '<img src="' + src + '" width="' + w + '" height="' + h + '" border="0" align="left" hspace="0" vspace="0"';
+		tag += (iconID != '') ? ' name="' + iconID + '"' : '';
+		tag += ' alt="' + ((altText)?altText:'') + '">';
+	}
+	return tag;
+}
+// The MenuItem object.  This contains the data and functions for drawing each item.
+function MenuItem (owner, id, type, text, url, status, nItem, pItem, parent) {
+	var t = this;
+	this.owner = owner;
+	this.id = id;
+	this.type = type;
+	this.text = text;
+	this.url = url;
+	this.status = status;
+	this.target = owner.defaultTarget;
+	this.nextItem = nItem;
+	this.prevItem = pItem;
+	this.FirstChild = -1;
+	this.parent = parent;
+	this.isopen = false;
+	this.isSelected = false;
+	this.draw = MIDraw;
+	this.PMIconName = MIGetPMIconName;
+	this.docIconName = MIGetDocIconName;
+	this.setImg = MISetImage;
+	this.setIsOpen = MISetIsOpen;
+	this.setSelected = MISetSelected;
+	this.setIcon = MISetIcon;
+	this.mouseOver = MIMouseOver;
+	this.mouseOut = MIMouseOut;
+	var i = (this.owner.imgStore) ? this.owner.imgStore.find(type) : -2;
+	if (i == -1) {i = this.owner.imgStore.find('iconPlus');}
+	this.height = (i > -1) ? this.owner.imgStore.img[i].h : 0;
+}
+function MIDraw (indentStr) {
+	var o = this.owner;
+	var mRef = '="return ' + o.reverseRef + "." + o.name;
+	var tmp = mRef + '.entry[' + this.id + '].';
+	var MOver = ' onMouseOver' + tmp + 'mouseOver(\''
+	var MOut = ' onMouseOut' + tmp + 'mouseOut(\''
+	var iconTag = o.imgStore.getTag(this.PMIconName(), 'plusMinusIcon' + this.id, '');
+	var aLine = '<nobr>' + indentStr;
+	if (!this.noOutlineImg) {
+		if (this.FirstChild != -1) {
+			aLine += '<A HREF="#" onClick' + mRef + '.toggle(' + this.id + ');"' + MOver + 'plusMinusIcon\',this);"' + MOut + 'plusMinusIcon\');">' + iconTag + '</A>';				
+		} else {
+			aLine += iconTag;
+		}
+	}
+	var tip = (o.tipText == 'text') ? this.text : ((o.tipText == 'status') ? this.status : '');
+	var theEntry = o.imgStore.getTag(this.docIconName(), 'docIcon' + this.id, tip) + this.text;
+	var theImg = o.imgStore.getTag(this.docIconName(), 'docIcon' + this.id, tip);
+	var sTxt = '<SPAN CLASS="' + ((this.CSSClass) ? this.CSSClass : ((this.FirstChild != -1) ? 'node' : 'leaf')) + '">';
+	var lTxt = '<A NAME="joustEntry' + this.id + '"';
+	var theUrl = (((this.url == '') && theBrowser.canJSVoid && o.showAllAsLinks) || o.wizardInstalled) ? 'javascript:void(0);' : this.url;
+	if (theUrl != '') {
+		if (this.target.charAt(1) == "_") {theUrl = "javascript:" + o.reverseRef + ".loadURLInTarget('" + theUrl + "', '" + this.target + "');";}
+			lTxt += ' HREF="' + theUrl + '" TARGET="' + this.target + '" onClick' + mRef + '.itemClicked(' + this.id + ');"'
+			+ MOver + 'docIcon\',this);"' + MOut + 'docIcon\');"';
+	}
+	lTxt += (tip) ? ' TITLE="' + tip + '">' : '>';
+	aLine += sTxt + lTxt + theImg;
+	if (this.multiLine) {
+		aLine += '</A></SPAN><TABLE BORDER="0" CELLPADDING="0" CELLSPACING="0"><TR><TD>' + sTxt + lTxt + this.text + '</A></SPAN></TD></TR></TABLE>';
+	} else {
+		aLine += this.text + '</A></SPAN>';
+	}
+	aLine += '</nobr>';
+	if ((theBrowser.hasW3CDOM) && (theBrowser.hasDHTML) && (!this.multiLine))  { aLine += '<br>'; }
+	return aLine
+}
+function MIGetPMIconName() {
+	var n = 'icon' + ((this.FirstChild != -1) ? ((this.isopen == true) ? 'Minus' : 'Plus') : 'Join');
+	n += (this.id == this.owner.firstEntry) ? ((this.nextItem == -1) ? 'Only' : 'Top') : ((this.nextItem == -1) ? 'Bottom' : '');
+	return n;
+}
+function MIGetDocIconName() {
+	var is = this.owner.imgStore; var n = this.type;
+	n += ((this.isopen) && (is.getSrc(n + 'Expanded') != '')) ? 'Expanded' : '';
+	n += ((this.isSelected) && (is.getSrc(n + 'Selected') != '')) ? 'Selected' : '';
+	return n;
+}
+function MISetImage(imgID, imgName) {
+	var o = this.owner; var s = o.imgStore.getSrc(imgName);
+	if ((s != '') && (theBrowser.canCache) && (!o.amBusy)) {
+		var img = (theBrowser.hasDHTML) ? getDHTMLImg(o.container + '.document', 'entryDIV' + this.id, imgID) : eval(o.container).document.images[imgID];
+		if (img && img.src != s) {img.src = s;} 
+	}
+}
+function MISetIsOpen (isOpen) {
+	if ((this.isopen != isOpen) && (this.FirstChild != -1)) {
+		this.isopen = isOpen;
+		this.setImg('plusMinusIcon' + this.id, this.PMIconName());
+		this.setImg('docIcon' + this.id, this.docIconName());
+		return true;
+	} else {
+		return false;
+	}
+}
+function MISetSelected (isSelected) {
+	this.isSelected = isSelected;
+	this.setImg('docIcon' + this.id, this.docIconName());
+	if ((this.parent >= 0) && this.owner.selectParents) {this.owner.entry[this.parent].setSelected(isSelected);}
+}
+function MISetIcon (newType) {
+	this.type = newType;
+	this.setImg('docIcon' + this.id, this.docIconName());
+}
+function MIMouseOver(imgName, theURL) {
+	eval(this.owner.container).status = '';  //Needed for setStatus to work on MSIE 3 - Go figure!?
+	var newImg = '';
+	var s = '';
+	if (imgName == 'plusMinusIcon') {
+		newImg = this.PMIconName();
+		s = 'Click to ' + ((this.isopen == true) ? 'collapse.' : 'expand.');
+	} else {
+		if (imgName == 'docIcon') {
+			newImg = this.docIconName();
+			s = (this.status != null) ? this.status : theURL;
+		}
+	}
+	setStatus(s);
+	if (theBrowser.canOnMouseOut) {this.setImg(imgName + this.id, newImg + 'MouseOver');}
+	if(this.onMouseOver) {var me=this;eval(me.onMouseOver);}
+	return true;
+}
+function MIMouseOut(imgName) {
+	clearStatus();
+	var newImg = '';
+	if (imgName == 'plusMinusIcon') {
+		newImg = this.PMIconName();
+	} else {
+		if (imgName == 'docIcon') {newImg = this.docIconName();}
+	}
+	this.setImg(imgName + this.id, newImg);
+	if(this.onMouseOut) {var me=this;eval(me.onMouseOut);}
+	return true;
+}
+// The Menu object.  This is basically an array object although the data in it is a tree.
+function Menu () {
+	this.count = -1;
+	this.version = '2.5.4';
+	this.firstEntry = -1;
+	this.autoScrolling = false;
+	this.modalFolders = false;
+	this.linkOnExpand = false;
+	this.toggleOnLink = false;
+	this.showAllAsLinks = false;
+	this.savePage = true;
+	this.name = 'theMenu';
+	this.container = 'menu';
+	this.reverseRef = 'parent';
+	this.contentFrame = 'text';
+	this.defaultTarget = 'text';
+	this.tipText = 'none';
+	this.selectParents = false;
+	this.lastPMClicked = -1;
+	this.selectedEntry = -1;
+	this.wizardInstalled = false;
+	this.amBusy = true;
+	this.maxHeight = 0;
+	this.imgStore = new imgStoreObject;
+	this.entry = new MenuItem(this, 0, '', '', '', '', -1, -1, -1);
+	this.contentWin = MenuGetContentWin;
+	this.getEmptyEntry = MenuGetEmptyEntry;
+	this.addEntry = MenuAddEntry;
+	this.addMenu = MenuAddEntry;
+	this.addChild = MenuAddChild;
+	this.rmvEntry = MenuRmvEntry;
+	this.rmvChildren = MenuRmvChildren;
+	this.draw = MenuDraw;
+	this.drawALevel = MenuDrawALevel;
+	this.refresh = MenuRefresh;
+	this.reload = MenuReload;
+	this.refreshDHTML = MenuRefreshDHTML;
+	this.scrollTo = MenuScrollTo;
+	this.itemClicked = MenuItemClicked;
+	this.selectEntry = MenuSelectEntry;
+	this.setEntry = MenuSetEntry;
+	this.setEntryByURL = MenuSetEntryByURL;
+	this.setAllChildren = MenuSetAllChildren;
+	this.setAll = MenuSetAll;
+	this.openAll = MenuOpenAll;
+	this.closeAll = MenuCloseAll;
+	this.findEntry = MenuFindEntry;
+	this.toggle = MenuToggle;
+}
+function MenuGetContentWin() {
+	return eval(((myOpener != null) ? 'myOpener.' : 'self.') + this.contentFrame);
+}
+function MenuGetEmptyEntry() {
+	for (var i = 0; i <= this.count; i++) {if (this.entry[i] == null) {break;}}
+	if (i > this.count) {this.count = i};
+	return i
+}
+function MenuAddEntry (addTo, type, text, url, status, insert) {
+	if (!insert) {insert=false;}
+	var theNI = -1;var theP = -1;var thePI = -1;
+	if (addTo < 0) {
+		var i = addTo = this.firstEntry;
+		if (!insert) {while (i > -1) {addTo = i;i = this.entry[i].nextItem;}}
+	}
+	if (addTo >= 0) {
+		var e = this.entry[addTo];
+		if (!e) {return -1;}
+		thePI = (insert)?e.prevItem:addTo;
+		theNI = (insert)?addTo:e.nextItem;
+		theP = e.parent;
+	}
+	var eNum = this.getEmptyEntry();
+	if (thePI >= 0) {
+		this.entry[thePI].nextItem = eNum;
+	} else {
+		if (theP >= 0) {
+			this.entry[theP].FirstChild = eNum;
+		} else {
+			this.firstEntry = eNum;
+		}
+	}
+	if (theNI >= 0) {this.entry[theNI].prevItem = eNum;}
+	this.entry[eNum] = new MenuItem(this, eNum, type, text, url, status, theNI, thePI, theP);
+	return eNum;
+}
+function MenuAddChild (addTo, type, text, url, status, insert) {
+	if (!insert) {insert=false;}
+	var eNum = -1;
+	if ((this.count == -1) || (addTo < 0)) {
+		eNum = this.addEntry(-1, type, text, url, status, false);
+	} else {
+		var e = this.entry[addTo];
+		if (!e) {return -1;}
+		var cID = e.FirstChild;
+		if (cID < 0) {
+			e.FirstChild = eNum = this.getEmptyEntry();
+			this.entry[eNum] = new MenuItem(this, eNum, type, text, url, status, -1, -1, addTo);	
+		} else {
+			while (!insert && (this.entry[cID].nextItem >= 0)) {cID = this.entry[cID].nextItem;}
+			eNum = this.addEntry(cID, type, text, url, status, insert);
+		}
+	}
+	return eNum;
+}
+function MenuRmvEntry (theEntry) {
+	var e = this.entry[theEntry];
+	if (e == null) {return;}
+	var p = e.prevItem;
+	var n = e.nextItem;
+	if (e.FirstChild > -1) {this.rmvChildren(theEntry);}
+	if (this.firstEntry == theEntry) {this.firstEntry = n}
+	if (this.selectedEntry == theEntry) {this.selectedEntry = n}
+	if (p > -1) {
+		this.entry[p].nextItem = n;
+	} else { 
+		if (e.parent > -1) {
+			this.entry[e.parent].FirstChild = n;
+		} else {
+			if (this.firstEntry == theEntry) {this.firstEntry = n}
+		}
+	} 
+	if (n > -1) {this.entry[n].prevItem = p;}
+	this.entry[theEntry] = null;
+}
+function MenuRmvChildren (theP) {
+	var eNum;var e;var tmp;
+	if (theP == -1) {
+		eNum = this.firstEntry;
+		this.firstEntry = -1;
+	} else {
+		eNum = this.entry[theP].FirstChild;
+		this.entry[theP].FirstChild = -1;
+	}
+	while (eNum > -1) {
+		e = this.entry[eNum];
+		if (e.FirstChild > -1) {this.rmvChildren(eNum);}
+		if (this.selectedEntry == eNum) {this.selectedEntry = e.parent;}
+		tmp = eNum;
+		eNum = e.nextItem;
+		this.entry[tmp] = null;
+	}
+}
+function MenuDraw() {
+	this.maxHeight = 0;
+	var theDoc = eval(this.container + ".document");
+	eval(this.container).document.writeln(this.drawALevel(this.firstEntry, '', true, theDoc));
+	if (theBrowser.hasDHTML) {
+		for (var i = 0; i <= this.count; i++) {
+			if (this.entry[i]) {
+				this.maxHeight += getDHTMLObjHeight(this.container + '.document', 'entryDIV' + i);
+			}
+		}
+	} else {
+		if ((this.lastPMClicked > 0) && theBrowser.mustMoveAfterLoad && this.autoScrolling) {
+			this.scrollTo(this.lastPMClicked);
+		}
+	}
+}
+function MenuDrawALevel(firstItem, indentStr, isVisible, theDoc) {
+	var currEntry = firstItem;
+	var padImg = "";
+	var aLine = "";
+	var theLevel = "";
+	var e = null;
+	while (currEntry > -1) {
+		e = this.entry[currEntry];
+		aLine = e.draw(indentStr);
+		if (theBrowser.hasDHTML) {
+			aLine = '<DIV ID="entryDIV' + currEntry + '" CLASS="menuItem">' + aLine + '</DIV>';
+		} else {
+			aLine += '<BR CLEAR="ALL">';
+		}
+		theBrowser.lineByLine = true;
+		if (theBrowser.lineByLine) {theDoc.writeln(aLine);} else {theLevel += aLine;}
+		if ((e.FirstChild > -1) && ((theBrowser.hasDHTML || (e.isopen && isVisible)))) {
+			padImg = (e.noOutlineImg) ? '' : this.imgStore.getTag((e.nextItem == -1) ? 'iconBlank' : 'iconLine', '', '');
+			theLevel += this.drawALevel(e.FirstChild, indentStr + padImg, (e.isopen && isVisible), theDoc);
+		}
+		currEntry = e.nextItem;
+	}
+	return theLevel;
+}
+function MenuRefresh() {
+	if (theBrowser.hasDHTML) {
+		if (!this.amBusy) {
+			this.refreshDHTML();
+			if (this.autoScrolling) {this.scrollTo(this.lastPMClicked);}
+		}
+	} else {
+		this.reload();
+	}
+}
+function MenuReload() {
+	if (!this.amBusy) {
+		this.amBusy = true;
+		var l = eval(this.container).location;
+		var rm = theBrowser.reloadMethod;
+		var newLoc = fixPath(l.pathname);
+		var s = '';
+		if (l.search) {s = l.search;}
+		if (theBrowser.needsMenuSearch) {
+			if (s == '') {
+				s = '?jtoggle=1';
+			} else {
+				var p = s.indexOf('jtoggle=');
+				if (p < 0) {
+					s += '&jtoggle=1';
+				} else {
+					var t = (s.substring(p + 8, p + 9) == "1") ? "2" : "1";
+					s = s.substring(0, p+8) + t;
+				}
+			}
+		}
+		newLoc += s;
+		if (this.autoScrolling && (this.lastPMClicked > 0) && !theBrowser.mustMoveAfterLoad) {
+			newLoc += "#joustEntry" + this.lastPMClicked;
+		}
+		if (rm == 'replace') {
+			l.replace(newLoc);
+		} else {
+			if (rm == 'reload') {
+				l.reload();
+			} else {
+				if (rm == 'timeout') {
+					setTimeout(this.container + ".location.href ='" + newLoc + "';", 100);
+				} else {
+					l.href = newLoc;
+				}
+			}
+		}
+	}
+}
+function MenuRefreshDHTML() {
+	var nextItemArray = new simpleArray;
+	var currEntry = this.firstEntry;
+	var level = (currEntry == -1) ? 0 : 1;
+	var isVisible = true;
+	var lastVisibleLevel = 1;
+	var co = eval(this.container);
+	var yPos = co.menuStart;
+	var d = this.container + '.document';
+	var e = null;var s = null;
+	while (level > 0) {
+		e = this.entry[currEntry];
+		s = getDHTMLObj(d, 'entryDIV' + currEntry);
+		if (isVisible) {
+			s.top = yPos;
+			s.visibility = 'visible';
+			yPos += getDHTMLObjHeight(d, 'entryDIV' + currEntry);
+			lastVisibleLevel = level;
+		} else {
+			s.visibility = 'hidden';
+			s.top = 0;
+		}
+		if (e.FirstChild > -1) {
+			isVisible = (e.isopen == true) && isVisible;
+			nextItemArray[level++] = e.nextItem;
+			currEntry = e.FirstChild;
+		} else {
+			if (e.nextItem != -1) {
+				currEntry = e.nextItem;
+			} else {
+				while (level > 0) {
+					if (nextItemArray[--level] != -1) {
+						currEntry = nextItemArray[level];
+						isVisible = (lastVisibleLevel >= level);
+						break;
+					}
+				}
+			}
+		}
+	}
+	this.maxHeight = yPos;
+	co.setMenuHeight(yPos);
+}
+function MenuScrollTo(entryNo) {
+	if (theBrowser.hasDHTML) {
+		var e = this.entry[entryNo];
+		if (!e) {return;}
+		var co = eval(this.container);
+		var d = this.container + '.document';
+		var srTop = getDHTMLObjTop(getDHTMLObj(d, 'entryDIV' + entryNo));
+		var srBot = (e.nextItem > 0) ? getDHTMLObjTop(getDHTMLObj(d, 'entryDIV' + e.nextItem)) : this.maxHeight;
+		if (theBrowser.code == 'MSIE') {
+			var curTop = co.document.body.scrollTop;
+			var curBot = curTop + co.document.body.clientHeight;
+		} else {
+			var curTop = co.pageYOffset;
+			var curBot = curTop + co.innerHeight;
+		}
+		if ((srBot > curBot) || (srTop < curTop)) {
+			var scrBy = srBot - curBot;
+			if (srTop < (curTop + scrBy)) {scrBy = srTop - curTop;}
+			co.setTimeout('self.scrollBy(0, ' + scrBy + ');', 100);
+		}
+	} else {
+		var l = fixPath(eval(this.container).location.pathname) + '#joustEntry' + entryNo;
+		setTimeout(this.container + '.location.href = "' + l + '";', 100);
+	}
+}
+function MenuItemClicked(entryNo, fromToggle) {
+	var r = true;
+	var e = this.entry[entryNo];
+	var w = this.contentWin();
+	var b = theBrowser;
+
+	this.selectEntry(entryNo);
+	if (this.wizardInstalled) {w.menuItemClicked(entryNo);}
+	if(e.onClickFunc) {e.onClick = e.onClickFunc;}
+	if(e.onClick) {var me=e;if(eval(e.onClick) == false) {r = false;}}
+	if (r) {
+		if (((this.toggleOnLink) && (e.FirstChild != -1) && !(fromToggle)) || e.noOutlineImg) {
+			if (b.hasDHTML) {
+				this.toggle(entryNo, true);
+			} else {
+				setTimeout(this.name + '.toggle(' + entryNo + ', true);', 100);
+			}
+		}
+	}
+	return (e.url != '') ? r : false;
+}
+function MenuSelectEntry(entryNo) {
+	var oe = this.entry[this.selectedEntry];
+	if (oe) {oe.setSelected(false);}
+	var e = this.entry[entryNo];
+	if (e) {e.setSelected(true);}
+	this.selectedEntry = entryNo;
+}
+function MenuSetEntry(entryNo, state) {
+	var cl = ',' + entryNo + ',';
+	var e = this.entry[entryNo];
+	this.lastPMClicked = entryNo;
+	var mc = e.setIsOpen(state);
+	var p = e.parent;
+	while (p >= 0) {
+		cl += p + ',';
+		e = this.entry[p];
+		mc |= (e.setIsOpen(true));
+		p = e.parent;
+	}
+	if (this.modalFolders) {
+		for (var i = 0; i <= this.count; i++) {
+			e = this.entry[i];
+			if ((cl.indexOf(',' + i + ',') < 0) && e) {mc |= e.setIsOpen(false);}
+		}
+	}
+	return mc;
+}
+function MenuSetEntryByURL(theURL, state) {
+	var i = this.findEntry(theURL, 'url', 'right', 0);
+	return (i != -1) ? this.setEntry(i, state) : false;
+}
+function MenuSetAllChildren(state, parentID) {
+	var hasChanged = false;
+	var currEntry = (parentID > -1) ? this.entry[parentID].FirstChild : this.firstEntry;
+	while (currEntry > -1) {
+		var e = this.entry[currEntry];
+		hasChanged |= e.setIsOpen(state);
+		if (e.FirstChild > -1) {hasChanged |= this.setAllChildren(state, currEntry);}
+		currEntry = e.nextItem;
+	}
+	return hasChanged;
+}
+function MenuSetAll(state, parentID) {
+	if (theBrowser.version >= 4) {
+		if (parentID == 'undefined') {parentID = -1;}
+	} else {
+		if (parentID == null) {parentID = -1;}
+	}
+	var hasChanged = false;
+	if (parentID > -1) {hasChanged |= this.entry[parentID].setIsOpen(state);}
+	hasChanged |= this.setAllChildren(state, parentID);
+	if (hasChanged) {
+		this.lastPMClicked = this.firstEntry;
+		this.refresh();
+	}
+}
+function MenuOpenAll() {this.setAll(true, -1);}
+function MenuCloseAll() {this.setAll(false, -1)}
+function MenuFindEntry(srchVal, srchProp, matchType, start) {
+	var e;
+	var sf;
+	if (srchVal == "") {return -1;}
+	if (!srchProp) {srchProp = "url";}
+	if (!matchType) {matchType = "exact";}
+	if (!start) {start = 0;}
+	if (srchProp == "URL") {srchProp = "url";}
+	if (srchProp == "title") {srchProp = "text";}
+	eval("sf = cmp_" + matchType);
+	for (var i = start; i <= this.count; i++) {
+		if (this.entry[i]) {
+			e = this.entry[i];
+			if (sf(eval("e." + srchProp), srchVal)) {return i;}
+		}		
+	}
+	return -1;
+}
+function cmp_exact(c, s) {return (c == s);}
+function cmp_left(c, s) {
+	var l = Math.min(c.length, s.length);
+	return ((c.substring(1, l) == s.substring(1, l)) && (c != ""));
+}
+function cmp_right(c, s) {
+	var l = Math.min(c.length, s.length);
+	return ((c.substring(c.length-l) == s.substring(s.length-l)) && (c != ""));
+}
+function cmp_contains(c, s) {return (c.indexOf(s) >= 0);}
+function MenuToggle(entryNo, fromClicked) {
+	var r = true;
+	var e = this.entry[entryNo];
+	if (e.onToggle) {var me=e;if(eval(e.onToggle) == false) {r = false;}}
+	if (r) {
+		var chg = this.setEntry(entryNo, e.isopen ^ 1);
+		if (this.linkOnExpand && e.isopen) {
+			if (e.url != '') {loadURLInTarget(e.url, e.target);}
+			if (!fromClicked) {this.itemClicked(entryNo, true);}
+		}
+		if (chg) {this.refresh();}
+	}
+	return false;
+}
+// Other functions
+function DrawMenu(m) {
+	m.draw();
+}
+function browserInfo() {
+	this.code = 'unknown';
+	this.version = 0;
+	this.platform = 'Win';
+	var ua = navigator.userAgent;
+	var i = ua.indexOf('WebTV');
+	if (i >= 0) {
+		this.code = 'WebTV';
+		i += 6;
+	} else {
+		i = ua.indexOf('Opera');
+		if (i >= 0) {
+			this.code = 'OP';
+			i = ua.indexOf(') ') + 2;
+		} else {
+			i = ua.indexOf('MSIE');
+			if (i >= 0) {
+				this.code = 'MSIE';
+				i += 5;
+			} else {
+				i = ua.indexOf('Mozilla/');
+				if (i >= 0) {
+					this.code = 'NS';
+					i += 8;
+				}
+			}
+		}
+	}
+	this.version = parseFloat(ua.substring(i, i+4));
+	if (ua.indexOf('Mac') >= 0) {this.platform = 'Mac';}
+	if (ua.indexOf('OS/2') >= 0) {this.platform = 'OS/2';}
+	if (ua.indexOf('X11') >= 0) {this.platform = 'UNIX';}
+	var v = this.version;
+	var p = this.platform;
+	var NS = (this.code == 'NS');
+	var IE = (this.code == 'MSIE');
+	var WTV = (this.code == 'WebTV');
+	var OP = (this.code == 'OP');
+	var OP32up = (OP && (v >= 3.2));
+	var OP5up = (OP && (v >= 5));
+	var IE4up = (IE && (v >= 4));
+	var NS3up = (NS && (v >= 3));
+	var NS6up = (NS && (v >= 5));
+	this.canCache = NS3up || IE4up || OP32up || WTV;
+	this.canOnMouseOut = this.canCache;
+	this.canOnError = NS3up || IE4up || OP32up;
+	this.canJSVoid = !((NS && !NS3up) || (IE && !IE4up) || (OP && (v < 3.5)));
+	this.lineByLine = (v < 4);
+	this.mustMoveAfterLoad = NS3up || (IE4up && (p != 'Mac')) || WTV;
+	if (NS6up == true) {
+		this.reloadMethod = 'reload';
+	} else {
+		if (NS3up || IE4up || WTV || OP5up) {
+			this.reloadMethod = 'replace';
+		} else {
+			this.reloadMethod = (NS && (v == 2.01) && (p != 'Win')) ? 'timeout' : 'href';
+		}
+	}
+	this.needsMenuSearch = (OP && !OP5up);
+	this.canFloat = NS || (IE && !((p == 'Mac') && (v >= 4) && (v < 5)));
+	this.hasDHTML = ((NS || IE) && (v >= 4)) && !(IE && (p == 'Mac') && (v < 4.5));
+	this.slowDHTML = IE4up || NS6up;
+	this.hasW3CDOM = (document.getElementById) ? true : false;
+	this.needLM = (!this.hasW3CDOM && NS) || (IE && (p == 'Mac') && (v >= 4.5));
+	this.DHTMLRange = IE ? '.all' : '';
+	this.DHTMLStyleObj = IE ? '.style' : '';
+	this.DHTMLDivHeight = IE ? '.offsetHeight' : '.clip.height';
+}
+function getWindow() {return (floatingMode) ? myOpener : self;}
+function setStatus(theText) {
+	var theWindow = getWindow();
+	if (theWindow) {
+		theWindow.status = theText;
+		if (!theBrowser.canOnMouseOut) {
+			clearTimeout(statusTimeout);
+			statusTimeout = setTimeout('clearStatus()', 5000);
+		}
+	}
+	return true;
+}
+function clearStatus() {
+	var theWindow = getWindow();
+	if (theWindow) {theWindow.status = '';}
+}
+function unloadFloating() {
+	if (myOpener) {
+		if (myOpener.JoustFrameset) {myOpener.setTimeout('menuClosed();', 100);}
+	}
+}
+function getMode() {
+	var theMode = getParm(document.cookie, 'mode', ';');
+	return ((theMode == "Floating") || (theMode == "NoFrames")) ? theMode : "Frames";
+}
+function smOnError (msg, url, lno) {
+	smCallerWin.onerror = oldErrorHandler;
+	if (confirm(smSecurityMsg)) {setTimeout('setMode("' + smNewMode + '");', 100);}
+	return true;
+}
+function smSetCookie(theMode) {
+	document.cookie = 'mode=' + theMode + '; path=/';
+	if (getMode() != theMode) {
+		alert(smCookieMsg);
+		return false;
+	} else {
+		return true;
+	}
+}
+function setMode(theMode, callerWin) {
+	smNewMode = theMode
+	smCallerWin = (theBrowser.code == 'NS') ? callerWin : self;
+	var okToGo = true;
+	var currentMode = getMode();
+	if (theMode != currentMode) {
+		if (currentMode == 'Floating') {
+			if (smSetCookie(theMode)) {self.close();}
+		} else {
+			var dest = '';
+			if (theBrowser.canFloat) {
+				if ((theMenu.savePage) && (callerWin)) {
+					if (theBrowser.canOnError) {
+						oldErrorHandler = smCallerWin.onerror;
+						smCallerWin.onerror = smOnError;
+					}
+					var l = theMenu.contentWin().location;
+					var p = l.pathname;
+					if (theBrowser.canOnError) {smCallerWin.onerror = oldErrorHandler;}
+					if (p) {
+						dest = fixPath(p) + l.search;
+					} else {
+						if (!confirm(smSecurityMsg)) {okToGo = false;}
+					}
+				}
+			} else {
+				okToGo = false;
+			}
+			if (okToGo && smSetCookie(theMode)) {
+				if (theMode == 'NoFrames') {
+					location.href = (index3 == '') ? ((dest == '') ? '/' : dest) : index3;
+				} else {
+					location.href = 'index2.htm' + ((dest == '') ? '' : '?page=' + escape(dest));
+				}
+			}
+		}
+	}
+}
+function fixPath(p) {
+	var i = p.indexOf('?', 0);
+	if (i >= 0) {p = p.substring(0,i);}
+	if (p.substring(0,2) == '/:') {p = p.substring(p.indexOf('/', 2), p.length);}
+	i = p.indexOf('\\', 0);
+	while (i >= 0) {
+		p = p.substring(0,i) + '/' + p.substring(i+1,p.length);
+		i = p.indexOf('\\', i);
+	}
+	return p;
+}
+function fileFromPath(p) {
+	p = fixPath(p);
+	var i = p.lastIndexOf('\\');
+	if (i >= 0) {p = p.substring(i+1,p.length);}
+	return p;
+}
+function getParm(theStr, parm, delim) {
+	// returns value of parm from string
+	if (theStr.length == 0) {return '';}
+	var sPos = theStr.indexOf(parm + "=");
+	if (sPos == -1) {return '';}
+	sPos = sPos + parm.length + 1;
+	var ePos = theStr.indexOf(delim, sPos);
+	if (ePos == -1) {ePos = theStr.length;}
+	return unescape(theStr.substring(sPos, ePos));
+}
+function pageFromSearch(def, m, selIt) {
+	var s = self.location.search;
+	if ((s == null) || (s.length <= 1)) {return def;}
+	var p = getParm(s, 'page', '&');
+	p = (p != '') ? fixPath(p) : def;
+	if (m != null) {
+		var e = m.findEntry(p, 'URL', 'exact');
+		if ((e != -1) && selIt) {
+			m.setEntry(e, true);
+			m.selectEntry(e);
+		}
+	}
+	return p;
+}
+function loadURLInTarget(u, t) {
+	var w = eval("self." + t);
+	if (!w && myOpener) {w = eval("myOpener." + t);}
+	if (!w && ("_top,_parent,_self".indexOf(t) >= 0)) {
+		w = eval("getWindow()." + t.substring(1));}
+	if (w) {w.location.href = u;} else {window.open(u, t);}
+}
+function defOnError(msg, url, lno) {
+	if (jsErrorMsg == '') {
+		return false;
+	} else {
+		alert(jsErrorMsg + '.\n\nError: ' + msg + '\nPage: ' + url + '\nLine: ' + lno + '\nBrowser: ' + navigator.userAgent);
+		return true;
+	}
+}
+function defaultResizeHandler() {
+	if ((theBrowser.code == "NS") && theBrowser.hasDHTML && (self.frames.length != 0)) {
+		if (!eval(theMenu.container + ".document.menuBottom")) {
+			theMenu.reload();
+		}
+	}
+}
+// Declare global variables
+var theBrowser = new browserInfo;
+
+var jsErrorMsg = 'A JavaScript error has occurred on this page!  Please note down the ';
+jsErrorMsg += 'following information and pass it on to the Webmaster.';
+if (theBrowser.canOnError) {self.onerror = defOnError;}
+
+var theMenu = new Menu;
+var JoustFrameset = true;
+var statusTimeout = 0;
+var index1 = 'index.htm';
+var smCallerWin;
+var smNewMode;
+var oldErrorHandler;
+var smNoFloat = 'Sorry, your browser does not support this feature!';
+var smCookieMsg = 'You must have Cookies enabled to change the display mode!';
+var smSecurityMsg = 'Due to security restrictions imposed by your browser, I cannot ';
+smSecurityMsg += 'change modes while a page from another server is being displayed. ';
+smSecurityMsg += 'The default home page for this site will be displayed instead.';
+
+var floatingMode = (getMode() == 'Floating');
+var myOpener = null;
+if (floatingMode == true) {
+	if (self.opener) {
+		myOpener = self.opener;
+		if (myOpener.JoustFrameset) {myOpener.setTimeout('setGlobals();', 100);}
+	} else {
+		document.cookie = 'mode=Frames; path=/';
+		floatingMode = false;
+	}
+} else {
+	if (getMode() != 'Frames') {document.cookie = 'mode=Frames; path=/';}
+}
+
+//	############################   End of Joust   ############################
+
+function initOutlineIcons(imgStore) {
+	var ip = 'imgmenu/';
+	imgStore.add('iconPlusTop', ip + 'plustop.gif', 18, 16);
+	imgStore.add('iconPlus', ip + 'plus.gif', 18, 16);
+	imgStore.add('iconPlusBottom', ip + 'plusbottom.gif', 18, 16);
+	imgStore.add('iconPlusOnly', ip + 'plusonly.gif', 18, 16);
+	imgStore.add('iconMinusTop', ip + 'minustop.gif', 18, 16);
+	imgStore.add('iconMinus', ip + 'minus.gif', 18, 16);
+	imgStore.add('iconMinusBottom', ip + 'minusbottom.gif', 18, 16);
+	imgStore.add('iconMinusOnly', ip + 'minusonly.gif', 18, 16);
+	imgStore.add('iconLine', ip + 'line.gif', 18, 16);
+	imgStore.add('iconBlank', ip + 'blank.gif', 18, 16);
+	imgStore.add('iconJoinTop', ip + 'jointop.gif', 18, 16);
+	imgStore.add('iconJoin', ip + 'join.gif', 18, 16);
+	imgStore.add('iconJoinBottom', ip + 'joinbottom.gif', 18, 16);
+
+	//Add folder and document images to the imgStore.
+	imgStore.add('Folder', ip + 'folderclosed.gif', 18, 16);
+	
+	var di = 'imgmenu/';
+	imgStore.add('Document', di + 'doc.gif', 18, 16);
+	imgStore.add('DocumentMouseOver', di + 'doc_mo.gif', 18, 16);
+	imgStore.add('DocumentSelected', di + 'doc_sel.gif', 18, 16);
+}
+
+self.defaultStatus = "";
+
+//-->
+</script>
+
+<SCRIPT src="menu.js" type=text/javascript>
+</SCRIPT>
+
+</HEAD>
+<SCRIPT LANGUAGE="JavaScript">
+<!--
+if (self.name == 'menu') {
+	// Sometimes, Netscape will try to load this index inside the menu frame.  I haven't
+	// worked out why but this will detect that situation and reset the location property.
+	self.location.href = "menu.htm";
+} else {
+	initialise();
+	var thePage = pageFromSearch('content.htm', theMenu, true);
+	
+	if (floatingMode) {
+		self.document.writeln('<frameset cols="100%" rows="*,48" onUnload="unloadFloating();" onResize="defaultResizeHandler();">');
+		self.document.writeln('<frame name="menu" src="menu.htm" scrolling="auto" marginwidth="1" marginheight="1" APPLICATION="yes">');
+		self.document.writeln('</frameset>');
+	} else {
+		self.document.writeln('<frameset cols="230,*" rows="100%">');
+		self.document.writeln('<frameset cols="100%" rows="45,35,*" frameborder=0 framespacing=0 border=0>');
+			self.document.writeln('<frame name="buttons" src="buttons.htm" scrolling="no" marginwidth="10" marginheight="5">');
+			self.document.writeln('<frame name="headline" src="head.htm" scrolling="no" marginwidth="10" marginheight="5">');
+			self.document.writeln('<frame name="menu" src="menu.htm" scrolling="auto" marginwidth="1" marginheight="1" APPLICATION="yes">');
+		self.document.writeln('</frameset>');
+		self.document.writeln('<frame name="text" src="' + thePage +'" scrolling="auto" APPLICATION="yes">');
+		self.document.writeln('</frameset>');
+	}
+}
+//-->
+</SCRIPT>
+<NOSCRIPT>
+<BODY BGCOLOR="#FFFFCC">
+<P>Your browser does not support JavaScript (if you are using Netscape 3 or higher or Microsoft Internet
+Explorer 4 or higher you may have JavaScript turned off in your preferences), so this page,
+does not include site navigation features. If you use
+a JavaScript-capable browser, such as Microsoft <A HREF="http://microsoft.com/ie/ie.htm">Internet
+Explorer version 3.0</A> or <A HREF="http://www.netscape.com/comprod/mirror/">Netscape Navigator
+version 2.0</A>, you'll have a much more pleasant experience navigating around this site.</P>
+
+<P><I><B>Opera Users:</B> Although Opera 3.0 supports JavaScript, there is a bug in their implementation 
+which prevents the menu system on this site from working.  Opera 3.2 fixes the problem.</I></P>
+
+<P><I><B>Note:</B> There is a know bug in Netscape Navigator version 4.0.x which will cause you to see this message
+if you have the local cache turned off.</I></P>
+
+<P>A non-JavaScript version do not exist</P>
+</BODY>
+</NOSCRIPT>
+
+</HTML>
\ No newline at end of file
diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/library/transistor_pnpMPA~bsim3_dc_cv_extract~spectre.scs b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/library/transistor_pnpMPA~bsim3_dc_cv_extract~spectre.scs
new file mode 100644
index 00000000..8d1ce9fe
--- /dev/null
+++ b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/library/transistor_pnpMPA~bsim3_dc_cv_extract~spectre.scs
@@ -0,0 +1,82 @@
+*******************************************************************************
+* pnpMPA section
+*******************************************************************************
+* 16.03.15 A.R.: update
+* 20.12.22 GGF update
+
+*simulator lang=spectre
+
+* SPECTRE-Parameter pnpMPA
+*--------------------------------------------------
+* Testfield: T323
+* Technology: SG13
+* Lot: PQA701
+* Wafer: 17
+* DUT: diode_pp=pnpMPA
+* Temperature range: -40C ... +125C
+* Date: Q4/22
+* Remarks:
+* DC Measurements at T=27C, T=-40C and T=125C (2013), 2022 only T=27C
+* CV Measurements at T=27C
+*
+*--------------------------------------------------------------------------
+*
+parameters isc0 = 2.576e-023  ikr0 = 3.882e-007  rc0 = 1.489e+004  
++ is_0 =  3.8e-019
++ bf_0 = 1.659
++ cje_0 = 8.716e-016
++ ccb0 = 76.28e-018
++ re_0 = 20
++ rb0 = 24.86
++ sgp_mpa_is =1
++ sgp_mpa_bf =1
++ sgp_mpa_cje =1
++ sgp_mpa_cjc =1
++ sgp_mpa_re =1
++ sgp_mpa_rb =1
+
+
+inline subckt pnpMPA E B C
+parameters a=204f p=1.96u ac=5.98p pc=9.8u DEV_A=a*1e12 DEV_P=p*1e6 sub_A=ac*1e12 sub_P=pc*1e6
+*
+pnpMPA (C B E C) pnpMPA_mod area = DEV_A
+model pnpMPA_mod bjt
++ type = pnp
++ tnom = 27
++ is = is_0*sgp_mpa_is
++ nf = 1.015
++ ise = 1e-022
++ ne = 1
++ bf = bf_0*sgp_mpa_bf
++ ikf = 0.0004695
++ vaf = 100
++ nr = 1
++ isc = (isc0*(sub_A))/(DEV_A)
++ nc = 1
++ br = 5.781e-005
++ ikr = (ikr0*(sub_A))/(DEV_A)
++ var = 150
++ rb = rb0*sgp_mpa_rb
++ irb = 1e-015
++ rbm = 0.9*rb0
++ re = re_0*sgp_mpa_re
++ rc = (rc0/(sub_A))*(DEV_A)
++ cje = cje_0*sgp_mpa_cje
++ vje = 0.61
++ mje = 0.3213
++ cjc = ccb0*(sub_A/DEV_A)*sgp_mpa_cjc
++ vjc = 0.5111
++ mjc = 0.455
++ cjs = 0
++ vjs = 0.95
++ mjs = 0.5
++ xtb = 2.44
++ xti = 2.538
++ eg = 1.17
++ trm1 = 0.001
++ trm2 = 0
++ trc1 = -0.01121
++ trc2 = 3.02E-005
++ tre1 = 0
++ tre2 = 0
+ends pnpMPA
diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/library/transistor_pnpMPA~bsim3_dc_cv_extract~spectre.scs~ b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/library/transistor_pnpMPA~bsim3_dc_cv_extract~spectre.scs~
new file mode 100644
index 00000000..1e2acd62
--- /dev/null
+++ b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/library/transistor_pnpMPA~bsim3_dc_cv_extract~spectre.scs~
@@ -0,0 +1,61 @@
+*--------------------------------------------------
+* Testfield: T270
+* Technology: SG13
+* Lot: PQT401
+* Wafer: 19
+* DUT: pnpMPA
+* Temperature range: -40C ... +125C
+* Date: 25.02.2013
+* Remarks: no scaling
+* DC Measurements  at T=27C, T=-40C and T=125C
+* CV Measurements at T=27C
+*--------------------------------------------------
+*
+parameters ccb0 = 76.28e-018  isc0 = 2.576e-023  ikr0 = 3.882e-007  rc0 = 1.489e+004  rb0 = 24.86
+*
+*
+inline subckt pnpMPA E B C
+parameters a=204f p=1.96u ac=5.98p pc=9.8u
+*parameters DEV_A=0.3 DEV_P=2.6 sub_A=6.716 sub_P=10.44  (real area and perim)
+parameters DEV_A=a*1e12 DEV_P=p*1e6 sub_A=ac*1e12 sub_P=pc*1e6
+*
+pnpMPA (C  B E C ) pnpMPA_mod area = DEV_A
+model pnpMPA_mod bjt
++ type = pnp
++ is = 3.8e-019
++ nf = 1.015
++ ise = 1e-022
++ ne = 1
++ bf = 1.659
++ ikf = 0.0004695
++ vaf = 100
++ nr = 1
++ isc = (isc0*(sub_A))/(DEV_A)
++ nc = 1
++ br = 5.781e-005
++ ikr = (ikr0*(sub_A))/(DEV_A)
++ var = 150
++ rb = rb0
++ irb = 1e-015
++ rbm = 0.9*rb0
++ re = 20
++ rc = (rc0/(sub_A))*(DEV_A)
++ cje = 8.716e-016
++ vje = 0.61
++ mje = 0.3213
++ cjc = (ccb0*(sub_A))/(DEV_A)
++ vjc = 0.5111
++ mjc = 0.455
++ cjs = 0
++ vjs = 0.95
++ mjs = 0.5
++ xtb = 2.44
++ xti = 2.538
++ eg = 1.17
++ trm1 = 0.001
++ trm2 = 0
++ trc1 = -0.01121
++ trc2 = 3.02E-005
++ tre1 = 0
++ tre2 = 0
+ends pnpMPA
diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/menu.htm b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/menu.htm
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index 00000000..ba788c28
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@@ -0,0 +1,210 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2 Final//EN">
+<HTML>
+<HEAD>
+<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=utf-8">
+<TITLE>The Joust Outliner - The Menu</TITLE>
+<META NAME="ROBOTS" CONTENT="NOINDEX,NOFOLLOW">
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+<STYLE ID="JoustStyles" TYPE="text/css">
+<!--
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+Joust Outliner Version 2.5.4
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+}
+function setBottom() {
+	if (theMenu) {
+		if (theBrowser.hasDHTML) {
+			var mb = getDHTMLObj('menuBottom');
+			if (mb) {
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+<!-- Place anything you want to appear before the menu between these DIV tags. -->
+<FONT FACE="Helvetica, ARIAL, MS SANS SERIF, SANS-SERIF" SIZE="1">
+</FONT></DIV>
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+<SCRIPT LANGUAGE="JavaScript">
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+<SCRIPT LANGUAGE="JavaScript">
+<!--
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diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/menu.js b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/menu.js
new file mode 100644
index 00000000..32a7e2be
--- /dev/null
+++ b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/menu.js
@@ -0,0 +1,60 @@
+//
+// Define the behaviour of the tree, specify the structure of
+// the web site and setup the menu entries
+//
+// Joust Outliner Version 2.4.1
+// (c) Copyright 1996-1999, Alchemy Computing Limited. All rights reserved.
+// This code may be freely copied and distributed provided that it is accompanied by this header.
+//
+// Do not modify anything between here and the "End of Joust" marker unless you know what you
+// are doing.  You can find the latest version of Joust and all associated files and help at
+// http://www.alchemy-computing.co.uk/joust/.  If you have any questions/problems or you want to be
+// added to the Joust mailing list, send an eMail to joust@alchemy.demon.co.uk.
+//
+// Window Tilte
+document.write("<title>pnpMPA (SG13)</title>");
+function initialise() {
+// Tell joust where to find the various index files it needs
+index1 = "index.htm";
+// Set up parameters to control menu behaviour
+theMenu.autoScrolling = true;
+theMenu.modalFolders = false;
+theMenu.linkOnExpand = false;
+theMenu.toggleOnLink = false;
+theMenu.showAllAsLinks = false;
+theMenu.savePage = true;
+theMenu.tipText = "status";
+theMenu.selectParents = false;
+theMenu.name = "theMenu";
+theMenu.container = "self.menu";
+theMenu.reverseRef = "parent";
+theMenu.contentFrame = "text";
+theMenu.defaultTarget = "text";
+// Initialise all the icons
+initOutlineIcons(theMenu.imgStore);
+// Now set up the menu with a whole lot of addEntry and addChild function calls
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diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/results/imgzoom/nwell_to_substrate.png b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/results/imgzoom/nwell_to_substrate.png
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index 00000000..d91736b9
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diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/results/library_transistor_pnpMPA.htm b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/results/library_transistor_pnpMPA.htm
new file mode 100644
index 00000000..3ed232ec
--- /dev/null
+++ b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/results/library_transistor_pnpMPA.htm
@@ -0,0 +1,6 @@
+<html>
+<head><title>Library</title></head>
+<frameset>
+  <frame src="../library/transistor_pnpMPA~bsim3_dc_cv_extract~spectre.scs">
+</frameset>
+</html>
diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/results/result_c_PSD_nwell.htm b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/results/result_c_PSD_nwell.htm
new file mode 100644
index 00000000..77b083cb
--- /dev/null
+++ b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/results/result_c_PSD_nwell.htm
@@ -0,0 +1,61 @@
+
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html>
+<head>
+<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=utf-8">
+<title>Junction Capacitance: PSD to Nwell</title>
+<SCRIPT LANGUAGE="JavaScript">
+var wImgOrg=0;
+var wImgPrint="300";
+var usePrintZoom=1;
+var d=new Array();
+var b=new Array();
+d[0]="images/";
+d[1]="imgzoom/";
+b[0] = "PSD_nwell_area.png";
+b[1] = "PSD_nwell_perim.png";
+function setPrintZoom(isZoom)
+{ var nImg=document.images.length;
+  if (wImgOrg==0) wImgOrg=document.images[0].width;
+  if (isZoom==0) wImg=wImgOrg;
+    else wImg=wImgPrint;
+  for (i=0;i<nImg;i++)
+  { if (b[i]!="")
+    { document.images[i].src=d[isZoom]+b[i];
+      document.images[i].width=wImg;
+    }
+    else document.images[i].width=wImg*2;
+  }
+}
+function showImg(imgSrc, H, W, Caption) {
+var newImg = window.open("","myImg",config="height="+H+",width="+W+"")
+newImg.document.write("<title>"+ Caption +"</title>")
+newImg.document.write("<img src='"+ imgSrc +"' height='"+ H +"' width='"+ W +"' onclick='window.close()' style='position:absolute;left:0;top:0'>")
+newImg.document.write("<script type='text/javascript'> document.oncontextmenu = new Function(\"return false\") </sc"+"ript>")
+newImg.document.close()
+}
+
+
+window.onunload=function(){
+
+}
+
+</SCRIPT>
+</head>
+<body bgcolor="FFFFFF">
+<h5>Capacitance: PSD to Nwell &nbsp;</h5>
+<table border="1" cellspacing="0" cellpadding="10">
+<tr>
+<td align="center" valign="top">
+  <img src="images/PSD_nwell_area.png" onclick="showImg('imgzoom/PSD_nwell_area.png',508, 800,'area');">
+<body bgcolor="FFFFFF">
+<p> C_Area: DEV_A=3.75E4 , &nbsp; DEV_P=850 </p>
+</td>
+<td align="center" valign="top">
+  <img src="images/PSD_nwell_perim.png" onclick="showImg('imgzoom/PSD_nwell_perim.png',508, 800,'perim');">
+<p>C_Perim: DEV_A=2.856E4 , &nbsp; DEV_P=1.024E5</p>
+</td>
+</tr>
+</table>
+</body>
+</html>
\ No newline at end of file
diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/results/result_c_nwell_sub.htm b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/results/result_c_nwell_sub.htm
new file mode 100644
index 00000000..518b8537
--- /dev/null
+++ b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/results/result_c_nwell_sub.htm
@@ -0,0 +1,55 @@
+
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html>
+<head>
+<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=utf-8">
+<title>Junction Capacitance: Nwell to Substrate</title>
+<SCRIPT LANGUAGE="JavaScript">
+var wImgOrg=0;
+var wImgPrint="300";
+var usePrintZoom=1;
+var d=new Array();
+var b=new Array();
+d[0]="images/";
+d[1]="imgzoom/";
+b[0] = "c_bd_area.png";
+b[1] = "d_bd_d_bd_area_log.png";
+function setPrintZoom(isZoom)
+{ var nImg=document.images.length;
+  if (wImgOrg==0) wImgOrg=document.images[0].width;
+  if (isZoom==0) wImg=wImgOrg;
+    else wImg=wImgPrint;
+  for (i=0;i<nImg;i++)
+  { if (b[i]!="")
+    { document.images[i].src=d[isZoom]+b[i];
+      document.images[i].width=wImg;
+    }
+    else document.images[i].width=wImg*2;
+  }
+}
+function showImg(imgSrc, H, W, Caption) {
+var newImg = window.open("","myImg",config="height="+H+",width="+W+"")
+newImg.document.write("<title>"+ Caption +"</title>")
+newImg.document.write("<img src='"+ imgSrc +"' height='"+ H +"' width='"+ W +"' onclick='window.close()' style='position:absolute;left:0;top:0'>")
+newImg.document.write("<script type='text/javascript'> document.oncontextmenu = new Function(\"return false\") </sc"+"ript>")
+newImg.document.close()
+}
+
+
+window.onunload=function(){
+
+}
+
+</SCRIPT>
+</head>
+<body bgcolor="FFFFFF">
+<h5>Capacitance: Nwell to Substrate &nbsp;(sub_A=1209000 , &nbsp; sub_P=4884)</h5>
+<table border="1" cellspacing="0" cellpadding="10">
+<tr>
+<td align="center" valign="top">
+  <img src="images/nwell_to_substrate.png" onclick="showImg('imgzoom/nwell_to_substrate.png',498,623,'nwell_to_substrate');">
+</td>
+</tr>
+</table>
+</body>
+</html>
\ No newline at end of file
diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/results/result_c_pnpMPA.htm b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/results/result_c_pnpMPA.htm
new file mode 100644
index 00000000..4bfedf6e
--- /dev/null
+++ b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/results/result_c_pnpMPA.htm
@@ -0,0 +1,56 @@
+
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html>
+<head>
+<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=utf-8">
+<title>Junction Capacitance: C_pnpMPA</title>
+<SCRIPT LANGUAGE="JavaScript">
+var wImgOrg=0;
+var wImgPrint="300";
+var usePrintZoom=1;
+var d=new Array();
+var b=new Array();
+d[0]="images/";
+d[1]="imgzoom/";
+b[0] = "C_pnpMPA.png";
+b[1] = "C_pnpMPA.png";
+function setPrintZoom(isZoom)
+{ var nImg=document.images.length;
+  if (wImgOrg==0) wImgOrg=document.images[0].width;
+  if (isZoom==0) wImg=wImgOrg;
+    else wImg=wImgPrint;
+  for (i=0;i<nImg;i++)
+  { if (b[i]!="")
+    { document.images[i].src=d[isZoom]+b[i];
+      document.images[i].width=wImg;
+    }
+    else document.images[i].width=wImg*2;
+  }
+}
+function showImg(imgSrc, H, W, Caption) {
+var newImg = window.open("","myImg",config="height="+H+",width="+W+"")
+newImg.document.write("<title>"+ Caption +"</title>")
+newImg.document.write("<img src='"+ imgSrc +"' height='"+ H +"' width='"+ W +"' onclick='window.close()' style='position:absolute;left:0;top:0'>")
+newImg.document.write("<script type='text/javascript'> document.oncontextmenu = new Function(\"return false\") </sc"+"ript>")
+newImg.document.close()
+}
+
+
+window.onunload=function(){
+
+}
+
+</SCRIPT>
+</head>
+<body bgcolor="FFFFFF">
+<h5>Capacitance C_pnpMPA &nbsp;( DEV_A=0.3 , &nbsp; DEV_P=2.6 , &nbsp; sub_A=6.716 , &nbsp; sub_P=10.44)</h5>
+<table border="1" cellspacing="0" cellpadding="10">
+<tr>
+<td align="center" valign="top">
+  <img src="images/C_pnpMPA.png" onclick="showImg('imgzoom/C_pnpMPA.png',508, 800,'area');">
+<body bgcolor="FFFFFF">
+</td>
+</tr>
+</table>
+</body>
+</html>
\ No newline at end of file
diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/results/result_c_pnpMPA_new.htm b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/results/result_c_pnpMPA_new.htm
new file mode 100644
index 00000000..0bc7bcf3
--- /dev/null
+++ b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/results/result_c_pnpMPA_new.htm
@@ -0,0 +1 @@
+

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">

<html>

<head>

<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=utf-8">

<title>Junction Capacitance: C_pnpMPA</title>

<SCRIPT LANGUAGE="JavaScript">

var wImgOrg=0;

var wImgPrint="300";

var usePrintZoom=1;

var d=new Array();

var b=new Array();

d[0]="images/";

d[1]="imgzoom/";

b[0] = "C_pnpMPA.png";

b[1] = "C_pnpMPA.png";

function setPrintZoom(isZoom)

{ var nImg=document.images.length;

  if (wImgOrg==0) wImgOrg=document.images[0].width;

  if (isZoom==0) wImg=wImgOrg;

    else wImg=wImgPrint;

  for (i=0;i<nImg;i++)

  { if (b[i]!="")

    { document.images[i].src=d[isZoom]+b[i];

      document.images[i].width=wImg;

    }

    else document.images[i].width=wImg*2;

  }

}

function showImg(imgSrc, H, W, Caption) {

var newImg = window.open("","myImg",config="height="+H+",width="+W+"")

newImg.document.write("<title>"+ Caption +"</title>")

newImg.document.write("<img src='"+ imgSrc +"' height='"+ H +"' width='"+ W +"' onclick='window.close()' style='position:absolute;left:0;top:0'>")

newImg.document.write("<script type='text/javascript'> document.oncontextmenu = new Function(\"return false\") </sc"+"ript>")

newImg.document.close()

}





window.onunload=function(){



}



</SCRIPT>

</head>

<body bgcolor="FFFFFF">
<h4>Junction Capacitances</h4>

<h5>Test Device: DUT16 (n x W x L = 12000 x 0.64 x 10 µm²)</h5>

<table border="1" cellspacing="1" cellpadding="10">

<tr>

<td align="center" valign="top">

  <img src="images/Cbe_pnpMPA_new.png" onclick="showImg('imgzoom/Cbe_pnpMPA_new.png',508, 800,'idvd');">

</td>


</table>

<table border="1" cellspacing="1" cellpadding="10">

<br>


<td align="center" valign="top">

  <img src="images/Ccb_pnpMPA_new.png" onclick="showImg('imgzoom/Ccb_pnpMPA_new.png',508,800,'idvd_rev');">

</td>

</table>

</td>

</tr>

</table>

</body>

</html>
\ No newline at end of file
diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/results/result_gummel_transistor_pnpMPA.htm b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/results/result_gummel_transistor_pnpMPA.htm
new file mode 100644
index 00000000..32dcc38e
--- /dev/null
+++ b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/results/result_gummel_transistor_pnpMPA.htm
@@ -0,0 +1,68 @@
+
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html>
+<head>
+<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=utf-8">
+<title>Temperature: diodevdd_2kv</title>
+<SCRIPT LANGUAGE="JavaScript">
+var wImgOrg=0;
+var wImgPrint="300";
+var usePrintZoom=1;
+var d=new Array();
+var b=new Array();
+d[0]="images/";
+d[1]="imgzoom/";
+b[0] = "forward_gummel.png";
+b[1] = "reverse_gummel.png";
+function setPrintZoom(isZoom)
+{ var nImg=document.images.length;
+  if (wImgOrg==0) wImgOrg=document.images[0].width;
+  if (isZoom==0) wImg=wImgOrg;
+    else wImg=wImgPrint;
+  for (i=0;i<nImg;i++)
+  { if (b[i]!="")
+    { document.images[i].src=d[isZoom]+b[i];
+      document.images[i].width=wImg;
+    }
+    else document.images[i].width=wImg*2;
+  }
+}
+function showImg(imgSrc, H, W, Caption) {
+var newImg = window.open("","myImg",config="height="+H+",width="+W+"")
+newImg.document.write("<title>"+ Caption +"</title>")
+newImg.document.write("<img src='"+ imgSrc +"' height='"+ H +"' width='"+ W +"' onclick='window.close()' style='position:absolute;left:0;top:0'>")
+newImg.document.write("<script type='text/javascript'> document.oncontextmenu = new Function(\"return false\") </sc"+"ript>")
+newImg.document.close()
+}
+
+
+window.onunload=function(){
+
+}
+
+</SCRIPT>
+</head>
+<body bgcolor="FFFFFF">
+<h5>pnpMPA &nbsp;( DEV_A=0.3 , &nbsp; DEV_P=2.6 , &nbsp; sub_A=6.716 , &nbsp; sub_P=10.44)  &nbsp;</h5>
+<table border="1" cellspacing="1" cellpadding="10">
+<tr>
+<td align="center" valign="top">
+  <img src="images/forward_gummel.png" onclick="showImg('imgzoom/forward_gummel.png',508, 800,'idvd');">
+</td>
+<td align="center" valign="top">
+  <img src="images/reverse_gummel.png" onclick="showImg('imgzoom/reverse_gummel.png',508,800,'idvd_rev');">
+</td>
+</table>
+<table border="1" cellspacing="1" cellpadding="10">
+<br>
+<td align="center" valign="top">
+  <img src="images/forward_gummel_vbvc.png" onclick="showImg('imgzoom/forward_gummel_vbvc.png',508, 800,'idvd');">
+<td align="center" valign="top">
+  <img src="images/beta.png" onclick="showImg('imgzoom/beta.png',508,800,'idvd_rev');">
+</td>
+</table>
+</td>
+</tr>
+</table>
+</body>
+</html>
\ No newline at end of file
diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/results/result_gummel_transistor_pnpMPA_new.htm b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/results/result_gummel_transistor_pnpMPA_new.htm
new file mode 100644
index 00000000..6c9fc4be
--- /dev/null
+++ b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/results/result_gummel_transistor_pnpMPA_new.htm
@@ -0,0 +1 @@
+

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">

<html>

<head>

<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=utf-8">

<title>pnpMPA Gummel Characteristics</title>

<SCRIPT LANGUAGE="JavaScript">

var wImgOrg=0;

var wImgPrint="300";

var usePrintZoom=1;

var d=new Array();

var b=new Array();

d[0]="images/";

d[1]="imgzoom/";

b[0] = "forward_gummel.png";

b[1] = "reverse_gummel.png";

function setPrintZoom(isZoom)

{ var nImg=document.images.length;

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    { document.images[i].src=d[isZoom]+b[i];

      document.images[i].width=wImg;

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    else document.images[i].width=wImg*2;

  }

}

function showImg(imgSrc, H, W, Caption) {

var newImg = window.open("","myImg",config="height="+H+",width="+W+"")

newImg.document.write("<title>"+ Caption +"</title>")

newImg.document.write("<img src='"+ imgSrc +"' height='"+ H +"' width='"+ W +"' onclick='window.close()' style='position:absolute;left:0;top:0'>")

newImg.document.write("<script type='text/javascript'> document.oncontextmenu = new Function(\"return false\") </sc"+"ript>")

newImg.document.close()

}





window.onunload=function(){



}



</SCRIPT>

</head>

<body bgcolor="FFFFFF">

<h4>Forward Gummel Characteristics</h4>
<h5>Golden Device: DUT7 (W x L = 1 x 2 µm²)</h5>

<table border="1" cellspacing="1" cellpadding="10">

<tr>

<td align="center" valign="top">

  <img src="images/forward_gummel_new.png" onclick="showImg('imgzoom/forward_gummel_new.png',508, 800,'Gummel');">

</td>

<td align="center" valign="top">

  <img src="images/forward_gummel_all.png" onclick="showImg('imgzoom/forward_gummel_all.png',508,800,'Gummel');">

</td>

</table>

<table border="1" cellspacing="1" cellpadding="10">

<br>

<td align="center" valign="top">

  <img src="images/beta_new.png" onclick="showImg('imgzoom/beta_new.png',508, 800,'Beta');">

<td align="center" valign="top">

  <img src="images/beta_all.png" onclick="showImg('imgzoom/beta_all.png',508,800,'Beta');">

</td>

</table>

</td>

</tr>

</table>

</body>

</html>
\ No newline at end of file
diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/results/result_output_transistor_pnpMPA.htm b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/results/result_output_transistor_pnpMPA.htm
new file mode 100644
index 00000000..598abca3
--- /dev/null
+++ b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/results/result_output_transistor_pnpMPA.htm
@@ -0,0 +1 @@
+

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">

<html>

<head>

<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=utf-8">

<title>pnpMPA Characteristics</title>

<SCRIPT LANGUAGE="JavaScript">

var wImgOrg=0;

var wImgPrint="300";

var usePrintZoom=1;

var d=new Array();

var b=new Array();

d[0]="images/";

d[1]="imgzoom/";

b[0] = "forward_gummel_new.png";

b[1] = "beta_new.png";

function setPrintZoom(isZoom)

{ var nImg=document.images.length;

  if (wImgOrg==0) wImgOrg=document.images[0].width;

  if (isZoom==0) wImg=wImgOrg;

    else wImg=wImgPrint;

  for (i=0;i<nImg;i++)

  { if (b[i]!="")

    { document.images[i].src=d[isZoom]+b[i];

      document.images[i].width=wImg;

    }

    else document.images[i].width=wImg*2;

  }

}

function showImg(imgSrc, H, W, Caption) {

var newImg = window.open("","myImg",config="height="+H+",width="+W+"")

newImg.document.write("<title>"+ Caption +"</title>")

newImg.document.write("<img src='"+ imgSrc +"' height='"+ H +"' width='"+ W +"' onclick='window.close()' style='position:absolute;left:0;top:0'>")

newImg.document.write("<script type='text/javascript'> document.oncontextmenu = new Function(\"return false\") </sc"+"ript>")

newImg.document.close()

}





window.onunload=function(){



}



</SCRIPT>

</head>

<body bgcolor="FFFFFF">

<h4>pnpMPA &nbsp;(Golden device is DUT7 with W x L = 1 x 2 µm²
)  &nbsp;</h4>

<h5>Forward Output Characteristics</h5>
<table border="1" cellspacing="1" cellpadding="10">

<tr>

<td align="center" valign="top">

  <img src="images/forward_gummel_new.png" onclick="showImg('imgzoom/forward_gummel_new.png',508, 800,'idvd');">

</td>


</table>

<table border="1" cellspacing="1" cellpadding="10">

<br>


<td align="center" valign="top">

  <img src="images/beta_new.png" onclick="showImg('imgzoom/beta_new.png',508,800,'idvd_rev');">

</td>

</table>

</td>

</tr>

</table>

</body>

</html>
\ No newline at end of file
diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/results/result_output_transistor_pnpMPA_new.htm b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/results/result_output_transistor_pnpMPA_new.htm
new file mode 100644
index 00000000..20e34453
--- /dev/null
+++ b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/results/result_output_transistor_pnpMPA_new.htm
@@ -0,0 +1 @@
+

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">

<html>

<head>

<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=utf-8">

<title>pnpMPA Output Characteristics</title>

<SCRIPT LANGUAGE="JavaScript">

var wImgOrg=0;

var wImgPrint="300";

var usePrintZoom=1;

var d=new Array();

var b=new Array();

d[0]="images/";

d[1]="imgzoom/";

b[0] = "forward_output_Veb.png";

b[1] = "forward_output_Ib_new.png";

function setPrintZoom(isZoom)

{ var nImg=document.images.length;

  if (wImgOrg==0) wImgOrg=document.images[0].width;

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  for (i=0;i<nImg;i++)

  { if (b[i]!="")

    { document.images[i].src=d[isZoom]+b[i];

      document.images[i].width=wImg;

    }

    else document.images[i].width=wImg*2;

  }

}

function showImg(imgSrc, H, W, Caption) {

var newImg = window.open("","myImg",config="height="+H+",width="+W+"")

newImg.document.write("<title>"+ Caption +"</title>")

newImg.document.write("<img src='"+ imgSrc +"' height='"+ H +"' width='"+ W +"' onclick='window.close()' style='position:absolute;left:0;top:0'>")

newImg.document.write("<script type='text/javascript'> document.oncontextmenu = new Function(\"return false\") </sc"+"ript>")

newImg.document.close()

}





window.onunload=function(){



}



</SCRIPT>

</head>

<body bgcolor="FFFFFF">



<h4>Forward Output Characteristics</h4>
<h5>Golden Device: DUT7 (W x L = 1 x 2 µm²)</h5>
<table border="1" cellspacing="1" cellpadding="10">

<tr>

<td align="center" valign="top">

  <img src="images/forward_output_Veb.png" onclick="showImg('imgzoom/forward_output_Veb.png',508, 800,'idvd');">

</td>


</table>

<table border="1" cellspacing="1" cellpadding="10">

<br>


<td align="center" valign="top">

  <img src="images/forward_output_Ib_new.png" onclick="showImg('imgzoom/forward_output_Ib_new.png',508,800,'idvd_rev');">

</td>

</table>

</td>

</tr>

</table>

</body>

</html>
\ No newline at end of file
diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/results/result_stats.htm b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/results/result_stats.htm
new file mode 100644
index 00000000..e3bd0195
--- /dev/null
+++ b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/results/result_stats.htm
@@ -0,0 +1 @@
+

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">

<html>

<head>

<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=utf-8">

<title>Monte-Carlo Statistical Data</title>

<SCRIPT LANGUAGE="JavaScript">

var wImgOrg=0;

var wImgPrint="300";

var usePrintZoom=1;

var d=new Array();

var b=new Array();

d[0]="images/";

d[1]="imgzoom/";

b[0] = "C_pnpMPA.png";

b[1] = "C_pnpMPA.png";

function setPrintZoom(isZoom)

{ var nImg=document.images.length;

  if (wImgOrg==0) wImgOrg=document.images[0].width;

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    { document.images[i].src=d[isZoom]+b[i];

      document.images[i].width=wImg;

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    else document.images[i].width=wImg*2;

  }

}

function showImg(imgSrc, H, W, Caption) {

var newImg = window.open("","myImg",config="height="+H+",width="+W+"")

newImg.document.write("<title>"+ Caption +"</title>")

newImg.document.write("<img src='"+ imgSrc +"' height='"+ H +"' width='"+ W +"' onclick='window.close()' style='position:absolute;left:0;top:0'>")

newImg.document.write("<script type='text/javascript'> document.oncontextmenu = new Function(\"return false\") </sc"+"ript>")

newImg.document.close()

}





window.onunload=function(){



}



</SCRIPT>

</head>

<body bgcolor="FFFFFF">
<h4>Monte-Carlo Statistical Data</h4>

<h5>Data from Lot PQA 701 and PQA703</h5>

<table border="1" cellspacing="1" cellpadding="10">

<tr>

<td align="center" valign="top">

  <img src="images/mc.png" onclick="showImg('imgzoom/mc.png',508, 800,'idvd');">

</td>


</table>


</td>

</tr>

</table>

</body>

</html>
\ No newline at end of file
diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/setup/cv.htm b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/setup/cv.htm
new file mode 100644
index 00000000..ed39cef9
--- /dev/null
+++ b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/setup/cv.htm
@@ -0,0 +1,33 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html>
+<head>
+<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=utf-8">
+<title>DUT Setup CV</title></head>
+<body bgcolor="FFFFFF">
+<h5>Setup of CV Test Devices</h5>
+<table border="1" cellspacing="0" cellpadding="5">
+<tr bgcolor=#C0C0C0>
+<td width="140" height="40">Name</td>
+<td width="50" align="right">Area<br>[um²]</td>
+<td width="50" align="right">Perimeter<br>[um]</td>
+</tr>
+<tr>
+<td>C_pnpMPA (sub) </td>
+<td align="right">6.716</td>
+<td align="right">10.44</td>
+</tr>
+<tr>
+<td>PSD to Nwell: area</td>
+<td align="right">37500</td>
+<td align="right">850</td>
+</tr>
+<td>PSD to Nwell: perim</td>
+<td align="right">28560</td>
+<td align="right">102400</td>
+<tr>
+<td>Nwell to substrate</td>
+<td align="right"> 1209000</td>
+<td align="right">4884</td>
+</table>
+</body>
+</html>
diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/setup/dc.htm b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/setup/dc.htm
new file mode 100644
index 00000000..eebc186d
--- /dev/null
+++ b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/setup/dc.htm
@@ -0,0 +1,24 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html>
+<head>
+<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=utf-8">
+<title>DUT Setup DC</title></head>
+<body bgcolor="FFFFFF">
+<h5>Setup of DC Test Devices</h5>
+<table border="1" cellspacing="0" cellpadding="5">
+<tr bgcolor=#C0C0C0>
+<td width="120" height="40">Name</td>
+<td width="50" align="right">W<br>[um]</td>
+<td width="50" align="right">L<br>[um]</td>
+<td width="50" align="right">Area<br>[um²]</td>
+<td width="50" align="right">Perimeter<br>[um]</td>
+  </tr><tr>
+<td>pnpMPA</td>
+<td align="right">0.3</td>
+<td align="right">1</td>
+<td align="right">0.3</td>
+<td align="right">2.6</td>
+  </tr>
+</table>
+</body>
+</html>
diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/setup/dc_new.htm b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/setup/dc_new.htm
new file mode 100644
index 00000000..e49fff1f
--- /dev/null
+++ b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/setup/dc_new.htm
@@ -0,0 +1 @@
+
<html>

<head>

<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=utf-8">

<title>DUT Setup DC</title></head>

<body bgcolor="FFFFFF">

<h5>Setup of DC Test Devices</h5>
<p>pnpMPA Test Structures on T323</p>

<table border="1" cellspacing="0" cellpadding="5">

<tr bgcolor=#C0C0C0>

<td width="80" height="40">Name</td>
<td width="80" height="40">Purpose of testing</td>
<td width="80" height="40">Number of devices</td>

<td width="80" align="center">Width, W<br>[um]</td>

<td width="80" align="center">Length, L<br>[um]</td>

<td width="80" align="center">Area, A<br>[um²]</td>

<td width="80" align="center">Perimeter, P<br>[um]</td>

  </tr>

<tr>
<td>DUT1</td>
<td align="center">Forwards & Reverse</td>
<td align="center">1</td>
<td align="center">2.00</td>
<td align="center">10.00</td>
<td align="center">20.00</td>
<td align="center">24.00</td>
</tr>

<tr>
<td>DUT2</td>
<td align="center">Forwards & Reverse</td>
<td align="center">1</td>
<td align="center">1.00</td>
<td align="center">10.00</td>
<td align="center">10.00</td>
<td align="center">22.00</td>
</tr>

<tr>
<td>DUT4</td>
<td align="center">Forwards & Reverse</td>
<td align="center">1</td>
<td align="center">1.00</td>
<td align="center">5.00</td>
<td align="center">5.00</td>
<td align="center">12.00</td>
</tr>

<tr>
<td>DUT6</td>
<td align="center">Forwards & Reverse</td>
<td align="center">1</td>
<td align="center">2.00</td>
<td align="center">2.00</td>
<td align="center">4.00</td>
<td align="center">8.00</td>
</tr>

<tr>
<td>DUT7</td>
<td align="center">Forwards & Reverse</td>
<td align="center">1</td>
<td align="center">1.00</td>
<td align="center">2.00</td>
<td align="center">2.00</td>
<td align="center">6.00</td>
</tr>

<tr>
<td>DUT8</td>
<td align="center">Forwards & Reverse</td>
<td align="center">1</td>
<td align="center">2.00</td>
<td align="center">1.00</td>
<td align="center">2.00</td>
<td align="center">6.00</td>
</tr>

<tr>
<td>DUT10</td>
<td align="center">Forwards & Reverse</td>
<td align="center">1</td>
<td align="center">1.00</td>
<td align="center">1.00</td>
<td align="center">1.00</td>
<td align="center">4.00</td>
</tr>

<tr>
<td>DUT11</td>
<td align="center">Forwards & Reverse</td>
<td align="center">1</td>
<td align="center">2.00</td>
<td align="center">0.68</td>
<td align="center">1.36</td>
<td align="center">5.36</td>
</tr>

<tr>
<td>DUT12</td>
<td align="center">Forwards & Reverse</td>
<td align="center">1</td>
<td align="center">1.00</td>
<td align="center">0.68</td>
<td align="center">0.68</td>
<td align="center">3.36</td>
</tr>

<tr>
<td>DUT16</td>
<td align="center">Capacitance</td>
<td align="center">12000</td>
<td align="center">0.64</td>
<td align="center">10.00</td>
<td align="center">76800.00</td>
<td align="center">255360.00</td>
</tr>
</table>

</body>

</html>

\ No newline at end of file
diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/setup/meas_cv.htm b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/setup/meas_cv.htm
new file mode 100644
index 00000000..9ac315d1
--- /dev/null
+++ b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/setup/meas_cv.htm
@@ -0,0 +1,38 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html>
+<head>
+<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=utf-8">
+<title>Measurement Setup</title></head>
+<body bgcolor="FFFFFF">
+<h5>Measurement Conditions for Test Devices</h5>
+<hr>
+<table border=0 width=600><tr>
+<td valign=top>
+<table border="1" cellpadding="3" cellspacing="0">
+<tr>
+<tr><td colspan=2 bgcolor=#C0C0C0><b>Device Type</strong></b></td></tr>
+<tr><td align="right">Capacitance: C_pnpMPA</td><td align="right">PMOS</td></tr>
+<tr><td align="right">Capacitance: PSD to Nwell</td><td align="right">PMOS</td></tr>
+<tr><td align="right">Capacitance: Nwell to Substrate</td><td align="right">NMOS</td></tr>
+</table>
+</td>
+<td valign=top>
+<table border="1" cellpadding="3" cellspacing="0">
+<tr><td colspan=2 bgcolor=#C0C0C0><b>Temperature Measurement</b></td></tr>
+<tr><td>TNOM</td><td align=right>27°C</td></tr>
+</table>
+</td>
+</tr></table>
+<table border=1 cellpadding="2" cellspacing="0">
+<tr><td bgcolor=#C0C0C0 colspan=7><b>Capacitances</b></td></tr>
+<tr bgcolor=#E1E1E1><td width="180">&#160</td><td width="60">Sweep</td><td width="60">Start</td><td width="60">Step</td><td width="60">Stop</td>
+<td width="60">High Node</td><td width="60">Low Node</td></tr>
+<tr><td bgcolor=#E1E1E1>C_pnpMPA</td><td>1 VHI</td><td align="right">-0.4 V</td><td align="right">0.1 V</td><td align="right">8 V</td>
+<td align="right">Nwell</td><td align="right">PSD</td></tr>
+<tr><td bgcolor=#E1E1E1>PSD to Nwell</td><td>1 VHI</td><td align="right">-0.4 V</td><td align="right">0.1 V</td><td align="right">8 V</td>
+<td align="right">Nwell</td><td align="right">PSD</td></tr>
+<tr><td bgcolor=#E1E1E1>Nwell to Substrate</td><td>1 VHI</td><td align="right">-0.4 V</td><td align="right">0.1 V</td><td align="right">8 V</td>
+<td align="right">Substrate</td><td align="right">Nwell</td>
+</table>
+</body>
+</html>
\ No newline at end of file
diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/setup/meas_pnpMPA.htm b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/setup/meas_pnpMPA.htm
new file mode 100644
index 00000000..189489b9
--- /dev/null
+++ b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/setup/meas_pnpMPA.htm
@@ -0,0 +1,62 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html>
+<head>
+<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=utf-8">
+<title>Measurement Setup</title></head>
+<body bgcolor="FFFFFF">
+<h5>Measurement Conditions for Test Devices</h5>
+<hr>
+<table border=0 width=600><tr>
+<td valign=top>
+<table border="1" cellpadding="3" cellspacing="0">
+<tr><td colspan=2 bgcolor=#C0C0C0><b>Device Type</strong></b></td></tr>
+<tr><td align="right">pnpMPA</td><td align="right">PMOS</td></tr>
+</table>
+</td>
+<td valign=top>
+<table border="1" cellpadding="3" cellspacing="0">
+<tr><td colspan=2 bgcolor=#C0C0C0><b>Temperature Measurement</b></td></tr>
+<tr><td>TNOM</td><td align=right>27°C</td></tr>
+<tr><td>Temperature 1</td><td align=right>-40°C</td></tr>
+<tr><td>Temperature 2</td><td align=right>125°C</td></tr>
+</table>
+</td>
+</tr></table>
+<br>
+<table border=1 cellpadding="2" cellspacing="0">
+<tr bgcolor=#C0C0C0><td colspan=5><b>pnpMPA transistor (gummel plots)</b></td></tr>
+<tr bgcolor=#E1E1E1><td width="100">&#160</td><td width="60">Sweep</td><td width="100">Start [V]</td><td width="100">Stop [V]</td><td width="100">No. Points</td></tr>
+<tr><td bgcolor=#E1E1E1 valign=top rowspan=2>fwd</td>
+<td valign=top>1: vb=vc</td>
+<td align="right"> 0.000 </td><td align="right"> -1.000 </td><td align="right">51</td></tr>
+<td valign=top>2: ve</td>
+<td align="right"> 0.000 </td><td align="right"> 0.000 </td><td align="right">1</td></tr>
+<tr><td bgcolor=#E1E1E1 valign=top rowspan=3>rev</td>
+<td valign=top>1: vb</td>
+<td align="right">0.000 </td><td align="right"> 1.000 </td><td align="right">131</td></tr>
+<td valign=top>2: vc</td>
+<td align="right"> 1.000 </td><td align="right"> 1.000 </td><td align="right">1</td></tr>
+<td valign=top>3: ve</td>
+<td align="right"> 0.000 </td><td align="right"> 0.000 </td><td align="right">1</td></tr>
+</table>
+<br>
+<table border=1 cellpadding="2" cellspacing="0">
+<tr bgcolor=#C0C0C0><td colspan=5><b>pnpMPA transistor (output characteristics)</b></td></tr>
+<tr bgcolor=#E1E1E1><td width="100">&#160</td><td width="60">Sweep</td><td width="100">Start [V]</td><td width="100">Stop [V]</td><td width="100">No. Points</td></tr>
+<tr><td bgcolor=#E1E1E1 valign=top rowspan=3>fwd</td>
+<td valign=top>1: vb</td>
+<td align="right"> -0.600 </td><td align="right"> -1.000 </td><td align="right">9</td></tr>
+<td valign=top>1: vc</td>
+<td align="right"> 0.000 </td><td align="right"> -5.000 </td><td align="right">51</td></tr>
+<td valign=top>2: ve</td>
+<td align="right"> 0.000 </td><td align="right"> 0.000 </td><td align="right">1</td></tr>
+<tr><td bgcolor=#E1E1E1 valign=top rowspan=3>rev</td>
+<td valign=top>1: vb</td>
+<td align="right">0.600 </td><td align="right"> 1.000 </td><td align="right">9</td></tr>
+<td valign=top>2: vc</td>
+<td align="right"> 0.000 </td><td align="right"> 0.000 </td><td align="right">1</td></tr>
+<td valign=top>3: ve</td>
+<td align="right"> 0.000 </td><td align="right"> 2.000 </td><td align="right">41</td></tr>
+</table>
+</body>
+</html>
\ No newline at end of file
diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/setup/meas_pnpMPA_new.htm b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/setup/meas_pnpMPA_new.htm
new file mode 100644
index 00000000..a4426081
--- /dev/null
+++ b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/setup/meas_pnpMPA_new.htm
@@ -0,0 +1 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">

<html>

<head>

<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=utf-8">

<title>Measurement Setup</title></head>

<body bgcolor="FFFFFF">

<h5>Measurement Conditions for Test Devices</h5>

<hr>

<table border=0 width=600><tr>

<td valign=top>

<table border="1" cellpadding="3" cellspacing="0">

<tr><td colspan=2 bgcolor=#C0C0C0><b>Device Type</strong></b></td></tr>

<tr><td align="right">pnpMPA</td><td align="right">PMOS</td></tr>

</table>

</td>

<td valign=top>

<table border="1" cellpadding="3" cellspacing="0">

<tr><td colspan=2 bgcolor=#C0C0C0><b>Temperature Measurement</b></td></tr>

<tr><td>TNOM</td><td align=right>27°C</td></tr>

</table>

</td>

</tr></table>

<br>

<table border=1 cellpadding="2" cellspacing="0">

<tr bgcolor=#C0C0C0><td colspan=5><b>pnpMPA Transistor (Gummel Plots)</b></td></tr>

<tr bgcolor=#E1E1E1><td width="100">&#160</td><td width="100">Sweep</td><td width="100">Start [V]</td><td width="100">Stop [V]</td><td width="100">No. Points</td></tr>

<tr><td bgcolor=#E1E1E1 valign=top rowspan=2>Forward</td>

<td valign=top>1: V<sub>b</sub>=V<sub>c</sub></td>

<td align="right"> 0.000 </td><td align="right"> -1.000 </td><td align="right">51</td></tr>

<td valign=top>2: V<sub>e</sub></td>

<td align="right"> 0.000 </td><td align="right"> 0.000 </td><td align="right">1</td></tr>

<tr><td bgcolor=#E1E1E1 valign=top rowspan=3>Reverse</td>

<td valign=top>1: V<sub>b</sub></td>

<td align="right">0.000 </td><td align="right"> 1.000 </td><td align="right">131</td></tr>

<td valign=top>2: V<sub>c</sub></td>

<td align="right"> 1.000 </td><td align="right"> 1.000 </td><td align="right">1</td></tr>

<td valign=top>3: V<sub>e</sub></td>

<td align="right"> 0.000 </td><td align="right"> 0.000 </td><td align="right">1</td></tr>

</table>

<br>

<table border=1 cellpadding="2" cellspacing="0">

<tr bgcolor=#C0C0C0><td colspan=5><b>pnpMPA Transistor (Output Characteristics)</b></td></tr>

<tr bgcolor=#E1E1E1><td width="100">&#160</td><td width="100">Sweep</td><td width="100">Start [V]</td><td width="100">Stop [V]</td><td width="100">No. Points</td></tr>

<tr><td bgcolor=#E1E1E1 valign=top rowspan=3>Forward</td>

<td valign=top>1: V<sub>b</sub></td>

<td align="right"> -0.600 </td><td align="right"> -1.000 </td><td align="right">9</td></tr>

<td valign=top>1: V<sub>c</sub></td>

<td align="right"> 0.000 </td><td align="right"> -5.000 </td><td align="right">51</td></tr>

<td valign=top>2: V<sub>e</sub></td>

<td align="right"> 0.000 </td><td align="right"> 0.000 </td><td align="right">1</td></tr>

<tr><td bgcolor=#E1E1E1 valign=top rowspan=3>Reverse</td>

<td valign=top>1: V<sub>b</sub></td>

<td align="right">0.600 </td><td align="right"> 1.000 </td><td align="right">9</td></tr>

<td valign=top>2: V<sub>c</sub></td>

<td align="right"> 0.000 </td><td align="right"> 0.000 </td><td align="right">1</td></tr>

<td valign=top>3: V<sub>e</sub></td>

<td align="right"> 0.000 </td><td align="right"> 2.000 </td><td align="right">41</td></tr>

</table>

</body>

</html>
\ No newline at end of file
diff --git a/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/word.htm b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/word.htm
new file mode 100644
index 00000000..31fce78a
--- /dev/null
+++ b/ihp-sg13g2/libs.doc/meas/pnpMPA/doc/word.htm
@@ -0,0 +1,5 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">

<html>

<head>

<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=utf-8">

<title>Content</title></head>

<body bgcolor="FFFFFF">

<hr>

<h1>pnpMPA (SG13)</h1>

<h2>pnpMPA</h2>

<p>Testfield: T323<br>Technology: SG13<br>Lot: PQA701 (SG13S)<br>Wafer: 01, 15-19, 24<br>Lot: PQA702 (SG13G2)<br>Wafer: 06-10<br>Date: October 2022<br>
<br>DC and CV Measurements&nbsp; at 27°C</p>
+
+</p>
+
+</body></html>
\ No newline at end of file
diff --git a/ihp-sg13g2/libs.tech/klayout/python/cni/paramarray.py b/ihp-sg13g2/libs.qa/stdcells/check_multiplier.sh
old mode 100644
new mode 100755
similarity index 77%
rename from ihp-sg13g2/libs.tech/klayout/python/cni/paramarray.py
rename to ihp-sg13g2/libs.qa/stdcells/check_multiplier.sh
index 4a3d9e5b..df60ec63
--- a/ihp-sg13g2/libs.tech/klayout/python/cni/paramarray.py
+++ b/ihp-sg13g2/libs.qa/stdcells/check_multiplier.sh
@@ -1,13 +1,15 @@
+#!/bin/bash
+
 ########################################################################
 #
 # Copyright 2024 IHP PDK Authors
-#
+# 
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
 # You may obtain a copy of the License at
-#
+# 
 #    https://www.apache.org/licenses/LICENSE-2.0
-#
+# 
 # Unless required by applicable law or agreed to in writing, software
 # distributed under the License is distributed on an "AS IS" BASIS,
 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -16,8 +18,10 @@
 #
 ########################################################################
 
+# checking CDL and SPICE netlists
+# the only allowed multiplier is m=1
 
-class ParamArray(dict):
-    def __init__(self, *arg, **kw):
-        super(ParamArry, self).__init__(*arg, **kw)
-
+cellset="sg13g2_stdcell"
+for view in cdl spice; do
+  grep -nHE 'm=[^1]' ../../libs.ref/${cellset}/${view}/${cellset}.*
+done
diff --git a/ihp-sg13g2/libs.ref/.gitignore b/ihp-sg13g2/libs.ref/.gitignore
new file mode 100644
index 00000000..39e7aa22
--- /dev/null
+++ b/ihp-sg13g2/libs.ref/.gitignore
@@ -0,0 +1,7 @@
+# Make sure we don't ignore sub-directories in the root .gitignore
+!cdl/
+!doc/
+!gds/
+!lib/
+!spice/
+!verilog/
diff --git a/ihp-sg13g2/libs.ref/sg13g2_io/cdl/sg13g2_iocell.cdl b/ihp-sg13g2/libs.ref/sg13g2_io/cdl/sg13g2_io.cdl
similarity index 96%
rename from ihp-sg13g2/libs.ref/sg13g2_io/cdl/sg13g2_iocell.cdl
rename to ihp-sg13g2/libs.ref/sg13g2_io/cdl/sg13g2_io.cdl
index b01deb72..65b4f4c5 100644
--- a/ihp-sg13g2/libs.ref/sg13g2_io/cdl/sg13g2_iocell.cdl
+++ b/ihp-sg13g2/libs.ref/sg13g2_io/cdl/sg13g2_io.cdl
@@ -28,7 +28,7 @@
 .PARAM
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    DCNDiode
 * View Name:    schematic
 ************************************************************************
@@ -39,7 +39,7 @@ DD0 anode cathode dantenna m=1 w=1.26u l=27.78u a=35.003p p=58.08u
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    DCPDiode
 * View Name:    schematic
 ************************************************************************
@@ -50,7 +50,7 @@ DD0 anode cathode dpantenna m=1 w=1.26u l=27.78u a=35.003p p=58.08u
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    inv_x1
 * View Name:    schematic
 ************************************************************************
@@ -62,7 +62,7 @@ MP0 nq i vdd vdd sg13_lv_pmos m=1 w=4.41u l=130.00n ng=1
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    LevelUp
 * View Name:    schematic
 ************************************************************************
@@ -80,7 +80,7 @@ MP1 net4 net3 iovdd iovdd sg13_hv_pmos m=1 w=300.0n l=450.00n ng=1
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    nor2_x1
 * View Name:    schematic
 ************************************************************************
@@ -94,7 +94,7 @@ MP0 nq i1 net1 vdd sg13_lv_pmos m=1 w=4.41u l=130.00n ng=1
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    nand2_x1
 * View Name:    schematic
 ************************************************************************
@@ -108,7 +108,7 @@ MN0 nq i1 net1 vss sg13_lv_nmos m=1 w=3.93u l=130.00n ng=1
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    GateDecode
 * View Name:    schematic
 ************************************************************************
@@ -123,7 +123,7 @@ XI1 core en net2 vdd vss / nand2_x1
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    SecondaryProtection
 * View Name:    schematic
 ************************************************************************
@@ -136,7 +136,7 @@ DD1 core plus dpantenna m=1 w=780.00n l=4.98u a=3.884p p=11.52u
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    LevelDown
 * View Name:    schematic
 ************************************************************************
@@ -151,7 +151,7 @@ MP1 core net2 vdd vdd sg13_lv_pmos m=1 w=4.75u l=130.00n ng=1
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_IOPadInOut30mA
 * View Name:    schematic
 ************************************************************************
@@ -167,7 +167,7 @@ XI1 p2c iovdd iovss pad vdd vss / LevelDown
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    LevelUpInv
 * View Name:    schematic
 ************************************************************************
@@ -185,7 +185,7 @@ MP1 net4 net3 iovdd iovdd sg13_hv_pmos m=1 w=300.0n l=450.00n ng=1
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    GateLevelUpInv
 * View Name:    schematic
 ************************************************************************
@@ -197,7 +197,7 @@ XI0 core iovdd ngate vdd vss / LevelUpInv
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_IOPadOut4mA
 * View Name:    schematic
 ************************************************************************
@@ -212,7 +212,7 @@ XI3 iovss pad iovdd / DCNDiode
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_Filler10000
 * View Name:    schematic
 ************************************************************************
@@ -222,7 +222,7 @@ XI3 iovss pad iovdd / DCNDiode
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_IOPadVss
 * View Name:    schematic
 ************************************************************************
@@ -234,7 +234,7 @@ XI1 iovss vss iovss / DCNDiode
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_IOPadIOVss
 * View Name:    schematic
 ************************************************************************
@@ -246,7 +246,7 @@ DD1 iovss iovdd dpantenna m=1 w=1.26u l=27.78u a=35.003p p=58.08u
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_IOPadOut16mA
 * View Name:    schematic
 ************************************************************************
@@ -261,7 +261,7 @@ XI3 iovss pad iovdd / DCNDiode
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    RCClampResistor
 * View Name:    schematic
 ************************************************************************
@@ -331,7 +331,7 @@ RR0 pin1 net1 rppd 5.239K m=1 l=20u w=1u ps=180n trise=0.0
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    Clamp_N43N43D4R
 * View Name:    schematic
 ************************************************************************
@@ -513,7 +513,7 @@ MN0<172> pad gate tie tie sg13_hv_nmos m=1 w=4.4u l=600.0n ng=1
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    RCClampInverter
 * View Name:    schematic
 ************************************************************************
@@ -526,7 +526,7 @@ MP0 out in supply supply sg13_hv_pmos m=1 w=350.000u l=500.0n ng=50
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_IOPadIOVdd
 * View Name:    schematic
 ************************************************************************
@@ -539,7 +539,7 @@ XI1 net1 iovss net2 iovdd / RCClampInverter
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_IOPadTriOut30mA
 * View Name:    schematic
 ************************************************************************
@@ -554,7 +554,7 @@ XI3 iovss pad iovdd / DCNDiode
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_IOPadTriOut16mA
 * View Name:    schematic
 ************************************************************************
@@ -569,7 +569,7 @@ XI3 iovss pad iovdd / DCNDiode
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_IOPadInOut16mA
 * View Name:    schematic
 ************************************************************************
@@ -585,7 +585,7 @@ XI1 p2c iovdd iovss pad vdd vss / LevelDown
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_Filler200
 * View Name:    schematic
 ************************************************************************
@@ -595,7 +595,7 @@ XI1 p2c iovdd iovss pad vdd vss / LevelDown
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_Filler2000
 * View Name:    schematic
 ************************************************************************
@@ -605,7 +605,7 @@ XI1 p2c iovdd iovss pad vdd vss / LevelDown
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_IOPadOut30mA
 * View Name:    schematic
 ************************************************************************
@@ -620,7 +620,7 @@ XI3 iovss pad iovdd / DCNDiode
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_IOPadInOut4mA
 * View Name:    schematic
 ************************************************************************
@@ -636,7 +636,7 @@ XI1 p2c iovdd iovss pad vdd vss / LevelDown
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    Clamp_N20N0D
 * View Name:    schematic
 ************************************************************************
@@ -649,7 +649,7 @@ RR1 iovss net2 rppd 1.959K m=1 l=3.54u w=500n ps=180n
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    Clamp_P20N0D
 * View Name:    schematic
 ************************************************************************
@@ -662,7 +662,7 @@ RR0 net2 iovdd rppd 6.768K m=1 l=12.9u w=500n ps=180n
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_IOPadAnalog
 * View Name:    schematic
 ************************************************************************
@@ -677,7 +677,7 @@ XI6 padres iovss pad iovdd / SecondaryProtection
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_Filler4000
 * View Name:    schematic
 ************************************************************************
@@ -687,7 +687,7 @@ XI6 padres iovss pad iovdd / SecondaryProtection
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_Corner
 * View Name:    schematic
 ************************************************************************
@@ -697,7 +697,7 @@ XI6 padres iovss pad iovdd / SecondaryProtection
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_Filler400
 * View Name:    schematic
 ************************************************************************
@@ -707,7 +707,7 @@ XI6 padres iovss pad iovdd / SecondaryProtection
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_IOPadTriOut4mA
 * View Name:    schematic
 ************************************************************************
@@ -722,7 +722,7 @@ XI3 iovss pad iovdd / DCNDiode
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_IOPadIn
 * View Name:    schematic
 ************************************************************************
@@ -735,7 +735,7 @@ XI3 iovss pad iovdd / DCNDiode
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_IOPadVdd
 * View Name:    schematic
 ************************************************************************
@@ -747,7 +747,7 @@ DD0 iovss vdd dantenna m=1 w=1.26u l=27.78u a=35.003p p=58.08u
 .ENDS
 
 ************************************************************************
-* Library Name: sg13g2_iocell
+* Library Name: sg13g2_io
 * Cell Name:    sg13g2_Filler1000
 * View Name:    schematic
 ************************************************************************
diff --git a/ihp-sg13g2/libs.ref/sg13g2_io/doc/README.md b/ihp-sg13g2/libs.ref/sg13g2_io/doc/README.md
index 7d4e03b8..627dfc0d 100644
--- a/ihp-sg13g2/libs.ref/sg13g2_io/doc/README.md
+++ b/ihp-sg13g2/libs.ref/sg13g2_io/doc/README.md
@@ -7,20 +7,20 @@ This is the sg13g2_io library. The following files are included in this library:
 * `gds/sg13g2_io.gds`: GDS view of the IO cells
 * `spice/sg13g2_io.spi`: spice netlists of the IO cells
 * `lef/sg13g2_io.lef`: LEF view of the IO cells
-* `liberty/sg13g2_io_dummy.lib`: dummy liberty view of the IO cells.  
+* `lib/sg13g2_io_dummy.lib`: dummy liberty view of the IO cells.  
   This file only contains enough information to get the OpenROAD flow going; no timing
   or power data is available in this file.
 
 These files are generated from python scripts of the Chips4Makers based IHP SG13G2
 PDK. The code can be found in the
 [c4m-pdk-ihpsg13g2](https://gitlab.com/Chips4Makers/c4m-pdk-ihpsg13g2.git) repo.
-This library is built from version `0.0.3` of that source code.
+This library is built from version `0.0.4` of that source code.
 The `README.md` file of this project explains how to use the code in there. The whole
 build of the files plus preparation of the files described above for upstreaming can be
 generated with the command `pdm doit patch4upstream`.
 
 It also contains externally contributed files:
 
-* cdl/sg13g2_iocell.cdl: CDL netlist
-* verilog/sg13g2_io.v: verilog netlist
-* liberty/sg13g2_iocell_*lib: liberty files with timing
+* cdl/sg13g2_io.cdl: CDL netlist
+* verilog/sg13g2_io.v: Verilog netlist
+* lib/sg13g2_io_*.lib: Liberty files with timing
diff --git a/ihp-sg13g2/libs.ref/sg13g2_io/gds/sg13g2_io.gds b/ihp-sg13g2/libs.ref/sg13g2_io/gds/sg13g2_io.gds
index efc29676..fc12e448 100644
Binary files a/ihp-sg13g2/libs.ref/sg13g2_io/gds/sg13g2_io.gds and b/ihp-sg13g2/libs.ref/sg13g2_io/gds/sg13g2_io.gds differ
diff --git a/ihp-sg13g2/libs.ref/sg13g2_io/liberty/sg13g2_io_dummy.lib b/ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_dummy.lib
similarity index 95%
rename from ihp-sg13g2/libs.ref/sg13g2_io/liberty/sg13g2_io_dummy.lib
rename to ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_dummy.lib
index f9856594..57efb7f7 100644
--- a/ihp-sg13g2/libs.ref/sg13g2_io/liberty/sg13g2_io_dummy.lib
+++ b/ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_dummy.lib
@@ -1540,4 +1540,78 @@ library (sg13g2_io_dummy) {
             voltage_name : "iovdd";
         }
     }
+    cell (sg13g2_IOPadAnalog) {
+        area: 14400;
+        dont_touch : true;
+        dont_use : true;
+        timing_model_type : abstracted;
+        pad_cell : true;
+        pg_pin (vss) {
+            pg_type : primary_ground;
+            voltage_name : "vss";
+        }
+        pg_pin (vdd) {
+            pg_type : primary_power;
+            voltage_name : "vdd";
+        }
+        pg_pin (iovss) {
+            pg_type : primary_ground;
+            voltage_name : "iovss";
+        }
+        pg_pin (iovdd) {
+            pg_type : primary_power;
+            voltage_name : "iovdd";
+        }
+        pin (pad) {
+            direction : inout;
+            function : "(pad)";
+            output_voltage : core_output;
+            related_ground_pin : vss;
+            related_power_pin : vdd;
+            max_capacitance : 500;
+            max_transition : 200;
+            timing () {
+                related_pin : "pad";
+                timing_type : combinational;
+                cell_rise (delay_template_2x2) {
+                    values ( \
+                        "1000, 1000", \
+                        "1000, 1000" \
+                    );
+                }
+                rise_transition (delay_template_2x2) {
+                    values ( \
+                        "200, 200", \
+                        "200, 200" \
+                    );
+                }
+                cell_fall (delay_template_2x2) {
+                    values ( \
+                        "1000, 1000", \
+                        "1000, 1000" \
+                    );
+                }
+                fall_transition (delay_template_2x2) {
+                    values ( \
+                        "200, 200", \
+                        "200, 200" \
+                    );
+                }
+            }
+        }
+        pin (padres) {
+            direction : inout;
+            is_pad : false;
+            input_voltage : io_input;
+            related_ground_pin : iovss;
+            related_power_pin : iovdd;
+            max_transition : 200;
+            capacitance : 15.0;
+            rise_capacitance : 15.0;
+            rise_capacitance_range (12.0, 15.0);
+            fall_capacitance : 15.0;
+            fall_capacitance_range (12.0, 15.0);
+        }
+    }
+
 }
diff --git a/ihp-sg13g2/libs.ref/sg13g2_io/liberty/sg13g2_iocell_fast_1p32V_3p6V_m40C.lib b/ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_fast_1p32V_3p6V_m40C.lib
similarity index 99%
rename from ihp-sg13g2/libs.ref/sg13g2_io/liberty/sg13g2_iocell_fast_1p32V_3p6V_m40C.lib
rename to ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_fast_1p32V_3p6V_m40C.lib
index e14472e7..c42ff8c0 100644
--- a/ihp-sg13g2/libs.ref/sg13g2_io/liberty/sg13g2_iocell_fast_1p32V_3p6V_m40C.lib
+++ b/ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_fast_1p32V_3p6V_m40C.lib
@@ -16,7 +16,7 @@
  
 ************************************************************************/
 
-library (sg13g2_iocell_fast_1p32V_3p6V_m40C) {
+library (sg13g2_io_fast_1p32V_3p6V_m40C) {
   comment : "IHP Microelectronics GmbH, 2024";
   date : "$Date: Wed May  8 12:23:04 2024 $";
   revision : "$Revision: 0.0.1 $";
@@ -60,7 +60,7 @@ library (sg13g2_iocell_fast_1p32V_3p6V_m40C) {
   slew_lower_threshold_pct_rise : 10;
   slew_upper_threshold_pct_fall : 90;
   slew_upper_threshold_pct_rise : 90;
-  operating_conditions (sg13g2_iocell_fast_1p32V_3p6V_m40C) {
+  operating_conditions (sg13g2_io_fast_1p32V_3p6V_m40C) {
     process : 1;
     temperature : -40;
     voltage : 1.32;
@@ -211,7 +211,7 @@ library (sg13g2_iocell_fast_1p32V_3p6V_m40C) {
     wire_load_from_area (1.27008e+06, 3.1752e+06, 500k);
   }
   default_wire_load : "1k";
-  default_operating_conditions : sg13g2_iocell_fast_1p32V_3p6V_m40C;
+  default_operating_conditions : sg13g2_io_fast_1p32V_3p6V_m40C;
   default_wire_load_selection : "4_metls_routing";
   lu_table_template (delay_template_7x6_16) {
     variable_1 : input_net_transition;
diff --git a/ihp-sg13g2/libs.ref/sg13g2_io/liberty/sg13g2_iocell_fast_1p65V_3p6V_m40C.lib b/ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_fast_1p65V_3p6V_m40C.lib
similarity index 99%
rename from ihp-sg13g2/libs.ref/sg13g2_io/liberty/sg13g2_iocell_fast_1p65V_3p6V_m40C.lib
rename to ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_fast_1p65V_3p6V_m40C.lib
index 0dec04d2..a8d38e28 100644
--- a/ihp-sg13g2/libs.ref/sg13g2_io/liberty/sg13g2_iocell_fast_1p65V_3p6V_m40C.lib
+++ b/ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_fast_1p65V_3p6V_m40C.lib
@@ -16,7 +16,7 @@
  
 ************************************************************************/
 
-library (sg13g2_iocell_fast_1p65V_3p6V_m40C) {
+library (sg13g2_io_fast_1p65V_3p6V_m40C) {
   comment : "IHP Microelectronics GmbH, 2024";
   date : "$Date: Wed May  8 12:28:37 2024 $";
   revision : "$Revision: 0.0.1 $";
@@ -60,7 +60,7 @@ library (sg13g2_iocell_fast_1p65V_3p6V_m40C) {
   slew_lower_threshold_pct_rise : 10;
   slew_upper_threshold_pct_fall : 90;
   slew_upper_threshold_pct_rise : 90;
-  operating_conditions (sg13g2_iocell_fast_1p65V_3p6V_m40C) {
+  operating_conditions (sg13g2_io_fast_1p65V_3p6V_m40C) {
     process : 1;
     temperature : -40;
     voltage : 1.65;
@@ -211,7 +211,7 @@ library (sg13g2_iocell_fast_1p65V_3p6V_m40C) {
     wire_load_from_area (1.27008e+06, 3.1752e+06, 500k);
   }
   default_wire_load : "1k";
-  default_operating_conditions : sg13g2_iocell_fast_1p65V_3p6V_m40C;
+  default_operating_conditions : sg13g2_io_fast_1p65V_3p6V_m40C;
   default_wire_load_selection : "4_metls_routing";
   lu_table_template (delay_template_7x6_16) {
     variable_1 : input_net_transition;
diff --git a/ihp-sg13g2/libs.ref/sg13g2_io/liberty/sg13g2_iocell_slow_1p08V_3p0V_125C.lib b/ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_slow_1p08V_3p0V_125C.lib
similarity index 99%
rename from ihp-sg13g2/libs.ref/sg13g2_io/liberty/sg13g2_iocell_slow_1p08V_3p0V_125C.lib
rename to ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_slow_1p08V_3p0V_125C.lib
index c38f5a01..64cb1db0 100644
--- a/ihp-sg13g2/libs.ref/sg13g2_io/liberty/sg13g2_iocell_slow_1p08V_3p0V_125C.lib
+++ b/ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_slow_1p08V_3p0V_125C.lib
@@ -16,7 +16,7 @@
  
 ************************************************************************/
 
-library (sg13g2_iocell_slow_1p08V_3p0V_125C) {
+library (sg13g2_io_slow_1p08V_3p0V_125C) {
   comment : "IHP Microelectronics GmbH, 2024";
   date : "$Date: Wed May  8 12:21:14 2024 $";
   revision : "$Revision: 0.0.1 $";
@@ -60,7 +60,7 @@ library (sg13g2_iocell_slow_1p08V_3p0V_125C) {
   slew_lower_threshold_pct_rise : 10;
   slew_upper_threshold_pct_fall : 90;
   slew_upper_threshold_pct_rise : 90;
-  operating_conditions (sg13g2_iocell_slow_1p08V_3p0V_125C) {
+  operating_conditions (sg13g2_io_slow_1p08V_3p0V_125C) {
     process : 1;
     temperature : 125;
     voltage : 1.08;
@@ -211,7 +211,7 @@ library (sg13g2_iocell_slow_1p08V_3p0V_125C) {
     wire_load_from_area (1.27008e+06, 3.1752e+06, 500k);
   }
   default_wire_load : "1k";
-  default_operating_conditions : sg13g2_iocell_slow_1p08V_3p0V_125C;
+  default_operating_conditions : sg13g2_io_slow_1p08V_3p0V_125C;
   default_wire_load_selection : "4_metls_routing";
   lu_table_template (delay_template_7x6_16) {
     variable_1 : input_net_transition;
diff --git a/ihp-sg13g2/libs.ref/sg13g2_io/liberty/sg13g2_iocell_slow_1p35V_3p0V_125C.lib b/ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_slow_1p35V_3p0V_125C.lib
similarity index 99%
rename from ihp-sg13g2/libs.ref/sg13g2_io/liberty/sg13g2_iocell_slow_1p35V_3p0V_125C.lib
rename to ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_slow_1p35V_3p0V_125C.lib
index 873c69b2..4f59f148 100644
--- a/ihp-sg13g2/libs.ref/sg13g2_io/liberty/sg13g2_iocell_slow_1p35V_3p0V_125C.lib
+++ b/ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_slow_1p35V_3p0V_125C.lib
@@ -16,7 +16,7 @@
  
 ************************************************************************/
 
-library (sg13g2_iocell_slow_1p35V_3p0V_125C) {
+library (sg13g2_io_slow_1p35V_3p0V_125C) {
   comment : "IHP Microelectronics GmbH, 2024";
   date : "$Date: Wed May  8 12:26:45 2024 $";
   revision : "$Revision: 0.0.1 $";
@@ -60,7 +60,7 @@ library (sg13g2_iocell_slow_1p35V_3p0V_125C) {
   slew_lower_threshold_pct_rise : 10;
   slew_upper_threshold_pct_fall : 90;
   slew_upper_threshold_pct_rise : 90;
-  operating_conditions (sg13g2_iocell_slow_1p35V_3p0V_125C) {
+  operating_conditions (sg13g2_io_slow_1p35V_3p0V_125C) {
     process : 1;
     temperature : 125;
     voltage : 1.35;
@@ -211,7 +211,7 @@ library (sg13g2_iocell_slow_1p35V_3p0V_125C) {
     wire_load_from_area (1.27008e+06, 3.1752e+06, 500k);
   }
   default_wire_load : "1k";
-  default_operating_conditions : sg13g2_iocell_slow_1p35V_3p0V_125C;
+  default_operating_conditions : sg13g2_io_slow_1p35V_3p0V_125C;
   default_wire_load_selection : "4_metls_routing";
   lu_table_template (delay_template_7x6_16) {
     variable_1 : input_net_transition;
diff --git a/ihp-sg13g2/libs.ref/sg13g2_io/liberty/sg13g2_iocell_typ_1p2V_3p3V_25C.lib b/ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_typ_1p2V_3p3V_25C.lib
similarity index 99%
rename from ihp-sg13g2/libs.ref/sg13g2_io/liberty/sg13g2_iocell_typ_1p2V_3p3V_25C.lib
rename to ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_typ_1p2V_3p3V_25C.lib
index 95d0b633..ba6b43f6 100644
--- a/ihp-sg13g2/libs.ref/sg13g2_io/liberty/sg13g2_iocell_typ_1p2V_3p3V_25C.lib
+++ b/ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_typ_1p2V_3p3V_25C.lib
@@ -16,7 +16,7 @@
  
 ************************************************************************/
 
-library (sg13g2_iocell_typ_1p2V_3p3V_25C) {
+library (sg13g2_io_typ_1p2V_3p3V_25C) {
   comment : "IHP Microelectronics GmbH, 2024";
   date : "$Date: Wed May  8 12:19:26 2024 $";
   revision : "$Revision: 0.0.1 $";
@@ -60,7 +60,7 @@ library (sg13g2_iocell_typ_1p2V_3p3V_25C) {
   slew_lower_threshold_pct_rise : 10;
   slew_upper_threshold_pct_fall : 90;
   slew_upper_threshold_pct_rise : 90;
-  operating_conditions (sg13g2_iocell_typ_1p2V_3p3V_25C) {
+  operating_conditions (sg13g2_io_typ_1p2V_3p3V_25C) {
     process : 1;
     temperature : 25;
     voltage : 1.2;
@@ -211,7 +211,7 @@ library (sg13g2_iocell_typ_1p2V_3p3V_25C) {
     wire_load_from_area (1.27008e+06, 3.1752e+06, 500k);
   }
   default_wire_load : "1k";
-  default_operating_conditions : sg13g2_iocell_typ_1p2V_3p3V_25C;
+  default_operating_conditions : sg13g2_io_typ_1p2V_3p3V_25C;
   default_wire_load_selection : "4_metls_routing";
   lu_table_template (delay_template_7x6_16) {
     variable_1 : input_net_transition;
diff --git a/ihp-sg13g2/libs.ref/sg13g2_io/liberty/sg13g2_iocell_typ_1p5V_3p3V_25C.lib b/ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_typ_1p5V_3p3V_25C.lib
similarity index 99%
rename from ihp-sg13g2/libs.ref/sg13g2_io/liberty/sg13g2_iocell_typ_1p5V_3p3V_25C.lib
rename to ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_typ_1p5V_3p3V_25C.lib
index dc44abb4..73e301b7 100644
--- a/ihp-sg13g2/libs.ref/sg13g2_io/liberty/sg13g2_iocell_typ_1p5V_3p3V_25C.lib
+++ b/ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_typ_1p5V_3p3V_25C.lib
@@ -16,7 +16,7 @@
  
 ************************************************************************/
 
-library (sg13g2_iocell_typ_1p5V_3p3V_25C) {
+library (sg13g2_io_typ_1p5V_3p3V_25C) {
   comment : "IHP Microelectronics GmbH, 2024";
   date : "$Date: Wed May  8 12:24:55 2024 $";
   revision : "$Revision: 0.0.1 $";
@@ -60,7 +60,7 @@ library (sg13g2_iocell_typ_1p5V_3p3V_25C) {
   slew_lower_threshold_pct_rise : 10;
   slew_upper_threshold_pct_fall : 90;
   slew_upper_threshold_pct_rise : 90;
-  operating_conditions (sg13g2_iocell_typ_1p5V_3p3V_25C) {
+  operating_conditions (sg13g2_io_typ_1p5V_3p3V_25C) {
     process : 1;
     temperature : 25;
     voltage : 1.5;
@@ -211,7 +211,7 @@ library (sg13g2_iocell_typ_1p5V_3p3V_25C) {
     wire_load_from_area (1.27008e+06, 3.1752e+06, 500k);
   }
   default_wire_load : "1k";
-  default_operating_conditions : sg13g2_iocell_typ_1p5V_3p3V_25C;
+  default_operating_conditions : sg13g2_io_typ_1p5V_3p3V_25C;
   default_wire_load_selection : "4_metls_routing";
   lu_table_template (delay_template_7x6_16) {
     variable_1 : input_net_transition;
diff --git a/ihp-sg13g2/libs.ref/sg13g2_io/spice/sg13g2_io.spi b/ihp-sg13g2/libs.ref/sg13g2_io/spice/sg13g2_io.spi
index 254f4b0f..eda69a71 100644
--- a/ihp-sg13g2/libs.ref/sg13g2_io/spice/sg13g2_io.spi
+++ b/ihp-sg13g2/libs.ref/sg13g2_io/spice/sg13g2_io.spi
@@ -1,7 +1,7 @@
 * sg13g2_io
 
 * Autogenerated file; please don't edit
-* date: 2024-05-06 15:00:13.438920
+* date: 2024-05-27 14:30:57.050559
 
 ************************************************************************
 *
@@ -356,7 +356,7 @@ Xclamp_g42_r2 iovss gate pad iovss sg13_hv_nmos l=0.6um w=4.4um
 Xclamp_g42_r3 iovss gate pad iovss sg13_hv_nmos l=0.6um w=4.4um
 XOuterRing iovdd sg13g2_GuardRing_N16000W4884HFF
 XInnerRing iovss sg13g2_GuardRing_P15280W4164HFF
-XDGATE iovss gate dantenna l=0.64um w=0.3um
+XDGATE iovss gate dantenna l=0.64um w=0.48um
 .ends sg13g2_Clamp_N43N43D4R
 
 * sg13g2_RCClampResistor
@@ -481,11 +481,17 @@ Xpmos49_r0 out in supply supply sg13_hv_pmos l=0.5um w=7.0um
 Xpmosguardring supply sg13g2_GuardRing_N9472W2216HTT
 .ends sg13g2_RCClampInverter
 
+* sg13g2_GuardRing_N16000W6624HFF
+.subckt sg13g2_GuardRing_N16000W6624HFF conn
+
+.ends sg13g2_GuardRing_N16000W6624HFF
+
 * sg13g2_IOPadVdd
 .subckt sg13g2_IOPadVdd vss vdd iovss iovdd
 Xnclamp iovss iovdd vdd ngate sg13g2_Clamp_N43N43D4R
 Xrcres vdd res_cap sg13g2_RCClampResistor
 Xrcinv vdd iovss res_cap ngate sg13g2_RCClampInverter
+Xpad_guard iovss sg13g2_GuardRing_N16000W6624HFF
 .ends sg13g2_IOPadVdd
 
 * sg13g2_IOPadIn
@@ -511,7 +517,7 @@ Xclamp_g0 iovss gate pad iovss sg13_hv_nmos l=0.6um w=4.4um
 Xclamp_g1 pad gate iovss iovss sg13_hv_nmos l=0.6um w=4.4um
 XOuterRing iovdd sg13g2_GuardRing_N16000W1980HFF
 XInnerRing iovss sg13g2_GuardRing_P15280W1260HFF
-XDGATE iovss gate dantenna l=0.64um w=0.3um
+XDGATE iovss gate dantenna l=0.64um w=0.48um
 .ends sg13g2_Clamp_N2N2D
 
 * sg13g2_GuardRing_P16000W3852HFF
@@ -532,7 +538,7 @@ Xclamp_g1_r0 pad gate iovdd iovdd sg13_hv_pmos l=0.6um w=6.66um
 Xclamp_g1_r1 pad gate iovdd iovdd sg13_hv_pmos l=0.6um w=6.66um
 XOuterRing iovss sg13g2_GuardRing_P16000W3852HFF
 XInnerRing iovdd sg13g2_GuardRing_N15280W3132HTF
-XDGATE gate iovdd dpantenna l=0.64um w=0.3um
+XDGATE gate iovdd dpantenna l=0.64um w=0.48um
 .ends sg13g2_Clamp_P2N2D
 
 * sg13g2_LevelUpInv
@@ -574,7 +580,7 @@ Xclamp_g6 iovss gate pad iovss sg13_hv_nmos l=0.6um w=4.4um
 Xclamp_g7 pad gate iovss iovss sg13_hv_nmos l=0.6um w=4.4um
 XOuterRing iovdd sg13g2_GuardRing_N16000W1980HFF
 XInnerRing iovss sg13g2_GuardRing_P15280W1260HFF
-XDGATE iovss gate dantenna l=0.64um w=0.3um
+XDGATE iovss gate dantenna l=0.64um w=0.48um
 .ends sg13g2_Clamp_N8N8D
 
 * sg13g2_Clamp_P8N8D
@@ -597,7 +603,7 @@ Xclamp_g7_r0 pad gate iovdd iovdd sg13_hv_pmos l=0.6um w=6.66um
 Xclamp_g7_r1 pad gate iovdd iovdd sg13_hv_pmos l=0.6um w=6.66um
 XOuterRing iovss sg13g2_GuardRing_P16000W3852HFF
 XInnerRing iovdd sg13g2_GuardRing_N15280W3132HTF
-XDGATE gate iovdd dpantenna l=0.64um w=0.3um
+XDGATE gate iovdd dpantenna l=0.64um w=0.48um
 .ends sg13g2_Clamp_P8N8D
 
 * sg13g2_IOPadOut16mA
@@ -628,7 +634,7 @@ Xclamp_g13 pad gate iovss iovss sg13_hv_nmos l=0.6um w=4.4um
 Xclamp_g14 iovss gate pad iovss sg13_hv_nmos l=0.6um w=4.4um
 XOuterRing iovdd sg13g2_GuardRing_N16000W1980HFF
 XInnerRing iovss sg13g2_GuardRing_P15280W1260HFF
-XDGATE iovss gate dantenna l=0.64um w=0.3um
+XDGATE iovss gate dantenna l=0.64um w=0.48um
 .ends sg13g2_Clamp_N15N15D
 
 * sg13g2_Clamp_P15N15D
@@ -665,7 +671,7 @@ Xclamp_g14_r0 iovdd gate pad iovdd sg13_hv_pmos l=0.6um w=6.66um
 Xclamp_g14_r1 iovdd gate pad iovdd sg13_hv_pmos l=0.6um w=6.66um
 XOuterRing iovss sg13g2_GuardRing_P16000W3852HFF
 XInnerRing iovdd sg13g2_GuardRing_N15280W3132HTF
-XDGATE gate iovdd dpantenna l=0.64um w=0.3um
+XDGATE gate iovdd dpantenna l=0.64um w=0.48um
 .ends sg13g2_Clamp_P15N15D
 
 * sg13g2_IOPadOut30mA
@@ -740,11 +746,6 @@ Xdcndiode iovss iovss iovdd sg13g2_DCNDiode
 Xdcpdiode iovss iovdd iovss sg13g2_DCPDiode
 .ends sg13g2_IOPadIOVss
 
-* sg13g2_GuardRing_N16000W6624HFF
-.subckt sg13g2_GuardRing_N16000W6624HFF conn
-
-.ends sg13g2_GuardRing_N16000W6624HFF
-
 * sg13g2_IOPadIOVdd
 .subckt sg13g2_IOPadIOVdd vss vdd iovss iovdd
 Xnclamp iovss iovdd iovdd ngate sg13g2_Clamp_N43N43D4R
diff --git a/ihp-sg13g2/libs.ref/sg13g2_io/verilog/sg13g2_io.v b/ihp-sg13g2/libs.ref/sg13g2_io/verilog/sg13g2_io.v
index c26682d0..1fa45dfc 100644
--- a/ihp-sg13g2/libs.ref/sg13g2_io/verilog/sg13g2_io.v
+++ b/ihp-sg13g2/libs.ref/sg13g2_io/verilog/sg13g2_io.v
@@ -72,7 +72,7 @@ module sg13g2_IOPadIn (pad, p2c);
 
 	// Timing
 	specify
-		(p2c => pad) = 0;
+		(pad => p2c) = 0;
 	endspecify
 endmodule
 `endcelldefine
@@ -89,7 +89,7 @@ module sg13g2_IOPadOut4mA (pad, c2p);
 
 	// Timing
 	specify
-		(pad => c2p) = 0;
+		(c2p => pad) = 0;
 	endspecify
 endmodule
 `endcelldefine
@@ -106,7 +106,7 @@ module sg13g2_IOPadOut16mA (pad, c2p);
 
 	// Timing
 	specify
-		(pad => c2p) = 0;
+		(c2p => pad) = 0;
 	endspecify
 endmodule
 `endcelldefine
@@ -123,7 +123,7 @@ module sg13g2_IOPadOut30mA (pad, c2p);
 
 	// Timing
 	specify
-		(pad => c2p) = 0;
+		(c2p => pad) = 0;
 	endspecify
 endmodule
 `endcelldefine
@@ -141,7 +141,8 @@ module sg13g2_IOPadTriOut4mA (pad, c2p, c2p_en);
 
 	// Timing
 	specify
-		(pad => c2p) = 0;
+		if (c2p_en == 1'b1)
+			(c2p => pad) = 0;
 	endspecify
 endmodule
 `endcelldefine
@@ -159,7 +160,8 @@ module sg13g2_IOPadTriOut16mA (pad, c2p, c2p_en);
 
 	// Timing
 	specify
-		(pad => c2p) = 0;
+		if (c2p_en == 1'b1)
+			(c2p => pad) = 0;
 	endspecify
 endmodule
 `endcelldefine
@@ -177,7 +179,8 @@ module sg13g2_IOPadTriOut30mA (pad, c2p, c2p_en);
 
 	// Timing
 	specify
-		(pad => c2p) = 0;
+		if (c2p_en == 1'b1)
+			(c2p => pad) = 0;
 	endspecify
 endmodule
 `endcelldefine
@@ -197,8 +200,9 @@ module sg13g2_IOPadInOut4mA (pad, c2p, c2p_en, p2c);
 
 	// Timing
 	specify
-		(pad => c2p) = 0;
-		(p2c => pad) = 0;
+		if (c2p_en == 1'b1)
+			(c2p => pad) = 0;
+		(pad => p2c) = 0;
 	endspecify
 endmodule
 `endcelldefine
@@ -218,8 +222,9 @@ module sg13g2_IOPadInOut16mA (pad, c2p, c2p_en, p2c);
 
 	// Timing
 	specify
-		(pad => c2p) = 0;
-		(p2c => pad) = 0;
+		if (c2p_en == 1'b1)
+			(c2p => pad) = 0;
+		(pad => p2c) = 0;
 	endspecify
 endmodule
 `endcelldefine
@@ -239,8 +244,9 @@ module sg13g2_IOPadInOut30mA (pad, c2p, c2p_en, p2c);
 
 	// Timing
 	specify
-		(pad => c2p) = 0;
-		(p2c => pad) = 0;
+		if (c2p_en == 1'b1)
+			(c2p => pad) = 0;
+		(pad => p2c) = 0;
 	endspecify
 endmodule
 `endcelldefine
diff --git a/ihp-sg13g2/libs.ref/sg13g2_sram/cdl/RM_IHPSG13_1P_1024x16_c2_bm_bist.cdl b/ihp-sg13g2/libs.ref/sg13g2_sram/cdl/RM_IHPSG13_1P_1024x16_c2_bm_bist.cdl
new file mode 100644
index 00000000..1f2dc467
--- /dev/null
+++ b/ihp-sg13g2/libs.ref/sg13g2_sram/cdl/RM_IHPSG13_1P_1024x16_c2_bm_bist.cdl
@@ -0,0 +1,6391 @@
+* ------------------------------------------------------
+*
+*		Copyright 2024 IHP PDK Authors
+*
+*		Licensed under the Apache License, Version 2.0 (the "License");
+*		you may not use this file except in compliance with the License.
+*		You may obtain a copy of the License at
+*		
+*		   https://www.apache.org/licenses/LICENSE-2.0
+*		
+*		Unless required by applicable law or agreed to in writing, software
+*		distributed under the License is distributed on an "AS IS" BASIS,
+*		WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+*		See the License for the specific language governing permissions and
+*		limitations under the License.
+*		
+*		Generated on Fri Jul 19 08:58:12 2024		
+*
+* ------------------------------------------------------ 
+
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_BITKIT_CORNER NW PW VDD VSS
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_CORNER VDD_CORE VSS
+XI16 VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_1P_BITKIT_CORNER
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR LWL NW PW VDD VSS
+MN1 VSS LWL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MN0 VSS net9 VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> 
++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> 
++ A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS
+XI0<15> A_WL<15> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR
+XI0<14> A_WL<14> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR
+XI0<13> A_WL<13> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR
+XI0<12> A_WL<12> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR
+XI0<11> A_WL<11> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR
+XI0<10> A_WL<10> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR
+XI0<9> A_WL<9> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR
+XI0<8> A_WL<8> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR
+XI0<7> A_WL<7> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR
+XI0<6> A_WL<6> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR
+XI0<5> A_WL<5> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR
+XI0<4> A_WL<4> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR
+XI0<3> A_WL<3> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR
+XI0<2> A_WL<2> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR
+XI0<1> A_WL<1> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR
+XI0<0> A_WL<0> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_LR
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL BLC_BOT BLC_TOP BLT_BOT BLT_TOP LWL NW PW 
++ RWL VDD VSS
+MN0 NC NT VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MN1 NT NC VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MN3 NC RWL BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MN2 BLT_BOT LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0
+MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0
+R1 BLC_BOT BLC_TOP lvsres w=2.6e-07 l=6e-07
+R0 BLT_BOT BLT_TOP lvsres w=2.6e-07 l=6e-07
+R2 RWL LWL lvsres w=2.6e-07 l=6e-07
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> 
++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> 
++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> 
++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> 
++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> 
++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE 
++ VSS
+XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_RWL<15> 
++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL
+XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_RWL<14> VDD_CORE 
++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL
+XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_RWL<13> VDD_CORE 
++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL
+XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_RWL<12> VDD_CORE 
++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL
+XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_RWL<11> VDD_CORE 
++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL
+XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_RWL<10> VDD_CORE 
++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL
+XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_RWL<9> VDD_CORE 
++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL
+XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_RWL<8> VDD_CORE 
++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL
+XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_RWL<7> VDD_CORE 
++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL
+XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_RWL<6> VDD_CORE 
++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL
+XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_RWL<5> VDD_CORE 
++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL
+XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_RWL<4> VDD_CORE 
++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL
+XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_RWL<3> VDD_CORE 
++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL
+XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_RWL<2> VDD_CORE 
++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL
+XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_RWL<1> VDD_CORE 
++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL
+XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_RWL<0> VDD_CORE 
++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL
+XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> 
++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL
+XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> VDD_CORE 
++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL
+XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> VDD_CORE 
++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL
+XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> VDD_CORE 
++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL
+XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> VDD_CORE 
++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL
+XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> VDD_CORE 
++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL
+XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> VDD_CORE 
++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL
+XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> VDD_CORE 
++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL
+XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> VDD_CORE 
++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL
+XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> VDD_CORE 
++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL
+XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> VDD_CORE 
++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL
+XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> VDD_CORE 
++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL
+XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> VDD_CORE 
++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL
+XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> VDD_CORE 
++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL
+XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> VDD_CORE 
++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL
+XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> VDD_CORE 
++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_CELL
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_TB BLC BLT NW PW VDD VSS
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> 
++ VDD_CORE VSS
+XEDGE<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_TB
+XEDGE<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_TB
+.ENDS
+
+.SUBCKT RSC_IHPSG13_CBUFX4 A Z VDD VSS
+MN0 net9 A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN1 Z net9 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0
+MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP1 Z net9 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> 
++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> 
++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> 
++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> 
++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O 
++ VDD VSS
+XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4
+XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4
+XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4
+.ENDS
+.SUBCKT RSC_IHPSG13_WLDRVX4 A Z VDD VSS
+MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0
+MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0
+MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> 
++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> 
++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS
+XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4
+.ENDS
+.SUBCKT RSC_IHPSG13_FILLCAP8 VDD VSS
+MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=4.98u l=130.00n ng=6 nrd=0 
++ nrs=0
+MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=6.48u l=385.000n ng=4 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_LHPQX2 CP D Q VDD VSS
+MN3 QIN CPN net14 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0
+MN2 net14 net10 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN5 net21 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN6 QIN CP net21 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 nrs=0
+MN1 net10 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN4 Q QIN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MP2 QIN CP net16 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0
+MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP4 Q QIN VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP3 net10 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 net16 net10 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP6 QIN CPN net20 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP5 net20 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_NAND2X2 A B Z VDD VSS
+MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MN0 Z B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MN1 net7 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_CINVX4 A Z VDD VSS
+MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0
+MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_CINVX2 A Z VDD VSS
+MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0
+MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_INVX2 A Z VDD VSS
+MN0 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_NAND3X2 A B C Z VDD VSS
+MP2 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP0 Z C VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MN1 net12 B net16 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MN0 Z C net12 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MN2 net16 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_NOR3X2 A B C Z VDD VSS
+MP0 net13 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP2 Z C net10 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP1 net10 B net13 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MN1 Z B VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0
+MN0 Z C VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0
+MN2 Z A VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_FILLCAP4 VDD VSS
+MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=130.00n ng=3 nrd=0 
++ nrs=0
+MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=385.000n ng=2 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_MET2RES A B
+R0 B A lvsres w=2.6e-07 l=6e-07
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT 
++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> 
++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS
+XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2
+XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2
+XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2
+XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2
+XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2
+XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2
+XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2
+XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2
+XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4
+XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2
+XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2
+XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2
+XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2
+XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4
+XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES
+XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> 
++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> 
++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> 
++ VDD VSS
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> 
++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> 
++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> 
++ WL_O<0> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04
+.ENDS
+.SUBCKT RSC_IHPSG13_CINVX8 A Z VDD VSS
+MN0 Z A VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0
+MP0 Z A VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_DFNQMX2IX1 BE BI CN D QI QIN VDD VSS
+MN15 net026 BI VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN14 MXI_OUT BE net026 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN1 net025 D VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN0 MXI_OUT BEN net025 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN10 QI CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 nrs=0
+MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN9 net37 MXI_OUT VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN5 QI CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0
+MN4 net25 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN2 QIN QI VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN13 BEN BE VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP15 MXI_OUT BEN net027 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP14 net027 BI VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP1 MXI_OUT BE net024 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP0 net024 D VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP13 BEN BE VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP3 QI CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0
+MP2 net27 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP10 net36 MXI_OUT VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP7 QIN QI VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP9 QI CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 nrs=0
+MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> 
++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> 
++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+.SUBCKT RSC_IHPSG13_CDLYX1 A Z VDD VSS
+MN1 net010 net032 VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 
++ nrd=0 nrs=0
+MN2 net032 A net014 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 
++ nrs=0
+MN0 Z net032 net010 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 
++ nrs=0
+MN3 net014 A VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 
++ nrs=0
+MP1 Z net032 net07 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 
++ nrs=0
+MP3 net011 A VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 
++ nrs=0
+MP0 net07 net032 VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 
++ nrd=0 nrs=0
+MP2 net032 A net011 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_CDLYX1_DUMMY A Z VDD VSS
+MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=300.0n ng=3 nrd=0 
++ nrs=0
+MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=640.00n ng=2 nrd=0 
++ nrs=0
+R0 Z A lvsres w=2.6e-07 l=6e-07
+.ENDS
+
+.SUBCKT RSC_IHPSG13_MX2IX1 A0 A1 S ZN VDD VSS
+MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0
+MP3 ZN SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0
+MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 ZN S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0
+MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN5 SN S VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0
+MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN2 ZN S net13 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0
+MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN0 ZN SN net15 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_DLY_MUX A SEL Z VDD VSS
+XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2
+XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1
+XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1
+XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1
+XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1
+.ENDS
+.SUBCKT RSC_IHPSG13_DFNQX2 CN D Q VDD VSS
+MN0 Q QIN_SL VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN10 QIN_SL CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN9 net37 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN5 QIN_SL CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN4 net25 QI_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN2 QI_SL QIN_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP0 Q QIN_SL VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 
++ nrs=0
+MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP3 QIN_SL CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP2 net27 QI_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP10 net36 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP7 QI_SL QIN_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP9 QIN_SL CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_CNAND2X2 A B Z VDD VSS
+MN0 Z B net6 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MN1 net6 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_CGATEPX4 CP E Q VDD VSS
+MN1 net08 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN2 net019 net08 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN3 QIN CP net019 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0
+MN6 Q net015 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 
++ nrs=0
+MN5 net015 net08 net018 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN8 QIN CPN net023 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN7 net023 E VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN4 net018 CP VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0
+MP3 net08 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP2 QIN CPN net017 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 net017 net08 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0
+MP8 QIN CP net024 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP7 net024 E VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP4 net015 CP VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 
++ nrs=0
+MP6 Q net015 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 
++ nrs=0
+MP5 net015 net08 VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_CBUFX8 A Z VDD VSS
+MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0
+MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0
+MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0
+MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_CDLYX2 A Z VDD VSS
+MN2 net4 A net9 VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0
+MN0 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN1 net9 A VSS VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0
+MP2 net4 A net10 VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0
+MP1 net10 A VDD VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0
+MP0 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_MX2X2 A0 A1 S Z VDD VSS
+MP6 Z net010 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 
++ nrs=0
+MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0
+MP3 net010 SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 net010 S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN6 Z net010 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN5 SN S VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 nrs=0
+MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN2 net010 S net13 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN0 net010 SN net15 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_AND2X2 A B Z VDD VSS
+MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0
+MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0
+MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_TIEL Z VDD VSS
+MN0 Z net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP0 net2 net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_XOR2X2 A B Z VDD VSS
+MP8 net012 B net7 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP7 net011 net3 net012 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP6 Z net012 VDD VDD sg13_lv_pmos m=1 w=1.535u l=130.00n ng=1 nrd=0 
++ nrs=0
+MP2 net7 A VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP4 net011 net7 VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP5 net3 B VDD VDD sg13_lv_pmos m=1 w=580.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN7 net012 B net011 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN6 net7 net3 net012 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN5 Z net012 VSS VSS sg13_lv_nmos m=1 w=775.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN2 net7 A VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN4 net3 B VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN3 net011 net7 VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 
++ nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_OA12X1 A B C Z VDD VSS
+MN2 net7 C VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN3 Z net17 VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN1 net17 B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MN0 net17 A net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MP0 net24 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP3 Z net17 VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 net17 B net24 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP2 net17 C VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I 
++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I 
++ ROW_CS WCLK WE_I VDD VSS
+XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2
+XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2
+XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2
+XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2
+XI77 col_we net9 net016 VDD VSS / RSC_IHPSG13_CNAND2X2
+XI76 col_re net9 net018 VDD VSS / RSC_IHPSG13_CNAND2X2
+XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4
+XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4
+XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8
+XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2
+XI8 net9 net8 VDD VSS / RSC_IHPSG13_CINVX2
+XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2
+XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2
+XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2
+XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2
+XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2
+XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2
+XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL
+XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4
+XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4
+XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4
+XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4
+XI6 PULSE_L PULSE_H net9 VDD VSS / RSC_IHPSG13_XOR2X2
+XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8
+XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8
+XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> 
++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> 
++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS
+XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI1<3> PADR<1> PADR<0> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2
+XI1<2> PADR<1> NADR<0> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2
+XI1<1> NADR<1> PADR<0> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2
+XI1<0> NADR<1> NADR<0> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2
+XI16<37> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<36> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<35> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<34> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<33> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<32> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<31> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<30> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2
+XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2
+XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2
+XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2
+XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL
+XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL
+XI17<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL
+XI17<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL
+XI17<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL
+XI17<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL
+.ENDS
+.SUBCKT RSC_IHPSG13_NOR2X2 A B Z VDD VSS
+MP1 Z B net9 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MN0 Z B VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MN1 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_CINVX4_WN A Z VDD VSS
+MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0
+MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_BLDRV BLC BLC_SEL BLT BLT_SEL PRE_N SEL_P WR_ONE WR_ZERO 
++ VDD VSS
+XCDEC SEL_P WR_ZERO BLC_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2
+XTDEC SEL_P WR_ONE BLT_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2
+MTWN BLT BLT_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MCWN BLC BLC_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MCWP BLC BLC_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 
++ nrd=0 nrs=0
+MTWP BLT BLT_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 
++ nrd=0 nrs=0
+MTSP BLT_SEL SEL_N BLT VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 
++ nrs=0
+MTPR BLT PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 
++ nrs=0
+MCSP BLC_SEL SEL_N BLC VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 
++ nrs=0
+MCPR BLC PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 
++ nrs=0
+XI86 SEL_P SEL_N VDD VSS / RSC_IHPSG13_INVX2
+XTINV BLC_PMOS_DRIVE BLT_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2
+XCINV BLT_PMOS_DRIVE BLC_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2
+.ENDS
+.SUBCKT RSC_IHPSG13_TIEH Z VDD VSS
+MN0 net2 net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP0 Z net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_MET3RES A B
+R0 B A lvsres w=2.6e-07 l=6e-07
+.ENDS
+.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2 CP DN DP QN QP VDD VSS
+MN12 SN RN DIFFP VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0
+MN13 TAIL CP VSS VSS sg13_lv_nmos m=1 w=2.4u l=130.00n ng=2 nrd=0 nrs=0
+MN9 DIFFP DP TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0
+MN10 DIFFN DN TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0
+MN11 RN SN DIFFN VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0
+MN19 net33 SN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN20 QN QP net37 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MN18 net37 RN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN17 QP QN net33 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MP15 SN RN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0
+MP16 RN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0
+MP14 DIFFP CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP12 RN SN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0
+MP13 DIFFN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP11 SN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0
+MP19 QN QP VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0
+MP20 QP SN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0
+MP18 QN RN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0
+MP17 QP QN VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_CBUFX2 A Z VDD VSS
+MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=540.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=1.1u l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_INVX4 A Z VDD VSS
+MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0
+MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> 
++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> 
++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R 
++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R 
++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS
+XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2
+XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2
+XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2
+XA_I44 A_WCLK_B_R A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES
+XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES
+XA_I91 A_RCLK_B_R A_RCLK_B_L / RSC_IHPSG13_MET3RES
+XA_R2 A_RCLK_R A_RCLK_L / RSC_IHPSG13_MET3RES
+XA_I90 A_WCLK_B_R A_WCLK_B_L / RSC_IHPSG13_MET3RES
+XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XA_I78 A_RCLK_B_R A_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XA_I50 A_WCLK_L A_WCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2
+XA_EBUF A_RCLK_R A_RCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLDRV13_FILL4 VDD VSS
+XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLDRV13_FILL4C2 VDD VSS
+XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> 
++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> 
++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> 
++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS
+XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL
+XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2
+XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net7<0> VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2
+XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2
+XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2
+XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2
+XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2
+XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2
+XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2
+XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2
+XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2
+XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+.SUBCKT RSC_IHPSG13_AND2X4 A B Z VDD VSS
+MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0
+MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0
+MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0
+MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0
+MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> 
++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> 
++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> 
++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> 
++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> 
++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> 
++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L 
++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L 
++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS
+XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2
+XA_I76 A_DO_WRITE_P A_DI_N A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4
+XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4
+XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4
+XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4
+XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4
+XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES
+XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES
+XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES
+XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES
+XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2
+XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> 
++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> 
++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> 
++ BIST_EN_I VDD VSS
+XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL
+XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL
+XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2
+XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net6<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2
+XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2
+XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2
+XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2
+XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2
+XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2
+XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2
+XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2
+XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> 
++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> 
++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> 
++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> 
++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L 
++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O 
++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS
+XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_R A_BM_I A_BM_R net23 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_I70<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XA_I44 A_BM_N A_WCLK_B_R A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_ADDR_DEC<6> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_ADDR_DEC<5> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<4> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES
+XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES
+XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES
+XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2
+XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2
+XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2
+XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_CORNER VDD_CORE VSS
+XI16 VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_1P_BITKIT_CORNER
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR A_WL B_WL NW PW VDD VSS
+MN1 VSS A_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MN0 VSS B_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> 
++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> 
++ A_WL<2> A_WL<1> A_WL<0> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> 
++ B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> 
++ B_WL<1> B_WL<0> VDD_CORE VSS
+XI0<15> A_WL<15> B_WL<15> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR
+XI0<14> A_WL<14> B_WL<14> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR
+XI0<13> A_WL<13> B_WL<13> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR
+XI0<12> A_WL<12> B_WL<12> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR
+XI0<11> A_WL<11> B_WL<11> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR
+XI0<10> A_WL<10> B_WL<10> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR
+XI0<9> A_WL<9> B_WL<9> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR
+XI0<8> A_WL<8> B_WL<8> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR
+XI0<7> A_WL<7> B_WL<7> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR
+XI0<6> A_WL<6> B_WL<6> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR
+XI0<5> A_WL<5> B_WL<5> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR
+XI0<4> A_WL<4> B_WL<4> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR
+XI0<3> A_WL<3> B_WL<3> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR
+XI0<2> A_WL<2> B_WL<2> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR
+XI0<1> A_WL<1> B_WL<1> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR
+XI0<0> A_WL<0> B_WL<0> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_LR
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL A_BLC_BOT A_BLC_TOP A_BLT_BOT A_BLT_TOP 
++ A_LWL A_RWL B_BLC_BOT B_BLC_TOP B_BLT_BOT B_BLT_TOP B_LWL B_RWL NW PW VDD VSS
+MN5 NC B_RWL B_BLC_BOT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MN4 B_BLT_BOT B_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MN0 NC NT VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0
+MN1 NT NC VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0
+MN3 NC A_RWL A_BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MN2 A_BLT_TOP A_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0
+MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0
+R5 B_RWL B_LWL lvsres w=2.6e-07 l=6e-07
+R4 B_BLC_BOT B_BLC_TOP lvsres w=2.6e-07 l=6e-07
+R3 B_BLT_BOT B_BLT_TOP lvsres w=2.6e-07 l=6e-07
+R1 A_BLC_BOT A_BLC_TOP lvsres w=2.6e-07 l=6e-07
+R0 A_BLT_BOT A_BLT_TOP lvsres w=2.6e-07 l=6e-07
+R2 A_RWL A_LWL lvsres w=2.6e-07 l=6e-07
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> 
++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> 
++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> 
++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> 
++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> 
++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> 
++ B_BLC_BOT<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_BOT<1> B_BLT_BOT<0> 
++ B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> 
++ B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> 
++ B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> 
++ B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> 
++ B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS
+XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_XWL<15> A_RWL<15> 
++ B_BLC_TOP<1> B_RBLC<15> B_BLT_TOP<1> B_RBLT<15> B_XWL<15> B_RWL<15> 
++ VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL
+XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_XWL<14> A_RWL<14> 
++ B_RBLC<14> B_RBLC<15> B_RBLT<14> B_RBLT<15> B_XWL<14> B_RWL<14> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL
+XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_XWL<13> A_RWL<13> 
++ B_RBLC<14> B_RBLC<13> B_RBLT<14> B_RBLT<13> B_XWL<13> B_RWL<13> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL
+XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_XWL<12> A_RWL<12> 
++ B_RBLC<12> B_RBLC<13> B_RBLT<12> B_RBLT<13> B_XWL<12> B_RWL<12> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL
+XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_XWL<11> A_RWL<11> 
++ B_RBLC<12> B_RBLC<11> B_RBLT<12> B_RBLT<11> B_XWL<11> B_RWL<11> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL
+XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_XWL<10> A_RWL<10> 
++ B_RBLC<10> B_RBLC<11> B_RBLT<10> B_RBLT<11> B_XWL<10> B_RWL<10> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL
+XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_XWL<9> A_RWL<9> 
++ B_RBLC<10> B_RBLC<9> B_RBLT<10> B_RBLT<9> B_XWL<9> B_RWL<9> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL
+XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_XWL<8> A_RWL<8> B_RBLC<8> 
++ B_RBLC<9> B_RBLT<8> B_RBLT<9> B_XWL<8> B_RWL<8> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL
+XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_XWL<7> A_RWL<7> B_RBLC<8> 
++ B_RBLC<7> B_RBLT<8> B_RBLT<7> B_XWL<7> B_RWL<7> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL
+XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_XWL<6> A_RWL<6> B_RBLC<6> 
++ B_RBLC<7> B_RBLT<6> B_RBLT<7> B_XWL<6> B_RWL<6> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL
+XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_XWL<5> A_RWL<5> B_RBLC<6> 
++ B_RBLC<5> B_RBLT<6> B_RBLT<5> B_XWL<5> B_RWL<5> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL
+XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_XWL<4> A_RWL<4> B_RBLC<4> 
++ B_RBLC<5> B_RBLT<4> B_RBLT<5> B_XWL<4> B_RWL<4> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL
+XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_XWL<3> A_RWL<3> B_RBLC<4> 
++ B_RBLC<3> B_RBLT<4> B_RBLT<3> B_XWL<3> B_RWL<3> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL
+XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_XWL<2> A_RWL<2> B_RBLC<2> 
++ B_RBLC<3> B_RBLT<2> B_RBLT<3> B_XWL<2> B_RWL<2> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL
+XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_XWL<1> A_RWL<1> B_RBLC<2> 
++ B_RBLC<1> B_RBLT<2> B_RBLT<1> B_XWL<1> B_RWL<1> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL
+XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_XWL<0> A_RWL<0> 
++ B_BLC_BOT<1> B_RBLC<1> B_BLT_BOT<1> B_RBLT<1> B_XWL<0> B_RWL<0> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL
+XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> A_XWL<15> 
++ B_BLC_TOP<0> B_LBLC<15> B_BLT_TOP<0> B_LBLT<15> B_LWL<15> B_XWL<15> 
++ VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL
+XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> A_XWL<14> 
++ B_LBLC<14> B_LBLC<15> B_LBLT<14> B_LBLT<15> B_LWL<14> B_XWL<14> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL
+XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> A_XWL<13> 
++ B_LBLC<14> B_LBLC<13> B_LBLT<14> B_LBLT<13> B_LWL<13> B_XWL<13> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL
+XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> A_XWL<12> 
++ B_LBLC<12> B_LBLC<13> B_LBLT<12> B_LBLT<13> B_LWL<12> B_XWL<12> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL
+XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> A_XWL<11> 
++ B_LBLC<12> B_LBLC<11> B_LBLT<12> B_LBLT<11> B_LWL<11> B_XWL<11> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL
+XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> A_XWL<10> 
++ B_LBLC<10> B_LBLC<11> B_LBLT<10> B_LBLT<11> B_LWL<10> B_XWL<10> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL
+XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> A_XWL<9> 
++ B_LBLC<10> B_LBLC<9> B_LBLT<10> B_LBLT<9> B_LWL<9> B_XWL<9> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL
+XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> A_XWL<8> B_LBLC<8> 
++ B_LBLC<9> B_LBLT<8> B_LBLT<9> B_LWL<8> B_XWL<8> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL
+XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> A_XWL<7> B_LBLC<8> 
++ B_LBLC<7> B_LBLT<8> B_LBLT<7> B_LWL<7> B_XWL<7> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL
+XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> A_XWL<6> B_LBLC<6> 
++ B_LBLC<7> B_LBLT<6> B_LBLT<7> B_LWL<6> B_XWL<6> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL
+XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> A_XWL<5> B_LBLC<6> 
++ B_LBLC<5> B_LBLT<6> B_LBLT<5> B_LWL<5> B_XWL<5> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL
+XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> A_XWL<4> B_LBLC<4> 
++ B_LBLC<5> B_LBLT<4> B_LBLT<5> B_LWL<4> B_XWL<4> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL
+XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> A_XWL<3> B_LBLC<4> 
++ B_LBLC<3> B_LBLT<4> B_LBLT<3> B_LWL<3> B_XWL<3> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL
+XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> A_XWL<2> B_LBLC<2> 
++ B_LBLC<3> B_LBLT<2> B_LBLT<3> B_LWL<2> B_XWL<2> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL
+XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> A_XWL<1> B_LBLC<2> 
++ B_LBLC<1> B_LBLT<2> B_LBLT<1> B_LWL<1> B_XWL<1> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL
+XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> A_XWL<0> 
++ B_BLC_BOT<0> B_LBLC<1> B_BLT_BOT<0> B_LBLT<1> B_LWL<0> B_XWL<0> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_CELL
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_TB A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> 
++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS
+XEDGE<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_TB
+XEDGE<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_TB
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_BITKIT_TAP A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> 
++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS
+XIEDGEBP_COL1<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_TB
+XIEDGEBP_COL1<0> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_TB
+XIEDGEBP_COL2<1> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_TB
+XIEDGEBP_COL2<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_EDGE_TB
+XITAP<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_TAP
+XITAP<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x16_c2_2P_BITKIT_TAP
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_BITKIT_TAP_LR NW PW VDD VSS
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_BITKIT_16x2_TAP_LR VDD_CORE VSS
+XCORNER<1> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_1P_BITKIT_CORNER
+XCORNER<0> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_1P_BITKIT_CORNER
+XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_1P_BITKIT_TAP_LR
+.ENDS
+
+.SUBCKT RSC_IHPSG13_CBUFX12 A Z VDD VSS
+MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=4.23u l=130.00n ng=6 nrd=0 nrs=0
+MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0
+MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0
+MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> 
++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> 
++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> 
++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> 
++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O 
++ VDD VSS
+XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12
+XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12
+XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12
+XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+.SUBCKT RSC_IHPSG13_WLDRVX12 A Z VDD VSS
+MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0
+MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0
+MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0
+MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> 
++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> 
++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS
+XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT 
++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> 
++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS
+XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2
+XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2
+XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2
+XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2
+XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4
+XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2
+XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2
+XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES
+XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES
+XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2
+XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2
+XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4
+XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2
+XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2
+XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2
+XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS
+XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2
+XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2
+XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4
+XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS
+XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2
+XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2
+XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4
+XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS
+XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2
+XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2
+XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS
+XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2
+XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> 
++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I 
++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> 
++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> 
++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> 
++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> 
++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> 
++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> 
++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> 
++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> 
++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> 
++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> 
++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> 
++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> 
++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> 
++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> 
++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> 
++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> 
++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> 
++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> 
++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> 
++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> 
++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> 
++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> 
++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> 
++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> 
++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> 
++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> 
++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> 
++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> 
++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> 
++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> 
++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> 
++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> 
++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> 
++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> 
++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> 
++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> 
++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> 
++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> 
++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> 
++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> 
++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> 
++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> 
++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> 
++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> 
++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> 
++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> 
++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> 
++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> 
++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> 
++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> 
++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> 
++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> 
++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> 
++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> 
++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> 
++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> 
++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> 
++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> 
++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> 
++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> 
++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> 
++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> 
++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> 
++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS
+XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> 
++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> 
++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> 
++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> 
++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> 
++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> 
++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> 
++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> 
++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> 
++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> 
++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> 
++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> 
++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> 
++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> 
++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> 
++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> 
++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> 
++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> 
++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> 
++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> 
++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> 
++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> 
++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> 
++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> 
++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> 
++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> 
++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> 
++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> 
++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> 
++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> 
++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> 
++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> 
++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> 
++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> 
++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> 
++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> 
++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> 
++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> 
++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> 
++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> 
++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> 
++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> 
++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> 
++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> 
++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> 
++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> 
++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> 
++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> 
++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> 
++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> 
++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> 
++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> 
++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> 
++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> 
++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> 
++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> 
++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> 
++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> 
++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> 
++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> 
++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> 
++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> 
++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> 
++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> 
++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> 
++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> 
++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> 
++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> 
++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> 
++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> 
++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> 
++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> 
++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> 
++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> 
++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> 
++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> 
++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> 
++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> 
++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> 
++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> 
++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> 
++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> 
++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> 
++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> 
++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> 
++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> 
++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04
+XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC02
+XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC02
+XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC02
+XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC02
+XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC02
+XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC02
+XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC02
+XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC02
+XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC02
+XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC02
+XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC01
+XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC01
+XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC01
+XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC01
+XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC01
+XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC01
+XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC01
+XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC01
+XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC01
+XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC01
+XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC01
+XL2<258> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<257> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<256> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<255> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<254> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<253> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<252> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<251> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<250> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<249> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<248> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<247> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<246> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<245> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<244> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<243> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<242> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<241> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<240> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<239> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<238> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<237> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<236> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<235> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<234> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<233> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<232> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<231> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<230> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<229> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<228> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<227> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<226> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<225> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<224> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<223> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<222> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<221> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<220> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<219> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<218> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<217> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<216> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<215> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<214> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<213> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<212> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<211> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<210> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<209> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<208> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<207> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<206> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<205> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<204> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<203> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<202> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<201> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<200> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<199> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<198> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<197> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<196> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<195> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<194> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<193> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<192> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<191> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<190> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<189> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<188> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<187> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<186> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<185> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<184> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<183> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<182> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<181> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<180> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<179> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<178> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<177> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<176> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<175> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<174> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<173> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC00
+XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC00
+XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC00
+XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC00
+XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC00
+XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC00
+XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC00
+XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC00
+XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC00
+XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC00
+XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC00
+XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC03
+XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC03
+XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC03
+XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC03
+XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC03
+XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC03
+XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC03
+XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC03
+XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC03
+XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC03
+XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> 
++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> 
++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> 
++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> 
++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> 
++ BIST_EN_I VDD VSS
+XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+.ENDS
+
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_DLY_MUX A SEL Z VDD VSS
+XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2
+XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1
+XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1
+XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1
+XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I 
++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I 
++ ROW_CS WCLK WE_I VDD VSS
+XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2
+XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2
+XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2
+XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2
+XI77 col_we net017 net016 VDD VSS / RSC_IHPSG13_CNAND2X2
+XI76 col_re net017 net018 VDD VSS / RSC_IHPSG13_CNAND2X2
+XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4
+XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4
+XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8
+XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2
+XI8 net017 net8 VDD VSS / RSC_IHPSG13_CINVX2
+XCAPS4<7> VDD VSS / RSC_IHPSG13_FILLCAP4
+XCAPS4<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XCAPS4<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XCAPS4<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XCAPS4<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XCAPS4<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XCAPS4<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL
+XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2
+XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2
+XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2
+XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2
+XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2
+XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4
+XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4
+XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4
+XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4
+XCAPS8<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XCAPS8<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XCAPS8<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XCAPS8<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XCAPS8<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XCAPS8<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XCAPS8<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI6 PULSE_L PULSE_H net017 VDD VSS / RSC_IHPSG13_XOR2X2
+XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2
+XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8
+XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8
+XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> 
++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> 
++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> 
++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS
+XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2
+XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net13<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net13<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2
+XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2
+XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2
+XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2
+XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2
+XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2
+XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2
+XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2
+XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2
+XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2
+XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_BLDRV A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL 
++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> 
++ A_SEL_P<1> A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> 
++ B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> 
++ B_SEL_P<2> B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS
+MA_CWN<3> A_BLC<3> A_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MA_CWN<2> A_BLC<2> A_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MA_CWN<1> A_BLC<1> A_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MA_CWN<0> A_BLC<0> A_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MA_TWN<3> A_BLT<3> A_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MA_TWN<2> A_BLT<2> A_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MA_TWN<1> A_BLT<1> A_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MA_TWN<0> A_BLT<0> A_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MB_TWN<3> B_BLT<3> B_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MB_TWN<2> B_BLT<2> B_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MB_TWN<1> B_BLT<1> B_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MB_TWN<0> B_BLT<0> B_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MB_CWN<3> B_BLC<3> B_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MB_CWN<2> B_BLC<2> B_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MB_CWN<1> B_BLC<1> B_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MB_CWN<0> B_BLC<0> B_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MA_CPR<3> A_BLC<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MA_CPR<2> A_BLC<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MA_CPR<1> A_BLC<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MA_CPR<0> A_BLC<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MA_TWP<3> A_BLT<3> A_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_TWP<2> A_BLT<2> A_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_TWP<1> A_BLT<1> A_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_TWP<0> A_BLT<0> A_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_CWP<3> A_BLC<3> A_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_CWP<2> A_BLC<2> A_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_CWP<1> A_BLC<1> A_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_CWP<0> A_BLC<0> A_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_TPR<3> A_BLT<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MA_TPR<2> A_BLT<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MA_TPR<1> A_BLT<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MA_TPR<0> A_BLT<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MA_TSP<3> A_BLT_SEL A_SEL_N<3> A_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_TSP<2> A_BLT_SEL A_SEL_N<2> A_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_TSP<1> A_BLT_SEL A_SEL_N<1> A_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_TSP<0> A_BLT_SEL A_SEL_N<0> A_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_CSP<3> A_BLC_SEL A_SEL_N<3> A_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_CSP<2> A_BLC_SEL A_SEL_N<2> A_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_CSP<1> A_BLC_SEL A_SEL_N<1> A_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_CSP<0> A_BLC_SEL A_SEL_N<0> A_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_CWP<3> B_BLC<3> B_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_CWP<2> B_BLC<2> B_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_CWP<1> B_BLC<1> B_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_CWP<0> B_BLC<0> B_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_TWP<3> B_BLT<3> B_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_TWP<2> B_BLT<2> B_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_TWP<1> B_BLT<1> B_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_TWP<0> B_BLT<0> B_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_TSP<3> B_BLT_SEL B_SEL_N<3> B_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_TSP<2> B_BLT_SEL B_SEL_N<2> B_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_TSP<1> B_BLT_SEL B_SEL_N<1> B_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_TSP<0> B_BLT_SEL B_SEL_N<0> B_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_TPR<3> B_BLT<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MB_TPR<2> B_BLT<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MB_TPR<1> B_BLT<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MB_TPR<0> B_BLT<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MB_CSP<3> B_BLC_SEL B_SEL_N<3> B_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_CSP<2> B_BLC_SEL B_SEL_N<2> B_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_CSP<1> B_BLC_SEL B_SEL_N<1> B_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_CSP<0> B_BLC_SEL B_SEL_N<0> B_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_CPR<3> B_BLC<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MB_CPR<2> B_BLC<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MB_CPR<1> B_BLC<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MB_CPR<0> B_BLC<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+XA_SEL<3> A_SEL_P<3> A_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2
+XA_SEL<2> A_SEL_P<2> A_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2
+XA_SEL<1> A_SEL_P<1> A_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2
+XA_SEL<0> A_SEL_P<0> A_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2
+XA_CINV<3> A_BLT_PMOS_DRIVE<3> A_BLC_NMOS_DRIVE<3> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XA_CINV<2> A_BLT_PMOS_DRIVE<2> A_BLC_NMOS_DRIVE<2> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XA_CINV<1> A_BLT_PMOS_DRIVE<1> A_BLC_NMOS_DRIVE<1> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XA_CINV<0> A_BLT_PMOS_DRIVE<0> A_BLC_NMOS_DRIVE<0> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XA_TINV<3> A_BLC_PMOS_DRIVE<3> A_BLT_NMOS_DRIVE<3> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XA_TINV<2> A_BLC_PMOS_DRIVE<2> A_BLT_NMOS_DRIVE<2> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XA_TINV<1> A_BLC_PMOS_DRIVE<1> A_BLT_NMOS_DRIVE<1> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XA_TINV<0> A_BLC_PMOS_DRIVE<0> A_BLT_NMOS_DRIVE<0> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XB_SEL<3> B_SEL_P<3> B_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2
+XB_SEL<2> B_SEL_P<2> B_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2
+XB_SEL<1> B_SEL_P<1> B_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2
+XB_SEL<0> B_SEL_P<0> B_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2
+XB_TINV<3> B_BLC_PMOS_DRIVE<3> B_BLT_NMOS_DRIVE<3> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XB_TINV<2> B_BLC_PMOS_DRIVE<2> B_BLT_NMOS_DRIVE<2> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XB_TINV<1> B_BLC_PMOS_DRIVE<1> B_BLT_NMOS_DRIVE<1> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XB_TINV<0> B_BLC_PMOS_DRIVE<0> B_BLT_NMOS_DRIVE<0> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XB_CINV<3> B_BLT_PMOS_DRIVE<3> B_BLC_NMOS_DRIVE<3> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XB_CINV<2> B_BLT_PMOS_DRIVE<2> B_BLC_NMOS_DRIVE<2> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XB_CINV<1> B_BLT_PMOS_DRIVE<1> B_BLC_NMOS_DRIVE<1> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XB_CINV<0> B_BLT_PMOS_DRIVE<0> B_BLC_NMOS_DRIVE<0> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XA_TDEC<3> A_SEL_P<3> A_WR_ONE A_BLT_PMOS_DRIVE<3> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XA_TDEC<2> A_SEL_P<2> A_WR_ONE A_BLT_PMOS_DRIVE<2> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XA_TDEC<1> A_SEL_P<1> A_WR_ONE A_BLT_PMOS_DRIVE<1> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XA_TDEC<0> A_SEL_P<0> A_WR_ONE A_BLT_PMOS_DRIVE<0> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XA_CDEC<3> A_SEL_P<3> A_WR_ZERO A_BLC_PMOS_DRIVE<3> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XA_CDEC<2> A_SEL_P<2> A_WR_ZERO A_BLC_PMOS_DRIVE<2> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XA_CDEC<1> A_SEL_P<1> A_WR_ZERO A_BLC_PMOS_DRIVE<1> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XA_CDEC<0> A_SEL_P<0> A_WR_ZERO A_BLC_PMOS_DRIVE<0> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XB_CDEC<3> B_SEL_P<3> B_WR_ZERO B_BLC_PMOS_DRIVE<3> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XB_CDEC<2> B_SEL_P<2> B_WR_ZERO B_BLC_PMOS_DRIVE<2> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XB_CDEC<1> B_SEL_P<1> B_WR_ZERO B_BLC_PMOS_DRIVE<1> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XB_CDEC<0> B_SEL_P<0> B_WR_ZERO B_BLC_PMOS_DRIVE<0> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XB_TDEC<3> B_SEL_P<3> B_WR_ONE B_BLT_PMOS_DRIVE<3> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XB_TDEC<2> B_SEL_P<2> B_WR_ONE B_BLT_PMOS_DRIVE<2> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XB_TDEC<1> B_SEL_P<1> B_WR_ONE B_BLT_PMOS_DRIVE<1> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XB_TDEC<0> B_SEL_P<0> B_WR_ONE B_BLT_PMOS_DRIVE<0> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+.ENDS
+.SUBCKT RSC_IHPSG13_AND2X6 A B Z VDD VSS
+MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=2.94u l=130.00n ng=3 nrd=0 nrs=0
+MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0
+MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0
+MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=4.86u l=130.00n ng=3 nrd=0 nrs=0
+MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> 
++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> 
++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> 
++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> 
++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> 
++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> 
++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> 
++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> 
++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> 
++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> 
++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> 
++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R 
++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R 
++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL<1> B_ADDR_COL<0> 
++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> 
++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I 
++ B_BIST_EN_I B_BLC<31> B_BLC<30> B_BLC<29> B_BLC<28> B_BLC<27> B_BLC<26> 
++ B_BLC<25> B_BLC<24> B_BLC<23> B_BLC<22> B_BLC<21> B_BLC<20> B_BLC<19> 
++ B_BLC<18> B_BLC<17> B_BLC<16> B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> 
++ B_BLC<11> B_BLC<10> B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> 
++ B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> 
++ B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT<23> B_BLT<22> B_BLT<21> 
++ B_BLT<20> B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT<15> B_BLT<14> 
++ B_BLT<13> B_BLT<12> B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> 
++ B_BLT<5> B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L 
++ B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L 
++ B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS
+XB_I80<1> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<1> VDD VSS / 
++ RSC_IHPSG13_AND2X2
+XB_I80<0> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<0> VDD VSS / 
++ RSC_IHPSG13_AND2X2
+XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / 
++ RSC_IHPSG13_AND2X2
+XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / 
++ RSC_IHPSG13_AND2X2
+XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XB_INV<6> B_N1<1> B_P1<1> VDD VSS / RSC_IHPSG13_CINVX4
+XB_INV<5> B_N0<1> B_P0<1> VDD VSS / RSC_IHPSG13_CINVX4
+XB_INV<4> B_N0<0> B_P0<0> VDD VSS / RSC_IHPSG13_CINVX4
+XB_INV<3> B_ADDR_COL<1> B_N1<1> VDD VSS / RSC_IHPSG13_CINVX4
+XB_INV<2> B_ADDR_COL<1> B_N1<0> VDD VSS / RSC_IHPSG13_CINVX4
+XB_INV<1> B_ADDR_COL<0> B_N0<1> VDD VSS / RSC_IHPSG13_CINVX4
+XB_INV<0> B_ADDR_COL<0> B_N0<0> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4
+XB_I81<3> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XB_I81<2> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XB_I81<1> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XB_I81<0> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XI_FILL8<78> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<77> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<76> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<75> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<74> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<73> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<72> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<71> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<70> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<69> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<68> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<67> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<66> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<65> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<64> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<63> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<62> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<61> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<60> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<59> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<58> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<57> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<56> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<55> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<54> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<53> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<52> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<51> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<50> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<49> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<48> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<47> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<46> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<45> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<44> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<43> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<42> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<41> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<40> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<39> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<38> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<37> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<36> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<35> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<34> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<33> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<32> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<31> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<30> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XAB_BLMUX<7> A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC_SEL A_BLT<31> 
++ A_BLT<30> A_BLT<29> A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<31> A_SEL_P<30> 
++ A_SEL_P<29> A_SEL_P<28> A_WR_ONE A_WR_ZERO B_BLC<31> B_BLC<30> B_BLC<29> 
++ B_BLC<28> B_BLC_SEL B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> B_BLT_SEL 
++ B_PRE_N B_SEL_P<31> B_SEL_P<30> B_SEL_P<29> B_SEL_P<28> B_WR_ONE B_WR_ZERO 
++ VDD VSS / RM_IHPSG13_1024x16_c2_2P_BLDRV
+XAB_BLMUX<6> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC_SEL A_BLT<27> 
++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<27> A_SEL_P<26> 
++ A_SEL_P<25> A_SEL_P<24> A_WR_ONE A_WR_ZERO B_BLC<27> B_BLC<26> B_BLC<25> 
++ B_BLC<24> B_BLC_SEL B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT_SEL 
++ B_PRE_N B_SEL_P<27> B_SEL_P<26> B_SEL_P<25> B_SEL_P<24> B_WR_ONE B_WR_ZERO 
++ VDD VSS / RM_IHPSG13_1024x16_c2_2P_BLDRV
+XAB_BLMUX<5> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC_SEL A_BLT<23> 
++ A_BLT<22> A_BLT<21> A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<23> A_SEL_P<22> 
++ A_SEL_P<21> A_SEL_P<20> A_WR_ONE A_WR_ZERO B_BLC<23> B_BLC<22> B_BLC<21> 
++ B_BLC<20> B_BLC_SEL B_BLT<23> B_BLT<22> B_BLT<21> B_BLT<20> B_BLT_SEL 
++ B_PRE_N B_SEL_P<23> B_SEL_P<22> B_SEL_P<21> B_SEL_P<20> B_WR_ONE B_WR_ZERO 
++ VDD VSS / RM_IHPSG13_1024x16_c2_2P_BLDRV
+XAB_BLMUX<4> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC_SEL A_BLT<19> 
++ A_BLT<18> A_BLT<17> A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<19> A_SEL_P<18> 
++ A_SEL_P<17> A_SEL_P<16> A_WR_ONE A_WR_ZERO B_BLC<19> B_BLC<18> B_BLC<17> 
++ B_BLC<16> B_BLC_SEL B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT_SEL 
++ B_PRE_N B_SEL_P<19> B_SEL_P<18> B_SEL_P<17> B_SEL_P<16> B_WR_ONE B_WR_ZERO 
++ VDD VSS / RM_IHPSG13_1024x16_c2_2P_BLDRV
+XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> 
++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> 
++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> 
++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL 
++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO 
++ VDD VSS / RM_IHPSG13_1024x16_c2_2P_BLDRV
+XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> 
++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> 
++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> 
++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N 
++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD 
++ VSS / RM_IHPSG13_1024x16_c2_2P_BLDRV
+XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> 
++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> 
++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL 
++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> 
++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_BLDRV
+XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> 
++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> 
++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL 
++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> 
++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_BLDRV
+XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8
+XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8
+XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8
+XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8
+XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8
+XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8
+XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6
+XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6
+XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6
+XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6
+XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<31> net041<0> B_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<30> net041<1> B_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<29> net041<2> B_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<28> net041<3> B_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<27> net041<4> B_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<26> net041<5> B_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<25> net041<6> B_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<24> net041<7> B_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<23> net041<8> B_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<22> net041<9> B_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<21> net041<10> B_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<20> net041<11> B_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<19> net041<12> B_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<18> net041<13> B_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<17> net041<14> B_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<16> net041<15> B_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<15> net041<16> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<14> net041<17> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<13> net041<18> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<12> net041<19> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<11> net041<20> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<10> net041<21> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<9> net041<22> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<8> net041<23> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<7> net041<24> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<6> net041<25> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<5> net041<26> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<4> net041<27> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<3> net041<28> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<2> net041<29> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<1> net041<30> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<0> net041<31> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2
+XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2
+XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net042 VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XB_DEC3<31> B_P1<1> B_P0<1> B_ADDR_DEC<7> net041<0> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<30> B_P1<1> B_P0<1> B_ADDR_DEC<6> net041<1> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<29> B_P1<1> B_P0<1> B_ADDR_DEC<5> net041<2> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<28> B_P1<1> B_P0<1> B_ADDR_DEC<4> net041<3> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<27> B_P1<1> B_P0<1> B_ADDR_DEC<3> net041<4> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<26> B_P1<1> B_P0<1> B_ADDR_DEC<2> net041<5> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<25> B_P1<1> B_P0<1> B_ADDR_DEC<1> net041<6> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<24> B_P1<1> B_P0<1> B_ADDR_DEC<0> net041<7> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<23> B_P1<1> B_N0<1> B_ADDR_DEC<7> net041<8> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<22> B_P1<1> B_N0<1> B_ADDR_DEC<6> net041<9> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<21> B_P1<1> B_N0<1> B_ADDR_DEC<5> net041<10> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<20> B_P1<1> B_N0<1> B_ADDR_DEC<4> net041<11> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<19> B_P1<1> B_N0<1> B_ADDR_DEC<3> net041<12> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<18> B_P1<1> B_N0<1> B_ADDR_DEC<2> net041<13> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<17> B_P1<1> B_N0<1> B_ADDR_DEC<1> net041<14> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<16> B_P1<1> B_N0<1> B_ADDR_DEC<0> net041<15> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<15> B_N1<0> B_P0<0> B_ADDR_DEC<7> net041<16> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<14> B_N1<0> B_P0<0> B_ADDR_DEC<6> net041<17> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<13> B_N1<0> B_P0<0> B_ADDR_DEC<5> net041<18> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<12> B_N1<0> B_P0<0> B_ADDR_DEC<4> net041<19> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<11> B_N1<0> B_P0<0> B_ADDR_DEC<3> net041<20> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<10> B_N1<0> B_P0<0> B_ADDR_DEC<2> net041<21> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<9> B_N1<0> B_P0<0> B_ADDR_DEC<1> net041<22> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<8> B_N1<0> B_P0<0> B_ADDR_DEC<0> net041<23> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<7> B_N1<0> B_N0<0> B_ADDR_DEC<7> net041<24> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<6> B_N1<0> B_N0<0> B_ADDR_DEC<6> net041<25> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<5> B_N1<0> B_N0<0> B_ADDR_DEC<5> net041<26> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<4> B_N1<0> B_N0<0> B_ADDR_DEC<4> net041<27> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<3> B_N1<0> B_N0<0> B_ADDR_DEC<3> net041<28> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<2> B_N1<0> B_N0<0> B_ADDR_DEC<2> net041<29> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<1> B_N1<0> B_N0<0> B_ADDR_DEC<1> net041<30> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<0> B_N1<0> B_N0<0> B_ADDR_DEC<0> net041<31> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES
+XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES
+XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES
+XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES
+XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES
+XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES
+XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLDRV13_FILL4 VDD VSS
+XI0<11> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<10> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+
+
+.SUBCKT RSC_IHPSG13_CBUFX16 A Z VDD VSS
+MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=2.115u l=130.00n ng=3 nrd=0 nrs=0
+MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=5.64u l=130.00n ng=8 nrd=0 nrs=0
+MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=13.000u l=130.00n ng=8 nrd=0 
++ nrs=0
+MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=4.89u l=130.00n ng=3 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> 
++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> 
++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> 
++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> 
++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O 
++ VDD VSS
+XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8
+XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16
+XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16
+XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16
+.ENDS
+.SUBCKT RSC_IHPSG13_WLDRVX16 A Z VDD VSS
+MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0
+MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0
+MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=12.96u l=130.00n ng=8 nrd=0 nrs=0
+MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> 
++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> 
++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS
+XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> 
++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> 
++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> 
++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> 
++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O 
++ VDD VSS
+XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4
+XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4
+XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4
+XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI1 VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> 
++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> 
++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS
+XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> 
++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> 
++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> 
++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> 
++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> 
++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> 
++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> 
++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> 
++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> 
++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> 
++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> 
++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> 
++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> 
++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> 
++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> 
++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> 
++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> 
++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> 
++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> 
++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> 
++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> 
++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> 
++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> 
++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> 
++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> 
++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> 
++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> 
++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> 
++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> 
++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> 
++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> 
++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> 
++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> 
++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> 
++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> 
++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> 
++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS
+XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC03
+XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC03
+XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC03
+XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC03
+XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC03
+XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> 
++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> 
++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> 
++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> 
++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> 
++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> 
++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> 
++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> 
++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> 
++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> 
++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> 
++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> 
++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> 
++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> 
++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> 
++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> 
++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> 
++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> 
++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> 
++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> 
++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> 
++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> 
++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> 
++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> 
++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> 
++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> 
++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> 
++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> 
++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> 
++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> 
++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> 
++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> 
++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> 
++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> 
++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> 
++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> 
++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> 
++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> 
++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04
+XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC02
+XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC02
+XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC02
+XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC02
+XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC02
+XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC00
+XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC00
+XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC00
+XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC00
+XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC00
+XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC01
+XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC01
+XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC01
+XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC01
+XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC01
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> 
++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> 
++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> 
++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> 
++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS
+XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI10 VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> 
++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> 
++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> 
++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS
+XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2
+XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net12<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net12<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2
+XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2
+XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2
+XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2
+XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2
+XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2
+XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2
+XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2
+XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2
+XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> 
++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> 
++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> 
++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> 
++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> 
++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> 
++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L 
++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L 
++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL 
++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> 
++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I 
++ B_BIST_EN_I B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> B_BLC<11> B_BLC<10> 
++ B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC<3> B_BLC<2> 
++ B_BLC<1> B_BLC<0> B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT<11> 
++ B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT<3> 
++ B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R 
++ B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L 
++ B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS
+XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2
+XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2
+XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4
+XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4
+XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4
+XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4
+XI_FILL4<26> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<25> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<24> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<23> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<22> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<21> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<20> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<19> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<18> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<17> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4
+XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4
+XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4
+XB_INV<1> B_N0 B_P0 VDD VSS / RSC_IHPSG13_CINVX4
+XB_INV<0> B_ADDR_COL B_N0 VDD VSS / RSC_IHPSG13_CINVX4
+XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4
+XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4
+XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4
+XB_I81<1> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XB_I81<0> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES
+XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES
+XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES
+XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES
+XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES
+XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES
+XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES
+XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES
+XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> 
++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> 
++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> 
++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL 
++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO 
++ VDD VSS / RM_IHPSG13_1024x16_c2_2P_BLDRV
+XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> 
++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> 
++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> 
++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N 
++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD 
++ VSS / RM_IHPSG13_1024x16_c2_2P_BLDRV
+XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> 
++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> 
++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL 
++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> 
++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_BLDRV
+XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> 
++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> 
++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL 
++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> 
++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_BLDRV
+XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2
+XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<15> net044<0> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<14> net044<1> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<13> net044<2> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<12> net044<3> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<11> net044<4> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<10> net044<5> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<9> net044<6> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<8> net044<7> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<7> net044<8> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<6> net044<9> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<5> net044<10> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<4> net044<11> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<3> net044<12> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<2> net044<13> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<1> net044<14> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<0> net044<15> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2
+XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<15> B_P0 B_ADDR_DEC<7> net044<0> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<14> B_P0 B_ADDR_DEC<6> net044<1> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<13> B_P0 B_ADDR_DEC<5> net044<2> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<12> B_P0 B_ADDR_DEC<4> net044<3> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<11> B_P0 B_ADDR_DEC<3> net044<4> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<10> B_P0 B_ADDR_DEC<2> net044<5> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<9> B_P0 B_ADDR_DEC<1> net044<6> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<8> B_P0 B_ADDR_DEC<0> net044<7> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<7> B_N0 B_ADDR_DEC<7> net044<8> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<6> B_N0 B_ADDR_DEC<6> net044<9> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<5> B_N0 B_ADDR_DEC<5> net044<10> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<4> B_N0 B_ADDR_DEC<4> net044<11> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<3> B_N0 B_ADDR_DEC<3> net044<12> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<2> B_N0 B_ADDR_DEC<2> net044<13> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<1> B_N0 B_ADDR_DEC<1> net044<14> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<0> B_N0 B_ADDR_DEC<0> net044<15> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> 
++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS
+XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC00
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04
+XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC01
+XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> 
++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> 
++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> 
++ BIST_EN_I VDD VSS
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> 
++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> 
++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> 
++ BIST_EN_I VDD VSS
+XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2
+XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL
+XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL
+XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2
+XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2
+XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2
+XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2
+XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2
+XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2
+XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2
+XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2
+XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2P CP DN DP QN QP VDD VSS
+XI_AMP CP DN DP QN QP VDD VSS / RSC_IHPSG13_DFPQD_MSAFFX2
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> 
++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> 
++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> 
++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> 
++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L 
++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O 
++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<7> B_ADDR_DEC<6> 
++ B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> 
++ B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<7> B_BLC<6> B_BLC<5> 
++ B_BLC<4> B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<7> B_BLT<6> B_BLT<5> 
++ B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R 
++ B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R 
++ B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS
+XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net044 VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2P
+XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2P
+XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> 
++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> A_ADDR_DEC<6> 
++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> 
++ B_BLC<4> B_BLC_SEL B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N 
++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_WR_ONE B_WR_ZERO 
++ VDD VSS / RM_IHPSG13_1024x16_c2_2P_BLDRV
+XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> 
++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> 
++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> 
++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N 
++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO 
++ VDD VSS / RM_IHPSG13_1024x16_c2_2P_BLDRV
+XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES
+XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES
+XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES
+XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES
+XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES
+XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES
+XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I80 B_WCLK_B_L B_RCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2
+XB_I76 B_DO_WRITE_P B_DI_N B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2
+XB_I75 B_DO_WRITE_P B_DI_R B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2
+XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2
+XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2
+XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2
+XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> 
++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> 
++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> 
++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> 
++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> 
++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> 
++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> 
++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> 
++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> 
++ WL_O<2> WL_O<1> WL_O<0> VDD VSS
+XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC02
+XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC00
+XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> 
++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> 
++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04
+XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC03
+XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC01
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> 
++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> 
++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> 
++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS
+XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> 
++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> 
++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> 
++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> 
++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O 
++ VDD VSS
+XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16
+XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16
+XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16
+XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XI1<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI1<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> 
++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> 
++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS
+XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS
+XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4
+XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2
+XI2 VDD VSS / RSC_IHPSG13_FILLCAP4
+XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS
+XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4
+XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2
+XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2
+XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI1 VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> 
++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC01
+XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC00
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04
+XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> 
++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> 
++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> 
++ BIST_EN_I VDD VSS
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> 
++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> 
++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> 
++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS
+XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2
+XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2
+XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net7<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net7<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2
+XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2
+XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2
+XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2
+XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2
+XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2
+XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2
+XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2
+XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> 
++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> 
++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> 
++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> 
++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> 
++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> 
++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> 
++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> 
++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> 
++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> 
++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> 
++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R 
++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R 
++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS
+XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / 
++ RSC_IHPSG13_AND2X2
+XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / 
++ RSC_IHPSG13_AND2X2
+XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XI80<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4
+XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_BLTMUX<31> A_BLC<31> A_BLC_SEL A_BLT<31> A_BLT_SEL A_PRE_N A_SEL_P<31> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<30> A_BLC<30> A_BLC_SEL A_BLT<30> A_BLT_SEL A_PRE_N A_SEL_P<30> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<29> A_BLC<29> A_BLC_SEL A_BLT<29> A_BLT_SEL A_PRE_N A_SEL_P<29> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<28> A_BLC<28> A_BLC_SEL A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<28> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<27> A_BLC<27> A_BLC_SEL A_BLT<27> A_BLT_SEL A_PRE_N A_SEL_P<27> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<26> A_BLC<26> A_BLC_SEL A_BLT<26> A_BLT_SEL A_PRE_N A_SEL_P<26> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<25> A_BLC<25> A_BLC_SEL A_BLT<25> A_BLT_SEL A_PRE_N A_SEL_P<25> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<24> A_BLC<24> A_BLC_SEL A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<24> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<23> A_BLC<23> A_BLC_SEL A_BLT<23> A_BLT_SEL A_PRE_N A_SEL_P<23> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<22> A_BLC<22> A_BLC_SEL A_BLT<22> A_BLT_SEL A_PRE_N A_SEL_P<22> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<21> A_BLC<21> A_BLC_SEL A_BLT<21> A_BLT_SEL A_PRE_N A_SEL_P<21> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<20> A_BLC<20> A_BLC_SEL A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<20> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<19> A_BLC<19> A_BLC_SEL A_BLT<19> A_BLT_SEL A_PRE_N A_SEL_P<19> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<18> A_BLC<18> A_BLC_SEL A_BLT<18> A_BLT_SEL A_PRE_N A_SEL_P<18> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<17> A_BLC<17> A_BLC_SEL A_BLT<17> A_BLT_SEL A_PRE_N A_SEL_P<17> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<16> A_BLC<16> A_BLC_SEL A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<16> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x16_c2_1P_BLDRV
+XA_CAPS<17> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<16> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<15> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<14> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<13> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<12> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<11> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<10> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<9> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8
+XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8
+XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8
+XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6
+XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6
+XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2
+XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES
+XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES
+XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES
+XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+.ENDS
+
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> 
++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> 
++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> 
++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> 
++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O 
++ VDD VSS
+XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8
+XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12
+XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12
+XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> 
++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> 
++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS
+XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12
+.ENDS
+
+
+
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> 
++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> 
++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> 
++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> 
++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O 
++ VDD VSS
+XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8
+XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8
+XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8
+XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+.SUBCKT RSC_IHPSG13_WLDRVX8 A Z VDD VSS
+MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0
+MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0
+MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0
+MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> 
++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> 
++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS
+XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8
+.ENDS
+
+
+
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> 
++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> 
++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS
+XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI1<3> PADR<0> PADR<1> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2
+XI1<2> NADR<0> PADR<1> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2
+XI1<1> PADR<0> NADR<1> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2
+XI1<0> NADR<0> NADR<1> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2
+XI17<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL
+XI17<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL
+XI14<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL
+XI14<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL
+XI14<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL
+XI14<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL
+XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2
+XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2
+XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2
+XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2
+XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI15<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI15<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI15<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI15<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI15<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI19<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI19<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI19<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI19<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> 
++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> 
++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R 
++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R 
++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<3> B_ADDR_DEC<2> 
++ B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<3> 
++ B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I 
++ B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R 
++ B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD 
++ VSS
+XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XB_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4
+XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2
+XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2
+XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2
+XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2
+XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2
+XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2
+XB_I44 B_WCLK_B_L B_BM_N B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XA_I44 A_WCLK_B_L A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES
+XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES
+XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES
+XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES
+XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES
+XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES
+XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES
+XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES
+XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES
+XAB_BLMUX A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> 
++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> 
++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> 
++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N 
++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO 
++ VDD VSS / RM_IHPSG13_1024x16_c2_2P_BLDRV
+XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net039 net040 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XB_I51 net039 B_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_COLDRV13_FILL4C2 VDD VSS
+XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> 
++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> 
++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> 
++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> 
++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> 
++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> 
++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> 
++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> 
++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> 
++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> 
++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> 
++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> 
++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> 
++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> 
++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> 
++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> 
++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> 
++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> 
++ VDD VSS
+XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> 
++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> 
++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> 
++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> 
++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> 
++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> 
++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> 
++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> 
++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> 
++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> 
++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> 
++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> 
++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> 
++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> 
++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04
+XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC03
+XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC03
+XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC01
+XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC01
+XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC01
+XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC02
+XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC02
+XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC00
+XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC00
+XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_2P_DEC00
+XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> 
++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> 
++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> 
++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> 
++ BIST_ADDR_I<0> BIST_EN_I VDD VSS
+XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<0> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> 
++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> 
++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> 
++ VDD VSS
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> 
++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> 
++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> 
++ WL_O<0> VDD VSS / RM_IHPSG13_1024x16_c2_2P_DEC04
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_2P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> 
++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> 
++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net7<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net7<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net7<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net7<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI12<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_BITKIT_TAP BLC BLT NW PW VDD VSS
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> 
++ VDD_CORE VSS
+XITAP<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_1024x16_c2_1P_BITKIT_TAP
+XITAP<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_1024x16_c2_1P_BITKIT_TAP
+XIEDGEBP_COL1<1> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE 
++ VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_TB
+XIEDGEBP_COL1<0> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE 
++ VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_TB
+XIEDGEBP_COL2<1> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE 
++ VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_TB
+XIEDGEBP_COL2<0> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE 
++ VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_EDGE_TB
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_TAP_LR VDD_CORE VSS
+XCORNER<1> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_1P_BITKIT_CORNER
+XCORNER<0> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_1P_BITKIT_CORNER
+XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x16_c2_1P_BITKIT_TAP_LR
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS
+XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4
+XI0 VDD VSS / RSC_IHPSG13_FILLCAP4
+XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS
+XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4
+XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2
+XI2 VDD VSS / RSC_IHPSG13_FILLCAP4
+XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> 
++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> 
++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> 
++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> 
++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> 
++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> 
++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> 
++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> 
++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> 
++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> 
++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> 
++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> 
++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> 
++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> 
++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> 
++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> 
++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> 
++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> 
++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> 
++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> 
++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> 
++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> 
++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> 
++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> 
++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> 
++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> 
++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> 
++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> 
++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> 
++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> 
++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> 
++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> 
++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> 
++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> 
++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> 
++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> 
++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS
+XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC03
+XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC03
+XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC03
+XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC03
+XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC03
+XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC02
+XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC02
+XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC02
+XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC02
+XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC02
+XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC00
+XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC00
+XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC00
+XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC00
+XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC00
+XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> 
++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> 
++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> 
++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> 
++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> 
++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> 
++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> 
++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> 
++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> 
++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> 
++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> 
++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> 
++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> 
++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> 
++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> 
++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> 
++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> 
++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> 
++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> 
++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> 
++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> 
++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> 
++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> 
++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> 
++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> 
++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> 
++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> 
++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> 
++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> 
++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> 
++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> 
++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> 
++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> 
++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> 
++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> 
++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> 
++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> 
++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> 
++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04
+XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC01
+XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC01
+XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC01
+XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC01
+XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC01
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> 
++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> 
++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> 
++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> 
++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS
+XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> 
++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I 
++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> 
++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> 
++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> 
++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> 
++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> 
++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> 
++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> 
++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> 
++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> 
++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> 
++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> 
++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> 
++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> 
++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> 
++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> 
++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> 
++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> 
++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> 
++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> 
++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> 
++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> 
++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> 
++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> 
++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> 
++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> 
++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> 
++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> 
++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> 
++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> 
++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> 
++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> 
++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> 
++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> 
++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> 
++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> 
++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> 
++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> 
++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> 
++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> 
++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> 
++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> 
++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> 
++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> 
++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> 
++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> 
++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> 
++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> 
++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> 
++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> 
++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> 
++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> 
++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> 
++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> 
++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> 
++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> 
++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> 
++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> 
++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> 
++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> 
++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> 
++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> 
++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> 
++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> 
++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS
+XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC03
+XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC03
+XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC03
+XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC03
+XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC03
+XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC03
+XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC03
+XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC03
+XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC03
+XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC03
+XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC00
+XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC00
+XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC00
+XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC00
+XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC00
+XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC00
+XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC00
+XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC00
+XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC00
+XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC00
+XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC00
+XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> 
++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> 
++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> 
++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> 
++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> 
++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> 
++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> 
++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> 
++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> 
++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> 
++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> 
++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> 
++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> 
++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> 
++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> 
++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> 
++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> 
++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> 
++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> 
++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> 
++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> 
++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> 
++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> 
++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> 
++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> 
++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> 
++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> 
++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> 
++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> 
++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> 
++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> 
++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> 
++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> 
++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> 
++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> 
++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> 
++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> 
++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> 
++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> 
++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> 
++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> 
++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> 
++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> 
++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> 
++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> 
++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> 
++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> 
++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> 
++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> 
++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> 
++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> 
++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> 
++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> 
++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> 
++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> 
++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> 
++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> 
++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> 
++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> 
++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> 
++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> 
++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> 
++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> 
++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> 
++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> 
++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> 
++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> 
++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> 
++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> 
++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> 
++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> 
++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> 
++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> 
++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> 
++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> 
++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> 
++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> 
++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> 
++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> 
++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> 
++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> 
++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> 
++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> 
++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> 
++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> 
++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> 
++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04
+XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC01
+XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC01
+XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC01
+XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC01
+XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC01
+XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC01
+XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC01
+XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC01
+XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC01
+XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC01
+XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC01
+XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC02
+XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC02
+XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC02
+XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC02
+XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC02
+XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC02
+XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC02
+XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC02
+XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC02
+XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC02
+XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> 
++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> 
++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> 
++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> 
++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> 
++ BIST_EN_I VDD VSS
+XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+.ENDS
+
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> 
++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> 
++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> 
++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> 
++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> 
++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> 
++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> 
++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> 
++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> 
++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> 
++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> 
++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> 
++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> 
++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> 
++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> 
++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> 
++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> 
++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> 
++ VDD VSS
+XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC03
+XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC03
+XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC02
+XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC02
+XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> 
++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> 
++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> 
++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> 
++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> 
++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> 
++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> 
++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> 
++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> 
++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> 
++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> 
++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> 
++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> 
++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> 
++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04
+XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC00
+XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC00
+XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC00
+XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC01
+XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC01
+XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC01
+XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> 
++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> 
++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> 
++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> 
++ BIST_ADDR_I<0> BIST_EN_I VDD VSS
+XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> 
++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> 
++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> 
++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> 
++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O 
++ VDD VSS
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8
+XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8
+XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> 
++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> 
++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS
+XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8
+.ENDS
+
+
+
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> 
++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> 
++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> 
++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> 
++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> 
++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> 
++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> 
++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> 
++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> 
++ WL_O<2> WL_O<1> WL_O<0> VDD VSS
+XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC03
+XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC00
+XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC01
+XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / 
++ RM_IHPSG13_1024x16_c2_1P_DEC02
+XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> 
++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> 
++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x16_c2_1P_DEC04
+XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> 
++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> 
++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> 
++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS
+XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_COLUMN_pcell_0 A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<255> A_LWL<254> A_LWL<253> A_LWL<252> A_LWL<251> A_LWL<250> A_LWL<249> A_LWL<248> A_LWL<247> A_LWL<246> A_LWL<245> A_LWL<244> A_LWL<243> A_LWL<242> A_LWL<241> A_LWL<240> A_LWL<239> A_LWL<238> A_LWL<237> A_LWL<236> A_LWL<235> A_LWL<234> A_LWL<233> A_LWL<232> A_LWL<231> A_LWL<230> A_LWL<229> A_LWL<228> A_LWL<227> A_LWL<226> A_LWL<225> A_LWL<224> A_LWL<223> A_LWL<222> A_LWL<221> A_LWL<220> A_LWL<219> A_LWL<218> A_LWL<217> A_LWL<216> A_LWL<215> A_LWL<214> A_LWL<213> A_LWL<212> A_LWL<211> A_LWL<210> A_LWL<209> A_LWL<208> A_LWL<207> A_LWL<206> A_LWL<205> A_LWL<204> A_LWL<203> A_LWL<202> A_LWL<201> A_LWL<200> A_LWL<199> A_LWL<198> A_LWL<197> A_LWL<196> A_LWL<195> A_LWL<194> A_LWL<193> A_LWL<192> A_LWL<191> A_LWL<190> A_LWL<189> A_LWL<188> A_LWL<187> A_LWL<186> A_LWL<185> A_LWL<184> A_LWL<183> A_LWL<182> A_LWL<181> A_LWL<180> A_LWL<179> A_LWL<178> A_LWL<177> A_LWL<176> A_LWL<175> A_LWL<174> A_LWL<173> A_LWL<172> A_LWL<171> A_LWL<170> A_LWL<169> A_LWL<168> A_LWL<167> A_LWL<166> A_LWL<165> A_LWL<164> A_LWL<163> A_LWL<162> A_LWL<161> A_LWL<160> A_LWL<159> A_LWL<158> A_LWL<157> A_LWL<156> A_LWL<155> A_LWL<154> A_LWL<153> A_LWL<152> A_LWL<151> A_LWL<150> A_LWL<149> A_LWL<148> A_LWL<147> A_LWL<146> A_LWL<145> A_LWL<144> A_LWL<143> A_LWL<142> A_LWL<141> A_LWL<140> A_LWL<139> A_LWL<138> A_LWL<137> A_LWL<136> A_LWL<135> A_LWL<134> A_LWL<133> A_LWL<132> A_LWL<131> A_LWL<130> A_LWL<129> A_LWL<128> A_LWL<127> A_LWL<126> A_LWL<125> A_LWL<124> A_LWL<123> A_LWL<122> A_LWL<121> A_LWL<120> A_LWL<119> A_LWL<118> A_LWL<117> A_LWL<116> A_LWL<115> A_LWL<114> A_LWL<113> A_LWL<112> A_LWL<111> A_LWL<110> A_LWL<109> A_LWL<108> A_LWL<107> A_LWL<106> A_LWL<105> A_LWL<104> A_LWL<103> A_LWL<102> A_LWL<101> A_LWL<100> A_LWL<99> A_LWL<98> A_LWL<97> A_LWL<96> A_LWL<95> A_LWL<94> A_LWL<93> A_LWL<92> A_LWL<91> A_LWL<90> A_LWL<89> A_LWL<88> A_LWL<87> A_LWL<86> A_LWL<85> A_LWL<84> A_LWL<83> A_LWL<82> A_LWL<81> A_LWL<80> A_LWL<79> A_LWL<78> A_LWL<77> A_LWL<76> A_LWL<75> A_LWL<74> A_LWL<73> A_LWL<72> A_LWL<71> A_LWL<70> A_LWL<69> A_LWL<68> A_LWL<67> A_LWL<66> A_LWL<65> A_LWL<64> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<255> A_RWL<254> A_RWL<253> A_RWL<252> A_RWL<251> A_RWL<250> A_RWL<249> A_RWL<248> A_RWL<247> A_RWL<246> A_RWL<245> A_RWL<244> A_RWL<243> A_RWL<242> A_RWL<241> A_RWL<240> A_RWL<239> A_RWL<238> A_RWL<237> A_RWL<236> A_RWL<235> A_RWL<234> A_RWL<233> A_RWL<232> A_RWL<231> A_RWL<230> A_RWL<229> A_RWL<228> A_RWL<227> A_RWL<226> A_RWL<225> A_RWL<224> A_RWL<223> A_RWL<222> A_RWL<221> A_RWL<220> A_RWL<219> A_RWL<218> A_RWL<217> A_RWL<216> A_RWL<215> A_RWL<214> A_RWL<213> A_RWL<212> A_RWL<211> A_RWL<210> A_RWL<209> A_RWL<208> A_RWL<207> A_RWL<206> A_RWL<205> A_RWL<204> A_RWL<203> A_RWL<202> A_RWL<201> A_RWL<200> A_RWL<199> A_RWL<198> A_RWL<197> A_RWL<196> A_RWL<195> A_RWL<194> A_RWL<193> A_RWL<192> A_RWL<191> A_RWL<190> A_RWL<189> A_RWL<188> A_RWL<187> A_RWL<186> A_RWL<185> A_RWL<184> A_RWL<183> A_RWL<182> A_RWL<181> A_RWL<180> A_RWL<179> A_RWL<178> A_RWL<177> A_RWL<176> A_RWL<175> A_RWL<174> A_RWL<173> A_RWL<172> A_RWL<171> A_RWL<170> A_RWL<169> A_RWL<168> A_RWL<167> A_RWL<166> A_RWL<165> A_RWL<164> A_RWL<163> A_RWL<162> A_RWL<161> A_RWL<160> A_RWL<159> A_RWL<158> A_RWL<157> A_RWL<156> A_RWL<155> A_RWL<154> A_RWL<153> A_RWL<152> A_RWL<151> A_RWL<150> A_RWL<149> A_RWL<148> A_RWL<147> A_RWL<146> A_RWL<145> A_RWL<144> A_RWL<143> A_RWL<142> A_RWL<141> A_RWL<140> A_RWL<139> A_RWL<138> A_RWL<137> A_RWL<136> A_RWL<135> A_RWL<134> A_RWL<133> A_RWL<132> A_RWL<131> A_RWL<130> A_RWL<129> A_RWL<128> A_RWL<127> A_RWL<126> A_RWL<125> A_RWL<124> A_RWL<123> A_RWL<122> A_RWL<121> A_RWL<120> A_RWL<119> A_RWL<118> A_RWL<117> A_RWL<116> A_RWL<115> A_RWL<114> A_RWL<113> A_RWL<112> A_RWL<111> A_RWL<110> A_RWL<109> A_RWL<108> A_RWL<107> A_RWL<106> A_RWL<105> A_RWL<104> A_RWL<103> A_RWL<102> A_RWL<101> A_RWL<100> A_RWL<99> A_RWL<98> A_RWL<97> A_RWL<96> A_RWL<95> A_RWL<94> A_RWL<93> A_RWL<92> A_RWL<91> A_RWL<90> A_RWL<89> A_RWL<88> A_RWL<87> A_RWL<86> A_RWL<85> A_RWL<84> A_RWL<83> A_RWL<82> A_RWL<81> A_RWL<80> A_RWL<79> A_RWL<78> A_RWL<77> A_RWL<76> A_RWL<75> A_RWL<74> A_RWL<73> A_RWL<72> A_RWL<71> A_RWL<70> A_RWL<69> A_RWL<68> A_RWL<67> A_RWL<66> A_RWL<65> A_RWL<64> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE VSS
+XRAM<16> A_BLC<29> A_BLC<28> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<29> A_BLT<28> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<255> A_LWL<254> A_LWL<253> A_LWL<252> A_LWL<251> A_LWL<250> A_LWL<249> A_LWL<248> A_LWL<247> A_LWL<246> A_LWL<245> A_LWL<244> A_LWL<243> A_LWL<242> A_LWL<241> A_LWL<240> A_RWL<255> A_RWL<254> A_RWL<253> A_RWL<252> A_RWL<251> A_RWL<250> A_RWL<249> A_RWL<248> A_RWL<247> A_RWL<246> A_RWL<245> A_RWL<244> A_RWL<243> A_RWL<242> A_RWL<241> A_RWL<240> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_SRAM
+XRAM<15> A_BLC<27> A_BLC<26> A_BLC<29> A_BLC<28> A_BLT<27> A_BLT<26> A_BLT<29> A_BLT<28> A_LWL<239> A_LWL<238> A_LWL<237> A_LWL<236> A_LWL<235> A_LWL<234> A_LWL<233> A_LWL<232> A_LWL<231> A_LWL<230> A_LWL<229> A_LWL<228> A_LWL<227> A_LWL<226> A_LWL<225> A_LWL<224> A_RWL<239> A_RWL<238> A_RWL<237> A_RWL<236> A_RWL<235> A_RWL<234> A_RWL<233> A_RWL<232> A_RWL<231> A_RWL<230> A_RWL<229> A_RWL<228> A_RWL<227> A_RWL<226> A_RWL<225> A_RWL<224> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_SRAM
+XRAM<14> A_BLC<25> A_BLC<24> A_BLC<27> A_BLC<26> A_BLT<25> A_BLT<24> A_BLT<27> A_BLT<26> A_LWL<223> A_LWL<222> A_LWL<221> A_LWL<220> A_LWL<219> A_LWL<218> A_LWL<217> A_LWL<216> A_LWL<215> A_LWL<214> A_LWL<213> A_LWL<212> A_LWL<211> A_LWL<210> A_LWL<209> A_LWL<208> A_RWL<223> A_RWL<222> A_RWL<221> A_RWL<220> A_RWL<219> A_RWL<218> A_RWL<217> A_RWL<216> A_RWL<215> A_RWL<214> A_RWL<213> A_RWL<212> A_RWL<211> A_RWL<210> A_RWL<209> A_RWL<208> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_SRAM
+XRAM<13> A_BLC<23> A_BLC<22> A_BLC<25> A_BLC<24> A_BLT<23> A_BLT<22> A_BLT<25> A_BLT<24> A_LWL<207> A_LWL<206> A_LWL<205> A_LWL<204> A_LWL<203> A_LWL<202> A_LWL<201> A_LWL<200> A_LWL<199> A_LWL<198> A_LWL<197> A_LWL<196> A_LWL<195> A_LWL<194> A_LWL<193> A_LWL<192> A_RWL<207> A_RWL<206> A_RWL<205> A_RWL<204> A_RWL<203> A_RWL<202> A_RWL<201> A_RWL<200> A_RWL<199> A_RWL<198> A_RWL<197> A_RWL<196> A_RWL<195> A_RWL<194> A_RWL<193> A_RWL<192> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_SRAM
+XRAM<12> A_BLC<21> A_BLC<20> A_BLC<23> A_BLC<22> A_BLT<21> A_BLT<20> A_BLT<23> A_BLT<22> A_LWL<191> A_LWL<190> A_LWL<189> A_LWL<188> A_LWL<187> A_LWL<186> A_LWL<185> A_LWL<184> A_LWL<183> A_LWL<182> A_LWL<181> A_LWL<180> A_LWL<179> A_LWL<178> A_LWL<177> A_LWL<176> A_RWL<191> A_RWL<190> A_RWL<189> A_RWL<188> A_RWL<187> A_RWL<186> A_RWL<185> A_RWL<184> A_RWL<183> A_RWL<182> A_RWL<181> A_RWL<180> A_RWL<179> A_RWL<178> A_RWL<177> A_RWL<176> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_SRAM
+XRAM<11> A_BLC<19> A_BLC<18> A_BLC<21> A_BLC<20> A_BLT<19> A_BLT<18> A_BLT<21> A_BLT<20> A_LWL<175> A_LWL<174> A_LWL<173> A_LWL<172> A_LWL<171> A_LWL<170> A_LWL<169> A_LWL<168> A_LWL<167> A_LWL<166> A_LWL<165> A_LWL<164> A_LWL<163> A_LWL<162> A_LWL<161> A_LWL<160> A_RWL<175> A_RWL<174> A_RWL<173> A_RWL<172> A_RWL<171> A_RWL<170> A_RWL<169> A_RWL<168> A_RWL<167> A_RWL<166> A_RWL<165> A_RWL<164> A_RWL<163> A_RWL<162> A_RWL<161> A_RWL<160> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_SRAM
+XRAM<10> A_BLC<17> A_BLC<16> A_BLC<19> A_BLC<18> A_BLT<17> A_BLT<16> A_BLT<19> A_BLT<18> A_LWL<159> A_LWL<158> A_LWL<157> A_LWL<156> A_LWL<155> A_LWL<154> A_LWL<153> A_LWL<152> A_LWL<151> A_LWL<150> A_LWL<149> A_LWL<148> A_LWL<147> A_LWL<146> A_LWL<145> A_LWL<144> A_RWL<159> A_RWL<158> A_RWL<157> A_RWL<156> A_RWL<155> A_RWL<154> A_RWL<153> A_RWL<152> A_RWL<151> A_RWL<150> A_RWL<149> A_RWL<148> A_RWL<147> A_RWL<146> A_RWL<145> A_RWL<144> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_SRAM
+XRAM<9> A_BLC<15> A_BLC<14> A_BLC<17> A_BLC<16> A_BLT<15> A_BLT<14> A_BLT<17> A_BLT<16> A_LWL<143> A_LWL<142> A_LWL<141> A_LWL<140> A_LWL<139> A_LWL<138> A_LWL<137> A_LWL<136> A_LWL<135> A_LWL<134> A_LWL<133> A_LWL<132> A_LWL<131> A_LWL<130> A_LWL<129> A_LWL<128> A_RWL<143> A_RWL<142> A_RWL<141> A_RWL<140> A_RWL<139> A_RWL<138> A_RWL<137> A_RWL<136> A_RWL<135> A_RWL<134> A_RWL<133> A_RWL<132> A_RWL<131> A_RWL<130> A_RWL<129> A_RWL<128> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_SRAM
+XRAM<8> A_BLC<13> A_BLC<12> A_BLC<15> A_BLC<14> A_BLT<13> A_BLT<12> A_BLT<15> A_BLT<14> A_LWL<127> A_LWL<126> A_LWL<125> A_LWL<124> A_LWL<123> A_LWL<122> A_LWL<121> A_LWL<120> A_LWL<119> A_LWL<118> A_LWL<117> A_LWL<116> A_LWL<115> A_LWL<114> A_LWL<113> A_LWL<112> A_RWL<127> A_RWL<126> A_RWL<125> A_RWL<124> A_RWL<123> A_RWL<122> A_RWL<121> A_RWL<120> A_RWL<119> A_RWL<118> A_RWL<117> A_RWL<116> A_RWL<115> A_RWL<114> A_RWL<113> A_RWL<112> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_SRAM
+XRAM<7> A_BLC<11> A_BLC<10> A_BLC<13> A_BLC<12> A_BLT<11> A_BLT<10> A_BLT<13> A_BLT<12> A_LWL<111> A_LWL<110> A_LWL<109> A_LWL<108> A_LWL<107> A_LWL<106> A_LWL<105> A_LWL<104> A_LWL<103> A_LWL<102> A_LWL<101> A_LWL<100> A_LWL<99> A_LWL<98> A_LWL<97> A_LWL<96> A_RWL<111> A_RWL<110> A_RWL<109> A_RWL<108> A_RWL<107> A_RWL<106> A_RWL<105> A_RWL<104> A_RWL<103> A_RWL<102> A_RWL<101> A_RWL<100> A_RWL<99> A_RWL<98> A_RWL<97> A_RWL<96> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_SRAM
+XRAM<6> A_BLC<9> A_BLC<8> A_BLC<11> A_BLC<10> A_BLT<9> A_BLT<8> A_BLT<11> A_BLT<10> A_LWL<95> A_LWL<94> A_LWL<93> A_LWL<92> A_LWL<91> A_LWL<90> A_LWL<89> A_LWL<88> A_LWL<87> A_LWL<86> A_LWL<85> A_LWL<84> A_LWL<83> A_LWL<82> A_LWL<81> A_LWL<80> A_RWL<95> A_RWL<94> A_RWL<93> A_RWL<92> A_RWL<91> A_RWL<90> A_RWL<89> A_RWL<88> A_RWL<87> A_RWL<86> A_RWL<85> A_RWL<84> A_RWL<83> A_RWL<82> A_RWL<81> A_RWL<80> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_SRAM
+XRAM<5> A_BLC<7> A_BLC<6> A_BLC<9> A_BLC<8> A_BLT<7> A_BLT<6> A_BLT<9> A_BLT<8> A_LWL<79> A_LWL<78> A_LWL<77> A_LWL<76> A_LWL<75> A_LWL<74> A_LWL<73> A_LWL<72> A_LWL<71> A_LWL<70> A_LWL<69> A_LWL<68> A_LWL<67> A_LWL<66> A_LWL<65> A_LWL<64> A_RWL<79> A_RWL<78> A_RWL<77> A_RWL<76> A_RWL<75> A_RWL<74> A_RWL<73> A_RWL<72> A_RWL<71> A_RWL<70> A_RWL<69> A_RWL<68> A_RWL<67> A_RWL<66> A_RWL<65> A_RWL<64> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_SRAM
+XRAM<4> A_BLC<5> A_BLC<4> A_BLC<7> A_BLC<6> A_BLT<5> A_BLT<4> A_BLT<7> A_BLT<6> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_SRAM
+XRAM<3> A_BLC<3> A_BLC<2> A_BLC<5> A_BLC<4> A_BLT<3> A_BLT<2> A_BLT<5> A_BLT<4> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_SRAM
+XRAM<2> A_BLC<1> A_BLC<0> A_BLC<3> A_BLC<2> A_BLT<1> A_BLT<0> A_BLT<3> A_BLT<2> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_SRAM
+XRAM<1> A_BLC_BOT<1> A_BLC_BOT<0> A_BLC<1> A_BLC<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT<1> A_BLT<0> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_SRAM
+XEDGE<1> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_TOP<1> A_BLT_TOP<0> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_TB
+XEDGE<0> A_BLC_BOT<1> A_BLC_BOT<0> A_BLT_BOT<1> A_BLT_BOT<0> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_TB
+.ENDS
+
+
+
+
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_MATRIX_pcell_1 A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_WL<255> A_WL<254> A_WL<253> A_WL<252> A_WL<251> A_WL<250> A_WL<249> A_WL<248> A_WL<247> A_WL<246> A_WL<245> A_WL<244> A_WL<243> A_WL<242> A_WL<241> A_WL<240> A_WL<239> A_WL<238> A_WL<237> A_WL<236> A_WL<235> A_WL<234> A_WL<233> A_WL<232> A_WL<231> A_WL<230> A_WL<229> A_WL<228> A_WL<227> A_WL<226> A_WL<225> A_WL<224> A_WL<223> A_WL<222> A_WL<221> A_WL<220> A_WL<219> A_WL<218> A_WL<217> A_WL<216> A_WL<215> A_WL<214> A_WL<213> A_WL<212> A_WL<211> A_WL<210> A_WL<209> A_WL<208> A_WL<207> A_WL<206> A_WL<205> A_WL<204> A_WL<203> A_WL<202> A_WL<201> A_WL<200> A_WL<199> A_WL<198> A_WL<197> A_WL<196> A_WL<195> A_WL<194> A_WL<193> A_WL<192> A_WL<191> A_WL<190> A_WL<189> A_WL<188> A_WL<187> A_WL<186> A_WL<185> A_WL<184> A_WL<183> A_WL<182> A_WL<181> A_WL<180> A_WL<179> A_WL<178> A_WL<177> A_WL<176> A_WL<175> A_WL<174> A_WL<173> A_WL<172> A_WL<171> A_WL<170> A_WL<169> A_WL<168> A_WL<167> A_WL<166> A_WL<165> A_WL<164> A_WL<163> A_WL<162> A_WL<161> A_WL<160> A_WL<159> A_WL<158> A_WL<157> A_WL<156> A_WL<155> A_WL<154> A_WL<153> A_WL<152> A_WL<151> A_WL<150> A_WL<149> A_WL<148> A_WL<147> A_WL<146> A_WL<145> A_WL<144> A_WL<143> A_WL<142> A_WL<141> A_WL<140> A_WL<139> A_WL<138> A_WL<137> A_WL<136> A_WL<135> A_WL<134> A_WL<133> A_WL<132> A_WL<131> A_WL<130> A_WL<129> A_WL<128> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS
+XCORNER<3> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_CORNER
+XCORNER<2> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_CORNER
+XCORNER<1> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_CORNER
+XCORNER<0> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_CORNER
+XRAMEDGE_L<15> A_WL<255> A_WL<254> A_WL<253> A_WL<252> A_WL<251> A_WL<250> A_WL<249> A_WL<248> A_WL<247> A_WL<246> A_WL<245> A_WL<244> A_WL<243> A_WL<242> A_WL<241> A_WL<240> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<14> A_WL<239> A_WL<238> A_WL<237> A_WL<236> A_WL<235> A_WL<234> A_WL<233> A_WL<232> A_WL<231> A_WL<230> A_WL<229> A_WL<228> A_WL<227> A_WL<226> A_WL<225> A_WL<224> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<13> A_WL<223> A_WL<222> A_WL<221> A_WL<220> A_WL<219> A_WL<218> A_WL<217> A_WL<216> A_WL<215> A_WL<214> A_WL<213> A_WL<212> A_WL<211> A_WL<210> A_WL<209> A_WL<208> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<12> A_WL<207> A_WL<206> A_WL<205> A_WL<204> A_WL<203> A_WL<202> A_WL<201> A_WL<200> A_WL<199> A_WL<198> A_WL<197> A_WL<196> A_WL<195> A_WL<194> A_WL<193> A_WL<192> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<11> A_WL<191> A_WL<190> A_WL<189> A_WL<188> A_WL<187> A_WL<186> A_WL<185> A_WL<184> A_WL<183> A_WL<182> A_WL<181> A_WL<180> A_WL<179> A_WL<178> A_WL<177> A_WL<176> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<10> A_WL<175> A_WL<174> A_WL<173> A_WL<172> A_WL<171> A_WL<170> A_WL<169> A_WL<168> A_WL<167> A_WL<166> A_WL<165> A_WL<164> A_WL<163> A_WL<162> A_WL<161> A_WL<160> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<9> A_WL<159> A_WL<158> A_WL<157> A_WL<156> A_WL<155> A_WL<154> A_WL<153> A_WL<152> A_WL<151> A_WL<150> A_WL<149> A_WL<148> A_WL<147> A_WL<146> A_WL<145> A_WL<144> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<8> A_WL<143> A_WL<142> A_WL<141> A_WL<140> A_WL<139> A_WL<138> A_WL<137> A_WL<136> A_WL<135> A_WL<134> A_WL<133> A_WL<132> A_WL<131> A_WL<130> A_WL<129> A_WL<128> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<7> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<6> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<5> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<4> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<3> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<2> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<1> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<0> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<15> A_IWL<4095> A_IWL<4094> A_IWL<4093> A_IWL<4092> A_IWL<4091> A_IWL<4090> A_IWL<4089> A_IWL<4088> A_IWL<4087> A_IWL<4086> A_IWL<4085> A_IWL<4084> A_IWL<4083> A_IWL<4082> A_IWL<4081> A_IWL<4080> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<14> A_IWL<4079> A_IWL<4078> A_IWL<4077> A_IWL<4076> A_IWL<4075> A_IWL<4074> A_IWL<4073> A_IWL<4072> A_IWL<4071> A_IWL<4070> A_IWL<4069> A_IWL<4068> A_IWL<4067> A_IWL<4066> A_IWL<4065> A_IWL<4064> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<13> A_IWL<4063> A_IWL<4062> A_IWL<4061> A_IWL<4060> A_IWL<4059> A_IWL<4058> A_IWL<4057> A_IWL<4056> A_IWL<4055> A_IWL<4054> A_IWL<4053> A_IWL<4052> A_IWL<4051> A_IWL<4050> A_IWL<4049> A_IWL<4048> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<12> A_IWL<4047> A_IWL<4046> A_IWL<4045> A_IWL<4044> A_IWL<4043> A_IWL<4042> A_IWL<4041> A_IWL<4040> A_IWL<4039> A_IWL<4038> A_IWL<4037> A_IWL<4036> A_IWL<4035> A_IWL<4034> A_IWL<4033> A_IWL<4032> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<11> A_IWL<4031> A_IWL<4030> A_IWL<4029> A_IWL<4028> A_IWL<4027> A_IWL<4026> A_IWL<4025> A_IWL<4024> A_IWL<4023> A_IWL<4022> A_IWL<4021> A_IWL<4020> A_IWL<4019> A_IWL<4018> A_IWL<4017> A_IWL<4016> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<10> A_IWL<4015> A_IWL<4014> A_IWL<4013> A_IWL<4012> A_IWL<4011> A_IWL<4010> A_IWL<4009> A_IWL<4008> A_IWL<4007> A_IWL<4006> A_IWL<4005> A_IWL<4004> A_IWL<4003> A_IWL<4002> A_IWL<4001> A_IWL<4000> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<9> A_IWL<3999> A_IWL<3998> A_IWL<3997> A_IWL<3996> A_IWL<3995> A_IWL<3994> A_IWL<3993> A_IWL<3992> A_IWL<3991> A_IWL<3990> A_IWL<3989> A_IWL<3988> A_IWL<3987> A_IWL<3986> A_IWL<3985> A_IWL<3984> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<8> A_IWL<3983> A_IWL<3982> A_IWL<3981> A_IWL<3980> A_IWL<3979> A_IWL<3978> A_IWL<3977> A_IWL<3976> A_IWL<3975> A_IWL<3974> A_IWL<3973> A_IWL<3972> A_IWL<3971> A_IWL<3970> A_IWL<3969> A_IWL<3968> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<7> A_IWL<3967> A_IWL<3966> A_IWL<3965> A_IWL<3964> A_IWL<3963> A_IWL<3962> A_IWL<3961> A_IWL<3960> A_IWL<3959> A_IWL<3958> A_IWL<3957> A_IWL<3956> A_IWL<3955> A_IWL<3954> A_IWL<3953> A_IWL<3952> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<6> A_IWL<3951> A_IWL<3950> A_IWL<3949> A_IWL<3948> A_IWL<3947> A_IWL<3946> A_IWL<3945> A_IWL<3944> A_IWL<3943> A_IWL<3942> A_IWL<3941> A_IWL<3940> A_IWL<3939> A_IWL<3938> A_IWL<3937> A_IWL<3936> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<5> A_IWL<3935> A_IWL<3934> A_IWL<3933> A_IWL<3932> A_IWL<3931> A_IWL<3930> A_IWL<3929> A_IWL<3928> A_IWL<3927> A_IWL<3926> A_IWL<3925> A_IWL<3924> A_IWL<3923> A_IWL<3922> A_IWL<3921> A_IWL<3920> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<4> A_IWL<3919> A_IWL<3918> A_IWL<3917> A_IWL<3916> A_IWL<3915> A_IWL<3914> A_IWL<3913> A_IWL<3912> A_IWL<3911> A_IWL<3910> A_IWL<3909> A_IWL<3908> A_IWL<3907> A_IWL<3906> A_IWL<3905> A_IWL<3904> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<3> A_IWL<3903> A_IWL<3902> A_IWL<3901> A_IWL<3900> A_IWL<3899> A_IWL<3898> A_IWL<3897> A_IWL<3896> A_IWL<3895> A_IWL<3894> A_IWL<3893> A_IWL<3892> A_IWL<3891> A_IWL<3890> A_IWL<3889> A_IWL<3888> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<2> A_IWL<3887> A_IWL<3886> A_IWL<3885> A_IWL<3884> A_IWL<3883> A_IWL<3882> A_IWL<3881> A_IWL<3880> A_IWL<3879> A_IWL<3878> A_IWL<3877> A_IWL<3876> A_IWL<3875> A_IWL<3874> A_IWL<3873> A_IWL<3872> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<1> A_IWL<3871> A_IWL<3870> A_IWL<3869> A_IWL<3868> A_IWL<3867> A_IWL<3866> A_IWL<3865> A_IWL<3864> A_IWL<3863> A_IWL<3862> A_IWL<3861> A_IWL<3860> A_IWL<3859> A_IWL<3858> A_IWL<3857> A_IWL<3856> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<0> A_IWL<3855> A_IWL<3854> A_IWL<3853> A_IWL<3852> A_IWL<3851> A_IWL<3850> A_IWL<3849> A_IWL<3848> A_IWL<3847> A_IWL<3846> A_IWL<3845> A_IWL<3844> A_IWL<3843> A_IWL<3842> A_IWL<3841> A_IWL<3840> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_BITKIT_16x2_EDGE_LR
+XCOL<15> A_BLC<31> A_BLC<30> A_BLC_TOP<31> A_BLC_TOP<30> A_BLT<31> A_BLT<30> A_BLT_TOP<31> A_BLT_TOP<30> A_IWL<3839> A_IWL<3838> A_IWL<3837> A_IWL<3836> A_IWL<3835> A_IWL<3834> A_IWL<3833> A_IWL<3832> A_IWL<3831> A_IWL<3830> A_IWL<3829> A_IWL<3828> A_IWL<3827> A_IWL<3826> A_IWL<3825> A_IWL<3824> A_IWL<3823> A_IWL<3822> A_IWL<3821> A_IWL<3820> A_IWL<3819> A_IWL<3818> A_IWL<3817> A_IWL<3816> A_IWL<3815> A_IWL<3814> A_IWL<3813> A_IWL<3812> A_IWL<3811> A_IWL<3810> A_IWL<3809> A_IWL<3808> A_IWL<3807> A_IWL<3806> A_IWL<3805> A_IWL<3804> A_IWL<3803> A_IWL<3802> A_IWL<3801> A_IWL<3800> A_IWL<3799> A_IWL<3798> A_IWL<3797> A_IWL<3796> A_IWL<3795> A_IWL<3794> A_IWL<3793> A_IWL<3792> A_IWL<3791> A_IWL<3790> A_IWL<3789> A_IWL<3788> A_IWL<3787> A_IWL<3786> A_IWL<3785> A_IWL<3784> A_IWL<3783> A_IWL<3782> A_IWL<3781> A_IWL<3780> A_IWL<3779> A_IWL<3778> A_IWL<3777> A_IWL<3776> A_IWL<3775> A_IWL<3774> A_IWL<3773> A_IWL<3772> A_IWL<3771> A_IWL<3770> A_IWL<3769> A_IWL<3768> A_IWL<3767> A_IWL<3766> A_IWL<3765> A_IWL<3764> A_IWL<3763> A_IWL<3762> A_IWL<3761> A_IWL<3760> A_IWL<3759> A_IWL<3758> A_IWL<3757> A_IWL<3756> A_IWL<3755> A_IWL<3754> A_IWL<3753> A_IWL<3752> A_IWL<3751> A_IWL<3750> A_IWL<3749> A_IWL<3748> A_IWL<3747> A_IWL<3746> A_IWL<3745> A_IWL<3744> A_IWL<3743> A_IWL<3742> A_IWL<3741> A_IWL<3740> A_IWL<3739> A_IWL<3738> A_IWL<3737> A_IWL<3736> A_IWL<3735> A_IWL<3734> A_IWL<3733> A_IWL<3732> A_IWL<3731> A_IWL<3730> A_IWL<3729> A_IWL<3728> A_IWL<3727> A_IWL<3726> A_IWL<3725> A_IWL<3724> A_IWL<3723> A_IWL<3722> A_IWL<3721> A_IWL<3720> A_IWL<3719> A_IWL<3718> A_IWL<3717> A_IWL<3716> A_IWL<3715> A_IWL<3714> A_IWL<3713> A_IWL<3712> A_IWL<3711> A_IWL<3710> A_IWL<3709> A_IWL<3708> A_IWL<3707> A_IWL<3706> A_IWL<3705> A_IWL<3704> A_IWL<3703> A_IWL<3702> A_IWL<3701> A_IWL<3700> A_IWL<3699> A_IWL<3698> A_IWL<3697> A_IWL<3696> A_IWL<3695> A_IWL<3694> A_IWL<3693> A_IWL<3692> A_IWL<3691> A_IWL<3690> A_IWL<3689> A_IWL<3688> A_IWL<3687> A_IWL<3686> A_IWL<3685> A_IWL<3684> A_IWL<3683> A_IWL<3682> A_IWL<3681> A_IWL<3680> A_IWL<3679> A_IWL<3678> A_IWL<3677> A_IWL<3676> A_IWL<3675> A_IWL<3674> A_IWL<3673> A_IWL<3672> A_IWL<3671> A_IWL<3670> A_IWL<3669> A_IWL<3668> A_IWL<3667> A_IWL<3666> A_IWL<3665> A_IWL<3664> A_IWL<3663> A_IWL<3662> A_IWL<3661> A_IWL<3660> A_IWL<3659> A_IWL<3658> A_IWL<3657> A_IWL<3656> A_IWL<3655> A_IWL<3654> A_IWL<3653> A_IWL<3652> A_IWL<3651> A_IWL<3650> A_IWL<3649> A_IWL<3648> A_IWL<3647> A_IWL<3646> A_IWL<3645> A_IWL<3644> A_IWL<3643> A_IWL<3642> A_IWL<3641> A_IWL<3640> A_IWL<3639> A_IWL<3638> A_IWL<3637> A_IWL<3636> A_IWL<3635> A_IWL<3634> A_IWL<3633> A_IWL<3632> A_IWL<3631> A_IWL<3630> A_IWL<3629> A_IWL<3628> A_IWL<3627> A_IWL<3626> A_IWL<3625> A_IWL<3624> A_IWL<3623> A_IWL<3622> A_IWL<3621> A_IWL<3620> A_IWL<3619> A_IWL<3618> A_IWL<3617> A_IWL<3616> A_IWL<3615> A_IWL<3614> A_IWL<3613> A_IWL<3612> A_IWL<3611> A_IWL<3610> A_IWL<3609> A_IWL<3608> A_IWL<3607> A_IWL<3606> A_IWL<3605> A_IWL<3604> A_IWL<3603> A_IWL<3602> A_IWL<3601> A_IWL<3600> A_IWL<3599> A_IWL<3598> A_IWL<3597> A_IWL<3596> A_IWL<3595> A_IWL<3594> A_IWL<3593> A_IWL<3592> A_IWL<3591> A_IWL<3590> A_IWL<3589> A_IWL<3588> A_IWL<3587> A_IWL<3586> A_IWL<3585> A_IWL<3584> A_IWL<4095> A_IWL<4094> A_IWL<4093> A_IWL<4092> A_IWL<4091> A_IWL<4090> A_IWL<4089> A_IWL<4088> A_IWL<4087> A_IWL<4086> A_IWL<4085> A_IWL<4084> A_IWL<4083> A_IWL<4082> A_IWL<4081> A_IWL<4080> A_IWL<4079> A_IWL<4078> A_IWL<4077> A_IWL<4076> A_IWL<4075> A_IWL<4074> A_IWL<4073> A_IWL<4072> A_IWL<4071> A_IWL<4070> A_IWL<4069> A_IWL<4068> A_IWL<4067> A_IWL<4066> A_IWL<4065> A_IWL<4064> A_IWL<4063> A_IWL<4062> A_IWL<4061> A_IWL<4060> A_IWL<4059> A_IWL<4058> A_IWL<4057> A_IWL<4056> A_IWL<4055> A_IWL<4054> A_IWL<4053> A_IWL<4052> A_IWL<4051> A_IWL<4050> A_IWL<4049> A_IWL<4048> A_IWL<4047> A_IWL<4046> A_IWL<4045> A_IWL<4044> A_IWL<4043> A_IWL<4042> A_IWL<4041> A_IWL<4040> A_IWL<4039> A_IWL<4038> A_IWL<4037> A_IWL<4036> A_IWL<4035> A_IWL<4034> A_IWL<4033> A_IWL<4032> A_IWL<4031> A_IWL<4030> A_IWL<4029> A_IWL<4028> A_IWL<4027> A_IWL<4026> A_IWL<4025> A_IWL<4024> A_IWL<4023> A_IWL<4022> A_IWL<4021> A_IWL<4020> A_IWL<4019> A_IWL<4018> A_IWL<4017> A_IWL<4016> A_IWL<4015> A_IWL<4014> A_IWL<4013> A_IWL<4012> A_IWL<4011> A_IWL<4010> A_IWL<4009> A_IWL<4008> A_IWL<4007> A_IWL<4006> A_IWL<4005> A_IWL<4004> A_IWL<4003> A_IWL<4002> A_IWL<4001> A_IWL<4000> A_IWL<3999> A_IWL<3998> A_IWL<3997> A_IWL<3996> A_IWL<3995> A_IWL<3994> A_IWL<3993> A_IWL<3992> A_IWL<3991> A_IWL<3990> A_IWL<3989> A_IWL<3988> A_IWL<3987> A_IWL<3986> A_IWL<3985> A_IWL<3984> A_IWL<3983> A_IWL<3982> A_IWL<3981> A_IWL<3980> A_IWL<3979> A_IWL<3978> A_IWL<3977> A_IWL<3976> A_IWL<3975> A_IWL<3974> A_IWL<3973> A_IWL<3972> A_IWL<3971> A_IWL<3970> A_IWL<3969> A_IWL<3968> A_IWL<3967> A_IWL<3966> A_IWL<3965> A_IWL<3964> A_IWL<3963> A_IWL<3962> A_IWL<3961> A_IWL<3960> A_IWL<3959> A_IWL<3958> A_IWL<3957> A_IWL<3956> A_IWL<3955> A_IWL<3954> A_IWL<3953> A_IWL<3952> A_IWL<3951> A_IWL<3950> A_IWL<3949> A_IWL<3948> A_IWL<3947> A_IWL<3946> A_IWL<3945> A_IWL<3944> A_IWL<3943> A_IWL<3942> A_IWL<3941> A_IWL<3940> A_IWL<3939> A_IWL<3938> A_IWL<3937> A_IWL<3936> A_IWL<3935> A_IWL<3934> A_IWL<3933> A_IWL<3932> A_IWL<3931> A_IWL<3930> A_IWL<3929> A_IWL<3928> A_IWL<3927> A_IWL<3926> A_IWL<3925> A_IWL<3924> A_IWL<3923> A_IWL<3922> A_IWL<3921> A_IWL<3920> A_IWL<3919> A_IWL<3918> A_IWL<3917> A_IWL<3916> A_IWL<3915> A_IWL<3914> A_IWL<3913> A_IWL<3912> A_IWL<3911> A_IWL<3910> A_IWL<3909> A_IWL<3908> A_IWL<3907> A_IWL<3906> A_IWL<3905> A_IWL<3904> A_IWL<3903> A_IWL<3902> A_IWL<3901> A_IWL<3900> A_IWL<3899> A_IWL<3898> A_IWL<3897> A_IWL<3896> A_IWL<3895> A_IWL<3894> A_IWL<3893> A_IWL<3892> A_IWL<3891> A_IWL<3890> A_IWL<3889> A_IWL<3888> A_IWL<3887> A_IWL<3886> A_IWL<3885> A_IWL<3884> A_IWL<3883> A_IWL<3882> A_IWL<3881> A_IWL<3880> A_IWL<3879> A_IWL<3878> A_IWL<3877> A_IWL<3876> A_IWL<3875> A_IWL<3874> A_IWL<3873> A_IWL<3872> A_IWL<3871> A_IWL<3870> A_IWL<3869> A_IWL<3868> A_IWL<3867> A_IWL<3866> A_IWL<3865> A_IWL<3864> A_IWL<3863> A_IWL<3862> A_IWL<3861> A_IWL<3860> A_IWL<3859> A_IWL<3858> A_IWL<3857> A_IWL<3856> A_IWL<3855> A_IWL<3854> A_IWL<3853> A_IWL<3852> A_IWL<3851> A_IWL<3850> A_IWL<3849> A_IWL<3848> A_IWL<3847> A_IWL<3846> A_IWL<3845> A_IWL<3844> A_IWL<3843> A_IWL<3842> A_IWL<3841> A_IWL<3840> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_COLUMN_pcell_0
+XCOL<14> A_BLC<29> A_BLC<28> A_BLC_TOP<29> A_BLC_TOP<28> A_BLT<29> A_BLT<28> A_BLT_TOP<29> A_BLT_TOP<28> A_IWL<3583> A_IWL<3582> A_IWL<3581> A_IWL<3580> A_IWL<3579> A_IWL<3578> A_IWL<3577> A_IWL<3576> A_IWL<3575> A_IWL<3574> A_IWL<3573> A_IWL<3572> A_IWL<3571> A_IWL<3570> A_IWL<3569> A_IWL<3568> A_IWL<3567> A_IWL<3566> A_IWL<3565> A_IWL<3564> A_IWL<3563> A_IWL<3562> A_IWL<3561> A_IWL<3560> A_IWL<3559> A_IWL<3558> A_IWL<3557> A_IWL<3556> A_IWL<3555> A_IWL<3554> A_IWL<3553> A_IWL<3552> A_IWL<3551> A_IWL<3550> A_IWL<3549> A_IWL<3548> A_IWL<3547> A_IWL<3546> A_IWL<3545> A_IWL<3544> A_IWL<3543> A_IWL<3542> A_IWL<3541> A_IWL<3540> A_IWL<3539> A_IWL<3538> A_IWL<3537> A_IWL<3536> A_IWL<3535> A_IWL<3534> A_IWL<3533> A_IWL<3532> A_IWL<3531> A_IWL<3530> A_IWL<3529> A_IWL<3528> A_IWL<3527> A_IWL<3526> A_IWL<3525> A_IWL<3524> A_IWL<3523> A_IWL<3522> A_IWL<3521> A_IWL<3520> A_IWL<3519> A_IWL<3518> A_IWL<3517> A_IWL<3516> A_IWL<3515> A_IWL<3514> A_IWL<3513> A_IWL<3512> A_IWL<3511> A_IWL<3510> A_IWL<3509> A_IWL<3508> A_IWL<3507> A_IWL<3506> A_IWL<3505> A_IWL<3504> A_IWL<3503> A_IWL<3502> A_IWL<3501> A_IWL<3500> A_IWL<3499> A_IWL<3498> A_IWL<3497> A_IWL<3496> A_IWL<3495> A_IWL<3494> A_IWL<3493> A_IWL<3492> A_IWL<3491> A_IWL<3490> A_IWL<3489> A_IWL<3488> A_IWL<3487> A_IWL<3486> A_IWL<3485> A_IWL<3484> A_IWL<3483> A_IWL<3482> A_IWL<3481> A_IWL<3480> A_IWL<3479> A_IWL<3478> A_IWL<3477> A_IWL<3476> A_IWL<3475> A_IWL<3474> A_IWL<3473> A_IWL<3472> A_IWL<3471> A_IWL<3470> A_IWL<3469> A_IWL<3468> A_IWL<3467> A_IWL<3466> A_IWL<3465> A_IWL<3464> A_IWL<3463> A_IWL<3462> A_IWL<3461> A_IWL<3460> A_IWL<3459> A_IWL<3458> A_IWL<3457> A_IWL<3456> A_IWL<3455> A_IWL<3454> A_IWL<3453> A_IWL<3452> A_IWL<3451> A_IWL<3450> A_IWL<3449> A_IWL<3448> A_IWL<3447> A_IWL<3446> A_IWL<3445> A_IWL<3444> A_IWL<3443> A_IWL<3442> A_IWL<3441> A_IWL<3440> A_IWL<3439> A_IWL<3438> A_IWL<3437> A_IWL<3436> A_IWL<3435> A_IWL<3434> A_IWL<3433> A_IWL<3432> A_IWL<3431> A_IWL<3430> A_IWL<3429> A_IWL<3428> A_IWL<3427> A_IWL<3426> A_IWL<3425> A_IWL<3424> A_IWL<3423> A_IWL<3422> A_IWL<3421> A_IWL<3420> A_IWL<3419> A_IWL<3418> A_IWL<3417> A_IWL<3416> A_IWL<3415> A_IWL<3414> A_IWL<3413> A_IWL<3412> A_IWL<3411> A_IWL<3410> A_IWL<3409> A_IWL<3408> A_IWL<3407> A_IWL<3406> A_IWL<3405> A_IWL<3404> A_IWL<3403> A_IWL<3402> A_IWL<3401> A_IWL<3400> A_IWL<3399> A_IWL<3398> A_IWL<3397> A_IWL<3396> A_IWL<3395> A_IWL<3394> A_IWL<3393> A_IWL<3392> A_IWL<3391> A_IWL<3390> A_IWL<3389> A_IWL<3388> A_IWL<3387> A_IWL<3386> A_IWL<3385> A_IWL<3384> A_IWL<3383> A_IWL<3382> A_IWL<3381> A_IWL<3380> A_IWL<3379> A_IWL<3378> A_IWL<3377> A_IWL<3376> A_IWL<3375> A_IWL<3374> A_IWL<3373> A_IWL<3372> A_IWL<3371> A_IWL<3370> A_IWL<3369> A_IWL<3368> A_IWL<3367> A_IWL<3366> A_IWL<3365> A_IWL<3364> A_IWL<3363> A_IWL<3362> A_IWL<3361> A_IWL<3360> A_IWL<3359> A_IWL<3358> A_IWL<3357> A_IWL<3356> A_IWL<3355> A_IWL<3354> A_IWL<3353> A_IWL<3352> A_IWL<3351> A_IWL<3350> A_IWL<3349> A_IWL<3348> A_IWL<3347> A_IWL<3346> A_IWL<3345> A_IWL<3344> A_IWL<3343> A_IWL<3342> A_IWL<3341> A_IWL<3340> A_IWL<3339> A_IWL<3338> A_IWL<3337> A_IWL<3336> A_IWL<3335> A_IWL<3334> A_IWL<3333> A_IWL<3332> A_IWL<3331> A_IWL<3330> A_IWL<3329> A_IWL<3328> A_IWL<3839> A_IWL<3838> A_IWL<3837> A_IWL<3836> A_IWL<3835> A_IWL<3834> A_IWL<3833> A_IWL<3832> A_IWL<3831> A_IWL<3830> A_IWL<3829> A_IWL<3828> A_IWL<3827> A_IWL<3826> A_IWL<3825> A_IWL<3824> A_IWL<3823> A_IWL<3822> A_IWL<3821> A_IWL<3820> A_IWL<3819> A_IWL<3818> A_IWL<3817> A_IWL<3816> A_IWL<3815> A_IWL<3814> A_IWL<3813> A_IWL<3812> A_IWL<3811> A_IWL<3810> A_IWL<3809> A_IWL<3808> A_IWL<3807> A_IWL<3806> A_IWL<3805> A_IWL<3804> A_IWL<3803> A_IWL<3802> A_IWL<3801> A_IWL<3800> A_IWL<3799> A_IWL<3798> A_IWL<3797> A_IWL<3796> A_IWL<3795> A_IWL<3794> A_IWL<3793> A_IWL<3792> A_IWL<3791> A_IWL<3790> A_IWL<3789> A_IWL<3788> A_IWL<3787> A_IWL<3786> A_IWL<3785> A_IWL<3784> A_IWL<3783> A_IWL<3782> A_IWL<3781> A_IWL<3780> A_IWL<3779> A_IWL<3778> A_IWL<3777> A_IWL<3776> A_IWL<3775> A_IWL<3774> A_IWL<3773> A_IWL<3772> A_IWL<3771> A_IWL<3770> A_IWL<3769> A_IWL<3768> A_IWL<3767> A_IWL<3766> A_IWL<3765> A_IWL<3764> A_IWL<3763> A_IWL<3762> A_IWL<3761> A_IWL<3760> A_IWL<3759> A_IWL<3758> A_IWL<3757> A_IWL<3756> A_IWL<3755> A_IWL<3754> A_IWL<3753> A_IWL<3752> A_IWL<3751> A_IWL<3750> A_IWL<3749> A_IWL<3748> A_IWL<3747> A_IWL<3746> A_IWL<3745> A_IWL<3744> A_IWL<3743> A_IWL<3742> A_IWL<3741> A_IWL<3740> A_IWL<3739> A_IWL<3738> A_IWL<3737> A_IWL<3736> A_IWL<3735> A_IWL<3734> A_IWL<3733> A_IWL<3732> A_IWL<3731> A_IWL<3730> A_IWL<3729> A_IWL<3728> A_IWL<3727> A_IWL<3726> A_IWL<3725> A_IWL<3724> A_IWL<3723> A_IWL<3722> A_IWL<3721> A_IWL<3720> A_IWL<3719> A_IWL<3718> A_IWL<3717> A_IWL<3716> A_IWL<3715> A_IWL<3714> A_IWL<3713> A_IWL<3712> A_IWL<3711> A_IWL<3710> A_IWL<3709> A_IWL<3708> A_IWL<3707> A_IWL<3706> A_IWL<3705> A_IWL<3704> A_IWL<3703> A_IWL<3702> A_IWL<3701> A_IWL<3700> A_IWL<3699> A_IWL<3698> A_IWL<3697> A_IWL<3696> A_IWL<3695> A_IWL<3694> A_IWL<3693> A_IWL<3692> A_IWL<3691> A_IWL<3690> A_IWL<3689> A_IWL<3688> A_IWL<3687> A_IWL<3686> A_IWL<3685> A_IWL<3684> A_IWL<3683> A_IWL<3682> A_IWL<3681> A_IWL<3680> A_IWL<3679> A_IWL<3678> A_IWL<3677> A_IWL<3676> A_IWL<3675> A_IWL<3674> A_IWL<3673> A_IWL<3672> A_IWL<3671> A_IWL<3670> A_IWL<3669> A_IWL<3668> A_IWL<3667> A_IWL<3666> A_IWL<3665> A_IWL<3664> A_IWL<3663> A_IWL<3662> A_IWL<3661> A_IWL<3660> A_IWL<3659> A_IWL<3658> A_IWL<3657> A_IWL<3656> A_IWL<3655> A_IWL<3654> A_IWL<3653> A_IWL<3652> A_IWL<3651> A_IWL<3650> A_IWL<3649> A_IWL<3648> A_IWL<3647> A_IWL<3646> A_IWL<3645> A_IWL<3644> A_IWL<3643> A_IWL<3642> A_IWL<3641> A_IWL<3640> A_IWL<3639> A_IWL<3638> A_IWL<3637> A_IWL<3636> A_IWL<3635> A_IWL<3634> A_IWL<3633> A_IWL<3632> A_IWL<3631> A_IWL<3630> A_IWL<3629> A_IWL<3628> A_IWL<3627> A_IWL<3626> A_IWL<3625> A_IWL<3624> A_IWL<3623> A_IWL<3622> A_IWL<3621> A_IWL<3620> A_IWL<3619> A_IWL<3618> A_IWL<3617> A_IWL<3616> A_IWL<3615> A_IWL<3614> A_IWL<3613> A_IWL<3612> A_IWL<3611> A_IWL<3610> A_IWL<3609> A_IWL<3608> A_IWL<3607> A_IWL<3606> A_IWL<3605> A_IWL<3604> A_IWL<3603> A_IWL<3602> A_IWL<3601> A_IWL<3600> A_IWL<3599> A_IWL<3598> A_IWL<3597> A_IWL<3596> A_IWL<3595> A_IWL<3594> A_IWL<3593> A_IWL<3592> A_IWL<3591> A_IWL<3590> A_IWL<3589> A_IWL<3588> A_IWL<3587> A_IWL<3586> A_IWL<3585> A_IWL<3584> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_COLUMN_pcell_0
+XCOL<13> A_BLC<27> A_BLC<26> A_BLC_TOP<27> A_BLC_TOP<26> A_BLT<27> A_BLT<26> A_BLT_TOP<27> A_BLT_TOP<26> A_IWL<3327> A_IWL<3326> A_IWL<3325> A_IWL<3324> A_IWL<3323> A_IWL<3322> A_IWL<3321> A_IWL<3320> A_IWL<3319> A_IWL<3318> A_IWL<3317> A_IWL<3316> A_IWL<3315> A_IWL<3314> A_IWL<3313> A_IWL<3312> A_IWL<3311> A_IWL<3310> A_IWL<3309> A_IWL<3308> A_IWL<3307> A_IWL<3306> A_IWL<3305> A_IWL<3304> A_IWL<3303> A_IWL<3302> A_IWL<3301> A_IWL<3300> A_IWL<3299> A_IWL<3298> A_IWL<3297> A_IWL<3296> A_IWL<3295> A_IWL<3294> A_IWL<3293> A_IWL<3292> A_IWL<3291> A_IWL<3290> A_IWL<3289> A_IWL<3288> A_IWL<3287> A_IWL<3286> A_IWL<3285> A_IWL<3284> A_IWL<3283> A_IWL<3282> A_IWL<3281> A_IWL<3280> A_IWL<3279> A_IWL<3278> A_IWL<3277> A_IWL<3276> A_IWL<3275> A_IWL<3274> A_IWL<3273> A_IWL<3272> A_IWL<3271> A_IWL<3270> A_IWL<3269> A_IWL<3268> A_IWL<3267> A_IWL<3266> A_IWL<3265> A_IWL<3264> A_IWL<3263> A_IWL<3262> A_IWL<3261> A_IWL<3260> A_IWL<3259> A_IWL<3258> A_IWL<3257> A_IWL<3256> A_IWL<3255> A_IWL<3254> A_IWL<3253> A_IWL<3252> A_IWL<3251> A_IWL<3250> A_IWL<3249> A_IWL<3248> A_IWL<3247> A_IWL<3246> A_IWL<3245> A_IWL<3244> A_IWL<3243> A_IWL<3242> A_IWL<3241> A_IWL<3240> A_IWL<3239> A_IWL<3238> A_IWL<3237> A_IWL<3236> A_IWL<3235> A_IWL<3234> A_IWL<3233> A_IWL<3232> A_IWL<3231> A_IWL<3230> A_IWL<3229> A_IWL<3228> A_IWL<3227> A_IWL<3226> A_IWL<3225> A_IWL<3224> A_IWL<3223> A_IWL<3222> A_IWL<3221> A_IWL<3220> A_IWL<3219> A_IWL<3218> A_IWL<3217> A_IWL<3216> A_IWL<3215> A_IWL<3214> A_IWL<3213> A_IWL<3212> A_IWL<3211> A_IWL<3210> A_IWL<3209> A_IWL<3208> A_IWL<3207> A_IWL<3206> A_IWL<3205> A_IWL<3204> A_IWL<3203> A_IWL<3202> A_IWL<3201> A_IWL<3200> A_IWL<3199> A_IWL<3198> A_IWL<3197> A_IWL<3196> A_IWL<3195> A_IWL<3194> A_IWL<3193> A_IWL<3192> A_IWL<3191> A_IWL<3190> A_IWL<3189> A_IWL<3188> A_IWL<3187> A_IWL<3186> A_IWL<3185> A_IWL<3184> A_IWL<3183> A_IWL<3182> A_IWL<3181> A_IWL<3180> A_IWL<3179> A_IWL<3178> A_IWL<3177> A_IWL<3176> A_IWL<3175> A_IWL<3174> A_IWL<3173> A_IWL<3172> A_IWL<3171> A_IWL<3170> A_IWL<3169> A_IWL<3168> A_IWL<3167> A_IWL<3166> A_IWL<3165> A_IWL<3164> A_IWL<3163> A_IWL<3162> A_IWL<3161> A_IWL<3160> A_IWL<3159> A_IWL<3158> A_IWL<3157> A_IWL<3156> A_IWL<3155> A_IWL<3154> A_IWL<3153> A_IWL<3152> A_IWL<3151> A_IWL<3150> A_IWL<3149> A_IWL<3148> A_IWL<3147> A_IWL<3146> A_IWL<3145> A_IWL<3144> A_IWL<3143> A_IWL<3142> A_IWL<3141> A_IWL<3140> A_IWL<3139> A_IWL<3138> A_IWL<3137> A_IWL<3136> A_IWL<3135> A_IWL<3134> A_IWL<3133> A_IWL<3132> A_IWL<3131> A_IWL<3130> A_IWL<3129> A_IWL<3128> A_IWL<3127> A_IWL<3126> A_IWL<3125> A_IWL<3124> A_IWL<3123> A_IWL<3122> A_IWL<3121> A_IWL<3120> A_IWL<3119> A_IWL<3118> A_IWL<3117> A_IWL<3116> A_IWL<3115> A_IWL<3114> A_IWL<3113> A_IWL<3112> A_IWL<3111> A_IWL<3110> A_IWL<3109> A_IWL<3108> A_IWL<3107> A_IWL<3106> A_IWL<3105> A_IWL<3104> A_IWL<3103> A_IWL<3102> A_IWL<3101> A_IWL<3100> A_IWL<3099> A_IWL<3098> A_IWL<3097> A_IWL<3096> A_IWL<3095> A_IWL<3094> A_IWL<3093> A_IWL<3092> A_IWL<3091> A_IWL<3090> A_IWL<3089> A_IWL<3088> A_IWL<3087> A_IWL<3086> A_IWL<3085> A_IWL<3084> A_IWL<3083> A_IWL<3082> A_IWL<3081> A_IWL<3080> A_IWL<3079> A_IWL<3078> A_IWL<3077> A_IWL<3076> A_IWL<3075> A_IWL<3074> A_IWL<3073> A_IWL<3072> A_IWL<3583> A_IWL<3582> A_IWL<3581> A_IWL<3580> A_IWL<3579> A_IWL<3578> A_IWL<3577> A_IWL<3576> A_IWL<3575> A_IWL<3574> A_IWL<3573> A_IWL<3572> A_IWL<3571> A_IWL<3570> A_IWL<3569> A_IWL<3568> A_IWL<3567> A_IWL<3566> A_IWL<3565> A_IWL<3564> A_IWL<3563> A_IWL<3562> A_IWL<3561> A_IWL<3560> A_IWL<3559> A_IWL<3558> A_IWL<3557> A_IWL<3556> A_IWL<3555> A_IWL<3554> A_IWL<3553> A_IWL<3552> A_IWL<3551> A_IWL<3550> A_IWL<3549> A_IWL<3548> A_IWL<3547> A_IWL<3546> A_IWL<3545> A_IWL<3544> A_IWL<3543> A_IWL<3542> A_IWL<3541> A_IWL<3540> A_IWL<3539> A_IWL<3538> A_IWL<3537> A_IWL<3536> A_IWL<3535> A_IWL<3534> A_IWL<3533> A_IWL<3532> A_IWL<3531> A_IWL<3530> A_IWL<3529> A_IWL<3528> A_IWL<3527> A_IWL<3526> A_IWL<3525> A_IWL<3524> A_IWL<3523> A_IWL<3522> A_IWL<3521> A_IWL<3520> A_IWL<3519> A_IWL<3518> A_IWL<3517> A_IWL<3516> A_IWL<3515> A_IWL<3514> A_IWL<3513> A_IWL<3512> A_IWL<3511> A_IWL<3510> A_IWL<3509> A_IWL<3508> A_IWL<3507> A_IWL<3506> A_IWL<3505> A_IWL<3504> A_IWL<3503> A_IWL<3502> A_IWL<3501> A_IWL<3500> A_IWL<3499> A_IWL<3498> A_IWL<3497> A_IWL<3496> A_IWL<3495> A_IWL<3494> A_IWL<3493> A_IWL<3492> A_IWL<3491> A_IWL<3490> A_IWL<3489> A_IWL<3488> A_IWL<3487> A_IWL<3486> A_IWL<3485> A_IWL<3484> A_IWL<3483> A_IWL<3482> A_IWL<3481> A_IWL<3480> A_IWL<3479> A_IWL<3478> A_IWL<3477> A_IWL<3476> A_IWL<3475> A_IWL<3474> A_IWL<3473> A_IWL<3472> A_IWL<3471> A_IWL<3470> A_IWL<3469> A_IWL<3468> A_IWL<3467> A_IWL<3466> A_IWL<3465> A_IWL<3464> A_IWL<3463> A_IWL<3462> A_IWL<3461> A_IWL<3460> A_IWL<3459> A_IWL<3458> A_IWL<3457> A_IWL<3456> A_IWL<3455> A_IWL<3454> A_IWL<3453> A_IWL<3452> A_IWL<3451> A_IWL<3450> A_IWL<3449> A_IWL<3448> A_IWL<3447> A_IWL<3446> A_IWL<3445> A_IWL<3444> A_IWL<3443> A_IWL<3442> A_IWL<3441> A_IWL<3440> A_IWL<3439> A_IWL<3438> A_IWL<3437> A_IWL<3436> A_IWL<3435> A_IWL<3434> A_IWL<3433> A_IWL<3432> A_IWL<3431> A_IWL<3430> A_IWL<3429> A_IWL<3428> A_IWL<3427> A_IWL<3426> A_IWL<3425> A_IWL<3424> A_IWL<3423> A_IWL<3422> A_IWL<3421> A_IWL<3420> A_IWL<3419> A_IWL<3418> A_IWL<3417> A_IWL<3416> A_IWL<3415> A_IWL<3414> A_IWL<3413> A_IWL<3412> A_IWL<3411> A_IWL<3410> A_IWL<3409> A_IWL<3408> A_IWL<3407> A_IWL<3406> A_IWL<3405> A_IWL<3404> A_IWL<3403> A_IWL<3402> A_IWL<3401> A_IWL<3400> A_IWL<3399> A_IWL<3398> A_IWL<3397> A_IWL<3396> A_IWL<3395> A_IWL<3394> A_IWL<3393> A_IWL<3392> A_IWL<3391> A_IWL<3390> A_IWL<3389> A_IWL<3388> A_IWL<3387> A_IWL<3386> A_IWL<3385> A_IWL<3384> A_IWL<3383> A_IWL<3382> A_IWL<3381> A_IWL<3380> A_IWL<3379> A_IWL<3378> A_IWL<3377> A_IWL<3376> A_IWL<3375> A_IWL<3374> A_IWL<3373> A_IWL<3372> A_IWL<3371> A_IWL<3370> A_IWL<3369> A_IWL<3368> A_IWL<3367> A_IWL<3366> A_IWL<3365> A_IWL<3364> A_IWL<3363> A_IWL<3362> A_IWL<3361> A_IWL<3360> A_IWL<3359> A_IWL<3358> A_IWL<3357> A_IWL<3356> A_IWL<3355> A_IWL<3354> A_IWL<3353> A_IWL<3352> A_IWL<3351> A_IWL<3350> A_IWL<3349> A_IWL<3348> A_IWL<3347> A_IWL<3346> A_IWL<3345> A_IWL<3344> A_IWL<3343> A_IWL<3342> A_IWL<3341> A_IWL<3340> A_IWL<3339> A_IWL<3338> A_IWL<3337> A_IWL<3336> A_IWL<3335> A_IWL<3334> A_IWL<3333> A_IWL<3332> A_IWL<3331> A_IWL<3330> A_IWL<3329> A_IWL<3328> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_COLUMN_pcell_0
+XCOL<12> A_BLC<25> A_BLC<24> A_BLC_TOP<25> A_BLC_TOP<24> A_BLT<25> A_BLT<24> A_BLT_TOP<25> A_BLT_TOP<24> A_IWL<3071> A_IWL<3070> A_IWL<3069> A_IWL<3068> A_IWL<3067> A_IWL<3066> A_IWL<3065> A_IWL<3064> A_IWL<3063> A_IWL<3062> A_IWL<3061> A_IWL<3060> A_IWL<3059> A_IWL<3058> A_IWL<3057> A_IWL<3056> A_IWL<3055> A_IWL<3054> A_IWL<3053> A_IWL<3052> A_IWL<3051> A_IWL<3050> A_IWL<3049> A_IWL<3048> A_IWL<3047> A_IWL<3046> A_IWL<3045> A_IWL<3044> A_IWL<3043> A_IWL<3042> A_IWL<3041> A_IWL<3040> A_IWL<3039> A_IWL<3038> A_IWL<3037> A_IWL<3036> A_IWL<3035> A_IWL<3034> A_IWL<3033> A_IWL<3032> A_IWL<3031> A_IWL<3030> A_IWL<3029> A_IWL<3028> A_IWL<3027> A_IWL<3026> A_IWL<3025> A_IWL<3024> A_IWL<3023> A_IWL<3022> A_IWL<3021> A_IWL<3020> A_IWL<3019> A_IWL<3018> A_IWL<3017> A_IWL<3016> A_IWL<3015> A_IWL<3014> A_IWL<3013> A_IWL<3012> A_IWL<3011> A_IWL<3010> A_IWL<3009> A_IWL<3008> A_IWL<3007> A_IWL<3006> A_IWL<3005> A_IWL<3004> A_IWL<3003> A_IWL<3002> A_IWL<3001> A_IWL<3000> A_IWL<2999> A_IWL<2998> A_IWL<2997> A_IWL<2996> A_IWL<2995> A_IWL<2994> A_IWL<2993> A_IWL<2992> A_IWL<2991> A_IWL<2990> A_IWL<2989> A_IWL<2988> A_IWL<2987> A_IWL<2986> A_IWL<2985> A_IWL<2984> A_IWL<2983> A_IWL<2982> A_IWL<2981> A_IWL<2980> A_IWL<2979> A_IWL<2978> A_IWL<2977> A_IWL<2976> A_IWL<2975> A_IWL<2974> A_IWL<2973> A_IWL<2972> A_IWL<2971> A_IWL<2970> A_IWL<2969> A_IWL<2968> A_IWL<2967> A_IWL<2966> A_IWL<2965> A_IWL<2964> A_IWL<2963> A_IWL<2962> A_IWL<2961> A_IWL<2960> A_IWL<2959> A_IWL<2958> A_IWL<2957> A_IWL<2956> A_IWL<2955> A_IWL<2954> A_IWL<2953> A_IWL<2952> A_IWL<2951> A_IWL<2950> A_IWL<2949> A_IWL<2948> A_IWL<2947> A_IWL<2946> A_IWL<2945> A_IWL<2944> A_IWL<2943> A_IWL<2942> A_IWL<2941> A_IWL<2940> A_IWL<2939> A_IWL<2938> A_IWL<2937> A_IWL<2936> A_IWL<2935> A_IWL<2934> A_IWL<2933> A_IWL<2932> A_IWL<2931> A_IWL<2930> A_IWL<2929> A_IWL<2928> A_IWL<2927> A_IWL<2926> A_IWL<2925> A_IWL<2924> A_IWL<2923> A_IWL<2922> A_IWL<2921> A_IWL<2920> A_IWL<2919> A_IWL<2918> A_IWL<2917> A_IWL<2916> A_IWL<2915> A_IWL<2914> A_IWL<2913> A_IWL<2912> A_IWL<2911> A_IWL<2910> A_IWL<2909> A_IWL<2908> A_IWL<2907> A_IWL<2906> A_IWL<2905> A_IWL<2904> A_IWL<2903> A_IWL<2902> A_IWL<2901> A_IWL<2900> A_IWL<2899> A_IWL<2898> A_IWL<2897> A_IWL<2896> A_IWL<2895> A_IWL<2894> A_IWL<2893> A_IWL<2892> A_IWL<2891> A_IWL<2890> A_IWL<2889> A_IWL<2888> A_IWL<2887> A_IWL<2886> A_IWL<2885> A_IWL<2884> A_IWL<2883> A_IWL<2882> A_IWL<2881> A_IWL<2880> A_IWL<2879> A_IWL<2878> A_IWL<2877> A_IWL<2876> A_IWL<2875> A_IWL<2874> A_IWL<2873> A_IWL<2872> A_IWL<2871> A_IWL<2870> A_IWL<2869> A_IWL<2868> A_IWL<2867> A_IWL<2866> A_IWL<2865> A_IWL<2864> A_IWL<2863> A_IWL<2862> A_IWL<2861> A_IWL<2860> A_IWL<2859> A_IWL<2858> A_IWL<2857> A_IWL<2856> A_IWL<2855> A_IWL<2854> A_IWL<2853> A_IWL<2852> A_IWL<2851> A_IWL<2850> A_IWL<2849> A_IWL<2848> A_IWL<2847> A_IWL<2846> A_IWL<2845> A_IWL<2844> A_IWL<2843> A_IWL<2842> A_IWL<2841> A_IWL<2840> A_IWL<2839> A_IWL<2838> A_IWL<2837> A_IWL<2836> A_IWL<2835> A_IWL<2834> A_IWL<2833> A_IWL<2832> A_IWL<2831> A_IWL<2830> A_IWL<2829> A_IWL<2828> A_IWL<2827> A_IWL<2826> A_IWL<2825> A_IWL<2824> A_IWL<2823> A_IWL<2822> A_IWL<2821> A_IWL<2820> A_IWL<2819> A_IWL<2818> A_IWL<2817> A_IWL<2816> A_IWL<3327> A_IWL<3326> A_IWL<3325> A_IWL<3324> A_IWL<3323> A_IWL<3322> A_IWL<3321> A_IWL<3320> A_IWL<3319> A_IWL<3318> A_IWL<3317> A_IWL<3316> A_IWL<3315> A_IWL<3314> A_IWL<3313> A_IWL<3312> A_IWL<3311> A_IWL<3310> A_IWL<3309> A_IWL<3308> A_IWL<3307> A_IWL<3306> A_IWL<3305> A_IWL<3304> A_IWL<3303> A_IWL<3302> A_IWL<3301> A_IWL<3300> A_IWL<3299> A_IWL<3298> A_IWL<3297> A_IWL<3296> A_IWL<3295> A_IWL<3294> A_IWL<3293> A_IWL<3292> A_IWL<3291> A_IWL<3290> A_IWL<3289> A_IWL<3288> A_IWL<3287> A_IWL<3286> A_IWL<3285> A_IWL<3284> A_IWL<3283> A_IWL<3282> A_IWL<3281> A_IWL<3280> A_IWL<3279> A_IWL<3278> A_IWL<3277> A_IWL<3276> A_IWL<3275> A_IWL<3274> A_IWL<3273> A_IWL<3272> A_IWL<3271> A_IWL<3270> A_IWL<3269> A_IWL<3268> A_IWL<3267> A_IWL<3266> A_IWL<3265> A_IWL<3264> A_IWL<3263> A_IWL<3262> A_IWL<3261> A_IWL<3260> A_IWL<3259> A_IWL<3258> A_IWL<3257> A_IWL<3256> A_IWL<3255> A_IWL<3254> A_IWL<3253> A_IWL<3252> A_IWL<3251> A_IWL<3250> A_IWL<3249> A_IWL<3248> A_IWL<3247> A_IWL<3246> A_IWL<3245> A_IWL<3244> A_IWL<3243> A_IWL<3242> A_IWL<3241> A_IWL<3240> A_IWL<3239> A_IWL<3238> A_IWL<3237> A_IWL<3236> A_IWL<3235> A_IWL<3234> A_IWL<3233> A_IWL<3232> A_IWL<3231> A_IWL<3230> A_IWL<3229> A_IWL<3228> A_IWL<3227> A_IWL<3226> A_IWL<3225> A_IWL<3224> A_IWL<3223> A_IWL<3222> A_IWL<3221> A_IWL<3220> A_IWL<3219> A_IWL<3218> A_IWL<3217> A_IWL<3216> A_IWL<3215> A_IWL<3214> A_IWL<3213> A_IWL<3212> A_IWL<3211> A_IWL<3210> A_IWL<3209> A_IWL<3208> A_IWL<3207> A_IWL<3206> A_IWL<3205> A_IWL<3204> A_IWL<3203> A_IWL<3202> A_IWL<3201> A_IWL<3200> A_IWL<3199> A_IWL<3198> A_IWL<3197> A_IWL<3196> A_IWL<3195> A_IWL<3194> A_IWL<3193> A_IWL<3192> A_IWL<3191> A_IWL<3190> A_IWL<3189> A_IWL<3188> A_IWL<3187> A_IWL<3186> A_IWL<3185> A_IWL<3184> A_IWL<3183> A_IWL<3182> A_IWL<3181> A_IWL<3180> A_IWL<3179> A_IWL<3178> A_IWL<3177> A_IWL<3176> A_IWL<3175> A_IWL<3174> A_IWL<3173> A_IWL<3172> A_IWL<3171> A_IWL<3170> A_IWL<3169> A_IWL<3168> A_IWL<3167> A_IWL<3166> A_IWL<3165> A_IWL<3164> A_IWL<3163> A_IWL<3162> A_IWL<3161> A_IWL<3160> A_IWL<3159> A_IWL<3158> A_IWL<3157> A_IWL<3156> A_IWL<3155> A_IWL<3154> A_IWL<3153> A_IWL<3152> A_IWL<3151> A_IWL<3150> A_IWL<3149> A_IWL<3148> A_IWL<3147> A_IWL<3146> A_IWL<3145> A_IWL<3144> A_IWL<3143> A_IWL<3142> A_IWL<3141> A_IWL<3140> A_IWL<3139> A_IWL<3138> A_IWL<3137> A_IWL<3136> A_IWL<3135> A_IWL<3134> A_IWL<3133> A_IWL<3132> A_IWL<3131> A_IWL<3130> A_IWL<3129> A_IWL<3128> A_IWL<3127> A_IWL<3126> A_IWL<3125> A_IWL<3124> A_IWL<3123> A_IWL<3122> A_IWL<3121> A_IWL<3120> A_IWL<3119> A_IWL<3118> A_IWL<3117> A_IWL<3116> A_IWL<3115> A_IWL<3114> A_IWL<3113> A_IWL<3112> A_IWL<3111> A_IWL<3110> A_IWL<3109> A_IWL<3108> A_IWL<3107> A_IWL<3106> A_IWL<3105> A_IWL<3104> A_IWL<3103> A_IWL<3102> A_IWL<3101> A_IWL<3100> A_IWL<3099> A_IWL<3098> A_IWL<3097> A_IWL<3096> A_IWL<3095> A_IWL<3094> A_IWL<3093> A_IWL<3092> A_IWL<3091> A_IWL<3090> A_IWL<3089> A_IWL<3088> A_IWL<3087> A_IWL<3086> A_IWL<3085> A_IWL<3084> A_IWL<3083> A_IWL<3082> A_IWL<3081> A_IWL<3080> A_IWL<3079> A_IWL<3078> A_IWL<3077> A_IWL<3076> A_IWL<3075> A_IWL<3074> A_IWL<3073> A_IWL<3072> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_COLUMN_pcell_0
+XCOL<11> A_BLC<23> A_BLC<22> A_BLC_TOP<23> A_BLC_TOP<22> A_BLT<23> A_BLT<22> A_BLT_TOP<23> A_BLT_TOP<22> A_IWL<2815> A_IWL<2814> A_IWL<2813> A_IWL<2812> A_IWL<2811> A_IWL<2810> A_IWL<2809> A_IWL<2808> A_IWL<2807> A_IWL<2806> A_IWL<2805> A_IWL<2804> A_IWL<2803> A_IWL<2802> A_IWL<2801> A_IWL<2800> A_IWL<2799> A_IWL<2798> A_IWL<2797> A_IWL<2796> A_IWL<2795> A_IWL<2794> A_IWL<2793> A_IWL<2792> A_IWL<2791> A_IWL<2790> A_IWL<2789> A_IWL<2788> A_IWL<2787> A_IWL<2786> A_IWL<2785> A_IWL<2784> A_IWL<2783> A_IWL<2782> A_IWL<2781> A_IWL<2780> A_IWL<2779> A_IWL<2778> A_IWL<2777> A_IWL<2776> A_IWL<2775> A_IWL<2774> A_IWL<2773> A_IWL<2772> A_IWL<2771> A_IWL<2770> A_IWL<2769> A_IWL<2768> A_IWL<2767> A_IWL<2766> A_IWL<2765> A_IWL<2764> A_IWL<2763> A_IWL<2762> A_IWL<2761> A_IWL<2760> A_IWL<2759> A_IWL<2758> A_IWL<2757> A_IWL<2756> A_IWL<2755> A_IWL<2754> A_IWL<2753> A_IWL<2752> A_IWL<2751> A_IWL<2750> A_IWL<2749> A_IWL<2748> A_IWL<2747> A_IWL<2746> A_IWL<2745> A_IWL<2744> A_IWL<2743> A_IWL<2742> A_IWL<2741> A_IWL<2740> A_IWL<2739> A_IWL<2738> A_IWL<2737> A_IWL<2736> A_IWL<2735> A_IWL<2734> A_IWL<2733> A_IWL<2732> A_IWL<2731> A_IWL<2730> A_IWL<2729> A_IWL<2728> A_IWL<2727> A_IWL<2726> A_IWL<2725> A_IWL<2724> A_IWL<2723> A_IWL<2722> A_IWL<2721> A_IWL<2720> A_IWL<2719> A_IWL<2718> A_IWL<2717> A_IWL<2716> A_IWL<2715> A_IWL<2714> A_IWL<2713> A_IWL<2712> A_IWL<2711> A_IWL<2710> A_IWL<2709> A_IWL<2708> A_IWL<2707> A_IWL<2706> A_IWL<2705> A_IWL<2704> A_IWL<2703> A_IWL<2702> A_IWL<2701> A_IWL<2700> A_IWL<2699> A_IWL<2698> A_IWL<2697> A_IWL<2696> A_IWL<2695> A_IWL<2694> A_IWL<2693> A_IWL<2692> A_IWL<2691> A_IWL<2690> A_IWL<2689> A_IWL<2688> A_IWL<2687> A_IWL<2686> A_IWL<2685> A_IWL<2684> A_IWL<2683> A_IWL<2682> A_IWL<2681> A_IWL<2680> A_IWL<2679> A_IWL<2678> A_IWL<2677> A_IWL<2676> A_IWL<2675> A_IWL<2674> A_IWL<2673> A_IWL<2672> A_IWL<2671> A_IWL<2670> A_IWL<2669> A_IWL<2668> A_IWL<2667> A_IWL<2666> A_IWL<2665> A_IWL<2664> A_IWL<2663> A_IWL<2662> A_IWL<2661> A_IWL<2660> A_IWL<2659> A_IWL<2658> A_IWL<2657> A_IWL<2656> A_IWL<2655> A_IWL<2654> A_IWL<2653> A_IWL<2652> A_IWL<2651> A_IWL<2650> A_IWL<2649> A_IWL<2648> A_IWL<2647> A_IWL<2646> A_IWL<2645> A_IWL<2644> A_IWL<2643> A_IWL<2642> A_IWL<2641> A_IWL<2640> A_IWL<2639> A_IWL<2638> A_IWL<2637> A_IWL<2636> A_IWL<2635> A_IWL<2634> A_IWL<2633> A_IWL<2632> A_IWL<2631> A_IWL<2630> A_IWL<2629> A_IWL<2628> A_IWL<2627> A_IWL<2626> A_IWL<2625> A_IWL<2624> A_IWL<2623> A_IWL<2622> A_IWL<2621> A_IWL<2620> A_IWL<2619> A_IWL<2618> A_IWL<2617> A_IWL<2616> A_IWL<2615> A_IWL<2614> A_IWL<2613> A_IWL<2612> A_IWL<2611> A_IWL<2610> A_IWL<2609> A_IWL<2608> A_IWL<2607> A_IWL<2606> A_IWL<2605> A_IWL<2604> A_IWL<2603> A_IWL<2602> A_IWL<2601> A_IWL<2600> A_IWL<2599> A_IWL<2598> A_IWL<2597> A_IWL<2596> A_IWL<2595> A_IWL<2594> A_IWL<2593> A_IWL<2592> A_IWL<2591> A_IWL<2590> A_IWL<2589> A_IWL<2588> A_IWL<2587> A_IWL<2586> A_IWL<2585> A_IWL<2584> A_IWL<2583> A_IWL<2582> A_IWL<2581> A_IWL<2580> A_IWL<2579> A_IWL<2578> A_IWL<2577> A_IWL<2576> A_IWL<2575> A_IWL<2574> A_IWL<2573> A_IWL<2572> A_IWL<2571> A_IWL<2570> A_IWL<2569> A_IWL<2568> A_IWL<2567> A_IWL<2566> A_IWL<2565> A_IWL<2564> A_IWL<2563> A_IWL<2562> A_IWL<2561> A_IWL<2560> A_IWL<3071> A_IWL<3070> A_IWL<3069> A_IWL<3068> A_IWL<3067> A_IWL<3066> A_IWL<3065> A_IWL<3064> A_IWL<3063> A_IWL<3062> A_IWL<3061> A_IWL<3060> A_IWL<3059> A_IWL<3058> A_IWL<3057> A_IWL<3056> A_IWL<3055> A_IWL<3054> A_IWL<3053> A_IWL<3052> A_IWL<3051> A_IWL<3050> A_IWL<3049> A_IWL<3048> A_IWL<3047> A_IWL<3046> A_IWL<3045> A_IWL<3044> A_IWL<3043> A_IWL<3042> A_IWL<3041> A_IWL<3040> A_IWL<3039> A_IWL<3038> A_IWL<3037> A_IWL<3036> A_IWL<3035> A_IWL<3034> A_IWL<3033> A_IWL<3032> A_IWL<3031> A_IWL<3030> A_IWL<3029> A_IWL<3028> A_IWL<3027> A_IWL<3026> A_IWL<3025> A_IWL<3024> A_IWL<3023> A_IWL<3022> A_IWL<3021> A_IWL<3020> A_IWL<3019> A_IWL<3018> A_IWL<3017> A_IWL<3016> A_IWL<3015> A_IWL<3014> A_IWL<3013> A_IWL<3012> A_IWL<3011> A_IWL<3010> A_IWL<3009> A_IWL<3008> A_IWL<3007> A_IWL<3006> A_IWL<3005> A_IWL<3004> A_IWL<3003> A_IWL<3002> A_IWL<3001> A_IWL<3000> A_IWL<2999> A_IWL<2998> A_IWL<2997> A_IWL<2996> A_IWL<2995> A_IWL<2994> A_IWL<2993> A_IWL<2992> A_IWL<2991> A_IWL<2990> A_IWL<2989> A_IWL<2988> A_IWL<2987> A_IWL<2986> A_IWL<2985> A_IWL<2984> A_IWL<2983> A_IWL<2982> A_IWL<2981> A_IWL<2980> A_IWL<2979> A_IWL<2978> A_IWL<2977> A_IWL<2976> A_IWL<2975> A_IWL<2974> A_IWL<2973> A_IWL<2972> A_IWL<2971> A_IWL<2970> A_IWL<2969> A_IWL<2968> A_IWL<2967> A_IWL<2966> A_IWL<2965> A_IWL<2964> A_IWL<2963> A_IWL<2962> A_IWL<2961> A_IWL<2960> A_IWL<2959> A_IWL<2958> A_IWL<2957> A_IWL<2956> A_IWL<2955> A_IWL<2954> A_IWL<2953> A_IWL<2952> A_IWL<2951> A_IWL<2950> A_IWL<2949> A_IWL<2948> A_IWL<2947> A_IWL<2946> A_IWL<2945> A_IWL<2944> A_IWL<2943> A_IWL<2942> A_IWL<2941> A_IWL<2940> A_IWL<2939> A_IWL<2938> A_IWL<2937> A_IWL<2936> A_IWL<2935> A_IWL<2934> A_IWL<2933> A_IWL<2932> A_IWL<2931> A_IWL<2930> A_IWL<2929> A_IWL<2928> A_IWL<2927> A_IWL<2926> A_IWL<2925> A_IWL<2924> A_IWL<2923> A_IWL<2922> A_IWL<2921> A_IWL<2920> A_IWL<2919> A_IWL<2918> A_IWL<2917> A_IWL<2916> A_IWL<2915> A_IWL<2914> A_IWL<2913> A_IWL<2912> A_IWL<2911> A_IWL<2910> A_IWL<2909> A_IWL<2908> A_IWL<2907> A_IWL<2906> A_IWL<2905> A_IWL<2904> A_IWL<2903> A_IWL<2902> A_IWL<2901> A_IWL<2900> A_IWL<2899> A_IWL<2898> A_IWL<2897> A_IWL<2896> A_IWL<2895> A_IWL<2894> A_IWL<2893> A_IWL<2892> A_IWL<2891> A_IWL<2890> A_IWL<2889> A_IWL<2888> A_IWL<2887> A_IWL<2886> A_IWL<2885> A_IWL<2884> A_IWL<2883> A_IWL<2882> A_IWL<2881> A_IWL<2880> A_IWL<2879> A_IWL<2878> A_IWL<2877> A_IWL<2876> A_IWL<2875> A_IWL<2874> A_IWL<2873> A_IWL<2872> A_IWL<2871> A_IWL<2870> A_IWL<2869> A_IWL<2868> A_IWL<2867> A_IWL<2866> A_IWL<2865> A_IWL<2864> A_IWL<2863> A_IWL<2862> A_IWL<2861> A_IWL<2860> A_IWL<2859> A_IWL<2858> A_IWL<2857> A_IWL<2856> A_IWL<2855> A_IWL<2854> A_IWL<2853> A_IWL<2852> A_IWL<2851> A_IWL<2850> A_IWL<2849> A_IWL<2848> A_IWL<2847> A_IWL<2846> A_IWL<2845> A_IWL<2844> A_IWL<2843> A_IWL<2842> A_IWL<2841> A_IWL<2840> A_IWL<2839> A_IWL<2838> A_IWL<2837> A_IWL<2836> A_IWL<2835> A_IWL<2834> A_IWL<2833> A_IWL<2832> A_IWL<2831> A_IWL<2830> A_IWL<2829> A_IWL<2828> A_IWL<2827> A_IWL<2826> A_IWL<2825> A_IWL<2824> A_IWL<2823> A_IWL<2822> A_IWL<2821> A_IWL<2820> A_IWL<2819> A_IWL<2818> A_IWL<2817> A_IWL<2816> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_COLUMN_pcell_0
+XCOL<10> A_BLC<21> A_BLC<20> A_BLC_TOP<21> A_BLC_TOP<20> A_BLT<21> A_BLT<20> A_BLT_TOP<21> A_BLT_TOP<20> A_IWL<2559> A_IWL<2558> A_IWL<2557> A_IWL<2556> A_IWL<2555> A_IWL<2554> A_IWL<2553> A_IWL<2552> A_IWL<2551> A_IWL<2550> A_IWL<2549> A_IWL<2548> A_IWL<2547> A_IWL<2546> A_IWL<2545> A_IWL<2544> A_IWL<2543> A_IWL<2542> A_IWL<2541> A_IWL<2540> A_IWL<2539> A_IWL<2538> A_IWL<2537> A_IWL<2536> A_IWL<2535> A_IWL<2534> A_IWL<2533> A_IWL<2532> A_IWL<2531> A_IWL<2530> A_IWL<2529> A_IWL<2528> A_IWL<2527> A_IWL<2526> A_IWL<2525> A_IWL<2524> A_IWL<2523> A_IWL<2522> A_IWL<2521> A_IWL<2520> A_IWL<2519> A_IWL<2518> A_IWL<2517> A_IWL<2516> A_IWL<2515> A_IWL<2514> A_IWL<2513> A_IWL<2512> A_IWL<2511> A_IWL<2510> A_IWL<2509> A_IWL<2508> A_IWL<2507> A_IWL<2506> A_IWL<2505> A_IWL<2504> A_IWL<2503> A_IWL<2502> A_IWL<2501> A_IWL<2500> A_IWL<2499> A_IWL<2498> A_IWL<2497> A_IWL<2496> A_IWL<2495> A_IWL<2494> A_IWL<2493> A_IWL<2492> A_IWL<2491> A_IWL<2490> A_IWL<2489> A_IWL<2488> A_IWL<2487> A_IWL<2486> A_IWL<2485> A_IWL<2484> A_IWL<2483> A_IWL<2482> A_IWL<2481> A_IWL<2480> A_IWL<2479> A_IWL<2478> A_IWL<2477> A_IWL<2476> A_IWL<2475> A_IWL<2474> A_IWL<2473> A_IWL<2472> A_IWL<2471> A_IWL<2470> A_IWL<2469> A_IWL<2468> A_IWL<2467> A_IWL<2466> A_IWL<2465> A_IWL<2464> A_IWL<2463> A_IWL<2462> A_IWL<2461> A_IWL<2460> A_IWL<2459> A_IWL<2458> A_IWL<2457> A_IWL<2456> A_IWL<2455> A_IWL<2454> A_IWL<2453> A_IWL<2452> A_IWL<2451> A_IWL<2450> A_IWL<2449> A_IWL<2448> A_IWL<2447> A_IWL<2446> A_IWL<2445> A_IWL<2444> A_IWL<2443> A_IWL<2442> A_IWL<2441> A_IWL<2440> A_IWL<2439> A_IWL<2438> A_IWL<2437> A_IWL<2436> A_IWL<2435> A_IWL<2434> A_IWL<2433> A_IWL<2432> A_IWL<2431> A_IWL<2430> A_IWL<2429> A_IWL<2428> A_IWL<2427> A_IWL<2426> A_IWL<2425> A_IWL<2424> A_IWL<2423> A_IWL<2422> A_IWL<2421> A_IWL<2420> A_IWL<2419> A_IWL<2418> A_IWL<2417> A_IWL<2416> A_IWL<2415> A_IWL<2414> A_IWL<2413> A_IWL<2412> A_IWL<2411> A_IWL<2410> A_IWL<2409> A_IWL<2408> A_IWL<2407> A_IWL<2406> A_IWL<2405> A_IWL<2404> A_IWL<2403> A_IWL<2402> A_IWL<2401> A_IWL<2400> A_IWL<2399> A_IWL<2398> A_IWL<2397> A_IWL<2396> A_IWL<2395> A_IWL<2394> A_IWL<2393> A_IWL<2392> A_IWL<2391> A_IWL<2390> A_IWL<2389> A_IWL<2388> A_IWL<2387> A_IWL<2386> A_IWL<2385> A_IWL<2384> A_IWL<2383> A_IWL<2382> A_IWL<2381> A_IWL<2380> A_IWL<2379> A_IWL<2378> A_IWL<2377> A_IWL<2376> A_IWL<2375> A_IWL<2374> A_IWL<2373> A_IWL<2372> A_IWL<2371> A_IWL<2370> A_IWL<2369> A_IWL<2368> A_IWL<2367> A_IWL<2366> A_IWL<2365> A_IWL<2364> A_IWL<2363> A_IWL<2362> A_IWL<2361> A_IWL<2360> A_IWL<2359> A_IWL<2358> A_IWL<2357> A_IWL<2356> A_IWL<2355> A_IWL<2354> A_IWL<2353> A_IWL<2352> A_IWL<2351> A_IWL<2350> A_IWL<2349> A_IWL<2348> A_IWL<2347> A_IWL<2346> A_IWL<2345> A_IWL<2344> A_IWL<2343> A_IWL<2342> A_IWL<2341> A_IWL<2340> A_IWL<2339> A_IWL<2338> A_IWL<2337> A_IWL<2336> A_IWL<2335> A_IWL<2334> A_IWL<2333> A_IWL<2332> A_IWL<2331> A_IWL<2330> A_IWL<2329> A_IWL<2328> A_IWL<2327> A_IWL<2326> A_IWL<2325> A_IWL<2324> A_IWL<2323> A_IWL<2322> A_IWL<2321> A_IWL<2320> A_IWL<2319> A_IWL<2318> A_IWL<2317> A_IWL<2316> A_IWL<2315> A_IWL<2314> A_IWL<2313> A_IWL<2312> A_IWL<2311> A_IWL<2310> A_IWL<2309> A_IWL<2308> A_IWL<2307> A_IWL<2306> A_IWL<2305> A_IWL<2304> A_IWL<2815> A_IWL<2814> A_IWL<2813> A_IWL<2812> A_IWL<2811> A_IWL<2810> A_IWL<2809> A_IWL<2808> A_IWL<2807> A_IWL<2806> A_IWL<2805> A_IWL<2804> A_IWL<2803> A_IWL<2802> A_IWL<2801> A_IWL<2800> A_IWL<2799> A_IWL<2798> A_IWL<2797> A_IWL<2796> A_IWL<2795> A_IWL<2794> A_IWL<2793> A_IWL<2792> A_IWL<2791> A_IWL<2790> A_IWL<2789> A_IWL<2788> A_IWL<2787> A_IWL<2786> A_IWL<2785> A_IWL<2784> A_IWL<2783> A_IWL<2782> A_IWL<2781> A_IWL<2780> A_IWL<2779> A_IWL<2778> A_IWL<2777> A_IWL<2776> A_IWL<2775> A_IWL<2774> A_IWL<2773> A_IWL<2772> A_IWL<2771> A_IWL<2770> A_IWL<2769> A_IWL<2768> A_IWL<2767> A_IWL<2766> A_IWL<2765> A_IWL<2764> A_IWL<2763> A_IWL<2762> A_IWL<2761> A_IWL<2760> A_IWL<2759> A_IWL<2758> A_IWL<2757> A_IWL<2756> A_IWL<2755> A_IWL<2754> A_IWL<2753> A_IWL<2752> A_IWL<2751> A_IWL<2750> A_IWL<2749> A_IWL<2748> A_IWL<2747> A_IWL<2746> A_IWL<2745> A_IWL<2744> A_IWL<2743> A_IWL<2742> A_IWL<2741> A_IWL<2740> A_IWL<2739> A_IWL<2738> A_IWL<2737> A_IWL<2736> A_IWL<2735> A_IWL<2734> A_IWL<2733> A_IWL<2732> A_IWL<2731> A_IWL<2730> A_IWL<2729> A_IWL<2728> A_IWL<2727> A_IWL<2726> A_IWL<2725> A_IWL<2724> A_IWL<2723> A_IWL<2722> A_IWL<2721> A_IWL<2720> A_IWL<2719> A_IWL<2718> A_IWL<2717> A_IWL<2716> A_IWL<2715> A_IWL<2714> A_IWL<2713> A_IWL<2712> A_IWL<2711> A_IWL<2710> A_IWL<2709> A_IWL<2708> A_IWL<2707> A_IWL<2706> A_IWL<2705> A_IWL<2704> A_IWL<2703> A_IWL<2702> A_IWL<2701> A_IWL<2700> A_IWL<2699> A_IWL<2698> A_IWL<2697> A_IWL<2696> A_IWL<2695> A_IWL<2694> A_IWL<2693> A_IWL<2692> A_IWL<2691> A_IWL<2690> A_IWL<2689> A_IWL<2688> A_IWL<2687> A_IWL<2686> A_IWL<2685> A_IWL<2684> A_IWL<2683> A_IWL<2682> A_IWL<2681> A_IWL<2680> A_IWL<2679> A_IWL<2678> A_IWL<2677> A_IWL<2676> A_IWL<2675> A_IWL<2674> A_IWL<2673> A_IWL<2672> A_IWL<2671> A_IWL<2670> A_IWL<2669> A_IWL<2668> A_IWL<2667> A_IWL<2666> A_IWL<2665> A_IWL<2664> A_IWL<2663> A_IWL<2662> A_IWL<2661> A_IWL<2660> A_IWL<2659> A_IWL<2658> A_IWL<2657> A_IWL<2656> A_IWL<2655> A_IWL<2654> A_IWL<2653> A_IWL<2652> A_IWL<2651> A_IWL<2650> A_IWL<2649> A_IWL<2648> A_IWL<2647> A_IWL<2646> A_IWL<2645> A_IWL<2644> A_IWL<2643> A_IWL<2642> A_IWL<2641> A_IWL<2640> A_IWL<2639> A_IWL<2638> A_IWL<2637> A_IWL<2636> A_IWL<2635> A_IWL<2634> A_IWL<2633> A_IWL<2632> A_IWL<2631> A_IWL<2630> A_IWL<2629> A_IWL<2628> A_IWL<2627> A_IWL<2626> A_IWL<2625> A_IWL<2624> A_IWL<2623> A_IWL<2622> A_IWL<2621> A_IWL<2620> A_IWL<2619> A_IWL<2618> A_IWL<2617> A_IWL<2616> A_IWL<2615> A_IWL<2614> A_IWL<2613> A_IWL<2612> A_IWL<2611> A_IWL<2610> A_IWL<2609> A_IWL<2608> A_IWL<2607> A_IWL<2606> A_IWL<2605> A_IWL<2604> A_IWL<2603> A_IWL<2602> A_IWL<2601> A_IWL<2600> A_IWL<2599> A_IWL<2598> A_IWL<2597> A_IWL<2596> A_IWL<2595> A_IWL<2594> A_IWL<2593> A_IWL<2592> A_IWL<2591> A_IWL<2590> A_IWL<2589> A_IWL<2588> A_IWL<2587> A_IWL<2586> A_IWL<2585> A_IWL<2584> A_IWL<2583> A_IWL<2582> A_IWL<2581> A_IWL<2580> A_IWL<2579> A_IWL<2578> A_IWL<2577> A_IWL<2576> A_IWL<2575> A_IWL<2574> A_IWL<2573> A_IWL<2572> A_IWL<2571> A_IWL<2570> A_IWL<2569> A_IWL<2568> A_IWL<2567> A_IWL<2566> A_IWL<2565> A_IWL<2564> A_IWL<2563> A_IWL<2562> A_IWL<2561> A_IWL<2560> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_COLUMN_pcell_0
+XCOL<9> A_BLC<19> A_BLC<18> A_BLC_TOP<19> A_BLC_TOP<18> A_BLT<19> A_BLT<18> A_BLT_TOP<19> A_BLT_TOP<18> A_IWL<2303> A_IWL<2302> A_IWL<2301> A_IWL<2300> A_IWL<2299> A_IWL<2298> A_IWL<2297> A_IWL<2296> A_IWL<2295> A_IWL<2294> A_IWL<2293> A_IWL<2292> A_IWL<2291> A_IWL<2290> A_IWL<2289> A_IWL<2288> A_IWL<2287> A_IWL<2286> A_IWL<2285> A_IWL<2284> A_IWL<2283> A_IWL<2282> A_IWL<2281> A_IWL<2280> A_IWL<2279> A_IWL<2278> A_IWL<2277> A_IWL<2276> A_IWL<2275> A_IWL<2274> A_IWL<2273> A_IWL<2272> A_IWL<2271> A_IWL<2270> A_IWL<2269> A_IWL<2268> A_IWL<2267> A_IWL<2266> A_IWL<2265> A_IWL<2264> A_IWL<2263> A_IWL<2262> A_IWL<2261> A_IWL<2260> A_IWL<2259> A_IWL<2258> A_IWL<2257> A_IWL<2256> A_IWL<2255> A_IWL<2254> A_IWL<2253> A_IWL<2252> A_IWL<2251> A_IWL<2250> A_IWL<2249> A_IWL<2248> A_IWL<2247> A_IWL<2246> A_IWL<2245> A_IWL<2244> A_IWL<2243> A_IWL<2242> A_IWL<2241> A_IWL<2240> A_IWL<2239> A_IWL<2238> A_IWL<2237> A_IWL<2236> A_IWL<2235> A_IWL<2234> A_IWL<2233> A_IWL<2232> A_IWL<2231> A_IWL<2230> A_IWL<2229> A_IWL<2228> A_IWL<2227> A_IWL<2226> A_IWL<2225> A_IWL<2224> A_IWL<2223> A_IWL<2222> A_IWL<2221> A_IWL<2220> A_IWL<2219> A_IWL<2218> A_IWL<2217> A_IWL<2216> A_IWL<2215> A_IWL<2214> A_IWL<2213> A_IWL<2212> A_IWL<2211> A_IWL<2210> A_IWL<2209> A_IWL<2208> A_IWL<2207> A_IWL<2206> A_IWL<2205> A_IWL<2204> A_IWL<2203> A_IWL<2202> A_IWL<2201> A_IWL<2200> A_IWL<2199> A_IWL<2198> A_IWL<2197> A_IWL<2196> A_IWL<2195> A_IWL<2194> A_IWL<2193> A_IWL<2192> A_IWL<2191> A_IWL<2190> A_IWL<2189> A_IWL<2188> A_IWL<2187> A_IWL<2186> A_IWL<2185> A_IWL<2184> A_IWL<2183> A_IWL<2182> A_IWL<2181> A_IWL<2180> A_IWL<2179> A_IWL<2178> A_IWL<2177> A_IWL<2176> A_IWL<2175> A_IWL<2174> A_IWL<2173> A_IWL<2172> A_IWL<2171> A_IWL<2170> A_IWL<2169> A_IWL<2168> A_IWL<2167> A_IWL<2166> A_IWL<2165> A_IWL<2164> A_IWL<2163> A_IWL<2162> A_IWL<2161> A_IWL<2160> A_IWL<2159> A_IWL<2158> A_IWL<2157> A_IWL<2156> A_IWL<2155> A_IWL<2154> A_IWL<2153> A_IWL<2152> A_IWL<2151> A_IWL<2150> A_IWL<2149> A_IWL<2148> A_IWL<2147> A_IWL<2146> A_IWL<2145> A_IWL<2144> A_IWL<2143> A_IWL<2142> A_IWL<2141> A_IWL<2140> A_IWL<2139> A_IWL<2138> A_IWL<2137> A_IWL<2136> A_IWL<2135> A_IWL<2134> A_IWL<2133> A_IWL<2132> A_IWL<2131> A_IWL<2130> A_IWL<2129> A_IWL<2128> A_IWL<2127> A_IWL<2126> A_IWL<2125> A_IWL<2124> A_IWL<2123> A_IWL<2122> A_IWL<2121> A_IWL<2120> A_IWL<2119> A_IWL<2118> A_IWL<2117> A_IWL<2116> A_IWL<2115> A_IWL<2114> A_IWL<2113> A_IWL<2112> A_IWL<2111> A_IWL<2110> A_IWL<2109> A_IWL<2108> A_IWL<2107> A_IWL<2106> A_IWL<2105> A_IWL<2104> A_IWL<2103> A_IWL<2102> A_IWL<2101> A_IWL<2100> A_IWL<2099> A_IWL<2098> A_IWL<2097> A_IWL<2096> A_IWL<2095> A_IWL<2094> A_IWL<2093> A_IWL<2092> A_IWL<2091> A_IWL<2090> A_IWL<2089> A_IWL<2088> A_IWL<2087> A_IWL<2086> A_IWL<2085> A_IWL<2084> A_IWL<2083> A_IWL<2082> A_IWL<2081> A_IWL<2080> A_IWL<2079> A_IWL<2078> A_IWL<2077> A_IWL<2076> A_IWL<2075> A_IWL<2074> A_IWL<2073> A_IWL<2072> A_IWL<2071> A_IWL<2070> A_IWL<2069> A_IWL<2068> A_IWL<2067> A_IWL<2066> A_IWL<2065> A_IWL<2064> A_IWL<2063> A_IWL<2062> A_IWL<2061> A_IWL<2060> A_IWL<2059> A_IWL<2058> A_IWL<2057> A_IWL<2056> A_IWL<2055> A_IWL<2054> A_IWL<2053> A_IWL<2052> A_IWL<2051> A_IWL<2050> A_IWL<2049> A_IWL<2048> A_IWL<2559> A_IWL<2558> A_IWL<2557> A_IWL<2556> A_IWL<2555> A_IWL<2554> A_IWL<2553> A_IWL<2552> A_IWL<2551> A_IWL<2550> A_IWL<2549> A_IWL<2548> A_IWL<2547> A_IWL<2546> A_IWL<2545> A_IWL<2544> A_IWL<2543> A_IWL<2542> A_IWL<2541> A_IWL<2540> A_IWL<2539> A_IWL<2538> A_IWL<2537> A_IWL<2536> A_IWL<2535> A_IWL<2534> A_IWL<2533> A_IWL<2532> A_IWL<2531> A_IWL<2530> A_IWL<2529> A_IWL<2528> A_IWL<2527> A_IWL<2526> A_IWL<2525> A_IWL<2524> A_IWL<2523> A_IWL<2522> A_IWL<2521> A_IWL<2520> A_IWL<2519> A_IWL<2518> A_IWL<2517> A_IWL<2516> A_IWL<2515> A_IWL<2514> A_IWL<2513> A_IWL<2512> A_IWL<2511> A_IWL<2510> A_IWL<2509> A_IWL<2508> A_IWL<2507> A_IWL<2506> A_IWL<2505> A_IWL<2504> A_IWL<2503> A_IWL<2502> A_IWL<2501> A_IWL<2500> A_IWL<2499> A_IWL<2498> A_IWL<2497> A_IWL<2496> A_IWL<2495> A_IWL<2494> A_IWL<2493> A_IWL<2492> A_IWL<2491> A_IWL<2490> A_IWL<2489> A_IWL<2488> A_IWL<2487> A_IWL<2486> A_IWL<2485> A_IWL<2484> A_IWL<2483> A_IWL<2482> A_IWL<2481> A_IWL<2480> A_IWL<2479> A_IWL<2478> A_IWL<2477> A_IWL<2476> A_IWL<2475> A_IWL<2474> A_IWL<2473> A_IWL<2472> A_IWL<2471> A_IWL<2470> A_IWL<2469> A_IWL<2468> A_IWL<2467> A_IWL<2466> A_IWL<2465> A_IWL<2464> A_IWL<2463> A_IWL<2462> A_IWL<2461> A_IWL<2460> A_IWL<2459> A_IWL<2458> A_IWL<2457> A_IWL<2456> A_IWL<2455> A_IWL<2454> A_IWL<2453> A_IWL<2452> A_IWL<2451> A_IWL<2450> A_IWL<2449> A_IWL<2448> A_IWL<2447> A_IWL<2446> A_IWL<2445> A_IWL<2444> A_IWL<2443> A_IWL<2442> A_IWL<2441> A_IWL<2440> A_IWL<2439> A_IWL<2438> A_IWL<2437> A_IWL<2436> A_IWL<2435> A_IWL<2434> A_IWL<2433> A_IWL<2432> A_IWL<2431> A_IWL<2430> A_IWL<2429> A_IWL<2428> A_IWL<2427> A_IWL<2426> A_IWL<2425> A_IWL<2424> A_IWL<2423> A_IWL<2422> A_IWL<2421> A_IWL<2420> A_IWL<2419> A_IWL<2418> A_IWL<2417> A_IWL<2416> A_IWL<2415> A_IWL<2414> A_IWL<2413> A_IWL<2412> A_IWL<2411> A_IWL<2410> A_IWL<2409> A_IWL<2408> A_IWL<2407> A_IWL<2406> A_IWL<2405> A_IWL<2404> A_IWL<2403> A_IWL<2402> A_IWL<2401> A_IWL<2400> A_IWL<2399> A_IWL<2398> A_IWL<2397> A_IWL<2396> A_IWL<2395> A_IWL<2394> A_IWL<2393> A_IWL<2392> A_IWL<2391> A_IWL<2390> A_IWL<2389> A_IWL<2388> A_IWL<2387> A_IWL<2386> A_IWL<2385> A_IWL<2384> A_IWL<2383> A_IWL<2382> A_IWL<2381> A_IWL<2380> A_IWL<2379> A_IWL<2378> A_IWL<2377> A_IWL<2376> A_IWL<2375> A_IWL<2374> A_IWL<2373> A_IWL<2372> A_IWL<2371> A_IWL<2370> A_IWL<2369> A_IWL<2368> A_IWL<2367> A_IWL<2366> A_IWL<2365> A_IWL<2364> A_IWL<2363> A_IWL<2362> A_IWL<2361> A_IWL<2360> A_IWL<2359> A_IWL<2358> A_IWL<2357> A_IWL<2356> A_IWL<2355> A_IWL<2354> A_IWL<2353> A_IWL<2352> A_IWL<2351> A_IWL<2350> A_IWL<2349> A_IWL<2348> A_IWL<2347> A_IWL<2346> A_IWL<2345> A_IWL<2344> A_IWL<2343> A_IWL<2342> A_IWL<2341> A_IWL<2340> A_IWL<2339> A_IWL<2338> A_IWL<2337> A_IWL<2336> A_IWL<2335> A_IWL<2334> A_IWL<2333> A_IWL<2332> A_IWL<2331> A_IWL<2330> A_IWL<2329> A_IWL<2328> A_IWL<2327> A_IWL<2326> A_IWL<2325> A_IWL<2324> A_IWL<2323> A_IWL<2322> A_IWL<2321> A_IWL<2320> A_IWL<2319> A_IWL<2318> A_IWL<2317> A_IWL<2316> A_IWL<2315> A_IWL<2314> A_IWL<2313> A_IWL<2312> A_IWL<2311> A_IWL<2310> A_IWL<2309> A_IWL<2308> A_IWL<2307> A_IWL<2306> A_IWL<2305> A_IWL<2304> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_COLUMN_pcell_0
+XCOL<8> A_BLC<17> A_BLC<16> A_BLC_TOP<17> A_BLC_TOP<16> A_BLT<17> A_BLT<16> A_BLT_TOP<17> A_BLT_TOP<16> A_IWL<2047> A_IWL<2046> A_IWL<2045> A_IWL<2044> A_IWL<2043> A_IWL<2042> A_IWL<2041> A_IWL<2040> A_IWL<2039> A_IWL<2038> A_IWL<2037> A_IWL<2036> A_IWL<2035> A_IWL<2034> A_IWL<2033> A_IWL<2032> A_IWL<2031> A_IWL<2030> A_IWL<2029> A_IWL<2028> A_IWL<2027> A_IWL<2026> A_IWL<2025> A_IWL<2024> A_IWL<2023> A_IWL<2022> A_IWL<2021> A_IWL<2020> A_IWL<2019> A_IWL<2018> A_IWL<2017> A_IWL<2016> A_IWL<2015> A_IWL<2014> A_IWL<2013> A_IWL<2012> A_IWL<2011> A_IWL<2010> A_IWL<2009> A_IWL<2008> A_IWL<2007> A_IWL<2006> A_IWL<2005> A_IWL<2004> A_IWL<2003> A_IWL<2002> A_IWL<2001> A_IWL<2000> A_IWL<1999> A_IWL<1998> A_IWL<1997> A_IWL<1996> A_IWL<1995> A_IWL<1994> A_IWL<1993> A_IWL<1992> A_IWL<1991> A_IWL<1990> A_IWL<1989> A_IWL<1988> A_IWL<1987> A_IWL<1986> A_IWL<1985> A_IWL<1984> A_IWL<1983> A_IWL<1982> A_IWL<1981> A_IWL<1980> A_IWL<1979> A_IWL<1978> A_IWL<1977> A_IWL<1976> A_IWL<1975> A_IWL<1974> A_IWL<1973> A_IWL<1972> A_IWL<1971> A_IWL<1970> A_IWL<1969> A_IWL<1968> A_IWL<1967> A_IWL<1966> A_IWL<1965> A_IWL<1964> A_IWL<1963> A_IWL<1962> A_IWL<1961> A_IWL<1960> A_IWL<1959> A_IWL<1958> A_IWL<1957> A_IWL<1956> A_IWL<1955> A_IWL<1954> A_IWL<1953> A_IWL<1952> A_IWL<1951> A_IWL<1950> A_IWL<1949> A_IWL<1948> A_IWL<1947> A_IWL<1946> A_IWL<1945> A_IWL<1944> A_IWL<1943> A_IWL<1942> A_IWL<1941> A_IWL<1940> A_IWL<1939> A_IWL<1938> A_IWL<1937> A_IWL<1936> A_IWL<1935> A_IWL<1934> A_IWL<1933> A_IWL<1932> A_IWL<1931> A_IWL<1930> A_IWL<1929> A_IWL<1928> A_IWL<1927> A_IWL<1926> A_IWL<1925> A_IWL<1924> A_IWL<1923> A_IWL<1922> A_IWL<1921> A_IWL<1920> A_IWL<1919> A_IWL<1918> A_IWL<1917> A_IWL<1916> A_IWL<1915> A_IWL<1914> A_IWL<1913> A_IWL<1912> A_IWL<1911> A_IWL<1910> A_IWL<1909> A_IWL<1908> A_IWL<1907> A_IWL<1906> A_IWL<1905> A_IWL<1904> A_IWL<1903> A_IWL<1902> A_IWL<1901> A_IWL<1900> A_IWL<1899> A_IWL<1898> A_IWL<1897> A_IWL<1896> A_IWL<1895> A_IWL<1894> A_IWL<1893> A_IWL<1892> A_IWL<1891> A_IWL<1890> A_IWL<1889> A_IWL<1888> A_IWL<1887> A_IWL<1886> A_IWL<1885> A_IWL<1884> A_IWL<1883> A_IWL<1882> A_IWL<1881> A_IWL<1880> A_IWL<1879> A_IWL<1878> A_IWL<1877> A_IWL<1876> A_IWL<1875> A_IWL<1874> A_IWL<1873> A_IWL<1872> A_IWL<1871> A_IWL<1870> A_IWL<1869> A_IWL<1868> A_IWL<1867> A_IWL<1866> A_IWL<1865> A_IWL<1864> A_IWL<1863> A_IWL<1862> A_IWL<1861> A_IWL<1860> A_IWL<1859> A_IWL<1858> A_IWL<1857> A_IWL<1856> A_IWL<1855> A_IWL<1854> A_IWL<1853> A_IWL<1852> A_IWL<1851> A_IWL<1850> A_IWL<1849> A_IWL<1848> A_IWL<1847> A_IWL<1846> A_IWL<1845> A_IWL<1844> A_IWL<1843> A_IWL<1842> A_IWL<1841> A_IWL<1840> A_IWL<1839> A_IWL<1838> A_IWL<1837> A_IWL<1836> A_IWL<1835> A_IWL<1834> A_IWL<1833> A_IWL<1832> A_IWL<1831> A_IWL<1830> A_IWL<1829> A_IWL<1828> A_IWL<1827> A_IWL<1826> A_IWL<1825> A_IWL<1824> A_IWL<1823> A_IWL<1822> A_IWL<1821> A_IWL<1820> A_IWL<1819> A_IWL<1818> A_IWL<1817> A_IWL<1816> A_IWL<1815> A_IWL<1814> A_IWL<1813> A_IWL<1812> A_IWL<1811> A_IWL<1810> A_IWL<1809> A_IWL<1808> A_IWL<1807> A_IWL<1806> A_IWL<1805> A_IWL<1804> A_IWL<1803> A_IWL<1802> A_IWL<1801> A_IWL<1800> A_IWL<1799> A_IWL<1798> A_IWL<1797> A_IWL<1796> A_IWL<1795> A_IWL<1794> A_IWL<1793> A_IWL<1792> A_IWL<2303> A_IWL<2302> A_IWL<2301> A_IWL<2300> A_IWL<2299> A_IWL<2298> A_IWL<2297> A_IWL<2296> A_IWL<2295> A_IWL<2294> A_IWL<2293> A_IWL<2292> A_IWL<2291> A_IWL<2290> A_IWL<2289> A_IWL<2288> A_IWL<2287> A_IWL<2286> A_IWL<2285> A_IWL<2284> A_IWL<2283> A_IWL<2282> A_IWL<2281> A_IWL<2280> A_IWL<2279> A_IWL<2278> A_IWL<2277> A_IWL<2276> A_IWL<2275> A_IWL<2274> A_IWL<2273> A_IWL<2272> A_IWL<2271> A_IWL<2270> A_IWL<2269> A_IWL<2268> A_IWL<2267> A_IWL<2266> A_IWL<2265> A_IWL<2264> A_IWL<2263> A_IWL<2262> A_IWL<2261> A_IWL<2260> A_IWL<2259> A_IWL<2258> A_IWL<2257> A_IWL<2256> A_IWL<2255> A_IWL<2254> A_IWL<2253> A_IWL<2252> A_IWL<2251> A_IWL<2250> A_IWL<2249> A_IWL<2248> A_IWL<2247> A_IWL<2246> A_IWL<2245> A_IWL<2244> A_IWL<2243> A_IWL<2242> A_IWL<2241> A_IWL<2240> A_IWL<2239> A_IWL<2238> A_IWL<2237> A_IWL<2236> A_IWL<2235> A_IWL<2234> A_IWL<2233> A_IWL<2232> A_IWL<2231> A_IWL<2230> A_IWL<2229> A_IWL<2228> A_IWL<2227> A_IWL<2226> A_IWL<2225> A_IWL<2224> A_IWL<2223> A_IWL<2222> A_IWL<2221> A_IWL<2220> A_IWL<2219> A_IWL<2218> A_IWL<2217> A_IWL<2216> A_IWL<2215> A_IWL<2214> A_IWL<2213> A_IWL<2212> A_IWL<2211> A_IWL<2210> A_IWL<2209> A_IWL<2208> A_IWL<2207> A_IWL<2206> A_IWL<2205> A_IWL<2204> A_IWL<2203> A_IWL<2202> A_IWL<2201> A_IWL<2200> A_IWL<2199> A_IWL<2198> A_IWL<2197> A_IWL<2196> A_IWL<2195> A_IWL<2194> A_IWL<2193> A_IWL<2192> A_IWL<2191> A_IWL<2190> A_IWL<2189> A_IWL<2188> A_IWL<2187> A_IWL<2186> A_IWL<2185> A_IWL<2184> A_IWL<2183> A_IWL<2182> A_IWL<2181> A_IWL<2180> A_IWL<2179> A_IWL<2178> A_IWL<2177> A_IWL<2176> A_IWL<2175> A_IWL<2174> A_IWL<2173> A_IWL<2172> A_IWL<2171> A_IWL<2170> A_IWL<2169> A_IWL<2168> A_IWL<2167> A_IWL<2166> A_IWL<2165> A_IWL<2164> A_IWL<2163> A_IWL<2162> A_IWL<2161> A_IWL<2160> A_IWL<2159> A_IWL<2158> A_IWL<2157> A_IWL<2156> A_IWL<2155> A_IWL<2154> A_IWL<2153> A_IWL<2152> A_IWL<2151> A_IWL<2150> A_IWL<2149> A_IWL<2148> A_IWL<2147> A_IWL<2146> A_IWL<2145> A_IWL<2144> A_IWL<2143> A_IWL<2142> A_IWL<2141> A_IWL<2140> A_IWL<2139> A_IWL<2138> A_IWL<2137> A_IWL<2136> A_IWL<2135> A_IWL<2134> A_IWL<2133> A_IWL<2132> A_IWL<2131> A_IWL<2130> A_IWL<2129> A_IWL<2128> A_IWL<2127> A_IWL<2126> A_IWL<2125> A_IWL<2124> A_IWL<2123> A_IWL<2122> A_IWL<2121> A_IWL<2120> A_IWL<2119> A_IWL<2118> A_IWL<2117> A_IWL<2116> A_IWL<2115> A_IWL<2114> A_IWL<2113> A_IWL<2112> A_IWL<2111> A_IWL<2110> A_IWL<2109> A_IWL<2108> A_IWL<2107> A_IWL<2106> A_IWL<2105> A_IWL<2104> A_IWL<2103> A_IWL<2102> A_IWL<2101> A_IWL<2100> A_IWL<2099> A_IWL<2098> A_IWL<2097> A_IWL<2096> A_IWL<2095> A_IWL<2094> A_IWL<2093> A_IWL<2092> A_IWL<2091> A_IWL<2090> A_IWL<2089> A_IWL<2088> A_IWL<2087> A_IWL<2086> A_IWL<2085> A_IWL<2084> A_IWL<2083> A_IWL<2082> A_IWL<2081> A_IWL<2080> A_IWL<2079> A_IWL<2078> A_IWL<2077> A_IWL<2076> A_IWL<2075> A_IWL<2074> A_IWL<2073> A_IWL<2072> A_IWL<2071> A_IWL<2070> A_IWL<2069> A_IWL<2068> A_IWL<2067> A_IWL<2066> A_IWL<2065> A_IWL<2064> A_IWL<2063> A_IWL<2062> A_IWL<2061> A_IWL<2060> A_IWL<2059> A_IWL<2058> A_IWL<2057> A_IWL<2056> A_IWL<2055> A_IWL<2054> A_IWL<2053> A_IWL<2052> A_IWL<2051> A_IWL<2050> A_IWL<2049> A_IWL<2048> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_COLUMN_pcell_0
+XCOL<7> A_BLC<15> A_BLC<14> A_BLC_TOP<15> A_BLC_TOP<14> A_BLT<15> A_BLT<14> A_BLT_TOP<15> A_BLT_TOP<14> A_IWL<1791> A_IWL<1790> A_IWL<1789> A_IWL<1788> A_IWL<1787> A_IWL<1786> A_IWL<1785> A_IWL<1784> A_IWL<1783> A_IWL<1782> A_IWL<1781> A_IWL<1780> A_IWL<1779> A_IWL<1778> A_IWL<1777> A_IWL<1776> A_IWL<1775> A_IWL<1774> A_IWL<1773> A_IWL<1772> A_IWL<1771> A_IWL<1770> A_IWL<1769> A_IWL<1768> A_IWL<1767> A_IWL<1766> A_IWL<1765> A_IWL<1764> A_IWL<1763> A_IWL<1762> A_IWL<1761> A_IWL<1760> A_IWL<1759> A_IWL<1758> A_IWL<1757> A_IWL<1756> A_IWL<1755> A_IWL<1754> A_IWL<1753> A_IWL<1752> A_IWL<1751> A_IWL<1750> A_IWL<1749> A_IWL<1748> A_IWL<1747> A_IWL<1746> A_IWL<1745> A_IWL<1744> A_IWL<1743> A_IWL<1742> A_IWL<1741> A_IWL<1740> A_IWL<1739> A_IWL<1738> A_IWL<1737> A_IWL<1736> A_IWL<1735> A_IWL<1734> A_IWL<1733> A_IWL<1732> A_IWL<1731> A_IWL<1730> A_IWL<1729> A_IWL<1728> A_IWL<1727> A_IWL<1726> A_IWL<1725> A_IWL<1724> A_IWL<1723> A_IWL<1722> A_IWL<1721> A_IWL<1720> A_IWL<1719> A_IWL<1718> A_IWL<1717> A_IWL<1716> A_IWL<1715> A_IWL<1714> A_IWL<1713> A_IWL<1712> A_IWL<1711> A_IWL<1710> A_IWL<1709> A_IWL<1708> A_IWL<1707> A_IWL<1706> A_IWL<1705> A_IWL<1704> A_IWL<1703> A_IWL<1702> A_IWL<1701> A_IWL<1700> A_IWL<1699> A_IWL<1698> A_IWL<1697> A_IWL<1696> A_IWL<1695> A_IWL<1694> A_IWL<1693> A_IWL<1692> A_IWL<1691> A_IWL<1690> A_IWL<1689> A_IWL<1688> A_IWL<1687> A_IWL<1686> A_IWL<1685> A_IWL<1684> A_IWL<1683> A_IWL<1682> A_IWL<1681> A_IWL<1680> A_IWL<1679> A_IWL<1678> A_IWL<1677> A_IWL<1676> A_IWL<1675> A_IWL<1674> A_IWL<1673> A_IWL<1672> A_IWL<1671> A_IWL<1670> A_IWL<1669> A_IWL<1668> A_IWL<1667> A_IWL<1666> A_IWL<1665> A_IWL<1664> A_IWL<1663> A_IWL<1662> A_IWL<1661> A_IWL<1660> A_IWL<1659> A_IWL<1658> A_IWL<1657> A_IWL<1656> A_IWL<1655> A_IWL<1654> A_IWL<1653> A_IWL<1652> A_IWL<1651> A_IWL<1650> A_IWL<1649> A_IWL<1648> A_IWL<1647> A_IWL<1646> A_IWL<1645> A_IWL<1644> A_IWL<1643> A_IWL<1642> A_IWL<1641> A_IWL<1640> A_IWL<1639> A_IWL<1638> A_IWL<1637> A_IWL<1636> A_IWL<1635> A_IWL<1634> A_IWL<1633> A_IWL<1632> A_IWL<1631> A_IWL<1630> A_IWL<1629> A_IWL<1628> A_IWL<1627> A_IWL<1626> A_IWL<1625> A_IWL<1624> A_IWL<1623> A_IWL<1622> A_IWL<1621> A_IWL<1620> A_IWL<1619> A_IWL<1618> A_IWL<1617> A_IWL<1616> A_IWL<1615> A_IWL<1614> A_IWL<1613> A_IWL<1612> A_IWL<1611> A_IWL<1610> A_IWL<1609> A_IWL<1608> A_IWL<1607> A_IWL<1606> A_IWL<1605> A_IWL<1604> A_IWL<1603> A_IWL<1602> A_IWL<1601> A_IWL<1600> A_IWL<1599> A_IWL<1598> A_IWL<1597> A_IWL<1596> A_IWL<1595> A_IWL<1594> A_IWL<1593> A_IWL<1592> A_IWL<1591> A_IWL<1590> A_IWL<1589> A_IWL<1588> A_IWL<1587> A_IWL<1586> A_IWL<1585> A_IWL<1584> A_IWL<1583> A_IWL<1582> A_IWL<1581> A_IWL<1580> A_IWL<1579> A_IWL<1578> A_IWL<1577> A_IWL<1576> A_IWL<1575> A_IWL<1574> A_IWL<1573> A_IWL<1572> A_IWL<1571> A_IWL<1570> A_IWL<1569> A_IWL<1568> A_IWL<1567> A_IWL<1566> A_IWL<1565> A_IWL<1564> A_IWL<1563> A_IWL<1562> A_IWL<1561> A_IWL<1560> A_IWL<1559> A_IWL<1558> A_IWL<1557> A_IWL<1556> A_IWL<1555> A_IWL<1554> A_IWL<1553> A_IWL<1552> A_IWL<1551> A_IWL<1550> A_IWL<1549> A_IWL<1548> A_IWL<1547> A_IWL<1546> A_IWL<1545> A_IWL<1544> A_IWL<1543> A_IWL<1542> A_IWL<1541> A_IWL<1540> A_IWL<1539> A_IWL<1538> A_IWL<1537> A_IWL<1536> A_IWL<2047> A_IWL<2046> A_IWL<2045> A_IWL<2044> A_IWL<2043> A_IWL<2042> A_IWL<2041> A_IWL<2040> A_IWL<2039> A_IWL<2038> A_IWL<2037> A_IWL<2036> A_IWL<2035> A_IWL<2034> A_IWL<2033> A_IWL<2032> A_IWL<2031> A_IWL<2030> A_IWL<2029> A_IWL<2028> A_IWL<2027> A_IWL<2026> A_IWL<2025> A_IWL<2024> A_IWL<2023> A_IWL<2022> A_IWL<2021> A_IWL<2020> A_IWL<2019> A_IWL<2018> A_IWL<2017> A_IWL<2016> A_IWL<2015> A_IWL<2014> A_IWL<2013> A_IWL<2012> A_IWL<2011> A_IWL<2010> A_IWL<2009> A_IWL<2008> A_IWL<2007> A_IWL<2006> A_IWL<2005> A_IWL<2004> A_IWL<2003> A_IWL<2002> A_IWL<2001> A_IWL<2000> A_IWL<1999> A_IWL<1998> A_IWL<1997> A_IWL<1996> A_IWL<1995> A_IWL<1994> A_IWL<1993> A_IWL<1992> A_IWL<1991> A_IWL<1990> A_IWL<1989> A_IWL<1988> A_IWL<1987> A_IWL<1986> A_IWL<1985> A_IWL<1984> A_IWL<1983> A_IWL<1982> A_IWL<1981> A_IWL<1980> A_IWL<1979> A_IWL<1978> A_IWL<1977> A_IWL<1976> A_IWL<1975> A_IWL<1974> A_IWL<1973> A_IWL<1972> A_IWL<1971> A_IWL<1970> A_IWL<1969> A_IWL<1968> A_IWL<1967> A_IWL<1966> A_IWL<1965> A_IWL<1964> A_IWL<1963> A_IWL<1962> A_IWL<1961> A_IWL<1960> A_IWL<1959> A_IWL<1958> A_IWL<1957> A_IWL<1956> A_IWL<1955> A_IWL<1954> A_IWL<1953> A_IWL<1952> A_IWL<1951> A_IWL<1950> A_IWL<1949> A_IWL<1948> A_IWL<1947> A_IWL<1946> A_IWL<1945> A_IWL<1944> A_IWL<1943> A_IWL<1942> A_IWL<1941> A_IWL<1940> A_IWL<1939> A_IWL<1938> A_IWL<1937> A_IWL<1936> A_IWL<1935> A_IWL<1934> A_IWL<1933> A_IWL<1932> A_IWL<1931> A_IWL<1930> A_IWL<1929> A_IWL<1928> A_IWL<1927> A_IWL<1926> A_IWL<1925> A_IWL<1924> A_IWL<1923> A_IWL<1922> A_IWL<1921> A_IWL<1920> A_IWL<1919> A_IWL<1918> A_IWL<1917> A_IWL<1916> A_IWL<1915> A_IWL<1914> A_IWL<1913> A_IWL<1912> A_IWL<1911> A_IWL<1910> A_IWL<1909> A_IWL<1908> A_IWL<1907> A_IWL<1906> A_IWL<1905> A_IWL<1904> A_IWL<1903> A_IWL<1902> A_IWL<1901> A_IWL<1900> A_IWL<1899> A_IWL<1898> A_IWL<1897> A_IWL<1896> A_IWL<1895> A_IWL<1894> A_IWL<1893> A_IWL<1892> A_IWL<1891> A_IWL<1890> A_IWL<1889> A_IWL<1888> A_IWL<1887> A_IWL<1886> A_IWL<1885> A_IWL<1884> A_IWL<1883> A_IWL<1882> A_IWL<1881> A_IWL<1880> A_IWL<1879> A_IWL<1878> A_IWL<1877> A_IWL<1876> A_IWL<1875> A_IWL<1874> A_IWL<1873> A_IWL<1872> A_IWL<1871> A_IWL<1870> A_IWL<1869> A_IWL<1868> A_IWL<1867> A_IWL<1866> A_IWL<1865> A_IWL<1864> A_IWL<1863> A_IWL<1862> A_IWL<1861> A_IWL<1860> A_IWL<1859> A_IWL<1858> A_IWL<1857> A_IWL<1856> A_IWL<1855> A_IWL<1854> A_IWL<1853> A_IWL<1852> A_IWL<1851> A_IWL<1850> A_IWL<1849> A_IWL<1848> A_IWL<1847> A_IWL<1846> A_IWL<1845> A_IWL<1844> A_IWL<1843> A_IWL<1842> A_IWL<1841> A_IWL<1840> A_IWL<1839> A_IWL<1838> A_IWL<1837> A_IWL<1836> A_IWL<1835> A_IWL<1834> A_IWL<1833> A_IWL<1832> A_IWL<1831> A_IWL<1830> A_IWL<1829> A_IWL<1828> A_IWL<1827> A_IWL<1826> A_IWL<1825> A_IWL<1824> A_IWL<1823> A_IWL<1822> A_IWL<1821> A_IWL<1820> A_IWL<1819> A_IWL<1818> A_IWL<1817> A_IWL<1816> A_IWL<1815> A_IWL<1814> A_IWL<1813> A_IWL<1812> A_IWL<1811> A_IWL<1810> A_IWL<1809> A_IWL<1808> A_IWL<1807> A_IWL<1806> A_IWL<1805> A_IWL<1804> A_IWL<1803> A_IWL<1802> A_IWL<1801> A_IWL<1800> A_IWL<1799> A_IWL<1798> A_IWL<1797> A_IWL<1796> A_IWL<1795> A_IWL<1794> A_IWL<1793> A_IWL<1792> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_COLUMN_pcell_0
+XCOL<6> A_BLC<13> A_BLC<12> A_BLC_TOP<13> A_BLC_TOP<12> A_BLT<13> A_BLT<12> A_BLT_TOP<13> A_BLT_TOP<12> A_IWL<1535> A_IWL<1534> A_IWL<1533> A_IWL<1532> A_IWL<1531> A_IWL<1530> A_IWL<1529> A_IWL<1528> A_IWL<1527> A_IWL<1526> A_IWL<1525> A_IWL<1524> A_IWL<1523> A_IWL<1522> A_IWL<1521> A_IWL<1520> A_IWL<1519> A_IWL<1518> A_IWL<1517> A_IWL<1516> A_IWL<1515> A_IWL<1514> A_IWL<1513> A_IWL<1512> A_IWL<1511> A_IWL<1510> A_IWL<1509> A_IWL<1508> A_IWL<1507> A_IWL<1506> A_IWL<1505> A_IWL<1504> A_IWL<1503> A_IWL<1502> A_IWL<1501> A_IWL<1500> A_IWL<1499> A_IWL<1498> A_IWL<1497> A_IWL<1496> A_IWL<1495> A_IWL<1494> A_IWL<1493> A_IWL<1492> A_IWL<1491> A_IWL<1490> A_IWL<1489> A_IWL<1488> A_IWL<1487> A_IWL<1486> A_IWL<1485> A_IWL<1484> A_IWL<1483> A_IWL<1482> A_IWL<1481> A_IWL<1480> A_IWL<1479> A_IWL<1478> A_IWL<1477> A_IWL<1476> A_IWL<1475> A_IWL<1474> A_IWL<1473> A_IWL<1472> A_IWL<1471> A_IWL<1470> A_IWL<1469> A_IWL<1468> A_IWL<1467> A_IWL<1466> A_IWL<1465> A_IWL<1464> A_IWL<1463> A_IWL<1462> A_IWL<1461> A_IWL<1460> A_IWL<1459> A_IWL<1458> A_IWL<1457> A_IWL<1456> A_IWL<1455> A_IWL<1454> A_IWL<1453> A_IWL<1452> A_IWL<1451> A_IWL<1450> A_IWL<1449> A_IWL<1448> A_IWL<1447> A_IWL<1446> A_IWL<1445> A_IWL<1444> A_IWL<1443> A_IWL<1442> A_IWL<1441> A_IWL<1440> A_IWL<1439> A_IWL<1438> A_IWL<1437> A_IWL<1436> A_IWL<1435> A_IWL<1434> A_IWL<1433> A_IWL<1432> A_IWL<1431> A_IWL<1430> A_IWL<1429> A_IWL<1428> A_IWL<1427> A_IWL<1426> A_IWL<1425> A_IWL<1424> A_IWL<1423> A_IWL<1422> A_IWL<1421> A_IWL<1420> A_IWL<1419> A_IWL<1418> A_IWL<1417> A_IWL<1416> A_IWL<1415> A_IWL<1414> A_IWL<1413> A_IWL<1412> A_IWL<1411> A_IWL<1410> A_IWL<1409> A_IWL<1408> A_IWL<1407> A_IWL<1406> A_IWL<1405> A_IWL<1404> A_IWL<1403> A_IWL<1402> A_IWL<1401> A_IWL<1400> A_IWL<1399> A_IWL<1398> A_IWL<1397> A_IWL<1396> A_IWL<1395> A_IWL<1394> A_IWL<1393> A_IWL<1392> A_IWL<1391> A_IWL<1390> A_IWL<1389> A_IWL<1388> A_IWL<1387> A_IWL<1386> A_IWL<1385> A_IWL<1384> A_IWL<1383> A_IWL<1382> A_IWL<1381> A_IWL<1380> A_IWL<1379> A_IWL<1378> A_IWL<1377> A_IWL<1376> A_IWL<1375> A_IWL<1374> A_IWL<1373> A_IWL<1372> A_IWL<1371> A_IWL<1370> A_IWL<1369> A_IWL<1368> A_IWL<1367> A_IWL<1366> A_IWL<1365> A_IWL<1364> A_IWL<1363> A_IWL<1362> A_IWL<1361> A_IWL<1360> A_IWL<1359> A_IWL<1358> A_IWL<1357> A_IWL<1356> A_IWL<1355> A_IWL<1354> A_IWL<1353> A_IWL<1352> A_IWL<1351> A_IWL<1350> A_IWL<1349> A_IWL<1348> A_IWL<1347> A_IWL<1346> A_IWL<1345> A_IWL<1344> A_IWL<1343> A_IWL<1342> A_IWL<1341> A_IWL<1340> A_IWL<1339> A_IWL<1338> A_IWL<1337> A_IWL<1336> A_IWL<1335> A_IWL<1334> A_IWL<1333> A_IWL<1332> A_IWL<1331> A_IWL<1330> A_IWL<1329> A_IWL<1328> A_IWL<1327> A_IWL<1326> A_IWL<1325> A_IWL<1324> A_IWL<1323> A_IWL<1322> A_IWL<1321> A_IWL<1320> A_IWL<1319> A_IWL<1318> A_IWL<1317> A_IWL<1316> A_IWL<1315> A_IWL<1314> A_IWL<1313> A_IWL<1312> A_IWL<1311> A_IWL<1310> A_IWL<1309> A_IWL<1308> A_IWL<1307> A_IWL<1306> A_IWL<1305> A_IWL<1304> A_IWL<1303> A_IWL<1302> A_IWL<1301> A_IWL<1300> A_IWL<1299> A_IWL<1298> A_IWL<1297> A_IWL<1296> A_IWL<1295> A_IWL<1294> A_IWL<1293> A_IWL<1292> A_IWL<1291> A_IWL<1290> A_IWL<1289> A_IWL<1288> A_IWL<1287> A_IWL<1286> A_IWL<1285> A_IWL<1284> A_IWL<1283> A_IWL<1282> A_IWL<1281> A_IWL<1280> A_IWL<1791> A_IWL<1790> A_IWL<1789> A_IWL<1788> A_IWL<1787> A_IWL<1786> A_IWL<1785> A_IWL<1784> A_IWL<1783> A_IWL<1782> A_IWL<1781> A_IWL<1780> A_IWL<1779> A_IWL<1778> A_IWL<1777> A_IWL<1776> A_IWL<1775> A_IWL<1774> A_IWL<1773> A_IWL<1772> A_IWL<1771> A_IWL<1770> A_IWL<1769> A_IWL<1768> A_IWL<1767> A_IWL<1766> A_IWL<1765> A_IWL<1764> A_IWL<1763> A_IWL<1762> A_IWL<1761> A_IWL<1760> A_IWL<1759> A_IWL<1758> A_IWL<1757> A_IWL<1756> A_IWL<1755> A_IWL<1754> A_IWL<1753> A_IWL<1752> A_IWL<1751> A_IWL<1750> A_IWL<1749> A_IWL<1748> A_IWL<1747> A_IWL<1746> A_IWL<1745> A_IWL<1744> A_IWL<1743> A_IWL<1742> A_IWL<1741> A_IWL<1740> A_IWL<1739> A_IWL<1738> A_IWL<1737> A_IWL<1736> A_IWL<1735> A_IWL<1734> A_IWL<1733> A_IWL<1732> A_IWL<1731> A_IWL<1730> A_IWL<1729> A_IWL<1728> A_IWL<1727> A_IWL<1726> A_IWL<1725> A_IWL<1724> A_IWL<1723> A_IWL<1722> A_IWL<1721> A_IWL<1720> A_IWL<1719> A_IWL<1718> A_IWL<1717> A_IWL<1716> A_IWL<1715> A_IWL<1714> A_IWL<1713> A_IWL<1712> A_IWL<1711> A_IWL<1710> A_IWL<1709> A_IWL<1708> A_IWL<1707> A_IWL<1706> A_IWL<1705> A_IWL<1704> A_IWL<1703> A_IWL<1702> A_IWL<1701> A_IWL<1700> A_IWL<1699> A_IWL<1698> A_IWL<1697> A_IWL<1696> A_IWL<1695> A_IWL<1694> A_IWL<1693> A_IWL<1692> A_IWL<1691> A_IWL<1690> A_IWL<1689> A_IWL<1688> A_IWL<1687> A_IWL<1686> A_IWL<1685> A_IWL<1684> A_IWL<1683> A_IWL<1682> A_IWL<1681> A_IWL<1680> A_IWL<1679> A_IWL<1678> A_IWL<1677> A_IWL<1676> A_IWL<1675> A_IWL<1674> A_IWL<1673> A_IWL<1672> A_IWL<1671> A_IWL<1670> A_IWL<1669> A_IWL<1668> A_IWL<1667> A_IWL<1666> A_IWL<1665> A_IWL<1664> A_IWL<1663> A_IWL<1662> A_IWL<1661> A_IWL<1660> A_IWL<1659> A_IWL<1658> A_IWL<1657> A_IWL<1656> A_IWL<1655> A_IWL<1654> A_IWL<1653> A_IWL<1652> A_IWL<1651> A_IWL<1650> A_IWL<1649> A_IWL<1648> A_IWL<1647> A_IWL<1646> A_IWL<1645> A_IWL<1644> A_IWL<1643> A_IWL<1642> A_IWL<1641> A_IWL<1640> A_IWL<1639> A_IWL<1638> A_IWL<1637> A_IWL<1636> A_IWL<1635> A_IWL<1634> A_IWL<1633> A_IWL<1632> A_IWL<1631> A_IWL<1630> A_IWL<1629> A_IWL<1628> A_IWL<1627> A_IWL<1626> A_IWL<1625> A_IWL<1624> A_IWL<1623> A_IWL<1622> A_IWL<1621> A_IWL<1620> A_IWL<1619> A_IWL<1618> A_IWL<1617> A_IWL<1616> A_IWL<1615> A_IWL<1614> A_IWL<1613> A_IWL<1612> A_IWL<1611> A_IWL<1610> A_IWL<1609> A_IWL<1608> A_IWL<1607> A_IWL<1606> A_IWL<1605> A_IWL<1604> A_IWL<1603> A_IWL<1602> A_IWL<1601> A_IWL<1600> A_IWL<1599> A_IWL<1598> A_IWL<1597> A_IWL<1596> A_IWL<1595> A_IWL<1594> A_IWL<1593> A_IWL<1592> A_IWL<1591> A_IWL<1590> A_IWL<1589> A_IWL<1588> A_IWL<1587> A_IWL<1586> A_IWL<1585> A_IWL<1584> A_IWL<1583> A_IWL<1582> A_IWL<1581> A_IWL<1580> A_IWL<1579> A_IWL<1578> A_IWL<1577> A_IWL<1576> A_IWL<1575> A_IWL<1574> A_IWL<1573> A_IWL<1572> A_IWL<1571> A_IWL<1570> A_IWL<1569> A_IWL<1568> A_IWL<1567> A_IWL<1566> A_IWL<1565> A_IWL<1564> A_IWL<1563> A_IWL<1562> A_IWL<1561> A_IWL<1560> A_IWL<1559> A_IWL<1558> A_IWL<1557> A_IWL<1556> A_IWL<1555> A_IWL<1554> A_IWL<1553> A_IWL<1552> A_IWL<1551> A_IWL<1550> A_IWL<1549> A_IWL<1548> A_IWL<1547> A_IWL<1546> A_IWL<1545> A_IWL<1544> A_IWL<1543> A_IWL<1542> A_IWL<1541> A_IWL<1540> A_IWL<1539> A_IWL<1538> A_IWL<1537> A_IWL<1536> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_COLUMN_pcell_0
+XCOL<5> A_BLC<11> A_BLC<10> A_BLC_TOP<11> A_BLC_TOP<10> A_BLT<11> A_BLT<10> A_BLT_TOP<11> A_BLT_TOP<10> A_IWL<1279> A_IWL<1278> A_IWL<1277> A_IWL<1276> A_IWL<1275> A_IWL<1274> A_IWL<1273> A_IWL<1272> A_IWL<1271> A_IWL<1270> A_IWL<1269> A_IWL<1268> A_IWL<1267> A_IWL<1266> A_IWL<1265> A_IWL<1264> A_IWL<1263> A_IWL<1262> A_IWL<1261> A_IWL<1260> A_IWL<1259> A_IWL<1258> A_IWL<1257> A_IWL<1256> A_IWL<1255> A_IWL<1254> A_IWL<1253> A_IWL<1252> A_IWL<1251> A_IWL<1250> A_IWL<1249> A_IWL<1248> A_IWL<1247> A_IWL<1246> A_IWL<1245> A_IWL<1244> A_IWL<1243> A_IWL<1242> A_IWL<1241> A_IWL<1240> A_IWL<1239> A_IWL<1238> A_IWL<1237> A_IWL<1236> A_IWL<1235> A_IWL<1234> A_IWL<1233> A_IWL<1232> A_IWL<1231> A_IWL<1230> A_IWL<1229> A_IWL<1228> A_IWL<1227> A_IWL<1226> A_IWL<1225> A_IWL<1224> A_IWL<1223> A_IWL<1222> A_IWL<1221> A_IWL<1220> A_IWL<1219> A_IWL<1218> A_IWL<1217> A_IWL<1216> A_IWL<1215> A_IWL<1214> A_IWL<1213> A_IWL<1212> A_IWL<1211> A_IWL<1210> A_IWL<1209> A_IWL<1208> A_IWL<1207> A_IWL<1206> A_IWL<1205> A_IWL<1204> A_IWL<1203> A_IWL<1202> A_IWL<1201> A_IWL<1200> A_IWL<1199> A_IWL<1198> A_IWL<1197> A_IWL<1196> A_IWL<1195> A_IWL<1194> A_IWL<1193> A_IWL<1192> A_IWL<1191> A_IWL<1190> A_IWL<1189> A_IWL<1188> A_IWL<1187> A_IWL<1186> A_IWL<1185> A_IWL<1184> A_IWL<1183> A_IWL<1182> A_IWL<1181> A_IWL<1180> A_IWL<1179> A_IWL<1178> A_IWL<1177> A_IWL<1176> A_IWL<1175> A_IWL<1174> A_IWL<1173> A_IWL<1172> A_IWL<1171> A_IWL<1170> A_IWL<1169> A_IWL<1168> A_IWL<1167> A_IWL<1166> A_IWL<1165> A_IWL<1164> A_IWL<1163> A_IWL<1162> A_IWL<1161> A_IWL<1160> A_IWL<1159> A_IWL<1158> A_IWL<1157> A_IWL<1156> A_IWL<1155> A_IWL<1154> A_IWL<1153> A_IWL<1152> A_IWL<1151> A_IWL<1150> A_IWL<1149> A_IWL<1148> A_IWL<1147> A_IWL<1146> A_IWL<1145> A_IWL<1144> A_IWL<1143> A_IWL<1142> A_IWL<1141> A_IWL<1140> A_IWL<1139> A_IWL<1138> A_IWL<1137> A_IWL<1136> A_IWL<1135> A_IWL<1134> A_IWL<1133> A_IWL<1132> A_IWL<1131> A_IWL<1130> A_IWL<1129> A_IWL<1128> A_IWL<1127> A_IWL<1126> A_IWL<1125> A_IWL<1124> A_IWL<1123> A_IWL<1122> A_IWL<1121> A_IWL<1120> A_IWL<1119> A_IWL<1118> A_IWL<1117> A_IWL<1116> A_IWL<1115> A_IWL<1114> A_IWL<1113> A_IWL<1112> A_IWL<1111> A_IWL<1110> A_IWL<1109> A_IWL<1108> A_IWL<1107> A_IWL<1106> A_IWL<1105> A_IWL<1104> A_IWL<1103> A_IWL<1102> A_IWL<1101> A_IWL<1100> A_IWL<1099> A_IWL<1098> A_IWL<1097> A_IWL<1096> A_IWL<1095> A_IWL<1094> A_IWL<1093> A_IWL<1092> A_IWL<1091> A_IWL<1090> A_IWL<1089> A_IWL<1088> A_IWL<1087> A_IWL<1086> A_IWL<1085> A_IWL<1084> A_IWL<1083> A_IWL<1082> A_IWL<1081> A_IWL<1080> A_IWL<1079> A_IWL<1078> A_IWL<1077> A_IWL<1076> A_IWL<1075> A_IWL<1074> A_IWL<1073> A_IWL<1072> A_IWL<1071> A_IWL<1070> A_IWL<1069> A_IWL<1068> A_IWL<1067> A_IWL<1066> A_IWL<1065> A_IWL<1064> A_IWL<1063> A_IWL<1062> A_IWL<1061> A_IWL<1060> A_IWL<1059> A_IWL<1058> A_IWL<1057> A_IWL<1056> A_IWL<1055> A_IWL<1054> A_IWL<1053> A_IWL<1052> A_IWL<1051> A_IWL<1050> A_IWL<1049> A_IWL<1048> A_IWL<1047> A_IWL<1046> A_IWL<1045> A_IWL<1044> A_IWL<1043> A_IWL<1042> A_IWL<1041> A_IWL<1040> A_IWL<1039> A_IWL<1038> A_IWL<1037> A_IWL<1036> A_IWL<1035> A_IWL<1034> A_IWL<1033> A_IWL<1032> A_IWL<1031> A_IWL<1030> A_IWL<1029> A_IWL<1028> A_IWL<1027> A_IWL<1026> A_IWL<1025> A_IWL<1024> A_IWL<1535> A_IWL<1534> A_IWL<1533> A_IWL<1532> A_IWL<1531> A_IWL<1530> A_IWL<1529> A_IWL<1528> A_IWL<1527> A_IWL<1526> A_IWL<1525> A_IWL<1524> A_IWL<1523> A_IWL<1522> A_IWL<1521> A_IWL<1520> A_IWL<1519> A_IWL<1518> A_IWL<1517> A_IWL<1516> A_IWL<1515> A_IWL<1514> A_IWL<1513> A_IWL<1512> A_IWL<1511> A_IWL<1510> A_IWL<1509> A_IWL<1508> A_IWL<1507> A_IWL<1506> A_IWL<1505> A_IWL<1504> A_IWL<1503> A_IWL<1502> A_IWL<1501> A_IWL<1500> A_IWL<1499> A_IWL<1498> A_IWL<1497> A_IWL<1496> A_IWL<1495> A_IWL<1494> A_IWL<1493> A_IWL<1492> A_IWL<1491> A_IWL<1490> A_IWL<1489> A_IWL<1488> A_IWL<1487> A_IWL<1486> A_IWL<1485> A_IWL<1484> A_IWL<1483> A_IWL<1482> A_IWL<1481> A_IWL<1480> A_IWL<1479> A_IWL<1478> A_IWL<1477> A_IWL<1476> A_IWL<1475> A_IWL<1474> A_IWL<1473> A_IWL<1472> A_IWL<1471> A_IWL<1470> A_IWL<1469> A_IWL<1468> A_IWL<1467> A_IWL<1466> A_IWL<1465> A_IWL<1464> A_IWL<1463> A_IWL<1462> A_IWL<1461> A_IWL<1460> A_IWL<1459> A_IWL<1458> A_IWL<1457> A_IWL<1456> A_IWL<1455> A_IWL<1454> A_IWL<1453> A_IWL<1452> A_IWL<1451> A_IWL<1450> A_IWL<1449> A_IWL<1448> A_IWL<1447> A_IWL<1446> A_IWL<1445> A_IWL<1444> A_IWL<1443> A_IWL<1442> A_IWL<1441> A_IWL<1440> A_IWL<1439> A_IWL<1438> A_IWL<1437> A_IWL<1436> A_IWL<1435> A_IWL<1434> A_IWL<1433> A_IWL<1432> A_IWL<1431> A_IWL<1430> A_IWL<1429> A_IWL<1428> A_IWL<1427> A_IWL<1426> A_IWL<1425> A_IWL<1424> A_IWL<1423> A_IWL<1422> A_IWL<1421> A_IWL<1420> A_IWL<1419> A_IWL<1418> A_IWL<1417> A_IWL<1416> A_IWL<1415> A_IWL<1414> A_IWL<1413> A_IWL<1412> A_IWL<1411> A_IWL<1410> A_IWL<1409> A_IWL<1408> A_IWL<1407> A_IWL<1406> A_IWL<1405> A_IWL<1404> A_IWL<1403> A_IWL<1402> A_IWL<1401> A_IWL<1400> A_IWL<1399> A_IWL<1398> A_IWL<1397> A_IWL<1396> A_IWL<1395> A_IWL<1394> A_IWL<1393> A_IWL<1392> A_IWL<1391> A_IWL<1390> A_IWL<1389> A_IWL<1388> A_IWL<1387> A_IWL<1386> A_IWL<1385> A_IWL<1384> A_IWL<1383> A_IWL<1382> A_IWL<1381> A_IWL<1380> A_IWL<1379> A_IWL<1378> A_IWL<1377> A_IWL<1376> A_IWL<1375> A_IWL<1374> A_IWL<1373> A_IWL<1372> A_IWL<1371> A_IWL<1370> A_IWL<1369> A_IWL<1368> A_IWL<1367> A_IWL<1366> A_IWL<1365> A_IWL<1364> A_IWL<1363> A_IWL<1362> A_IWL<1361> A_IWL<1360> A_IWL<1359> A_IWL<1358> A_IWL<1357> A_IWL<1356> A_IWL<1355> A_IWL<1354> A_IWL<1353> A_IWL<1352> A_IWL<1351> A_IWL<1350> A_IWL<1349> A_IWL<1348> A_IWL<1347> A_IWL<1346> A_IWL<1345> A_IWL<1344> A_IWL<1343> A_IWL<1342> A_IWL<1341> A_IWL<1340> A_IWL<1339> A_IWL<1338> A_IWL<1337> A_IWL<1336> A_IWL<1335> A_IWL<1334> A_IWL<1333> A_IWL<1332> A_IWL<1331> A_IWL<1330> A_IWL<1329> A_IWL<1328> A_IWL<1327> A_IWL<1326> A_IWL<1325> A_IWL<1324> A_IWL<1323> A_IWL<1322> A_IWL<1321> A_IWL<1320> A_IWL<1319> A_IWL<1318> A_IWL<1317> A_IWL<1316> A_IWL<1315> A_IWL<1314> A_IWL<1313> A_IWL<1312> A_IWL<1311> A_IWL<1310> A_IWL<1309> A_IWL<1308> A_IWL<1307> A_IWL<1306> A_IWL<1305> A_IWL<1304> A_IWL<1303> A_IWL<1302> A_IWL<1301> A_IWL<1300> A_IWL<1299> A_IWL<1298> A_IWL<1297> A_IWL<1296> A_IWL<1295> A_IWL<1294> A_IWL<1293> A_IWL<1292> A_IWL<1291> A_IWL<1290> A_IWL<1289> A_IWL<1288> A_IWL<1287> A_IWL<1286> A_IWL<1285> A_IWL<1284> A_IWL<1283> A_IWL<1282> A_IWL<1281> A_IWL<1280> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_COLUMN_pcell_0
+XCOL<4> A_BLC<9> A_BLC<8> A_BLC_TOP<9> A_BLC_TOP<8> A_BLT<9> A_BLT<8> A_BLT_TOP<9> A_BLT_TOP<8> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> A_IWL<1279> A_IWL<1278> A_IWL<1277> A_IWL<1276> A_IWL<1275> A_IWL<1274> A_IWL<1273> A_IWL<1272> A_IWL<1271> A_IWL<1270> A_IWL<1269> A_IWL<1268> A_IWL<1267> A_IWL<1266> A_IWL<1265> A_IWL<1264> A_IWL<1263> A_IWL<1262> A_IWL<1261> A_IWL<1260> A_IWL<1259> A_IWL<1258> A_IWL<1257> A_IWL<1256> A_IWL<1255> A_IWL<1254> A_IWL<1253> A_IWL<1252> A_IWL<1251> A_IWL<1250> A_IWL<1249> A_IWL<1248> A_IWL<1247> A_IWL<1246> A_IWL<1245> A_IWL<1244> A_IWL<1243> A_IWL<1242> A_IWL<1241> A_IWL<1240> A_IWL<1239> A_IWL<1238> A_IWL<1237> A_IWL<1236> A_IWL<1235> A_IWL<1234> A_IWL<1233> A_IWL<1232> A_IWL<1231> A_IWL<1230> A_IWL<1229> A_IWL<1228> A_IWL<1227> A_IWL<1226> A_IWL<1225> A_IWL<1224> A_IWL<1223> A_IWL<1222> A_IWL<1221> A_IWL<1220> A_IWL<1219> A_IWL<1218> A_IWL<1217> A_IWL<1216> A_IWL<1215> A_IWL<1214> A_IWL<1213> A_IWL<1212> A_IWL<1211> A_IWL<1210> A_IWL<1209> A_IWL<1208> A_IWL<1207> A_IWL<1206> A_IWL<1205> A_IWL<1204> A_IWL<1203> A_IWL<1202> A_IWL<1201> A_IWL<1200> A_IWL<1199> A_IWL<1198> A_IWL<1197> A_IWL<1196> A_IWL<1195> A_IWL<1194> A_IWL<1193> A_IWL<1192> A_IWL<1191> A_IWL<1190> A_IWL<1189> A_IWL<1188> A_IWL<1187> A_IWL<1186> A_IWL<1185> A_IWL<1184> A_IWL<1183> A_IWL<1182> A_IWL<1181> A_IWL<1180> A_IWL<1179> A_IWL<1178> A_IWL<1177> A_IWL<1176> A_IWL<1175> A_IWL<1174> A_IWL<1173> A_IWL<1172> A_IWL<1171> A_IWL<1170> A_IWL<1169> A_IWL<1168> A_IWL<1167> A_IWL<1166> A_IWL<1165> A_IWL<1164> A_IWL<1163> A_IWL<1162> A_IWL<1161> A_IWL<1160> A_IWL<1159> A_IWL<1158> A_IWL<1157> A_IWL<1156> A_IWL<1155> A_IWL<1154> A_IWL<1153> A_IWL<1152> A_IWL<1151> A_IWL<1150> A_IWL<1149> A_IWL<1148> A_IWL<1147> A_IWL<1146> A_IWL<1145> A_IWL<1144> A_IWL<1143> A_IWL<1142> A_IWL<1141> A_IWL<1140> A_IWL<1139> A_IWL<1138> A_IWL<1137> A_IWL<1136> A_IWL<1135> A_IWL<1134> A_IWL<1133> A_IWL<1132> A_IWL<1131> A_IWL<1130> A_IWL<1129> A_IWL<1128> A_IWL<1127> A_IWL<1126> A_IWL<1125> A_IWL<1124> A_IWL<1123> A_IWL<1122> A_IWL<1121> A_IWL<1120> A_IWL<1119> A_IWL<1118> A_IWL<1117> A_IWL<1116> A_IWL<1115> A_IWL<1114> A_IWL<1113> A_IWL<1112> A_IWL<1111> A_IWL<1110> A_IWL<1109> A_IWL<1108> A_IWL<1107> A_IWL<1106> A_IWL<1105> A_IWL<1104> A_IWL<1103> A_IWL<1102> A_IWL<1101> A_IWL<1100> A_IWL<1099> A_IWL<1098> A_IWL<1097> A_IWL<1096> A_IWL<1095> A_IWL<1094> A_IWL<1093> A_IWL<1092> A_IWL<1091> A_IWL<1090> A_IWL<1089> A_IWL<1088> A_IWL<1087> A_IWL<1086> A_IWL<1085> A_IWL<1084> A_IWL<1083> A_IWL<1082> A_IWL<1081> A_IWL<1080> A_IWL<1079> A_IWL<1078> A_IWL<1077> A_IWL<1076> A_IWL<1075> A_IWL<1074> A_IWL<1073> A_IWL<1072> A_IWL<1071> A_IWL<1070> A_IWL<1069> A_IWL<1068> A_IWL<1067> A_IWL<1066> A_IWL<1065> A_IWL<1064> A_IWL<1063> A_IWL<1062> A_IWL<1061> A_IWL<1060> A_IWL<1059> A_IWL<1058> A_IWL<1057> A_IWL<1056> A_IWL<1055> A_IWL<1054> A_IWL<1053> A_IWL<1052> A_IWL<1051> A_IWL<1050> A_IWL<1049> A_IWL<1048> A_IWL<1047> A_IWL<1046> A_IWL<1045> A_IWL<1044> A_IWL<1043> A_IWL<1042> A_IWL<1041> A_IWL<1040> A_IWL<1039> A_IWL<1038> A_IWL<1037> A_IWL<1036> A_IWL<1035> A_IWL<1034> A_IWL<1033> A_IWL<1032> A_IWL<1031> A_IWL<1030> A_IWL<1029> A_IWL<1028> A_IWL<1027> A_IWL<1026> A_IWL<1025> A_IWL<1024> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_COLUMN_pcell_0
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A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> 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A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_COLUMN_pcell_0
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A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_COLUMN_pcell_0
+XCOL<1> A_BLC<3> A_BLC<2> A_BLC_TOP<3> A_BLC_TOP<2> A_BLT<3> A_BLT<2> A_BLT_TOP<3> A_BLT_TOP<2> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_COLUMN_pcell_0
+XCOL<0> A_BLC<1> A_BLC<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<1> A_BLT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_WL<255> A_WL<254> A_WL<253> A_WL<252> A_WL<251> A_WL<250> A_WL<249> A_WL<248> A_WL<247> A_WL<246> A_WL<245> A_WL<244> A_WL<243> A_WL<242> A_WL<241> A_WL<240> A_WL<239> A_WL<238> A_WL<237> A_WL<236> A_WL<235> A_WL<234> A_WL<233> A_WL<232> A_WL<231> A_WL<230> A_WL<229> A_WL<228> A_WL<227> A_WL<226> A_WL<225> A_WL<224> A_WL<223> A_WL<222> A_WL<221> A_WL<220> A_WL<219> A_WL<218> A_WL<217> A_WL<216> A_WL<215> A_WL<214> A_WL<213> A_WL<212> A_WL<211> A_WL<210> A_WL<209> A_WL<208> A_WL<207> A_WL<206> A_WL<205> A_WL<204> A_WL<203> A_WL<202> A_WL<201> A_WL<200> A_WL<199> A_WL<198> A_WL<197> A_WL<196> A_WL<195> A_WL<194> A_WL<193> A_WL<192> A_WL<191> A_WL<190> A_WL<189> A_WL<188> A_WL<187> A_WL<186> A_WL<185> A_WL<184> A_WL<183> A_WL<182> A_WL<181> A_WL<180> A_WL<179> A_WL<178> A_WL<177> A_WL<176> A_WL<175> A_WL<174> A_WL<173> A_WL<172> A_WL<171> A_WL<170> A_WL<169> A_WL<168> A_WL<167> A_WL<166> A_WL<165> A_WL<164> A_WL<163> A_WL<162> A_WL<161> A_WL<160> A_WL<159> A_WL<158> A_WL<157> A_WL<156> A_WL<155> A_WL<154> A_WL<153> A_WL<152> A_WL<151> A_WL<150> A_WL<149> A_WL<148> A_WL<147> A_WL<146> A_WL<145> A_WL<144> A_WL<143> A_WL<142> A_WL<141> A_WL<140> A_WL<139> A_WL<138> A_WL<137> A_WL<136> A_WL<135> A_WL<134> A_WL<133> A_WL<132> A_WL<131> A_WL<130> A_WL<129> A_WL<128> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> VDD_CORE VSS / RM_IHPSG13_1024x16_c2_1P_COLUMN_pcell_0
+.ENDS
+
+
+
+
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_DLY_pcell_2 A Z VDD VSS
+	XIDL<2> D<7> Z VDD VSS / RSC_IHPSG13_CDLYX1 
+	XIDL<1> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1 
+	XIDM<6> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY 
+	XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY 
+	XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY 
+	XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY 
+	XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY 
+	XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY 
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_1024x16_c2_1P_DLY_pcell_3 A Z VDD VSS
+	XIDL<4> D<7> Z VDD VSS / RSC_IHPSG13_CDLYX1 
+	XIDL<3> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1 
+	XIDL<2> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1 
+	XIDL<1> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1 
+	XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY 
+	XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY 
+	XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY 
+	XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY 
+.ENDS
+
+
+
+.SUBCKT RM_IHPSG13_1P_1024x16_c2_bm_bist A_ADDR<9> A_ADDR<8> A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> A_ADDR<1> A_ADDR<0> A_BIST_ADDR<9> A_BIST_ADDR<8> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_BM<15> A_BIST_BM<14> A_BIST_BM<13> A_BIST_BM<12> A_BIST_BM<11> A_BIST_BM<10> A_BIST_BM<9> A_BIST_BM<8> A_BIST_BM<7> A_BIST_BM<6> A_BIST_BM<5> A_BIST_BM<4> A_BIST_BM<3> A_BIST_BM<2> A_BIST_BM<1> A_BIST_BM<0> A_BIST_CLK A_BIST_DIN<15> A_BIST_DIN<14> A_BIST_DIN<13> A_BIST_DIN<12> A_BIST_DIN<11> A_BIST_DIN<10> A_BIST_DIN<9> A_BIST_DIN<8> A_BIST_DIN<7> A_BIST_DIN<6> A_BIST_DIN<5> A_BIST_DIN<4> A_BIST_DIN<3> A_BIST_DIN<2> A_BIST_DIN<1> A_BIST_DIN<0> A_BIST_EN A_BIST_MEN A_BIST_REN A_BIST_WEN A_BM<15> A_BM<14> A_BM<13> A_BM<12> A_BM<11> A_BM<10> A_BM<9> A_BM<8> A_BM<7> A_BM<6> A_BM<5> A_BM<4> A_BM<3> A_BM<2> A_BM<1> A_BM<0> A_CLK A_DIN<15> A_DIN<14> A_DIN<13> A_DIN<12> A_DIN<11> A_DIN<10> A_DIN<9> A_DIN<8> A_DIN<7> A_DIN<6> A_DIN<5> A_DIN<4> A_DIN<3> A_DIN<2> A_DIN<1> A_DIN<0> A_DLY A_DOUT<15> A_DOUT<14> A_DOUT<13> A_DOUT<12> A_DOUT<11> A_DOUT<10> A_DOUT<9> A_DOUT<8> A_DOUT<7> A_DOUT<6> A_DOUT<5> A_DOUT<4> A_DOUT<3> A_DOUT<2> A_DOUT<1> A_DOUT<0> A_MEN A_REN A_WEN VDD! VDDARRAY! VSS!
+
+
+XRAM<1> a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> a_wl_r<255> a_wl_r<254> a_wl_r<253> a_wl_r<252> a_wl_r<251> a_wl_r<250> a_wl_r<249> a_wl_r<248> a_wl_r<247> a_wl_r<246> a_wl_r<245> a_wl_r<244> a_wl_r<243> a_wl_r<242> a_wl_r<241> a_wl_r<240> a_wl_r<239> a_wl_r<238> a_wl_r<237> a_wl_r<236> a_wl_r<235> a_wl_r<234> a_wl_r<233> a_wl_r<232> a_wl_r<231> a_wl_r<230> a_wl_r<229> a_wl_r<228> a_wl_r<227> a_wl_r<226> a_wl_r<225> a_wl_r<224> a_wl_r<223> a_wl_r<222> a_wl_r<221> a_wl_r<220> a_wl_r<219> a_wl_r<218> a_wl_r<217> a_wl_r<216> a_wl_r<215> a_wl_r<214> a_wl_r<213> a_wl_r<212> a_wl_r<211> a_wl_r<210> a_wl_r<209> a_wl_r<208> a_wl_r<207> a_wl_r<206> a_wl_r<205> a_wl_r<204> a_wl_r<203> a_wl_r<202> a_wl_r<201> a_wl_r<200> a_wl_r<199> a_wl_r<198> a_wl_r<197> a_wl_r<196> a_wl_r<195> a_wl_r<194> a_wl_r<193> a_wl_r<192> a_wl_r<191> a_wl_r<190> a_wl_r<189> a_wl_r<188> a_wl_r<187> a_wl_r<186> a_wl_r<185> a_wl_r<184> a_wl_r<183> a_wl_r<182> a_wl_r<181> a_wl_r<180> a_wl_r<179> a_wl_r<178> a_wl_r<177> a_wl_r<176> a_wl_r<175> a_wl_r<174> a_wl_r<173> a_wl_r<172> a_wl_r<171> a_wl_r<170> a_wl_r<169> a_wl_r<168> a_wl_r<167> a_wl_r<166> a_wl_r<165> a_wl_r<164> a_wl_r<163> a_wl_r<162> a_wl_r<161> a_wl_r<160> a_wl_r<159> a_wl_r<158> a_wl_r<157> a_wl_r<156> a_wl_r<155> a_wl_r<154> a_wl_r<153> a_wl_r<152> a_wl_r<151> a_wl_r<150> a_wl_r<149> a_wl_r<148> a_wl_r<147> a_wl_r<146> a_wl_r<145> a_wl_r<144> a_wl_r<143> a_wl_r<142> a_wl_r<141> a_wl_r<140> a_wl_r<139> a_wl_r<138> a_wl_r<137> a_wl_r<136> a_wl_r<135> a_wl_r<134> a_wl_r<133> a_wl_r<132> a_wl_r<131> a_wl_r<130> a_wl_r<129> a_wl_r<128> a_wl_r<127> a_wl_r<126> a_wl_r<125> a_wl_r<124> a_wl_r<123> a_wl_r<122> a_wl_r<121> a_wl_r<120> a_wl_r<119> a_wl_r<118> a_wl_r<117> a_wl_r<116> a_wl_r<115> a_wl_r<114> a_wl_r<113> a_wl_r<112> a_wl_r<111> a_wl_r<110> a_wl_r<109> a_wl_r<108> a_wl_r<107> a_wl_r<106> a_wl_r<105> a_wl_r<104> a_wl_r<103> a_wl_r<102> a_wl_r<101> a_wl_r<100> a_wl_r<99> a_wl_r<98> a_wl_r<97> a_wl_r<96> a_wl_r<95> a_wl_r<94> a_wl_r<93> a_wl_r<92> a_wl_r<91> a_wl_r<90> a_wl_r<89> a_wl_r<88> a_wl_r<87> a_wl_r<86> a_wl_r<85> a_wl_r<84> a_wl_r<83> a_wl_r<82> a_wl_r<81> a_wl_r<80> a_wl_r<79> a_wl_r<78> a_wl_r<77> a_wl_r<76> a_wl_r<75> a_wl_r<74> a_wl_r<73> a_wl_r<72> a_wl_r<71> a_wl_r<70> a_wl_r<69> a_wl_r<68> a_wl_r<67> a_wl_r<66> a_wl_r<65> a_wl_r<64> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDDARRAY! VSS! / RM_IHPSG13_1024x16_c2_1P_MATRIX_pcell_1
+XRAM<0> a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> a_wl_l<255> a_wl_l<254> a_wl_l<253> a_wl_l<252> a_wl_l<251> a_wl_l<250> a_wl_l<249> a_wl_l<248> a_wl_l<247> a_wl_l<246> a_wl_l<245> a_wl_l<244> a_wl_l<243> a_wl_l<242> a_wl_l<241> a_wl_l<240> a_wl_l<239> a_wl_l<238> a_wl_l<237> a_wl_l<236> a_wl_l<235> a_wl_l<234> a_wl_l<233> a_wl_l<232> a_wl_l<231> a_wl_l<230> a_wl_l<229> a_wl_l<228> a_wl_l<227> a_wl_l<226> a_wl_l<225> a_wl_l<224> a_wl_l<223> a_wl_l<222> a_wl_l<221> a_wl_l<220> a_wl_l<219> a_wl_l<218> a_wl_l<217> a_wl_l<216> a_wl_l<215> a_wl_l<214> a_wl_l<213> a_wl_l<212> a_wl_l<211> a_wl_l<210> a_wl_l<209> a_wl_l<208> a_wl_l<207> a_wl_l<206> a_wl_l<205> a_wl_l<204> a_wl_l<203> a_wl_l<202> a_wl_l<201> a_wl_l<200> a_wl_l<199> a_wl_l<198> a_wl_l<197> a_wl_l<196> a_wl_l<195> a_wl_l<194> a_wl_l<193> a_wl_l<192> a_wl_l<191> a_wl_l<190> a_wl_l<189> a_wl_l<188> a_wl_l<187> a_wl_l<186> a_wl_l<185> a_wl_l<184> a_wl_l<183> a_wl_l<182> a_wl_l<181> a_wl_l<180> a_wl_l<179> a_wl_l<178> a_wl_l<177> a_wl_l<176> a_wl_l<175> a_wl_l<174> a_wl_l<173> a_wl_l<172> a_wl_l<171> a_wl_l<170> a_wl_l<169> a_wl_l<168> a_wl_l<167> a_wl_l<166> a_wl_l<165> a_wl_l<164> a_wl_l<163> a_wl_l<162> a_wl_l<161> a_wl_l<160> a_wl_l<159> a_wl_l<158> a_wl_l<157> a_wl_l<156> a_wl_l<155> a_wl_l<154> a_wl_l<153> a_wl_l<152> a_wl_l<151> a_wl_l<150> a_wl_l<149> a_wl_l<148> a_wl_l<147> a_wl_l<146> a_wl_l<145> a_wl_l<144> a_wl_l<143> a_wl_l<142> a_wl_l<141> a_wl_l<140> a_wl_l<139> a_wl_l<138> a_wl_l<137> a_wl_l<136> a_wl_l<135> a_wl_l<134> a_wl_l<133> a_wl_l<132> a_wl_l<131> a_wl_l<130> a_wl_l<129> a_wl_l<128> a_wl_l<127> a_wl_l<126> a_wl_l<125> a_wl_l<124> a_wl_l<123> a_wl_l<122> a_wl_l<121> a_wl_l<120> a_wl_l<119> a_wl_l<118> a_wl_l<117> a_wl_l<116> a_wl_l<115> a_wl_l<114> a_wl_l<113> a_wl_l<112> a_wl_l<111> a_wl_l<110> a_wl_l<109> a_wl_l<108> a_wl_l<107> a_wl_l<106> a_wl_l<105> a_wl_l<104> a_wl_l<103> a_wl_l<102> a_wl_l<101> a_wl_l<100> a_wl_l<99> a_wl_l<98> a_wl_l<97> a_wl_l<96> a_wl_l<95> a_wl_l<94> a_wl_l<93> a_wl_l<92> a_wl_l<91> a_wl_l<90> a_wl_l<89> a_wl_l<88> a_wl_l<87> a_wl_l<86> a_wl_l<85> a_wl_l<84> a_wl_l<83> a_wl_l<82> a_wl_l<81> a_wl_l<80> a_wl_l<79> a_wl_l<78> a_wl_l<77> a_wl_l<76> a_wl_l<75> a_wl_l<74> a_wl_l<73> a_wl_l<72> a_wl_l<71> a_wl_l<70> a_wl_l<69> a_wl_l<68> a_wl_l<67> a_wl_l<66> a_wl_l<65> a_wl_l<64> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDDARRAY! VSS! / RM_IHPSG13_1024x16_c2_1P_MATRIX_pcell_1
+
+
+XA_COLDRV<1> a_addr_col<1> a_addr_col<0> a_addr_col_r<1> a_addr_col_r<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_dclk a_dclk_p_r<0> a_rclk a_rclk_p_r<0> a_wclk a_wclk_p_r<0> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLDRV13X4
+XA_COLDRV<0> a_addr_col<1> a_addr_col<0> a_addr_col_l<1> a_addr_col_l<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_dclk a_dclk_p_l<0> a_rclk a_rclk_p_l<0> a_wclk a_wclk_p_l<0> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLDRV13X4
+
+
+XA_WLDRV<31> a_wi<255> a_wi<254> a_wi<253> a_wi<252> a_wi<251> a_wi<250> a_wi<249> a_wi<248> a_wi<247> a_wi<246> a_wi<245> a_wi<244> a_wi<243> a_wi<242> a_wi<241> a_wi<240> a_wl_r<255> a_wl_r<254> a_wl_r<253> a_wl_r<252> a_wl_r<251> a_wl_r<250> a_wl_r<249> a_wl_r<248> a_wl_r<247> a_wl_r<246> a_wl_r<245> a_wl_r<244> a_wl_r<243> a_wl_r<242> a_wl_r<241> a_wl_r<240>  VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4
+XA_WLDRV<30> a_wi<239> a_wi<238> a_wi<237> a_wi<236> a_wi<235> a_wi<234> a_wi<233> a_wi<232> a_wi<231> a_wi<230> a_wi<229> a_wi<228> a_wi<227> a_wi<226> a_wi<225> a_wi<224> a_wl_r<239> a_wl_r<238> a_wl_r<237> a_wl_r<236> a_wl_r<235> a_wl_r<234> a_wl_r<233> a_wl_r<232> a_wl_r<231> a_wl_r<230> a_wl_r<229> a_wl_r<228> a_wl_r<227> a_wl_r<226> a_wl_r<225> a_wl_r<224>  VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4
+XA_WLDRV<29> a_wi<223> a_wi<222> a_wi<221> a_wi<220> a_wi<219> a_wi<218> a_wi<217> a_wi<216> a_wi<215> a_wi<214> a_wi<213> a_wi<212> a_wi<211> a_wi<210> a_wi<209> a_wi<208> a_wl_r<223> a_wl_r<222> a_wl_r<221> a_wl_r<220> a_wl_r<219> a_wl_r<218> a_wl_r<217> a_wl_r<216> a_wl_r<215> a_wl_r<214> a_wl_r<213> a_wl_r<212> a_wl_r<211> a_wl_r<210> a_wl_r<209> a_wl_r<208>  VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4
+XA_WLDRV<28> a_wi<207> a_wi<206> a_wi<205> a_wi<204> a_wi<203> a_wi<202> a_wi<201> a_wi<200> a_wi<199> a_wi<198> a_wi<197> a_wi<196> a_wi<195> a_wi<194> a_wi<193> a_wi<192> a_wl_r<207> a_wl_r<206> a_wl_r<205> a_wl_r<204> a_wl_r<203> a_wl_r<202> a_wl_r<201> a_wl_r<200> a_wl_r<199> a_wl_r<198> a_wl_r<197> a_wl_r<196> a_wl_r<195> a_wl_r<194> a_wl_r<193> a_wl_r<192>  VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4
+XA_WLDRV<27> a_wi<191> a_wi<190> a_wi<189> a_wi<188> a_wi<187> a_wi<186> a_wi<185> a_wi<184> a_wi<183> a_wi<182> a_wi<181> a_wi<180> a_wi<179> a_wi<178> a_wi<177> a_wi<176> a_wl_r<191> a_wl_r<190> a_wl_r<189> a_wl_r<188> a_wl_r<187> a_wl_r<186> a_wl_r<185> a_wl_r<184> a_wl_r<183> a_wl_r<182> a_wl_r<181> a_wl_r<180> a_wl_r<179> a_wl_r<178> a_wl_r<177> a_wl_r<176>  VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4
+XA_WLDRV<26> a_wi<175> a_wi<174> a_wi<173> a_wi<172> a_wi<171> a_wi<170> a_wi<169> a_wi<168> a_wi<167> a_wi<166> a_wi<165> a_wi<164> a_wi<163> a_wi<162> a_wi<161> a_wi<160> a_wl_r<175> a_wl_r<174> a_wl_r<173> a_wl_r<172> a_wl_r<171> a_wl_r<170> a_wl_r<169> a_wl_r<168> a_wl_r<167> a_wl_r<166> a_wl_r<165> a_wl_r<164> a_wl_r<163> a_wl_r<162> a_wl_r<161> a_wl_r<160>  VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4
+XA_WLDRV<25> a_wi<159> a_wi<158> a_wi<157> a_wi<156> a_wi<155> a_wi<154> a_wi<153> a_wi<152> a_wi<151> a_wi<150> a_wi<149> a_wi<148> a_wi<147> a_wi<146> a_wi<145> a_wi<144> a_wl_r<159> a_wl_r<158> a_wl_r<157> a_wl_r<156> a_wl_r<155> a_wl_r<154> a_wl_r<153> a_wl_r<152> a_wl_r<151> a_wl_r<150> a_wl_r<149> a_wl_r<148> a_wl_r<147> a_wl_r<146> a_wl_r<145> a_wl_r<144>  VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4
+XA_WLDRV<24> a_wi<143> a_wi<142> a_wi<141> a_wi<140> a_wi<139> a_wi<138> a_wi<137> a_wi<136> a_wi<135> a_wi<134> a_wi<133> a_wi<132> a_wi<131> a_wi<130> a_wi<129> a_wi<128> a_wl_r<143> a_wl_r<142> a_wl_r<141> a_wl_r<140> a_wl_r<139> a_wl_r<138> a_wl_r<137> a_wl_r<136> a_wl_r<135> a_wl_r<134> a_wl_r<133> a_wl_r<132> a_wl_r<131> a_wl_r<130> a_wl_r<129> a_wl_r<128>  VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4
+XA_WLDRV<23> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wl_r<127> a_wl_r<126> a_wl_r<125> a_wl_r<124> a_wl_r<123> a_wl_r<122> a_wl_r<121> a_wl_r<120> a_wl_r<119> a_wl_r<118> a_wl_r<117> a_wl_r<116> a_wl_r<115> a_wl_r<114> a_wl_r<113> a_wl_r<112>  VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4
+XA_WLDRV<22> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wl_r<111> a_wl_r<110> a_wl_r<109> a_wl_r<108> a_wl_r<107> a_wl_r<106> a_wl_r<105> a_wl_r<104> a_wl_r<103> a_wl_r<102> a_wl_r<101> a_wl_r<100> a_wl_r<99> a_wl_r<98> a_wl_r<97> a_wl_r<96>  VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4
+XA_WLDRV<21> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wl_r<95> a_wl_r<94> a_wl_r<93> a_wl_r<92> a_wl_r<91> a_wl_r<90> a_wl_r<89> a_wl_r<88> a_wl_r<87> a_wl_r<86> a_wl_r<85> a_wl_r<84> a_wl_r<83> a_wl_r<82> a_wl_r<81> a_wl_r<80>  VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4
+XA_WLDRV<20> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wl_r<79> a_wl_r<78> a_wl_r<77> a_wl_r<76> a_wl_r<75> a_wl_r<74> a_wl_r<73> a_wl_r<72> a_wl_r<71> a_wl_r<70> a_wl_r<69> a_wl_r<68> a_wl_r<67> a_wl_r<66> a_wl_r<65> a_wl_r<64>  VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4
+XA_WLDRV<19> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48>  VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4
+XA_WLDRV<18> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32>  VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4
+XA_WLDRV<17> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16>  VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4
+XA_WLDRV<16> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0>  VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4
+XA_WLDRV<15> a_wi<255> a_wi<254> a_wi<253> a_wi<252> a_wi<251> a_wi<250> a_wi<249> a_wi<248> a_wi<247> a_wi<246> a_wi<245> a_wi<244> a_wi<243> a_wi<242> a_wi<241> a_wi<240> a_wl_l<255> a_wl_l<254> a_wl_l<253> a_wl_l<252> a_wl_l<251> a_wl_l<250> a_wl_l<249> a_wl_l<248> a_wl_l<247> a_wl_l<246> a_wl_l<245> a_wl_l<244> a_wl_l<243> a_wl_l<242> a_wl_l<241> a_wl_l<240>  VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4
+XA_WLDRV<14> a_wi<239> a_wi<238> a_wi<237> a_wi<236> a_wi<235> a_wi<234> a_wi<233> a_wi<232> a_wi<231> a_wi<230> a_wi<229> a_wi<228> a_wi<227> a_wi<226> a_wi<225> a_wi<224> a_wl_l<239> a_wl_l<238> a_wl_l<237> a_wl_l<236> a_wl_l<235> a_wl_l<234> a_wl_l<233> a_wl_l<232> a_wl_l<231> a_wl_l<230> a_wl_l<229> a_wl_l<228> a_wl_l<227> a_wl_l<226> a_wl_l<225> a_wl_l<224>  VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4
+XA_WLDRV<13> a_wi<223> a_wi<222> a_wi<221> a_wi<220> a_wi<219> a_wi<218> a_wi<217> a_wi<216> a_wi<215> a_wi<214> a_wi<213> a_wi<212> a_wi<211> a_wi<210> a_wi<209> a_wi<208> a_wl_l<223> a_wl_l<222> a_wl_l<221> a_wl_l<220> a_wl_l<219> a_wl_l<218> a_wl_l<217> a_wl_l<216> a_wl_l<215> a_wl_l<214> a_wl_l<213> a_wl_l<212> a_wl_l<211> a_wl_l<210> a_wl_l<209> a_wl_l<208>  VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4
+XA_WLDRV<12> a_wi<207> a_wi<206> a_wi<205> a_wi<204> a_wi<203> a_wi<202> a_wi<201> a_wi<200> a_wi<199> a_wi<198> a_wi<197> a_wi<196> a_wi<195> a_wi<194> a_wi<193> a_wi<192> a_wl_l<207> a_wl_l<206> a_wl_l<205> a_wl_l<204> a_wl_l<203> a_wl_l<202> a_wl_l<201> a_wl_l<200> a_wl_l<199> a_wl_l<198> a_wl_l<197> a_wl_l<196> a_wl_l<195> a_wl_l<194> a_wl_l<193> a_wl_l<192>  VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4
+XA_WLDRV<11> a_wi<191> a_wi<190> a_wi<189> a_wi<188> a_wi<187> a_wi<186> a_wi<185> a_wi<184> a_wi<183> a_wi<182> a_wi<181> a_wi<180> a_wi<179> a_wi<178> a_wi<177> a_wi<176> a_wl_l<191> a_wl_l<190> a_wl_l<189> a_wl_l<188> a_wl_l<187> a_wl_l<186> a_wl_l<185> a_wl_l<184> a_wl_l<183> a_wl_l<182> a_wl_l<181> a_wl_l<180> a_wl_l<179> a_wl_l<178> a_wl_l<177> a_wl_l<176>  VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4
+XA_WLDRV<10> a_wi<175> a_wi<174> a_wi<173> a_wi<172> a_wi<171> a_wi<170> a_wi<169> a_wi<168> a_wi<167> a_wi<166> a_wi<165> a_wi<164> a_wi<163> a_wi<162> a_wi<161> a_wi<160> a_wl_l<175> a_wl_l<174> a_wl_l<173> a_wl_l<172> a_wl_l<171> a_wl_l<170> a_wl_l<169> a_wl_l<168> a_wl_l<167> a_wl_l<166> a_wl_l<165> a_wl_l<164> a_wl_l<163> a_wl_l<162> a_wl_l<161> a_wl_l<160>  VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4
+XA_WLDRV<9> a_wi<159> a_wi<158> a_wi<157> a_wi<156> a_wi<155> a_wi<154> a_wi<153> a_wi<152> a_wi<151> a_wi<150> a_wi<149> a_wi<148> a_wi<147> a_wi<146> a_wi<145> a_wi<144> a_wl_l<159> a_wl_l<158> a_wl_l<157> a_wl_l<156> a_wl_l<155> a_wl_l<154> a_wl_l<153> a_wl_l<152> a_wl_l<151> a_wl_l<150> a_wl_l<149> a_wl_l<148> a_wl_l<147> a_wl_l<146> a_wl_l<145> a_wl_l<144>  VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4
+XA_WLDRV<8> a_wi<143> a_wi<142> a_wi<141> a_wi<140> a_wi<139> a_wi<138> a_wi<137> a_wi<136> a_wi<135> a_wi<134> a_wi<133> a_wi<132> a_wi<131> a_wi<130> a_wi<129> a_wi<128> a_wl_l<143> a_wl_l<142> a_wl_l<141> a_wl_l<140> a_wl_l<139> a_wl_l<138> a_wl_l<137> a_wl_l<136> a_wl_l<135> a_wl_l<134> a_wl_l<133> a_wl_l<132> a_wl_l<131> a_wl_l<130> a_wl_l<129> a_wl_l<128>  VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4
+XA_WLDRV<7> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wl_l<127> a_wl_l<126> a_wl_l<125> a_wl_l<124> a_wl_l<123> a_wl_l<122> a_wl_l<121> a_wl_l<120> a_wl_l<119> a_wl_l<118> a_wl_l<117> a_wl_l<116> a_wl_l<115> a_wl_l<114> a_wl_l<113> a_wl_l<112>  VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4
+XA_WLDRV<6> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wl_l<111> a_wl_l<110> a_wl_l<109> a_wl_l<108> a_wl_l<107> a_wl_l<106> a_wl_l<105> a_wl_l<104> a_wl_l<103> a_wl_l<102> a_wl_l<101> a_wl_l<100> a_wl_l<99> a_wl_l<98> a_wl_l<97> a_wl_l<96>  VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4
+XA_WLDRV<5> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wl_l<95> a_wl_l<94> a_wl_l<93> a_wl_l<92> a_wl_l<91> a_wl_l<90> a_wl_l<89> a_wl_l<88> a_wl_l<87> a_wl_l<86> a_wl_l<85> a_wl_l<84> a_wl_l<83> a_wl_l<82> a_wl_l<81> a_wl_l<80>  VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4
+XA_WLDRV<4> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wl_l<79> a_wl_l<78> a_wl_l<77> a_wl_l<76> a_wl_l<75> a_wl_l<74> a_wl_l<73> a_wl_l<72> a_wl_l<71> a_wl_l<70> a_wl_l<69> a_wl_l<68> a_wl_l<67> a_wl_l<66> a_wl_l<65> a_wl_l<64>  VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4
+XA_WLDRV<3> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48>  VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4
+XA_WLDRV<2> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32>  VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4
+XA_WLDRV<1> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16>  VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4
+XA_WLDRV<0> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0>  VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_WLDRV16X4
+
+
+XA_CTRL a_aclk_n A_BIST_CLK A_BIST_MEN A_BIST_EN A_BIST_REN A_BIST_WEN a_tiel A_CLK A_MEN a_dclk a_eclk a_pulse_h a_pulse_l a_pulse a_rclk A_REN a_cs a_wclk A_WEN VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_CTRL
+
+
+XA_ROWDEC a_addr_row<7> a_addr_row<6> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> a_cs a_eclk a_wi<255> a_wi<254> a_wi<253> a_wi<252> a_wi<251> a_wi<250> a_wi<249> a_wi<248> a_wi<247> a_wi<246> a_wi<245> a_wi<244> a_wi<243> a_wi<242> a_wi<241> a_wi<240> a_wi<239> a_wi<238> a_wi<237> a_wi<236> a_wi<235> a_wi<234> a_wi<233> a_wi<232> a_wi<231> a_wi<230> a_wi<229> a_wi<228> a_wi<227> a_wi<226> a_wi<225> a_wi<224> a_wi<223> a_wi<222> a_wi<221> a_wi<220> a_wi<219> a_wi<218> a_wi<217> a_wi<216> a_wi<215> a_wi<214> a_wi<213> a_wi<212> a_wi<211> a_wi<210> a_wi<209> a_wi<208> a_wi<207> a_wi<206> a_wi<205> a_wi<204> a_wi<203> a_wi<202> a_wi<201> a_wi<200> a_wi<199> a_wi<198> a_wi<197> a_wi<196> a_wi<195> a_wi<194> a_wi<193> a_wi<192> a_wi<191> a_wi<190> a_wi<189> a_wi<188> a_wi<187> a_wi<186> a_wi<185> a_wi<184> a_wi<183> a_wi<182> a_wi<181> a_wi<180> a_wi<179> a_wi<178> a_wi<177> a_wi<176> a_wi<175> a_wi<174> a_wi<173> a_wi<172> a_wi<171> a_wi<170> a_wi<169> a_wi<168> a_wi<167> a_wi<166> a_wi<165> a_wi<164> a_wi<163> a_wi<162> a_wi<161> a_wi<160> a_wi<159> a_wi<158> a_wi<157> a_wi<156> a_wi<155> a_wi<154> a_wi<153> a_wi<152> a_wi<151> a_wi<150> a_wi<149> a_wi<148> a_wi<147> a_wi<146> a_wi<145> a_wi<144> a_wi<143> a_wi<142> a_wi<141> a_wi<140> a_wi<139> a_wi<138> a_wi<137> a_wi<136> a_wi<135> a_wi<134> a_wi<133> a_wi<132> a_wi<131> a_wi<130> a_wi<129> a_wi<128> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_ROWDEC8
+XA_ROWREG a_aclk_n A_ADDR<9> A_ADDR<8> A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> a_addr_row<7> a_addr_row<6> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> A_BIST_ADDR<9> A_BIST_ADDR<8> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_EN VDD! VSS!  / RM_IHPSG13_1024x16_c2_1P_ROWREG8
+XA_COLDEC a_aclk_n A_ADDR<1> A_ADDR<0> a_addr_col<1> a_addr_col<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_EN VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLDEC2
+
+
+XA_DLYH a_pulse a_pulse_h VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_DLY_pcell_2
+XA_DLYL a_pulse_x a_pulse_l VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_DLY_pcell_3
+XA_DLYMUX a_pulse_h A_DLY a_pulse_x VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_DLY_MUX
+
+XCOLCTRL<15> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<15> A_BIST_DIN<15> A_BIST_EN a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> A_BM<15> a_dclk_n_r<7> a_dclk_n_r<8> a_dclk_p_r<7> a_dclk_p_r<8> A_DOUT<15> A_DIN<15> a_rclk_n_r<7> a_rclk_n_r<8> a_rclk_p_r<7> a_rclk_p_r<8> a_tieh<15> a_wclk_n_r<7> a_wclk_n_r<8> a_wclk_p_r<7> a_wclk_p_r<8> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLCTRL2
+XCOLCTRL<14> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<14> A_BIST_DIN<14> A_BIST_EN a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> A_BM<14> a_dclk_n_r<6> a_dclk_n_r<7> a_dclk_p_r<6> a_dclk_p_r<7> A_DOUT<14> A_DIN<14> a_rclk_n_r<6> a_rclk_n_r<7> a_rclk_p_r<6> a_rclk_p_r<7> a_tieh<14> a_wclk_n_r<6> a_wclk_n_r<7> a_wclk_p_r<6> a_wclk_p_r<7> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLCTRL2
+XCOLCTRL<13> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<13> A_BIST_DIN<13> A_BIST_EN a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> A_BM<13> a_dclk_n_r<5> a_dclk_n_r<6> a_dclk_p_r<5> a_dclk_p_r<6> A_DOUT<13> A_DIN<13> a_rclk_n_r<5> a_rclk_n_r<6> a_rclk_p_r<5> a_rclk_p_r<6> a_tieh<13> a_wclk_n_r<5> a_wclk_n_r<6> a_wclk_p_r<5> a_wclk_p_r<6> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLCTRL2
+XCOLCTRL<12> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<12> A_BIST_DIN<12> A_BIST_EN a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> A_BM<12> a_dclk_n_r<4> a_dclk_n_r<5> a_dclk_p_r<4> a_dclk_p_r<5> A_DOUT<12> A_DIN<12> a_rclk_n_r<4> a_rclk_n_r<5> a_rclk_p_r<4> a_rclk_p_r<5> a_tieh<12> a_wclk_n_r<4> a_wclk_n_r<5> a_wclk_p_r<4> a_wclk_p_r<5> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLCTRL2
+XCOLCTRL<11> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<11> A_BIST_DIN<11> A_BIST_EN a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> A_BM<11> a_dclk_n_r<3> a_dclk_n_r<4> a_dclk_p_r<3> a_dclk_p_r<4> A_DOUT<11> A_DIN<11> a_rclk_n_r<3> a_rclk_n_r<4> a_rclk_p_r<3> a_rclk_p_r<4> a_tieh<11> a_wclk_n_r<3> a_wclk_n_r<4> a_wclk_p_r<3> a_wclk_p_r<4> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLCTRL2
+XCOLCTRL<10> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<10> A_BIST_DIN<10> A_BIST_EN a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> A_BM<10> a_dclk_n_r<2> a_dclk_n_r<3> a_dclk_p_r<2> a_dclk_p_r<3> A_DOUT<10> A_DIN<10> a_rclk_n_r<2> a_rclk_n_r<3> a_rclk_p_r<2> a_rclk_p_r<3> a_tieh<10> a_wclk_n_r<2> a_wclk_n_r<3> a_wclk_p_r<2> a_wclk_p_r<3> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLCTRL2
+XCOLCTRL<9> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<9> A_BIST_DIN<9> A_BIST_EN a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> A_BM<9> a_dclk_n_r<1> a_dclk_n_r<2> a_dclk_p_r<1> a_dclk_p_r<2> A_DOUT<9> A_DIN<9> a_rclk_n_r<1> a_rclk_n_r<2> a_rclk_p_r<1> a_rclk_p_r<2> a_tieh<9> a_wclk_n_r<1> a_wclk_n_r<2> a_wclk_p_r<1> a_wclk_p_r<2> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLCTRL2
+XCOLCTRL<8> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<8> A_BIST_DIN<8> A_BIST_EN a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> A_BM<8> a_dclk_n_r<0> a_dclk_n_r<1> a_dclk_p_r<0> a_dclk_p_r<1> A_DOUT<8> A_DIN<8> a_rclk_n_r<0> a_rclk_n_r<1> a_rclk_p_r<0> a_rclk_p_r<1> a_tieh<8> a_wclk_n_r<0> a_wclk_n_r<1> a_wclk_p_r<0> a_wclk_p_r<1> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLCTRL2
+XCOLCTRL<7> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<0> A_BIST_DIN<0> A_BIST_EN a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> A_BM<0> a_dclk_n_l<7> a_dclk_n_l<8> a_dclk_p_l<7> a_dclk_p_l<8> A_DOUT<0> A_DIN<0> a_rclk_n_l<7> a_rclk_n_l<8> a_rclk_p_l<7> a_rclk_p_l<8> a_tieh<0> a_wclk_n_l<7> a_wclk_n_l<8> a_wclk_p_l<7> a_wclk_p_l<8> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLCTRL2
+XCOLCTRL<6> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<1> A_BIST_DIN<1> A_BIST_EN a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> A_BM<1> a_dclk_n_l<6> a_dclk_n_l<7> a_dclk_p_l<6> a_dclk_p_l<7> A_DOUT<1> A_DIN<1> a_rclk_n_l<6> a_rclk_n_l<7> a_rclk_p_l<6> a_rclk_p_l<7> a_tieh<1> a_wclk_n_l<6> a_wclk_n_l<7> a_wclk_p_l<6> a_wclk_p_l<7> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLCTRL2
+XCOLCTRL<5> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<2> A_BIST_DIN<2> A_BIST_EN a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> A_BM<2> a_dclk_n_l<5> a_dclk_n_l<6> a_dclk_p_l<5> a_dclk_p_l<6> A_DOUT<2> A_DIN<2> a_rclk_n_l<5> a_rclk_n_l<6> a_rclk_p_l<5> a_rclk_p_l<6> a_tieh<2> a_wclk_n_l<5> a_wclk_n_l<6> a_wclk_p_l<5> a_wclk_p_l<6> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLCTRL2
+XCOLCTRL<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<3> A_BIST_DIN<3> A_BIST_EN a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> A_BM<3> a_dclk_n_l<4> a_dclk_n_l<5> a_dclk_p_l<4> a_dclk_p_l<5> A_DOUT<3> A_DIN<3> a_rclk_n_l<4> a_rclk_n_l<5> a_rclk_p_l<4> a_rclk_p_l<5> a_tieh<3> a_wclk_n_l<4> a_wclk_n_l<5> a_wclk_p_l<4> a_wclk_p_l<5> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLCTRL2
+XCOLCTRL<3> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<4> A_BIST_DIN<4> A_BIST_EN a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> A_BM<4> a_dclk_n_l<3> a_dclk_n_l<4> a_dclk_p_l<3> a_dclk_p_l<4> A_DOUT<4> A_DIN<4> a_rclk_n_l<3> a_rclk_n_l<4> a_rclk_p_l<3> a_rclk_p_l<4> a_tieh<4> a_wclk_n_l<3> a_wclk_n_l<4> a_wclk_p_l<3> a_wclk_p_l<4> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLCTRL2
+XCOLCTRL<2> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<5> A_BIST_DIN<5> A_BIST_EN a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> A_BM<5> a_dclk_n_l<2> a_dclk_n_l<3> a_dclk_p_l<2> a_dclk_p_l<3> A_DOUT<5> A_DIN<5> a_rclk_n_l<2> a_rclk_n_l<3> a_rclk_p_l<2> a_rclk_p_l<3> a_tieh<5> a_wclk_n_l<2> a_wclk_n_l<3> a_wclk_p_l<2> a_wclk_p_l<3> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLCTRL2
+XCOLCTRL<1> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<6> A_BIST_DIN<6> A_BIST_EN a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> A_BM<6> a_dclk_n_l<1> a_dclk_n_l<2> a_dclk_p_l<1> a_dclk_p_l<2> A_DOUT<6> A_DIN<6> a_rclk_n_l<1> a_rclk_n_l<2> a_rclk_p_l<1> a_rclk_p_l<2> a_tieh<6> a_wclk_n_l<1> a_wclk_n_l<2> a_wclk_p_l<1> a_wclk_p_l<2> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLCTRL2
+XCOLCTRL<0> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<7> A_BIST_DIN<7> A_BIST_EN a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> A_BM<7> a_dclk_n_l<0> a_dclk_n_l<1> a_dclk_p_l<0> a_dclk_p_l<1> A_DOUT<7> A_DIN<7> a_rclk_n_l<0> a_rclk_n_l<1> a_rclk_p_l<0> a_rclk_p_l<1> a_tieh<7> a_wclk_n_l<0> a_wclk_n_l<1> a_wclk_p_l<0> a_wclk_p_l<1> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLCTRL2
+
+
+XDRVFILL4<1> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLDRV13_FILL4
+XDRVFILL4<2> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLDRV13_FILL4
+XCOLFILL4<1> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLDRV13_FILL4C2
+XCOLFILL4<2> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLDRV13_FILL4C2
+XCOLFILL4<3> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLDRV13_FILL4C2
+XCOLFILL4<4> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLDRV13_FILL4C2
+XCOLFILL4<5> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLDRV13_FILL4C2
+XCOLFILL4<6> VDD! VSS! / RM_IHPSG13_1024x16_c2_1P_COLDRV13_FILL4C2
+.ENDS
diff --git a/ihp-sg13g2/libs.ref/sg13g2_sram/cdl/RM_IHPSG13_1P_1024x8_c2_bm_bist.cdl b/ihp-sg13g2/libs.ref/sg13g2_sram/cdl/RM_IHPSG13_1P_1024x8_c2_bm_bist.cdl
new file mode 100644
index 00000000..97f55918
--- /dev/null
+++ b/ihp-sg13g2/libs.ref/sg13g2_sram/cdl/RM_IHPSG13_1P_1024x8_c2_bm_bist.cdl
@@ -0,0 +1,6375 @@
+* ------------------------------------------------------
+*
+*		Copyright 2024 IHP PDK Authors
+*
+*		Licensed under the Apache License, Version 2.0 (the "License");
+*		you may not use this file except in compliance with the License.
+*		You may obtain a copy of the License at
+*		
+*		   https://www.apache.org/licenses/LICENSE-2.0
+*		
+*		Unless required by applicable law or agreed to in writing, software
+*		distributed under the License is distributed on an "AS IS" BASIS,
+*		WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+*		See the License for the specific language governing permissions and
+*		limitations under the License.
+*		
+*		Generated on Fri Jul 19 09:01:22 2024		
+*
+* ------------------------------------------------------ 
+
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_BITKIT_CORNER NW PW VDD VSS
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_CORNER VDD_CORE VSS
+XI16 VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_1P_BITKIT_CORNER
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_LR LWL NW PW VDD VSS
+MN1 VSS LWL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MN0 VSS net9 VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> 
++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> 
++ A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS
+XI0<15> A_WL<15> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_LR
+XI0<14> A_WL<14> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_LR
+XI0<13> A_WL<13> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_LR
+XI0<12> A_WL<12> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_LR
+XI0<11> A_WL<11> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_LR
+XI0<10> A_WL<10> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_LR
+XI0<9> A_WL<9> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_LR
+XI0<8> A_WL<8> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_LR
+XI0<7> A_WL<7> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_LR
+XI0<6> A_WL<6> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_LR
+XI0<5> A_WL<5> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_LR
+XI0<4> A_WL<4> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_LR
+XI0<3> A_WL<3> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_LR
+XI0<2> A_WL<2> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_LR
+XI0<1> A_WL<1> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_LR
+XI0<0> A_WL<0> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_LR
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL BLC_BOT BLC_TOP BLT_BOT BLT_TOP LWL NW PW 
++ RWL VDD VSS
+MN0 NC NT VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MN1 NT NC VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MN3 NC RWL BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MN2 BLT_BOT LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0
+MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0
+R1 BLC_BOT BLC_TOP lvsres w=2.6e-07 l=6e-07
+R0 BLT_BOT BLT_TOP lvsres w=2.6e-07 l=6e-07
+R2 RWL LWL lvsres w=2.6e-07 l=6e-07
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> 
++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> 
++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> 
++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> 
++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> 
++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE 
++ VSS
+XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_RWL<15> 
++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL
+XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_RWL<14> VDD_CORE 
++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL
+XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_RWL<13> VDD_CORE 
++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL
+XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_RWL<12> VDD_CORE 
++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL
+XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_RWL<11> VDD_CORE 
++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL
+XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_RWL<10> VDD_CORE 
++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL
+XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_RWL<9> VDD_CORE 
++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL
+XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_RWL<8> VDD_CORE 
++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL
+XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_RWL<7> VDD_CORE 
++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL
+XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_RWL<6> VDD_CORE 
++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL
+XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_RWL<5> VDD_CORE 
++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL
+XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_RWL<4> VDD_CORE 
++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL
+XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_RWL<3> VDD_CORE 
++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL
+XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_RWL<2> VDD_CORE 
++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL
+XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_RWL<1> VDD_CORE 
++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL
+XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_RWL<0> VDD_CORE 
++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL
+XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> 
++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL
+XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> VDD_CORE 
++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL
+XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> VDD_CORE 
++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL
+XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> VDD_CORE 
++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL
+XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> VDD_CORE 
++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL
+XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> VDD_CORE 
++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL
+XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> VDD_CORE 
++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL
+XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> VDD_CORE 
++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL
+XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> VDD_CORE 
++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL
+XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> VDD_CORE 
++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL
+XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> VDD_CORE 
++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL
+XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> VDD_CORE 
++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL
+XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> VDD_CORE 
++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL
+XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> VDD_CORE 
++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL
+XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> VDD_CORE 
++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL
+XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> VDD_CORE 
++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_CELL
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_TB BLC BLT NW PW VDD VSS
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> 
++ VDD_CORE VSS
+XEDGE<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_TB
+XEDGE<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_TB
+.ENDS
+
+.SUBCKT RSC_IHPSG13_CBUFX4 A Z VDD VSS
+MN0 net9 A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN1 Z net9 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0
+MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP1 Z net9 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> 
++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> 
++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> 
++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> 
++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O 
++ VDD VSS
+XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4
+XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4
+XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4
+.ENDS
+.SUBCKT RSC_IHPSG13_WLDRVX4 A Z VDD VSS
+MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0
+MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0
+MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> 
++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> 
++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS
+XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4
+.ENDS
+.SUBCKT RSC_IHPSG13_FILLCAP8 VDD VSS
+MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=4.98u l=130.00n ng=6 nrd=0 
++ nrs=0
+MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=6.48u l=385.000n ng=4 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_LHPQX2 CP D Q VDD VSS
+MN3 QIN CPN net14 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0
+MN2 net14 net10 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN5 net21 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN6 QIN CP net21 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 nrs=0
+MN1 net10 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN4 Q QIN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MP2 QIN CP net16 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0
+MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP4 Q QIN VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP3 net10 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 net16 net10 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP6 QIN CPN net20 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP5 net20 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_NAND2X2 A B Z VDD VSS
+MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MN0 Z B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MN1 net7 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_CINVX4 A Z VDD VSS
+MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0
+MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_CINVX2 A Z VDD VSS
+MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0
+MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_INVX2 A Z VDD VSS
+MN0 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_NAND3X2 A B C Z VDD VSS
+MP2 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP0 Z C VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MN1 net12 B net16 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MN0 Z C net12 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MN2 net16 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_NOR3X2 A B C Z VDD VSS
+MP0 net13 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP2 Z C net10 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP1 net10 B net13 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MN1 Z B VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0
+MN0 Z C VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0
+MN2 Z A VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_FILLCAP4 VDD VSS
+MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=130.00n ng=3 nrd=0 
++ nrs=0
+MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=385.000n ng=2 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_MET2RES A B
+R0 B A lvsres w=2.6e-07 l=6e-07
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT 
++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> 
++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS
+XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2
+XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2
+XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2
+XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2
+XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2
+XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2
+XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2
+XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2
+XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4
+XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2
+XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2
+XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2
+XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2
+XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4
+XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES
+XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> 
++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> 
++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> 
++ VDD VSS
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> 
++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> 
++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> 
++ WL_O<0> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04
+.ENDS
+.SUBCKT RSC_IHPSG13_CINVX8 A Z VDD VSS
+MN0 Z A VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0
+MP0 Z A VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_DFNQMX2IX1 BE BI CN D QI QIN VDD VSS
+MN15 net026 BI VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN14 MXI_OUT BE net026 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN1 net025 D VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN0 MXI_OUT BEN net025 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN10 QI CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 nrs=0
+MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN9 net37 MXI_OUT VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN5 QI CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0
+MN4 net25 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN2 QIN QI VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN13 BEN BE VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP15 MXI_OUT BEN net027 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP14 net027 BI VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP1 MXI_OUT BE net024 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP0 net024 D VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP13 BEN BE VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP3 QI CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0
+MP2 net27 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP10 net36 MXI_OUT VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP7 QIN QI VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP9 QI CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 nrs=0
+MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> 
++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> 
++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+.SUBCKT RSC_IHPSG13_CDLYX1 A Z VDD VSS
+MN1 net010 net032 VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 
++ nrd=0 nrs=0
+MN2 net032 A net014 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 
++ nrs=0
+MN0 Z net032 net010 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 
++ nrs=0
+MN3 net014 A VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 
++ nrs=0
+MP1 Z net032 net07 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 
++ nrs=0
+MP3 net011 A VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 
++ nrs=0
+MP0 net07 net032 VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 
++ nrd=0 nrs=0
+MP2 net032 A net011 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_CDLYX1_DUMMY A Z VDD VSS
+MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=300.0n ng=3 nrd=0 
++ nrs=0
+MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=640.00n ng=2 nrd=0 
++ nrs=0
+R0 Z A lvsres w=2.6e-07 l=6e-07
+.ENDS
+
+.SUBCKT RSC_IHPSG13_MX2IX1 A0 A1 S ZN VDD VSS
+MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0
+MP3 ZN SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0
+MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 ZN S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0
+MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN5 SN S VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0
+MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN2 ZN S net13 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0
+MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN0 ZN SN net15 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_DLY_MUX A SEL Z VDD VSS
+XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2
+XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1
+XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1
+XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1
+XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1
+.ENDS
+.SUBCKT RSC_IHPSG13_DFNQX2 CN D Q VDD VSS
+MN0 Q QIN_SL VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN10 QIN_SL CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN9 net37 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN5 QIN_SL CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN4 net25 QI_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN2 QI_SL QIN_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP0 Q QIN_SL VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 
++ nrs=0
+MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP3 QIN_SL CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP2 net27 QI_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP10 net36 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP7 QI_SL QIN_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP9 QIN_SL CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_CNAND2X2 A B Z VDD VSS
+MN0 Z B net6 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MN1 net6 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_CGATEPX4 CP E Q VDD VSS
+MN1 net08 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN2 net019 net08 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN3 QIN CP net019 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0
+MN6 Q net015 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 
++ nrs=0
+MN5 net015 net08 net018 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN8 QIN CPN net023 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN7 net023 E VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN4 net018 CP VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0
+MP3 net08 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP2 QIN CPN net017 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 net017 net08 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0
+MP8 QIN CP net024 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP7 net024 E VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP4 net015 CP VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 
++ nrs=0
+MP6 Q net015 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 
++ nrs=0
+MP5 net015 net08 VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_CBUFX8 A Z VDD VSS
+MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0
+MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0
+MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0
+MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_CDLYX2 A Z VDD VSS
+MN2 net4 A net9 VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0
+MN0 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN1 net9 A VSS VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0
+MP2 net4 A net10 VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0
+MP1 net10 A VDD VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0
+MP0 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_MX2X2 A0 A1 S Z VDD VSS
+MP6 Z net010 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 
++ nrs=0
+MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0
+MP3 net010 SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 net010 S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN6 Z net010 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN5 SN S VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 nrs=0
+MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN2 net010 S net13 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN0 net010 SN net15 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_AND2X2 A B Z VDD VSS
+MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0
+MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0
+MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_TIEL Z VDD VSS
+MN0 Z net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP0 net2 net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_XOR2X2 A B Z VDD VSS
+MP8 net012 B net7 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP7 net011 net3 net012 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP6 Z net012 VDD VDD sg13_lv_pmos m=1 w=1.535u l=130.00n ng=1 nrd=0 
++ nrs=0
+MP2 net7 A VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP4 net011 net7 VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP5 net3 B VDD VDD sg13_lv_pmos m=1 w=580.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN7 net012 B net011 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN6 net7 net3 net012 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN5 Z net012 VSS VSS sg13_lv_nmos m=1 w=775.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN2 net7 A VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN4 net3 B VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN3 net011 net7 VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 
++ nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_OA12X1 A B C Z VDD VSS
+MN2 net7 C VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN3 Z net17 VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN1 net17 B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MN0 net17 A net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MP0 net24 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP3 Z net17 VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 net17 B net24 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP2 net17 C VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I 
++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I 
++ ROW_CS WCLK WE_I VDD VSS
+XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2
+XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2
+XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2
+XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2
+XI77 col_we net9 net016 VDD VSS / RSC_IHPSG13_CNAND2X2
+XI76 col_re net9 net018 VDD VSS / RSC_IHPSG13_CNAND2X2
+XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4
+XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4
+XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8
+XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2
+XI8 net9 net8 VDD VSS / RSC_IHPSG13_CINVX2
+XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2
+XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2
+XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2
+XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2
+XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2
+XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2
+XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL
+XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4
+XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4
+XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4
+XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4
+XI6 PULSE_L PULSE_H net9 VDD VSS / RSC_IHPSG13_XOR2X2
+XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8
+XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8
+XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> 
++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> 
++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS
+XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI1<3> PADR<1> PADR<0> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2
+XI1<2> PADR<1> NADR<0> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2
+XI1<1> NADR<1> PADR<0> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2
+XI1<0> NADR<1> NADR<0> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2
+XI16<37> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<36> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<35> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<34> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<33> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<32> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<31> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<30> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2
+XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2
+XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2
+XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2
+XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL
+XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL
+XI17<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL
+XI17<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL
+XI17<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL
+XI17<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL
+.ENDS
+.SUBCKT RSC_IHPSG13_NOR2X2 A B Z VDD VSS
+MP1 Z B net9 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MN0 Z B VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MN1 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_CINVX4_WN A Z VDD VSS
+MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0
+MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_BLDRV BLC BLC_SEL BLT BLT_SEL PRE_N SEL_P WR_ONE WR_ZERO 
++ VDD VSS
+XCDEC SEL_P WR_ZERO BLC_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2
+XTDEC SEL_P WR_ONE BLT_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2
+MTWN BLT BLT_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MCWN BLC BLC_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MCWP BLC BLC_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 
++ nrd=0 nrs=0
+MTWP BLT BLT_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 
++ nrd=0 nrs=0
+MTSP BLT_SEL SEL_N BLT VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 
++ nrs=0
+MTPR BLT PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 
++ nrs=0
+MCSP BLC_SEL SEL_N BLC VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 
++ nrs=0
+MCPR BLC PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 
++ nrs=0
+XI86 SEL_P SEL_N VDD VSS / RSC_IHPSG13_INVX2
+XTINV BLC_PMOS_DRIVE BLT_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2
+XCINV BLT_PMOS_DRIVE BLC_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2
+.ENDS
+.SUBCKT RSC_IHPSG13_TIEH Z VDD VSS
+MN0 net2 net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP0 Z net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_MET3RES A B
+R0 B A lvsres w=2.6e-07 l=6e-07
+.ENDS
+.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2 CP DN DP QN QP VDD VSS
+MN12 SN RN DIFFP VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0
+MN13 TAIL CP VSS VSS sg13_lv_nmos m=1 w=2.4u l=130.00n ng=2 nrd=0 nrs=0
+MN9 DIFFP DP TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0
+MN10 DIFFN DN TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0
+MN11 RN SN DIFFN VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0
+MN19 net33 SN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN20 QN QP net37 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MN18 net37 RN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN17 QP QN net33 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MP15 SN RN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0
+MP16 RN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0
+MP14 DIFFP CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP12 RN SN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0
+MP13 DIFFN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP11 SN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0
+MP19 QN QP VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0
+MP20 QP SN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0
+MP18 QN RN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0
+MP17 QP QN VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_CBUFX2 A Z VDD VSS
+MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=540.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=1.1u l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_INVX4 A Z VDD VSS
+MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0
+MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> 
++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> 
++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R 
++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R 
++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS
+XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2
+XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2
+XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2
+XA_I44 A_WCLK_B_R A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES
+XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES
+XA_I91 A_RCLK_B_R A_RCLK_B_L / RSC_IHPSG13_MET3RES
+XA_R2 A_RCLK_R A_RCLK_L / RSC_IHPSG13_MET3RES
+XA_I90 A_WCLK_B_R A_WCLK_B_L / RSC_IHPSG13_MET3RES
+XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XA_I78 A_RCLK_B_R A_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XA_I50 A_WCLK_L A_WCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2
+XA_EBUF A_RCLK_R A_RCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_COLDRV13_FILL4 VDD VSS
+XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_COLDRV13_FILL4C2 VDD VSS
+XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> 
++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> 
++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> 
++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS
+XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL
+XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2
+XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net7<0> VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2
+XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2
+XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2
+XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2
+XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2
+XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2
+XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2
+XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2
+XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2
+XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+.SUBCKT RSC_IHPSG13_AND2X4 A B Z VDD VSS
+MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0
+MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0
+MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0
+MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0
+MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> 
++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> 
++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> 
++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> 
++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> 
++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> 
++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L 
++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L 
++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS
+XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2
+XA_I76 A_DO_WRITE_P A_DI_N A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4
+XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4
+XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4
+XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4
+XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4
+XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES
+XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES
+XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES
+XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES
+XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2
+XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> 
++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> 
++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> 
++ BIST_EN_I VDD VSS
+XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL
+XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL
+XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2
+XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net6<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2
+XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2
+XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2
+XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2
+XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2
+XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2
+XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2
+XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2
+XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> 
++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> 
++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> 
++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> 
++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L 
++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O 
++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS
+XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_R A_BM_I A_BM_R net23 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_I70<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XA_I44 A_BM_N A_WCLK_B_R A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_ADDR_DEC<6> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_ADDR_DEC<5> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<4> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES
+XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES
+XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES
+XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2
+XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2
+XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2
+XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_BITKIT_16x2_CORNER VDD_CORE VSS
+XI16 VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_1P_BITKIT_CORNER
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_LR A_WL B_WL NW PW VDD VSS
+MN1 VSS A_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MN0 VSS B_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> 
++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> 
++ A_WL<2> A_WL<1> A_WL<0> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> 
++ B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> 
++ B_WL<1> B_WL<0> VDD_CORE VSS
+XI0<15> A_WL<15> B_WL<15> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_LR
+XI0<14> A_WL<14> B_WL<14> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_LR
+XI0<13> A_WL<13> B_WL<13> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_LR
+XI0<12> A_WL<12> B_WL<12> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_LR
+XI0<11> A_WL<11> B_WL<11> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_LR
+XI0<10> A_WL<10> B_WL<10> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_LR
+XI0<9> A_WL<9> B_WL<9> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_LR
+XI0<8> A_WL<8> B_WL<8> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_LR
+XI0<7> A_WL<7> B_WL<7> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_LR
+XI0<6> A_WL<6> B_WL<6> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_LR
+XI0<5> A_WL<5> B_WL<5> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_LR
+XI0<4> A_WL<4> B_WL<4> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_LR
+XI0<3> A_WL<3> B_WL<3> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_LR
+XI0<2> A_WL<2> B_WL<2> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_LR
+XI0<1> A_WL<1> B_WL<1> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_LR
+XI0<0> A_WL<0> B_WL<0> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_LR
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL A_BLC_BOT A_BLC_TOP A_BLT_BOT A_BLT_TOP 
++ A_LWL A_RWL B_BLC_BOT B_BLC_TOP B_BLT_BOT B_BLT_TOP B_LWL B_RWL NW PW VDD VSS
+MN5 NC B_RWL B_BLC_BOT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MN4 B_BLT_BOT B_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MN0 NC NT VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0
+MN1 NT NC VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0
+MN3 NC A_RWL A_BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MN2 A_BLT_TOP A_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0
+MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0
+R5 B_RWL B_LWL lvsres w=2.6e-07 l=6e-07
+R4 B_BLC_BOT B_BLC_TOP lvsres w=2.6e-07 l=6e-07
+R3 B_BLT_BOT B_BLT_TOP lvsres w=2.6e-07 l=6e-07
+R1 A_BLC_BOT A_BLC_TOP lvsres w=2.6e-07 l=6e-07
+R0 A_BLT_BOT A_BLT_TOP lvsres w=2.6e-07 l=6e-07
+R2 A_RWL A_LWL lvsres w=2.6e-07 l=6e-07
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> 
++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> 
++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> 
++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> 
++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> 
++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> 
++ B_BLC_BOT<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_BOT<1> B_BLT_BOT<0> 
++ B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> 
++ B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> 
++ B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> 
++ B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> 
++ B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS
+XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_XWL<15> A_RWL<15> 
++ B_BLC_TOP<1> B_RBLC<15> B_BLT_TOP<1> B_RBLT<15> B_XWL<15> B_RWL<15> 
++ VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL
+XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_XWL<14> A_RWL<14> 
++ B_RBLC<14> B_RBLC<15> B_RBLT<14> B_RBLT<15> B_XWL<14> B_RWL<14> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL
+XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_XWL<13> A_RWL<13> 
++ B_RBLC<14> B_RBLC<13> B_RBLT<14> B_RBLT<13> B_XWL<13> B_RWL<13> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL
+XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_XWL<12> A_RWL<12> 
++ B_RBLC<12> B_RBLC<13> B_RBLT<12> B_RBLT<13> B_XWL<12> B_RWL<12> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL
+XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_XWL<11> A_RWL<11> 
++ B_RBLC<12> B_RBLC<11> B_RBLT<12> B_RBLT<11> B_XWL<11> B_RWL<11> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL
+XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_XWL<10> A_RWL<10> 
++ B_RBLC<10> B_RBLC<11> B_RBLT<10> B_RBLT<11> B_XWL<10> B_RWL<10> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL
+XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_XWL<9> A_RWL<9> 
++ B_RBLC<10> B_RBLC<9> B_RBLT<10> B_RBLT<9> B_XWL<9> B_RWL<9> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL
+XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_XWL<8> A_RWL<8> B_RBLC<8> 
++ B_RBLC<9> B_RBLT<8> B_RBLT<9> B_XWL<8> B_RWL<8> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL
+XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_XWL<7> A_RWL<7> B_RBLC<8> 
++ B_RBLC<7> B_RBLT<8> B_RBLT<7> B_XWL<7> B_RWL<7> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL
+XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_XWL<6> A_RWL<6> B_RBLC<6> 
++ B_RBLC<7> B_RBLT<6> B_RBLT<7> B_XWL<6> B_RWL<6> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL
+XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_XWL<5> A_RWL<5> B_RBLC<6> 
++ B_RBLC<5> B_RBLT<6> B_RBLT<5> B_XWL<5> B_RWL<5> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL
+XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_XWL<4> A_RWL<4> B_RBLC<4> 
++ B_RBLC<5> B_RBLT<4> B_RBLT<5> B_XWL<4> B_RWL<4> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL
+XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_XWL<3> A_RWL<3> B_RBLC<4> 
++ B_RBLC<3> B_RBLT<4> B_RBLT<3> B_XWL<3> B_RWL<3> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL
+XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_XWL<2> A_RWL<2> B_RBLC<2> 
++ B_RBLC<3> B_RBLT<2> B_RBLT<3> B_XWL<2> B_RWL<2> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL
+XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_XWL<1> A_RWL<1> B_RBLC<2> 
++ B_RBLC<1> B_RBLT<2> B_RBLT<1> B_XWL<1> B_RWL<1> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL
+XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_XWL<0> A_RWL<0> 
++ B_BLC_BOT<1> B_RBLC<1> B_BLT_BOT<1> B_RBLT<1> B_XWL<0> B_RWL<0> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL
+XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> A_XWL<15> 
++ B_BLC_TOP<0> B_LBLC<15> B_BLT_TOP<0> B_LBLT<15> B_LWL<15> B_XWL<15> 
++ VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL
+XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> A_XWL<14> 
++ B_LBLC<14> B_LBLC<15> B_LBLT<14> B_LBLT<15> B_LWL<14> B_XWL<14> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL
+XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> A_XWL<13> 
++ B_LBLC<14> B_LBLC<13> B_LBLT<14> B_LBLT<13> B_LWL<13> B_XWL<13> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL
+XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> A_XWL<12> 
++ B_LBLC<12> B_LBLC<13> B_LBLT<12> B_LBLT<13> B_LWL<12> B_XWL<12> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL
+XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> A_XWL<11> 
++ B_LBLC<12> B_LBLC<11> B_LBLT<12> B_LBLT<11> B_LWL<11> B_XWL<11> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL
+XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> A_XWL<10> 
++ B_LBLC<10> B_LBLC<11> B_LBLT<10> B_LBLT<11> B_LWL<10> B_XWL<10> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL
+XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> A_XWL<9> 
++ B_LBLC<10> B_LBLC<9> B_LBLT<10> B_LBLT<9> B_LWL<9> B_XWL<9> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL
+XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> A_XWL<8> B_LBLC<8> 
++ B_LBLC<9> B_LBLT<8> B_LBLT<9> B_LWL<8> B_XWL<8> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL
+XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> A_XWL<7> B_LBLC<8> 
++ B_LBLC<7> B_LBLT<8> B_LBLT<7> B_LWL<7> B_XWL<7> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL
+XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> A_XWL<6> B_LBLC<6> 
++ B_LBLC<7> B_LBLT<6> B_LBLT<7> B_LWL<6> B_XWL<6> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL
+XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> A_XWL<5> B_LBLC<6> 
++ B_LBLC<5> B_LBLT<6> B_LBLT<5> B_LWL<5> B_XWL<5> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL
+XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> A_XWL<4> B_LBLC<4> 
++ B_LBLC<5> B_LBLT<4> B_LBLT<5> B_LWL<4> B_XWL<4> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL
+XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> A_XWL<3> B_LBLC<4> 
++ B_LBLC<3> B_LBLT<4> B_LBLT<3> B_LWL<3> B_XWL<3> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL
+XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> A_XWL<2> B_LBLC<2> 
++ B_LBLC<3> B_LBLT<2> B_LBLT<3> B_LWL<2> B_XWL<2> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL
+XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> A_XWL<1> B_LBLC<2> 
++ B_LBLC<1> B_LBLT<2> B_LBLT<1> B_LWL<1> B_XWL<1> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL
+XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> A_XWL<0> 
++ B_BLC_BOT<0> B_LBLC<1> B_BLT_BOT<0> B_LBLT<1> B_LWL<0> B_XWL<0> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_CELL
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_TB A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> 
++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS
+XEDGE<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_TB
+XEDGE<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_TB
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_BITKIT_TAP A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> 
++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS
+XIEDGEBP_COL1<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_TB
+XIEDGEBP_COL1<0> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_TB
+XIEDGEBP_COL2<1> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_TB
+XIEDGEBP_COL2<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_EDGE_TB
+XITAP<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_TAP
+XITAP<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_1024x8_c2_2P_BITKIT_TAP
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_BITKIT_TAP_LR NW PW VDD VSS
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_BITKIT_16x2_TAP_LR VDD_CORE VSS
+XCORNER<1> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_1P_BITKIT_CORNER
+XCORNER<0> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_1P_BITKIT_CORNER
+XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_1P_BITKIT_TAP_LR
+.ENDS
+
+.SUBCKT RSC_IHPSG13_CBUFX12 A Z VDD VSS
+MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=4.23u l=130.00n ng=6 nrd=0 nrs=0
+MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0
+MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0
+MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> 
++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> 
++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> 
++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> 
++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O 
++ VDD VSS
+XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12
+XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12
+XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12
+XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+.SUBCKT RSC_IHPSG13_WLDRVX12 A Z VDD VSS
+MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0
+MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0
+MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0
+MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> 
++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> 
++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS
+XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT 
++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> 
++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS
+XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2
+XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2
+XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2
+XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2
+XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4
+XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2
+XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2
+XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES
+XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES
+XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2
+XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2
+XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4
+XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2
+XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2
+XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2
+XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS
+XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2
+XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2
+XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4
+XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS
+XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2
+XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2
+XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4
+XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS
+XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2
+XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2
+XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS
+XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2
+XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> 
++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I 
++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> 
++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> 
++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> 
++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> 
++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> 
++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> 
++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> 
++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> 
++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> 
++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> 
++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> 
++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> 
++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> 
++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> 
++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> 
++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> 
++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> 
++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> 
++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> 
++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> 
++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> 
++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> 
++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> 
++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> 
++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> 
++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> 
++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> 
++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> 
++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> 
++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> 
++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> 
++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> 
++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> 
++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> 
++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> 
++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> 
++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> 
++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> 
++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> 
++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> 
++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> 
++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> 
++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> 
++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> 
++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> 
++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> 
++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> 
++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> 
++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> 
++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> 
++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> 
++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> 
++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> 
++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> 
++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> 
++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> 
++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> 
++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> 
++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> 
++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> 
++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> 
++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> 
++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> 
++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS
+XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> 
++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> 
++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> 
++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> 
++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> 
++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> 
++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> 
++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> 
++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> 
++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> 
++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> 
++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> 
++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> 
++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> 
++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> 
++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> 
++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> 
++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> 
++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> 
++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> 
++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> 
++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> 
++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> 
++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> 
++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> 
++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> 
++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> 
++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> 
++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> 
++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> 
++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> 
++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> 
++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> 
++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> 
++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> 
++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> 
++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> 
++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> 
++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> 
++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> 
++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> 
++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> 
++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> 
++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> 
++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> 
++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> 
++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> 
++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> 
++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> 
++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> 
++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> 
++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> 
++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> 
++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> 
++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> 
++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> 
++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> 
++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> 
++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> 
++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> 
++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> 
++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> 
++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> 
++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> 
++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> 
++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> 
++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> 
++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> 
++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> 
++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> 
++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> 
++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> 
++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> 
++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> 
++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> 
++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> 
++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> 
++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> 
++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> 
++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> 
++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> 
++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> 
++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> 
++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> 
++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> 
++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> 
++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04
+XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC02
+XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC02
+XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC02
+XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC02
+XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC02
+XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC02
+XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC02
+XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC02
+XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC02
+XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC02
+XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC01
+XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC01
+XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC01
+XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC01
+XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC01
+XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC01
+XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC01
+XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC01
+XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC01
+XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC01
+XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC01
+XL2<258> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<257> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<256> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<255> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<254> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<253> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<252> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<251> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<250> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<249> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<248> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<247> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<246> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<245> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<244> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<243> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<242> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<241> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<240> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<239> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<238> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<237> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<236> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<235> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<234> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<233> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<232> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<231> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<230> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<229> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<228> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<227> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<226> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<225> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<224> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<223> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<222> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<221> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<220> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<219> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<218> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<217> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<216> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<215> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<214> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<213> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<212> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<211> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<210> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<209> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<208> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<207> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<206> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<205> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<204> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<203> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<202> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<201> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<200> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<199> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<198> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<197> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<196> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<195> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<194> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<193> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<192> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<191> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<190> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<189> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<188> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<187> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<186> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<185> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<184> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<183> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<182> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<181> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<180> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<179> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<178> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<177> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<176> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<175> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<174> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<173> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC00
+XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC00
+XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC00
+XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC00
+XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC00
+XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC00
+XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC00
+XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC00
+XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC00
+XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC00
+XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC00
+XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC03
+XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC03
+XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC03
+XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC03
+XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC03
+XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC03
+XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC03
+XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC03
+XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC03
+XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC03
+XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> 
++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> 
++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> 
++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> 
++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> 
++ BIST_EN_I VDD VSS
+XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+.ENDS
+
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_DLY_MUX A SEL Z VDD VSS
+XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2
+XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1
+XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1
+XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1
+XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I 
++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I 
++ ROW_CS WCLK WE_I VDD VSS
+XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2
+XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2
+XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2
+XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2
+XI77 col_we net017 net016 VDD VSS / RSC_IHPSG13_CNAND2X2
+XI76 col_re net017 net018 VDD VSS / RSC_IHPSG13_CNAND2X2
+XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4
+XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4
+XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8
+XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2
+XI8 net017 net8 VDD VSS / RSC_IHPSG13_CINVX2
+XCAPS4<7> VDD VSS / RSC_IHPSG13_FILLCAP4
+XCAPS4<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XCAPS4<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XCAPS4<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XCAPS4<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XCAPS4<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XCAPS4<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL
+XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2
+XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2
+XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2
+XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2
+XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2
+XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4
+XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4
+XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4
+XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4
+XCAPS8<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XCAPS8<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XCAPS8<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XCAPS8<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XCAPS8<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XCAPS8<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XCAPS8<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI6 PULSE_L PULSE_H net017 VDD VSS / RSC_IHPSG13_XOR2X2
+XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2
+XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8
+XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8
+XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> 
++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> 
++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> 
++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS
+XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2
+XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net13<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net13<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2
+XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2
+XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2
+XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2
+XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2
+XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2
+XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2
+XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2
+XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2
+XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2
+XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_BLDRV A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL 
++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> 
++ A_SEL_P<1> A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> 
++ B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> 
++ B_SEL_P<2> B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS
+MA_CWN<3> A_BLC<3> A_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MA_CWN<2> A_BLC<2> A_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MA_CWN<1> A_BLC<1> A_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MA_CWN<0> A_BLC<0> A_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MA_TWN<3> A_BLT<3> A_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MA_TWN<2> A_BLT<2> A_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MA_TWN<1> A_BLT<1> A_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MA_TWN<0> A_BLT<0> A_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MB_TWN<3> B_BLT<3> B_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MB_TWN<2> B_BLT<2> B_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MB_TWN<1> B_BLT<1> B_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MB_TWN<0> B_BLT<0> B_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MB_CWN<3> B_BLC<3> B_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MB_CWN<2> B_BLC<2> B_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MB_CWN<1> B_BLC<1> B_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MB_CWN<0> B_BLC<0> B_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MA_CPR<3> A_BLC<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MA_CPR<2> A_BLC<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MA_CPR<1> A_BLC<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MA_CPR<0> A_BLC<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MA_TWP<3> A_BLT<3> A_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_TWP<2> A_BLT<2> A_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_TWP<1> A_BLT<1> A_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_TWP<0> A_BLT<0> A_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_CWP<3> A_BLC<3> A_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_CWP<2> A_BLC<2> A_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_CWP<1> A_BLC<1> A_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_CWP<0> A_BLC<0> A_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_TPR<3> A_BLT<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MA_TPR<2> A_BLT<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MA_TPR<1> A_BLT<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MA_TPR<0> A_BLT<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MA_TSP<3> A_BLT_SEL A_SEL_N<3> A_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_TSP<2> A_BLT_SEL A_SEL_N<2> A_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_TSP<1> A_BLT_SEL A_SEL_N<1> A_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_TSP<0> A_BLT_SEL A_SEL_N<0> A_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_CSP<3> A_BLC_SEL A_SEL_N<3> A_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_CSP<2> A_BLC_SEL A_SEL_N<2> A_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_CSP<1> A_BLC_SEL A_SEL_N<1> A_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_CSP<0> A_BLC_SEL A_SEL_N<0> A_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_CWP<3> B_BLC<3> B_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_CWP<2> B_BLC<2> B_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_CWP<1> B_BLC<1> B_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_CWP<0> B_BLC<0> B_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_TWP<3> B_BLT<3> B_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_TWP<2> B_BLT<2> B_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_TWP<1> B_BLT<1> B_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_TWP<0> B_BLT<0> B_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_TSP<3> B_BLT_SEL B_SEL_N<3> B_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_TSP<2> B_BLT_SEL B_SEL_N<2> B_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_TSP<1> B_BLT_SEL B_SEL_N<1> B_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_TSP<0> B_BLT_SEL B_SEL_N<0> B_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_TPR<3> B_BLT<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MB_TPR<2> B_BLT<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MB_TPR<1> B_BLT<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MB_TPR<0> B_BLT<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MB_CSP<3> B_BLC_SEL B_SEL_N<3> B_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_CSP<2> B_BLC_SEL B_SEL_N<2> B_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_CSP<1> B_BLC_SEL B_SEL_N<1> B_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_CSP<0> B_BLC_SEL B_SEL_N<0> B_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_CPR<3> B_BLC<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MB_CPR<2> B_BLC<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MB_CPR<1> B_BLC<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MB_CPR<0> B_BLC<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+XA_SEL<3> A_SEL_P<3> A_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2
+XA_SEL<2> A_SEL_P<2> A_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2
+XA_SEL<1> A_SEL_P<1> A_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2
+XA_SEL<0> A_SEL_P<0> A_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2
+XA_CINV<3> A_BLT_PMOS_DRIVE<3> A_BLC_NMOS_DRIVE<3> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XA_CINV<2> A_BLT_PMOS_DRIVE<2> A_BLC_NMOS_DRIVE<2> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XA_CINV<1> A_BLT_PMOS_DRIVE<1> A_BLC_NMOS_DRIVE<1> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XA_CINV<0> A_BLT_PMOS_DRIVE<0> A_BLC_NMOS_DRIVE<0> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XA_TINV<3> A_BLC_PMOS_DRIVE<3> A_BLT_NMOS_DRIVE<3> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XA_TINV<2> A_BLC_PMOS_DRIVE<2> A_BLT_NMOS_DRIVE<2> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XA_TINV<1> A_BLC_PMOS_DRIVE<1> A_BLT_NMOS_DRIVE<1> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XA_TINV<0> A_BLC_PMOS_DRIVE<0> A_BLT_NMOS_DRIVE<0> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XB_SEL<3> B_SEL_P<3> B_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2
+XB_SEL<2> B_SEL_P<2> B_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2
+XB_SEL<1> B_SEL_P<1> B_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2
+XB_SEL<0> B_SEL_P<0> B_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2
+XB_TINV<3> B_BLC_PMOS_DRIVE<3> B_BLT_NMOS_DRIVE<3> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XB_TINV<2> B_BLC_PMOS_DRIVE<2> B_BLT_NMOS_DRIVE<2> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XB_TINV<1> B_BLC_PMOS_DRIVE<1> B_BLT_NMOS_DRIVE<1> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XB_TINV<0> B_BLC_PMOS_DRIVE<0> B_BLT_NMOS_DRIVE<0> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XB_CINV<3> B_BLT_PMOS_DRIVE<3> B_BLC_NMOS_DRIVE<3> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XB_CINV<2> B_BLT_PMOS_DRIVE<2> B_BLC_NMOS_DRIVE<2> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XB_CINV<1> B_BLT_PMOS_DRIVE<1> B_BLC_NMOS_DRIVE<1> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XB_CINV<0> B_BLT_PMOS_DRIVE<0> B_BLC_NMOS_DRIVE<0> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XA_TDEC<3> A_SEL_P<3> A_WR_ONE A_BLT_PMOS_DRIVE<3> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XA_TDEC<2> A_SEL_P<2> A_WR_ONE A_BLT_PMOS_DRIVE<2> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XA_TDEC<1> A_SEL_P<1> A_WR_ONE A_BLT_PMOS_DRIVE<1> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XA_TDEC<0> A_SEL_P<0> A_WR_ONE A_BLT_PMOS_DRIVE<0> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XA_CDEC<3> A_SEL_P<3> A_WR_ZERO A_BLC_PMOS_DRIVE<3> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XA_CDEC<2> A_SEL_P<2> A_WR_ZERO A_BLC_PMOS_DRIVE<2> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XA_CDEC<1> A_SEL_P<1> A_WR_ZERO A_BLC_PMOS_DRIVE<1> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XA_CDEC<0> A_SEL_P<0> A_WR_ZERO A_BLC_PMOS_DRIVE<0> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XB_CDEC<3> B_SEL_P<3> B_WR_ZERO B_BLC_PMOS_DRIVE<3> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XB_CDEC<2> B_SEL_P<2> B_WR_ZERO B_BLC_PMOS_DRIVE<2> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XB_CDEC<1> B_SEL_P<1> B_WR_ZERO B_BLC_PMOS_DRIVE<1> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XB_CDEC<0> B_SEL_P<0> B_WR_ZERO B_BLC_PMOS_DRIVE<0> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XB_TDEC<3> B_SEL_P<3> B_WR_ONE B_BLT_PMOS_DRIVE<3> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XB_TDEC<2> B_SEL_P<2> B_WR_ONE B_BLT_PMOS_DRIVE<2> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XB_TDEC<1> B_SEL_P<1> B_WR_ONE B_BLT_PMOS_DRIVE<1> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XB_TDEC<0> B_SEL_P<0> B_WR_ONE B_BLT_PMOS_DRIVE<0> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+.ENDS
+.SUBCKT RSC_IHPSG13_AND2X6 A B Z VDD VSS
+MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=2.94u l=130.00n ng=3 nrd=0 nrs=0
+MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0
+MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0
+MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=4.86u l=130.00n ng=3 nrd=0 nrs=0
+MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> 
++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> 
++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> 
++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> 
++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> 
++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> 
++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> 
++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> 
++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> 
++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> 
++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> 
++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R 
++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R 
++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL<1> B_ADDR_COL<0> 
++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> 
++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I 
++ B_BIST_EN_I B_BLC<31> B_BLC<30> B_BLC<29> B_BLC<28> B_BLC<27> B_BLC<26> 
++ B_BLC<25> B_BLC<24> B_BLC<23> B_BLC<22> B_BLC<21> B_BLC<20> B_BLC<19> 
++ B_BLC<18> B_BLC<17> B_BLC<16> B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> 
++ B_BLC<11> B_BLC<10> B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> 
++ B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> 
++ B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT<23> B_BLT<22> B_BLT<21> 
++ B_BLT<20> B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT<15> B_BLT<14> 
++ B_BLT<13> B_BLT<12> B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> 
++ B_BLT<5> B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L 
++ B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L 
++ B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS
+XB_I80<1> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<1> VDD VSS / 
++ RSC_IHPSG13_AND2X2
+XB_I80<0> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<0> VDD VSS / 
++ RSC_IHPSG13_AND2X2
+XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / 
++ RSC_IHPSG13_AND2X2
+XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / 
++ RSC_IHPSG13_AND2X2
+XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XB_INV<6> B_N1<1> B_P1<1> VDD VSS / RSC_IHPSG13_CINVX4
+XB_INV<5> B_N0<1> B_P0<1> VDD VSS / RSC_IHPSG13_CINVX4
+XB_INV<4> B_N0<0> B_P0<0> VDD VSS / RSC_IHPSG13_CINVX4
+XB_INV<3> B_ADDR_COL<1> B_N1<1> VDD VSS / RSC_IHPSG13_CINVX4
+XB_INV<2> B_ADDR_COL<1> B_N1<0> VDD VSS / RSC_IHPSG13_CINVX4
+XB_INV<1> B_ADDR_COL<0> B_N0<1> VDD VSS / RSC_IHPSG13_CINVX4
+XB_INV<0> B_ADDR_COL<0> B_N0<0> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4
+XB_I81<3> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XB_I81<2> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XB_I81<1> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XB_I81<0> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XI_FILL8<78> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<77> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<76> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<75> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<74> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<73> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<72> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<71> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<70> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<69> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<68> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<67> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<66> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<65> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<64> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<63> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<62> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<61> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<60> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<59> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<58> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<57> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<56> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<55> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<54> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<53> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<52> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<51> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<50> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<49> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<48> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<47> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<46> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<45> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<44> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<43> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<42> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<41> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<40> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<39> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<38> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<37> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<36> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<35> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<34> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<33> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<32> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<31> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<30> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XAB_BLMUX<7> A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC_SEL A_BLT<31> 
++ A_BLT<30> A_BLT<29> A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<31> A_SEL_P<30> 
++ A_SEL_P<29> A_SEL_P<28> A_WR_ONE A_WR_ZERO B_BLC<31> B_BLC<30> B_BLC<29> 
++ B_BLC<28> B_BLC_SEL B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> B_BLT_SEL 
++ B_PRE_N B_SEL_P<31> B_SEL_P<30> B_SEL_P<29> B_SEL_P<28> B_WR_ONE B_WR_ZERO 
++ VDD VSS / RM_IHPSG13_1024x8_c2_2P_BLDRV
+XAB_BLMUX<6> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC_SEL A_BLT<27> 
++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<27> A_SEL_P<26> 
++ A_SEL_P<25> A_SEL_P<24> A_WR_ONE A_WR_ZERO B_BLC<27> B_BLC<26> B_BLC<25> 
++ B_BLC<24> B_BLC_SEL B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT_SEL 
++ B_PRE_N B_SEL_P<27> B_SEL_P<26> B_SEL_P<25> B_SEL_P<24> B_WR_ONE B_WR_ZERO 
++ VDD VSS / RM_IHPSG13_1024x8_c2_2P_BLDRV
+XAB_BLMUX<5> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC_SEL A_BLT<23> 
++ A_BLT<22> A_BLT<21> A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<23> A_SEL_P<22> 
++ A_SEL_P<21> A_SEL_P<20> A_WR_ONE A_WR_ZERO B_BLC<23> B_BLC<22> B_BLC<21> 
++ B_BLC<20> B_BLC_SEL B_BLT<23> B_BLT<22> B_BLT<21> B_BLT<20> B_BLT_SEL 
++ B_PRE_N B_SEL_P<23> B_SEL_P<22> B_SEL_P<21> B_SEL_P<20> B_WR_ONE B_WR_ZERO 
++ VDD VSS / RM_IHPSG13_1024x8_c2_2P_BLDRV
+XAB_BLMUX<4> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC_SEL A_BLT<19> 
++ A_BLT<18> A_BLT<17> A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<19> A_SEL_P<18> 
++ A_SEL_P<17> A_SEL_P<16> A_WR_ONE A_WR_ZERO B_BLC<19> B_BLC<18> B_BLC<17> 
++ B_BLC<16> B_BLC_SEL B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT_SEL 
++ B_PRE_N B_SEL_P<19> B_SEL_P<18> B_SEL_P<17> B_SEL_P<16> B_WR_ONE B_WR_ZERO 
++ VDD VSS / RM_IHPSG13_1024x8_c2_2P_BLDRV
+XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> 
++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> 
++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> 
++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL 
++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO 
++ VDD VSS / RM_IHPSG13_1024x8_c2_2P_BLDRV
+XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> 
++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> 
++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> 
++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N 
++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD 
++ VSS / RM_IHPSG13_1024x8_c2_2P_BLDRV
+XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> 
++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> 
++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL 
++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> 
++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_BLDRV
+XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> 
++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> 
++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL 
++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> 
++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_BLDRV
+XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8
+XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8
+XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8
+XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8
+XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8
+XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8
+XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6
+XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6
+XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6
+XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6
+XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<31> net041<0> B_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<30> net041<1> B_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<29> net041<2> B_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<28> net041<3> B_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<27> net041<4> B_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<26> net041<5> B_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<25> net041<6> B_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<24> net041<7> B_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<23> net041<8> B_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<22> net041<9> B_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<21> net041<10> B_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<20> net041<11> B_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<19> net041<12> B_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<18> net041<13> B_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<17> net041<14> B_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<16> net041<15> B_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<15> net041<16> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<14> net041<17> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<13> net041<18> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<12> net041<19> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<11> net041<20> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<10> net041<21> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<9> net041<22> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<8> net041<23> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<7> net041<24> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<6> net041<25> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<5> net041<26> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<4> net041<27> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<3> net041<28> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<2> net041<29> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<1> net041<30> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<0> net041<31> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2
+XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2
+XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net042 VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XB_DEC3<31> B_P1<1> B_P0<1> B_ADDR_DEC<7> net041<0> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<30> B_P1<1> B_P0<1> B_ADDR_DEC<6> net041<1> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<29> B_P1<1> B_P0<1> B_ADDR_DEC<5> net041<2> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<28> B_P1<1> B_P0<1> B_ADDR_DEC<4> net041<3> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<27> B_P1<1> B_P0<1> B_ADDR_DEC<3> net041<4> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<26> B_P1<1> B_P0<1> B_ADDR_DEC<2> net041<5> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<25> B_P1<1> B_P0<1> B_ADDR_DEC<1> net041<6> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<24> B_P1<1> B_P0<1> B_ADDR_DEC<0> net041<7> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<23> B_P1<1> B_N0<1> B_ADDR_DEC<7> net041<8> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<22> B_P1<1> B_N0<1> B_ADDR_DEC<6> net041<9> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<21> B_P1<1> B_N0<1> B_ADDR_DEC<5> net041<10> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<20> B_P1<1> B_N0<1> B_ADDR_DEC<4> net041<11> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<19> B_P1<1> B_N0<1> B_ADDR_DEC<3> net041<12> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<18> B_P1<1> B_N0<1> B_ADDR_DEC<2> net041<13> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<17> B_P1<1> B_N0<1> B_ADDR_DEC<1> net041<14> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<16> B_P1<1> B_N0<1> B_ADDR_DEC<0> net041<15> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<15> B_N1<0> B_P0<0> B_ADDR_DEC<7> net041<16> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<14> B_N1<0> B_P0<0> B_ADDR_DEC<6> net041<17> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<13> B_N1<0> B_P0<0> B_ADDR_DEC<5> net041<18> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<12> B_N1<0> B_P0<0> B_ADDR_DEC<4> net041<19> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<11> B_N1<0> B_P0<0> B_ADDR_DEC<3> net041<20> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<10> B_N1<0> B_P0<0> B_ADDR_DEC<2> net041<21> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<9> B_N1<0> B_P0<0> B_ADDR_DEC<1> net041<22> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<8> B_N1<0> B_P0<0> B_ADDR_DEC<0> net041<23> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<7> B_N1<0> B_N0<0> B_ADDR_DEC<7> net041<24> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<6> B_N1<0> B_N0<0> B_ADDR_DEC<6> net041<25> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<5> B_N1<0> B_N0<0> B_ADDR_DEC<5> net041<26> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<4> B_N1<0> B_N0<0> B_ADDR_DEC<4> net041<27> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<3> B_N1<0> B_N0<0> B_ADDR_DEC<3> net041<28> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<2> B_N1<0> B_N0<0> B_ADDR_DEC<2> net041<29> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<1> B_N1<0> B_N0<0> B_ADDR_DEC<1> net041<30> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<0> B_N1<0> B_N0<0> B_ADDR_DEC<0> net041<31> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES
+XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES
+XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES
+XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES
+XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES
+XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES
+XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_COLDRV13_FILL4 VDD VSS
+XI0<11> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<10> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+
+
+.SUBCKT RSC_IHPSG13_CBUFX16 A Z VDD VSS
+MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=2.115u l=130.00n ng=3 nrd=0 nrs=0
+MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=5.64u l=130.00n ng=8 nrd=0 nrs=0
+MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=13.000u l=130.00n ng=8 nrd=0 
++ nrs=0
+MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=4.89u l=130.00n ng=3 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> 
++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> 
++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> 
++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> 
++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O 
++ VDD VSS
+XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8
+XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16
+XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16
+XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16
+.ENDS
+.SUBCKT RSC_IHPSG13_WLDRVX16 A Z VDD VSS
+MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0
+MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0
+MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=12.96u l=130.00n ng=8 nrd=0 nrs=0
+MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> 
++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> 
++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS
+XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> 
++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> 
++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> 
++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> 
++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O 
++ VDD VSS
+XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4
+XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4
+XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4
+XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI1 VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> 
++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> 
++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS
+XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> 
++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> 
++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> 
++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> 
++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> 
++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> 
++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> 
++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> 
++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> 
++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> 
++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> 
++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> 
++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> 
++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> 
++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> 
++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> 
++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> 
++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> 
++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> 
++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> 
++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> 
++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> 
++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> 
++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> 
++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> 
++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> 
++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> 
++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> 
++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> 
++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> 
++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> 
++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> 
++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> 
++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> 
++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> 
++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> 
++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS
+XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC03
+XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC03
+XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC03
+XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC03
+XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC03
+XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> 
++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> 
++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> 
++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> 
++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> 
++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> 
++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> 
++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> 
++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> 
++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> 
++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> 
++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> 
++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> 
++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> 
++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> 
++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> 
++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> 
++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> 
++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> 
++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> 
++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> 
++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> 
++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> 
++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> 
++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> 
++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> 
++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> 
++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> 
++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> 
++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> 
++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> 
++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> 
++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> 
++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> 
++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> 
++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> 
++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> 
++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> 
++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04
+XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC02
+XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC02
+XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC02
+XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC02
+XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC02
+XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC00
+XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC00
+XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC00
+XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC00
+XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC00
+XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC01
+XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC01
+XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC01
+XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC01
+XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC01
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> 
++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> 
++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> 
++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> 
++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS
+XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI10 VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> 
++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> 
++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> 
++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS
+XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2
+XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net12<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net12<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2
+XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2
+XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2
+XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2
+XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2
+XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2
+XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2
+XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2
+XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2
+XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> 
++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> 
++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> 
++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> 
++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> 
++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> 
++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L 
++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L 
++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL 
++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> 
++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I 
++ B_BIST_EN_I B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> B_BLC<11> B_BLC<10> 
++ B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC<3> B_BLC<2> 
++ B_BLC<1> B_BLC<0> B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT<11> 
++ B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT<3> 
++ B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R 
++ B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L 
++ B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS
+XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2
+XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2
+XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4
+XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4
+XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4
+XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4
+XI_FILL4<26> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<25> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<24> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<23> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<22> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<21> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<20> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<19> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<18> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<17> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4
+XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4
+XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4
+XB_INV<1> B_N0 B_P0 VDD VSS / RSC_IHPSG13_CINVX4
+XB_INV<0> B_ADDR_COL B_N0 VDD VSS / RSC_IHPSG13_CINVX4
+XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4
+XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4
+XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4
+XB_I81<1> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XB_I81<0> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES
+XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES
+XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES
+XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES
+XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES
+XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES
+XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES
+XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES
+XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> 
++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> 
++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> 
++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL 
++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO 
++ VDD VSS / RM_IHPSG13_1024x8_c2_2P_BLDRV
+XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> 
++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> 
++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> 
++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N 
++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD 
++ VSS / RM_IHPSG13_1024x8_c2_2P_BLDRV
+XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> 
++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> 
++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL 
++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> 
++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_BLDRV
+XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> 
++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> 
++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL 
++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> 
++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_BLDRV
+XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2
+XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<15> net044<0> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<14> net044<1> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<13> net044<2> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<12> net044<3> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<11> net044<4> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<10> net044<5> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<9> net044<6> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<8> net044<7> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<7> net044<8> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<6> net044<9> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<5> net044<10> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<4> net044<11> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<3> net044<12> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<2> net044<13> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<1> net044<14> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<0> net044<15> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2
+XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<15> B_P0 B_ADDR_DEC<7> net044<0> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<14> B_P0 B_ADDR_DEC<6> net044<1> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<13> B_P0 B_ADDR_DEC<5> net044<2> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<12> B_P0 B_ADDR_DEC<4> net044<3> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<11> B_P0 B_ADDR_DEC<3> net044<4> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<10> B_P0 B_ADDR_DEC<2> net044<5> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<9> B_P0 B_ADDR_DEC<1> net044<6> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<8> B_P0 B_ADDR_DEC<0> net044<7> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<7> B_N0 B_ADDR_DEC<7> net044<8> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<6> B_N0 B_ADDR_DEC<6> net044<9> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<5> B_N0 B_ADDR_DEC<5> net044<10> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<4> B_N0 B_ADDR_DEC<4> net044<11> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<3> B_N0 B_ADDR_DEC<3> net044<12> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<2> B_N0 B_ADDR_DEC<2> net044<13> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<1> B_N0 B_ADDR_DEC<1> net044<14> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<0> B_N0 B_ADDR_DEC<0> net044<15> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> 
++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS
+XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC00
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04
+XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC01
+XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> 
++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> 
++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> 
++ BIST_EN_I VDD VSS
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> 
++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> 
++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> 
++ BIST_EN_I VDD VSS
+XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2
+XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL
+XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL
+XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2
+XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2
+XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2
+XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2
+XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2
+XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2
+XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2
+XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2
+XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2P CP DN DP QN QP VDD VSS
+XI_AMP CP DN DP QN QP VDD VSS / RSC_IHPSG13_DFPQD_MSAFFX2
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> 
++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> 
++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> 
++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> 
++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L 
++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O 
++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<7> B_ADDR_DEC<6> 
++ B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> 
++ B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<7> B_BLC<6> B_BLC<5> 
++ B_BLC<4> B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<7> B_BLT<6> B_BLT<5> 
++ B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R 
++ B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R 
++ B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS
+XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net044 VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2P
+XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2P
+XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> 
++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> A_ADDR_DEC<6> 
++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> 
++ B_BLC<4> B_BLC_SEL B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N 
++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_WR_ONE B_WR_ZERO 
++ VDD VSS / RM_IHPSG13_1024x8_c2_2P_BLDRV
+XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> 
++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> 
++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> 
++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N 
++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO 
++ VDD VSS / RM_IHPSG13_1024x8_c2_2P_BLDRV
+XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES
+XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES
+XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES
+XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES
+XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES
+XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES
+XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I80 B_WCLK_B_L B_RCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2
+XB_I76 B_DO_WRITE_P B_DI_N B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2
+XB_I75 B_DO_WRITE_P B_DI_R B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2
+XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2
+XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2
+XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2
+XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> 
++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> 
++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> 
++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> 
++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> 
++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> 
++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> 
++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> 
++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> 
++ WL_O<2> WL_O<1> WL_O<0> VDD VSS
+XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC02
+XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC00
+XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> 
++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> 
++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04
+XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC03
+XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC01
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> 
++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> 
++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> 
++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS
+XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> 
++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> 
++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> 
++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> 
++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O 
++ VDD VSS
+XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16
+XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16
+XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16
+XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XI1<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI1<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> 
++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> 
++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS
+XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS
+XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4
+XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2
+XI2 VDD VSS / RSC_IHPSG13_FILLCAP4
+XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS
+XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4
+XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2
+XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2
+XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI1 VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> 
++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC01
+XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC00
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04
+XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> 
++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> 
++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> 
++ BIST_EN_I VDD VSS
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> 
++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> 
++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> 
++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS
+XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2
+XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2
+XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net7<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net7<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2
+XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2
+XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2
+XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2
+XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2
+XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2
+XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2
+XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2
+XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> 
++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> 
++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> 
++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> 
++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> 
++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> 
++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> 
++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> 
++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> 
++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> 
++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> 
++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R 
++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R 
++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS
+XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / 
++ RSC_IHPSG13_AND2X2
+XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / 
++ RSC_IHPSG13_AND2X2
+XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XI80<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4
+XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_BLTMUX<31> A_BLC<31> A_BLC_SEL A_BLT<31> A_BLT_SEL A_PRE_N A_SEL_P<31> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<30> A_BLC<30> A_BLC_SEL A_BLT<30> A_BLT_SEL A_PRE_N A_SEL_P<30> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<29> A_BLC<29> A_BLC_SEL A_BLT<29> A_BLT_SEL A_PRE_N A_SEL_P<29> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<28> A_BLC<28> A_BLC_SEL A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<28> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<27> A_BLC<27> A_BLC_SEL A_BLT<27> A_BLT_SEL A_PRE_N A_SEL_P<27> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<26> A_BLC<26> A_BLC_SEL A_BLT<26> A_BLT_SEL A_PRE_N A_SEL_P<26> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<25> A_BLC<25> A_BLC_SEL A_BLT<25> A_BLT_SEL A_PRE_N A_SEL_P<25> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<24> A_BLC<24> A_BLC_SEL A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<24> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<23> A_BLC<23> A_BLC_SEL A_BLT<23> A_BLT_SEL A_PRE_N A_SEL_P<23> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<22> A_BLC<22> A_BLC_SEL A_BLT<22> A_BLT_SEL A_PRE_N A_SEL_P<22> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<21> A_BLC<21> A_BLC_SEL A_BLT<21> A_BLT_SEL A_PRE_N A_SEL_P<21> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<20> A_BLC<20> A_BLC_SEL A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<20> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<19> A_BLC<19> A_BLC_SEL A_BLT<19> A_BLT_SEL A_PRE_N A_SEL_P<19> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<18> A_BLC<18> A_BLC_SEL A_BLT<18> A_BLT_SEL A_PRE_N A_SEL_P<18> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<17> A_BLC<17> A_BLC_SEL A_BLT<17> A_BLT_SEL A_PRE_N A_SEL_P<17> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<16> A_BLC<16> A_BLC_SEL A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<16> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_1024x8_c2_1P_BLDRV
+XA_CAPS<17> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<16> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<15> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<14> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<13> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<12> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<11> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<10> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<9> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8
+XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8
+XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8
+XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6
+XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6
+XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2
+XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES
+XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES
+XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES
+XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+.ENDS
+
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> 
++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> 
++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> 
++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> 
++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O 
++ VDD VSS
+XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8
+XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12
+XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12
+XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> 
++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> 
++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS
+XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12
+.ENDS
+
+
+
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> 
++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> 
++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> 
++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> 
++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O 
++ VDD VSS
+XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8
+XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8
+XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8
+XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+.SUBCKT RSC_IHPSG13_WLDRVX8 A Z VDD VSS
+MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0
+MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0
+MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0
+MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> 
++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> 
++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS
+XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8
+.ENDS
+
+
+
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> 
++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> 
++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS
+XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI1<3> PADR<0> PADR<1> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2
+XI1<2> NADR<0> PADR<1> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2
+XI1<1> PADR<0> NADR<1> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2
+XI1<0> NADR<0> NADR<1> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2
+XI17<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL
+XI17<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL
+XI14<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL
+XI14<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL
+XI14<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL
+XI14<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL
+XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2
+XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2
+XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2
+XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2
+XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI15<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI15<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI15<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI15<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI15<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI19<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI19<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI19<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI19<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> 
++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> 
++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R 
++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R 
++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<3> B_ADDR_DEC<2> 
++ B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<3> 
++ B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I 
++ B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R 
++ B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD 
++ VSS
+XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XB_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4
+XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2
+XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2
+XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2
+XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2
+XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2
+XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2
+XB_I44 B_WCLK_B_L B_BM_N B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XA_I44 A_WCLK_B_L A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES
+XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES
+XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES
+XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES
+XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES
+XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES
+XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES
+XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES
+XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES
+XAB_BLMUX A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> 
++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> 
++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> 
++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N 
++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO 
++ VDD VSS / RM_IHPSG13_1024x8_c2_2P_BLDRV
+XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net039 net040 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XB_I51 net039 B_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_COLDRV13_FILL4C2 VDD VSS
+XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> 
++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> 
++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> 
++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> 
++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> 
++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> 
++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> 
++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> 
++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> 
++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> 
++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> 
++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> 
++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> 
++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> 
++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> 
++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> 
++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> 
++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> 
++ VDD VSS
+XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> 
++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> 
++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> 
++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> 
++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> 
++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> 
++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> 
++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> 
++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> 
++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> 
++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> 
++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> 
++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> 
++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> 
++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04
+XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC03
+XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC03
+XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC01
+XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC01
+XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC01
+XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC02
+XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC02
+XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC00
+XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC00
+XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_2P_DEC00
+XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> 
++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> 
++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> 
++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> 
++ BIST_ADDR_I<0> BIST_EN_I VDD VSS
+XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<0> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> 
++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> 
++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> 
++ VDD VSS
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> 
++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> 
++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> 
++ WL_O<0> VDD VSS / RM_IHPSG13_1024x8_c2_2P_DEC04
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_2P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> 
++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> 
++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net7<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net7<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net7<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net7<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI12<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_BITKIT_TAP BLC BLT NW PW VDD VSS
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> 
++ VDD_CORE VSS
+XITAP<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_1024x8_c2_1P_BITKIT_TAP
+XITAP<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_1024x8_c2_1P_BITKIT_TAP
+XIEDGEBP_COL1<1> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE 
++ VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_TB
+XIEDGEBP_COL1<0> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE 
++ VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_TB
+XIEDGEBP_COL2<1> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE 
++ VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_TB
+XIEDGEBP_COL2<0> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE 
++ VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_EDGE_TB
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_TAP_LR VDD_CORE VSS
+XCORNER<1> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_1P_BITKIT_CORNER
+XCORNER<0> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_1P_BITKIT_CORNER
+XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_1024x8_c2_1P_BITKIT_TAP_LR
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS
+XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4
+XI0 VDD VSS / RSC_IHPSG13_FILLCAP4
+XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS
+XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4
+XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2
+XI2 VDD VSS / RSC_IHPSG13_FILLCAP4
+XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> 
++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> 
++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> 
++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> 
++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> 
++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> 
++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> 
++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> 
++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> 
++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> 
++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> 
++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> 
++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> 
++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> 
++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> 
++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> 
++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> 
++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> 
++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> 
++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> 
++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> 
++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> 
++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> 
++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> 
++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> 
++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> 
++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> 
++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> 
++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> 
++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> 
++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> 
++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> 
++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> 
++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> 
++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> 
++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> 
++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS
+XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC03
+XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC03
+XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC03
+XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC03
+XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC03
+XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC02
+XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC02
+XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC02
+XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC02
+XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC02
+XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC00
+XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC00
+XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC00
+XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC00
+XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC00
+XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> 
++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> 
++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> 
++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> 
++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> 
++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> 
++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> 
++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> 
++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> 
++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> 
++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> 
++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> 
++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> 
++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> 
++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> 
++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> 
++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> 
++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> 
++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> 
++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> 
++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> 
++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> 
++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> 
++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> 
++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> 
++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> 
++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> 
++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> 
++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> 
++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> 
++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> 
++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> 
++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> 
++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> 
++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> 
++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> 
++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> 
++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> 
++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04
+XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC01
+XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC01
+XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC01
+XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC01
+XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC01
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> 
++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> 
++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> 
++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> 
++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS
+XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> 
++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I 
++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> 
++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> 
++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> 
++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> 
++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> 
++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> 
++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> 
++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> 
++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> 
++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> 
++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> 
++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> 
++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> 
++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> 
++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> 
++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> 
++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> 
++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> 
++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> 
++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> 
++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> 
++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> 
++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> 
++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> 
++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> 
++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> 
++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> 
++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> 
++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> 
++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> 
++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> 
++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> 
++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> 
++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> 
++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> 
++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> 
++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> 
++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> 
++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> 
++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> 
++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> 
++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> 
++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> 
++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> 
++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> 
++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> 
++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> 
++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> 
++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> 
++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> 
++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> 
++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> 
++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> 
++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> 
++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> 
++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> 
++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> 
++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> 
++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> 
++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> 
++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> 
++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> 
++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> 
++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS
+XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC03
+XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC03
+XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC03
+XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC03
+XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC03
+XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC03
+XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC03
+XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC03
+XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC03
+XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC03
+XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC00
+XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC00
+XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC00
+XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC00
+XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC00
+XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC00
+XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC00
+XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC00
+XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC00
+XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC00
+XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC00
+XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> 
++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> 
++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> 
++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> 
++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> 
++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> 
++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> 
++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> 
++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> 
++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> 
++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> 
++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> 
++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> 
++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> 
++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> 
++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> 
++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> 
++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> 
++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> 
++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> 
++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> 
++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> 
++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> 
++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> 
++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> 
++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> 
++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> 
++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> 
++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> 
++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> 
++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> 
++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> 
++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> 
++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> 
++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> 
++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> 
++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> 
++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> 
++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> 
++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> 
++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> 
++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> 
++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> 
++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> 
++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> 
++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> 
++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> 
++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> 
++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> 
++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> 
++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> 
++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> 
++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> 
++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> 
++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> 
++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> 
++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> 
++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> 
++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> 
++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> 
++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> 
++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> 
++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> 
++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> 
++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> 
++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> 
++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> 
++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> 
++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> 
++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> 
++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> 
++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> 
++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> 
++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> 
++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> 
++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> 
++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> 
++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> 
++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> 
++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> 
++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> 
++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> 
++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> 
++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> 
++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> 
++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> 
++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04
+XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC01
+XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC01
+XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC01
+XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC01
+XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC01
+XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC01
+XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC01
+XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC01
+XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC01
+XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC01
+XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC01
+XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC02
+XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC02
+XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC02
+XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC02
+XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC02
+XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC02
+XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC02
+XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC02
+XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC02
+XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC02
+XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> 
++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> 
++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> 
++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> 
++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> 
++ BIST_EN_I VDD VSS
+XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+.ENDS
+
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> 
++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> 
++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> 
++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> 
++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> 
++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> 
++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> 
++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> 
++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> 
++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> 
++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> 
++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> 
++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> 
++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> 
++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> 
++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> 
++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> 
++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> 
++ VDD VSS
+XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC03
+XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC03
+XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC02
+XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC02
+XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> 
++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> 
++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> 
++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> 
++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> 
++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> 
++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> 
++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> 
++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> 
++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> 
++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> 
++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> 
++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> 
++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> 
++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04
+XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC00
+XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC00
+XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC00
+XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC01
+XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC01
+XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC01
+XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> 
++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> 
++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> 
++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> 
++ BIST_ADDR_I<0> BIST_EN_I VDD VSS
+XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> 
++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> 
++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> 
++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> 
++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O 
++ VDD VSS
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8
+XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8
+XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> 
++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> 
++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS
+XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8
+.ENDS
+
+
+
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> 
++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> 
++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> 
++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> 
++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> 
++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> 
++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> 
++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> 
++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> 
++ WL_O<2> WL_O<1> WL_O<0> VDD VSS
+XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC03
+XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC00
+XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC01
+XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / 
++ RM_IHPSG13_1024x8_c2_1P_DEC02
+XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> 
++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> 
++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_1024x8_c2_1P_DEC04
+XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> 
++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> 
++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> 
++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS
+XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_COLUMN_pcell_0 A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<255> A_LWL<254> A_LWL<253> A_LWL<252> A_LWL<251> A_LWL<250> A_LWL<249> A_LWL<248> A_LWL<247> A_LWL<246> A_LWL<245> A_LWL<244> A_LWL<243> A_LWL<242> A_LWL<241> A_LWL<240> A_LWL<239> A_LWL<238> A_LWL<237> A_LWL<236> A_LWL<235> A_LWL<234> A_LWL<233> A_LWL<232> A_LWL<231> A_LWL<230> A_LWL<229> A_LWL<228> A_LWL<227> A_LWL<226> A_LWL<225> A_LWL<224> A_LWL<223> A_LWL<222> A_LWL<221> A_LWL<220> A_LWL<219> A_LWL<218> A_LWL<217> A_LWL<216> A_LWL<215> A_LWL<214> A_LWL<213> A_LWL<212> A_LWL<211> A_LWL<210> A_LWL<209> A_LWL<208> A_LWL<207> A_LWL<206> A_LWL<205> A_LWL<204> A_LWL<203> A_LWL<202> A_LWL<201> A_LWL<200> A_LWL<199> A_LWL<198> A_LWL<197> A_LWL<196> A_LWL<195> A_LWL<194> A_LWL<193> A_LWL<192> A_LWL<191> A_LWL<190> A_LWL<189> A_LWL<188> A_LWL<187> A_LWL<186> A_LWL<185> A_LWL<184> A_LWL<183> A_LWL<182> A_LWL<181> A_LWL<180> A_LWL<179> A_LWL<178> A_LWL<177> A_LWL<176> A_LWL<175> A_LWL<174> A_LWL<173> A_LWL<172> A_LWL<171> A_LWL<170> A_LWL<169> A_LWL<168> A_LWL<167> A_LWL<166> A_LWL<165> A_LWL<164> A_LWL<163> A_LWL<162> A_LWL<161> A_LWL<160> A_LWL<159> A_LWL<158> A_LWL<157> A_LWL<156> A_LWL<155> A_LWL<154> A_LWL<153> A_LWL<152> A_LWL<151> A_LWL<150> A_LWL<149> A_LWL<148> A_LWL<147> A_LWL<146> A_LWL<145> A_LWL<144> A_LWL<143> A_LWL<142> A_LWL<141> A_LWL<140> A_LWL<139> A_LWL<138> A_LWL<137> A_LWL<136> A_LWL<135> A_LWL<134> A_LWL<133> A_LWL<132> A_LWL<131> A_LWL<130> A_LWL<129> A_LWL<128> A_LWL<127> A_LWL<126> A_LWL<125> A_LWL<124> A_LWL<123> A_LWL<122> A_LWL<121> A_LWL<120> A_LWL<119> A_LWL<118> A_LWL<117> A_LWL<116> A_LWL<115> A_LWL<114> A_LWL<113> A_LWL<112> A_LWL<111> A_LWL<110> A_LWL<109> A_LWL<108> A_LWL<107> A_LWL<106> A_LWL<105> A_LWL<104> A_LWL<103> A_LWL<102> A_LWL<101> A_LWL<100> A_LWL<99> A_LWL<98> A_LWL<97> A_LWL<96> A_LWL<95> A_LWL<94> A_LWL<93> A_LWL<92> A_LWL<91> A_LWL<90> A_LWL<89> A_LWL<88> A_LWL<87> A_LWL<86> A_LWL<85> A_LWL<84> A_LWL<83> A_LWL<82> A_LWL<81> A_LWL<80> A_LWL<79> A_LWL<78> A_LWL<77> A_LWL<76> A_LWL<75> A_LWL<74> A_LWL<73> A_LWL<72> A_LWL<71> A_LWL<70> A_LWL<69> A_LWL<68> A_LWL<67> A_LWL<66> A_LWL<65> A_LWL<64> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<255> A_RWL<254> A_RWL<253> A_RWL<252> A_RWL<251> A_RWL<250> A_RWL<249> A_RWL<248> A_RWL<247> A_RWL<246> A_RWL<245> A_RWL<244> A_RWL<243> A_RWL<242> A_RWL<241> A_RWL<240> A_RWL<239> A_RWL<238> A_RWL<237> A_RWL<236> A_RWL<235> A_RWL<234> A_RWL<233> A_RWL<232> A_RWL<231> A_RWL<230> A_RWL<229> A_RWL<228> A_RWL<227> A_RWL<226> A_RWL<225> A_RWL<224> A_RWL<223> A_RWL<222> A_RWL<221> A_RWL<220> A_RWL<219> A_RWL<218> A_RWL<217> A_RWL<216> A_RWL<215> A_RWL<214> A_RWL<213> A_RWL<212> A_RWL<211> A_RWL<210> A_RWL<209> A_RWL<208> A_RWL<207> A_RWL<206> A_RWL<205> A_RWL<204> A_RWL<203> A_RWL<202> A_RWL<201> A_RWL<200> A_RWL<199> A_RWL<198> A_RWL<197> A_RWL<196> A_RWL<195> A_RWL<194> A_RWL<193> A_RWL<192> A_RWL<191> A_RWL<190> A_RWL<189> A_RWL<188> A_RWL<187> A_RWL<186> A_RWL<185> A_RWL<184> A_RWL<183> A_RWL<182> A_RWL<181> A_RWL<180> A_RWL<179> A_RWL<178> A_RWL<177> A_RWL<176> A_RWL<175> A_RWL<174> A_RWL<173> A_RWL<172> A_RWL<171> A_RWL<170> A_RWL<169> A_RWL<168> A_RWL<167> A_RWL<166> A_RWL<165> A_RWL<164> A_RWL<163> A_RWL<162> A_RWL<161> A_RWL<160> A_RWL<159> A_RWL<158> A_RWL<157> A_RWL<156> A_RWL<155> A_RWL<154> A_RWL<153> A_RWL<152> A_RWL<151> A_RWL<150> A_RWL<149> A_RWL<148> A_RWL<147> A_RWL<146> A_RWL<145> A_RWL<144> A_RWL<143> A_RWL<142> A_RWL<141> A_RWL<140> A_RWL<139> A_RWL<138> A_RWL<137> A_RWL<136> A_RWL<135> A_RWL<134> A_RWL<133> A_RWL<132> A_RWL<131> A_RWL<130> A_RWL<129> A_RWL<128> A_RWL<127> A_RWL<126> A_RWL<125> A_RWL<124> A_RWL<123> A_RWL<122> A_RWL<121> A_RWL<120> A_RWL<119> A_RWL<118> A_RWL<117> A_RWL<116> A_RWL<115> A_RWL<114> A_RWL<113> A_RWL<112> A_RWL<111> A_RWL<110> A_RWL<109> A_RWL<108> A_RWL<107> A_RWL<106> A_RWL<105> A_RWL<104> A_RWL<103> A_RWL<102> A_RWL<101> A_RWL<100> A_RWL<99> A_RWL<98> A_RWL<97> A_RWL<96> A_RWL<95> A_RWL<94> A_RWL<93> A_RWL<92> A_RWL<91> A_RWL<90> A_RWL<89> A_RWL<88> A_RWL<87> A_RWL<86> A_RWL<85> A_RWL<84> A_RWL<83> A_RWL<82> A_RWL<81> A_RWL<80> A_RWL<79> A_RWL<78> A_RWL<77> A_RWL<76> A_RWL<75> A_RWL<74> A_RWL<73> A_RWL<72> A_RWL<71> A_RWL<70> A_RWL<69> A_RWL<68> A_RWL<67> A_RWL<66> A_RWL<65> A_RWL<64> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE VSS
+XRAM<16> A_BLC<29> A_BLC<28> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<29> A_BLT<28> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<255> A_LWL<254> A_LWL<253> A_LWL<252> A_LWL<251> A_LWL<250> A_LWL<249> A_LWL<248> A_LWL<247> A_LWL<246> A_LWL<245> A_LWL<244> A_LWL<243> A_LWL<242> A_LWL<241> A_LWL<240> A_RWL<255> A_RWL<254> A_RWL<253> A_RWL<252> A_RWL<251> A_RWL<250> A_RWL<249> A_RWL<248> A_RWL<247> A_RWL<246> A_RWL<245> A_RWL<244> A_RWL<243> A_RWL<242> A_RWL<241> A_RWL<240> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_SRAM
+XRAM<15> A_BLC<27> A_BLC<26> A_BLC<29> A_BLC<28> A_BLT<27> A_BLT<26> A_BLT<29> A_BLT<28> A_LWL<239> A_LWL<238> A_LWL<237> A_LWL<236> A_LWL<235> A_LWL<234> A_LWL<233> A_LWL<232> A_LWL<231> A_LWL<230> A_LWL<229> A_LWL<228> A_LWL<227> A_LWL<226> A_LWL<225> A_LWL<224> A_RWL<239> A_RWL<238> A_RWL<237> A_RWL<236> A_RWL<235> A_RWL<234> A_RWL<233> A_RWL<232> A_RWL<231> A_RWL<230> A_RWL<229> A_RWL<228> A_RWL<227> A_RWL<226> A_RWL<225> A_RWL<224> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_SRAM
+XRAM<14> A_BLC<25> A_BLC<24> A_BLC<27> A_BLC<26> A_BLT<25> A_BLT<24> A_BLT<27> A_BLT<26> A_LWL<223> A_LWL<222> A_LWL<221> A_LWL<220> A_LWL<219> A_LWL<218> A_LWL<217> A_LWL<216> A_LWL<215> A_LWL<214> A_LWL<213> A_LWL<212> A_LWL<211> A_LWL<210> A_LWL<209> A_LWL<208> A_RWL<223> A_RWL<222> A_RWL<221> A_RWL<220> A_RWL<219> A_RWL<218> A_RWL<217> A_RWL<216> A_RWL<215> A_RWL<214> A_RWL<213> A_RWL<212> A_RWL<211> A_RWL<210> A_RWL<209> A_RWL<208> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_SRAM
+XRAM<13> A_BLC<23> A_BLC<22> A_BLC<25> A_BLC<24> A_BLT<23> A_BLT<22> A_BLT<25> A_BLT<24> A_LWL<207> A_LWL<206> A_LWL<205> A_LWL<204> A_LWL<203> A_LWL<202> A_LWL<201> A_LWL<200> A_LWL<199> A_LWL<198> A_LWL<197> A_LWL<196> A_LWL<195> A_LWL<194> A_LWL<193> A_LWL<192> A_RWL<207> A_RWL<206> A_RWL<205> A_RWL<204> A_RWL<203> A_RWL<202> A_RWL<201> A_RWL<200> A_RWL<199> A_RWL<198> A_RWL<197> A_RWL<196> A_RWL<195> A_RWL<194> A_RWL<193> A_RWL<192> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_SRAM
+XRAM<12> A_BLC<21> A_BLC<20> A_BLC<23> A_BLC<22> A_BLT<21> A_BLT<20> A_BLT<23> A_BLT<22> A_LWL<191> A_LWL<190> A_LWL<189> A_LWL<188> A_LWL<187> A_LWL<186> A_LWL<185> A_LWL<184> A_LWL<183> A_LWL<182> A_LWL<181> A_LWL<180> A_LWL<179> A_LWL<178> A_LWL<177> A_LWL<176> A_RWL<191> A_RWL<190> A_RWL<189> A_RWL<188> A_RWL<187> A_RWL<186> A_RWL<185> A_RWL<184> A_RWL<183> A_RWL<182> A_RWL<181> A_RWL<180> A_RWL<179> A_RWL<178> A_RWL<177> A_RWL<176> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_SRAM
+XRAM<11> A_BLC<19> A_BLC<18> A_BLC<21> A_BLC<20> A_BLT<19> A_BLT<18> A_BLT<21> A_BLT<20> A_LWL<175> A_LWL<174> A_LWL<173> A_LWL<172> A_LWL<171> A_LWL<170> A_LWL<169> A_LWL<168> A_LWL<167> A_LWL<166> A_LWL<165> A_LWL<164> A_LWL<163> A_LWL<162> A_LWL<161> A_LWL<160> A_RWL<175> A_RWL<174> A_RWL<173> A_RWL<172> A_RWL<171> A_RWL<170> A_RWL<169> A_RWL<168> A_RWL<167> A_RWL<166> A_RWL<165> A_RWL<164> A_RWL<163> A_RWL<162> A_RWL<161> A_RWL<160> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_SRAM
+XRAM<10> A_BLC<17> A_BLC<16> A_BLC<19> A_BLC<18> A_BLT<17> A_BLT<16> A_BLT<19> A_BLT<18> A_LWL<159> A_LWL<158> A_LWL<157> A_LWL<156> A_LWL<155> A_LWL<154> A_LWL<153> A_LWL<152> A_LWL<151> A_LWL<150> A_LWL<149> A_LWL<148> A_LWL<147> A_LWL<146> A_LWL<145> A_LWL<144> A_RWL<159> A_RWL<158> A_RWL<157> A_RWL<156> A_RWL<155> A_RWL<154> A_RWL<153> A_RWL<152> A_RWL<151> A_RWL<150> A_RWL<149> A_RWL<148> A_RWL<147> A_RWL<146> A_RWL<145> A_RWL<144> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_SRAM
+XRAM<9> A_BLC<15> A_BLC<14> A_BLC<17> A_BLC<16> A_BLT<15> A_BLT<14> A_BLT<17> A_BLT<16> A_LWL<143> A_LWL<142> A_LWL<141> A_LWL<140> A_LWL<139> A_LWL<138> A_LWL<137> A_LWL<136> A_LWL<135> A_LWL<134> A_LWL<133> A_LWL<132> A_LWL<131> A_LWL<130> A_LWL<129> A_LWL<128> A_RWL<143> A_RWL<142> A_RWL<141> A_RWL<140> A_RWL<139> A_RWL<138> A_RWL<137> A_RWL<136> A_RWL<135> A_RWL<134> A_RWL<133> A_RWL<132> A_RWL<131> A_RWL<130> A_RWL<129> A_RWL<128> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_SRAM
+XRAM<8> A_BLC<13> A_BLC<12> A_BLC<15> A_BLC<14> A_BLT<13> A_BLT<12> A_BLT<15> A_BLT<14> A_LWL<127> A_LWL<126> A_LWL<125> A_LWL<124> A_LWL<123> A_LWL<122> A_LWL<121> A_LWL<120> A_LWL<119> A_LWL<118> A_LWL<117> A_LWL<116> A_LWL<115> A_LWL<114> A_LWL<113> A_LWL<112> A_RWL<127> A_RWL<126> A_RWL<125> A_RWL<124> A_RWL<123> A_RWL<122> A_RWL<121> A_RWL<120> A_RWL<119> A_RWL<118> A_RWL<117> A_RWL<116> A_RWL<115> A_RWL<114> A_RWL<113> A_RWL<112> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_SRAM
+XRAM<7> A_BLC<11> A_BLC<10> A_BLC<13> A_BLC<12> A_BLT<11> A_BLT<10> A_BLT<13> A_BLT<12> A_LWL<111> A_LWL<110> A_LWL<109> A_LWL<108> A_LWL<107> A_LWL<106> A_LWL<105> A_LWL<104> A_LWL<103> A_LWL<102> A_LWL<101> A_LWL<100> A_LWL<99> A_LWL<98> A_LWL<97> A_LWL<96> A_RWL<111> A_RWL<110> A_RWL<109> A_RWL<108> A_RWL<107> A_RWL<106> A_RWL<105> A_RWL<104> A_RWL<103> A_RWL<102> A_RWL<101> A_RWL<100> A_RWL<99> A_RWL<98> A_RWL<97> A_RWL<96> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_SRAM
+XRAM<6> A_BLC<9> A_BLC<8> A_BLC<11> A_BLC<10> A_BLT<9> A_BLT<8> A_BLT<11> A_BLT<10> A_LWL<95> A_LWL<94> A_LWL<93> A_LWL<92> A_LWL<91> A_LWL<90> A_LWL<89> A_LWL<88> A_LWL<87> A_LWL<86> A_LWL<85> A_LWL<84> A_LWL<83> A_LWL<82> A_LWL<81> A_LWL<80> A_RWL<95> A_RWL<94> A_RWL<93> A_RWL<92> A_RWL<91> A_RWL<90> A_RWL<89> A_RWL<88> A_RWL<87> A_RWL<86> A_RWL<85> A_RWL<84> A_RWL<83> A_RWL<82> A_RWL<81> A_RWL<80> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_SRAM
+XRAM<5> A_BLC<7> A_BLC<6> A_BLC<9> A_BLC<8> A_BLT<7> A_BLT<6> A_BLT<9> A_BLT<8> A_LWL<79> A_LWL<78> A_LWL<77> A_LWL<76> A_LWL<75> A_LWL<74> A_LWL<73> A_LWL<72> A_LWL<71> A_LWL<70> A_LWL<69> A_LWL<68> A_LWL<67> A_LWL<66> A_LWL<65> A_LWL<64> A_RWL<79> A_RWL<78> A_RWL<77> A_RWL<76> A_RWL<75> A_RWL<74> A_RWL<73> A_RWL<72> A_RWL<71> A_RWL<70> A_RWL<69> A_RWL<68> A_RWL<67> A_RWL<66> A_RWL<65> A_RWL<64> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_SRAM
+XRAM<4> A_BLC<5> A_BLC<4> A_BLC<7> A_BLC<6> A_BLT<5> A_BLT<4> A_BLT<7> A_BLT<6> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_SRAM
+XRAM<3> A_BLC<3> A_BLC<2> A_BLC<5> A_BLC<4> A_BLT<3> A_BLT<2> A_BLT<5> A_BLT<4> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_SRAM
+XRAM<2> A_BLC<1> A_BLC<0> A_BLC<3> A_BLC<2> A_BLT<1> A_BLT<0> A_BLT<3> A_BLT<2> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_SRAM
+XRAM<1> A_BLC_BOT<1> A_BLC_BOT<0> A_BLC<1> A_BLC<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT<1> A_BLT<0> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_SRAM
+XEDGE<1> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_TOP<1> A_BLT_TOP<0> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_TB
+XEDGE<0> A_BLC_BOT<1> A_BLC_BOT<0> A_BLT_BOT<1> A_BLT_BOT<0> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_TB
+.ENDS
+
+
+
+
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_MATRIX_pcell_1 A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_WL<255> A_WL<254> A_WL<253> A_WL<252> A_WL<251> A_WL<250> A_WL<249> A_WL<248> A_WL<247> A_WL<246> A_WL<245> A_WL<244> A_WL<243> A_WL<242> A_WL<241> A_WL<240> A_WL<239> A_WL<238> A_WL<237> A_WL<236> A_WL<235> A_WL<234> A_WL<233> A_WL<232> A_WL<231> A_WL<230> A_WL<229> A_WL<228> A_WL<227> A_WL<226> A_WL<225> A_WL<224> A_WL<223> A_WL<222> A_WL<221> A_WL<220> A_WL<219> A_WL<218> A_WL<217> A_WL<216> A_WL<215> A_WL<214> A_WL<213> A_WL<212> A_WL<211> A_WL<210> A_WL<209> A_WL<208> A_WL<207> A_WL<206> A_WL<205> A_WL<204> A_WL<203> A_WL<202> A_WL<201> A_WL<200> A_WL<199> A_WL<198> A_WL<197> A_WL<196> A_WL<195> A_WL<194> A_WL<193> A_WL<192> A_WL<191> A_WL<190> A_WL<189> A_WL<188> A_WL<187> A_WL<186> A_WL<185> A_WL<184> A_WL<183> A_WL<182> A_WL<181> A_WL<180> A_WL<179> A_WL<178> A_WL<177> A_WL<176> A_WL<175> A_WL<174> A_WL<173> A_WL<172> A_WL<171> A_WL<170> A_WL<169> A_WL<168> A_WL<167> A_WL<166> A_WL<165> A_WL<164> A_WL<163> A_WL<162> A_WL<161> A_WL<160> A_WL<159> A_WL<158> A_WL<157> A_WL<156> A_WL<155> A_WL<154> A_WL<153> A_WL<152> A_WL<151> A_WL<150> A_WL<149> A_WL<148> A_WL<147> A_WL<146> A_WL<145> A_WL<144> A_WL<143> A_WL<142> A_WL<141> A_WL<140> A_WL<139> A_WL<138> A_WL<137> A_WL<136> A_WL<135> A_WL<134> A_WL<133> A_WL<132> A_WL<131> A_WL<130> A_WL<129> A_WL<128> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS
+XCORNER<3> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_CORNER
+XCORNER<2> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_CORNER
+XCORNER<1> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_CORNER
+XCORNER<0> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_CORNER
+XRAMEDGE_L<15> A_WL<255> A_WL<254> A_WL<253> A_WL<252> A_WL<251> A_WL<250> A_WL<249> A_WL<248> A_WL<247> A_WL<246> A_WL<245> A_WL<244> A_WL<243> A_WL<242> A_WL<241> A_WL<240> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<14> A_WL<239> A_WL<238> A_WL<237> A_WL<236> A_WL<235> A_WL<234> A_WL<233> A_WL<232> A_WL<231> A_WL<230> A_WL<229> A_WL<228> A_WL<227> A_WL<226> A_WL<225> A_WL<224> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<13> A_WL<223> A_WL<222> A_WL<221> A_WL<220> A_WL<219> A_WL<218> A_WL<217> A_WL<216> A_WL<215> A_WL<214> A_WL<213> A_WL<212> A_WL<211> A_WL<210> A_WL<209> A_WL<208> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<12> A_WL<207> A_WL<206> A_WL<205> A_WL<204> A_WL<203> A_WL<202> A_WL<201> A_WL<200> A_WL<199> A_WL<198> A_WL<197> A_WL<196> A_WL<195> A_WL<194> A_WL<193> A_WL<192> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<11> A_WL<191> A_WL<190> A_WL<189> A_WL<188> A_WL<187> A_WL<186> A_WL<185> A_WL<184> A_WL<183> A_WL<182> A_WL<181> A_WL<180> A_WL<179> A_WL<178> A_WL<177> A_WL<176> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<10> A_WL<175> A_WL<174> A_WL<173> A_WL<172> A_WL<171> A_WL<170> A_WL<169> A_WL<168> A_WL<167> A_WL<166> A_WL<165> A_WL<164> A_WL<163> A_WL<162> A_WL<161> A_WL<160> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<9> A_WL<159> A_WL<158> A_WL<157> A_WL<156> A_WL<155> A_WL<154> A_WL<153> A_WL<152> A_WL<151> A_WL<150> A_WL<149> A_WL<148> A_WL<147> A_WL<146> A_WL<145> A_WL<144> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<8> A_WL<143> A_WL<142> A_WL<141> A_WL<140> A_WL<139> A_WL<138> A_WL<137> A_WL<136> A_WL<135> A_WL<134> A_WL<133> A_WL<132> A_WL<131> A_WL<130> A_WL<129> A_WL<128> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<7> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<6> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<5> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<4> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<3> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<2> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<1> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<0> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<15> A_IWL<2047> A_IWL<2046> A_IWL<2045> A_IWL<2044> A_IWL<2043> A_IWL<2042> A_IWL<2041> A_IWL<2040> A_IWL<2039> A_IWL<2038> A_IWL<2037> A_IWL<2036> A_IWL<2035> A_IWL<2034> A_IWL<2033> A_IWL<2032> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<14> A_IWL<2031> A_IWL<2030> A_IWL<2029> A_IWL<2028> A_IWL<2027> A_IWL<2026> A_IWL<2025> A_IWL<2024> A_IWL<2023> A_IWL<2022> A_IWL<2021> A_IWL<2020> A_IWL<2019> A_IWL<2018> A_IWL<2017> A_IWL<2016> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<13> A_IWL<2015> A_IWL<2014> A_IWL<2013> A_IWL<2012> A_IWL<2011> A_IWL<2010> A_IWL<2009> A_IWL<2008> A_IWL<2007> A_IWL<2006> A_IWL<2005> A_IWL<2004> A_IWL<2003> A_IWL<2002> A_IWL<2001> A_IWL<2000> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<12> A_IWL<1999> A_IWL<1998> A_IWL<1997> A_IWL<1996> A_IWL<1995> A_IWL<1994> A_IWL<1993> A_IWL<1992> A_IWL<1991> A_IWL<1990> A_IWL<1989> A_IWL<1988> A_IWL<1987> A_IWL<1986> A_IWL<1985> A_IWL<1984> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<11> A_IWL<1983> A_IWL<1982> A_IWL<1981> A_IWL<1980> A_IWL<1979> A_IWL<1978> A_IWL<1977> A_IWL<1976> A_IWL<1975> A_IWL<1974> A_IWL<1973> A_IWL<1972> A_IWL<1971> A_IWL<1970> A_IWL<1969> A_IWL<1968> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<10> A_IWL<1967> A_IWL<1966> A_IWL<1965> A_IWL<1964> A_IWL<1963> A_IWL<1962> A_IWL<1961> A_IWL<1960> A_IWL<1959> A_IWL<1958> A_IWL<1957> A_IWL<1956> A_IWL<1955> A_IWL<1954> A_IWL<1953> A_IWL<1952> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<9> A_IWL<1951> A_IWL<1950> A_IWL<1949> A_IWL<1948> A_IWL<1947> A_IWL<1946> A_IWL<1945> A_IWL<1944> A_IWL<1943> A_IWL<1942> A_IWL<1941> A_IWL<1940> A_IWL<1939> A_IWL<1938> A_IWL<1937> A_IWL<1936> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<8> A_IWL<1935> A_IWL<1934> A_IWL<1933> A_IWL<1932> A_IWL<1931> A_IWL<1930> A_IWL<1929> A_IWL<1928> A_IWL<1927> A_IWL<1926> A_IWL<1925> A_IWL<1924> A_IWL<1923> A_IWL<1922> A_IWL<1921> A_IWL<1920> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<7> A_IWL<1919> A_IWL<1918> A_IWL<1917> A_IWL<1916> A_IWL<1915> A_IWL<1914> A_IWL<1913> A_IWL<1912> A_IWL<1911> A_IWL<1910> A_IWL<1909> A_IWL<1908> A_IWL<1907> A_IWL<1906> A_IWL<1905> A_IWL<1904> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<6> A_IWL<1903> A_IWL<1902> A_IWL<1901> A_IWL<1900> A_IWL<1899> A_IWL<1898> A_IWL<1897> A_IWL<1896> A_IWL<1895> A_IWL<1894> A_IWL<1893> A_IWL<1892> A_IWL<1891> A_IWL<1890> A_IWL<1889> A_IWL<1888> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<5> A_IWL<1887> A_IWL<1886> A_IWL<1885> A_IWL<1884> A_IWL<1883> A_IWL<1882> A_IWL<1881> A_IWL<1880> A_IWL<1879> A_IWL<1878> A_IWL<1877> A_IWL<1876> A_IWL<1875> A_IWL<1874> A_IWL<1873> A_IWL<1872> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<4> A_IWL<1871> A_IWL<1870> A_IWL<1869> A_IWL<1868> A_IWL<1867> A_IWL<1866> A_IWL<1865> A_IWL<1864> A_IWL<1863> A_IWL<1862> A_IWL<1861> A_IWL<1860> A_IWL<1859> A_IWL<1858> A_IWL<1857> A_IWL<1856> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<3> A_IWL<1855> A_IWL<1854> A_IWL<1853> A_IWL<1852> A_IWL<1851> A_IWL<1850> A_IWL<1849> A_IWL<1848> A_IWL<1847> A_IWL<1846> A_IWL<1845> A_IWL<1844> A_IWL<1843> A_IWL<1842> A_IWL<1841> A_IWL<1840> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<2> A_IWL<1839> A_IWL<1838> A_IWL<1837> A_IWL<1836> A_IWL<1835> A_IWL<1834> A_IWL<1833> A_IWL<1832> A_IWL<1831> A_IWL<1830> A_IWL<1829> A_IWL<1828> A_IWL<1827> A_IWL<1826> A_IWL<1825> A_IWL<1824> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<1> A_IWL<1823> A_IWL<1822> A_IWL<1821> A_IWL<1820> A_IWL<1819> A_IWL<1818> A_IWL<1817> A_IWL<1816> A_IWL<1815> A_IWL<1814> A_IWL<1813> A_IWL<1812> A_IWL<1811> A_IWL<1810> A_IWL<1809> A_IWL<1808> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<0> A_IWL<1807> A_IWL<1806> A_IWL<1805> A_IWL<1804> A_IWL<1803> A_IWL<1802> A_IWL<1801> A_IWL<1800> A_IWL<1799> A_IWL<1798> A_IWL<1797> A_IWL<1796> A_IWL<1795> A_IWL<1794> A_IWL<1793> A_IWL<1792> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_BITKIT_16x2_EDGE_LR
+XCOL<7> A_BLC<15> A_BLC<14> A_BLC_TOP<15> A_BLC_TOP<14> A_BLT<15> A_BLT<14> A_BLT_TOP<15> A_BLT_TOP<14> A_IWL<1791> A_IWL<1790> A_IWL<1789> A_IWL<1788> A_IWL<1787> A_IWL<1786> A_IWL<1785> A_IWL<1784> A_IWL<1783> A_IWL<1782> A_IWL<1781> A_IWL<1780> A_IWL<1779> A_IWL<1778> A_IWL<1777> A_IWL<1776> A_IWL<1775> A_IWL<1774> A_IWL<1773> A_IWL<1772> A_IWL<1771> A_IWL<1770> A_IWL<1769> A_IWL<1768> A_IWL<1767> A_IWL<1766> A_IWL<1765> A_IWL<1764> A_IWL<1763> A_IWL<1762> A_IWL<1761> A_IWL<1760> A_IWL<1759> A_IWL<1758> A_IWL<1757> A_IWL<1756> A_IWL<1755> A_IWL<1754> A_IWL<1753> A_IWL<1752> A_IWL<1751> A_IWL<1750> A_IWL<1749> A_IWL<1748> A_IWL<1747> A_IWL<1746> A_IWL<1745> A_IWL<1744> A_IWL<1743> A_IWL<1742> A_IWL<1741> A_IWL<1740> A_IWL<1739> A_IWL<1738> A_IWL<1737> A_IWL<1736> A_IWL<1735> A_IWL<1734> A_IWL<1733> A_IWL<1732> A_IWL<1731> A_IWL<1730> A_IWL<1729> A_IWL<1728> A_IWL<1727> A_IWL<1726> A_IWL<1725> A_IWL<1724> A_IWL<1723> A_IWL<1722> A_IWL<1721> A_IWL<1720> A_IWL<1719> A_IWL<1718> A_IWL<1717> A_IWL<1716> A_IWL<1715> A_IWL<1714> A_IWL<1713> A_IWL<1712> A_IWL<1711> A_IWL<1710> A_IWL<1709> A_IWL<1708> A_IWL<1707> A_IWL<1706> A_IWL<1705> A_IWL<1704> A_IWL<1703> A_IWL<1702> A_IWL<1701> A_IWL<1700> A_IWL<1699> A_IWL<1698> A_IWL<1697> A_IWL<1696> A_IWL<1695> A_IWL<1694> A_IWL<1693> A_IWL<1692> A_IWL<1691> A_IWL<1690> A_IWL<1689> A_IWL<1688> A_IWL<1687> A_IWL<1686> A_IWL<1685> A_IWL<1684> A_IWL<1683> A_IWL<1682> A_IWL<1681> A_IWL<1680> A_IWL<1679> A_IWL<1678> A_IWL<1677> A_IWL<1676> A_IWL<1675> A_IWL<1674> A_IWL<1673> A_IWL<1672> A_IWL<1671> A_IWL<1670> A_IWL<1669> A_IWL<1668> A_IWL<1667> A_IWL<1666> A_IWL<1665> A_IWL<1664> A_IWL<1663> A_IWL<1662> A_IWL<1661> A_IWL<1660> A_IWL<1659> A_IWL<1658> A_IWL<1657> A_IWL<1656> A_IWL<1655> A_IWL<1654> A_IWL<1653> A_IWL<1652> A_IWL<1651> A_IWL<1650> A_IWL<1649> A_IWL<1648> A_IWL<1647> A_IWL<1646> A_IWL<1645> A_IWL<1644> A_IWL<1643> A_IWL<1642> A_IWL<1641> A_IWL<1640> A_IWL<1639> A_IWL<1638> A_IWL<1637> A_IWL<1636> A_IWL<1635> A_IWL<1634> A_IWL<1633> A_IWL<1632> A_IWL<1631> A_IWL<1630> A_IWL<1629> A_IWL<1628> A_IWL<1627> A_IWL<1626> A_IWL<1625> A_IWL<1624> A_IWL<1623> A_IWL<1622> A_IWL<1621> A_IWL<1620> A_IWL<1619> A_IWL<1618> A_IWL<1617> A_IWL<1616> A_IWL<1615> A_IWL<1614> A_IWL<1613> A_IWL<1612> A_IWL<1611> A_IWL<1610> A_IWL<1609> A_IWL<1608> A_IWL<1607> A_IWL<1606> A_IWL<1605> A_IWL<1604> A_IWL<1603> A_IWL<1602> A_IWL<1601> A_IWL<1600> A_IWL<1599> A_IWL<1598> A_IWL<1597> A_IWL<1596> A_IWL<1595> A_IWL<1594> A_IWL<1593> A_IWL<1592> A_IWL<1591> A_IWL<1590> A_IWL<1589> A_IWL<1588> A_IWL<1587> A_IWL<1586> A_IWL<1585> A_IWL<1584> A_IWL<1583> A_IWL<1582> A_IWL<1581> A_IWL<1580> A_IWL<1579> A_IWL<1578> A_IWL<1577> A_IWL<1576> A_IWL<1575> A_IWL<1574> A_IWL<1573> A_IWL<1572> A_IWL<1571> A_IWL<1570> A_IWL<1569> A_IWL<1568> A_IWL<1567> A_IWL<1566> A_IWL<1565> A_IWL<1564> A_IWL<1563> A_IWL<1562> A_IWL<1561> A_IWL<1560> A_IWL<1559> A_IWL<1558> A_IWL<1557> A_IWL<1556> A_IWL<1555> A_IWL<1554> A_IWL<1553> A_IWL<1552> A_IWL<1551> A_IWL<1550> A_IWL<1549> A_IWL<1548> A_IWL<1547> A_IWL<1546> A_IWL<1545> A_IWL<1544> A_IWL<1543> A_IWL<1542> A_IWL<1541> A_IWL<1540> A_IWL<1539> A_IWL<1538> A_IWL<1537> A_IWL<1536> A_IWL<2047> A_IWL<2046> A_IWL<2045> A_IWL<2044> A_IWL<2043> A_IWL<2042> A_IWL<2041> A_IWL<2040> A_IWL<2039> A_IWL<2038> A_IWL<2037> A_IWL<2036> A_IWL<2035> A_IWL<2034> A_IWL<2033> A_IWL<2032> A_IWL<2031> A_IWL<2030> A_IWL<2029> A_IWL<2028> A_IWL<2027> A_IWL<2026> A_IWL<2025> A_IWL<2024> A_IWL<2023> A_IWL<2022> A_IWL<2021> A_IWL<2020> A_IWL<2019> A_IWL<2018> A_IWL<2017> A_IWL<2016> A_IWL<2015> A_IWL<2014> A_IWL<2013> A_IWL<2012> A_IWL<2011> A_IWL<2010> A_IWL<2009> A_IWL<2008> A_IWL<2007> A_IWL<2006> A_IWL<2005> A_IWL<2004> A_IWL<2003> A_IWL<2002> A_IWL<2001> A_IWL<2000> A_IWL<1999> A_IWL<1998> A_IWL<1997> A_IWL<1996> A_IWL<1995> A_IWL<1994> A_IWL<1993> A_IWL<1992> A_IWL<1991> A_IWL<1990> A_IWL<1989> A_IWL<1988> A_IWL<1987> A_IWL<1986> A_IWL<1985> A_IWL<1984> A_IWL<1983> A_IWL<1982> A_IWL<1981> A_IWL<1980> A_IWL<1979> A_IWL<1978> A_IWL<1977> A_IWL<1976> A_IWL<1975> A_IWL<1974> A_IWL<1973> A_IWL<1972> A_IWL<1971> A_IWL<1970> A_IWL<1969> A_IWL<1968> A_IWL<1967> A_IWL<1966> A_IWL<1965> A_IWL<1964> A_IWL<1963> A_IWL<1962> A_IWL<1961> A_IWL<1960> A_IWL<1959> A_IWL<1958> A_IWL<1957> A_IWL<1956> A_IWL<1955> A_IWL<1954> A_IWL<1953> A_IWL<1952> A_IWL<1951> A_IWL<1950> A_IWL<1949> A_IWL<1948> A_IWL<1947> A_IWL<1946> A_IWL<1945> A_IWL<1944> A_IWL<1943> A_IWL<1942> A_IWL<1941> A_IWL<1940> A_IWL<1939> A_IWL<1938> A_IWL<1937> A_IWL<1936> A_IWL<1935> A_IWL<1934> A_IWL<1933> A_IWL<1932> A_IWL<1931> A_IWL<1930> A_IWL<1929> A_IWL<1928> A_IWL<1927> A_IWL<1926> A_IWL<1925> A_IWL<1924> A_IWL<1923> A_IWL<1922> A_IWL<1921> A_IWL<1920> A_IWL<1919> A_IWL<1918> A_IWL<1917> A_IWL<1916> A_IWL<1915> A_IWL<1914> A_IWL<1913> A_IWL<1912> A_IWL<1911> A_IWL<1910> A_IWL<1909> A_IWL<1908> A_IWL<1907> A_IWL<1906> A_IWL<1905> A_IWL<1904> A_IWL<1903> A_IWL<1902> A_IWL<1901> A_IWL<1900> A_IWL<1899> A_IWL<1898> A_IWL<1897> A_IWL<1896> A_IWL<1895> A_IWL<1894> A_IWL<1893> A_IWL<1892> A_IWL<1891> A_IWL<1890> A_IWL<1889> A_IWL<1888> A_IWL<1887> A_IWL<1886> A_IWL<1885> A_IWL<1884> A_IWL<1883> A_IWL<1882> A_IWL<1881> A_IWL<1880> A_IWL<1879> A_IWL<1878> A_IWL<1877> A_IWL<1876> A_IWL<1875> A_IWL<1874> A_IWL<1873> A_IWL<1872> A_IWL<1871> A_IWL<1870> A_IWL<1869> A_IWL<1868> A_IWL<1867> A_IWL<1866> A_IWL<1865> A_IWL<1864> A_IWL<1863> A_IWL<1862> A_IWL<1861> A_IWL<1860> A_IWL<1859> A_IWL<1858> A_IWL<1857> A_IWL<1856> A_IWL<1855> A_IWL<1854> A_IWL<1853> A_IWL<1852> A_IWL<1851> A_IWL<1850> A_IWL<1849> A_IWL<1848> A_IWL<1847> A_IWL<1846> A_IWL<1845> A_IWL<1844> A_IWL<1843> A_IWL<1842> A_IWL<1841> A_IWL<1840> A_IWL<1839> A_IWL<1838> A_IWL<1837> A_IWL<1836> A_IWL<1835> A_IWL<1834> A_IWL<1833> A_IWL<1832> A_IWL<1831> A_IWL<1830> A_IWL<1829> A_IWL<1828> A_IWL<1827> A_IWL<1826> A_IWL<1825> A_IWL<1824> A_IWL<1823> A_IWL<1822> A_IWL<1821> A_IWL<1820> A_IWL<1819> A_IWL<1818> A_IWL<1817> A_IWL<1816> A_IWL<1815> A_IWL<1814> A_IWL<1813> A_IWL<1812> A_IWL<1811> A_IWL<1810> A_IWL<1809> A_IWL<1808> A_IWL<1807> A_IWL<1806> A_IWL<1805> A_IWL<1804> A_IWL<1803> A_IWL<1802> A_IWL<1801> A_IWL<1800> A_IWL<1799> A_IWL<1798> A_IWL<1797> A_IWL<1796> A_IWL<1795> A_IWL<1794> A_IWL<1793> A_IWL<1792> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_COLUMN_pcell_0
+XCOL<6> A_BLC<13> A_BLC<12> A_BLC_TOP<13> A_BLC_TOP<12> A_BLT<13> A_BLT<12> A_BLT_TOP<13> A_BLT_TOP<12> A_IWL<1535> A_IWL<1534> A_IWL<1533> A_IWL<1532> A_IWL<1531> A_IWL<1530> A_IWL<1529> A_IWL<1528> A_IWL<1527> A_IWL<1526> A_IWL<1525> A_IWL<1524> A_IWL<1523> A_IWL<1522> A_IWL<1521> A_IWL<1520> A_IWL<1519> A_IWL<1518> A_IWL<1517> A_IWL<1516> A_IWL<1515> A_IWL<1514> A_IWL<1513> A_IWL<1512> A_IWL<1511> A_IWL<1510> A_IWL<1509> A_IWL<1508> A_IWL<1507> A_IWL<1506> A_IWL<1505> A_IWL<1504> A_IWL<1503> A_IWL<1502> A_IWL<1501> A_IWL<1500> A_IWL<1499> A_IWL<1498> A_IWL<1497> A_IWL<1496> A_IWL<1495> A_IWL<1494> A_IWL<1493> A_IWL<1492> A_IWL<1491> A_IWL<1490> A_IWL<1489> A_IWL<1488> A_IWL<1487> A_IWL<1486> A_IWL<1485> A_IWL<1484> A_IWL<1483> A_IWL<1482> A_IWL<1481> A_IWL<1480> A_IWL<1479> A_IWL<1478> A_IWL<1477> A_IWL<1476> A_IWL<1475> A_IWL<1474> A_IWL<1473> A_IWL<1472> A_IWL<1471> A_IWL<1470> A_IWL<1469> A_IWL<1468> A_IWL<1467> A_IWL<1466> A_IWL<1465> A_IWL<1464> A_IWL<1463> A_IWL<1462> A_IWL<1461> A_IWL<1460> A_IWL<1459> A_IWL<1458> A_IWL<1457> A_IWL<1456> A_IWL<1455> A_IWL<1454> A_IWL<1453> A_IWL<1452> A_IWL<1451> A_IWL<1450> A_IWL<1449> A_IWL<1448> A_IWL<1447> A_IWL<1446> A_IWL<1445> A_IWL<1444> A_IWL<1443> A_IWL<1442> A_IWL<1441> A_IWL<1440> A_IWL<1439> A_IWL<1438> A_IWL<1437> A_IWL<1436> A_IWL<1435> A_IWL<1434> A_IWL<1433> A_IWL<1432> A_IWL<1431> A_IWL<1430> A_IWL<1429> A_IWL<1428> A_IWL<1427> A_IWL<1426> A_IWL<1425> A_IWL<1424> A_IWL<1423> A_IWL<1422> A_IWL<1421> A_IWL<1420> A_IWL<1419> A_IWL<1418> A_IWL<1417> A_IWL<1416> A_IWL<1415> A_IWL<1414> A_IWL<1413> A_IWL<1412> A_IWL<1411> A_IWL<1410> A_IWL<1409> A_IWL<1408> A_IWL<1407> A_IWL<1406> A_IWL<1405> A_IWL<1404> A_IWL<1403> A_IWL<1402> A_IWL<1401> A_IWL<1400> A_IWL<1399> A_IWL<1398> A_IWL<1397> A_IWL<1396> A_IWL<1395> A_IWL<1394> A_IWL<1393> A_IWL<1392> A_IWL<1391> A_IWL<1390> A_IWL<1389> A_IWL<1388> A_IWL<1387> A_IWL<1386> A_IWL<1385> A_IWL<1384> A_IWL<1383> A_IWL<1382> A_IWL<1381> A_IWL<1380> A_IWL<1379> A_IWL<1378> A_IWL<1377> A_IWL<1376> A_IWL<1375> A_IWL<1374> A_IWL<1373> A_IWL<1372> A_IWL<1371> A_IWL<1370> A_IWL<1369> A_IWL<1368> A_IWL<1367> A_IWL<1366> A_IWL<1365> A_IWL<1364> A_IWL<1363> A_IWL<1362> A_IWL<1361> A_IWL<1360> A_IWL<1359> A_IWL<1358> A_IWL<1357> A_IWL<1356> A_IWL<1355> A_IWL<1354> A_IWL<1353> A_IWL<1352> A_IWL<1351> A_IWL<1350> A_IWL<1349> A_IWL<1348> A_IWL<1347> A_IWL<1346> A_IWL<1345> A_IWL<1344> A_IWL<1343> A_IWL<1342> A_IWL<1341> A_IWL<1340> A_IWL<1339> A_IWL<1338> A_IWL<1337> A_IWL<1336> A_IWL<1335> A_IWL<1334> A_IWL<1333> A_IWL<1332> A_IWL<1331> A_IWL<1330> A_IWL<1329> A_IWL<1328> A_IWL<1327> A_IWL<1326> A_IWL<1325> A_IWL<1324> A_IWL<1323> A_IWL<1322> A_IWL<1321> A_IWL<1320> A_IWL<1319> A_IWL<1318> A_IWL<1317> A_IWL<1316> A_IWL<1315> A_IWL<1314> A_IWL<1313> A_IWL<1312> A_IWL<1311> A_IWL<1310> A_IWL<1309> A_IWL<1308> A_IWL<1307> A_IWL<1306> A_IWL<1305> A_IWL<1304> A_IWL<1303> A_IWL<1302> A_IWL<1301> A_IWL<1300> A_IWL<1299> A_IWL<1298> A_IWL<1297> A_IWL<1296> A_IWL<1295> A_IWL<1294> A_IWL<1293> A_IWL<1292> A_IWL<1291> A_IWL<1290> A_IWL<1289> A_IWL<1288> A_IWL<1287> A_IWL<1286> A_IWL<1285> A_IWL<1284> A_IWL<1283> A_IWL<1282> A_IWL<1281> A_IWL<1280> A_IWL<1791> A_IWL<1790> A_IWL<1789> A_IWL<1788> A_IWL<1787> A_IWL<1786> A_IWL<1785> A_IWL<1784> A_IWL<1783> A_IWL<1782> A_IWL<1781> A_IWL<1780> A_IWL<1779> A_IWL<1778> A_IWL<1777> A_IWL<1776> A_IWL<1775> A_IWL<1774> A_IWL<1773> A_IWL<1772> A_IWL<1771> A_IWL<1770> A_IWL<1769> A_IWL<1768> A_IWL<1767> A_IWL<1766> A_IWL<1765> A_IWL<1764> A_IWL<1763> A_IWL<1762> A_IWL<1761> A_IWL<1760> A_IWL<1759> A_IWL<1758> A_IWL<1757> A_IWL<1756> A_IWL<1755> A_IWL<1754> A_IWL<1753> A_IWL<1752> A_IWL<1751> A_IWL<1750> A_IWL<1749> A_IWL<1748> A_IWL<1747> A_IWL<1746> A_IWL<1745> A_IWL<1744> A_IWL<1743> A_IWL<1742> A_IWL<1741> A_IWL<1740> A_IWL<1739> A_IWL<1738> A_IWL<1737> A_IWL<1736> A_IWL<1735> A_IWL<1734> A_IWL<1733> A_IWL<1732> A_IWL<1731> A_IWL<1730> A_IWL<1729> A_IWL<1728> A_IWL<1727> A_IWL<1726> A_IWL<1725> A_IWL<1724> A_IWL<1723> A_IWL<1722> A_IWL<1721> A_IWL<1720> A_IWL<1719> A_IWL<1718> A_IWL<1717> A_IWL<1716> A_IWL<1715> A_IWL<1714> A_IWL<1713> A_IWL<1712> A_IWL<1711> A_IWL<1710> A_IWL<1709> A_IWL<1708> A_IWL<1707> A_IWL<1706> A_IWL<1705> A_IWL<1704> A_IWL<1703> A_IWL<1702> A_IWL<1701> A_IWL<1700> A_IWL<1699> A_IWL<1698> A_IWL<1697> A_IWL<1696> A_IWL<1695> A_IWL<1694> A_IWL<1693> A_IWL<1692> A_IWL<1691> A_IWL<1690> A_IWL<1689> A_IWL<1688> A_IWL<1687> A_IWL<1686> A_IWL<1685> A_IWL<1684> A_IWL<1683> A_IWL<1682> A_IWL<1681> A_IWL<1680> A_IWL<1679> A_IWL<1678> A_IWL<1677> A_IWL<1676> A_IWL<1675> A_IWL<1674> A_IWL<1673> A_IWL<1672> A_IWL<1671> A_IWL<1670> A_IWL<1669> A_IWL<1668> A_IWL<1667> A_IWL<1666> A_IWL<1665> A_IWL<1664> A_IWL<1663> A_IWL<1662> A_IWL<1661> A_IWL<1660> A_IWL<1659> A_IWL<1658> A_IWL<1657> A_IWL<1656> A_IWL<1655> A_IWL<1654> A_IWL<1653> A_IWL<1652> A_IWL<1651> A_IWL<1650> A_IWL<1649> A_IWL<1648> A_IWL<1647> A_IWL<1646> A_IWL<1645> A_IWL<1644> A_IWL<1643> A_IWL<1642> A_IWL<1641> A_IWL<1640> A_IWL<1639> A_IWL<1638> A_IWL<1637> A_IWL<1636> A_IWL<1635> A_IWL<1634> A_IWL<1633> A_IWL<1632> A_IWL<1631> A_IWL<1630> A_IWL<1629> A_IWL<1628> A_IWL<1627> A_IWL<1626> A_IWL<1625> A_IWL<1624> A_IWL<1623> A_IWL<1622> A_IWL<1621> A_IWL<1620> A_IWL<1619> A_IWL<1618> A_IWL<1617> A_IWL<1616> A_IWL<1615> A_IWL<1614> A_IWL<1613> A_IWL<1612> A_IWL<1611> A_IWL<1610> A_IWL<1609> A_IWL<1608> A_IWL<1607> A_IWL<1606> A_IWL<1605> A_IWL<1604> A_IWL<1603> A_IWL<1602> A_IWL<1601> A_IWL<1600> A_IWL<1599> A_IWL<1598> A_IWL<1597> A_IWL<1596> A_IWL<1595> A_IWL<1594> A_IWL<1593> A_IWL<1592> A_IWL<1591> A_IWL<1590> A_IWL<1589> A_IWL<1588> A_IWL<1587> A_IWL<1586> A_IWL<1585> A_IWL<1584> A_IWL<1583> A_IWL<1582> A_IWL<1581> A_IWL<1580> A_IWL<1579> A_IWL<1578> A_IWL<1577> A_IWL<1576> A_IWL<1575> A_IWL<1574> A_IWL<1573> A_IWL<1572> A_IWL<1571> A_IWL<1570> A_IWL<1569> A_IWL<1568> A_IWL<1567> A_IWL<1566> A_IWL<1565> A_IWL<1564> A_IWL<1563> A_IWL<1562> A_IWL<1561> A_IWL<1560> A_IWL<1559> A_IWL<1558> A_IWL<1557> A_IWL<1556> A_IWL<1555> A_IWL<1554> A_IWL<1553> A_IWL<1552> A_IWL<1551> A_IWL<1550> A_IWL<1549> A_IWL<1548> A_IWL<1547> A_IWL<1546> A_IWL<1545> A_IWL<1544> A_IWL<1543> A_IWL<1542> A_IWL<1541> A_IWL<1540> A_IWL<1539> A_IWL<1538> A_IWL<1537> A_IWL<1536> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_COLUMN_pcell_0
+XCOL<5> A_BLC<11> A_BLC<10> A_BLC_TOP<11> A_BLC_TOP<10> A_BLT<11> A_BLT<10> A_BLT_TOP<11> A_BLT_TOP<10> A_IWL<1279> A_IWL<1278> A_IWL<1277> A_IWL<1276> A_IWL<1275> A_IWL<1274> A_IWL<1273> A_IWL<1272> A_IWL<1271> A_IWL<1270> A_IWL<1269> A_IWL<1268> A_IWL<1267> A_IWL<1266> A_IWL<1265> A_IWL<1264> A_IWL<1263> A_IWL<1262> A_IWL<1261> A_IWL<1260> A_IWL<1259> A_IWL<1258> A_IWL<1257> A_IWL<1256> A_IWL<1255> A_IWL<1254> A_IWL<1253> A_IWL<1252> A_IWL<1251> A_IWL<1250> A_IWL<1249> A_IWL<1248> A_IWL<1247> A_IWL<1246> A_IWL<1245> A_IWL<1244> A_IWL<1243> A_IWL<1242> A_IWL<1241> A_IWL<1240> A_IWL<1239> A_IWL<1238> A_IWL<1237> A_IWL<1236> A_IWL<1235> A_IWL<1234> A_IWL<1233> A_IWL<1232> A_IWL<1231> A_IWL<1230> A_IWL<1229> A_IWL<1228> A_IWL<1227> A_IWL<1226> A_IWL<1225> A_IWL<1224> A_IWL<1223> A_IWL<1222> A_IWL<1221> A_IWL<1220> A_IWL<1219> A_IWL<1218> A_IWL<1217> A_IWL<1216> A_IWL<1215> A_IWL<1214> A_IWL<1213> A_IWL<1212> A_IWL<1211> A_IWL<1210> A_IWL<1209> A_IWL<1208> A_IWL<1207> A_IWL<1206> A_IWL<1205> A_IWL<1204> A_IWL<1203> A_IWL<1202> A_IWL<1201> A_IWL<1200> A_IWL<1199> A_IWL<1198> A_IWL<1197> A_IWL<1196> A_IWL<1195> A_IWL<1194> A_IWL<1193> A_IWL<1192> A_IWL<1191> A_IWL<1190> A_IWL<1189> A_IWL<1188> A_IWL<1187> A_IWL<1186> A_IWL<1185> A_IWL<1184> A_IWL<1183> A_IWL<1182> A_IWL<1181> A_IWL<1180> A_IWL<1179> A_IWL<1178> A_IWL<1177> A_IWL<1176> A_IWL<1175> A_IWL<1174> A_IWL<1173> A_IWL<1172> A_IWL<1171> A_IWL<1170> A_IWL<1169> A_IWL<1168> A_IWL<1167> A_IWL<1166> A_IWL<1165> A_IWL<1164> A_IWL<1163> A_IWL<1162> A_IWL<1161> A_IWL<1160> A_IWL<1159> A_IWL<1158> A_IWL<1157> A_IWL<1156> A_IWL<1155> A_IWL<1154> A_IWL<1153> A_IWL<1152> A_IWL<1151> A_IWL<1150> A_IWL<1149> A_IWL<1148> A_IWL<1147> A_IWL<1146> A_IWL<1145> A_IWL<1144> A_IWL<1143> A_IWL<1142> A_IWL<1141> A_IWL<1140> A_IWL<1139> A_IWL<1138> A_IWL<1137> A_IWL<1136> A_IWL<1135> A_IWL<1134> A_IWL<1133> A_IWL<1132> A_IWL<1131> A_IWL<1130> A_IWL<1129> A_IWL<1128> A_IWL<1127> A_IWL<1126> A_IWL<1125> A_IWL<1124> A_IWL<1123> A_IWL<1122> A_IWL<1121> A_IWL<1120> A_IWL<1119> A_IWL<1118> A_IWL<1117> A_IWL<1116> A_IWL<1115> A_IWL<1114> A_IWL<1113> A_IWL<1112> A_IWL<1111> A_IWL<1110> A_IWL<1109> A_IWL<1108> A_IWL<1107> A_IWL<1106> A_IWL<1105> A_IWL<1104> A_IWL<1103> A_IWL<1102> A_IWL<1101> A_IWL<1100> A_IWL<1099> A_IWL<1098> A_IWL<1097> A_IWL<1096> A_IWL<1095> A_IWL<1094> A_IWL<1093> A_IWL<1092> A_IWL<1091> A_IWL<1090> A_IWL<1089> A_IWL<1088> A_IWL<1087> A_IWL<1086> A_IWL<1085> A_IWL<1084> A_IWL<1083> A_IWL<1082> A_IWL<1081> A_IWL<1080> A_IWL<1079> A_IWL<1078> A_IWL<1077> A_IWL<1076> A_IWL<1075> A_IWL<1074> A_IWL<1073> A_IWL<1072> A_IWL<1071> A_IWL<1070> A_IWL<1069> A_IWL<1068> A_IWL<1067> A_IWL<1066> A_IWL<1065> A_IWL<1064> A_IWL<1063> A_IWL<1062> A_IWL<1061> A_IWL<1060> A_IWL<1059> A_IWL<1058> A_IWL<1057> A_IWL<1056> A_IWL<1055> A_IWL<1054> A_IWL<1053> A_IWL<1052> A_IWL<1051> A_IWL<1050> A_IWL<1049> A_IWL<1048> A_IWL<1047> A_IWL<1046> A_IWL<1045> A_IWL<1044> A_IWL<1043> A_IWL<1042> A_IWL<1041> A_IWL<1040> A_IWL<1039> A_IWL<1038> A_IWL<1037> A_IWL<1036> A_IWL<1035> A_IWL<1034> A_IWL<1033> A_IWL<1032> A_IWL<1031> A_IWL<1030> A_IWL<1029> A_IWL<1028> A_IWL<1027> A_IWL<1026> A_IWL<1025> A_IWL<1024> A_IWL<1535> A_IWL<1534> A_IWL<1533> A_IWL<1532> A_IWL<1531> A_IWL<1530> A_IWL<1529> A_IWL<1528> A_IWL<1527> A_IWL<1526> A_IWL<1525> A_IWL<1524> A_IWL<1523> A_IWL<1522> A_IWL<1521> A_IWL<1520> A_IWL<1519> A_IWL<1518> A_IWL<1517> A_IWL<1516> A_IWL<1515> A_IWL<1514> A_IWL<1513> A_IWL<1512> A_IWL<1511> A_IWL<1510> A_IWL<1509> A_IWL<1508> A_IWL<1507> A_IWL<1506> A_IWL<1505> A_IWL<1504> A_IWL<1503> A_IWL<1502> A_IWL<1501> A_IWL<1500> A_IWL<1499> A_IWL<1498> A_IWL<1497> A_IWL<1496> A_IWL<1495> A_IWL<1494> A_IWL<1493> A_IWL<1492> A_IWL<1491> A_IWL<1490> A_IWL<1489> A_IWL<1488> A_IWL<1487> A_IWL<1486> A_IWL<1485> A_IWL<1484> A_IWL<1483> A_IWL<1482> A_IWL<1481> A_IWL<1480> A_IWL<1479> A_IWL<1478> A_IWL<1477> A_IWL<1476> A_IWL<1475> A_IWL<1474> A_IWL<1473> A_IWL<1472> A_IWL<1471> A_IWL<1470> A_IWL<1469> A_IWL<1468> A_IWL<1467> A_IWL<1466> A_IWL<1465> A_IWL<1464> A_IWL<1463> A_IWL<1462> A_IWL<1461> A_IWL<1460> A_IWL<1459> A_IWL<1458> A_IWL<1457> A_IWL<1456> A_IWL<1455> A_IWL<1454> A_IWL<1453> A_IWL<1452> A_IWL<1451> A_IWL<1450> A_IWL<1449> A_IWL<1448> A_IWL<1447> A_IWL<1446> A_IWL<1445> A_IWL<1444> A_IWL<1443> A_IWL<1442> A_IWL<1441> A_IWL<1440> A_IWL<1439> A_IWL<1438> A_IWL<1437> A_IWL<1436> A_IWL<1435> A_IWL<1434> A_IWL<1433> A_IWL<1432> A_IWL<1431> A_IWL<1430> A_IWL<1429> A_IWL<1428> A_IWL<1427> A_IWL<1426> A_IWL<1425> A_IWL<1424> A_IWL<1423> A_IWL<1422> A_IWL<1421> A_IWL<1420> A_IWL<1419> A_IWL<1418> A_IWL<1417> A_IWL<1416> A_IWL<1415> A_IWL<1414> A_IWL<1413> A_IWL<1412> A_IWL<1411> A_IWL<1410> A_IWL<1409> A_IWL<1408> A_IWL<1407> A_IWL<1406> A_IWL<1405> A_IWL<1404> A_IWL<1403> A_IWL<1402> A_IWL<1401> A_IWL<1400> A_IWL<1399> A_IWL<1398> A_IWL<1397> A_IWL<1396> A_IWL<1395> A_IWL<1394> A_IWL<1393> A_IWL<1392> A_IWL<1391> A_IWL<1390> A_IWL<1389> A_IWL<1388> A_IWL<1387> A_IWL<1386> A_IWL<1385> A_IWL<1384> A_IWL<1383> A_IWL<1382> A_IWL<1381> A_IWL<1380> A_IWL<1379> A_IWL<1378> A_IWL<1377> A_IWL<1376> A_IWL<1375> A_IWL<1374> A_IWL<1373> A_IWL<1372> A_IWL<1371> A_IWL<1370> A_IWL<1369> A_IWL<1368> A_IWL<1367> A_IWL<1366> A_IWL<1365> A_IWL<1364> A_IWL<1363> A_IWL<1362> A_IWL<1361> A_IWL<1360> A_IWL<1359> A_IWL<1358> A_IWL<1357> A_IWL<1356> A_IWL<1355> A_IWL<1354> A_IWL<1353> A_IWL<1352> A_IWL<1351> A_IWL<1350> A_IWL<1349> A_IWL<1348> A_IWL<1347> A_IWL<1346> A_IWL<1345> A_IWL<1344> A_IWL<1343> A_IWL<1342> A_IWL<1341> A_IWL<1340> A_IWL<1339> A_IWL<1338> A_IWL<1337> A_IWL<1336> A_IWL<1335> A_IWL<1334> A_IWL<1333> A_IWL<1332> A_IWL<1331> A_IWL<1330> A_IWL<1329> A_IWL<1328> A_IWL<1327> A_IWL<1326> A_IWL<1325> A_IWL<1324> A_IWL<1323> A_IWL<1322> A_IWL<1321> A_IWL<1320> A_IWL<1319> A_IWL<1318> A_IWL<1317> A_IWL<1316> A_IWL<1315> A_IWL<1314> A_IWL<1313> A_IWL<1312> A_IWL<1311> A_IWL<1310> A_IWL<1309> A_IWL<1308> A_IWL<1307> A_IWL<1306> A_IWL<1305> A_IWL<1304> A_IWL<1303> A_IWL<1302> A_IWL<1301> A_IWL<1300> A_IWL<1299> A_IWL<1298> A_IWL<1297> A_IWL<1296> A_IWL<1295> A_IWL<1294> A_IWL<1293> A_IWL<1292> A_IWL<1291> A_IWL<1290> A_IWL<1289> A_IWL<1288> A_IWL<1287> A_IWL<1286> A_IWL<1285> A_IWL<1284> A_IWL<1283> A_IWL<1282> A_IWL<1281> A_IWL<1280> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_COLUMN_pcell_0
+XCOL<4> A_BLC<9> A_BLC<8> A_BLC_TOP<9> A_BLC_TOP<8> A_BLT<9> A_BLT<8> A_BLT_TOP<9> A_BLT_TOP<8> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> A_IWL<1279> A_IWL<1278> A_IWL<1277> A_IWL<1276> A_IWL<1275> A_IWL<1274> A_IWL<1273> A_IWL<1272> A_IWL<1271> A_IWL<1270> A_IWL<1269> A_IWL<1268> A_IWL<1267> A_IWL<1266> A_IWL<1265> A_IWL<1264> A_IWL<1263> A_IWL<1262> A_IWL<1261> A_IWL<1260> A_IWL<1259> A_IWL<1258> A_IWL<1257> A_IWL<1256> A_IWL<1255> A_IWL<1254> A_IWL<1253> A_IWL<1252> A_IWL<1251> A_IWL<1250> A_IWL<1249> A_IWL<1248> A_IWL<1247> A_IWL<1246> A_IWL<1245> A_IWL<1244> A_IWL<1243> A_IWL<1242> A_IWL<1241> A_IWL<1240> A_IWL<1239> A_IWL<1238> A_IWL<1237> A_IWL<1236> A_IWL<1235> A_IWL<1234> A_IWL<1233> A_IWL<1232> A_IWL<1231> A_IWL<1230> A_IWL<1229> A_IWL<1228> A_IWL<1227> A_IWL<1226> A_IWL<1225> A_IWL<1224> A_IWL<1223> A_IWL<1222> A_IWL<1221> A_IWL<1220> A_IWL<1219> A_IWL<1218> A_IWL<1217> A_IWL<1216> A_IWL<1215> A_IWL<1214> A_IWL<1213> A_IWL<1212> A_IWL<1211> A_IWL<1210> A_IWL<1209> A_IWL<1208> A_IWL<1207> A_IWL<1206> A_IWL<1205> A_IWL<1204> A_IWL<1203> A_IWL<1202> A_IWL<1201> A_IWL<1200> A_IWL<1199> A_IWL<1198> A_IWL<1197> A_IWL<1196> A_IWL<1195> A_IWL<1194> A_IWL<1193> A_IWL<1192> A_IWL<1191> A_IWL<1190> A_IWL<1189> A_IWL<1188> A_IWL<1187> A_IWL<1186> A_IWL<1185> A_IWL<1184> A_IWL<1183> A_IWL<1182> A_IWL<1181> A_IWL<1180> A_IWL<1179> A_IWL<1178> A_IWL<1177> A_IWL<1176> A_IWL<1175> A_IWL<1174> A_IWL<1173> A_IWL<1172> A_IWL<1171> A_IWL<1170> A_IWL<1169> A_IWL<1168> A_IWL<1167> A_IWL<1166> A_IWL<1165> A_IWL<1164> A_IWL<1163> A_IWL<1162> A_IWL<1161> A_IWL<1160> A_IWL<1159> A_IWL<1158> A_IWL<1157> A_IWL<1156> A_IWL<1155> A_IWL<1154> A_IWL<1153> A_IWL<1152> A_IWL<1151> A_IWL<1150> A_IWL<1149> A_IWL<1148> A_IWL<1147> A_IWL<1146> A_IWL<1145> A_IWL<1144> A_IWL<1143> A_IWL<1142> A_IWL<1141> A_IWL<1140> A_IWL<1139> A_IWL<1138> A_IWL<1137> A_IWL<1136> A_IWL<1135> A_IWL<1134> A_IWL<1133> A_IWL<1132> A_IWL<1131> A_IWL<1130> A_IWL<1129> A_IWL<1128> A_IWL<1127> A_IWL<1126> A_IWL<1125> A_IWL<1124> A_IWL<1123> A_IWL<1122> A_IWL<1121> A_IWL<1120> A_IWL<1119> A_IWL<1118> A_IWL<1117> A_IWL<1116> A_IWL<1115> A_IWL<1114> A_IWL<1113> A_IWL<1112> A_IWL<1111> A_IWL<1110> A_IWL<1109> A_IWL<1108> A_IWL<1107> A_IWL<1106> A_IWL<1105> A_IWL<1104> A_IWL<1103> A_IWL<1102> A_IWL<1101> A_IWL<1100> A_IWL<1099> A_IWL<1098> A_IWL<1097> A_IWL<1096> A_IWL<1095> A_IWL<1094> A_IWL<1093> A_IWL<1092> A_IWL<1091> A_IWL<1090> A_IWL<1089> A_IWL<1088> A_IWL<1087> A_IWL<1086> A_IWL<1085> A_IWL<1084> A_IWL<1083> A_IWL<1082> A_IWL<1081> A_IWL<1080> A_IWL<1079> A_IWL<1078> A_IWL<1077> A_IWL<1076> A_IWL<1075> A_IWL<1074> A_IWL<1073> A_IWL<1072> A_IWL<1071> A_IWL<1070> A_IWL<1069> A_IWL<1068> A_IWL<1067> A_IWL<1066> A_IWL<1065> A_IWL<1064> A_IWL<1063> A_IWL<1062> A_IWL<1061> A_IWL<1060> A_IWL<1059> A_IWL<1058> A_IWL<1057> A_IWL<1056> A_IWL<1055> A_IWL<1054> A_IWL<1053> A_IWL<1052> A_IWL<1051> A_IWL<1050> A_IWL<1049> A_IWL<1048> A_IWL<1047> A_IWL<1046> A_IWL<1045> A_IWL<1044> A_IWL<1043> A_IWL<1042> A_IWL<1041> A_IWL<1040> A_IWL<1039> A_IWL<1038> A_IWL<1037> A_IWL<1036> A_IWL<1035> A_IWL<1034> A_IWL<1033> A_IWL<1032> A_IWL<1031> A_IWL<1030> A_IWL<1029> A_IWL<1028> A_IWL<1027> A_IWL<1026> A_IWL<1025> A_IWL<1024> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_COLUMN_pcell_0
+XCOL<3> A_BLC<7> A_BLC<6> A_BLC_TOP<7> A_BLC_TOP<6> A_BLT<7> A_BLT<6> A_BLT_TOP<7> A_BLT_TOP<6> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_COLUMN_pcell_0
+XCOL<2> A_BLC<5> A_BLC<4> A_BLC_TOP<5> A_BLC_TOP<4> A_BLT<5> A_BLT<4> A_BLT_TOP<5> A_BLT_TOP<4> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_COLUMN_pcell_0
+XCOL<1> A_BLC<3> A_BLC<2> A_BLC_TOP<3> A_BLC_TOP<2> A_BLT<3> A_BLT<2> A_BLT_TOP<3> A_BLT_TOP<2> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_COLUMN_pcell_0
+XCOL<0> A_BLC<1> A_BLC<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<1> A_BLT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_WL<255> A_WL<254> A_WL<253> A_WL<252> A_WL<251> A_WL<250> A_WL<249> A_WL<248> A_WL<247> A_WL<246> A_WL<245> A_WL<244> A_WL<243> A_WL<242> A_WL<241> A_WL<240> A_WL<239> A_WL<238> A_WL<237> A_WL<236> A_WL<235> A_WL<234> A_WL<233> A_WL<232> A_WL<231> A_WL<230> A_WL<229> A_WL<228> A_WL<227> A_WL<226> A_WL<225> A_WL<224> A_WL<223> A_WL<222> A_WL<221> A_WL<220> A_WL<219> A_WL<218> A_WL<217> A_WL<216> A_WL<215> A_WL<214> A_WL<213> A_WL<212> A_WL<211> A_WL<210> A_WL<209> A_WL<208> A_WL<207> A_WL<206> A_WL<205> A_WL<204> A_WL<203> A_WL<202> A_WL<201> A_WL<200> A_WL<199> A_WL<198> A_WL<197> A_WL<196> A_WL<195> A_WL<194> A_WL<193> A_WL<192> A_WL<191> A_WL<190> A_WL<189> A_WL<188> A_WL<187> A_WL<186> A_WL<185> A_WL<184> A_WL<183> A_WL<182> A_WL<181> A_WL<180> A_WL<179> A_WL<178> A_WL<177> A_WL<176> A_WL<175> A_WL<174> A_WL<173> A_WL<172> A_WL<171> A_WL<170> A_WL<169> A_WL<168> A_WL<167> A_WL<166> A_WL<165> A_WL<164> A_WL<163> A_WL<162> A_WL<161> A_WL<160> A_WL<159> A_WL<158> A_WL<157> A_WL<156> A_WL<155> A_WL<154> A_WL<153> A_WL<152> A_WL<151> A_WL<150> A_WL<149> A_WL<148> A_WL<147> A_WL<146> A_WL<145> A_WL<144> A_WL<143> A_WL<142> A_WL<141> A_WL<140> A_WL<139> A_WL<138> A_WL<137> A_WL<136> A_WL<135> A_WL<134> A_WL<133> A_WL<132> A_WL<131> A_WL<130> A_WL<129> A_WL<128> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> VDD_CORE VSS / RM_IHPSG13_1024x8_c2_1P_COLUMN_pcell_0
+.ENDS
+
+
+
+
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_DLY_pcell_2 A Z VDD VSS
+	XIDL<2> D<7> Z VDD VSS / RSC_IHPSG13_CDLYX1 
+	XIDL<1> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1 
+	XIDM<6> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY 
+	XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY 
+	XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY 
+	XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY 
+	XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY 
+	XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY 
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_1024x8_c2_1P_DLY_pcell_3 A Z VDD VSS
+	XIDL<4> D<7> Z VDD VSS / RSC_IHPSG13_CDLYX1 
+	XIDL<3> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1 
+	XIDL<2> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1 
+	XIDL<1> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1 
+	XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY 
+	XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY 
+	XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY 
+	XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY 
+.ENDS
+
+
+
+.SUBCKT RM_IHPSG13_1P_1024x8_c2_bm_bist A_ADDR<9> A_ADDR<8> A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> A_ADDR<1> A_ADDR<0> A_BIST_ADDR<9> A_BIST_ADDR<8> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_BM<7> A_BIST_BM<6> A_BIST_BM<5> A_BIST_BM<4> A_BIST_BM<3> A_BIST_BM<2> A_BIST_BM<1> A_BIST_BM<0> A_BIST_CLK A_BIST_DIN<7> A_BIST_DIN<6> A_BIST_DIN<5> A_BIST_DIN<4> A_BIST_DIN<3> A_BIST_DIN<2> A_BIST_DIN<1> A_BIST_DIN<0> A_BIST_EN A_BIST_MEN A_BIST_REN A_BIST_WEN A_BM<7> A_BM<6> A_BM<5> A_BM<4> A_BM<3> A_BM<2> A_BM<1> A_BM<0> A_CLK A_DIN<7> A_DIN<6> A_DIN<5> A_DIN<4> A_DIN<3> A_DIN<2> A_DIN<1> A_DIN<0> A_DLY A_DOUT<7> A_DOUT<6> A_DOUT<5> A_DOUT<4> A_DOUT<3> A_DOUT<2> A_DOUT<1> A_DOUT<0> A_MEN A_REN A_WEN VDD! VDDARRAY! VSS!
+
+
+XRAM<1> a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> a_wl_r<255> a_wl_r<254> a_wl_r<253> a_wl_r<252> a_wl_r<251> a_wl_r<250> a_wl_r<249> a_wl_r<248> a_wl_r<247> a_wl_r<246> a_wl_r<245> a_wl_r<244> a_wl_r<243> a_wl_r<242> a_wl_r<241> a_wl_r<240> a_wl_r<239> a_wl_r<238> a_wl_r<237> a_wl_r<236> a_wl_r<235> a_wl_r<234> a_wl_r<233> a_wl_r<232> a_wl_r<231> a_wl_r<230> a_wl_r<229> a_wl_r<228> a_wl_r<227> a_wl_r<226> a_wl_r<225> a_wl_r<224> a_wl_r<223> a_wl_r<222> a_wl_r<221> a_wl_r<220> a_wl_r<219> a_wl_r<218> a_wl_r<217> a_wl_r<216> a_wl_r<215> a_wl_r<214> a_wl_r<213> a_wl_r<212> a_wl_r<211> a_wl_r<210> a_wl_r<209> a_wl_r<208> a_wl_r<207> a_wl_r<206> a_wl_r<205> a_wl_r<204> a_wl_r<203> a_wl_r<202> a_wl_r<201> a_wl_r<200> a_wl_r<199> a_wl_r<198> a_wl_r<197> a_wl_r<196> a_wl_r<195> a_wl_r<194> a_wl_r<193> a_wl_r<192> a_wl_r<191> a_wl_r<190> a_wl_r<189> a_wl_r<188> a_wl_r<187> a_wl_r<186> a_wl_r<185> a_wl_r<184> a_wl_r<183> a_wl_r<182> a_wl_r<181> a_wl_r<180> a_wl_r<179> a_wl_r<178> a_wl_r<177> a_wl_r<176> a_wl_r<175> a_wl_r<174> a_wl_r<173> a_wl_r<172> a_wl_r<171> a_wl_r<170> a_wl_r<169> a_wl_r<168> a_wl_r<167> a_wl_r<166> a_wl_r<165> a_wl_r<164> a_wl_r<163> a_wl_r<162> a_wl_r<161> a_wl_r<160> a_wl_r<159> a_wl_r<158> a_wl_r<157> a_wl_r<156> a_wl_r<155> a_wl_r<154> a_wl_r<153> a_wl_r<152> a_wl_r<151> a_wl_r<150> a_wl_r<149> a_wl_r<148> a_wl_r<147> a_wl_r<146> a_wl_r<145> a_wl_r<144> a_wl_r<143> a_wl_r<142> a_wl_r<141> a_wl_r<140> a_wl_r<139> a_wl_r<138> a_wl_r<137> a_wl_r<136> a_wl_r<135> a_wl_r<134> a_wl_r<133> a_wl_r<132> a_wl_r<131> a_wl_r<130> a_wl_r<129> a_wl_r<128> a_wl_r<127> a_wl_r<126> a_wl_r<125> a_wl_r<124> a_wl_r<123> a_wl_r<122> a_wl_r<121> a_wl_r<120> a_wl_r<119> a_wl_r<118> a_wl_r<117> a_wl_r<116> a_wl_r<115> a_wl_r<114> a_wl_r<113> a_wl_r<112> a_wl_r<111> a_wl_r<110> a_wl_r<109> a_wl_r<108> a_wl_r<107> a_wl_r<106> a_wl_r<105> a_wl_r<104> a_wl_r<103> a_wl_r<102> a_wl_r<101> a_wl_r<100> a_wl_r<99> a_wl_r<98> a_wl_r<97> a_wl_r<96> a_wl_r<95> a_wl_r<94> a_wl_r<93> a_wl_r<92> a_wl_r<91> a_wl_r<90> a_wl_r<89> a_wl_r<88> a_wl_r<87> a_wl_r<86> a_wl_r<85> a_wl_r<84> a_wl_r<83> a_wl_r<82> a_wl_r<81> a_wl_r<80> a_wl_r<79> a_wl_r<78> a_wl_r<77> a_wl_r<76> a_wl_r<75> a_wl_r<74> a_wl_r<73> a_wl_r<72> a_wl_r<71> a_wl_r<70> a_wl_r<69> a_wl_r<68> a_wl_r<67> a_wl_r<66> a_wl_r<65> a_wl_r<64> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDDARRAY! VSS! / RM_IHPSG13_1024x8_c2_1P_MATRIX_pcell_1
+XRAM<0> a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> a_wl_l<255> a_wl_l<254> a_wl_l<253> a_wl_l<252> a_wl_l<251> a_wl_l<250> a_wl_l<249> a_wl_l<248> a_wl_l<247> a_wl_l<246> a_wl_l<245> a_wl_l<244> a_wl_l<243> a_wl_l<242> a_wl_l<241> a_wl_l<240> a_wl_l<239> a_wl_l<238> a_wl_l<237> a_wl_l<236> a_wl_l<235> a_wl_l<234> a_wl_l<233> a_wl_l<232> a_wl_l<231> a_wl_l<230> a_wl_l<229> a_wl_l<228> a_wl_l<227> a_wl_l<226> a_wl_l<225> a_wl_l<224> a_wl_l<223> a_wl_l<222> a_wl_l<221> a_wl_l<220> a_wl_l<219> a_wl_l<218> a_wl_l<217> a_wl_l<216> a_wl_l<215> a_wl_l<214> a_wl_l<213> a_wl_l<212> a_wl_l<211> a_wl_l<210> a_wl_l<209> a_wl_l<208> a_wl_l<207> a_wl_l<206> a_wl_l<205> a_wl_l<204> a_wl_l<203> a_wl_l<202> a_wl_l<201> a_wl_l<200> a_wl_l<199> a_wl_l<198> a_wl_l<197> a_wl_l<196> a_wl_l<195> a_wl_l<194> a_wl_l<193> a_wl_l<192> a_wl_l<191> a_wl_l<190> a_wl_l<189> a_wl_l<188> a_wl_l<187> a_wl_l<186> a_wl_l<185> a_wl_l<184> a_wl_l<183> a_wl_l<182> a_wl_l<181> a_wl_l<180> a_wl_l<179> a_wl_l<178> a_wl_l<177> a_wl_l<176> a_wl_l<175> a_wl_l<174> a_wl_l<173> a_wl_l<172> a_wl_l<171> a_wl_l<170> a_wl_l<169> a_wl_l<168> a_wl_l<167> a_wl_l<166> a_wl_l<165> a_wl_l<164> a_wl_l<163> a_wl_l<162> a_wl_l<161> a_wl_l<160> a_wl_l<159> a_wl_l<158> a_wl_l<157> a_wl_l<156> a_wl_l<155> a_wl_l<154> a_wl_l<153> a_wl_l<152> a_wl_l<151> a_wl_l<150> a_wl_l<149> a_wl_l<148> a_wl_l<147> a_wl_l<146> a_wl_l<145> a_wl_l<144> a_wl_l<143> a_wl_l<142> a_wl_l<141> a_wl_l<140> a_wl_l<139> a_wl_l<138> a_wl_l<137> a_wl_l<136> a_wl_l<135> a_wl_l<134> a_wl_l<133> a_wl_l<132> a_wl_l<131> a_wl_l<130> a_wl_l<129> a_wl_l<128> a_wl_l<127> a_wl_l<126> a_wl_l<125> a_wl_l<124> a_wl_l<123> a_wl_l<122> a_wl_l<121> a_wl_l<120> a_wl_l<119> a_wl_l<118> a_wl_l<117> a_wl_l<116> a_wl_l<115> a_wl_l<114> a_wl_l<113> a_wl_l<112> a_wl_l<111> a_wl_l<110> a_wl_l<109> a_wl_l<108> a_wl_l<107> a_wl_l<106> a_wl_l<105> a_wl_l<104> a_wl_l<103> a_wl_l<102> a_wl_l<101> a_wl_l<100> a_wl_l<99> a_wl_l<98> a_wl_l<97> a_wl_l<96> a_wl_l<95> a_wl_l<94> a_wl_l<93> a_wl_l<92> a_wl_l<91> a_wl_l<90> a_wl_l<89> a_wl_l<88> a_wl_l<87> a_wl_l<86> a_wl_l<85> a_wl_l<84> a_wl_l<83> a_wl_l<82> a_wl_l<81> a_wl_l<80> a_wl_l<79> a_wl_l<78> a_wl_l<77> a_wl_l<76> a_wl_l<75> a_wl_l<74> a_wl_l<73> a_wl_l<72> a_wl_l<71> a_wl_l<70> a_wl_l<69> a_wl_l<68> a_wl_l<67> a_wl_l<66> a_wl_l<65> a_wl_l<64> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDDARRAY! VSS! / RM_IHPSG13_1024x8_c2_1P_MATRIX_pcell_1
+
+
+XA_COLDRV<1> a_addr_col<1> a_addr_col<0> a_addr_col_r<1> a_addr_col_r<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_dclk a_dclk_p_r<0> a_rclk a_rclk_p_r<0> a_wclk a_wclk_p_r<0> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLDRV13X4
+XA_COLDRV<0> a_addr_col<1> a_addr_col<0> a_addr_col_l<1> a_addr_col_l<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_dclk a_dclk_p_l<0> a_rclk a_rclk_p_l<0> a_wclk a_wclk_p_l<0> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLDRV13X4
+
+
+XA_WLDRV<31> a_wi<255> a_wi<254> a_wi<253> a_wi<252> a_wi<251> a_wi<250> a_wi<249> a_wi<248> a_wi<247> a_wi<246> a_wi<245> a_wi<244> a_wi<243> a_wi<242> a_wi<241> a_wi<240> a_wl_r<255> a_wl_r<254> a_wl_r<253> a_wl_r<252> a_wl_r<251> a_wl_r<250> a_wl_r<249> a_wl_r<248> a_wl_r<247> a_wl_r<246> a_wl_r<245> a_wl_r<244> a_wl_r<243> a_wl_r<242> a_wl_r<241> a_wl_r<240>  VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4
+XA_WLDRV<30> a_wi<239> a_wi<238> a_wi<237> a_wi<236> a_wi<235> a_wi<234> a_wi<233> a_wi<232> a_wi<231> a_wi<230> a_wi<229> a_wi<228> a_wi<227> a_wi<226> a_wi<225> a_wi<224> a_wl_r<239> a_wl_r<238> a_wl_r<237> a_wl_r<236> a_wl_r<235> a_wl_r<234> a_wl_r<233> a_wl_r<232> a_wl_r<231> a_wl_r<230> a_wl_r<229> a_wl_r<228> a_wl_r<227> a_wl_r<226> a_wl_r<225> a_wl_r<224>  VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4
+XA_WLDRV<29> a_wi<223> a_wi<222> a_wi<221> a_wi<220> a_wi<219> a_wi<218> a_wi<217> a_wi<216> a_wi<215> a_wi<214> a_wi<213> a_wi<212> a_wi<211> a_wi<210> a_wi<209> a_wi<208> a_wl_r<223> a_wl_r<222> a_wl_r<221> a_wl_r<220> a_wl_r<219> a_wl_r<218> a_wl_r<217> a_wl_r<216> a_wl_r<215> a_wl_r<214> a_wl_r<213> a_wl_r<212> a_wl_r<211> a_wl_r<210> a_wl_r<209> a_wl_r<208>  VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4
+XA_WLDRV<28> a_wi<207> a_wi<206> a_wi<205> a_wi<204> a_wi<203> a_wi<202> a_wi<201> a_wi<200> a_wi<199> a_wi<198> a_wi<197> a_wi<196> a_wi<195> a_wi<194> a_wi<193> a_wi<192> a_wl_r<207> a_wl_r<206> a_wl_r<205> a_wl_r<204> a_wl_r<203> a_wl_r<202> a_wl_r<201> a_wl_r<200> a_wl_r<199> a_wl_r<198> a_wl_r<197> a_wl_r<196> a_wl_r<195> a_wl_r<194> a_wl_r<193> a_wl_r<192>  VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4
+XA_WLDRV<27> a_wi<191> a_wi<190> a_wi<189> a_wi<188> a_wi<187> a_wi<186> a_wi<185> a_wi<184> a_wi<183> a_wi<182> a_wi<181> a_wi<180> a_wi<179> a_wi<178> a_wi<177> a_wi<176> a_wl_r<191> a_wl_r<190> a_wl_r<189> a_wl_r<188> a_wl_r<187> a_wl_r<186> a_wl_r<185> a_wl_r<184> a_wl_r<183> a_wl_r<182> a_wl_r<181> a_wl_r<180> a_wl_r<179> a_wl_r<178> a_wl_r<177> a_wl_r<176>  VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4
+XA_WLDRV<26> a_wi<175> a_wi<174> a_wi<173> a_wi<172> a_wi<171> a_wi<170> a_wi<169> a_wi<168> a_wi<167> a_wi<166> a_wi<165> a_wi<164> a_wi<163> a_wi<162> a_wi<161> a_wi<160> a_wl_r<175> a_wl_r<174> a_wl_r<173> a_wl_r<172> a_wl_r<171> a_wl_r<170> a_wl_r<169> a_wl_r<168> a_wl_r<167> a_wl_r<166> a_wl_r<165> a_wl_r<164> a_wl_r<163> a_wl_r<162> a_wl_r<161> a_wl_r<160>  VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4
+XA_WLDRV<25> a_wi<159> a_wi<158> a_wi<157> a_wi<156> a_wi<155> a_wi<154> a_wi<153> a_wi<152> a_wi<151> a_wi<150> a_wi<149> a_wi<148> a_wi<147> a_wi<146> a_wi<145> a_wi<144> a_wl_r<159> a_wl_r<158> a_wl_r<157> a_wl_r<156> a_wl_r<155> a_wl_r<154> a_wl_r<153> a_wl_r<152> a_wl_r<151> a_wl_r<150> a_wl_r<149> a_wl_r<148> a_wl_r<147> a_wl_r<146> a_wl_r<145> a_wl_r<144>  VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4
+XA_WLDRV<24> a_wi<143> a_wi<142> a_wi<141> a_wi<140> a_wi<139> a_wi<138> a_wi<137> a_wi<136> a_wi<135> a_wi<134> a_wi<133> a_wi<132> a_wi<131> a_wi<130> a_wi<129> a_wi<128> a_wl_r<143> a_wl_r<142> a_wl_r<141> a_wl_r<140> a_wl_r<139> a_wl_r<138> a_wl_r<137> a_wl_r<136> a_wl_r<135> a_wl_r<134> a_wl_r<133> a_wl_r<132> a_wl_r<131> a_wl_r<130> a_wl_r<129> a_wl_r<128>  VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4
+XA_WLDRV<23> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wl_r<127> a_wl_r<126> a_wl_r<125> a_wl_r<124> a_wl_r<123> a_wl_r<122> a_wl_r<121> a_wl_r<120> a_wl_r<119> a_wl_r<118> a_wl_r<117> a_wl_r<116> a_wl_r<115> a_wl_r<114> a_wl_r<113> a_wl_r<112>  VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4
+XA_WLDRV<22> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wl_r<111> a_wl_r<110> a_wl_r<109> a_wl_r<108> a_wl_r<107> a_wl_r<106> a_wl_r<105> a_wl_r<104> a_wl_r<103> a_wl_r<102> a_wl_r<101> a_wl_r<100> a_wl_r<99> a_wl_r<98> a_wl_r<97> a_wl_r<96>  VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4
+XA_WLDRV<21> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wl_r<95> a_wl_r<94> a_wl_r<93> a_wl_r<92> a_wl_r<91> a_wl_r<90> a_wl_r<89> a_wl_r<88> a_wl_r<87> a_wl_r<86> a_wl_r<85> a_wl_r<84> a_wl_r<83> a_wl_r<82> a_wl_r<81> a_wl_r<80>  VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4
+XA_WLDRV<20> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wl_r<79> a_wl_r<78> a_wl_r<77> a_wl_r<76> a_wl_r<75> a_wl_r<74> a_wl_r<73> a_wl_r<72> a_wl_r<71> a_wl_r<70> a_wl_r<69> a_wl_r<68> a_wl_r<67> a_wl_r<66> a_wl_r<65> a_wl_r<64>  VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4
+XA_WLDRV<19> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48>  VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4
+XA_WLDRV<18> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32>  VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4
+XA_WLDRV<17> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16>  VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4
+XA_WLDRV<16> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0>  VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4
+XA_WLDRV<15> a_wi<255> a_wi<254> a_wi<253> a_wi<252> a_wi<251> a_wi<250> a_wi<249> a_wi<248> a_wi<247> a_wi<246> a_wi<245> a_wi<244> a_wi<243> a_wi<242> a_wi<241> a_wi<240> a_wl_l<255> a_wl_l<254> a_wl_l<253> a_wl_l<252> a_wl_l<251> a_wl_l<250> a_wl_l<249> a_wl_l<248> a_wl_l<247> a_wl_l<246> a_wl_l<245> a_wl_l<244> a_wl_l<243> a_wl_l<242> a_wl_l<241> a_wl_l<240>  VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4
+XA_WLDRV<14> a_wi<239> a_wi<238> a_wi<237> a_wi<236> a_wi<235> a_wi<234> a_wi<233> a_wi<232> a_wi<231> a_wi<230> a_wi<229> a_wi<228> a_wi<227> a_wi<226> a_wi<225> a_wi<224> a_wl_l<239> a_wl_l<238> a_wl_l<237> a_wl_l<236> a_wl_l<235> a_wl_l<234> a_wl_l<233> a_wl_l<232> a_wl_l<231> a_wl_l<230> a_wl_l<229> a_wl_l<228> a_wl_l<227> a_wl_l<226> a_wl_l<225> a_wl_l<224>  VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4
+XA_WLDRV<13> a_wi<223> a_wi<222> a_wi<221> a_wi<220> a_wi<219> a_wi<218> a_wi<217> a_wi<216> a_wi<215> a_wi<214> a_wi<213> a_wi<212> a_wi<211> a_wi<210> a_wi<209> a_wi<208> a_wl_l<223> a_wl_l<222> a_wl_l<221> a_wl_l<220> a_wl_l<219> a_wl_l<218> a_wl_l<217> a_wl_l<216> a_wl_l<215> a_wl_l<214> a_wl_l<213> a_wl_l<212> a_wl_l<211> a_wl_l<210> a_wl_l<209> a_wl_l<208>  VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4
+XA_WLDRV<12> a_wi<207> a_wi<206> a_wi<205> a_wi<204> a_wi<203> a_wi<202> a_wi<201> a_wi<200> a_wi<199> a_wi<198> a_wi<197> a_wi<196> a_wi<195> a_wi<194> a_wi<193> a_wi<192> a_wl_l<207> a_wl_l<206> a_wl_l<205> a_wl_l<204> a_wl_l<203> a_wl_l<202> a_wl_l<201> a_wl_l<200> a_wl_l<199> a_wl_l<198> a_wl_l<197> a_wl_l<196> a_wl_l<195> a_wl_l<194> a_wl_l<193> a_wl_l<192>  VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4
+XA_WLDRV<11> a_wi<191> a_wi<190> a_wi<189> a_wi<188> a_wi<187> a_wi<186> a_wi<185> a_wi<184> a_wi<183> a_wi<182> a_wi<181> a_wi<180> a_wi<179> a_wi<178> a_wi<177> a_wi<176> a_wl_l<191> a_wl_l<190> a_wl_l<189> a_wl_l<188> a_wl_l<187> a_wl_l<186> a_wl_l<185> a_wl_l<184> a_wl_l<183> a_wl_l<182> a_wl_l<181> a_wl_l<180> a_wl_l<179> a_wl_l<178> a_wl_l<177> a_wl_l<176>  VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4
+XA_WLDRV<10> a_wi<175> a_wi<174> a_wi<173> a_wi<172> a_wi<171> a_wi<170> a_wi<169> a_wi<168> a_wi<167> a_wi<166> a_wi<165> a_wi<164> a_wi<163> a_wi<162> a_wi<161> a_wi<160> a_wl_l<175> a_wl_l<174> a_wl_l<173> a_wl_l<172> a_wl_l<171> a_wl_l<170> a_wl_l<169> a_wl_l<168> a_wl_l<167> a_wl_l<166> a_wl_l<165> a_wl_l<164> a_wl_l<163> a_wl_l<162> a_wl_l<161> a_wl_l<160>  VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4
+XA_WLDRV<9> a_wi<159> a_wi<158> a_wi<157> a_wi<156> a_wi<155> a_wi<154> a_wi<153> a_wi<152> a_wi<151> a_wi<150> a_wi<149> a_wi<148> a_wi<147> a_wi<146> a_wi<145> a_wi<144> a_wl_l<159> a_wl_l<158> a_wl_l<157> a_wl_l<156> a_wl_l<155> a_wl_l<154> a_wl_l<153> a_wl_l<152> a_wl_l<151> a_wl_l<150> a_wl_l<149> a_wl_l<148> a_wl_l<147> a_wl_l<146> a_wl_l<145> a_wl_l<144>  VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4
+XA_WLDRV<8> a_wi<143> a_wi<142> a_wi<141> a_wi<140> a_wi<139> a_wi<138> a_wi<137> a_wi<136> a_wi<135> a_wi<134> a_wi<133> a_wi<132> a_wi<131> a_wi<130> a_wi<129> a_wi<128> a_wl_l<143> a_wl_l<142> a_wl_l<141> a_wl_l<140> a_wl_l<139> a_wl_l<138> a_wl_l<137> a_wl_l<136> a_wl_l<135> a_wl_l<134> a_wl_l<133> a_wl_l<132> a_wl_l<131> a_wl_l<130> a_wl_l<129> a_wl_l<128>  VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4
+XA_WLDRV<7> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wl_l<127> a_wl_l<126> a_wl_l<125> a_wl_l<124> a_wl_l<123> a_wl_l<122> a_wl_l<121> a_wl_l<120> a_wl_l<119> a_wl_l<118> a_wl_l<117> a_wl_l<116> a_wl_l<115> a_wl_l<114> a_wl_l<113> a_wl_l<112>  VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4
+XA_WLDRV<6> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wl_l<111> a_wl_l<110> a_wl_l<109> a_wl_l<108> a_wl_l<107> a_wl_l<106> a_wl_l<105> a_wl_l<104> a_wl_l<103> a_wl_l<102> a_wl_l<101> a_wl_l<100> a_wl_l<99> a_wl_l<98> a_wl_l<97> a_wl_l<96>  VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4
+XA_WLDRV<5> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wl_l<95> a_wl_l<94> a_wl_l<93> a_wl_l<92> a_wl_l<91> a_wl_l<90> a_wl_l<89> a_wl_l<88> a_wl_l<87> a_wl_l<86> a_wl_l<85> a_wl_l<84> a_wl_l<83> a_wl_l<82> a_wl_l<81> a_wl_l<80>  VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4
+XA_WLDRV<4> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wl_l<79> a_wl_l<78> a_wl_l<77> a_wl_l<76> a_wl_l<75> a_wl_l<74> a_wl_l<73> a_wl_l<72> a_wl_l<71> a_wl_l<70> a_wl_l<69> a_wl_l<68> a_wl_l<67> a_wl_l<66> a_wl_l<65> a_wl_l<64>  VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4
+XA_WLDRV<3> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48>  VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4
+XA_WLDRV<2> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32>  VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4
+XA_WLDRV<1> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16>  VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4
+XA_WLDRV<0> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0>  VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_WLDRV16X4
+
+
+XA_CTRL a_aclk_n A_BIST_CLK A_BIST_MEN A_BIST_EN A_BIST_REN A_BIST_WEN a_tiel A_CLK A_MEN a_dclk a_eclk a_pulse_h a_pulse_l a_pulse a_rclk A_REN a_cs a_wclk A_WEN VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_CTRL
+
+
+XA_ROWDEC a_addr_row<7> a_addr_row<6> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> a_cs a_eclk a_wi<255> a_wi<254> a_wi<253> a_wi<252> a_wi<251> a_wi<250> a_wi<249> a_wi<248> a_wi<247> a_wi<246> a_wi<245> a_wi<244> a_wi<243> a_wi<242> a_wi<241> a_wi<240> a_wi<239> a_wi<238> a_wi<237> a_wi<236> a_wi<235> a_wi<234> a_wi<233> a_wi<232> a_wi<231> a_wi<230> a_wi<229> a_wi<228> a_wi<227> a_wi<226> a_wi<225> a_wi<224> a_wi<223> a_wi<222> a_wi<221> a_wi<220> a_wi<219> a_wi<218> a_wi<217> a_wi<216> a_wi<215> a_wi<214> a_wi<213> a_wi<212> a_wi<211> a_wi<210> a_wi<209> a_wi<208> a_wi<207> a_wi<206> a_wi<205> a_wi<204> a_wi<203> a_wi<202> a_wi<201> a_wi<200> a_wi<199> a_wi<198> a_wi<197> a_wi<196> a_wi<195> a_wi<194> a_wi<193> a_wi<192> a_wi<191> a_wi<190> a_wi<189> a_wi<188> a_wi<187> a_wi<186> a_wi<185> a_wi<184> a_wi<183> a_wi<182> a_wi<181> a_wi<180> a_wi<179> a_wi<178> a_wi<177> a_wi<176> a_wi<175> a_wi<174> a_wi<173> a_wi<172> a_wi<171> a_wi<170> a_wi<169> a_wi<168> a_wi<167> a_wi<166> a_wi<165> a_wi<164> a_wi<163> a_wi<162> a_wi<161> a_wi<160> a_wi<159> a_wi<158> a_wi<157> a_wi<156> a_wi<155> a_wi<154> a_wi<153> a_wi<152> a_wi<151> a_wi<150> a_wi<149> a_wi<148> a_wi<147> a_wi<146> a_wi<145> a_wi<144> a_wi<143> a_wi<142> a_wi<141> a_wi<140> a_wi<139> a_wi<138> a_wi<137> a_wi<136> a_wi<135> a_wi<134> a_wi<133> a_wi<132> a_wi<131> a_wi<130> a_wi<129> a_wi<128> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_ROWDEC8
+XA_ROWREG a_aclk_n A_ADDR<9> A_ADDR<8> A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> a_addr_row<7> a_addr_row<6> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> A_BIST_ADDR<9> A_BIST_ADDR<8> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_EN VDD! VSS!  / RM_IHPSG13_1024x8_c2_1P_ROWREG8
+XA_COLDEC a_aclk_n A_ADDR<1> A_ADDR<0> a_addr_col<1> a_addr_col<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_EN VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLDEC2
+
+
+XA_DLYH a_pulse a_pulse_h VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_DLY_pcell_2
+XA_DLYL a_pulse_x a_pulse_l VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_DLY_pcell_3
+XA_DLYMUX a_pulse_h A_DLY a_pulse_x VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_DLY_MUX
+
+XCOLCTRL<7> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<7> A_BIST_DIN<7> A_BIST_EN a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> A_BM<7> a_dclk_n_r<3> a_dclk_n_r<4> a_dclk_p_r<3> a_dclk_p_r<4> A_DOUT<7> A_DIN<7> a_rclk_n_r<3> a_rclk_n_r<4> a_rclk_p_r<3> a_rclk_p_r<4> a_tieh<7> a_wclk_n_r<3> a_wclk_n_r<4> a_wclk_p_r<3> a_wclk_p_r<4> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLCTRL2
+XCOLCTRL<6> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<6> A_BIST_DIN<6> A_BIST_EN a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> A_BM<6> a_dclk_n_r<2> a_dclk_n_r<3> a_dclk_p_r<2> a_dclk_p_r<3> A_DOUT<6> A_DIN<6> a_rclk_n_r<2> a_rclk_n_r<3> a_rclk_p_r<2> a_rclk_p_r<3> a_tieh<6> a_wclk_n_r<2> a_wclk_n_r<3> a_wclk_p_r<2> a_wclk_p_r<3> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLCTRL2
+XCOLCTRL<5> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<5> A_BIST_DIN<5> A_BIST_EN a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> A_BM<5> a_dclk_n_r<1> a_dclk_n_r<2> a_dclk_p_r<1> a_dclk_p_r<2> A_DOUT<5> A_DIN<5> a_rclk_n_r<1> a_rclk_n_r<2> a_rclk_p_r<1> a_rclk_p_r<2> a_tieh<5> a_wclk_n_r<1> a_wclk_n_r<2> a_wclk_p_r<1> a_wclk_p_r<2> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLCTRL2
+XCOLCTRL<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<4> A_BIST_DIN<4> A_BIST_EN a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> A_BM<4> a_dclk_n_r<0> a_dclk_n_r<1> a_dclk_p_r<0> a_dclk_p_r<1> A_DOUT<4> A_DIN<4> a_rclk_n_r<0> a_rclk_n_r<1> a_rclk_p_r<0> a_rclk_p_r<1> a_tieh<4> a_wclk_n_r<0> a_wclk_n_r<1> a_wclk_p_r<0> a_wclk_p_r<1> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLCTRL2
+XCOLCTRL<3> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<0> A_BIST_DIN<0> A_BIST_EN a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> A_BM<0> a_dclk_n_l<3> a_dclk_n_l<4> a_dclk_p_l<3> a_dclk_p_l<4> A_DOUT<0> A_DIN<0> a_rclk_n_l<3> a_rclk_n_l<4> a_rclk_p_l<3> a_rclk_p_l<4> a_tieh<0> a_wclk_n_l<3> a_wclk_n_l<4> a_wclk_p_l<3> a_wclk_p_l<4> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLCTRL2
+XCOLCTRL<2> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<1> A_BIST_DIN<1> A_BIST_EN a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> A_BM<1> a_dclk_n_l<2> a_dclk_n_l<3> a_dclk_p_l<2> a_dclk_p_l<3> A_DOUT<1> A_DIN<1> a_rclk_n_l<2> a_rclk_n_l<3> a_rclk_p_l<2> a_rclk_p_l<3> a_tieh<1> a_wclk_n_l<2> a_wclk_n_l<3> a_wclk_p_l<2> a_wclk_p_l<3> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLCTRL2
+XCOLCTRL<1> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<2> A_BIST_DIN<2> A_BIST_EN a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> A_BM<2> a_dclk_n_l<1> a_dclk_n_l<2> a_dclk_p_l<1> a_dclk_p_l<2> A_DOUT<2> A_DIN<2> a_rclk_n_l<1> a_rclk_n_l<2> a_rclk_p_l<1> a_rclk_p_l<2> a_tieh<2> a_wclk_n_l<1> a_wclk_n_l<2> a_wclk_p_l<1> a_wclk_p_l<2> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLCTRL2
+XCOLCTRL<0> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<3> A_BIST_DIN<3> A_BIST_EN a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> A_BM<3> a_dclk_n_l<0> a_dclk_n_l<1> a_dclk_p_l<0> a_dclk_p_l<1> A_DOUT<3> A_DIN<3> a_rclk_n_l<0> a_rclk_n_l<1> a_rclk_p_l<0> a_rclk_p_l<1> a_tieh<3> a_wclk_n_l<0> a_wclk_n_l<1> a_wclk_p_l<0> a_wclk_p_l<1> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLCTRL2
+
+
+XDRVFILL4<1> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLDRV13_FILL4
+XDRVFILL4<2> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLDRV13_FILL4
+XCOLFILL4<1> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLDRV13_FILL4C2
+XCOLFILL4<2> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLDRV13_FILL4C2
+XCOLFILL4<3> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLDRV13_FILL4C2
+XCOLFILL4<4> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLDRV13_FILL4C2
+XCOLFILL4<5> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLDRV13_FILL4C2
+XCOLFILL4<6> VDD! VSS! / RM_IHPSG13_1024x8_c2_1P_COLDRV13_FILL4C2
+.ENDS
diff --git a/ihp-sg13g2/libs.ref/sg13g2_sram/cdl/RM_IHPSG13_1P_4096x16_c3_bm_bist.cdl b/ihp-sg13g2/libs.ref/sg13g2_sram/cdl/RM_IHPSG13_1P_4096x16_c3_bm_bist.cdl
new file mode 100644
index 00000000..5c3abf3d
--- /dev/null
+++ b/ihp-sg13g2/libs.ref/sg13g2_sram/cdl/RM_IHPSG13_1P_4096x16_c3_bm_bist.cdl
@@ -0,0 +1,6481 @@
+* ------------------------------------------------------
+*
+*		Copyright 2024 IHP PDK Authors
+*
+*		Licensed under the Apache License, Version 2.0 (the "License");
+*		you may not use this file except in compliance with the License.
+*		You may obtain a copy of the License at
+*		
+*		   https://www.apache.org/licenses/LICENSE-2.0
+*		
+*		Unless required by applicable law or agreed to in writing, software
+*		distributed under the License is distributed on an "AS IS" BASIS,
+*		WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+*		See the License for the specific language governing permissions and
+*		limitations under the License.
+*		
+*		Generated on Fri Jul 12 17:37:44 2024		
+*
+* ------------------------------------------------------ 
+
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_BITKIT_CORNER NW PW VDD VSS
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_CORNER VDD_CORE VSS
+XI16 VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_1P_BITKIT_CORNER
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_LR LWL NW PW VDD VSS
+MN1 VSS LWL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MN0 VSS net9 VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> 
++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> 
++ A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS
+XI0<15> A_WL<15> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_LR
+XI0<14> A_WL<14> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_LR
+XI0<13> A_WL<13> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_LR
+XI0<12> A_WL<12> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_LR
+XI0<11> A_WL<11> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_LR
+XI0<10> A_WL<10> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_LR
+XI0<9> A_WL<9> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_LR
+XI0<8> A_WL<8> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_LR
+XI0<7> A_WL<7> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_LR
+XI0<6> A_WL<6> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_LR
+XI0<5> A_WL<5> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_LR
+XI0<4> A_WL<4> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_LR
+XI0<3> A_WL<3> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_LR
+XI0<2> A_WL<2> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_LR
+XI0<1> A_WL<1> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_LR
+XI0<0> A_WL<0> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_LR
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL BLC_BOT BLC_TOP BLT_BOT BLT_TOP LWL NW PW 
++ RWL VDD VSS
+MN0 NC NT VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MN1 NT NC VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MN3 NC RWL BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MN2 BLT_BOT LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0
+MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0
+R1 BLC_BOT BLC_TOP lvsres w=2.6e-07 l=6e-07
+R0 BLT_BOT BLT_TOP lvsres w=2.6e-07 l=6e-07
+R2 RWL LWL lvsres w=2.6e-07 l=6e-07
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> 
++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> 
++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> 
++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> 
++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> 
++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE 
++ VSS
+XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_RWL<15> 
++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL
+XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_RWL<14> VDD_CORE 
++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL
+XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_RWL<13> VDD_CORE 
++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL
+XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_RWL<12> VDD_CORE 
++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL
+XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_RWL<11> VDD_CORE 
++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL
+XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_RWL<10> VDD_CORE 
++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL
+XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_RWL<9> VDD_CORE 
++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL
+XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_RWL<8> VDD_CORE 
++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL
+XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_RWL<7> VDD_CORE 
++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL
+XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_RWL<6> VDD_CORE 
++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL
+XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_RWL<5> VDD_CORE 
++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL
+XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_RWL<4> VDD_CORE 
++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL
+XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_RWL<3> VDD_CORE 
++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL
+XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_RWL<2> VDD_CORE 
++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL
+XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_RWL<1> VDD_CORE 
++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL
+XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_RWL<0> VDD_CORE 
++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL
+XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> 
++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL
+XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> VDD_CORE 
++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL
+XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> VDD_CORE 
++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL
+XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> VDD_CORE 
++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL
+XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> VDD_CORE 
++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL
+XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> VDD_CORE 
++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL
+XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> VDD_CORE 
++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL
+XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> VDD_CORE 
++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL
+XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> VDD_CORE 
++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL
+XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> VDD_CORE 
++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL
+XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> VDD_CORE 
++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL
+XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> VDD_CORE 
++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL
+XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> VDD_CORE 
++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL
+XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> VDD_CORE 
++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL
+XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> VDD_CORE 
++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL
+XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> VDD_CORE 
++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_CELL
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_TB BLC BLT NW PW VDD VSS
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> 
++ VDD_CORE VSS
+XEDGE<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_TB
+XEDGE<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_TB
+.ENDS
+
+.SUBCKT RSC_IHPSG13_CBUFX4 A Z VDD VSS
+MN0 net9 A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN1 Z net9 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0
+MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP1 Z net9 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> 
++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> 
++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> 
++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> 
++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O 
++ VDD VSS
+XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4
+XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4
+XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4
+.ENDS
+.SUBCKT RSC_IHPSG13_WLDRVX4 A Z VDD VSS
+MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0
+MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0
+MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> 
++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> 
++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS
+XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4
+.ENDS
+.SUBCKT RSC_IHPSG13_FILLCAP8 VDD VSS
+MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=4.98u l=130.00n ng=6 nrd=0 
++ nrs=0
+MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=6.48u l=385.000n ng=4 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_LHPQX2 CP D Q VDD VSS
+MN3 QIN CPN net14 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0
+MN2 net14 net10 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN5 net21 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN6 QIN CP net21 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 nrs=0
+MN1 net10 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN4 Q QIN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MP2 QIN CP net16 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0
+MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP4 Q QIN VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP3 net10 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 net16 net10 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP6 QIN CPN net20 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP5 net20 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_NAND2X2 A B Z VDD VSS
+MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MN0 Z B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MN1 net7 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_CINVX4 A Z VDD VSS
+MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0
+MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_CINVX2 A Z VDD VSS
+MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0
+MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_INVX2 A Z VDD VSS
+MN0 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_NAND3X2 A B C Z VDD VSS
+MP2 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP0 Z C VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MN1 net12 B net16 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MN0 Z C net12 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MN2 net16 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_NOR3X2 A B C Z VDD VSS
+MP0 net13 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP2 Z C net10 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP1 net10 B net13 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MN1 Z B VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0
+MN0 Z C VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0
+MN2 Z A VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_FILLCAP4 VDD VSS
+MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=130.00n ng=3 nrd=0 
++ nrs=0
+MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=385.000n ng=2 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_MET2RES A B
+R0 B A lvsres w=2.6e-07 l=6e-07
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT 
++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> 
++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS
+XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2
+XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2
+XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2
+XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2
+XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2
+XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2
+XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2
+XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2
+XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4
+XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2
+XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2
+XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2
+XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2
+XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4
+XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES
+XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> 
++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> 
++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> 
++ VDD VSS
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> 
++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> 
++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> 
++ WL_O<0> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04
+.ENDS
+.SUBCKT RSC_IHPSG13_CINVX8 A Z VDD VSS
+MN0 Z A VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0
+MP0 Z A VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_DFNQMX2IX1 BE BI CN D QI QIN VDD VSS
+MN15 net026 BI VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN14 MXI_OUT BE net026 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN1 net025 D VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN0 MXI_OUT BEN net025 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN10 QI CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 nrs=0
+MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN9 net37 MXI_OUT VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN5 QI CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0
+MN4 net25 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN2 QIN QI VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN13 BEN BE VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP15 MXI_OUT BEN net027 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP14 net027 BI VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP1 MXI_OUT BE net024 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP0 net024 D VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP13 BEN BE VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP3 QI CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0
+MP2 net27 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP10 net36 MXI_OUT VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP7 QIN QI VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP9 QI CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 nrs=0
+MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> 
++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> 
++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+.SUBCKT RSC_IHPSG13_CDLYX1 A Z VDD VSS
+MN1 net010 net032 VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 
++ nrd=0 nrs=0
+MN2 net032 A net014 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 
++ nrs=0
+MN0 Z net032 net010 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 
++ nrs=0
+MN3 net014 A VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 
++ nrs=0
+MP1 Z net032 net07 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 
++ nrs=0
+MP3 net011 A VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 
++ nrs=0
+MP0 net07 net032 VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 
++ nrd=0 nrs=0
+MP2 net032 A net011 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_CDLYX1_DUMMY A Z VDD VSS
+MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=300.0n ng=3 nrd=0 
++ nrs=0
+MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=640.00n ng=2 nrd=0 
++ nrs=0
+R0 Z A lvsres w=2.6e-07 l=6e-07
+.ENDS
+
+.SUBCKT RSC_IHPSG13_MX2IX1 A0 A1 S ZN VDD VSS
+MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0
+MP3 ZN SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0
+MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 ZN S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0
+MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN5 SN S VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0
+MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN2 ZN S net13 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0
+MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN0 ZN SN net15 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_DLY_MUX A SEL Z VDD VSS
+XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2
+XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1
+XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1
+XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1
+XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1
+.ENDS
+.SUBCKT RSC_IHPSG13_DFNQX2 CN D Q VDD VSS
+MN0 Q QIN_SL VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN10 QIN_SL CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN9 net37 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN5 QIN_SL CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN4 net25 QI_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN2 QI_SL QIN_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP0 Q QIN_SL VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 
++ nrs=0
+MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP3 QIN_SL CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP2 net27 QI_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP10 net36 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP7 QI_SL QIN_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP9 QIN_SL CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_CNAND2X2 A B Z VDD VSS
+MN0 Z B net6 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MN1 net6 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_CGATEPX4 CP E Q VDD VSS
+MN1 net08 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN2 net019 net08 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN3 QIN CP net019 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0
+MN6 Q net015 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 
++ nrs=0
+MN5 net015 net08 net018 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN8 QIN CPN net023 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN7 net023 E VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN4 net018 CP VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0
+MP3 net08 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP2 QIN CPN net017 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 net017 net08 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0
+MP8 QIN CP net024 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP7 net024 E VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP4 net015 CP VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 
++ nrs=0
+MP6 Q net015 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 
++ nrs=0
+MP5 net015 net08 VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_CBUFX8 A Z VDD VSS
+MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0
+MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0
+MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0
+MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_CDLYX2 A Z VDD VSS
+MN2 net4 A net9 VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0
+MN0 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN1 net9 A VSS VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0
+MP2 net4 A net10 VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0
+MP1 net10 A VDD VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0
+MP0 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_MX2X2 A0 A1 S Z VDD VSS
+MP6 Z net010 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 
++ nrs=0
+MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0
+MP3 net010 SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 net010 S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN6 Z net010 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN5 SN S VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 nrs=0
+MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN2 net010 S net13 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN0 net010 SN net15 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_AND2X2 A B Z VDD VSS
+MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0
+MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0
+MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_TIEL Z VDD VSS
+MN0 Z net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP0 net2 net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_XOR2X2 A B Z VDD VSS
+MP8 net012 B net7 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP7 net011 net3 net012 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP6 Z net012 VDD VDD sg13_lv_pmos m=1 w=1.535u l=130.00n ng=1 nrd=0 
++ nrs=0
+MP2 net7 A VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP4 net011 net7 VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP5 net3 B VDD VDD sg13_lv_pmos m=1 w=580.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN7 net012 B net011 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN6 net7 net3 net012 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN5 Z net012 VSS VSS sg13_lv_nmos m=1 w=775.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN2 net7 A VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN4 net3 B VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN3 net011 net7 VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 
++ nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_OA12X1 A B C Z VDD VSS
+MN2 net7 C VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN3 Z net17 VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN1 net17 B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MN0 net17 A net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MP0 net24 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP3 Z net17 VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 net17 B net24 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP2 net17 C VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I 
++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I 
++ ROW_CS WCLK WE_I VDD VSS
+XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2
+XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2
+XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2
+XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2
+XI77 col_we net9 net016 VDD VSS / RSC_IHPSG13_CNAND2X2
+XI76 col_re net9 net018 VDD VSS / RSC_IHPSG13_CNAND2X2
+XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4
+XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4
+XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8
+XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2
+XI8 net9 net8 VDD VSS / RSC_IHPSG13_CINVX2
+XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2
+XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2
+XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2
+XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2
+XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2
+XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2
+XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL
+XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4
+XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4
+XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4
+XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4
+XI6 PULSE_L PULSE_H net9 VDD VSS / RSC_IHPSG13_XOR2X2
+XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8
+XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8
+XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> 
++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> 
++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS
+XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI1<3> PADR<1> PADR<0> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2
+XI1<2> PADR<1> NADR<0> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2
+XI1<1> NADR<1> PADR<0> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2
+XI1<0> NADR<1> NADR<0> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2
+XI16<37> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<36> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<35> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<34> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<33> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<32> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<31> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<30> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2
+XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2
+XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2
+XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2
+XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL
+XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL
+XI17<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL
+XI17<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL
+XI17<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL
+XI17<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL
+.ENDS
+.SUBCKT RSC_IHPSG13_NOR2X2 A B Z VDD VSS
+MP1 Z B net9 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MN0 Z B VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MN1 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_CINVX4_WN A Z VDD VSS
+MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0
+MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_BLDRV BLC BLC_SEL BLT BLT_SEL PRE_N SEL_P WR_ONE WR_ZERO 
++ VDD VSS
+XCDEC SEL_P WR_ZERO BLC_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2
+XTDEC SEL_P WR_ONE BLT_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2
+MTWN BLT BLT_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MCWN BLC BLC_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MCWP BLC BLC_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 
++ nrd=0 nrs=0
+MTWP BLT BLT_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 
++ nrd=0 nrs=0
+MTSP BLT_SEL SEL_N BLT VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 
++ nrs=0
+MTPR BLT PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 
++ nrs=0
+MCSP BLC_SEL SEL_N BLC VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 
++ nrs=0
+MCPR BLC PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 
++ nrs=0
+XI86 SEL_P SEL_N VDD VSS / RSC_IHPSG13_INVX2
+XTINV BLC_PMOS_DRIVE BLT_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2
+XCINV BLT_PMOS_DRIVE BLC_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2
+.ENDS
+.SUBCKT RSC_IHPSG13_TIEH Z VDD VSS
+MN0 net2 net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP0 Z net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_MET3RES A B
+R0 B A lvsres w=2.6e-07 l=6e-07
+.ENDS
+.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2 CP DN DP QN QP VDD VSS
+MN12 SN RN DIFFP VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0
+MN13 TAIL CP VSS VSS sg13_lv_nmos m=1 w=2.4u l=130.00n ng=2 nrd=0 nrs=0
+MN9 DIFFP DP TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0
+MN10 DIFFN DN TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0
+MN11 RN SN DIFFN VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0
+MN19 net33 SN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN20 QN QP net37 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MN18 net37 RN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN17 QP QN net33 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MP15 SN RN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0
+MP16 RN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0
+MP14 DIFFP CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP12 RN SN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0
+MP13 DIFFN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP11 SN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0
+MP19 QN QP VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0
+MP20 QP SN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0
+MP18 QN RN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0
+MP17 QP QN VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_CBUFX2 A Z VDD VSS
+MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=540.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=1.1u l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_INVX4 A Z VDD VSS
+MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0
+MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> 
++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> 
++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R 
++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R 
++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS
+XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2
+XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2
+XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2
+XA_I44 A_WCLK_B_R A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES
+XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES
+XA_I91 A_RCLK_B_R A_RCLK_B_L / RSC_IHPSG13_MET3RES
+XA_R2 A_RCLK_R A_RCLK_L / RSC_IHPSG13_MET3RES
+XA_I90 A_WCLK_B_R A_WCLK_B_L / RSC_IHPSG13_MET3RES
+XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XA_I78 A_RCLK_B_R A_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XA_I50 A_WCLK_L A_WCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2
+XA_EBUF A_RCLK_R A_RCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_COLDRV13_FILL4 VDD VSS
+XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_COLDRV13_FILL4C2 VDD VSS
+XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> 
++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> 
++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> 
++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS
+XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL
+XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2
+XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net7<0> VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2
+XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2
+XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2
+XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2
+XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2
+XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2
+XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2
+XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2
+XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2
+XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+.SUBCKT RSC_IHPSG13_AND2X4 A B Z VDD VSS
+MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0
+MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0
+MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0
+MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0
+MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> 
++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> 
++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> 
++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> 
++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> 
++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> 
++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L 
++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L 
++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS
+XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2
+XA_I76 A_DO_WRITE_P A_DI_N A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4
+XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4
+XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4
+XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4
+XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4
+XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES
+XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES
+XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES
+XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES
+XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2
+XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> 
++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> 
++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> 
++ BIST_EN_I VDD VSS
+XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL
+XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL
+XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2
+XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net6<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2
+XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2
+XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2
+XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2
+XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2
+XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2
+XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2
+XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2
+XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> 
++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> 
++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> 
++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> 
++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L 
++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O 
++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS
+XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_R A_BM_I A_BM_R net23 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_I70<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XA_I44 A_BM_N A_WCLK_B_R A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_ADDR_DEC<6> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_ADDR_DEC<5> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<4> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES
+XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES
+XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES
+XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2
+XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2
+XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2
+XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_BITKIT_16x2_CORNER VDD_CORE VSS
+XI16 VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_1P_BITKIT_CORNER
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_LR A_WL B_WL NW PW VDD VSS
+MN1 VSS A_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MN0 VSS B_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> 
++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> 
++ A_WL<2> A_WL<1> A_WL<0> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> 
++ B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> 
++ B_WL<1> B_WL<0> VDD_CORE VSS
+XI0<15> A_WL<15> B_WL<15> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_LR
+XI0<14> A_WL<14> B_WL<14> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_LR
+XI0<13> A_WL<13> B_WL<13> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_LR
+XI0<12> A_WL<12> B_WL<12> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_LR
+XI0<11> A_WL<11> B_WL<11> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_LR
+XI0<10> A_WL<10> B_WL<10> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_LR
+XI0<9> A_WL<9> B_WL<9> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_LR
+XI0<8> A_WL<8> B_WL<8> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_LR
+XI0<7> A_WL<7> B_WL<7> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_LR
+XI0<6> A_WL<6> B_WL<6> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_LR
+XI0<5> A_WL<5> B_WL<5> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_LR
+XI0<4> A_WL<4> B_WL<4> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_LR
+XI0<3> A_WL<3> B_WL<3> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_LR
+XI0<2> A_WL<2> B_WL<2> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_LR
+XI0<1> A_WL<1> B_WL<1> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_LR
+XI0<0> A_WL<0> B_WL<0> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_LR
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL A_BLC_BOT A_BLC_TOP A_BLT_BOT A_BLT_TOP 
++ A_LWL A_RWL B_BLC_BOT B_BLC_TOP B_BLT_BOT B_BLT_TOP B_LWL B_RWL NW PW VDD VSS
+MN5 NC B_RWL B_BLC_BOT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MN4 B_BLT_BOT B_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MN0 NC NT VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0
+MN1 NT NC VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0
+MN3 NC A_RWL A_BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MN2 A_BLT_TOP A_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0
+MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0
+R5 B_RWL B_LWL lvsres w=2.6e-07 l=6e-07
+R4 B_BLC_BOT B_BLC_TOP lvsres w=2.6e-07 l=6e-07
+R3 B_BLT_BOT B_BLT_TOP lvsres w=2.6e-07 l=6e-07
+R1 A_BLC_BOT A_BLC_TOP lvsres w=2.6e-07 l=6e-07
+R0 A_BLT_BOT A_BLT_TOP lvsres w=2.6e-07 l=6e-07
+R2 A_RWL A_LWL lvsres w=2.6e-07 l=6e-07
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> 
++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> 
++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> 
++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> 
++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> 
++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> 
++ B_BLC_BOT<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_BOT<1> B_BLT_BOT<0> 
++ B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> 
++ B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> 
++ B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> 
++ B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> 
++ B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS
+XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_XWL<15> A_RWL<15> 
++ B_BLC_TOP<1> B_RBLC<15> B_BLT_TOP<1> B_RBLT<15> B_XWL<15> B_RWL<15> 
++ VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL
+XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_XWL<14> A_RWL<14> 
++ B_RBLC<14> B_RBLC<15> B_RBLT<14> B_RBLT<15> B_XWL<14> B_RWL<14> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL
+XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_XWL<13> A_RWL<13> 
++ B_RBLC<14> B_RBLC<13> B_RBLT<14> B_RBLT<13> B_XWL<13> B_RWL<13> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL
+XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_XWL<12> A_RWL<12> 
++ B_RBLC<12> B_RBLC<13> B_RBLT<12> B_RBLT<13> B_XWL<12> B_RWL<12> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL
+XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_XWL<11> A_RWL<11> 
++ B_RBLC<12> B_RBLC<11> B_RBLT<12> B_RBLT<11> B_XWL<11> B_RWL<11> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL
+XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_XWL<10> A_RWL<10> 
++ B_RBLC<10> B_RBLC<11> B_RBLT<10> B_RBLT<11> B_XWL<10> B_RWL<10> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL
+XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_XWL<9> A_RWL<9> 
++ B_RBLC<10> B_RBLC<9> B_RBLT<10> B_RBLT<9> B_XWL<9> B_RWL<9> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL
+XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_XWL<8> A_RWL<8> B_RBLC<8> 
++ B_RBLC<9> B_RBLT<8> B_RBLT<9> B_XWL<8> B_RWL<8> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL
+XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_XWL<7> A_RWL<7> B_RBLC<8> 
++ B_RBLC<7> B_RBLT<8> B_RBLT<7> B_XWL<7> B_RWL<7> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL
+XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_XWL<6> A_RWL<6> B_RBLC<6> 
++ B_RBLC<7> B_RBLT<6> B_RBLT<7> B_XWL<6> B_RWL<6> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL
+XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_XWL<5> A_RWL<5> B_RBLC<6> 
++ B_RBLC<5> B_RBLT<6> B_RBLT<5> B_XWL<5> B_RWL<5> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL
+XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_XWL<4> A_RWL<4> B_RBLC<4> 
++ B_RBLC<5> B_RBLT<4> B_RBLT<5> B_XWL<4> B_RWL<4> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL
+XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_XWL<3> A_RWL<3> B_RBLC<4> 
++ B_RBLC<3> B_RBLT<4> B_RBLT<3> B_XWL<3> B_RWL<3> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL
+XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_XWL<2> A_RWL<2> B_RBLC<2> 
++ B_RBLC<3> B_RBLT<2> B_RBLT<3> B_XWL<2> B_RWL<2> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL
+XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_XWL<1> A_RWL<1> B_RBLC<2> 
++ B_RBLC<1> B_RBLT<2> B_RBLT<1> B_XWL<1> B_RWL<1> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL
+XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_XWL<0> A_RWL<0> 
++ B_BLC_BOT<1> B_RBLC<1> B_BLT_BOT<1> B_RBLT<1> B_XWL<0> B_RWL<0> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL
+XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> A_XWL<15> 
++ B_BLC_TOP<0> B_LBLC<15> B_BLT_TOP<0> B_LBLT<15> B_LWL<15> B_XWL<15> 
++ VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL
+XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> A_XWL<14> 
++ B_LBLC<14> B_LBLC<15> B_LBLT<14> B_LBLT<15> B_LWL<14> B_XWL<14> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL
+XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> A_XWL<13> 
++ B_LBLC<14> B_LBLC<13> B_LBLT<14> B_LBLT<13> B_LWL<13> B_XWL<13> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL
+XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> A_XWL<12> 
++ B_LBLC<12> B_LBLC<13> B_LBLT<12> B_LBLT<13> B_LWL<12> B_XWL<12> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL
+XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> A_XWL<11> 
++ B_LBLC<12> B_LBLC<11> B_LBLT<12> B_LBLT<11> B_LWL<11> B_XWL<11> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL
+XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> A_XWL<10> 
++ B_LBLC<10> B_LBLC<11> B_LBLT<10> B_LBLT<11> B_LWL<10> B_XWL<10> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL
+XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> A_XWL<9> 
++ B_LBLC<10> B_LBLC<9> B_LBLT<10> B_LBLT<9> B_LWL<9> B_XWL<9> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL
+XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> A_XWL<8> B_LBLC<8> 
++ B_LBLC<9> B_LBLT<8> B_LBLT<9> B_LWL<8> B_XWL<8> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL
+XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> A_XWL<7> B_LBLC<8> 
++ B_LBLC<7> B_LBLT<8> B_LBLT<7> B_LWL<7> B_XWL<7> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL
+XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> A_XWL<6> B_LBLC<6> 
++ B_LBLC<7> B_LBLT<6> B_LBLT<7> B_LWL<6> B_XWL<6> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL
+XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> A_XWL<5> B_LBLC<6> 
++ B_LBLC<5> B_LBLT<6> B_LBLT<5> B_LWL<5> B_XWL<5> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL
+XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> A_XWL<4> B_LBLC<4> 
++ B_LBLC<5> B_LBLT<4> B_LBLT<5> B_LWL<4> B_XWL<4> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL
+XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> A_XWL<3> B_LBLC<4> 
++ B_LBLC<3> B_LBLT<4> B_LBLT<3> B_LWL<3> B_XWL<3> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL
+XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> A_XWL<2> B_LBLC<2> 
++ B_LBLC<3> B_LBLT<2> B_LBLT<3> B_LWL<2> B_XWL<2> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL
+XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> A_XWL<1> B_LBLC<2> 
++ B_LBLC<1> B_LBLT<2> B_LBLT<1> B_LWL<1> B_XWL<1> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL
+XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> A_XWL<0> 
++ B_BLC_BOT<0> B_LBLC<1> B_BLT_BOT<0> B_LBLT<1> B_LWL<0> B_XWL<0> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_CELL
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_TB A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> 
++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS
+XEDGE<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_TB
+XEDGE<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_TB
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_BITKIT_TAP A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> 
++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS
+XIEDGEBP_COL1<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_TB
+XIEDGEBP_COL1<0> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_TB
+XIEDGEBP_COL2<1> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_TB
+XIEDGEBP_COL2<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_EDGE_TB
+XITAP<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_TAP
+XITAP<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x16_c3_2P_BITKIT_TAP
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_BITKIT_TAP_LR NW PW VDD VSS
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_BITKIT_16x2_TAP_LR VDD_CORE VSS
+XCORNER<1> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_1P_BITKIT_CORNER
+XCORNER<0> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_1P_BITKIT_CORNER
+XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_1P_BITKIT_TAP_LR
+.ENDS
+
+.SUBCKT RSC_IHPSG13_CBUFX12 A Z VDD VSS
+MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=4.23u l=130.00n ng=6 nrd=0 nrs=0
+MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0
+MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0
+MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> 
++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> 
++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> 
++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> 
++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O 
++ VDD VSS
+XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12
+XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12
+XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12
+XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+.SUBCKT RSC_IHPSG13_WLDRVX12 A Z VDD VSS
+MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0
+MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0
+MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0
+MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> 
++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> 
++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS
+XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT 
++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> 
++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS
+XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2
+XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2
+XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2
+XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2
+XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4
+XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2
+XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2
+XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES
+XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES
+XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2
+XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2
+XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4
+XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2
+XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2
+XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2
+XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS
+XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2
+XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2
+XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4
+XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS
+XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2
+XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2
+XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4
+XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS
+XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2
+XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2
+XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS
+XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2
+XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> 
++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I 
++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> 
++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> 
++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> 
++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> 
++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> 
++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> 
++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> 
++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> 
++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> 
++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> 
++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> 
++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> 
++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> 
++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> 
++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> 
++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> 
++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> 
++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> 
++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> 
++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> 
++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> 
++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> 
++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> 
++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> 
++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> 
++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> 
++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> 
++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> 
++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> 
++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> 
++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> 
++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> 
++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> 
++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> 
++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> 
++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> 
++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> 
++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> 
++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> 
++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> 
++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> 
++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> 
++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> 
++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> 
++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> 
++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> 
++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> 
++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> 
++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> 
++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> 
++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> 
++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> 
++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> 
++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> 
++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> 
++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> 
++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> 
++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> 
++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> 
++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> 
++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> 
++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> 
++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> 
++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS
+XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> 
++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> 
++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> 
++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> 
++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> 
++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> 
++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> 
++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> 
++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> 
++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> 
++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> 
++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> 
++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> 
++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> 
++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> 
++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> 
++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> 
++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> 
++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> 
++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> 
++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> 
++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> 
++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> 
++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> 
++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> 
++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> 
++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> 
++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> 
++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> 
++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> 
++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> 
++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> 
++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> 
++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> 
++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> 
++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> 
++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> 
++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> 
++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> 
++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> 
++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> 
++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> 
++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> 
++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> 
++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> 
++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> 
++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> 
++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> 
++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> 
++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> 
++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> 
++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> 
++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> 
++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> 
++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> 
++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> 
++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> 
++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> 
++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> 
++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> 
++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> 
++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> 
++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> 
++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> 
++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> 
++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> 
++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> 
++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> 
++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> 
++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> 
++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> 
++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> 
++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> 
++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> 
++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> 
++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> 
++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> 
++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> 
++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> 
++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> 
++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> 
++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> 
++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> 
++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> 
++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> 
++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> 
++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04
+XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC02
+XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC02
+XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC02
+XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC02
+XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC02
+XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC02
+XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC02
+XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC02
+XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC02
+XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC02
+XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC01
+XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC01
+XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC01
+XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC01
+XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC01
+XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC01
+XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC01
+XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC01
+XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC01
+XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC01
+XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC01
+XL2<258> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<257> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<256> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<255> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<254> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<253> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<252> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<251> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<250> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<249> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<248> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<247> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<246> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<245> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<244> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<243> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<242> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<241> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<240> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<239> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<238> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<237> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<236> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<235> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<234> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<233> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<232> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<231> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<230> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<229> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<228> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<227> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<226> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<225> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<224> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<223> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<222> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<221> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<220> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<219> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<218> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<217> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<216> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<215> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<214> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<213> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<212> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<211> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<210> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<209> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<208> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<207> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<206> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<205> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<204> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<203> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<202> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<201> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<200> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<199> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<198> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<197> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<196> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<195> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<194> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<193> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<192> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<191> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<190> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<189> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<188> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<187> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<186> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<185> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<184> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<183> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<182> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<181> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<180> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<179> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<178> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<177> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<176> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<175> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<174> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<173> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC00
+XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC00
+XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC00
+XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC00
+XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC00
+XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC00
+XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC00
+XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC00
+XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC00
+XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC00
+XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC00
+XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC03
+XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC03
+XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC03
+XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC03
+XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC03
+XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC03
+XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC03
+XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC03
+XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC03
+XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC03
+XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> 
++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> 
++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> 
++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> 
++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> 
++ BIST_EN_I VDD VSS
+XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+.ENDS
+
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_DLY_MUX A SEL Z VDD VSS
+XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2
+XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1
+XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1
+XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1
+XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I 
++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I 
++ ROW_CS WCLK WE_I VDD VSS
+XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2
+XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2
+XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2
+XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2
+XI77 col_we net017 net016 VDD VSS / RSC_IHPSG13_CNAND2X2
+XI76 col_re net017 net018 VDD VSS / RSC_IHPSG13_CNAND2X2
+XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4
+XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4
+XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8
+XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2
+XI8 net017 net8 VDD VSS / RSC_IHPSG13_CINVX2
+XCAPS4<7> VDD VSS / RSC_IHPSG13_FILLCAP4
+XCAPS4<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XCAPS4<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XCAPS4<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XCAPS4<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XCAPS4<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XCAPS4<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL
+XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2
+XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2
+XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2
+XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2
+XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2
+XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4
+XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4
+XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4
+XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4
+XCAPS8<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XCAPS8<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XCAPS8<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XCAPS8<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XCAPS8<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XCAPS8<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XCAPS8<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI6 PULSE_L PULSE_H net017 VDD VSS / RSC_IHPSG13_XOR2X2
+XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2
+XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8
+XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8
+XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> 
++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> 
++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> 
++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS
+XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2
+XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net13<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net13<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2
+XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2
+XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2
+XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2
+XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2
+XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2
+XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2
+XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2
+XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2
+XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2
+XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_BLDRV A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL 
++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> 
++ A_SEL_P<1> A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> 
++ B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> 
++ B_SEL_P<2> B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS
+MA_CWN<3> A_BLC<3> A_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MA_CWN<2> A_BLC<2> A_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MA_CWN<1> A_BLC<1> A_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MA_CWN<0> A_BLC<0> A_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MA_TWN<3> A_BLT<3> A_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MA_TWN<2> A_BLT<2> A_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MA_TWN<1> A_BLT<1> A_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MA_TWN<0> A_BLT<0> A_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MB_TWN<3> B_BLT<3> B_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MB_TWN<2> B_BLT<2> B_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MB_TWN<1> B_BLT<1> B_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MB_TWN<0> B_BLT<0> B_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MB_CWN<3> B_BLC<3> B_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MB_CWN<2> B_BLC<2> B_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MB_CWN<1> B_BLC<1> B_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MB_CWN<0> B_BLC<0> B_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MA_CPR<3> A_BLC<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MA_CPR<2> A_BLC<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MA_CPR<1> A_BLC<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MA_CPR<0> A_BLC<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MA_TWP<3> A_BLT<3> A_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_TWP<2> A_BLT<2> A_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_TWP<1> A_BLT<1> A_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_TWP<0> A_BLT<0> A_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_CWP<3> A_BLC<3> A_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_CWP<2> A_BLC<2> A_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_CWP<1> A_BLC<1> A_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_CWP<0> A_BLC<0> A_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_TPR<3> A_BLT<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MA_TPR<2> A_BLT<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MA_TPR<1> A_BLT<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MA_TPR<0> A_BLT<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MA_TSP<3> A_BLT_SEL A_SEL_N<3> A_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_TSP<2> A_BLT_SEL A_SEL_N<2> A_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_TSP<1> A_BLT_SEL A_SEL_N<1> A_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_TSP<0> A_BLT_SEL A_SEL_N<0> A_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_CSP<3> A_BLC_SEL A_SEL_N<3> A_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_CSP<2> A_BLC_SEL A_SEL_N<2> A_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_CSP<1> A_BLC_SEL A_SEL_N<1> A_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_CSP<0> A_BLC_SEL A_SEL_N<0> A_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_CWP<3> B_BLC<3> B_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_CWP<2> B_BLC<2> B_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_CWP<1> B_BLC<1> B_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_CWP<0> B_BLC<0> B_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_TWP<3> B_BLT<3> B_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_TWP<2> B_BLT<2> B_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_TWP<1> B_BLT<1> B_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_TWP<0> B_BLT<0> B_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_TSP<3> B_BLT_SEL B_SEL_N<3> B_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_TSP<2> B_BLT_SEL B_SEL_N<2> B_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_TSP<1> B_BLT_SEL B_SEL_N<1> B_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_TSP<0> B_BLT_SEL B_SEL_N<0> B_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_TPR<3> B_BLT<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MB_TPR<2> B_BLT<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MB_TPR<1> B_BLT<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MB_TPR<0> B_BLT<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MB_CSP<3> B_BLC_SEL B_SEL_N<3> B_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_CSP<2> B_BLC_SEL B_SEL_N<2> B_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_CSP<1> B_BLC_SEL B_SEL_N<1> B_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_CSP<0> B_BLC_SEL B_SEL_N<0> B_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_CPR<3> B_BLC<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MB_CPR<2> B_BLC<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MB_CPR<1> B_BLC<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MB_CPR<0> B_BLC<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+XA_SEL<3> A_SEL_P<3> A_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2
+XA_SEL<2> A_SEL_P<2> A_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2
+XA_SEL<1> A_SEL_P<1> A_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2
+XA_SEL<0> A_SEL_P<0> A_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2
+XA_CINV<3> A_BLT_PMOS_DRIVE<3> A_BLC_NMOS_DRIVE<3> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XA_CINV<2> A_BLT_PMOS_DRIVE<2> A_BLC_NMOS_DRIVE<2> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XA_CINV<1> A_BLT_PMOS_DRIVE<1> A_BLC_NMOS_DRIVE<1> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XA_CINV<0> A_BLT_PMOS_DRIVE<0> A_BLC_NMOS_DRIVE<0> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XA_TINV<3> A_BLC_PMOS_DRIVE<3> A_BLT_NMOS_DRIVE<3> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XA_TINV<2> A_BLC_PMOS_DRIVE<2> A_BLT_NMOS_DRIVE<2> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XA_TINV<1> A_BLC_PMOS_DRIVE<1> A_BLT_NMOS_DRIVE<1> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XA_TINV<0> A_BLC_PMOS_DRIVE<0> A_BLT_NMOS_DRIVE<0> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XB_SEL<3> B_SEL_P<3> B_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2
+XB_SEL<2> B_SEL_P<2> B_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2
+XB_SEL<1> B_SEL_P<1> B_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2
+XB_SEL<0> B_SEL_P<0> B_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2
+XB_TINV<3> B_BLC_PMOS_DRIVE<3> B_BLT_NMOS_DRIVE<3> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XB_TINV<2> B_BLC_PMOS_DRIVE<2> B_BLT_NMOS_DRIVE<2> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XB_TINV<1> B_BLC_PMOS_DRIVE<1> B_BLT_NMOS_DRIVE<1> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XB_TINV<0> B_BLC_PMOS_DRIVE<0> B_BLT_NMOS_DRIVE<0> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XB_CINV<3> B_BLT_PMOS_DRIVE<3> B_BLC_NMOS_DRIVE<3> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XB_CINV<2> B_BLT_PMOS_DRIVE<2> B_BLC_NMOS_DRIVE<2> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XB_CINV<1> B_BLT_PMOS_DRIVE<1> B_BLC_NMOS_DRIVE<1> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XB_CINV<0> B_BLT_PMOS_DRIVE<0> B_BLC_NMOS_DRIVE<0> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XA_TDEC<3> A_SEL_P<3> A_WR_ONE A_BLT_PMOS_DRIVE<3> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XA_TDEC<2> A_SEL_P<2> A_WR_ONE A_BLT_PMOS_DRIVE<2> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XA_TDEC<1> A_SEL_P<1> A_WR_ONE A_BLT_PMOS_DRIVE<1> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XA_TDEC<0> A_SEL_P<0> A_WR_ONE A_BLT_PMOS_DRIVE<0> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XA_CDEC<3> A_SEL_P<3> A_WR_ZERO A_BLC_PMOS_DRIVE<3> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XA_CDEC<2> A_SEL_P<2> A_WR_ZERO A_BLC_PMOS_DRIVE<2> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XA_CDEC<1> A_SEL_P<1> A_WR_ZERO A_BLC_PMOS_DRIVE<1> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XA_CDEC<0> A_SEL_P<0> A_WR_ZERO A_BLC_PMOS_DRIVE<0> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XB_CDEC<3> B_SEL_P<3> B_WR_ZERO B_BLC_PMOS_DRIVE<3> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XB_CDEC<2> B_SEL_P<2> B_WR_ZERO B_BLC_PMOS_DRIVE<2> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XB_CDEC<1> B_SEL_P<1> B_WR_ZERO B_BLC_PMOS_DRIVE<1> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XB_CDEC<0> B_SEL_P<0> B_WR_ZERO B_BLC_PMOS_DRIVE<0> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XB_TDEC<3> B_SEL_P<3> B_WR_ONE B_BLT_PMOS_DRIVE<3> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XB_TDEC<2> B_SEL_P<2> B_WR_ONE B_BLT_PMOS_DRIVE<2> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XB_TDEC<1> B_SEL_P<1> B_WR_ONE B_BLT_PMOS_DRIVE<1> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XB_TDEC<0> B_SEL_P<0> B_WR_ONE B_BLT_PMOS_DRIVE<0> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+.ENDS
+.SUBCKT RSC_IHPSG13_AND2X6 A B Z VDD VSS
+MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=2.94u l=130.00n ng=3 nrd=0 nrs=0
+MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0
+MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0
+MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=4.86u l=130.00n ng=3 nrd=0 nrs=0
+MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> 
++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> 
++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> 
++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> 
++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> 
++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> 
++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> 
++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> 
++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> 
++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> 
++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> 
++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R 
++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R 
++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL<1> B_ADDR_COL<0> 
++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> 
++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I 
++ B_BIST_EN_I B_BLC<31> B_BLC<30> B_BLC<29> B_BLC<28> B_BLC<27> B_BLC<26> 
++ B_BLC<25> B_BLC<24> B_BLC<23> B_BLC<22> B_BLC<21> B_BLC<20> B_BLC<19> 
++ B_BLC<18> B_BLC<17> B_BLC<16> B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> 
++ B_BLC<11> B_BLC<10> B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> 
++ B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> 
++ B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT<23> B_BLT<22> B_BLT<21> 
++ B_BLT<20> B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT<15> B_BLT<14> 
++ B_BLT<13> B_BLT<12> B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> 
++ B_BLT<5> B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L 
++ B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L 
++ B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS
+XB_I80<1> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<1> VDD VSS / 
++ RSC_IHPSG13_AND2X2
+XB_I80<0> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<0> VDD VSS / 
++ RSC_IHPSG13_AND2X2
+XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / 
++ RSC_IHPSG13_AND2X2
+XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / 
++ RSC_IHPSG13_AND2X2
+XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XB_INV<6> B_N1<1> B_P1<1> VDD VSS / RSC_IHPSG13_CINVX4
+XB_INV<5> B_N0<1> B_P0<1> VDD VSS / RSC_IHPSG13_CINVX4
+XB_INV<4> B_N0<0> B_P0<0> VDD VSS / RSC_IHPSG13_CINVX4
+XB_INV<3> B_ADDR_COL<1> B_N1<1> VDD VSS / RSC_IHPSG13_CINVX4
+XB_INV<2> B_ADDR_COL<1> B_N1<0> VDD VSS / RSC_IHPSG13_CINVX4
+XB_INV<1> B_ADDR_COL<0> B_N0<1> VDD VSS / RSC_IHPSG13_CINVX4
+XB_INV<0> B_ADDR_COL<0> B_N0<0> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4
+XB_I81<3> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XB_I81<2> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XB_I81<1> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XB_I81<0> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XI_FILL8<78> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<77> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<76> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<75> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<74> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<73> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<72> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<71> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<70> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<69> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<68> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<67> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<66> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<65> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<64> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<63> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<62> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<61> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<60> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<59> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<58> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<57> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<56> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<55> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<54> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<53> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<52> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<51> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<50> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<49> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<48> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<47> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<46> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<45> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<44> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<43> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<42> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<41> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<40> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<39> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<38> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<37> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<36> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<35> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<34> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<33> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<32> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<31> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<30> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XAB_BLMUX<7> A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC_SEL A_BLT<31> 
++ A_BLT<30> A_BLT<29> A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<31> A_SEL_P<30> 
++ A_SEL_P<29> A_SEL_P<28> A_WR_ONE A_WR_ZERO B_BLC<31> B_BLC<30> B_BLC<29> 
++ B_BLC<28> B_BLC_SEL B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> B_BLT_SEL 
++ B_PRE_N B_SEL_P<31> B_SEL_P<30> B_SEL_P<29> B_SEL_P<28> B_WR_ONE B_WR_ZERO 
++ VDD VSS / RM_IHPSG13_4096x16_c3_2P_BLDRV
+XAB_BLMUX<6> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC_SEL A_BLT<27> 
++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<27> A_SEL_P<26> 
++ A_SEL_P<25> A_SEL_P<24> A_WR_ONE A_WR_ZERO B_BLC<27> B_BLC<26> B_BLC<25> 
++ B_BLC<24> B_BLC_SEL B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT_SEL 
++ B_PRE_N B_SEL_P<27> B_SEL_P<26> B_SEL_P<25> B_SEL_P<24> B_WR_ONE B_WR_ZERO 
++ VDD VSS / RM_IHPSG13_4096x16_c3_2P_BLDRV
+XAB_BLMUX<5> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC_SEL A_BLT<23> 
++ A_BLT<22> A_BLT<21> A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<23> A_SEL_P<22> 
++ A_SEL_P<21> A_SEL_P<20> A_WR_ONE A_WR_ZERO B_BLC<23> B_BLC<22> B_BLC<21> 
++ B_BLC<20> B_BLC_SEL B_BLT<23> B_BLT<22> B_BLT<21> B_BLT<20> B_BLT_SEL 
++ B_PRE_N B_SEL_P<23> B_SEL_P<22> B_SEL_P<21> B_SEL_P<20> B_WR_ONE B_WR_ZERO 
++ VDD VSS / RM_IHPSG13_4096x16_c3_2P_BLDRV
+XAB_BLMUX<4> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC_SEL A_BLT<19> 
++ A_BLT<18> A_BLT<17> A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<19> A_SEL_P<18> 
++ A_SEL_P<17> A_SEL_P<16> A_WR_ONE A_WR_ZERO B_BLC<19> B_BLC<18> B_BLC<17> 
++ B_BLC<16> B_BLC_SEL B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT_SEL 
++ B_PRE_N B_SEL_P<19> B_SEL_P<18> B_SEL_P<17> B_SEL_P<16> B_WR_ONE B_WR_ZERO 
++ VDD VSS / RM_IHPSG13_4096x16_c3_2P_BLDRV
+XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> 
++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> 
++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> 
++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL 
++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO 
++ VDD VSS / RM_IHPSG13_4096x16_c3_2P_BLDRV
+XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> 
++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> 
++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> 
++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N 
++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD 
++ VSS / RM_IHPSG13_4096x16_c3_2P_BLDRV
+XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> 
++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> 
++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL 
++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> 
++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_BLDRV
+XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> 
++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> 
++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL 
++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> 
++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_BLDRV
+XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8
+XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8
+XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8
+XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8
+XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8
+XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8
+XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6
+XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6
+XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6
+XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6
+XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<31> net041<0> B_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<30> net041<1> B_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<29> net041<2> B_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<28> net041<3> B_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<27> net041<4> B_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<26> net041<5> B_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<25> net041<6> B_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<24> net041<7> B_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<23> net041<8> B_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<22> net041<9> B_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<21> net041<10> B_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<20> net041<11> B_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<19> net041<12> B_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<18> net041<13> B_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<17> net041<14> B_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<16> net041<15> B_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<15> net041<16> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<14> net041<17> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<13> net041<18> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<12> net041<19> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<11> net041<20> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<10> net041<21> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<9> net041<22> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<8> net041<23> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<7> net041<24> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<6> net041<25> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<5> net041<26> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<4> net041<27> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<3> net041<28> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<2> net041<29> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<1> net041<30> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<0> net041<31> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2
+XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2
+XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net042 VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XB_DEC3<31> B_P1<1> B_P0<1> B_ADDR_DEC<7> net041<0> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<30> B_P1<1> B_P0<1> B_ADDR_DEC<6> net041<1> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<29> B_P1<1> B_P0<1> B_ADDR_DEC<5> net041<2> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<28> B_P1<1> B_P0<1> B_ADDR_DEC<4> net041<3> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<27> B_P1<1> B_P0<1> B_ADDR_DEC<3> net041<4> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<26> B_P1<1> B_P0<1> B_ADDR_DEC<2> net041<5> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<25> B_P1<1> B_P0<1> B_ADDR_DEC<1> net041<6> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<24> B_P1<1> B_P0<1> B_ADDR_DEC<0> net041<7> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<23> B_P1<1> B_N0<1> B_ADDR_DEC<7> net041<8> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<22> B_P1<1> B_N0<1> B_ADDR_DEC<6> net041<9> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<21> B_P1<1> B_N0<1> B_ADDR_DEC<5> net041<10> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<20> B_P1<1> B_N0<1> B_ADDR_DEC<4> net041<11> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<19> B_P1<1> B_N0<1> B_ADDR_DEC<3> net041<12> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<18> B_P1<1> B_N0<1> B_ADDR_DEC<2> net041<13> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<17> B_P1<1> B_N0<1> B_ADDR_DEC<1> net041<14> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<16> B_P1<1> B_N0<1> B_ADDR_DEC<0> net041<15> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<15> B_N1<0> B_P0<0> B_ADDR_DEC<7> net041<16> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<14> B_N1<0> B_P0<0> B_ADDR_DEC<6> net041<17> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<13> B_N1<0> B_P0<0> B_ADDR_DEC<5> net041<18> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<12> B_N1<0> B_P0<0> B_ADDR_DEC<4> net041<19> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<11> B_N1<0> B_P0<0> B_ADDR_DEC<3> net041<20> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<10> B_N1<0> B_P0<0> B_ADDR_DEC<2> net041<21> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<9> B_N1<0> B_P0<0> B_ADDR_DEC<1> net041<22> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<8> B_N1<0> B_P0<0> B_ADDR_DEC<0> net041<23> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<7> B_N1<0> B_N0<0> B_ADDR_DEC<7> net041<24> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<6> B_N1<0> B_N0<0> B_ADDR_DEC<6> net041<25> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<5> B_N1<0> B_N0<0> B_ADDR_DEC<5> net041<26> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<4> B_N1<0> B_N0<0> B_ADDR_DEC<4> net041<27> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<3> B_N1<0> B_N0<0> B_ADDR_DEC<3> net041<28> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<2> B_N1<0> B_N0<0> B_ADDR_DEC<2> net041<29> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<1> B_N1<0> B_N0<0> B_ADDR_DEC<1> net041<30> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<0> B_N1<0> B_N0<0> B_ADDR_DEC<0> net041<31> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES
+XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES
+XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES
+XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES
+XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES
+XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES
+XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_COLDRV13_FILL4 VDD VSS
+XI0<11> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<10> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+
+
+.SUBCKT RSC_IHPSG13_CBUFX16 A Z VDD VSS
+MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=2.115u l=130.00n ng=3 nrd=0 nrs=0
+MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=5.64u l=130.00n ng=8 nrd=0 nrs=0
+MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=13.000u l=130.00n ng=8 nrd=0 
++ nrs=0
+MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=4.89u l=130.00n ng=3 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> 
++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> 
++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> 
++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> 
++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O 
++ VDD VSS
+XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8
+XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16
+XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16
+XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16
+.ENDS
+.SUBCKT RSC_IHPSG13_WLDRVX16 A Z VDD VSS
+MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0
+MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0
+MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=12.96u l=130.00n ng=8 nrd=0 nrs=0
+MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> 
++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> 
++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS
+XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> 
++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> 
++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> 
++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> 
++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O 
++ VDD VSS
+XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4
+XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4
+XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4
+XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI1 VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> 
++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> 
++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS
+XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> 
++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> 
++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> 
++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> 
++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> 
++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> 
++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> 
++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> 
++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> 
++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> 
++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> 
++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> 
++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> 
++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> 
++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> 
++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> 
++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> 
++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> 
++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> 
++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> 
++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> 
++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> 
++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> 
++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> 
++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> 
++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> 
++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> 
++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> 
++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> 
++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> 
++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> 
++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> 
++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> 
++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> 
++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> 
++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> 
++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS
+XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC03
+XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC03
+XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC03
+XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC03
+XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC03
+XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> 
++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> 
++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> 
++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> 
++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> 
++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> 
++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> 
++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> 
++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> 
++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> 
++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> 
++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> 
++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> 
++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> 
++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> 
++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> 
++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> 
++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> 
++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> 
++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> 
++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> 
++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> 
++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> 
++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> 
++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> 
++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> 
++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> 
++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> 
++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> 
++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> 
++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> 
++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> 
++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> 
++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> 
++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> 
++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> 
++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> 
++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> 
++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04
+XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC02
+XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC02
+XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC02
+XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC02
+XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC02
+XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC00
+XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC00
+XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC00
+XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC00
+XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC00
+XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC01
+XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC01
+XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC01
+XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC01
+XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC01
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> 
++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> 
++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> 
++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> 
++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS
+XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI10 VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> 
++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> 
++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> 
++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS
+XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2
+XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net12<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net12<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2
+XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2
+XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2
+XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2
+XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2
+XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2
+XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2
+XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2
+XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2
+XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> 
++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> 
++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> 
++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> 
++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> 
++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> 
++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L 
++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L 
++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL 
++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> 
++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I 
++ B_BIST_EN_I B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> B_BLC<11> B_BLC<10> 
++ B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC<3> B_BLC<2> 
++ B_BLC<1> B_BLC<0> B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT<11> 
++ B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT<3> 
++ B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R 
++ B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L 
++ B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS
+XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2
+XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2
+XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4
+XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4
+XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4
+XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4
+XI_FILL4<26> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<25> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<24> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<23> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<22> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<21> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<20> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<19> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<18> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<17> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4
+XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4
+XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4
+XB_INV<1> B_N0 B_P0 VDD VSS / RSC_IHPSG13_CINVX4
+XB_INV<0> B_ADDR_COL B_N0 VDD VSS / RSC_IHPSG13_CINVX4
+XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4
+XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4
+XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4
+XB_I81<1> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XB_I81<0> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES
+XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES
+XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES
+XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES
+XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES
+XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES
+XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES
+XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES
+XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> 
++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> 
++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> 
++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL 
++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO 
++ VDD VSS / RM_IHPSG13_4096x16_c3_2P_BLDRV
+XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> 
++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> 
++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> 
++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N 
++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD 
++ VSS / RM_IHPSG13_4096x16_c3_2P_BLDRV
+XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> 
++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> 
++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL 
++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> 
++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_BLDRV
+XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> 
++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> 
++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL 
++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> 
++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_BLDRV
+XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2
+XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<15> net044<0> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<14> net044<1> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<13> net044<2> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<12> net044<3> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<11> net044<4> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<10> net044<5> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<9> net044<6> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<8> net044<7> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<7> net044<8> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<6> net044<9> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<5> net044<10> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<4> net044<11> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<3> net044<12> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<2> net044<13> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<1> net044<14> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<0> net044<15> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2
+XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<15> B_P0 B_ADDR_DEC<7> net044<0> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<14> B_P0 B_ADDR_DEC<6> net044<1> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<13> B_P0 B_ADDR_DEC<5> net044<2> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<12> B_P0 B_ADDR_DEC<4> net044<3> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<11> B_P0 B_ADDR_DEC<3> net044<4> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<10> B_P0 B_ADDR_DEC<2> net044<5> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<9> B_P0 B_ADDR_DEC<1> net044<6> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<8> B_P0 B_ADDR_DEC<0> net044<7> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<7> B_N0 B_ADDR_DEC<7> net044<8> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<6> B_N0 B_ADDR_DEC<6> net044<9> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<5> B_N0 B_ADDR_DEC<5> net044<10> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<4> B_N0 B_ADDR_DEC<4> net044<11> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<3> B_N0 B_ADDR_DEC<3> net044<12> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<2> B_N0 B_ADDR_DEC<2> net044<13> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<1> B_N0 B_ADDR_DEC<1> net044<14> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<0> B_N0 B_ADDR_DEC<0> net044<15> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> 
++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS
+XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC00
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04
+XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC01
+XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> 
++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> 
++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> 
++ BIST_EN_I VDD VSS
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> 
++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> 
++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> 
++ BIST_EN_I VDD VSS
+XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2
+XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL
+XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL
+XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2
+XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2
+XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2
+XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2
+XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2
+XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2
+XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2
+XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2
+XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2P CP DN DP QN QP VDD VSS
+XI_AMP CP DN DP QN QP VDD VSS / RSC_IHPSG13_DFPQD_MSAFFX2
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> 
++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> 
++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> 
++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> 
++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L 
++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O 
++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<7> B_ADDR_DEC<6> 
++ B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> 
++ B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<7> B_BLC<6> B_BLC<5> 
++ B_BLC<4> B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<7> B_BLT<6> B_BLT<5> 
++ B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R 
++ B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R 
++ B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS
+XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net044 VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2P
+XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2P
+XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> 
++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> A_ADDR_DEC<6> 
++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> 
++ B_BLC<4> B_BLC_SEL B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N 
++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_WR_ONE B_WR_ZERO 
++ VDD VSS / RM_IHPSG13_4096x16_c3_2P_BLDRV
+XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> 
++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> 
++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> 
++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N 
++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO 
++ VDD VSS / RM_IHPSG13_4096x16_c3_2P_BLDRV
+XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES
+XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES
+XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES
+XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES
+XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES
+XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES
+XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I80 B_WCLK_B_L B_RCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2
+XB_I76 B_DO_WRITE_P B_DI_N B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2
+XB_I75 B_DO_WRITE_P B_DI_R B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2
+XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2
+XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2
+XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2
+XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> 
++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> 
++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> 
++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> 
++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> 
++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> 
++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> 
++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> 
++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> 
++ WL_O<2> WL_O<1> WL_O<0> VDD VSS
+XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC02
+XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC00
+XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> 
++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> 
++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04
+XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC03
+XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC01
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> 
++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> 
++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> 
++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS
+XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> 
++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> 
++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> 
++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> 
++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O 
++ VDD VSS
+XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16
+XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16
+XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16
+XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XI1<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI1<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> 
++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> 
++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS
+XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS
+XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4
+XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2
+XI2 VDD VSS / RSC_IHPSG13_FILLCAP4
+XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS
+XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4
+XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2
+XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2
+XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI1 VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> 
++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC01
+XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC00
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04
+XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> 
++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> 
++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> 
++ BIST_EN_I VDD VSS
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> 
++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> 
++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> 
++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS
+XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2
+XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2
+XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net7<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net7<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2
+XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2
+XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2
+XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2
+XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2
+XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2
+XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2
+XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2
+XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> 
++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> 
++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> 
++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> 
++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> 
++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> 
++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> 
++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> 
++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> 
++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> 
++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> 
++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R 
++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R 
++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS
+XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / 
++ RSC_IHPSG13_AND2X2
+XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / 
++ RSC_IHPSG13_AND2X2
+XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XI80<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4
+XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_BLTMUX<31> A_BLC<31> A_BLC_SEL A_BLT<31> A_BLT_SEL A_PRE_N A_SEL_P<31> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<30> A_BLC<30> A_BLC_SEL A_BLT<30> A_BLT_SEL A_PRE_N A_SEL_P<30> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<29> A_BLC<29> A_BLC_SEL A_BLT<29> A_BLT_SEL A_PRE_N A_SEL_P<29> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<28> A_BLC<28> A_BLC_SEL A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<28> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<27> A_BLC<27> A_BLC_SEL A_BLT<27> A_BLT_SEL A_PRE_N A_SEL_P<27> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<26> A_BLC<26> A_BLC_SEL A_BLT<26> A_BLT_SEL A_PRE_N A_SEL_P<26> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<25> A_BLC<25> A_BLC_SEL A_BLT<25> A_BLT_SEL A_PRE_N A_SEL_P<25> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<24> A_BLC<24> A_BLC_SEL A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<24> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<23> A_BLC<23> A_BLC_SEL A_BLT<23> A_BLT_SEL A_PRE_N A_SEL_P<23> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<22> A_BLC<22> A_BLC_SEL A_BLT<22> A_BLT_SEL A_PRE_N A_SEL_P<22> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<21> A_BLC<21> A_BLC_SEL A_BLT<21> A_BLT_SEL A_PRE_N A_SEL_P<21> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<20> A_BLC<20> A_BLC_SEL A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<20> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<19> A_BLC<19> A_BLC_SEL A_BLT<19> A_BLT_SEL A_PRE_N A_SEL_P<19> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<18> A_BLC<18> A_BLC_SEL A_BLT<18> A_BLT_SEL A_PRE_N A_SEL_P<18> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<17> A_BLC<17> A_BLC_SEL A_BLT<17> A_BLT_SEL A_PRE_N A_SEL_P<17> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<16> A_BLC<16> A_BLC_SEL A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<16> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x16_c3_1P_BLDRV
+XA_CAPS<17> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<16> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<15> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<14> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<13> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<12> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<11> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<10> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<9> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8
+XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8
+XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8
+XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6
+XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6
+XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2
+XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES
+XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES
+XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES
+XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+.ENDS
+
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> 
++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> 
++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> 
++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> 
++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O 
++ VDD VSS
+XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8
+XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12
+XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12
+XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> 
++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> 
++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS
+XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12
+.ENDS
+
+
+
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> 
++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> 
++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> 
++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> 
++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O 
++ VDD VSS
+XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8
+XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8
+XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8
+XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+.SUBCKT RSC_IHPSG13_WLDRVX8 A Z VDD VSS
+MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0
+MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0
+MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0
+MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> 
++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> 
++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS
+XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8
+.ENDS
+
+
+
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> 
++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> 
++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS
+XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI1<3> PADR<0> PADR<1> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2
+XI1<2> NADR<0> PADR<1> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2
+XI1<1> PADR<0> NADR<1> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2
+XI1<0> NADR<0> NADR<1> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2
+XI17<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL
+XI17<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL
+XI14<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL
+XI14<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL
+XI14<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL
+XI14<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL
+XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2
+XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2
+XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2
+XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2
+XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI15<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI15<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI15<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI15<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI15<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI19<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI19<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI19<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI19<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> 
++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> 
++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R 
++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R 
++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<3> B_ADDR_DEC<2> 
++ B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<3> 
++ B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I 
++ B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R 
++ B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD 
++ VSS
+XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XB_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4
+XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2
+XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2
+XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2
+XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2
+XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2
+XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2
+XB_I44 B_WCLK_B_L B_BM_N B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XA_I44 A_WCLK_B_L A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES
+XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES
+XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES
+XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES
+XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES
+XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES
+XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES
+XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES
+XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES
+XAB_BLMUX A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> 
++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> 
++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> 
++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N 
++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO 
++ VDD VSS / RM_IHPSG13_4096x16_c3_2P_BLDRV
+XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net039 net040 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XB_I51 net039 B_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_COLDRV13_FILL4C2 VDD VSS
+XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> 
++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> 
++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> 
++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> 
++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> 
++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> 
++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> 
++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> 
++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> 
++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> 
++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> 
++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> 
++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> 
++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> 
++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> 
++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> 
++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> 
++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> 
++ VDD VSS
+XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> 
++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> 
++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> 
++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> 
++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> 
++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> 
++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> 
++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> 
++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> 
++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> 
++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> 
++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> 
++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> 
++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> 
++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04
+XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC03
+XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC03
+XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC01
+XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC01
+XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC01
+XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC02
+XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC02
+XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC00
+XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC00
+XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_2P_DEC00
+XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> 
++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> 
++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> 
++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> 
++ BIST_ADDR_I<0> BIST_EN_I VDD VSS
+XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<0> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> 
++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> 
++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> 
++ VDD VSS
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> 
++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> 
++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> 
++ WL_O<0> VDD VSS / RM_IHPSG13_4096x16_c3_2P_DEC04
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_2P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> 
++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> 
++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net7<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net7<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net7<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net7<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI12<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_BITKIT_TAP BLC BLT NW PW VDD VSS
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> 
++ VDD_CORE VSS
+XITAP<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_4096x16_c3_1P_BITKIT_TAP
+XITAP<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_4096x16_c3_1P_BITKIT_TAP
+XIEDGEBP_COL1<1> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE 
++ VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_TB
+XIEDGEBP_COL1<0> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE 
++ VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_TB
+XIEDGEBP_COL2<1> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE 
++ VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_TB
+XIEDGEBP_COL2<0> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE 
++ VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_EDGE_TB
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_TAP_LR VDD_CORE VSS
+XCORNER<1> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_1P_BITKIT_CORNER
+XCORNER<0> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_1P_BITKIT_CORNER
+XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x16_c3_1P_BITKIT_TAP_LR
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS
+XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4
+XI0 VDD VSS / RSC_IHPSG13_FILLCAP4
+XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS
+XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4
+XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2
+XI2 VDD VSS / RSC_IHPSG13_FILLCAP4
+XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> 
++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> 
++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> 
++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> 
++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> 
++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> 
++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> 
++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> 
++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> 
++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> 
++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> 
++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> 
++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> 
++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> 
++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> 
++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> 
++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> 
++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> 
++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> 
++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> 
++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> 
++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> 
++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> 
++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> 
++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> 
++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> 
++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> 
++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> 
++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> 
++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> 
++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> 
++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> 
++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> 
++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> 
++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> 
++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> 
++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS
+XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC03
+XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC03
+XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC03
+XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC03
+XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC03
+XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC02
+XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC02
+XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC02
+XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC02
+XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC02
+XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC00
+XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC00
+XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC00
+XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC00
+XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC00
+XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> 
++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> 
++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> 
++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> 
++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> 
++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> 
++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> 
++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> 
++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> 
++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> 
++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> 
++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> 
++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> 
++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> 
++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> 
++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> 
++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> 
++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> 
++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> 
++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> 
++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> 
++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> 
++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> 
++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> 
++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> 
++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> 
++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> 
++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> 
++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> 
++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> 
++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> 
++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> 
++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> 
++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> 
++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> 
++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> 
++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> 
++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> 
++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04
+XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC01
+XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC01
+XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC01
+XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC01
+XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC01
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> 
++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> 
++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> 
++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> 
++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS
+XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> 
++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I 
++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> 
++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> 
++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> 
++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> 
++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> 
++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> 
++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> 
++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> 
++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> 
++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> 
++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> 
++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> 
++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> 
++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> 
++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> 
++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> 
++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> 
++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> 
++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> 
++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> 
++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> 
++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> 
++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> 
++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> 
++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> 
++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> 
++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> 
++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> 
++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> 
++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> 
++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> 
++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> 
++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> 
++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> 
++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> 
++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> 
++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> 
++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> 
++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> 
++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> 
++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> 
++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> 
++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> 
++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> 
++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> 
++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> 
++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> 
++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> 
++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> 
++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> 
++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> 
++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> 
++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> 
++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> 
++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> 
++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> 
++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> 
++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> 
++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> 
++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> 
++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> 
++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> 
++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> 
++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS
+XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC03
+XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC03
+XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC03
+XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC03
+XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC03
+XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC03
+XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC03
+XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC03
+XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC03
+XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC03
+XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC00
+XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC00
+XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC00
+XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC00
+XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC00
+XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC00
+XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC00
+XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC00
+XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC00
+XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC00
+XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC00
+XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> 
++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> 
++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> 
++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> 
++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> 
++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> 
++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> 
++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> 
++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> 
++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> 
++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> 
++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> 
++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> 
++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> 
++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> 
++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> 
++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> 
++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> 
++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> 
++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> 
++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> 
++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> 
++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> 
++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> 
++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> 
++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> 
++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> 
++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> 
++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> 
++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> 
++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> 
++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> 
++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> 
++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> 
++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> 
++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> 
++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> 
++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> 
++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> 
++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> 
++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> 
++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> 
++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> 
++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> 
++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> 
++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> 
++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> 
++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> 
++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> 
++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> 
++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> 
++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> 
++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> 
++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> 
++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> 
++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> 
++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> 
++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> 
++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> 
++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> 
++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> 
++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> 
++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> 
++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> 
++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> 
++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> 
++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> 
++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> 
++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> 
++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> 
++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> 
++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> 
++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> 
++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> 
++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> 
++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> 
++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> 
++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> 
++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> 
++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> 
++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> 
++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> 
++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> 
++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> 
++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> 
++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> 
++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04
+XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC01
+XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC01
+XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC01
+XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC01
+XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC01
+XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC01
+XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC01
+XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC01
+XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC01
+XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC01
+XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC01
+XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC02
+XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC02
+XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC02
+XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC02
+XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC02
+XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC02
+XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC02
+XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC02
+XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC02
+XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC02
+XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> 
++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> 
++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> 
++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> 
++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> 
++ BIST_EN_I VDD VSS
+XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+.ENDS
+
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> 
++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> 
++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> 
++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> 
++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> 
++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> 
++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> 
++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> 
++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> 
++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> 
++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> 
++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> 
++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> 
++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> 
++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> 
++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> 
++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> 
++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> 
++ VDD VSS
+XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC03
+XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC03
+XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC02
+XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC02
+XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> 
++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> 
++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> 
++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> 
++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> 
++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> 
++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> 
++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> 
++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> 
++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> 
++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> 
++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> 
++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> 
++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> 
++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04
+XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC00
+XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC00
+XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC00
+XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC01
+XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC01
+XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC01
+XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> 
++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> 
++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> 
++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> 
++ BIST_ADDR_I<0> BIST_EN_I VDD VSS
+XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> 
++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> 
++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> 
++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> 
++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O 
++ VDD VSS
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8
+XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8
+XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> 
++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> 
++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS
+XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8
+.ENDS
+
+
+
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> 
++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> 
++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> 
++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> 
++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> 
++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> 
++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> 
++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> 
++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> 
++ WL_O<2> WL_O<1> WL_O<0> VDD VSS
+XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC03
+XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC00
+XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC01
+XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / 
++ RM_IHPSG13_4096x16_c3_1P_DEC02
+XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> 
++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> 
++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x16_c3_1P_DEC04
+XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> 
++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> 
++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> 
++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS
+XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0 A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<511> A_LWL<510> A_LWL<509> A_LWL<508> A_LWL<507> A_LWL<506> A_LWL<505> A_LWL<504> A_LWL<503> A_LWL<502> A_LWL<501> A_LWL<500> A_LWL<499> A_LWL<498> A_LWL<497> A_LWL<496> A_LWL<495> A_LWL<494> A_LWL<493> A_LWL<492> A_LWL<491> A_LWL<490> A_LWL<489> A_LWL<488> A_LWL<487> A_LWL<486> A_LWL<485> A_LWL<484> A_LWL<483> A_LWL<482> A_LWL<481> A_LWL<480> A_LWL<479> A_LWL<478> A_LWL<477> A_LWL<476> A_LWL<475> A_LWL<474> A_LWL<473> A_LWL<472> A_LWL<471> A_LWL<470> A_LWL<469> A_LWL<468> A_LWL<467> A_LWL<466> A_LWL<465> A_LWL<464> A_LWL<463> A_LWL<462> A_LWL<461> A_LWL<460> A_LWL<459> A_LWL<458> A_LWL<457> A_LWL<456> A_LWL<455> A_LWL<454> A_LWL<453> A_LWL<452> A_LWL<451> A_LWL<450> A_LWL<449> A_LWL<448> A_LWL<447> A_LWL<446> A_LWL<445> A_LWL<444> A_LWL<443> A_LWL<442> A_LWL<441> A_LWL<440> A_LWL<439> A_LWL<438> A_LWL<437> A_LWL<436> A_LWL<435> A_LWL<434> A_LWL<433> A_LWL<432> A_LWL<431> A_LWL<430> A_LWL<429> A_LWL<428> A_LWL<427> A_LWL<426> A_LWL<425> A_LWL<424> A_LWL<423> A_LWL<422> A_LWL<421> A_LWL<420> A_LWL<419> A_LWL<418> A_LWL<417> A_LWL<416> A_LWL<415> A_LWL<414> A_LWL<413> A_LWL<412> A_LWL<411> A_LWL<410> A_LWL<409> A_LWL<408> A_LWL<407> A_LWL<406> A_LWL<405> A_LWL<404> A_LWL<403> A_LWL<402> A_LWL<401> A_LWL<400> A_LWL<399> A_LWL<398> A_LWL<397> A_LWL<396> A_LWL<395> A_LWL<394> A_LWL<393> A_LWL<392> A_LWL<391> A_LWL<390> A_LWL<389> A_LWL<388> A_LWL<387> A_LWL<386> A_LWL<385> A_LWL<384> A_LWL<383> A_LWL<382> A_LWL<381> A_LWL<380> A_LWL<379> A_LWL<378> A_LWL<377> A_LWL<376> A_LWL<375> A_LWL<374> A_LWL<373> A_LWL<372> A_LWL<371> A_LWL<370> A_LWL<369> A_LWL<368> A_LWL<367> A_LWL<366> A_LWL<365> A_LWL<364> A_LWL<363> A_LWL<362> A_LWL<361> A_LWL<360> A_LWL<359> A_LWL<358> A_LWL<357> A_LWL<356> A_LWL<355> A_LWL<354> A_LWL<353> A_LWL<352> A_LWL<351> A_LWL<350> A_LWL<349> A_LWL<348> A_LWL<347> A_LWL<346> A_LWL<345> A_LWL<344> A_LWL<343> A_LWL<342> A_LWL<341> A_LWL<340> A_LWL<339> A_LWL<338> A_LWL<337> A_LWL<336> A_LWL<335> A_LWL<334> A_LWL<333> A_LWL<332> A_LWL<331> A_LWL<330> A_LWL<329> A_LWL<328> A_LWL<327> A_LWL<326> A_LWL<325> A_LWL<324> A_LWL<323> A_LWL<322> A_LWL<321> A_LWL<320> A_LWL<319> A_LWL<318> A_LWL<317> A_LWL<316> A_LWL<315> A_LWL<314> A_LWL<313> A_LWL<312> A_LWL<311> A_LWL<310> A_LWL<309> A_LWL<308> A_LWL<307> A_LWL<306> A_LWL<305> A_LWL<304> A_LWL<303> A_LWL<302> A_LWL<301> A_LWL<300> A_LWL<299> A_LWL<298> A_LWL<297> A_LWL<296> A_LWL<295> A_LWL<294> A_LWL<293> A_LWL<292> A_LWL<291> A_LWL<290> A_LWL<289> A_LWL<288> A_LWL<287> A_LWL<286> A_LWL<285> A_LWL<284> A_LWL<283> A_LWL<282> A_LWL<281> A_LWL<280> A_LWL<279> A_LWL<278> A_LWL<277> A_LWL<276> A_LWL<275> A_LWL<274> A_LWL<273> A_LWL<272> A_LWL<271> A_LWL<270> A_LWL<269> A_LWL<268> A_LWL<267> A_LWL<266> A_LWL<265> A_LWL<264> A_LWL<263> A_LWL<262> A_LWL<261> A_LWL<260> A_LWL<259> A_LWL<258> A_LWL<257> A_LWL<256> A_LWL<255> A_LWL<254> A_LWL<253> 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A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE VSS
+XRAM<32> A_BLC<61> A_BLC<60> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<61> A_BLT<60> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<511> A_LWL<510> A_LWL<509> A_LWL<508> A_LWL<507> A_LWL<506> A_LWL<505> A_LWL<504> A_LWL<503> A_LWL<502> A_LWL<501> A_LWL<500> A_LWL<499> A_LWL<498> A_LWL<497> A_LWL<496> A_RWL<511> A_RWL<510> A_RWL<509> A_RWL<508> A_RWL<507> A_RWL<506> A_RWL<505> A_RWL<504> A_RWL<503> A_RWL<502> A_RWL<501> A_RWL<500> A_RWL<499> A_RWL<498> A_RWL<497> A_RWL<496> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM
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+XRAM<30> A_BLC<57> A_BLC<56> A_BLC<59> A_BLC<58> A_BLT<57> A_BLT<56> A_BLT<59> A_BLT<58> A_LWL<479> A_LWL<478> A_LWL<477> A_LWL<476> A_LWL<475> A_LWL<474> A_LWL<473> A_LWL<472> A_LWL<471> A_LWL<470> A_LWL<469> A_LWL<468> A_LWL<467> A_LWL<466> A_LWL<465> A_LWL<464> A_RWL<479> A_RWL<478> A_RWL<477> A_RWL<476> A_RWL<475> A_RWL<474> A_RWL<473> A_RWL<472> A_RWL<471> A_RWL<470> A_RWL<469> A_RWL<468> A_RWL<467> A_RWL<466> A_RWL<465> A_RWL<464> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM
+XRAM<29> A_BLC<55> A_BLC<54> A_BLC<57> A_BLC<56> A_BLT<55> A_BLT<54> A_BLT<57> A_BLT<56> A_LWL<463> A_LWL<462> A_LWL<461> A_LWL<460> A_LWL<459> A_LWL<458> A_LWL<457> A_LWL<456> A_LWL<455> A_LWL<454> A_LWL<453> A_LWL<452> A_LWL<451> A_LWL<450> A_LWL<449> A_LWL<448> A_RWL<463> A_RWL<462> A_RWL<461> A_RWL<460> A_RWL<459> A_RWL<458> A_RWL<457> A_RWL<456> A_RWL<455> A_RWL<454> A_RWL<453> A_RWL<452> A_RWL<451> A_RWL<450> A_RWL<449> A_RWL<448> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM
+XRAM<28> A_BLC<53> A_BLC<52> A_BLC<55> A_BLC<54> A_BLT<53> A_BLT<52> A_BLT<55> A_BLT<54> A_LWL<447> A_LWL<446> A_LWL<445> A_LWL<444> A_LWL<443> A_LWL<442> A_LWL<441> A_LWL<440> A_LWL<439> A_LWL<438> A_LWL<437> A_LWL<436> A_LWL<435> A_LWL<434> A_LWL<433> A_LWL<432> A_RWL<447> A_RWL<446> A_RWL<445> A_RWL<444> A_RWL<443> A_RWL<442> A_RWL<441> A_RWL<440> A_RWL<439> A_RWL<438> A_RWL<437> A_RWL<436> A_RWL<435> A_RWL<434> A_RWL<433> A_RWL<432> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM
+XRAM<27> A_BLC<51> A_BLC<50> A_BLC<53> A_BLC<52> A_BLT<51> A_BLT<50> A_BLT<53> A_BLT<52> A_LWL<431> A_LWL<430> A_LWL<429> A_LWL<428> A_LWL<427> A_LWL<426> A_LWL<425> A_LWL<424> A_LWL<423> A_LWL<422> A_LWL<421> A_LWL<420> A_LWL<419> A_LWL<418> A_LWL<417> A_LWL<416> A_RWL<431> A_RWL<430> A_RWL<429> A_RWL<428> A_RWL<427> A_RWL<426> A_RWL<425> A_RWL<424> A_RWL<423> A_RWL<422> A_RWL<421> A_RWL<420> A_RWL<419> A_RWL<418> A_RWL<417> A_RWL<416> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM
+XRAM<26> A_BLC<49> A_BLC<48> A_BLC<51> A_BLC<50> A_BLT<49> A_BLT<48> A_BLT<51> A_BLT<50> A_LWL<415> A_LWL<414> A_LWL<413> A_LWL<412> A_LWL<411> A_LWL<410> A_LWL<409> A_LWL<408> A_LWL<407> A_LWL<406> A_LWL<405> A_LWL<404> A_LWL<403> A_LWL<402> A_LWL<401> A_LWL<400> A_RWL<415> A_RWL<414> A_RWL<413> A_RWL<412> A_RWL<411> A_RWL<410> A_RWL<409> A_RWL<408> A_RWL<407> A_RWL<406> A_RWL<405> A_RWL<404> A_RWL<403> A_RWL<402> A_RWL<401> A_RWL<400> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM
+XRAM<25> A_BLC<47> A_BLC<46> A_BLC<49> A_BLC<48> A_BLT<47> A_BLT<46> A_BLT<49> A_BLT<48> A_LWL<399> A_LWL<398> A_LWL<397> A_LWL<396> A_LWL<395> A_LWL<394> A_LWL<393> A_LWL<392> A_LWL<391> A_LWL<390> A_LWL<389> A_LWL<388> A_LWL<387> A_LWL<386> A_LWL<385> A_LWL<384> A_RWL<399> A_RWL<398> A_RWL<397> A_RWL<396> A_RWL<395> A_RWL<394> A_RWL<393> A_RWL<392> A_RWL<391> A_RWL<390> A_RWL<389> A_RWL<388> A_RWL<387> A_RWL<386> A_RWL<385> A_RWL<384> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM
+XRAM<24> A_BLC<45> A_BLC<44> A_BLC<47> A_BLC<46> A_BLT<45> A_BLT<44> A_BLT<47> A_BLT<46> A_LWL<383> A_LWL<382> A_LWL<381> A_LWL<380> A_LWL<379> A_LWL<378> A_LWL<377> A_LWL<376> A_LWL<375> A_LWL<374> A_LWL<373> A_LWL<372> A_LWL<371> A_LWL<370> A_LWL<369> A_LWL<368> A_RWL<383> A_RWL<382> A_RWL<381> A_RWL<380> A_RWL<379> A_RWL<378> A_RWL<377> A_RWL<376> A_RWL<375> A_RWL<374> A_RWL<373> A_RWL<372> A_RWL<371> A_RWL<370> A_RWL<369> A_RWL<368> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM
+XRAM<23> A_BLC<43> A_BLC<42> A_BLC<45> A_BLC<44> A_BLT<43> A_BLT<42> A_BLT<45> A_BLT<44> A_LWL<367> A_LWL<366> A_LWL<365> A_LWL<364> A_LWL<363> A_LWL<362> A_LWL<361> A_LWL<360> A_LWL<359> A_LWL<358> A_LWL<357> A_LWL<356> A_LWL<355> A_LWL<354> A_LWL<353> A_LWL<352> A_RWL<367> A_RWL<366> A_RWL<365> A_RWL<364> A_RWL<363> A_RWL<362> A_RWL<361> A_RWL<360> A_RWL<359> A_RWL<358> A_RWL<357> A_RWL<356> A_RWL<355> A_RWL<354> A_RWL<353> A_RWL<352> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM
+XRAM<22> A_BLC<41> A_BLC<40> A_BLC<43> A_BLC<42> A_BLT<41> A_BLT<40> A_BLT<43> A_BLT<42> A_LWL<351> A_LWL<350> A_LWL<349> A_LWL<348> A_LWL<347> A_LWL<346> A_LWL<345> A_LWL<344> A_LWL<343> A_LWL<342> A_LWL<341> A_LWL<340> A_LWL<339> A_LWL<338> A_LWL<337> A_LWL<336> A_RWL<351> A_RWL<350> A_RWL<349> A_RWL<348> A_RWL<347> A_RWL<346> A_RWL<345> A_RWL<344> A_RWL<343> A_RWL<342> A_RWL<341> A_RWL<340> A_RWL<339> A_RWL<338> A_RWL<337> A_RWL<336> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM
+XRAM<21> A_BLC<39> A_BLC<38> A_BLC<41> A_BLC<40> A_BLT<39> A_BLT<38> A_BLT<41> A_BLT<40> A_LWL<335> A_LWL<334> A_LWL<333> A_LWL<332> A_LWL<331> A_LWL<330> A_LWL<329> A_LWL<328> A_LWL<327> A_LWL<326> A_LWL<325> A_LWL<324> A_LWL<323> A_LWL<322> A_LWL<321> A_LWL<320> A_RWL<335> A_RWL<334> A_RWL<333> A_RWL<332> A_RWL<331> A_RWL<330> A_RWL<329> A_RWL<328> A_RWL<327> A_RWL<326> A_RWL<325> A_RWL<324> A_RWL<323> A_RWL<322> A_RWL<321> A_RWL<320> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM
+XRAM<20> A_BLC<37> A_BLC<36> A_BLC<39> A_BLC<38> A_BLT<37> A_BLT<36> A_BLT<39> A_BLT<38> A_LWL<319> A_LWL<318> A_LWL<317> A_LWL<316> A_LWL<315> A_LWL<314> A_LWL<313> A_LWL<312> A_LWL<311> A_LWL<310> A_LWL<309> A_LWL<308> A_LWL<307> A_LWL<306> A_LWL<305> A_LWL<304> A_RWL<319> A_RWL<318> A_RWL<317> A_RWL<316> A_RWL<315> A_RWL<314> A_RWL<313> A_RWL<312> A_RWL<311> A_RWL<310> A_RWL<309> A_RWL<308> A_RWL<307> A_RWL<306> A_RWL<305> A_RWL<304> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM
+XRAM<19> A_BLC<35> A_BLC<34> A_BLC<37> A_BLC<36> A_BLT<35> A_BLT<34> A_BLT<37> A_BLT<36> A_LWL<303> A_LWL<302> A_LWL<301> A_LWL<300> A_LWL<299> A_LWL<298> A_LWL<297> A_LWL<296> A_LWL<295> A_LWL<294> A_LWL<293> A_LWL<292> A_LWL<291> A_LWL<290> A_LWL<289> A_LWL<288> A_RWL<303> A_RWL<302> A_RWL<301> A_RWL<300> A_RWL<299> A_RWL<298> A_RWL<297> A_RWL<296> A_RWL<295> A_RWL<294> A_RWL<293> A_RWL<292> A_RWL<291> A_RWL<290> A_RWL<289> A_RWL<288> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM
+XRAM<18> A_BLC<33> A_BLC<32> A_BLC<35> A_BLC<34> A_BLT<33> A_BLT<32> A_BLT<35> A_BLT<34> A_LWL<287> A_LWL<286> A_LWL<285> A_LWL<284> A_LWL<283> A_LWL<282> A_LWL<281> A_LWL<280> A_LWL<279> A_LWL<278> A_LWL<277> A_LWL<276> A_LWL<275> A_LWL<274> A_LWL<273> A_LWL<272> A_RWL<287> A_RWL<286> A_RWL<285> A_RWL<284> A_RWL<283> A_RWL<282> A_RWL<281> A_RWL<280> A_RWL<279> A_RWL<278> A_RWL<277> A_RWL<276> A_RWL<275> A_RWL<274> A_RWL<273> A_RWL<272> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM
+XRAM<17> A_BLC<31> A_BLC<30> A_BLC<33> A_BLC<32> A_BLT<31> A_BLT<30> A_BLT<33> A_BLT<32> A_LWL<271> A_LWL<270> A_LWL<269> A_LWL<268> A_LWL<267> A_LWL<266> A_LWL<265> A_LWL<264> A_LWL<263> A_LWL<262> A_LWL<261> A_LWL<260> A_LWL<259> A_LWL<258> A_LWL<257> A_LWL<256> A_RWL<271> A_RWL<270> A_RWL<269> A_RWL<268> A_RWL<267> A_RWL<266> A_RWL<265> A_RWL<264> A_RWL<263> A_RWL<262> A_RWL<261> A_RWL<260> A_RWL<259> A_RWL<258> A_RWL<257> A_RWL<256> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM
+XRAM<16> A_BLC<29> A_BLC<28> A_BLC<31> A_BLC<30> A_BLT<29> A_BLT<28> A_BLT<31> A_BLT<30> A_LWL<255> A_LWL<254> A_LWL<253> A_LWL<252> A_LWL<251> A_LWL<250> A_LWL<249> A_LWL<248> A_LWL<247> A_LWL<246> A_LWL<245> A_LWL<244> A_LWL<243> A_LWL<242> A_LWL<241> A_LWL<240> A_RWL<255> A_RWL<254> A_RWL<253> A_RWL<252> A_RWL<251> A_RWL<250> A_RWL<249> A_RWL<248> A_RWL<247> A_RWL<246> A_RWL<245> A_RWL<244> A_RWL<243> A_RWL<242> A_RWL<241> A_RWL<240> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM
+XRAM<15> A_BLC<27> A_BLC<26> A_BLC<29> A_BLC<28> A_BLT<27> A_BLT<26> A_BLT<29> A_BLT<28> A_LWL<239> A_LWL<238> A_LWL<237> A_LWL<236> A_LWL<235> A_LWL<234> A_LWL<233> A_LWL<232> A_LWL<231> A_LWL<230> A_LWL<229> A_LWL<228> A_LWL<227> A_LWL<226> A_LWL<225> A_LWL<224> A_RWL<239> A_RWL<238> A_RWL<237> A_RWL<236> A_RWL<235> A_RWL<234> A_RWL<233> A_RWL<232> A_RWL<231> A_RWL<230> A_RWL<229> A_RWL<228> A_RWL<227> A_RWL<226> A_RWL<225> A_RWL<224> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM
+XRAM<14> A_BLC<25> A_BLC<24> A_BLC<27> A_BLC<26> A_BLT<25> A_BLT<24> A_BLT<27> A_BLT<26> A_LWL<223> A_LWL<222> A_LWL<221> A_LWL<220> A_LWL<219> A_LWL<218> A_LWL<217> A_LWL<216> A_LWL<215> A_LWL<214> A_LWL<213> A_LWL<212> A_LWL<211> A_LWL<210> A_LWL<209> A_LWL<208> A_RWL<223> A_RWL<222> A_RWL<221> A_RWL<220> A_RWL<219> A_RWL<218> A_RWL<217> A_RWL<216> A_RWL<215> A_RWL<214> A_RWL<213> A_RWL<212> A_RWL<211> A_RWL<210> A_RWL<209> A_RWL<208> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM
+XRAM<13> A_BLC<23> A_BLC<22> A_BLC<25> A_BLC<24> A_BLT<23> A_BLT<22> A_BLT<25> A_BLT<24> A_LWL<207> A_LWL<206> A_LWL<205> A_LWL<204> A_LWL<203> A_LWL<202> A_LWL<201> A_LWL<200> A_LWL<199> A_LWL<198> A_LWL<197> A_LWL<196> A_LWL<195> A_LWL<194> A_LWL<193> A_LWL<192> A_RWL<207> A_RWL<206> A_RWL<205> A_RWL<204> A_RWL<203> A_RWL<202> A_RWL<201> A_RWL<200> A_RWL<199> A_RWL<198> A_RWL<197> A_RWL<196> A_RWL<195> A_RWL<194> A_RWL<193> A_RWL<192> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM
+XRAM<12> A_BLC<21> A_BLC<20> A_BLC<23> A_BLC<22> A_BLT<21> A_BLT<20> A_BLT<23> A_BLT<22> A_LWL<191> A_LWL<190> A_LWL<189> A_LWL<188> A_LWL<187> A_LWL<186> A_LWL<185> A_LWL<184> A_LWL<183> A_LWL<182> A_LWL<181> A_LWL<180> A_LWL<179> A_LWL<178> A_LWL<177> A_LWL<176> A_RWL<191> A_RWL<190> A_RWL<189> A_RWL<188> A_RWL<187> A_RWL<186> A_RWL<185> A_RWL<184> A_RWL<183> A_RWL<182> A_RWL<181> A_RWL<180> A_RWL<179> A_RWL<178> A_RWL<177> A_RWL<176> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM
+XRAM<11> A_BLC<19> A_BLC<18> A_BLC<21> A_BLC<20> A_BLT<19> A_BLT<18> A_BLT<21> A_BLT<20> A_LWL<175> A_LWL<174> A_LWL<173> A_LWL<172> A_LWL<171> A_LWL<170> A_LWL<169> A_LWL<168> A_LWL<167> A_LWL<166> A_LWL<165> A_LWL<164> A_LWL<163> A_LWL<162> A_LWL<161> A_LWL<160> A_RWL<175> A_RWL<174> A_RWL<173> A_RWL<172> A_RWL<171> A_RWL<170> A_RWL<169> A_RWL<168> A_RWL<167> A_RWL<166> A_RWL<165> A_RWL<164> A_RWL<163> A_RWL<162> A_RWL<161> A_RWL<160> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM
+XRAM<10> A_BLC<17> A_BLC<16> A_BLC<19> A_BLC<18> A_BLT<17> A_BLT<16> A_BLT<19> A_BLT<18> A_LWL<159> A_LWL<158> A_LWL<157> A_LWL<156> A_LWL<155> A_LWL<154> A_LWL<153> A_LWL<152> A_LWL<151> A_LWL<150> A_LWL<149> A_LWL<148> A_LWL<147> A_LWL<146> A_LWL<145> A_LWL<144> A_RWL<159> A_RWL<158> A_RWL<157> A_RWL<156> A_RWL<155> A_RWL<154> A_RWL<153> A_RWL<152> A_RWL<151> A_RWL<150> A_RWL<149> A_RWL<148> A_RWL<147> A_RWL<146> A_RWL<145> A_RWL<144> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM
+XRAM<9> A_BLC<15> A_BLC<14> A_BLC<17> A_BLC<16> A_BLT<15> A_BLT<14> A_BLT<17> A_BLT<16> A_LWL<143> A_LWL<142> A_LWL<141> A_LWL<140> A_LWL<139> A_LWL<138> A_LWL<137> A_LWL<136> A_LWL<135> A_LWL<134> A_LWL<133> A_LWL<132> A_LWL<131> A_LWL<130> A_LWL<129> A_LWL<128> A_RWL<143> A_RWL<142> A_RWL<141> A_RWL<140> A_RWL<139> A_RWL<138> A_RWL<137> A_RWL<136> A_RWL<135> A_RWL<134> A_RWL<133> A_RWL<132> A_RWL<131> A_RWL<130> A_RWL<129> A_RWL<128> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM
+XRAM<8> A_BLC<13> A_BLC<12> A_BLC<15> A_BLC<14> A_BLT<13> A_BLT<12> A_BLT<15> A_BLT<14> A_LWL<127> A_LWL<126> A_LWL<125> A_LWL<124> A_LWL<123> A_LWL<122> A_LWL<121> A_LWL<120> A_LWL<119> A_LWL<118> A_LWL<117> A_LWL<116> A_LWL<115> A_LWL<114> A_LWL<113> A_LWL<112> A_RWL<127> A_RWL<126> A_RWL<125> A_RWL<124> A_RWL<123> A_RWL<122> A_RWL<121> A_RWL<120> A_RWL<119> A_RWL<118> A_RWL<117> A_RWL<116> A_RWL<115> A_RWL<114> A_RWL<113> A_RWL<112> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM
+XRAM<7> A_BLC<11> A_BLC<10> A_BLC<13> A_BLC<12> A_BLT<11> A_BLT<10> A_BLT<13> A_BLT<12> A_LWL<111> A_LWL<110> A_LWL<109> A_LWL<108> A_LWL<107> A_LWL<106> A_LWL<105> A_LWL<104> A_LWL<103> A_LWL<102> A_LWL<101> A_LWL<100> A_LWL<99> A_LWL<98> A_LWL<97> A_LWL<96> A_RWL<111> A_RWL<110> A_RWL<109> A_RWL<108> A_RWL<107> A_RWL<106> A_RWL<105> A_RWL<104> A_RWL<103> A_RWL<102> A_RWL<101> A_RWL<100> A_RWL<99> A_RWL<98> A_RWL<97> A_RWL<96> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM
+XRAM<6> A_BLC<9> A_BLC<8> A_BLC<11> A_BLC<10> A_BLT<9> A_BLT<8> A_BLT<11> A_BLT<10> A_LWL<95> A_LWL<94> A_LWL<93> A_LWL<92> A_LWL<91> A_LWL<90> A_LWL<89> A_LWL<88> A_LWL<87> A_LWL<86> A_LWL<85> A_LWL<84> A_LWL<83> A_LWL<82> A_LWL<81> A_LWL<80> A_RWL<95> A_RWL<94> A_RWL<93> A_RWL<92> A_RWL<91> A_RWL<90> A_RWL<89> A_RWL<88> A_RWL<87> A_RWL<86> A_RWL<85> A_RWL<84> A_RWL<83> A_RWL<82> A_RWL<81> A_RWL<80> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM
+XRAM<5> A_BLC<7> A_BLC<6> A_BLC<9> A_BLC<8> A_BLT<7> A_BLT<6> A_BLT<9> A_BLT<8> A_LWL<79> A_LWL<78> A_LWL<77> A_LWL<76> A_LWL<75> A_LWL<74> A_LWL<73> A_LWL<72> A_LWL<71> A_LWL<70> A_LWL<69> A_LWL<68> A_LWL<67> A_LWL<66> A_LWL<65> A_LWL<64> A_RWL<79> A_RWL<78> A_RWL<77> A_RWL<76> A_RWL<75> A_RWL<74> A_RWL<73> A_RWL<72> A_RWL<71> A_RWL<70> A_RWL<69> A_RWL<68> A_RWL<67> A_RWL<66> A_RWL<65> A_RWL<64> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM
+XRAM<4> A_BLC<5> A_BLC<4> A_BLC<7> A_BLC<6> A_BLT<5> A_BLT<4> A_BLT<7> A_BLT<6> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM
+XRAM<3> A_BLC<3> A_BLC<2> A_BLC<5> A_BLC<4> A_BLT<3> A_BLT<2> A_BLT<5> A_BLT<4> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM
+XRAM<2> A_BLC<1> A_BLC<0> A_BLC<3> A_BLC<2> A_BLT<1> A_BLT<0> A_BLT<3> A_BLT<2> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM
+XRAM<1> A_BLC_BOT<1> A_BLC_BOT<0> A_BLC<1> A_BLC<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT<1> A_BLT<0> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_SRAM
+XEDGE<1> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_TOP<1> A_BLT_TOP<0> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_TB
+XEDGE<0> A_BLC_BOT<1> A_BLC_BOT<0> A_BLT_BOT<1> A_BLT_BOT<0> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_TB
+.ENDS
+
+
+
+
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_MATRIX_pcell_1 A_BLC<63> A_BLC<62> A_BLC<61> A_BLC<60> A_BLC<59> A_BLC<58> A_BLC<57> A_BLC<56> A_BLC<55> A_BLC<54> A_BLC<53> A_BLC<52> A_BLC<51> A_BLC<50> A_BLC<49> A_BLC<48> A_BLC<47> A_BLC<46> A_BLC<45> A_BLC<44> A_BLC<43> A_BLC<42> A_BLC<41> A_BLC<40> A_BLC<39> A_BLC<38> A_BLC<37> A_BLC<36> A_BLC<35> A_BLC<34> A_BLC<33> A_BLC<32> A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<63> A_BLT<62> A_BLT<61> A_BLT<60> A_BLT<59> A_BLT<58> A_BLT<57> A_BLT<56> A_BLT<55> A_BLT<54> A_BLT<53> A_BLT<52> A_BLT<51> A_BLT<50> A_BLT<49> A_BLT<48> A_BLT<47> A_BLT<46> A_BLT<45> A_BLT<44> A_BLT<43> A_BLT<42> A_BLT<41> A_BLT<40> A_BLT<39> A_BLT<38> A_BLT<37> A_BLT<36> A_BLT<35> A_BLT<34> A_BLT<33> A_BLT<32> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_WL<511> A_WL<510> A_WL<509> A_WL<508> A_WL<507> A_WL<506> A_WL<505> A_WL<504> A_WL<503> A_WL<502> A_WL<501> A_WL<500> A_WL<499> A_WL<498> A_WL<497> A_WL<496> A_WL<495> A_WL<494> A_WL<493> A_WL<492> A_WL<491> A_WL<490> A_WL<489> A_WL<488> A_WL<487> A_WL<486> A_WL<485> A_WL<484> A_WL<483> A_WL<482> A_WL<481> A_WL<480> A_WL<479> A_WL<478> A_WL<477> A_WL<476> A_WL<475> A_WL<474> A_WL<473> A_WL<472> A_WL<471> A_WL<470> A_WL<469> A_WL<468> A_WL<467> A_WL<466> A_WL<465> A_WL<464> A_WL<463> A_WL<462> A_WL<461> A_WL<460> A_WL<459> A_WL<458> A_WL<457> A_WL<456> A_WL<455> A_WL<454> A_WL<453> A_WL<452> A_WL<451> A_WL<450> A_WL<449> A_WL<448> A_WL<447> A_WL<446> A_WL<445> A_WL<444> A_WL<443> A_WL<442> A_WL<441> A_WL<440> A_WL<439> A_WL<438> A_WL<437> A_WL<436> A_WL<435> A_WL<434> A_WL<433> A_WL<432> A_WL<431> A_WL<430> A_WL<429> A_WL<428> A_WL<427> A_WL<426> A_WL<425> A_WL<424> A_WL<423> A_WL<422> A_WL<421> A_WL<420> A_WL<419> A_WL<418> A_WL<417> A_WL<416> A_WL<415> A_WL<414> A_WL<413> A_WL<412> A_WL<411> A_WL<410> A_WL<409> A_WL<408> A_WL<407> A_WL<406> A_WL<405> A_WL<404> A_WL<403> A_WL<402> A_WL<401> A_WL<400> A_WL<399> A_WL<398> A_WL<397> A_WL<396> A_WL<395> A_WL<394> A_WL<393> A_WL<392> A_WL<391> A_WL<390> A_WL<389> A_WL<388> A_WL<387> A_WL<386> A_WL<385> A_WL<384> A_WL<383> A_WL<382> A_WL<381> A_WL<380> A_WL<379> A_WL<378> A_WL<377> A_WL<376> A_WL<375> A_WL<374> A_WL<373> A_WL<372> A_WL<371> A_WL<370> A_WL<369> A_WL<368> A_WL<367> A_WL<366> A_WL<365> A_WL<364> A_WL<363> A_WL<362> A_WL<361> A_WL<360> A_WL<359> A_WL<358> A_WL<357> A_WL<356> A_WL<355> A_WL<354> A_WL<353> A_WL<352> A_WL<351> A_WL<350> A_WL<349> A_WL<348> A_WL<347> A_WL<346> A_WL<345> A_WL<344> A_WL<343> A_WL<342> A_WL<341> A_WL<340> A_WL<339> A_WL<338> A_WL<337> A_WL<336> A_WL<335> A_WL<334> A_WL<333> A_WL<332> A_WL<331> A_WL<330> A_WL<329> A_WL<328> A_WL<327> A_WL<326> A_WL<325> A_WL<324> A_WL<323> A_WL<322> A_WL<321> A_WL<320> A_WL<319> A_WL<318> A_WL<317> A_WL<316> A_WL<315> A_WL<314> A_WL<313> A_WL<312> A_WL<311> A_WL<310> A_WL<309> A_WL<308> A_WL<307> A_WL<306> A_WL<305> A_WL<304> A_WL<303> A_WL<302> A_WL<301> A_WL<300> A_WL<299> A_WL<298> A_WL<297> A_WL<296> A_WL<295> A_WL<294> A_WL<293> A_WL<292> A_WL<291> A_WL<290> A_WL<289> A_WL<288> A_WL<287> A_WL<286> A_WL<285> A_WL<284> A_WL<283> A_WL<282> A_WL<281> A_WL<280> A_WL<279> A_WL<278> A_WL<277> A_WL<276> A_WL<275> A_WL<274> A_WL<273> A_WL<272> A_WL<271> A_WL<270> A_WL<269> A_WL<268> A_WL<267> A_WL<266> A_WL<265> A_WL<264> A_WL<263> A_WL<262> A_WL<261> A_WL<260> A_WL<259> A_WL<258> A_WL<257> A_WL<256> A_WL<255> A_WL<254> A_WL<253> A_WL<252> A_WL<251> A_WL<250> A_WL<249> A_WL<248> A_WL<247> A_WL<246> A_WL<245> A_WL<244> A_WL<243> A_WL<242> A_WL<241> A_WL<240> A_WL<239> A_WL<238> A_WL<237> A_WL<236> A_WL<235> A_WL<234> A_WL<233> A_WL<232> A_WL<231> A_WL<230> A_WL<229> A_WL<228> A_WL<227> A_WL<226> A_WL<225> A_WL<224> A_WL<223> A_WL<222> A_WL<221> A_WL<220> A_WL<219> A_WL<218> A_WL<217> A_WL<216> A_WL<215> A_WL<214> A_WL<213> A_WL<212> A_WL<211> A_WL<210> A_WL<209> A_WL<208> A_WL<207> A_WL<206> A_WL<205> A_WL<204> A_WL<203> A_WL<202> A_WL<201> A_WL<200> A_WL<199> A_WL<198> A_WL<197> A_WL<196> A_WL<195> A_WL<194> A_WL<193> A_WL<192> A_WL<191> A_WL<190> A_WL<189> A_WL<188> A_WL<187> A_WL<186> A_WL<185> A_WL<184> A_WL<183> A_WL<182> A_WL<181> A_WL<180> A_WL<179> A_WL<178> A_WL<177> A_WL<176> A_WL<175> A_WL<174> A_WL<173> A_WL<172> A_WL<171> A_WL<170> A_WL<169> A_WL<168> A_WL<167> A_WL<166> A_WL<165> A_WL<164> A_WL<163> A_WL<162> A_WL<161> A_WL<160> A_WL<159> A_WL<158> A_WL<157> A_WL<156> A_WL<155> A_WL<154> A_WL<153> A_WL<152> A_WL<151> A_WL<150> A_WL<149> A_WL<148> A_WL<147> A_WL<146> A_WL<145> A_WL<144> A_WL<143> A_WL<142> A_WL<141> A_WL<140> A_WL<139> A_WL<138> A_WL<137> A_WL<136> A_WL<135> A_WL<134> A_WL<133> A_WL<132> A_WL<131> A_WL<130> A_WL<129> A_WL<128> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS
+XCORNER<3> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_CORNER
+XCORNER<2> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_CORNER
+XCORNER<1> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_CORNER
+XCORNER<0> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_CORNER
+XRAMEDGE_L<31> A_WL<511> A_WL<510> A_WL<509> A_WL<508> A_WL<507> A_WL<506> A_WL<505> A_WL<504> A_WL<503> A_WL<502> A_WL<501> A_WL<500> A_WL<499> A_WL<498> A_WL<497> A_WL<496> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<30> A_WL<495> A_WL<494> A_WL<493> A_WL<492> A_WL<491> A_WL<490> A_WL<489> A_WL<488> A_WL<487> A_WL<486> A_WL<485> A_WL<484> A_WL<483> A_WL<482> A_WL<481> A_WL<480> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<29> A_WL<479> A_WL<478> A_WL<477> A_WL<476> A_WL<475> A_WL<474> A_WL<473> A_WL<472> A_WL<471> A_WL<470> A_WL<469> A_WL<468> A_WL<467> A_WL<466> A_WL<465> A_WL<464> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<28> A_WL<463> A_WL<462> A_WL<461> A_WL<460> A_WL<459> A_WL<458> A_WL<457> A_WL<456> A_WL<455> A_WL<454> A_WL<453> A_WL<452> A_WL<451> A_WL<450> A_WL<449> A_WL<448> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<27> A_WL<447> A_WL<446> A_WL<445> A_WL<444> A_WL<443> A_WL<442> A_WL<441> A_WL<440> A_WL<439> A_WL<438> A_WL<437> A_WL<436> A_WL<435> A_WL<434> A_WL<433> A_WL<432> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<26> A_WL<431> A_WL<430> A_WL<429> A_WL<428> A_WL<427> A_WL<426> A_WL<425> A_WL<424> A_WL<423> A_WL<422> A_WL<421> A_WL<420> A_WL<419> A_WL<418> A_WL<417> A_WL<416> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<25> A_WL<415> A_WL<414> A_WL<413> A_WL<412> A_WL<411> A_WL<410> A_WL<409> A_WL<408> A_WL<407> A_WL<406> A_WL<405> A_WL<404> A_WL<403> A_WL<402> A_WL<401> A_WL<400> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<24> A_WL<399> A_WL<398> A_WL<397> A_WL<396> A_WL<395> A_WL<394> A_WL<393> A_WL<392> A_WL<391> A_WL<390> A_WL<389> A_WL<388> A_WL<387> A_WL<386> A_WL<385> A_WL<384> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<23> A_WL<383> A_WL<382> A_WL<381> A_WL<380> A_WL<379> A_WL<378> A_WL<377> A_WL<376> A_WL<375> A_WL<374> A_WL<373> A_WL<372> A_WL<371> A_WL<370> A_WL<369> A_WL<368> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<22> A_WL<367> A_WL<366> A_WL<365> A_WL<364> A_WL<363> A_WL<362> A_WL<361> A_WL<360> A_WL<359> A_WL<358> A_WL<357> A_WL<356> A_WL<355> A_WL<354> A_WL<353> A_WL<352> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<21> A_WL<351> A_WL<350> A_WL<349> A_WL<348> A_WL<347> A_WL<346> A_WL<345> A_WL<344> A_WL<343> A_WL<342> A_WL<341> A_WL<340> A_WL<339> A_WL<338> A_WL<337> A_WL<336> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<20> A_WL<335> A_WL<334> A_WL<333> A_WL<332> A_WL<331> A_WL<330> A_WL<329> A_WL<328> A_WL<327> A_WL<326> A_WL<325> A_WL<324> A_WL<323> A_WL<322> A_WL<321> A_WL<320> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<19> A_WL<319> A_WL<318> A_WL<317> A_WL<316> A_WL<315> A_WL<314> A_WL<313> A_WL<312> A_WL<311> A_WL<310> A_WL<309> A_WL<308> A_WL<307> A_WL<306> A_WL<305> A_WL<304> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<18> A_WL<303> A_WL<302> A_WL<301> A_WL<300> A_WL<299> A_WL<298> A_WL<297> A_WL<296> A_WL<295> A_WL<294> A_WL<293> A_WL<292> A_WL<291> A_WL<290> A_WL<289> A_WL<288> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<17> A_WL<287> A_WL<286> A_WL<285> A_WL<284> A_WL<283> A_WL<282> A_WL<281> A_WL<280> A_WL<279> A_WL<278> A_WL<277> A_WL<276> A_WL<275> A_WL<274> A_WL<273> A_WL<272> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<16> A_WL<271> A_WL<270> A_WL<269> A_WL<268> A_WL<267> A_WL<266> A_WL<265> A_WL<264> A_WL<263> A_WL<262> A_WL<261> A_WL<260> A_WL<259> A_WL<258> A_WL<257> A_WL<256> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<15> A_WL<255> A_WL<254> A_WL<253> A_WL<252> A_WL<251> A_WL<250> A_WL<249> A_WL<248> A_WL<247> A_WL<246> A_WL<245> A_WL<244> A_WL<243> A_WL<242> A_WL<241> A_WL<240> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<14> A_WL<239> A_WL<238> A_WL<237> A_WL<236> A_WL<235> A_WL<234> A_WL<233> A_WL<232> A_WL<231> A_WL<230> A_WL<229> A_WL<228> A_WL<227> A_WL<226> A_WL<225> A_WL<224> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<13> A_WL<223> A_WL<222> A_WL<221> A_WL<220> A_WL<219> A_WL<218> A_WL<217> A_WL<216> A_WL<215> A_WL<214> A_WL<213> A_WL<212> A_WL<211> A_WL<210> A_WL<209> A_WL<208> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<12> A_WL<207> A_WL<206> A_WL<205> A_WL<204> A_WL<203> A_WL<202> A_WL<201> A_WL<200> A_WL<199> A_WL<198> A_WL<197> A_WL<196> A_WL<195> A_WL<194> A_WL<193> A_WL<192> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<11> A_WL<191> A_WL<190> A_WL<189> A_WL<188> A_WL<187> A_WL<186> A_WL<185> A_WL<184> A_WL<183> A_WL<182> A_WL<181> A_WL<180> A_WL<179> A_WL<178> A_WL<177> A_WL<176> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<10> A_WL<175> A_WL<174> A_WL<173> A_WL<172> A_WL<171> A_WL<170> A_WL<169> A_WL<168> A_WL<167> A_WL<166> A_WL<165> A_WL<164> A_WL<163> A_WL<162> A_WL<161> A_WL<160> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<9> A_WL<159> A_WL<158> A_WL<157> A_WL<156> A_WL<155> A_WL<154> A_WL<153> A_WL<152> A_WL<151> A_WL<150> A_WL<149> A_WL<148> A_WL<147> A_WL<146> A_WL<145> A_WL<144> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<8> A_WL<143> A_WL<142> A_WL<141> A_WL<140> A_WL<139> A_WL<138> A_WL<137> A_WL<136> A_WL<135> A_WL<134> A_WL<133> A_WL<132> A_WL<131> A_WL<130> A_WL<129> A_WL<128> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<7> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<6> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<5> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<4> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<3> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<2> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<1> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<0> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<31> A_IWL<16383> A_IWL<16382> A_IWL<16381> A_IWL<16380> A_IWL<16379> A_IWL<16378> A_IWL<16377> A_IWL<16376> A_IWL<16375> A_IWL<16374> A_IWL<16373> A_IWL<16372> A_IWL<16371> A_IWL<16370> A_IWL<16369> A_IWL<16368> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<30> A_IWL<16367> A_IWL<16366> A_IWL<16365> A_IWL<16364> A_IWL<16363> A_IWL<16362> A_IWL<16361> A_IWL<16360> A_IWL<16359> A_IWL<16358> A_IWL<16357> A_IWL<16356> A_IWL<16355> A_IWL<16354> A_IWL<16353> A_IWL<16352> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<29> A_IWL<16351> A_IWL<16350> A_IWL<16349> A_IWL<16348> A_IWL<16347> A_IWL<16346> A_IWL<16345> A_IWL<16344> A_IWL<16343> A_IWL<16342> A_IWL<16341> A_IWL<16340> A_IWL<16339> A_IWL<16338> A_IWL<16337> A_IWL<16336> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<28> A_IWL<16335> A_IWL<16334> A_IWL<16333> A_IWL<16332> A_IWL<16331> A_IWL<16330> A_IWL<16329> A_IWL<16328> A_IWL<16327> A_IWL<16326> A_IWL<16325> A_IWL<16324> A_IWL<16323> A_IWL<16322> A_IWL<16321> A_IWL<16320> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<27> A_IWL<16319> A_IWL<16318> A_IWL<16317> A_IWL<16316> A_IWL<16315> A_IWL<16314> A_IWL<16313> A_IWL<16312> A_IWL<16311> A_IWL<16310> A_IWL<16309> A_IWL<16308> A_IWL<16307> A_IWL<16306> A_IWL<16305> A_IWL<16304> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<26> A_IWL<16303> A_IWL<16302> A_IWL<16301> A_IWL<16300> A_IWL<16299> A_IWL<16298> A_IWL<16297> A_IWL<16296> A_IWL<16295> A_IWL<16294> A_IWL<16293> A_IWL<16292> A_IWL<16291> A_IWL<16290> A_IWL<16289> A_IWL<16288> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<25> A_IWL<16287> A_IWL<16286> A_IWL<16285> A_IWL<16284> A_IWL<16283> A_IWL<16282> A_IWL<16281> A_IWL<16280> A_IWL<16279> A_IWL<16278> A_IWL<16277> A_IWL<16276> A_IWL<16275> A_IWL<16274> A_IWL<16273> A_IWL<16272> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<24> A_IWL<16271> A_IWL<16270> A_IWL<16269> A_IWL<16268> A_IWL<16267> A_IWL<16266> A_IWL<16265> A_IWL<16264> A_IWL<16263> A_IWL<16262> A_IWL<16261> A_IWL<16260> A_IWL<16259> A_IWL<16258> A_IWL<16257> A_IWL<16256> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<23> A_IWL<16255> A_IWL<16254> A_IWL<16253> A_IWL<16252> A_IWL<16251> A_IWL<16250> A_IWL<16249> A_IWL<16248> A_IWL<16247> A_IWL<16246> A_IWL<16245> A_IWL<16244> A_IWL<16243> A_IWL<16242> A_IWL<16241> A_IWL<16240> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<22> A_IWL<16239> A_IWL<16238> A_IWL<16237> A_IWL<16236> A_IWL<16235> A_IWL<16234> A_IWL<16233> A_IWL<16232> A_IWL<16231> A_IWL<16230> A_IWL<16229> A_IWL<16228> A_IWL<16227> A_IWL<16226> A_IWL<16225> A_IWL<16224> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<21> A_IWL<16223> A_IWL<16222> A_IWL<16221> A_IWL<16220> A_IWL<16219> A_IWL<16218> A_IWL<16217> A_IWL<16216> A_IWL<16215> A_IWL<16214> A_IWL<16213> A_IWL<16212> A_IWL<16211> A_IWL<16210> A_IWL<16209> A_IWL<16208> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<20> A_IWL<16207> A_IWL<16206> A_IWL<16205> A_IWL<16204> A_IWL<16203> A_IWL<16202> A_IWL<16201> A_IWL<16200> A_IWL<16199> A_IWL<16198> A_IWL<16197> A_IWL<16196> A_IWL<16195> A_IWL<16194> A_IWL<16193> A_IWL<16192> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<19> A_IWL<16191> A_IWL<16190> A_IWL<16189> A_IWL<16188> A_IWL<16187> A_IWL<16186> A_IWL<16185> A_IWL<16184> A_IWL<16183> A_IWL<16182> A_IWL<16181> A_IWL<16180> A_IWL<16179> A_IWL<16178> A_IWL<16177> A_IWL<16176> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<18> A_IWL<16175> A_IWL<16174> A_IWL<16173> A_IWL<16172> A_IWL<16171> A_IWL<16170> A_IWL<16169> A_IWL<16168> A_IWL<16167> A_IWL<16166> A_IWL<16165> A_IWL<16164> A_IWL<16163> A_IWL<16162> A_IWL<16161> A_IWL<16160> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<17> A_IWL<16159> A_IWL<16158> A_IWL<16157> A_IWL<16156> A_IWL<16155> A_IWL<16154> A_IWL<16153> A_IWL<16152> A_IWL<16151> A_IWL<16150> A_IWL<16149> A_IWL<16148> A_IWL<16147> A_IWL<16146> A_IWL<16145> A_IWL<16144> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<16> A_IWL<16143> A_IWL<16142> A_IWL<16141> A_IWL<16140> A_IWL<16139> A_IWL<16138> A_IWL<16137> A_IWL<16136> A_IWL<16135> A_IWL<16134> A_IWL<16133> A_IWL<16132> A_IWL<16131> A_IWL<16130> A_IWL<16129> A_IWL<16128> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<15> A_IWL<16127> A_IWL<16126> A_IWL<16125> A_IWL<16124> A_IWL<16123> A_IWL<16122> A_IWL<16121> A_IWL<16120> A_IWL<16119> A_IWL<16118> A_IWL<16117> A_IWL<16116> A_IWL<16115> A_IWL<16114> A_IWL<16113> A_IWL<16112> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<14> A_IWL<16111> A_IWL<16110> A_IWL<16109> A_IWL<16108> A_IWL<16107> A_IWL<16106> A_IWL<16105> A_IWL<16104> A_IWL<16103> A_IWL<16102> A_IWL<16101> A_IWL<16100> A_IWL<16099> A_IWL<16098> A_IWL<16097> A_IWL<16096> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<13> A_IWL<16095> A_IWL<16094> A_IWL<16093> A_IWL<16092> A_IWL<16091> A_IWL<16090> A_IWL<16089> A_IWL<16088> A_IWL<16087> A_IWL<16086> A_IWL<16085> A_IWL<16084> A_IWL<16083> A_IWL<16082> A_IWL<16081> A_IWL<16080> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<12> A_IWL<16079> A_IWL<16078> A_IWL<16077> A_IWL<16076> A_IWL<16075> A_IWL<16074> A_IWL<16073> A_IWL<16072> A_IWL<16071> A_IWL<16070> A_IWL<16069> A_IWL<16068> A_IWL<16067> A_IWL<16066> A_IWL<16065> A_IWL<16064> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<11> A_IWL<16063> A_IWL<16062> A_IWL<16061> A_IWL<16060> A_IWL<16059> A_IWL<16058> A_IWL<16057> A_IWL<16056> A_IWL<16055> A_IWL<16054> A_IWL<16053> A_IWL<16052> A_IWL<16051> A_IWL<16050> A_IWL<16049> A_IWL<16048> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<10> A_IWL<16047> A_IWL<16046> A_IWL<16045> A_IWL<16044> A_IWL<16043> A_IWL<16042> A_IWL<16041> A_IWL<16040> A_IWL<16039> A_IWL<16038> A_IWL<16037> A_IWL<16036> A_IWL<16035> A_IWL<16034> A_IWL<16033> A_IWL<16032> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<9> A_IWL<16031> A_IWL<16030> A_IWL<16029> A_IWL<16028> A_IWL<16027> A_IWL<16026> A_IWL<16025> A_IWL<16024> A_IWL<16023> A_IWL<16022> A_IWL<16021> A_IWL<16020> A_IWL<16019> A_IWL<16018> A_IWL<16017> A_IWL<16016> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<8> A_IWL<16015> A_IWL<16014> A_IWL<16013> A_IWL<16012> A_IWL<16011> A_IWL<16010> A_IWL<16009> A_IWL<16008> A_IWL<16007> A_IWL<16006> A_IWL<16005> A_IWL<16004> A_IWL<16003> A_IWL<16002> A_IWL<16001> A_IWL<16000> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<7> A_IWL<15999> A_IWL<15998> A_IWL<15997> A_IWL<15996> A_IWL<15995> A_IWL<15994> A_IWL<15993> A_IWL<15992> A_IWL<15991> A_IWL<15990> A_IWL<15989> A_IWL<15988> A_IWL<15987> A_IWL<15986> A_IWL<15985> A_IWL<15984> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<6> A_IWL<15983> A_IWL<15982> A_IWL<15981> A_IWL<15980> A_IWL<15979> A_IWL<15978> A_IWL<15977> A_IWL<15976> A_IWL<15975> A_IWL<15974> A_IWL<15973> A_IWL<15972> A_IWL<15971> A_IWL<15970> A_IWL<15969> A_IWL<15968> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<5> A_IWL<15967> A_IWL<15966> A_IWL<15965> A_IWL<15964> A_IWL<15963> A_IWL<15962> A_IWL<15961> A_IWL<15960> A_IWL<15959> A_IWL<15958> A_IWL<15957> A_IWL<15956> A_IWL<15955> A_IWL<15954> A_IWL<15953> A_IWL<15952> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<4> A_IWL<15951> A_IWL<15950> A_IWL<15949> A_IWL<15948> A_IWL<15947> A_IWL<15946> A_IWL<15945> A_IWL<15944> A_IWL<15943> A_IWL<15942> A_IWL<15941> A_IWL<15940> A_IWL<15939> A_IWL<15938> A_IWL<15937> A_IWL<15936> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<3> A_IWL<15935> A_IWL<15934> A_IWL<15933> A_IWL<15932> A_IWL<15931> A_IWL<15930> A_IWL<15929> A_IWL<15928> A_IWL<15927> A_IWL<15926> A_IWL<15925> A_IWL<15924> A_IWL<15923> A_IWL<15922> A_IWL<15921> A_IWL<15920> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<2> A_IWL<15919> A_IWL<15918> A_IWL<15917> A_IWL<15916> A_IWL<15915> A_IWL<15914> A_IWL<15913> A_IWL<15912> A_IWL<15911> A_IWL<15910> A_IWL<15909> A_IWL<15908> A_IWL<15907> A_IWL<15906> A_IWL<15905> A_IWL<15904> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<1> A_IWL<15903> A_IWL<15902> A_IWL<15901> A_IWL<15900> A_IWL<15899> A_IWL<15898> A_IWL<15897> A_IWL<15896> A_IWL<15895> A_IWL<15894> A_IWL<15893> A_IWL<15892> A_IWL<15891> A_IWL<15890> A_IWL<15889> A_IWL<15888> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<0> A_IWL<15887> A_IWL<15886> A_IWL<15885> A_IWL<15884> A_IWL<15883> A_IWL<15882> A_IWL<15881> A_IWL<15880> A_IWL<15879> A_IWL<15878> A_IWL<15877> A_IWL<15876> A_IWL<15875> A_IWL<15874> A_IWL<15873> A_IWL<15872> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_BITKIT_16x2_EDGE_LR
+XCOL<31> A_BLC<63> A_BLC<62> A_BLC_TOP<63> A_BLC_TOP<62> A_BLT<63> A_BLT<62> A_BLT_TOP<63> A_BLT_TOP<62> A_IWL<15871> A_IWL<15870> A_IWL<15869> A_IWL<15868> A_IWL<15867> A_IWL<15866> A_IWL<15865> A_IWL<15864> A_IWL<15863> A_IWL<15862> A_IWL<15861> A_IWL<15860> A_IWL<15859> A_IWL<15858> A_IWL<15857> A_IWL<15856> A_IWL<15855> A_IWL<15854> A_IWL<15853> A_IWL<15852> A_IWL<15851> A_IWL<15850> A_IWL<15849> A_IWL<15848> A_IWL<15847> A_IWL<15846> A_IWL<15845> A_IWL<15844> A_IWL<15843> A_IWL<15842> A_IWL<15841> A_IWL<15840> A_IWL<15839> A_IWL<15838> A_IWL<15837> A_IWL<15836> A_IWL<15835> A_IWL<15834> A_IWL<15833> A_IWL<15832> A_IWL<15831> A_IWL<15830> A_IWL<15829> A_IWL<15828> A_IWL<15827> A_IWL<15826> A_IWL<15825> A_IWL<15824> A_IWL<15823> A_IWL<15822> A_IWL<15821> A_IWL<15820> A_IWL<15819> A_IWL<15818> A_IWL<15817> A_IWL<15816> A_IWL<15815> A_IWL<15814> A_IWL<15813> A_IWL<15812> A_IWL<15811> A_IWL<15810> A_IWL<15809> A_IWL<15808> A_IWL<15807> A_IWL<15806> A_IWL<15805> A_IWL<15804> A_IWL<15803> A_IWL<15802> A_IWL<15801> A_IWL<15800> A_IWL<15799> A_IWL<15798> A_IWL<15797> A_IWL<15796> A_IWL<15795> A_IWL<15794> A_IWL<15793> A_IWL<15792> A_IWL<15791> A_IWL<15790> A_IWL<15789> A_IWL<15788> A_IWL<15787> A_IWL<15786> A_IWL<15785> A_IWL<15784> A_IWL<15783> A_IWL<15782> A_IWL<15781> A_IWL<15780> A_IWL<15779> A_IWL<15778> A_IWL<15777> A_IWL<15776> A_IWL<15775> A_IWL<15774> A_IWL<15773> A_IWL<15772> A_IWL<15771> A_IWL<15770> A_IWL<15769> A_IWL<15768> A_IWL<15767> A_IWL<15766> A_IWL<15765> A_IWL<15764> A_IWL<15763> A_IWL<15762> A_IWL<15761> A_IWL<15760> A_IWL<15759> A_IWL<15758> A_IWL<15757> A_IWL<15756> A_IWL<15755> A_IWL<15754> A_IWL<15753> A_IWL<15752> A_IWL<15751> A_IWL<15750> A_IWL<15749> A_IWL<15748> A_IWL<15747> A_IWL<15746> A_IWL<15745> A_IWL<15744> A_IWL<15743> A_IWL<15742> A_IWL<15741> A_IWL<15740> A_IWL<15739> A_IWL<15738> A_IWL<15737> A_IWL<15736> A_IWL<15735> A_IWL<15734> A_IWL<15733> A_IWL<15732> A_IWL<15731> A_IWL<15730> A_IWL<15729> A_IWL<15728> A_IWL<15727> A_IWL<15726> A_IWL<15725> A_IWL<15724> A_IWL<15723> A_IWL<15722> A_IWL<15721> A_IWL<15720> A_IWL<15719> A_IWL<15718> A_IWL<15717> A_IWL<15716> A_IWL<15715> A_IWL<15714> A_IWL<15713> A_IWL<15712> A_IWL<15711> A_IWL<15710> A_IWL<15709> A_IWL<15708> A_IWL<15707> A_IWL<15706> A_IWL<15705> A_IWL<15704> A_IWL<15703> A_IWL<15702> A_IWL<15701> A_IWL<15700> A_IWL<15699> A_IWL<15698> A_IWL<15697> A_IWL<15696> A_IWL<15695> A_IWL<15694> A_IWL<15693> A_IWL<15692> A_IWL<15691> A_IWL<15690> A_IWL<15689> A_IWL<15688> A_IWL<15687> A_IWL<15686> A_IWL<15685> A_IWL<15684> A_IWL<15683> A_IWL<15682> A_IWL<15681> A_IWL<15680> A_IWL<15679> A_IWL<15678> A_IWL<15677> A_IWL<15676> A_IWL<15675> A_IWL<15674> A_IWL<15673> A_IWL<15672> A_IWL<15671> A_IWL<15670> A_IWL<15669> A_IWL<15668> A_IWL<15667> A_IWL<15666> A_IWL<15665> A_IWL<15664> A_IWL<15663> A_IWL<15662> A_IWL<15661> A_IWL<15660> A_IWL<15659> A_IWL<15658> A_IWL<15657> A_IWL<15656> A_IWL<15655> A_IWL<15654> A_IWL<15653> A_IWL<15652> A_IWL<15651> A_IWL<15650> A_IWL<15649> A_IWL<15648> A_IWL<15647> A_IWL<15646> A_IWL<15645> A_IWL<15644> A_IWL<15643> A_IWL<15642> A_IWL<15641> A_IWL<15640> A_IWL<15639> A_IWL<15638> A_IWL<15637> A_IWL<15636> A_IWL<15635> A_IWL<15634> A_IWL<15633> A_IWL<15632> A_IWL<15631> A_IWL<15630> A_IWL<15629> A_IWL<15628> A_IWL<15627> A_IWL<15626> A_IWL<15625> A_IWL<15624> A_IWL<15623> A_IWL<15622> A_IWL<15621> A_IWL<15620> A_IWL<15619> A_IWL<15618> A_IWL<15617> A_IWL<15616> A_IWL<15615> A_IWL<15614> A_IWL<15613> A_IWL<15612> A_IWL<15611> A_IWL<15610> A_IWL<15609> A_IWL<15608> A_IWL<15607> A_IWL<15606> A_IWL<15605> A_IWL<15604> A_IWL<15603> A_IWL<15602> A_IWL<15601> A_IWL<15600> A_IWL<15599> A_IWL<15598> A_IWL<15597> A_IWL<15596> A_IWL<15595> A_IWL<15594> A_IWL<15593> A_IWL<15592> A_IWL<15591> A_IWL<15590> A_IWL<15589> A_IWL<15588> A_IWL<15587> A_IWL<15586> A_IWL<15585> A_IWL<15584> A_IWL<15583> A_IWL<15582> A_IWL<15581> A_IWL<15580> A_IWL<15579> A_IWL<15578> A_IWL<15577> A_IWL<15576> A_IWL<15575> A_IWL<15574> A_IWL<15573> A_IWL<15572> A_IWL<15571> A_IWL<15570> A_IWL<15569> A_IWL<15568> A_IWL<15567> A_IWL<15566> A_IWL<15565> A_IWL<15564> A_IWL<15563> A_IWL<15562> A_IWL<15561> A_IWL<15560> A_IWL<15559> A_IWL<15558> A_IWL<15557> A_IWL<15556> A_IWL<15555> A_IWL<15554> A_IWL<15553> A_IWL<15552> A_IWL<15551> A_IWL<15550> A_IWL<15549> A_IWL<15548> A_IWL<15547> A_IWL<15546> A_IWL<15545> A_IWL<15544> A_IWL<15543> A_IWL<15542> A_IWL<15541> A_IWL<15540> A_IWL<15539> A_IWL<15538> A_IWL<15537> A_IWL<15536> A_IWL<15535> A_IWL<15534> A_IWL<15533> A_IWL<15532> A_IWL<15531> A_IWL<15530> A_IWL<15529> A_IWL<15528> A_IWL<15527> A_IWL<15526> A_IWL<15525> A_IWL<15524> A_IWL<15523> A_IWL<15522> A_IWL<15521> A_IWL<15520> A_IWL<15519> A_IWL<15518> A_IWL<15517> A_IWL<15516> A_IWL<15515> A_IWL<15514> A_IWL<15513> A_IWL<15512> A_IWL<15511> A_IWL<15510> A_IWL<15509> A_IWL<15508> A_IWL<15507> A_IWL<15506> A_IWL<15505> A_IWL<15504> A_IWL<15503> A_IWL<15502> A_IWL<15501> A_IWL<15500> A_IWL<15499> A_IWL<15498> A_IWL<15497> A_IWL<15496> A_IWL<15495> A_IWL<15494> A_IWL<15493> A_IWL<15492> A_IWL<15491> A_IWL<15490> A_IWL<15489> A_IWL<15488> A_IWL<15487> A_IWL<15486> A_IWL<15485> A_IWL<15484> A_IWL<15483> A_IWL<15482> A_IWL<15481> A_IWL<15480> A_IWL<15479> A_IWL<15478> A_IWL<15477> A_IWL<15476> A_IWL<15475> A_IWL<15474> A_IWL<15473> A_IWL<15472> A_IWL<15471> A_IWL<15470> A_IWL<15469> A_IWL<15468> A_IWL<15467> A_IWL<15466> A_IWL<15465> A_IWL<15464> A_IWL<15463> A_IWL<15462> A_IWL<15461> A_IWL<15460> A_IWL<15459> A_IWL<15458> A_IWL<15457> A_IWL<15456> A_IWL<15455> A_IWL<15454> A_IWL<15453> A_IWL<15452> A_IWL<15451> A_IWL<15450> A_IWL<15449> A_IWL<15448> A_IWL<15447> A_IWL<15446> A_IWL<15445> A_IWL<15444> A_IWL<15443> A_IWL<15442> A_IWL<15441> A_IWL<15440> A_IWL<15439> A_IWL<15438> A_IWL<15437> A_IWL<15436> A_IWL<15435> A_IWL<15434> A_IWL<15433> A_IWL<15432> A_IWL<15431> A_IWL<15430> A_IWL<15429> A_IWL<15428> A_IWL<15427> A_IWL<15426> A_IWL<15425> A_IWL<15424> A_IWL<15423> A_IWL<15422> A_IWL<15421> A_IWL<15420> A_IWL<15419> A_IWL<15418> A_IWL<15417> A_IWL<15416> A_IWL<15415> A_IWL<15414> A_IWL<15413> A_IWL<15412> A_IWL<15411> A_IWL<15410> A_IWL<15409> A_IWL<15408> A_IWL<15407> A_IWL<15406> A_IWL<15405> A_IWL<15404> A_IWL<15403> A_IWL<15402> A_IWL<15401> A_IWL<15400> A_IWL<15399> A_IWL<15398> A_IWL<15397> A_IWL<15396> A_IWL<15395> A_IWL<15394> A_IWL<15393> A_IWL<15392> A_IWL<15391> A_IWL<15390> A_IWL<15389> A_IWL<15388> A_IWL<15387> A_IWL<15386> A_IWL<15385> A_IWL<15384> A_IWL<15383> A_IWL<15382> A_IWL<15381> A_IWL<15380> A_IWL<15379> A_IWL<15378> A_IWL<15377> A_IWL<15376> A_IWL<15375> A_IWL<15374> A_IWL<15373> A_IWL<15372> A_IWL<15371> A_IWL<15370> A_IWL<15369> A_IWL<15368> A_IWL<15367> A_IWL<15366> A_IWL<15365> A_IWL<15364> A_IWL<15363> A_IWL<15362> A_IWL<15361> A_IWL<15360> A_IWL<16383> A_IWL<16382> A_IWL<16381> A_IWL<16380> A_IWL<16379> A_IWL<16378> A_IWL<16377> A_IWL<16376> A_IWL<16375> A_IWL<16374> A_IWL<16373> A_IWL<16372> A_IWL<16371> A_IWL<16370> A_IWL<16369> A_IWL<16368> A_IWL<16367> A_IWL<16366> A_IWL<16365> A_IWL<16364> A_IWL<16363> A_IWL<16362> A_IWL<16361> A_IWL<16360> A_IWL<16359> A_IWL<16358> A_IWL<16357> A_IWL<16356> A_IWL<16355> A_IWL<16354> A_IWL<16353> A_IWL<16352> A_IWL<16351> A_IWL<16350> A_IWL<16349> A_IWL<16348> A_IWL<16347> A_IWL<16346> A_IWL<16345> A_IWL<16344> A_IWL<16343> A_IWL<16342> A_IWL<16341> A_IWL<16340> A_IWL<16339> A_IWL<16338> A_IWL<16337> A_IWL<16336> A_IWL<16335> A_IWL<16334> A_IWL<16333> A_IWL<16332> A_IWL<16331> A_IWL<16330> A_IWL<16329> A_IWL<16328> A_IWL<16327> A_IWL<16326> A_IWL<16325> A_IWL<16324> A_IWL<16323> A_IWL<16322> A_IWL<16321> A_IWL<16320> A_IWL<16319> A_IWL<16318> A_IWL<16317> A_IWL<16316> A_IWL<16315> A_IWL<16314> A_IWL<16313> A_IWL<16312> A_IWL<16311> A_IWL<16310> A_IWL<16309> A_IWL<16308> A_IWL<16307> A_IWL<16306> A_IWL<16305> A_IWL<16304> A_IWL<16303> A_IWL<16302> A_IWL<16301> A_IWL<16300> A_IWL<16299> A_IWL<16298> A_IWL<16297> A_IWL<16296> A_IWL<16295> A_IWL<16294> A_IWL<16293> A_IWL<16292> A_IWL<16291> A_IWL<16290> A_IWL<16289> A_IWL<16288> A_IWL<16287> A_IWL<16286> A_IWL<16285> A_IWL<16284> A_IWL<16283> A_IWL<16282> A_IWL<16281> A_IWL<16280> A_IWL<16279> A_IWL<16278> A_IWL<16277> A_IWL<16276> A_IWL<16275> A_IWL<16274> A_IWL<16273> A_IWL<16272> A_IWL<16271> A_IWL<16270> A_IWL<16269> A_IWL<16268> A_IWL<16267> A_IWL<16266> A_IWL<16265> A_IWL<16264> A_IWL<16263> A_IWL<16262> A_IWL<16261> A_IWL<16260> A_IWL<16259> A_IWL<16258> A_IWL<16257> A_IWL<16256> A_IWL<16255> A_IWL<16254> A_IWL<16253> A_IWL<16252> A_IWL<16251> A_IWL<16250> A_IWL<16249> A_IWL<16248> A_IWL<16247> A_IWL<16246> A_IWL<16245> A_IWL<16244> A_IWL<16243> A_IWL<16242> A_IWL<16241> A_IWL<16240> A_IWL<16239> A_IWL<16238> A_IWL<16237> A_IWL<16236> A_IWL<16235> A_IWL<16234> A_IWL<16233> A_IWL<16232> A_IWL<16231> A_IWL<16230> A_IWL<16229> A_IWL<16228> A_IWL<16227> A_IWL<16226> A_IWL<16225> A_IWL<16224> A_IWL<16223> A_IWL<16222> A_IWL<16221> A_IWL<16220> A_IWL<16219> A_IWL<16218> A_IWL<16217> A_IWL<16216> A_IWL<16215> A_IWL<16214> A_IWL<16213> A_IWL<16212> A_IWL<16211> A_IWL<16210> A_IWL<16209> A_IWL<16208> A_IWL<16207> A_IWL<16206> A_IWL<16205> A_IWL<16204> A_IWL<16203> A_IWL<16202> A_IWL<16201> A_IWL<16200> A_IWL<16199> A_IWL<16198> A_IWL<16197> A_IWL<16196> A_IWL<16195> A_IWL<16194> A_IWL<16193> A_IWL<16192> A_IWL<16191> A_IWL<16190> A_IWL<16189> A_IWL<16188> A_IWL<16187> A_IWL<16186> A_IWL<16185> A_IWL<16184> A_IWL<16183> A_IWL<16182> A_IWL<16181> A_IWL<16180> A_IWL<16179> A_IWL<16178> A_IWL<16177> A_IWL<16176> A_IWL<16175> A_IWL<16174> A_IWL<16173> A_IWL<16172> A_IWL<16171> A_IWL<16170> A_IWL<16169> A_IWL<16168> A_IWL<16167> A_IWL<16166> A_IWL<16165> A_IWL<16164> A_IWL<16163> A_IWL<16162> A_IWL<16161> A_IWL<16160> A_IWL<16159> A_IWL<16158> A_IWL<16157> A_IWL<16156> A_IWL<16155> A_IWL<16154> A_IWL<16153> A_IWL<16152> A_IWL<16151> A_IWL<16150> A_IWL<16149> A_IWL<16148> A_IWL<16147> A_IWL<16146> A_IWL<16145> A_IWL<16144> A_IWL<16143> A_IWL<16142> A_IWL<16141> A_IWL<16140> A_IWL<16139> A_IWL<16138> A_IWL<16137> A_IWL<16136> A_IWL<16135> A_IWL<16134> A_IWL<16133> A_IWL<16132> A_IWL<16131> A_IWL<16130> A_IWL<16129> A_IWL<16128> A_IWL<16127> A_IWL<16126> A_IWL<16125> A_IWL<16124> A_IWL<16123> A_IWL<16122> A_IWL<16121> A_IWL<16120> A_IWL<16119> A_IWL<16118> A_IWL<16117> A_IWL<16116> A_IWL<16115> A_IWL<16114> A_IWL<16113> A_IWL<16112> A_IWL<16111> A_IWL<16110> A_IWL<16109> A_IWL<16108> A_IWL<16107> A_IWL<16106> A_IWL<16105> A_IWL<16104> A_IWL<16103> A_IWL<16102> A_IWL<16101> A_IWL<16100> A_IWL<16099> A_IWL<16098> A_IWL<16097> A_IWL<16096> A_IWL<16095> A_IWL<16094> A_IWL<16093> A_IWL<16092> A_IWL<16091> A_IWL<16090> A_IWL<16089> A_IWL<16088> A_IWL<16087> A_IWL<16086> A_IWL<16085> A_IWL<16084> A_IWL<16083> A_IWL<16082> A_IWL<16081> A_IWL<16080> A_IWL<16079> A_IWL<16078> A_IWL<16077> A_IWL<16076> A_IWL<16075> A_IWL<16074> A_IWL<16073> A_IWL<16072> A_IWL<16071> A_IWL<16070> A_IWL<16069> A_IWL<16068> A_IWL<16067> A_IWL<16066> A_IWL<16065> A_IWL<16064> A_IWL<16063> A_IWL<16062> A_IWL<16061> A_IWL<16060> A_IWL<16059> A_IWL<16058> A_IWL<16057> A_IWL<16056> A_IWL<16055> A_IWL<16054> A_IWL<16053> A_IWL<16052> A_IWL<16051> A_IWL<16050> A_IWL<16049> A_IWL<16048> A_IWL<16047> A_IWL<16046> A_IWL<16045> A_IWL<16044> A_IWL<16043> A_IWL<16042> A_IWL<16041> A_IWL<16040> A_IWL<16039> A_IWL<16038> A_IWL<16037> A_IWL<16036> A_IWL<16035> A_IWL<16034> A_IWL<16033> A_IWL<16032> A_IWL<16031> A_IWL<16030> A_IWL<16029> A_IWL<16028> A_IWL<16027> A_IWL<16026> A_IWL<16025> A_IWL<16024> A_IWL<16023> A_IWL<16022> A_IWL<16021> A_IWL<16020> A_IWL<16019> A_IWL<16018> A_IWL<16017> A_IWL<16016> A_IWL<16015> A_IWL<16014> A_IWL<16013> A_IWL<16012> A_IWL<16011> A_IWL<16010> A_IWL<16009> A_IWL<16008> A_IWL<16007> A_IWL<16006> A_IWL<16005> A_IWL<16004> A_IWL<16003> A_IWL<16002> A_IWL<16001> A_IWL<16000> A_IWL<15999> A_IWL<15998> A_IWL<15997> A_IWL<15996> A_IWL<15995> A_IWL<15994> A_IWL<15993> A_IWL<15992> A_IWL<15991> A_IWL<15990> A_IWL<15989> A_IWL<15988> A_IWL<15987> A_IWL<15986> A_IWL<15985> A_IWL<15984> A_IWL<15983> A_IWL<15982> A_IWL<15981> A_IWL<15980> A_IWL<15979> A_IWL<15978> A_IWL<15977> A_IWL<15976> A_IWL<15975> A_IWL<15974> A_IWL<15973> A_IWL<15972> A_IWL<15971> A_IWL<15970> A_IWL<15969> A_IWL<15968> A_IWL<15967> A_IWL<15966> A_IWL<15965> A_IWL<15964> A_IWL<15963> A_IWL<15962> A_IWL<15961> A_IWL<15960> A_IWL<15959> A_IWL<15958> A_IWL<15957> A_IWL<15956> A_IWL<15955> A_IWL<15954> A_IWL<15953> A_IWL<15952> A_IWL<15951> A_IWL<15950> A_IWL<15949> A_IWL<15948> A_IWL<15947> A_IWL<15946> A_IWL<15945> A_IWL<15944> A_IWL<15943> A_IWL<15942> A_IWL<15941> A_IWL<15940> A_IWL<15939> A_IWL<15938> A_IWL<15937> A_IWL<15936> A_IWL<15935> A_IWL<15934> A_IWL<15933> A_IWL<15932> A_IWL<15931> A_IWL<15930> A_IWL<15929> A_IWL<15928> A_IWL<15927> A_IWL<15926> A_IWL<15925> A_IWL<15924> A_IWL<15923> A_IWL<15922> A_IWL<15921> A_IWL<15920> A_IWL<15919> A_IWL<15918> A_IWL<15917> A_IWL<15916> A_IWL<15915> A_IWL<15914> A_IWL<15913> A_IWL<15912> A_IWL<15911> A_IWL<15910> A_IWL<15909> A_IWL<15908> A_IWL<15907> A_IWL<15906> A_IWL<15905> A_IWL<15904> A_IWL<15903> A_IWL<15902> A_IWL<15901> A_IWL<15900> A_IWL<15899> A_IWL<15898> A_IWL<15897> A_IWL<15896> A_IWL<15895> A_IWL<15894> A_IWL<15893> A_IWL<15892> A_IWL<15891> A_IWL<15890> A_IWL<15889> A_IWL<15888> A_IWL<15887> A_IWL<15886> A_IWL<15885> A_IWL<15884> A_IWL<15883> A_IWL<15882> A_IWL<15881> A_IWL<15880> A_IWL<15879> A_IWL<15878> A_IWL<15877> A_IWL<15876> A_IWL<15875> A_IWL<15874> A_IWL<15873> A_IWL<15872> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0
+XCOL<30> A_BLC<61> A_BLC<60> A_BLC_TOP<61> A_BLC_TOP<60> A_BLT<61> A_BLT<60> A_BLT_TOP<61> A_BLT_TOP<60> A_IWL<15359> A_IWL<15358> A_IWL<15357> A_IWL<15356> A_IWL<15355> A_IWL<15354> A_IWL<15353> A_IWL<15352> A_IWL<15351> A_IWL<15350> A_IWL<15349> A_IWL<15348> A_IWL<15347> A_IWL<15346> A_IWL<15345> A_IWL<15344> A_IWL<15343> A_IWL<15342> A_IWL<15341> A_IWL<15340> A_IWL<15339> A_IWL<15338> A_IWL<15337> A_IWL<15336> A_IWL<15335> A_IWL<15334> A_IWL<15333> A_IWL<15332> A_IWL<15331> A_IWL<15330> A_IWL<15329> A_IWL<15328> A_IWL<15327> A_IWL<15326> A_IWL<15325> A_IWL<15324> A_IWL<15323> A_IWL<15322> A_IWL<15321> A_IWL<15320> A_IWL<15319> A_IWL<15318> A_IWL<15317> A_IWL<15316> A_IWL<15315> A_IWL<15314> A_IWL<15313> A_IWL<15312> A_IWL<15311> A_IWL<15310> A_IWL<15309> A_IWL<15308> A_IWL<15307> A_IWL<15306> A_IWL<15305> A_IWL<15304> A_IWL<15303> A_IWL<15302> A_IWL<15301> A_IWL<15300> A_IWL<15299> A_IWL<15298> A_IWL<15297> A_IWL<15296> A_IWL<15295> A_IWL<15294> A_IWL<15293> A_IWL<15292> A_IWL<15291> A_IWL<15290> A_IWL<15289> A_IWL<15288> A_IWL<15287> A_IWL<15286> A_IWL<15285> A_IWL<15284> A_IWL<15283> A_IWL<15282> A_IWL<15281> A_IWL<15280> A_IWL<15279> A_IWL<15278> A_IWL<15277> A_IWL<15276> A_IWL<15275> A_IWL<15274> A_IWL<15273> A_IWL<15272> A_IWL<15271> A_IWL<15270> A_IWL<15269> A_IWL<15268> A_IWL<15267> A_IWL<15266> A_IWL<15265> A_IWL<15264> A_IWL<15263> A_IWL<15262> A_IWL<15261> A_IWL<15260> A_IWL<15259> A_IWL<15258> A_IWL<15257> A_IWL<15256> A_IWL<15255> A_IWL<15254> A_IWL<15253> A_IWL<15252> A_IWL<15251> A_IWL<15250> A_IWL<15249> A_IWL<15248> A_IWL<15247> A_IWL<15246> A_IWL<15245> A_IWL<15244> A_IWL<15243> A_IWL<15242> A_IWL<15241> A_IWL<15240> A_IWL<15239> A_IWL<15238> A_IWL<15237> A_IWL<15236> A_IWL<15235> A_IWL<15234> A_IWL<15233> A_IWL<15232> A_IWL<15231> A_IWL<15230> A_IWL<15229> A_IWL<15228> A_IWL<15227> A_IWL<15226> A_IWL<15225> A_IWL<15224> A_IWL<15223> A_IWL<15222> A_IWL<15221> A_IWL<15220> A_IWL<15219> A_IWL<15218> A_IWL<15217> A_IWL<15216> A_IWL<15215> A_IWL<15214> A_IWL<15213> A_IWL<15212> A_IWL<15211> A_IWL<15210> A_IWL<15209> A_IWL<15208> A_IWL<15207> A_IWL<15206> A_IWL<15205> A_IWL<15204> A_IWL<15203> A_IWL<15202> A_IWL<15201> A_IWL<15200> A_IWL<15199> A_IWL<15198> A_IWL<15197> A_IWL<15196> A_IWL<15195> A_IWL<15194> A_IWL<15193> A_IWL<15192> A_IWL<15191> A_IWL<15190> A_IWL<15189> A_IWL<15188> A_IWL<15187> A_IWL<15186> A_IWL<15185> A_IWL<15184> A_IWL<15183> A_IWL<15182> A_IWL<15181> A_IWL<15180> A_IWL<15179> A_IWL<15178> A_IWL<15177> A_IWL<15176> A_IWL<15175> A_IWL<15174> A_IWL<15173> A_IWL<15172> A_IWL<15171> A_IWL<15170> A_IWL<15169> A_IWL<15168> A_IWL<15167> A_IWL<15166> A_IWL<15165> A_IWL<15164> A_IWL<15163> A_IWL<15162> A_IWL<15161> A_IWL<15160> A_IWL<15159> A_IWL<15158> A_IWL<15157> A_IWL<15156> A_IWL<15155> A_IWL<15154> A_IWL<15153> A_IWL<15152> A_IWL<15151> A_IWL<15150> A_IWL<15149> A_IWL<15148> A_IWL<15147> A_IWL<15146> A_IWL<15145> A_IWL<15144> A_IWL<15143> A_IWL<15142> A_IWL<15141> A_IWL<15140> A_IWL<15139> A_IWL<15138> A_IWL<15137> A_IWL<15136> A_IWL<15135> A_IWL<15134> A_IWL<15133> A_IWL<15132> A_IWL<15131> A_IWL<15130> A_IWL<15129> A_IWL<15128> A_IWL<15127> A_IWL<15126> A_IWL<15125> A_IWL<15124> A_IWL<15123> A_IWL<15122> A_IWL<15121> A_IWL<15120> A_IWL<15119> A_IWL<15118> A_IWL<15117> A_IWL<15116> A_IWL<15115> A_IWL<15114> A_IWL<15113> A_IWL<15112> A_IWL<15111> A_IWL<15110> A_IWL<15109> A_IWL<15108> A_IWL<15107> A_IWL<15106> A_IWL<15105> A_IWL<15104> A_IWL<15103> A_IWL<15102> A_IWL<15101> A_IWL<15100> A_IWL<15099> A_IWL<15098> A_IWL<15097> A_IWL<15096> A_IWL<15095> A_IWL<15094> A_IWL<15093> A_IWL<15092> A_IWL<15091> A_IWL<15090> A_IWL<15089> A_IWL<15088> A_IWL<15087> A_IWL<15086> A_IWL<15085> A_IWL<15084> A_IWL<15083> A_IWL<15082> A_IWL<15081> A_IWL<15080> A_IWL<15079> A_IWL<15078> A_IWL<15077> A_IWL<15076> A_IWL<15075> A_IWL<15074> A_IWL<15073> A_IWL<15072> A_IWL<15071> A_IWL<15070> A_IWL<15069> A_IWL<15068> A_IWL<15067> A_IWL<15066> A_IWL<15065> A_IWL<15064> A_IWL<15063> A_IWL<15062> A_IWL<15061> A_IWL<15060> A_IWL<15059> A_IWL<15058> A_IWL<15057> A_IWL<15056> A_IWL<15055> A_IWL<15054> A_IWL<15053> A_IWL<15052> A_IWL<15051> A_IWL<15050> A_IWL<15049> A_IWL<15048> A_IWL<15047> A_IWL<15046> A_IWL<15045> A_IWL<15044> A_IWL<15043> A_IWL<15042> A_IWL<15041> A_IWL<15040> A_IWL<15039> A_IWL<15038> A_IWL<15037> A_IWL<15036> A_IWL<15035> A_IWL<15034> A_IWL<15033> A_IWL<15032> A_IWL<15031> A_IWL<15030> A_IWL<15029> A_IWL<15028> A_IWL<15027> A_IWL<15026> A_IWL<15025> A_IWL<15024> A_IWL<15023> A_IWL<15022> A_IWL<15021> A_IWL<15020> A_IWL<15019> A_IWL<15018> A_IWL<15017> A_IWL<15016> A_IWL<15015> A_IWL<15014> A_IWL<15013> A_IWL<15012> A_IWL<15011> A_IWL<15010> A_IWL<15009> A_IWL<15008> A_IWL<15007> A_IWL<15006> A_IWL<15005> A_IWL<15004> A_IWL<15003> A_IWL<15002> A_IWL<15001> A_IWL<15000> A_IWL<14999> A_IWL<14998> A_IWL<14997> A_IWL<14996> A_IWL<14995> A_IWL<14994> A_IWL<14993> A_IWL<14992> A_IWL<14991> A_IWL<14990> A_IWL<14989> A_IWL<14988> A_IWL<14987> A_IWL<14986> A_IWL<14985> A_IWL<14984> A_IWL<14983> A_IWL<14982> A_IWL<14981> A_IWL<14980> A_IWL<14979> A_IWL<14978> A_IWL<14977> A_IWL<14976> A_IWL<14975> A_IWL<14974> A_IWL<14973> A_IWL<14972> A_IWL<14971> A_IWL<14970> A_IWL<14969> A_IWL<14968> A_IWL<14967> A_IWL<14966> A_IWL<14965> A_IWL<14964> A_IWL<14963> A_IWL<14962> A_IWL<14961> A_IWL<14960> A_IWL<14959> A_IWL<14958> A_IWL<14957> A_IWL<14956> A_IWL<14955> A_IWL<14954> A_IWL<14953> A_IWL<14952> A_IWL<14951> A_IWL<14950> A_IWL<14949> A_IWL<14948> A_IWL<14947> A_IWL<14946> A_IWL<14945> A_IWL<14944> A_IWL<14943> A_IWL<14942> A_IWL<14941> A_IWL<14940> A_IWL<14939> A_IWL<14938> A_IWL<14937> A_IWL<14936> A_IWL<14935> A_IWL<14934> A_IWL<14933> A_IWL<14932> A_IWL<14931> A_IWL<14930> A_IWL<14929> A_IWL<14928> A_IWL<14927> A_IWL<14926> A_IWL<14925> A_IWL<14924> A_IWL<14923> A_IWL<14922> A_IWL<14921> A_IWL<14920> A_IWL<14919> A_IWL<14918> A_IWL<14917> A_IWL<14916> A_IWL<14915> A_IWL<14914> A_IWL<14913> A_IWL<14912> A_IWL<14911> A_IWL<14910> A_IWL<14909> A_IWL<14908> A_IWL<14907> A_IWL<14906> A_IWL<14905> A_IWL<14904> A_IWL<14903> A_IWL<14902> A_IWL<14901> A_IWL<14900> A_IWL<14899> A_IWL<14898> A_IWL<14897> A_IWL<14896> A_IWL<14895> A_IWL<14894> A_IWL<14893> A_IWL<14892> A_IWL<14891> A_IWL<14890> A_IWL<14889> A_IWL<14888> A_IWL<14887> A_IWL<14886> A_IWL<14885> A_IWL<14884> A_IWL<14883> A_IWL<14882> A_IWL<14881> A_IWL<14880> A_IWL<14879> A_IWL<14878> A_IWL<14877> A_IWL<14876> A_IWL<14875> A_IWL<14874> A_IWL<14873> A_IWL<14872> A_IWL<14871> A_IWL<14870> A_IWL<14869> A_IWL<14868> A_IWL<14867> A_IWL<14866> A_IWL<14865> A_IWL<14864> A_IWL<14863> A_IWL<14862> A_IWL<14861> A_IWL<14860> A_IWL<14859> A_IWL<14858> A_IWL<14857> A_IWL<14856> A_IWL<14855> A_IWL<14854> A_IWL<14853> A_IWL<14852> A_IWL<14851> A_IWL<14850> A_IWL<14849> A_IWL<14848> A_IWL<15871> A_IWL<15870> A_IWL<15869> A_IWL<15868> A_IWL<15867> A_IWL<15866> A_IWL<15865> A_IWL<15864> A_IWL<15863> A_IWL<15862> A_IWL<15861> A_IWL<15860> A_IWL<15859> A_IWL<15858> A_IWL<15857> A_IWL<15856> A_IWL<15855> A_IWL<15854> A_IWL<15853> A_IWL<15852> A_IWL<15851> A_IWL<15850> A_IWL<15849> A_IWL<15848> A_IWL<15847> A_IWL<15846> A_IWL<15845> A_IWL<15844> A_IWL<15843> A_IWL<15842> A_IWL<15841> A_IWL<15840> A_IWL<15839> A_IWL<15838> A_IWL<15837> A_IWL<15836> A_IWL<15835> A_IWL<15834> A_IWL<15833> A_IWL<15832> A_IWL<15831> A_IWL<15830> A_IWL<15829> A_IWL<15828> A_IWL<15827> A_IWL<15826> A_IWL<15825> A_IWL<15824> A_IWL<15823> A_IWL<15822> A_IWL<15821> A_IWL<15820> A_IWL<15819> A_IWL<15818> A_IWL<15817> A_IWL<15816> A_IWL<15815> A_IWL<15814> A_IWL<15813> A_IWL<15812> A_IWL<15811> A_IWL<15810> A_IWL<15809> A_IWL<15808> A_IWL<15807> A_IWL<15806> A_IWL<15805> A_IWL<15804> A_IWL<15803> A_IWL<15802> A_IWL<15801> A_IWL<15800> A_IWL<15799> A_IWL<15798> A_IWL<15797> A_IWL<15796> A_IWL<15795> A_IWL<15794> A_IWL<15793> A_IWL<15792> A_IWL<15791> A_IWL<15790> A_IWL<15789> A_IWL<15788> A_IWL<15787> A_IWL<15786> A_IWL<15785> A_IWL<15784> A_IWL<15783> A_IWL<15782> A_IWL<15781> A_IWL<15780> A_IWL<15779> A_IWL<15778> A_IWL<15777> A_IWL<15776> A_IWL<15775> A_IWL<15774> A_IWL<15773> A_IWL<15772> A_IWL<15771> A_IWL<15770> A_IWL<15769> A_IWL<15768> A_IWL<15767> A_IWL<15766> A_IWL<15765> A_IWL<15764> A_IWL<15763> A_IWL<15762> A_IWL<15761> A_IWL<15760> A_IWL<15759> A_IWL<15758> A_IWL<15757> A_IWL<15756> A_IWL<15755> A_IWL<15754> A_IWL<15753> A_IWL<15752> A_IWL<15751> A_IWL<15750> A_IWL<15749> A_IWL<15748> A_IWL<15747> A_IWL<15746> A_IWL<15745> A_IWL<15744> A_IWL<15743> A_IWL<15742> A_IWL<15741> A_IWL<15740> A_IWL<15739> A_IWL<15738> A_IWL<15737> A_IWL<15736> A_IWL<15735> A_IWL<15734> A_IWL<15733> A_IWL<15732> A_IWL<15731> A_IWL<15730> A_IWL<15729> A_IWL<15728> A_IWL<15727> A_IWL<15726> A_IWL<15725> A_IWL<15724> A_IWL<15723> A_IWL<15722> A_IWL<15721> A_IWL<15720> A_IWL<15719> A_IWL<15718> A_IWL<15717> A_IWL<15716> A_IWL<15715> A_IWL<15714> A_IWL<15713> A_IWL<15712> A_IWL<15711> A_IWL<15710> A_IWL<15709> A_IWL<15708> A_IWL<15707> A_IWL<15706> A_IWL<15705> A_IWL<15704> A_IWL<15703> A_IWL<15702> A_IWL<15701> A_IWL<15700> A_IWL<15699> A_IWL<15698> A_IWL<15697> A_IWL<15696> A_IWL<15695> A_IWL<15694> A_IWL<15693> A_IWL<15692> A_IWL<15691> A_IWL<15690> A_IWL<15689> A_IWL<15688> A_IWL<15687> A_IWL<15686> A_IWL<15685> A_IWL<15684> A_IWL<15683> A_IWL<15682> A_IWL<15681> A_IWL<15680> A_IWL<15679> A_IWL<15678> A_IWL<15677> A_IWL<15676> A_IWL<15675> A_IWL<15674> A_IWL<15673> A_IWL<15672> A_IWL<15671> A_IWL<15670> A_IWL<15669> A_IWL<15668> A_IWL<15667> A_IWL<15666> A_IWL<15665> A_IWL<15664> A_IWL<15663> A_IWL<15662> A_IWL<15661> A_IWL<15660> A_IWL<15659> A_IWL<15658> A_IWL<15657> A_IWL<15656> A_IWL<15655> A_IWL<15654> A_IWL<15653> A_IWL<15652> A_IWL<15651> A_IWL<15650> A_IWL<15649> A_IWL<15648> A_IWL<15647> A_IWL<15646> A_IWL<15645> A_IWL<15644> A_IWL<15643> A_IWL<15642> A_IWL<15641> A_IWL<15640> A_IWL<15639> A_IWL<15638> A_IWL<15637> A_IWL<15636> A_IWL<15635> A_IWL<15634> A_IWL<15633> A_IWL<15632> A_IWL<15631> A_IWL<15630> A_IWL<15629> A_IWL<15628> A_IWL<15627> A_IWL<15626> A_IWL<15625> A_IWL<15624> A_IWL<15623> A_IWL<15622> A_IWL<15621> A_IWL<15620> A_IWL<15619> A_IWL<15618> A_IWL<15617> A_IWL<15616> A_IWL<15615> A_IWL<15614> A_IWL<15613> A_IWL<15612> A_IWL<15611> A_IWL<15610> A_IWL<15609> A_IWL<15608> A_IWL<15607> A_IWL<15606> A_IWL<15605> A_IWL<15604> A_IWL<15603> A_IWL<15602> A_IWL<15601> A_IWL<15600> A_IWL<15599> A_IWL<15598> A_IWL<15597> A_IWL<15596> A_IWL<15595> A_IWL<15594> A_IWL<15593> A_IWL<15592> A_IWL<15591> A_IWL<15590> A_IWL<15589> A_IWL<15588> A_IWL<15587> A_IWL<15586> A_IWL<15585> A_IWL<15584> A_IWL<15583> A_IWL<15582> A_IWL<15581> A_IWL<15580> A_IWL<15579> A_IWL<15578> A_IWL<15577> A_IWL<15576> A_IWL<15575> A_IWL<15574> A_IWL<15573> A_IWL<15572> A_IWL<15571> A_IWL<15570> A_IWL<15569> A_IWL<15568> A_IWL<15567> A_IWL<15566> A_IWL<15565> A_IWL<15564> A_IWL<15563> A_IWL<15562> A_IWL<15561> A_IWL<15560> A_IWL<15559> A_IWL<15558> A_IWL<15557> A_IWL<15556> A_IWL<15555> A_IWL<15554> A_IWL<15553> A_IWL<15552> A_IWL<15551> A_IWL<15550> A_IWL<15549> A_IWL<15548> A_IWL<15547> A_IWL<15546> A_IWL<15545> A_IWL<15544> A_IWL<15543> A_IWL<15542> A_IWL<15541> A_IWL<15540> A_IWL<15539> A_IWL<15538> A_IWL<15537> A_IWL<15536> A_IWL<15535> A_IWL<15534> A_IWL<15533> A_IWL<15532> A_IWL<15531> A_IWL<15530> A_IWL<15529> A_IWL<15528> A_IWL<15527> A_IWL<15526> A_IWL<15525> A_IWL<15524> A_IWL<15523> A_IWL<15522> A_IWL<15521> A_IWL<15520> A_IWL<15519> A_IWL<15518> A_IWL<15517> A_IWL<15516> A_IWL<15515> A_IWL<15514> A_IWL<15513> A_IWL<15512> A_IWL<15511> A_IWL<15510> A_IWL<15509> A_IWL<15508> A_IWL<15507> A_IWL<15506> A_IWL<15505> A_IWL<15504> A_IWL<15503> A_IWL<15502> A_IWL<15501> A_IWL<15500> A_IWL<15499> A_IWL<15498> A_IWL<15497> A_IWL<15496> A_IWL<15495> A_IWL<15494> A_IWL<15493> A_IWL<15492> A_IWL<15491> A_IWL<15490> A_IWL<15489> A_IWL<15488> A_IWL<15487> A_IWL<15486> A_IWL<15485> A_IWL<15484> A_IWL<15483> A_IWL<15482> A_IWL<15481> A_IWL<15480> A_IWL<15479> A_IWL<15478> A_IWL<15477> A_IWL<15476> A_IWL<15475> A_IWL<15474> A_IWL<15473> A_IWL<15472> A_IWL<15471> A_IWL<15470> A_IWL<15469> A_IWL<15468> A_IWL<15467> A_IWL<15466> A_IWL<15465> A_IWL<15464> A_IWL<15463> A_IWL<15462> A_IWL<15461> A_IWL<15460> A_IWL<15459> A_IWL<15458> A_IWL<15457> A_IWL<15456> A_IWL<15455> A_IWL<15454> A_IWL<15453> A_IWL<15452> A_IWL<15451> A_IWL<15450> A_IWL<15449> A_IWL<15448> A_IWL<15447> A_IWL<15446> A_IWL<15445> A_IWL<15444> A_IWL<15443> A_IWL<15442> A_IWL<15441> A_IWL<15440> A_IWL<15439> A_IWL<15438> A_IWL<15437> A_IWL<15436> A_IWL<15435> A_IWL<15434> A_IWL<15433> A_IWL<15432> A_IWL<15431> A_IWL<15430> A_IWL<15429> A_IWL<15428> A_IWL<15427> A_IWL<15426> A_IWL<15425> A_IWL<15424> A_IWL<15423> A_IWL<15422> A_IWL<15421> A_IWL<15420> A_IWL<15419> A_IWL<15418> A_IWL<15417> A_IWL<15416> A_IWL<15415> A_IWL<15414> A_IWL<15413> A_IWL<15412> A_IWL<15411> A_IWL<15410> A_IWL<15409> A_IWL<15408> A_IWL<15407> A_IWL<15406> A_IWL<15405> A_IWL<15404> A_IWL<15403> A_IWL<15402> A_IWL<15401> A_IWL<15400> A_IWL<15399> A_IWL<15398> A_IWL<15397> A_IWL<15396> A_IWL<15395> A_IWL<15394> A_IWL<15393> A_IWL<15392> A_IWL<15391> A_IWL<15390> A_IWL<15389> A_IWL<15388> A_IWL<15387> A_IWL<15386> A_IWL<15385> A_IWL<15384> A_IWL<15383> A_IWL<15382> A_IWL<15381> A_IWL<15380> A_IWL<15379> A_IWL<15378> A_IWL<15377> A_IWL<15376> A_IWL<15375> A_IWL<15374> A_IWL<15373> A_IWL<15372> A_IWL<15371> A_IWL<15370> A_IWL<15369> A_IWL<15368> A_IWL<15367> A_IWL<15366> A_IWL<15365> A_IWL<15364> A_IWL<15363> A_IWL<15362> A_IWL<15361> A_IWL<15360> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0
+XCOL<29> A_BLC<59> A_BLC<58> A_BLC_TOP<59> A_BLC_TOP<58> A_BLT<59> A_BLT<58> A_BLT_TOP<59> A_BLT_TOP<58> A_IWL<14847> A_IWL<14846> A_IWL<14845> A_IWL<14844> A_IWL<14843> A_IWL<14842> A_IWL<14841> A_IWL<14840> A_IWL<14839> A_IWL<14838> A_IWL<14837> A_IWL<14836> A_IWL<14835> A_IWL<14834> A_IWL<14833> A_IWL<14832> A_IWL<14831> A_IWL<14830> A_IWL<14829> A_IWL<14828> A_IWL<14827> A_IWL<14826> A_IWL<14825> A_IWL<14824> A_IWL<14823> A_IWL<14822> A_IWL<14821> A_IWL<14820> A_IWL<14819> A_IWL<14818> A_IWL<14817> A_IWL<14816> A_IWL<14815> A_IWL<14814> A_IWL<14813> A_IWL<14812> A_IWL<14811> A_IWL<14810> A_IWL<14809> A_IWL<14808> A_IWL<14807> A_IWL<14806> A_IWL<14805> A_IWL<14804> A_IWL<14803> A_IWL<14802> A_IWL<14801> A_IWL<14800> A_IWL<14799> A_IWL<14798> A_IWL<14797> A_IWL<14796> A_IWL<14795> A_IWL<14794> A_IWL<14793> A_IWL<14792> A_IWL<14791> A_IWL<14790> A_IWL<14789> A_IWL<14788> A_IWL<14787> A_IWL<14786> A_IWL<14785> A_IWL<14784> A_IWL<14783> A_IWL<14782> A_IWL<14781> A_IWL<14780> A_IWL<14779> A_IWL<14778> A_IWL<14777> A_IWL<14776> A_IWL<14775> A_IWL<14774> A_IWL<14773> A_IWL<14772> A_IWL<14771> A_IWL<14770> A_IWL<14769> A_IWL<14768> A_IWL<14767> A_IWL<14766> A_IWL<14765> A_IWL<14764> A_IWL<14763> A_IWL<14762> A_IWL<14761> A_IWL<14760> A_IWL<14759> A_IWL<14758> A_IWL<14757> A_IWL<14756> A_IWL<14755> A_IWL<14754> A_IWL<14753> A_IWL<14752> A_IWL<14751> A_IWL<14750> A_IWL<14749> A_IWL<14748> A_IWL<14747> A_IWL<14746> A_IWL<14745> A_IWL<14744> A_IWL<14743> A_IWL<14742> A_IWL<14741> A_IWL<14740> A_IWL<14739> A_IWL<14738> A_IWL<14737> A_IWL<14736> A_IWL<14735> A_IWL<14734> A_IWL<14733> A_IWL<14732> A_IWL<14731> A_IWL<14730> A_IWL<14729> A_IWL<14728> A_IWL<14727> A_IWL<14726> A_IWL<14725> A_IWL<14724> A_IWL<14723> A_IWL<14722> A_IWL<14721> A_IWL<14720> A_IWL<14719> A_IWL<14718> A_IWL<14717> A_IWL<14716> A_IWL<14715> A_IWL<14714> A_IWL<14713> A_IWL<14712> A_IWL<14711> A_IWL<14710> A_IWL<14709> A_IWL<14708> A_IWL<14707> A_IWL<14706> A_IWL<14705> A_IWL<14704> A_IWL<14703> A_IWL<14702> A_IWL<14701> A_IWL<14700> A_IWL<14699> A_IWL<14698> A_IWL<14697> A_IWL<14696> A_IWL<14695> A_IWL<14694> A_IWL<14693> A_IWL<14692> A_IWL<14691> A_IWL<14690> A_IWL<14689> A_IWL<14688> A_IWL<14687> A_IWL<14686> A_IWL<14685> A_IWL<14684> A_IWL<14683> A_IWL<14682> A_IWL<14681> A_IWL<14680> A_IWL<14679> A_IWL<14678> A_IWL<14677> A_IWL<14676> A_IWL<14675> A_IWL<14674> A_IWL<14673> A_IWL<14672> A_IWL<14671> A_IWL<14670> A_IWL<14669> A_IWL<14668> A_IWL<14667> A_IWL<14666> A_IWL<14665> A_IWL<14664> A_IWL<14663> A_IWL<14662> A_IWL<14661> A_IWL<14660> A_IWL<14659> A_IWL<14658> A_IWL<14657> A_IWL<14656> A_IWL<14655> A_IWL<14654> A_IWL<14653> A_IWL<14652> A_IWL<14651> A_IWL<14650> A_IWL<14649> A_IWL<14648> A_IWL<14647> A_IWL<14646> A_IWL<14645> A_IWL<14644> A_IWL<14643> A_IWL<14642> A_IWL<14641> A_IWL<14640> A_IWL<14639> A_IWL<14638> A_IWL<14637> A_IWL<14636> A_IWL<14635> A_IWL<14634> A_IWL<14633> A_IWL<14632> A_IWL<14631> A_IWL<14630> A_IWL<14629> A_IWL<14628> A_IWL<14627> A_IWL<14626> A_IWL<14625> A_IWL<14624> A_IWL<14623> A_IWL<14622> A_IWL<14621> A_IWL<14620> A_IWL<14619> A_IWL<14618> A_IWL<14617> A_IWL<14616> A_IWL<14615> A_IWL<14614> A_IWL<14613> A_IWL<14612> A_IWL<14611> A_IWL<14610> A_IWL<14609> A_IWL<14608> A_IWL<14607> A_IWL<14606> A_IWL<14605> A_IWL<14604> A_IWL<14603> A_IWL<14602> A_IWL<14601> A_IWL<14600> A_IWL<14599> A_IWL<14598> A_IWL<14597> A_IWL<14596> A_IWL<14595> A_IWL<14594> A_IWL<14593> A_IWL<14592> A_IWL<14591> A_IWL<14590> A_IWL<14589> A_IWL<14588> A_IWL<14587> A_IWL<14586> A_IWL<14585> A_IWL<14584> A_IWL<14583> A_IWL<14582> A_IWL<14581> A_IWL<14580> A_IWL<14579> A_IWL<14578> A_IWL<14577> A_IWL<14576> A_IWL<14575> A_IWL<14574> A_IWL<14573> A_IWL<14572> A_IWL<14571> A_IWL<14570> A_IWL<14569> A_IWL<14568> A_IWL<14567> A_IWL<14566> A_IWL<14565> A_IWL<14564> A_IWL<14563> A_IWL<14562> A_IWL<14561> A_IWL<14560> A_IWL<14559> A_IWL<14558> A_IWL<14557> A_IWL<14556> A_IWL<14555> A_IWL<14554> A_IWL<14553> A_IWL<14552> A_IWL<14551> A_IWL<14550> A_IWL<14549> A_IWL<14548> A_IWL<14547> A_IWL<14546> A_IWL<14545> A_IWL<14544> A_IWL<14543> A_IWL<14542> A_IWL<14541> A_IWL<14540> A_IWL<14539> A_IWL<14538> A_IWL<14537> A_IWL<14536> A_IWL<14535> A_IWL<14534> A_IWL<14533> A_IWL<14532> A_IWL<14531> A_IWL<14530> A_IWL<14529> A_IWL<14528> A_IWL<14527> A_IWL<14526> A_IWL<14525> A_IWL<14524> A_IWL<14523> A_IWL<14522> A_IWL<14521> A_IWL<14520> A_IWL<14519> A_IWL<14518> A_IWL<14517> A_IWL<14516> A_IWL<14515> A_IWL<14514> A_IWL<14513> A_IWL<14512> A_IWL<14511> A_IWL<14510> A_IWL<14509> A_IWL<14508> A_IWL<14507> A_IWL<14506> A_IWL<14505> A_IWL<14504> A_IWL<14503> A_IWL<14502> A_IWL<14501> A_IWL<14500> A_IWL<14499> A_IWL<14498> A_IWL<14497> A_IWL<14496> A_IWL<14495> A_IWL<14494> A_IWL<14493> A_IWL<14492> A_IWL<14491> A_IWL<14490> A_IWL<14489> A_IWL<14488> A_IWL<14487> A_IWL<14486> A_IWL<14485> A_IWL<14484> A_IWL<14483> A_IWL<14482> A_IWL<14481> A_IWL<14480> A_IWL<14479> A_IWL<14478> A_IWL<14477> A_IWL<14476> A_IWL<14475> A_IWL<14474> A_IWL<14473> A_IWL<14472> A_IWL<14471> A_IWL<14470> A_IWL<14469> A_IWL<14468> A_IWL<14467> A_IWL<14466> A_IWL<14465> A_IWL<14464> A_IWL<14463> A_IWL<14462> A_IWL<14461> A_IWL<14460> A_IWL<14459> A_IWL<14458> A_IWL<14457> A_IWL<14456> A_IWL<14455> A_IWL<14454> A_IWL<14453> A_IWL<14452> A_IWL<14451> A_IWL<14450> A_IWL<14449> A_IWL<14448> A_IWL<14447> A_IWL<14446> A_IWL<14445> A_IWL<14444> A_IWL<14443> A_IWL<14442> A_IWL<14441> A_IWL<14440> A_IWL<14439> A_IWL<14438> A_IWL<14437> A_IWL<14436> A_IWL<14435> A_IWL<14434> A_IWL<14433> A_IWL<14432> A_IWL<14431> A_IWL<14430> A_IWL<14429> A_IWL<14428> A_IWL<14427> A_IWL<14426> A_IWL<14425> A_IWL<14424> A_IWL<14423> A_IWL<14422> A_IWL<14421> A_IWL<14420> A_IWL<14419> A_IWL<14418> A_IWL<14417> A_IWL<14416> A_IWL<14415> A_IWL<14414> A_IWL<14413> A_IWL<14412> A_IWL<14411> A_IWL<14410> A_IWL<14409> A_IWL<14408> A_IWL<14407> A_IWL<14406> A_IWL<14405> A_IWL<14404> A_IWL<14403> A_IWL<14402> A_IWL<14401> A_IWL<14400> A_IWL<14399> A_IWL<14398> A_IWL<14397> A_IWL<14396> A_IWL<14395> A_IWL<14394> A_IWL<14393> A_IWL<14392> A_IWL<14391> A_IWL<14390> A_IWL<14389> A_IWL<14388> A_IWL<14387> A_IWL<14386> A_IWL<14385> A_IWL<14384> A_IWL<14383> A_IWL<14382> A_IWL<14381> A_IWL<14380> A_IWL<14379> A_IWL<14378> A_IWL<14377> A_IWL<14376> A_IWL<14375> A_IWL<14374> A_IWL<14373> A_IWL<14372> A_IWL<14371> A_IWL<14370> A_IWL<14369> A_IWL<14368> A_IWL<14367> A_IWL<14366> A_IWL<14365> A_IWL<14364> A_IWL<14363> A_IWL<14362> A_IWL<14361> A_IWL<14360> A_IWL<14359> A_IWL<14358> A_IWL<14357> A_IWL<14356> A_IWL<14355> A_IWL<14354> A_IWL<14353> A_IWL<14352> A_IWL<14351> A_IWL<14350> A_IWL<14349> A_IWL<14348> A_IWL<14347> A_IWL<14346> A_IWL<14345> A_IWL<14344> A_IWL<14343> A_IWL<14342> A_IWL<14341> A_IWL<14340> A_IWL<14339> A_IWL<14338> A_IWL<14337> A_IWL<14336> A_IWL<15359> A_IWL<15358> A_IWL<15357> A_IWL<15356> A_IWL<15355> A_IWL<15354> A_IWL<15353> A_IWL<15352> A_IWL<15351> A_IWL<15350> A_IWL<15349> A_IWL<15348> A_IWL<15347> A_IWL<15346> A_IWL<15345> A_IWL<15344> A_IWL<15343> A_IWL<15342> A_IWL<15341> A_IWL<15340> A_IWL<15339> A_IWL<15338> A_IWL<15337> A_IWL<15336> A_IWL<15335> A_IWL<15334> A_IWL<15333> A_IWL<15332> A_IWL<15331> A_IWL<15330> A_IWL<15329> A_IWL<15328> A_IWL<15327> A_IWL<15326> A_IWL<15325> A_IWL<15324> A_IWL<15323> A_IWL<15322> A_IWL<15321> A_IWL<15320> A_IWL<15319> A_IWL<15318> A_IWL<15317> A_IWL<15316> A_IWL<15315> A_IWL<15314> A_IWL<15313> A_IWL<15312> A_IWL<15311> A_IWL<15310> A_IWL<15309> A_IWL<15308> A_IWL<15307> A_IWL<15306> A_IWL<15305> A_IWL<15304> A_IWL<15303> A_IWL<15302> A_IWL<15301> A_IWL<15300> A_IWL<15299> A_IWL<15298> A_IWL<15297> A_IWL<15296> A_IWL<15295> A_IWL<15294> A_IWL<15293> A_IWL<15292> A_IWL<15291> A_IWL<15290> A_IWL<15289> A_IWL<15288> A_IWL<15287> A_IWL<15286> A_IWL<15285> A_IWL<15284> A_IWL<15283> A_IWL<15282> A_IWL<15281> A_IWL<15280> A_IWL<15279> A_IWL<15278> A_IWL<15277> A_IWL<15276> A_IWL<15275> A_IWL<15274> A_IWL<15273> A_IWL<15272> A_IWL<15271> A_IWL<15270> A_IWL<15269> A_IWL<15268> A_IWL<15267> A_IWL<15266> A_IWL<15265> A_IWL<15264> A_IWL<15263> A_IWL<15262> A_IWL<15261> A_IWL<15260> A_IWL<15259> A_IWL<15258> A_IWL<15257> A_IWL<15256> A_IWL<15255> A_IWL<15254> A_IWL<15253> A_IWL<15252> A_IWL<15251> A_IWL<15250> A_IWL<15249> A_IWL<15248> A_IWL<15247> A_IWL<15246> A_IWL<15245> A_IWL<15244> A_IWL<15243> A_IWL<15242> A_IWL<15241> A_IWL<15240> A_IWL<15239> A_IWL<15238> A_IWL<15237> A_IWL<15236> A_IWL<15235> A_IWL<15234> A_IWL<15233> A_IWL<15232> A_IWL<15231> A_IWL<15230> A_IWL<15229> A_IWL<15228> A_IWL<15227> A_IWL<15226> A_IWL<15225> A_IWL<15224> A_IWL<15223> A_IWL<15222> A_IWL<15221> A_IWL<15220> A_IWL<15219> A_IWL<15218> A_IWL<15217> A_IWL<15216> A_IWL<15215> A_IWL<15214> A_IWL<15213> A_IWL<15212> A_IWL<15211> A_IWL<15210> A_IWL<15209> A_IWL<15208> A_IWL<15207> A_IWL<15206> A_IWL<15205> A_IWL<15204> A_IWL<15203> A_IWL<15202> A_IWL<15201> A_IWL<15200> A_IWL<15199> A_IWL<15198> A_IWL<15197> A_IWL<15196> A_IWL<15195> A_IWL<15194> A_IWL<15193> A_IWL<15192> A_IWL<15191> A_IWL<15190> A_IWL<15189> A_IWL<15188> A_IWL<15187> A_IWL<15186> A_IWL<15185> A_IWL<15184> A_IWL<15183> A_IWL<15182> A_IWL<15181> A_IWL<15180> A_IWL<15179> A_IWL<15178> A_IWL<15177> A_IWL<15176> A_IWL<15175> A_IWL<15174> A_IWL<15173> A_IWL<15172> A_IWL<15171> A_IWL<15170> A_IWL<15169> A_IWL<15168> A_IWL<15167> A_IWL<15166> A_IWL<15165> A_IWL<15164> A_IWL<15163> A_IWL<15162> A_IWL<15161> A_IWL<15160> A_IWL<15159> A_IWL<15158> A_IWL<15157> A_IWL<15156> A_IWL<15155> A_IWL<15154> A_IWL<15153> A_IWL<15152> A_IWL<15151> A_IWL<15150> A_IWL<15149> A_IWL<15148> A_IWL<15147> A_IWL<15146> A_IWL<15145> A_IWL<15144> A_IWL<15143> A_IWL<15142> A_IWL<15141> A_IWL<15140> A_IWL<15139> A_IWL<15138> A_IWL<15137> A_IWL<15136> A_IWL<15135> A_IWL<15134> A_IWL<15133> A_IWL<15132> A_IWL<15131> A_IWL<15130> A_IWL<15129> A_IWL<15128> A_IWL<15127> A_IWL<15126> A_IWL<15125> A_IWL<15124> A_IWL<15123> A_IWL<15122> A_IWL<15121> A_IWL<15120> A_IWL<15119> A_IWL<15118> A_IWL<15117> A_IWL<15116> A_IWL<15115> A_IWL<15114> A_IWL<15113> A_IWL<15112> A_IWL<15111> A_IWL<15110> A_IWL<15109> A_IWL<15108> A_IWL<15107> A_IWL<15106> A_IWL<15105> A_IWL<15104> A_IWL<15103> A_IWL<15102> A_IWL<15101> A_IWL<15100> A_IWL<15099> A_IWL<15098> A_IWL<15097> A_IWL<15096> A_IWL<15095> A_IWL<15094> A_IWL<15093> A_IWL<15092> A_IWL<15091> A_IWL<15090> A_IWL<15089> A_IWL<15088> A_IWL<15087> A_IWL<15086> A_IWL<15085> A_IWL<15084> A_IWL<15083> A_IWL<15082> A_IWL<15081> A_IWL<15080> A_IWL<15079> A_IWL<15078> A_IWL<15077> A_IWL<15076> A_IWL<15075> A_IWL<15074> A_IWL<15073> A_IWL<15072> A_IWL<15071> A_IWL<15070> A_IWL<15069> A_IWL<15068> A_IWL<15067> A_IWL<15066> A_IWL<15065> A_IWL<15064> A_IWL<15063> A_IWL<15062> A_IWL<15061> A_IWL<15060> A_IWL<15059> A_IWL<15058> A_IWL<15057> A_IWL<15056> A_IWL<15055> A_IWL<15054> A_IWL<15053> A_IWL<15052> A_IWL<15051> A_IWL<15050> A_IWL<15049> A_IWL<15048> A_IWL<15047> A_IWL<15046> A_IWL<15045> A_IWL<15044> A_IWL<15043> A_IWL<15042> A_IWL<15041> A_IWL<15040> A_IWL<15039> A_IWL<15038> A_IWL<15037> A_IWL<15036> A_IWL<15035> A_IWL<15034> A_IWL<15033> A_IWL<15032> A_IWL<15031> A_IWL<15030> A_IWL<15029> A_IWL<15028> A_IWL<15027> A_IWL<15026> A_IWL<15025> A_IWL<15024> A_IWL<15023> A_IWL<15022> A_IWL<15021> A_IWL<15020> A_IWL<15019> A_IWL<15018> A_IWL<15017> A_IWL<15016> A_IWL<15015> A_IWL<15014> A_IWL<15013> A_IWL<15012> A_IWL<15011> A_IWL<15010> A_IWL<15009> A_IWL<15008> A_IWL<15007> A_IWL<15006> A_IWL<15005> A_IWL<15004> A_IWL<15003> A_IWL<15002> A_IWL<15001> A_IWL<15000> A_IWL<14999> A_IWL<14998> A_IWL<14997> A_IWL<14996> A_IWL<14995> A_IWL<14994> A_IWL<14993> A_IWL<14992> A_IWL<14991> A_IWL<14990> A_IWL<14989> A_IWL<14988> A_IWL<14987> A_IWL<14986> A_IWL<14985> A_IWL<14984> A_IWL<14983> A_IWL<14982> A_IWL<14981> A_IWL<14980> A_IWL<14979> A_IWL<14978> A_IWL<14977> A_IWL<14976> A_IWL<14975> A_IWL<14974> A_IWL<14973> A_IWL<14972> A_IWL<14971> A_IWL<14970> A_IWL<14969> A_IWL<14968> A_IWL<14967> A_IWL<14966> A_IWL<14965> A_IWL<14964> A_IWL<14963> A_IWL<14962> A_IWL<14961> A_IWL<14960> A_IWL<14959> A_IWL<14958> A_IWL<14957> A_IWL<14956> A_IWL<14955> A_IWL<14954> A_IWL<14953> A_IWL<14952> A_IWL<14951> A_IWL<14950> A_IWL<14949> A_IWL<14948> A_IWL<14947> A_IWL<14946> A_IWL<14945> A_IWL<14944> A_IWL<14943> A_IWL<14942> A_IWL<14941> A_IWL<14940> A_IWL<14939> A_IWL<14938> A_IWL<14937> A_IWL<14936> A_IWL<14935> A_IWL<14934> A_IWL<14933> A_IWL<14932> A_IWL<14931> A_IWL<14930> A_IWL<14929> A_IWL<14928> A_IWL<14927> A_IWL<14926> A_IWL<14925> A_IWL<14924> A_IWL<14923> A_IWL<14922> A_IWL<14921> A_IWL<14920> A_IWL<14919> A_IWL<14918> A_IWL<14917> A_IWL<14916> A_IWL<14915> A_IWL<14914> A_IWL<14913> A_IWL<14912> A_IWL<14911> A_IWL<14910> A_IWL<14909> A_IWL<14908> A_IWL<14907> A_IWL<14906> A_IWL<14905> A_IWL<14904> A_IWL<14903> A_IWL<14902> A_IWL<14901> A_IWL<14900> A_IWL<14899> A_IWL<14898> A_IWL<14897> A_IWL<14896> A_IWL<14895> A_IWL<14894> A_IWL<14893> A_IWL<14892> A_IWL<14891> A_IWL<14890> A_IWL<14889> A_IWL<14888> A_IWL<14887> A_IWL<14886> A_IWL<14885> A_IWL<14884> A_IWL<14883> A_IWL<14882> A_IWL<14881> A_IWL<14880> A_IWL<14879> A_IWL<14878> A_IWL<14877> A_IWL<14876> A_IWL<14875> A_IWL<14874> A_IWL<14873> A_IWL<14872> A_IWL<14871> A_IWL<14870> A_IWL<14869> A_IWL<14868> A_IWL<14867> A_IWL<14866> A_IWL<14865> A_IWL<14864> A_IWL<14863> A_IWL<14862> A_IWL<14861> A_IWL<14860> A_IWL<14859> A_IWL<14858> A_IWL<14857> A_IWL<14856> A_IWL<14855> A_IWL<14854> A_IWL<14853> A_IWL<14852> A_IWL<14851> A_IWL<14850> A_IWL<14849> A_IWL<14848> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0
+XCOL<28> A_BLC<57> A_BLC<56> A_BLC_TOP<57> A_BLC_TOP<56> A_BLT<57> A_BLT<56> A_BLT_TOP<57> A_BLT_TOP<56> A_IWL<14335> A_IWL<14334> A_IWL<14333> A_IWL<14332> A_IWL<14331> A_IWL<14330> A_IWL<14329> A_IWL<14328> A_IWL<14327> A_IWL<14326> A_IWL<14325> A_IWL<14324> A_IWL<14323> A_IWL<14322> A_IWL<14321> A_IWL<14320> A_IWL<14319> A_IWL<14318> A_IWL<14317> A_IWL<14316> A_IWL<14315> A_IWL<14314> A_IWL<14313> A_IWL<14312> A_IWL<14311> A_IWL<14310> A_IWL<14309> A_IWL<14308> A_IWL<14307> A_IWL<14306> A_IWL<14305> A_IWL<14304> A_IWL<14303> A_IWL<14302> A_IWL<14301> A_IWL<14300> A_IWL<14299> A_IWL<14298> A_IWL<14297> A_IWL<14296> A_IWL<14295> A_IWL<14294> A_IWL<14293> A_IWL<14292> A_IWL<14291> A_IWL<14290> A_IWL<14289> A_IWL<14288> A_IWL<14287> A_IWL<14286> A_IWL<14285> A_IWL<14284> A_IWL<14283> A_IWL<14282> A_IWL<14281> A_IWL<14280> A_IWL<14279> A_IWL<14278> A_IWL<14277> A_IWL<14276> A_IWL<14275> A_IWL<14274> A_IWL<14273> A_IWL<14272> A_IWL<14271> A_IWL<14270> A_IWL<14269> A_IWL<14268> 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A_IWL<14317> A_IWL<14316> A_IWL<14315> A_IWL<14314> A_IWL<14313> A_IWL<14312> A_IWL<14311> A_IWL<14310> A_IWL<14309> A_IWL<14308> A_IWL<14307> A_IWL<14306> A_IWL<14305> A_IWL<14304> A_IWL<14303> A_IWL<14302> A_IWL<14301> A_IWL<14300> A_IWL<14299> A_IWL<14298> A_IWL<14297> A_IWL<14296> A_IWL<14295> A_IWL<14294> A_IWL<14293> A_IWL<14292> A_IWL<14291> A_IWL<14290> A_IWL<14289> A_IWL<14288> A_IWL<14287> A_IWL<14286> A_IWL<14285> A_IWL<14284> A_IWL<14283> A_IWL<14282> A_IWL<14281> A_IWL<14280> A_IWL<14279> A_IWL<14278> A_IWL<14277> A_IWL<14276> A_IWL<14275> A_IWL<14274> A_IWL<14273> A_IWL<14272> A_IWL<14271> A_IWL<14270> A_IWL<14269> A_IWL<14268> A_IWL<14267> A_IWL<14266> A_IWL<14265> A_IWL<14264> A_IWL<14263> A_IWL<14262> A_IWL<14261> A_IWL<14260> A_IWL<14259> A_IWL<14258> A_IWL<14257> A_IWL<14256> A_IWL<14255> A_IWL<14254> A_IWL<14253> A_IWL<14252> A_IWL<14251> A_IWL<14250> A_IWL<14249> A_IWL<14248> A_IWL<14247> A_IWL<14246> A_IWL<14245> A_IWL<14244> A_IWL<14243> A_IWL<14242> A_IWL<14241> A_IWL<14240> A_IWL<14239> A_IWL<14238> A_IWL<14237> A_IWL<14236> A_IWL<14235> A_IWL<14234> A_IWL<14233> A_IWL<14232> A_IWL<14231> A_IWL<14230> A_IWL<14229> A_IWL<14228> A_IWL<14227> A_IWL<14226> A_IWL<14225> A_IWL<14224> A_IWL<14223> A_IWL<14222> A_IWL<14221> A_IWL<14220> A_IWL<14219> A_IWL<14218> A_IWL<14217> A_IWL<14216> A_IWL<14215> A_IWL<14214> A_IWL<14213> A_IWL<14212> A_IWL<14211> A_IWL<14210> A_IWL<14209> A_IWL<14208> A_IWL<14207> A_IWL<14206> A_IWL<14205> A_IWL<14204> A_IWL<14203> A_IWL<14202> A_IWL<14201> A_IWL<14200> A_IWL<14199> A_IWL<14198> A_IWL<14197> A_IWL<14196> A_IWL<14195> A_IWL<14194> A_IWL<14193> A_IWL<14192> A_IWL<14191> A_IWL<14190> A_IWL<14189> A_IWL<14188> A_IWL<14187> A_IWL<14186> A_IWL<14185> A_IWL<14184> A_IWL<14183> A_IWL<14182> A_IWL<14181> A_IWL<14180> A_IWL<14179> A_IWL<14178> A_IWL<14177> A_IWL<14176> A_IWL<14175> A_IWL<14174> A_IWL<14173> A_IWL<14172> A_IWL<14171> A_IWL<14170> A_IWL<14169> A_IWL<14168> A_IWL<14167> A_IWL<14166> A_IWL<14165> A_IWL<14164> A_IWL<14163> A_IWL<14162> A_IWL<14161> A_IWL<14160> A_IWL<14159> A_IWL<14158> A_IWL<14157> A_IWL<14156> A_IWL<14155> A_IWL<14154> A_IWL<14153> A_IWL<14152> A_IWL<14151> A_IWL<14150> A_IWL<14149> A_IWL<14148> A_IWL<14147> A_IWL<14146> A_IWL<14145> A_IWL<14144> A_IWL<14143> A_IWL<14142> A_IWL<14141> A_IWL<14140> A_IWL<14139> A_IWL<14138> A_IWL<14137> A_IWL<14136> A_IWL<14135> A_IWL<14134> A_IWL<14133> A_IWL<14132> A_IWL<14131> A_IWL<14130> A_IWL<14129> A_IWL<14128> A_IWL<14127> A_IWL<14126> A_IWL<14125> A_IWL<14124> A_IWL<14123> A_IWL<14122> A_IWL<14121> A_IWL<14120> A_IWL<14119> A_IWL<14118> A_IWL<14117> A_IWL<14116> A_IWL<14115> A_IWL<14114> A_IWL<14113> A_IWL<14112> A_IWL<14111> A_IWL<14110> A_IWL<14109> A_IWL<14108> A_IWL<14107> A_IWL<14106> A_IWL<14105> A_IWL<14104> A_IWL<14103> A_IWL<14102> A_IWL<14101> A_IWL<14100> A_IWL<14099> A_IWL<14098> A_IWL<14097> A_IWL<14096> A_IWL<14095> A_IWL<14094> A_IWL<14093> A_IWL<14092> A_IWL<14091> A_IWL<14090> A_IWL<14089> A_IWL<14088> A_IWL<14087> A_IWL<14086> A_IWL<14085> A_IWL<14084> A_IWL<14083> A_IWL<14082> A_IWL<14081> A_IWL<14080> A_IWL<14079> A_IWL<14078> A_IWL<14077> A_IWL<14076> A_IWL<14075> A_IWL<14074> A_IWL<14073> A_IWL<14072> A_IWL<14071> A_IWL<14070> A_IWL<14069> A_IWL<14068> A_IWL<14067> A_IWL<14066> A_IWL<14065> A_IWL<14064> A_IWL<14063> A_IWL<14062> A_IWL<14061> A_IWL<14060> A_IWL<14059> A_IWL<14058> A_IWL<14057> A_IWL<14056> A_IWL<14055> A_IWL<14054> A_IWL<14053> A_IWL<14052> A_IWL<14051> A_IWL<14050> A_IWL<14049> A_IWL<14048> A_IWL<14047> A_IWL<14046> A_IWL<14045> A_IWL<14044> A_IWL<14043> A_IWL<14042> A_IWL<14041> A_IWL<14040> A_IWL<14039> A_IWL<14038> A_IWL<14037> A_IWL<14036> A_IWL<14035> A_IWL<14034> A_IWL<14033> A_IWL<14032> A_IWL<14031> A_IWL<14030> A_IWL<14029> A_IWL<14028> A_IWL<14027> A_IWL<14026> A_IWL<14025> A_IWL<14024> A_IWL<14023> A_IWL<14022> A_IWL<14021> A_IWL<14020> A_IWL<14019> A_IWL<14018> A_IWL<14017> A_IWL<14016> A_IWL<14015> A_IWL<14014> A_IWL<14013> A_IWL<14012> A_IWL<14011> A_IWL<14010> A_IWL<14009> A_IWL<14008> A_IWL<14007> A_IWL<14006> A_IWL<14005> A_IWL<14004> A_IWL<14003> A_IWL<14002> A_IWL<14001> A_IWL<14000> A_IWL<13999> A_IWL<13998> A_IWL<13997> A_IWL<13996> A_IWL<13995> A_IWL<13994> A_IWL<13993> A_IWL<13992> A_IWL<13991> A_IWL<13990> A_IWL<13989> A_IWL<13988> A_IWL<13987> A_IWL<13986> A_IWL<13985> A_IWL<13984> A_IWL<13983> A_IWL<13982> A_IWL<13981> A_IWL<13980> A_IWL<13979> A_IWL<13978> A_IWL<13977> A_IWL<13976> A_IWL<13975> A_IWL<13974> A_IWL<13973> A_IWL<13972> A_IWL<13971> A_IWL<13970> A_IWL<13969> A_IWL<13968> A_IWL<13967> A_IWL<13966> A_IWL<13965> A_IWL<13964> A_IWL<13963> A_IWL<13962> A_IWL<13961> A_IWL<13960> A_IWL<13959> A_IWL<13958> A_IWL<13957> A_IWL<13956> A_IWL<13955> A_IWL<13954> A_IWL<13953> A_IWL<13952> A_IWL<13951> A_IWL<13950> A_IWL<13949> A_IWL<13948> A_IWL<13947> A_IWL<13946> A_IWL<13945> A_IWL<13944> A_IWL<13943> A_IWL<13942> A_IWL<13941> A_IWL<13940> A_IWL<13939> A_IWL<13938> A_IWL<13937> A_IWL<13936> A_IWL<13935> A_IWL<13934> A_IWL<13933> A_IWL<13932> A_IWL<13931> A_IWL<13930> A_IWL<13929> A_IWL<13928> A_IWL<13927> A_IWL<13926> A_IWL<13925> A_IWL<13924> A_IWL<13923> A_IWL<13922> A_IWL<13921> A_IWL<13920> A_IWL<13919> A_IWL<13918> A_IWL<13917> A_IWL<13916> A_IWL<13915> A_IWL<13914> A_IWL<13913> A_IWL<13912> A_IWL<13911> A_IWL<13910> A_IWL<13909> A_IWL<13908> A_IWL<13907> A_IWL<13906> A_IWL<13905> A_IWL<13904> A_IWL<13903> A_IWL<13902> A_IWL<13901> A_IWL<13900> A_IWL<13899> A_IWL<13898> A_IWL<13897> A_IWL<13896> A_IWL<13895> A_IWL<13894> A_IWL<13893> A_IWL<13892> A_IWL<13891> A_IWL<13890> A_IWL<13889> A_IWL<13888> A_IWL<13887> A_IWL<13886> A_IWL<13885> A_IWL<13884> A_IWL<13883> A_IWL<13882> A_IWL<13881> A_IWL<13880> A_IWL<13879> A_IWL<13878> A_IWL<13877> A_IWL<13876> A_IWL<13875> A_IWL<13874> A_IWL<13873> A_IWL<13872> A_IWL<13871> A_IWL<13870> A_IWL<13869> A_IWL<13868> A_IWL<13867> A_IWL<13866> A_IWL<13865> A_IWL<13864> A_IWL<13863> A_IWL<13862> A_IWL<13861> A_IWL<13860> A_IWL<13859> A_IWL<13858> A_IWL<13857> A_IWL<13856> A_IWL<13855> A_IWL<13854> A_IWL<13853> A_IWL<13852> A_IWL<13851> A_IWL<13850> A_IWL<13849> A_IWL<13848> A_IWL<13847> A_IWL<13846> A_IWL<13845> A_IWL<13844> A_IWL<13843> A_IWL<13842> A_IWL<13841> A_IWL<13840> A_IWL<13839> A_IWL<13838> A_IWL<13837> A_IWL<13836> A_IWL<13835> A_IWL<13834> A_IWL<13833> A_IWL<13832> A_IWL<13831> A_IWL<13830> A_IWL<13829> A_IWL<13828> A_IWL<13827> A_IWL<13826> A_IWL<13825> A_IWL<13824> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0
+XCOL<26> A_BLC<53> A_BLC<52> A_BLC_TOP<53> A_BLC_TOP<52> A_BLT<53> A_BLT<52> A_BLT_TOP<53> A_BLT_TOP<52> A_IWL<13311> A_IWL<13310> A_IWL<13309> A_IWL<13308> A_IWL<13307> A_IWL<13306> A_IWL<13305> A_IWL<13304> A_IWL<13303> A_IWL<13302> A_IWL<13301> A_IWL<13300> A_IWL<13299> A_IWL<13298> A_IWL<13297> A_IWL<13296> A_IWL<13295> A_IWL<13294> A_IWL<13293> A_IWL<13292> A_IWL<13291> A_IWL<13290> A_IWL<13289> A_IWL<13288> A_IWL<13287> A_IWL<13286> A_IWL<13285> A_IWL<13284> A_IWL<13283> A_IWL<13282> A_IWL<13281> A_IWL<13280> A_IWL<13279> A_IWL<13278> A_IWL<13277> A_IWL<13276> A_IWL<13275> A_IWL<13274> A_IWL<13273> A_IWL<13272> A_IWL<13271> A_IWL<13270> A_IWL<13269> A_IWL<13268> A_IWL<13267> A_IWL<13266> A_IWL<13265> A_IWL<13264> A_IWL<13263> A_IWL<13262> A_IWL<13261> A_IWL<13260> A_IWL<13259> A_IWL<13258> A_IWL<13257> A_IWL<13256> A_IWL<13255> A_IWL<13254> A_IWL<13253> A_IWL<13252> A_IWL<13251> A_IWL<13250> A_IWL<13249> A_IWL<13248> A_IWL<13247> A_IWL<13246> A_IWL<13245> A_IWL<13244> A_IWL<13243> A_IWL<13242> A_IWL<13241> A_IWL<13240> A_IWL<13239> A_IWL<13238> A_IWL<13237> A_IWL<13236> A_IWL<13235> A_IWL<13234> A_IWL<13233> A_IWL<13232> A_IWL<13231> A_IWL<13230> A_IWL<13229> A_IWL<13228> A_IWL<13227> A_IWL<13226> A_IWL<13225> A_IWL<13224> A_IWL<13223> A_IWL<13222> A_IWL<13221> A_IWL<13220> A_IWL<13219> A_IWL<13218> A_IWL<13217> A_IWL<13216> A_IWL<13215> A_IWL<13214> A_IWL<13213> A_IWL<13212> A_IWL<13211> A_IWL<13210> A_IWL<13209> A_IWL<13208> A_IWL<13207> A_IWL<13206> A_IWL<13205> A_IWL<13204> A_IWL<13203> A_IWL<13202> A_IWL<13201> A_IWL<13200> A_IWL<13199> A_IWL<13198> A_IWL<13197> A_IWL<13196> A_IWL<13195> A_IWL<13194> A_IWL<13193> A_IWL<13192> A_IWL<13191> A_IWL<13190> A_IWL<13189> A_IWL<13188> A_IWL<13187> A_IWL<13186> A_IWL<13185> A_IWL<13184> A_IWL<13183> A_IWL<13182> A_IWL<13181> A_IWL<13180> A_IWL<13179> A_IWL<13178> A_IWL<13177> A_IWL<13176> A_IWL<13175> A_IWL<13174> A_IWL<13173> A_IWL<13172> A_IWL<13171> A_IWL<13170> A_IWL<13169> A_IWL<13168> A_IWL<13167> A_IWL<13166> A_IWL<13165> A_IWL<13164> A_IWL<13163> A_IWL<13162> A_IWL<13161> A_IWL<13160> A_IWL<13159> A_IWL<13158> A_IWL<13157> A_IWL<13156> A_IWL<13155> A_IWL<13154> A_IWL<13153> A_IWL<13152> A_IWL<13151> A_IWL<13150> A_IWL<13149> A_IWL<13148> A_IWL<13147> A_IWL<13146> A_IWL<13145> A_IWL<13144> A_IWL<13143> A_IWL<13142> A_IWL<13141> A_IWL<13140> A_IWL<13139> A_IWL<13138> A_IWL<13137> A_IWL<13136> A_IWL<13135> A_IWL<13134> A_IWL<13133> A_IWL<13132> A_IWL<13131> A_IWL<13130> A_IWL<13129> A_IWL<13128> A_IWL<13127> A_IWL<13126> A_IWL<13125> A_IWL<13124> A_IWL<13123> A_IWL<13122> A_IWL<13121> A_IWL<13120> A_IWL<13119> A_IWL<13118> A_IWL<13117> A_IWL<13116> A_IWL<13115> A_IWL<13114> A_IWL<13113> A_IWL<13112> A_IWL<13111> A_IWL<13110> A_IWL<13109> A_IWL<13108> A_IWL<13107> A_IWL<13106> A_IWL<13105> A_IWL<13104> A_IWL<13103> A_IWL<13102> A_IWL<13101> A_IWL<13100> A_IWL<13099> A_IWL<13098> A_IWL<13097> A_IWL<13096> A_IWL<13095> A_IWL<13094> A_IWL<13093> A_IWL<13092> A_IWL<13091> A_IWL<13090> A_IWL<13089> A_IWL<13088> A_IWL<13087> A_IWL<13086> A_IWL<13085> A_IWL<13084> A_IWL<13083> A_IWL<13082> A_IWL<13081> A_IWL<13080> A_IWL<13079> A_IWL<13078> A_IWL<13077> A_IWL<13076> A_IWL<13075> A_IWL<13074> A_IWL<13073> A_IWL<13072> A_IWL<13071> A_IWL<13070> A_IWL<13069> A_IWL<13068> A_IWL<13067> A_IWL<13066> A_IWL<13065> A_IWL<13064> A_IWL<13063> A_IWL<13062> A_IWL<13061> A_IWL<13060> A_IWL<13059> A_IWL<13058> A_IWL<13057> A_IWL<13056> A_IWL<13055> A_IWL<13054> A_IWL<13053> A_IWL<13052> A_IWL<13051> A_IWL<13050> A_IWL<13049> A_IWL<13048> A_IWL<13047> A_IWL<13046> A_IWL<13045> A_IWL<13044> A_IWL<13043> A_IWL<13042> A_IWL<13041> A_IWL<13040> A_IWL<13039> A_IWL<13038> A_IWL<13037> A_IWL<13036> A_IWL<13035> A_IWL<13034> A_IWL<13033> A_IWL<13032> A_IWL<13031> A_IWL<13030> A_IWL<13029> A_IWL<13028> A_IWL<13027> A_IWL<13026> A_IWL<13025> A_IWL<13024> A_IWL<13023> A_IWL<13022> A_IWL<13021> A_IWL<13020> A_IWL<13019> A_IWL<13018> A_IWL<13017> A_IWL<13016> A_IWL<13015> A_IWL<13014> A_IWL<13013> A_IWL<13012> A_IWL<13011> A_IWL<13010> A_IWL<13009> A_IWL<13008> A_IWL<13007> A_IWL<13006> A_IWL<13005> A_IWL<13004> A_IWL<13003> A_IWL<13002> A_IWL<13001> A_IWL<13000> A_IWL<12999> A_IWL<12998> A_IWL<12997> A_IWL<12996> A_IWL<12995> A_IWL<12994> A_IWL<12993> A_IWL<12992> A_IWL<12991> A_IWL<12990> A_IWL<12989> A_IWL<12988> A_IWL<12987> A_IWL<12986> A_IWL<12985> A_IWL<12984> A_IWL<12983> A_IWL<12982> A_IWL<12981> A_IWL<12980> A_IWL<12979> A_IWL<12978> A_IWL<12977> A_IWL<12976> A_IWL<12975> A_IWL<12974> A_IWL<12973> A_IWL<12972> A_IWL<12971> A_IWL<12970> A_IWL<12969> A_IWL<12968> A_IWL<12967> A_IWL<12966> A_IWL<12965> A_IWL<12964> A_IWL<12963> A_IWL<12962> A_IWL<12961> A_IWL<12960> A_IWL<12959> A_IWL<12958> A_IWL<12957> A_IWL<12956> A_IWL<12955> A_IWL<12954> A_IWL<12953> A_IWL<12952> A_IWL<12951> A_IWL<12950> A_IWL<12949> A_IWL<12948> A_IWL<12947> A_IWL<12946> A_IWL<12945> A_IWL<12944> A_IWL<12943> A_IWL<12942> A_IWL<12941> A_IWL<12940> A_IWL<12939> A_IWL<12938> A_IWL<12937> A_IWL<12936> A_IWL<12935> A_IWL<12934> A_IWL<12933> A_IWL<12932> A_IWL<12931> A_IWL<12930> A_IWL<12929> A_IWL<12928> A_IWL<12927> A_IWL<12926> A_IWL<12925> A_IWL<12924> A_IWL<12923> A_IWL<12922> A_IWL<12921> A_IWL<12920> A_IWL<12919> A_IWL<12918> A_IWL<12917> A_IWL<12916> A_IWL<12915> A_IWL<12914> A_IWL<12913> A_IWL<12912> A_IWL<12911> A_IWL<12910> A_IWL<12909> A_IWL<12908> A_IWL<12907> A_IWL<12906> A_IWL<12905> A_IWL<12904> A_IWL<12903> A_IWL<12902> A_IWL<12901> A_IWL<12900> A_IWL<12899> A_IWL<12898> A_IWL<12897> A_IWL<12896> A_IWL<12895> A_IWL<12894> A_IWL<12893> A_IWL<12892> A_IWL<12891> A_IWL<12890> A_IWL<12889> A_IWL<12888> A_IWL<12887> A_IWL<12886> A_IWL<12885> A_IWL<12884> A_IWL<12883> A_IWL<12882> A_IWL<12881> A_IWL<12880> A_IWL<12879> A_IWL<12878> A_IWL<12877> A_IWL<12876> A_IWL<12875> A_IWL<12874> A_IWL<12873> A_IWL<12872> A_IWL<12871> A_IWL<12870> A_IWL<12869> A_IWL<12868> A_IWL<12867> A_IWL<12866> A_IWL<12865> A_IWL<12864> A_IWL<12863> A_IWL<12862> A_IWL<12861> A_IWL<12860> A_IWL<12859> A_IWL<12858> A_IWL<12857> A_IWL<12856> A_IWL<12855> A_IWL<12854> A_IWL<12853> A_IWL<12852> A_IWL<12851> A_IWL<12850> A_IWL<12849> A_IWL<12848> A_IWL<12847> A_IWL<12846> A_IWL<12845> A_IWL<12844> A_IWL<12843> A_IWL<12842> A_IWL<12841> A_IWL<12840> A_IWL<12839> A_IWL<12838> A_IWL<12837> A_IWL<12836> A_IWL<12835> A_IWL<12834> A_IWL<12833> A_IWL<12832> A_IWL<12831> A_IWL<12830> A_IWL<12829> A_IWL<12828> A_IWL<12827> A_IWL<12826> A_IWL<12825> A_IWL<12824> A_IWL<12823> A_IWL<12822> A_IWL<12821> A_IWL<12820> A_IWL<12819> A_IWL<12818> A_IWL<12817> A_IWL<12816> A_IWL<12815> A_IWL<12814> A_IWL<12813> A_IWL<12812> A_IWL<12811> A_IWL<12810> A_IWL<12809> A_IWL<12808> A_IWL<12807> A_IWL<12806> A_IWL<12805> A_IWL<12804> A_IWL<12803> A_IWL<12802> A_IWL<12801> A_IWL<12800> A_IWL<13823> A_IWL<13822> A_IWL<13821> A_IWL<13820> A_IWL<13819> A_IWL<13818> A_IWL<13817> A_IWL<13816> A_IWL<13815> A_IWL<13814> A_IWL<13813> A_IWL<13812> A_IWL<13811> A_IWL<13810> A_IWL<13809> A_IWL<13808> A_IWL<13807> A_IWL<13806> A_IWL<13805> A_IWL<13804> A_IWL<13803> A_IWL<13802> A_IWL<13801> A_IWL<13800> A_IWL<13799> A_IWL<13798> A_IWL<13797> A_IWL<13796> A_IWL<13795> A_IWL<13794> A_IWL<13793> A_IWL<13792> A_IWL<13791> A_IWL<13790> A_IWL<13789> A_IWL<13788> A_IWL<13787> A_IWL<13786> A_IWL<13785> A_IWL<13784> A_IWL<13783> A_IWL<13782> A_IWL<13781> A_IWL<13780> A_IWL<13779> A_IWL<13778> A_IWL<13777> A_IWL<13776> A_IWL<13775> A_IWL<13774> A_IWL<13773> A_IWL<13772> A_IWL<13771> A_IWL<13770> A_IWL<13769> A_IWL<13768> A_IWL<13767> A_IWL<13766> A_IWL<13765> A_IWL<13764> A_IWL<13763> A_IWL<13762> A_IWL<13761> A_IWL<13760> A_IWL<13759> A_IWL<13758> A_IWL<13757> A_IWL<13756> A_IWL<13755> A_IWL<13754> A_IWL<13753> A_IWL<13752> A_IWL<13751> A_IWL<13750> A_IWL<13749> A_IWL<13748> A_IWL<13747> A_IWL<13746> A_IWL<13745> A_IWL<13744> A_IWL<13743> A_IWL<13742> A_IWL<13741> A_IWL<13740> A_IWL<13739> A_IWL<13738> A_IWL<13737> A_IWL<13736> A_IWL<13735> A_IWL<13734> A_IWL<13733> A_IWL<13732> A_IWL<13731> A_IWL<13730> A_IWL<13729> A_IWL<13728> A_IWL<13727> A_IWL<13726> A_IWL<13725> A_IWL<13724> A_IWL<13723> A_IWL<13722> A_IWL<13721> A_IWL<13720> A_IWL<13719> A_IWL<13718> A_IWL<13717> A_IWL<13716> A_IWL<13715> A_IWL<13714> A_IWL<13713> A_IWL<13712> A_IWL<13711> A_IWL<13710> A_IWL<13709> A_IWL<13708> A_IWL<13707> A_IWL<13706> A_IWL<13705> A_IWL<13704> A_IWL<13703> A_IWL<13702> A_IWL<13701> A_IWL<13700> A_IWL<13699> A_IWL<13698> A_IWL<13697> A_IWL<13696> A_IWL<13695> A_IWL<13694> A_IWL<13693> A_IWL<13692> A_IWL<13691> A_IWL<13690> A_IWL<13689> A_IWL<13688> A_IWL<13687> A_IWL<13686> A_IWL<13685> A_IWL<13684> A_IWL<13683> A_IWL<13682> A_IWL<13681> A_IWL<13680> A_IWL<13679> A_IWL<13678> A_IWL<13677> A_IWL<13676> A_IWL<13675> A_IWL<13674> A_IWL<13673> A_IWL<13672> A_IWL<13671> A_IWL<13670> A_IWL<13669> A_IWL<13668> A_IWL<13667> A_IWL<13666> A_IWL<13665> A_IWL<13664> A_IWL<13663> A_IWL<13662> A_IWL<13661> A_IWL<13660> A_IWL<13659> A_IWL<13658> A_IWL<13657> A_IWL<13656> A_IWL<13655> A_IWL<13654> A_IWL<13653> A_IWL<13652> A_IWL<13651> A_IWL<13650> A_IWL<13649> A_IWL<13648> A_IWL<13647> A_IWL<13646> A_IWL<13645> A_IWL<13644> A_IWL<13643> A_IWL<13642> A_IWL<13641> A_IWL<13640> A_IWL<13639> A_IWL<13638> A_IWL<13637> A_IWL<13636> A_IWL<13635> A_IWL<13634> A_IWL<13633> A_IWL<13632> A_IWL<13631> A_IWL<13630> A_IWL<13629> A_IWL<13628> A_IWL<13627> A_IWL<13626> A_IWL<13625> A_IWL<13624> A_IWL<13623> A_IWL<13622> A_IWL<13621> A_IWL<13620> A_IWL<13619> A_IWL<13618> A_IWL<13617> A_IWL<13616> A_IWL<13615> A_IWL<13614> A_IWL<13613> A_IWL<13612> A_IWL<13611> A_IWL<13610> A_IWL<13609> A_IWL<13608> A_IWL<13607> A_IWL<13606> A_IWL<13605> A_IWL<13604> A_IWL<13603> A_IWL<13602> A_IWL<13601> A_IWL<13600> A_IWL<13599> A_IWL<13598> A_IWL<13597> A_IWL<13596> A_IWL<13595> A_IWL<13594> A_IWL<13593> A_IWL<13592> A_IWL<13591> A_IWL<13590> A_IWL<13589> A_IWL<13588> A_IWL<13587> A_IWL<13586> A_IWL<13585> A_IWL<13584> A_IWL<13583> A_IWL<13582> A_IWL<13581> A_IWL<13580> A_IWL<13579> A_IWL<13578> A_IWL<13577> A_IWL<13576> A_IWL<13575> A_IWL<13574> A_IWL<13573> A_IWL<13572> A_IWL<13571> A_IWL<13570> A_IWL<13569> A_IWL<13568> A_IWL<13567> A_IWL<13566> A_IWL<13565> A_IWL<13564> A_IWL<13563> A_IWL<13562> A_IWL<13561> A_IWL<13560> A_IWL<13559> A_IWL<13558> A_IWL<13557> A_IWL<13556> A_IWL<13555> A_IWL<13554> A_IWL<13553> A_IWL<13552> A_IWL<13551> A_IWL<13550> A_IWL<13549> A_IWL<13548> A_IWL<13547> A_IWL<13546> A_IWL<13545> A_IWL<13544> A_IWL<13543> A_IWL<13542> A_IWL<13541> A_IWL<13540> A_IWL<13539> A_IWL<13538> A_IWL<13537> A_IWL<13536> A_IWL<13535> A_IWL<13534> A_IWL<13533> A_IWL<13532> A_IWL<13531> A_IWL<13530> A_IWL<13529> A_IWL<13528> A_IWL<13527> A_IWL<13526> A_IWL<13525> A_IWL<13524> A_IWL<13523> A_IWL<13522> A_IWL<13521> A_IWL<13520> A_IWL<13519> A_IWL<13518> A_IWL<13517> A_IWL<13516> A_IWL<13515> A_IWL<13514> A_IWL<13513> A_IWL<13512> A_IWL<13511> A_IWL<13510> A_IWL<13509> A_IWL<13508> A_IWL<13507> A_IWL<13506> A_IWL<13505> A_IWL<13504> A_IWL<13503> A_IWL<13502> A_IWL<13501> A_IWL<13500> A_IWL<13499> A_IWL<13498> A_IWL<13497> A_IWL<13496> A_IWL<13495> A_IWL<13494> A_IWL<13493> A_IWL<13492> A_IWL<13491> A_IWL<13490> A_IWL<13489> A_IWL<13488> A_IWL<13487> A_IWL<13486> A_IWL<13485> A_IWL<13484> A_IWL<13483> A_IWL<13482> A_IWL<13481> A_IWL<13480> A_IWL<13479> A_IWL<13478> A_IWL<13477> A_IWL<13476> A_IWL<13475> A_IWL<13474> A_IWL<13473> A_IWL<13472> A_IWL<13471> A_IWL<13470> A_IWL<13469> A_IWL<13468> A_IWL<13467> A_IWL<13466> A_IWL<13465> A_IWL<13464> A_IWL<13463> A_IWL<13462> A_IWL<13461> A_IWL<13460> A_IWL<13459> A_IWL<13458> A_IWL<13457> A_IWL<13456> A_IWL<13455> A_IWL<13454> A_IWL<13453> A_IWL<13452> A_IWL<13451> A_IWL<13450> A_IWL<13449> A_IWL<13448> A_IWL<13447> A_IWL<13446> A_IWL<13445> A_IWL<13444> A_IWL<13443> A_IWL<13442> A_IWL<13441> A_IWL<13440> A_IWL<13439> A_IWL<13438> A_IWL<13437> A_IWL<13436> A_IWL<13435> A_IWL<13434> A_IWL<13433> A_IWL<13432> A_IWL<13431> A_IWL<13430> A_IWL<13429> A_IWL<13428> A_IWL<13427> A_IWL<13426> A_IWL<13425> A_IWL<13424> A_IWL<13423> A_IWL<13422> A_IWL<13421> A_IWL<13420> A_IWL<13419> A_IWL<13418> A_IWL<13417> A_IWL<13416> A_IWL<13415> A_IWL<13414> A_IWL<13413> A_IWL<13412> A_IWL<13411> A_IWL<13410> A_IWL<13409> A_IWL<13408> A_IWL<13407> A_IWL<13406> A_IWL<13405> A_IWL<13404> A_IWL<13403> A_IWL<13402> A_IWL<13401> A_IWL<13400> A_IWL<13399> A_IWL<13398> A_IWL<13397> A_IWL<13396> A_IWL<13395> A_IWL<13394> A_IWL<13393> A_IWL<13392> A_IWL<13391> A_IWL<13390> A_IWL<13389> A_IWL<13388> A_IWL<13387> A_IWL<13386> A_IWL<13385> A_IWL<13384> A_IWL<13383> A_IWL<13382> A_IWL<13381> A_IWL<13380> A_IWL<13379> A_IWL<13378> A_IWL<13377> A_IWL<13376> A_IWL<13375> A_IWL<13374> A_IWL<13373> A_IWL<13372> A_IWL<13371> A_IWL<13370> A_IWL<13369> A_IWL<13368> A_IWL<13367> A_IWL<13366> A_IWL<13365> A_IWL<13364> A_IWL<13363> A_IWL<13362> A_IWL<13361> A_IWL<13360> A_IWL<13359> A_IWL<13358> A_IWL<13357> A_IWL<13356> A_IWL<13355> A_IWL<13354> A_IWL<13353> A_IWL<13352> A_IWL<13351> A_IWL<13350> A_IWL<13349> A_IWL<13348> A_IWL<13347> A_IWL<13346> A_IWL<13345> A_IWL<13344> A_IWL<13343> A_IWL<13342> A_IWL<13341> A_IWL<13340> A_IWL<13339> A_IWL<13338> A_IWL<13337> A_IWL<13336> A_IWL<13335> A_IWL<13334> A_IWL<13333> A_IWL<13332> A_IWL<13331> A_IWL<13330> A_IWL<13329> A_IWL<13328> A_IWL<13327> A_IWL<13326> A_IWL<13325> A_IWL<13324> A_IWL<13323> A_IWL<13322> A_IWL<13321> A_IWL<13320> A_IWL<13319> A_IWL<13318> A_IWL<13317> A_IWL<13316> A_IWL<13315> A_IWL<13314> A_IWL<13313> A_IWL<13312> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0
+XCOL<25> A_BLC<51> A_BLC<50> A_BLC_TOP<51> A_BLC_TOP<50> A_BLT<51> A_BLT<50> A_BLT_TOP<51> A_BLT_TOP<50> A_IWL<12799> A_IWL<12798> A_IWL<12797> A_IWL<12796> A_IWL<12795> A_IWL<12794> A_IWL<12793> A_IWL<12792> A_IWL<12791> A_IWL<12790> A_IWL<12789> A_IWL<12788> A_IWL<12787> A_IWL<12786> A_IWL<12785> A_IWL<12784> A_IWL<12783> A_IWL<12782> A_IWL<12781> A_IWL<12780> A_IWL<12779> A_IWL<12778> A_IWL<12777> A_IWL<12776> A_IWL<12775> A_IWL<12774> A_IWL<12773> A_IWL<12772> A_IWL<12771> A_IWL<12770> A_IWL<12769> A_IWL<12768> A_IWL<12767> A_IWL<12766> A_IWL<12765> A_IWL<12764> A_IWL<12763> A_IWL<12762> A_IWL<12761> A_IWL<12760> A_IWL<12759> A_IWL<12758> A_IWL<12757> A_IWL<12756> A_IWL<12755> A_IWL<12754> A_IWL<12753> A_IWL<12752> A_IWL<12751> A_IWL<12750> A_IWL<12749> A_IWL<12748> A_IWL<12747> A_IWL<12746> A_IWL<12745> A_IWL<12744> A_IWL<12743> A_IWL<12742> A_IWL<12741> A_IWL<12740> A_IWL<12739> A_IWL<12738> A_IWL<12737> A_IWL<12736> A_IWL<12735> A_IWL<12734> A_IWL<12733> A_IWL<12732> A_IWL<12731> A_IWL<12730> A_IWL<12729> A_IWL<12728> A_IWL<12727> A_IWL<12726> A_IWL<12725> A_IWL<12724> A_IWL<12723> A_IWL<12722> A_IWL<12721> A_IWL<12720> A_IWL<12719> A_IWL<12718> A_IWL<12717> A_IWL<12716> A_IWL<12715> A_IWL<12714> A_IWL<12713> A_IWL<12712> A_IWL<12711> A_IWL<12710> A_IWL<12709> A_IWL<12708> A_IWL<12707> A_IWL<12706> A_IWL<12705> A_IWL<12704> A_IWL<12703> A_IWL<12702> A_IWL<12701> A_IWL<12700> A_IWL<12699> A_IWL<12698> A_IWL<12697> A_IWL<12696> A_IWL<12695> A_IWL<12694> A_IWL<12693> A_IWL<12692> A_IWL<12691> A_IWL<12690> A_IWL<12689> A_IWL<12688> A_IWL<12687> A_IWL<12686> A_IWL<12685> A_IWL<12684> A_IWL<12683> A_IWL<12682> A_IWL<12681> A_IWL<12680> A_IWL<12679> A_IWL<12678> A_IWL<12677> A_IWL<12676> A_IWL<12675> A_IWL<12674> A_IWL<12673> A_IWL<12672> A_IWL<12671> A_IWL<12670> A_IWL<12669> A_IWL<12668> A_IWL<12667> A_IWL<12666> A_IWL<12665> A_IWL<12664> A_IWL<12663> A_IWL<12662> A_IWL<12661> A_IWL<12660> A_IWL<12659> A_IWL<12658> A_IWL<12657> A_IWL<12656> A_IWL<12655> A_IWL<12654> A_IWL<12653> A_IWL<12652> A_IWL<12651> A_IWL<12650> A_IWL<12649> A_IWL<12648> A_IWL<12647> A_IWL<12646> A_IWL<12645> A_IWL<12644> A_IWL<12643> A_IWL<12642> A_IWL<12641> A_IWL<12640> A_IWL<12639> A_IWL<12638> A_IWL<12637> A_IWL<12636> A_IWL<12635> A_IWL<12634> A_IWL<12633> A_IWL<12632> A_IWL<12631> A_IWL<12630> A_IWL<12629> A_IWL<12628> A_IWL<12627> A_IWL<12626> A_IWL<12625> A_IWL<12624> A_IWL<12623> A_IWL<12622> A_IWL<12621> A_IWL<12620> A_IWL<12619> A_IWL<12618> A_IWL<12617> A_IWL<12616> A_IWL<12615> A_IWL<12614> A_IWL<12613> A_IWL<12612> A_IWL<12611> A_IWL<12610> A_IWL<12609> A_IWL<12608> A_IWL<12607> A_IWL<12606> A_IWL<12605> A_IWL<12604> A_IWL<12603> A_IWL<12602> A_IWL<12601> A_IWL<12600> A_IWL<12599> A_IWL<12598> A_IWL<12597> A_IWL<12596> A_IWL<12595> A_IWL<12594> A_IWL<12593> A_IWL<12592> A_IWL<12591> A_IWL<12590> A_IWL<12589> A_IWL<12588> A_IWL<12587> A_IWL<12586> A_IWL<12585> A_IWL<12584> A_IWL<12583> A_IWL<12582> A_IWL<12581> A_IWL<12580> A_IWL<12579> A_IWL<12578> A_IWL<12577> A_IWL<12576> A_IWL<12575> A_IWL<12574> A_IWL<12573> A_IWL<12572> A_IWL<12571> A_IWL<12570> A_IWL<12569> A_IWL<12568> A_IWL<12567> A_IWL<12566> A_IWL<12565> A_IWL<12564> A_IWL<12563> A_IWL<12562> A_IWL<12561> A_IWL<12560> A_IWL<12559> A_IWL<12558> A_IWL<12557> A_IWL<12556> A_IWL<12555> A_IWL<12554> A_IWL<12553> A_IWL<12552> A_IWL<12551> A_IWL<12550> A_IWL<12549> A_IWL<12548> A_IWL<12547> A_IWL<12546> A_IWL<12545> A_IWL<12544> A_IWL<12543> A_IWL<12542> A_IWL<12541> A_IWL<12540> A_IWL<12539> A_IWL<12538> A_IWL<12537> A_IWL<12536> A_IWL<12535> A_IWL<12534> A_IWL<12533> A_IWL<12532> A_IWL<12531> A_IWL<12530> A_IWL<12529> A_IWL<12528> A_IWL<12527> A_IWL<12526> A_IWL<12525> A_IWL<12524> A_IWL<12523> A_IWL<12522> A_IWL<12521> A_IWL<12520> A_IWL<12519> A_IWL<12518> A_IWL<12517> A_IWL<12516> A_IWL<12515> A_IWL<12514> A_IWL<12513> A_IWL<12512> A_IWL<12511> A_IWL<12510> A_IWL<12509> A_IWL<12508> A_IWL<12507> A_IWL<12506> A_IWL<12505> A_IWL<12504> A_IWL<12503> A_IWL<12502> A_IWL<12501> A_IWL<12500> A_IWL<12499> A_IWL<12498> A_IWL<12497> A_IWL<12496> A_IWL<12495> A_IWL<12494> A_IWL<12493> A_IWL<12492> A_IWL<12491> A_IWL<12490> A_IWL<12489> A_IWL<12488> A_IWL<12487> A_IWL<12486> A_IWL<12485> A_IWL<12484> A_IWL<12483> A_IWL<12482> A_IWL<12481> A_IWL<12480> A_IWL<12479> A_IWL<12478> A_IWL<12477> A_IWL<12476> A_IWL<12475> A_IWL<12474> A_IWL<12473> A_IWL<12472> A_IWL<12471> A_IWL<12470> A_IWL<12469> A_IWL<12468> A_IWL<12467> A_IWL<12466> A_IWL<12465> A_IWL<12464> A_IWL<12463> A_IWL<12462> A_IWL<12461> A_IWL<12460> A_IWL<12459> A_IWL<12458> A_IWL<12457> A_IWL<12456> A_IWL<12455> A_IWL<12454> A_IWL<12453> A_IWL<12452> A_IWL<12451> A_IWL<12450> A_IWL<12449> A_IWL<12448> A_IWL<12447> A_IWL<12446> A_IWL<12445> A_IWL<12444> A_IWL<12443> A_IWL<12442> A_IWL<12441> A_IWL<12440> A_IWL<12439> A_IWL<12438> A_IWL<12437> A_IWL<12436> A_IWL<12435> A_IWL<12434> A_IWL<12433> A_IWL<12432> A_IWL<12431> A_IWL<12430> A_IWL<12429> A_IWL<12428> A_IWL<12427> A_IWL<12426> A_IWL<12425> A_IWL<12424> A_IWL<12423> A_IWL<12422> A_IWL<12421> A_IWL<12420> A_IWL<12419> A_IWL<12418> A_IWL<12417> A_IWL<12416> A_IWL<12415> A_IWL<12414> A_IWL<12413> A_IWL<12412> A_IWL<12411> A_IWL<12410> A_IWL<12409> A_IWL<12408> A_IWL<12407> A_IWL<12406> A_IWL<12405> A_IWL<12404> A_IWL<12403> A_IWL<12402> A_IWL<12401> A_IWL<12400> A_IWL<12399> A_IWL<12398> A_IWL<12397> A_IWL<12396> A_IWL<12395> A_IWL<12394> A_IWL<12393> A_IWL<12392> A_IWL<12391> A_IWL<12390> A_IWL<12389> A_IWL<12388> A_IWL<12387> A_IWL<12386> A_IWL<12385> A_IWL<12384> A_IWL<12383> A_IWL<12382> A_IWL<12381> A_IWL<12380> A_IWL<12379> A_IWL<12378> A_IWL<12377> A_IWL<12376> A_IWL<12375> A_IWL<12374> A_IWL<12373> A_IWL<12372> A_IWL<12371> A_IWL<12370> A_IWL<12369> A_IWL<12368> A_IWL<12367> A_IWL<12366> A_IWL<12365> A_IWL<12364> A_IWL<12363> A_IWL<12362> A_IWL<12361> A_IWL<12360> A_IWL<12359> A_IWL<12358> A_IWL<12357> A_IWL<12356> A_IWL<12355> A_IWL<12354> A_IWL<12353> A_IWL<12352> A_IWL<12351> A_IWL<12350> A_IWL<12349> A_IWL<12348> A_IWL<12347> A_IWL<12346> A_IWL<12345> A_IWL<12344> A_IWL<12343> A_IWL<12342> A_IWL<12341> A_IWL<12340> A_IWL<12339> A_IWL<12338> A_IWL<12337> A_IWL<12336> A_IWL<12335> A_IWL<12334> A_IWL<12333> A_IWL<12332> A_IWL<12331> A_IWL<12330> A_IWL<12329> A_IWL<12328> A_IWL<12327> A_IWL<12326> A_IWL<12325> A_IWL<12324> A_IWL<12323> A_IWL<12322> A_IWL<12321> A_IWL<12320> A_IWL<12319> A_IWL<12318> A_IWL<12317> A_IWL<12316> A_IWL<12315> A_IWL<12314> A_IWL<12313> A_IWL<12312> A_IWL<12311> A_IWL<12310> A_IWL<12309> A_IWL<12308> A_IWL<12307> A_IWL<12306> A_IWL<12305> A_IWL<12304> A_IWL<12303> A_IWL<12302> A_IWL<12301> A_IWL<12300> A_IWL<12299> A_IWL<12298> A_IWL<12297> A_IWL<12296> A_IWL<12295> A_IWL<12294> A_IWL<12293> A_IWL<12292> A_IWL<12291> A_IWL<12290> A_IWL<12289> A_IWL<12288> A_IWL<13311> A_IWL<13310> A_IWL<13309> A_IWL<13308> A_IWL<13307> A_IWL<13306> A_IWL<13305> A_IWL<13304> A_IWL<13303> A_IWL<13302> A_IWL<13301> A_IWL<13300> A_IWL<13299> A_IWL<13298> A_IWL<13297> A_IWL<13296> A_IWL<13295> A_IWL<13294> A_IWL<13293> A_IWL<13292> A_IWL<13291> A_IWL<13290> A_IWL<13289> A_IWL<13288> A_IWL<13287> A_IWL<13286> A_IWL<13285> A_IWL<13284> A_IWL<13283> A_IWL<13282> A_IWL<13281> A_IWL<13280> A_IWL<13279> A_IWL<13278> A_IWL<13277> A_IWL<13276> A_IWL<13275> A_IWL<13274> A_IWL<13273> A_IWL<13272> A_IWL<13271> A_IWL<13270> A_IWL<13269> A_IWL<13268> A_IWL<13267> A_IWL<13266> A_IWL<13265> A_IWL<13264> A_IWL<13263> A_IWL<13262> A_IWL<13261> A_IWL<13260> A_IWL<13259> A_IWL<13258> A_IWL<13257> A_IWL<13256> A_IWL<13255> A_IWL<13254> A_IWL<13253> A_IWL<13252> A_IWL<13251> A_IWL<13250> A_IWL<13249> A_IWL<13248> A_IWL<13247> A_IWL<13246> A_IWL<13245> A_IWL<13244> A_IWL<13243> A_IWL<13242> A_IWL<13241> A_IWL<13240> A_IWL<13239> A_IWL<13238> A_IWL<13237> A_IWL<13236> A_IWL<13235> A_IWL<13234> A_IWL<13233> A_IWL<13232> A_IWL<13231> A_IWL<13230> A_IWL<13229> A_IWL<13228> A_IWL<13227> A_IWL<13226> A_IWL<13225> A_IWL<13224> A_IWL<13223> A_IWL<13222> A_IWL<13221> A_IWL<13220> A_IWL<13219> A_IWL<13218> A_IWL<13217> A_IWL<13216> A_IWL<13215> A_IWL<13214> A_IWL<13213> A_IWL<13212> A_IWL<13211> A_IWL<13210> A_IWL<13209> A_IWL<13208> A_IWL<13207> A_IWL<13206> A_IWL<13205> A_IWL<13204> A_IWL<13203> A_IWL<13202> A_IWL<13201> A_IWL<13200> A_IWL<13199> A_IWL<13198> A_IWL<13197> A_IWL<13196> A_IWL<13195> A_IWL<13194> A_IWL<13193> A_IWL<13192> A_IWL<13191> A_IWL<13190> A_IWL<13189> A_IWL<13188> A_IWL<13187> A_IWL<13186> A_IWL<13185> A_IWL<13184> A_IWL<13183> A_IWL<13182> A_IWL<13181> A_IWL<13180> A_IWL<13179> A_IWL<13178> A_IWL<13177> A_IWL<13176> A_IWL<13175> A_IWL<13174> A_IWL<13173> A_IWL<13172> A_IWL<13171> A_IWL<13170> A_IWL<13169> A_IWL<13168> A_IWL<13167> A_IWL<13166> A_IWL<13165> A_IWL<13164> A_IWL<13163> A_IWL<13162> A_IWL<13161> A_IWL<13160> A_IWL<13159> A_IWL<13158> A_IWL<13157> A_IWL<13156> A_IWL<13155> A_IWL<13154> A_IWL<13153> A_IWL<13152> A_IWL<13151> A_IWL<13150> A_IWL<13149> A_IWL<13148> A_IWL<13147> A_IWL<13146> A_IWL<13145> A_IWL<13144> A_IWL<13143> A_IWL<13142> A_IWL<13141> A_IWL<13140> A_IWL<13139> A_IWL<13138> A_IWL<13137> A_IWL<13136> A_IWL<13135> A_IWL<13134> A_IWL<13133> A_IWL<13132> A_IWL<13131> A_IWL<13130> A_IWL<13129> A_IWL<13128> A_IWL<13127> A_IWL<13126> A_IWL<13125> A_IWL<13124> A_IWL<13123> A_IWL<13122> A_IWL<13121> A_IWL<13120> A_IWL<13119> A_IWL<13118> A_IWL<13117> A_IWL<13116> A_IWL<13115> A_IWL<13114> A_IWL<13113> A_IWL<13112> A_IWL<13111> A_IWL<13110> A_IWL<13109> A_IWL<13108> A_IWL<13107> A_IWL<13106> A_IWL<13105> A_IWL<13104> A_IWL<13103> A_IWL<13102> A_IWL<13101> A_IWL<13100> A_IWL<13099> A_IWL<13098> A_IWL<13097> A_IWL<13096> A_IWL<13095> A_IWL<13094> A_IWL<13093> A_IWL<13092> A_IWL<13091> A_IWL<13090> A_IWL<13089> A_IWL<13088> A_IWL<13087> A_IWL<13086> A_IWL<13085> A_IWL<13084> A_IWL<13083> A_IWL<13082> A_IWL<13081> A_IWL<13080> A_IWL<13079> A_IWL<13078> A_IWL<13077> A_IWL<13076> A_IWL<13075> A_IWL<13074> A_IWL<13073> A_IWL<13072> A_IWL<13071> A_IWL<13070> A_IWL<13069> A_IWL<13068> A_IWL<13067> A_IWL<13066> A_IWL<13065> A_IWL<13064> A_IWL<13063> A_IWL<13062> A_IWL<13061> A_IWL<13060> A_IWL<13059> A_IWL<13058> A_IWL<13057> A_IWL<13056> A_IWL<13055> A_IWL<13054> A_IWL<13053> A_IWL<13052> A_IWL<13051> A_IWL<13050> A_IWL<13049> A_IWL<13048> A_IWL<13047> A_IWL<13046> A_IWL<13045> A_IWL<13044> A_IWL<13043> A_IWL<13042> A_IWL<13041> A_IWL<13040> A_IWL<13039> A_IWL<13038> A_IWL<13037> A_IWL<13036> A_IWL<13035> A_IWL<13034> A_IWL<13033> A_IWL<13032> A_IWL<13031> A_IWL<13030> A_IWL<13029> A_IWL<13028> A_IWL<13027> A_IWL<13026> A_IWL<13025> A_IWL<13024> A_IWL<13023> A_IWL<13022> A_IWL<13021> A_IWL<13020> A_IWL<13019> A_IWL<13018> A_IWL<13017> A_IWL<13016> A_IWL<13015> A_IWL<13014> A_IWL<13013> A_IWL<13012> A_IWL<13011> A_IWL<13010> A_IWL<13009> A_IWL<13008> A_IWL<13007> A_IWL<13006> A_IWL<13005> A_IWL<13004> A_IWL<13003> A_IWL<13002> A_IWL<13001> A_IWL<13000> A_IWL<12999> A_IWL<12998> A_IWL<12997> A_IWL<12996> A_IWL<12995> A_IWL<12994> A_IWL<12993> A_IWL<12992> A_IWL<12991> A_IWL<12990> A_IWL<12989> A_IWL<12988> A_IWL<12987> A_IWL<12986> A_IWL<12985> A_IWL<12984> A_IWL<12983> A_IWL<12982> A_IWL<12981> A_IWL<12980> A_IWL<12979> A_IWL<12978> A_IWL<12977> A_IWL<12976> A_IWL<12975> A_IWL<12974> A_IWL<12973> A_IWL<12972> A_IWL<12971> A_IWL<12970> A_IWL<12969> A_IWL<12968> A_IWL<12967> A_IWL<12966> A_IWL<12965> A_IWL<12964> A_IWL<12963> A_IWL<12962> A_IWL<12961> A_IWL<12960> A_IWL<12959> A_IWL<12958> A_IWL<12957> A_IWL<12956> A_IWL<12955> A_IWL<12954> A_IWL<12953> A_IWL<12952> A_IWL<12951> A_IWL<12950> A_IWL<12949> A_IWL<12948> A_IWL<12947> A_IWL<12946> A_IWL<12945> A_IWL<12944> A_IWL<12943> A_IWL<12942> A_IWL<12941> A_IWL<12940> A_IWL<12939> A_IWL<12938> A_IWL<12937> A_IWL<12936> A_IWL<12935> A_IWL<12934> A_IWL<12933> A_IWL<12932> A_IWL<12931> A_IWL<12930> A_IWL<12929> A_IWL<12928> A_IWL<12927> A_IWL<12926> A_IWL<12925> A_IWL<12924> A_IWL<12923> A_IWL<12922> A_IWL<12921> A_IWL<12920> A_IWL<12919> A_IWL<12918> A_IWL<12917> A_IWL<12916> A_IWL<12915> A_IWL<12914> A_IWL<12913> A_IWL<12912> A_IWL<12911> A_IWL<12910> A_IWL<12909> A_IWL<12908> A_IWL<12907> A_IWL<12906> A_IWL<12905> A_IWL<12904> A_IWL<12903> A_IWL<12902> A_IWL<12901> A_IWL<12900> A_IWL<12899> A_IWL<12898> A_IWL<12897> A_IWL<12896> A_IWL<12895> A_IWL<12894> A_IWL<12893> A_IWL<12892> A_IWL<12891> A_IWL<12890> A_IWL<12889> A_IWL<12888> A_IWL<12887> A_IWL<12886> A_IWL<12885> A_IWL<12884> A_IWL<12883> A_IWL<12882> A_IWL<12881> A_IWL<12880> A_IWL<12879> A_IWL<12878> A_IWL<12877> A_IWL<12876> A_IWL<12875> A_IWL<12874> A_IWL<12873> A_IWL<12872> A_IWL<12871> A_IWL<12870> A_IWL<12869> A_IWL<12868> A_IWL<12867> A_IWL<12866> A_IWL<12865> A_IWL<12864> A_IWL<12863> A_IWL<12862> A_IWL<12861> A_IWL<12860> A_IWL<12859> A_IWL<12858> A_IWL<12857> A_IWL<12856> A_IWL<12855> A_IWL<12854> A_IWL<12853> A_IWL<12852> A_IWL<12851> A_IWL<12850> A_IWL<12849> A_IWL<12848> A_IWL<12847> A_IWL<12846> A_IWL<12845> A_IWL<12844> A_IWL<12843> A_IWL<12842> A_IWL<12841> A_IWL<12840> A_IWL<12839> A_IWL<12838> A_IWL<12837> A_IWL<12836> A_IWL<12835> A_IWL<12834> A_IWL<12833> A_IWL<12832> A_IWL<12831> A_IWL<12830> A_IWL<12829> A_IWL<12828> A_IWL<12827> A_IWL<12826> A_IWL<12825> A_IWL<12824> A_IWL<12823> A_IWL<12822> A_IWL<12821> A_IWL<12820> A_IWL<12819> A_IWL<12818> A_IWL<12817> A_IWL<12816> A_IWL<12815> A_IWL<12814> A_IWL<12813> A_IWL<12812> A_IWL<12811> A_IWL<12810> A_IWL<12809> A_IWL<12808> A_IWL<12807> A_IWL<12806> A_IWL<12805> A_IWL<12804> A_IWL<12803> A_IWL<12802> A_IWL<12801> A_IWL<12800> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0
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A_IWL<12473> A_IWL<12472> A_IWL<12471> A_IWL<12470> A_IWL<12469> A_IWL<12468> A_IWL<12467> A_IWL<12466> A_IWL<12465> A_IWL<12464> A_IWL<12463> A_IWL<12462> A_IWL<12461> A_IWL<12460> A_IWL<12459> A_IWL<12458> A_IWL<12457> A_IWL<12456> A_IWL<12455> A_IWL<12454> A_IWL<12453> A_IWL<12452> A_IWL<12451> A_IWL<12450> A_IWL<12449> A_IWL<12448> A_IWL<12447> A_IWL<12446> A_IWL<12445> A_IWL<12444> A_IWL<12443> A_IWL<12442> A_IWL<12441> A_IWL<12440> A_IWL<12439> A_IWL<12438> A_IWL<12437> A_IWL<12436> A_IWL<12435> A_IWL<12434> A_IWL<12433> A_IWL<12432> A_IWL<12431> A_IWL<12430> A_IWL<12429> A_IWL<12428> A_IWL<12427> A_IWL<12426> A_IWL<12425> A_IWL<12424> A_IWL<12423> A_IWL<12422> A_IWL<12421> A_IWL<12420> A_IWL<12419> A_IWL<12418> A_IWL<12417> A_IWL<12416> A_IWL<12415> A_IWL<12414> A_IWL<12413> A_IWL<12412> A_IWL<12411> A_IWL<12410> A_IWL<12409> A_IWL<12408> A_IWL<12407> A_IWL<12406> A_IWL<12405> A_IWL<12404> A_IWL<12403> A_IWL<12402> A_IWL<12401> A_IWL<12400> A_IWL<12399> A_IWL<12398> A_IWL<12397> A_IWL<12396> A_IWL<12395> A_IWL<12394> A_IWL<12393> A_IWL<12392> A_IWL<12391> A_IWL<12390> A_IWL<12389> A_IWL<12388> A_IWL<12387> A_IWL<12386> A_IWL<12385> A_IWL<12384> A_IWL<12383> A_IWL<12382> A_IWL<12381> A_IWL<12380> A_IWL<12379> A_IWL<12378> A_IWL<12377> A_IWL<12376> A_IWL<12375> A_IWL<12374> A_IWL<12373> A_IWL<12372> A_IWL<12371> A_IWL<12370> A_IWL<12369> A_IWL<12368> A_IWL<12367> A_IWL<12366> A_IWL<12365> A_IWL<12364> A_IWL<12363> A_IWL<12362> A_IWL<12361> A_IWL<12360> A_IWL<12359> A_IWL<12358> A_IWL<12357> A_IWL<12356> A_IWL<12355> A_IWL<12354> A_IWL<12353> A_IWL<12352> A_IWL<12351> A_IWL<12350> A_IWL<12349> A_IWL<12348> A_IWL<12347> A_IWL<12346> A_IWL<12345> A_IWL<12344> A_IWL<12343> A_IWL<12342> A_IWL<12341> A_IWL<12340> A_IWL<12339> A_IWL<12338> A_IWL<12337> A_IWL<12336> A_IWL<12335> A_IWL<12334> A_IWL<12333> A_IWL<12332> A_IWL<12331> A_IWL<12330> A_IWL<12329> A_IWL<12328> A_IWL<12327> A_IWL<12326> A_IWL<12325> A_IWL<12324> A_IWL<12323> A_IWL<12322> A_IWL<12321> A_IWL<12320> A_IWL<12319> A_IWL<12318> A_IWL<12317> A_IWL<12316> A_IWL<12315> A_IWL<12314> A_IWL<12313> A_IWL<12312> A_IWL<12311> A_IWL<12310> A_IWL<12309> A_IWL<12308> A_IWL<12307> A_IWL<12306> A_IWL<12305> A_IWL<12304> A_IWL<12303> A_IWL<12302> A_IWL<12301> A_IWL<12300> A_IWL<12299> A_IWL<12298> A_IWL<12297> A_IWL<12296> A_IWL<12295> A_IWL<12294> A_IWL<12293> A_IWL<12292> A_IWL<12291> A_IWL<12290> A_IWL<12289> A_IWL<12288> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0
+XCOL<23> A_BLC<47> A_BLC<46> A_BLC_TOP<47> A_BLC_TOP<46> A_BLT<47> A_BLT<46> A_BLT_TOP<47> A_BLT_TOP<46> A_IWL<11775> A_IWL<11774> A_IWL<11773> A_IWL<11772> A_IWL<11771> A_IWL<11770> A_IWL<11769> A_IWL<11768> A_IWL<11767> A_IWL<11766> A_IWL<11765> A_IWL<11764> A_IWL<11763> A_IWL<11762> A_IWL<11761> A_IWL<11760> A_IWL<11759> A_IWL<11758> A_IWL<11757> A_IWL<11756> A_IWL<11755> A_IWL<11754> A_IWL<11753> A_IWL<11752> A_IWL<11751> A_IWL<11750> A_IWL<11749> A_IWL<11748> A_IWL<11747> A_IWL<11746> A_IWL<11745> A_IWL<11744> A_IWL<11743> A_IWL<11742> A_IWL<11741> A_IWL<11740> A_IWL<11739> A_IWL<11738> A_IWL<11737> A_IWL<11736> A_IWL<11735> A_IWL<11734> A_IWL<11733> A_IWL<11732> A_IWL<11731> A_IWL<11730> A_IWL<11729> A_IWL<11728> A_IWL<11727> A_IWL<11726> A_IWL<11725> A_IWL<11724> A_IWL<11723> A_IWL<11722> A_IWL<11721> A_IWL<11720> A_IWL<11719> A_IWL<11718> A_IWL<11717> A_IWL<11716> A_IWL<11715> A_IWL<11714> A_IWL<11713> A_IWL<11712> A_IWL<11711> A_IWL<11710> A_IWL<11709> A_IWL<11708> A_IWL<11707> A_IWL<11706> A_IWL<11705> A_IWL<11704> A_IWL<11703> A_IWL<11702> A_IWL<11701> A_IWL<11700> A_IWL<11699> A_IWL<11698> A_IWL<11697> A_IWL<11696> A_IWL<11695> A_IWL<11694> A_IWL<11693> A_IWL<11692> A_IWL<11691> A_IWL<11690> A_IWL<11689> A_IWL<11688> A_IWL<11687> A_IWL<11686> A_IWL<11685> A_IWL<11684> A_IWL<11683> A_IWL<11682> A_IWL<11681> A_IWL<11680> A_IWL<11679> A_IWL<11678> A_IWL<11677> A_IWL<11676> A_IWL<11675> A_IWL<11674> A_IWL<11673> A_IWL<11672> A_IWL<11671> A_IWL<11670> A_IWL<11669> A_IWL<11668> A_IWL<11667> A_IWL<11666> A_IWL<11665> A_IWL<11664> A_IWL<11663> A_IWL<11662> A_IWL<11661> A_IWL<11660> A_IWL<11659> A_IWL<11658> A_IWL<11657> A_IWL<11656> A_IWL<11655> A_IWL<11654> A_IWL<11653> A_IWL<11652> A_IWL<11651> A_IWL<11650> A_IWL<11649> A_IWL<11648> A_IWL<11647> A_IWL<11646> A_IWL<11645> A_IWL<11644> A_IWL<11643> A_IWL<11642> A_IWL<11641> A_IWL<11640> A_IWL<11639> A_IWL<11638> A_IWL<11637> A_IWL<11636> A_IWL<11635> A_IWL<11634> A_IWL<11633> A_IWL<11632> A_IWL<11631> A_IWL<11630> A_IWL<11629> A_IWL<11628> A_IWL<11627> A_IWL<11626> A_IWL<11625> A_IWL<11624> A_IWL<11623> A_IWL<11622> A_IWL<11621> A_IWL<11620> A_IWL<11619> A_IWL<11618> A_IWL<11617> A_IWL<11616> A_IWL<11615> A_IWL<11614> A_IWL<11613> A_IWL<11612> A_IWL<11611> A_IWL<11610> A_IWL<11609> A_IWL<11608> A_IWL<11607> A_IWL<11606> A_IWL<11605> A_IWL<11604> A_IWL<11603> A_IWL<11602> A_IWL<11601> A_IWL<11600> A_IWL<11599> A_IWL<11598> A_IWL<11597> A_IWL<11596> A_IWL<11595> A_IWL<11594> A_IWL<11593> A_IWL<11592> A_IWL<11591> A_IWL<11590> A_IWL<11589> A_IWL<11588> A_IWL<11587> A_IWL<11586> A_IWL<11585> A_IWL<11584> A_IWL<11583> A_IWL<11582> A_IWL<11581> A_IWL<11580> A_IWL<11579> A_IWL<11578> A_IWL<11577> A_IWL<11576> A_IWL<11575> A_IWL<11574> A_IWL<11573> A_IWL<11572> A_IWL<11571> A_IWL<11570> A_IWL<11569> A_IWL<11568> A_IWL<11567> A_IWL<11566> A_IWL<11565> A_IWL<11564> A_IWL<11563> A_IWL<11562> A_IWL<11561> A_IWL<11560> A_IWL<11559> A_IWL<11558> A_IWL<11557> A_IWL<11556> A_IWL<11555> A_IWL<11554> A_IWL<11553> A_IWL<11552> A_IWL<11551> A_IWL<11550> A_IWL<11549> A_IWL<11548> A_IWL<11547> A_IWL<11546> A_IWL<11545> A_IWL<11544> A_IWL<11543> A_IWL<11542> A_IWL<11541> A_IWL<11540> A_IWL<11539> A_IWL<11538> A_IWL<11537> A_IWL<11536> A_IWL<11535> A_IWL<11534> A_IWL<11533> A_IWL<11532> A_IWL<11531> A_IWL<11530> A_IWL<11529> A_IWL<11528> A_IWL<11527> A_IWL<11526> A_IWL<11525> A_IWL<11524> A_IWL<11523> A_IWL<11522> A_IWL<11521> A_IWL<11520> A_IWL<11519> A_IWL<11518> A_IWL<11517> A_IWL<11516> A_IWL<11515> A_IWL<11514> A_IWL<11513> A_IWL<11512> A_IWL<11511> A_IWL<11510> A_IWL<11509> A_IWL<11508> A_IWL<11507> A_IWL<11506> A_IWL<11505> A_IWL<11504> A_IWL<11503> A_IWL<11502> A_IWL<11501> A_IWL<11500> A_IWL<11499> A_IWL<11498> A_IWL<11497> A_IWL<11496> A_IWL<11495> A_IWL<11494> A_IWL<11493> A_IWL<11492> A_IWL<11491> A_IWL<11490> A_IWL<11489> A_IWL<11488> A_IWL<11487> A_IWL<11486> A_IWL<11485> A_IWL<11484> A_IWL<11483> A_IWL<11482> A_IWL<11481> A_IWL<11480> A_IWL<11479> A_IWL<11478> A_IWL<11477> A_IWL<11476> A_IWL<11475> A_IWL<11474> A_IWL<11473> A_IWL<11472> A_IWL<11471> A_IWL<11470> A_IWL<11469> A_IWL<11468> A_IWL<11467> A_IWL<11466> A_IWL<11465> A_IWL<11464> A_IWL<11463> A_IWL<11462> A_IWL<11461> A_IWL<11460> A_IWL<11459> A_IWL<11458> A_IWL<11457> A_IWL<11456> A_IWL<11455> A_IWL<11454> A_IWL<11453> A_IWL<11452> A_IWL<11451> A_IWL<11450> A_IWL<11449> A_IWL<11448> A_IWL<11447> A_IWL<11446> A_IWL<11445> A_IWL<11444> A_IWL<11443> A_IWL<11442> A_IWL<11441> A_IWL<11440> A_IWL<11439> A_IWL<11438> A_IWL<11437> A_IWL<11436> A_IWL<11435> A_IWL<11434> A_IWL<11433> A_IWL<11432> A_IWL<11431> A_IWL<11430> A_IWL<11429> A_IWL<11428> A_IWL<11427> A_IWL<11426> A_IWL<11425> A_IWL<11424> A_IWL<11423> A_IWL<11422> A_IWL<11421> A_IWL<11420> A_IWL<11419> A_IWL<11418> A_IWL<11417> A_IWL<11416> A_IWL<11415> A_IWL<11414> A_IWL<11413> A_IWL<11412> A_IWL<11411> A_IWL<11410> A_IWL<11409> A_IWL<11408> A_IWL<11407> A_IWL<11406> A_IWL<11405> A_IWL<11404> A_IWL<11403> A_IWL<11402> A_IWL<11401> A_IWL<11400> A_IWL<11399> A_IWL<11398> A_IWL<11397> A_IWL<11396> A_IWL<11395> A_IWL<11394> A_IWL<11393> A_IWL<11392> A_IWL<11391> A_IWL<11390> A_IWL<11389> A_IWL<11388> A_IWL<11387> A_IWL<11386> A_IWL<11385> A_IWL<11384> A_IWL<11383> A_IWL<11382> A_IWL<11381> A_IWL<11380> A_IWL<11379> A_IWL<11378> A_IWL<11377> A_IWL<11376> A_IWL<11375> A_IWL<11374> A_IWL<11373> A_IWL<11372> A_IWL<11371> A_IWL<11370> A_IWL<11369> A_IWL<11368> A_IWL<11367> A_IWL<11366> A_IWL<11365> A_IWL<11364> A_IWL<11363> A_IWL<11362> A_IWL<11361> A_IWL<11360> A_IWL<11359> A_IWL<11358> A_IWL<11357> A_IWL<11356> A_IWL<11355> A_IWL<11354> A_IWL<11353> A_IWL<11352> A_IWL<11351> A_IWL<11350> A_IWL<11349> A_IWL<11348> A_IWL<11347> A_IWL<11346> A_IWL<11345> A_IWL<11344> A_IWL<11343> A_IWL<11342> A_IWL<11341> A_IWL<11340> A_IWL<11339> A_IWL<11338> A_IWL<11337> A_IWL<11336> A_IWL<11335> A_IWL<11334> A_IWL<11333> A_IWL<11332> A_IWL<11331> A_IWL<11330> A_IWL<11329> A_IWL<11328> A_IWL<11327> A_IWL<11326> A_IWL<11325> A_IWL<11324> A_IWL<11323> A_IWL<11322> A_IWL<11321> A_IWL<11320> A_IWL<11319> A_IWL<11318> A_IWL<11317> A_IWL<11316> A_IWL<11315> A_IWL<11314> A_IWL<11313> A_IWL<11312> A_IWL<11311> A_IWL<11310> A_IWL<11309> A_IWL<11308> A_IWL<11307> A_IWL<11306> A_IWL<11305> A_IWL<11304> A_IWL<11303> A_IWL<11302> A_IWL<11301> A_IWL<11300> A_IWL<11299> A_IWL<11298> A_IWL<11297> A_IWL<11296> A_IWL<11295> A_IWL<11294> A_IWL<11293> A_IWL<11292> A_IWL<11291> A_IWL<11290> A_IWL<11289> A_IWL<11288> A_IWL<11287> A_IWL<11286> A_IWL<11285> A_IWL<11284> A_IWL<11283> A_IWL<11282> A_IWL<11281> A_IWL<11280> A_IWL<11279> A_IWL<11278> A_IWL<11277> A_IWL<11276> A_IWL<11275> A_IWL<11274> A_IWL<11273> A_IWL<11272> A_IWL<11271> A_IWL<11270> A_IWL<11269> A_IWL<11268> A_IWL<11267> A_IWL<11266> A_IWL<11265> A_IWL<11264> A_IWL<12287> A_IWL<12286> A_IWL<12285> A_IWL<12284> A_IWL<12283> A_IWL<12282> A_IWL<12281> A_IWL<12280> A_IWL<12279> A_IWL<12278> A_IWL<12277> A_IWL<12276> A_IWL<12275> A_IWL<12274> A_IWL<12273> A_IWL<12272> A_IWL<12271> A_IWL<12270> A_IWL<12269> A_IWL<12268> A_IWL<12267> A_IWL<12266> A_IWL<12265> A_IWL<12264> A_IWL<12263> A_IWL<12262> A_IWL<12261> A_IWL<12260> A_IWL<12259> A_IWL<12258> A_IWL<12257> A_IWL<12256> A_IWL<12255> A_IWL<12254> A_IWL<12253> A_IWL<12252> A_IWL<12251> A_IWL<12250> A_IWL<12249> A_IWL<12248> A_IWL<12247> A_IWL<12246> A_IWL<12245> A_IWL<12244> A_IWL<12243> A_IWL<12242> A_IWL<12241> A_IWL<12240> A_IWL<12239> A_IWL<12238> A_IWL<12237> A_IWL<12236> A_IWL<12235> A_IWL<12234> A_IWL<12233> A_IWL<12232> A_IWL<12231> A_IWL<12230> A_IWL<12229> A_IWL<12228> A_IWL<12227> A_IWL<12226> A_IWL<12225> A_IWL<12224> A_IWL<12223> A_IWL<12222> A_IWL<12221> A_IWL<12220> A_IWL<12219> A_IWL<12218> A_IWL<12217> A_IWL<12216> A_IWL<12215> A_IWL<12214> A_IWL<12213> A_IWL<12212> A_IWL<12211> A_IWL<12210> A_IWL<12209> A_IWL<12208> A_IWL<12207> A_IWL<12206> A_IWL<12205> A_IWL<12204> A_IWL<12203> A_IWL<12202> A_IWL<12201> A_IWL<12200> A_IWL<12199> A_IWL<12198> A_IWL<12197> A_IWL<12196> A_IWL<12195> A_IWL<12194> A_IWL<12193> A_IWL<12192> A_IWL<12191> A_IWL<12190> A_IWL<12189> A_IWL<12188> A_IWL<12187> A_IWL<12186> A_IWL<12185> A_IWL<12184> A_IWL<12183> A_IWL<12182> A_IWL<12181> A_IWL<12180> A_IWL<12179> A_IWL<12178> A_IWL<12177> A_IWL<12176> A_IWL<12175> A_IWL<12174> A_IWL<12173> A_IWL<12172> A_IWL<12171> A_IWL<12170> A_IWL<12169> A_IWL<12168> A_IWL<12167> A_IWL<12166> A_IWL<12165> A_IWL<12164> A_IWL<12163> A_IWL<12162> A_IWL<12161> A_IWL<12160> A_IWL<12159> A_IWL<12158> A_IWL<12157> A_IWL<12156> A_IWL<12155> A_IWL<12154> A_IWL<12153> A_IWL<12152> A_IWL<12151> A_IWL<12150> A_IWL<12149> A_IWL<12148> A_IWL<12147> A_IWL<12146> A_IWL<12145> A_IWL<12144> A_IWL<12143> A_IWL<12142> A_IWL<12141> A_IWL<12140> A_IWL<12139> A_IWL<12138> A_IWL<12137> A_IWL<12136> A_IWL<12135> A_IWL<12134> A_IWL<12133> A_IWL<12132> A_IWL<12131> A_IWL<12130> A_IWL<12129> A_IWL<12128> A_IWL<12127> A_IWL<12126> A_IWL<12125> A_IWL<12124> A_IWL<12123> A_IWL<12122> A_IWL<12121> A_IWL<12120> A_IWL<12119> A_IWL<12118> A_IWL<12117> A_IWL<12116> A_IWL<12115> A_IWL<12114> A_IWL<12113> A_IWL<12112> A_IWL<12111> A_IWL<12110> A_IWL<12109> A_IWL<12108> A_IWL<12107> A_IWL<12106> A_IWL<12105> A_IWL<12104> A_IWL<12103> A_IWL<12102> A_IWL<12101> A_IWL<12100> A_IWL<12099> A_IWL<12098> A_IWL<12097> A_IWL<12096> A_IWL<12095> A_IWL<12094> A_IWL<12093> A_IWL<12092> A_IWL<12091> A_IWL<12090> A_IWL<12089> A_IWL<12088> A_IWL<12087> A_IWL<12086> A_IWL<12085> A_IWL<12084> A_IWL<12083> A_IWL<12082> A_IWL<12081> A_IWL<12080> A_IWL<12079> A_IWL<12078> A_IWL<12077> A_IWL<12076> A_IWL<12075> A_IWL<12074> A_IWL<12073> A_IWL<12072> A_IWL<12071> A_IWL<12070> A_IWL<12069> A_IWL<12068> A_IWL<12067> A_IWL<12066> A_IWL<12065> A_IWL<12064> A_IWL<12063> A_IWL<12062> A_IWL<12061> A_IWL<12060> A_IWL<12059> A_IWL<12058> A_IWL<12057> A_IWL<12056> A_IWL<12055> A_IWL<12054> A_IWL<12053> A_IWL<12052> A_IWL<12051> A_IWL<12050> A_IWL<12049> A_IWL<12048> A_IWL<12047> A_IWL<12046> A_IWL<12045> A_IWL<12044> A_IWL<12043> A_IWL<12042> A_IWL<12041> A_IWL<12040> A_IWL<12039> A_IWL<12038> A_IWL<12037> A_IWL<12036> A_IWL<12035> A_IWL<12034> A_IWL<12033> A_IWL<12032> A_IWL<12031> A_IWL<12030> A_IWL<12029> A_IWL<12028> A_IWL<12027> A_IWL<12026> A_IWL<12025> A_IWL<12024> A_IWL<12023> A_IWL<12022> A_IWL<12021> A_IWL<12020> A_IWL<12019> A_IWL<12018> A_IWL<12017> A_IWL<12016> A_IWL<12015> A_IWL<12014> A_IWL<12013> A_IWL<12012> A_IWL<12011> A_IWL<12010> A_IWL<12009> A_IWL<12008> A_IWL<12007> A_IWL<12006> A_IWL<12005> A_IWL<12004> A_IWL<12003> A_IWL<12002> A_IWL<12001> A_IWL<12000> A_IWL<11999> A_IWL<11998> A_IWL<11997> A_IWL<11996> A_IWL<11995> A_IWL<11994> A_IWL<11993> A_IWL<11992> A_IWL<11991> A_IWL<11990> A_IWL<11989> A_IWL<11988> A_IWL<11987> A_IWL<11986> A_IWL<11985> A_IWL<11984> A_IWL<11983> A_IWL<11982> A_IWL<11981> A_IWL<11980> A_IWL<11979> A_IWL<11978> A_IWL<11977> A_IWL<11976> A_IWL<11975> A_IWL<11974> A_IWL<11973> A_IWL<11972> A_IWL<11971> A_IWL<11970> A_IWL<11969> A_IWL<11968> A_IWL<11967> A_IWL<11966> A_IWL<11965> A_IWL<11964> A_IWL<11963> A_IWL<11962> A_IWL<11961> A_IWL<11960> A_IWL<11959> A_IWL<11958> A_IWL<11957> A_IWL<11956> A_IWL<11955> A_IWL<11954> A_IWL<11953> A_IWL<11952> A_IWL<11951> A_IWL<11950> A_IWL<11949> A_IWL<11948> A_IWL<11947> A_IWL<11946> A_IWL<11945> A_IWL<11944> A_IWL<11943> A_IWL<11942> A_IWL<11941> A_IWL<11940> A_IWL<11939> A_IWL<11938> A_IWL<11937> A_IWL<11936> A_IWL<11935> A_IWL<11934> A_IWL<11933> A_IWL<11932> A_IWL<11931> A_IWL<11930> A_IWL<11929> A_IWL<11928> A_IWL<11927> A_IWL<11926> A_IWL<11925> A_IWL<11924> A_IWL<11923> A_IWL<11922> A_IWL<11921> A_IWL<11920> A_IWL<11919> A_IWL<11918> A_IWL<11917> A_IWL<11916> A_IWL<11915> A_IWL<11914> A_IWL<11913> A_IWL<11912> A_IWL<11911> A_IWL<11910> A_IWL<11909> A_IWL<11908> A_IWL<11907> A_IWL<11906> A_IWL<11905> A_IWL<11904> A_IWL<11903> A_IWL<11902> A_IWL<11901> A_IWL<11900> A_IWL<11899> A_IWL<11898> A_IWL<11897> A_IWL<11896> A_IWL<11895> A_IWL<11894> A_IWL<11893> A_IWL<11892> A_IWL<11891> A_IWL<11890> A_IWL<11889> A_IWL<11888> A_IWL<11887> A_IWL<11886> A_IWL<11885> A_IWL<11884> A_IWL<11883> A_IWL<11882> A_IWL<11881> A_IWL<11880> A_IWL<11879> A_IWL<11878> A_IWL<11877> A_IWL<11876> A_IWL<11875> A_IWL<11874> A_IWL<11873> A_IWL<11872> A_IWL<11871> A_IWL<11870> A_IWL<11869> A_IWL<11868> A_IWL<11867> A_IWL<11866> A_IWL<11865> A_IWL<11864> A_IWL<11863> A_IWL<11862> A_IWL<11861> A_IWL<11860> A_IWL<11859> A_IWL<11858> A_IWL<11857> A_IWL<11856> A_IWL<11855> A_IWL<11854> A_IWL<11853> A_IWL<11852> A_IWL<11851> A_IWL<11850> A_IWL<11849> A_IWL<11848> A_IWL<11847> A_IWL<11846> A_IWL<11845> A_IWL<11844> A_IWL<11843> A_IWL<11842> A_IWL<11841> A_IWL<11840> A_IWL<11839> A_IWL<11838> A_IWL<11837> A_IWL<11836> A_IWL<11835> A_IWL<11834> A_IWL<11833> A_IWL<11832> A_IWL<11831> A_IWL<11830> A_IWL<11829> A_IWL<11828> A_IWL<11827> A_IWL<11826> A_IWL<11825> A_IWL<11824> A_IWL<11823> A_IWL<11822> A_IWL<11821> A_IWL<11820> A_IWL<11819> A_IWL<11818> A_IWL<11817> A_IWL<11816> A_IWL<11815> A_IWL<11814> A_IWL<11813> A_IWL<11812> A_IWL<11811> A_IWL<11810> A_IWL<11809> A_IWL<11808> A_IWL<11807> A_IWL<11806> A_IWL<11805> A_IWL<11804> A_IWL<11803> A_IWL<11802> A_IWL<11801> A_IWL<11800> A_IWL<11799> A_IWL<11798> A_IWL<11797> A_IWL<11796> A_IWL<11795> A_IWL<11794> A_IWL<11793> A_IWL<11792> A_IWL<11791> A_IWL<11790> A_IWL<11789> A_IWL<11788> A_IWL<11787> A_IWL<11786> A_IWL<11785> A_IWL<11784> A_IWL<11783> A_IWL<11782> A_IWL<11781> A_IWL<11780> A_IWL<11779> A_IWL<11778> A_IWL<11777> A_IWL<11776> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0
+XCOL<22> A_BLC<45> A_BLC<44> A_BLC_TOP<45> A_BLC_TOP<44> A_BLT<45> A_BLT<44> A_BLT_TOP<45> A_BLT_TOP<44> A_IWL<11263> A_IWL<11262> A_IWL<11261> A_IWL<11260> A_IWL<11259> A_IWL<11258> A_IWL<11257> A_IWL<11256> A_IWL<11255> A_IWL<11254> A_IWL<11253> A_IWL<11252> A_IWL<11251> A_IWL<11250> A_IWL<11249> A_IWL<11248> A_IWL<11247> A_IWL<11246> A_IWL<11245> A_IWL<11244> A_IWL<11243> A_IWL<11242> A_IWL<11241> A_IWL<11240> A_IWL<11239> A_IWL<11238> A_IWL<11237> A_IWL<11236> A_IWL<11235> A_IWL<11234> A_IWL<11233> A_IWL<11232> A_IWL<11231> A_IWL<11230> A_IWL<11229> A_IWL<11228> A_IWL<11227> A_IWL<11226> A_IWL<11225> A_IWL<11224> A_IWL<11223> A_IWL<11222> A_IWL<11221> A_IWL<11220> A_IWL<11219> A_IWL<11218> A_IWL<11217> A_IWL<11216> A_IWL<11215> A_IWL<11214> A_IWL<11213> A_IWL<11212> A_IWL<11211> A_IWL<11210> A_IWL<11209> A_IWL<11208> A_IWL<11207> A_IWL<11206> A_IWL<11205> A_IWL<11204> A_IWL<11203> A_IWL<11202> A_IWL<11201> A_IWL<11200> A_IWL<11199> A_IWL<11198> A_IWL<11197> A_IWL<11196> A_IWL<11195> A_IWL<11194> A_IWL<11193> A_IWL<11192> A_IWL<11191> A_IWL<11190> A_IWL<11189> A_IWL<11188> A_IWL<11187> A_IWL<11186> A_IWL<11185> A_IWL<11184> A_IWL<11183> A_IWL<11182> A_IWL<11181> A_IWL<11180> A_IWL<11179> A_IWL<11178> A_IWL<11177> A_IWL<11176> A_IWL<11175> A_IWL<11174> A_IWL<11173> A_IWL<11172> A_IWL<11171> A_IWL<11170> A_IWL<11169> A_IWL<11168> A_IWL<11167> A_IWL<11166> A_IWL<11165> A_IWL<11164> A_IWL<11163> A_IWL<11162> A_IWL<11161> A_IWL<11160> A_IWL<11159> A_IWL<11158> A_IWL<11157> A_IWL<11156> A_IWL<11155> A_IWL<11154> A_IWL<11153> A_IWL<11152> A_IWL<11151> A_IWL<11150> A_IWL<11149> A_IWL<11148> A_IWL<11147> A_IWL<11146> A_IWL<11145> A_IWL<11144> A_IWL<11143> A_IWL<11142> A_IWL<11141> A_IWL<11140> A_IWL<11139> A_IWL<11138> A_IWL<11137> A_IWL<11136> A_IWL<11135> A_IWL<11134> A_IWL<11133> A_IWL<11132> A_IWL<11131> A_IWL<11130> A_IWL<11129> A_IWL<11128> A_IWL<11127> A_IWL<11126> A_IWL<11125> A_IWL<11124> A_IWL<11123> A_IWL<11122> A_IWL<11121> A_IWL<11120> A_IWL<11119> A_IWL<11118> A_IWL<11117> A_IWL<11116> A_IWL<11115> A_IWL<11114> A_IWL<11113> A_IWL<11112> A_IWL<11111> A_IWL<11110> A_IWL<11109> A_IWL<11108> A_IWL<11107> A_IWL<11106> A_IWL<11105> A_IWL<11104> A_IWL<11103> A_IWL<11102> A_IWL<11101> A_IWL<11100> A_IWL<11099> A_IWL<11098> A_IWL<11097> A_IWL<11096> A_IWL<11095> A_IWL<11094> A_IWL<11093> A_IWL<11092> A_IWL<11091> A_IWL<11090> A_IWL<11089> A_IWL<11088> A_IWL<11087> A_IWL<11086> A_IWL<11085> A_IWL<11084> A_IWL<11083> A_IWL<11082> A_IWL<11081> A_IWL<11080> A_IWL<11079> A_IWL<11078> A_IWL<11077> A_IWL<11076> A_IWL<11075> A_IWL<11074> A_IWL<11073> A_IWL<11072> A_IWL<11071> A_IWL<11070> A_IWL<11069> A_IWL<11068> A_IWL<11067> A_IWL<11066> A_IWL<11065> A_IWL<11064> A_IWL<11063> A_IWL<11062> A_IWL<11061> A_IWL<11060> A_IWL<11059> A_IWL<11058> A_IWL<11057> A_IWL<11056> A_IWL<11055> A_IWL<11054> A_IWL<11053> A_IWL<11052> A_IWL<11051> A_IWL<11050> A_IWL<11049> A_IWL<11048> A_IWL<11047> A_IWL<11046> A_IWL<11045> A_IWL<11044> A_IWL<11043> A_IWL<11042> A_IWL<11041> A_IWL<11040> A_IWL<11039> A_IWL<11038> A_IWL<11037> A_IWL<11036> A_IWL<11035> A_IWL<11034> A_IWL<11033> A_IWL<11032> A_IWL<11031> A_IWL<11030> A_IWL<11029> A_IWL<11028> A_IWL<11027> A_IWL<11026> A_IWL<11025> A_IWL<11024> A_IWL<11023> A_IWL<11022> A_IWL<11021> A_IWL<11020> A_IWL<11019> A_IWL<11018> A_IWL<11017> A_IWL<11016> A_IWL<11015> A_IWL<11014> A_IWL<11013> A_IWL<11012> A_IWL<11011> A_IWL<11010> A_IWL<11009> A_IWL<11008> A_IWL<11007> A_IWL<11006> A_IWL<11005> A_IWL<11004> A_IWL<11003> A_IWL<11002> A_IWL<11001> A_IWL<11000> A_IWL<10999> A_IWL<10998> A_IWL<10997> A_IWL<10996> A_IWL<10995> A_IWL<10994> A_IWL<10993> A_IWL<10992> A_IWL<10991> A_IWL<10990> A_IWL<10989> A_IWL<10988> A_IWL<10987> A_IWL<10986> A_IWL<10985> A_IWL<10984> A_IWL<10983> A_IWL<10982> A_IWL<10981> A_IWL<10980> A_IWL<10979> A_IWL<10978> A_IWL<10977> A_IWL<10976> A_IWL<10975> A_IWL<10974> A_IWL<10973> A_IWL<10972> A_IWL<10971> A_IWL<10970> A_IWL<10969> A_IWL<10968> A_IWL<10967> A_IWL<10966> A_IWL<10965> A_IWL<10964> A_IWL<10963> A_IWL<10962> A_IWL<10961> A_IWL<10960> A_IWL<10959> A_IWL<10958> A_IWL<10957> A_IWL<10956> A_IWL<10955> A_IWL<10954> A_IWL<10953> A_IWL<10952> A_IWL<10951> A_IWL<10950> A_IWL<10949> A_IWL<10948> A_IWL<10947> A_IWL<10946> A_IWL<10945> A_IWL<10944> A_IWL<10943> A_IWL<10942> A_IWL<10941> A_IWL<10940> A_IWL<10939> A_IWL<10938> A_IWL<10937> A_IWL<10936> A_IWL<10935> A_IWL<10934> A_IWL<10933> A_IWL<10932> A_IWL<10931> A_IWL<10930> A_IWL<10929> A_IWL<10928> A_IWL<10927> A_IWL<10926> A_IWL<10925> A_IWL<10924> A_IWL<10923> A_IWL<10922> A_IWL<10921> A_IWL<10920> A_IWL<10919> A_IWL<10918> A_IWL<10917> A_IWL<10916> A_IWL<10915> A_IWL<10914> A_IWL<10913> A_IWL<10912> A_IWL<10911> A_IWL<10910> A_IWL<10909> A_IWL<10908> A_IWL<10907> A_IWL<10906> A_IWL<10905> A_IWL<10904> A_IWL<10903> A_IWL<10902> A_IWL<10901> A_IWL<10900> A_IWL<10899> A_IWL<10898> A_IWL<10897> A_IWL<10896> A_IWL<10895> A_IWL<10894> A_IWL<10893> A_IWL<10892> A_IWL<10891> A_IWL<10890> A_IWL<10889> A_IWL<10888> A_IWL<10887> A_IWL<10886> A_IWL<10885> A_IWL<10884> A_IWL<10883> A_IWL<10882> A_IWL<10881> A_IWL<10880> A_IWL<10879> A_IWL<10878> A_IWL<10877> A_IWL<10876> A_IWL<10875> A_IWL<10874> A_IWL<10873> A_IWL<10872> A_IWL<10871> A_IWL<10870> A_IWL<10869> A_IWL<10868> A_IWL<10867> A_IWL<10866> A_IWL<10865> A_IWL<10864> A_IWL<10863> A_IWL<10862> A_IWL<10861> A_IWL<10860> A_IWL<10859> A_IWL<10858> A_IWL<10857> A_IWL<10856> A_IWL<10855> A_IWL<10854> A_IWL<10853> A_IWL<10852> A_IWL<10851> A_IWL<10850> A_IWL<10849> A_IWL<10848> A_IWL<10847> A_IWL<10846> A_IWL<10845> A_IWL<10844> A_IWL<10843> A_IWL<10842> A_IWL<10841> A_IWL<10840> A_IWL<10839> A_IWL<10838> A_IWL<10837> A_IWL<10836> A_IWL<10835> A_IWL<10834> A_IWL<10833> A_IWL<10832> A_IWL<10831> A_IWL<10830> A_IWL<10829> A_IWL<10828> A_IWL<10827> A_IWL<10826> A_IWL<10825> A_IWL<10824> A_IWL<10823> A_IWL<10822> A_IWL<10821> A_IWL<10820> A_IWL<10819> A_IWL<10818> A_IWL<10817> A_IWL<10816> A_IWL<10815> A_IWL<10814> A_IWL<10813> A_IWL<10812> A_IWL<10811> A_IWL<10810> A_IWL<10809> A_IWL<10808> A_IWL<10807> A_IWL<10806> A_IWL<10805> A_IWL<10804> A_IWL<10803> A_IWL<10802> A_IWL<10801> A_IWL<10800> A_IWL<10799> A_IWL<10798> A_IWL<10797> A_IWL<10796> A_IWL<10795> A_IWL<10794> A_IWL<10793> A_IWL<10792> A_IWL<10791> A_IWL<10790> A_IWL<10789> A_IWL<10788> A_IWL<10787> A_IWL<10786> A_IWL<10785> A_IWL<10784> A_IWL<10783> A_IWL<10782> A_IWL<10781> A_IWL<10780> A_IWL<10779> A_IWL<10778> A_IWL<10777> A_IWL<10776> A_IWL<10775> A_IWL<10774> A_IWL<10773> A_IWL<10772> A_IWL<10771> A_IWL<10770> A_IWL<10769> A_IWL<10768> A_IWL<10767> A_IWL<10766> A_IWL<10765> A_IWL<10764> A_IWL<10763> A_IWL<10762> A_IWL<10761> A_IWL<10760> A_IWL<10759> A_IWL<10758> A_IWL<10757> A_IWL<10756> A_IWL<10755> A_IWL<10754> A_IWL<10753> A_IWL<10752> A_IWL<11775> A_IWL<11774> A_IWL<11773> A_IWL<11772> A_IWL<11771> A_IWL<11770> A_IWL<11769> A_IWL<11768> A_IWL<11767> A_IWL<11766> A_IWL<11765> A_IWL<11764> A_IWL<11763> A_IWL<11762> A_IWL<11761> A_IWL<11760> A_IWL<11759> A_IWL<11758> A_IWL<11757> A_IWL<11756> A_IWL<11755> A_IWL<11754> A_IWL<11753> A_IWL<11752> A_IWL<11751> A_IWL<11750> A_IWL<11749> A_IWL<11748> A_IWL<11747> A_IWL<11746> A_IWL<11745> A_IWL<11744> A_IWL<11743> A_IWL<11742> A_IWL<11741> A_IWL<11740> A_IWL<11739> A_IWL<11738> A_IWL<11737> A_IWL<11736> A_IWL<11735> A_IWL<11734> A_IWL<11733> A_IWL<11732> A_IWL<11731> A_IWL<11730> A_IWL<11729> A_IWL<11728> A_IWL<11727> A_IWL<11726> A_IWL<11725> A_IWL<11724> A_IWL<11723> A_IWL<11722> A_IWL<11721> A_IWL<11720> A_IWL<11719> A_IWL<11718> A_IWL<11717> A_IWL<11716> A_IWL<11715> A_IWL<11714> A_IWL<11713> A_IWL<11712> A_IWL<11711> A_IWL<11710> A_IWL<11709> A_IWL<11708> A_IWL<11707> A_IWL<11706> A_IWL<11705> A_IWL<11704> A_IWL<11703> A_IWL<11702> A_IWL<11701> A_IWL<11700> A_IWL<11699> A_IWL<11698> A_IWL<11697> A_IWL<11696> A_IWL<11695> A_IWL<11694> A_IWL<11693> A_IWL<11692> A_IWL<11691> A_IWL<11690> A_IWL<11689> A_IWL<11688> A_IWL<11687> A_IWL<11686> A_IWL<11685> A_IWL<11684> A_IWL<11683> A_IWL<11682> A_IWL<11681> A_IWL<11680> A_IWL<11679> A_IWL<11678> A_IWL<11677> A_IWL<11676> A_IWL<11675> A_IWL<11674> A_IWL<11673> A_IWL<11672> A_IWL<11671> A_IWL<11670> A_IWL<11669> A_IWL<11668> A_IWL<11667> A_IWL<11666> A_IWL<11665> A_IWL<11664> A_IWL<11663> A_IWL<11662> A_IWL<11661> A_IWL<11660> A_IWL<11659> A_IWL<11658> A_IWL<11657> A_IWL<11656> A_IWL<11655> A_IWL<11654> A_IWL<11653> A_IWL<11652> A_IWL<11651> A_IWL<11650> A_IWL<11649> A_IWL<11648> A_IWL<11647> A_IWL<11646> A_IWL<11645> A_IWL<11644> A_IWL<11643> A_IWL<11642> A_IWL<11641> A_IWL<11640> A_IWL<11639> A_IWL<11638> A_IWL<11637> A_IWL<11636> A_IWL<11635> A_IWL<11634> A_IWL<11633> A_IWL<11632> A_IWL<11631> A_IWL<11630> A_IWL<11629> A_IWL<11628> A_IWL<11627> A_IWL<11626> A_IWL<11625> A_IWL<11624> A_IWL<11623> A_IWL<11622> A_IWL<11621> A_IWL<11620> A_IWL<11619> A_IWL<11618> A_IWL<11617> A_IWL<11616> A_IWL<11615> A_IWL<11614> A_IWL<11613> A_IWL<11612> A_IWL<11611> A_IWL<11610> A_IWL<11609> A_IWL<11608> A_IWL<11607> A_IWL<11606> A_IWL<11605> A_IWL<11604> A_IWL<11603> A_IWL<11602> A_IWL<11601> A_IWL<11600> A_IWL<11599> A_IWL<11598> A_IWL<11597> A_IWL<11596> A_IWL<11595> A_IWL<11594> A_IWL<11593> A_IWL<11592> A_IWL<11591> A_IWL<11590> A_IWL<11589> A_IWL<11588> A_IWL<11587> A_IWL<11586> A_IWL<11585> A_IWL<11584> A_IWL<11583> A_IWL<11582> A_IWL<11581> A_IWL<11580> A_IWL<11579> A_IWL<11578> A_IWL<11577> A_IWL<11576> A_IWL<11575> A_IWL<11574> A_IWL<11573> A_IWL<11572> A_IWL<11571> A_IWL<11570> A_IWL<11569> A_IWL<11568> A_IWL<11567> A_IWL<11566> A_IWL<11565> A_IWL<11564> A_IWL<11563> A_IWL<11562> A_IWL<11561> A_IWL<11560> A_IWL<11559> A_IWL<11558> A_IWL<11557> A_IWL<11556> A_IWL<11555> A_IWL<11554> A_IWL<11553> A_IWL<11552> A_IWL<11551> A_IWL<11550> A_IWL<11549> A_IWL<11548> A_IWL<11547> A_IWL<11546> A_IWL<11545> A_IWL<11544> A_IWL<11543> A_IWL<11542> A_IWL<11541> A_IWL<11540> A_IWL<11539> A_IWL<11538> A_IWL<11537> A_IWL<11536> A_IWL<11535> A_IWL<11534> A_IWL<11533> A_IWL<11532> A_IWL<11531> A_IWL<11530> A_IWL<11529> A_IWL<11528> A_IWL<11527> A_IWL<11526> A_IWL<11525> A_IWL<11524> A_IWL<11523> A_IWL<11522> A_IWL<11521> A_IWL<11520> A_IWL<11519> A_IWL<11518> A_IWL<11517> A_IWL<11516> A_IWL<11515> A_IWL<11514> A_IWL<11513> A_IWL<11512> A_IWL<11511> A_IWL<11510> A_IWL<11509> A_IWL<11508> A_IWL<11507> A_IWL<11506> A_IWL<11505> A_IWL<11504> A_IWL<11503> A_IWL<11502> A_IWL<11501> A_IWL<11500> A_IWL<11499> A_IWL<11498> A_IWL<11497> A_IWL<11496> A_IWL<11495> A_IWL<11494> A_IWL<11493> A_IWL<11492> A_IWL<11491> A_IWL<11490> A_IWL<11489> A_IWL<11488> A_IWL<11487> A_IWL<11486> A_IWL<11485> A_IWL<11484> A_IWL<11483> A_IWL<11482> A_IWL<11481> A_IWL<11480> A_IWL<11479> A_IWL<11478> A_IWL<11477> A_IWL<11476> A_IWL<11475> A_IWL<11474> A_IWL<11473> A_IWL<11472> A_IWL<11471> A_IWL<11470> A_IWL<11469> A_IWL<11468> A_IWL<11467> A_IWL<11466> A_IWL<11465> A_IWL<11464> A_IWL<11463> A_IWL<11462> A_IWL<11461> A_IWL<11460> A_IWL<11459> A_IWL<11458> A_IWL<11457> A_IWL<11456> A_IWL<11455> A_IWL<11454> A_IWL<11453> A_IWL<11452> A_IWL<11451> A_IWL<11450> A_IWL<11449> A_IWL<11448> A_IWL<11447> A_IWL<11446> A_IWL<11445> A_IWL<11444> A_IWL<11443> A_IWL<11442> A_IWL<11441> A_IWL<11440> A_IWL<11439> A_IWL<11438> A_IWL<11437> A_IWL<11436> A_IWL<11435> A_IWL<11434> A_IWL<11433> A_IWL<11432> A_IWL<11431> A_IWL<11430> A_IWL<11429> A_IWL<11428> A_IWL<11427> A_IWL<11426> A_IWL<11425> A_IWL<11424> A_IWL<11423> A_IWL<11422> A_IWL<11421> A_IWL<11420> A_IWL<11419> A_IWL<11418> A_IWL<11417> A_IWL<11416> A_IWL<11415> A_IWL<11414> A_IWL<11413> A_IWL<11412> A_IWL<11411> A_IWL<11410> A_IWL<11409> A_IWL<11408> A_IWL<11407> A_IWL<11406> A_IWL<11405> A_IWL<11404> A_IWL<11403> A_IWL<11402> A_IWL<11401> A_IWL<11400> A_IWL<11399> A_IWL<11398> A_IWL<11397> A_IWL<11396> A_IWL<11395> A_IWL<11394> A_IWL<11393> A_IWL<11392> A_IWL<11391> A_IWL<11390> A_IWL<11389> A_IWL<11388> A_IWL<11387> A_IWL<11386> A_IWL<11385> A_IWL<11384> A_IWL<11383> A_IWL<11382> A_IWL<11381> A_IWL<11380> A_IWL<11379> A_IWL<11378> A_IWL<11377> A_IWL<11376> A_IWL<11375> A_IWL<11374> A_IWL<11373> A_IWL<11372> A_IWL<11371> A_IWL<11370> A_IWL<11369> A_IWL<11368> A_IWL<11367> A_IWL<11366> A_IWL<11365> A_IWL<11364> A_IWL<11363> A_IWL<11362> A_IWL<11361> A_IWL<11360> A_IWL<11359> A_IWL<11358> A_IWL<11357> A_IWL<11356> A_IWL<11355> A_IWL<11354> A_IWL<11353> A_IWL<11352> A_IWL<11351> A_IWL<11350> A_IWL<11349> A_IWL<11348> A_IWL<11347> A_IWL<11346> A_IWL<11345> A_IWL<11344> A_IWL<11343> A_IWL<11342> A_IWL<11341> A_IWL<11340> A_IWL<11339> A_IWL<11338> A_IWL<11337> A_IWL<11336> A_IWL<11335> A_IWL<11334> A_IWL<11333> A_IWL<11332> A_IWL<11331> A_IWL<11330> A_IWL<11329> A_IWL<11328> A_IWL<11327> A_IWL<11326> A_IWL<11325> A_IWL<11324> A_IWL<11323> A_IWL<11322> A_IWL<11321> A_IWL<11320> A_IWL<11319> A_IWL<11318> A_IWL<11317> A_IWL<11316> A_IWL<11315> A_IWL<11314> A_IWL<11313> A_IWL<11312> A_IWL<11311> A_IWL<11310> A_IWL<11309> A_IWL<11308> A_IWL<11307> A_IWL<11306> A_IWL<11305> A_IWL<11304> A_IWL<11303> A_IWL<11302> A_IWL<11301> A_IWL<11300> A_IWL<11299> A_IWL<11298> A_IWL<11297> A_IWL<11296> A_IWL<11295> A_IWL<11294> A_IWL<11293> A_IWL<11292> A_IWL<11291> A_IWL<11290> A_IWL<11289> A_IWL<11288> A_IWL<11287> A_IWL<11286> A_IWL<11285> A_IWL<11284> A_IWL<11283> A_IWL<11282> A_IWL<11281> A_IWL<11280> A_IWL<11279> A_IWL<11278> A_IWL<11277> A_IWL<11276> A_IWL<11275> A_IWL<11274> A_IWL<11273> A_IWL<11272> A_IWL<11271> A_IWL<11270> A_IWL<11269> A_IWL<11268> A_IWL<11267> A_IWL<11266> A_IWL<11265> A_IWL<11264> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0
+XCOL<21> A_BLC<43> A_BLC<42> A_BLC_TOP<43> A_BLC_TOP<42> A_BLT<43> A_BLT<42> A_BLT_TOP<43> A_BLT_TOP<42> A_IWL<10751> A_IWL<10750> A_IWL<10749> A_IWL<10748> A_IWL<10747> A_IWL<10746> A_IWL<10745> A_IWL<10744> A_IWL<10743> A_IWL<10742> A_IWL<10741> A_IWL<10740> A_IWL<10739> A_IWL<10738> A_IWL<10737> A_IWL<10736> A_IWL<10735> A_IWL<10734> A_IWL<10733> A_IWL<10732> A_IWL<10731> A_IWL<10730> A_IWL<10729> A_IWL<10728> A_IWL<10727> A_IWL<10726> A_IWL<10725> A_IWL<10724> A_IWL<10723> A_IWL<10722> A_IWL<10721> A_IWL<10720> A_IWL<10719> A_IWL<10718> A_IWL<10717> A_IWL<10716> A_IWL<10715> A_IWL<10714> A_IWL<10713> A_IWL<10712> A_IWL<10711> A_IWL<10710> A_IWL<10709> A_IWL<10708> A_IWL<10707> A_IWL<10706> A_IWL<10705> A_IWL<10704> A_IWL<10703> A_IWL<10702> A_IWL<10701> A_IWL<10700> A_IWL<10699> A_IWL<10698> A_IWL<10697> A_IWL<10696> A_IWL<10695> A_IWL<10694> A_IWL<10693> A_IWL<10692> A_IWL<10691> A_IWL<10690> A_IWL<10689> A_IWL<10688> A_IWL<10687> A_IWL<10686> A_IWL<10685> A_IWL<10684> A_IWL<10683> A_IWL<10682> A_IWL<10681> A_IWL<10680> A_IWL<10679> A_IWL<10678> A_IWL<10677> A_IWL<10676> A_IWL<10675> A_IWL<10674> A_IWL<10673> A_IWL<10672> A_IWL<10671> A_IWL<10670> A_IWL<10669> A_IWL<10668> A_IWL<10667> A_IWL<10666> A_IWL<10665> A_IWL<10664> A_IWL<10663> A_IWL<10662> A_IWL<10661> A_IWL<10660> A_IWL<10659> A_IWL<10658> A_IWL<10657> A_IWL<10656> A_IWL<10655> A_IWL<10654> A_IWL<10653> A_IWL<10652> A_IWL<10651> A_IWL<10650> A_IWL<10649> A_IWL<10648> A_IWL<10647> A_IWL<10646> A_IWL<10645> A_IWL<10644> A_IWL<10643> A_IWL<10642> A_IWL<10641> A_IWL<10640> A_IWL<10639> A_IWL<10638> A_IWL<10637> A_IWL<10636> A_IWL<10635> A_IWL<10634> A_IWL<10633> A_IWL<10632> A_IWL<10631> A_IWL<10630> A_IWL<10629> A_IWL<10628> A_IWL<10627> A_IWL<10626> A_IWL<10625> A_IWL<10624> A_IWL<10623> A_IWL<10622> A_IWL<10621> A_IWL<10620> A_IWL<10619> A_IWL<10618> A_IWL<10617> A_IWL<10616> A_IWL<10615> A_IWL<10614> A_IWL<10613> A_IWL<10612> A_IWL<10611> A_IWL<10610> A_IWL<10609> A_IWL<10608> A_IWL<10607> A_IWL<10606> A_IWL<10605> A_IWL<10604> A_IWL<10603> A_IWL<10602> A_IWL<10601> A_IWL<10600> A_IWL<10599> A_IWL<10598> A_IWL<10597> A_IWL<10596> A_IWL<10595> A_IWL<10594> A_IWL<10593> A_IWL<10592> A_IWL<10591> A_IWL<10590> A_IWL<10589> A_IWL<10588> A_IWL<10587> A_IWL<10586> A_IWL<10585> A_IWL<10584> A_IWL<10583> A_IWL<10582> A_IWL<10581> A_IWL<10580> A_IWL<10579> A_IWL<10578> A_IWL<10577> A_IWL<10576> A_IWL<10575> A_IWL<10574> A_IWL<10573> A_IWL<10572> A_IWL<10571> A_IWL<10570> A_IWL<10569> A_IWL<10568> A_IWL<10567> A_IWL<10566> A_IWL<10565> A_IWL<10564> A_IWL<10563> A_IWL<10562> A_IWL<10561> A_IWL<10560> A_IWL<10559> A_IWL<10558> A_IWL<10557> A_IWL<10556> A_IWL<10555> A_IWL<10554> A_IWL<10553> A_IWL<10552> A_IWL<10551> A_IWL<10550> A_IWL<10549> A_IWL<10548> A_IWL<10547> A_IWL<10546> A_IWL<10545> A_IWL<10544> A_IWL<10543> A_IWL<10542> A_IWL<10541> A_IWL<10540> A_IWL<10539> A_IWL<10538> A_IWL<10537> A_IWL<10536> A_IWL<10535> A_IWL<10534> A_IWL<10533> A_IWL<10532> A_IWL<10531> A_IWL<10530> A_IWL<10529> A_IWL<10528> A_IWL<10527> A_IWL<10526> A_IWL<10525> A_IWL<10524> A_IWL<10523> A_IWL<10522> A_IWL<10521> A_IWL<10520> A_IWL<10519> A_IWL<10518> A_IWL<10517> A_IWL<10516> A_IWL<10515> A_IWL<10514> A_IWL<10513> A_IWL<10512> A_IWL<10511> A_IWL<10510> A_IWL<10509> A_IWL<10508> A_IWL<10507> A_IWL<10506> A_IWL<10505> A_IWL<10504> A_IWL<10503> A_IWL<10502> A_IWL<10501> A_IWL<10500> A_IWL<10499> A_IWL<10498> A_IWL<10497> A_IWL<10496> A_IWL<10495> A_IWL<10494> A_IWL<10493> A_IWL<10492> A_IWL<10491> A_IWL<10490> A_IWL<10489> A_IWL<10488> A_IWL<10487> A_IWL<10486> A_IWL<10485> A_IWL<10484> A_IWL<10483> A_IWL<10482> A_IWL<10481> A_IWL<10480> A_IWL<10479> A_IWL<10478> A_IWL<10477> A_IWL<10476> A_IWL<10475> A_IWL<10474> A_IWL<10473> A_IWL<10472> A_IWL<10471> A_IWL<10470> A_IWL<10469> A_IWL<10468> A_IWL<10467> A_IWL<10466> A_IWL<10465> A_IWL<10464> A_IWL<10463> A_IWL<10462> A_IWL<10461> A_IWL<10460> A_IWL<10459> A_IWL<10458> A_IWL<10457> A_IWL<10456> A_IWL<10455> A_IWL<10454> A_IWL<10453> A_IWL<10452> A_IWL<10451> A_IWL<10450> A_IWL<10449> A_IWL<10448> A_IWL<10447> A_IWL<10446> A_IWL<10445> A_IWL<10444> A_IWL<10443> A_IWL<10442> A_IWL<10441> A_IWL<10440> A_IWL<10439> A_IWL<10438> A_IWL<10437> A_IWL<10436> A_IWL<10435> A_IWL<10434> A_IWL<10433> A_IWL<10432> A_IWL<10431> A_IWL<10430> A_IWL<10429> A_IWL<10428> A_IWL<10427> A_IWL<10426> A_IWL<10425> A_IWL<10424> A_IWL<10423> A_IWL<10422> A_IWL<10421> A_IWL<10420> A_IWL<10419> A_IWL<10418> A_IWL<10417> A_IWL<10416> A_IWL<10415> A_IWL<10414> A_IWL<10413> A_IWL<10412> A_IWL<10411> A_IWL<10410> A_IWL<10409> A_IWL<10408> A_IWL<10407> A_IWL<10406> A_IWL<10405> A_IWL<10404> A_IWL<10403> A_IWL<10402> A_IWL<10401> A_IWL<10400> A_IWL<10399> A_IWL<10398> A_IWL<10397> A_IWL<10396> A_IWL<10395> A_IWL<10394> A_IWL<10393> A_IWL<10392> A_IWL<10391> A_IWL<10390> A_IWL<10389> A_IWL<10388> A_IWL<10387> A_IWL<10386> A_IWL<10385> A_IWL<10384> A_IWL<10383> A_IWL<10382> A_IWL<10381> A_IWL<10380> A_IWL<10379> A_IWL<10378> A_IWL<10377> A_IWL<10376> A_IWL<10375> A_IWL<10374> A_IWL<10373> A_IWL<10372> A_IWL<10371> A_IWL<10370> A_IWL<10369> A_IWL<10368> A_IWL<10367> A_IWL<10366> A_IWL<10365> A_IWL<10364> A_IWL<10363> A_IWL<10362> A_IWL<10361> A_IWL<10360> A_IWL<10359> A_IWL<10358> A_IWL<10357> A_IWL<10356> A_IWL<10355> A_IWL<10354> A_IWL<10353> A_IWL<10352> A_IWL<10351> A_IWL<10350> A_IWL<10349> A_IWL<10348> A_IWL<10347> A_IWL<10346> A_IWL<10345> A_IWL<10344> A_IWL<10343> A_IWL<10342> A_IWL<10341> A_IWL<10340> A_IWL<10339> A_IWL<10338> A_IWL<10337> A_IWL<10336> A_IWL<10335> A_IWL<10334> A_IWL<10333> A_IWL<10332> A_IWL<10331> A_IWL<10330> A_IWL<10329> A_IWL<10328> A_IWL<10327> A_IWL<10326> A_IWL<10325> A_IWL<10324> A_IWL<10323> A_IWL<10322> A_IWL<10321> A_IWL<10320> A_IWL<10319> A_IWL<10318> A_IWL<10317> A_IWL<10316> A_IWL<10315> A_IWL<10314> A_IWL<10313> A_IWL<10312> A_IWL<10311> A_IWL<10310> A_IWL<10309> A_IWL<10308> A_IWL<10307> A_IWL<10306> A_IWL<10305> A_IWL<10304> A_IWL<10303> A_IWL<10302> A_IWL<10301> A_IWL<10300> A_IWL<10299> A_IWL<10298> A_IWL<10297> A_IWL<10296> A_IWL<10295> A_IWL<10294> A_IWL<10293> A_IWL<10292> A_IWL<10291> A_IWL<10290> A_IWL<10289> A_IWL<10288> A_IWL<10287> A_IWL<10286> A_IWL<10285> A_IWL<10284> A_IWL<10283> A_IWL<10282> A_IWL<10281> A_IWL<10280> A_IWL<10279> A_IWL<10278> A_IWL<10277> A_IWL<10276> A_IWL<10275> A_IWL<10274> A_IWL<10273> A_IWL<10272> A_IWL<10271> A_IWL<10270> A_IWL<10269> A_IWL<10268> A_IWL<10267> A_IWL<10266> A_IWL<10265> A_IWL<10264> A_IWL<10263> A_IWL<10262> A_IWL<10261> A_IWL<10260> A_IWL<10259> A_IWL<10258> A_IWL<10257> A_IWL<10256> A_IWL<10255> A_IWL<10254> A_IWL<10253> A_IWL<10252> A_IWL<10251> A_IWL<10250> A_IWL<10249> A_IWL<10248> A_IWL<10247> A_IWL<10246> A_IWL<10245> A_IWL<10244> A_IWL<10243> A_IWL<10242> A_IWL<10241> A_IWL<10240> A_IWL<11263> A_IWL<11262> A_IWL<11261> A_IWL<11260> A_IWL<11259> A_IWL<11258> A_IWL<11257> A_IWL<11256> A_IWL<11255> A_IWL<11254> A_IWL<11253> A_IWL<11252> A_IWL<11251> A_IWL<11250> A_IWL<11249> A_IWL<11248> A_IWL<11247> A_IWL<11246> A_IWL<11245> A_IWL<11244> A_IWL<11243> A_IWL<11242> A_IWL<11241> A_IWL<11240> A_IWL<11239> A_IWL<11238> A_IWL<11237> A_IWL<11236> A_IWL<11235> A_IWL<11234> A_IWL<11233> A_IWL<11232> A_IWL<11231> A_IWL<11230> A_IWL<11229> A_IWL<11228> A_IWL<11227> A_IWL<11226> A_IWL<11225> A_IWL<11224> A_IWL<11223> A_IWL<11222> A_IWL<11221> A_IWL<11220> A_IWL<11219> A_IWL<11218> A_IWL<11217> A_IWL<11216> A_IWL<11215> A_IWL<11214> A_IWL<11213> A_IWL<11212> A_IWL<11211> A_IWL<11210> A_IWL<11209> A_IWL<11208> A_IWL<11207> A_IWL<11206> A_IWL<11205> A_IWL<11204> A_IWL<11203> A_IWL<11202> A_IWL<11201> A_IWL<11200> A_IWL<11199> A_IWL<11198> A_IWL<11197> A_IWL<11196> A_IWL<11195> A_IWL<11194> A_IWL<11193> A_IWL<11192> A_IWL<11191> A_IWL<11190> A_IWL<11189> A_IWL<11188> A_IWL<11187> A_IWL<11186> A_IWL<11185> A_IWL<11184> A_IWL<11183> A_IWL<11182> A_IWL<11181> A_IWL<11180> A_IWL<11179> A_IWL<11178> A_IWL<11177> A_IWL<11176> A_IWL<11175> A_IWL<11174> A_IWL<11173> A_IWL<11172> A_IWL<11171> A_IWL<11170> A_IWL<11169> A_IWL<11168> A_IWL<11167> A_IWL<11166> A_IWL<11165> A_IWL<11164> A_IWL<11163> A_IWL<11162> A_IWL<11161> A_IWL<11160> A_IWL<11159> A_IWL<11158> A_IWL<11157> A_IWL<11156> A_IWL<11155> A_IWL<11154> A_IWL<11153> A_IWL<11152> A_IWL<11151> A_IWL<11150> A_IWL<11149> A_IWL<11148> A_IWL<11147> A_IWL<11146> A_IWL<11145> A_IWL<11144> A_IWL<11143> A_IWL<11142> A_IWL<11141> A_IWL<11140> A_IWL<11139> A_IWL<11138> A_IWL<11137> A_IWL<11136> A_IWL<11135> A_IWL<11134> A_IWL<11133> A_IWL<11132> A_IWL<11131> A_IWL<11130> A_IWL<11129> A_IWL<11128> A_IWL<11127> A_IWL<11126> A_IWL<11125> A_IWL<11124> A_IWL<11123> A_IWL<11122> A_IWL<11121> A_IWL<11120> A_IWL<11119> A_IWL<11118> A_IWL<11117> A_IWL<11116> A_IWL<11115> A_IWL<11114> A_IWL<11113> A_IWL<11112> A_IWL<11111> A_IWL<11110> A_IWL<11109> A_IWL<11108> A_IWL<11107> A_IWL<11106> A_IWL<11105> A_IWL<11104> A_IWL<11103> A_IWL<11102> A_IWL<11101> A_IWL<11100> A_IWL<11099> A_IWL<11098> A_IWL<11097> A_IWL<11096> A_IWL<11095> A_IWL<11094> A_IWL<11093> A_IWL<11092> A_IWL<11091> A_IWL<11090> A_IWL<11089> A_IWL<11088> A_IWL<11087> A_IWL<11086> A_IWL<11085> A_IWL<11084> A_IWL<11083> A_IWL<11082> A_IWL<11081> A_IWL<11080> A_IWL<11079> A_IWL<11078> A_IWL<11077> A_IWL<11076> A_IWL<11075> A_IWL<11074> A_IWL<11073> A_IWL<11072> A_IWL<11071> A_IWL<11070> A_IWL<11069> A_IWL<11068> A_IWL<11067> A_IWL<11066> A_IWL<11065> A_IWL<11064> A_IWL<11063> A_IWL<11062> A_IWL<11061> A_IWL<11060> A_IWL<11059> A_IWL<11058> A_IWL<11057> A_IWL<11056> A_IWL<11055> A_IWL<11054> A_IWL<11053> A_IWL<11052> A_IWL<11051> A_IWL<11050> A_IWL<11049> A_IWL<11048> A_IWL<11047> A_IWL<11046> A_IWL<11045> A_IWL<11044> A_IWL<11043> A_IWL<11042> A_IWL<11041> A_IWL<11040> A_IWL<11039> A_IWL<11038> A_IWL<11037> A_IWL<11036> A_IWL<11035> A_IWL<11034> A_IWL<11033> A_IWL<11032> A_IWL<11031> A_IWL<11030> A_IWL<11029> A_IWL<11028> A_IWL<11027> A_IWL<11026> A_IWL<11025> A_IWL<11024> A_IWL<11023> A_IWL<11022> A_IWL<11021> A_IWL<11020> A_IWL<11019> A_IWL<11018> A_IWL<11017> A_IWL<11016> A_IWL<11015> A_IWL<11014> A_IWL<11013> A_IWL<11012> A_IWL<11011> A_IWL<11010> A_IWL<11009> A_IWL<11008> A_IWL<11007> A_IWL<11006> A_IWL<11005> A_IWL<11004> A_IWL<11003> A_IWL<11002> A_IWL<11001> A_IWL<11000> A_IWL<10999> A_IWL<10998> A_IWL<10997> A_IWL<10996> A_IWL<10995> A_IWL<10994> A_IWL<10993> A_IWL<10992> A_IWL<10991> A_IWL<10990> A_IWL<10989> A_IWL<10988> A_IWL<10987> A_IWL<10986> A_IWL<10985> A_IWL<10984> A_IWL<10983> A_IWL<10982> A_IWL<10981> A_IWL<10980> A_IWL<10979> A_IWL<10978> A_IWL<10977> A_IWL<10976> A_IWL<10975> A_IWL<10974> A_IWL<10973> A_IWL<10972> A_IWL<10971> A_IWL<10970> A_IWL<10969> A_IWL<10968> A_IWL<10967> A_IWL<10966> A_IWL<10965> A_IWL<10964> A_IWL<10963> A_IWL<10962> A_IWL<10961> A_IWL<10960> A_IWL<10959> A_IWL<10958> A_IWL<10957> A_IWL<10956> A_IWL<10955> A_IWL<10954> A_IWL<10953> A_IWL<10952> A_IWL<10951> A_IWL<10950> A_IWL<10949> A_IWL<10948> A_IWL<10947> A_IWL<10946> A_IWL<10945> A_IWL<10944> A_IWL<10943> A_IWL<10942> A_IWL<10941> A_IWL<10940> A_IWL<10939> A_IWL<10938> A_IWL<10937> A_IWL<10936> A_IWL<10935> A_IWL<10934> A_IWL<10933> A_IWL<10932> A_IWL<10931> A_IWL<10930> A_IWL<10929> A_IWL<10928> A_IWL<10927> A_IWL<10926> A_IWL<10925> A_IWL<10924> A_IWL<10923> A_IWL<10922> A_IWL<10921> A_IWL<10920> A_IWL<10919> A_IWL<10918> A_IWL<10917> A_IWL<10916> A_IWL<10915> A_IWL<10914> A_IWL<10913> A_IWL<10912> A_IWL<10911> A_IWL<10910> A_IWL<10909> A_IWL<10908> A_IWL<10907> A_IWL<10906> A_IWL<10905> A_IWL<10904> A_IWL<10903> A_IWL<10902> A_IWL<10901> A_IWL<10900> A_IWL<10899> A_IWL<10898> A_IWL<10897> A_IWL<10896> A_IWL<10895> A_IWL<10894> A_IWL<10893> A_IWL<10892> A_IWL<10891> A_IWL<10890> A_IWL<10889> A_IWL<10888> A_IWL<10887> A_IWL<10886> A_IWL<10885> A_IWL<10884> A_IWL<10883> A_IWL<10882> A_IWL<10881> A_IWL<10880> A_IWL<10879> A_IWL<10878> A_IWL<10877> A_IWL<10876> A_IWL<10875> A_IWL<10874> A_IWL<10873> A_IWL<10872> A_IWL<10871> A_IWL<10870> A_IWL<10869> A_IWL<10868> A_IWL<10867> A_IWL<10866> A_IWL<10865> A_IWL<10864> A_IWL<10863> A_IWL<10862> A_IWL<10861> A_IWL<10860> A_IWL<10859> A_IWL<10858> A_IWL<10857> A_IWL<10856> A_IWL<10855> A_IWL<10854> A_IWL<10853> A_IWL<10852> A_IWL<10851> A_IWL<10850> A_IWL<10849> A_IWL<10848> A_IWL<10847> A_IWL<10846> A_IWL<10845> A_IWL<10844> A_IWL<10843> A_IWL<10842> A_IWL<10841> A_IWL<10840> A_IWL<10839> A_IWL<10838> A_IWL<10837> A_IWL<10836> A_IWL<10835> A_IWL<10834> A_IWL<10833> A_IWL<10832> A_IWL<10831> A_IWL<10830> A_IWL<10829> A_IWL<10828> A_IWL<10827> A_IWL<10826> A_IWL<10825> A_IWL<10824> A_IWL<10823> A_IWL<10822> A_IWL<10821> A_IWL<10820> A_IWL<10819> A_IWL<10818> A_IWL<10817> A_IWL<10816> A_IWL<10815> A_IWL<10814> A_IWL<10813> A_IWL<10812> A_IWL<10811> A_IWL<10810> A_IWL<10809> A_IWL<10808> A_IWL<10807> A_IWL<10806> A_IWL<10805> A_IWL<10804> A_IWL<10803> A_IWL<10802> A_IWL<10801> A_IWL<10800> A_IWL<10799> A_IWL<10798> A_IWL<10797> A_IWL<10796> A_IWL<10795> A_IWL<10794> A_IWL<10793> A_IWL<10792> A_IWL<10791> A_IWL<10790> A_IWL<10789> A_IWL<10788> A_IWL<10787> A_IWL<10786> A_IWL<10785> A_IWL<10784> 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A_IWL<10252> A_IWL<10251> A_IWL<10250> A_IWL<10249> A_IWL<10248> A_IWL<10247> A_IWL<10246> A_IWL<10245> A_IWL<10244> A_IWL<10243> A_IWL<10242> A_IWL<10241> A_IWL<10240> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0
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A_IWL<9653> A_IWL<9652> A_IWL<9651> A_IWL<9650> A_IWL<9649> A_IWL<9648> A_IWL<9647> A_IWL<9646> A_IWL<9645> A_IWL<9644> A_IWL<9643> A_IWL<9642> A_IWL<9641> A_IWL<9640> A_IWL<9639> A_IWL<9638> A_IWL<9637> A_IWL<9636> A_IWL<9635> A_IWL<9634> A_IWL<9633> A_IWL<9632> A_IWL<9631> A_IWL<9630> A_IWL<9629> A_IWL<9628> A_IWL<9627> A_IWL<9626> A_IWL<9625> A_IWL<9624> A_IWL<9623> A_IWL<9622> A_IWL<9621> A_IWL<9620> A_IWL<9619> A_IWL<9618> A_IWL<9617> A_IWL<9616> A_IWL<9615> A_IWL<9614> A_IWL<9613> A_IWL<9612> A_IWL<9611> A_IWL<9610> A_IWL<9609> A_IWL<9608> A_IWL<9607> A_IWL<9606> A_IWL<9605> A_IWL<9604> A_IWL<9603> A_IWL<9602> A_IWL<9601> A_IWL<9600> A_IWL<9599> A_IWL<9598> A_IWL<9597> A_IWL<9596> A_IWL<9595> A_IWL<9594> A_IWL<9593> A_IWL<9592> A_IWL<9591> A_IWL<9590> A_IWL<9589> A_IWL<9588> A_IWL<9587> A_IWL<9586> A_IWL<9585> A_IWL<9584> A_IWL<9583> A_IWL<9582> A_IWL<9581> A_IWL<9580> A_IWL<9579> A_IWL<9578> A_IWL<9577> A_IWL<9576> A_IWL<9575> A_IWL<9574> A_IWL<9573> A_IWL<9572> A_IWL<9571> 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A_IWL<9321> A_IWL<9320> A_IWL<9319> A_IWL<9318> A_IWL<9317> A_IWL<9316> A_IWL<9315> A_IWL<9314> A_IWL<9313> A_IWL<9312> A_IWL<9311> A_IWL<9310> A_IWL<9309> A_IWL<9308> A_IWL<9307> A_IWL<9306> A_IWL<9305> A_IWL<9304> A_IWL<9303> A_IWL<9302> A_IWL<9301> A_IWL<9300> A_IWL<9299> A_IWL<9298> A_IWL<9297> A_IWL<9296> A_IWL<9295> A_IWL<9294> A_IWL<9293> A_IWL<9292> A_IWL<9291> A_IWL<9290> A_IWL<9289> A_IWL<9288> A_IWL<9287> A_IWL<9286> A_IWL<9285> A_IWL<9284> A_IWL<9283> A_IWL<9282> A_IWL<9281> A_IWL<9280> A_IWL<9279> A_IWL<9278> A_IWL<9277> A_IWL<9276> A_IWL<9275> A_IWL<9274> A_IWL<9273> A_IWL<9272> A_IWL<9271> A_IWL<9270> A_IWL<9269> A_IWL<9268> A_IWL<9267> A_IWL<9266> A_IWL<9265> A_IWL<9264> A_IWL<9263> A_IWL<9262> A_IWL<9261> A_IWL<9260> A_IWL<9259> A_IWL<9258> A_IWL<9257> A_IWL<9256> A_IWL<9255> A_IWL<9254> A_IWL<9253> A_IWL<9252> A_IWL<9251> A_IWL<9250> A_IWL<9249> A_IWL<9248> A_IWL<9247> A_IWL<9246> A_IWL<9245> A_IWL<9244> A_IWL<9243> A_IWL<9242> A_IWL<9241> A_IWL<9240> A_IWL<9239> A_IWL<9238> A_IWL<9237> A_IWL<9236> A_IWL<9235> A_IWL<9234> A_IWL<9233> A_IWL<9232> A_IWL<9231> A_IWL<9230> A_IWL<9229> A_IWL<9228> A_IWL<9227> A_IWL<9226> A_IWL<9225> A_IWL<9224> A_IWL<9223> A_IWL<9222> A_IWL<9221> A_IWL<9220> A_IWL<9219> A_IWL<9218> A_IWL<9217> A_IWL<9216> A_IWL<10239> A_IWL<10238> A_IWL<10237> A_IWL<10236> A_IWL<10235> A_IWL<10234> A_IWL<10233> A_IWL<10232> A_IWL<10231> A_IWL<10230> A_IWL<10229> A_IWL<10228> A_IWL<10227> A_IWL<10226> A_IWL<10225> A_IWL<10224> A_IWL<10223> A_IWL<10222> A_IWL<10221> A_IWL<10220> A_IWL<10219> A_IWL<10218> A_IWL<10217> A_IWL<10216> A_IWL<10215> A_IWL<10214> A_IWL<10213> A_IWL<10212> A_IWL<10211> A_IWL<10210> A_IWL<10209> A_IWL<10208> A_IWL<10207> A_IWL<10206> A_IWL<10205> A_IWL<10204> A_IWL<10203> A_IWL<10202> A_IWL<10201> A_IWL<10200> A_IWL<10199> A_IWL<10198> A_IWL<10197> A_IWL<10196> A_IWL<10195> A_IWL<10194> A_IWL<10193> A_IWL<10192> A_IWL<10191> A_IWL<10190> A_IWL<10189> A_IWL<10188> A_IWL<10187> A_IWL<10186> A_IWL<10185> A_IWL<10184> A_IWL<10183> A_IWL<10182> A_IWL<10181> A_IWL<10180> A_IWL<10179> A_IWL<10178> A_IWL<10177> A_IWL<10176> A_IWL<10175> A_IWL<10174> A_IWL<10173> A_IWL<10172> A_IWL<10171> A_IWL<10170> A_IWL<10169> A_IWL<10168> A_IWL<10167> A_IWL<10166> A_IWL<10165> A_IWL<10164> A_IWL<10163> A_IWL<10162> A_IWL<10161> A_IWL<10160> A_IWL<10159> A_IWL<10158> A_IWL<10157> A_IWL<10156> A_IWL<10155> A_IWL<10154> A_IWL<10153> A_IWL<10152> A_IWL<10151> A_IWL<10150> A_IWL<10149> A_IWL<10148> A_IWL<10147> A_IWL<10146> A_IWL<10145> A_IWL<10144> A_IWL<10143> A_IWL<10142> A_IWL<10141> A_IWL<10140> A_IWL<10139> A_IWL<10138> A_IWL<10137> A_IWL<10136> A_IWL<10135> A_IWL<10134> A_IWL<10133> A_IWL<10132> A_IWL<10131> A_IWL<10130> A_IWL<10129> A_IWL<10128> A_IWL<10127> A_IWL<10126> A_IWL<10125> A_IWL<10124> A_IWL<10123> A_IWL<10122> A_IWL<10121> A_IWL<10120> A_IWL<10119> A_IWL<10118> A_IWL<10117> A_IWL<10116> A_IWL<10115> A_IWL<10114> A_IWL<10113> A_IWL<10112> A_IWL<10111> A_IWL<10110> A_IWL<10109> A_IWL<10108> A_IWL<10107> A_IWL<10106> A_IWL<10105> A_IWL<10104> A_IWL<10103> A_IWL<10102> A_IWL<10101> A_IWL<10100> A_IWL<10099> A_IWL<10098> A_IWL<10097> A_IWL<10096> A_IWL<10095> A_IWL<10094> A_IWL<10093> A_IWL<10092> A_IWL<10091> A_IWL<10090> A_IWL<10089> A_IWL<10088> A_IWL<10087> A_IWL<10086> A_IWL<10085> A_IWL<10084> A_IWL<10083> A_IWL<10082> A_IWL<10081> A_IWL<10080> A_IWL<10079> A_IWL<10078> A_IWL<10077> A_IWL<10076> A_IWL<10075> A_IWL<10074> A_IWL<10073> A_IWL<10072> A_IWL<10071> A_IWL<10070> A_IWL<10069> A_IWL<10068> A_IWL<10067> A_IWL<10066> A_IWL<10065> A_IWL<10064> A_IWL<10063> A_IWL<10062> A_IWL<10061> A_IWL<10060> A_IWL<10059> A_IWL<10058> A_IWL<10057> A_IWL<10056> A_IWL<10055> A_IWL<10054> A_IWL<10053> A_IWL<10052> A_IWL<10051> A_IWL<10050> A_IWL<10049> A_IWL<10048> A_IWL<10047> A_IWL<10046> A_IWL<10045> A_IWL<10044> A_IWL<10043> A_IWL<10042> A_IWL<10041> A_IWL<10040> A_IWL<10039> A_IWL<10038> A_IWL<10037> A_IWL<10036> A_IWL<10035> A_IWL<10034> A_IWL<10033> A_IWL<10032> A_IWL<10031> A_IWL<10030> A_IWL<10029> A_IWL<10028> A_IWL<10027> A_IWL<10026> A_IWL<10025> A_IWL<10024> A_IWL<10023> A_IWL<10022> A_IWL<10021> A_IWL<10020> A_IWL<10019> A_IWL<10018> A_IWL<10017> A_IWL<10016> A_IWL<10015> A_IWL<10014> A_IWL<10013> A_IWL<10012> A_IWL<10011> A_IWL<10010> A_IWL<10009> A_IWL<10008> A_IWL<10007> A_IWL<10006> A_IWL<10005> A_IWL<10004> A_IWL<10003> A_IWL<10002> A_IWL<10001> A_IWL<10000> A_IWL<9999> A_IWL<9998> A_IWL<9997> A_IWL<9996> A_IWL<9995> A_IWL<9994> A_IWL<9993> A_IWL<9992> A_IWL<9991> A_IWL<9990> A_IWL<9989> A_IWL<9988> A_IWL<9987> A_IWL<9986> A_IWL<9985> A_IWL<9984> A_IWL<9983> A_IWL<9982> A_IWL<9981> A_IWL<9980> A_IWL<9979> A_IWL<9978> A_IWL<9977> A_IWL<9976> A_IWL<9975> A_IWL<9974> A_IWL<9973> A_IWL<9972> A_IWL<9971> A_IWL<9970> A_IWL<9969> A_IWL<9968> A_IWL<9967> A_IWL<9966> A_IWL<9965> A_IWL<9964> A_IWL<9963> A_IWL<9962> A_IWL<9961> A_IWL<9960> A_IWL<9959> A_IWL<9958> A_IWL<9957> A_IWL<9956> A_IWL<9955> A_IWL<9954> A_IWL<9953> A_IWL<9952> A_IWL<9951> A_IWL<9950> A_IWL<9949> A_IWL<9948> A_IWL<9947> A_IWL<9946> A_IWL<9945> A_IWL<9944> A_IWL<9943> A_IWL<9942> A_IWL<9941> A_IWL<9940> A_IWL<9939> A_IWL<9938> A_IWL<9937> A_IWL<9936> A_IWL<9935> A_IWL<9934> A_IWL<9933> A_IWL<9932> A_IWL<9931> A_IWL<9930> A_IWL<9929> A_IWL<9928> A_IWL<9927> A_IWL<9926> A_IWL<9925> A_IWL<9924> A_IWL<9923> A_IWL<9922> A_IWL<9921> A_IWL<9920> A_IWL<9919> A_IWL<9918> A_IWL<9917> A_IWL<9916> A_IWL<9915> A_IWL<9914> A_IWL<9913> A_IWL<9912> A_IWL<9911> A_IWL<9910> A_IWL<9909> A_IWL<9908> A_IWL<9907> A_IWL<9906> A_IWL<9905> A_IWL<9904> A_IWL<9903> A_IWL<9902> A_IWL<9901> A_IWL<9900> A_IWL<9899> A_IWL<9898> A_IWL<9897> A_IWL<9896> A_IWL<9895> A_IWL<9894> A_IWL<9893> A_IWL<9892> A_IWL<9891> A_IWL<9890> A_IWL<9889> A_IWL<9888> A_IWL<9887> A_IWL<9886> A_IWL<9885> A_IWL<9884> A_IWL<9883> A_IWL<9882> A_IWL<9881> A_IWL<9880> A_IWL<9879> A_IWL<9878> A_IWL<9877> A_IWL<9876> A_IWL<9875> A_IWL<9874> A_IWL<9873> A_IWL<9872> A_IWL<9871> A_IWL<9870> A_IWL<9869> A_IWL<9868> A_IWL<9867> A_IWL<9866> A_IWL<9865> A_IWL<9864> A_IWL<9863> A_IWL<9862> A_IWL<9861> A_IWL<9860> A_IWL<9859> A_IWL<9858> A_IWL<9857> A_IWL<9856> A_IWL<9855> A_IWL<9854> A_IWL<9853> A_IWL<9852> A_IWL<9851> A_IWL<9850> A_IWL<9849> A_IWL<9848> A_IWL<9847> A_IWL<9846> A_IWL<9845> A_IWL<9844> A_IWL<9843> A_IWL<9842> A_IWL<9841> A_IWL<9840> A_IWL<9839> A_IWL<9838> A_IWL<9837> A_IWL<9836> A_IWL<9835> A_IWL<9834> A_IWL<9833> A_IWL<9832> A_IWL<9831> A_IWL<9830> A_IWL<9829> A_IWL<9828> A_IWL<9827> A_IWL<9826> A_IWL<9825> A_IWL<9824> A_IWL<9823> A_IWL<9822> A_IWL<9821> A_IWL<9820> A_IWL<9819> A_IWL<9818> A_IWL<9817> A_IWL<9816> A_IWL<9815> A_IWL<9814> A_IWL<9813> A_IWL<9812> A_IWL<9811> A_IWL<9810> A_IWL<9809> A_IWL<9808> A_IWL<9807> A_IWL<9806> A_IWL<9805> A_IWL<9804> A_IWL<9803> A_IWL<9802> A_IWL<9801> A_IWL<9800> A_IWL<9799> A_IWL<9798> A_IWL<9797> A_IWL<9796> A_IWL<9795> A_IWL<9794> A_IWL<9793> A_IWL<9792> A_IWL<9791> A_IWL<9790> A_IWL<9789> A_IWL<9788> A_IWL<9787> A_IWL<9786> A_IWL<9785> A_IWL<9784> A_IWL<9783> A_IWL<9782> A_IWL<9781> A_IWL<9780> A_IWL<9779> A_IWL<9778> A_IWL<9777> A_IWL<9776> A_IWL<9775> A_IWL<9774> A_IWL<9773> A_IWL<9772> A_IWL<9771> A_IWL<9770> A_IWL<9769> A_IWL<9768> A_IWL<9767> A_IWL<9766> A_IWL<9765> A_IWL<9764> A_IWL<9763> A_IWL<9762> A_IWL<9761> A_IWL<9760> A_IWL<9759> A_IWL<9758> A_IWL<9757> A_IWL<9756> A_IWL<9755> A_IWL<9754> A_IWL<9753> A_IWL<9752> A_IWL<9751> A_IWL<9750> A_IWL<9749> A_IWL<9748> A_IWL<9747> A_IWL<9746> A_IWL<9745> A_IWL<9744> A_IWL<9743> A_IWL<9742> A_IWL<9741> A_IWL<9740> A_IWL<9739> A_IWL<9738> A_IWL<9737> A_IWL<9736> A_IWL<9735> A_IWL<9734> A_IWL<9733> A_IWL<9732> A_IWL<9731> A_IWL<9730> A_IWL<9729> A_IWL<9728> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0
+XCOL<18> A_BLC<37> A_BLC<36> A_BLC_TOP<37> A_BLC_TOP<36> A_BLT<37> A_BLT<36> A_BLT_TOP<37> A_BLT_TOP<36> A_IWL<9215> A_IWL<9214> A_IWL<9213> A_IWL<9212> A_IWL<9211> A_IWL<9210> A_IWL<9209> A_IWL<9208> A_IWL<9207> A_IWL<9206> A_IWL<9205> A_IWL<9204> A_IWL<9203> A_IWL<9202> A_IWL<9201> A_IWL<9200> A_IWL<9199> A_IWL<9198> A_IWL<9197> A_IWL<9196> A_IWL<9195> A_IWL<9194> A_IWL<9193> A_IWL<9192> A_IWL<9191> A_IWL<9190> A_IWL<9189> A_IWL<9188> A_IWL<9187> A_IWL<9186> A_IWL<9185> A_IWL<9184> A_IWL<9183> A_IWL<9182> A_IWL<9181> A_IWL<9180> A_IWL<9179> A_IWL<9178> A_IWL<9177> A_IWL<9176> A_IWL<9175> A_IWL<9174> A_IWL<9173> A_IWL<9172> A_IWL<9171> A_IWL<9170> A_IWL<9169> A_IWL<9168> A_IWL<9167> A_IWL<9166> A_IWL<9165> A_IWL<9164> A_IWL<9163> A_IWL<9162> A_IWL<9161> A_IWL<9160> A_IWL<9159> A_IWL<9158> A_IWL<9157> A_IWL<9156> A_IWL<9155> A_IWL<9154> A_IWL<9153> A_IWL<9152> A_IWL<9151> A_IWL<9150> A_IWL<9149> A_IWL<9148> A_IWL<9147> A_IWL<9146> A_IWL<9145> A_IWL<9144> A_IWL<9143> A_IWL<9142> A_IWL<9141> A_IWL<9140> A_IWL<9139> A_IWL<9138> A_IWL<9137> A_IWL<9136> A_IWL<9135> A_IWL<9134> A_IWL<9133> A_IWL<9132> A_IWL<9131> A_IWL<9130> A_IWL<9129> A_IWL<9128> A_IWL<9127> A_IWL<9126> A_IWL<9125> A_IWL<9124> A_IWL<9123> A_IWL<9122> A_IWL<9121> A_IWL<9120> A_IWL<9119> A_IWL<9118> A_IWL<9117> A_IWL<9116> A_IWL<9115> A_IWL<9114> A_IWL<9113> A_IWL<9112> A_IWL<9111> A_IWL<9110> A_IWL<9109> A_IWL<9108> A_IWL<9107> A_IWL<9106> A_IWL<9105> A_IWL<9104> A_IWL<9103> A_IWL<9102> A_IWL<9101> A_IWL<9100> A_IWL<9099> A_IWL<9098> A_IWL<9097> A_IWL<9096> A_IWL<9095> A_IWL<9094> A_IWL<9093> A_IWL<9092> A_IWL<9091> A_IWL<9090> A_IWL<9089> A_IWL<9088> A_IWL<9087> A_IWL<9086> A_IWL<9085> A_IWL<9084> A_IWL<9083> A_IWL<9082> A_IWL<9081> A_IWL<9080> A_IWL<9079> A_IWL<9078> A_IWL<9077> A_IWL<9076> A_IWL<9075> A_IWL<9074> A_IWL<9073> A_IWL<9072> A_IWL<9071> A_IWL<9070> A_IWL<9069> A_IWL<9068> A_IWL<9067> A_IWL<9066> A_IWL<9065> A_IWL<9064> A_IWL<9063> A_IWL<9062> A_IWL<9061> A_IWL<9060> A_IWL<9059> A_IWL<9058> A_IWL<9057> A_IWL<9056> A_IWL<9055> A_IWL<9054> A_IWL<9053> A_IWL<9052> A_IWL<9051> A_IWL<9050> A_IWL<9049> A_IWL<9048> A_IWL<9047> A_IWL<9046> A_IWL<9045> A_IWL<9044> A_IWL<9043> A_IWL<9042> A_IWL<9041> A_IWL<9040> A_IWL<9039> A_IWL<9038> A_IWL<9037> A_IWL<9036> A_IWL<9035> A_IWL<9034> A_IWL<9033> A_IWL<9032> A_IWL<9031> A_IWL<9030> A_IWL<9029> A_IWL<9028> A_IWL<9027> A_IWL<9026> A_IWL<9025> A_IWL<9024> A_IWL<9023> A_IWL<9022> A_IWL<9021> A_IWL<9020> A_IWL<9019> A_IWL<9018> A_IWL<9017> A_IWL<9016> A_IWL<9015> A_IWL<9014> A_IWL<9013> A_IWL<9012> A_IWL<9011> A_IWL<9010> A_IWL<9009> A_IWL<9008> A_IWL<9007> A_IWL<9006> A_IWL<9005> A_IWL<9004> A_IWL<9003> A_IWL<9002> A_IWL<9001> A_IWL<9000> A_IWL<8999> A_IWL<8998> A_IWL<8997> A_IWL<8996> A_IWL<8995> A_IWL<8994> A_IWL<8993> A_IWL<8992> A_IWL<8991> A_IWL<8990> A_IWL<8989> A_IWL<8988> A_IWL<8987> A_IWL<8986> A_IWL<8985> A_IWL<8984> A_IWL<8983> A_IWL<8982> A_IWL<8981> A_IWL<8980> A_IWL<8979> A_IWL<8978> A_IWL<8977> A_IWL<8976> A_IWL<8975> A_IWL<8974> A_IWL<8973> A_IWL<8972> A_IWL<8971> A_IWL<8970> A_IWL<8969> A_IWL<8968> A_IWL<8967> A_IWL<8966> A_IWL<8965> A_IWL<8964> A_IWL<8963> A_IWL<8962> A_IWL<8961> A_IWL<8960> A_IWL<8959> A_IWL<8958> A_IWL<8957> A_IWL<8956> A_IWL<8955> A_IWL<8954> A_IWL<8953> A_IWL<8952> A_IWL<8951> A_IWL<8950> A_IWL<8949> A_IWL<8948> A_IWL<8947> A_IWL<8946> A_IWL<8945> A_IWL<8944> A_IWL<8943> A_IWL<8942> A_IWL<8941> A_IWL<8940> A_IWL<8939> A_IWL<8938> A_IWL<8937> A_IWL<8936> A_IWL<8935> A_IWL<8934> A_IWL<8933> A_IWL<8932> A_IWL<8931> A_IWL<8930> A_IWL<8929> A_IWL<8928> A_IWL<8927> A_IWL<8926> A_IWL<8925> A_IWL<8924> A_IWL<8923> A_IWL<8922> A_IWL<8921> A_IWL<8920> A_IWL<8919> A_IWL<8918> A_IWL<8917> A_IWL<8916> A_IWL<8915> A_IWL<8914> A_IWL<8913> A_IWL<8912> A_IWL<8911> A_IWL<8910> A_IWL<8909> A_IWL<8908> A_IWL<8907> A_IWL<8906> A_IWL<8905> A_IWL<8904> A_IWL<8903> A_IWL<8902> A_IWL<8901> A_IWL<8900> A_IWL<8899> A_IWL<8898> A_IWL<8897> A_IWL<8896> A_IWL<8895> A_IWL<8894> A_IWL<8893> A_IWL<8892> A_IWL<8891> A_IWL<8890> A_IWL<8889> A_IWL<8888> A_IWL<8887> A_IWL<8886> A_IWL<8885> A_IWL<8884> A_IWL<8883> A_IWL<8882> A_IWL<8881> A_IWL<8880> A_IWL<8879> A_IWL<8878> A_IWL<8877> A_IWL<8876> A_IWL<8875> A_IWL<8874> A_IWL<8873> A_IWL<8872> A_IWL<8871> A_IWL<8870> A_IWL<8869> A_IWL<8868> A_IWL<8867> A_IWL<8866> A_IWL<8865> A_IWL<8864> A_IWL<8863> A_IWL<8862> A_IWL<8861> A_IWL<8860> A_IWL<8859> A_IWL<8858> A_IWL<8857> A_IWL<8856> A_IWL<8855> A_IWL<8854> A_IWL<8853> A_IWL<8852> A_IWL<8851> A_IWL<8850> A_IWL<8849> A_IWL<8848> A_IWL<8847> A_IWL<8846> A_IWL<8845> A_IWL<8844> A_IWL<8843> A_IWL<8842> A_IWL<8841> A_IWL<8840> A_IWL<8839> A_IWL<8838> A_IWL<8837> A_IWL<8836> A_IWL<8835> A_IWL<8834> A_IWL<8833> A_IWL<8832> A_IWL<8831> A_IWL<8830> A_IWL<8829> A_IWL<8828> A_IWL<8827> A_IWL<8826> A_IWL<8825> A_IWL<8824> A_IWL<8823> A_IWL<8822> A_IWL<8821> A_IWL<8820> A_IWL<8819> A_IWL<8818> A_IWL<8817> A_IWL<8816> A_IWL<8815> A_IWL<8814> A_IWL<8813> A_IWL<8812> A_IWL<8811> A_IWL<8810> A_IWL<8809> A_IWL<8808> A_IWL<8807> A_IWL<8806> A_IWL<8805> A_IWL<8804> A_IWL<8803> A_IWL<8802> A_IWL<8801> A_IWL<8800> A_IWL<8799> A_IWL<8798> A_IWL<8797> A_IWL<8796> A_IWL<8795> A_IWL<8794> A_IWL<8793> A_IWL<8792> A_IWL<8791> A_IWL<8790> A_IWL<8789> A_IWL<8788> A_IWL<8787> A_IWL<8786> A_IWL<8785> A_IWL<8784> A_IWL<8783> A_IWL<8782> A_IWL<8781> A_IWL<8780> A_IWL<8779> A_IWL<8778> A_IWL<8777> A_IWL<8776> A_IWL<8775> A_IWL<8774> A_IWL<8773> A_IWL<8772> A_IWL<8771> A_IWL<8770> A_IWL<8769> A_IWL<8768> A_IWL<8767> A_IWL<8766> A_IWL<8765> A_IWL<8764> A_IWL<8763> A_IWL<8762> A_IWL<8761> A_IWL<8760> A_IWL<8759> A_IWL<8758> A_IWL<8757> A_IWL<8756> A_IWL<8755> A_IWL<8754> A_IWL<8753> A_IWL<8752> A_IWL<8751> A_IWL<8750> A_IWL<8749> A_IWL<8748> A_IWL<8747> A_IWL<8746> A_IWL<8745> A_IWL<8744> A_IWL<8743> A_IWL<8742> A_IWL<8741> A_IWL<8740> A_IWL<8739> A_IWL<8738> A_IWL<8737> A_IWL<8736> A_IWL<8735> A_IWL<8734> A_IWL<8733> A_IWL<8732> A_IWL<8731> A_IWL<8730> A_IWL<8729> A_IWL<8728> A_IWL<8727> A_IWL<8726> A_IWL<8725> A_IWL<8724> A_IWL<8723> A_IWL<8722> A_IWL<8721> A_IWL<8720> A_IWL<8719> A_IWL<8718> A_IWL<8717> A_IWL<8716> A_IWL<8715> A_IWL<8714> A_IWL<8713> A_IWL<8712> A_IWL<8711> A_IWL<8710> A_IWL<8709> A_IWL<8708> A_IWL<8707> A_IWL<8706> A_IWL<8705> A_IWL<8704> A_IWL<9727> A_IWL<9726> A_IWL<9725> A_IWL<9724> A_IWL<9723> A_IWL<9722> A_IWL<9721> A_IWL<9720> A_IWL<9719> A_IWL<9718> A_IWL<9717> A_IWL<9716> A_IWL<9715> A_IWL<9714> A_IWL<9713> A_IWL<9712> A_IWL<9711> A_IWL<9710> A_IWL<9709> A_IWL<9708> A_IWL<9707> A_IWL<9706> A_IWL<9705> A_IWL<9704> A_IWL<9703> A_IWL<9702> A_IWL<9701> A_IWL<9700> A_IWL<9699> A_IWL<9698> A_IWL<9697> A_IWL<9696> A_IWL<9695> A_IWL<9694> A_IWL<9693> A_IWL<9692> A_IWL<9691> A_IWL<9690> A_IWL<9689> A_IWL<9688> A_IWL<9687> A_IWL<9686> A_IWL<9685> A_IWL<9684> A_IWL<9683> A_IWL<9682> A_IWL<9681> A_IWL<9680> A_IWL<9679> A_IWL<9678> A_IWL<9677> A_IWL<9676> A_IWL<9675> A_IWL<9674> A_IWL<9673> A_IWL<9672> A_IWL<9671> A_IWL<9670> A_IWL<9669> A_IWL<9668> A_IWL<9667> A_IWL<9666> A_IWL<9665> A_IWL<9664> A_IWL<9663> A_IWL<9662> A_IWL<9661> A_IWL<9660> A_IWL<9659> A_IWL<9658> A_IWL<9657> A_IWL<9656> A_IWL<9655> A_IWL<9654> A_IWL<9653> A_IWL<9652> A_IWL<9651> A_IWL<9650> A_IWL<9649> A_IWL<9648> A_IWL<9647> A_IWL<9646> A_IWL<9645> A_IWL<9644> A_IWL<9643> A_IWL<9642> A_IWL<9641> A_IWL<9640> A_IWL<9639> A_IWL<9638> A_IWL<9637> A_IWL<9636> A_IWL<9635> A_IWL<9634> A_IWL<9633> A_IWL<9632> A_IWL<9631> A_IWL<9630> A_IWL<9629> A_IWL<9628> A_IWL<9627> A_IWL<9626> A_IWL<9625> A_IWL<9624> A_IWL<9623> A_IWL<9622> A_IWL<9621> A_IWL<9620> A_IWL<9619> A_IWL<9618> A_IWL<9617> A_IWL<9616> A_IWL<9615> A_IWL<9614> A_IWL<9613> A_IWL<9612> A_IWL<9611> A_IWL<9610> A_IWL<9609> A_IWL<9608> A_IWL<9607> A_IWL<9606> A_IWL<9605> A_IWL<9604> A_IWL<9603> A_IWL<9602> A_IWL<9601> A_IWL<9600> A_IWL<9599> A_IWL<9598> A_IWL<9597> A_IWL<9596> A_IWL<9595> A_IWL<9594> A_IWL<9593> A_IWL<9592> A_IWL<9591> A_IWL<9590> A_IWL<9589> A_IWL<9588> A_IWL<9587> A_IWL<9586> A_IWL<9585> A_IWL<9584> A_IWL<9583> A_IWL<9582> A_IWL<9581> A_IWL<9580> A_IWL<9579> A_IWL<9578> A_IWL<9577> A_IWL<9576> A_IWL<9575> A_IWL<9574> A_IWL<9573> A_IWL<9572> A_IWL<9571> A_IWL<9570> A_IWL<9569> A_IWL<9568> A_IWL<9567> A_IWL<9566> A_IWL<9565> A_IWL<9564> A_IWL<9563> A_IWL<9562> A_IWL<9561> A_IWL<9560> A_IWL<9559> A_IWL<9558> A_IWL<9557> A_IWL<9556> A_IWL<9555> A_IWL<9554> A_IWL<9553> A_IWL<9552> A_IWL<9551> A_IWL<9550> A_IWL<9549> A_IWL<9548> A_IWL<9547> A_IWL<9546> A_IWL<9545> A_IWL<9544> A_IWL<9543> A_IWL<9542> A_IWL<9541> A_IWL<9540> A_IWL<9539> A_IWL<9538> A_IWL<9537> A_IWL<9536> A_IWL<9535> A_IWL<9534> A_IWL<9533> A_IWL<9532> A_IWL<9531> A_IWL<9530> A_IWL<9529> A_IWL<9528> A_IWL<9527> A_IWL<9526> A_IWL<9525> A_IWL<9524> A_IWL<9523> A_IWL<9522> A_IWL<9521> A_IWL<9520> A_IWL<9519> A_IWL<9518> A_IWL<9517> A_IWL<9516> A_IWL<9515> A_IWL<9514> A_IWL<9513> A_IWL<9512> A_IWL<9511> A_IWL<9510> A_IWL<9509> A_IWL<9508> A_IWL<9507> A_IWL<9506> A_IWL<9505> A_IWL<9504> A_IWL<9503> A_IWL<9502> A_IWL<9501> A_IWL<9500> A_IWL<9499> A_IWL<9498> A_IWL<9497> A_IWL<9496> A_IWL<9495> A_IWL<9494> A_IWL<9493> A_IWL<9492> A_IWL<9491> A_IWL<9490> A_IWL<9489> A_IWL<9488> A_IWL<9487> A_IWL<9486> A_IWL<9485> A_IWL<9484> A_IWL<9483> A_IWL<9482> A_IWL<9481> A_IWL<9480> A_IWL<9479> A_IWL<9478> A_IWL<9477> A_IWL<9476> A_IWL<9475> A_IWL<9474> A_IWL<9473> A_IWL<9472> A_IWL<9471> A_IWL<9470> A_IWL<9469> A_IWL<9468> A_IWL<9467> A_IWL<9466> A_IWL<9465> A_IWL<9464> A_IWL<9463> A_IWL<9462> A_IWL<9461> A_IWL<9460> A_IWL<9459> A_IWL<9458> A_IWL<9457> A_IWL<9456> A_IWL<9455> A_IWL<9454> A_IWL<9453> A_IWL<9452> A_IWL<9451> A_IWL<9450> A_IWL<9449> A_IWL<9448> A_IWL<9447> A_IWL<9446> A_IWL<9445> A_IWL<9444> A_IWL<9443> A_IWL<9442> A_IWL<9441> A_IWL<9440> A_IWL<9439> A_IWL<9438> A_IWL<9437> A_IWL<9436> A_IWL<9435> A_IWL<9434> A_IWL<9433> A_IWL<9432> A_IWL<9431> A_IWL<9430> A_IWL<9429> A_IWL<9428> A_IWL<9427> A_IWL<9426> A_IWL<9425> A_IWL<9424> A_IWL<9423> A_IWL<9422> A_IWL<9421> A_IWL<9420> A_IWL<9419> A_IWL<9418> A_IWL<9417> A_IWL<9416> A_IWL<9415> A_IWL<9414> A_IWL<9413> A_IWL<9412> A_IWL<9411> A_IWL<9410> A_IWL<9409> A_IWL<9408> A_IWL<9407> A_IWL<9406> A_IWL<9405> A_IWL<9404> A_IWL<9403> A_IWL<9402> A_IWL<9401> A_IWL<9400> A_IWL<9399> A_IWL<9398> A_IWL<9397> A_IWL<9396> A_IWL<9395> A_IWL<9394> A_IWL<9393> A_IWL<9392> A_IWL<9391> A_IWL<9390> A_IWL<9389> A_IWL<9388> A_IWL<9387> A_IWL<9386> A_IWL<9385> A_IWL<9384> A_IWL<9383> A_IWL<9382> A_IWL<9381> A_IWL<9380> A_IWL<9379> A_IWL<9378> A_IWL<9377> A_IWL<9376> A_IWL<9375> A_IWL<9374> A_IWL<9373> A_IWL<9372> A_IWL<9371> A_IWL<9370> A_IWL<9369> A_IWL<9368> A_IWL<9367> A_IWL<9366> A_IWL<9365> A_IWL<9364> A_IWL<9363> A_IWL<9362> A_IWL<9361> A_IWL<9360> A_IWL<9359> A_IWL<9358> A_IWL<9357> A_IWL<9356> A_IWL<9355> A_IWL<9354> A_IWL<9353> A_IWL<9352> A_IWL<9351> A_IWL<9350> A_IWL<9349> A_IWL<9348> A_IWL<9347> A_IWL<9346> A_IWL<9345> A_IWL<9344> A_IWL<9343> A_IWL<9342> A_IWL<9341> A_IWL<9340> A_IWL<9339> A_IWL<9338> A_IWL<9337> A_IWL<9336> A_IWL<9335> A_IWL<9334> A_IWL<9333> A_IWL<9332> A_IWL<9331> A_IWL<9330> A_IWL<9329> A_IWL<9328> A_IWL<9327> A_IWL<9326> A_IWL<9325> A_IWL<9324> A_IWL<9323> A_IWL<9322> A_IWL<9321> A_IWL<9320> A_IWL<9319> A_IWL<9318> A_IWL<9317> A_IWL<9316> A_IWL<9315> A_IWL<9314> A_IWL<9313> A_IWL<9312> A_IWL<9311> A_IWL<9310> A_IWL<9309> A_IWL<9308> A_IWL<9307> A_IWL<9306> A_IWL<9305> A_IWL<9304> A_IWL<9303> A_IWL<9302> A_IWL<9301> A_IWL<9300> A_IWL<9299> A_IWL<9298> A_IWL<9297> A_IWL<9296> A_IWL<9295> A_IWL<9294> A_IWL<9293> A_IWL<9292> A_IWL<9291> A_IWL<9290> A_IWL<9289> A_IWL<9288> A_IWL<9287> A_IWL<9286> A_IWL<9285> A_IWL<9284> A_IWL<9283> A_IWL<9282> A_IWL<9281> A_IWL<9280> A_IWL<9279> A_IWL<9278> A_IWL<9277> A_IWL<9276> A_IWL<9275> A_IWL<9274> A_IWL<9273> A_IWL<9272> A_IWL<9271> A_IWL<9270> A_IWL<9269> A_IWL<9268> A_IWL<9267> A_IWL<9266> A_IWL<9265> A_IWL<9264> A_IWL<9263> A_IWL<9262> A_IWL<9261> A_IWL<9260> A_IWL<9259> A_IWL<9258> A_IWL<9257> A_IWL<9256> A_IWL<9255> A_IWL<9254> A_IWL<9253> A_IWL<9252> A_IWL<9251> A_IWL<9250> A_IWL<9249> A_IWL<9248> A_IWL<9247> A_IWL<9246> A_IWL<9245> A_IWL<9244> A_IWL<9243> A_IWL<9242> A_IWL<9241> A_IWL<9240> A_IWL<9239> A_IWL<9238> A_IWL<9237> A_IWL<9236> A_IWL<9235> A_IWL<9234> A_IWL<9233> A_IWL<9232> A_IWL<9231> A_IWL<9230> A_IWL<9229> A_IWL<9228> A_IWL<9227> A_IWL<9226> A_IWL<9225> A_IWL<9224> A_IWL<9223> A_IWL<9222> A_IWL<9221> A_IWL<9220> A_IWL<9219> A_IWL<9218> A_IWL<9217> A_IWL<9216> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0
+XCOL<17> A_BLC<35> A_BLC<34> A_BLC_TOP<35> A_BLC_TOP<34> A_BLT<35> A_BLT<34> A_BLT_TOP<35> A_BLT_TOP<34> A_IWL<8703> A_IWL<8702> A_IWL<8701> A_IWL<8700> A_IWL<8699> A_IWL<8698> A_IWL<8697> A_IWL<8696> A_IWL<8695> A_IWL<8694> A_IWL<8693> A_IWL<8692> A_IWL<8691> A_IWL<8690> A_IWL<8689> A_IWL<8688> A_IWL<8687> A_IWL<8686> A_IWL<8685> A_IWL<8684> A_IWL<8683> A_IWL<8682> A_IWL<8681> A_IWL<8680> A_IWL<8679> A_IWL<8678> A_IWL<8677> A_IWL<8676> A_IWL<8675> A_IWL<8674> A_IWL<8673> A_IWL<8672> A_IWL<8671> A_IWL<8670> A_IWL<8669> A_IWL<8668> A_IWL<8667> A_IWL<8666> A_IWL<8665> A_IWL<8664> A_IWL<8663> A_IWL<8662> A_IWL<8661> A_IWL<8660> A_IWL<8659> A_IWL<8658> A_IWL<8657> A_IWL<8656> A_IWL<8655> A_IWL<8654> A_IWL<8653> A_IWL<8652> A_IWL<8651> A_IWL<8650> A_IWL<8649> A_IWL<8648> A_IWL<8647> A_IWL<8646> A_IWL<8645> A_IWL<8644> A_IWL<8643> A_IWL<8642> A_IWL<8641> A_IWL<8640> A_IWL<8639> A_IWL<8638> A_IWL<8637> A_IWL<8636> A_IWL<8635> A_IWL<8634> A_IWL<8633> A_IWL<8632> A_IWL<8631> A_IWL<8630> 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A_IWL<8560> A_IWL<8559> A_IWL<8558> A_IWL<8557> A_IWL<8556> A_IWL<8555> A_IWL<8554> A_IWL<8553> A_IWL<8552> A_IWL<8551> A_IWL<8550> A_IWL<8549> A_IWL<8548> A_IWL<8547> A_IWL<8546> A_IWL<8545> A_IWL<8544> A_IWL<8543> A_IWL<8542> A_IWL<8541> A_IWL<8540> A_IWL<8539> A_IWL<8538> A_IWL<8537> A_IWL<8536> A_IWL<8535> A_IWL<8534> A_IWL<8533> A_IWL<8532> A_IWL<8531> A_IWL<8530> A_IWL<8529> A_IWL<8528> A_IWL<8527> A_IWL<8526> A_IWL<8525> A_IWL<8524> A_IWL<8523> A_IWL<8522> A_IWL<8521> A_IWL<8520> A_IWL<8519> A_IWL<8518> A_IWL<8517> A_IWL<8516> A_IWL<8515> A_IWL<8514> A_IWL<8513> A_IWL<8512> A_IWL<8511> A_IWL<8510> A_IWL<8509> A_IWL<8508> A_IWL<8507> A_IWL<8506> A_IWL<8505> A_IWL<8504> A_IWL<8503> A_IWL<8502> A_IWL<8501> A_IWL<8500> A_IWL<8499> A_IWL<8498> A_IWL<8497> A_IWL<8496> A_IWL<8495> A_IWL<8494> A_IWL<8493> A_IWL<8492> A_IWL<8491> A_IWL<8490> A_IWL<8489> A_IWL<8488> A_IWL<8487> A_IWL<8486> A_IWL<8485> A_IWL<8484> A_IWL<8483> A_IWL<8482> A_IWL<8481> A_IWL<8480> A_IWL<8479> A_IWL<8478> A_IWL<8477> A_IWL<8476> A_IWL<8475> A_IWL<8474> A_IWL<8473> A_IWL<8472> A_IWL<8471> A_IWL<8470> A_IWL<8469> A_IWL<8468> A_IWL<8467> A_IWL<8466> A_IWL<8465> A_IWL<8464> A_IWL<8463> A_IWL<8462> A_IWL<8461> A_IWL<8460> A_IWL<8459> A_IWL<8458> A_IWL<8457> A_IWL<8456> A_IWL<8455> A_IWL<8454> A_IWL<8453> A_IWL<8452> A_IWL<8451> A_IWL<8450> A_IWL<8449> A_IWL<8448> A_IWL<8447> A_IWL<8446> A_IWL<8445> A_IWL<8444> A_IWL<8443> A_IWL<8442> A_IWL<8441> A_IWL<8440> A_IWL<8439> A_IWL<8438> A_IWL<8437> A_IWL<8436> A_IWL<8435> A_IWL<8434> A_IWL<8433> A_IWL<8432> A_IWL<8431> A_IWL<8430> A_IWL<8429> A_IWL<8428> A_IWL<8427> A_IWL<8426> A_IWL<8425> A_IWL<8424> A_IWL<8423> A_IWL<8422> A_IWL<8421> A_IWL<8420> A_IWL<8419> A_IWL<8418> A_IWL<8417> A_IWL<8416> A_IWL<8415> A_IWL<8414> A_IWL<8413> A_IWL<8412> A_IWL<8411> A_IWL<8410> A_IWL<8409> A_IWL<8408> A_IWL<8407> A_IWL<8406> A_IWL<8405> A_IWL<8404> A_IWL<8403> A_IWL<8402> A_IWL<8401> A_IWL<8400> A_IWL<8399> A_IWL<8398> A_IWL<8397> A_IWL<8396> A_IWL<8395> A_IWL<8394> A_IWL<8393> A_IWL<8392> A_IWL<8391> A_IWL<8390> A_IWL<8389> A_IWL<8388> A_IWL<8387> A_IWL<8386> A_IWL<8385> A_IWL<8384> A_IWL<8383> A_IWL<8382> A_IWL<8381> A_IWL<8380> A_IWL<8379> A_IWL<8378> A_IWL<8377> A_IWL<8376> A_IWL<8375> A_IWL<8374> A_IWL<8373> A_IWL<8372> A_IWL<8371> A_IWL<8370> A_IWL<8369> A_IWL<8368> A_IWL<8367> A_IWL<8366> A_IWL<8365> A_IWL<8364> A_IWL<8363> A_IWL<8362> A_IWL<8361> A_IWL<8360> A_IWL<8359> A_IWL<8358> A_IWL<8357> A_IWL<8356> A_IWL<8355> A_IWL<8354> A_IWL<8353> A_IWL<8352> A_IWL<8351> A_IWL<8350> A_IWL<8349> A_IWL<8348> A_IWL<8347> A_IWL<8346> A_IWL<8345> A_IWL<8344> A_IWL<8343> A_IWL<8342> A_IWL<8341> A_IWL<8340> A_IWL<8339> A_IWL<8338> A_IWL<8337> A_IWL<8336> A_IWL<8335> A_IWL<8334> A_IWL<8333> A_IWL<8332> A_IWL<8331> A_IWL<8330> A_IWL<8329> A_IWL<8328> A_IWL<8327> A_IWL<8326> A_IWL<8325> A_IWL<8324> A_IWL<8323> A_IWL<8322> A_IWL<8321> A_IWL<8320> A_IWL<8319> A_IWL<8318> A_IWL<8317> A_IWL<8316> A_IWL<8315> A_IWL<8314> A_IWL<8313> A_IWL<8312> A_IWL<8311> A_IWL<8310> A_IWL<8309> A_IWL<8308> A_IWL<8307> A_IWL<8306> A_IWL<8305> A_IWL<8304> A_IWL<8303> A_IWL<8302> A_IWL<8301> A_IWL<8300> A_IWL<8299> A_IWL<8298> A_IWL<8297> A_IWL<8296> A_IWL<8295> A_IWL<8294> A_IWL<8293> A_IWL<8292> A_IWL<8291> A_IWL<8290> A_IWL<8289> A_IWL<8288> A_IWL<8287> A_IWL<8286> A_IWL<8285> A_IWL<8284> A_IWL<8283> A_IWL<8282> A_IWL<8281> A_IWL<8280> A_IWL<8279> A_IWL<8278> A_IWL<8277> A_IWL<8276> A_IWL<8275> A_IWL<8274> A_IWL<8273> A_IWL<8272> A_IWL<8271> A_IWL<8270> A_IWL<8269> A_IWL<8268> A_IWL<8267> A_IWL<8266> A_IWL<8265> A_IWL<8264> A_IWL<8263> A_IWL<8262> A_IWL<8261> A_IWL<8260> A_IWL<8259> A_IWL<8258> A_IWL<8257> A_IWL<8256> A_IWL<8255> A_IWL<8254> A_IWL<8253> A_IWL<8252> A_IWL<8251> A_IWL<8250> A_IWL<8249> A_IWL<8248> A_IWL<8247> A_IWL<8246> A_IWL<8245> A_IWL<8244> A_IWL<8243> A_IWL<8242> A_IWL<8241> A_IWL<8240> A_IWL<8239> A_IWL<8238> A_IWL<8237> A_IWL<8236> A_IWL<8235> A_IWL<8234> A_IWL<8233> A_IWL<8232> A_IWL<8231> A_IWL<8230> A_IWL<8229> A_IWL<8228> A_IWL<8227> A_IWL<8226> A_IWL<8225> A_IWL<8224> A_IWL<8223> A_IWL<8222> A_IWL<8221> A_IWL<8220> A_IWL<8219> A_IWL<8218> A_IWL<8217> A_IWL<8216> A_IWL<8215> A_IWL<8214> A_IWL<8213> A_IWL<8212> A_IWL<8211> A_IWL<8210> A_IWL<8209> A_IWL<8208> A_IWL<8207> A_IWL<8206> A_IWL<8205> A_IWL<8204> A_IWL<8203> A_IWL<8202> A_IWL<8201> A_IWL<8200> A_IWL<8199> A_IWL<8198> A_IWL<8197> A_IWL<8196> A_IWL<8195> A_IWL<8194> A_IWL<8193> A_IWL<8192> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0
+XCOL<15> A_BLC<31> A_BLC<30> A_BLC_TOP<31> A_BLC_TOP<30> A_BLT<31> A_BLT<30> A_BLT_TOP<31> A_BLT_TOP<30> A_IWL<7679> A_IWL<7678> A_IWL<7677> A_IWL<7676> A_IWL<7675> A_IWL<7674> A_IWL<7673> A_IWL<7672> A_IWL<7671> A_IWL<7670> A_IWL<7669> A_IWL<7668> A_IWL<7667> A_IWL<7666> A_IWL<7665> A_IWL<7664> A_IWL<7663> A_IWL<7662> A_IWL<7661> A_IWL<7660> A_IWL<7659> A_IWL<7658> A_IWL<7657> A_IWL<7656> A_IWL<7655> A_IWL<7654> A_IWL<7653> A_IWL<7652> A_IWL<7651> A_IWL<7650> A_IWL<7649> A_IWL<7648> A_IWL<7647> A_IWL<7646> A_IWL<7645> A_IWL<7644> A_IWL<7643> A_IWL<7642> A_IWL<7641> A_IWL<7640> A_IWL<7639> A_IWL<7638> A_IWL<7637> A_IWL<7636> A_IWL<7635> A_IWL<7634> A_IWL<7633> A_IWL<7632> A_IWL<7631> A_IWL<7630> A_IWL<7629> A_IWL<7628> A_IWL<7627> A_IWL<7626> A_IWL<7625> A_IWL<7624> A_IWL<7623> A_IWL<7622> A_IWL<7621> A_IWL<7620> A_IWL<7619> A_IWL<7618> A_IWL<7617> A_IWL<7616> A_IWL<7615> A_IWL<7614> A_IWL<7613> A_IWL<7612> A_IWL<7611> A_IWL<7610> A_IWL<7609> A_IWL<7608> A_IWL<7607> A_IWL<7606> A_IWL<7605> A_IWL<7604> A_IWL<7603> A_IWL<7602> A_IWL<7601> A_IWL<7600> A_IWL<7599> A_IWL<7598> A_IWL<7597> A_IWL<7596> A_IWL<7595> A_IWL<7594> A_IWL<7593> A_IWL<7592> A_IWL<7591> A_IWL<7590> A_IWL<7589> A_IWL<7588> A_IWL<7587> A_IWL<7586> A_IWL<7585> A_IWL<7584> A_IWL<7583> A_IWL<7582> A_IWL<7581> A_IWL<7580> A_IWL<7579> A_IWL<7578> A_IWL<7577> A_IWL<7576> A_IWL<7575> A_IWL<7574> A_IWL<7573> A_IWL<7572> A_IWL<7571> A_IWL<7570> A_IWL<7569> A_IWL<7568> A_IWL<7567> A_IWL<7566> A_IWL<7565> A_IWL<7564> A_IWL<7563> A_IWL<7562> A_IWL<7561> A_IWL<7560> A_IWL<7559> A_IWL<7558> A_IWL<7557> A_IWL<7556> A_IWL<7555> A_IWL<7554> A_IWL<7553> A_IWL<7552> A_IWL<7551> A_IWL<7550> A_IWL<7549> A_IWL<7548> A_IWL<7547> A_IWL<7546> A_IWL<7545> A_IWL<7544> A_IWL<7543> A_IWL<7542> A_IWL<7541> A_IWL<7540> A_IWL<7539> A_IWL<7538> A_IWL<7537> A_IWL<7536> A_IWL<7535> A_IWL<7534> A_IWL<7533> A_IWL<7532> A_IWL<7531> A_IWL<7530> A_IWL<7529> A_IWL<7528> A_IWL<7527> A_IWL<7526> A_IWL<7525> A_IWL<7524> A_IWL<7523> A_IWL<7522> A_IWL<7521> A_IWL<7520> A_IWL<7519> A_IWL<7518> A_IWL<7517> A_IWL<7516> A_IWL<7515> A_IWL<7514> A_IWL<7513> A_IWL<7512> A_IWL<7511> A_IWL<7510> A_IWL<7509> A_IWL<7508> A_IWL<7507> A_IWL<7506> A_IWL<7505> A_IWL<7504> A_IWL<7503> A_IWL<7502> A_IWL<7501> A_IWL<7500> A_IWL<7499> A_IWL<7498> A_IWL<7497> A_IWL<7496> A_IWL<7495> A_IWL<7494> A_IWL<7493> A_IWL<7492> A_IWL<7491> A_IWL<7490> A_IWL<7489> A_IWL<7488> A_IWL<7487> A_IWL<7486> A_IWL<7485> A_IWL<7484> A_IWL<7483> A_IWL<7482> A_IWL<7481> A_IWL<7480> A_IWL<7479> A_IWL<7478> A_IWL<7477> A_IWL<7476> A_IWL<7475> A_IWL<7474> A_IWL<7473> A_IWL<7472> A_IWL<7471> A_IWL<7470> A_IWL<7469> A_IWL<7468> A_IWL<7467> A_IWL<7466> A_IWL<7465> A_IWL<7464> A_IWL<7463> A_IWL<7462> A_IWL<7461> A_IWL<7460> A_IWL<7459> A_IWL<7458> A_IWL<7457> A_IWL<7456> A_IWL<7455> A_IWL<7454> A_IWL<7453> A_IWL<7452> A_IWL<7451> A_IWL<7450> A_IWL<7449> A_IWL<7448> A_IWL<7447> A_IWL<7446> A_IWL<7445> A_IWL<7444> A_IWL<7443> A_IWL<7442> A_IWL<7441> A_IWL<7440> A_IWL<7439> A_IWL<7438> A_IWL<7437> A_IWL<7436> A_IWL<7435> A_IWL<7434> A_IWL<7433> A_IWL<7432> A_IWL<7431> A_IWL<7430> A_IWL<7429> A_IWL<7428> A_IWL<7427> A_IWL<7426> A_IWL<7425> A_IWL<7424> A_IWL<7423> A_IWL<7422> A_IWL<7421> A_IWL<7420> A_IWL<7419> A_IWL<7418> A_IWL<7417> A_IWL<7416> A_IWL<7415> A_IWL<7414> A_IWL<7413> A_IWL<7412> A_IWL<7411> A_IWL<7410> A_IWL<7409> A_IWL<7408> A_IWL<7407> A_IWL<7406> A_IWL<7405> A_IWL<7404> A_IWL<7403> A_IWL<7402> A_IWL<7401> A_IWL<7400> A_IWL<7399> A_IWL<7398> A_IWL<7397> A_IWL<7396> A_IWL<7395> A_IWL<7394> A_IWL<7393> A_IWL<7392> A_IWL<7391> A_IWL<7390> A_IWL<7389> A_IWL<7388> A_IWL<7387> A_IWL<7386> A_IWL<7385> A_IWL<7384> A_IWL<7383> A_IWL<7382> A_IWL<7381> A_IWL<7380> A_IWL<7379> A_IWL<7378> A_IWL<7377> A_IWL<7376> A_IWL<7375> A_IWL<7374> A_IWL<7373> A_IWL<7372> A_IWL<7371> A_IWL<7370> A_IWL<7369> A_IWL<7368> A_IWL<7367> A_IWL<7366> A_IWL<7365> A_IWL<7364> A_IWL<7363> A_IWL<7362> A_IWL<7361> A_IWL<7360> A_IWL<7359> A_IWL<7358> A_IWL<7357> A_IWL<7356> A_IWL<7355> A_IWL<7354> A_IWL<7353> A_IWL<7352> A_IWL<7351> A_IWL<7350> A_IWL<7349> A_IWL<7348> A_IWL<7347> A_IWL<7346> A_IWL<7345> A_IWL<7344> A_IWL<7343> A_IWL<7342> A_IWL<7341> A_IWL<7340> A_IWL<7339> A_IWL<7338> A_IWL<7337> A_IWL<7336> A_IWL<7335> A_IWL<7334> A_IWL<7333> A_IWL<7332> A_IWL<7331> A_IWL<7330> A_IWL<7329> A_IWL<7328> A_IWL<7327> A_IWL<7326> A_IWL<7325> A_IWL<7324> A_IWL<7323> A_IWL<7322> A_IWL<7321> A_IWL<7320> A_IWL<7319> A_IWL<7318> A_IWL<7317> A_IWL<7316> A_IWL<7315> A_IWL<7314> A_IWL<7313> A_IWL<7312> A_IWL<7311> A_IWL<7310> A_IWL<7309> A_IWL<7308> A_IWL<7307> A_IWL<7306> A_IWL<7305> A_IWL<7304> A_IWL<7303> A_IWL<7302> A_IWL<7301> A_IWL<7300> A_IWL<7299> A_IWL<7298> A_IWL<7297> A_IWL<7296> A_IWL<7295> A_IWL<7294> A_IWL<7293> A_IWL<7292> A_IWL<7291> A_IWL<7290> A_IWL<7289> A_IWL<7288> A_IWL<7287> A_IWL<7286> A_IWL<7285> A_IWL<7284> A_IWL<7283> A_IWL<7282> A_IWL<7281> A_IWL<7280> A_IWL<7279> A_IWL<7278> A_IWL<7277> A_IWL<7276> A_IWL<7275> A_IWL<7274> A_IWL<7273> A_IWL<7272> A_IWL<7271> A_IWL<7270> A_IWL<7269> A_IWL<7268> A_IWL<7267> A_IWL<7266> A_IWL<7265> A_IWL<7264> A_IWL<7263> A_IWL<7262> A_IWL<7261> A_IWL<7260> A_IWL<7259> A_IWL<7258> A_IWL<7257> A_IWL<7256> A_IWL<7255> A_IWL<7254> A_IWL<7253> A_IWL<7252> A_IWL<7251> A_IWL<7250> A_IWL<7249> A_IWL<7248> A_IWL<7247> A_IWL<7246> A_IWL<7245> A_IWL<7244> A_IWL<7243> A_IWL<7242> A_IWL<7241> A_IWL<7240> A_IWL<7239> A_IWL<7238> A_IWL<7237> A_IWL<7236> A_IWL<7235> A_IWL<7234> A_IWL<7233> A_IWL<7232> A_IWL<7231> A_IWL<7230> A_IWL<7229> A_IWL<7228> A_IWL<7227> A_IWL<7226> A_IWL<7225> A_IWL<7224> A_IWL<7223> A_IWL<7222> A_IWL<7221> A_IWL<7220> A_IWL<7219> A_IWL<7218> A_IWL<7217> A_IWL<7216> A_IWL<7215> A_IWL<7214> A_IWL<7213> A_IWL<7212> A_IWL<7211> A_IWL<7210> A_IWL<7209> A_IWL<7208> A_IWL<7207> A_IWL<7206> A_IWL<7205> A_IWL<7204> A_IWL<7203> A_IWL<7202> A_IWL<7201> A_IWL<7200> A_IWL<7199> A_IWL<7198> A_IWL<7197> A_IWL<7196> A_IWL<7195> A_IWL<7194> A_IWL<7193> A_IWL<7192> A_IWL<7191> A_IWL<7190> A_IWL<7189> A_IWL<7188> A_IWL<7187> A_IWL<7186> A_IWL<7185> A_IWL<7184> A_IWL<7183> A_IWL<7182> A_IWL<7181> A_IWL<7180> A_IWL<7179> A_IWL<7178> A_IWL<7177> A_IWL<7176> A_IWL<7175> A_IWL<7174> A_IWL<7173> A_IWL<7172> A_IWL<7171> A_IWL<7170> A_IWL<7169> A_IWL<7168> A_IWL<8191> A_IWL<8190> A_IWL<8189> A_IWL<8188> A_IWL<8187> A_IWL<8186> A_IWL<8185> A_IWL<8184> A_IWL<8183> A_IWL<8182> A_IWL<8181> A_IWL<8180> A_IWL<8179> A_IWL<8178> A_IWL<8177> A_IWL<8176> A_IWL<8175> A_IWL<8174> A_IWL<8173> A_IWL<8172> A_IWL<8171> A_IWL<8170> A_IWL<8169> A_IWL<8168> A_IWL<8167> A_IWL<8166> A_IWL<8165> A_IWL<8164> A_IWL<8163> A_IWL<8162> A_IWL<8161> A_IWL<8160> A_IWL<8159> A_IWL<8158> A_IWL<8157> A_IWL<8156> A_IWL<8155> A_IWL<8154> A_IWL<8153> A_IWL<8152> A_IWL<8151> A_IWL<8150> A_IWL<8149> A_IWL<8148> A_IWL<8147> A_IWL<8146> A_IWL<8145> A_IWL<8144> A_IWL<8143> A_IWL<8142> A_IWL<8141> A_IWL<8140> A_IWL<8139> A_IWL<8138> A_IWL<8137> A_IWL<8136> A_IWL<8135> A_IWL<8134> A_IWL<8133> A_IWL<8132> A_IWL<8131> A_IWL<8130> A_IWL<8129> A_IWL<8128> A_IWL<8127> A_IWL<8126> A_IWL<8125> A_IWL<8124> A_IWL<8123> A_IWL<8122> A_IWL<8121> A_IWL<8120> A_IWL<8119> A_IWL<8118> A_IWL<8117> A_IWL<8116> A_IWL<8115> A_IWL<8114> A_IWL<8113> A_IWL<8112> A_IWL<8111> A_IWL<8110> A_IWL<8109> A_IWL<8108> A_IWL<8107> A_IWL<8106> A_IWL<8105> A_IWL<8104> A_IWL<8103> A_IWL<8102> A_IWL<8101> A_IWL<8100> A_IWL<8099> A_IWL<8098> A_IWL<8097> A_IWL<8096> A_IWL<8095> A_IWL<8094> A_IWL<8093> A_IWL<8092> A_IWL<8091> A_IWL<8090> A_IWL<8089> A_IWL<8088> A_IWL<8087> A_IWL<8086> A_IWL<8085> A_IWL<8084> A_IWL<8083> A_IWL<8082> A_IWL<8081> A_IWL<8080> A_IWL<8079> A_IWL<8078> A_IWL<8077> A_IWL<8076> A_IWL<8075> A_IWL<8074> A_IWL<8073> A_IWL<8072> A_IWL<8071> A_IWL<8070> A_IWL<8069> A_IWL<8068> A_IWL<8067> A_IWL<8066> A_IWL<8065> A_IWL<8064> A_IWL<8063> A_IWL<8062> A_IWL<8061> A_IWL<8060> A_IWL<8059> A_IWL<8058> A_IWL<8057> A_IWL<8056> A_IWL<8055> A_IWL<8054> A_IWL<8053> A_IWL<8052> A_IWL<8051> A_IWL<8050> A_IWL<8049> A_IWL<8048> A_IWL<8047> A_IWL<8046> A_IWL<8045> A_IWL<8044> A_IWL<8043> A_IWL<8042> A_IWL<8041> A_IWL<8040> A_IWL<8039> A_IWL<8038> A_IWL<8037> A_IWL<8036> A_IWL<8035> A_IWL<8034> A_IWL<8033> A_IWL<8032> A_IWL<8031> A_IWL<8030> A_IWL<8029> A_IWL<8028> A_IWL<8027> A_IWL<8026> A_IWL<8025> A_IWL<8024> A_IWL<8023> A_IWL<8022> A_IWL<8021> A_IWL<8020> A_IWL<8019> A_IWL<8018> A_IWL<8017> A_IWL<8016> A_IWL<8015> A_IWL<8014> A_IWL<8013> A_IWL<8012> A_IWL<8011> A_IWL<8010> A_IWL<8009> A_IWL<8008> A_IWL<8007> A_IWL<8006> A_IWL<8005> A_IWL<8004> A_IWL<8003> A_IWL<8002> A_IWL<8001> A_IWL<8000> A_IWL<7999> A_IWL<7998> A_IWL<7997> A_IWL<7996> A_IWL<7995> A_IWL<7994> A_IWL<7993> A_IWL<7992> A_IWL<7991> A_IWL<7990> A_IWL<7989> A_IWL<7988> A_IWL<7987> A_IWL<7986> A_IWL<7985> A_IWL<7984> A_IWL<7983> A_IWL<7982> A_IWL<7981> A_IWL<7980> A_IWL<7979> A_IWL<7978> A_IWL<7977> A_IWL<7976> A_IWL<7975> A_IWL<7974> A_IWL<7973> A_IWL<7972> A_IWL<7971> A_IWL<7970> A_IWL<7969> A_IWL<7968> A_IWL<7967> A_IWL<7966> A_IWL<7965> A_IWL<7964> A_IWL<7963> A_IWL<7962> A_IWL<7961> A_IWL<7960> A_IWL<7959> A_IWL<7958> A_IWL<7957> A_IWL<7956> A_IWL<7955> A_IWL<7954> A_IWL<7953> A_IWL<7952> A_IWL<7951> A_IWL<7950> A_IWL<7949> A_IWL<7948> A_IWL<7947> A_IWL<7946> A_IWL<7945> A_IWL<7944> A_IWL<7943> A_IWL<7942> A_IWL<7941> A_IWL<7940> A_IWL<7939> A_IWL<7938> A_IWL<7937> A_IWL<7936> A_IWL<7935> A_IWL<7934> A_IWL<7933> A_IWL<7932> A_IWL<7931> A_IWL<7930> A_IWL<7929> A_IWL<7928> A_IWL<7927> A_IWL<7926> A_IWL<7925> A_IWL<7924> A_IWL<7923> A_IWL<7922> A_IWL<7921> A_IWL<7920> A_IWL<7919> A_IWL<7918> A_IWL<7917> A_IWL<7916> A_IWL<7915> A_IWL<7914> A_IWL<7913> A_IWL<7912> A_IWL<7911> A_IWL<7910> A_IWL<7909> A_IWL<7908> A_IWL<7907> A_IWL<7906> A_IWL<7905> A_IWL<7904> A_IWL<7903> A_IWL<7902> A_IWL<7901> A_IWL<7900> A_IWL<7899> A_IWL<7898> A_IWL<7897> A_IWL<7896> A_IWL<7895> A_IWL<7894> A_IWL<7893> A_IWL<7892> A_IWL<7891> A_IWL<7890> A_IWL<7889> A_IWL<7888> A_IWL<7887> A_IWL<7886> A_IWL<7885> A_IWL<7884> A_IWL<7883> A_IWL<7882> A_IWL<7881> A_IWL<7880> A_IWL<7879> A_IWL<7878> A_IWL<7877> A_IWL<7876> A_IWL<7875> A_IWL<7874> A_IWL<7873> A_IWL<7872> A_IWL<7871> A_IWL<7870> A_IWL<7869> A_IWL<7868> A_IWL<7867> A_IWL<7866> A_IWL<7865> A_IWL<7864> A_IWL<7863> A_IWL<7862> A_IWL<7861> A_IWL<7860> A_IWL<7859> A_IWL<7858> A_IWL<7857> A_IWL<7856> A_IWL<7855> A_IWL<7854> A_IWL<7853> A_IWL<7852> A_IWL<7851> A_IWL<7850> A_IWL<7849> A_IWL<7848> A_IWL<7847> A_IWL<7846> A_IWL<7845> A_IWL<7844> A_IWL<7843> A_IWL<7842> A_IWL<7841> A_IWL<7840> A_IWL<7839> A_IWL<7838> A_IWL<7837> A_IWL<7836> A_IWL<7835> A_IWL<7834> A_IWL<7833> A_IWL<7832> A_IWL<7831> A_IWL<7830> A_IWL<7829> A_IWL<7828> A_IWL<7827> A_IWL<7826> A_IWL<7825> A_IWL<7824> A_IWL<7823> A_IWL<7822> A_IWL<7821> A_IWL<7820> A_IWL<7819> A_IWL<7818> A_IWL<7817> A_IWL<7816> A_IWL<7815> A_IWL<7814> A_IWL<7813> A_IWL<7812> A_IWL<7811> A_IWL<7810> A_IWL<7809> A_IWL<7808> A_IWL<7807> A_IWL<7806> A_IWL<7805> A_IWL<7804> A_IWL<7803> A_IWL<7802> A_IWL<7801> A_IWL<7800> A_IWL<7799> A_IWL<7798> A_IWL<7797> A_IWL<7796> A_IWL<7795> A_IWL<7794> A_IWL<7793> A_IWL<7792> A_IWL<7791> A_IWL<7790> A_IWL<7789> A_IWL<7788> A_IWL<7787> A_IWL<7786> A_IWL<7785> A_IWL<7784> A_IWL<7783> A_IWL<7782> A_IWL<7781> A_IWL<7780> A_IWL<7779> A_IWL<7778> A_IWL<7777> A_IWL<7776> A_IWL<7775> A_IWL<7774> A_IWL<7773> A_IWL<7772> A_IWL<7771> A_IWL<7770> A_IWL<7769> A_IWL<7768> A_IWL<7767> A_IWL<7766> A_IWL<7765> A_IWL<7764> A_IWL<7763> A_IWL<7762> A_IWL<7761> A_IWL<7760> A_IWL<7759> A_IWL<7758> A_IWL<7757> A_IWL<7756> A_IWL<7755> A_IWL<7754> A_IWL<7753> A_IWL<7752> A_IWL<7751> A_IWL<7750> A_IWL<7749> A_IWL<7748> A_IWL<7747> A_IWL<7746> A_IWL<7745> A_IWL<7744> A_IWL<7743> A_IWL<7742> A_IWL<7741> A_IWL<7740> A_IWL<7739> A_IWL<7738> A_IWL<7737> A_IWL<7736> A_IWL<7735> A_IWL<7734> A_IWL<7733> A_IWL<7732> A_IWL<7731> A_IWL<7730> A_IWL<7729> A_IWL<7728> A_IWL<7727> A_IWL<7726> A_IWL<7725> A_IWL<7724> A_IWL<7723> A_IWL<7722> A_IWL<7721> A_IWL<7720> A_IWL<7719> A_IWL<7718> A_IWL<7717> A_IWL<7716> A_IWL<7715> A_IWL<7714> A_IWL<7713> A_IWL<7712> A_IWL<7711> A_IWL<7710> A_IWL<7709> A_IWL<7708> A_IWL<7707> A_IWL<7706> A_IWL<7705> A_IWL<7704> A_IWL<7703> A_IWL<7702> A_IWL<7701> A_IWL<7700> A_IWL<7699> A_IWL<7698> A_IWL<7697> A_IWL<7696> A_IWL<7695> A_IWL<7694> A_IWL<7693> A_IWL<7692> A_IWL<7691> A_IWL<7690> A_IWL<7689> A_IWL<7688> A_IWL<7687> A_IWL<7686> A_IWL<7685> A_IWL<7684> A_IWL<7683> A_IWL<7682> A_IWL<7681> A_IWL<7680> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0
+XCOL<14> A_BLC<29> A_BLC<28> A_BLC_TOP<29> A_BLC_TOP<28> A_BLT<29> A_BLT<28> A_BLT_TOP<29> A_BLT_TOP<28> A_IWL<7167> A_IWL<7166> A_IWL<7165> A_IWL<7164> A_IWL<7163> A_IWL<7162> A_IWL<7161> A_IWL<7160> A_IWL<7159> A_IWL<7158> A_IWL<7157> A_IWL<7156> A_IWL<7155> A_IWL<7154> A_IWL<7153> A_IWL<7152> A_IWL<7151> A_IWL<7150> A_IWL<7149> A_IWL<7148> A_IWL<7147> A_IWL<7146> A_IWL<7145> A_IWL<7144> A_IWL<7143> A_IWL<7142> A_IWL<7141> A_IWL<7140> A_IWL<7139> A_IWL<7138> A_IWL<7137> A_IWL<7136> A_IWL<7135> A_IWL<7134> A_IWL<7133> A_IWL<7132> A_IWL<7131> A_IWL<7130> A_IWL<7129> A_IWL<7128> A_IWL<7127> A_IWL<7126> A_IWL<7125> A_IWL<7124> A_IWL<7123> A_IWL<7122> A_IWL<7121> A_IWL<7120> A_IWL<7119> A_IWL<7118> A_IWL<7117> A_IWL<7116> A_IWL<7115> A_IWL<7114> A_IWL<7113> A_IWL<7112> A_IWL<7111> A_IWL<7110> A_IWL<7109> A_IWL<7108> A_IWL<7107> A_IWL<7106> A_IWL<7105> A_IWL<7104> A_IWL<7103> A_IWL<7102> A_IWL<7101> A_IWL<7100> A_IWL<7099> A_IWL<7098> A_IWL<7097> A_IWL<7096> A_IWL<7095> A_IWL<7094> A_IWL<7093> A_IWL<7092> A_IWL<7091> A_IWL<7090> A_IWL<7089> A_IWL<7088> A_IWL<7087> A_IWL<7086> A_IWL<7085> A_IWL<7084> A_IWL<7083> A_IWL<7082> A_IWL<7081> A_IWL<7080> A_IWL<7079> A_IWL<7078> A_IWL<7077> A_IWL<7076> A_IWL<7075> A_IWL<7074> A_IWL<7073> A_IWL<7072> A_IWL<7071> A_IWL<7070> A_IWL<7069> A_IWL<7068> A_IWL<7067> A_IWL<7066> A_IWL<7065> A_IWL<7064> A_IWL<7063> A_IWL<7062> A_IWL<7061> A_IWL<7060> A_IWL<7059> A_IWL<7058> A_IWL<7057> A_IWL<7056> A_IWL<7055> A_IWL<7054> A_IWL<7053> A_IWL<7052> A_IWL<7051> A_IWL<7050> A_IWL<7049> A_IWL<7048> A_IWL<7047> A_IWL<7046> A_IWL<7045> A_IWL<7044> A_IWL<7043> A_IWL<7042> A_IWL<7041> A_IWL<7040> A_IWL<7039> A_IWL<7038> A_IWL<7037> A_IWL<7036> A_IWL<7035> A_IWL<7034> A_IWL<7033> A_IWL<7032> A_IWL<7031> A_IWL<7030> A_IWL<7029> A_IWL<7028> A_IWL<7027> A_IWL<7026> A_IWL<7025> A_IWL<7024> A_IWL<7023> A_IWL<7022> A_IWL<7021> A_IWL<7020> A_IWL<7019> A_IWL<7018> A_IWL<7017> A_IWL<7016> A_IWL<7015> A_IWL<7014> A_IWL<7013> A_IWL<7012> A_IWL<7011> A_IWL<7010> A_IWL<7009> A_IWL<7008> A_IWL<7007> A_IWL<7006> A_IWL<7005> A_IWL<7004> A_IWL<7003> A_IWL<7002> A_IWL<7001> A_IWL<7000> A_IWL<6999> A_IWL<6998> A_IWL<6997> A_IWL<6996> A_IWL<6995> A_IWL<6994> A_IWL<6993> A_IWL<6992> A_IWL<6991> A_IWL<6990> A_IWL<6989> A_IWL<6988> A_IWL<6987> A_IWL<6986> A_IWL<6985> A_IWL<6984> A_IWL<6983> A_IWL<6982> A_IWL<6981> A_IWL<6980> A_IWL<6979> A_IWL<6978> A_IWL<6977> A_IWL<6976> A_IWL<6975> A_IWL<6974> A_IWL<6973> A_IWL<6972> A_IWL<6971> A_IWL<6970> A_IWL<6969> A_IWL<6968> A_IWL<6967> A_IWL<6966> A_IWL<6965> A_IWL<6964> A_IWL<6963> A_IWL<6962> A_IWL<6961> A_IWL<6960> A_IWL<6959> A_IWL<6958> A_IWL<6957> A_IWL<6956> A_IWL<6955> A_IWL<6954> A_IWL<6953> A_IWL<6952> A_IWL<6951> A_IWL<6950> A_IWL<6949> A_IWL<6948> A_IWL<6947> A_IWL<6946> A_IWL<6945> A_IWL<6944> A_IWL<6943> A_IWL<6942> A_IWL<6941> A_IWL<6940> A_IWL<6939> A_IWL<6938> A_IWL<6937> A_IWL<6936> A_IWL<6935> A_IWL<6934> A_IWL<6933> A_IWL<6932> A_IWL<6931> A_IWL<6930> A_IWL<6929> A_IWL<6928> A_IWL<6927> A_IWL<6926> A_IWL<6925> A_IWL<6924> A_IWL<6923> A_IWL<6922> A_IWL<6921> A_IWL<6920> A_IWL<6919> A_IWL<6918> A_IWL<6917> A_IWL<6916> A_IWL<6915> A_IWL<6914> A_IWL<6913> A_IWL<6912> A_IWL<6911> A_IWL<6910> A_IWL<6909> A_IWL<6908> A_IWL<6907> A_IWL<6906> A_IWL<6905> A_IWL<6904> A_IWL<6903> A_IWL<6902> A_IWL<6901> A_IWL<6900> A_IWL<6899> A_IWL<6898> A_IWL<6897> A_IWL<6896> A_IWL<6895> A_IWL<6894> A_IWL<6893> A_IWL<6892> A_IWL<6891> A_IWL<6890> A_IWL<6889> A_IWL<6888> A_IWL<6887> A_IWL<6886> A_IWL<6885> A_IWL<6884> A_IWL<6883> A_IWL<6882> A_IWL<6881> A_IWL<6880> A_IWL<6879> A_IWL<6878> A_IWL<6877> A_IWL<6876> A_IWL<6875> A_IWL<6874> A_IWL<6873> A_IWL<6872> A_IWL<6871> A_IWL<6870> A_IWL<6869> A_IWL<6868> A_IWL<6867> A_IWL<6866> A_IWL<6865> A_IWL<6864> A_IWL<6863> A_IWL<6862> A_IWL<6861> A_IWL<6860> A_IWL<6859> A_IWL<6858> A_IWL<6857> A_IWL<6856> A_IWL<6855> A_IWL<6854> A_IWL<6853> A_IWL<6852> A_IWL<6851> A_IWL<6850> A_IWL<6849> A_IWL<6848> A_IWL<6847> A_IWL<6846> A_IWL<6845> A_IWL<6844> A_IWL<6843> A_IWL<6842> A_IWL<6841> A_IWL<6840> A_IWL<6839> A_IWL<6838> A_IWL<6837> A_IWL<6836> A_IWL<6835> A_IWL<6834> A_IWL<6833> A_IWL<6832> A_IWL<6831> A_IWL<6830> A_IWL<6829> A_IWL<6828> A_IWL<6827> A_IWL<6826> A_IWL<6825> A_IWL<6824> A_IWL<6823> A_IWL<6822> A_IWL<6821> A_IWL<6820> A_IWL<6819> A_IWL<6818> A_IWL<6817> A_IWL<6816> A_IWL<6815> A_IWL<6814> A_IWL<6813> A_IWL<6812> A_IWL<6811> A_IWL<6810> A_IWL<6809> A_IWL<6808> A_IWL<6807> A_IWL<6806> A_IWL<6805> A_IWL<6804> A_IWL<6803> A_IWL<6802> A_IWL<6801> A_IWL<6800> A_IWL<6799> A_IWL<6798> A_IWL<6797> A_IWL<6796> A_IWL<6795> A_IWL<6794> A_IWL<6793> A_IWL<6792> A_IWL<6791> A_IWL<6790> A_IWL<6789> A_IWL<6788> A_IWL<6787> A_IWL<6786> A_IWL<6785> A_IWL<6784> A_IWL<6783> A_IWL<6782> A_IWL<6781> A_IWL<6780> A_IWL<6779> A_IWL<6778> A_IWL<6777> A_IWL<6776> A_IWL<6775> A_IWL<6774> A_IWL<6773> A_IWL<6772> A_IWL<6771> A_IWL<6770> A_IWL<6769> A_IWL<6768> A_IWL<6767> A_IWL<6766> A_IWL<6765> A_IWL<6764> A_IWL<6763> A_IWL<6762> A_IWL<6761> A_IWL<6760> A_IWL<6759> A_IWL<6758> A_IWL<6757> A_IWL<6756> A_IWL<6755> A_IWL<6754> A_IWL<6753> A_IWL<6752> A_IWL<6751> A_IWL<6750> A_IWL<6749> A_IWL<6748> A_IWL<6747> A_IWL<6746> A_IWL<6745> A_IWL<6744> A_IWL<6743> A_IWL<6742> A_IWL<6741> A_IWL<6740> A_IWL<6739> A_IWL<6738> A_IWL<6737> A_IWL<6736> A_IWL<6735> A_IWL<6734> A_IWL<6733> A_IWL<6732> A_IWL<6731> A_IWL<6730> A_IWL<6729> A_IWL<6728> A_IWL<6727> A_IWL<6726> A_IWL<6725> A_IWL<6724> A_IWL<6723> A_IWL<6722> A_IWL<6721> A_IWL<6720> A_IWL<6719> A_IWL<6718> A_IWL<6717> A_IWL<6716> A_IWL<6715> A_IWL<6714> A_IWL<6713> A_IWL<6712> A_IWL<6711> A_IWL<6710> A_IWL<6709> A_IWL<6708> A_IWL<6707> A_IWL<6706> A_IWL<6705> A_IWL<6704> A_IWL<6703> A_IWL<6702> A_IWL<6701> A_IWL<6700> A_IWL<6699> A_IWL<6698> A_IWL<6697> A_IWL<6696> A_IWL<6695> A_IWL<6694> A_IWL<6693> A_IWL<6692> A_IWL<6691> A_IWL<6690> A_IWL<6689> A_IWL<6688> A_IWL<6687> A_IWL<6686> A_IWL<6685> A_IWL<6684> A_IWL<6683> A_IWL<6682> A_IWL<6681> A_IWL<6680> A_IWL<6679> A_IWL<6678> A_IWL<6677> A_IWL<6676> A_IWL<6675> A_IWL<6674> A_IWL<6673> A_IWL<6672> A_IWL<6671> A_IWL<6670> A_IWL<6669> A_IWL<6668> A_IWL<6667> A_IWL<6666> A_IWL<6665> A_IWL<6664> A_IWL<6663> A_IWL<6662> A_IWL<6661> A_IWL<6660> A_IWL<6659> A_IWL<6658> A_IWL<6657> A_IWL<6656> A_IWL<7679> A_IWL<7678> A_IWL<7677> A_IWL<7676> A_IWL<7675> A_IWL<7674> A_IWL<7673> A_IWL<7672> A_IWL<7671> A_IWL<7670> A_IWL<7669> A_IWL<7668> A_IWL<7667> A_IWL<7666> A_IWL<7665> A_IWL<7664> A_IWL<7663> A_IWL<7662> A_IWL<7661> A_IWL<7660> A_IWL<7659> A_IWL<7658> A_IWL<7657> A_IWL<7656> A_IWL<7655> A_IWL<7654> A_IWL<7653> A_IWL<7652> A_IWL<7651> A_IWL<7650> A_IWL<7649> A_IWL<7648> A_IWL<7647> A_IWL<7646> A_IWL<7645> A_IWL<7644> A_IWL<7643> A_IWL<7642> A_IWL<7641> A_IWL<7640> A_IWL<7639> A_IWL<7638> A_IWL<7637> A_IWL<7636> A_IWL<7635> A_IWL<7634> A_IWL<7633> A_IWL<7632> A_IWL<7631> A_IWL<7630> A_IWL<7629> A_IWL<7628> A_IWL<7627> A_IWL<7626> A_IWL<7625> A_IWL<7624> A_IWL<7623> A_IWL<7622> A_IWL<7621> A_IWL<7620> A_IWL<7619> A_IWL<7618> A_IWL<7617> A_IWL<7616> A_IWL<7615> A_IWL<7614> A_IWL<7613> A_IWL<7612> A_IWL<7611> A_IWL<7610> A_IWL<7609> A_IWL<7608> A_IWL<7607> A_IWL<7606> A_IWL<7605> A_IWL<7604> A_IWL<7603> A_IWL<7602> A_IWL<7601> A_IWL<7600> A_IWL<7599> A_IWL<7598> A_IWL<7597> A_IWL<7596> A_IWL<7595> A_IWL<7594> A_IWL<7593> A_IWL<7592> A_IWL<7591> A_IWL<7590> A_IWL<7589> A_IWL<7588> A_IWL<7587> A_IWL<7586> A_IWL<7585> A_IWL<7584> A_IWL<7583> A_IWL<7582> A_IWL<7581> A_IWL<7580> A_IWL<7579> A_IWL<7578> A_IWL<7577> A_IWL<7576> A_IWL<7575> A_IWL<7574> A_IWL<7573> A_IWL<7572> A_IWL<7571> A_IWL<7570> A_IWL<7569> A_IWL<7568> A_IWL<7567> A_IWL<7566> A_IWL<7565> A_IWL<7564> A_IWL<7563> A_IWL<7562> A_IWL<7561> A_IWL<7560> A_IWL<7559> A_IWL<7558> A_IWL<7557> A_IWL<7556> A_IWL<7555> A_IWL<7554> A_IWL<7553> A_IWL<7552> A_IWL<7551> A_IWL<7550> A_IWL<7549> A_IWL<7548> A_IWL<7547> A_IWL<7546> A_IWL<7545> A_IWL<7544> A_IWL<7543> A_IWL<7542> A_IWL<7541> A_IWL<7540> A_IWL<7539> A_IWL<7538> A_IWL<7537> A_IWL<7536> A_IWL<7535> A_IWL<7534> A_IWL<7533> A_IWL<7532> A_IWL<7531> A_IWL<7530> A_IWL<7529> A_IWL<7528> A_IWL<7527> A_IWL<7526> A_IWL<7525> A_IWL<7524> A_IWL<7523> A_IWL<7522> A_IWL<7521> A_IWL<7520> A_IWL<7519> A_IWL<7518> A_IWL<7517> A_IWL<7516> A_IWL<7515> A_IWL<7514> A_IWL<7513> A_IWL<7512> A_IWL<7511> A_IWL<7510> A_IWL<7509> A_IWL<7508> A_IWL<7507> A_IWL<7506> A_IWL<7505> A_IWL<7504> A_IWL<7503> A_IWL<7502> A_IWL<7501> A_IWL<7500> A_IWL<7499> A_IWL<7498> A_IWL<7497> A_IWL<7496> A_IWL<7495> A_IWL<7494> A_IWL<7493> A_IWL<7492> A_IWL<7491> A_IWL<7490> A_IWL<7489> A_IWL<7488> A_IWL<7487> A_IWL<7486> A_IWL<7485> A_IWL<7484> A_IWL<7483> A_IWL<7482> A_IWL<7481> A_IWL<7480> A_IWL<7479> A_IWL<7478> A_IWL<7477> A_IWL<7476> A_IWL<7475> A_IWL<7474> A_IWL<7473> A_IWL<7472> A_IWL<7471> A_IWL<7470> A_IWL<7469> A_IWL<7468> A_IWL<7467> A_IWL<7466> A_IWL<7465> A_IWL<7464> A_IWL<7463> A_IWL<7462> A_IWL<7461> A_IWL<7460> A_IWL<7459> A_IWL<7458> A_IWL<7457> A_IWL<7456> A_IWL<7455> A_IWL<7454> A_IWL<7453> A_IWL<7452> A_IWL<7451> A_IWL<7450> A_IWL<7449> A_IWL<7448> A_IWL<7447> A_IWL<7446> A_IWL<7445> A_IWL<7444> A_IWL<7443> A_IWL<7442> A_IWL<7441> A_IWL<7440> A_IWL<7439> A_IWL<7438> A_IWL<7437> A_IWL<7436> A_IWL<7435> A_IWL<7434> A_IWL<7433> A_IWL<7432> A_IWL<7431> A_IWL<7430> A_IWL<7429> A_IWL<7428> A_IWL<7427> A_IWL<7426> A_IWL<7425> A_IWL<7424> A_IWL<7423> A_IWL<7422> A_IWL<7421> A_IWL<7420> A_IWL<7419> A_IWL<7418> A_IWL<7417> A_IWL<7416> A_IWL<7415> A_IWL<7414> A_IWL<7413> A_IWL<7412> A_IWL<7411> A_IWL<7410> A_IWL<7409> A_IWL<7408> A_IWL<7407> A_IWL<7406> A_IWL<7405> A_IWL<7404> A_IWL<7403> A_IWL<7402> A_IWL<7401> A_IWL<7400> A_IWL<7399> A_IWL<7398> A_IWL<7397> A_IWL<7396> A_IWL<7395> A_IWL<7394> A_IWL<7393> A_IWL<7392> A_IWL<7391> A_IWL<7390> A_IWL<7389> A_IWL<7388> A_IWL<7387> A_IWL<7386> A_IWL<7385> A_IWL<7384> A_IWL<7383> A_IWL<7382> A_IWL<7381> A_IWL<7380> A_IWL<7379> A_IWL<7378> A_IWL<7377> A_IWL<7376> A_IWL<7375> A_IWL<7374> A_IWL<7373> A_IWL<7372> A_IWL<7371> A_IWL<7370> A_IWL<7369> A_IWL<7368> A_IWL<7367> A_IWL<7366> A_IWL<7365> A_IWL<7364> A_IWL<7363> A_IWL<7362> A_IWL<7361> A_IWL<7360> A_IWL<7359> A_IWL<7358> A_IWL<7357> A_IWL<7356> A_IWL<7355> A_IWL<7354> A_IWL<7353> A_IWL<7352> A_IWL<7351> A_IWL<7350> A_IWL<7349> A_IWL<7348> A_IWL<7347> A_IWL<7346> A_IWL<7345> A_IWL<7344> A_IWL<7343> A_IWL<7342> A_IWL<7341> A_IWL<7340> A_IWL<7339> A_IWL<7338> A_IWL<7337> A_IWL<7336> A_IWL<7335> A_IWL<7334> A_IWL<7333> A_IWL<7332> A_IWL<7331> A_IWL<7330> A_IWL<7329> A_IWL<7328> A_IWL<7327> A_IWL<7326> A_IWL<7325> A_IWL<7324> A_IWL<7323> A_IWL<7322> A_IWL<7321> A_IWL<7320> A_IWL<7319> A_IWL<7318> A_IWL<7317> A_IWL<7316> A_IWL<7315> A_IWL<7314> A_IWL<7313> A_IWL<7312> A_IWL<7311> A_IWL<7310> A_IWL<7309> A_IWL<7308> A_IWL<7307> A_IWL<7306> A_IWL<7305> A_IWL<7304> A_IWL<7303> A_IWL<7302> A_IWL<7301> A_IWL<7300> A_IWL<7299> A_IWL<7298> A_IWL<7297> A_IWL<7296> A_IWL<7295> A_IWL<7294> A_IWL<7293> A_IWL<7292> A_IWL<7291> A_IWL<7290> A_IWL<7289> A_IWL<7288> A_IWL<7287> A_IWL<7286> A_IWL<7285> A_IWL<7284> A_IWL<7283> A_IWL<7282> A_IWL<7281> A_IWL<7280> A_IWL<7279> A_IWL<7278> A_IWL<7277> A_IWL<7276> A_IWL<7275> A_IWL<7274> A_IWL<7273> A_IWL<7272> A_IWL<7271> A_IWL<7270> A_IWL<7269> A_IWL<7268> A_IWL<7267> A_IWL<7266> A_IWL<7265> A_IWL<7264> A_IWL<7263> A_IWL<7262> A_IWL<7261> A_IWL<7260> A_IWL<7259> A_IWL<7258> A_IWL<7257> A_IWL<7256> A_IWL<7255> A_IWL<7254> A_IWL<7253> A_IWL<7252> A_IWL<7251> A_IWL<7250> A_IWL<7249> A_IWL<7248> A_IWL<7247> A_IWL<7246> A_IWL<7245> A_IWL<7244> A_IWL<7243> A_IWL<7242> A_IWL<7241> A_IWL<7240> A_IWL<7239> A_IWL<7238> A_IWL<7237> A_IWL<7236> A_IWL<7235> A_IWL<7234> A_IWL<7233> A_IWL<7232> A_IWL<7231> A_IWL<7230> A_IWL<7229> A_IWL<7228> A_IWL<7227> A_IWL<7226> A_IWL<7225> A_IWL<7224> A_IWL<7223> A_IWL<7222> A_IWL<7221> A_IWL<7220> A_IWL<7219> A_IWL<7218> A_IWL<7217> A_IWL<7216> A_IWL<7215> A_IWL<7214> A_IWL<7213> A_IWL<7212> A_IWL<7211> A_IWL<7210> A_IWL<7209> A_IWL<7208> A_IWL<7207> A_IWL<7206> A_IWL<7205> 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A_IWL<6941> A_IWL<6940> A_IWL<6939> A_IWL<6938> A_IWL<6937> A_IWL<6936> A_IWL<6935> A_IWL<6934> A_IWL<6933> A_IWL<6932> A_IWL<6931> A_IWL<6930> A_IWL<6929> A_IWL<6928> A_IWL<6927> A_IWL<6926> A_IWL<6925> A_IWL<6924> A_IWL<6923> A_IWL<6922> A_IWL<6921> A_IWL<6920> A_IWL<6919> A_IWL<6918> A_IWL<6917> A_IWL<6916> A_IWL<6915> A_IWL<6914> A_IWL<6913> A_IWL<6912> A_IWL<6911> A_IWL<6910> A_IWL<6909> A_IWL<6908> A_IWL<6907> A_IWL<6906> A_IWL<6905> A_IWL<6904> A_IWL<6903> A_IWL<6902> A_IWL<6901> A_IWL<6900> A_IWL<6899> A_IWL<6898> A_IWL<6897> A_IWL<6896> A_IWL<6895> A_IWL<6894> A_IWL<6893> A_IWL<6892> A_IWL<6891> A_IWL<6890> A_IWL<6889> A_IWL<6888> A_IWL<6887> A_IWL<6886> A_IWL<6885> A_IWL<6884> A_IWL<6883> A_IWL<6882> A_IWL<6881> A_IWL<6880> A_IWL<6879> A_IWL<6878> A_IWL<6877> A_IWL<6876> A_IWL<6875> A_IWL<6874> A_IWL<6873> A_IWL<6872> A_IWL<6871> A_IWL<6870> A_IWL<6869> A_IWL<6868> A_IWL<6867> A_IWL<6866> A_IWL<6865> A_IWL<6864> A_IWL<6863> A_IWL<6862> A_IWL<6861> A_IWL<6860> A_IWL<6859> A_IWL<6858> A_IWL<6857> A_IWL<6856> A_IWL<6855> A_IWL<6854> A_IWL<6853> A_IWL<6852> A_IWL<6851> A_IWL<6850> A_IWL<6849> A_IWL<6848> A_IWL<6847> A_IWL<6846> A_IWL<6845> A_IWL<6844> A_IWL<6843> A_IWL<6842> A_IWL<6841> A_IWL<6840> A_IWL<6839> A_IWL<6838> A_IWL<6837> A_IWL<6836> A_IWL<6835> A_IWL<6834> A_IWL<6833> A_IWL<6832> A_IWL<6831> A_IWL<6830> A_IWL<6829> A_IWL<6828> A_IWL<6827> A_IWL<6826> A_IWL<6825> A_IWL<6824> A_IWL<6823> A_IWL<6822> A_IWL<6821> A_IWL<6820> A_IWL<6819> A_IWL<6818> A_IWL<6817> A_IWL<6816> A_IWL<6815> A_IWL<6814> A_IWL<6813> A_IWL<6812> A_IWL<6811> A_IWL<6810> A_IWL<6809> A_IWL<6808> A_IWL<6807> A_IWL<6806> A_IWL<6805> A_IWL<6804> A_IWL<6803> A_IWL<6802> A_IWL<6801> A_IWL<6800> A_IWL<6799> A_IWL<6798> A_IWL<6797> A_IWL<6796> A_IWL<6795> A_IWL<6794> A_IWL<6793> A_IWL<6792> A_IWL<6791> A_IWL<6790> A_IWL<6789> A_IWL<6788> A_IWL<6787> A_IWL<6786> A_IWL<6785> A_IWL<6784> A_IWL<6783> A_IWL<6782> A_IWL<6781> A_IWL<6780> A_IWL<6779> A_IWL<6778> A_IWL<6777> A_IWL<6776> A_IWL<6775> A_IWL<6774> A_IWL<6773> A_IWL<6772> A_IWL<6771> A_IWL<6770> A_IWL<6769> A_IWL<6768> A_IWL<6767> A_IWL<6766> A_IWL<6765> A_IWL<6764> A_IWL<6763> A_IWL<6762> A_IWL<6761> A_IWL<6760> A_IWL<6759> A_IWL<6758> A_IWL<6757> A_IWL<6756> A_IWL<6755> A_IWL<6754> A_IWL<6753> A_IWL<6752> A_IWL<6751> A_IWL<6750> A_IWL<6749> A_IWL<6748> A_IWL<6747> A_IWL<6746> A_IWL<6745> A_IWL<6744> A_IWL<6743> A_IWL<6742> A_IWL<6741> A_IWL<6740> A_IWL<6739> A_IWL<6738> A_IWL<6737> A_IWL<6736> A_IWL<6735> A_IWL<6734> A_IWL<6733> A_IWL<6732> A_IWL<6731> A_IWL<6730> A_IWL<6729> A_IWL<6728> A_IWL<6727> A_IWL<6726> A_IWL<6725> A_IWL<6724> A_IWL<6723> A_IWL<6722> A_IWL<6721> A_IWL<6720> A_IWL<6719> A_IWL<6718> A_IWL<6717> A_IWL<6716> A_IWL<6715> A_IWL<6714> A_IWL<6713> A_IWL<6712> A_IWL<6711> A_IWL<6710> A_IWL<6709> A_IWL<6708> A_IWL<6707> A_IWL<6706> A_IWL<6705> A_IWL<6704> A_IWL<6703> A_IWL<6702> A_IWL<6701> A_IWL<6700> A_IWL<6699> A_IWL<6698> A_IWL<6697> A_IWL<6696> A_IWL<6695> A_IWL<6694> A_IWL<6693> A_IWL<6692> A_IWL<6691> A_IWL<6690> A_IWL<6689> A_IWL<6688> A_IWL<6687> A_IWL<6686> A_IWL<6685> A_IWL<6684> A_IWL<6683> A_IWL<6682> A_IWL<6681> A_IWL<6680> A_IWL<6679> A_IWL<6678> A_IWL<6677> A_IWL<6676> A_IWL<6675> A_IWL<6674> A_IWL<6673> A_IWL<6672> A_IWL<6671> A_IWL<6670> A_IWL<6669> A_IWL<6668> A_IWL<6667> A_IWL<6666> A_IWL<6665> A_IWL<6664> A_IWL<6663> A_IWL<6662> A_IWL<6661> A_IWL<6660> A_IWL<6659> A_IWL<6658> A_IWL<6657> A_IWL<6656> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0
+XCOL<12> A_BLC<25> A_BLC<24> A_BLC_TOP<25> A_BLC_TOP<24> A_BLT<25> A_BLT<24> A_BLT_TOP<25> A_BLT_TOP<24> A_IWL<6143> A_IWL<6142> A_IWL<6141> A_IWL<6140> A_IWL<6139> A_IWL<6138> A_IWL<6137> A_IWL<6136> A_IWL<6135> A_IWL<6134> A_IWL<6133> A_IWL<6132> A_IWL<6131> A_IWL<6130> A_IWL<6129> A_IWL<6128> A_IWL<6127> A_IWL<6126> A_IWL<6125> A_IWL<6124> A_IWL<6123> A_IWL<6122> A_IWL<6121> A_IWL<6120> A_IWL<6119> A_IWL<6118> A_IWL<6117> A_IWL<6116> A_IWL<6115> A_IWL<6114> A_IWL<6113> A_IWL<6112> A_IWL<6111> A_IWL<6110> A_IWL<6109> A_IWL<6108> A_IWL<6107> A_IWL<6106> A_IWL<6105> A_IWL<6104> A_IWL<6103> A_IWL<6102> A_IWL<6101> A_IWL<6100> A_IWL<6099> A_IWL<6098> A_IWL<6097> A_IWL<6096> A_IWL<6095> A_IWL<6094> A_IWL<6093> A_IWL<6092> A_IWL<6091> A_IWL<6090> A_IWL<6089> A_IWL<6088> A_IWL<6087> A_IWL<6086> A_IWL<6085> A_IWL<6084> A_IWL<6083> A_IWL<6082> A_IWL<6081> A_IWL<6080> A_IWL<6079> A_IWL<6078> A_IWL<6077> A_IWL<6076> A_IWL<6075> A_IWL<6074> A_IWL<6073> A_IWL<6072> A_IWL<6071> A_IWL<6070> A_IWL<6069> A_IWL<6068> A_IWL<6067> A_IWL<6066> A_IWL<6065> A_IWL<6064> A_IWL<6063> A_IWL<6062> A_IWL<6061> A_IWL<6060> A_IWL<6059> A_IWL<6058> A_IWL<6057> A_IWL<6056> A_IWL<6055> A_IWL<6054> A_IWL<6053> A_IWL<6052> A_IWL<6051> A_IWL<6050> A_IWL<6049> A_IWL<6048> A_IWL<6047> A_IWL<6046> A_IWL<6045> A_IWL<6044> A_IWL<6043> A_IWL<6042> A_IWL<6041> A_IWL<6040> A_IWL<6039> A_IWL<6038> A_IWL<6037> A_IWL<6036> A_IWL<6035> A_IWL<6034> A_IWL<6033> A_IWL<6032> A_IWL<6031> A_IWL<6030> A_IWL<6029> A_IWL<6028> A_IWL<6027> A_IWL<6026> A_IWL<6025> A_IWL<6024> A_IWL<6023> A_IWL<6022> A_IWL<6021> A_IWL<6020> A_IWL<6019> A_IWL<6018> A_IWL<6017> A_IWL<6016> A_IWL<6015> A_IWL<6014> A_IWL<6013> A_IWL<6012> A_IWL<6011> A_IWL<6010> A_IWL<6009> A_IWL<6008> A_IWL<6007> A_IWL<6006> A_IWL<6005> A_IWL<6004> A_IWL<6003> A_IWL<6002> A_IWL<6001> A_IWL<6000> A_IWL<5999> A_IWL<5998> A_IWL<5997> A_IWL<5996> A_IWL<5995> A_IWL<5994> A_IWL<5993> A_IWL<5992> A_IWL<5991> A_IWL<5990> A_IWL<5989> A_IWL<5988> A_IWL<5987> A_IWL<5986> A_IWL<5985> A_IWL<5984> A_IWL<5983> A_IWL<5982> A_IWL<5981> A_IWL<5980> A_IWL<5979> A_IWL<5978> A_IWL<5977> A_IWL<5976> A_IWL<5975> A_IWL<5974> A_IWL<5973> A_IWL<5972> A_IWL<5971> A_IWL<5970> A_IWL<5969> A_IWL<5968> A_IWL<5967> A_IWL<5966> A_IWL<5965> A_IWL<5964> A_IWL<5963> A_IWL<5962> A_IWL<5961> A_IWL<5960> A_IWL<5959> A_IWL<5958> A_IWL<5957> A_IWL<5956> A_IWL<5955> A_IWL<5954> A_IWL<5953> A_IWL<5952> A_IWL<5951> A_IWL<5950> A_IWL<5949> A_IWL<5948> A_IWL<5947> A_IWL<5946> A_IWL<5945> A_IWL<5944> A_IWL<5943> A_IWL<5942> A_IWL<5941> A_IWL<5940> A_IWL<5939> A_IWL<5938> A_IWL<5937> A_IWL<5936> A_IWL<5935> A_IWL<5934> A_IWL<5933> A_IWL<5932> A_IWL<5931> A_IWL<5930> A_IWL<5929> A_IWL<5928> A_IWL<5927> A_IWL<5926> A_IWL<5925> A_IWL<5924> A_IWL<5923> A_IWL<5922> A_IWL<5921> A_IWL<5920> A_IWL<5919> A_IWL<5918> A_IWL<5917> A_IWL<5916> A_IWL<5915> A_IWL<5914> A_IWL<5913> A_IWL<5912> A_IWL<5911> A_IWL<5910> A_IWL<5909> A_IWL<5908> A_IWL<5907> A_IWL<5906> A_IWL<5905> A_IWL<5904> A_IWL<5903> A_IWL<5902> A_IWL<5901> A_IWL<5900> A_IWL<5899> A_IWL<5898> A_IWL<5897> A_IWL<5896> A_IWL<5895> A_IWL<5894> A_IWL<5893> A_IWL<5892> A_IWL<5891> A_IWL<5890> A_IWL<5889> A_IWL<5888> A_IWL<5887> A_IWL<5886> A_IWL<5885> A_IWL<5884> A_IWL<5883> A_IWL<5882> A_IWL<5881> A_IWL<5880> A_IWL<5879> A_IWL<5878> A_IWL<5877> A_IWL<5876> A_IWL<5875> A_IWL<5874> A_IWL<5873> A_IWL<5872> A_IWL<5871> A_IWL<5870> A_IWL<5869> A_IWL<5868> A_IWL<5867> A_IWL<5866> A_IWL<5865> A_IWL<5864> A_IWL<5863> A_IWL<5862> A_IWL<5861> A_IWL<5860> A_IWL<5859> A_IWL<5858> A_IWL<5857> A_IWL<5856> A_IWL<5855> A_IWL<5854> A_IWL<5853> A_IWL<5852> A_IWL<5851> A_IWL<5850> A_IWL<5849> A_IWL<5848> A_IWL<5847> A_IWL<5846> A_IWL<5845> A_IWL<5844> A_IWL<5843> A_IWL<5842> A_IWL<5841> A_IWL<5840> A_IWL<5839> A_IWL<5838> A_IWL<5837> A_IWL<5836> A_IWL<5835> A_IWL<5834> A_IWL<5833> A_IWL<5832> A_IWL<5831> A_IWL<5830> A_IWL<5829> A_IWL<5828> A_IWL<5827> A_IWL<5826> A_IWL<5825> A_IWL<5824> A_IWL<5823> A_IWL<5822> A_IWL<5821> A_IWL<5820> A_IWL<5819> A_IWL<5818> A_IWL<5817> A_IWL<5816> A_IWL<5815> A_IWL<5814> A_IWL<5813> A_IWL<5812> A_IWL<5811> A_IWL<5810> A_IWL<5809> A_IWL<5808> A_IWL<5807> A_IWL<5806> A_IWL<5805> A_IWL<5804> A_IWL<5803> A_IWL<5802> A_IWL<5801> A_IWL<5800> A_IWL<5799> A_IWL<5798> A_IWL<5797> A_IWL<5796> A_IWL<5795> A_IWL<5794> A_IWL<5793> A_IWL<5792> A_IWL<5791> A_IWL<5790> A_IWL<5789> A_IWL<5788> A_IWL<5787> A_IWL<5786> A_IWL<5785> A_IWL<5784> A_IWL<5783> A_IWL<5782> A_IWL<5781> A_IWL<5780> A_IWL<5779> A_IWL<5778> A_IWL<5777> A_IWL<5776> A_IWL<5775> A_IWL<5774> A_IWL<5773> A_IWL<5772> A_IWL<5771> A_IWL<5770> A_IWL<5769> A_IWL<5768> A_IWL<5767> A_IWL<5766> A_IWL<5765> A_IWL<5764> A_IWL<5763> A_IWL<5762> A_IWL<5761> A_IWL<5760> A_IWL<5759> A_IWL<5758> A_IWL<5757> A_IWL<5756> A_IWL<5755> A_IWL<5754> A_IWL<5753> A_IWL<5752> A_IWL<5751> A_IWL<5750> A_IWL<5749> A_IWL<5748> A_IWL<5747> A_IWL<5746> A_IWL<5745> A_IWL<5744> A_IWL<5743> A_IWL<5742> A_IWL<5741> A_IWL<5740> A_IWL<5739> A_IWL<5738> A_IWL<5737> A_IWL<5736> A_IWL<5735> A_IWL<5734> A_IWL<5733> A_IWL<5732> A_IWL<5731> A_IWL<5730> A_IWL<5729> A_IWL<5728> A_IWL<5727> A_IWL<5726> A_IWL<5725> A_IWL<5724> A_IWL<5723> A_IWL<5722> A_IWL<5721> A_IWL<5720> A_IWL<5719> A_IWL<5718> A_IWL<5717> A_IWL<5716> A_IWL<5715> A_IWL<5714> A_IWL<5713> A_IWL<5712> A_IWL<5711> A_IWL<5710> A_IWL<5709> A_IWL<5708> A_IWL<5707> A_IWL<5706> A_IWL<5705> A_IWL<5704> A_IWL<5703> A_IWL<5702> A_IWL<5701> A_IWL<5700> A_IWL<5699> A_IWL<5698> A_IWL<5697> A_IWL<5696> A_IWL<5695> A_IWL<5694> A_IWL<5693> A_IWL<5692> A_IWL<5691> A_IWL<5690> A_IWL<5689> A_IWL<5688> A_IWL<5687> A_IWL<5686> A_IWL<5685> A_IWL<5684> A_IWL<5683> A_IWL<5682> A_IWL<5681> A_IWL<5680> A_IWL<5679> A_IWL<5678> A_IWL<5677> A_IWL<5676> A_IWL<5675> A_IWL<5674> A_IWL<5673> A_IWL<5672> A_IWL<5671> A_IWL<5670> A_IWL<5669> A_IWL<5668> A_IWL<5667> A_IWL<5666> A_IWL<5665> A_IWL<5664> A_IWL<5663> A_IWL<5662> A_IWL<5661> A_IWL<5660> A_IWL<5659> A_IWL<5658> A_IWL<5657> A_IWL<5656> A_IWL<5655> A_IWL<5654> A_IWL<5653> A_IWL<5652> A_IWL<5651> A_IWL<5650> A_IWL<5649> A_IWL<5648> A_IWL<5647> A_IWL<5646> A_IWL<5645> A_IWL<5644> A_IWL<5643> A_IWL<5642> A_IWL<5641> A_IWL<5640> A_IWL<5639> A_IWL<5638> A_IWL<5637> A_IWL<5636> A_IWL<5635> A_IWL<5634> A_IWL<5633> A_IWL<5632> A_IWL<6655> A_IWL<6654> A_IWL<6653> A_IWL<6652> A_IWL<6651> A_IWL<6650> A_IWL<6649> A_IWL<6648> A_IWL<6647> A_IWL<6646> A_IWL<6645> A_IWL<6644> A_IWL<6643> A_IWL<6642> A_IWL<6641> A_IWL<6640> A_IWL<6639> A_IWL<6638> A_IWL<6637> A_IWL<6636> A_IWL<6635> A_IWL<6634> A_IWL<6633> A_IWL<6632> A_IWL<6631> A_IWL<6630> A_IWL<6629> A_IWL<6628> A_IWL<6627> A_IWL<6626> A_IWL<6625> A_IWL<6624> A_IWL<6623> A_IWL<6622> A_IWL<6621> A_IWL<6620> A_IWL<6619> A_IWL<6618> A_IWL<6617> A_IWL<6616> A_IWL<6615> A_IWL<6614> A_IWL<6613> A_IWL<6612> A_IWL<6611> A_IWL<6610> A_IWL<6609> A_IWL<6608> A_IWL<6607> A_IWL<6606> A_IWL<6605> A_IWL<6604> A_IWL<6603> A_IWL<6602> A_IWL<6601> A_IWL<6600> A_IWL<6599> A_IWL<6598> A_IWL<6597> A_IWL<6596> A_IWL<6595> A_IWL<6594> A_IWL<6593> A_IWL<6592> A_IWL<6591> A_IWL<6590> A_IWL<6589> A_IWL<6588> A_IWL<6587> A_IWL<6586> A_IWL<6585> A_IWL<6584> A_IWL<6583> A_IWL<6582> A_IWL<6581> A_IWL<6580> A_IWL<6579> A_IWL<6578> A_IWL<6577> A_IWL<6576> A_IWL<6575> A_IWL<6574> A_IWL<6573> A_IWL<6572> A_IWL<6571> A_IWL<6570> A_IWL<6569> A_IWL<6568> A_IWL<6567> A_IWL<6566> A_IWL<6565> A_IWL<6564> A_IWL<6563> A_IWL<6562> A_IWL<6561> A_IWL<6560> A_IWL<6559> A_IWL<6558> A_IWL<6557> A_IWL<6556> A_IWL<6555> A_IWL<6554> A_IWL<6553> A_IWL<6552> A_IWL<6551> A_IWL<6550> A_IWL<6549> A_IWL<6548> A_IWL<6547> A_IWL<6546> A_IWL<6545> A_IWL<6544> A_IWL<6543> A_IWL<6542> A_IWL<6541> A_IWL<6540> A_IWL<6539> A_IWL<6538> A_IWL<6537> A_IWL<6536> A_IWL<6535> A_IWL<6534> A_IWL<6533> A_IWL<6532> A_IWL<6531> A_IWL<6530> A_IWL<6529> A_IWL<6528> A_IWL<6527> A_IWL<6526> A_IWL<6525> A_IWL<6524> A_IWL<6523> A_IWL<6522> A_IWL<6521> A_IWL<6520> A_IWL<6519> A_IWL<6518> A_IWL<6517> A_IWL<6516> A_IWL<6515> A_IWL<6514> A_IWL<6513> A_IWL<6512> A_IWL<6511> A_IWL<6510> A_IWL<6509> A_IWL<6508> A_IWL<6507> A_IWL<6506> A_IWL<6505> A_IWL<6504> A_IWL<6503> A_IWL<6502> A_IWL<6501> A_IWL<6500> A_IWL<6499> A_IWL<6498> A_IWL<6497> A_IWL<6496> A_IWL<6495> A_IWL<6494> A_IWL<6493> A_IWL<6492> A_IWL<6491> A_IWL<6490> A_IWL<6489> A_IWL<6488> A_IWL<6487> A_IWL<6486> A_IWL<6485> A_IWL<6484> A_IWL<6483> A_IWL<6482> A_IWL<6481> A_IWL<6480> A_IWL<6479> A_IWL<6478> A_IWL<6477> A_IWL<6476> A_IWL<6475> A_IWL<6474> A_IWL<6473> A_IWL<6472> A_IWL<6471> A_IWL<6470> A_IWL<6469> A_IWL<6468> A_IWL<6467> A_IWL<6466> A_IWL<6465> A_IWL<6464> A_IWL<6463> A_IWL<6462> A_IWL<6461> A_IWL<6460> A_IWL<6459> A_IWL<6458> A_IWL<6457> A_IWL<6456> A_IWL<6455> A_IWL<6454> A_IWL<6453> A_IWL<6452> A_IWL<6451> A_IWL<6450> A_IWL<6449> A_IWL<6448> A_IWL<6447> A_IWL<6446> A_IWL<6445> A_IWL<6444> A_IWL<6443> A_IWL<6442> A_IWL<6441> A_IWL<6440> A_IWL<6439> A_IWL<6438> A_IWL<6437> A_IWL<6436> A_IWL<6435> A_IWL<6434> A_IWL<6433> A_IWL<6432> A_IWL<6431> A_IWL<6430> A_IWL<6429> A_IWL<6428> A_IWL<6427> A_IWL<6426> A_IWL<6425> A_IWL<6424> A_IWL<6423> A_IWL<6422> A_IWL<6421> A_IWL<6420> A_IWL<6419> A_IWL<6418> A_IWL<6417> A_IWL<6416> A_IWL<6415> A_IWL<6414> A_IWL<6413> A_IWL<6412> A_IWL<6411> A_IWL<6410> A_IWL<6409> A_IWL<6408> A_IWL<6407> A_IWL<6406> A_IWL<6405> A_IWL<6404> A_IWL<6403> A_IWL<6402> A_IWL<6401> A_IWL<6400> A_IWL<6399> A_IWL<6398> A_IWL<6397> A_IWL<6396> A_IWL<6395> A_IWL<6394> A_IWL<6393> A_IWL<6392> A_IWL<6391> A_IWL<6390> A_IWL<6389> A_IWL<6388> A_IWL<6387> A_IWL<6386> A_IWL<6385> A_IWL<6384> A_IWL<6383> A_IWL<6382> A_IWL<6381> A_IWL<6380> A_IWL<6379> A_IWL<6378> A_IWL<6377> A_IWL<6376> A_IWL<6375> A_IWL<6374> A_IWL<6373> A_IWL<6372> A_IWL<6371> A_IWL<6370> A_IWL<6369> A_IWL<6368> A_IWL<6367> A_IWL<6366> A_IWL<6365> A_IWL<6364> A_IWL<6363> A_IWL<6362> A_IWL<6361> A_IWL<6360> A_IWL<6359> A_IWL<6358> A_IWL<6357> A_IWL<6356> A_IWL<6355> A_IWL<6354> A_IWL<6353> A_IWL<6352> A_IWL<6351> A_IWL<6350> A_IWL<6349> A_IWL<6348> A_IWL<6347> A_IWL<6346> A_IWL<6345> A_IWL<6344> A_IWL<6343> A_IWL<6342> A_IWL<6341> A_IWL<6340> A_IWL<6339> A_IWL<6338> A_IWL<6337> A_IWL<6336> A_IWL<6335> A_IWL<6334> A_IWL<6333> A_IWL<6332> A_IWL<6331> A_IWL<6330> A_IWL<6329> A_IWL<6328> A_IWL<6327> A_IWL<6326> A_IWL<6325> A_IWL<6324> A_IWL<6323> A_IWL<6322> A_IWL<6321> A_IWL<6320> A_IWL<6319> A_IWL<6318> A_IWL<6317> A_IWL<6316> A_IWL<6315> A_IWL<6314> A_IWL<6313> A_IWL<6312> A_IWL<6311> A_IWL<6310> A_IWL<6309> A_IWL<6308> A_IWL<6307> A_IWL<6306> A_IWL<6305> A_IWL<6304> A_IWL<6303> A_IWL<6302> A_IWL<6301> A_IWL<6300> A_IWL<6299> A_IWL<6298> A_IWL<6297> A_IWL<6296> A_IWL<6295> A_IWL<6294> A_IWL<6293> A_IWL<6292> A_IWL<6291> A_IWL<6290> A_IWL<6289> A_IWL<6288> A_IWL<6287> A_IWL<6286> A_IWL<6285> A_IWL<6284> A_IWL<6283> A_IWL<6282> A_IWL<6281> A_IWL<6280> A_IWL<6279> A_IWL<6278> A_IWL<6277> A_IWL<6276> A_IWL<6275> A_IWL<6274> A_IWL<6273> A_IWL<6272> A_IWL<6271> A_IWL<6270> A_IWL<6269> A_IWL<6268> A_IWL<6267> A_IWL<6266> A_IWL<6265> A_IWL<6264> A_IWL<6263> A_IWL<6262> A_IWL<6261> A_IWL<6260> A_IWL<6259> A_IWL<6258> A_IWL<6257> A_IWL<6256> A_IWL<6255> A_IWL<6254> A_IWL<6253> A_IWL<6252> A_IWL<6251> A_IWL<6250> A_IWL<6249> A_IWL<6248> A_IWL<6247> A_IWL<6246> A_IWL<6245> A_IWL<6244> A_IWL<6243> A_IWL<6242> A_IWL<6241> A_IWL<6240> A_IWL<6239> A_IWL<6238> A_IWL<6237> A_IWL<6236> A_IWL<6235> A_IWL<6234> A_IWL<6233> A_IWL<6232> A_IWL<6231> A_IWL<6230> A_IWL<6229> A_IWL<6228> A_IWL<6227> A_IWL<6226> A_IWL<6225> A_IWL<6224> A_IWL<6223> A_IWL<6222> A_IWL<6221> A_IWL<6220> A_IWL<6219> A_IWL<6218> A_IWL<6217> A_IWL<6216> A_IWL<6215> A_IWL<6214> A_IWL<6213> A_IWL<6212> A_IWL<6211> A_IWL<6210> A_IWL<6209> A_IWL<6208> A_IWL<6207> A_IWL<6206> A_IWL<6205> A_IWL<6204> A_IWL<6203> A_IWL<6202> A_IWL<6201> A_IWL<6200> A_IWL<6199> A_IWL<6198> A_IWL<6197> A_IWL<6196> A_IWL<6195> A_IWL<6194> A_IWL<6193> A_IWL<6192> A_IWL<6191> A_IWL<6190> A_IWL<6189> A_IWL<6188> A_IWL<6187> A_IWL<6186> A_IWL<6185> A_IWL<6184> A_IWL<6183> A_IWL<6182> A_IWL<6181> A_IWL<6180> A_IWL<6179> A_IWL<6178> A_IWL<6177> A_IWL<6176> A_IWL<6175> A_IWL<6174> A_IWL<6173> A_IWL<6172> A_IWL<6171> A_IWL<6170> A_IWL<6169> A_IWL<6168> A_IWL<6167> A_IWL<6166> A_IWL<6165> A_IWL<6164> A_IWL<6163> A_IWL<6162> A_IWL<6161> A_IWL<6160> A_IWL<6159> A_IWL<6158> A_IWL<6157> A_IWL<6156> A_IWL<6155> A_IWL<6154> A_IWL<6153> A_IWL<6152> A_IWL<6151> A_IWL<6150> A_IWL<6149> A_IWL<6148> A_IWL<6147> A_IWL<6146> A_IWL<6145> A_IWL<6144> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0
+XCOL<11> A_BLC<23> A_BLC<22> A_BLC_TOP<23> A_BLC_TOP<22> A_BLT<23> A_BLT<22> A_BLT_TOP<23> A_BLT_TOP<22> A_IWL<5631> A_IWL<5630> A_IWL<5629> A_IWL<5628> A_IWL<5627> A_IWL<5626> A_IWL<5625> A_IWL<5624> A_IWL<5623> A_IWL<5622> A_IWL<5621> A_IWL<5620> A_IWL<5619> A_IWL<5618> A_IWL<5617> A_IWL<5616> A_IWL<5615> A_IWL<5614> A_IWL<5613> A_IWL<5612> A_IWL<5611> A_IWL<5610> A_IWL<5609> A_IWL<5608> A_IWL<5607> A_IWL<5606> A_IWL<5605> A_IWL<5604> A_IWL<5603> A_IWL<5602> A_IWL<5601> A_IWL<5600> A_IWL<5599> A_IWL<5598> A_IWL<5597> A_IWL<5596> A_IWL<5595> A_IWL<5594> A_IWL<5593> A_IWL<5592> A_IWL<5591> A_IWL<5590> A_IWL<5589> A_IWL<5588> A_IWL<5587> A_IWL<5586> A_IWL<5585> A_IWL<5584> A_IWL<5583> A_IWL<5582> A_IWL<5581> A_IWL<5580> A_IWL<5579> A_IWL<5578> A_IWL<5577> A_IWL<5576> A_IWL<5575> A_IWL<5574> A_IWL<5573> A_IWL<5572> A_IWL<5571> A_IWL<5570> A_IWL<5569> A_IWL<5568> A_IWL<5567> A_IWL<5566> A_IWL<5565> A_IWL<5564> A_IWL<5563> A_IWL<5562> A_IWL<5561> A_IWL<5560> A_IWL<5559> A_IWL<5558> A_IWL<5557> A_IWL<5556> A_IWL<5555> A_IWL<5554> A_IWL<5553> A_IWL<5552> A_IWL<5551> A_IWL<5550> A_IWL<5549> A_IWL<5548> A_IWL<5547> A_IWL<5546> A_IWL<5545> A_IWL<5544> A_IWL<5543> A_IWL<5542> A_IWL<5541> A_IWL<5540> A_IWL<5539> A_IWL<5538> A_IWL<5537> A_IWL<5536> A_IWL<5535> A_IWL<5534> A_IWL<5533> A_IWL<5532> A_IWL<5531> A_IWL<5530> A_IWL<5529> A_IWL<5528> A_IWL<5527> A_IWL<5526> A_IWL<5525> A_IWL<5524> A_IWL<5523> A_IWL<5522> A_IWL<5521> A_IWL<5520> A_IWL<5519> A_IWL<5518> A_IWL<5517> A_IWL<5516> A_IWL<5515> A_IWL<5514> A_IWL<5513> A_IWL<5512> A_IWL<5511> A_IWL<5510> A_IWL<5509> A_IWL<5508> A_IWL<5507> A_IWL<5506> A_IWL<5505> A_IWL<5504> A_IWL<5503> A_IWL<5502> A_IWL<5501> A_IWL<5500> A_IWL<5499> A_IWL<5498> A_IWL<5497> A_IWL<5496> A_IWL<5495> A_IWL<5494> A_IWL<5493> A_IWL<5492> A_IWL<5491> A_IWL<5490> A_IWL<5489> A_IWL<5488> A_IWL<5487> A_IWL<5486> A_IWL<5485> A_IWL<5484> A_IWL<5483> A_IWL<5482> A_IWL<5481> A_IWL<5480> A_IWL<5479> A_IWL<5478> A_IWL<5477> A_IWL<5476> A_IWL<5475> A_IWL<5474> A_IWL<5473> A_IWL<5472> A_IWL<5471> A_IWL<5470> A_IWL<5469> A_IWL<5468> A_IWL<5467> A_IWL<5466> A_IWL<5465> A_IWL<5464> A_IWL<5463> A_IWL<5462> A_IWL<5461> A_IWL<5460> A_IWL<5459> A_IWL<5458> A_IWL<5457> A_IWL<5456> A_IWL<5455> A_IWL<5454> A_IWL<5453> A_IWL<5452> A_IWL<5451> A_IWL<5450> A_IWL<5449> A_IWL<5448> A_IWL<5447> A_IWL<5446> A_IWL<5445> A_IWL<5444> A_IWL<5443> A_IWL<5442> A_IWL<5441> A_IWL<5440> A_IWL<5439> A_IWL<5438> A_IWL<5437> A_IWL<5436> A_IWL<5435> A_IWL<5434> A_IWL<5433> A_IWL<5432> A_IWL<5431> A_IWL<5430> A_IWL<5429> A_IWL<5428> A_IWL<5427> A_IWL<5426> A_IWL<5425> A_IWL<5424> A_IWL<5423> A_IWL<5422> A_IWL<5421> A_IWL<5420> A_IWL<5419> A_IWL<5418> A_IWL<5417> A_IWL<5416> A_IWL<5415> A_IWL<5414> A_IWL<5413> A_IWL<5412> A_IWL<5411> A_IWL<5410> A_IWL<5409> A_IWL<5408> A_IWL<5407> A_IWL<5406> A_IWL<5405> A_IWL<5404> A_IWL<5403> A_IWL<5402> A_IWL<5401> A_IWL<5400> A_IWL<5399> A_IWL<5398> A_IWL<5397> A_IWL<5396> A_IWL<5395> A_IWL<5394> A_IWL<5393> A_IWL<5392> A_IWL<5391> A_IWL<5390> A_IWL<5389> A_IWL<5388> A_IWL<5387> A_IWL<5386> A_IWL<5385> A_IWL<5384> A_IWL<5383> A_IWL<5382> A_IWL<5381> A_IWL<5380> A_IWL<5379> A_IWL<5378> A_IWL<5377> A_IWL<5376> A_IWL<5375> A_IWL<5374> A_IWL<5373> A_IWL<5372> A_IWL<5371> A_IWL<5370> A_IWL<5369> A_IWL<5368> A_IWL<5367> A_IWL<5366> A_IWL<5365> A_IWL<5364> A_IWL<5363> A_IWL<5362> A_IWL<5361> A_IWL<5360> A_IWL<5359> A_IWL<5358> A_IWL<5357> A_IWL<5356> A_IWL<5355> A_IWL<5354> A_IWL<5353> A_IWL<5352> A_IWL<5351> A_IWL<5350> A_IWL<5349> A_IWL<5348> A_IWL<5347> A_IWL<5346> A_IWL<5345> A_IWL<5344> A_IWL<5343> A_IWL<5342> A_IWL<5341> A_IWL<5340> A_IWL<5339> A_IWL<5338> A_IWL<5337> A_IWL<5336> A_IWL<5335> A_IWL<5334> A_IWL<5333> A_IWL<5332> A_IWL<5331> A_IWL<5330> A_IWL<5329> A_IWL<5328> A_IWL<5327> A_IWL<5326> A_IWL<5325> A_IWL<5324> A_IWL<5323> A_IWL<5322> A_IWL<5321> A_IWL<5320> A_IWL<5319> A_IWL<5318> A_IWL<5317> A_IWL<5316> A_IWL<5315> A_IWL<5314> A_IWL<5313> A_IWL<5312> A_IWL<5311> A_IWL<5310> A_IWL<5309> A_IWL<5308> A_IWL<5307> A_IWL<5306> A_IWL<5305> A_IWL<5304> A_IWL<5303> A_IWL<5302> A_IWL<5301> A_IWL<5300> A_IWL<5299> A_IWL<5298> A_IWL<5297> A_IWL<5296> A_IWL<5295> A_IWL<5294> A_IWL<5293> A_IWL<5292> A_IWL<5291> A_IWL<5290> A_IWL<5289> A_IWL<5288> A_IWL<5287> A_IWL<5286> A_IWL<5285> A_IWL<5284> A_IWL<5283> A_IWL<5282> A_IWL<5281> A_IWL<5280> A_IWL<5279> A_IWL<5278> A_IWL<5277> A_IWL<5276> A_IWL<5275> A_IWL<5274> A_IWL<5273> A_IWL<5272> A_IWL<5271> A_IWL<5270> A_IWL<5269> A_IWL<5268> A_IWL<5267> A_IWL<5266> A_IWL<5265> A_IWL<5264> A_IWL<5263> A_IWL<5262> A_IWL<5261> A_IWL<5260> A_IWL<5259> A_IWL<5258> A_IWL<5257> A_IWL<5256> A_IWL<5255> A_IWL<5254> A_IWL<5253> A_IWL<5252> A_IWL<5251> A_IWL<5250> A_IWL<5249> A_IWL<5248> A_IWL<5247> A_IWL<5246> A_IWL<5245> A_IWL<5244> A_IWL<5243> A_IWL<5242> A_IWL<5241> A_IWL<5240> A_IWL<5239> A_IWL<5238> A_IWL<5237> A_IWL<5236> A_IWL<5235> A_IWL<5234> A_IWL<5233> A_IWL<5232> A_IWL<5231> A_IWL<5230> A_IWL<5229> A_IWL<5228> A_IWL<5227> A_IWL<5226> A_IWL<5225> A_IWL<5224> A_IWL<5223> A_IWL<5222> A_IWL<5221> A_IWL<5220> A_IWL<5219> A_IWL<5218> A_IWL<5217> A_IWL<5216> A_IWL<5215> A_IWL<5214> A_IWL<5213> A_IWL<5212> A_IWL<5211> A_IWL<5210> A_IWL<5209> A_IWL<5208> A_IWL<5207> A_IWL<5206> A_IWL<5205> A_IWL<5204> A_IWL<5203> A_IWL<5202> A_IWL<5201> A_IWL<5200> A_IWL<5199> A_IWL<5198> A_IWL<5197> A_IWL<5196> A_IWL<5195> A_IWL<5194> A_IWL<5193> A_IWL<5192> A_IWL<5191> A_IWL<5190> A_IWL<5189> A_IWL<5188> A_IWL<5187> A_IWL<5186> A_IWL<5185> A_IWL<5184> A_IWL<5183> A_IWL<5182> A_IWL<5181> A_IWL<5180> A_IWL<5179> A_IWL<5178> A_IWL<5177> A_IWL<5176> A_IWL<5175> A_IWL<5174> A_IWL<5173> A_IWL<5172> A_IWL<5171> A_IWL<5170> A_IWL<5169> A_IWL<5168> A_IWL<5167> A_IWL<5166> A_IWL<5165> A_IWL<5164> A_IWL<5163> A_IWL<5162> A_IWL<5161> A_IWL<5160> A_IWL<5159> A_IWL<5158> A_IWL<5157> A_IWL<5156> A_IWL<5155> A_IWL<5154> A_IWL<5153> A_IWL<5152> A_IWL<5151> A_IWL<5150> A_IWL<5149> A_IWL<5148> A_IWL<5147> A_IWL<5146> A_IWL<5145> A_IWL<5144> A_IWL<5143> A_IWL<5142> A_IWL<5141> A_IWL<5140> A_IWL<5139> A_IWL<5138> A_IWL<5137> A_IWL<5136> A_IWL<5135> A_IWL<5134> A_IWL<5133> A_IWL<5132> A_IWL<5131> A_IWL<5130> A_IWL<5129> A_IWL<5128> A_IWL<5127> A_IWL<5126> A_IWL<5125> A_IWL<5124> A_IWL<5123> A_IWL<5122> A_IWL<5121> A_IWL<5120> A_IWL<6143> A_IWL<6142> A_IWL<6141> A_IWL<6140> A_IWL<6139> A_IWL<6138> A_IWL<6137> A_IWL<6136> A_IWL<6135> A_IWL<6134> A_IWL<6133> A_IWL<6132> A_IWL<6131> A_IWL<6130> A_IWL<6129> A_IWL<6128> A_IWL<6127> A_IWL<6126> A_IWL<6125> A_IWL<6124> A_IWL<6123> A_IWL<6122> A_IWL<6121> A_IWL<6120> A_IWL<6119> A_IWL<6118> A_IWL<6117> A_IWL<6116> A_IWL<6115> A_IWL<6114> A_IWL<6113> A_IWL<6112> A_IWL<6111> A_IWL<6110> A_IWL<6109> A_IWL<6108> A_IWL<6107> A_IWL<6106> A_IWL<6105> A_IWL<6104> A_IWL<6103> A_IWL<6102> A_IWL<6101> A_IWL<6100> A_IWL<6099> A_IWL<6098> A_IWL<6097> A_IWL<6096> A_IWL<6095> A_IWL<6094> A_IWL<6093> A_IWL<6092> A_IWL<6091> A_IWL<6090> A_IWL<6089> A_IWL<6088> A_IWL<6087> A_IWL<6086> A_IWL<6085> A_IWL<6084> A_IWL<6083> A_IWL<6082> A_IWL<6081> A_IWL<6080> A_IWL<6079> A_IWL<6078> A_IWL<6077> A_IWL<6076> A_IWL<6075> A_IWL<6074> A_IWL<6073> A_IWL<6072> A_IWL<6071> A_IWL<6070> A_IWL<6069> A_IWL<6068> A_IWL<6067> A_IWL<6066> A_IWL<6065> A_IWL<6064> A_IWL<6063> A_IWL<6062> A_IWL<6061> A_IWL<6060> A_IWL<6059> A_IWL<6058> A_IWL<6057> A_IWL<6056> A_IWL<6055> A_IWL<6054> A_IWL<6053> A_IWL<6052> A_IWL<6051> A_IWL<6050> A_IWL<6049> A_IWL<6048> A_IWL<6047> A_IWL<6046> A_IWL<6045> A_IWL<6044> A_IWL<6043> A_IWL<6042> A_IWL<6041> A_IWL<6040> A_IWL<6039> A_IWL<6038> A_IWL<6037> A_IWL<6036> A_IWL<6035> A_IWL<6034> A_IWL<6033> A_IWL<6032> A_IWL<6031> A_IWL<6030> A_IWL<6029> A_IWL<6028> A_IWL<6027> A_IWL<6026> A_IWL<6025> A_IWL<6024> A_IWL<6023> A_IWL<6022> A_IWL<6021> A_IWL<6020> A_IWL<6019> A_IWL<6018> A_IWL<6017> A_IWL<6016> A_IWL<6015> A_IWL<6014> A_IWL<6013> A_IWL<6012> A_IWL<6011> A_IWL<6010> A_IWL<6009> A_IWL<6008> A_IWL<6007> A_IWL<6006> A_IWL<6005> A_IWL<6004> A_IWL<6003> A_IWL<6002> A_IWL<6001> A_IWL<6000> A_IWL<5999> A_IWL<5998> A_IWL<5997> A_IWL<5996> A_IWL<5995> A_IWL<5994> A_IWL<5993> A_IWL<5992> A_IWL<5991> A_IWL<5990> A_IWL<5989> A_IWL<5988> A_IWL<5987> A_IWL<5986> A_IWL<5985> A_IWL<5984> A_IWL<5983> A_IWL<5982> A_IWL<5981> A_IWL<5980> A_IWL<5979> A_IWL<5978> A_IWL<5977> A_IWL<5976> A_IWL<5975> A_IWL<5974> A_IWL<5973> A_IWL<5972> A_IWL<5971> A_IWL<5970> A_IWL<5969> A_IWL<5968> A_IWL<5967> A_IWL<5966> A_IWL<5965> A_IWL<5964> A_IWL<5963> A_IWL<5962> A_IWL<5961> A_IWL<5960> A_IWL<5959> A_IWL<5958> A_IWL<5957> A_IWL<5956> A_IWL<5955> A_IWL<5954> A_IWL<5953> A_IWL<5952> A_IWL<5951> A_IWL<5950> A_IWL<5949> A_IWL<5948> A_IWL<5947> A_IWL<5946> A_IWL<5945> A_IWL<5944> A_IWL<5943> A_IWL<5942> A_IWL<5941> A_IWL<5940> A_IWL<5939> A_IWL<5938> A_IWL<5937> A_IWL<5936> A_IWL<5935> A_IWL<5934> A_IWL<5933> A_IWL<5932> A_IWL<5931> A_IWL<5930> A_IWL<5929> A_IWL<5928> A_IWL<5927> A_IWL<5926> A_IWL<5925> A_IWL<5924> A_IWL<5923> A_IWL<5922> A_IWL<5921> A_IWL<5920> A_IWL<5919> A_IWL<5918> A_IWL<5917> A_IWL<5916> A_IWL<5915> A_IWL<5914> A_IWL<5913> A_IWL<5912> A_IWL<5911> A_IWL<5910> A_IWL<5909> A_IWL<5908> A_IWL<5907> A_IWL<5906> A_IWL<5905> A_IWL<5904> A_IWL<5903> A_IWL<5902> A_IWL<5901> A_IWL<5900> A_IWL<5899> A_IWL<5898> A_IWL<5897> A_IWL<5896> A_IWL<5895> A_IWL<5894> A_IWL<5893> A_IWL<5892> A_IWL<5891> A_IWL<5890> A_IWL<5889> A_IWL<5888> A_IWL<5887> A_IWL<5886> A_IWL<5885> A_IWL<5884> A_IWL<5883> A_IWL<5882> A_IWL<5881> A_IWL<5880> A_IWL<5879> A_IWL<5878> A_IWL<5877> A_IWL<5876> A_IWL<5875> A_IWL<5874> A_IWL<5873> A_IWL<5872> A_IWL<5871> A_IWL<5870> A_IWL<5869> A_IWL<5868> A_IWL<5867> A_IWL<5866> A_IWL<5865> A_IWL<5864> A_IWL<5863> A_IWL<5862> A_IWL<5861> A_IWL<5860> A_IWL<5859> A_IWL<5858> A_IWL<5857> A_IWL<5856> A_IWL<5855> A_IWL<5854> A_IWL<5853> A_IWL<5852> A_IWL<5851> A_IWL<5850> A_IWL<5849> A_IWL<5848> A_IWL<5847> A_IWL<5846> A_IWL<5845> A_IWL<5844> A_IWL<5843> A_IWL<5842> A_IWL<5841> A_IWL<5840> A_IWL<5839> A_IWL<5838> A_IWL<5837> A_IWL<5836> A_IWL<5835> A_IWL<5834> A_IWL<5833> A_IWL<5832> A_IWL<5831> A_IWL<5830> A_IWL<5829> A_IWL<5828> A_IWL<5827> A_IWL<5826> A_IWL<5825> A_IWL<5824> A_IWL<5823> A_IWL<5822> A_IWL<5821> A_IWL<5820> A_IWL<5819> A_IWL<5818> A_IWL<5817> A_IWL<5816> A_IWL<5815> A_IWL<5814> A_IWL<5813> A_IWL<5812> A_IWL<5811> A_IWL<5810> A_IWL<5809> A_IWL<5808> A_IWL<5807> A_IWL<5806> A_IWL<5805> A_IWL<5804> A_IWL<5803> A_IWL<5802> A_IWL<5801> A_IWL<5800> A_IWL<5799> A_IWL<5798> A_IWL<5797> A_IWL<5796> A_IWL<5795> A_IWL<5794> A_IWL<5793> A_IWL<5792> A_IWL<5791> A_IWL<5790> A_IWL<5789> A_IWL<5788> A_IWL<5787> A_IWL<5786> A_IWL<5785> A_IWL<5784> A_IWL<5783> A_IWL<5782> A_IWL<5781> A_IWL<5780> A_IWL<5779> A_IWL<5778> A_IWL<5777> A_IWL<5776> A_IWL<5775> A_IWL<5774> A_IWL<5773> A_IWL<5772> A_IWL<5771> A_IWL<5770> A_IWL<5769> A_IWL<5768> A_IWL<5767> A_IWL<5766> A_IWL<5765> A_IWL<5764> A_IWL<5763> A_IWL<5762> A_IWL<5761> A_IWL<5760> A_IWL<5759> A_IWL<5758> A_IWL<5757> A_IWL<5756> A_IWL<5755> A_IWL<5754> A_IWL<5753> A_IWL<5752> A_IWL<5751> A_IWL<5750> A_IWL<5749> A_IWL<5748> A_IWL<5747> A_IWL<5746> A_IWL<5745> A_IWL<5744> A_IWL<5743> A_IWL<5742> A_IWL<5741> A_IWL<5740> A_IWL<5739> A_IWL<5738> A_IWL<5737> A_IWL<5736> A_IWL<5735> A_IWL<5734> A_IWL<5733> A_IWL<5732> A_IWL<5731> A_IWL<5730> A_IWL<5729> A_IWL<5728> A_IWL<5727> A_IWL<5726> A_IWL<5725> A_IWL<5724> A_IWL<5723> A_IWL<5722> A_IWL<5721> A_IWL<5720> A_IWL<5719> A_IWL<5718> A_IWL<5717> A_IWL<5716> A_IWL<5715> A_IWL<5714> A_IWL<5713> A_IWL<5712> A_IWL<5711> A_IWL<5710> A_IWL<5709> A_IWL<5708> A_IWL<5707> A_IWL<5706> A_IWL<5705> A_IWL<5704> A_IWL<5703> A_IWL<5702> A_IWL<5701> A_IWL<5700> A_IWL<5699> A_IWL<5698> A_IWL<5697> A_IWL<5696> A_IWL<5695> A_IWL<5694> A_IWL<5693> A_IWL<5692> A_IWL<5691> A_IWL<5690> A_IWL<5689> A_IWL<5688> A_IWL<5687> A_IWL<5686> A_IWL<5685> A_IWL<5684> A_IWL<5683> A_IWL<5682> A_IWL<5681> A_IWL<5680> A_IWL<5679> A_IWL<5678> A_IWL<5677> A_IWL<5676> A_IWL<5675> A_IWL<5674> A_IWL<5673> A_IWL<5672> A_IWL<5671> A_IWL<5670> A_IWL<5669> A_IWL<5668> A_IWL<5667> A_IWL<5666> A_IWL<5665> A_IWL<5664> A_IWL<5663> A_IWL<5662> A_IWL<5661> A_IWL<5660> A_IWL<5659> A_IWL<5658> A_IWL<5657> A_IWL<5656> A_IWL<5655> A_IWL<5654> A_IWL<5653> A_IWL<5652> A_IWL<5651> A_IWL<5650> A_IWL<5649> A_IWL<5648> A_IWL<5647> A_IWL<5646> A_IWL<5645> A_IWL<5644> A_IWL<5643> A_IWL<5642> A_IWL<5641> A_IWL<5640> A_IWL<5639> A_IWL<5638> A_IWL<5637> A_IWL<5636> A_IWL<5635> A_IWL<5634> A_IWL<5633> A_IWL<5632> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0
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A_IWL<5156> A_IWL<5155> A_IWL<5154> A_IWL<5153> A_IWL<5152> A_IWL<5151> A_IWL<5150> A_IWL<5149> A_IWL<5148> A_IWL<5147> A_IWL<5146> A_IWL<5145> A_IWL<5144> A_IWL<5143> A_IWL<5142> A_IWL<5141> A_IWL<5140> A_IWL<5139> A_IWL<5138> A_IWL<5137> A_IWL<5136> A_IWL<5135> A_IWL<5134> A_IWL<5133> A_IWL<5132> A_IWL<5131> A_IWL<5130> A_IWL<5129> A_IWL<5128> A_IWL<5127> A_IWL<5126> A_IWL<5125> A_IWL<5124> A_IWL<5123> A_IWL<5122> A_IWL<5121> A_IWL<5120> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0
+XCOL<9> A_BLC<19> A_BLC<18> A_BLC_TOP<19> A_BLC_TOP<18> A_BLT<19> A_BLT<18> A_BLT_TOP<19> A_BLT_TOP<18> A_IWL<4607> A_IWL<4606> A_IWL<4605> A_IWL<4604> A_IWL<4603> A_IWL<4602> A_IWL<4601> A_IWL<4600> A_IWL<4599> A_IWL<4598> A_IWL<4597> A_IWL<4596> A_IWL<4595> A_IWL<4594> A_IWL<4593> A_IWL<4592> A_IWL<4591> A_IWL<4590> A_IWL<4589> A_IWL<4588> A_IWL<4587> A_IWL<4586> A_IWL<4585> A_IWL<4584> A_IWL<4583> A_IWL<4582> A_IWL<4581> A_IWL<4580> A_IWL<4579> A_IWL<4578> A_IWL<4577> A_IWL<4576> A_IWL<4575> A_IWL<4574> A_IWL<4573> A_IWL<4572> A_IWL<4571> A_IWL<4570> A_IWL<4569> A_IWL<4568> A_IWL<4567> A_IWL<4566> A_IWL<4565> A_IWL<4564> A_IWL<4563> A_IWL<4562> A_IWL<4561> A_IWL<4560> A_IWL<4559> A_IWL<4558> A_IWL<4557> A_IWL<4556> A_IWL<4555> A_IWL<4554> A_IWL<4553> A_IWL<4552> A_IWL<4551> A_IWL<4550> A_IWL<4549> A_IWL<4548> A_IWL<4547> A_IWL<4546> A_IWL<4545> A_IWL<4544> A_IWL<4543> A_IWL<4542> A_IWL<4541> A_IWL<4540> A_IWL<4539> A_IWL<4538> A_IWL<4537> A_IWL<4536> A_IWL<4535> A_IWL<4534> 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A_IWL<4118> A_IWL<4117> A_IWL<4116> A_IWL<4115> A_IWL<4114> A_IWL<4113> A_IWL<4112> A_IWL<4111> A_IWL<4110> A_IWL<4109> A_IWL<4108> A_IWL<4107> A_IWL<4106> A_IWL<4105> A_IWL<4104> A_IWL<4103> A_IWL<4102> A_IWL<4101> A_IWL<4100> A_IWL<4099> A_IWL<4098> A_IWL<4097> A_IWL<4096> A_IWL<5119> A_IWL<5118> A_IWL<5117> A_IWL<5116> A_IWL<5115> A_IWL<5114> A_IWL<5113> A_IWL<5112> A_IWL<5111> A_IWL<5110> A_IWL<5109> A_IWL<5108> A_IWL<5107> A_IWL<5106> A_IWL<5105> A_IWL<5104> A_IWL<5103> A_IWL<5102> A_IWL<5101> A_IWL<5100> A_IWL<5099> A_IWL<5098> A_IWL<5097> A_IWL<5096> A_IWL<5095> A_IWL<5094> A_IWL<5093> A_IWL<5092> A_IWL<5091> A_IWL<5090> A_IWL<5089> A_IWL<5088> A_IWL<5087> A_IWL<5086> A_IWL<5085> A_IWL<5084> A_IWL<5083> A_IWL<5082> A_IWL<5081> A_IWL<5080> A_IWL<5079> A_IWL<5078> A_IWL<5077> A_IWL<5076> A_IWL<5075> A_IWL<5074> A_IWL<5073> A_IWL<5072> A_IWL<5071> A_IWL<5070> A_IWL<5069> A_IWL<5068> A_IWL<5067> A_IWL<5066> A_IWL<5065> A_IWL<5064> A_IWL<5063> A_IWL<5062> A_IWL<5061> A_IWL<5060> A_IWL<5059> A_IWL<5058> A_IWL<5057> A_IWL<5056> A_IWL<5055> A_IWL<5054> A_IWL<5053> A_IWL<5052> A_IWL<5051> A_IWL<5050> A_IWL<5049> A_IWL<5048> A_IWL<5047> A_IWL<5046> A_IWL<5045> A_IWL<5044> A_IWL<5043> A_IWL<5042> A_IWL<5041> A_IWL<5040> A_IWL<5039> A_IWL<5038> A_IWL<5037> A_IWL<5036> A_IWL<5035> A_IWL<5034> A_IWL<5033> A_IWL<5032> A_IWL<5031> A_IWL<5030> A_IWL<5029> A_IWL<5028> A_IWL<5027> A_IWL<5026> A_IWL<5025> A_IWL<5024> A_IWL<5023> A_IWL<5022> A_IWL<5021> A_IWL<5020> A_IWL<5019> A_IWL<5018> A_IWL<5017> A_IWL<5016> A_IWL<5015> A_IWL<5014> A_IWL<5013> A_IWL<5012> A_IWL<5011> A_IWL<5010> A_IWL<5009> A_IWL<5008> A_IWL<5007> A_IWL<5006> A_IWL<5005> A_IWL<5004> A_IWL<5003> A_IWL<5002> A_IWL<5001> A_IWL<5000> A_IWL<4999> A_IWL<4998> A_IWL<4997> A_IWL<4996> A_IWL<4995> A_IWL<4994> A_IWL<4993> A_IWL<4992> A_IWL<4991> A_IWL<4990> A_IWL<4989> A_IWL<4988> A_IWL<4987> A_IWL<4986> A_IWL<4985> A_IWL<4984> A_IWL<4983> A_IWL<4982> A_IWL<4981> A_IWL<4980> A_IWL<4979> A_IWL<4978> A_IWL<4977> A_IWL<4976> A_IWL<4975> A_IWL<4974> A_IWL<4973> A_IWL<4972> A_IWL<4971> A_IWL<4970> A_IWL<4969> A_IWL<4968> A_IWL<4967> A_IWL<4966> A_IWL<4965> A_IWL<4964> A_IWL<4963> A_IWL<4962> A_IWL<4961> A_IWL<4960> A_IWL<4959> A_IWL<4958> A_IWL<4957> A_IWL<4956> A_IWL<4955> A_IWL<4954> A_IWL<4953> A_IWL<4952> A_IWL<4951> A_IWL<4950> A_IWL<4949> A_IWL<4948> A_IWL<4947> A_IWL<4946> A_IWL<4945> A_IWL<4944> A_IWL<4943> A_IWL<4942> A_IWL<4941> A_IWL<4940> A_IWL<4939> A_IWL<4938> A_IWL<4937> A_IWL<4936> A_IWL<4935> A_IWL<4934> A_IWL<4933> A_IWL<4932> A_IWL<4931> A_IWL<4930> A_IWL<4929> A_IWL<4928> A_IWL<4927> A_IWL<4926> A_IWL<4925> A_IWL<4924> A_IWL<4923> A_IWL<4922> A_IWL<4921> A_IWL<4920> A_IWL<4919> A_IWL<4918> A_IWL<4917> A_IWL<4916> A_IWL<4915> A_IWL<4914> A_IWL<4913> A_IWL<4912> A_IWL<4911> A_IWL<4910> A_IWL<4909> A_IWL<4908> A_IWL<4907> A_IWL<4906> A_IWL<4905> A_IWL<4904> A_IWL<4903> A_IWL<4902> A_IWL<4901> A_IWL<4900> A_IWL<4899> A_IWL<4898> A_IWL<4897> A_IWL<4896> A_IWL<4895> A_IWL<4894> A_IWL<4893> A_IWL<4892> A_IWL<4891> A_IWL<4890> A_IWL<4889> A_IWL<4888> A_IWL<4887> A_IWL<4886> A_IWL<4885> A_IWL<4884> A_IWL<4883> A_IWL<4882> A_IWL<4881> A_IWL<4880> A_IWL<4879> A_IWL<4878> A_IWL<4877> A_IWL<4876> A_IWL<4875> A_IWL<4874> A_IWL<4873> A_IWL<4872> A_IWL<4871> A_IWL<4870> A_IWL<4869> A_IWL<4868> A_IWL<4867> A_IWL<4866> A_IWL<4865> A_IWL<4864> A_IWL<4863> A_IWL<4862> A_IWL<4861> A_IWL<4860> A_IWL<4859> A_IWL<4858> A_IWL<4857> A_IWL<4856> A_IWL<4855> A_IWL<4854> A_IWL<4853> A_IWL<4852> A_IWL<4851> A_IWL<4850> A_IWL<4849> A_IWL<4848> A_IWL<4847> A_IWL<4846> A_IWL<4845> A_IWL<4844> A_IWL<4843> A_IWL<4842> A_IWL<4841> A_IWL<4840> A_IWL<4839> A_IWL<4838> A_IWL<4837> A_IWL<4836> A_IWL<4835> A_IWL<4834> A_IWL<4833> A_IWL<4832> A_IWL<4831> A_IWL<4830> A_IWL<4829> A_IWL<4828> A_IWL<4827> A_IWL<4826> A_IWL<4825> A_IWL<4824> A_IWL<4823> A_IWL<4822> A_IWL<4821> A_IWL<4820> A_IWL<4819> A_IWL<4818> A_IWL<4817> A_IWL<4816> A_IWL<4815> A_IWL<4814> A_IWL<4813> A_IWL<4812> A_IWL<4811> A_IWL<4810> A_IWL<4809> A_IWL<4808> A_IWL<4807> A_IWL<4806> A_IWL<4805> A_IWL<4804> A_IWL<4803> A_IWL<4802> A_IWL<4801> A_IWL<4800> A_IWL<4799> A_IWL<4798> A_IWL<4797> A_IWL<4796> A_IWL<4795> A_IWL<4794> A_IWL<4793> A_IWL<4792> A_IWL<4791> A_IWL<4790> A_IWL<4789> A_IWL<4788> A_IWL<4787> A_IWL<4786> A_IWL<4785> A_IWL<4784> A_IWL<4783> A_IWL<4782> A_IWL<4781> A_IWL<4780> A_IWL<4779> A_IWL<4778> A_IWL<4777> A_IWL<4776> A_IWL<4775> A_IWL<4774> A_IWL<4773> A_IWL<4772> A_IWL<4771> A_IWL<4770> A_IWL<4769> A_IWL<4768> A_IWL<4767> A_IWL<4766> A_IWL<4765> A_IWL<4764> A_IWL<4763> A_IWL<4762> A_IWL<4761> A_IWL<4760> A_IWL<4759> A_IWL<4758> A_IWL<4757> A_IWL<4756> A_IWL<4755> A_IWL<4754> A_IWL<4753> A_IWL<4752> A_IWL<4751> A_IWL<4750> A_IWL<4749> A_IWL<4748> A_IWL<4747> A_IWL<4746> A_IWL<4745> A_IWL<4744> A_IWL<4743> A_IWL<4742> A_IWL<4741> A_IWL<4740> A_IWL<4739> A_IWL<4738> A_IWL<4737> A_IWL<4736> A_IWL<4735> A_IWL<4734> A_IWL<4733> A_IWL<4732> A_IWL<4731> A_IWL<4730> A_IWL<4729> A_IWL<4728> A_IWL<4727> A_IWL<4726> A_IWL<4725> A_IWL<4724> A_IWL<4723> A_IWL<4722> A_IWL<4721> A_IWL<4720> A_IWL<4719> A_IWL<4718> A_IWL<4717> A_IWL<4716> A_IWL<4715> A_IWL<4714> A_IWL<4713> A_IWL<4712> A_IWL<4711> A_IWL<4710> A_IWL<4709> A_IWL<4708> A_IWL<4707> A_IWL<4706> A_IWL<4705> A_IWL<4704> A_IWL<4703> A_IWL<4702> A_IWL<4701> A_IWL<4700> A_IWL<4699> A_IWL<4698> A_IWL<4697> A_IWL<4696> A_IWL<4695> A_IWL<4694> A_IWL<4693> A_IWL<4692> A_IWL<4691> A_IWL<4690> A_IWL<4689> A_IWL<4688> A_IWL<4687> A_IWL<4686> A_IWL<4685> A_IWL<4684> A_IWL<4683> A_IWL<4682> A_IWL<4681> A_IWL<4680> A_IWL<4679> A_IWL<4678> A_IWL<4677> A_IWL<4676> A_IWL<4675> A_IWL<4674> A_IWL<4673> A_IWL<4672> A_IWL<4671> A_IWL<4670> A_IWL<4669> A_IWL<4668> A_IWL<4667> A_IWL<4666> A_IWL<4665> A_IWL<4664> A_IWL<4663> A_IWL<4662> A_IWL<4661> A_IWL<4660> A_IWL<4659> A_IWL<4658> A_IWL<4657> A_IWL<4656> A_IWL<4655> A_IWL<4654> A_IWL<4653> A_IWL<4652> A_IWL<4651> A_IWL<4650> A_IWL<4649> A_IWL<4648> A_IWL<4647> A_IWL<4646> A_IWL<4645> A_IWL<4644> A_IWL<4643> A_IWL<4642> A_IWL<4641> A_IWL<4640> A_IWL<4639> A_IWL<4638> A_IWL<4637> A_IWL<4636> A_IWL<4635> A_IWL<4634> A_IWL<4633> A_IWL<4632> A_IWL<4631> A_IWL<4630> A_IWL<4629> A_IWL<4628> A_IWL<4627> A_IWL<4626> A_IWL<4625> A_IWL<4624> A_IWL<4623> A_IWL<4622> A_IWL<4621> A_IWL<4620> A_IWL<4619> A_IWL<4618> A_IWL<4617> A_IWL<4616> A_IWL<4615> A_IWL<4614> A_IWL<4613> A_IWL<4612> A_IWL<4611> A_IWL<4610> A_IWL<4609> A_IWL<4608> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0
+XCOL<8> A_BLC<17> A_BLC<16> A_BLC_TOP<17> A_BLC_TOP<16> A_BLT<17> A_BLT<16> A_BLT_TOP<17> A_BLT_TOP<16> A_IWL<4095> A_IWL<4094> A_IWL<4093> A_IWL<4092> A_IWL<4091> A_IWL<4090> A_IWL<4089> A_IWL<4088> A_IWL<4087> A_IWL<4086> A_IWL<4085> A_IWL<4084> A_IWL<4083> A_IWL<4082> A_IWL<4081> A_IWL<4080> A_IWL<4079> A_IWL<4078> A_IWL<4077> A_IWL<4076> A_IWL<4075> A_IWL<4074> A_IWL<4073> A_IWL<4072> A_IWL<4071> A_IWL<4070> A_IWL<4069> A_IWL<4068> A_IWL<4067> A_IWL<4066> A_IWL<4065> A_IWL<4064> A_IWL<4063> A_IWL<4062> A_IWL<4061> A_IWL<4060> A_IWL<4059> A_IWL<4058> A_IWL<4057> A_IWL<4056> A_IWL<4055> A_IWL<4054> A_IWL<4053> A_IWL<4052> A_IWL<4051> A_IWL<4050> A_IWL<4049> A_IWL<4048> A_IWL<4047> A_IWL<4046> A_IWL<4045> A_IWL<4044> A_IWL<4043> A_IWL<4042> A_IWL<4041> A_IWL<4040> A_IWL<4039> A_IWL<4038> A_IWL<4037> A_IWL<4036> A_IWL<4035> A_IWL<4034> A_IWL<4033> A_IWL<4032> A_IWL<4031> A_IWL<4030> A_IWL<4029> A_IWL<4028> A_IWL<4027> A_IWL<4026> A_IWL<4025> A_IWL<4024> A_IWL<4023> A_IWL<4022> A_IWL<4021> A_IWL<4020> A_IWL<4019> A_IWL<4018> A_IWL<4017> A_IWL<4016> A_IWL<4015> A_IWL<4014> A_IWL<4013> A_IWL<4012> A_IWL<4011> A_IWL<4010> A_IWL<4009> A_IWL<4008> A_IWL<4007> A_IWL<4006> A_IWL<4005> A_IWL<4004> A_IWL<4003> A_IWL<4002> A_IWL<4001> A_IWL<4000> A_IWL<3999> A_IWL<3998> A_IWL<3997> A_IWL<3996> A_IWL<3995> A_IWL<3994> A_IWL<3993> A_IWL<3992> A_IWL<3991> A_IWL<3990> A_IWL<3989> A_IWL<3988> A_IWL<3987> A_IWL<3986> A_IWL<3985> A_IWL<3984> A_IWL<3983> A_IWL<3982> A_IWL<3981> A_IWL<3980> A_IWL<3979> A_IWL<3978> A_IWL<3977> A_IWL<3976> A_IWL<3975> A_IWL<3974> A_IWL<3973> A_IWL<3972> A_IWL<3971> A_IWL<3970> A_IWL<3969> A_IWL<3968> A_IWL<3967> A_IWL<3966> A_IWL<3965> A_IWL<3964> A_IWL<3963> A_IWL<3962> A_IWL<3961> A_IWL<3960> A_IWL<3959> A_IWL<3958> A_IWL<3957> A_IWL<3956> A_IWL<3955> A_IWL<3954> A_IWL<3953> A_IWL<3952> A_IWL<3951> A_IWL<3950> A_IWL<3949> A_IWL<3948> A_IWL<3947> A_IWL<3946> A_IWL<3945> A_IWL<3944> A_IWL<3943> A_IWL<3942> A_IWL<3941> A_IWL<3940> A_IWL<3939> A_IWL<3938> A_IWL<3937> A_IWL<3936> A_IWL<3935> A_IWL<3934> A_IWL<3933> A_IWL<3932> A_IWL<3931> A_IWL<3930> A_IWL<3929> A_IWL<3928> A_IWL<3927> A_IWL<3926> A_IWL<3925> A_IWL<3924> A_IWL<3923> A_IWL<3922> A_IWL<3921> A_IWL<3920> A_IWL<3919> A_IWL<3918> A_IWL<3917> A_IWL<3916> A_IWL<3915> A_IWL<3914> A_IWL<3913> A_IWL<3912> A_IWL<3911> A_IWL<3910> A_IWL<3909> A_IWL<3908> A_IWL<3907> A_IWL<3906> A_IWL<3905> A_IWL<3904> A_IWL<3903> A_IWL<3902> A_IWL<3901> A_IWL<3900> A_IWL<3899> A_IWL<3898> A_IWL<3897> A_IWL<3896> A_IWL<3895> A_IWL<3894> A_IWL<3893> A_IWL<3892> A_IWL<3891> A_IWL<3890> A_IWL<3889> A_IWL<3888> A_IWL<3887> A_IWL<3886> A_IWL<3885> A_IWL<3884> A_IWL<3883> A_IWL<3882> A_IWL<3881> A_IWL<3880> A_IWL<3879> A_IWL<3878> A_IWL<3877> A_IWL<3876> A_IWL<3875> A_IWL<3874> A_IWL<3873> A_IWL<3872> A_IWL<3871> A_IWL<3870> A_IWL<3869> A_IWL<3868> A_IWL<3867> A_IWL<3866> A_IWL<3865> A_IWL<3864> A_IWL<3863> A_IWL<3862> A_IWL<3861> A_IWL<3860> A_IWL<3859> A_IWL<3858> A_IWL<3857> A_IWL<3856> A_IWL<3855> A_IWL<3854> A_IWL<3853> A_IWL<3852> A_IWL<3851> A_IWL<3850> A_IWL<3849> A_IWL<3848> A_IWL<3847> A_IWL<3846> A_IWL<3845> A_IWL<3844> A_IWL<3843> A_IWL<3842> A_IWL<3841> A_IWL<3840> A_IWL<3839> A_IWL<3838> A_IWL<3837> A_IWL<3836> A_IWL<3835> A_IWL<3834> A_IWL<3833> A_IWL<3832> A_IWL<3831> A_IWL<3830> A_IWL<3829> A_IWL<3828> A_IWL<3827> A_IWL<3826> A_IWL<3825> A_IWL<3824> A_IWL<3823> A_IWL<3822> A_IWL<3821> A_IWL<3820> A_IWL<3819> A_IWL<3818> A_IWL<3817> A_IWL<3816> A_IWL<3815> A_IWL<3814> A_IWL<3813> A_IWL<3812> A_IWL<3811> A_IWL<3810> A_IWL<3809> A_IWL<3808> A_IWL<3807> A_IWL<3806> A_IWL<3805> A_IWL<3804> A_IWL<3803> A_IWL<3802> A_IWL<3801> A_IWL<3800> A_IWL<3799> A_IWL<3798> A_IWL<3797> A_IWL<3796> A_IWL<3795> A_IWL<3794> A_IWL<3793> A_IWL<3792> A_IWL<3791> A_IWL<3790> A_IWL<3789> A_IWL<3788> A_IWL<3787> A_IWL<3786> A_IWL<3785> A_IWL<3784> A_IWL<3783> A_IWL<3782> A_IWL<3781> A_IWL<3780> A_IWL<3779> A_IWL<3778> A_IWL<3777> A_IWL<3776> A_IWL<3775> A_IWL<3774> A_IWL<3773> A_IWL<3772> A_IWL<3771> A_IWL<3770> A_IWL<3769> A_IWL<3768> A_IWL<3767> A_IWL<3766> A_IWL<3765> A_IWL<3764> A_IWL<3763> A_IWL<3762> A_IWL<3761> A_IWL<3760> A_IWL<3759> A_IWL<3758> A_IWL<3757> A_IWL<3756> A_IWL<3755> A_IWL<3754> A_IWL<3753> A_IWL<3752> A_IWL<3751> A_IWL<3750> A_IWL<3749> A_IWL<3748> A_IWL<3747> A_IWL<3746> A_IWL<3745> A_IWL<3744> A_IWL<3743> A_IWL<3742> A_IWL<3741> A_IWL<3740> A_IWL<3739> A_IWL<3738> A_IWL<3737> A_IWL<3736> A_IWL<3735> A_IWL<3734> A_IWL<3733> A_IWL<3732> A_IWL<3731> A_IWL<3730> A_IWL<3729> A_IWL<3728> A_IWL<3727> A_IWL<3726> A_IWL<3725> A_IWL<3724> A_IWL<3723> A_IWL<3722> A_IWL<3721> A_IWL<3720> A_IWL<3719> A_IWL<3718> A_IWL<3717> A_IWL<3716> A_IWL<3715> A_IWL<3714> A_IWL<3713> A_IWL<3712> A_IWL<3711> A_IWL<3710> A_IWL<3709> A_IWL<3708> A_IWL<3707> A_IWL<3706> A_IWL<3705> A_IWL<3704> A_IWL<3703> A_IWL<3702> A_IWL<3701> A_IWL<3700> A_IWL<3699> A_IWL<3698> A_IWL<3697> A_IWL<3696> A_IWL<3695> A_IWL<3694> A_IWL<3693> A_IWL<3692> A_IWL<3691> A_IWL<3690> A_IWL<3689> A_IWL<3688> A_IWL<3687> A_IWL<3686> A_IWL<3685> A_IWL<3684> A_IWL<3683> A_IWL<3682> A_IWL<3681> A_IWL<3680> A_IWL<3679> A_IWL<3678> A_IWL<3677> A_IWL<3676> A_IWL<3675> A_IWL<3674> A_IWL<3673> A_IWL<3672> A_IWL<3671> A_IWL<3670> A_IWL<3669> A_IWL<3668> A_IWL<3667> A_IWL<3666> A_IWL<3665> A_IWL<3664> A_IWL<3663> A_IWL<3662> A_IWL<3661> A_IWL<3660> A_IWL<3659> A_IWL<3658> A_IWL<3657> A_IWL<3656> A_IWL<3655> A_IWL<3654> A_IWL<3653> A_IWL<3652> A_IWL<3651> A_IWL<3650> A_IWL<3649> A_IWL<3648> A_IWL<3647> A_IWL<3646> A_IWL<3645> A_IWL<3644> A_IWL<3643> A_IWL<3642> A_IWL<3641> A_IWL<3640> A_IWL<3639> A_IWL<3638> A_IWL<3637> A_IWL<3636> A_IWL<3635> A_IWL<3634> A_IWL<3633> A_IWL<3632> A_IWL<3631> A_IWL<3630> A_IWL<3629> A_IWL<3628> A_IWL<3627> A_IWL<3626> A_IWL<3625> A_IWL<3624> A_IWL<3623> A_IWL<3622> A_IWL<3621> A_IWL<3620> A_IWL<3619> A_IWL<3618> A_IWL<3617> A_IWL<3616> A_IWL<3615> A_IWL<3614> A_IWL<3613> A_IWL<3612> A_IWL<3611> A_IWL<3610> A_IWL<3609> A_IWL<3608> A_IWL<3607> A_IWL<3606> A_IWL<3605> A_IWL<3604> A_IWL<3603> A_IWL<3602> A_IWL<3601> A_IWL<3600> A_IWL<3599> A_IWL<3598> A_IWL<3597> A_IWL<3596> A_IWL<3595> A_IWL<3594> A_IWL<3593> A_IWL<3592> A_IWL<3591> A_IWL<3590> A_IWL<3589> A_IWL<3588> A_IWL<3587> A_IWL<3586> A_IWL<3585> A_IWL<3584> A_IWL<4607> A_IWL<4606> A_IWL<4605> A_IWL<4604> A_IWL<4603> A_IWL<4602> A_IWL<4601> A_IWL<4600> A_IWL<4599> A_IWL<4598> A_IWL<4597> A_IWL<4596> A_IWL<4595> A_IWL<4594> A_IWL<4593> A_IWL<4592> A_IWL<4591> A_IWL<4590> A_IWL<4589> A_IWL<4588> A_IWL<4587> A_IWL<4586> A_IWL<4585> A_IWL<4584> A_IWL<4583> A_IWL<4582> A_IWL<4581> A_IWL<4580> A_IWL<4579> A_IWL<4578> A_IWL<4577> A_IWL<4576> A_IWL<4575> A_IWL<4574> A_IWL<4573> A_IWL<4572> A_IWL<4571> A_IWL<4570> A_IWL<4569> A_IWL<4568> A_IWL<4567> A_IWL<4566> A_IWL<4565> A_IWL<4564> A_IWL<4563> A_IWL<4562> A_IWL<4561> A_IWL<4560> A_IWL<4559> A_IWL<4558> A_IWL<4557> A_IWL<4556> A_IWL<4555> A_IWL<4554> A_IWL<4553> A_IWL<4552> A_IWL<4551> A_IWL<4550> A_IWL<4549> A_IWL<4548> A_IWL<4547> A_IWL<4546> A_IWL<4545> A_IWL<4544> A_IWL<4543> A_IWL<4542> A_IWL<4541> A_IWL<4540> A_IWL<4539> A_IWL<4538> A_IWL<4537> A_IWL<4536> A_IWL<4535> A_IWL<4534> A_IWL<4533> A_IWL<4532> A_IWL<4531> A_IWL<4530> A_IWL<4529> A_IWL<4528> A_IWL<4527> A_IWL<4526> A_IWL<4525> A_IWL<4524> A_IWL<4523> A_IWL<4522> A_IWL<4521> A_IWL<4520> A_IWL<4519> A_IWL<4518> A_IWL<4517> A_IWL<4516> A_IWL<4515> A_IWL<4514> A_IWL<4513> A_IWL<4512> A_IWL<4511> A_IWL<4510> A_IWL<4509> A_IWL<4508> A_IWL<4507> A_IWL<4506> A_IWL<4505> A_IWL<4504> A_IWL<4503> A_IWL<4502> A_IWL<4501> A_IWL<4500> A_IWL<4499> A_IWL<4498> A_IWL<4497> A_IWL<4496> A_IWL<4495> A_IWL<4494> A_IWL<4493> A_IWL<4492> A_IWL<4491> A_IWL<4490> A_IWL<4489> A_IWL<4488> A_IWL<4487> A_IWL<4486> A_IWL<4485> A_IWL<4484> A_IWL<4483> A_IWL<4482> A_IWL<4481> A_IWL<4480> A_IWL<4479> A_IWL<4478> A_IWL<4477> A_IWL<4476> A_IWL<4475> A_IWL<4474> A_IWL<4473> A_IWL<4472> A_IWL<4471> A_IWL<4470> A_IWL<4469> A_IWL<4468> A_IWL<4467> A_IWL<4466> A_IWL<4465> A_IWL<4464> A_IWL<4463> A_IWL<4462> A_IWL<4461> A_IWL<4460> A_IWL<4459> A_IWL<4458> A_IWL<4457> A_IWL<4456> A_IWL<4455> A_IWL<4454> A_IWL<4453> A_IWL<4452> A_IWL<4451> A_IWL<4450> A_IWL<4449> A_IWL<4448> A_IWL<4447> A_IWL<4446> A_IWL<4445> A_IWL<4444> A_IWL<4443> A_IWL<4442> A_IWL<4441> A_IWL<4440> A_IWL<4439> A_IWL<4438> A_IWL<4437> A_IWL<4436> A_IWL<4435> A_IWL<4434> A_IWL<4433> A_IWL<4432> A_IWL<4431> A_IWL<4430> A_IWL<4429> A_IWL<4428> A_IWL<4427> A_IWL<4426> A_IWL<4425> A_IWL<4424> A_IWL<4423> A_IWL<4422> A_IWL<4421> A_IWL<4420> A_IWL<4419> A_IWL<4418> A_IWL<4417> A_IWL<4416> A_IWL<4415> A_IWL<4414> A_IWL<4413> A_IWL<4412> A_IWL<4411> A_IWL<4410> A_IWL<4409> A_IWL<4408> A_IWL<4407> A_IWL<4406> A_IWL<4405> A_IWL<4404> A_IWL<4403> A_IWL<4402> A_IWL<4401> A_IWL<4400> A_IWL<4399> A_IWL<4398> A_IWL<4397> A_IWL<4396> A_IWL<4395> A_IWL<4394> A_IWL<4393> A_IWL<4392> A_IWL<4391> A_IWL<4390> A_IWL<4389> A_IWL<4388> A_IWL<4387> A_IWL<4386> A_IWL<4385> A_IWL<4384> A_IWL<4383> A_IWL<4382> A_IWL<4381> A_IWL<4380> A_IWL<4379> A_IWL<4378> A_IWL<4377> A_IWL<4376> A_IWL<4375> A_IWL<4374> A_IWL<4373> A_IWL<4372> A_IWL<4371> A_IWL<4370> A_IWL<4369> A_IWL<4368> A_IWL<4367> A_IWL<4366> A_IWL<4365> A_IWL<4364> A_IWL<4363> A_IWL<4362> A_IWL<4361> A_IWL<4360> A_IWL<4359> A_IWL<4358> A_IWL<4357> A_IWL<4356> A_IWL<4355> A_IWL<4354> A_IWL<4353> A_IWL<4352> A_IWL<4351> A_IWL<4350> A_IWL<4349> A_IWL<4348> A_IWL<4347> A_IWL<4346> A_IWL<4345> A_IWL<4344> A_IWL<4343> A_IWL<4342> A_IWL<4341> A_IWL<4340> A_IWL<4339> A_IWL<4338> A_IWL<4337> A_IWL<4336> A_IWL<4335> A_IWL<4334> A_IWL<4333> A_IWL<4332> A_IWL<4331> A_IWL<4330> A_IWL<4329> A_IWL<4328> A_IWL<4327> A_IWL<4326> A_IWL<4325> A_IWL<4324> A_IWL<4323> A_IWL<4322> A_IWL<4321> A_IWL<4320> A_IWL<4319> A_IWL<4318> A_IWL<4317> A_IWL<4316> A_IWL<4315> A_IWL<4314> A_IWL<4313> A_IWL<4312> A_IWL<4311> A_IWL<4310> A_IWL<4309> A_IWL<4308> A_IWL<4307> A_IWL<4306> A_IWL<4305> A_IWL<4304> A_IWL<4303> A_IWL<4302> A_IWL<4301> A_IWL<4300> A_IWL<4299> A_IWL<4298> A_IWL<4297> A_IWL<4296> A_IWL<4295> A_IWL<4294> A_IWL<4293> A_IWL<4292> A_IWL<4291> A_IWL<4290> A_IWL<4289> A_IWL<4288> A_IWL<4287> A_IWL<4286> A_IWL<4285> A_IWL<4284> A_IWL<4283> A_IWL<4282> A_IWL<4281> A_IWL<4280> A_IWL<4279> A_IWL<4278> A_IWL<4277> A_IWL<4276> A_IWL<4275> A_IWL<4274> A_IWL<4273> A_IWL<4272> A_IWL<4271> A_IWL<4270> A_IWL<4269> A_IWL<4268> A_IWL<4267> A_IWL<4266> A_IWL<4265> A_IWL<4264> A_IWL<4263> A_IWL<4262> A_IWL<4261> A_IWL<4260> A_IWL<4259> A_IWL<4258> A_IWL<4257> A_IWL<4256> A_IWL<4255> A_IWL<4254> A_IWL<4253> A_IWL<4252> A_IWL<4251> A_IWL<4250> A_IWL<4249> A_IWL<4248> A_IWL<4247> A_IWL<4246> A_IWL<4245> A_IWL<4244> A_IWL<4243> A_IWL<4242> A_IWL<4241> A_IWL<4240> A_IWL<4239> A_IWL<4238> A_IWL<4237> A_IWL<4236> A_IWL<4235> A_IWL<4234> A_IWL<4233> A_IWL<4232> A_IWL<4231> A_IWL<4230> A_IWL<4229> A_IWL<4228> A_IWL<4227> A_IWL<4226> A_IWL<4225> A_IWL<4224> A_IWL<4223> A_IWL<4222> A_IWL<4221> A_IWL<4220> A_IWL<4219> A_IWL<4218> A_IWL<4217> A_IWL<4216> A_IWL<4215> A_IWL<4214> A_IWL<4213> A_IWL<4212> A_IWL<4211> A_IWL<4210> A_IWL<4209> A_IWL<4208> A_IWL<4207> A_IWL<4206> A_IWL<4205> A_IWL<4204> A_IWL<4203> A_IWL<4202> A_IWL<4201> A_IWL<4200> A_IWL<4199> A_IWL<4198> A_IWL<4197> A_IWL<4196> A_IWL<4195> A_IWL<4194> A_IWL<4193> A_IWL<4192> A_IWL<4191> A_IWL<4190> A_IWL<4189> A_IWL<4188> A_IWL<4187> A_IWL<4186> A_IWL<4185> A_IWL<4184> A_IWL<4183> A_IWL<4182> A_IWL<4181> A_IWL<4180> A_IWL<4179> A_IWL<4178> A_IWL<4177> A_IWL<4176> A_IWL<4175> A_IWL<4174> A_IWL<4173> A_IWL<4172> A_IWL<4171> A_IWL<4170> A_IWL<4169> A_IWL<4168> A_IWL<4167> A_IWL<4166> A_IWL<4165> A_IWL<4164> A_IWL<4163> A_IWL<4162> A_IWL<4161> A_IWL<4160> A_IWL<4159> A_IWL<4158> A_IWL<4157> A_IWL<4156> A_IWL<4155> A_IWL<4154> A_IWL<4153> A_IWL<4152> A_IWL<4151> A_IWL<4150> A_IWL<4149> A_IWL<4148> A_IWL<4147> A_IWL<4146> A_IWL<4145> A_IWL<4144> A_IWL<4143> A_IWL<4142> A_IWL<4141> A_IWL<4140> A_IWL<4139> A_IWL<4138> A_IWL<4137> A_IWL<4136> A_IWL<4135> A_IWL<4134> A_IWL<4133> A_IWL<4132> A_IWL<4131> A_IWL<4130> A_IWL<4129> A_IWL<4128> A_IWL<4127> A_IWL<4126> A_IWL<4125> A_IWL<4124> A_IWL<4123> A_IWL<4122> A_IWL<4121> A_IWL<4120> A_IWL<4119> A_IWL<4118> A_IWL<4117> A_IWL<4116> A_IWL<4115> A_IWL<4114> A_IWL<4113> A_IWL<4112> A_IWL<4111> A_IWL<4110> A_IWL<4109> A_IWL<4108> A_IWL<4107> A_IWL<4106> A_IWL<4105> A_IWL<4104> A_IWL<4103> A_IWL<4102> A_IWL<4101> A_IWL<4100> A_IWL<4099> A_IWL<4098> A_IWL<4097> A_IWL<4096> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0
+XCOL<7> A_BLC<15> A_BLC<14> A_BLC_TOP<15> A_BLC_TOP<14> A_BLT<15> A_BLT<14> A_BLT_TOP<15> A_BLT_TOP<14> A_IWL<3583> A_IWL<3582> A_IWL<3581> A_IWL<3580> A_IWL<3579> A_IWL<3578> A_IWL<3577> A_IWL<3576> A_IWL<3575> A_IWL<3574> A_IWL<3573> A_IWL<3572> A_IWL<3571> A_IWL<3570> A_IWL<3569> A_IWL<3568> A_IWL<3567> A_IWL<3566> A_IWL<3565> A_IWL<3564> A_IWL<3563> A_IWL<3562> A_IWL<3561> A_IWL<3560> A_IWL<3559> A_IWL<3558> A_IWL<3557> A_IWL<3556> A_IWL<3555> A_IWL<3554> A_IWL<3553> A_IWL<3552> A_IWL<3551> A_IWL<3550> A_IWL<3549> A_IWL<3548> A_IWL<3547> A_IWL<3546> A_IWL<3545> A_IWL<3544> A_IWL<3543> A_IWL<3542> A_IWL<3541> A_IWL<3540> A_IWL<3539> A_IWL<3538> A_IWL<3537> A_IWL<3536> A_IWL<3535> A_IWL<3534> A_IWL<3533> A_IWL<3532> A_IWL<3531> A_IWL<3530> A_IWL<3529> A_IWL<3528> A_IWL<3527> A_IWL<3526> A_IWL<3525> A_IWL<3524> A_IWL<3523> A_IWL<3522> A_IWL<3521> A_IWL<3520> A_IWL<3519> A_IWL<3518> A_IWL<3517> A_IWL<3516> A_IWL<3515> A_IWL<3514> A_IWL<3513> A_IWL<3512> A_IWL<3511> A_IWL<3510> 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A_IWL<3703> A_IWL<3702> A_IWL<3701> A_IWL<3700> A_IWL<3699> A_IWL<3698> A_IWL<3697> A_IWL<3696> A_IWL<3695> A_IWL<3694> A_IWL<3693> A_IWL<3692> A_IWL<3691> A_IWL<3690> A_IWL<3689> A_IWL<3688> A_IWL<3687> A_IWL<3686> A_IWL<3685> A_IWL<3684> A_IWL<3683> A_IWL<3682> A_IWL<3681> A_IWL<3680> A_IWL<3679> A_IWL<3678> A_IWL<3677> A_IWL<3676> A_IWL<3675> A_IWL<3674> A_IWL<3673> A_IWL<3672> A_IWL<3671> A_IWL<3670> A_IWL<3669> A_IWL<3668> A_IWL<3667> A_IWL<3666> A_IWL<3665> A_IWL<3664> A_IWL<3663> A_IWL<3662> A_IWL<3661> A_IWL<3660> A_IWL<3659> A_IWL<3658> A_IWL<3657> A_IWL<3656> A_IWL<3655> A_IWL<3654> A_IWL<3653> A_IWL<3652> A_IWL<3651> A_IWL<3650> A_IWL<3649> A_IWL<3648> A_IWL<3647> A_IWL<3646> A_IWL<3645> A_IWL<3644> A_IWL<3643> A_IWL<3642> A_IWL<3641> A_IWL<3640> A_IWL<3639> A_IWL<3638> A_IWL<3637> A_IWL<3636> A_IWL<3635> A_IWL<3634> A_IWL<3633> A_IWL<3632> A_IWL<3631> A_IWL<3630> A_IWL<3629> A_IWL<3628> A_IWL<3627> A_IWL<3626> A_IWL<3625> A_IWL<3624> A_IWL<3623> A_IWL<3622> A_IWL<3621> A_IWL<3620> A_IWL<3619> A_IWL<3618> A_IWL<3617> A_IWL<3616> A_IWL<3615> A_IWL<3614> A_IWL<3613> A_IWL<3612> A_IWL<3611> A_IWL<3610> A_IWL<3609> A_IWL<3608> A_IWL<3607> A_IWL<3606> A_IWL<3605> A_IWL<3604> A_IWL<3603> A_IWL<3602> A_IWL<3601> A_IWL<3600> A_IWL<3599> A_IWL<3598> A_IWL<3597> A_IWL<3596> A_IWL<3595> A_IWL<3594> A_IWL<3593> A_IWL<3592> A_IWL<3591> A_IWL<3590> A_IWL<3589> A_IWL<3588> A_IWL<3587> A_IWL<3586> A_IWL<3585> A_IWL<3584> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0
+XCOL<6> A_BLC<13> A_BLC<12> A_BLC_TOP<13> A_BLC_TOP<12> A_BLT<13> A_BLT<12> A_BLT_TOP<13> A_BLT_TOP<12> A_IWL<3071> A_IWL<3070> A_IWL<3069> A_IWL<3068> A_IWL<3067> A_IWL<3066> A_IWL<3065> A_IWL<3064> A_IWL<3063> A_IWL<3062> A_IWL<3061> A_IWL<3060> A_IWL<3059> A_IWL<3058> A_IWL<3057> A_IWL<3056> A_IWL<3055> A_IWL<3054> A_IWL<3053> A_IWL<3052> A_IWL<3051> A_IWL<3050> A_IWL<3049> A_IWL<3048> A_IWL<3047> A_IWL<3046> A_IWL<3045> A_IWL<3044> A_IWL<3043> A_IWL<3042> A_IWL<3041> A_IWL<3040> A_IWL<3039> A_IWL<3038> A_IWL<3037> A_IWL<3036> A_IWL<3035> A_IWL<3034> A_IWL<3033> A_IWL<3032> A_IWL<3031> A_IWL<3030> A_IWL<3029> A_IWL<3028> A_IWL<3027> A_IWL<3026> A_IWL<3025> A_IWL<3024> A_IWL<3023> A_IWL<3022> A_IWL<3021> A_IWL<3020> A_IWL<3019> A_IWL<3018> A_IWL<3017> A_IWL<3016> A_IWL<3015> A_IWL<3014> A_IWL<3013> A_IWL<3012> A_IWL<3011> A_IWL<3010> A_IWL<3009> A_IWL<3008> A_IWL<3007> A_IWL<3006> A_IWL<3005> A_IWL<3004> A_IWL<3003> A_IWL<3002> A_IWL<3001> A_IWL<3000> A_IWL<2999> A_IWL<2998> A_IWL<2997> A_IWL<2996> A_IWL<2995> A_IWL<2994> A_IWL<2993> A_IWL<2992> A_IWL<2991> A_IWL<2990> A_IWL<2989> A_IWL<2988> A_IWL<2987> A_IWL<2986> A_IWL<2985> A_IWL<2984> A_IWL<2983> A_IWL<2982> A_IWL<2981> A_IWL<2980> A_IWL<2979> A_IWL<2978> A_IWL<2977> A_IWL<2976> A_IWL<2975> A_IWL<2974> A_IWL<2973> A_IWL<2972> A_IWL<2971> A_IWL<2970> A_IWL<2969> A_IWL<2968> A_IWL<2967> A_IWL<2966> A_IWL<2965> A_IWL<2964> A_IWL<2963> A_IWL<2962> A_IWL<2961> A_IWL<2960> A_IWL<2959> A_IWL<2958> A_IWL<2957> A_IWL<2956> A_IWL<2955> A_IWL<2954> A_IWL<2953> A_IWL<2952> A_IWL<2951> A_IWL<2950> A_IWL<2949> A_IWL<2948> A_IWL<2947> A_IWL<2946> A_IWL<2945> A_IWL<2944> A_IWL<2943> A_IWL<2942> A_IWL<2941> A_IWL<2940> A_IWL<2939> A_IWL<2938> A_IWL<2937> A_IWL<2936> A_IWL<2935> A_IWL<2934> A_IWL<2933> A_IWL<2932> A_IWL<2931> A_IWL<2930> A_IWL<2929> A_IWL<2928> A_IWL<2927> A_IWL<2926> A_IWL<2925> A_IWL<2924> A_IWL<2923> A_IWL<2922> A_IWL<2921> A_IWL<2920> A_IWL<2919> A_IWL<2918> A_IWL<2917> A_IWL<2916> A_IWL<2915> A_IWL<2914> A_IWL<2913> A_IWL<2912> A_IWL<2911> A_IWL<2910> A_IWL<2909> A_IWL<2908> A_IWL<2907> A_IWL<2906> A_IWL<2905> A_IWL<2904> A_IWL<2903> A_IWL<2902> A_IWL<2901> A_IWL<2900> A_IWL<2899> A_IWL<2898> A_IWL<2897> A_IWL<2896> A_IWL<2895> A_IWL<2894> A_IWL<2893> A_IWL<2892> A_IWL<2891> A_IWL<2890> A_IWL<2889> A_IWL<2888> A_IWL<2887> A_IWL<2886> A_IWL<2885> A_IWL<2884> A_IWL<2883> A_IWL<2882> A_IWL<2881> A_IWL<2880> A_IWL<2879> A_IWL<2878> A_IWL<2877> A_IWL<2876> A_IWL<2875> A_IWL<2874> A_IWL<2873> A_IWL<2872> A_IWL<2871> A_IWL<2870> A_IWL<2869> A_IWL<2868> A_IWL<2867> A_IWL<2866> A_IWL<2865> A_IWL<2864> A_IWL<2863> A_IWL<2862> A_IWL<2861> A_IWL<2860> A_IWL<2859> A_IWL<2858> A_IWL<2857> A_IWL<2856> A_IWL<2855> A_IWL<2854> A_IWL<2853> A_IWL<2852> A_IWL<2851> A_IWL<2850> A_IWL<2849> A_IWL<2848> A_IWL<2847> A_IWL<2846> A_IWL<2845> A_IWL<2844> A_IWL<2843> A_IWL<2842> A_IWL<2841> A_IWL<2840> A_IWL<2839> A_IWL<2838> A_IWL<2837> A_IWL<2836> A_IWL<2835> A_IWL<2834> A_IWL<2833> A_IWL<2832> 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A_IWL<2665> A_IWL<2664> A_IWL<2663> A_IWL<2662> A_IWL<2661> A_IWL<2660> A_IWL<2659> A_IWL<2658> A_IWL<2657> A_IWL<2656> A_IWL<2655> A_IWL<2654> A_IWL<2653> A_IWL<2652> A_IWL<2651> A_IWL<2650> A_IWL<2649> A_IWL<2648> A_IWL<2647> A_IWL<2646> A_IWL<2645> A_IWL<2644> A_IWL<2643> A_IWL<2642> A_IWL<2641> A_IWL<2640> A_IWL<2639> A_IWL<2638> A_IWL<2637> A_IWL<2636> A_IWL<2635> A_IWL<2634> A_IWL<2633> A_IWL<2632> A_IWL<2631> A_IWL<2630> A_IWL<2629> A_IWL<2628> A_IWL<2627> A_IWL<2626> A_IWL<2625> A_IWL<2624> A_IWL<2623> A_IWL<2622> A_IWL<2621> A_IWL<2620> A_IWL<2619> A_IWL<2618> A_IWL<2617> A_IWL<2616> A_IWL<2615> A_IWL<2614> A_IWL<2613> A_IWL<2612> A_IWL<2611> A_IWL<2610> A_IWL<2609> A_IWL<2608> A_IWL<2607> A_IWL<2606> A_IWL<2605> A_IWL<2604> A_IWL<2603> A_IWL<2602> A_IWL<2601> A_IWL<2600> A_IWL<2599> A_IWL<2598> A_IWL<2597> A_IWL<2596> A_IWL<2595> A_IWL<2594> A_IWL<2593> A_IWL<2592> A_IWL<2591> A_IWL<2590> A_IWL<2589> A_IWL<2588> A_IWL<2587> A_IWL<2586> A_IWL<2585> A_IWL<2584> A_IWL<2583> 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A_IWL<3523> A_IWL<3522> A_IWL<3521> A_IWL<3520> A_IWL<3519> A_IWL<3518> A_IWL<3517> A_IWL<3516> A_IWL<3515> A_IWL<3514> A_IWL<3513> A_IWL<3512> A_IWL<3511> A_IWL<3510> A_IWL<3509> A_IWL<3508> A_IWL<3507> A_IWL<3506> A_IWL<3505> A_IWL<3504> A_IWL<3503> A_IWL<3502> A_IWL<3501> A_IWL<3500> A_IWL<3499> A_IWL<3498> A_IWL<3497> A_IWL<3496> A_IWL<3495> A_IWL<3494> A_IWL<3493> A_IWL<3492> A_IWL<3491> A_IWL<3490> A_IWL<3489> A_IWL<3488> A_IWL<3487> A_IWL<3486> A_IWL<3485> A_IWL<3484> A_IWL<3483> A_IWL<3482> A_IWL<3481> A_IWL<3480> A_IWL<3479> A_IWL<3478> A_IWL<3477> A_IWL<3476> A_IWL<3475> A_IWL<3474> A_IWL<3473> A_IWL<3472> A_IWL<3471> A_IWL<3470> A_IWL<3469> A_IWL<3468> A_IWL<3467> A_IWL<3466> A_IWL<3465> A_IWL<3464> A_IWL<3463> A_IWL<3462> A_IWL<3461> A_IWL<3460> A_IWL<3459> A_IWL<3458> A_IWL<3457> A_IWL<3456> A_IWL<3455> A_IWL<3454> A_IWL<3453> A_IWL<3452> A_IWL<3451> A_IWL<3450> A_IWL<3449> A_IWL<3448> A_IWL<3447> A_IWL<3446> A_IWL<3445> A_IWL<3444> A_IWL<3443> A_IWL<3442> A_IWL<3441> A_IWL<3440> A_IWL<3439> A_IWL<3438> A_IWL<3437> A_IWL<3436> A_IWL<3435> A_IWL<3434> A_IWL<3433> A_IWL<3432> A_IWL<3431> A_IWL<3430> A_IWL<3429> A_IWL<3428> A_IWL<3427> A_IWL<3426> A_IWL<3425> A_IWL<3424> A_IWL<3423> A_IWL<3422> A_IWL<3421> A_IWL<3420> A_IWL<3419> A_IWL<3418> A_IWL<3417> A_IWL<3416> A_IWL<3415> A_IWL<3414> A_IWL<3413> A_IWL<3412> A_IWL<3411> A_IWL<3410> A_IWL<3409> A_IWL<3408> A_IWL<3407> A_IWL<3406> A_IWL<3405> A_IWL<3404> A_IWL<3403> A_IWL<3402> A_IWL<3401> A_IWL<3400> A_IWL<3399> A_IWL<3398> A_IWL<3397> A_IWL<3396> A_IWL<3395> A_IWL<3394> A_IWL<3393> A_IWL<3392> A_IWL<3391> A_IWL<3390> A_IWL<3389> A_IWL<3388> A_IWL<3387> A_IWL<3386> A_IWL<3385> A_IWL<3384> A_IWL<3383> A_IWL<3382> A_IWL<3381> A_IWL<3380> A_IWL<3379> A_IWL<3378> A_IWL<3377> A_IWL<3376> A_IWL<3375> A_IWL<3374> A_IWL<3373> A_IWL<3372> A_IWL<3371> A_IWL<3370> A_IWL<3369> A_IWL<3368> A_IWL<3367> A_IWL<3366> A_IWL<3365> A_IWL<3364> A_IWL<3363> A_IWL<3362> A_IWL<3361> A_IWL<3360> A_IWL<3359> A_IWL<3358> A_IWL<3357> A_IWL<3356> A_IWL<3355> A_IWL<3354> A_IWL<3353> A_IWL<3352> A_IWL<3351> A_IWL<3350> A_IWL<3349> A_IWL<3348> A_IWL<3347> A_IWL<3346> A_IWL<3345> A_IWL<3344> A_IWL<3343> A_IWL<3342> A_IWL<3341> A_IWL<3340> A_IWL<3339> A_IWL<3338> A_IWL<3337> A_IWL<3336> A_IWL<3335> A_IWL<3334> A_IWL<3333> A_IWL<3332> A_IWL<3331> A_IWL<3330> A_IWL<3329> A_IWL<3328> A_IWL<3327> A_IWL<3326> A_IWL<3325> A_IWL<3324> A_IWL<3323> A_IWL<3322> A_IWL<3321> A_IWL<3320> A_IWL<3319> A_IWL<3318> A_IWL<3317> A_IWL<3316> A_IWL<3315> A_IWL<3314> A_IWL<3313> A_IWL<3312> A_IWL<3311> A_IWL<3310> A_IWL<3309> A_IWL<3308> A_IWL<3307> A_IWL<3306> A_IWL<3305> A_IWL<3304> A_IWL<3303> A_IWL<3302> A_IWL<3301> A_IWL<3300> A_IWL<3299> A_IWL<3298> A_IWL<3297> A_IWL<3296> A_IWL<3295> A_IWL<3294> A_IWL<3293> A_IWL<3292> A_IWL<3291> A_IWL<3290> A_IWL<3289> A_IWL<3288> A_IWL<3287> A_IWL<3286> A_IWL<3285> A_IWL<3284> A_IWL<3283> A_IWL<3282> A_IWL<3281> A_IWL<3280> A_IWL<3279> A_IWL<3278> A_IWL<3277> A_IWL<3276> A_IWL<3275> A_IWL<3274> A_IWL<3273> A_IWL<3272> A_IWL<3271> A_IWL<3270> A_IWL<3269> A_IWL<3268> A_IWL<3267> A_IWL<3266> A_IWL<3265> A_IWL<3264> A_IWL<3263> A_IWL<3262> A_IWL<3261> A_IWL<3260> A_IWL<3259> A_IWL<3258> A_IWL<3257> A_IWL<3256> A_IWL<3255> A_IWL<3254> A_IWL<3253> A_IWL<3252> A_IWL<3251> A_IWL<3250> A_IWL<3249> A_IWL<3248> A_IWL<3247> A_IWL<3246> A_IWL<3245> A_IWL<3244> A_IWL<3243> A_IWL<3242> A_IWL<3241> A_IWL<3240> A_IWL<3239> A_IWL<3238> A_IWL<3237> A_IWL<3236> A_IWL<3235> A_IWL<3234> A_IWL<3233> A_IWL<3232> A_IWL<3231> A_IWL<3230> A_IWL<3229> A_IWL<3228> A_IWL<3227> A_IWL<3226> A_IWL<3225> A_IWL<3224> A_IWL<3223> A_IWL<3222> A_IWL<3221> A_IWL<3220> A_IWL<3219> A_IWL<3218> A_IWL<3217> A_IWL<3216> A_IWL<3215> A_IWL<3214> A_IWL<3213> A_IWL<3212> A_IWL<3211> A_IWL<3210> A_IWL<3209> A_IWL<3208> A_IWL<3207> A_IWL<3206> A_IWL<3205> A_IWL<3204> A_IWL<3203> A_IWL<3202> A_IWL<3201> A_IWL<3200> A_IWL<3199> A_IWL<3198> A_IWL<3197> A_IWL<3196> A_IWL<3195> A_IWL<3194> A_IWL<3193> A_IWL<3192> A_IWL<3191> A_IWL<3190> A_IWL<3189> A_IWL<3188> A_IWL<3187> A_IWL<3186> A_IWL<3185> A_IWL<3184> A_IWL<3183> A_IWL<3182> A_IWL<3181> A_IWL<3180> A_IWL<3179> A_IWL<3178> A_IWL<3177> A_IWL<3176> A_IWL<3175> A_IWL<3174> A_IWL<3173> A_IWL<3172> A_IWL<3171> A_IWL<3170> A_IWL<3169> A_IWL<3168> A_IWL<3167> A_IWL<3166> A_IWL<3165> A_IWL<3164> A_IWL<3163> A_IWL<3162> A_IWL<3161> A_IWL<3160> A_IWL<3159> A_IWL<3158> A_IWL<3157> A_IWL<3156> A_IWL<3155> A_IWL<3154> A_IWL<3153> A_IWL<3152> A_IWL<3151> A_IWL<3150> A_IWL<3149> A_IWL<3148> A_IWL<3147> A_IWL<3146> A_IWL<3145> A_IWL<3144> A_IWL<3143> A_IWL<3142> A_IWL<3141> A_IWL<3140> A_IWL<3139> A_IWL<3138> A_IWL<3137> A_IWL<3136> A_IWL<3135> A_IWL<3134> A_IWL<3133> A_IWL<3132> A_IWL<3131> A_IWL<3130> A_IWL<3129> A_IWL<3128> A_IWL<3127> A_IWL<3126> A_IWL<3125> A_IWL<3124> A_IWL<3123> A_IWL<3122> A_IWL<3121> A_IWL<3120> A_IWL<3119> A_IWL<3118> A_IWL<3117> A_IWL<3116> A_IWL<3115> A_IWL<3114> A_IWL<3113> A_IWL<3112> A_IWL<3111> A_IWL<3110> A_IWL<3109> A_IWL<3108> A_IWL<3107> A_IWL<3106> A_IWL<3105> A_IWL<3104> A_IWL<3103> A_IWL<3102> A_IWL<3101> A_IWL<3100> A_IWL<3099> A_IWL<3098> A_IWL<3097> A_IWL<3096> A_IWL<3095> A_IWL<3094> A_IWL<3093> A_IWL<3092> A_IWL<3091> A_IWL<3090> A_IWL<3089> A_IWL<3088> A_IWL<3087> A_IWL<3086> A_IWL<3085> A_IWL<3084> A_IWL<3083> A_IWL<3082> A_IWL<3081> A_IWL<3080> A_IWL<3079> A_IWL<3078> A_IWL<3077> A_IWL<3076> A_IWL<3075> A_IWL<3074> A_IWL<3073> A_IWL<3072> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0
+XCOL<5> A_BLC<11> A_BLC<10> A_BLC_TOP<11> A_BLC_TOP<10> A_BLT<11> A_BLT<10> A_BLT_TOP<11> A_BLT_TOP<10> A_IWL<2559> A_IWL<2558> A_IWL<2557> A_IWL<2556> A_IWL<2555> A_IWL<2554> A_IWL<2553> A_IWL<2552> A_IWL<2551> A_IWL<2550> A_IWL<2549> A_IWL<2548> A_IWL<2547> A_IWL<2546> A_IWL<2545> A_IWL<2544> A_IWL<2543> A_IWL<2542> A_IWL<2541> A_IWL<2540> A_IWL<2539> A_IWL<2538> A_IWL<2537> A_IWL<2536> A_IWL<2535> A_IWL<2534> A_IWL<2533> A_IWL<2532> A_IWL<2531> A_IWL<2530> A_IWL<2529> A_IWL<2528> A_IWL<2527> A_IWL<2526> A_IWL<2525> A_IWL<2524> A_IWL<2523> A_IWL<2522> A_IWL<2521> A_IWL<2520> A_IWL<2519> A_IWL<2518> A_IWL<2517> A_IWL<2516> A_IWL<2515> A_IWL<2514> A_IWL<2513> A_IWL<2512> A_IWL<2511> A_IWL<2510> A_IWL<2509> A_IWL<2508> A_IWL<2507> A_IWL<2506> A_IWL<2505> A_IWL<2504> A_IWL<2503> A_IWL<2502> A_IWL<2501> A_IWL<2500> A_IWL<2499> A_IWL<2498> A_IWL<2497> A_IWL<2496> A_IWL<2495> A_IWL<2494> A_IWL<2493> A_IWL<2492> A_IWL<2491> A_IWL<2490> A_IWL<2489> A_IWL<2488> A_IWL<2487> A_IWL<2486> A_IWL<2485> A_IWL<2484> A_IWL<2483> A_IWL<2482> A_IWL<2481> A_IWL<2480> A_IWL<2479> A_IWL<2478> A_IWL<2477> A_IWL<2476> A_IWL<2475> A_IWL<2474> A_IWL<2473> A_IWL<2472> A_IWL<2471> A_IWL<2470> A_IWL<2469> A_IWL<2468> A_IWL<2467> A_IWL<2466> A_IWL<2465> A_IWL<2464> A_IWL<2463> A_IWL<2462> A_IWL<2461> A_IWL<2460> A_IWL<2459> A_IWL<2458> A_IWL<2457> A_IWL<2456> A_IWL<2455> A_IWL<2454> A_IWL<2453> A_IWL<2452> A_IWL<2451> A_IWL<2450> A_IWL<2449> A_IWL<2448> A_IWL<2447> A_IWL<2446> A_IWL<2445> A_IWL<2444> A_IWL<2443> A_IWL<2442> A_IWL<2441> A_IWL<2440> A_IWL<2439> A_IWL<2438> A_IWL<2437> A_IWL<2436> A_IWL<2435> A_IWL<2434> A_IWL<2433> A_IWL<2432> A_IWL<2431> A_IWL<2430> A_IWL<2429> A_IWL<2428> A_IWL<2427> A_IWL<2426> A_IWL<2425> A_IWL<2424> A_IWL<2423> A_IWL<2422> A_IWL<2421> A_IWL<2420> A_IWL<2419> A_IWL<2418> A_IWL<2417> A_IWL<2416> A_IWL<2415> A_IWL<2414> A_IWL<2413> A_IWL<2412> A_IWL<2411> A_IWL<2410> A_IWL<2409> A_IWL<2408> A_IWL<2407> A_IWL<2406> A_IWL<2405> A_IWL<2404> A_IWL<2403> A_IWL<2402> A_IWL<2401> A_IWL<2400> A_IWL<2399> A_IWL<2398> A_IWL<2397> A_IWL<2396> A_IWL<2395> A_IWL<2394> A_IWL<2393> A_IWL<2392> A_IWL<2391> A_IWL<2390> A_IWL<2389> A_IWL<2388> A_IWL<2387> A_IWL<2386> A_IWL<2385> A_IWL<2384> A_IWL<2383> A_IWL<2382> A_IWL<2381> A_IWL<2380> A_IWL<2379> A_IWL<2378> A_IWL<2377> A_IWL<2376> A_IWL<2375> A_IWL<2374> A_IWL<2373> A_IWL<2372> A_IWL<2371> A_IWL<2370> A_IWL<2369> A_IWL<2368> A_IWL<2367> A_IWL<2366> A_IWL<2365> A_IWL<2364> A_IWL<2363> A_IWL<2362> A_IWL<2361> A_IWL<2360> A_IWL<2359> A_IWL<2358> A_IWL<2357> A_IWL<2356> A_IWL<2355> A_IWL<2354> A_IWL<2353> A_IWL<2352> A_IWL<2351> A_IWL<2350> A_IWL<2349> A_IWL<2348> A_IWL<2347> A_IWL<2346> A_IWL<2345> A_IWL<2344> A_IWL<2343> A_IWL<2342> A_IWL<2341> A_IWL<2340> A_IWL<2339> A_IWL<2338> A_IWL<2337> A_IWL<2336> A_IWL<2335> A_IWL<2334> A_IWL<2333> A_IWL<2332> A_IWL<2331> A_IWL<2330> A_IWL<2329> A_IWL<2328> A_IWL<2327> A_IWL<2326> A_IWL<2325> A_IWL<2324> A_IWL<2323> A_IWL<2322> A_IWL<2321> A_IWL<2320> A_IWL<2319> A_IWL<2318> A_IWL<2317> A_IWL<2316> A_IWL<2315> A_IWL<2314> A_IWL<2313> A_IWL<2312> A_IWL<2311> A_IWL<2310> A_IWL<2309> A_IWL<2308> A_IWL<2307> A_IWL<2306> A_IWL<2305> A_IWL<2304> A_IWL<2303> A_IWL<2302> A_IWL<2301> A_IWL<2300> A_IWL<2299> A_IWL<2298> A_IWL<2297> A_IWL<2296> A_IWL<2295> A_IWL<2294> A_IWL<2293> A_IWL<2292> A_IWL<2291> A_IWL<2290> A_IWL<2289> A_IWL<2288> A_IWL<2287> A_IWL<2286> A_IWL<2285> A_IWL<2284> A_IWL<2283> A_IWL<2282> A_IWL<2281> A_IWL<2280> A_IWL<2279> A_IWL<2278> A_IWL<2277> A_IWL<2276> A_IWL<2275> A_IWL<2274> A_IWL<2273> A_IWL<2272> A_IWL<2271> A_IWL<2270> A_IWL<2269> A_IWL<2268> A_IWL<2267> A_IWL<2266> A_IWL<2265> A_IWL<2264> A_IWL<2263> A_IWL<2262> A_IWL<2261> A_IWL<2260> A_IWL<2259> A_IWL<2258> A_IWL<2257> A_IWL<2256> A_IWL<2255> A_IWL<2254> A_IWL<2253> A_IWL<2252> A_IWL<2251> A_IWL<2250> A_IWL<2249> A_IWL<2248> A_IWL<2247> A_IWL<2246> A_IWL<2245> A_IWL<2244> A_IWL<2243> A_IWL<2242> A_IWL<2241> A_IWL<2240> A_IWL<2239> A_IWL<2238> A_IWL<2237> A_IWL<2236> A_IWL<2235> A_IWL<2234> A_IWL<2233> A_IWL<2232> A_IWL<2231> A_IWL<2230> A_IWL<2229> A_IWL<2228> A_IWL<2227> A_IWL<2226> A_IWL<2225> A_IWL<2224> A_IWL<2223> A_IWL<2222> A_IWL<2221> A_IWL<2220> A_IWL<2219> A_IWL<2218> A_IWL<2217> A_IWL<2216> A_IWL<2215> A_IWL<2214> A_IWL<2213> A_IWL<2212> A_IWL<2211> A_IWL<2210> A_IWL<2209> A_IWL<2208> A_IWL<2207> A_IWL<2206> A_IWL<2205> A_IWL<2204> A_IWL<2203> A_IWL<2202> A_IWL<2201> A_IWL<2200> A_IWL<2199> A_IWL<2198> A_IWL<2197> A_IWL<2196> A_IWL<2195> A_IWL<2194> A_IWL<2193> A_IWL<2192> A_IWL<2191> A_IWL<2190> A_IWL<2189> A_IWL<2188> A_IWL<2187> A_IWL<2186> A_IWL<2185> A_IWL<2184> A_IWL<2183> A_IWL<2182> A_IWL<2181> A_IWL<2180> A_IWL<2179> A_IWL<2178> A_IWL<2177> A_IWL<2176> A_IWL<2175> A_IWL<2174> A_IWL<2173> A_IWL<2172> A_IWL<2171> A_IWL<2170> A_IWL<2169> A_IWL<2168> A_IWL<2167> A_IWL<2166> A_IWL<2165> A_IWL<2164> A_IWL<2163> A_IWL<2162> A_IWL<2161> A_IWL<2160> A_IWL<2159> A_IWL<2158> A_IWL<2157> A_IWL<2156> A_IWL<2155> A_IWL<2154> A_IWL<2153> A_IWL<2152> A_IWL<2151> A_IWL<2150> A_IWL<2149> A_IWL<2148> A_IWL<2147> A_IWL<2146> A_IWL<2145> A_IWL<2144> A_IWL<2143> A_IWL<2142> A_IWL<2141> A_IWL<2140> A_IWL<2139> A_IWL<2138> A_IWL<2137> A_IWL<2136> A_IWL<2135> A_IWL<2134> A_IWL<2133> A_IWL<2132> A_IWL<2131> A_IWL<2130> A_IWL<2129> A_IWL<2128> A_IWL<2127> A_IWL<2126> A_IWL<2125> A_IWL<2124> A_IWL<2123> A_IWL<2122> A_IWL<2121> A_IWL<2120> A_IWL<2119> A_IWL<2118> A_IWL<2117> A_IWL<2116> A_IWL<2115> A_IWL<2114> A_IWL<2113> A_IWL<2112> A_IWL<2111> A_IWL<2110> A_IWL<2109> A_IWL<2108> A_IWL<2107> A_IWL<2106> A_IWL<2105> A_IWL<2104> A_IWL<2103> A_IWL<2102> A_IWL<2101> A_IWL<2100> A_IWL<2099> A_IWL<2098> A_IWL<2097> A_IWL<2096> A_IWL<2095> A_IWL<2094> A_IWL<2093> A_IWL<2092> A_IWL<2091> A_IWL<2090> A_IWL<2089> A_IWL<2088> A_IWL<2087> A_IWL<2086> A_IWL<2085> A_IWL<2084> A_IWL<2083> A_IWL<2082> A_IWL<2081> A_IWL<2080> A_IWL<2079> A_IWL<2078> A_IWL<2077> A_IWL<2076> A_IWL<2075> A_IWL<2074> A_IWL<2073> A_IWL<2072> A_IWL<2071> A_IWL<2070> A_IWL<2069> A_IWL<2068> A_IWL<2067> A_IWL<2066> A_IWL<2065> A_IWL<2064> A_IWL<2063> A_IWL<2062> A_IWL<2061> A_IWL<2060> A_IWL<2059> A_IWL<2058> A_IWL<2057> A_IWL<2056> A_IWL<2055> A_IWL<2054> A_IWL<2053> A_IWL<2052> A_IWL<2051> A_IWL<2050> A_IWL<2049> A_IWL<2048> A_IWL<3071> A_IWL<3070> A_IWL<3069> A_IWL<3068> A_IWL<3067> A_IWL<3066> A_IWL<3065> A_IWL<3064> A_IWL<3063> A_IWL<3062> A_IWL<3061> A_IWL<3060> A_IWL<3059> A_IWL<3058> A_IWL<3057> A_IWL<3056> A_IWL<3055> A_IWL<3054> A_IWL<3053> A_IWL<3052> A_IWL<3051> A_IWL<3050> A_IWL<3049> A_IWL<3048> A_IWL<3047> A_IWL<3046> A_IWL<3045> A_IWL<3044> A_IWL<3043> A_IWL<3042> A_IWL<3041> A_IWL<3040> A_IWL<3039> A_IWL<3038> A_IWL<3037> A_IWL<3036> A_IWL<3035> A_IWL<3034> A_IWL<3033> A_IWL<3032> A_IWL<3031> A_IWL<3030> A_IWL<3029> A_IWL<3028> A_IWL<3027> A_IWL<3026> A_IWL<3025> A_IWL<3024> A_IWL<3023> A_IWL<3022> A_IWL<3021> A_IWL<3020> A_IWL<3019> A_IWL<3018> A_IWL<3017> A_IWL<3016> A_IWL<3015> A_IWL<3014> A_IWL<3013> A_IWL<3012> A_IWL<3011> A_IWL<3010> A_IWL<3009> A_IWL<3008> A_IWL<3007> A_IWL<3006> A_IWL<3005> A_IWL<3004> A_IWL<3003> A_IWL<3002> A_IWL<3001> A_IWL<3000> A_IWL<2999> A_IWL<2998> A_IWL<2997> A_IWL<2996> A_IWL<2995> A_IWL<2994> A_IWL<2993> A_IWL<2992> A_IWL<2991> A_IWL<2990> A_IWL<2989> A_IWL<2988> A_IWL<2987> A_IWL<2986> A_IWL<2985> A_IWL<2984> A_IWL<2983> A_IWL<2982> A_IWL<2981> A_IWL<2980> A_IWL<2979> A_IWL<2978> A_IWL<2977> A_IWL<2976> A_IWL<2975> A_IWL<2974> A_IWL<2973> A_IWL<2972> A_IWL<2971> A_IWL<2970> A_IWL<2969> A_IWL<2968> A_IWL<2967> A_IWL<2966> A_IWL<2965> A_IWL<2964> A_IWL<2963> A_IWL<2962> A_IWL<2961> A_IWL<2960> A_IWL<2959> A_IWL<2958> A_IWL<2957> A_IWL<2956> A_IWL<2955> A_IWL<2954> A_IWL<2953> A_IWL<2952> A_IWL<2951> A_IWL<2950> A_IWL<2949> A_IWL<2948> A_IWL<2947> A_IWL<2946> A_IWL<2945> A_IWL<2944> A_IWL<2943> A_IWL<2942> A_IWL<2941> A_IWL<2940> A_IWL<2939> A_IWL<2938> A_IWL<2937> A_IWL<2936> A_IWL<2935> A_IWL<2934> A_IWL<2933> A_IWL<2932> A_IWL<2931> A_IWL<2930> A_IWL<2929> A_IWL<2928> A_IWL<2927> A_IWL<2926> A_IWL<2925> A_IWL<2924> A_IWL<2923> A_IWL<2922> A_IWL<2921> A_IWL<2920> A_IWL<2919> A_IWL<2918> A_IWL<2917> A_IWL<2916> A_IWL<2915> A_IWL<2914> A_IWL<2913> A_IWL<2912> A_IWL<2911> A_IWL<2910> A_IWL<2909> A_IWL<2908> A_IWL<2907> A_IWL<2906> A_IWL<2905> A_IWL<2904> A_IWL<2903> A_IWL<2902> A_IWL<2901> A_IWL<2900> A_IWL<2899> A_IWL<2898> A_IWL<2897> A_IWL<2896> A_IWL<2895> A_IWL<2894> A_IWL<2893> A_IWL<2892> A_IWL<2891> A_IWL<2890> A_IWL<2889> A_IWL<2888> A_IWL<2887> A_IWL<2886> A_IWL<2885> A_IWL<2884> A_IWL<2883> A_IWL<2882> A_IWL<2881> A_IWL<2880> A_IWL<2879> A_IWL<2878> A_IWL<2877> A_IWL<2876> A_IWL<2875> A_IWL<2874> A_IWL<2873> A_IWL<2872> A_IWL<2871> A_IWL<2870> A_IWL<2869> A_IWL<2868> A_IWL<2867> A_IWL<2866> A_IWL<2865> A_IWL<2864> A_IWL<2863> A_IWL<2862> A_IWL<2861> A_IWL<2860> A_IWL<2859> A_IWL<2858> A_IWL<2857> A_IWL<2856> A_IWL<2855> A_IWL<2854> A_IWL<2853> A_IWL<2852> A_IWL<2851> A_IWL<2850> A_IWL<2849> A_IWL<2848> A_IWL<2847> A_IWL<2846> A_IWL<2845> A_IWL<2844> A_IWL<2843> A_IWL<2842> A_IWL<2841> A_IWL<2840> A_IWL<2839> A_IWL<2838> A_IWL<2837> A_IWL<2836> A_IWL<2835> A_IWL<2834> A_IWL<2833> A_IWL<2832> A_IWL<2831> A_IWL<2830> A_IWL<2829> A_IWL<2828> A_IWL<2827> A_IWL<2826> A_IWL<2825> A_IWL<2824> A_IWL<2823> A_IWL<2822> A_IWL<2821> A_IWL<2820> A_IWL<2819> A_IWL<2818> A_IWL<2817> A_IWL<2816> A_IWL<2815> A_IWL<2814> A_IWL<2813> A_IWL<2812> A_IWL<2811> A_IWL<2810> A_IWL<2809> A_IWL<2808> A_IWL<2807> A_IWL<2806> A_IWL<2805> A_IWL<2804> A_IWL<2803> A_IWL<2802> A_IWL<2801> A_IWL<2800> A_IWL<2799> A_IWL<2798> A_IWL<2797> A_IWL<2796> A_IWL<2795> A_IWL<2794> A_IWL<2793> A_IWL<2792> A_IWL<2791> A_IWL<2790> A_IWL<2789> A_IWL<2788> A_IWL<2787> A_IWL<2786> A_IWL<2785> A_IWL<2784> A_IWL<2783> A_IWL<2782> A_IWL<2781> A_IWL<2780> A_IWL<2779> A_IWL<2778> A_IWL<2777> A_IWL<2776> A_IWL<2775> A_IWL<2774> A_IWL<2773> A_IWL<2772> A_IWL<2771> A_IWL<2770> A_IWL<2769> A_IWL<2768> A_IWL<2767> A_IWL<2766> A_IWL<2765> A_IWL<2764> A_IWL<2763> A_IWL<2762> A_IWL<2761> A_IWL<2760> A_IWL<2759> A_IWL<2758> A_IWL<2757> A_IWL<2756> A_IWL<2755> A_IWL<2754> A_IWL<2753> A_IWL<2752> A_IWL<2751> A_IWL<2750> A_IWL<2749> A_IWL<2748> A_IWL<2747> A_IWL<2746> A_IWL<2745> A_IWL<2744> A_IWL<2743> A_IWL<2742> A_IWL<2741> A_IWL<2740> A_IWL<2739> A_IWL<2738> A_IWL<2737> A_IWL<2736> A_IWL<2735> A_IWL<2734> A_IWL<2733> A_IWL<2732> A_IWL<2731> A_IWL<2730> A_IWL<2729> A_IWL<2728> A_IWL<2727> A_IWL<2726> A_IWL<2725> A_IWL<2724> A_IWL<2723> A_IWL<2722> A_IWL<2721> A_IWL<2720> A_IWL<2719> A_IWL<2718> A_IWL<2717> A_IWL<2716> A_IWL<2715> A_IWL<2714> A_IWL<2713> A_IWL<2712> A_IWL<2711> A_IWL<2710> A_IWL<2709> A_IWL<2708> A_IWL<2707> A_IWL<2706> A_IWL<2705> A_IWL<2704> A_IWL<2703> A_IWL<2702> A_IWL<2701> A_IWL<2700> A_IWL<2699> A_IWL<2698> A_IWL<2697> A_IWL<2696> A_IWL<2695> A_IWL<2694> A_IWL<2693> A_IWL<2692> A_IWL<2691> A_IWL<2690> A_IWL<2689> A_IWL<2688> A_IWL<2687> A_IWL<2686> A_IWL<2685> A_IWL<2684> A_IWL<2683> A_IWL<2682> A_IWL<2681> A_IWL<2680> A_IWL<2679> A_IWL<2678> A_IWL<2677> A_IWL<2676> A_IWL<2675> A_IWL<2674> A_IWL<2673> A_IWL<2672> A_IWL<2671> A_IWL<2670> A_IWL<2669> A_IWL<2668> A_IWL<2667> A_IWL<2666> A_IWL<2665> A_IWL<2664> A_IWL<2663> A_IWL<2662> A_IWL<2661> A_IWL<2660> A_IWL<2659> A_IWL<2658> A_IWL<2657> A_IWL<2656> A_IWL<2655> A_IWL<2654> A_IWL<2653> A_IWL<2652> A_IWL<2651> A_IWL<2650> A_IWL<2649> A_IWL<2648> A_IWL<2647> A_IWL<2646> A_IWL<2645> A_IWL<2644> A_IWL<2643> A_IWL<2642> A_IWL<2641> A_IWL<2640> A_IWL<2639> A_IWL<2638> A_IWL<2637> A_IWL<2636> A_IWL<2635> A_IWL<2634> A_IWL<2633> A_IWL<2632> A_IWL<2631> A_IWL<2630> A_IWL<2629> A_IWL<2628> A_IWL<2627> A_IWL<2626> A_IWL<2625> A_IWL<2624> A_IWL<2623> A_IWL<2622> A_IWL<2621> A_IWL<2620> A_IWL<2619> A_IWL<2618> A_IWL<2617> A_IWL<2616> A_IWL<2615> A_IWL<2614> A_IWL<2613> A_IWL<2612> A_IWL<2611> A_IWL<2610> A_IWL<2609> A_IWL<2608> A_IWL<2607> A_IWL<2606> A_IWL<2605> A_IWL<2604> A_IWL<2603> A_IWL<2602> A_IWL<2601> A_IWL<2600> A_IWL<2599> A_IWL<2598> A_IWL<2597> A_IWL<2596> A_IWL<2595> A_IWL<2594> A_IWL<2593> A_IWL<2592> A_IWL<2591> A_IWL<2590> A_IWL<2589> A_IWL<2588> A_IWL<2587> A_IWL<2586> A_IWL<2585> A_IWL<2584> A_IWL<2583> A_IWL<2582> A_IWL<2581> A_IWL<2580> A_IWL<2579> A_IWL<2578> A_IWL<2577> A_IWL<2576> A_IWL<2575> A_IWL<2574> A_IWL<2573> A_IWL<2572> A_IWL<2571> A_IWL<2570> A_IWL<2569> A_IWL<2568> A_IWL<2567> A_IWL<2566> A_IWL<2565> A_IWL<2564> A_IWL<2563> A_IWL<2562> A_IWL<2561> A_IWL<2560> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0
+XCOL<4> A_BLC<9> A_BLC<8> A_BLC_TOP<9> A_BLC_TOP<8> A_BLT<9> A_BLT<8> A_BLT_TOP<9> A_BLT_TOP<8> A_IWL<2047> A_IWL<2046> A_IWL<2045> A_IWL<2044> A_IWL<2043> A_IWL<2042> A_IWL<2041> A_IWL<2040> A_IWL<2039> A_IWL<2038> A_IWL<2037> A_IWL<2036> A_IWL<2035> A_IWL<2034> A_IWL<2033> A_IWL<2032> A_IWL<2031> A_IWL<2030> A_IWL<2029> A_IWL<2028> A_IWL<2027> A_IWL<2026> A_IWL<2025> A_IWL<2024> A_IWL<2023> A_IWL<2022> A_IWL<2021> A_IWL<2020> A_IWL<2019> A_IWL<2018> A_IWL<2017> A_IWL<2016> A_IWL<2015> A_IWL<2014> A_IWL<2013> A_IWL<2012> A_IWL<2011> A_IWL<2010> A_IWL<2009> A_IWL<2008> A_IWL<2007> A_IWL<2006> A_IWL<2005> A_IWL<2004> A_IWL<2003> A_IWL<2002> A_IWL<2001> A_IWL<2000> A_IWL<1999> A_IWL<1998> A_IWL<1997> A_IWL<1996> A_IWL<1995> A_IWL<1994> A_IWL<1993> A_IWL<1992> A_IWL<1991> A_IWL<1990> A_IWL<1989> A_IWL<1988> A_IWL<1987> A_IWL<1986> A_IWL<1985> A_IWL<1984> A_IWL<1983> A_IWL<1982> A_IWL<1981> A_IWL<1980> A_IWL<1979> A_IWL<1978> A_IWL<1977> A_IWL<1976> A_IWL<1975> A_IWL<1974> A_IWL<1973> A_IWL<1972> A_IWL<1971> A_IWL<1970> A_IWL<1969> A_IWL<1968> A_IWL<1967> A_IWL<1966> A_IWL<1965> A_IWL<1964> A_IWL<1963> A_IWL<1962> A_IWL<1961> A_IWL<1960> A_IWL<1959> A_IWL<1958> A_IWL<1957> A_IWL<1956> A_IWL<1955> A_IWL<1954> A_IWL<1953> A_IWL<1952> A_IWL<1951> A_IWL<1950> A_IWL<1949> A_IWL<1948> A_IWL<1947> A_IWL<1946> A_IWL<1945> A_IWL<1944> A_IWL<1943> A_IWL<1942> A_IWL<1941> A_IWL<1940> A_IWL<1939> A_IWL<1938> A_IWL<1937> A_IWL<1936> A_IWL<1935> A_IWL<1934> A_IWL<1933> A_IWL<1932> A_IWL<1931> A_IWL<1930> A_IWL<1929> A_IWL<1928> A_IWL<1927> A_IWL<1926> A_IWL<1925> A_IWL<1924> A_IWL<1923> A_IWL<1922> A_IWL<1921> A_IWL<1920> A_IWL<1919> A_IWL<1918> A_IWL<1917> A_IWL<1916> A_IWL<1915> A_IWL<1914> A_IWL<1913> A_IWL<1912> A_IWL<1911> A_IWL<1910> A_IWL<1909> A_IWL<1908> A_IWL<1907> A_IWL<1906> A_IWL<1905> A_IWL<1904> A_IWL<1903> A_IWL<1902> A_IWL<1901> A_IWL<1900> A_IWL<1899> A_IWL<1898> A_IWL<1897> A_IWL<1896> A_IWL<1895> A_IWL<1894> A_IWL<1893> A_IWL<1892> A_IWL<1891> A_IWL<1890> A_IWL<1889> A_IWL<1888> A_IWL<1887> A_IWL<1886> A_IWL<1885> A_IWL<1884> A_IWL<1883> A_IWL<1882> A_IWL<1881> A_IWL<1880> A_IWL<1879> A_IWL<1878> A_IWL<1877> A_IWL<1876> A_IWL<1875> A_IWL<1874> A_IWL<1873> A_IWL<1872> A_IWL<1871> A_IWL<1870> A_IWL<1869> A_IWL<1868> A_IWL<1867> A_IWL<1866> A_IWL<1865> A_IWL<1864> A_IWL<1863> A_IWL<1862> A_IWL<1861> A_IWL<1860> A_IWL<1859> A_IWL<1858> A_IWL<1857> A_IWL<1856> A_IWL<1855> A_IWL<1854> A_IWL<1853> A_IWL<1852> A_IWL<1851> A_IWL<1850> A_IWL<1849> A_IWL<1848> A_IWL<1847> A_IWL<1846> A_IWL<1845> A_IWL<1844> A_IWL<1843> A_IWL<1842> A_IWL<1841> A_IWL<1840> A_IWL<1839> A_IWL<1838> A_IWL<1837> A_IWL<1836> A_IWL<1835> A_IWL<1834> A_IWL<1833> A_IWL<1832> A_IWL<1831> A_IWL<1830> A_IWL<1829> A_IWL<1828> A_IWL<1827> A_IWL<1826> A_IWL<1825> A_IWL<1824> A_IWL<1823> A_IWL<1822> A_IWL<1821> A_IWL<1820> A_IWL<1819> A_IWL<1818> A_IWL<1817> A_IWL<1816> A_IWL<1815> A_IWL<1814> A_IWL<1813> A_IWL<1812> A_IWL<1811> A_IWL<1810> A_IWL<1809> A_IWL<1808> A_IWL<1807> A_IWL<1806> A_IWL<1805> A_IWL<1804> A_IWL<1803> A_IWL<1802> A_IWL<1801> A_IWL<1800> A_IWL<1799> A_IWL<1798> A_IWL<1797> A_IWL<1796> A_IWL<1795> A_IWL<1794> A_IWL<1793> A_IWL<1792> A_IWL<1791> A_IWL<1790> A_IWL<1789> A_IWL<1788> A_IWL<1787> A_IWL<1786> A_IWL<1785> A_IWL<1784> A_IWL<1783> A_IWL<1782> A_IWL<1781> A_IWL<1780> A_IWL<1779> A_IWL<1778> A_IWL<1777> A_IWL<1776> A_IWL<1775> A_IWL<1774> A_IWL<1773> A_IWL<1772> A_IWL<1771> A_IWL<1770> A_IWL<1769> A_IWL<1768> A_IWL<1767> A_IWL<1766> A_IWL<1765> A_IWL<1764> A_IWL<1763> A_IWL<1762> A_IWL<1761> A_IWL<1760> A_IWL<1759> A_IWL<1758> A_IWL<1757> A_IWL<1756> A_IWL<1755> A_IWL<1754> A_IWL<1753> A_IWL<1752> A_IWL<1751> A_IWL<1750> A_IWL<1749> A_IWL<1748> A_IWL<1747> A_IWL<1746> A_IWL<1745> A_IWL<1744> A_IWL<1743> A_IWL<1742> A_IWL<1741> A_IWL<1740> A_IWL<1739> A_IWL<1738> A_IWL<1737> A_IWL<1736> A_IWL<1735> A_IWL<1734> A_IWL<1733> A_IWL<1732> A_IWL<1731> A_IWL<1730> A_IWL<1729> A_IWL<1728> A_IWL<1727> A_IWL<1726> A_IWL<1725> A_IWL<1724> A_IWL<1723> A_IWL<1722> A_IWL<1721> A_IWL<1720> A_IWL<1719> A_IWL<1718> A_IWL<1717> A_IWL<1716> A_IWL<1715> A_IWL<1714> A_IWL<1713> A_IWL<1712> A_IWL<1711> A_IWL<1710> A_IWL<1709> A_IWL<1708> A_IWL<1707> A_IWL<1706> A_IWL<1705> A_IWL<1704> A_IWL<1703> A_IWL<1702> A_IWL<1701> A_IWL<1700> A_IWL<1699> A_IWL<1698> A_IWL<1697> A_IWL<1696> A_IWL<1695> A_IWL<1694> A_IWL<1693> A_IWL<1692> A_IWL<1691> A_IWL<1690> A_IWL<1689> A_IWL<1688> A_IWL<1687> A_IWL<1686> A_IWL<1685> A_IWL<1684> A_IWL<1683> A_IWL<1682> A_IWL<1681> A_IWL<1680> A_IWL<1679> A_IWL<1678> A_IWL<1677> A_IWL<1676> A_IWL<1675> A_IWL<1674> A_IWL<1673> A_IWL<1672> A_IWL<1671> A_IWL<1670> A_IWL<1669> A_IWL<1668> A_IWL<1667> A_IWL<1666> A_IWL<1665> A_IWL<1664> A_IWL<1663> A_IWL<1662> A_IWL<1661> A_IWL<1660> A_IWL<1659> A_IWL<1658> A_IWL<1657> A_IWL<1656> A_IWL<1655> A_IWL<1654> A_IWL<1653> A_IWL<1652> A_IWL<1651> A_IWL<1650> A_IWL<1649> A_IWL<1648> A_IWL<1647> A_IWL<1646> A_IWL<1645> A_IWL<1644> A_IWL<1643> A_IWL<1642> A_IWL<1641> A_IWL<1640> A_IWL<1639> A_IWL<1638> A_IWL<1637> A_IWL<1636> A_IWL<1635> A_IWL<1634> A_IWL<1633> A_IWL<1632> A_IWL<1631> A_IWL<1630> A_IWL<1629> A_IWL<1628> A_IWL<1627> A_IWL<1626> A_IWL<1625> A_IWL<1624> A_IWL<1623> A_IWL<1622> A_IWL<1621> A_IWL<1620> A_IWL<1619> A_IWL<1618> A_IWL<1617> A_IWL<1616> A_IWL<1615> A_IWL<1614> A_IWL<1613> A_IWL<1612> A_IWL<1611> A_IWL<1610> A_IWL<1609> A_IWL<1608> A_IWL<1607> A_IWL<1606> A_IWL<1605> A_IWL<1604> A_IWL<1603> A_IWL<1602> A_IWL<1601> A_IWL<1600> A_IWL<1599> A_IWL<1598> A_IWL<1597> A_IWL<1596> A_IWL<1595> A_IWL<1594> A_IWL<1593> A_IWL<1592> A_IWL<1591> A_IWL<1590> A_IWL<1589> A_IWL<1588> A_IWL<1587> A_IWL<1586> A_IWL<1585> A_IWL<1584> A_IWL<1583> A_IWL<1582> A_IWL<1581> A_IWL<1580> A_IWL<1579> A_IWL<1578> A_IWL<1577> A_IWL<1576> A_IWL<1575> A_IWL<1574> A_IWL<1573> A_IWL<1572> A_IWL<1571> A_IWL<1570> A_IWL<1569> A_IWL<1568> A_IWL<1567> A_IWL<1566> A_IWL<1565> A_IWL<1564> A_IWL<1563> A_IWL<1562> A_IWL<1561> A_IWL<1560> A_IWL<1559> A_IWL<1558> A_IWL<1557> A_IWL<1556> A_IWL<1555> A_IWL<1554> A_IWL<1553> A_IWL<1552> A_IWL<1551> A_IWL<1550> A_IWL<1549> A_IWL<1548> A_IWL<1547> A_IWL<1546> A_IWL<1545> A_IWL<1544> A_IWL<1543> A_IWL<1542> A_IWL<1541> A_IWL<1540> A_IWL<1539> A_IWL<1538> A_IWL<1537> A_IWL<1536> A_IWL<2559> A_IWL<2558> A_IWL<2557> A_IWL<2556> A_IWL<2555> A_IWL<2554> A_IWL<2553> A_IWL<2552> A_IWL<2551> A_IWL<2550> A_IWL<2549> A_IWL<2548> A_IWL<2547> A_IWL<2546> A_IWL<2545> A_IWL<2544> A_IWL<2543> A_IWL<2542> A_IWL<2541> A_IWL<2540> A_IWL<2539> A_IWL<2538> A_IWL<2537> A_IWL<2536> A_IWL<2535> A_IWL<2534> A_IWL<2533> A_IWL<2532> A_IWL<2531> A_IWL<2530> A_IWL<2529> A_IWL<2528> A_IWL<2527> A_IWL<2526> A_IWL<2525> A_IWL<2524> A_IWL<2523> A_IWL<2522> A_IWL<2521> A_IWL<2520> A_IWL<2519> A_IWL<2518> A_IWL<2517> A_IWL<2516> A_IWL<2515> A_IWL<2514> A_IWL<2513> A_IWL<2512> A_IWL<2511> A_IWL<2510> A_IWL<2509> A_IWL<2508> A_IWL<2507> A_IWL<2506> A_IWL<2505> A_IWL<2504> A_IWL<2503> A_IWL<2502> A_IWL<2501> A_IWL<2500> A_IWL<2499> A_IWL<2498> A_IWL<2497> A_IWL<2496> A_IWL<2495> A_IWL<2494> A_IWL<2493> A_IWL<2492> A_IWL<2491> A_IWL<2490> A_IWL<2489> A_IWL<2488> A_IWL<2487> A_IWL<2486> A_IWL<2485> A_IWL<2484> A_IWL<2483> A_IWL<2482> A_IWL<2481> A_IWL<2480> A_IWL<2479> A_IWL<2478> A_IWL<2477> A_IWL<2476> A_IWL<2475> A_IWL<2474> A_IWL<2473> A_IWL<2472> A_IWL<2471> A_IWL<2470> A_IWL<2469> A_IWL<2468> A_IWL<2467> A_IWL<2466> A_IWL<2465> A_IWL<2464> A_IWL<2463> A_IWL<2462> A_IWL<2461> A_IWL<2460> A_IWL<2459> A_IWL<2458> A_IWL<2457> A_IWL<2456> A_IWL<2455> A_IWL<2454> A_IWL<2453> A_IWL<2452> A_IWL<2451> A_IWL<2450> A_IWL<2449> A_IWL<2448> A_IWL<2447> A_IWL<2446> A_IWL<2445> A_IWL<2444> A_IWL<2443> A_IWL<2442> A_IWL<2441> A_IWL<2440> A_IWL<2439> A_IWL<2438> A_IWL<2437> A_IWL<2436> A_IWL<2435> A_IWL<2434> A_IWL<2433> A_IWL<2432> A_IWL<2431> A_IWL<2430> A_IWL<2429> A_IWL<2428> A_IWL<2427> A_IWL<2426> A_IWL<2425> A_IWL<2424> A_IWL<2423> A_IWL<2422> A_IWL<2421> A_IWL<2420> A_IWL<2419> A_IWL<2418> A_IWL<2417> A_IWL<2416> A_IWL<2415> A_IWL<2414> A_IWL<2413> A_IWL<2412> A_IWL<2411> A_IWL<2410> A_IWL<2409> A_IWL<2408> A_IWL<2407> A_IWL<2406> A_IWL<2405> A_IWL<2404> A_IWL<2403> A_IWL<2402> A_IWL<2401> A_IWL<2400> A_IWL<2399> A_IWL<2398> A_IWL<2397> A_IWL<2396> A_IWL<2395> A_IWL<2394> A_IWL<2393> A_IWL<2392> A_IWL<2391> A_IWL<2390> A_IWL<2389> A_IWL<2388> A_IWL<2387> A_IWL<2386> A_IWL<2385> A_IWL<2384> A_IWL<2383> A_IWL<2382> A_IWL<2381> A_IWL<2380> A_IWL<2379> A_IWL<2378> A_IWL<2377> A_IWL<2376> A_IWL<2375> A_IWL<2374> A_IWL<2373> A_IWL<2372> A_IWL<2371> A_IWL<2370> A_IWL<2369> A_IWL<2368> A_IWL<2367> A_IWL<2366> A_IWL<2365> A_IWL<2364> A_IWL<2363> A_IWL<2362> A_IWL<2361> A_IWL<2360> A_IWL<2359> A_IWL<2358> A_IWL<2357> A_IWL<2356> A_IWL<2355> A_IWL<2354> A_IWL<2353> A_IWL<2352> A_IWL<2351> A_IWL<2350> A_IWL<2349> A_IWL<2348> A_IWL<2347> A_IWL<2346> A_IWL<2345> A_IWL<2344> A_IWL<2343> A_IWL<2342> A_IWL<2341> A_IWL<2340> A_IWL<2339> A_IWL<2338> A_IWL<2337> A_IWL<2336> A_IWL<2335> A_IWL<2334> A_IWL<2333> A_IWL<2332> A_IWL<2331> A_IWL<2330> A_IWL<2329> A_IWL<2328> A_IWL<2327> A_IWL<2326> A_IWL<2325> A_IWL<2324> A_IWL<2323> A_IWL<2322> A_IWL<2321> A_IWL<2320> A_IWL<2319> A_IWL<2318> A_IWL<2317> A_IWL<2316> A_IWL<2315> A_IWL<2314> A_IWL<2313> A_IWL<2312> A_IWL<2311> A_IWL<2310> A_IWL<2309> A_IWL<2308> A_IWL<2307> A_IWL<2306> A_IWL<2305> A_IWL<2304> A_IWL<2303> A_IWL<2302> A_IWL<2301> A_IWL<2300> A_IWL<2299> A_IWL<2298> A_IWL<2297> A_IWL<2296> A_IWL<2295> A_IWL<2294> A_IWL<2293> A_IWL<2292> A_IWL<2291> A_IWL<2290> A_IWL<2289> A_IWL<2288> A_IWL<2287> A_IWL<2286> A_IWL<2285> A_IWL<2284> A_IWL<2283> A_IWL<2282> A_IWL<2281> A_IWL<2280> A_IWL<2279> A_IWL<2278> A_IWL<2277> A_IWL<2276> A_IWL<2275> A_IWL<2274> A_IWL<2273> A_IWL<2272> A_IWL<2271> A_IWL<2270> A_IWL<2269> A_IWL<2268> A_IWL<2267> A_IWL<2266> A_IWL<2265> A_IWL<2264> A_IWL<2263> A_IWL<2262> A_IWL<2261> A_IWL<2260> A_IWL<2259> A_IWL<2258> A_IWL<2257> A_IWL<2256> A_IWL<2255> A_IWL<2254> A_IWL<2253> A_IWL<2252> A_IWL<2251> A_IWL<2250> A_IWL<2249> A_IWL<2248> A_IWL<2247> A_IWL<2246> A_IWL<2245> A_IWL<2244> A_IWL<2243> A_IWL<2242> A_IWL<2241> A_IWL<2240> A_IWL<2239> A_IWL<2238> A_IWL<2237> A_IWL<2236> A_IWL<2235> A_IWL<2234> A_IWL<2233> A_IWL<2232> A_IWL<2231> A_IWL<2230> A_IWL<2229> A_IWL<2228> A_IWL<2227> A_IWL<2226> A_IWL<2225> A_IWL<2224> A_IWL<2223> A_IWL<2222> A_IWL<2221> A_IWL<2220> A_IWL<2219> A_IWL<2218> A_IWL<2217> A_IWL<2216> A_IWL<2215> A_IWL<2214> A_IWL<2213> A_IWL<2212> A_IWL<2211> A_IWL<2210> A_IWL<2209> A_IWL<2208> A_IWL<2207> A_IWL<2206> A_IWL<2205> A_IWL<2204> A_IWL<2203> A_IWL<2202> A_IWL<2201> A_IWL<2200> A_IWL<2199> A_IWL<2198> A_IWL<2197> A_IWL<2196> A_IWL<2195> A_IWL<2194> A_IWL<2193> A_IWL<2192> A_IWL<2191> A_IWL<2190> A_IWL<2189> A_IWL<2188> A_IWL<2187> A_IWL<2186> A_IWL<2185> A_IWL<2184> A_IWL<2183> A_IWL<2182> A_IWL<2181> A_IWL<2180> A_IWL<2179> A_IWL<2178> A_IWL<2177> A_IWL<2176> A_IWL<2175> A_IWL<2174> A_IWL<2173> A_IWL<2172> A_IWL<2171> A_IWL<2170> A_IWL<2169> A_IWL<2168> A_IWL<2167> A_IWL<2166> A_IWL<2165> A_IWL<2164> A_IWL<2163> A_IWL<2162> A_IWL<2161> A_IWL<2160> A_IWL<2159> A_IWL<2158> A_IWL<2157> A_IWL<2156> A_IWL<2155> A_IWL<2154> A_IWL<2153> A_IWL<2152> A_IWL<2151> A_IWL<2150> A_IWL<2149> A_IWL<2148> A_IWL<2147> A_IWL<2146> A_IWL<2145> A_IWL<2144> A_IWL<2143> A_IWL<2142> A_IWL<2141> A_IWL<2140> A_IWL<2139> A_IWL<2138> A_IWL<2137> A_IWL<2136> A_IWL<2135> A_IWL<2134> A_IWL<2133> A_IWL<2132> A_IWL<2131> A_IWL<2130> A_IWL<2129> A_IWL<2128> A_IWL<2127> A_IWL<2126> A_IWL<2125> A_IWL<2124> A_IWL<2123> A_IWL<2122> A_IWL<2121> A_IWL<2120> A_IWL<2119> A_IWL<2118> A_IWL<2117> A_IWL<2116> A_IWL<2115> A_IWL<2114> A_IWL<2113> A_IWL<2112> A_IWL<2111> A_IWL<2110> A_IWL<2109> A_IWL<2108> A_IWL<2107> A_IWL<2106> A_IWL<2105> A_IWL<2104> A_IWL<2103> A_IWL<2102> A_IWL<2101> A_IWL<2100> A_IWL<2099> A_IWL<2098> A_IWL<2097> A_IWL<2096> A_IWL<2095> A_IWL<2094> A_IWL<2093> A_IWL<2092> A_IWL<2091> A_IWL<2090> A_IWL<2089> A_IWL<2088> A_IWL<2087> A_IWL<2086> A_IWL<2085> A_IWL<2084> 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A_IWL<1820> A_IWL<1819> A_IWL<1818> A_IWL<1817> A_IWL<1816> A_IWL<1815> A_IWL<1814> A_IWL<1813> A_IWL<1812> A_IWL<1811> A_IWL<1810> A_IWL<1809> A_IWL<1808> A_IWL<1807> A_IWL<1806> A_IWL<1805> A_IWL<1804> A_IWL<1803> A_IWL<1802> A_IWL<1801> A_IWL<1800> A_IWL<1799> A_IWL<1798> A_IWL<1797> A_IWL<1796> A_IWL<1795> A_IWL<1794> A_IWL<1793> A_IWL<1792> A_IWL<1791> A_IWL<1790> A_IWL<1789> A_IWL<1788> A_IWL<1787> A_IWL<1786> A_IWL<1785> A_IWL<1784> A_IWL<1783> A_IWL<1782> A_IWL<1781> A_IWL<1780> A_IWL<1779> A_IWL<1778> A_IWL<1777> A_IWL<1776> A_IWL<1775> A_IWL<1774> A_IWL<1773> A_IWL<1772> A_IWL<1771> A_IWL<1770> A_IWL<1769> A_IWL<1768> A_IWL<1767> A_IWL<1766> A_IWL<1765> A_IWL<1764> A_IWL<1763> A_IWL<1762> A_IWL<1761> A_IWL<1760> A_IWL<1759> A_IWL<1758> A_IWL<1757> A_IWL<1756> A_IWL<1755> A_IWL<1754> A_IWL<1753> A_IWL<1752> A_IWL<1751> A_IWL<1750> A_IWL<1749> A_IWL<1748> A_IWL<1747> A_IWL<1746> A_IWL<1745> A_IWL<1744> A_IWL<1743> A_IWL<1742> A_IWL<1741> A_IWL<1740> A_IWL<1739> A_IWL<1738> A_IWL<1737> A_IWL<1736> A_IWL<1735> A_IWL<1734> A_IWL<1733> A_IWL<1732> A_IWL<1731> A_IWL<1730> A_IWL<1729> A_IWL<1728> A_IWL<1727> A_IWL<1726> A_IWL<1725> A_IWL<1724> A_IWL<1723> A_IWL<1722> A_IWL<1721> A_IWL<1720> A_IWL<1719> A_IWL<1718> A_IWL<1717> A_IWL<1716> A_IWL<1715> A_IWL<1714> A_IWL<1713> A_IWL<1712> A_IWL<1711> A_IWL<1710> A_IWL<1709> A_IWL<1708> A_IWL<1707> A_IWL<1706> A_IWL<1705> A_IWL<1704> A_IWL<1703> A_IWL<1702> A_IWL<1701> A_IWL<1700> A_IWL<1699> A_IWL<1698> A_IWL<1697> A_IWL<1696> A_IWL<1695> A_IWL<1694> A_IWL<1693> A_IWL<1692> A_IWL<1691> A_IWL<1690> A_IWL<1689> A_IWL<1688> A_IWL<1687> A_IWL<1686> A_IWL<1685> A_IWL<1684> A_IWL<1683> A_IWL<1682> A_IWL<1681> A_IWL<1680> A_IWL<1679> A_IWL<1678> A_IWL<1677> A_IWL<1676> A_IWL<1675> A_IWL<1674> A_IWL<1673> A_IWL<1672> A_IWL<1671> A_IWL<1670> A_IWL<1669> A_IWL<1668> A_IWL<1667> A_IWL<1666> A_IWL<1665> A_IWL<1664> A_IWL<1663> A_IWL<1662> A_IWL<1661> A_IWL<1660> A_IWL<1659> A_IWL<1658> A_IWL<1657> A_IWL<1656> A_IWL<1655> A_IWL<1654> A_IWL<1653> A_IWL<1652> A_IWL<1651> A_IWL<1650> A_IWL<1649> A_IWL<1648> A_IWL<1647> A_IWL<1646> A_IWL<1645> A_IWL<1644> A_IWL<1643> A_IWL<1642> A_IWL<1641> A_IWL<1640> A_IWL<1639> A_IWL<1638> A_IWL<1637> A_IWL<1636> A_IWL<1635> A_IWL<1634> A_IWL<1633> A_IWL<1632> A_IWL<1631> A_IWL<1630> A_IWL<1629> A_IWL<1628> A_IWL<1627> A_IWL<1626> A_IWL<1625> A_IWL<1624> A_IWL<1623> A_IWL<1622> A_IWL<1621> A_IWL<1620> A_IWL<1619> A_IWL<1618> A_IWL<1617> A_IWL<1616> A_IWL<1615> A_IWL<1614> A_IWL<1613> A_IWL<1612> A_IWL<1611> A_IWL<1610> A_IWL<1609> A_IWL<1608> A_IWL<1607> A_IWL<1606> A_IWL<1605> A_IWL<1604> A_IWL<1603> A_IWL<1602> A_IWL<1601> A_IWL<1600> A_IWL<1599> A_IWL<1598> A_IWL<1597> A_IWL<1596> A_IWL<1595> A_IWL<1594> A_IWL<1593> A_IWL<1592> A_IWL<1591> A_IWL<1590> A_IWL<1589> A_IWL<1588> A_IWL<1587> A_IWL<1586> A_IWL<1585> A_IWL<1584> A_IWL<1583> A_IWL<1582> A_IWL<1581> A_IWL<1580> A_IWL<1579> A_IWL<1578> A_IWL<1577> A_IWL<1576> A_IWL<1575> A_IWL<1574> A_IWL<1573> A_IWL<1572> A_IWL<1571> A_IWL<1570> A_IWL<1569> A_IWL<1568> A_IWL<1567> A_IWL<1566> A_IWL<1565> A_IWL<1564> A_IWL<1563> A_IWL<1562> A_IWL<1561> A_IWL<1560> A_IWL<1559> A_IWL<1558> A_IWL<1557> A_IWL<1556> A_IWL<1555> A_IWL<1554> A_IWL<1553> A_IWL<1552> A_IWL<1551> A_IWL<1550> A_IWL<1549> A_IWL<1548> A_IWL<1547> A_IWL<1546> A_IWL<1545> A_IWL<1544> A_IWL<1543> A_IWL<1542> A_IWL<1541> A_IWL<1540> A_IWL<1539> A_IWL<1538> A_IWL<1537> A_IWL<1536> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0
+XCOL<2> A_BLC<5> A_BLC<4> A_BLC_TOP<5> A_BLC_TOP<4> A_BLT<5> A_BLT<4> A_BLT_TOP<5> A_BLT_TOP<4> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> A_IWL<1535> A_IWL<1534> A_IWL<1533> A_IWL<1532> A_IWL<1531> A_IWL<1530> A_IWL<1529> A_IWL<1528> A_IWL<1527> A_IWL<1526> A_IWL<1525> A_IWL<1524> A_IWL<1523> A_IWL<1522> A_IWL<1521> A_IWL<1520> A_IWL<1519> A_IWL<1518> A_IWL<1517> A_IWL<1516> A_IWL<1515> A_IWL<1514> A_IWL<1513> A_IWL<1512> A_IWL<1511> A_IWL<1510> A_IWL<1509> A_IWL<1508> A_IWL<1507> A_IWL<1506> A_IWL<1505> A_IWL<1504> A_IWL<1503> A_IWL<1502> A_IWL<1501> A_IWL<1500> A_IWL<1499> A_IWL<1498> A_IWL<1497> A_IWL<1496> A_IWL<1495> A_IWL<1494> A_IWL<1493> A_IWL<1492> A_IWL<1491> A_IWL<1490> A_IWL<1489> A_IWL<1488> A_IWL<1487> A_IWL<1486> A_IWL<1485> A_IWL<1484> A_IWL<1483> A_IWL<1482> A_IWL<1481> A_IWL<1480> A_IWL<1479> A_IWL<1478> A_IWL<1477> A_IWL<1476> A_IWL<1475> A_IWL<1474> A_IWL<1473> A_IWL<1472> A_IWL<1471> A_IWL<1470> A_IWL<1469> A_IWL<1468> A_IWL<1467> A_IWL<1466> A_IWL<1465> A_IWL<1464> A_IWL<1463> A_IWL<1462> A_IWL<1461> A_IWL<1460> A_IWL<1459> A_IWL<1458> A_IWL<1457> A_IWL<1456> A_IWL<1455> A_IWL<1454> A_IWL<1453> A_IWL<1452> A_IWL<1451> A_IWL<1450> A_IWL<1449> A_IWL<1448> A_IWL<1447> A_IWL<1446> A_IWL<1445> A_IWL<1444> A_IWL<1443> A_IWL<1442> A_IWL<1441> A_IWL<1440> A_IWL<1439> A_IWL<1438> A_IWL<1437> A_IWL<1436> A_IWL<1435> A_IWL<1434> A_IWL<1433> A_IWL<1432> A_IWL<1431> A_IWL<1430> A_IWL<1429> A_IWL<1428> A_IWL<1427> A_IWL<1426> A_IWL<1425> A_IWL<1424> A_IWL<1423> A_IWL<1422> A_IWL<1421> A_IWL<1420> A_IWL<1419> A_IWL<1418> A_IWL<1417> A_IWL<1416> A_IWL<1415> A_IWL<1414> A_IWL<1413> A_IWL<1412> A_IWL<1411> A_IWL<1410> A_IWL<1409> A_IWL<1408> A_IWL<1407> A_IWL<1406> A_IWL<1405> A_IWL<1404> A_IWL<1403> A_IWL<1402> A_IWL<1401> A_IWL<1400> A_IWL<1399> A_IWL<1398> A_IWL<1397> A_IWL<1396> A_IWL<1395> A_IWL<1394> A_IWL<1393> A_IWL<1392> A_IWL<1391> A_IWL<1390> A_IWL<1389> A_IWL<1388> A_IWL<1387> A_IWL<1386> A_IWL<1385> A_IWL<1384> A_IWL<1383> A_IWL<1382> A_IWL<1381> A_IWL<1380> A_IWL<1379> A_IWL<1378> A_IWL<1377> A_IWL<1376> A_IWL<1375> A_IWL<1374> A_IWL<1373> A_IWL<1372> A_IWL<1371> A_IWL<1370> A_IWL<1369> A_IWL<1368> A_IWL<1367> A_IWL<1366> A_IWL<1365> A_IWL<1364> A_IWL<1363> A_IWL<1362> A_IWL<1361> A_IWL<1360> A_IWL<1359> A_IWL<1358> A_IWL<1357> A_IWL<1356> A_IWL<1355> A_IWL<1354> A_IWL<1353> A_IWL<1352> A_IWL<1351> A_IWL<1350> A_IWL<1349> A_IWL<1348> A_IWL<1347> A_IWL<1346> A_IWL<1345> A_IWL<1344> A_IWL<1343> A_IWL<1342> A_IWL<1341> A_IWL<1340> A_IWL<1339> A_IWL<1338> A_IWL<1337> A_IWL<1336> A_IWL<1335> A_IWL<1334> A_IWL<1333> A_IWL<1332> A_IWL<1331> A_IWL<1330> A_IWL<1329> A_IWL<1328> A_IWL<1327> A_IWL<1326> A_IWL<1325> A_IWL<1324> A_IWL<1323> A_IWL<1322> A_IWL<1321> A_IWL<1320> A_IWL<1319> A_IWL<1318> A_IWL<1317> A_IWL<1316> A_IWL<1315> A_IWL<1314> A_IWL<1313> A_IWL<1312> A_IWL<1311> A_IWL<1310> A_IWL<1309> A_IWL<1308> A_IWL<1307> A_IWL<1306> A_IWL<1305> A_IWL<1304> A_IWL<1303> A_IWL<1302> A_IWL<1301> A_IWL<1300> A_IWL<1299> A_IWL<1298> A_IWL<1297> A_IWL<1296> A_IWL<1295> A_IWL<1294> A_IWL<1293> A_IWL<1292> A_IWL<1291> A_IWL<1290> A_IWL<1289> A_IWL<1288> A_IWL<1287> A_IWL<1286> A_IWL<1285> A_IWL<1284> A_IWL<1283> A_IWL<1282> A_IWL<1281> A_IWL<1280> A_IWL<1279> A_IWL<1278> A_IWL<1277> A_IWL<1276> A_IWL<1275> A_IWL<1274> A_IWL<1273> A_IWL<1272> A_IWL<1271> A_IWL<1270> A_IWL<1269> A_IWL<1268> A_IWL<1267> A_IWL<1266> A_IWL<1265> A_IWL<1264> A_IWL<1263> A_IWL<1262> A_IWL<1261> A_IWL<1260> A_IWL<1259> A_IWL<1258> A_IWL<1257> A_IWL<1256> A_IWL<1255> A_IWL<1254> A_IWL<1253> A_IWL<1252> A_IWL<1251> A_IWL<1250> A_IWL<1249> A_IWL<1248> A_IWL<1247> A_IWL<1246> A_IWL<1245> A_IWL<1244> A_IWL<1243> A_IWL<1242> A_IWL<1241> A_IWL<1240> A_IWL<1239> A_IWL<1238> A_IWL<1237> A_IWL<1236> A_IWL<1235> A_IWL<1234> A_IWL<1233> A_IWL<1232> A_IWL<1231> A_IWL<1230> A_IWL<1229> A_IWL<1228> A_IWL<1227> A_IWL<1226> A_IWL<1225> A_IWL<1224> A_IWL<1223> A_IWL<1222> A_IWL<1221> A_IWL<1220> A_IWL<1219> A_IWL<1218> A_IWL<1217> A_IWL<1216> A_IWL<1215> A_IWL<1214> A_IWL<1213> A_IWL<1212> A_IWL<1211> A_IWL<1210> A_IWL<1209> A_IWL<1208> A_IWL<1207> A_IWL<1206> A_IWL<1205> A_IWL<1204> A_IWL<1203> A_IWL<1202> A_IWL<1201> A_IWL<1200> A_IWL<1199> A_IWL<1198> A_IWL<1197> A_IWL<1196> A_IWL<1195> A_IWL<1194> A_IWL<1193> A_IWL<1192> A_IWL<1191> A_IWL<1190> A_IWL<1189> A_IWL<1188> A_IWL<1187> A_IWL<1186> A_IWL<1185> A_IWL<1184> A_IWL<1183> A_IWL<1182> A_IWL<1181> A_IWL<1180> A_IWL<1179> A_IWL<1178> A_IWL<1177> A_IWL<1176> A_IWL<1175> A_IWL<1174> A_IWL<1173> A_IWL<1172> A_IWL<1171> A_IWL<1170> A_IWL<1169> A_IWL<1168> A_IWL<1167> A_IWL<1166> A_IWL<1165> A_IWL<1164> A_IWL<1163> A_IWL<1162> A_IWL<1161> A_IWL<1160> A_IWL<1159> A_IWL<1158> A_IWL<1157> A_IWL<1156> A_IWL<1155> A_IWL<1154> A_IWL<1153> A_IWL<1152> A_IWL<1151> A_IWL<1150> A_IWL<1149> A_IWL<1148> A_IWL<1147> A_IWL<1146> A_IWL<1145> A_IWL<1144> A_IWL<1143> A_IWL<1142> A_IWL<1141> A_IWL<1140> A_IWL<1139> A_IWL<1138> A_IWL<1137> A_IWL<1136> A_IWL<1135> A_IWL<1134> A_IWL<1133> A_IWL<1132> A_IWL<1131> A_IWL<1130> A_IWL<1129> A_IWL<1128> A_IWL<1127> A_IWL<1126> A_IWL<1125> A_IWL<1124> A_IWL<1123> A_IWL<1122> A_IWL<1121> A_IWL<1120> A_IWL<1119> A_IWL<1118> A_IWL<1117> A_IWL<1116> A_IWL<1115> A_IWL<1114> A_IWL<1113> A_IWL<1112> A_IWL<1111> A_IWL<1110> A_IWL<1109> A_IWL<1108> A_IWL<1107> A_IWL<1106> A_IWL<1105> A_IWL<1104> A_IWL<1103> A_IWL<1102> A_IWL<1101> A_IWL<1100> A_IWL<1099> A_IWL<1098> A_IWL<1097> A_IWL<1096> A_IWL<1095> A_IWL<1094> A_IWL<1093> A_IWL<1092> A_IWL<1091> A_IWL<1090> A_IWL<1089> A_IWL<1088> A_IWL<1087> A_IWL<1086> A_IWL<1085> A_IWL<1084> A_IWL<1083> A_IWL<1082> A_IWL<1081> A_IWL<1080> A_IWL<1079> A_IWL<1078> A_IWL<1077> A_IWL<1076> A_IWL<1075> A_IWL<1074> A_IWL<1073> A_IWL<1072> A_IWL<1071> A_IWL<1070> A_IWL<1069> A_IWL<1068> A_IWL<1067> A_IWL<1066> A_IWL<1065> A_IWL<1064> A_IWL<1063> A_IWL<1062> A_IWL<1061> A_IWL<1060> A_IWL<1059> A_IWL<1058> A_IWL<1057> A_IWL<1056> A_IWL<1055> A_IWL<1054> A_IWL<1053> A_IWL<1052> A_IWL<1051> A_IWL<1050> A_IWL<1049> A_IWL<1048> A_IWL<1047> A_IWL<1046> A_IWL<1045> A_IWL<1044> A_IWL<1043> A_IWL<1042> A_IWL<1041> A_IWL<1040> A_IWL<1039> A_IWL<1038> A_IWL<1037> A_IWL<1036> A_IWL<1035> A_IWL<1034> A_IWL<1033> A_IWL<1032> A_IWL<1031> A_IWL<1030> A_IWL<1029> A_IWL<1028> A_IWL<1027> A_IWL<1026> A_IWL<1025> A_IWL<1024> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0
+XCOL<1> A_BLC<3> A_BLC<2> A_BLC_TOP<3> A_BLC_TOP<2> A_BLT<3> A_BLT<2> A_BLT_TOP<3> A_BLT_TOP<2> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0
+XCOL<0> A_BLC<1> A_BLC<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<1> A_BLT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_WL<511> A_WL<510> A_WL<509> A_WL<508> A_WL<507> A_WL<506> A_WL<505> A_WL<504> A_WL<503> A_WL<502> A_WL<501> A_WL<500> A_WL<499> A_WL<498> A_WL<497> A_WL<496> A_WL<495> A_WL<494> A_WL<493> A_WL<492> A_WL<491> A_WL<490> A_WL<489> A_WL<488> A_WL<487> A_WL<486> A_WL<485> A_WL<484> A_WL<483> A_WL<482> A_WL<481> A_WL<480> A_WL<479> A_WL<478> A_WL<477> A_WL<476> A_WL<475> A_WL<474> A_WL<473> A_WL<472> A_WL<471> A_WL<470> A_WL<469> A_WL<468> A_WL<467> A_WL<466> A_WL<465> A_WL<464> A_WL<463> A_WL<462> A_WL<461> A_WL<460> A_WL<459> A_WL<458> A_WL<457> A_WL<456> A_WL<455> A_WL<454> A_WL<453> A_WL<452> A_WL<451> A_WL<450> A_WL<449> A_WL<448> A_WL<447> A_WL<446> A_WL<445> A_WL<444> A_WL<443> A_WL<442> A_WL<441> A_WL<440> A_WL<439> A_WL<438> A_WL<437> A_WL<436> A_WL<435> A_WL<434> A_WL<433> A_WL<432> A_WL<431> A_WL<430> A_WL<429> A_WL<428> A_WL<427> A_WL<426> A_WL<425> A_WL<424> A_WL<423> A_WL<422> A_WL<421> A_WL<420> A_WL<419> A_WL<418> A_WL<417> A_WL<416> A_WL<415> A_WL<414> A_WL<413> A_WL<412> A_WL<411> A_WL<410> A_WL<409> A_WL<408> A_WL<407> A_WL<406> A_WL<405> A_WL<404> A_WL<403> A_WL<402> A_WL<401> A_WL<400> A_WL<399> A_WL<398> A_WL<397> A_WL<396> A_WL<395> A_WL<394> A_WL<393> A_WL<392> A_WL<391> A_WL<390> A_WL<389> A_WL<388> A_WL<387> A_WL<386> A_WL<385> A_WL<384> A_WL<383> A_WL<382> A_WL<381> A_WL<380> A_WL<379> A_WL<378> A_WL<377> A_WL<376> A_WL<375> A_WL<374> A_WL<373> A_WL<372> A_WL<371> A_WL<370> A_WL<369> A_WL<368> A_WL<367> A_WL<366> A_WL<365> A_WL<364> A_WL<363> A_WL<362> A_WL<361> A_WL<360> A_WL<359> A_WL<358> A_WL<357> A_WL<356> A_WL<355> A_WL<354> A_WL<353> A_WL<352> A_WL<351> A_WL<350> A_WL<349> A_WL<348> A_WL<347> A_WL<346> A_WL<345> A_WL<344> A_WL<343> A_WL<342> A_WL<341> A_WL<340> A_WL<339> A_WL<338> A_WL<337> A_WL<336> A_WL<335> A_WL<334> A_WL<333> A_WL<332> A_WL<331> A_WL<330> A_WL<329> A_WL<328> A_WL<327> A_WL<326> A_WL<325> A_WL<324> A_WL<323> A_WL<322> A_WL<321> A_WL<320> A_WL<319> A_WL<318> A_WL<317> A_WL<316> A_WL<315> A_WL<314> A_WL<313> A_WL<312> A_WL<311> A_WL<310> A_WL<309> A_WL<308> A_WL<307> A_WL<306> A_WL<305> A_WL<304> A_WL<303> A_WL<302> A_WL<301> A_WL<300> A_WL<299> A_WL<298> A_WL<297> A_WL<296> A_WL<295> A_WL<294> A_WL<293> A_WL<292> A_WL<291> A_WL<290> A_WL<289> A_WL<288> A_WL<287> A_WL<286> A_WL<285> A_WL<284> A_WL<283> A_WL<282> A_WL<281> A_WL<280> A_WL<279> A_WL<278> A_WL<277> A_WL<276> A_WL<275> A_WL<274> A_WL<273> A_WL<272> A_WL<271> A_WL<270> A_WL<269> A_WL<268> A_WL<267> A_WL<266> A_WL<265> A_WL<264> A_WL<263> A_WL<262> A_WL<261> A_WL<260> A_WL<259> A_WL<258> A_WL<257> A_WL<256> A_WL<255> A_WL<254> A_WL<253> A_WL<252> A_WL<251> A_WL<250> A_WL<249> A_WL<248> A_WL<247> A_WL<246> A_WL<245> A_WL<244> A_WL<243> A_WL<242> A_WL<241> A_WL<240> A_WL<239> A_WL<238> A_WL<237> A_WL<236> A_WL<235> A_WL<234> A_WL<233> A_WL<232> A_WL<231> A_WL<230> A_WL<229> A_WL<228> A_WL<227> A_WL<226> A_WL<225> A_WL<224> A_WL<223> A_WL<222> A_WL<221> A_WL<220> A_WL<219> A_WL<218> A_WL<217> A_WL<216> A_WL<215> A_WL<214> A_WL<213> A_WL<212> A_WL<211> A_WL<210> A_WL<209> A_WL<208> A_WL<207> A_WL<206> A_WL<205> A_WL<204> A_WL<203> A_WL<202> A_WL<201> A_WL<200> A_WL<199> A_WL<198> A_WL<197> A_WL<196> A_WL<195> A_WL<194> A_WL<193> A_WL<192> A_WL<191> A_WL<190> A_WL<189> A_WL<188> A_WL<187> A_WL<186> A_WL<185> A_WL<184> A_WL<183> A_WL<182> A_WL<181> A_WL<180> A_WL<179> A_WL<178> A_WL<177> A_WL<176> A_WL<175> A_WL<174> A_WL<173> A_WL<172> A_WL<171> A_WL<170> A_WL<169> A_WL<168> A_WL<167> A_WL<166> A_WL<165> A_WL<164> A_WL<163> A_WL<162> A_WL<161> A_WL<160> A_WL<159> A_WL<158> A_WL<157> A_WL<156> A_WL<155> A_WL<154> A_WL<153> A_WL<152> A_WL<151> A_WL<150> A_WL<149> A_WL<148> A_WL<147> A_WL<146> A_WL<145> A_WL<144> A_WL<143> A_WL<142> A_WL<141> A_WL<140> A_WL<139> A_WL<138> A_WL<137> A_WL<136> A_WL<135> A_WL<134> A_WL<133> A_WL<132> A_WL<131> A_WL<130> A_WL<129> A_WL<128> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> VDD_CORE VSS / RM_IHPSG13_4096x16_c3_1P_COLUMN_pcell_0
+.ENDS
+
+
+
+
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_DLY_pcell_2 A Z VDD VSS
+	XIDL<3> D<7> Z VDD VSS / RSC_IHPSG13_CDLYX1 
+	XIDL<2> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1 
+	XIDL<1> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1 
+	XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY 
+	XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY 
+	XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY 
+	XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY 
+	XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY 
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_4096x16_c3_1P_DLY_pcell_3 A Z VDD VSS
+	XIDL<7> D<7> Z VDD VSS / RSC_IHPSG13_CDLYX1 
+	XIDL<6> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1 
+	XIDL<5> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1 
+	XIDL<4> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1 
+	XIDL<3> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1 
+	XIDL<2> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 
+	XIDL<1> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 
+	XIDM A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY 
+.ENDS
+
+
+
+.SUBCKT RM_IHPSG13_1P_4096x16_c3_bm_bist A_ADDR<11> A_ADDR<10> A_ADDR<9> A_ADDR<8> A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> A_ADDR<1> A_ADDR<0> A_BIST_ADDR<11> A_BIST_ADDR<10> A_BIST_ADDR<9> A_BIST_ADDR<8> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_BM<15> A_BIST_BM<14> A_BIST_BM<13> A_BIST_BM<12> A_BIST_BM<11> A_BIST_BM<10> A_BIST_BM<9> A_BIST_BM<8> A_BIST_BM<7> A_BIST_BM<6> A_BIST_BM<5> A_BIST_BM<4> A_BIST_BM<3> A_BIST_BM<2> A_BIST_BM<1> A_BIST_BM<0> A_BIST_CLK A_BIST_DIN<15> A_BIST_DIN<14> A_BIST_DIN<13> A_BIST_DIN<12> A_BIST_DIN<11> A_BIST_DIN<10> A_BIST_DIN<9> A_BIST_DIN<8> A_BIST_DIN<7> A_BIST_DIN<6> A_BIST_DIN<5> A_BIST_DIN<4> A_BIST_DIN<3> A_BIST_DIN<2> A_BIST_DIN<1> A_BIST_DIN<0> A_BIST_EN A_BIST_MEN A_BIST_REN A_BIST_WEN A_BM<15> A_BM<14> A_BM<13> A_BM<12> A_BM<11> A_BM<10> A_BM<9> A_BM<8> A_BM<7> A_BM<6> A_BM<5> A_BM<4> A_BM<3> A_BM<2> A_BM<1> A_BM<0> A_CLK A_DIN<15> A_DIN<14> A_DIN<13> A_DIN<12> A_DIN<11> A_DIN<10> A_DIN<9> A_DIN<8> A_DIN<7> A_DIN<6> A_DIN<5> A_DIN<4> A_DIN<3> A_DIN<2> A_DIN<1> A_DIN<0> A_DLY A_DOUT<15> A_DOUT<14> A_DOUT<13> A_DOUT<12> A_DOUT<11> A_DOUT<10> A_DOUT<9> A_DOUT<8> A_DOUT<7> A_DOUT<6> A_DOUT<5> A_DOUT<4> A_DOUT<3> A_DOUT<2> A_DOUT<1> A_DOUT<0> A_MEN A_REN A_WEN VDD! VDDARRAY! VSS!
+
+
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a_wl_r<472> a_wl_r<471> a_wl_r<470> a_wl_r<469> a_wl_r<468> a_wl_r<467> a_wl_r<466> a_wl_r<465> a_wl_r<464> a_wl_r<463> a_wl_r<462> a_wl_r<461> a_wl_r<460> a_wl_r<459> a_wl_r<458> a_wl_r<457> a_wl_r<456> a_wl_r<455> a_wl_r<454> a_wl_r<453> a_wl_r<452> a_wl_r<451> a_wl_r<450> a_wl_r<449> a_wl_r<448> a_wl_r<447> a_wl_r<446> a_wl_r<445> a_wl_r<444> a_wl_r<443> a_wl_r<442> a_wl_r<441> a_wl_r<440> a_wl_r<439> a_wl_r<438> a_wl_r<437> a_wl_r<436> a_wl_r<435> a_wl_r<434> a_wl_r<433> a_wl_r<432> a_wl_r<431> a_wl_r<430> a_wl_r<429> a_wl_r<428> a_wl_r<427> a_wl_r<426> a_wl_r<425> a_wl_r<424> a_wl_r<423> a_wl_r<422> a_wl_r<421> a_wl_r<420> a_wl_r<419> a_wl_r<418> a_wl_r<417> a_wl_r<416> a_wl_r<415> a_wl_r<414> a_wl_r<413> a_wl_r<412> a_wl_r<411> a_wl_r<410> a_wl_r<409> a_wl_r<408> a_wl_r<407> a_wl_r<406> a_wl_r<405> a_wl_r<404> a_wl_r<403> a_wl_r<402> a_wl_r<401> a_wl_r<400> a_wl_r<399> a_wl_r<398> a_wl_r<397> a_wl_r<396> a_wl_r<395> a_wl_r<394> a_wl_r<393> a_wl_r<392> a_wl_r<391> a_wl_r<390> a_wl_r<389> a_wl_r<388> a_wl_r<387> a_wl_r<386> a_wl_r<385> a_wl_r<384> a_wl_r<383> a_wl_r<382> a_wl_r<381> a_wl_r<380> a_wl_r<379> a_wl_r<378> a_wl_r<377> a_wl_r<376> a_wl_r<375> a_wl_r<374> a_wl_r<373> a_wl_r<372> a_wl_r<371> a_wl_r<370> a_wl_r<369> a_wl_r<368> a_wl_r<367> a_wl_r<366> a_wl_r<365> a_wl_r<364> a_wl_r<363> a_wl_r<362> a_wl_r<361> a_wl_r<360> a_wl_r<359> a_wl_r<358> a_wl_r<357> a_wl_r<356> a_wl_r<355> a_wl_r<354> a_wl_r<353> a_wl_r<352> a_wl_r<351> a_wl_r<350> a_wl_r<349> a_wl_r<348> a_wl_r<347> a_wl_r<346> a_wl_r<345> a_wl_r<344> a_wl_r<343> a_wl_r<342> a_wl_r<341> a_wl_r<340> a_wl_r<339> a_wl_r<338> a_wl_r<337> a_wl_r<336> a_wl_r<335> a_wl_r<334> a_wl_r<333> a_wl_r<332> a_wl_r<331> a_wl_r<330> a_wl_r<329> a_wl_r<328> a_wl_r<327> a_wl_r<326> a_wl_r<325> a_wl_r<324> a_wl_r<323> a_wl_r<322> a_wl_r<321> a_wl_r<320> a_wl_r<319> a_wl_r<318> a_wl_r<317> a_wl_r<316> a_wl_r<315> a_wl_r<314> a_wl_r<313> a_wl_r<312> a_wl_r<311> a_wl_r<310> a_wl_r<309> a_wl_r<308> a_wl_r<307> a_wl_r<306> a_wl_r<305> a_wl_r<304> a_wl_r<303> a_wl_r<302> a_wl_r<301> a_wl_r<300> a_wl_r<299> a_wl_r<298> a_wl_r<297> a_wl_r<296> a_wl_r<295> a_wl_r<294> a_wl_r<293> a_wl_r<292> a_wl_r<291> a_wl_r<290> a_wl_r<289> a_wl_r<288> a_wl_r<287> a_wl_r<286> a_wl_r<285> a_wl_r<284> a_wl_r<283> a_wl_r<282> a_wl_r<281> a_wl_r<280> a_wl_r<279> a_wl_r<278> a_wl_r<277> a_wl_r<276> a_wl_r<275> a_wl_r<274> a_wl_r<273> a_wl_r<272> a_wl_r<271> a_wl_r<270> a_wl_r<269> a_wl_r<268> a_wl_r<267> a_wl_r<266> a_wl_r<265> a_wl_r<264> a_wl_r<263> a_wl_r<262> a_wl_r<261> a_wl_r<260> a_wl_r<259> a_wl_r<258> a_wl_r<257> a_wl_r<256> a_wl_r<255> a_wl_r<254> a_wl_r<253> a_wl_r<252> a_wl_r<251> a_wl_r<250> a_wl_r<249> a_wl_r<248> a_wl_r<247> a_wl_r<246> a_wl_r<245> a_wl_r<244> a_wl_r<243> a_wl_r<242> a_wl_r<241> a_wl_r<240> a_wl_r<239> a_wl_r<238> a_wl_r<237> a_wl_r<236> a_wl_r<235> a_wl_r<234> a_wl_r<233> a_wl_r<232> a_wl_r<231> a_wl_r<230> a_wl_r<229> a_wl_r<228> a_wl_r<227> a_wl_r<226> a_wl_r<225> a_wl_r<224> a_wl_r<223> a_wl_r<222> a_wl_r<221> a_wl_r<220> a_wl_r<219> a_wl_r<218> a_wl_r<217> a_wl_r<216> a_wl_r<215> a_wl_r<214> a_wl_r<213> a_wl_r<212> a_wl_r<211> a_wl_r<210> a_wl_r<209> a_wl_r<208> a_wl_r<207> a_wl_r<206> a_wl_r<205> a_wl_r<204> a_wl_r<203> a_wl_r<202> a_wl_r<201> a_wl_r<200> a_wl_r<199> a_wl_r<198> a_wl_r<197> a_wl_r<196> a_wl_r<195> a_wl_r<194> a_wl_r<193> a_wl_r<192> a_wl_r<191> a_wl_r<190> a_wl_r<189> a_wl_r<188> a_wl_r<187> a_wl_r<186> a_wl_r<185> a_wl_r<184> a_wl_r<183> a_wl_r<182> a_wl_r<181> a_wl_r<180> a_wl_r<179> a_wl_r<178> a_wl_r<177> a_wl_r<176> a_wl_r<175> a_wl_r<174> a_wl_r<173> a_wl_r<172> a_wl_r<171> a_wl_r<170> a_wl_r<169> a_wl_r<168> a_wl_r<167> a_wl_r<166> a_wl_r<165> a_wl_r<164> a_wl_r<163> a_wl_r<162> a_wl_r<161> a_wl_r<160> a_wl_r<159> a_wl_r<158> a_wl_r<157> a_wl_r<156> a_wl_r<155> a_wl_r<154> a_wl_r<153> a_wl_r<152> a_wl_r<151> a_wl_r<150> a_wl_r<149> a_wl_r<148> a_wl_r<147> a_wl_r<146> a_wl_r<145> a_wl_r<144> a_wl_r<143> a_wl_r<142> a_wl_r<141> a_wl_r<140> a_wl_r<139> a_wl_r<138> a_wl_r<137> a_wl_r<136> a_wl_r<135> a_wl_r<134> a_wl_r<133> a_wl_r<132> a_wl_r<131> a_wl_r<130> a_wl_r<129> a_wl_r<128> a_wl_r<127> a_wl_r<126> a_wl_r<125> a_wl_r<124> a_wl_r<123> a_wl_r<122> a_wl_r<121> a_wl_r<120> a_wl_r<119> a_wl_r<118> a_wl_r<117> a_wl_r<116> a_wl_r<115> a_wl_r<114> a_wl_r<113> a_wl_r<112> a_wl_r<111> a_wl_r<110> a_wl_r<109> a_wl_r<108> a_wl_r<107> a_wl_r<106> a_wl_r<105> a_wl_r<104> a_wl_r<103> a_wl_r<102> a_wl_r<101> a_wl_r<100> a_wl_r<99> a_wl_r<98> a_wl_r<97> a_wl_r<96> a_wl_r<95> a_wl_r<94> a_wl_r<93> a_wl_r<92> a_wl_r<91> a_wl_r<90> a_wl_r<89> a_wl_r<88> a_wl_r<87> a_wl_r<86> a_wl_r<85> a_wl_r<84> a_wl_r<83> a_wl_r<82> a_wl_r<81> a_wl_r<80> a_wl_r<79> a_wl_r<78> a_wl_r<77> a_wl_r<76> a_wl_r<75> a_wl_r<74> a_wl_r<73> a_wl_r<72> a_wl_r<71> a_wl_r<70> a_wl_r<69> a_wl_r<68> a_wl_r<67> a_wl_r<66> a_wl_r<65> a_wl_r<64> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDDARRAY! VSS! / RM_IHPSG13_4096x16_c3_1P_MATRIX_pcell_1
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a_wl_l<472> a_wl_l<471> a_wl_l<470> a_wl_l<469> a_wl_l<468> a_wl_l<467> a_wl_l<466> a_wl_l<465> a_wl_l<464> a_wl_l<463> a_wl_l<462> a_wl_l<461> a_wl_l<460> a_wl_l<459> a_wl_l<458> a_wl_l<457> a_wl_l<456> a_wl_l<455> a_wl_l<454> a_wl_l<453> a_wl_l<452> a_wl_l<451> a_wl_l<450> a_wl_l<449> a_wl_l<448> a_wl_l<447> a_wl_l<446> a_wl_l<445> a_wl_l<444> a_wl_l<443> a_wl_l<442> a_wl_l<441> a_wl_l<440> a_wl_l<439> a_wl_l<438> a_wl_l<437> a_wl_l<436> a_wl_l<435> a_wl_l<434> a_wl_l<433> a_wl_l<432> a_wl_l<431> a_wl_l<430> a_wl_l<429> a_wl_l<428> a_wl_l<427> a_wl_l<426> a_wl_l<425> a_wl_l<424> a_wl_l<423> a_wl_l<422> a_wl_l<421> a_wl_l<420> a_wl_l<419> a_wl_l<418> a_wl_l<417> a_wl_l<416> a_wl_l<415> a_wl_l<414> a_wl_l<413> a_wl_l<412> a_wl_l<411> a_wl_l<410> a_wl_l<409> a_wl_l<408> a_wl_l<407> a_wl_l<406> a_wl_l<405> a_wl_l<404> a_wl_l<403> a_wl_l<402> a_wl_l<401> a_wl_l<400> a_wl_l<399> a_wl_l<398> a_wl_l<397> a_wl_l<396> a_wl_l<395> a_wl_l<394> a_wl_l<393> a_wl_l<392> a_wl_l<391> a_wl_l<390> a_wl_l<389> a_wl_l<388> a_wl_l<387> a_wl_l<386> a_wl_l<385> a_wl_l<384> a_wl_l<383> a_wl_l<382> a_wl_l<381> a_wl_l<380> a_wl_l<379> a_wl_l<378> a_wl_l<377> a_wl_l<376> a_wl_l<375> a_wl_l<374> a_wl_l<373> a_wl_l<372> a_wl_l<371> a_wl_l<370> a_wl_l<369> a_wl_l<368> a_wl_l<367> a_wl_l<366> a_wl_l<365> a_wl_l<364> a_wl_l<363> a_wl_l<362> a_wl_l<361> a_wl_l<360> a_wl_l<359> a_wl_l<358> a_wl_l<357> a_wl_l<356> a_wl_l<355> a_wl_l<354> a_wl_l<353> a_wl_l<352> a_wl_l<351> a_wl_l<350> a_wl_l<349> a_wl_l<348> a_wl_l<347> a_wl_l<346> a_wl_l<345> a_wl_l<344> a_wl_l<343> a_wl_l<342> a_wl_l<341> a_wl_l<340> a_wl_l<339> a_wl_l<338> a_wl_l<337> a_wl_l<336> a_wl_l<335> a_wl_l<334> a_wl_l<333> a_wl_l<332> a_wl_l<331> a_wl_l<330> a_wl_l<329> a_wl_l<328> a_wl_l<327> a_wl_l<326> a_wl_l<325> a_wl_l<324> a_wl_l<323> a_wl_l<322> a_wl_l<321> a_wl_l<320> a_wl_l<319> a_wl_l<318> a_wl_l<317> a_wl_l<316> a_wl_l<315> a_wl_l<314> a_wl_l<313> a_wl_l<312> a_wl_l<311> a_wl_l<310> a_wl_l<309> a_wl_l<308> a_wl_l<307> a_wl_l<306> a_wl_l<305> a_wl_l<304> a_wl_l<303> a_wl_l<302> a_wl_l<301> a_wl_l<300> a_wl_l<299> a_wl_l<298> a_wl_l<297> a_wl_l<296> a_wl_l<295> a_wl_l<294> a_wl_l<293> a_wl_l<292> a_wl_l<291> a_wl_l<290> a_wl_l<289> a_wl_l<288> a_wl_l<287> a_wl_l<286> a_wl_l<285> a_wl_l<284> a_wl_l<283> a_wl_l<282> a_wl_l<281> a_wl_l<280> a_wl_l<279> a_wl_l<278> a_wl_l<277> a_wl_l<276> a_wl_l<275> a_wl_l<274> a_wl_l<273> a_wl_l<272> a_wl_l<271> a_wl_l<270> a_wl_l<269> a_wl_l<268> a_wl_l<267> a_wl_l<266> a_wl_l<265> a_wl_l<264> a_wl_l<263> a_wl_l<262> a_wl_l<261> a_wl_l<260> a_wl_l<259> a_wl_l<258> a_wl_l<257> a_wl_l<256> a_wl_l<255> a_wl_l<254> a_wl_l<253> a_wl_l<252> a_wl_l<251> a_wl_l<250> a_wl_l<249> a_wl_l<248> a_wl_l<247> a_wl_l<246> a_wl_l<245> a_wl_l<244> a_wl_l<243> a_wl_l<242> a_wl_l<241> a_wl_l<240> a_wl_l<239> a_wl_l<238> a_wl_l<237> a_wl_l<236> a_wl_l<235> a_wl_l<234> a_wl_l<233> a_wl_l<232> a_wl_l<231> a_wl_l<230> a_wl_l<229> a_wl_l<228> a_wl_l<227> a_wl_l<226> a_wl_l<225> a_wl_l<224> a_wl_l<223> a_wl_l<222> a_wl_l<221> a_wl_l<220> a_wl_l<219> a_wl_l<218> a_wl_l<217> a_wl_l<216> a_wl_l<215> a_wl_l<214> a_wl_l<213> a_wl_l<212> a_wl_l<211> a_wl_l<210> a_wl_l<209> a_wl_l<208> a_wl_l<207> a_wl_l<206> a_wl_l<205> a_wl_l<204> a_wl_l<203> a_wl_l<202> a_wl_l<201> a_wl_l<200> a_wl_l<199> a_wl_l<198> a_wl_l<197> a_wl_l<196> a_wl_l<195> a_wl_l<194> a_wl_l<193> a_wl_l<192> a_wl_l<191> a_wl_l<190> a_wl_l<189> a_wl_l<188> a_wl_l<187> a_wl_l<186> a_wl_l<185> a_wl_l<184> a_wl_l<183> a_wl_l<182> a_wl_l<181> a_wl_l<180> a_wl_l<179> a_wl_l<178> a_wl_l<177> a_wl_l<176> a_wl_l<175> a_wl_l<174> a_wl_l<173> a_wl_l<172> a_wl_l<171> a_wl_l<170> a_wl_l<169> a_wl_l<168> a_wl_l<167> a_wl_l<166> a_wl_l<165> a_wl_l<164> a_wl_l<163> a_wl_l<162> a_wl_l<161> a_wl_l<160> a_wl_l<159> a_wl_l<158> a_wl_l<157> a_wl_l<156> a_wl_l<155> a_wl_l<154> a_wl_l<153> a_wl_l<152> a_wl_l<151> a_wl_l<150> a_wl_l<149> a_wl_l<148> a_wl_l<147> a_wl_l<146> a_wl_l<145> a_wl_l<144> a_wl_l<143> a_wl_l<142> a_wl_l<141> a_wl_l<140> a_wl_l<139> a_wl_l<138> a_wl_l<137> a_wl_l<136> a_wl_l<135> a_wl_l<134> a_wl_l<133> a_wl_l<132> a_wl_l<131> a_wl_l<130> a_wl_l<129> a_wl_l<128> a_wl_l<127> a_wl_l<126> a_wl_l<125> a_wl_l<124> a_wl_l<123> a_wl_l<122> a_wl_l<121> a_wl_l<120> a_wl_l<119> a_wl_l<118> a_wl_l<117> a_wl_l<116> a_wl_l<115> a_wl_l<114> a_wl_l<113> a_wl_l<112> a_wl_l<111> a_wl_l<110> a_wl_l<109> a_wl_l<108> a_wl_l<107> a_wl_l<106> a_wl_l<105> a_wl_l<104> a_wl_l<103> a_wl_l<102> a_wl_l<101> a_wl_l<100> a_wl_l<99> a_wl_l<98> a_wl_l<97> a_wl_l<96> a_wl_l<95> a_wl_l<94> a_wl_l<93> a_wl_l<92> a_wl_l<91> a_wl_l<90> a_wl_l<89> a_wl_l<88> a_wl_l<87> a_wl_l<86> a_wl_l<85> a_wl_l<84> a_wl_l<83> a_wl_l<82> a_wl_l<81> a_wl_l<80> a_wl_l<79> a_wl_l<78> a_wl_l<77> a_wl_l<76> a_wl_l<75> a_wl_l<74> a_wl_l<73> a_wl_l<72> a_wl_l<71> a_wl_l<70> a_wl_l<69> a_wl_l<68> a_wl_l<67> a_wl_l<66> a_wl_l<65> a_wl_l<64> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDDARRAY! VSS! / RM_IHPSG13_4096x16_c3_1P_MATRIX_pcell_1
+
+
+XA_COLDRV<1> a_addr_col<1> a_addr_col<0> a_addr_col_r<1> a_addr_col_r<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_dclk a_dclk_p_r<0> a_rclk a_rclk_p_r<0> a_wclk a_wclk_p_r<0> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLDRV13X4
+XA_COLDRV<0> a_addr_col<1> a_addr_col<0> a_addr_col_l<1> a_addr_col_l<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_dclk a_dclk_p_l<0> a_rclk a_rclk_p_l<0> a_wclk a_wclk_p_l<0> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLDRV13X4
+
+
+XA_WLDRV<63> a_wi<511> a_wi<510> a_wi<509> a_wi<508> a_wi<507> a_wi<506> a_wi<505> a_wi<504> a_wi<503> a_wi<502> a_wi<501> a_wi<500> a_wi<499> a_wi<498> a_wi<497> a_wi<496> a_wl_r<511> a_wl_r<510> a_wl_r<509> a_wl_r<508> a_wl_r<507> a_wl_r<506> a_wl_r<505> a_wl_r<504> a_wl_r<503> a_wl_r<502> a_wl_r<501> a_wl_r<500> a_wl_r<499> a_wl_r<498> a_wl_r<497> a_wl_r<496>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<62> a_wi<495> a_wi<494> a_wi<493> a_wi<492> a_wi<491> a_wi<490> a_wi<489> a_wi<488> a_wi<487> a_wi<486> a_wi<485> a_wi<484> a_wi<483> a_wi<482> a_wi<481> a_wi<480> a_wl_r<495> a_wl_r<494> a_wl_r<493> a_wl_r<492> a_wl_r<491> a_wl_r<490> a_wl_r<489> a_wl_r<488> a_wl_r<487> a_wl_r<486> a_wl_r<485> a_wl_r<484> a_wl_r<483> a_wl_r<482> a_wl_r<481> a_wl_r<480>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<61> a_wi<479> a_wi<478> a_wi<477> a_wi<476> a_wi<475> a_wi<474> a_wi<473> a_wi<472> a_wi<471> a_wi<470> a_wi<469> a_wi<468> a_wi<467> a_wi<466> a_wi<465> a_wi<464> a_wl_r<479> a_wl_r<478> a_wl_r<477> a_wl_r<476> a_wl_r<475> a_wl_r<474> a_wl_r<473> a_wl_r<472> a_wl_r<471> a_wl_r<470> a_wl_r<469> a_wl_r<468> a_wl_r<467> a_wl_r<466> a_wl_r<465> a_wl_r<464>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<60> a_wi<463> a_wi<462> a_wi<461> a_wi<460> a_wi<459> a_wi<458> a_wi<457> a_wi<456> a_wi<455> a_wi<454> a_wi<453> a_wi<452> a_wi<451> a_wi<450> a_wi<449> a_wi<448> a_wl_r<463> a_wl_r<462> a_wl_r<461> a_wl_r<460> a_wl_r<459> a_wl_r<458> a_wl_r<457> a_wl_r<456> a_wl_r<455> a_wl_r<454> a_wl_r<453> a_wl_r<452> a_wl_r<451> a_wl_r<450> a_wl_r<449> a_wl_r<448>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<59> a_wi<447> a_wi<446> a_wi<445> a_wi<444> a_wi<443> a_wi<442> a_wi<441> a_wi<440> a_wi<439> a_wi<438> a_wi<437> a_wi<436> a_wi<435> a_wi<434> a_wi<433> a_wi<432> a_wl_r<447> a_wl_r<446> a_wl_r<445> a_wl_r<444> a_wl_r<443> a_wl_r<442> a_wl_r<441> a_wl_r<440> a_wl_r<439> a_wl_r<438> a_wl_r<437> a_wl_r<436> a_wl_r<435> a_wl_r<434> a_wl_r<433> a_wl_r<432>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<58> a_wi<431> a_wi<430> a_wi<429> a_wi<428> a_wi<427> a_wi<426> a_wi<425> a_wi<424> a_wi<423> a_wi<422> a_wi<421> a_wi<420> a_wi<419> a_wi<418> a_wi<417> a_wi<416> a_wl_r<431> a_wl_r<430> a_wl_r<429> a_wl_r<428> a_wl_r<427> a_wl_r<426> a_wl_r<425> a_wl_r<424> a_wl_r<423> a_wl_r<422> a_wl_r<421> a_wl_r<420> a_wl_r<419> a_wl_r<418> a_wl_r<417> a_wl_r<416>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<57> a_wi<415> a_wi<414> a_wi<413> a_wi<412> a_wi<411> a_wi<410> a_wi<409> a_wi<408> a_wi<407> a_wi<406> a_wi<405> a_wi<404> a_wi<403> a_wi<402> a_wi<401> a_wi<400> a_wl_r<415> a_wl_r<414> a_wl_r<413> a_wl_r<412> a_wl_r<411> a_wl_r<410> a_wl_r<409> a_wl_r<408> a_wl_r<407> a_wl_r<406> a_wl_r<405> a_wl_r<404> a_wl_r<403> a_wl_r<402> a_wl_r<401> a_wl_r<400>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<56> a_wi<399> a_wi<398> a_wi<397> a_wi<396> a_wi<395> a_wi<394> a_wi<393> a_wi<392> a_wi<391> a_wi<390> a_wi<389> a_wi<388> a_wi<387> a_wi<386> a_wi<385> a_wi<384> a_wl_r<399> a_wl_r<398> a_wl_r<397> a_wl_r<396> a_wl_r<395> a_wl_r<394> a_wl_r<393> a_wl_r<392> a_wl_r<391> a_wl_r<390> a_wl_r<389> a_wl_r<388> a_wl_r<387> a_wl_r<386> a_wl_r<385> a_wl_r<384>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<55> a_wi<383> a_wi<382> a_wi<381> a_wi<380> a_wi<379> a_wi<378> a_wi<377> a_wi<376> a_wi<375> a_wi<374> a_wi<373> a_wi<372> a_wi<371> a_wi<370> a_wi<369> a_wi<368> a_wl_r<383> a_wl_r<382> a_wl_r<381> a_wl_r<380> a_wl_r<379> a_wl_r<378> a_wl_r<377> a_wl_r<376> a_wl_r<375> a_wl_r<374> a_wl_r<373> a_wl_r<372> a_wl_r<371> a_wl_r<370> a_wl_r<369> a_wl_r<368>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<54> a_wi<367> a_wi<366> a_wi<365> a_wi<364> a_wi<363> a_wi<362> a_wi<361> a_wi<360> a_wi<359> a_wi<358> a_wi<357> a_wi<356> a_wi<355> a_wi<354> a_wi<353> a_wi<352> a_wl_r<367> a_wl_r<366> a_wl_r<365> a_wl_r<364> a_wl_r<363> a_wl_r<362> a_wl_r<361> a_wl_r<360> a_wl_r<359> a_wl_r<358> a_wl_r<357> a_wl_r<356> a_wl_r<355> a_wl_r<354> a_wl_r<353> a_wl_r<352>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<53> a_wi<351> a_wi<350> a_wi<349> a_wi<348> a_wi<347> a_wi<346> a_wi<345> a_wi<344> a_wi<343> a_wi<342> a_wi<341> a_wi<340> a_wi<339> a_wi<338> a_wi<337> a_wi<336> a_wl_r<351> a_wl_r<350> a_wl_r<349> a_wl_r<348> a_wl_r<347> a_wl_r<346> a_wl_r<345> a_wl_r<344> a_wl_r<343> a_wl_r<342> a_wl_r<341> a_wl_r<340> a_wl_r<339> a_wl_r<338> a_wl_r<337> a_wl_r<336>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<52> a_wi<335> a_wi<334> a_wi<333> a_wi<332> a_wi<331> a_wi<330> a_wi<329> a_wi<328> a_wi<327> a_wi<326> a_wi<325> a_wi<324> a_wi<323> a_wi<322> a_wi<321> a_wi<320> a_wl_r<335> a_wl_r<334> a_wl_r<333> a_wl_r<332> a_wl_r<331> a_wl_r<330> a_wl_r<329> a_wl_r<328> a_wl_r<327> a_wl_r<326> a_wl_r<325> a_wl_r<324> a_wl_r<323> a_wl_r<322> a_wl_r<321> a_wl_r<320>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<51> a_wi<319> a_wi<318> a_wi<317> a_wi<316> a_wi<315> a_wi<314> a_wi<313> a_wi<312> a_wi<311> a_wi<310> a_wi<309> a_wi<308> a_wi<307> a_wi<306> a_wi<305> a_wi<304> a_wl_r<319> a_wl_r<318> a_wl_r<317> a_wl_r<316> a_wl_r<315> a_wl_r<314> a_wl_r<313> a_wl_r<312> a_wl_r<311> a_wl_r<310> a_wl_r<309> a_wl_r<308> a_wl_r<307> a_wl_r<306> a_wl_r<305> a_wl_r<304>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<50> a_wi<303> a_wi<302> a_wi<301> a_wi<300> a_wi<299> a_wi<298> a_wi<297> a_wi<296> a_wi<295> a_wi<294> a_wi<293> a_wi<292> a_wi<291> a_wi<290> a_wi<289> a_wi<288> a_wl_r<303> a_wl_r<302> a_wl_r<301> a_wl_r<300> a_wl_r<299> a_wl_r<298> a_wl_r<297> a_wl_r<296> a_wl_r<295> a_wl_r<294> a_wl_r<293> a_wl_r<292> a_wl_r<291> a_wl_r<290> a_wl_r<289> a_wl_r<288>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<49> a_wi<287> a_wi<286> a_wi<285> a_wi<284> a_wi<283> a_wi<282> a_wi<281> a_wi<280> a_wi<279> a_wi<278> a_wi<277> a_wi<276> a_wi<275> a_wi<274> a_wi<273> a_wi<272> a_wl_r<287> a_wl_r<286> a_wl_r<285> a_wl_r<284> a_wl_r<283> a_wl_r<282> a_wl_r<281> a_wl_r<280> a_wl_r<279> a_wl_r<278> a_wl_r<277> a_wl_r<276> a_wl_r<275> a_wl_r<274> a_wl_r<273> a_wl_r<272>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<48> a_wi<271> a_wi<270> a_wi<269> a_wi<268> a_wi<267> a_wi<266> a_wi<265> a_wi<264> a_wi<263> a_wi<262> a_wi<261> a_wi<260> a_wi<259> a_wi<258> a_wi<257> a_wi<256> a_wl_r<271> a_wl_r<270> a_wl_r<269> a_wl_r<268> a_wl_r<267> a_wl_r<266> a_wl_r<265> a_wl_r<264> a_wl_r<263> a_wl_r<262> a_wl_r<261> a_wl_r<260> a_wl_r<259> a_wl_r<258> a_wl_r<257> a_wl_r<256>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<47> a_wi<255> a_wi<254> a_wi<253> a_wi<252> a_wi<251> a_wi<250> a_wi<249> a_wi<248> a_wi<247> a_wi<246> a_wi<245> a_wi<244> a_wi<243> a_wi<242> a_wi<241> a_wi<240> a_wl_r<255> a_wl_r<254> a_wl_r<253> a_wl_r<252> a_wl_r<251> a_wl_r<250> a_wl_r<249> a_wl_r<248> a_wl_r<247> a_wl_r<246> a_wl_r<245> a_wl_r<244> a_wl_r<243> a_wl_r<242> a_wl_r<241> a_wl_r<240>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<46> a_wi<239> a_wi<238> a_wi<237> a_wi<236> a_wi<235> a_wi<234> a_wi<233> a_wi<232> a_wi<231> a_wi<230> a_wi<229> a_wi<228> a_wi<227> a_wi<226> a_wi<225> a_wi<224> a_wl_r<239> a_wl_r<238> a_wl_r<237> a_wl_r<236> a_wl_r<235> a_wl_r<234> a_wl_r<233> a_wl_r<232> a_wl_r<231> a_wl_r<230> a_wl_r<229> a_wl_r<228> a_wl_r<227> a_wl_r<226> a_wl_r<225> a_wl_r<224>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<45> a_wi<223> a_wi<222> a_wi<221> a_wi<220> a_wi<219> a_wi<218> a_wi<217> a_wi<216> a_wi<215> a_wi<214> a_wi<213> a_wi<212> a_wi<211> a_wi<210> a_wi<209> a_wi<208> a_wl_r<223> a_wl_r<222> a_wl_r<221> a_wl_r<220> a_wl_r<219> a_wl_r<218> a_wl_r<217> a_wl_r<216> a_wl_r<215> a_wl_r<214> a_wl_r<213> a_wl_r<212> a_wl_r<211> a_wl_r<210> a_wl_r<209> a_wl_r<208>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<44> a_wi<207> a_wi<206> a_wi<205> a_wi<204> a_wi<203> a_wi<202> a_wi<201> a_wi<200> a_wi<199> a_wi<198> a_wi<197> a_wi<196> a_wi<195> a_wi<194> a_wi<193> a_wi<192> a_wl_r<207> a_wl_r<206> a_wl_r<205> a_wl_r<204> a_wl_r<203> a_wl_r<202> a_wl_r<201> a_wl_r<200> a_wl_r<199> a_wl_r<198> a_wl_r<197> a_wl_r<196> a_wl_r<195> a_wl_r<194> a_wl_r<193> a_wl_r<192>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<43> a_wi<191> a_wi<190> a_wi<189> a_wi<188> a_wi<187> a_wi<186> a_wi<185> a_wi<184> a_wi<183> a_wi<182> a_wi<181> a_wi<180> a_wi<179> a_wi<178> a_wi<177> a_wi<176> a_wl_r<191> a_wl_r<190> a_wl_r<189> a_wl_r<188> a_wl_r<187> a_wl_r<186> a_wl_r<185> a_wl_r<184> a_wl_r<183> a_wl_r<182> a_wl_r<181> a_wl_r<180> a_wl_r<179> a_wl_r<178> a_wl_r<177> a_wl_r<176>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<42> a_wi<175> a_wi<174> a_wi<173> a_wi<172> a_wi<171> a_wi<170> a_wi<169> a_wi<168> a_wi<167> a_wi<166> a_wi<165> a_wi<164> a_wi<163> a_wi<162> a_wi<161> a_wi<160> a_wl_r<175> a_wl_r<174> a_wl_r<173> a_wl_r<172> a_wl_r<171> a_wl_r<170> a_wl_r<169> a_wl_r<168> a_wl_r<167> a_wl_r<166> a_wl_r<165> a_wl_r<164> a_wl_r<163> a_wl_r<162> a_wl_r<161> a_wl_r<160>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<41> a_wi<159> a_wi<158> a_wi<157> a_wi<156> a_wi<155> a_wi<154> a_wi<153> a_wi<152> a_wi<151> a_wi<150> a_wi<149> a_wi<148> a_wi<147> a_wi<146> a_wi<145> a_wi<144> a_wl_r<159> a_wl_r<158> a_wl_r<157> a_wl_r<156> a_wl_r<155> a_wl_r<154> a_wl_r<153> a_wl_r<152> a_wl_r<151> a_wl_r<150> a_wl_r<149> a_wl_r<148> a_wl_r<147> a_wl_r<146> a_wl_r<145> a_wl_r<144>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<40> a_wi<143> a_wi<142> a_wi<141> a_wi<140> a_wi<139> a_wi<138> a_wi<137> a_wi<136> a_wi<135> a_wi<134> a_wi<133> a_wi<132> a_wi<131> a_wi<130> a_wi<129> a_wi<128> a_wl_r<143> a_wl_r<142> a_wl_r<141> a_wl_r<140> a_wl_r<139> a_wl_r<138> a_wl_r<137> a_wl_r<136> a_wl_r<135> a_wl_r<134> a_wl_r<133> a_wl_r<132> a_wl_r<131> a_wl_r<130> a_wl_r<129> a_wl_r<128>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<39> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wl_r<127> a_wl_r<126> a_wl_r<125> a_wl_r<124> a_wl_r<123> a_wl_r<122> a_wl_r<121> a_wl_r<120> a_wl_r<119> a_wl_r<118> a_wl_r<117> a_wl_r<116> a_wl_r<115> a_wl_r<114> a_wl_r<113> a_wl_r<112>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<38> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wl_r<111> a_wl_r<110> a_wl_r<109> a_wl_r<108> a_wl_r<107> a_wl_r<106> a_wl_r<105> a_wl_r<104> a_wl_r<103> a_wl_r<102> a_wl_r<101> a_wl_r<100> a_wl_r<99> a_wl_r<98> a_wl_r<97> a_wl_r<96>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<37> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wl_r<95> a_wl_r<94> a_wl_r<93> a_wl_r<92> a_wl_r<91> a_wl_r<90> a_wl_r<89> a_wl_r<88> a_wl_r<87> a_wl_r<86> a_wl_r<85> a_wl_r<84> a_wl_r<83> a_wl_r<82> a_wl_r<81> a_wl_r<80>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<36> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wl_r<79> a_wl_r<78> a_wl_r<77> a_wl_r<76> a_wl_r<75> a_wl_r<74> a_wl_r<73> a_wl_r<72> a_wl_r<71> a_wl_r<70> a_wl_r<69> a_wl_r<68> a_wl_r<67> a_wl_r<66> a_wl_r<65> a_wl_r<64>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<35> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<34> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<33> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<32> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<31> a_wi<511> a_wi<510> a_wi<509> a_wi<508> a_wi<507> a_wi<506> a_wi<505> a_wi<504> a_wi<503> a_wi<502> a_wi<501> a_wi<500> a_wi<499> a_wi<498> a_wi<497> a_wi<496> a_wl_l<511> a_wl_l<510> a_wl_l<509> a_wl_l<508> a_wl_l<507> a_wl_l<506> a_wl_l<505> a_wl_l<504> a_wl_l<503> a_wl_l<502> a_wl_l<501> a_wl_l<500> a_wl_l<499> a_wl_l<498> a_wl_l<497> a_wl_l<496>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<30> a_wi<495> a_wi<494> a_wi<493> a_wi<492> a_wi<491> a_wi<490> a_wi<489> a_wi<488> a_wi<487> a_wi<486> a_wi<485> a_wi<484> a_wi<483> a_wi<482> a_wi<481> a_wi<480> a_wl_l<495> a_wl_l<494> a_wl_l<493> a_wl_l<492> a_wl_l<491> a_wl_l<490> a_wl_l<489> a_wl_l<488> a_wl_l<487> a_wl_l<486> a_wl_l<485> a_wl_l<484> a_wl_l<483> a_wl_l<482> a_wl_l<481> a_wl_l<480>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<29> a_wi<479> a_wi<478> a_wi<477> a_wi<476> a_wi<475> a_wi<474> a_wi<473> a_wi<472> a_wi<471> a_wi<470> a_wi<469> a_wi<468> a_wi<467> a_wi<466> a_wi<465> a_wi<464> a_wl_l<479> a_wl_l<478> a_wl_l<477> a_wl_l<476> a_wl_l<475> a_wl_l<474> a_wl_l<473> a_wl_l<472> a_wl_l<471> a_wl_l<470> a_wl_l<469> a_wl_l<468> a_wl_l<467> a_wl_l<466> a_wl_l<465> a_wl_l<464>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<28> a_wi<463> a_wi<462> a_wi<461> a_wi<460> a_wi<459> a_wi<458> a_wi<457> a_wi<456> a_wi<455> a_wi<454> a_wi<453> a_wi<452> a_wi<451> a_wi<450> a_wi<449> a_wi<448> a_wl_l<463> a_wl_l<462> a_wl_l<461> a_wl_l<460> a_wl_l<459> a_wl_l<458> a_wl_l<457> a_wl_l<456> a_wl_l<455> a_wl_l<454> a_wl_l<453> a_wl_l<452> a_wl_l<451> a_wl_l<450> a_wl_l<449> a_wl_l<448>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<27> a_wi<447> a_wi<446> a_wi<445> a_wi<444> a_wi<443> a_wi<442> a_wi<441> a_wi<440> a_wi<439> a_wi<438> a_wi<437> a_wi<436> a_wi<435> a_wi<434> a_wi<433> a_wi<432> a_wl_l<447> a_wl_l<446> a_wl_l<445> a_wl_l<444> a_wl_l<443> a_wl_l<442> a_wl_l<441> a_wl_l<440> a_wl_l<439> a_wl_l<438> a_wl_l<437> a_wl_l<436> a_wl_l<435> a_wl_l<434> a_wl_l<433> a_wl_l<432>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<26> a_wi<431> a_wi<430> a_wi<429> a_wi<428> a_wi<427> a_wi<426> a_wi<425> a_wi<424> a_wi<423> a_wi<422> a_wi<421> a_wi<420> a_wi<419> a_wi<418> a_wi<417> a_wi<416> a_wl_l<431> a_wl_l<430> a_wl_l<429> a_wl_l<428> a_wl_l<427> a_wl_l<426> a_wl_l<425> a_wl_l<424> a_wl_l<423> a_wl_l<422> a_wl_l<421> a_wl_l<420> a_wl_l<419> a_wl_l<418> a_wl_l<417> a_wl_l<416>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<25> a_wi<415> a_wi<414> a_wi<413> a_wi<412> a_wi<411> a_wi<410> a_wi<409> a_wi<408> a_wi<407> a_wi<406> a_wi<405> a_wi<404> a_wi<403> a_wi<402> a_wi<401> a_wi<400> a_wl_l<415> a_wl_l<414> a_wl_l<413> a_wl_l<412> a_wl_l<411> a_wl_l<410> a_wl_l<409> a_wl_l<408> a_wl_l<407> a_wl_l<406> a_wl_l<405> a_wl_l<404> a_wl_l<403> a_wl_l<402> a_wl_l<401> a_wl_l<400>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<24> a_wi<399> a_wi<398> a_wi<397> a_wi<396> a_wi<395> a_wi<394> a_wi<393> a_wi<392> a_wi<391> a_wi<390> a_wi<389> a_wi<388> a_wi<387> a_wi<386> a_wi<385> a_wi<384> a_wl_l<399> a_wl_l<398> a_wl_l<397> a_wl_l<396> a_wl_l<395> a_wl_l<394> a_wl_l<393> a_wl_l<392> a_wl_l<391> a_wl_l<390> a_wl_l<389> a_wl_l<388> a_wl_l<387> a_wl_l<386> a_wl_l<385> a_wl_l<384>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<23> a_wi<383> a_wi<382> a_wi<381> a_wi<380> a_wi<379> a_wi<378> a_wi<377> a_wi<376> a_wi<375> a_wi<374> a_wi<373> a_wi<372> a_wi<371> a_wi<370> a_wi<369> a_wi<368> a_wl_l<383> a_wl_l<382> a_wl_l<381> a_wl_l<380> a_wl_l<379> a_wl_l<378> a_wl_l<377> a_wl_l<376> a_wl_l<375> a_wl_l<374> a_wl_l<373> a_wl_l<372> a_wl_l<371> a_wl_l<370> a_wl_l<369> a_wl_l<368>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<22> a_wi<367> a_wi<366> a_wi<365> a_wi<364> a_wi<363> a_wi<362> a_wi<361> a_wi<360> a_wi<359> a_wi<358> a_wi<357> a_wi<356> a_wi<355> a_wi<354> a_wi<353> a_wi<352> a_wl_l<367> a_wl_l<366> a_wl_l<365> a_wl_l<364> a_wl_l<363> a_wl_l<362> a_wl_l<361> a_wl_l<360> a_wl_l<359> a_wl_l<358> a_wl_l<357> a_wl_l<356> a_wl_l<355> a_wl_l<354> a_wl_l<353> a_wl_l<352>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<21> a_wi<351> a_wi<350> a_wi<349> a_wi<348> a_wi<347> a_wi<346> a_wi<345> a_wi<344> a_wi<343> a_wi<342> a_wi<341> a_wi<340> a_wi<339> a_wi<338> a_wi<337> a_wi<336> a_wl_l<351> a_wl_l<350> a_wl_l<349> a_wl_l<348> a_wl_l<347> a_wl_l<346> a_wl_l<345> a_wl_l<344> a_wl_l<343> a_wl_l<342> a_wl_l<341> a_wl_l<340> a_wl_l<339> a_wl_l<338> a_wl_l<337> a_wl_l<336>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<20> a_wi<335> a_wi<334> a_wi<333> a_wi<332> a_wi<331> a_wi<330> a_wi<329> a_wi<328> a_wi<327> a_wi<326> a_wi<325> a_wi<324> a_wi<323> a_wi<322> a_wi<321> a_wi<320> a_wl_l<335> a_wl_l<334> a_wl_l<333> a_wl_l<332> a_wl_l<331> a_wl_l<330> a_wl_l<329> a_wl_l<328> a_wl_l<327> a_wl_l<326> a_wl_l<325> a_wl_l<324> a_wl_l<323> a_wl_l<322> a_wl_l<321> a_wl_l<320>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<19> a_wi<319> a_wi<318> a_wi<317> a_wi<316> a_wi<315> a_wi<314> a_wi<313> a_wi<312> a_wi<311> a_wi<310> a_wi<309> a_wi<308> a_wi<307> a_wi<306> a_wi<305> a_wi<304> a_wl_l<319> a_wl_l<318> a_wl_l<317> a_wl_l<316> a_wl_l<315> a_wl_l<314> a_wl_l<313> a_wl_l<312> a_wl_l<311> a_wl_l<310> a_wl_l<309> a_wl_l<308> a_wl_l<307> a_wl_l<306> a_wl_l<305> a_wl_l<304>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<18> a_wi<303> a_wi<302> a_wi<301> a_wi<300> a_wi<299> a_wi<298> a_wi<297> a_wi<296> a_wi<295> a_wi<294> a_wi<293> a_wi<292> a_wi<291> a_wi<290> a_wi<289> a_wi<288> a_wl_l<303> a_wl_l<302> a_wl_l<301> a_wl_l<300> a_wl_l<299> a_wl_l<298> a_wl_l<297> a_wl_l<296> a_wl_l<295> a_wl_l<294> a_wl_l<293> a_wl_l<292> a_wl_l<291> a_wl_l<290> a_wl_l<289> a_wl_l<288>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<17> a_wi<287> a_wi<286> a_wi<285> a_wi<284> a_wi<283> a_wi<282> a_wi<281> a_wi<280> a_wi<279> a_wi<278> a_wi<277> a_wi<276> a_wi<275> a_wi<274> a_wi<273> a_wi<272> a_wl_l<287> a_wl_l<286> a_wl_l<285> a_wl_l<284> a_wl_l<283> a_wl_l<282> a_wl_l<281> a_wl_l<280> a_wl_l<279> a_wl_l<278> a_wl_l<277> a_wl_l<276> a_wl_l<275> a_wl_l<274> a_wl_l<273> a_wl_l<272>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<16> a_wi<271> a_wi<270> a_wi<269> a_wi<268> a_wi<267> a_wi<266> a_wi<265> a_wi<264> a_wi<263> a_wi<262> a_wi<261> a_wi<260> a_wi<259> a_wi<258> a_wi<257> a_wi<256> a_wl_l<271> a_wl_l<270> a_wl_l<269> a_wl_l<268> a_wl_l<267> a_wl_l<266> a_wl_l<265> a_wl_l<264> a_wl_l<263> a_wl_l<262> a_wl_l<261> a_wl_l<260> a_wl_l<259> a_wl_l<258> a_wl_l<257> a_wl_l<256>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<15> a_wi<255> a_wi<254> a_wi<253> a_wi<252> a_wi<251> a_wi<250> a_wi<249> a_wi<248> a_wi<247> a_wi<246> a_wi<245> a_wi<244> a_wi<243> a_wi<242> a_wi<241> a_wi<240> a_wl_l<255> a_wl_l<254> a_wl_l<253> a_wl_l<252> a_wl_l<251> a_wl_l<250> a_wl_l<249> a_wl_l<248> a_wl_l<247> a_wl_l<246> a_wl_l<245> a_wl_l<244> a_wl_l<243> a_wl_l<242> a_wl_l<241> a_wl_l<240>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<14> a_wi<239> a_wi<238> a_wi<237> a_wi<236> a_wi<235> a_wi<234> a_wi<233> a_wi<232> a_wi<231> a_wi<230> a_wi<229> a_wi<228> a_wi<227> a_wi<226> a_wi<225> a_wi<224> a_wl_l<239> a_wl_l<238> a_wl_l<237> a_wl_l<236> a_wl_l<235> a_wl_l<234> a_wl_l<233> a_wl_l<232> a_wl_l<231> a_wl_l<230> a_wl_l<229> a_wl_l<228> a_wl_l<227> a_wl_l<226> a_wl_l<225> a_wl_l<224>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<13> a_wi<223> a_wi<222> a_wi<221> a_wi<220> a_wi<219> a_wi<218> a_wi<217> a_wi<216> a_wi<215> a_wi<214> a_wi<213> a_wi<212> a_wi<211> a_wi<210> a_wi<209> a_wi<208> a_wl_l<223> a_wl_l<222> a_wl_l<221> a_wl_l<220> a_wl_l<219> a_wl_l<218> a_wl_l<217> a_wl_l<216> a_wl_l<215> a_wl_l<214> a_wl_l<213> a_wl_l<212> a_wl_l<211> a_wl_l<210> a_wl_l<209> a_wl_l<208>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<12> a_wi<207> a_wi<206> a_wi<205> a_wi<204> a_wi<203> a_wi<202> a_wi<201> a_wi<200> a_wi<199> a_wi<198> a_wi<197> a_wi<196> a_wi<195> a_wi<194> a_wi<193> a_wi<192> a_wl_l<207> a_wl_l<206> a_wl_l<205> a_wl_l<204> a_wl_l<203> a_wl_l<202> a_wl_l<201> a_wl_l<200> a_wl_l<199> a_wl_l<198> a_wl_l<197> a_wl_l<196> a_wl_l<195> a_wl_l<194> a_wl_l<193> a_wl_l<192>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<11> a_wi<191> a_wi<190> a_wi<189> a_wi<188> a_wi<187> a_wi<186> a_wi<185> a_wi<184> a_wi<183> a_wi<182> a_wi<181> a_wi<180> a_wi<179> a_wi<178> a_wi<177> a_wi<176> a_wl_l<191> a_wl_l<190> a_wl_l<189> a_wl_l<188> a_wl_l<187> a_wl_l<186> a_wl_l<185> a_wl_l<184> a_wl_l<183> a_wl_l<182> a_wl_l<181> a_wl_l<180> a_wl_l<179> a_wl_l<178> a_wl_l<177> a_wl_l<176>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<10> a_wi<175> a_wi<174> a_wi<173> a_wi<172> a_wi<171> a_wi<170> a_wi<169> a_wi<168> a_wi<167> a_wi<166> a_wi<165> a_wi<164> a_wi<163> a_wi<162> a_wi<161> a_wi<160> a_wl_l<175> a_wl_l<174> a_wl_l<173> a_wl_l<172> a_wl_l<171> a_wl_l<170> a_wl_l<169> a_wl_l<168> a_wl_l<167> a_wl_l<166> a_wl_l<165> a_wl_l<164> a_wl_l<163> a_wl_l<162> a_wl_l<161> a_wl_l<160>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<9> a_wi<159> a_wi<158> a_wi<157> a_wi<156> a_wi<155> a_wi<154> a_wi<153> a_wi<152> a_wi<151> a_wi<150> a_wi<149> a_wi<148> a_wi<147> a_wi<146> a_wi<145> a_wi<144> a_wl_l<159> a_wl_l<158> a_wl_l<157> a_wl_l<156> a_wl_l<155> a_wl_l<154> a_wl_l<153> a_wl_l<152> a_wl_l<151> a_wl_l<150> a_wl_l<149> a_wl_l<148> a_wl_l<147> a_wl_l<146> a_wl_l<145> a_wl_l<144>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<8> a_wi<143> a_wi<142> a_wi<141> a_wi<140> a_wi<139> a_wi<138> a_wi<137> a_wi<136> a_wi<135> a_wi<134> a_wi<133> a_wi<132> a_wi<131> a_wi<130> a_wi<129> a_wi<128> a_wl_l<143> a_wl_l<142> a_wl_l<141> a_wl_l<140> a_wl_l<139> a_wl_l<138> a_wl_l<137> a_wl_l<136> a_wl_l<135> a_wl_l<134> a_wl_l<133> a_wl_l<132> a_wl_l<131> a_wl_l<130> a_wl_l<129> a_wl_l<128>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<7> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wl_l<127> a_wl_l<126> a_wl_l<125> a_wl_l<124> a_wl_l<123> a_wl_l<122> a_wl_l<121> a_wl_l<120> a_wl_l<119> a_wl_l<118> a_wl_l<117> a_wl_l<116> a_wl_l<115> a_wl_l<114> a_wl_l<113> a_wl_l<112>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<6> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wl_l<111> a_wl_l<110> a_wl_l<109> a_wl_l<108> a_wl_l<107> a_wl_l<106> a_wl_l<105> a_wl_l<104> a_wl_l<103> a_wl_l<102> a_wl_l<101> a_wl_l<100> a_wl_l<99> a_wl_l<98> a_wl_l<97> a_wl_l<96>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<5> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wl_l<95> a_wl_l<94> a_wl_l<93> a_wl_l<92> a_wl_l<91> a_wl_l<90> a_wl_l<89> a_wl_l<88> a_wl_l<87> a_wl_l<86> a_wl_l<85> a_wl_l<84> a_wl_l<83> a_wl_l<82> a_wl_l<81> a_wl_l<80>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<4> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wl_l<79> a_wl_l<78> a_wl_l<77> a_wl_l<76> a_wl_l<75> a_wl_l<74> a_wl_l<73> a_wl_l<72> a_wl_l<71> a_wl_l<70> a_wl_l<69> a_wl_l<68> a_wl_l<67> a_wl_l<66> a_wl_l<65> a_wl_l<64>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<3> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<2> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<1> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+XA_WLDRV<0> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0>  VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_WLDRV16X4
+
+
+XA_CTRL a_aclk_n A_BIST_CLK A_BIST_MEN A_BIST_EN A_BIST_REN A_BIST_WEN a_tiel A_CLK A_MEN a_dclk a_eclk a_pulse_h a_pulse_l a_pulse a_rclk A_REN a_cs a_wclk A_WEN VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_CTRL
+
+
+XA_ROWDEC a_addr_row<8> a_addr_row<7> a_addr_row<6> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> a_cs a_eclk a_wi<511> a_wi<510> a_wi<509> a_wi<508> a_wi<507> a_wi<506> a_wi<505> a_wi<504> a_wi<503> a_wi<502> a_wi<501> a_wi<500> a_wi<499> a_wi<498> a_wi<497> a_wi<496> a_wi<495> a_wi<494> a_wi<493> a_wi<492> a_wi<491> a_wi<490> a_wi<489> a_wi<488> a_wi<487> a_wi<486> a_wi<485> a_wi<484> a_wi<483> a_wi<482> a_wi<481> a_wi<480> a_wi<479> a_wi<478> a_wi<477> a_wi<476> a_wi<475> a_wi<474> a_wi<473> a_wi<472> a_wi<471> a_wi<470> a_wi<469> a_wi<468> a_wi<467> a_wi<466> a_wi<465> a_wi<464> a_wi<463> a_wi<462> a_wi<461> a_wi<460> a_wi<459> a_wi<458> a_wi<457> a_wi<456> a_wi<455> a_wi<454> a_wi<453> a_wi<452> a_wi<451> a_wi<450> a_wi<449> a_wi<448> a_wi<447> a_wi<446> a_wi<445> a_wi<444> a_wi<443> a_wi<442> a_wi<441> a_wi<440> a_wi<439> a_wi<438> a_wi<437> a_wi<436> a_wi<435> a_wi<434> a_wi<433> a_wi<432> a_wi<431> a_wi<430> a_wi<429> a_wi<428> a_wi<427> a_wi<426> a_wi<425> a_wi<424> a_wi<423> a_wi<422> a_wi<421> a_wi<420> a_wi<419> a_wi<418> a_wi<417> a_wi<416> a_wi<415> a_wi<414> a_wi<413> a_wi<412> a_wi<411> a_wi<410> a_wi<409> a_wi<408> a_wi<407> a_wi<406> a_wi<405> a_wi<404> a_wi<403> a_wi<402> a_wi<401> a_wi<400> a_wi<399> a_wi<398> a_wi<397> a_wi<396> a_wi<395> a_wi<394> a_wi<393> a_wi<392> a_wi<391> a_wi<390> a_wi<389> a_wi<388> a_wi<387> a_wi<386> a_wi<385> a_wi<384> a_wi<383> a_wi<382> a_wi<381> a_wi<380> a_wi<379> a_wi<378> a_wi<377> a_wi<376> a_wi<375> a_wi<374> a_wi<373> a_wi<372> a_wi<371> a_wi<370> a_wi<369> a_wi<368> a_wi<367> a_wi<366> a_wi<365> a_wi<364> a_wi<363> a_wi<362> a_wi<361> a_wi<360> a_wi<359> a_wi<358> a_wi<357> a_wi<356> a_wi<355> a_wi<354> a_wi<353> a_wi<352> a_wi<351> a_wi<350> a_wi<349> a_wi<348> a_wi<347> a_wi<346> a_wi<345> a_wi<344> a_wi<343> a_wi<342> a_wi<341> a_wi<340> a_wi<339> a_wi<338> a_wi<337> a_wi<336> a_wi<335> a_wi<334> a_wi<333> a_wi<332> a_wi<331> a_wi<330> a_wi<329> a_wi<328> a_wi<327> a_wi<326> a_wi<325> a_wi<324> a_wi<323> a_wi<322> a_wi<321> a_wi<320> a_wi<319> a_wi<318> a_wi<317> a_wi<316> a_wi<315> a_wi<314> a_wi<313> a_wi<312> a_wi<311> a_wi<310> a_wi<309> a_wi<308> a_wi<307> a_wi<306> a_wi<305> a_wi<304> a_wi<303> a_wi<302> a_wi<301> a_wi<300> a_wi<299> a_wi<298> a_wi<297> a_wi<296> a_wi<295> a_wi<294> a_wi<293> a_wi<292> a_wi<291> a_wi<290> a_wi<289> a_wi<288> a_wi<287> a_wi<286> a_wi<285> a_wi<284> a_wi<283> a_wi<282> a_wi<281> a_wi<280> a_wi<279> a_wi<278> a_wi<277> a_wi<276> a_wi<275> a_wi<274> a_wi<273> a_wi<272> a_wi<271> a_wi<270> a_wi<269> a_wi<268> a_wi<267> a_wi<266> a_wi<265> a_wi<264> a_wi<263> a_wi<262> a_wi<261> a_wi<260> a_wi<259> a_wi<258> a_wi<257> a_wi<256> a_wi<255> a_wi<254> a_wi<253> a_wi<252> a_wi<251> a_wi<250> a_wi<249> a_wi<248> a_wi<247> a_wi<246> a_wi<245> a_wi<244> a_wi<243> a_wi<242> a_wi<241> a_wi<240> a_wi<239> a_wi<238> a_wi<237> a_wi<236> a_wi<235> a_wi<234> a_wi<233> a_wi<232> a_wi<231> a_wi<230> a_wi<229> a_wi<228> a_wi<227> a_wi<226> a_wi<225> a_wi<224> a_wi<223> a_wi<222> a_wi<221> a_wi<220> a_wi<219> a_wi<218> a_wi<217> a_wi<216> a_wi<215> a_wi<214> a_wi<213> a_wi<212> a_wi<211> a_wi<210> a_wi<209> a_wi<208> a_wi<207> a_wi<206> a_wi<205> a_wi<204> a_wi<203> a_wi<202> a_wi<201> a_wi<200> a_wi<199> a_wi<198> a_wi<197> a_wi<196> a_wi<195> a_wi<194> a_wi<193> a_wi<192> a_wi<191> a_wi<190> a_wi<189> a_wi<188> a_wi<187> a_wi<186> a_wi<185> a_wi<184> a_wi<183> a_wi<182> a_wi<181> a_wi<180> a_wi<179> a_wi<178> a_wi<177> a_wi<176> a_wi<175> a_wi<174> a_wi<173> a_wi<172> a_wi<171> a_wi<170> a_wi<169> a_wi<168> a_wi<167> a_wi<166> a_wi<165> a_wi<164> a_wi<163> a_wi<162> a_wi<161> a_wi<160> a_wi<159> a_wi<158> a_wi<157> a_wi<156> a_wi<155> a_wi<154> a_wi<153> a_wi<152> a_wi<151> a_wi<150> a_wi<149> a_wi<148> a_wi<147> a_wi<146> a_wi<145> a_wi<144> a_wi<143> a_wi<142> a_wi<141> a_wi<140> a_wi<139> a_wi<138> a_wi<137> a_wi<136> a_wi<135> a_wi<134> a_wi<133> a_wi<132> a_wi<131> a_wi<130> a_wi<129> a_wi<128> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_ROWDEC9
+XA_ROWREG a_aclk_n A_ADDR<11> A_ADDR<10> A_ADDR<9> A_ADDR<8> A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> a_addr_row<8> a_addr_row<7> a_addr_row<6> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> A_BIST_ADDR<11> A_BIST_ADDR<10> A_BIST_ADDR<9> A_BIST_ADDR<8> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_EN VDD! VSS!  / RM_IHPSG13_4096x16_c3_1P_ROWREG9
+XA_COLDEC a_aclk_n A_ADDR<2> A_ADDR<1> A_ADDR<0> a_addr_col<1> a_addr_col<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> A_BIST_ADDR<2> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_EN VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLDEC3
+
+
+XA_DLYH a_pulse a_pulse_h VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_DLY_pcell_2
+XA_DLYL a_pulse_x a_pulse_l VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_DLY_pcell_3
+XA_DLYMUX a_pulse_h A_DLY a_pulse_x VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_DLY_MUX
+
+XCOLCTRL<15> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<15> A_BIST_DIN<15> A_BIST_EN a_blc_r<63> a_blc_r<62> a_blc_r<61> a_blc_r<60> a_blc_r<59> a_blc_r<58> a_blc_r<57> a_blc_r<56> a_blt_r<63> a_blt_r<62> a_blt_r<61> a_blt_r<60> a_blt_r<59> a_blt_r<58> a_blt_r<57> a_blt_r<56> A_BM<15> a_dclk_n_r<7> a_dclk_n_r<8> a_dclk_p_r<7> a_dclk_p_r<8> A_DOUT<15> A_DIN<15> a_rclk_n_r<7> a_rclk_n_r<8> a_rclk_p_r<7> a_rclk_p_r<8> a_tieh<15> a_wclk_n_r<7> a_wclk_n_r<8> a_wclk_p_r<7> a_wclk_p_r<8> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLCTRL3
+XCOLCTRL<14> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<14> A_BIST_DIN<14> A_BIST_EN a_blc_r<55> a_blc_r<54> a_blc_r<53> a_blc_r<52> a_blc_r<51> a_blc_r<50> a_blc_r<49> a_blc_r<48> a_blt_r<55> a_blt_r<54> a_blt_r<53> a_blt_r<52> a_blt_r<51> a_blt_r<50> a_blt_r<49> a_blt_r<48> A_BM<14> a_dclk_n_r<6> a_dclk_n_r<7> a_dclk_p_r<6> a_dclk_p_r<7> A_DOUT<14> A_DIN<14> a_rclk_n_r<6> a_rclk_n_r<7> a_rclk_p_r<6> a_rclk_p_r<7> a_tieh<14> a_wclk_n_r<6> a_wclk_n_r<7> a_wclk_p_r<6> a_wclk_p_r<7> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLCTRL3
+XCOLCTRL<13> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<13> A_BIST_DIN<13> A_BIST_EN a_blc_r<47> a_blc_r<46> a_blc_r<45> a_blc_r<44> a_blc_r<43> a_blc_r<42> a_blc_r<41> a_blc_r<40> a_blt_r<47> a_blt_r<46> a_blt_r<45> a_blt_r<44> a_blt_r<43> a_blt_r<42> a_blt_r<41> a_blt_r<40> A_BM<13> a_dclk_n_r<5> a_dclk_n_r<6> a_dclk_p_r<5> a_dclk_p_r<6> A_DOUT<13> A_DIN<13> a_rclk_n_r<5> a_rclk_n_r<6> a_rclk_p_r<5> a_rclk_p_r<6> a_tieh<13> a_wclk_n_r<5> a_wclk_n_r<6> a_wclk_p_r<5> a_wclk_p_r<6> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLCTRL3
+XCOLCTRL<12> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<12> A_BIST_DIN<12> A_BIST_EN a_blc_r<39> a_blc_r<38> a_blc_r<37> a_blc_r<36> a_blc_r<35> a_blc_r<34> a_blc_r<33> a_blc_r<32> a_blt_r<39> a_blt_r<38> a_blt_r<37> a_blt_r<36> a_blt_r<35> a_blt_r<34> a_blt_r<33> a_blt_r<32> A_BM<12> a_dclk_n_r<4> a_dclk_n_r<5> a_dclk_p_r<4> a_dclk_p_r<5> A_DOUT<12> A_DIN<12> a_rclk_n_r<4> a_rclk_n_r<5> a_rclk_p_r<4> a_rclk_p_r<5> a_tieh<12> a_wclk_n_r<4> a_wclk_n_r<5> a_wclk_p_r<4> a_wclk_p_r<5> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLCTRL3
+XCOLCTRL<11> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<11> A_BIST_DIN<11> A_BIST_EN a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> A_BM<11> a_dclk_n_r<3> a_dclk_n_r<4> a_dclk_p_r<3> a_dclk_p_r<4> A_DOUT<11> A_DIN<11> a_rclk_n_r<3> a_rclk_n_r<4> a_rclk_p_r<3> a_rclk_p_r<4> a_tieh<11> a_wclk_n_r<3> a_wclk_n_r<4> a_wclk_p_r<3> a_wclk_p_r<4> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLCTRL3
+XCOLCTRL<10> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<10> A_BIST_DIN<10> A_BIST_EN a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> A_BM<10> a_dclk_n_r<2> a_dclk_n_r<3> a_dclk_p_r<2> a_dclk_p_r<3> A_DOUT<10> A_DIN<10> a_rclk_n_r<2> a_rclk_n_r<3> a_rclk_p_r<2> a_rclk_p_r<3> a_tieh<10> a_wclk_n_r<2> a_wclk_n_r<3> a_wclk_p_r<2> a_wclk_p_r<3> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLCTRL3
+XCOLCTRL<9> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<9> A_BIST_DIN<9> A_BIST_EN a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> A_BM<9> a_dclk_n_r<1> a_dclk_n_r<2> a_dclk_p_r<1> a_dclk_p_r<2> A_DOUT<9> A_DIN<9> a_rclk_n_r<1> a_rclk_n_r<2> a_rclk_p_r<1> a_rclk_p_r<2> a_tieh<9> a_wclk_n_r<1> a_wclk_n_r<2> a_wclk_p_r<1> a_wclk_p_r<2> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLCTRL3
+XCOLCTRL<8> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<8> A_BIST_DIN<8> A_BIST_EN a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> A_BM<8> a_dclk_n_r<0> a_dclk_n_r<1> a_dclk_p_r<0> a_dclk_p_r<1> A_DOUT<8> A_DIN<8> a_rclk_n_r<0> a_rclk_n_r<1> a_rclk_p_r<0> a_rclk_p_r<1> a_tieh<8> a_wclk_n_r<0> a_wclk_n_r<1> a_wclk_p_r<0> a_wclk_p_r<1> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLCTRL3
+XCOLCTRL<7> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<0> A_BIST_DIN<0> A_BIST_EN a_blc_l<63> a_blc_l<62> a_blc_l<61> a_blc_l<60> a_blc_l<59> a_blc_l<58> a_blc_l<57> a_blc_l<56> a_blt_l<63> a_blt_l<62> a_blt_l<61> a_blt_l<60> a_blt_l<59> a_blt_l<58> a_blt_l<57> a_blt_l<56> A_BM<0> a_dclk_n_l<7> a_dclk_n_l<8> a_dclk_p_l<7> a_dclk_p_l<8> A_DOUT<0> A_DIN<0> a_rclk_n_l<7> a_rclk_n_l<8> a_rclk_p_l<7> a_rclk_p_l<8> a_tieh<0> a_wclk_n_l<7> a_wclk_n_l<8> a_wclk_p_l<7> a_wclk_p_l<8> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLCTRL3
+XCOLCTRL<6> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<1> A_BIST_DIN<1> A_BIST_EN a_blc_l<55> a_blc_l<54> a_blc_l<53> a_blc_l<52> a_blc_l<51> a_blc_l<50> a_blc_l<49> a_blc_l<48> a_blt_l<55> a_blt_l<54> a_blt_l<53> a_blt_l<52> a_blt_l<51> a_blt_l<50> a_blt_l<49> a_blt_l<48> A_BM<1> a_dclk_n_l<6> a_dclk_n_l<7> a_dclk_p_l<6> a_dclk_p_l<7> A_DOUT<1> A_DIN<1> a_rclk_n_l<6> a_rclk_n_l<7> a_rclk_p_l<6> a_rclk_p_l<7> a_tieh<1> a_wclk_n_l<6> a_wclk_n_l<7> a_wclk_p_l<6> a_wclk_p_l<7> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLCTRL3
+XCOLCTRL<5> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<2> A_BIST_DIN<2> A_BIST_EN a_blc_l<47> a_blc_l<46> a_blc_l<45> a_blc_l<44> a_blc_l<43> a_blc_l<42> a_blc_l<41> a_blc_l<40> a_blt_l<47> a_blt_l<46> a_blt_l<45> a_blt_l<44> a_blt_l<43> a_blt_l<42> a_blt_l<41> a_blt_l<40> A_BM<2> a_dclk_n_l<5> a_dclk_n_l<6> a_dclk_p_l<5> a_dclk_p_l<6> A_DOUT<2> A_DIN<2> a_rclk_n_l<5> a_rclk_n_l<6> a_rclk_p_l<5> a_rclk_p_l<6> a_tieh<2> a_wclk_n_l<5> a_wclk_n_l<6> a_wclk_p_l<5> a_wclk_p_l<6> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLCTRL3
+XCOLCTRL<4> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<3> A_BIST_DIN<3> A_BIST_EN a_blc_l<39> a_blc_l<38> a_blc_l<37> a_blc_l<36> a_blc_l<35> a_blc_l<34> a_blc_l<33> a_blc_l<32> a_blt_l<39> a_blt_l<38> a_blt_l<37> a_blt_l<36> a_blt_l<35> a_blt_l<34> a_blt_l<33> a_blt_l<32> A_BM<3> a_dclk_n_l<4> a_dclk_n_l<5> a_dclk_p_l<4> a_dclk_p_l<5> A_DOUT<3> A_DIN<3> a_rclk_n_l<4> a_rclk_n_l<5> a_rclk_p_l<4> a_rclk_p_l<5> a_tieh<3> a_wclk_n_l<4> a_wclk_n_l<5> a_wclk_p_l<4> a_wclk_p_l<5> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLCTRL3
+XCOLCTRL<3> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<4> A_BIST_DIN<4> A_BIST_EN a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> A_BM<4> a_dclk_n_l<3> a_dclk_n_l<4> a_dclk_p_l<3> a_dclk_p_l<4> A_DOUT<4> A_DIN<4> a_rclk_n_l<3> a_rclk_n_l<4> a_rclk_p_l<3> a_rclk_p_l<4> a_tieh<4> a_wclk_n_l<3> a_wclk_n_l<4> a_wclk_p_l<3> a_wclk_p_l<4> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLCTRL3
+XCOLCTRL<2> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<5> A_BIST_DIN<5> A_BIST_EN a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> A_BM<5> a_dclk_n_l<2> a_dclk_n_l<3> a_dclk_p_l<2> a_dclk_p_l<3> A_DOUT<5> A_DIN<5> a_rclk_n_l<2> a_rclk_n_l<3> a_rclk_p_l<2> a_rclk_p_l<3> a_tieh<5> a_wclk_n_l<2> a_wclk_n_l<3> a_wclk_p_l<2> a_wclk_p_l<3> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLCTRL3
+XCOLCTRL<1> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<6> A_BIST_DIN<6> A_BIST_EN a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> A_BM<6> a_dclk_n_l<1> a_dclk_n_l<2> a_dclk_p_l<1> a_dclk_p_l<2> A_DOUT<6> A_DIN<6> a_rclk_n_l<1> a_rclk_n_l<2> a_rclk_p_l<1> a_rclk_p_l<2> a_tieh<6> a_wclk_n_l<1> a_wclk_n_l<2> a_wclk_p_l<1> a_wclk_p_l<2> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLCTRL3
+XCOLCTRL<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<7> A_BIST_DIN<7> A_BIST_EN a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> A_BM<7> a_dclk_n_l<0> a_dclk_n_l<1> a_dclk_p_l<0> a_dclk_p_l<1> A_DOUT<7> A_DIN<7> a_rclk_n_l<0> a_rclk_n_l<1> a_rclk_p_l<0> a_rclk_p_l<1> a_tieh<7> a_wclk_n_l<0> a_wclk_n_l<1> a_wclk_p_l<0> a_wclk_p_l<1> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLCTRL3
+
+
+XDRVFILL4<1> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLDRV13_FILL4
+XDRVFILL4<2> VDD! VSS! / RM_IHPSG13_4096x16_c3_1P_COLDRV13_FILL4
+.ENDS
diff --git a/ihp-sg13g2/libs.ref/sg13g2_sram/cdl/RM_IHPSG13_1P_4096x8_c3_bm_bist.cdl b/ihp-sg13g2/libs.ref/sg13g2_sram/cdl/RM_IHPSG13_1P_4096x8_c3_bm_bist.cdl
new file mode 100644
index 00000000..408d8604
--- /dev/null
+++ b/ihp-sg13g2/libs.ref/sg13g2_sram/cdl/RM_IHPSG13_1P_4096x8_c3_bm_bist.cdl
@@ -0,0 +1,6457 @@
+* ------------------------------------------------------
+*
+*		Copyright 2024 IHP PDK Authors
+*
+*		Licensed under the Apache License, Version 2.0 (the "License");
+*		you may not use this file except in compliance with the License.
+*		You may obtain a copy of the License at
+*		
+*		   https://www.apache.org/licenses/LICENSE-2.0
+*		
+*		Unless required by applicable law or agreed to in writing, software
+*		distributed under the License is distributed on an "AS IS" BASIS,
+*		WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+*		See the License for the specific language governing permissions and
+*		limitations under the License.
+*		
+*		Generated on Fri Jul 19 08:59:30 2024		
+*
+* ------------------------------------------------------ 
+
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_BITKIT_CORNER NW PW VDD VSS
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_CORNER VDD_CORE VSS
+XI16 VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_1P_BITKIT_CORNER
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_LR LWL NW PW VDD VSS
+MN1 VSS LWL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MN0 VSS net9 VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> 
++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> 
++ A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS
+XI0<15> A_WL<15> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_LR
+XI0<14> A_WL<14> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_LR
+XI0<13> A_WL<13> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_LR
+XI0<12> A_WL<12> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_LR
+XI0<11> A_WL<11> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_LR
+XI0<10> A_WL<10> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_LR
+XI0<9> A_WL<9> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_LR
+XI0<8> A_WL<8> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_LR
+XI0<7> A_WL<7> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_LR
+XI0<6> A_WL<6> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_LR
+XI0<5> A_WL<5> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_LR
+XI0<4> A_WL<4> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_LR
+XI0<3> A_WL<3> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_LR
+XI0<2> A_WL<2> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_LR
+XI0<1> A_WL<1> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_LR
+XI0<0> A_WL<0> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_LR
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL BLC_BOT BLC_TOP BLT_BOT BLT_TOP LWL NW PW 
++ RWL VDD VSS
+MN0 NC NT VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MN1 NT NC VSS PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MN3 NC RWL BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MN2 BLT_BOT LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0
+MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0
+R1 BLC_BOT BLC_TOP lvsres w=2.6e-07 l=6e-07
+R0 BLT_BOT BLT_TOP lvsres w=2.6e-07 l=6e-07
+R2 RWL LWL lvsres w=2.6e-07 l=6e-07
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> 
++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> 
++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> 
++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> 
++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> 
++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE 
++ VSS
+XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_RWL<15> 
++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL
+XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_RWL<14> VDD_CORE 
++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL
+XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_RWL<13> VDD_CORE 
++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL
+XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_RWL<12> VDD_CORE 
++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL
+XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_RWL<11> VDD_CORE 
++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL
+XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_RWL<10> VDD_CORE 
++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL
+XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_RWL<9> VDD_CORE 
++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL
+XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_RWL<8> VDD_CORE 
++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL
+XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_RWL<7> VDD_CORE 
++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL
+XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_RWL<6> VDD_CORE 
++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL
+XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_RWL<5> VDD_CORE 
++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL
+XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_RWL<4> VDD_CORE 
++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL
+XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_RWL<3> VDD_CORE 
++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL
+XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_RWL<2> VDD_CORE 
++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL
+XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_RWL<1> VDD_CORE 
++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL
+XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_RWL<0> VDD_CORE 
++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL
+XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> 
++ VDD_CORE VSS A_XWL<15> VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL
+XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> VDD_CORE 
++ VSS A_XWL<14> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL
+XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> VDD_CORE 
++ VSS A_XWL<13> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL
+XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> VDD_CORE 
++ VSS A_XWL<12> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL
+XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> VDD_CORE 
++ VSS A_XWL<11> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL
+XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> VDD_CORE 
++ VSS A_XWL<10> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL
+XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> VDD_CORE 
++ VSS A_XWL<9> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL
+XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> VDD_CORE 
++ VSS A_XWL<8> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL
+XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> VDD_CORE 
++ VSS A_XWL<7> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL
+XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> VDD_CORE 
++ VSS A_XWL<6> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL
+XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> VDD_CORE 
++ VSS A_XWL<5> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL
+XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> VDD_CORE 
++ VSS A_XWL<4> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL
+XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> VDD_CORE 
++ VSS A_XWL<3> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL
+XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> VDD_CORE 
++ VSS A_XWL<2> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL
+XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> VDD_CORE 
++ VSS A_XWL<1> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL
+XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> VDD_CORE 
++ VSS A_XWL<0> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_CELL
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_TB BLC BLT NW PW VDD VSS
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> 
++ VDD_CORE VSS
+XEDGE<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_TB
+XEDGE<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_TB
+.ENDS
+
+.SUBCKT RSC_IHPSG13_CBUFX4 A Z VDD VSS
+MN0 net9 A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN1 Z net9 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0
+MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP1 Z net9 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> 
++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> 
++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> 
++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> 
++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O 
++ VDD VSS
+XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4
+XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4
+XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4
+.ENDS
+.SUBCKT RSC_IHPSG13_WLDRVX4 A Z VDD VSS
+MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0
+MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0
+MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> 
++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> 
++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS
+XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4
+.ENDS
+.SUBCKT RSC_IHPSG13_FILLCAP8 VDD VSS
+MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=4.98u l=130.00n ng=6 nrd=0 
++ nrs=0
+MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=6.48u l=385.000n ng=4 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_LHPQX2 CP D Q VDD VSS
+MN3 QIN CPN net14 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0
+MN2 net14 net10 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN5 net21 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN6 QIN CP net21 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 nrs=0
+MN1 net10 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN4 Q QIN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MP2 QIN CP net16 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0
+MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP4 Q QIN VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP3 net10 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 net16 net10 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP6 QIN CPN net20 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP5 net20 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_NAND2X2 A B Z VDD VSS
+MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MN0 Z B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MN1 net7 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_CINVX4 A Z VDD VSS
+MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0
+MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_CINVX2 A Z VDD VSS
+MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0
+MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_INVX2 A Z VDD VSS
+MN0 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_NAND3X2 A B C Z VDD VSS
+MP2 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP0 Z C VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MN1 net12 B net16 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MN0 Z C net12 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MN2 net16 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_NOR3X2 A B C Z VDD VSS
+MP0 net13 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP2 Z C net10 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP1 net10 B net13 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MN1 Z B VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0
+MN0 Z C VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0
+MN2 Z A VSS VSS sg13_lv_nmos m=1 w=875.000n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_FILLCAP4 VDD VSS
+MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=130.00n ng=3 nrd=0 
++ nrs=0
+MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=385.000n ng=2 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_MET2RES A B
+R0 B A lvsres w=2.6e-07 l=6e-07
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT 
++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> 
++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS
+XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2
+XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2
+XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2
+XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2
+XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2
+XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2
+XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2
+XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2
+XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4
+XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2
+XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2
+XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2
+XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2
+XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4
+XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES
+XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> 
++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> 
++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> 
++ VDD VSS
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> 
++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> 
++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> 
++ WL_O<0> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04
+.ENDS
+.SUBCKT RSC_IHPSG13_CINVX8 A Z VDD VSS
+MN0 Z A VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0
+MP0 Z A VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_DFNQMX2IX1 BE BI CN D QI QIN VDD VSS
+MN15 net026 BI VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN14 MXI_OUT BE net026 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN1 net025 D VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN0 MXI_OUT BEN net025 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN10 QI CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 nrs=0
+MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN9 net37 MXI_OUT VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN5 QI CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0
+MN4 net25 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN2 QIN QI VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN13 BEN BE VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP15 MXI_OUT BEN net027 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP14 net027 BI VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP1 MXI_OUT BE net024 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP0 net024 D VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP13 BEN BE VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP3 QI CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0
+MP2 net27 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP10 net36 MXI_OUT VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP7 QIN QI VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP9 QI CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 nrs=0
+MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> 
++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> 
++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+.SUBCKT RSC_IHPSG13_CDLYX1 A Z VDD VSS
+MN1 net010 net032 VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 
++ nrd=0 nrs=0
+MN2 net032 A net014 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 
++ nrs=0
+MN0 Z net032 net010 VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 
++ nrs=0
+MN3 net014 A VSS VSS sg13_lv_nmos m=1 w=300.0n l=160.00n ng=1 nrd=0 
++ nrs=0
+MP1 Z net032 net07 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 
++ nrs=0
+MP3 net011 A VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 
++ nrs=0
+MP0 net07 net032 VDD VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 
++ nrd=0 nrs=0
+MP2 net032 A net011 VDD sg13_lv_pmos m=1 w=720.00n l=160.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_CDLYX1_DUMMY A Z VDD VSS
+MN0 vss_r vdd_r VSS VSS sg13_lv_nmos m=1 w=2.49u l=300.0n ng=3 nrd=0 
++ nrs=0
+MP0 vdd_r vss_r VDD VDD sg13_lv_pmos m=1 w=3.24u l=640.00n ng=2 nrd=0 
++ nrs=0
+R0 Z A lvsres w=2.6e-07 l=6e-07
+.ENDS
+
+.SUBCKT RSC_IHPSG13_MX2IX1 A0 A1 S ZN VDD VSS
+MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0
+MP3 ZN SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0
+MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 ZN S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 nrs=0
+MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN5 SN S VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0
+MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN2 ZN S net13 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0
+MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN0 ZN SN net15 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_DLY_MUX A SEL Z VDD VSS
+XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2
+XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1
+XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1
+XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1
+XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1
+.ENDS
+.SUBCKT RSC_IHPSG13_DFNQX2 CN D Q VDD VSS
+MN0 Q QIN_SL VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN10 QIN_SL CNN net21 VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN11 net21 QI_MS VSS VSS sg13_lv_nmos m=1 w=850.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN7 net30 QI_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN6 QIN_MS CNN net30 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN3 QI_MS QIN_MS VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN12 CNN CN VSS VSS sg13_lv_nmos m=1 w=495.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN9 net37 D VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN8 QIN_MS CN net37 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN5 QIN_SL CN net25 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN4 net25 QI_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN2 QI_SL QIN_SL VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP0 Q QIN_SL VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 
++ nrs=0
+MP6 QI_MS QIN_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP3 QIN_SL CNN net27 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP2 net27 QI_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP10 net36 D VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP11 QIN_MS CNN net36 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP4 net32 QI_MS VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP5 QIN_MS CN net32 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP7 QI_SL QIN_SL VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP12 CNN CN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP9 QIN_SL CN net19 VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP8 net19 QI_MS VDD VDD sg13_lv_pmos m=1 w=990.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_CNAND2X2 A B Z VDD VSS
+MN0 Z B net6 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MN1 net6 A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 Z B VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP0 Z A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_CGATEPX4 CP E Q VDD VSS
+MN1 net08 QIN VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN2 net019 net08 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN3 QIN CP net019 VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 nrs=0
+MN6 Q net015 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 
++ nrs=0
+MN5 net015 net08 net018 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MN8 QIN CPN net023 VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN7 net023 E VSS VSS sg13_lv_nmos m=1 w=870.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN4 net018 CP VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN0 CPN CP VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0
+MP3 net08 QIN VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP2 QIN CPN net017 VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 net017 net08 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP0 CPN CP VDD VDD sg13_lv_pmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0
+MP8 QIN CP net024 VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP7 net024 E VDD VDD sg13_lv_pmos m=1 w=975.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP4 net015 CP VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 
++ nrs=0
+MP6 Q net015 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 
++ nrs=0
+MP5 net015 net08 VDD VDD sg13_lv_pmos m=1 w=1.27u l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_CBUFX8 A Z VDD VSS
+MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0
+MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0
+MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=2.82u l=130.00n ng=4 nrd=0 nrs=0
+MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_CDLYX2 A Z VDD VSS
+MN2 net4 A net9 VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0
+MN0 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN1 net9 A VSS VSS sg13_lv_nmos m=1 w=320.00n l=200.0n ng=1 nrd=0 nrs=0
+MP2 net4 A net10 VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0
+MP1 net10 A VDD VDD sg13_lv_pmos m=1 w=1.2u l=200.0n ng=1 nrd=0 nrs=0
+MP0 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_MX2X2 A0 A1 S Z VDD VSS
+MP6 Z net010 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 
++ nrs=0
+MP4 SN S VDD VDD sg13_lv_pmos m=1 w=645.000n l=130.00n ng=1 nrd=0 nrs=0
+MP3 net010 SN net12 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP2 net12 A1 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 net010 S net17 VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP0 net17 A0 VDD VDD sg13_lv_pmos m=1 w=985.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN6 Z net010 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN5 SN S VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 nrs=0
+MN3 net13 A1 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN2 net010 S net13 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN1 net15 A0 VSS VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN0 net010 SN net15 VSS sg13_lv_nmos m=1 w=560.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_AND2X2 A B Z VDD VSS
+MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0
+MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0
+MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_TIEL Z VDD VSS
+MN0 Z net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP0 net2 net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_XOR2X2 A B Z VDD VSS
+MP8 net012 B net7 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP7 net011 net3 net012 VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP6 Z net012 VDD VDD sg13_lv_pmos m=1 w=1.535u l=130.00n ng=1 nrd=0 
++ nrs=0
+MP2 net7 A VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP4 net011 net7 VDD VDD sg13_lv_pmos m=1 w=825.000n l=130.00n ng=1 
++ nrd=0 nrs=0
+MP5 net3 B VDD VDD sg13_lv_pmos m=1 w=580.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN7 net012 B net011 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN6 net7 net3 net012 VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN5 Z net012 VSS VSS sg13_lv_nmos m=1 w=775.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN2 net7 A VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN4 net3 B VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN3 net011 net7 VSS VSS sg13_lv_nmos m=1 w=555.000n l=130.00n ng=1 
++ nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_OA12X1 A B C Z VDD VSS
+MN2 net7 C VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN3 Z net17 VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN1 net17 B net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MN0 net17 A net7 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MP0 net24 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP3 Z net17 VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 net17 B net24 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP2 net17 C VDD VDD sg13_lv_pmos m=1 w=905.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I 
++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I 
++ ROW_CS WCLK WE_I VDD VSS
+XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2
+XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2
+XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2
+XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2
+XI77 col_we net9 net016 VDD VSS / RSC_IHPSG13_CNAND2X2
+XI76 col_re net9 net018 VDD VSS / RSC_IHPSG13_CNAND2X2
+XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4
+XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4
+XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8
+XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2
+XI8 net9 net8 VDD VSS / RSC_IHPSG13_CINVX2
+XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2
+XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2
+XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2
+XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2
+XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2
+XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2
+XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL
+XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4
+XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4
+XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4
+XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4
+XI6 PULSE_L PULSE_H net9 VDD VSS / RSC_IHPSG13_XOR2X2
+XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8
+XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8
+XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> 
++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> 
++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS
+XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI1<3> PADR<1> PADR<0> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2
+XI1<2> PADR<1> NADR<0> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2
+XI1<1> NADR<1> PADR<0> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2
+XI1<0> NADR<1> NADR<0> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2
+XI16<37> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<36> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<35> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<34> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<33> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<32> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<31> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<30> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2
+XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2
+XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2
+XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2
+XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL
+XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL
+XI17<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL
+XI17<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL
+XI17<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL
+XI17<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL
+.ENDS
+.SUBCKT RSC_IHPSG13_NOR2X2 A B Z VDD VSS
+MP1 Z B net9 VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP0 net9 A VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MN0 Z B VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MN1 Z A VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_CINVX4_WN A Z VDD VSS
+MN0 Z A VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 nrs=0
+MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_BLDRV BLC BLC_SEL BLT BLT_SEL PRE_N SEL_P WR_ONE WR_ZERO 
++ VDD VSS
+XCDEC SEL_P WR_ZERO BLC_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2
+XTDEC SEL_P WR_ONE BLT_PMOS_DRIVE VDD VSS / RSC_IHPSG13_NAND2X2
+MTWN BLT BLT_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MCWN BLC BLC_NMOS_DRIVE VSS VSS sg13_lv_nmos m=1 w=4.82u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MCWP BLC BLC_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 
++ nrd=0 nrs=0
+MTWP BLT BLT_PMOS_DRIVE VDD VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 
++ nrd=0 nrs=0
+MTSP BLT_SEL SEL_N BLT VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 
++ nrs=0
+MTPR BLT PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 
++ nrs=0
+MCSP BLC_SEL SEL_N BLC VDD sg13_lv_pmos m=1 w=1.5u l=130.00n ng=1 nrd=0 
++ nrs=0
+MCPR BLC PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n ng=2 nrd=0 
++ nrs=0
+XI86 SEL_P SEL_N VDD VSS / RSC_IHPSG13_INVX2
+XTINV BLC_PMOS_DRIVE BLT_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2
+XCINV BLT_PMOS_DRIVE BLC_NMOS_DRIVE VDD VSS / RSC_IHPSG13_INVX2
+.ENDS
+.SUBCKT RSC_IHPSG13_TIEH Z VDD VSS
+MN0 net2 net2 VSS VSS sg13_lv_nmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP0 Z net2 VDD VDD sg13_lv_pmos m=1 w=480.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_MET3RES A B
+R0 B A lvsres w=2.6e-07 l=6e-07
+.ENDS
+.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2 CP DN DP QN QP VDD VSS
+MN12 SN RN DIFFP VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0
+MN13 TAIL CP VSS VSS sg13_lv_nmos m=1 w=2.4u l=130.00n ng=2 nrd=0 nrs=0
+MN9 DIFFP DP TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0
+MN10 DIFFN DN TAIL VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0
+MN11 RN SN DIFFN VSS sg13_lv_nmos m=1 w=2.4u l=200.0n ng=2 nrd=0 nrs=0
+MN19 net33 SN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN20 QN QP net37 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MN18 net37 RN VSS VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN17 QP QN net33 VSS sg13_lv_nmos m=1 w=980.00n l=130.00n ng=1 nrd=0 nrs=0
+MP15 SN RN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0
+MP16 RN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0
+MP14 DIFFP CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP12 RN SN VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0
+MP13 DIFFN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP11 SN CP VDD VDD sg13_lv_pmos m=1 w=800.0n l=130.00n ng=1 nrd=0 nrs=0
+MP19 QN QP VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0
+MP20 QP SN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0
+MP18 QN RN VDD VDD sg13_lv_pmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0
+MP17 QP QN VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_CBUFX2 A Z VDD VSS
+MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=705.000n l=130.00n ng=1 nrd=0 
++ nrs=0
+MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=540.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=1.62u l=130.00n ng=1 nrd=0 nrs=0
+MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=1.1u l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RSC_IHPSG13_INVX4 A Z VDD VSS
+MN0 Z A VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0
+MP0 Z A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> 
++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> 
++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R 
++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R 
++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS
+XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2
+XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2
+XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2
+XA_I44 A_WCLK_B_R A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES
+XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES
+XA_I91 A_RCLK_B_R A_RCLK_B_L / RSC_IHPSG13_MET3RES
+XA_R2 A_RCLK_R A_RCLK_L / RSC_IHPSG13_MET3RES
+XA_I90 A_WCLK_B_R A_WCLK_B_L / RSC_IHPSG13_MET3RES
+XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XA_I78 A_RCLK_B_R A_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XA_I50 A_WCLK_L A_WCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2
+XA_EBUF A_RCLK_R A_RCLK_B_R VDD VSS / RSC_IHPSG13_CINVX2
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_COLDRV13_FILL4 VDD VSS
+XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_COLDRV13_FILL4C2 VDD VSS
+XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> 
++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> 
++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> 
++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS
+XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL
+XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2
+XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net7<0> VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2
+XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2
+XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2
+XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2
+XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2
+XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2
+XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2
+XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2
+XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2
+XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+.SUBCKT RSC_IHPSG13_AND2X4 A B Z VDD VSS
+MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.96u l=130.00n ng=2 nrd=0 nrs=0
+MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0
+MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0
+MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0
+MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> 
++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> 
++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> 
++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> 
++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> 
++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> 
++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L 
++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L 
++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS
+XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2
+XA_I76 A_DO_WRITE_P A_DI_N A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4
+XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4
+XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4
+XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4
+XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4
+XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES
+XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES
+XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES
+XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES
+XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2
+XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI73<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> 
++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> 
++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> 
++ BIST_EN_I VDD VSS
+XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL
+XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL
+XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2
+XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net6<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net6<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net6<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2
+XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2
+XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2
+XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2
+XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2
+XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2
+XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2
+XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2
+XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> 
++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> 
++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> 
++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> 
++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L 
++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O 
++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS
+XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_R A_BM_I A_BM_R net23 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_I70<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I70<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XA_I44 A_BM_N A_WCLK_B_R A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_ADDR_DEC<6> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_ADDR_DEC<5> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<4> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_ADDR_DEC<2> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_ADDR_DEC<1> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<0> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES
+XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES
+XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES
+XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I80 A_WCLK_B_R A_RCLK_B_R net21 VDD VSS / RSC_IHPSG13_AND2X2
+XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2
+XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2
+XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_BITKIT_16x2_CORNER VDD_CORE VSS
+XI16 VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_1P_BITKIT_CORNER
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_LR A_WL B_WL NW PW VDD VSS
+MN1 VSS A_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MN0 VSS B_WL VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_BITKIT_16x2_EDGE_LR A_WL<15> A_WL<14> A_WL<13> A_WL<12> 
++ A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> 
++ A_WL<2> A_WL<1> A_WL<0> B_WL<15> B_WL<14> B_WL<13> B_WL<12> B_WL<11> 
++ B_WL<10> B_WL<9> B_WL<8> B_WL<7> B_WL<6> B_WL<5> B_WL<4> B_WL<3> B_WL<2> 
++ B_WL<1> B_WL<0> VDD_CORE VSS
+XI0<15> A_WL<15> B_WL<15> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_LR
+XI0<14> A_WL<14> B_WL<14> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_LR
+XI0<13> A_WL<13> B_WL<13> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_LR
+XI0<12> A_WL<12> B_WL<12> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_LR
+XI0<11> A_WL<11> B_WL<11> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_LR
+XI0<10> A_WL<10> B_WL<10> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_LR
+XI0<9> A_WL<9> B_WL<9> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_LR
+XI0<8> A_WL<8> B_WL<8> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_LR
+XI0<7> A_WL<7> B_WL<7> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_LR
+XI0<6> A_WL<6> B_WL<6> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_LR
+XI0<5> A_WL<5> B_WL<5> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_LR
+XI0<4> A_WL<4> B_WL<4> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_LR
+XI0<3> A_WL<3> B_WL<3> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_LR
+XI0<2> A_WL<2> B_WL<2> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_LR
+XI0<1> A_WL<1> B_WL<1> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_LR
+XI0<0> A_WL<0> B_WL<0> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_LR
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL A_BLC_BOT A_BLC_TOP A_BLT_BOT A_BLT_TOP 
++ A_LWL A_RWL B_BLC_BOT B_BLC_TOP B_BLT_BOT B_BLT_TOP B_LWL B_RWL NW PW VDD VSS
+MN5 NC B_RWL B_BLC_BOT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MN4 B_BLT_BOT B_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MN0 NC NT VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0
+MN1 NT NC VSS PW sg13_lv_nmos m=1 w=600.0n l=130.00n ng=2 nrd=0 nrs=0
+MN3 NC A_RWL A_BLC_TOP PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MN2 A_BLT_TOP A_LWL NT PW sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1 nrd=0 nrs=0
+MP1 NT NC VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0
+MP0 NC NT VDD NW sg13_lv_pmos m=1 w=150.00n l=130.00n ng=1 nrd=0 nrs=0
+R5 B_RWL B_LWL lvsres w=2.6e-07 l=6e-07
+R4 B_BLC_BOT B_BLC_TOP lvsres w=2.6e-07 l=6e-07
+R3 B_BLT_BOT B_BLT_TOP lvsres w=2.6e-07 l=6e-07
+R1 A_BLC_BOT A_BLC_TOP lvsres w=2.6e-07 l=6e-07
+R0 A_BLT_BOT A_BLT_TOP lvsres w=2.6e-07 l=6e-07
+R2 A_RWL A_LWL lvsres w=2.6e-07 l=6e-07
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_BITKIT_16x2_SRAM A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> 
++ A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<15> 
++ A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> 
++ A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> 
++ A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> 
++ A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> B_BLC_BOT<1> 
++ B_BLC_BOT<0> B_BLC_TOP<1> B_BLC_TOP<0> B_BLT_BOT<1> B_BLT_BOT<0> 
++ B_BLT_TOP<1> B_BLT_TOP<0> B_LWL<15> B_LWL<14> B_LWL<13> B_LWL<12> B_LWL<11> 
++ B_LWL<10> B_LWL<9> B_LWL<8> B_LWL<7> B_LWL<6> B_LWL<5> B_LWL<4> B_LWL<3> 
++ B_LWL<2> B_LWL<1> B_LWL<0> B_RWL<15> B_RWL<14> B_RWL<13> B_RWL<12> B_RWL<11> 
++ B_RWL<10> B_RWL<9> B_RWL<8> B_RWL<7> B_RWL<6> B_RWL<5> B_RWL<4> B_RWL<3> 
++ B_RWL<2> B_RWL<1> B_RWL<0> VDD_CORE VSS
+XCELL<31> A_BLC_TOP<1> A_RBLC<15> A_BLT_TOP<1> A_RBLT<15> A_XWL<15> A_RWL<15> 
++ B_BLC_TOP<1> B_RBLC<15> B_BLT_TOP<1> B_RBLT<15> B_XWL<15> B_RWL<15> 
++ VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL
+XCELL<30> A_RBLC<14> A_RBLC<15> A_RBLT<14> A_RBLT<15> A_XWL<14> A_RWL<14> 
++ B_RBLC<14> B_RBLC<15> B_RBLT<14> B_RBLT<15> B_XWL<14> B_RWL<14> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL
+XCELL<29> A_RBLC<14> A_RBLC<13> A_RBLT<14> A_RBLT<13> A_XWL<13> A_RWL<13> 
++ B_RBLC<14> B_RBLC<13> B_RBLT<14> B_RBLT<13> B_XWL<13> B_RWL<13> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL
+XCELL<28> A_RBLC<12> A_RBLC<13> A_RBLT<12> A_RBLT<13> A_XWL<12> A_RWL<12> 
++ B_RBLC<12> B_RBLC<13> B_RBLT<12> B_RBLT<13> B_XWL<12> B_RWL<12> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL
+XCELL<27> A_RBLC<12> A_RBLC<11> A_RBLT<12> A_RBLT<11> A_XWL<11> A_RWL<11> 
++ B_RBLC<12> B_RBLC<11> B_RBLT<12> B_RBLT<11> B_XWL<11> B_RWL<11> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL
+XCELL<26> A_RBLC<10> A_RBLC<11> A_RBLT<10> A_RBLT<11> A_XWL<10> A_RWL<10> 
++ B_RBLC<10> B_RBLC<11> B_RBLT<10> B_RBLT<11> B_XWL<10> B_RWL<10> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL
+XCELL<25> A_RBLC<10> A_RBLC<9> A_RBLT<10> A_RBLT<9> A_XWL<9> A_RWL<9> 
++ B_RBLC<10> B_RBLC<9> B_RBLT<10> B_RBLT<9> B_XWL<9> B_RWL<9> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL
+XCELL<24> A_RBLC<8> A_RBLC<9> A_RBLT<8> A_RBLT<9> A_XWL<8> A_RWL<8> B_RBLC<8> 
++ B_RBLC<9> B_RBLT<8> B_RBLT<9> B_XWL<8> B_RWL<8> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL
+XCELL<23> A_RBLC<8> A_RBLC<7> A_RBLT<8> A_RBLT<7> A_XWL<7> A_RWL<7> B_RBLC<8> 
++ B_RBLC<7> B_RBLT<8> B_RBLT<7> B_XWL<7> B_RWL<7> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL
+XCELL<22> A_RBLC<6> A_RBLC<7> A_RBLT<6> A_RBLT<7> A_XWL<6> A_RWL<6> B_RBLC<6> 
++ B_RBLC<7> B_RBLT<6> B_RBLT<7> B_XWL<6> B_RWL<6> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL
+XCELL<21> A_RBLC<6> A_RBLC<5> A_RBLT<6> A_RBLT<5> A_XWL<5> A_RWL<5> B_RBLC<6> 
++ B_RBLC<5> B_RBLT<6> B_RBLT<5> B_XWL<5> B_RWL<5> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL
+XCELL<20> A_RBLC<4> A_RBLC<5> A_RBLT<4> A_RBLT<5> A_XWL<4> A_RWL<4> B_RBLC<4> 
++ B_RBLC<5> B_RBLT<4> B_RBLT<5> B_XWL<4> B_RWL<4> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL
+XCELL<19> A_RBLC<4> A_RBLC<3> A_RBLT<4> A_RBLT<3> A_XWL<3> A_RWL<3> B_RBLC<4> 
++ B_RBLC<3> B_RBLT<4> B_RBLT<3> B_XWL<3> B_RWL<3> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL
+XCELL<18> A_RBLC<2> A_RBLC<3> A_RBLT<2> A_RBLT<3> A_XWL<2> A_RWL<2> B_RBLC<2> 
++ B_RBLC<3> B_RBLT<2> B_RBLT<3> B_XWL<2> B_RWL<2> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL
+XCELL<17> A_RBLC<2> A_RBLC<1> A_RBLT<2> A_RBLT<1> A_XWL<1> A_RWL<1> B_RBLC<2> 
++ B_RBLC<1> B_RBLT<2> B_RBLT<1> B_XWL<1> B_RWL<1> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL
+XCELL<16> A_BLC_BOT<1> A_RBLC<1> A_BLT_BOT<1> A_RBLT<1> A_XWL<0> A_RWL<0> 
++ B_BLC_BOT<1> B_RBLC<1> B_BLT_BOT<1> B_RBLT<1> B_XWL<0> B_RWL<0> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL
+XCELL<15> A_BLC_TOP<0> A_LBLC<15> A_BLT_TOP<0> A_LBLT<15> A_LWL<15> A_XWL<15> 
++ B_BLC_TOP<0> B_LBLC<15> B_BLT_TOP<0> B_LBLT<15> B_LWL<15> B_XWL<15> 
++ VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL
+XCELL<14> A_LBLC<14> A_LBLC<15> A_LBLT<14> A_LBLT<15> A_LWL<14> A_XWL<14> 
++ B_LBLC<14> B_LBLC<15> B_LBLT<14> B_LBLT<15> B_LWL<14> B_XWL<14> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL
+XCELL<13> A_LBLC<14> A_LBLC<13> A_LBLT<14> A_LBLT<13> A_LWL<13> A_XWL<13> 
++ B_LBLC<14> B_LBLC<13> B_LBLT<14> B_LBLT<13> B_LWL<13> B_XWL<13> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL
+XCELL<12> A_LBLC<12> A_LBLC<13> A_LBLT<12> A_LBLT<13> A_LWL<12> A_XWL<12> 
++ B_LBLC<12> B_LBLC<13> B_LBLT<12> B_LBLT<13> B_LWL<12> B_XWL<12> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL
+XCELL<11> A_LBLC<12> A_LBLC<11> A_LBLT<12> A_LBLT<11> A_LWL<11> A_XWL<11> 
++ B_LBLC<12> B_LBLC<11> B_LBLT<12> B_LBLT<11> B_LWL<11> B_XWL<11> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL
+XCELL<10> A_LBLC<10> A_LBLC<11> A_LBLT<10> A_LBLT<11> A_LWL<10> A_XWL<10> 
++ B_LBLC<10> B_LBLC<11> B_LBLT<10> B_LBLT<11> B_LWL<10> B_XWL<10> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL
+XCELL<9> A_LBLC<10> A_LBLC<9> A_LBLT<10> A_LBLT<9> A_LWL<9> A_XWL<9> 
++ B_LBLC<10> B_LBLC<9> B_LBLT<10> B_LBLT<9> B_LWL<9> B_XWL<9> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL
+XCELL<8> A_LBLC<8> A_LBLC<9> A_LBLT<8> A_LBLT<9> A_LWL<8> A_XWL<8> B_LBLC<8> 
++ B_LBLC<9> B_LBLT<8> B_LBLT<9> B_LWL<8> B_XWL<8> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL
+XCELL<7> A_LBLC<8> A_LBLC<7> A_LBLT<8> A_LBLT<7> A_LWL<7> A_XWL<7> B_LBLC<8> 
++ B_LBLC<7> B_LBLT<8> B_LBLT<7> B_LWL<7> B_XWL<7> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL
+XCELL<6> A_LBLC<6> A_LBLC<7> A_LBLT<6> A_LBLT<7> A_LWL<6> A_XWL<6> B_LBLC<6> 
++ B_LBLC<7> B_LBLT<6> B_LBLT<7> B_LWL<6> B_XWL<6> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL
+XCELL<5> A_LBLC<6> A_LBLC<5> A_LBLT<6> A_LBLT<5> A_LWL<5> A_XWL<5> B_LBLC<6> 
++ B_LBLC<5> B_LBLT<6> B_LBLT<5> B_LWL<5> B_XWL<5> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL
+XCELL<4> A_LBLC<4> A_LBLC<5> A_LBLT<4> A_LBLT<5> A_LWL<4> A_XWL<4> B_LBLC<4> 
++ B_LBLC<5> B_LBLT<4> B_LBLT<5> B_LWL<4> B_XWL<4> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL
+XCELL<3> A_LBLC<4> A_LBLC<3> A_LBLT<4> A_LBLT<3> A_LWL<3> A_XWL<3> B_LBLC<4> 
++ B_LBLC<3> B_LBLT<4> B_LBLT<3> B_LWL<3> B_XWL<3> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL
+XCELL<2> A_LBLC<2> A_LBLC<3> A_LBLT<2> A_LBLT<3> A_LWL<2> A_XWL<2> B_LBLC<2> 
++ B_LBLC<3> B_LBLT<2> B_LBLT<3> B_LWL<2> B_XWL<2> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL
+XCELL<1> A_LBLC<2> A_LBLC<1> A_LBLT<2> A_LBLT<1> A_LWL<1> A_XWL<1> B_LBLC<2> 
++ B_LBLC<1> B_LBLT<2> B_LBLT<1> B_LWL<1> B_XWL<1> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL
+XCELL<0> A_BLC_BOT<0> A_LBLC<1> A_BLT_BOT<0> A_LBLT<1> A_LWL<0> A_XWL<0> 
++ B_BLC_BOT<0> B_LBLC<1> B_BLT_BOT<0> B_LBLT<1> B_LWL<0> B_XWL<0> VDD_CORE 
++ VSS VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_CELL
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_TB A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_BITKIT_16x2_EDGE_TB A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> 
++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS
+XEDGE<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_TB
+XEDGE<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_TB
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_BITKIT_TAP A_BLC A_BLT B_BLC B_BLT NW PW VDD VSS
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> 
++ B_BLC<1> B_BLC<0> B_BLT<1> B_BLT<0> VDD_CORE VSS
+XIEDGEBP_COL1<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_TB
+XIEDGEBP_COL1<0> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_TB
+XIEDGEBP_COL2<1> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_TB
+XIEDGEBP_COL2<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_EDGE_TB
+XITAP<1> A_BLC<1> A_BLT<1> B_BLC<1> B_BLT<1> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_TAP
+XITAP<0> A_BLC<0> A_BLT<0> B_BLC<0> B_BLT<0> VDD_CORE VSS 
++ VDD_CORE VSS / RM_IHPSG13_4096x8_c3_2P_BITKIT_TAP
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_BITKIT_TAP_LR NW PW VDD VSS
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_BITKIT_16x2_TAP_LR VDD_CORE VSS
+XCORNER<1> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_1P_BITKIT_CORNER
+XCORNER<0> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_1P_BITKIT_CORNER
+XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_1P_BITKIT_TAP_LR
+.ENDS
+
+.SUBCKT RSC_IHPSG13_CBUFX12 A Z VDD VSS
+MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=4.23u l=130.00n ng=6 nrd=0 nrs=0
+MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0
+MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0
+MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=3.24u l=130.00n ng=2 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> 
++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> 
++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> 
++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> 
++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O 
++ VDD VSS
+XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12
+XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12
+XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12
+XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+.SUBCKT RSC_IHPSG13_WLDRVX12 A Z VDD VSS
+MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0
+MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0
+MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=9.72u l=130.00n ng=6 nrd=0 nrs=0
+MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> 
++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> 
++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS
+XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_DEC04 ADDR<3> ADDR<2> ADDR<1> ADDR<0> CS ECLK_H_BOT 
++ ECLK_H_TOP ECLK_L_BOT ECLK_L_TOP WL<15> WL<14> WL<13> WL<12> WL<11> WL<10> 
++ WL<9> WL<8> WL<7> WL<6> WL<5> WL<4> WL<3> WL<2> WL<1> WL<0> VDD VSS
+XI0<3> PADR<1> PADR<0> sel01<3> VDD VSS / RSC_IHPSG13_NAND2X2
+XI0<2> PADR<1> NADR<0> sel01<2> VDD VSS / RSC_IHPSG13_NAND2X2
+XI0<1> NADR<1> PADR<0> sel01<1> VDD VSS / RSC_IHPSG13_NAND2X2
+XI0<0> NADR<1> NADR<0> sel01<0> VDD VSS / RSC_IHPSG13_NAND2X2
+XI4 ECLK_L_BOT EN VDD VSS / RSC_IHPSG13_CINVX4
+XI5 ECLK_H_BOT ECLK_L_BOT VDD VSS / RSC_IHPSG13_CINVX2
+XI3<3> PADR<3> NADR<3> VDD VSS / RSC_IHPSG13_INVX2
+XI3<2> PADR<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI3<1> PADR<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> PADR<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XR0 ECLK_H_BOT ECLK_H_TOP / RSC_IHPSG13_MET2RES
+XI11 ECLK_L_BOT ECLK_L_TOP / RSC_IHPSG13_MET2RES
+XI1<3> PADR<2> PADR<3> CS sel23<3> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<2> NADR<2> PADR<3> CS sel23<2> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<1> PADR<2> NADR<3> CS sel23<1> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<0> NADR<2> NADR<3> CS sel23<0> VDD VSS / RSC_IHPSG13_NAND3X2
+XI2<15> sel23<3> sel01<3> EN WL<15> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<14> sel23<3> sel01<2> EN WL<14> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<13> sel23<3> sel01<1> EN WL<13> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<12> sel23<3> sel01<0> EN WL<12> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<11> sel23<2> sel01<3> EN WL<11> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<10> sel23<2> sel01<2> EN WL<10> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<9> sel23<2> sel01<1> EN WL<9> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<8> sel23<2> sel01<0> EN WL<8> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<7> sel23<1> sel01<3> EN WL<7> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<6> sel23<1> sel01<2> EN WL<6> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<5> sel23<1> sel01<1> EN WL<5> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<4> sel23<1> sel01<0> EN WL<4> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<3> sel23<0> sel01<3> EN WL<3> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<2> sel23<0> sel01<2> EN WL<2> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<1> sel23<0> sel01<1> EN WL<1> VDD VSS / RSC_IHPSG13_NOR3X2
+XI2<0> sel23<0> sel01<0> EN WL<0> VDD VSS / RSC_IHPSG13_NOR3X2
+XCAPS4 VDD VSS / RSC_IHPSG13_FILLCAP4
+XLATCH<3> CS ADDR<3> PADR<3> VDD VSS / RSC_IHPSG13_LHPQX2
+XLATCH<2> CS ADDR<2> PADR<2> VDD VSS / RSC_IHPSG13_LHPQX2
+XLATCH<1> CS ADDR<1> PADR<1> VDD VSS / RSC_IHPSG13_LHPQX2
+XLATCH<0> CS ADDR<0> PADR<0> VDD VSS / RSC_IHPSG13_LHPQX2
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS
+XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2
+XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2
+XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4
+XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS
+XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2
+XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2
+XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4
+XI2<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI2<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS
+XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2
+XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2
+XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS
+XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2
+XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> 
++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I 
++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> 
++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> 
++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> 
++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> 
++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> 
++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> 
++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> 
++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> 
++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> 
++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> 
++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> 
++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> 
++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> 
++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> 
++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> 
++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> 
++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> 
++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> 
++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> 
++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> 
++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> 
++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> 
++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> 
++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> 
++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> 
++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> 
++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> 
++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> 
++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> 
++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> 
++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> 
++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> 
++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> 
++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> 
++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> 
++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> 
++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> 
++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> 
++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> 
++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> 
++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> 
++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> 
++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> 
++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> 
++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> 
++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> 
++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> 
++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> 
++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> 
++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> 
++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> 
++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> 
++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> 
++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> 
++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> 
++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> 
++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> 
++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> 
++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> 
++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> 
++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> 
++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> 
++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> 
++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS
+XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> 
++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> 
++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> 
++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> 
++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> 
++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> 
++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> 
++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> 
++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> 
++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> 
++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> 
++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> 
++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> 
++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> 
++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> 
++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> 
++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> 
++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> 
++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> 
++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> 
++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> 
++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> 
++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> 
++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> 
++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> 
++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> 
++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> 
++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> 
++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> 
++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> 
++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> 
++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> 
++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> 
++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> 
++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> 
++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> 
++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> 
++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> 
++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> 
++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> 
++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> 
++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> 
++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> 
++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> 
++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> 
++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> 
++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> 
++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> 
++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> 
++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> 
++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> 
++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> 
++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> 
++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> 
++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> 
++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> 
++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> 
++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> 
++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> 
++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> 
++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> 
++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> 
++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> 
++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> 
++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> 
++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> 
++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> 
++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> 
++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> 
++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> 
++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> 
++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> 
++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> 
++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> 
++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> 
++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> 
++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> 
++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> 
++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> 
++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> 
++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> 
++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> 
++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> 
++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> 
++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> 
++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> 
++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04
+XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC02
+XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC02
+XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC02
+XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC02
+XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC02
+XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC02
+XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC02
+XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC02
+XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC02
+XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC02
+XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC01
+XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC01
+XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC01
+XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC01
+XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC01
+XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC01
+XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC01
+XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC01
+XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC01
+XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC01
+XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC01
+XL2<258> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<257> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<256> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<255> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<254> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<253> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<252> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<251> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<250> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<249> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<248> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<247> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<246> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<245> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<244> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<243> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<242> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<241> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<240> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<239> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<238> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<237> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<236> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<235> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<234> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<233> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<232> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<231> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<230> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<229> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<228> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<227> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<226> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<225> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<224> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<223> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<222> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<221> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<220> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<219> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<218> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<217> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<216> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<215> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<214> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<213> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<212> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<211> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<210> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<209> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<208> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<207> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<206> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<205> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<204> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<203> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<202> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<201> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<200> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<199> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<198> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<197> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<196> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<195> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<194> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<193> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<192> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<191> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<190> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<189> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<188> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<187> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<186> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<185> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<184> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<183> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<182> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<181> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<180> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<179> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<178> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<177> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<176> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<175> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<174> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<173> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC00
+XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC00
+XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC00
+XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC00
+XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC00
+XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC00
+XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC00
+XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC00
+XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC00
+XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC00
+XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC00
+XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC03
+XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC03
+XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC03
+XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC03
+XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC03
+XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC03
+XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC03
+XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC03
+XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC03
+XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC03
+XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> 
++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> 
++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> 
++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> 
++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> 
++ BIST_EN_I VDD VSS
+XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+.ENDS
+
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_DLY_MUX A SEL Z VDD VSS
+XI11 net4 Z VDD VSS / RSC_IHPSG13_CINVX2
+XI8 A D<3> SEL net4 VDD VSS / RSC_IHPSG13_MX2IX1
+XI20<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1
+XI20<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1
+XI20<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_CTRL ACLK_N BIST_CK_I BIST_CS_I BIST_EN BIST_RE_I 
++ BIST_WE_I B_TIEL_O CK_I CS_I DCLK ECLK PULSE_H PULSE_L PULSE_O RCLK RE_I 
++ ROW_CS WCLK WE_I VDD VSS
+XI17 ck_regs we col_we VDD VSS / RSC_IHPSG13_DFNQX2
+XI16 ck_regs re col_re VDD VSS / RSC_IHPSG13_DFNQX2
+XI18 ck_regs cs net7 VDD VSS / RSC_IHPSG13_DFNQX2
+XI71 ACLK_N net012 PULSE_O VDD VSS / RSC_IHPSG13_DFNQX2
+XI77 col_we net017 net016 VDD VSS / RSC_IHPSG13_CNAND2X2
+XI76 col_re net017 net018 VDD VSS / RSC_IHPSG13_CNAND2X2
+XI15 ck_dly WEorREandCS aclk VDD VSS / RSC_IHPSG13_CGATEPX4
+XI14 ck WEandCS DCLK VDD VSS / RSC_IHPSG13_CGATEPX4
+XI60 net7 ROW_CS VDD VSS / RSC_IHPSG13_CBUFX8
+XI73 PULSE_O net012 VDD VSS / RSC_IHPSG13_CINVX2
+XI8 net017 net8 VDD VSS / RSC_IHPSG13_CINVX2
+XCAPS4<7> VDD VSS / RSC_IHPSG13_FILLCAP4
+XCAPS4<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XCAPS4<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XCAPS4<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XCAPS4<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XCAPS4<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XCAPS4<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XBM_TIEL B_TIEL_O VDD VSS / RSC_IHPSG13_TIEL
+XI64 ck ck_dly VDD VSS / RSC_IHPSG13_CDLYX2
+XI86 CS_I BIST_CS_I BIST_EN cs VDD VSS / RSC_IHPSG13_MX2X2
+XI87 CK_I BIST_CK_I BIST_EN ck VDD VSS / RSC_IHPSG13_MX2X2
+XI85 WE_I BIST_WE_I BIST_EN we VDD VSS / RSC_IHPSG13_MX2X2
+XI84 RE_I BIST_RE_I BIST_EN re VDD VSS / RSC_IHPSG13_MX2X2
+XI48 ck_dly ck_regs VDD VSS / RSC_IHPSG13_CINVX4
+XI81 net016 WCLK VDD VSS / RSC_IHPSG13_CINVX4
+XI80 net018 RCLK VDD VSS / RSC_IHPSG13_CINVX4
+XI78 net8 net020 VDD VSS / RSC_IHPSG13_CINVX4
+XCAPS8<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XCAPS8<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XCAPS8<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XCAPS8<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XCAPS8<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XCAPS8<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XCAPS8<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI6 PULSE_L PULSE_H net017 VDD VSS / RSC_IHPSG13_XOR2X2
+XI22 we cs WEandCS VDD VSS / RSC_IHPSG13_AND2X2
+XI79 net020 ECLK VDD VSS / RSC_IHPSG13_CINVX8
+XI63 aclk ACLK_N VDD VSS / RSC_IHPSG13_CINVX8
+XI21 re we cs WEorREandCS VDD VSS / RSC_IHPSG13_OA12X1
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> 
++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> 
++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> 
++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS
+XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2
+XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net13<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net13<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2
+XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2
+XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2
+XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2
+XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2
+XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2
+XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2
+XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2
+XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2
+XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2
+XI14<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI14<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI14<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI14<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI14<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_BLDRV A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL 
++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> 
++ A_SEL_P<1> A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> 
++ B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> 
++ B_SEL_P<2> B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS
+MA_CWN<3> A_BLC<3> A_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MA_CWN<2> A_BLC<2> A_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MA_CWN<1> A_BLC<1> A_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MA_CWN<0> A_BLC<0> A_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MA_TWN<3> A_BLT<3> A_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MA_TWN<2> A_BLT<2> A_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MA_TWN<1> A_BLT<1> A_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MA_TWN<0> A_BLT<0> A_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MB_TWN<3> B_BLT<3> B_BLT_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MB_TWN<2> B_BLT<2> B_BLT_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MB_TWN<1> B_BLT<1> B_BLT_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MB_TWN<0> B_BLT<0> B_BLT_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MB_CWN<3> B_BLC<3> B_BLC_NMOS_DRIVE<3> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MB_CWN<2> B_BLC<2> B_BLC_NMOS_DRIVE<2> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MB_CWN<1> B_BLC<1> B_BLC_NMOS_DRIVE<1> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MB_CWN<0> B_BLC<0> B_BLC_NMOS_DRIVE<0> VSS VSS sg13_lv_nmos m=1 
++ w=4.82u l=130.00n ng=2 nrd=0 nrs=0
+MA_CPR<3> A_BLC<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MA_CPR<2> A_BLC<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MA_CPR<1> A_BLC<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MA_CPR<0> A_BLC<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MA_TWP<3> A_BLT<3> A_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_TWP<2> A_BLT<2> A_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_TWP<1> A_BLT<1> A_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_TWP<0> A_BLT<0> A_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_CWP<3> A_BLC<3> A_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_CWP<2> A_BLC<2> A_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_CWP<1> A_BLC<1> A_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_CWP<0> A_BLC<0> A_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_TPR<3> A_BLT<3> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MA_TPR<2> A_BLT<2> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MA_TPR<1> A_BLT<1> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MA_TPR<0> A_BLT<0> A_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MA_TSP<3> A_BLT_SEL A_SEL_N<3> A_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_TSP<2> A_BLT_SEL A_SEL_N<2> A_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_TSP<1> A_BLT_SEL A_SEL_N<1> A_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_TSP<0> A_BLT_SEL A_SEL_N<0> A_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_CSP<3> A_BLC_SEL A_SEL_N<3> A_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_CSP<2> A_BLC_SEL A_SEL_N<2> A_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_CSP<1> A_BLC_SEL A_SEL_N<1> A_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MA_CSP<0> A_BLC_SEL A_SEL_N<0> A_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_CWP<3> B_BLC<3> B_BLC_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_CWP<2> B_BLC<2> B_BLC_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_CWP<1> B_BLC<1> B_BLC_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_CWP<0> B_BLC<0> B_BLC_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_TWP<3> B_BLT<3> B_BLT_PMOS_DRIVE<3> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_TWP<2> B_BLT<2> B_BLT_PMOS_DRIVE<2> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_TWP<1> B_BLT<1> B_BLT_PMOS_DRIVE<1> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_TWP<0> B_BLT<0> B_BLT_PMOS_DRIVE<0> VDD VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_TSP<3> B_BLT_SEL B_SEL_N<3> B_BLT<3> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_TSP<2> B_BLT_SEL B_SEL_N<2> B_BLT<2> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_TSP<1> B_BLT_SEL B_SEL_N<1> B_BLT<1> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_TSP<0> B_BLT_SEL B_SEL_N<0> B_BLT<0> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_TPR<3> B_BLT<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MB_TPR<2> B_BLT<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MB_TPR<1> B_BLT<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MB_TPR<0> B_BLT<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MB_CSP<3> B_BLC_SEL B_SEL_N<3> B_BLC<3> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_CSP<2> B_BLC_SEL B_SEL_N<2> B_BLC<2> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_CSP<1> B_BLC_SEL B_SEL_N<1> B_BLC<1> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_CSP<0> B_BLC_SEL B_SEL_N<0> B_BLC<0> VDD sg13_lv_pmos m=1 w=1.5u 
++ l=130.00n ng=1 nrd=0 nrs=0
+MB_CPR<3> B_BLC<3> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MB_CPR<2> B_BLC<2> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MB_CPR<1> B_BLC<1> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+MB_CPR<0> B_BLC<0> B_PRE_N VDD VDD sg13_lv_pmos m=1 w=3.000u l=130.00n 
++ ng=2 nrd=0 nrs=0
+XA_SEL<3> A_SEL_P<3> A_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2
+XA_SEL<2> A_SEL_P<2> A_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2
+XA_SEL<1> A_SEL_P<1> A_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2
+XA_SEL<0> A_SEL_P<0> A_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2
+XA_CINV<3> A_BLT_PMOS_DRIVE<3> A_BLC_NMOS_DRIVE<3> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XA_CINV<2> A_BLT_PMOS_DRIVE<2> A_BLC_NMOS_DRIVE<2> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XA_CINV<1> A_BLT_PMOS_DRIVE<1> A_BLC_NMOS_DRIVE<1> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XA_CINV<0> A_BLT_PMOS_DRIVE<0> A_BLC_NMOS_DRIVE<0> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XA_TINV<3> A_BLC_PMOS_DRIVE<3> A_BLT_NMOS_DRIVE<3> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XA_TINV<2> A_BLC_PMOS_DRIVE<2> A_BLT_NMOS_DRIVE<2> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XA_TINV<1> A_BLC_PMOS_DRIVE<1> A_BLT_NMOS_DRIVE<1> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XA_TINV<0> A_BLC_PMOS_DRIVE<0> A_BLT_NMOS_DRIVE<0> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XB_SEL<3> B_SEL_P<3> B_SEL_N<3> VDD VSS / RSC_IHPSG13_INVX2
+XB_SEL<2> B_SEL_P<2> B_SEL_N<2> VDD VSS / RSC_IHPSG13_INVX2
+XB_SEL<1> B_SEL_P<1> B_SEL_N<1> VDD VSS / RSC_IHPSG13_INVX2
+XB_SEL<0> B_SEL_P<0> B_SEL_N<0> VDD VSS / RSC_IHPSG13_INVX2
+XB_TINV<3> B_BLC_PMOS_DRIVE<3> B_BLT_NMOS_DRIVE<3> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XB_TINV<2> B_BLC_PMOS_DRIVE<2> B_BLT_NMOS_DRIVE<2> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XB_TINV<1> B_BLC_PMOS_DRIVE<1> B_BLT_NMOS_DRIVE<1> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XB_TINV<0> B_BLC_PMOS_DRIVE<0> B_BLT_NMOS_DRIVE<0> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XB_CINV<3> B_BLT_PMOS_DRIVE<3> B_BLC_NMOS_DRIVE<3> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XB_CINV<2> B_BLT_PMOS_DRIVE<2> B_BLC_NMOS_DRIVE<2> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XB_CINV<1> B_BLT_PMOS_DRIVE<1> B_BLC_NMOS_DRIVE<1> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XB_CINV<0> B_BLT_PMOS_DRIVE<0> B_BLC_NMOS_DRIVE<0> VDD VSS / 
++ RSC_IHPSG13_INVX2
+XA_TDEC<3> A_SEL_P<3> A_WR_ONE A_BLT_PMOS_DRIVE<3> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XA_TDEC<2> A_SEL_P<2> A_WR_ONE A_BLT_PMOS_DRIVE<2> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XA_TDEC<1> A_SEL_P<1> A_WR_ONE A_BLT_PMOS_DRIVE<1> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XA_TDEC<0> A_SEL_P<0> A_WR_ONE A_BLT_PMOS_DRIVE<0> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XA_CDEC<3> A_SEL_P<3> A_WR_ZERO A_BLC_PMOS_DRIVE<3> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XA_CDEC<2> A_SEL_P<2> A_WR_ZERO A_BLC_PMOS_DRIVE<2> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XA_CDEC<1> A_SEL_P<1> A_WR_ZERO A_BLC_PMOS_DRIVE<1> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XA_CDEC<0> A_SEL_P<0> A_WR_ZERO A_BLC_PMOS_DRIVE<0> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XB_CDEC<3> B_SEL_P<3> B_WR_ZERO B_BLC_PMOS_DRIVE<3> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XB_CDEC<2> B_SEL_P<2> B_WR_ZERO B_BLC_PMOS_DRIVE<2> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XB_CDEC<1> B_SEL_P<1> B_WR_ZERO B_BLC_PMOS_DRIVE<1> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XB_CDEC<0> B_SEL_P<0> B_WR_ZERO B_BLC_PMOS_DRIVE<0> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XB_TDEC<3> B_SEL_P<3> B_WR_ONE B_BLT_PMOS_DRIVE<3> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XB_TDEC<2> B_SEL_P<2> B_WR_ONE B_BLT_PMOS_DRIVE<2> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XB_TDEC<1> B_SEL_P<1> B_WR_ONE B_BLT_PMOS_DRIVE<1> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+XB_TDEC<0> B_SEL_P<0> B_WR_ONE B_BLT_PMOS_DRIVE<0> VDD VSS / 
++ RSC_IHPSG13_NAND2X2
+.ENDS
+.SUBCKT RSC_IHPSG13_AND2X6 A B Z VDD VSS
+MN3 Z net6 VSS VSS sg13_lv_nmos m=1 w=2.94u l=130.00n ng=3 nrd=0 nrs=0
+MN4 net9 B VSS VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0
+MN6 net6 A net9 VSS sg13_lv_nmos m=1 w=500.0n l=130.00n ng=1 nrd=0 nrs=0
+MP2 Z net6 VDD VDD sg13_lv_pmos m=1 w=4.86u l=130.00n ng=3 nrd=0 nrs=0
+MP0 net6 B VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+MP1 net6 A VDD VDD sg13_lv_pmos m=1 w=860.00n l=130.00n ng=1 nrd=0 
++ nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> 
++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> 
++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> 
++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> 
++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> 
++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> 
++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> 
++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> 
++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> 
++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> 
++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> 
++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R 
++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R 
++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL<1> B_ADDR_COL<0> 
++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> 
++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I 
++ B_BIST_EN_I B_BLC<31> B_BLC<30> B_BLC<29> B_BLC<28> B_BLC<27> B_BLC<26> 
++ B_BLC<25> B_BLC<24> B_BLC<23> B_BLC<22> B_BLC<21> B_BLC<20> B_BLC<19> 
++ B_BLC<18> B_BLC<17> B_BLC<16> B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> 
++ B_BLC<11> B_BLC<10> B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> 
++ B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> 
++ B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT<23> B_BLT<22> B_BLT<21> 
++ B_BLT<20> B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT<15> B_BLT<14> 
++ B_BLT<13> B_BLT<12> B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> 
++ B_BLT<5> B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L 
++ B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L 
++ B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS
+XB_I80<1> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<1> VDD VSS / 
++ RSC_IHPSG13_AND2X2
+XB_I80<0> B_WCLK_B_L B_RCLK_B_L B_W_nor_R<0> VDD VSS / 
++ RSC_IHPSG13_AND2X2
+XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / 
++ RSC_IHPSG13_AND2X2
+XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / 
++ RSC_IHPSG13_AND2X2
+XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XB_INV<6> B_N1<1> B_P1<1> VDD VSS / RSC_IHPSG13_CINVX4
+XB_INV<5> B_N0<1> B_P0<1> VDD VSS / RSC_IHPSG13_CINVX4
+XB_INV<4> B_N0<0> B_P0<0> VDD VSS / RSC_IHPSG13_CINVX4
+XB_INV<3> B_ADDR_COL<1> B_N1<1> VDD VSS / RSC_IHPSG13_CINVX4
+XB_INV<2> B_ADDR_COL<1> B_N1<0> VDD VSS / RSC_IHPSG13_CINVX4
+XB_INV<1> B_ADDR_COL<0> B_N0<1> VDD VSS / RSC_IHPSG13_CINVX4
+XB_INV<0> B_ADDR_COL<0> B_N0<0> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4
+XB_I81<3> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XB_I81<2> B_W_nor_R<1> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XB_I81<1> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XB_I81<0> B_W_nor_R<0> B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XI_FILL8<78> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<77> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<76> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<75> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<74> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<73> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<72> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<71> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<70> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<69> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<68> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<67> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<66> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<65> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<64> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<63> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<62> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<61> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<60> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<59> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<58> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<57> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<56> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<55> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<54> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<53> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<52> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<51> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<50> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<49> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<48> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<47> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<46> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<45> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<44> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<43> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<42> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<41> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<40> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<39> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<38> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<37> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<36> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<35> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<34> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<33> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<32> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<31> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<30> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XAB_BLMUX<7> A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC_SEL A_BLT<31> 
++ A_BLT<30> A_BLT<29> A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<31> A_SEL_P<30> 
++ A_SEL_P<29> A_SEL_P<28> A_WR_ONE A_WR_ZERO B_BLC<31> B_BLC<30> B_BLC<29> 
++ B_BLC<28> B_BLC_SEL B_BLT<31> B_BLT<30> B_BLT<29> B_BLT<28> B_BLT_SEL 
++ B_PRE_N B_SEL_P<31> B_SEL_P<30> B_SEL_P<29> B_SEL_P<28> B_WR_ONE B_WR_ZERO 
++ VDD VSS / RM_IHPSG13_4096x8_c3_2P_BLDRV
+XAB_BLMUX<6> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC_SEL A_BLT<27> 
++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<27> A_SEL_P<26> 
++ A_SEL_P<25> A_SEL_P<24> A_WR_ONE A_WR_ZERO B_BLC<27> B_BLC<26> B_BLC<25> 
++ B_BLC<24> B_BLC_SEL B_BLT<27> B_BLT<26> B_BLT<25> B_BLT<24> B_BLT_SEL 
++ B_PRE_N B_SEL_P<27> B_SEL_P<26> B_SEL_P<25> B_SEL_P<24> B_WR_ONE B_WR_ZERO 
++ VDD VSS / RM_IHPSG13_4096x8_c3_2P_BLDRV
+XAB_BLMUX<5> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC_SEL A_BLT<23> 
++ A_BLT<22> A_BLT<21> A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<23> A_SEL_P<22> 
++ A_SEL_P<21> A_SEL_P<20> A_WR_ONE A_WR_ZERO B_BLC<23> B_BLC<22> B_BLC<21> 
++ B_BLC<20> B_BLC_SEL B_BLT<23> B_BLT<22> B_BLT<21> B_BLT<20> B_BLT_SEL 
++ B_PRE_N B_SEL_P<23> B_SEL_P<22> B_SEL_P<21> B_SEL_P<20> B_WR_ONE B_WR_ZERO 
++ VDD VSS / RM_IHPSG13_4096x8_c3_2P_BLDRV
+XAB_BLMUX<4> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC_SEL A_BLT<19> 
++ A_BLT<18> A_BLT<17> A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<19> A_SEL_P<18> 
++ A_SEL_P<17> A_SEL_P<16> A_WR_ONE A_WR_ZERO B_BLC<19> B_BLC<18> B_BLC<17> 
++ B_BLC<16> B_BLC_SEL B_BLT<19> B_BLT<18> B_BLT<17> B_BLT<16> B_BLT_SEL 
++ B_PRE_N B_SEL_P<19> B_SEL_P<18> B_SEL_P<17> B_SEL_P<16> B_WR_ONE B_WR_ZERO 
++ VDD VSS / RM_IHPSG13_4096x8_c3_2P_BLDRV
+XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> 
++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> 
++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> 
++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL 
++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO 
++ VDD VSS / RM_IHPSG13_4096x8_c3_2P_BLDRV
+XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> 
++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> 
++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> 
++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N 
++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD 
++ VSS / RM_IHPSG13_4096x8_c3_2P_BLDRV
+XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> 
++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> 
++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL 
++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> 
++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_BLDRV
+XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> 
++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> 
++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL 
++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> 
++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_BLDRV
+XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8
+XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8
+XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8
+XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8
+XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8
+XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8
+XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6
+XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6
+XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6
+XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6
+XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<31> net041<0> B_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<30> net041<1> B_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<29> net041<2> B_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<28> net041<3> B_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<27> net041<4> B_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<26> net041<5> B_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<25> net041<6> B_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<24> net041<7> B_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<23> net041<8> B_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<22> net041<9> B_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<21> net041<10> B_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<20> net041<11> B_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<19> net041<12> B_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<18> net041<13> B_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<17> net041<14> B_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<16> net041<15> B_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<15> net041<16> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<14> net041<17> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<13> net041<18> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<12> net041<19> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<11> net041<20> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<10> net041<21> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<9> net041<22> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<8> net041<23> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<7> net041<24> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<6> net041<25> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<5> net041<26> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<4> net041<27> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<3> net041<28> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<2> net041<29> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<1> net041<30> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<0> net041<31> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2
+XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2
+XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net042 VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XB_DEC3<31> B_P1<1> B_P0<1> B_ADDR_DEC<7> net041<0> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<30> B_P1<1> B_P0<1> B_ADDR_DEC<6> net041<1> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<29> B_P1<1> B_P0<1> B_ADDR_DEC<5> net041<2> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<28> B_P1<1> B_P0<1> B_ADDR_DEC<4> net041<3> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<27> B_P1<1> B_P0<1> B_ADDR_DEC<3> net041<4> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<26> B_P1<1> B_P0<1> B_ADDR_DEC<2> net041<5> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<25> B_P1<1> B_P0<1> B_ADDR_DEC<1> net041<6> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<24> B_P1<1> B_P0<1> B_ADDR_DEC<0> net041<7> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<23> B_P1<1> B_N0<1> B_ADDR_DEC<7> net041<8> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<22> B_P1<1> B_N0<1> B_ADDR_DEC<6> net041<9> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<21> B_P1<1> B_N0<1> B_ADDR_DEC<5> net041<10> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<20> B_P1<1> B_N0<1> B_ADDR_DEC<4> net041<11> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<19> B_P1<1> B_N0<1> B_ADDR_DEC<3> net041<12> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<18> B_P1<1> B_N0<1> B_ADDR_DEC<2> net041<13> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<17> B_P1<1> B_N0<1> B_ADDR_DEC<1> net041<14> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<16> B_P1<1> B_N0<1> B_ADDR_DEC<0> net041<15> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<15> B_N1<0> B_P0<0> B_ADDR_DEC<7> net041<16> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<14> B_N1<0> B_P0<0> B_ADDR_DEC<6> net041<17> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<13> B_N1<0> B_P0<0> B_ADDR_DEC<5> net041<18> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<12> B_N1<0> B_P0<0> B_ADDR_DEC<4> net041<19> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<11> B_N1<0> B_P0<0> B_ADDR_DEC<3> net041<20> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<10> B_N1<0> B_P0<0> B_ADDR_DEC<2> net041<21> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<9> B_N1<0> B_P0<0> B_ADDR_DEC<1> net041<22> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<8> B_N1<0> B_P0<0> B_ADDR_DEC<0> net041<23> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<7> B_N1<0> B_N0<0> B_ADDR_DEC<7> net041<24> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<6> B_N1<0> B_N0<0> B_ADDR_DEC<6> net041<25> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<5> B_N1<0> B_N0<0> B_ADDR_DEC<5> net041<26> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<4> B_N1<0> B_N0<0> B_ADDR_DEC<4> net041<27> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<3> B_N1<0> B_N0<0> B_ADDR_DEC<3> net041<28> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<2> B_N1<0> B_N0<0> B_ADDR_DEC<2> net041<29> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<1> B_N1<0> B_N0<0> B_ADDR_DEC<1> net041<30> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_DEC3<0> B_N1<0> B_N0<0> B_ADDR_DEC<0> net041<31> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES
+XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES
+XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES
+XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES
+XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES
+XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES
+XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_COLDRV13_FILL4 VDD VSS
+XI0<11> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<10> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<9> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<8> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+
+
+.SUBCKT RSC_IHPSG13_CBUFX16 A Z VDD VSS
+MN0 net4 A VSS VSS sg13_lv_nmos m=1 w=2.115u l=130.00n ng=3 nrd=0 nrs=0
+MN1 Z net4 VSS VSS sg13_lv_nmos m=1 w=5.64u l=130.00n ng=8 nrd=0 nrs=0
+MP1 Z net4 VDD VDD sg13_lv_pmos m=1 w=13.000u l=130.00n ng=8 nrd=0 
++ nrs=0
+MP0 net4 A VDD VDD sg13_lv_pmos m=1 w=4.89u l=130.00n ng=3 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> 
++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> 
++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> 
++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> 
++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O 
++ VDD VSS
+XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8
+XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16
+XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16
+XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16
+.ENDS
+.SUBCKT RSC_IHPSG13_WLDRVX16 A Z VDD VSS
+MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0
+MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0
+MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=12.96u l=130.00n ng=8 nrd=0 nrs=0
+MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> 
++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> 
++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS
+XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_COLDRV13X4 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> 
++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> 
++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> 
++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> 
++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O 
++ VDD VSS
+XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX4
+XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX4
+XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX4
+XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX4
+XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI1 VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_WLDRV16X4 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> 
++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> 
++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS
+XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX4
+XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX4
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> 
++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> 
++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> 
++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> 
++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> 
++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> 
++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> 
++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> 
++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> 
++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> 
++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> 
++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> 
++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> 
++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> 
++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> 
++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> 
++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> 
++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> 
++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> 
++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> 
++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> 
++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> 
++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> 
++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> 
++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> 
++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> 
++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> 
++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> 
++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> 
++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> 
++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> 
++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> 
++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> 
++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> 
++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> 
++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> 
++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS
+XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC03
+XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC03
+XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC03
+XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC03
+XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC03
+XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> 
++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> 
++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> 
++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> 
++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> 
++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> 
++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> 
++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> 
++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> 
++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> 
++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> 
++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> 
++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> 
++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> 
++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> 
++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> 
++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> 
++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> 
++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> 
++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> 
++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> 
++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> 
++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> 
++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> 
++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> 
++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> 
++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> 
++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> 
++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> 
++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> 
++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> 
++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> 
++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> 
++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> 
++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> 
++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> 
++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> 
++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> 
++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04
+XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC02
+XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC02
+XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC02
+XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC02
+XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC02
+XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC00
+XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC00
+XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC00
+XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC00
+XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC00
+XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC01
+XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC01
+XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC01
+XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC01
+XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC01
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> 
++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> 
++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> 
++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> 
++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS
+XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI10 VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_COLDEC4 ACLK_N ADDR<3> ADDR<2> ADDR<1> ADDR<0> 
++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> 
++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<3> BIST_ADDR<2> 
++ BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS
+XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2
+XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int net12<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net12<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2
+XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2
+XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2
+XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2
+XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2
+XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2
+XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2
+XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2
+XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI14 addr_int ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2
+XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI15 ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_COLCTRL4 A_ADDR_COL A_ADDR_DEC<7> A_ADDR_DEC<6> 
++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> 
++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<15> A_BLC<14> 
++ A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> 
++ A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<15> A_BLT<14> 
++ A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> 
++ A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L 
++ A_DCLK_B_R A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L 
++ A_RCLK_R A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_COL 
++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> 
++ B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I 
++ B_BIST_EN_I B_BLC<15> B_BLC<14> B_BLC<13> B_BLC<12> B_BLC<11> B_BLC<10> 
++ B_BLC<9> B_BLC<8> B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC<3> B_BLC<2> 
++ B_BLC<1> B_BLC<0> B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT<11> 
++ B_BLT<10> B_BLT<9> B_BLT<8> B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT<3> 
++ B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R 
++ B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L 
++ B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS
+XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2
+XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2
+XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4
+XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4
+XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X4
+XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X4
+XI_FILL4<26> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<25> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<24> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<23> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<22> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<21> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<20> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<19> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<18> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<17> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<16> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<15> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<14> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<13> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<12> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<11> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4
+XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4
+XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4
+XB_INV<1> B_N0 B_P0 VDD VSS / RSC_IHPSG13_CINVX4
+XB_INV<0> B_ADDR_COL B_N0 VDD VSS / RSC_IHPSG13_CINVX4
+XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4
+XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4
+XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<1> A_N0 A_P0 VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<0> A_ADDR_COL A_N0 VDD VSS / RSC_IHPSG13_CINVX4
+XB_I81<1> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XB_I81<0> net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<1> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<0> net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES
+XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES
+XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES
+XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES
+XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES
+XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES
+XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES
+XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES
+XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XAB_BLMUX<3> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC_SEL A_BLT<15> 
++ A_BLT<14> A_BLT<13> A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<15> A_SEL_P<14> 
++ A_SEL_P<13> A_SEL_P<12> A_WR_ONE A_WR_ZERO B_BLC<15> B_BLC<14> B_BLC<13> 
++ B_BLC<12> B_BLC_SEL B_BLT<15> B_BLT<14> B_BLT<13> B_BLT<12> B_BLT_SEL 
++ B_PRE_N B_SEL_P<15> B_SEL_P<14> B_SEL_P<13> B_SEL_P<12> B_WR_ONE B_WR_ZERO 
++ VDD VSS / RM_IHPSG13_4096x8_c3_2P_BLDRV
+XAB_BLMUX<2> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC_SEL A_BLT<11> 
++ A_BLT<10> A_BLT<9> A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<11> A_SEL_P<10> 
++ A_SEL_P<9> A_SEL_P<8> A_WR_ONE A_WR_ZERO B_BLC<11> B_BLC<10> B_BLC<9> 
++ B_BLC<8> B_BLC_SEL B_BLT<11> B_BLT<10> B_BLT<9> B_BLT<8> B_BLT_SEL B_PRE_N 
++ B_SEL_P<11> B_SEL_P<10> B_SEL_P<9> B_SEL_P<8> B_WR_ONE B_WR_ZERO VDD 
++ VSS / RM_IHPSG13_4096x8_c3_2P_BLDRV
+XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> 
++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<7> A_SEL_P<6> A_SEL_P<5> 
++ A_SEL_P<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> B_BLC<4> B_BLC_SEL 
++ B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N B_SEL_P<7> B_SEL_P<6> 
++ B_SEL_P<5> B_SEL_P<4> B_WR_ONE B_WR_ZERO VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_BLDRV
+XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> 
++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<3> A_SEL_P<2> A_SEL_P<1> 
++ A_SEL_P<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLC_SEL 
++ B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N B_SEL_P<3> B_SEL_P<2> 
++ B_SEL_P<1> B_SEL_P<0> B_WR_ONE B_WR_ZERO VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_BLDRV
+XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net24 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_DEC3INV<15> net23<0> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<14> net23<1> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<13> net23<2> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<12> net23<3> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<11> net23<4> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<10> net23<5> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<9> net23<6> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<8> net23<7> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<7> net23<8> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<6> net23<9> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<5> net23<10> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<4> net23<11> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<3> net23<12> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<2> net23<13> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<1> net23<14> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<0> net23<15> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2
+XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<15> net044<0> B_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<14> net044<1> B_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<13> net044<2> B_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<12> net044<3> B_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<11> net044<4> B_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<10> net044<5> B_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<9> net044<6> B_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<8> net044<7> B_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<7> net044<8> B_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<6> net044<9> B_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<5> net044<10> B_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<4> net044<11> B_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<3> net044<12> B_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<2> net044<13> B_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<1> net044<14> B_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2
+XB_DEC3INV<0> net044<15> B_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2
+XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XI_FILL8<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XA_DEC3<15> A_P0 A_ADDR_DEC<7> net23<0> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<14> A_P0 A_ADDR_DEC<6> net23<1> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<13> A_P0 A_ADDR_DEC<5> net23<2> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<12> A_P0 A_ADDR_DEC<4> net23<3> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<11> A_P0 A_ADDR_DEC<3> net23<4> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<10> A_P0 A_ADDR_DEC<2> net23<5> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<9> A_P0 A_ADDR_DEC<1> net23<6> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<8> A_P0 A_ADDR_DEC<0> net23<7> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<7> A_N0 A_ADDR_DEC<7> net23<8> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<6> A_N0 A_ADDR_DEC<6> net23<9> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<5> A_N0 A_ADDR_DEC<5> net23<10> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<4> A_N0 A_ADDR_DEC<4> net23<11> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<3> A_N0 A_ADDR_DEC<3> net23<12> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<2> A_N0 A_ADDR_DEC<2> net23<13> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<1> A_N0 A_ADDR_DEC<1> net23<14> VDD VSS / RSC_IHPSG13_NAND2X2
+XA_DEC3<0> A_N0 A_ADDR_DEC<0> net23<15> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<15> B_P0 B_ADDR_DEC<7> net044<0> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<14> B_P0 B_ADDR_DEC<6> net044<1> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<13> B_P0 B_ADDR_DEC<5> net044<2> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<12> B_P0 B_ADDR_DEC<4> net044<3> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<11> B_P0 B_ADDR_DEC<3> net044<4> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<10> B_P0 B_ADDR_DEC<2> net044<5> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<9> B_P0 B_ADDR_DEC<1> net044<6> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<8> B_P0 B_ADDR_DEC<0> net044<7> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<7> B_N0 B_ADDR_DEC<7> net044<8> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<6> B_N0 B_ADDR_DEC<6> net044<9> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<5> B_N0 B_ADDR_DEC<5> net044<10> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<4> B_N0 B_ADDR_DEC<4> net044<11> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<3> B_N0 B_ADDR_DEC<3> net044<12> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<2> B_N0 B_ADDR_DEC<2> net044<13> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<1> B_N0 B_ADDR_DEC<1> net044<14> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_DEC3<0> B_N0 B_ADDR_DEC<0> net044<15> VDD VSS / RSC_IHPSG13_NAND2X2
+XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> 
++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS
+XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC00
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04
+XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC01
+XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> 
++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> 
++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> 
++ BIST_EN_I VDD VSS
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_COLDEC3 ACLK_N ADDR<2> ADDR<1> ADDR<0> ADDR_COL<1> 
++ ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> 
++ ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> 
++ BIST_EN_I VDD VSS
+XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2
+XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net13<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net13<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net13<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI15<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL
+XI15<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL
+XI13<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2
+XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2
+XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2
+XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2
+XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2
+XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2
+XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2
+XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2
+XI17<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+.SUBCKT RSC_IHPSG13_DFPQD_MSAFFX2P CP DN DP QN QP VDD VSS
+XI_AMP CP DN DP QN QP VDD VSS / RSC_IHPSG13_DFPQD_MSAFFX2
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_COLCTRL3 A_ADDR_DEC<7> A_ADDR_DEC<6> A_ADDR_DEC<5> 
++ A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> A_ADDR_DEC<0> 
++ A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> 
++ A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> 
++ A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R A_DCLK_L 
++ A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R A_TIEH_O 
++ A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<7> B_ADDR_DEC<6> 
++ B_ADDR_DEC<5> B_ADDR_DEC<4> B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> 
++ B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<7> B_BLC<6> B_BLC<5> 
++ B_BLC<4> B_BLC<3> B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<7> B_BLT<6> B_BLT<5> 
++ B_BLT<4> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I B_DCLK_B_L B_DCLK_B_R 
++ B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R B_RCLK_L B_RCLK_R 
++ B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD VSS
+XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net044 VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net043 VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XI_FILL8<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI_FILL8<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XB_I51 net037 B_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XB_I44 B_BM_N B_WCLK_B_L B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net037 net038 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2P
+XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2P
+XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XAB_BLMUX<1> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC_SEL A_BLT<7> A_BLT<6> 
++ A_BLT<5> A_BLT<4> A_BLT_SEL A_PRE_N A_ADDR_DEC<7> A_ADDR_DEC<6> 
++ A_ADDR_DEC<5> A_ADDR_DEC<4> A_WR_ONE A_WR_ZERO B_BLC<7> B_BLC<6> B_BLC<5> 
++ B_BLC<4> B_BLC_SEL B_BLT<7> B_BLT<6> B_BLT<5> B_BLT<4> B_BLT_SEL B_PRE_N 
++ B_ADDR_DEC<7> B_ADDR_DEC<6> B_ADDR_DEC<5> B_ADDR_DEC<4> B_WR_ONE B_WR_ZERO 
++ VDD VSS / RM_IHPSG13_4096x8_c3_2P_BLDRV
+XAB_BLMUX<0> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> 
++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> 
++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> 
++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N 
++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO 
++ VDD VSS / RM_IHPSG13_4096x8_c3_2P_BLDRV
+XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES
+XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES
+XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES
+XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES
+XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES
+XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES
+XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I80 B_WCLK_B_L B_RCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2
+XB_I76 B_DO_WRITE_P B_DI_N B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2
+XB_I75 B_DO_WRITE_P B_DI_R B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2
+XA_I80 A_WCLK_B_L A_RCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2
+XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2
+XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2
+XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XI_FILL4<10> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<9> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<8> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<7> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI_FILL4<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> 
++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> 
++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> 
++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> 
++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> 
++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> 
++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> 
++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> 
++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> 
++ WL_O<2> WL_O<1> WL_O<0> VDD VSS
+XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC02
+XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC00
+XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> 
++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> 
++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04
+XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC03
+XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC01
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> 
++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> 
++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> 
++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS
+XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_COLDRV13X16 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> 
++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> 
++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> 
++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> 
++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O 
++ VDD VSS
+XI0<7> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX16
+XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX16
+XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX16
+XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX16
+XI1<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI1<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_WLDRV16X16 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> 
++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> 
++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS
+XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX16
+XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX16
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_DEC01 ADDR<1> ADDR<0> CS CS_OUT VDD VSS
+XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4
+XDEC NADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2
+XI2 VDD VSS / RSC_IHPSG13_FILLCAP4
+XADDRINV ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_DEC00 ADDR<1> ADDR<0> CS CS_OUT VDD VSS
+XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4
+XDEC NADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2
+XADDRINV<1> ADDR<1> NADDR<1> VDD VSS / RSC_IHPSG13_INVX2
+XADDRINV<0> ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI1 VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_ROWDEC5 ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> 
++ ADDR_N_I<0> CS_I ECLK_I WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC01
+XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC00
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04
+XI0 ADDR_N_I<5> VDD VSS / RSC_IHPSG13_TIEL
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_ROWREG5 ACLK_N_I ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> 
++ ADDR_I<0> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> 
++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> 
++ BIST_EN_I VDD VSS
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_COLDEC5 ACLK_N ADDR<4> ADDR<3> ADDR<2> ADDR<1> ADDR<0> 
++ ADDR_COL<1> ADDR_COL<0> ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> 
++ ADDR_DEC<3> ADDR_DEC<2> ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<4> BIST_ADDR<3> 
++ BIST_ADDR<2> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS
+XI17<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI17<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI13<1> addr_int<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_CBUFX2
+XI13<0> addr_int<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_CBUFX2
+XDFF<4> BIST_EN_I BIST_ADDR<4> ACLK_N ADDR<4> addr_int<1> net7<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR<3> ACLK_N ADDR<3> addr_int<0> net7<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR<2> ACLK_N ADDR<2> padr_int<2> net7<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net7<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net7<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI1<7> PADR<0> PADR<1> PADR<2> addr_n<7> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<6> NADR<0> PADR<1> PADR<2> addr_n<6> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<5> PADR<0> NADR<1> PADR<2> addr_n<5> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<4> NADR<0> NADR<1> PADR<2> addr_n<4> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<3> PADR<0> PADR<1> NADR<2> addr_n<3> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<2> NADR<0> PADR<1> NADR<2> addr_n<2> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<1> PADR<0> NADR<1> NADR<2> addr_n<1> VDD VSS / RSC_IHPSG13_NAND3X2
+XI1<0> NADR<0> NADR<1> NADR<2> addr_n<0> VDD VSS / RSC_IHPSG13_NAND3X2
+XI15<2> NADR<2> PADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI15<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI15<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI3<2> padr_int<2> NADR<2> VDD VSS / RSC_IHPSG13_INVX2
+XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI2<7> addr_n<7> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_INVX2
+XI2<6> addr_n<6> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_INVX2
+XI2<5> addr_n<5> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_INVX2
+XI2<4> addr_n<4> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_INVX2
+XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2
+XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2
+XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2
+XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_COLCTRL5 A_ADDR_COL<1> A_ADDR_COL<0> A_ADDR_DEC<7> 
++ A_ADDR_DEC<6> A_ADDR_DEC<5> A_ADDR_DEC<4> A_ADDR_DEC<3> A_ADDR_DEC<2> 
++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<31> 
++ A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> 
++ A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> 
++ A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> 
++ A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> 
++ A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> 
++ A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> 
++ A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> 
++ A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> 
++ A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R 
++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R 
++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R VDD VSS
+XA_I80<1> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<1> VDD VSS / 
++ RSC_IHPSG13_AND2X2
+XA_I80<0> A_WCLK_B_L A_RCLK_B_L A_W_nor_R<0> VDD VSS / 
++ RSC_IHPSG13_AND2X2
+XA_I44 A_BM_N A_WCLK_B_L A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XI80<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI80<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_I74<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XA_INV<6> A_N1<1> A_P1<1> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<5> A_N0<1> A_P0<1> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<4> A_N0<0> A_P0<0> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<3> A_ADDR_COL<1> A_N1<1> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<2> A_ADDR_COL<1> A_N1<0> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<1> A_ADDR_COL<0> A_N0<1> VDD VSS / RSC_IHPSG13_CINVX4
+XA_INV<0> A_ADDR_COL<0> A_N0<0> VDD VSS / RSC_IHPSG13_CINVX4
+XA_I81<3> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<2> A_W_nor_R<1> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<1> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81<0> A_W_nor_R<0> A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_BLTMUX<31> A_BLC<31> A_BLC_SEL A_BLT<31> A_BLT_SEL A_PRE_N A_SEL_P<31> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<30> A_BLC<30> A_BLC_SEL A_BLT<30> A_BLT_SEL A_PRE_N A_SEL_P<30> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<29> A_BLC<29> A_BLC_SEL A_BLT<29> A_BLT_SEL A_PRE_N A_SEL_P<29> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<28> A_BLC<28> A_BLC_SEL A_BLT<28> A_BLT_SEL A_PRE_N A_SEL_P<28> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<27> A_BLC<27> A_BLC_SEL A_BLT<27> A_BLT_SEL A_PRE_N A_SEL_P<27> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<26> A_BLC<26> A_BLC_SEL A_BLT<26> A_BLT_SEL A_PRE_N A_SEL_P<26> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<25> A_BLC<25> A_BLC_SEL A_BLT<25> A_BLT_SEL A_PRE_N A_SEL_P<25> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<24> A_BLC<24> A_BLC_SEL A_BLT<24> A_BLT_SEL A_PRE_N A_SEL_P<24> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<23> A_BLC<23> A_BLC_SEL A_BLT<23> A_BLT_SEL A_PRE_N A_SEL_P<23> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<22> A_BLC<22> A_BLC_SEL A_BLT<22> A_BLT_SEL A_PRE_N A_SEL_P<22> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<21> A_BLC<21> A_BLC_SEL A_BLT<21> A_BLT_SEL A_PRE_N A_SEL_P<21> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<20> A_BLC<20> A_BLC_SEL A_BLT<20> A_BLT_SEL A_PRE_N A_SEL_P<20> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<19> A_BLC<19> A_BLC_SEL A_BLT<19> A_BLT_SEL A_PRE_N A_SEL_P<19> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<18> A_BLC<18> A_BLC_SEL A_BLT<18> A_BLT_SEL A_PRE_N A_SEL_P<18> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<17> A_BLC<17> A_BLC_SEL A_BLT<17> A_BLT_SEL A_PRE_N A_SEL_P<17> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<16> A_BLC<16> A_BLC_SEL A_BLT<16> A_BLT_SEL A_PRE_N A_SEL_P<16> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<15> A_BLC<15> A_BLC_SEL A_BLT<15> A_BLT_SEL A_PRE_N A_SEL_P<15> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<14> A_BLC<14> A_BLC_SEL A_BLT<14> A_BLT_SEL A_PRE_N A_SEL_P<14> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<13> A_BLC<13> A_BLC_SEL A_BLT<13> A_BLT_SEL A_PRE_N A_SEL_P<13> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<12> A_BLC<12> A_BLC_SEL A_BLT<12> A_BLT_SEL A_PRE_N A_SEL_P<12> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<11> A_BLC<11> A_BLC_SEL A_BLT<11> A_BLT_SEL A_PRE_N A_SEL_P<11> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<10> A_BLC<10> A_BLC_SEL A_BLT<10> A_BLT_SEL A_PRE_N A_SEL_P<10> 
++ A_WR_ONE A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<9> A_BLC<9> A_BLC_SEL A_BLT<9> A_BLT_SEL A_PRE_N A_SEL_P<9> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<8> A_BLC<8> A_BLC_SEL A_BLT<8> A_BLT_SEL A_PRE_N A_SEL_P<8> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<7> A_BLC<7> A_BLC_SEL A_BLT<7> A_BLT_SEL A_PRE_N A_SEL_P<7> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<6> A_BLC<6> A_BLC_SEL A_BLT<6> A_BLT_SEL A_PRE_N A_SEL_P<6> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<5> A_BLC<5> A_BLC_SEL A_BLT<5> A_BLT_SEL A_PRE_N A_SEL_P<5> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<4> A_BLC<4> A_BLC_SEL A_BLT<4> A_BLT_SEL A_PRE_N A_SEL_P<4> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<3> A_BLC<3> A_BLC_SEL A_BLT<3> A_BLT_SEL A_PRE_N A_SEL_P<3> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<2> A_BLC<2> A_BLC_SEL A_BLT<2> A_BLT_SEL A_PRE_N A_SEL_P<2> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<1> A_BLC<1> A_BLC_SEL A_BLT<1> A_BLT_SEL A_PRE_N A_SEL_P<1> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_BLTMUX<0> A_BLC<0> A_BLC_SEL A_BLT<0> A_BLT_SEL A_PRE_N A_SEL_P<0> A_WR_ONE 
++ A_WR_ZERO VDD VSS / RM_IHPSG13_4096x8_c3_1P_BLDRV
+XA_CAPS<17> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<16> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<15> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<14> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<13> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<12> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<11> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<10> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<9> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<8> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<7> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<6> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8
+XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8
+XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX8
+XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X6
+XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X6
+XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<31> net23<0> A_SEL_P<31> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<30> net23<1> A_SEL_P<30> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<29> net23<2> A_SEL_P<29> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<28> net23<3> A_SEL_P<28> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<27> net23<4> A_SEL_P<27> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<26> net23<5> A_SEL_P<26> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<25> net23<6> A_SEL_P<25> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<24> net23<7> A_SEL_P<24> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<23> net23<8> A_SEL_P<23> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<22> net23<9> A_SEL_P<22> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<21> net23<10> A_SEL_P<21> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<20> net23<11> A_SEL_P<20> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<19> net23<12> A_SEL_P<19> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<18> net23<13> A_SEL_P<18> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<17> net23<14> A_SEL_P<17> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<16> net23<15> A_SEL_P<16> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<15> net23<16> A_SEL_P<15> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<14> net23<17> A_SEL_P<14> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<13> net23<18> A_SEL_P<13> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<12> net23<19> A_SEL_P<12> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<11> net23<20> A_SEL_P<11> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<10> net23<21> A_SEL_P<10> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<9> net23<22> A_SEL_P<9> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<8> net23<23> A_SEL_P<8> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<7> net23<24> A_SEL_P<7> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<6> net23<25> A_SEL_P<6> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<5> net23<26> A_SEL_P<5> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<4> net23<27> A_SEL_P<4> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<3> net23<28> A_SEL_P<3> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<2> net23<29> A_SEL_P<2> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<1> net23<30> A_SEL_P<1> VDD VSS / RSC_IHPSG13_INVX2
+XA_DEC3INV<0> net23<31> A_SEL_P<0> VDD VSS / RSC_IHPSG13_INVX2
+XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net21 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_DEC3<31> A_P1<1> A_P0<1> A_ADDR_DEC<7> net23<0> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<30> A_P1<1> A_P0<1> A_ADDR_DEC<6> net23<1> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<29> A_P1<1> A_P0<1> A_ADDR_DEC<5> net23<2> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<28> A_P1<1> A_P0<1> A_ADDR_DEC<4> net23<3> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<27> A_P1<1> A_P0<1> A_ADDR_DEC<3> net23<4> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<26> A_P1<1> A_P0<1> A_ADDR_DEC<2> net23<5> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<25> A_P1<1> A_P0<1> A_ADDR_DEC<1> net23<6> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<24> A_P1<1> A_P0<1> A_ADDR_DEC<0> net23<7> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<23> A_P1<1> A_N0<1> A_ADDR_DEC<7> net23<8> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<22> A_P1<1> A_N0<1> A_ADDR_DEC<6> net23<9> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<21> A_P1<1> A_N0<1> A_ADDR_DEC<5> net23<10> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<20> A_P1<1> A_N0<1> A_ADDR_DEC<4> net23<11> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<19> A_P1<1> A_N0<1> A_ADDR_DEC<3> net23<12> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<18> A_P1<1> A_N0<1> A_ADDR_DEC<2> net23<13> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<17> A_P1<1> A_N0<1> A_ADDR_DEC<1> net23<14> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<16> A_P1<1> A_N0<1> A_ADDR_DEC<0> net23<15> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<15> A_N1<0> A_P0<0> A_ADDR_DEC<7> net23<16> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<14> A_N1<0> A_P0<0> A_ADDR_DEC<6> net23<17> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<13> A_N1<0> A_P0<0> A_ADDR_DEC<5> net23<18> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<12> A_N1<0> A_P0<0> A_ADDR_DEC<4> net23<19> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<11> A_N1<0> A_P0<0> A_ADDR_DEC<3> net23<20> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<10> A_N1<0> A_P0<0> A_ADDR_DEC<2> net23<21> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<9> A_N1<0> A_P0<0> A_ADDR_DEC<1> net23<22> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<8> A_N1<0> A_P0<0> A_ADDR_DEC<0> net23<23> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<7> A_N1<0> A_N0<0> A_ADDR_DEC<7> net23<24> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<6> A_N1<0> A_N0<0> A_ADDR_DEC<6> net23<25> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<5> A_N1<0> A_N0<0> A_ADDR_DEC<5> net23<26> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<4> A_N1<0> A_N0<0> A_ADDR_DEC<4> net23<27> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<3> A_N1<0> A_N0<0> A_ADDR_DEC<3> net23<28> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<2> A_N1<0> A_N0<0> A_ADDR_DEC<2> net23<29> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<1> A_N1<0> A_N0<0> A_ADDR_DEC<1> net23<30> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_DEC3<0> A_N1<0> A_N0<0> A_ADDR_DEC<0> net23<31> VDD VSS / 
++ RSC_IHPSG13_NAND3X2
+XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES
+XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES
+XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES
+XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+.ENDS
+
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_COLDRV13X12 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> 
++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> 
++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> 
++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> 
++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O 
++ VDD VSS
+XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI1<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP8
+XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX12
+XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX12
+XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX12
+XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX12
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_WLDRV16X12 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> 
++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> 
++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS
+XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX12
+XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX12
+.ENDS
+
+
+
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> 
++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> 
++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> 
++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> 
++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O 
++ VDD VSS
+XI0<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8
+XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8
+XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8
+XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XI1<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI1<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI1<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+.SUBCKT RSC_IHPSG13_WLDRVX8 A Z VDD VSS
+MN1 Z net6 VSS VSS sg13_lv_nmos m=1 w=1.41u l=130.00n ng=2 nrd=0 nrs=0
+MN0 net6 A VSS VSS sg13_lv_nmos m=1 w=1.8u l=130.00n ng=2 nrd=0 nrs=0
+MP1 Z net6 VDD VDD sg13_lv_pmos m=1 w=6.48u l=130.00n ng=4 nrd=0 nrs=0
+MP0 net6 A VDD VDD sg13_lv_pmos m=1 w=900.0n l=130.00n ng=1 nrd=0 nrs=0
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> 
++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> 
++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS
+XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8
+.ENDS
+
+
+
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_COLDEC2 ACLK_N ADDR<1> ADDR<0> ADDR_COL<1> ADDR_COL<0> 
++ ADDR_DEC<7> ADDR_DEC<6> ADDR_DEC<5> ADDR_DEC<4> ADDR_DEC<3> ADDR_DEC<2> 
++ ADDR_DEC<1> ADDR_DEC<0> BIST_ADDR<1> BIST_ADDR<0> BIST_EN_I VDD VSS
+XI16<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI16<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI18<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI1<3> PADR<0> PADR<1> addr_n<3> VDD VSS / RSC_IHPSG13_NAND2X2
+XI1<2> NADR<0> PADR<1> addr_n<2> VDD VSS / RSC_IHPSG13_NAND2X2
+XI1<1> PADR<0> NADR<1> addr_n<1> VDD VSS / RSC_IHPSG13_NAND2X2
+XI1<0> NADR<0> NADR<1> addr_n<0> VDD VSS / RSC_IHPSG13_NAND2X2
+XI17<1> ADDR_COL<1> VDD VSS / RSC_IHPSG13_TIEL
+XI17<0> ADDR_COL<0> VDD VSS / RSC_IHPSG13_TIEL
+XI14<3> ADDR_DEC<7> VDD VSS / RSC_IHPSG13_TIEL
+XI14<2> ADDR_DEC<6> VDD VSS / RSC_IHPSG13_TIEL
+XI14<1> ADDR_DEC<5> VDD VSS / RSC_IHPSG13_TIEL
+XI14<0> ADDR_DEC<4> VDD VSS / RSC_IHPSG13_TIEL
+XI13<1> NADR<1> PADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI13<0> NADR<0> PADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI3<1> padr_int<1> NADR<1> VDD VSS / RSC_IHPSG13_INVX2
+XI3<0> padr_int<0> NADR<0> VDD VSS / RSC_IHPSG13_INVX2
+XI2<3> addr_n<3> ADDR_DEC<3> VDD VSS / RSC_IHPSG13_INVX2
+XI2<2> addr_n<2> ADDR_DEC<2> VDD VSS / RSC_IHPSG13_INVX2
+XI2<1> addr_n<1> ADDR_DEC<1> VDD VSS / RSC_IHPSG13_INVX2
+XI2<0> addr_n<0> ADDR_DEC<0> VDD VSS / RSC_IHPSG13_INVX2
+XDFF<1> BIST_EN_I BIST_ADDR<1> ACLK_N ADDR<1> padr_int<1> net12<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR<0> ACLK_N ADDR<0> padr_int<0> net12<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI15<5> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI15<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI15<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI15<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI15<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI19<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI19<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI19<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI19<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_COLCTRL2 A_ADDR_DEC<3> A_ADDR_DEC<2> A_ADDR_DEC<1> 
++ A_ADDR_DEC<0> A_BIST_BM_I A_BIST_DW_I A_BIST_EN_I A_BLC<3> A_BLC<2> A_BLC<1> 
++ A_BLC<0> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_BM_I A_DCLK_B_L A_DCLK_B_R 
++ A_DCLK_L A_DCLK_R A_DR_O A_DW_I A_RCLK_B_L A_RCLK_B_R A_RCLK_L A_RCLK_R 
++ A_TIEH_O A_WCLK_B_L A_WCLK_B_R A_WCLK_L A_WCLK_R B_ADDR_DEC<3> B_ADDR_DEC<2> 
++ B_ADDR_DEC<1> B_ADDR_DEC<0> B_BIST_BM_I B_BIST_DW_I B_BIST_EN_I B_BLC<3> 
++ B_BLC<2> B_BLC<1> B_BLC<0> B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BM_I 
++ B_DCLK_B_L B_DCLK_B_R B_DCLK_L B_DCLK_R B_DR_O B_DW_I B_RCLK_B_L B_RCLK_B_R 
++ B_RCLK_L B_RCLK_R B_TIEH_O B_WCLK_B_L B_WCLK_B_R B_WCLK_L B_WCLK_R VDD 
++ VSS
+XB_DREG B_BIST_EN_I B_BIST_DW_I B_DCLK_B_L B_DW_I B_DI_R net046 VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XB_BREG B_BIST_EN_I B_BIST_BM_I B_DCLK_B_L B_BM_I B_BM_R net045 VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XA_DREG A_BIST_EN_I A_BIST_DW_I A_DCLK_B_L A_DW_I A_DI_R net22 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XA_BREG A_BIST_EN_I A_BIST_BM_I A_DCLK_B_L A_BM_I A_BM_R net23 VDD VSS 
++ / RSC_IHPSG13_DFNQMX2IX1
+XB_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4
+XA_CAPS VDD VSS / RSC_IHPSG13_FILLCAP4
+XB_I75 B_DI_R B_DO_WRITE_P B_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2
+XB_I80 B_RCLK_B_L B_WCLK_B_L net041 VDD VSS / RSC_IHPSG13_AND2X2
+XB_I76 B_DI_N B_DO_WRITE_P B_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2
+XA_I80 A_RCLK_B_L A_WCLK_B_L net21 VDD VSS / RSC_IHPSG13_AND2X2
+XA_I75 A_DI_R A_DO_WRITE_P A_WR_ONE VDD VSS / RSC_IHPSG13_AND2X2
+XA_I76 A_DI_N A_DO_WRITE_P A_WR_ZERO VDD VSS / RSC_IHPSG13_AND2X2
+XB_I44 B_WCLK_B_L B_BM_N B_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XA_I44 A_WCLK_B_L A_BM_N A_DO_WRITE_P VDD VSS / RSC_IHPSG13_NOR2X2
+XB_I81 net041 B_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XA_I81 net21 A_PRE_N VDD VSS / RSC_IHPSG13_CINVX4_WN
+XB_BM_TIEH B_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+XA_BM_TIEH A_TIEH_O VDD VSS / RSC_IHPSG13_TIEH
+XA_I89 A_DCLK_B_L A_DCLK_B_R / RSC_IHPSG13_MET3RES
+XA_I88 A_DCLK_L A_DCLK_R / RSC_IHPSG13_MET3RES
+XA_I87 A_WCLK_L A_WCLK_R / RSC_IHPSG13_MET3RES
+XA_I91 A_RCLK_B_L A_RCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I87 B_WCLK_L B_WCLK_R / RSC_IHPSG13_MET3RES
+XB_I88 B_DCLK_L B_DCLK_R / RSC_IHPSG13_MET3RES
+XB_I89 B_DCLK_B_L B_DCLK_B_R / RSC_IHPSG13_MET3RES
+XB_I90 B_WCLK_B_L B_WCLK_B_R / RSC_IHPSG13_MET3RES
+XB_R2 B_RCLK_L B_RCLK_R / RSC_IHPSG13_MET3RES
+XB_I91 B_RCLK_B_L B_RCLK_B_R / RSC_IHPSG13_MET3RES
+XA_R2 A_RCLK_L A_RCLK_R / RSC_IHPSG13_MET3RES
+XA_I90 A_WCLK_B_L A_WCLK_B_R / RSC_IHPSG13_MET3RES
+XAB_BLMUX A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLC_SEL A_BLT<3> A_BLT<2> 
++ A_BLT<1> A_BLT<0> A_BLT_SEL A_PRE_N A_ADDR_DEC<3> A_ADDR_DEC<2> 
++ A_ADDR_DEC<1> A_ADDR_DEC<0> A_WR_ONE A_WR_ZERO B_BLC<3> B_BLC<2> B_BLC<1> 
++ B_BLC<0> B_BLC_SEL B_BLT<3> B_BLT<2> B_BLT<1> B_BLT<0> B_BLT_SEL B_PRE_N 
++ B_ADDR_DEC<3> B_ADDR_DEC<2> B_ADDR_DEC<1> B_ADDR_DEC<0> B_WR_ONE B_WR_ZERO 
++ VDD VSS / RM_IHPSG13_4096x8_c3_2P_BLDRV
+XB_ISENSE B_SAE B_BLC_SEL B_BLT_SEL net039 net040 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XA_ISENSE A_SAE A_BLC_SEL A_BLT_SEL net19 net20 VDD VSS / 
++ RSC_IHPSG13_DFPQD_MSAFFX2
+XB_I78 B_RCLK_B_L B_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XA_I78 A_RCLK_B_L A_SAE VDD VSS / RSC_IHPSG13_CBUFX2
+XB_I83 B_BM_R B_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XB_I49 B_DI_R B_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I83 A_BM_R A_BM_N VDD VSS / RSC_IHPSG13_INVX2
+XA_I49 A_DI_R A_DI_N VDD VSS / RSC_IHPSG13_INVX2
+XB_I51 net039 B_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XA_I51 net19 A_DR_O VDD VSS / RSC_IHPSG13_INVX4
+XA_I69 A_DCLK_L A_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XA_I50 A_WCLK_L A_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XA_EBUF A_RCLK_L A_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XB_EBUF B_RCLK_L B_RCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XB_I50 B_WCLK_L B_WCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+XB_I69 B_DCLK_L B_DCLK_B_L VDD VSS / RSC_IHPSG13_CINVX2
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_COLDRV13_FILL4C2 VDD VSS
+XI0<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> 
++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> 
++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> 
++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> 
++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> 
++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> 
++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> 
++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> 
++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> 
++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> 
++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> 
++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> 
++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> 
++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> 
++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> 
++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> 
++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> 
++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> 
++ VDD VSS
+XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> 
++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> 
++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> 
++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> 
++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> 
++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> 
++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> 
++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> 
++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> 
++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> 
++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> 
++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> 
++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> 
++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> 
++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04
+XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC03
+XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC03
+XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC01
+XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC01
+XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC01
+XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC02
+XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC02
+XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC00
+XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC00
+XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_2P_DEC00
+XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> 
++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> 
++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> 
++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> 
++ BIST_ADDR_I<0> BIST_EN_I VDD VSS
+XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<0> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_ROWDEC4 ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> 
++ CS_I ECLK_I WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> 
++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> 
++ VDD VSS
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XSEL ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I ECLK_H<1> 
++ ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> 
++ WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> 
++ WL_O<0> VDD VSS / RM_IHPSG13_4096x8_c3_2P_DEC04
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_2P_ROWREG4 ACLK_N_I ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> 
++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<3> 
++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net7<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net7<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net7<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net7<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI12<4> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<3> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<2> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI12<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_BITKIT_TAP BLC BLT NW PW VDD VSS
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_TAP A_BLC<1> A_BLC<0> A_BLT<1> A_BLT<0> 
++ VDD_CORE VSS
+XITAP<1> A_BLC<1> A_BLT<1> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_4096x8_c3_1P_BITKIT_TAP
+XITAP<0> A_BLC<0> A_BLT<0> VDD_CORE VSS VDD_CORE VSS 
++ / RM_IHPSG13_4096x8_c3_1P_BITKIT_TAP
+XIEDGEBP_COL1<1> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE 
++ VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_TB
+XIEDGEBP_COL1<0> BLC<1> BLT<1> VDD_CORE VSS VDD_CORE 
++ VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_TB
+XIEDGEBP_COL2<1> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE 
++ VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_TB
+XIEDGEBP_COL2<0> BLC<0> BLT<0> VDD_CORE VSS VDD_CORE 
++ VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_EDGE_TB
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_TAP_LR VDD_CORE VSS
+XCORNER<1> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_1P_BITKIT_CORNER
+XCORNER<0> VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_1P_BITKIT_CORNER
+XTAP_BORDER VDD_CORE VSS VDD_CORE VSS / 
++ RM_IHPSG13_4096x8_c3_1P_BITKIT_TAP_LR
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_DEC03 ADDR<1> ADDR<0> CS CS_OUT VDD VSS
+XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4
+XI0 VDD VSS / RSC_IHPSG13_FILLCAP4
+XDEC ADDR<1> ADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_DEC02 ADDR<1> ADDR<0> CS CS_OUT VDD VSS
+XDECINV net1 CS_OUT VDD VSS / RSC_IHPSG13_INVX4
+XDEC ADDR<1> NADDR<0> CS net1 VDD VSS / RSC_IHPSG13_NAND3X2
+XI2 VDD VSS / RSC_IHPSG13_FILLCAP4
+XADDRINV ADDR<0> NADDR<0> VDD VSS / RSC_IHPSG13_INVX2
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_ROWDEC8 ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> 
++ ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<255> 
++ WL_O<254> WL_O<253> WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> 
++ WL_O<247> WL_O<246> WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> 
++ WL_O<240> WL_O<239> WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> 
++ WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> 
++ WL_O<226> WL_O<225> WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> 
++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> 
++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> 
++ WL_O<205> WL_O<204> WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> 
++ WL_O<198> WL_O<197> WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> 
++ WL_O<191> WL_O<190> WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> 
++ WL_O<184> WL_O<183> WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> 
++ WL_O<177> WL_O<176> WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> 
++ WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> 
++ WL_O<163> WL_O<162> WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> 
++ WL_O<156> WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> 
++ WL_O<149> WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> 
++ WL_O<142> WL_O<141> WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> 
++ WL_O<135> WL_O<134> WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> 
++ WL_O<128> WL_O<127> WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> 
++ WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> 
++ WL_O<114> WL_O<113> WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> 
++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> 
++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> 
++ WL_O<92> WL_O<91> WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> 
++ WL_O<84> WL_O<83> WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> 
++ WL_O<76> WL_O<75> WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> 
++ WL_O<68> WL_O<67> WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> 
++ WL_O<60> WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> 
++ WL_O<52> WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> 
++ WL_O<44> WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> 
++ WL_O<36> WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> 
++ WL_O<28> WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> 
++ WL_O<20> WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> 
++ WL_O<12> WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> 
++ WL_O<3> WL_O<2> WL_O<1> WL_O<0> VDD VSS
+XDEC11<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<3> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC03
+XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<15> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC03
+XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<11> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC03
+XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC03
+XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC03
+XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XDEC10<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<2> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC02
+XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<14> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC02
+XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<10> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC02
+XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC02
+XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC02
+XDEC00<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC00
+XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<12> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC00
+XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<8> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC00
+XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC00
+XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC00
+XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> 
++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> 
++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> 
++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> 
++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> 
++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> 
++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> 
++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> 
++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> 
++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> 
++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> 
++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> 
++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> 
++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> 
++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> 
++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> 
++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> 
++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> 
++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> 
++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> 
++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> 
++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> 
++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> 
++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> 
++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> 
++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> 
++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> 
++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> 
++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> 
++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> 
++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> 
++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> 
++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> 
++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> 
++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> 
++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> 
++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> 
++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> 
++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04
+XDEC01<4> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC01
+XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS04<3> CS00<13> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC01
+XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS04<2> CS00<9> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC01
+XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC01
+XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC01
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_ROWREG8 ACLK_N_I ADDR_I<7> ADDR_I<6> ADDR_I<5> ADDR_I<4> 
++ ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<7> ADDR_N_O<6> ADDR_N_O<5> 
++ ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<7> 
++ BIST_ADDR_I<6> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> 
++ BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS
+XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net2<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<5> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<6> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<7> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_ROWDEC9 ADDR_N_I<8> ADDR_N_I<7> ADDR_N_I<6> ADDR_N_I<5> 
++ ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I 
++ WL_O<511> WL_O<510> WL_O<509> WL_O<508> WL_O<507> WL_O<506> WL_O<505> 
++ WL_O<504> WL_O<503> WL_O<502> WL_O<501> WL_O<500> WL_O<499> WL_O<498> 
++ WL_O<497> WL_O<496> WL_O<495> WL_O<494> WL_O<493> WL_O<492> WL_O<491> 
++ WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> WL_O<484> 
++ WL_O<483> WL_O<482> WL_O<481> WL_O<480> WL_O<479> WL_O<478> WL_O<477> 
++ WL_O<476> WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> 
++ WL_O<469> WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> WL_O<463> 
++ WL_O<462> WL_O<461> WL_O<460> WL_O<459> WL_O<458> WL_O<457> WL_O<456> 
++ WL_O<455> WL_O<454> WL_O<453> WL_O<452> WL_O<451> WL_O<450> WL_O<449> 
++ WL_O<448> WL_O<447> WL_O<446> WL_O<445> WL_O<444> WL_O<443> WL_O<442> 
++ WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> WL_O<436> WL_O<435> 
++ WL_O<434> WL_O<433> WL_O<432> WL_O<431> WL_O<430> WL_O<429> WL_O<428> 
++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> 
++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> WL_O<415> WL_O<414> 
++ WL_O<413> WL_O<412> WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> 
++ WL_O<406> WL_O<405> WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> 
++ WL_O<399> WL_O<398> WL_O<397> WL_O<396> WL_O<395> WL_O<394> WL_O<393> 
++ WL_O<392> WL_O<391> WL_O<390> WL_O<389> WL_O<388> WL_O<387> WL_O<386> 
++ WL_O<385> WL_O<384> WL_O<383> WL_O<382> WL_O<381> WL_O<380> WL_O<379> 
++ WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> WL_O<372> 
++ WL_O<371> WL_O<370> WL_O<369> WL_O<368> WL_O<367> WL_O<366> WL_O<365> 
++ WL_O<364> WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> 
++ WL_O<357> WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> WL_O<351> 
++ WL_O<350> WL_O<349> WL_O<348> WL_O<347> WL_O<346> WL_O<345> WL_O<344> 
++ WL_O<343> WL_O<342> WL_O<341> WL_O<340> WL_O<339> WL_O<338> WL_O<337> 
++ WL_O<336> WL_O<335> WL_O<334> WL_O<333> WL_O<332> WL_O<331> WL_O<330> 
++ WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> WL_O<324> WL_O<323> 
++ WL_O<322> WL_O<321> WL_O<320> WL_O<319> WL_O<318> WL_O<317> WL_O<316> 
++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> 
++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> WL_O<303> WL_O<302> 
++ WL_O<301> WL_O<300> WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> 
++ WL_O<294> WL_O<293> WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> 
++ WL_O<287> WL_O<286> WL_O<285> WL_O<284> WL_O<283> WL_O<282> WL_O<281> 
++ WL_O<280> WL_O<279> WL_O<278> WL_O<277> WL_O<276> WL_O<275> WL_O<274> 
++ WL_O<273> WL_O<272> WL_O<271> WL_O<270> WL_O<269> WL_O<268> WL_O<267> 
++ WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> WL_O<260> 
++ WL_O<259> WL_O<258> WL_O<257> WL_O<256> WL_O<255> WL_O<254> WL_O<253> 
++ WL_O<252> WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> 
++ WL_O<245> WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> WL_O<239> 
++ WL_O<238> WL_O<237> WL_O<236> WL_O<235> WL_O<234> WL_O<233> WL_O<232> 
++ WL_O<231> WL_O<230> WL_O<229> WL_O<228> WL_O<227> WL_O<226> WL_O<225> 
++ WL_O<224> WL_O<223> WL_O<222> WL_O<221> WL_O<220> WL_O<219> WL_O<218> 
++ WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> WL_O<212> WL_O<211> 
++ WL_O<210> WL_O<209> WL_O<208> WL_O<207> WL_O<206> WL_O<205> WL_O<204> 
++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> 
++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> WL_O<191> WL_O<190> 
++ WL_O<189> WL_O<188> WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> 
++ WL_O<182> WL_O<181> WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> 
++ WL_O<175> WL_O<174> WL_O<173> WL_O<172> WL_O<171> WL_O<170> WL_O<169> 
++ WL_O<168> WL_O<167> WL_O<166> WL_O<165> WL_O<164> WL_O<163> WL_O<162> 
++ WL_O<161> WL_O<160> WL_O<159> WL_O<158> WL_O<157> WL_O<156> WL_O<155> 
++ WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> WL_O<148> 
++ WL_O<147> WL_O<146> WL_O<145> WL_O<144> WL_O<143> WL_O<142> WL_O<141> 
++ WL_O<140> WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> 
++ WL_O<133> WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> WL_O<127> 
++ WL_O<126> WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> 
++ WL_O<119> WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> 
++ WL_O<112> WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> 
++ WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> 
++ WL_O<98> WL_O<97> WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> 
++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> 
++ WL_O<82> WL_O<81> WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> 
++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> 
++ WL_O<66> WL_O<65> WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS
+XL2<172> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<171> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<170> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<169> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<168> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<167> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<166> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<165> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<164> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<163> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<162> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<161> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<160> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<159> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<158> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<157> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<156> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<155> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<154> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<153> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<152> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<151> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<150> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<149> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<148> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<147> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<146> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<145> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<144> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<143> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<142> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<141> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<140> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<139> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<138> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<137> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<136> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<135> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<134> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<133> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<132> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<131> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<130> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<129> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<128> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<127> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<126> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<125> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<124> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<123> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<122> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<121> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<120> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<119> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<118> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<117> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<116> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<115> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<114> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<113> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<112> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<111> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<110> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<109> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<108> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<107> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<106> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<105> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<104> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<103> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<102> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<101> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<100> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<99> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<98> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<97> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<96> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<95> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<94> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<93> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<92> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<91> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<90> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<89> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<88> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<87> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<86> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<85> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<84> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<83> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<82> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<81> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<80> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<79> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<78> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<77> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<76> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<75> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<74> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<73> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<72> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<71> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<70> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<69> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<68> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<67> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<66> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<65> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<64> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<63> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<62> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<61> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<60> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<59> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<58> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<57> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<56> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<55> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<54> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<53> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<52> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<51> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<50> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<49> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<48> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<47> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<46> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<45> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XDEC11<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<7> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC03
+XDEC11<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<3> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC03
+XDEC11<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<31> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC03
+XDEC11<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<27> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC03
+XDEC11<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<23> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC03
+XDEC11<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<19> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC03
+XDEC11<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<15> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC03
+XDEC11<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<11> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC03
+XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<7> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC03
+XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<3> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC03
+XDEC00<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<0> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC00
+XDEC00<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<4> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC00
+XDEC00<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<0> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC00
+XDEC00<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<28> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC00
+XDEC00<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<24> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC00
+XDEC00<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<20> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC00
+XDEC00<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<16> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC00
+XDEC00<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<12> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC00
+XDEC00<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<8> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC00
+XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<4> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC00
+XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<0> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC00
+XSEL<31> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<31> ECLK_H<31> 
++ ECLK_H<32> ECLK_B<31> ECLK_B<32> WL_O<511> WL_O<510> WL_O<509> WL_O<508> 
++ WL_O<507> WL_O<506> WL_O<505> WL_O<504> WL_O<503> WL_O<502> WL_O<501> 
++ WL_O<500> WL_O<499> WL_O<498> WL_O<497> WL_O<496> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<30> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<30> ECLK_H<30> 
++ ECLK_H<31> ECLK_B<30> ECLK_B<31> WL_O<495> WL_O<494> WL_O<493> WL_O<492> 
++ WL_O<491> WL_O<490> WL_O<489> WL_O<488> WL_O<487> WL_O<486> WL_O<485> 
++ WL_O<484> WL_O<483> WL_O<482> WL_O<481> WL_O<480> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<29> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<29> ECLK_H<29> 
++ ECLK_H<30> ECLK_B<29> ECLK_B<30> WL_O<479> WL_O<478> WL_O<477> WL_O<476> 
++ WL_O<475> WL_O<474> WL_O<473> WL_O<472> WL_O<471> WL_O<470> WL_O<469> 
++ WL_O<468> WL_O<467> WL_O<466> WL_O<465> WL_O<464> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<28> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<28> ECLK_H<28> 
++ ECLK_H<29> ECLK_B<28> ECLK_B<29> WL_O<463> WL_O<462> WL_O<461> WL_O<460> 
++ WL_O<459> WL_O<458> WL_O<457> WL_O<456> WL_O<455> WL_O<454> WL_O<453> 
++ WL_O<452> WL_O<451> WL_O<450> WL_O<449> WL_O<448> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<27> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<27> ECLK_H<27> 
++ ECLK_H<28> ECLK_B<27> ECLK_B<28> WL_O<447> WL_O<446> WL_O<445> WL_O<444> 
++ WL_O<443> WL_O<442> WL_O<441> WL_O<440> WL_O<439> WL_O<438> WL_O<437> 
++ WL_O<436> WL_O<435> WL_O<434> WL_O<433> WL_O<432> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<26> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<26> ECLK_H<26> 
++ ECLK_H<27> ECLK_B<26> ECLK_B<27> WL_O<431> WL_O<430> WL_O<429> WL_O<428> 
++ WL_O<427> WL_O<426> WL_O<425> WL_O<424> WL_O<423> WL_O<422> WL_O<421> 
++ WL_O<420> WL_O<419> WL_O<418> WL_O<417> WL_O<416> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<25> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<25> ECLK_H<25> 
++ ECLK_H<26> ECLK_B<25> ECLK_B<26> WL_O<415> WL_O<414> WL_O<413> WL_O<412> 
++ WL_O<411> WL_O<410> WL_O<409> WL_O<408> WL_O<407> WL_O<406> WL_O<405> 
++ WL_O<404> WL_O<403> WL_O<402> WL_O<401> WL_O<400> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<24> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<24> ECLK_H<24> 
++ ECLK_H<25> ECLK_B<24> ECLK_B<25> WL_O<399> WL_O<398> WL_O<397> WL_O<396> 
++ WL_O<395> WL_O<394> WL_O<393> WL_O<392> WL_O<391> WL_O<390> WL_O<389> 
++ WL_O<388> WL_O<387> WL_O<386> WL_O<385> WL_O<384> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<23> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<23> ECLK_H<23> 
++ ECLK_H<24> ECLK_B<23> ECLK_B<24> WL_O<383> WL_O<382> WL_O<381> WL_O<380> 
++ WL_O<379> WL_O<378> WL_O<377> WL_O<376> WL_O<375> WL_O<374> WL_O<373> 
++ WL_O<372> WL_O<371> WL_O<370> WL_O<369> WL_O<368> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<22> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<22> ECLK_H<22> 
++ ECLK_H<23> ECLK_B<22> ECLK_B<23> WL_O<367> WL_O<366> WL_O<365> WL_O<364> 
++ WL_O<363> WL_O<362> WL_O<361> WL_O<360> WL_O<359> WL_O<358> WL_O<357> 
++ WL_O<356> WL_O<355> WL_O<354> WL_O<353> WL_O<352> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<21> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<21> ECLK_H<21> 
++ ECLK_H<22> ECLK_B<21> ECLK_B<22> WL_O<351> WL_O<350> WL_O<349> WL_O<348> 
++ WL_O<347> WL_O<346> WL_O<345> WL_O<344> WL_O<343> WL_O<342> WL_O<341> 
++ WL_O<340> WL_O<339> WL_O<338> WL_O<337> WL_O<336> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<20> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<20> ECLK_H<20> 
++ ECLK_H<21> ECLK_B<20> ECLK_B<21> WL_O<335> WL_O<334> WL_O<333> WL_O<332> 
++ WL_O<331> WL_O<330> WL_O<329> WL_O<328> WL_O<327> WL_O<326> WL_O<325> 
++ WL_O<324> WL_O<323> WL_O<322> WL_O<321> WL_O<320> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<19> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<19> ECLK_H<19> 
++ ECLK_H<20> ECLK_B<19> ECLK_B<20> WL_O<319> WL_O<318> WL_O<317> WL_O<316> 
++ WL_O<315> WL_O<314> WL_O<313> WL_O<312> WL_O<311> WL_O<310> WL_O<309> 
++ WL_O<308> WL_O<307> WL_O<306> WL_O<305> WL_O<304> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<18> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<18> ECLK_H<18> 
++ ECLK_H<19> ECLK_B<18> ECLK_B<19> WL_O<303> WL_O<302> WL_O<301> WL_O<300> 
++ WL_O<299> WL_O<298> WL_O<297> WL_O<296> WL_O<295> WL_O<294> WL_O<293> 
++ WL_O<292> WL_O<291> WL_O<290> WL_O<289> WL_O<288> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<17> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<17> ECLK_H<17> 
++ ECLK_H<18> ECLK_B<17> ECLK_B<18> WL_O<287> WL_O<286> WL_O<285> WL_O<284> 
++ WL_O<283> WL_O<282> WL_O<281> WL_O<280> WL_O<279> WL_O<278> WL_O<277> 
++ WL_O<276> WL_O<275> WL_O<274> WL_O<273> WL_O<272> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<16> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<16> ECLK_H<16> 
++ ECLK_H<17> ECLK_B<16> ECLK_B<17> WL_O<271> WL_O<270> WL_O<269> WL_O<268> 
++ WL_O<267> WL_O<266> WL_O<265> WL_O<264> WL_O<263> WL_O<262> WL_O<261> 
++ WL_O<260> WL_O<259> WL_O<258> WL_O<257> WL_O<256> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<15> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<15> ECLK_H<15> 
++ ECLK_H<16> ECLK_B<15> ECLK_B<16> WL_O<255> WL_O<254> WL_O<253> WL_O<252> 
++ WL_O<251> WL_O<250> WL_O<249> WL_O<248> WL_O<247> WL_O<246> WL_O<245> 
++ WL_O<244> WL_O<243> WL_O<242> WL_O<241> WL_O<240> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<14> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<14> ECLK_H<14> 
++ ECLK_H<15> ECLK_B<14> ECLK_B<15> WL_O<239> WL_O<238> WL_O<237> WL_O<236> 
++ WL_O<235> WL_O<234> WL_O<233> WL_O<232> WL_O<231> WL_O<230> WL_O<229> 
++ WL_O<228> WL_O<227> WL_O<226> WL_O<225> WL_O<224> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<13> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<13> ECLK_H<13> 
++ ECLK_H<14> ECLK_B<13> ECLK_B<14> WL_O<223> WL_O<222> WL_O<221> WL_O<220> 
++ WL_O<219> WL_O<218> WL_O<217> WL_O<216> WL_O<215> WL_O<214> WL_O<213> 
++ WL_O<212> WL_O<211> WL_O<210> WL_O<209> WL_O<208> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<12> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<12> ECLK_H<12> 
++ ECLK_H<13> ECLK_B<12> ECLK_B<13> WL_O<207> WL_O<206> WL_O<205> WL_O<204> 
++ WL_O<203> WL_O<202> WL_O<201> WL_O<200> WL_O<199> WL_O<198> WL_O<197> 
++ WL_O<196> WL_O<195> WL_O<194> WL_O<193> WL_O<192> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<11> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<11> ECLK_H<11> 
++ ECLK_H<12> ECLK_B<11> ECLK_B<12> WL_O<191> WL_O<190> WL_O<189> WL_O<188> 
++ WL_O<187> WL_O<186> WL_O<185> WL_O<184> WL_O<183> WL_O<182> WL_O<181> 
++ WL_O<180> WL_O<179> WL_O<178> WL_O<177> WL_O<176> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<10> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<10> ECLK_H<10> 
++ ECLK_H<11> ECLK_B<10> ECLK_B<11> WL_O<175> WL_O<174> WL_O<173> WL_O<172> 
++ WL_O<171> WL_O<170> WL_O<169> WL_O<168> WL_O<167> WL_O<166> WL_O<165> 
++ WL_O<164> WL_O<163> WL_O<162> WL_O<161> WL_O<160> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<9> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<9> ECLK_H<9> 
++ ECLK_H<10> ECLK_B<9> ECLK_B<10> WL_O<159> WL_O<158> WL_O<157> WL_O<156> 
++ WL_O<155> WL_O<154> WL_O<153> WL_O<152> WL_O<151> WL_O<150> WL_O<149> 
++ WL_O<148> WL_O<147> WL_O<146> WL_O<145> WL_O<144> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<8> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<8> ECLK_H<8> 
++ ECLK_H<9> ECLK_B<8> ECLK_B<9> WL_O<143> WL_O<142> WL_O<141> WL_O<140> 
++ WL_O<139> WL_O<138> WL_O<137> WL_O<136> WL_O<135> WL_O<134> WL_O<133> 
++ WL_O<132> WL_O<131> WL_O<130> WL_O<129> WL_O<128> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> 
++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> 
++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> 
++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> 
++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> 
++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> 
++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> 
++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> 
++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> 
++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> 
++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> 
++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> 
++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> 
++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> 
++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04
+XDEC01<10> ADDR_N_I<9> ADDR_N_I<8> CS_I CS04<1> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC01
+XDEC01<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<5> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC01
+XDEC01<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<1> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC01
+XDEC01<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<29> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC01
+XDEC01<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<25> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC01
+XDEC01<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<21> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC01
+XDEC01<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<17> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC01
+XDEC01<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<13> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC01
+XDEC01<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<9> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC01
+XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<5> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC01
+XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<1> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC01
+XDEC10<9> ADDR_N_I<7> ADDR_N_I<6> CS04<1> CS02<6> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC02
+XDEC10<8> ADDR_N_I<7> ADDR_N_I<6> CS04<0> CS02<2> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC02
+XDEC10<7> ADDR_N_I<5> ADDR_N_I<4> CS02<7> CS00<30> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC02
+XDEC10<6> ADDR_N_I<5> ADDR_N_I<4> CS02<6> CS00<26> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC02
+XDEC10<5> ADDR_N_I<5> ADDR_N_I<4> CS02<5> CS00<22> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC02
+XDEC10<4> ADDR_N_I<5> ADDR_N_I<4> CS02<4> CS00<18> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC02
+XDEC10<3> ADDR_N_I<5> ADDR_N_I<4> CS02<3> CS00<14> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC02
+XDEC10<2> ADDR_N_I<5> ADDR_N_I<4> CS02<2> CS00<10> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC02
+XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS02<1> CS00<6> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC02
+XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS02<0> CS00<2> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC02
+XI0 ADDR_N_I<9> VDD VSS / RSC_IHPSG13_TIEL
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_ROWREG9 ACLK_N_I ADDR_I<8> ADDR_I<7> ADDR_I<6> ADDR_I<5> 
++ ADDR_I<4> ADDR_I<3> ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<8> ADDR_N_O<7> 
++ ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> 
++ ADDR_N_O<0> BIST_ADDR_I<8> BIST_ADDR_I<7> BIST_ADDR_I<6> BIST_ADDR_I<5> 
++ BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> 
++ BIST_EN_I VDD VSS
+XINV<8> q_int<8> qn_int<8> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<7> q_int<7> qn_int<7> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<8> qn_int<8> ADDR_N_O<8> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<7> qn_int<7> ADDR_N_O<7> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<8> BIST_EN_I BIST_ADDR_I<8> ACLK_N_I ADDR_I<8> q_int<8> net04<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<7> BIST_EN_I BIST_ADDR_I<7> ACLK_N_I ADDR_I<7> q_int<7> net04<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net04<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net04<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net04<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net04<5> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net04<6> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net04<7> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net04<8> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+.ENDS
+
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_ROWDEC7 ADDR_N_I<6> ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> 
++ ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<127> WL_O<126> 
++ WL_O<125> WL_O<124> WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> 
++ WL_O<118> WL_O<117> WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> 
++ WL_O<111> WL_O<110> WL_O<109> WL_O<108> WL_O<107> WL_O<106> WL_O<105> 
++ WL_O<104> WL_O<103> WL_O<102> WL_O<101> WL_O<100> WL_O<99> WL_O<98> WL_O<97> 
++ WL_O<96> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> WL_O<90> WL_O<89> 
++ WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> WL_O<82> WL_O<81> 
++ WL_O<80> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> WL_O<74> WL_O<73> 
++ WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> WL_O<66> WL_O<65> 
++ WL_O<64> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> WL_O<58> WL_O<57> 
++ WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> WL_O<50> WL_O<49> 
++ WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> WL_O<42> WL_O<41> 
++ WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> WL_O<34> WL_O<33> 
++ WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> WL_O<26> WL_O<25> 
++ WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> WL_O<18> WL_O<17> 
++ WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> WL_O<10> WL_O<9> 
++ WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> WL_O<1> WL_O<0> 
++ VDD VSS
+XDEC11<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<7> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC03
+XDEC11<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<3> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC03
+XDEC10<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<6> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC02
+XDEC10<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<2> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC02
+XSEL<7> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<7> ECLK_H<7> 
++ ECLK_H<8> ECLK_B<7> ECLK_B<8> WL_O<127> WL_O<126> WL_O<125> WL_O<124> 
++ WL_O<123> WL_O<122> WL_O<121> WL_O<120> WL_O<119> WL_O<118> WL_O<117> 
++ WL_O<116> WL_O<115> WL_O<114> WL_O<113> WL_O<112> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<6> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<6> ECLK_H<6> 
++ ECLK_H<7> ECLK_B<6> ECLK_B<7> WL_O<111> WL_O<110> WL_O<109> WL_O<108> 
++ WL_O<107> WL_O<106> WL_O<105> WL_O<104> WL_O<103> WL_O<102> WL_O<101> 
++ WL_O<100> WL_O<99> WL_O<98> WL_O<97> WL_O<96> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<5> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<5> ECLK_H<5> 
++ ECLK_H<6> ECLK_B<5> ECLK_B<6> WL_O<95> WL_O<94> WL_O<93> WL_O<92> WL_O<91> 
++ WL_O<90> WL_O<89> WL_O<88> WL_O<87> WL_O<86> WL_O<85> WL_O<84> WL_O<83> 
++ WL_O<82> WL_O<81> WL_O<80> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<4> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<4> ECLK_H<4> 
++ ECLK_H<5> ECLK_B<4> ECLK_B<5> WL_O<79> WL_O<78> WL_O<77> WL_O<76> WL_O<75> 
++ WL_O<74> WL_O<73> WL_O<72> WL_O<71> WL_O<70> WL_O<69> WL_O<68> WL_O<67> 
++ WL_O<66> WL_O<65> WL_O<64> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> 
++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> 
++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04
+XDEC00<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<0> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC00
+XDEC00<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<4> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC00
+XDEC00<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<0> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC00
+XDEC01<2> ADDR_N_I<7> ADDR_N_I<6> CS_I CS04<1> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC01
+XDEC01<1> ADDR_N_I<5> ADDR_N_I<4> CS04<1> CS00<5> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC01
+XDEC01<0> ADDR_N_I<5> ADDR_N_I<4> CS04<0> CS00<1> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC01
+XL2<44> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<43> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<42> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<41> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<40> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<39> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<38> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<37> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<36> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<35> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<34> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<33> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<32> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<31> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<30> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<29> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<28> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<27> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<26> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<25> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI0 ADDR_N_I<7> VDD VSS / RSC_IHPSG13_TIEL
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_ROWREG7 ACLK_N_I ADDR_I<6> ADDR_I<5> ADDR_I<4> ADDR_I<3> 
++ ADDR_I<2> ADDR_I<1> ADDR_I<0> ADDR_N_O<6> ADDR_N_O<5> ADDR_N_O<4> 
++ ADDR_N_O<3> ADDR_N_O<2> ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<6> 
++ BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> BIST_ADDR_I<2> BIST_ADDR_I<1> 
++ BIST_ADDR_I<0> BIST_EN_I VDD VSS
+XINV<6> q_int<6> qn_int<6> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<6> qn_int<6> ADDR_N_O<6> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<6> BIST_EN_I BIST_ADDR_I<6> ACLK_N_I ADDR_I<6> q_int<6> net2<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<5> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<6> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_COLDRV13X8 ADDR_COL_I<1> ADDR_COL_I<0> ADDR_COL_O<1> 
++ ADDR_COL_O<0> ADDR_DEC_I<7> ADDR_DEC_I<6> ADDR_DEC_I<5> ADDR_DEC_I<4> 
++ ADDR_DEC_I<3> ADDR_DEC_I<2> ADDR_DEC_I<1> ADDR_DEC_I<0> ADDR_DEC_O<7> 
++ ADDR_DEC_O<6> ADDR_DEC_O<5> ADDR_DEC_O<4> ADDR_DEC_O<3> ADDR_DEC_O<2> 
++ ADDR_DEC_O<1> ADDR_DEC_O<0> DCLK_I DCLK_O RCLK_I RCLK_O WCLK_I WCLK_O 
++ VDD VSS
+XI0<1> VDD VSS / RSC_IHPSG13_FILLCAP4
+XI0<0> VDD VSS / RSC_IHPSG13_FILLCAP4
+XADDR_COL_DRV<1> ADDR_COL_I<1> ADDR_COL_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_COL_DRV<0> ADDR_COL_I<0> ADDR_COL_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<7> ADDR_DEC_I<7> ADDR_DEC_O<7> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<6> ADDR_DEC_I<6> ADDR_DEC_O<6> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<5> ADDR_DEC_I<5> ADDR_DEC_O<5> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<4> ADDR_DEC_I<4> ADDR_DEC_O<4> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<3> ADDR_DEC_I<3> ADDR_DEC_O<3> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<2> ADDR_DEC_I<2> ADDR_DEC_O<2> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<1> ADDR_DEC_I<1> ADDR_DEC_O<1> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XADDR_DEC_DRV<0> ADDR_DEC_I<0> ADDR_DEC_O<0> VDD VSS / 
++ RSC_IHPSG13_CBUFX8
+XDCLK_DRV DCLK_I DCLK_O VDD VSS / RSC_IHPSG13_CBUFX8
+XRCLK_DRV RCLK_I RCLK_O VDD VSS / RSC_IHPSG13_CBUFX8
+XWCLK_DRV WCLK_I WCLK_O VDD VSS / RSC_IHPSG13_CBUFX8
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_WLDRV16X8 A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> 
++ A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> Z<15> Z<14> Z<13> Z<12> Z<11> Z<10> 
++ Z<9> Z<8> Z<7> Z<6> Z<5> Z<4> Z<3> Z<2> Z<1> Z<0> VDD VSS
+XBUF<15> A<15> Z<15> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<14> A<14> Z<14> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<13> A<13> Z<13> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<12> A<12> Z<12> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<11> A<11> Z<11> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<10> A<10> Z<10> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<9> A<9> Z<9> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<8> A<8> Z<8> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<7> A<7> Z<7> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<6> A<6> Z<6> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<5> A<5> Z<5> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<4> A<4> Z<4> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<3> A<3> Z<3> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<2> A<2> Z<2> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<1> A<1> Z<1> VDD VSS / RSC_IHPSG13_WLDRVX8
+XBUF<0> A<0> Z<0> VDD VSS / RSC_IHPSG13_WLDRVX8
+.ENDS
+
+
+
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_ROWDEC6 ADDR_N_I<5> ADDR_N_I<4> ADDR_N_I<3> ADDR_N_I<2> 
++ ADDR_N_I<1> ADDR_N_I<0> CS_I ECLK_I WL_O<63> WL_O<62> WL_O<61> WL_O<60> 
++ WL_O<59> WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> 
++ WL_O<51> WL_O<50> WL_O<49> WL_O<48> WL_O<47> WL_O<46> WL_O<45> WL_O<44> 
++ WL_O<43> WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> 
++ WL_O<35> WL_O<34> WL_O<33> WL_O<32> WL_O<31> WL_O<30> WL_O<29> WL_O<28> 
++ WL_O<27> WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> 
++ WL_O<19> WL_O<18> WL_O<17> WL_O<16> WL_O<15> WL_O<14> WL_O<13> WL_O<12> 
++ WL_O<11> WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> 
++ WL_O<2> WL_O<1> WL_O<0> VDD VSS
+XDEC11 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<3> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC03
+XDEC00 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<0> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC00
+XDEC01 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<1> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC01
+XDEC10 ADDR_N_I<5> ADDR_N_I<4> CS_I CS00<2> VDD VSS / 
++ RM_IHPSG13_4096x8_c3_1P_DEC02
+XSEL<3> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<3> ECLK_H<3> 
++ ECLK_H<4> ECLK_B<3> ECLK_B<4> WL_O<63> WL_O<62> WL_O<61> WL_O<60> WL_O<59> 
++ WL_O<58> WL_O<57> WL_O<56> WL_O<55> WL_O<54> WL_O<53> WL_O<52> WL_O<51> 
++ WL_O<50> WL_O<49> WL_O<48> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<2> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<2> ECLK_H<2> 
++ ECLK_H<3> ECLK_B<2> ECLK_B<3> WL_O<47> WL_O<46> WL_O<45> WL_O<44> WL_O<43> 
++ WL_O<42> WL_O<41> WL_O<40> WL_O<39> WL_O<38> WL_O<37> WL_O<36> WL_O<35> 
++ WL_O<34> WL_O<33> WL_O<32> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<1> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<1> ECLK_H<1> 
++ ECLK_H<2> ECLK_B<1> ECLK_B<2> WL_O<31> WL_O<30> WL_O<29> WL_O<28> WL_O<27> 
++ WL_O<26> WL_O<25> WL_O<24> WL_O<23> WL_O<22> WL_O<21> WL_O<20> WL_O<19> 
++ WL_O<18> WL_O<17> WL_O<16> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04
+XSEL<0> ADDR_N_I<3> ADDR_N_I<2> ADDR_N_I<1> ADDR_N_I<0> CS00<0> ECLK_I 
++ ECLK_H<1> ECLK_B<0> ECLK_B<1> WL_O<15> WL_O<14> WL_O<13> WL_O<12> WL_O<11> 
++ WL_O<10> WL_O<9> WL_O<8> WL_O<7> WL_O<6> WL_O<5> WL_O<4> WL_O<3> WL_O<2> 
++ WL_O<1> WL_O<0> VDD VSS / RM_IHPSG13_4096x8_c3_1P_DEC04
+XL2<24> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<23> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<22> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<21> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<20> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<19> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<18> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<17> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<16> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<15> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<14> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<13> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XL2<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_ROWREG6 ACLK_N_I ADDR_I<5> ADDR_I<4> ADDR_I<3> ADDR_I<2> 
++ ADDR_I<1> ADDR_I<0> ADDR_N_O<5> ADDR_N_O<4> ADDR_N_O<3> ADDR_N_O<2> 
++ ADDR_N_O<1> ADDR_N_O<0> BIST_ADDR_I<5> BIST_ADDR_I<4> BIST_ADDR_I<3> 
++ BIST_ADDR_I<2> BIST_ADDR_I<1> BIST_ADDR_I<0> BIST_EN_I VDD VSS
+XINV<5> q_int<5> qn_int<5> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<4> q_int<4> qn_int<4> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<3> q_int<3> qn_int<3> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<2> q_int<2> qn_int<2> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<1> q_int<1> qn_int<1> VDD VSS / RSC_IHPSG13_CINVX2
+XINV<0> q_int<0> qn_int<0> VDD VSS / RSC_IHPSG13_CINVX2
+XDRV<5> qn_int<5> ADDR_N_O<5> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<4> qn_int<4> ADDR_N_O<4> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<3> qn_int<3> ADDR_N_O<3> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<2> qn_int<2> ADDR_N_O<2> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<1> qn_int<1> ADDR_N_O<1> VDD VSS / RSC_IHPSG13_CINVX8
+XDRV<0> qn_int<0> ADDR_N_O<0> VDD VSS / RSC_IHPSG13_CINVX8
+XDFF<5> BIST_EN_I BIST_ADDR_I<5> ACLK_N_I ADDR_I<5> q_int<5> net2<0> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<4> BIST_EN_I BIST_ADDR_I<4> ACLK_N_I ADDR_I<4> q_int<4> net2<1> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<3> BIST_EN_I BIST_ADDR_I<3> ACLK_N_I ADDR_I<3> q_int<3> net2<2> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<2> BIST_EN_I BIST_ADDR_I<2> ACLK_N_I ADDR_I<2> q_int<2> net2<3> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<1> BIST_EN_I BIST_ADDR_I<1> ACLK_N_I ADDR_I<1> q_int<1> net2<4> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XDFF<0> BIST_EN_I BIST_ADDR_I<0> ACLK_N_I ADDR_I<0> q_int<0> net2<5> VDD 
++ VSS / RSC_IHPSG13_DFNQMX2IX1
+XI11<12> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<11> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<10> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<9> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<8> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<7> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<6> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<5> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<4> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<3> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<2> VDD VSS / RSC_IHPSG13_FILLCAP8
+XI11<1> VDD VSS / RSC_IHPSG13_FILLCAP8
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_COLUMN_pcell_0 A_BLC_BOT<1> A_BLC_BOT<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<511> A_LWL<510> A_LWL<509> A_LWL<508> A_LWL<507> A_LWL<506> A_LWL<505> A_LWL<504> A_LWL<503> A_LWL<502> A_LWL<501> A_LWL<500> A_LWL<499> A_LWL<498> A_LWL<497> A_LWL<496> A_LWL<495> A_LWL<494> A_LWL<493> A_LWL<492> A_LWL<491> A_LWL<490> A_LWL<489> A_LWL<488> A_LWL<487> A_LWL<486> A_LWL<485> A_LWL<484> A_LWL<483> A_LWL<482> A_LWL<481> A_LWL<480> A_LWL<479> A_LWL<478> A_LWL<477> A_LWL<476> A_LWL<475> A_LWL<474> A_LWL<473> A_LWL<472> A_LWL<471> A_LWL<470> A_LWL<469> A_LWL<468> A_LWL<467> A_LWL<466> A_LWL<465> A_LWL<464> A_LWL<463> A_LWL<462> A_LWL<461> A_LWL<460> A_LWL<459> A_LWL<458> A_LWL<457> A_LWL<456> A_LWL<455> A_LWL<454> A_LWL<453> A_LWL<452> A_LWL<451> A_LWL<450> A_LWL<449> A_LWL<448> A_LWL<447> A_LWL<446> A_LWL<445> A_LWL<444> A_LWL<443> A_LWL<442> A_LWL<441> A_LWL<440> A_LWL<439> A_LWL<438> A_LWL<437> A_LWL<436> A_LWL<435> A_LWL<434> A_LWL<433> A_LWL<432> A_LWL<431> A_LWL<430> A_LWL<429> A_LWL<428> A_LWL<427> A_LWL<426> A_LWL<425> A_LWL<424> A_LWL<423> A_LWL<422> A_LWL<421> A_LWL<420> A_LWL<419> A_LWL<418> A_LWL<417> A_LWL<416> A_LWL<415> A_LWL<414> A_LWL<413> A_LWL<412> A_LWL<411> A_LWL<410> A_LWL<409> A_LWL<408> A_LWL<407> A_LWL<406> A_LWL<405> A_LWL<404> A_LWL<403> A_LWL<402> A_LWL<401> A_LWL<400> A_LWL<399> A_LWL<398> A_LWL<397> A_LWL<396> A_LWL<395> A_LWL<394> A_LWL<393> A_LWL<392> A_LWL<391> A_LWL<390> A_LWL<389> A_LWL<388> A_LWL<387> A_LWL<386> A_LWL<385> A_LWL<384> A_LWL<383> A_LWL<382> A_LWL<381> A_LWL<380> A_LWL<379> A_LWL<378> A_LWL<377> A_LWL<376> A_LWL<375> A_LWL<374> A_LWL<373> A_LWL<372> A_LWL<371> A_LWL<370> A_LWL<369> A_LWL<368> A_LWL<367> A_LWL<366> A_LWL<365> A_LWL<364> A_LWL<363> A_LWL<362> A_LWL<361> A_LWL<360> A_LWL<359> A_LWL<358> A_LWL<357> A_LWL<356> A_LWL<355> A_LWL<354> A_LWL<353> A_LWL<352> A_LWL<351> A_LWL<350> A_LWL<349> A_LWL<348> A_LWL<347> A_LWL<346> A_LWL<345> A_LWL<344> A_LWL<343> A_LWL<342> A_LWL<341> A_LWL<340> A_LWL<339> A_LWL<338> A_LWL<337> A_LWL<336> A_LWL<335> A_LWL<334> A_LWL<333> A_LWL<332> A_LWL<331> A_LWL<330> A_LWL<329> A_LWL<328> A_LWL<327> A_LWL<326> A_LWL<325> A_LWL<324> A_LWL<323> A_LWL<322> A_LWL<321> A_LWL<320> A_LWL<319> A_LWL<318> A_LWL<317> A_LWL<316> A_LWL<315> A_LWL<314> A_LWL<313> A_LWL<312> A_LWL<311> A_LWL<310> A_LWL<309> A_LWL<308> A_LWL<307> A_LWL<306> A_LWL<305> A_LWL<304> A_LWL<303> A_LWL<302> A_LWL<301> A_LWL<300> A_LWL<299> A_LWL<298> A_LWL<297> A_LWL<296> A_LWL<295> A_LWL<294> A_LWL<293> A_LWL<292> A_LWL<291> A_LWL<290> A_LWL<289> A_LWL<288> A_LWL<287> A_LWL<286> A_LWL<285> A_LWL<284> A_LWL<283> A_LWL<282> A_LWL<281> A_LWL<280> A_LWL<279> A_LWL<278> A_LWL<277> A_LWL<276> A_LWL<275> A_LWL<274> A_LWL<273> A_LWL<272> A_LWL<271> A_LWL<270> A_LWL<269> A_LWL<268> A_LWL<267> A_LWL<266> A_LWL<265> A_LWL<264> A_LWL<263> A_LWL<262> A_LWL<261> A_LWL<260> A_LWL<259> A_LWL<258> A_LWL<257> A_LWL<256> A_LWL<255> A_LWL<254> A_LWL<253> A_LWL<252> A_LWL<251> A_LWL<250> A_LWL<249> A_LWL<248> A_LWL<247> A_LWL<246> A_LWL<245> A_LWL<244> A_LWL<243> A_LWL<242> A_LWL<241> A_LWL<240> A_LWL<239> A_LWL<238> A_LWL<237> A_LWL<236> A_LWL<235> A_LWL<234> A_LWL<233> A_LWL<232> A_LWL<231> A_LWL<230> A_LWL<229> A_LWL<228> A_LWL<227> A_LWL<226> A_LWL<225> A_LWL<224> A_LWL<223> A_LWL<222> A_LWL<221> A_LWL<220> A_LWL<219> A_LWL<218> A_LWL<217> A_LWL<216> A_LWL<215> A_LWL<214> A_LWL<213> A_LWL<212> A_LWL<211> A_LWL<210> A_LWL<209> A_LWL<208> A_LWL<207> A_LWL<206> A_LWL<205> A_LWL<204> A_LWL<203> A_LWL<202> A_LWL<201> A_LWL<200> A_LWL<199> A_LWL<198> A_LWL<197> A_LWL<196> A_LWL<195> A_LWL<194> A_LWL<193> A_LWL<192> A_LWL<191> A_LWL<190> A_LWL<189> A_LWL<188> A_LWL<187> A_LWL<186> A_LWL<185> A_LWL<184> A_LWL<183> A_LWL<182> A_LWL<181> A_LWL<180> A_LWL<179> A_LWL<178> A_LWL<177> A_LWL<176> A_LWL<175> A_LWL<174> A_LWL<173> A_LWL<172> A_LWL<171> A_LWL<170> A_LWL<169> A_LWL<168> A_LWL<167> A_LWL<166> A_LWL<165> A_LWL<164> A_LWL<163> A_LWL<162> A_LWL<161> A_LWL<160> A_LWL<159> A_LWL<158> A_LWL<157> A_LWL<156> A_LWL<155> A_LWL<154> A_LWL<153> A_LWL<152> A_LWL<151> A_LWL<150> A_LWL<149> A_LWL<148> A_LWL<147> A_LWL<146> A_LWL<145> A_LWL<144> A_LWL<143> A_LWL<142> A_LWL<141> A_LWL<140> A_LWL<139> A_LWL<138> A_LWL<137> A_LWL<136> A_LWL<135> A_LWL<134> A_LWL<133> A_LWL<132> A_LWL<131> A_LWL<130> A_LWL<129> A_LWL<128> A_LWL<127> A_LWL<126> A_LWL<125> A_LWL<124> A_LWL<123> A_LWL<122> A_LWL<121> A_LWL<120> A_LWL<119> A_LWL<118> A_LWL<117> A_LWL<116> A_LWL<115> A_LWL<114> A_LWL<113> A_LWL<112> A_LWL<111> A_LWL<110> A_LWL<109> A_LWL<108> A_LWL<107> A_LWL<106> A_LWL<105> A_LWL<104> A_LWL<103> A_LWL<102> A_LWL<101> A_LWL<100> A_LWL<99> A_LWL<98> A_LWL<97> A_LWL<96> A_LWL<95> A_LWL<94> A_LWL<93> A_LWL<92> A_LWL<91> A_LWL<90> A_LWL<89> A_LWL<88> A_LWL<87> A_LWL<86> A_LWL<85> A_LWL<84> A_LWL<83> A_LWL<82> A_LWL<81> A_LWL<80> A_LWL<79> A_LWL<78> A_LWL<77> A_LWL<76> A_LWL<75> A_LWL<74> A_LWL<73> A_LWL<72> A_LWL<71> A_LWL<70> A_LWL<69> A_LWL<68> A_LWL<67> A_LWL<66> A_LWL<65> A_LWL<64> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<511> A_RWL<510> A_RWL<509> A_RWL<508> A_RWL<507> A_RWL<506> A_RWL<505> A_RWL<504> A_RWL<503> A_RWL<502> A_RWL<501> A_RWL<500> A_RWL<499> A_RWL<498> A_RWL<497> A_RWL<496> A_RWL<495> A_RWL<494> A_RWL<493> A_RWL<492> A_RWL<491> A_RWL<490> A_RWL<489> A_RWL<488> A_RWL<487> A_RWL<486> A_RWL<485> A_RWL<484> A_RWL<483> A_RWL<482> A_RWL<481> A_RWL<480> A_RWL<479> A_RWL<478> A_RWL<477> A_RWL<476> A_RWL<475> A_RWL<474> A_RWL<473> A_RWL<472> A_RWL<471> A_RWL<470> A_RWL<469> A_RWL<468> A_RWL<467> A_RWL<466> A_RWL<465> A_RWL<464> A_RWL<463> A_RWL<462> A_RWL<461> A_RWL<460> A_RWL<459> A_RWL<458> A_RWL<457> A_RWL<456> A_RWL<455> A_RWL<454> A_RWL<453> A_RWL<452> A_RWL<451> A_RWL<450> A_RWL<449> A_RWL<448> A_RWL<447> A_RWL<446> A_RWL<445> A_RWL<444> A_RWL<443> A_RWL<442> A_RWL<441> A_RWL<440> A_RWL<439> A_RWL<438> A_RWL<437> A_RWL<436> A_RWL<435> A_RWL<434> A_RWL<433> A_RWL<432> A_RWL<431> A_RWL<430> A_RWL<429> A_RWL<428> A_RWL<427> A_RWL<426> A_RWL<425> A_RWL<424> A_RWL<423> A_RWL<422> A_RWL<421> A_RWL<420> A_RWL<419> A_RWL<418> A_RWL<417> A_RWL<416> A_RWL<415> A_RWL<414> A_RWL<413> A_RWL<412> A_RWL<411> A_RWL<410> A_RWL<409> A_RWL<408> A_RWL<407> A_RWL<406> A_RWL<405> A_RWL<404> A_RWL<403> A_RWL<402> A_RWL<401> A_RWL<400> A_RWL<399> A_RWL<398> A_RWL<397> A_RWL<396> A_RWL<395> A_RWL<394> A_RWL<393> A_RWL<392> A_RWL<391> A_RWL<390> A_RWL<389> A_RWL<388> A_RWL<387> A_RWL<386> A_RWL<385> A_RWL<384> A_RWL<383> A_RWL<382> A_RWL<381> A_RWL<380> A_RWL<379> A_RWL<378> A_RWL<377> A_RWL<376> A_RWL<375> A_RWL<374> A_RWL<373> A_RWL<372> A_RWL<371> A_RWL<370> A_RWL<369> A_RWL<368> A_RWL<367> A_RWL<366> A_RWL<365> A_RWL<364> A_RWL<363> A_RWL<362> A_RWL<361> A_RWL<360> A_RWL<359> A_RWL<358> A_RWL<357> A_RWL<356> A_RWL<355> A_RWL<354> A_RWL<353> A_RWL<352> A_RWL<351> A_RWL<350> A_RWL<349> A_RWL<348> A_RWL<347> A_RWL<346> A_RWL<345> A_RWL<344> A_RWL<343> A_RWL<342> A_RWL<341> A_RWL<340> A_RWL<339> A_RWL<338> A_RWL<337> A_RWL<336> A_RWL<335> A_RWL<334> A_RWL<333> A_RWL<332> A_RWL<331> A_RWL<330> A_RWL<329> A_RWL<328> A_RWL<327> A_RWL<326> A_RWL<325> A_RWL<324> A_RWL<323> A_RWL<322> A_RWL<321> A_RWL<320> A_RWL<319> A_RWL<318> A_RWL<317> A_RWL<316> A_RWL<315> A_RWL<314> A_RWL<313> A_RWL<312> A_RWL<311> A_RWL<310> A_RWL<309> A_RWL<308> A_RWL<307> A_RWL<306> A_RWL<305> A_RWL<304> A_RWL<303> A_RWL<302> A_RWL<301> A_RWL<300> A_RWL<299> A_RWL<298> A_RWL<297> A_RWL<296> A_RWL<295> A_RWL<294> A_RWL<293> A_RWL<292> A_RWL<291> A_RWL<290> A_RWL<289> A_RWL<288> A_RWL<287> A_RWL<286> A_RWL<285> A_RWL<284> A_RWL<283> A_RWL<282> A_RWL<281> A_RWL<280> A_RWL<279> A_RWL<278> A_RWL<277> A_RWL<276> A_RWL<275> A_RWL<274> A_RWL<273> A_RWL<272> A_RWL<271> A_RWL<270> A_RWL<269> A_RWL<268> A_RWL<267> A_RWL<266> A_RWL<265> A_RWL<264> A_RWL<263> A_RWL<262> A_RWL<261> A_RWL<260> A_RWL<259> A_RWL<258> A_RWL<257> A_RWL<256> A_RWL<255> A_RWL<254> A_RWL<253> A_RWL<252> A_RWL<251> A_RWL<250> A_RWL<249> A_RWL<248> A_RWL<247> A_RWL<246> A_RWL<245> A_RWL<244> A_RWL<243> A_RWL<242> A_RWL<241> A_RWL<240> A_RWL<239> A_RWL<238> A_RWL<237> A_RWL<236> A_RWL<235> A_RWL<234> A_RWL<233> A_RWL<232> A_RWL<231> A_RWL<230> A_RWL<229> A_RWL<228> A_RWL<227> A_RWL<226> A_RWL<225> A_RWL<224> A_RWL<223> A_RWL<222> A_RWL<221> A_RWL<220> A_RWL<219> A_RWL<218> A_RWL<217> A_RWL<216> A_RWL<215> A_RWL<214> A_RWL<213> A_RWL<212> A_RWL<211> A_RWL<210> A_RWL<209> A_RWL<208> A_RWL<207> A_RWL<206> A_RWL<205> A_RWL<204> A_RWL<203> A_RWL<202> A_RWL<201> A_RWL<200> A_RWL<199> A_RWL<198> A_RWL<197> A_RWL<196> A_RWL<195> A_RWL<194> A_RWL<193> A_RWL<192> A_RWL<191> A_RWL<190> A_RWL<189> A_RWL<188> A_RWL<187> A_RWL<186> A_RWL<185> A_RWL<184> A_RWL<183> A_RWL<182> A_RWL<181> A_RWL<180> A_RWL<179> A_RWL<178> A_RWL<177> A_RWL<176> A_RWL<175> A_RWL<174> A_RWL<173> A_RWL<172> A_RWL<171> A_RWL<170> A_RWL<169> A_RWL<168> A_RWL<167> A_RWL<166> A_RWL<165> A_RWL<164> A_RWL<163> A_RWL<162> A_RWL<161> A_RWL<160> A_RWL<159> A_RWL<158> A_RWL<157> A_RWL<156> A_RWL<155> A_RWL<154> A_RWL<153> A_RWL<152> A_RWL<151> A_RWL<150> A_RWL<149> A_RWL<148> A_RWL<147> A_RWL<146> A_RWL<145> A_RWL<144> A_RWL<143> A_RWL<142> A_RWL<141> A_RWL<140> A_RWL<139> A_RWL<138> A_RWL<137> A_RWL<136> A_RWL<135> A_RWL<134> A_RWL<133> A_RWL<132> A_RWL<131> A_RWL<130> A_RWL<129> A_RWL<128> A_RWL<127> A_RWL<126> A_RWL<125> A_RWL<124> A_RWL<123> A_RWL<122> A_RWL<121> A_RWL<120> A_RWL<119> A_RWL<118> A_RWL<117> A_RWL<116> A_RWL<115> A_RWL<114> A_RWL<113> A_RWL<112> A_RWL<111> A_RWL<110> A_RWL<109> A_RWL<108> A_RWL<107> A_RWL<106> A_RWL<105> A_RWL<104> A_RWL<103> A_RWL<102> A_RWL<101> A_RWL<100> A_RWL<99> A_RWL<98> A_RWL<97> A_RWL<96> A_RWL<95> A_RWL<94> A_RWL<93> A_RWL<92> A_RWL<91> A_RWL<90> A_RWL<89> A_RWL<88> A_RWL<87> A_RWL<86> A_RWL<85> A_RWL<84> A_RWL<83> A_RWL<82> A_RWL<81> A_RWL<80> A_RWL<79> A_RWL<78> A_RWL<77> A_RWL<76> A_RWL<75> A_RWL<74> A_RWL<73> A_RWL<72> A_RWL<71> A_RWL<70> A_RWL<69> A_RWL<68> A_RWL<67> A_RWL<66> A_RWL<65> A_RWL<64> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE VSS
+XRAM<32> A_BLC<61> A_BLC<60> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<61> A_BLT<60> A_BLT_TOP<1> A_BLT_TOP<0> A_LWL<511> A_LWL<510> A_LWL<509> A_LWL<508> A_LWL<507> A_LWL<506> A_LWL<505> A_LWL<504> A_LWL<503> A_LWL<502> A_LWL<501> A_LWL<500> A_LWL<499> A_LWL<498> A_LWL<497> A_LWL<496> A_RWL<511> A_RWL<510> A_RWL<509> A_RWL<508> A_RWL<507> A_RWL<506> A_RWL<505> A_RWL<504> A_RWL<503> A_RWL<502> A_RWL<501> A_RWL<500> A_RWL<499> A_RWL<498> A_RWL<497> A_RWL<496> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM
+XRAM<31> A_BLC<59> A_BLC<58> A_BLC<61> A_BLC<60> A_BLT<59> A_BLT<58> A_BLT<61> A_BLT<60> A_LWL<495> A_LWL<494> A_LWL<493> A_LWL<492> A_LWL<491> A_LWL<490> A_LWL<489> A_LWL<488> A_LWL<487> A_LWL<486> A_LWL<485> A_LWL<484> A_LWL<483> A_LWL<482> A_LWL<481> A_LWL<480> A_RWL<495> A_RWL<494> A_RWL<493> A_RWL<492> A_RWL<491> A_RWL<490> A_RWL<489> A_RWL<488> A_RWL<487> A_RWL<486> A_RWL<485> A_RWL<484> A_RWL<483> A_RWL<482> A_RWL<481> A_RWL<480> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM
+XRAM<30> A_BLC<57> A_BLC<56> A_BLC<59> A_BLC<58> A_BLT<57> A_BLT<56> A_BLT<59> A_BLT<58> A_LWL<479> A_LWL<478> A_LWL<477> A_LWL<476> A_LWL<475> A_LWL<474> A_LWL<473> A_LWL<472> A_LWL<471> A_LWL<470> A_LWL<469> A_LWL<468> A_LWL<467> A_LWL<466> A_LWL<465> A_LWL<464> A_RWL<479> A_RWL<478> A_RWL<477> A_RWL<476> A_RWL<475> A_RWL<474> A_RWL<473> A_RWL<472> A_RWL<471> A_RWL<470> A_RWL<469> A_RWL<468> A_RWL<467> A_RWL<466> A_RWL<465> A_RWL<464> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM
+XRAM<29> A_BLC<55> A_BLC<54> A_BLC<57> A_BLC<56> A_BLT<55> A_BLT<54> A_BLT<57> A_BLT<56> A_LWL<463> A_LWL<462> A_LWL<461> A_LWL<460> A_LWL<459> A_LWL<458> A_LWL<457> A_LWL<456> A_LWL<455> A_LWL<454> A_LWL<453> A_LWL<452> A_LWL<451> A_LWL<450> A_LWL<449> A_LWL<448> A_RWL<463> A_RWL<462> A_RWL<461> A_RWL<460> A_RWL<459> A_RWL<458> A_RWL<457> A_RWL<456> A_RWL<455> A_RWL<454> A_RWL<453> A_RWL<452> A_RWL<451> A_RWL<450> A_RWL<449> A_RWL<448> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM
+XRAM<28> A_BLC<53> A_BLC<52> A_BLC<55> A_BLC<54> A_BLT<53> A_BLT<52> A_BLT<55> A_BLT<54> A_LWL<447> A_LWL<446> A_LWL<445> A_LWL<444> A_LWL<443> A_LWL<442> A_LWL<441> A_LWL<440> A_LWL<439> A_LWL<438> A_LWL<437> A_LWL<436> A_LWL<435> A_LWL<434> A_LWL<433> A_LWL<432> A_RWL<447> A_RWL<446> A_RWL<445> A_RWL<444> A_RWL<443> A_RWL<442> A_RWL<441> A_RWL<440> A_RWL<439> A_RWL<438> A_RWL<437> A_RWL<436> A_RWL<435> A_RWL<434> A_RWL<433> A_RWL<432> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM
+XRAM<27> A_BLC<51> A_BLC<50> A_BLC<53> A_BLC<52> A_BLT<51> A_BLT<50> A_BLT<53> A_BLT<52> A_LWL<431> A_LWL<430> A_LWL<429> A_LWL<428> A_LWL<427> A_LWL<426> A_LWL<425> A_LWL<424> A_LWL<423> A_LWL<422> A_LWL<421> A_LWL<420> A_LWL<419> A_LWL<418> A_LWL<417> A_LWL<416> A_RWL<431> A_RWL<430> A_RWL<429> A_RWL<428> A_RWL<427> A_RWL<426> A_RWL<425> A_RWL<424> A_RWL<423> A_RWL<422> A_RWL<421> A_RWL<420> A_RWL<419> A_RWL<418> A_RWL<417> A_RWL<416> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM
+XRAM<26> A_BLC<49> A_BLC<48> A_BLC<51> A_BLC<50> A_BLT<49> A_BLT<48> A_BLT<51> A_BLT<50> A_LWL<415> A_LWL<414> A_LWL<413> A_LWL<412> A_LWL<411> A_LWL<410> A_LWL<409> A_LWL<408> A_LWL<407> A_LWL<406> A_LWL<405> A_LWL<404> A_LWL<403> A_LWL<402> A_LWL<401> A_LWL<400> A_RWL<415> A_RWL<414> A_RWL<413> A_RWL<412> A_RWL<411> A_RWL<410> A_RWL<409> A_RWL<408> A_RWL<407> A_RWL<406> A_RWL<405> A_RWL<404> A_RWL<403> A_RWL<402> A_RWL<401> A_RWL<400> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM
+XRAM<25> A_BLC<47> A_BLC<46> A_BLC<49> A_BLC<48> A_BLT<47> A_BLT<46> A_BLT<49> A_BLT<48> A_LWL<399> A_LWL<398> A_LWL<397> A_LWL<396> A_LWL<395> A_LWL<394> A_LWL<393> A_LWL<392> A_LWL<391> A_LWL<390> A_LWL<389> A_LWL<388> A_LWL<387> A_LWL<386> A_LWL<385> A_LWL<384> A_RWL<399> A_RWL<398> A_RWL<397> A_RWL<396> A_RWL<395> A_RWL<394> A_RWL<393> A_RWL<392> A_RWL<391> A_RWL<390> A_RWL<389> A_RWL<388> A_RWL<387> A_RWL<386> A_RWL<385> A_RWL<384> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM
+XRAM<24> A_BLC<45> A_BLC<44> A_BLC<47> A_BLC<46> A_BLT<45> A_BLT<44> A_BLT<47> A_BLT<46> A_LWL<383> A_LWL<382> A_LWL<381> A_LWL<380> A_LWL<379> A_LWL<378> A_LWL<377> A_LWL<376> A_LWL<375> A_LWL<374> A_LWL<373> A_LWL<372> A_LWL<371> A_LWL<370> A_LWL<369> A_LWL<368> A_RWL<383> A_RWL<382> A_RWL<381> A_RWL<380> A_RWL<379> A_RWL<378> A_RWL<377> A_RWL<376> A_RWL<375> A_RWL<374> A_RWL<373> A_RWL<372> A_RWL<371> A_RWL<370> A_RWL<369> A_RWL<368> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM
+XRAM<23> A_BLC<43> A_BLC<42> A_BLC<45> A_BLC<44> A_BLT<43> A_BLT<42> A_BLT<45> A_BLT<44> A_LWL<367> A_LWL<366> A_LWL<365> A_LWL<364> A_LWL<363> A_LWL<362> A_LWL<361> A_LWL<360> A_LWL<359> A_LWL<358> A_LWL<357> A_LWL<356> A_LWL<355> A_LWL<354> A_LWL<353> A_LWL<352> A_RWL<367> A_RWL<366> A_RWL<365> A_RWL<364> A_RWL<363> A_RWL<362> A_RWL<361> A_RWL<360> A_RWL<359> A_RWL<358> A_RWL<357> A_RWL<356> A_RWL<355> A_RWL<354> A_RWL<353> A_RWL<352> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM
+XRAM<22> A_BLC<41> A_BLC<40> A_BLC<43> A_BLC<42> A_BLT<41> A_BLT<40> A_BLT<43> A_BLT<42> A_LWL<351> A_LWL<350> A_LWL<349> A_LWL<348> A_LWL<347> A_LWL<346> A_LWL<345> A_LWL<344> A_LWL<343> A_LWL<342> A_LWL<341> A_LWL<340> A_LWL<339> A_LWL<338> A_LWL<337> A_LWL<336> A_RWL<351> A_RWL<350> A_RWL<349> A_RWL<348> A_RWL<347> A_RWL<346> A_RWL<345> A_RWL<344> A_RWL<343> A_RWL<342> A_RWL<341> A_RWL<340> A_RWL<339> A_RWL<338> A_RWL<337> A_RWL<336> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM
+XRAM<21> A_BLC<39> A_BLC<38> A_BLC<41> A_BLC<40> A_BLT<39> A_BLT<38> A_BLT<41> A_BLT<40> A_LWL<335> A_LWL<334> A_LWL<333> A_LWL<332> A_LWL<331> A_LWL<330> A_LWL<329> A_LWL<328> A_LWL<327> A_LWL<326> A_LWL<325> A_LWL<324> A_LWL<323> A_LWL<322> A_LWL<321> A_LWL<320> A_RWL<335> A_RWL<334> A_RWL<333> A_RWL<332> A_RWL<331> A_RWL<330> A_RWL<329> A_RWL<328> A_RWL<327> A_RWL<326> A_RWL<325> A_RWL<324> A_RWL<323> A_RWL<322> A_RWL<321> A_RWL<320> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM
+XRAM<20> A_BLC<37> A_BLC<36> A_BLC<39> A_BLC<38> A_BLT<37> A_BLT<36> A_BLT<39> A_BLT<38> A_LWL<319> A_LWL<318> A_LWL<317> A_LWL<316> A_LWL<315> A_LWL<314> A_LWL<313> A_LWL<312> A_LWL<311> A_LWL<310> A_LWL<309> A_LWL<308> A_LWL<307> A_LWL<306> A_LWL<305> A_LWL<304> A_RWL<319> A_RWL<318> A_RWL<317> A_RWL<316> A_RWL<315> A_RWL<314> A_RWL<313> A_RWL<312> A_RWL<311> A_RWL<310> A_RWL<309> A_RWL<308> A_RWL<307> A_RWL<306> A_RWL<305> A_RWL<304> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM
+XRAM<19> A_BLC<35> A_BLC<34> A_BLC<37> A_BLC<36> A_BLT<35> A_BLT<34> A_BLT<37> A_BLT<36> A_LWL<303> A_LWL<302> A_LWL<301> A_LWL<300> A_LWL<299> A_LWL<298> A_LWL<297> A_LWL<296> A_LWL<295> A_LWL<294> A_LWL<293> A_LWL<292> A_LWL<291> A_LWL<290> A_LWL<289> A_LWL<288> A_RWL<303> A_RWL<302> A_RWL<301> A_RWL<300> A_RWL<299> A_RWL<298> A_RWL<297> A_RWL<296> A_RWL<295> A_RWL<294> A_RWL<293> A_RWL<292> A_RWL<291> A_RWL<290> A_RWL<289> A_RWL<288> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM
+XRAM<18> A_BLC<33> A_BLC<32> A_BLC<35> A_BLC<34> A_BLT<33> A_BLT<32> A_BLT<35> A_BLT<34> A_LWL<287> A_LWL<286> A_LWL<285> A_LWL<284> A_LWL<283> A_LWL<282> A_LWL<281> A_LWL<280> A_LWL<279> A_LWL<278> A_LWL<277> A_LWL<276> A_LWL<275> A_LWL<274> A_LWL<273> A_LWL<272> A_RWL<287> A_RWL<286> A_RWL<285> A_RWL<284> A_RWL<283> A_RWL<282> A_RWL<281> A_RWL<280> A_RWL<279> A_RWL<278> A_RWL<277> A_RWL<276> A_RWL<275> A_RWL<274> A_RWL<273> A_RWL<272> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM
+XRAM<17> A_BLC<31> A_BLC<30> A_BLC<33> A_BLC<32> A_BLT<31> A_BLT<30> A_BLT<33> A_BLT<32> A_LWL<271> A_LWL<270> A_LWL<269> A_LWL<268> A_LWL<267> A_LWL<266> A_LWL<265> A_LWL<264> A_LWL<263> A_LWL<262> A_LWL<261> A_LWL<260> A_LWL<259> A_LWL<258> A_LWL<257> A_LWL<256> A_RWL<271> A_RWL<270> A_RWL<269> A_RWL<268> A_RWL<267> A_RWL<266> A_RWL<265> A_RWL<264> A_RWL<263> A_RWL<262> A_RWL<261> A_RWL<260> A_RWL<259> A_RWL<258> A_RWL<257> A_RWL<256> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM
+XRAM<16> A_BLC<29> A_BLC<28> A_BLC<31> A_BLC<30> A_BLT<29> A_BLT<28> A_BLT<31> A_BLT<30> A_LWL<255> A_LWL<254> A_LWL<253> A_LWL<252> A_LWL<251> A_LWL<250> A_LWL<249> A_LWL<248> A_LWL<247> A_LWL<246> A_LWL<245> A_LWL<244> A_LWL<243> A_LWL<242> A_LWL<241> A_LWL<240> A_RWL<255> A_RWL<254> A_RWL<253> A_RWL<252> A_RWL<251> A_RWL<250> A_RWL<249> A_RWL<248> A_RWL<247> A_RWL<246> A_RWL<245> A_RWL<244> A_RWL<243> A_RWL<242> A_RWL<241> A_RWL<240> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM
+XRAM<15> A_BLC<27> A_BLC<26> A_BLC<29> A_BLC<28> A_BLT<27> A_BLT<26> A_BLT<29> A_BLT<28> A_LWL<239> A_LWL<238> A_LWL<237> A_LWL<236> A_LWL<235> A_LWL<234> A_LWL<233> A_LWL<232> A_LWL<231> A_LWL<230> A_LWL<229> A_LWL<228> A_LWL<227> A_LWL<226> A_LWL<225> A_LWL<224> A_RWL<239> A_RWL<238> A_RWL<237> A_RWL<236> A_RWL<235> A_RWL<234> A_RWL<233> A_RWL<232> A_RWL<231> A_RWL<230> A_RWL<229> A_RWL<228> A_RWL<227> A_RWL<226> A_RWL<225> A_RWL<224> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM
+XRAM<14> A_BLC<25> A_BLC<24> A_BLC<27> A_BLC<26> A_BLT<25> A_BLT<24> A_BLT<27> A_BLT<26> A_LWL<223> A_LWL<222> A_LWL<221> A_LWL<220> A_LWL<219> A_LWL<218> A_LWL<217> A_LWL<216> A_LWL<215> A_LWL<214> A_LWL<213> A_LWL<212> A_LWL<211> A_LWL<210> A_LWL<209> A_LWL<208> A_RWL<223> A_RWL<222> A_RWL<221> A_RWL<220> A_RWL<219> A_RWL<218> A_RWL<217> A_RWL<216> A_RWL<215> A_RWL<214> A_RWL<213> A_RWL<212> A_RWL<211> A_RWL<210> A_RWL<209> A_RWL<208> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM
+XRAM<13> A_BLC<23> A_BLC<22> A_BLC<25> A_BLC<24> A_BLT<23> A_BLT<22> A_BLT<25> A_BLT<24> A_LWL<207> A_LWL<206> A_LWL<205> A_LWL<204> A_LWL<203> A_LWL<202> A_LWL<201> A_LWL<200> A_LWL<199> A_LWL<198> A_LWL<197> A_LWL<196> A_LWL<195> A_LWL<194> A_LWL<193> A_LWL<192> A_RWL<207> A_RWL<206> A_RWL<205> A_RWL<204> A_RWL<203> A_RWL<202> A_RWL<201> A_RWL<200> A_RWL<199> A_RWL<198> A_RWL<197> A_RWL<196> A_RWL<195> A_RWL<194> A_RWL<193> A_RWL<192> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM
+XRAM<12> A_BLC<21> A_BLC<20> A_BLC<23> A_BLC<22> A_BLT<21> A_BLT<20> A_BLT<23> A_BLT<22> A_LWL<191> A_LWL<190> A_LWL<189> A_LWL<188> A_LWL<187> A_LWL<186> A_LWL<185> A_LWL<184> A_LWL<183> A_LWL<182> A_LWL<181> A_LWL<180> A_LWL<179> A_LWL<178> A_LWL<177> A_LWL<176> A_RWL<191> A_RWL<190> A_RWL<189> A_RWL<188> A_RWL<187> A_RWL<186> A_RWL<185> A_RWL<184> A_RWL<183> A_RWL<182> A_RWL<181> A_RWL<180> A_RWL<179> A_RWL<178> A_RWL<177> A_RWL<176> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM
+XRAM<11> A_BLC<19> A_BLC<18> A_BLC<21> A_BLC<20> A_BLT<19> A_BLT<18> A_BLT<21> A_BLT<20> A_LWL<175> A_LWL<174> A_LWL<173> A_LWL<172> A_LWL<171> A_LWL<170> A_LWL<169> A_LWL<168> A_LWL<167> A_LWL<166> A_LWL<165> A_LWL<164> A_LWL<163> A_LWL<162> A_LWL<161> A_LWL<160> A_RWL<175> A_RWL<174> A_RWL<173> A_RWL<172> A_RWL<171> A_RWL<170> A_RWL<169> A_RWL<168> A_RWL<167> A_RWL<166> A_RWL<165> A_RWL<164> A_RWL<163> A_RWL<162> A_RWL<161> A_RWL<160> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM
+XRAM<10> A_BLC<17> A_BLC<16> A_BLC<19> A_BLC<18> A_BLT<17> A_BLT<16> A_BLT<19> A_BLT<18> A_LWL<159> A_LWL<158> A_LWL<157> A_LWL<156> A_LWL<155> A_LWL<154> A_LWL<153> A_LWL<152> A_LWL<151> A_LWL<150> A_LWL<149> A_LWL<148> A_LWL<147> A_LWL<146> A_LWL<145> A_LWL<144> A_RWL<159> A_RWL<158> A_RWL<157> A_RWL<156> A_RWL<155> A_RWL<154> A_RWL<153> A_RWL<152> A_RWL<151> A_RWL<150> A_RWL<149> A_RWL<148> A_RWL<147> A_RWL<146> A_RWL<145> A_RWL<144> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM
+XRAM<9> A_BLC<15> A_BLC<14> A_BLC<17> A_BLC<16> A_BLT<15> A_BLT<14> A_BLT<17> A_BLT<16> A_LWL<143> A_LWL<142> A_LWL<141> A_LWL<140> A_LWL<139> A_LWL<138> A_LWL<137> A_LWL<136> A_LWL<135> A_LWL<134> A_LWL<133> A_LWL<132> A_LWL<131> A_LWL<130> A_LWL<129> A_LWL<128> A_RWL<143> A_RWL<142> A_RWL<141> A_RWL<140> A_RWL<139> A_RWL<138> A_RWL<137> A_RWL<136> A_RWL<135> A_RWL<134> A_RWL<133> A_RWL<132> A_RWL<131> A_RWL<130> A_RWL<129> A_RWL<128> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM
+XRAM<8> A_BLC<13> A_BLC<12> A_BLC<15> A_BLC<14> A_BLT<13> A_BLT<12> A_BLT<15> A_BLT<14> A_LWL<127> A_LWL<126> A_LWL<125> A_LWL<124> A_LWL<123> A_LWL<122> A_LWL<121> A_LWL<120> A_LWL<119> A_LWL<118> A_LWL<117> A_LWL<116> A_LWL<115> A_LWL<114> A_LWL<113> A_LWL<112> A_RWL<127> A_RWL<126> A_RWL<125> A_RWL<124> A_RWL<123> A_RWL<122> A_RWL<121> A_RWL<120> A_RWL<119> A_RWL<118> A_RWL<117> A_RWL<116> A_RWL<115> A_RWL<114> A_RWL<113> A_RWL<112> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM
+XRAM<7> A_BLC<11> A_BLC<10> A_BLC<13> A_BLC<12> A_BLT<11> A_BLT<10> A_BLT<13> A_BLT<12> A_LWL<111> A_LWL<110> A_LWL<109> A_LWL<108> A_LWL<107> A_LWL<106> A_LWL<105> A_LWL<104> A_LWL<103> A_LWL<102> A_LWL<101> A_LWL<100> A_LWL<99> A_LWL<98> A_LWL<97> A_LWL<96> A_RWL<111> A_RWL<110> A_RWL<109> A_RWL<108> A_RWL<107> A_RWL<106> A_RWL<105> A_RWL<104> A_RWL<103> A_RWL<102> A_RWL<101> A_RWL<100> A_RWL<99> A_RWL<98> A_RWL<97> A_RWL<96> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM
+XRAM<6> A_BLC<9> A_BLC<8> A_BLC<11> A_BLC<10> A_BLT<9> A_BLT<8> A_BLT<11> A_BLT<10> A_LWL<95> A_LWL<94> A_LWL<93> A_LWL<92> A_LWL<91> A_LWL<90> A_LWL<89> A_LWL<88> A_LWL<87> A_LWL<86> A_LWL<85> A_LWL<84> A_LWL<83> A_LWL<82> A_LWL<81> A_LWL<80> A_RWL<95> A_RWL<94> A_RWL<93> A_RWL<92> A_RWL<91> A_RWL<90> A_RWL<89> A_RWL<88> A_RWL<87> A_RWL<86> A_RWL<85> A_RWL<84> A_RWL<83> A_RWL<82> A_RWL<81> A_RWL<80> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM
+XRAM<5> A_BLC<7> A_BLC<6> A_BLC<9> A_BLC<8> A_BLT<7> A_BLT<6> A_BLT<9> A_BLT<8> A_LWL<79> A_LWL<78> A_LWL<77> A_LWL<76> A_LWL<75> A_LWL<74> A_LWL<73> A_LWL<72> A_LWL<71> A_LWL<70> A_LWL<69> A_LWL<68> A_LWL<67> A_LWL<66> A_LWL<65> A_LWL<64> A_RWL<79> A_RWL<78> A_RWL<77> A_RWL<76> A_RWL<75> A_RWL<74> A_RWL<73> A_RWL<72> A_RWL<71> A_RWL<70> A_RWL<69> A_RWL<68> A_RWL<67> A_RWL<66> A_RWL<65> A_RWL<64> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM
+XRAM<4> A_BLC<5> A_BLC<4> A_BLC<7> A_BLC<6> A_BLT<5> A_BLT<4> A_BLT<7> A_BLT<6> A_LWL<63> A_LWL<62> A_LWL<61> A_LWL<60> A_LWL<59> A_LWL<58> A_LWL<57> A_LWL<56> A_LWL<55> A_LWL<54> A_LWL<53> A_LWL<52> A_LWL<51> A_LWL<50> A_LWL<49> A_LWL<48> A_RWL<63> A_RWL<62> A_RWL<61> A_RWL<60> A_RWL<59> A_RWL<58> A_RWL<57> A_RWL<56> A_RWL<55> A_RWL<54> A_RWL<53> A_RWL<52> A_RWL<51> A_RWL<50> A_RWL<49> A_RWL<48> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM
+XRAM<3> A_BLC<3> A_BLC<2> A_BLC<5> A_BLC<4> A_BLT<3> A_BLT<2> A_BLT<5> A_BLT<4> A_LWL<47> A_LWL<46> A_LWL<45> A_LWL<44> A_LWL<43> A_LWL<42> A_LWL<41> A_LWL<40> A_LWL<39> A_LWL<38> A_LWL<37> A_LWL<36> A_LWL<35> A_LWL<34> A_LWL<33> A_LWL<32> A_RWL<47> A_RWL<46> A_RWL<45> A_RWL<44> A_RWL<43> A_RWL<42> A_RWL<41> A_RWL<40> A_RWL<39> A_RWL<38> A_RWL<37> A_RWL<36> A_RWL<35> A_RWL<34> A_RWL<33> A_RWL<32> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM
+XRAM<2> A_BLC<1> A_BLC<0> A_BLC<3> A_BLC<2> A_BLT<1> A_BLT<0> A_BLT<3> A_BLT<2> A_LWL<31> A_LWL<30> A_LWL<29> A_LWL<28> A_LWL<27> A_LWL<26> A_LWL<25> A_LWL<24> A_LWL<23> A_LWL<22> A_LWL<21> A_LWL<20> A_LWL<19> A_LWL<18> A_LWL<17> A_LWL<16> A_RWL<31> A_RWL<30> A_RWL<29> A_RWL<28> A_RWL<27> A_RWL<26> A_RWL<25> A_RWL<24> A_RWL<23> A_RWL<22> A_RWL<21> A_RWL<20> A_RWL<19> A_RWL<18> A_RWL<17> A_RWL<16> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM
+XRAM<1> A_BLC_BOT<1> A_BLC_BOT<0> A_BLC<1> A_BLC<0> A_BLT_BOT<1> A_BLT_BOT<0> A_BLT<1> A_BLT<0> A_LWL<15> A_LWL<14> A_LWL<13> A_LWL<12> A_LWL<11> A_LWL<10> A_LWL<9> A_LWL<8> A_LWL<7> A_LWL<6> A_LWL<5> A_LWL<4> A_LWL<3> A_LWL<2> A_LWL<1> A_LWL<0> A_RWL<15> A_RWL<14> A_RWL<13> A_RWL<12> A_RWL<11> A_RWL<10> A_RWL<9> A_RWL<8> A_RWL<7> A_RWL<6> A_RWL<5> A_RWL<4> A_RWL<3> A_RWL<2> A_RWL<1> A_RWL<0> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_SRAM
+XEDGE<1> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT_TOP<1> A_BLT_TOP<0> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_TB
+XEDGE<0> A_BLC_BOT<1> A_BLC_BOT<0> A_BLT_BOT<1> A_BLT_BOT<0> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_TB
+.ENDS
+
+
+
+
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_MATRIX_pcell_1 A_BLC<31> A_BLC<30> A_BLC<29> A_BLC<28> A_BLC<27> A_BLC<26> A_BLC<25> A_BLC<24> A_BLC<23> A_BLC<22> A_BLC<21> A_BLC<20> A_BLC<19> A_BLC<18> A_BLC<17> A_BLC<16> A_BLC<15> A_BLC<14> A_BLC<13> A_BLC<12> A_BLC<11> A_BLC<10> A_BLC<9> A_BLC<8> A_BLC<7> A_BLC<6> A_BLC<5> A_BLC<4> A_BLC<3> A_BLC<2> A_BLC<1> A_BLC<0> A_BLT<31> A_BLT<30> A_BLT<29> A_BLT<28> A_BLT<27> A_BLT<26> A_BLT<25> A_BLT<24> A_BLT<23> A_BLT<22> A_BLT<21> A_BLT<20> A_BLT<19> A_BLT<18> A_BLT<17> A_BLT<16> A_BLT<15> A_BLT<14> A_BLT<13> A_BLT<12> A_BLT<11> A_BLT<10> A_BLT<9> A_BLT<8> A_BLT<7> A_BLT<6> A_BLT<5> A_BLT<4> A_BLT<3> A_BLT<2> A_BLT<1> A_BLT<0> A_WL<511> A_WL<510> A_WL<509> A_WL<508> A_WL<507> A_WL<506> A_WL<505> A_WL<504> A_WL<503> A_WL<502> A_WL<501> A_WL<500> A_WL<499> A_WL<498> A_WL<497> A_WL<496> A_WL<495> A_WL<494> A_WL<493> A_WL<492> A_WL<491> A_WL<490> A_WL<489> A_WL<488> A_WL<487> A_WL<486> A_WL<485> A_WL<484> A_WL<483> A_WL<482> A_WL<481> A_WL<480> A_WL<479> A_WL<478> A_WL<477> A_WL<476> A_WL<475> A_WL<474> A_WL<473> A_WL<472> A_WL<471> A_WL<470> A_WL<469> A_WL<468> A_WL<467> A_WL<466> A_WL<465> A_WL<464> A_WL<463> A_WL<462> A_WL<461> A_WL<460> A_WL<459> A_WL<458> A_WL<457> A_WL<456> A_WL<455> A_WL<454> A_WL<453> A_WL<452> A_WL<451> A_WL<450> A_WL<449> A_WL<448> A_WL<447> A_WL<446> A_WL<445> A_WL<444> A_WL<443> A_WL<442> A_WL<441> A_WL<440> A_WL<439> A_WL<438> A_WL<437> A_WL<436> A_WL<435> A_WL<434> A_WL<433> A_WL<432> A_WL<431> A_WL<430> A_WL<429> A_WL<428> A_WL<427> A_WL<426> A_WL<425> A_WL<424> A_WL<423> A_WL<422> A_WL<421> A_WL<420> A_WL<419> A_WL<418> A_WL<417> A_WL<416> A_WL<415> A_WL<414> A_WL<413> A_WL<412> A_WL<411> A_WL<410> A_WL<409> A_WL<408> A_WL<407> A_WL<406> A_WL<405> A_WL<404> A_WL<403> A_WL<402> A_WL<401> A_WL<400> A_WL<399> A_WL<398> A_WL<397> A_WL<396> A_WL<395> A_WL<394> A_WL<393> A_WL<392> A_WL<391> A_WL<390> A_WL<389> A_WL<388> A_WL<387> A_WL<386> A_WL<385> A_WL<384> A_WL<383> A_WL<382> A_WL<381> A_WL<380> A_WL<379> A_WL<378> A_WL<377> A_WL<376> A_WL<375> A_WL<374> A_WL<373> A_WL<372> A_WL<371> A_WL<370> A_WL<369> A_WL<368> A_WL<367> A_WL<366> A_WL<365> A_WL<364> A_WL<363> A_WL<362> A_WL<361> A_WL<360> A_WL<359> A_WL<358> A_WL<357> A_WL<356> A_WL<355> A_WL<354> A_WL<353> A_WL<352> A_WL<351> A_WL<350> A_WL<349> A_WL<348> A_WL<347> A_WL<346> A_WL<345> A_WL<344> A_WL<343> A_WL<342> A_WL<341> A_WL<340> A_WL<339> A_WL<338> A_WL<337> A_WL<336> A_WL<335> A_WL<334> A_WL<333> A_WL<332> A_WL<331> A_WL<330> A_WL<329> A_WL<328> A_WL<327> A_WL<326> A_WL<325> A_WL<324> A_WL<323> A_WL<322> A_WL<321> A_WL<320> A_WL<319> A_WL<318> A_WL<317> A_WL<316> A_WL<315> A_WL<314> A_WL<313> A_WL<312> A_WL<311> A_WL<310> A_WL<309> A_WL<308> A_WL<307> A_WL<306> A_WL<305> A_WL<304> A_WL<303> A_WL<302> A_WL<301> A_WL<300> A_WL<299> A_WL<298> A_WL<297> A_WL<296> A_WL<295> A_WL<294> A_WL<293> A_WL<292> A_WL<291> A_WL<290> A_WL<289> A_WL<288> A_WL<287> A_WL<286> A_WL<285> A_WL<284> A_WL<283> A_WL<282> A_WL<281> A_WL<280> A_WL<279> A_WL<278> A_WL<277> A_WL<276> A_WL<275> A_WL<274> A_WL<273> A_WL<272> A_WL<271> A_WL<270> A_WL<269> A_WL<268> A_WL<267> A_WL<266> A_WL<265> A_WL<264> A_WL<263> A_WL<262> A_WL<261> A_WL<260> A_WL<259> A_WL<258> A_WL<257> A_WL<256> A_WL<255> A_WL<254> A_WL<253> A_WL<252> A_WL<251> A_WL<250> A_WL<249> A_WL<248> A_WL<247> A_WL<246> A_WL<245> A_WL<244> A_WL<243> A_WL<242> A_WL<241> A_WL<240> A_WL<239> A_WL<238> A_WL<237> A_WL<236> A_WL<235> A_WL<234> A_WL<233> A_WL<232> A_WL<231> A_WL<230> A_WL<229> A_WL<228> A_WL<227> A_WL<226> A_WL<225> A_WL<224> A_WL<223> A_WL<222> A_WL<221> A_WL<220> A_WL<219> A_WL<218> A_WL<217> A_WL<216> A_WL<215> A_WL<214> A_WL<213> A_WL<212> A_WL<211> A_WL<210> A_WL<209> A_WL<208> A_WL<207> A_WL<206> A_WL<205> A_WL<204> A_WL<203> A_WL<202> A_WL<201> A_WL<200> A_WL<199> A_WL<198> A_WL<197> A_WL<196> A_WL<195> A_WL<194> A_WL<193> A_WL<192> A_WL<191> A_WL<190> A_WL<189> A_WL<188> A_WL<187> A_WL<186> A_WL<185> A_WL<184> A_WL<183> A_WL<182> A_WL<181> A_WL<180> A_WL<179> A_WL<178> A_WL<177> A_WL<176> A_WL<175> A_WL<174> A_WL<173> A_WL<172> A_WL<171> A_WL<170> A_WL<169> A_WL<168> A_WL<167> A_WL<166> A_WL<165> A_WL<164> A_WL<163> A_WL<162> A_WL<161> A_WL<160> A_WL<159> A_WL<158> A_WL<157> A_WL<156> A_WL<155> A_WL<154> A_WL<153> A_WL<152> A_WL<151> A_WL<150> A_WL<149> A_WL<148> A_WL<147> A_WL<146> A_WL<145> A_WL<144> A_WL<143> A_WL<142> A_WL<141> A_WL<140> A_WL<139> A_WL<138> A_WL<137> A_WL<136> A_WL<135> A_WL<134> A_WL<133> A_WL<132> A_WL<131> A_WL<130> A_WL<129> A_WL<128> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS
+XCORNER<3> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_CORNER
+XCORNER<2> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_CORNER
+XCORNER<1> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_CORNER
+XCORNER<0> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_CORNER
+XRAMEDGE_L<31> A_WL<511> A_WL<510> A_WL<509> A_WL<508> A_WL<507> A_WL<506> A_WL<505> A_WL<504> A_WL<503> A_WL<502> A_WL<501> A_WL<500> A_WL<499> A_WL<498> A_WL<497> A_WL<496> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<30> A_WL<495> A_WL<494> A_WL<493> A_WL<492> A_WL<491> A_WL<490> A_WL<489> A_WL<488> A_WL<487> A_WL<486> A_WL<485> A_WL<484> A_WL<483> A_WL<482> A_WL<481> A_WL<480> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<29> A_WL<479> A_WL<478> A_WL<477> A_WL<476> A_WL<475> A_WL<474> A_WL<473> A_WL<472> A_WL<471> A_WL<470> A_WL<469> A_WL<468> A_WL<467> A_WL<466> A_WL<465> A_WL<464> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<28> A_WL<463> A_WL<462> A_WL<461> A_WL<460> A_WL<459> A_WL<458> A_WL<457> A_WL<456> A_WL<455> A_WL<454> A_WL<453> A_WL<452> A_WL<451> A_WL<450> A_WL<449> A_WL<448> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<27> A_WL<447> A_WL<446> A_WL<445> A_WL<444> A_WL<443> A_WL<442> A_WL<441> A_WL<440> A_WL<439> A_WL<438> A_WL<437> A_WL<436> A_WL<435> A_WL<434> A_WL<433> A_WL<432> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<26> A_WL<431> A_WL<430> A_WL<429> A_WL<428> A_WL<427> A_WL<426> A_WL<425> A_WL<424> A_WL<423> A_WL<422> A_WL<421> A_WL<420> A_WL<419> A_WL<418> A_WL<417> A_WL<416> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<25> A_WL<415> A_WL<414> A_WL<413> A_WL<412> A_WL<411> A_WL<410> A_WL<409> A_WL<408> A_WL<407> A_WL<406> A_WL<405> A_WL<404> A_WL<403> A_WL<402> A_WL<401> A_WL<400> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<24> A_WL<399> A_WL<398> A_WL<397> A_WL<396> A_WL<395> A_WL<394> A_WL<393> A_WL<392> A_WL<391> A_WL<390> A_WL<389> A_WL<388> A_WL<387> A_WL<386> A_WL<385> A_WL<384> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<23> A_WL<383> A_WL<382> A_WL<381> A_WL<380> A_WL<379> A_WL<378> A_WL<377> A_WL<376> A_WL<375> A_WL<374> A_WL<373> A_WL<372> A_WL<371> A_WL<370> A_WL<369> A_WL<368> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<22> A_WL<367> A_WL<366> A_WL<365> A_WL<364> A_WL<363> A_WL<362> A_WL<361> A_WL<360> A_WL<359> A_WL<358> A_WL<357> A_WL<356> A_WL<355> A_WL<354> A_WL<353> A_WL<352> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<21> A_WL<351> A_WL<350> A_WL<349> A_WL<348> A_WL<347> A_WL<346> A_WL<345> A_WL<344> A_WL<343> A_WL<342> A_WL<341> A_WL<340> A_WL<339> A_WL<338> A_WL<337> A_WL<336> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<20> A_WL<335> A_WL<334> A_WL<333> A_WL<332> A_WL<331> A_WL<330> A_WL<329> A_WL<328> A_WL<327> A_WL<326> A_WL<325> A_WL<324> A_WL<323> A_WL<322> A_WL<321> A_WL<320> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<19> A_WL<319> A_WL<318> A_WL<317> A_WL<316> A_WL<315> A_WL<314> A_WL<313> A_WL<312> A_WL<311> A_WL<310> A_WL<309> A_WL<308> A_WL<307> A_WL<306> A_WL<305> A_WL<304> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<18> A_WL<303> A_WL<302> A_WL<301> A_WL<300> A_WL<299> A_WL<298> A_WL<297> A_WL<296> A_WL<295> A_WL<294> A_WL<293> A_WL<292> A_WL<291> A_WL<290> A_WL<289> A_WL<288> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<17> A_WL<287> A_WL<286> A_WL<285> A_WL<284> A_WL<283> A_WL<282> A_WL<281> A_WL<280> A_WL<279> A_WL<278> A_WL<277> A_WL<276> A_WL<275> A_WL<274> A_WL<273> A_WL<272> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<16> A_WL<271> A_WL<270> A_WL<269> A_WL<268> A_WL<267> A_WL<266> A_WL<265> A_WL<264> A_WL<263> A_WL<262> A_WL<261> A_WL<260> A_WL<259> A_WL<258> A_WL<257> A_WL<256> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<15> A_WL<255> A_WL<254> A_WL<253> A_WL<252> A_WL<251> A_WL<250> A_WL<249> A_WL<248> A_WL<247> A_WL<246> A_WL<245> A_WL<244> A_WL<243> A_WL<242> A_WL<241> A_WL<240> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<14> A_WL<239> A_WL<238> A_WL<237> A_WL<236> A_WL<235> A_WL<234> A_WL<233> A_WL<232> A_WL<231> A_WL<230> A_WL<229> A_WL<228> A_WL<227> A_WL<226> A_WL<225> A_WL<224> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<13> A_WL<223> A_WL<222> A_WL<221> A_WL<220> A_WL<219> A_WL<218> A_WL<217> A_WL<216> A_WL<215> A_WL<214> A_WL<213> A_WL<212> A_WL<211> A_WL<210> A_WL<209> A_WL<208> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<12> A_WL<207> A_WL<206> A_WL<205> A_WL<204> A_WL<203> A_WL<202> A_WL<201> A_WL<200> A_WL<199> A_WL<198> A_WL<197> A_WL<196> A_WL<195> A_WL<194> A_WL<193> A_WL<192> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<11> A_WL<191> A_WL<190> A_WL<189> A_WL<188> A_WL<187> A_WL<186> A_WL<185> A_WL<184> A_WL<183> A_WL<182> A_WL<181> A_WL<180> A_WL<179> A_WL<178> A_WL<177> A_WL<176> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<10> A_WL<175> A_WL<174> A_WL<173> A_WL<172> A_WL<171> A_WL<170> A_WL<169> A_WL<168> A_WL<167> A_WL<166> A_WL<165> A_WL<164> A_WL<163> A_WL<162> A_WL<161> A_WL<160> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<9> A_WL<159> A_WL<158> A_WL<157> A_WL<156> A_WL<155> A_WL<154> A_WL<153> A_WL<152> A_WL<151> A_WL<150> A_WL<149> A_WL<148> A_WL<147> A_WL<146> A_WL<145> A_WL<144> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<8> A_WL<143> A_WL<142> A_WL<141> A_WL<140> A_WL<139> A_WL<138> A_WL<137> A_WL<136> A_WL<135> A_WL<134> A_WL<133> A_WL<132> A_WL<131> A_WL<130> A_WL<129> A_WL<128> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<7> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<6> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<5> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<4> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<3> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<2> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<1> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_L<0> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<31> A_IWL<8191> A_IWL<8190> A_IWL<8189> A_IWL<8188> A_IWL<8187> A_IWL<8186> A_IWL<8185> A_IWL<8184> A_IWL<8183> A_IWL<8182> A_IWL<8181> A_IWL<8180> A_IWL<8179> A_IWL<8178> A_IWL<8177> A_IWL<8176> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<30> A_IWL<8175> A_IWL<8174> A_IWL<8173> A_IWL<8172> A_IWL<8171> A_IWL<8170> A_IWL<8169> A_IWL<8168> A_IWL<8167> A_IWL<8166> A_IWL<8165> A_IWL<8164> A_IWL<8163> A_IWL<8162> A_IWL<8161> A_IWL<8160> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<29> A_IWL<8159> A_IWL<8158> A_IWL<8157> A_IWL<8156> A_IWL<8155> A_IWL<8154> A_IWL<8153> A_IWL<8152> A_IWL<8151> A_IWL<8150> A_IWL<8149> A_IWL<8148> A_IWL<8147> A_IWL<8146> A_IWL<8145> A_IWL<8144> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<28> A_IWL<8143> A_IWL<8142> A_IWL<8141> A_IWL<8140> A_IWL<8139> A_IWL<8138> A_IWL<8137> A_IWL<8136> A_IWL<8135> A_IWL<8134> A_IWL<8133> A_IWL<8132> A_IWL<8131> A_IWL<8130> A_IWL<8129> A_IWL<8128> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<27> A_IWL<8127> A_IWL<8126> A_IWL<8125> A_IWL<8124> A_IWL<8123> A_IWL<8122> A_IWL<8121> A_IWL<8120> A_IWL<8119> A_IWL<8118> A_IWL<8117> A_IWL<8116> A_IWL<8115> A_IWL<8114> A_IWL<8113> A_IWL<8112> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<26> A_IWL<8111> A_IWL<8110> A_IWL<8109> A_IWL<8108> A_IWL<8107> A_IWL<8106> A_IWL<8105> A_IWL<8104> A_IWL<8103> A_IWL<8102> A_IWL<8101> A_IWL<8100> A_IWL<8099> A_IWL<8098> A_IWL<8097> A_IWL<8096> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<25> A_IWL<8095> A_IWL<8094> A_IWL<8093> A_IWL<8092> A_IWL<8091> A_IWL<8090> A_IWL<8089> A_IWL<8088> A_IWL<8087> A_IWL<8086> A_IWL<8085> A_IWL<8084> A_IWL<8083> A_IWL<8082> A_IWL<8081> A_IWL<8080> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<24> A_IWL<8079> A_IWL<8078> A_IWL<8077> A_IWL<8076> A_IWL<8075> A_IWL<8074> A_IWL<8073> A_IWL<8072> A_IWL<8071> A_IWL<8070> A_IWL<8069> A_IWL<8068> A_IWL<8067> A_IWL<8066> A_IWL<8065> A_IWL<8064> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<23> A_IWL<8063> A_IWL<8062> A_IWL<8061> A_IWL<8060> A_IWL<8059> A_IWL<8058> A_IWL<8057> A_IWL<8056> A_IWL<8055> A_IWL<8054> A_IWL<8053> A_IWL<8052> A_IWL<8051> A_IWL<8050> A_IWL<8049> A_IWL<8048> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<22> A_IWL<8047> A_IWL<8046> A_IWL<8045> A_IWL<8044> A_IWL<8043> A_IWL<8042> A_IWL<8041> A_IWL<8040> A_IWL<8039> A_IWL<8038> A_IWL<8037> A_IWL<8036> A_IWL<8035> A_IWL<8034> A_IWL<8033> A_IWL<8032> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<21> A_IWL<8031> A_IWL<8030> A_IWL<8029> A_IWL<8028> A_IWL<8027> A_IWL<8026> A_IWL<8025> A_IWL<8024> A_IWL<8023> A_IWL<8022> A_IWL<8021> A_IWL<8020> A_IWL<8019> A_IWL<8018> A_IWL<8017> A_IWL<8016> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<20> A_IWL<8015> A_IWL<8014> A_IWL<8013> A_IWL<8012> A_IWL<8011> A_IWL<8010> A_IWL<8009> A_IWL<8008> A_IWL<8007> A_IWL<8006> A_IWL<8005> A_IWL<8004> A_IWL<8003> A_IWL<8002> A_IWL<8001> A_IWL<8000> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<19> A_IWL<7999> A_IWL<7998> A_IWL<7997> A_IWL<7996> A_IWL<7995> A_IWL<7994> A_IWL<7993> A_IWL<7992> A_IWL<7991> A_IWL<7990> A_IWL<7989> A_IWL<7988> A_IWL<7987> A_IWL<7986> A_IWL<7985> A_IWL<7984> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<18> A_IWL<7983> A_IWL<7982> A_IWL<7981> A_IWL<7980> A_IWL<7979> A_IWL<7978> A_IWL<7977> A_IWL<7976> A_IWL<7975> A_IWL<7974> A_IWL<7973> A_IWL<7972> A_IWL<7971> A_IWL<7970> A_IWL<7969> A_IWL<7968> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<17> A_IWL<7967> A_IWL<7966> A_IWL<7965> A_IWL<7964> A_IWL<7963> A_IWL<7962> A_IWL<7961> A_IWL<7960> A_IWL<7959> A_IWL<7958> A_IWL<7957> A_IWL<7956> A_IWL<7955> A_IWL<7954> A_IWL<7953> A_IWL<7952> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<16> A_IWL<7951> A_IWL<7950> A_IWL<7949> A_IWL<7948> A_IWL<7947> A_IWL<7946> A_IWL<7945> A_IWL<7944> A_IWL<7943> A_IWL<7942> A_IWL<7941> A_IWL<7940> A_IWL<7939> A_IWL<7938> A_IWL<7937> A_IWL<7936> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<15> A_IWL<7935> A_IWL<7934> A_IWL<7933> A_IWL<7932> A_IWL<7931> A_IWL<7930> A_IWL<7929> A_IWL<7928> A_IWL<7927> A_IWL<7926> A_IWL<7925> A_IWL<7924> A_IWL<7923> A_IWL<7922> A_IWL<7921> A_IWL<7920> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<14> A_IWL<7919> A_IWL<7918> A_IWL<7917> A_IWL<7916> A_IWL<7915> A_IWL<7914> A_IWL<7913> A_IWL<7912> A_IWL<7911> A_IWL<7910> A_IWL<7909> A_IWL<7908> A_IWL<7907> A_IWL<7906> A_IWL<7905> A_IWL<7904> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<13> A_IWL<7903> A_IWL<7902> A_IWL<7901> A_IWL<7900> A_IWL<7899> A_IWL<7898> A_IWL<7897> A_IWL<7896> A_IWL<7895> A_IWL<7894> A_IWL<7893> A_IWL<7892> A_IWL<7891> A_IWL<7890> A_IWL<7889> A_IWL<7888> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<12> A_IWL<7887> A_IWL<7886> A_IWL<7885> A_IWL<7884> A_IWL<7883> A_IWL<7882> A_IWL<7881> A_IWL<7880> A_IWL<7879> A_IWL<7878> A_IWL<7877> A_IWL<7876> A_IWL<7875> A_IWL<7874> A_IWL<7873> A_IWL<7872> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<11> A_IWL<7871> A_IWL<7870> A_IWL<7869> A_IWL<7868> A_IWL<7867> A_IWL<7866> A_IWL<7865> A_IWL<7864> A_IWL<7863> A_IWL<7862> A_IWL<7861> A_IWL<7860> A_IWL<7859> A_IWL<7858> A_IWL<7857> A_IWL<7856> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<10> A_IWL<7855> A_IWL<7854> A_IWL<7853> A_IWL<7852> A_IWL<7851> A_IWL<7850> A_IWL<7849> A_IWL<7848> A_IWL<7847> A_IWL<7846> A_IWL<7845> A_IWL<7844> A_IWL<7843> A_IWL<7842> A_IWL<7841> A_IWL<7840> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<9> A_IWL<7839> A_IWL<7838> A_IWL<7837> A_IWL<7836> A_IWL<7835> A_IWL<7834> A_IWL<7833> A_IWL<7832> A_IWL<7831> A_IWL<7830> A_IWL<7829> A_IWL<7828> A_IWL<7827> A_IWL<7826> A_IWL<7825> A_IWL<7824> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<8> A_IWL<7823> A_IWL<7822> A_IWL<7821> A_IWL<7820> A_IWL<7819> A_IWL<7818> A_IWL<7817> A_IWL<7816> A_IWL<7815> A_IWL<7814> A_IWL<7813> A_IWL<7812> A_IWL<7811> A_IWL<7810> A_IWL<7809> A_IWL<7808> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<7> A_IWL<7807> A_IWL<7806> A_IWL<7805> A_IWL<7804> A_IWL<7803> A_IWL<7802> A_IWL<7801> A_IWL<7800> A_IWL<7799> A_IWL<7798> A_IWL<7797> A_IWL<7796> A_IWL<7795> A_IWL<7794> A_IWL<7793> A_IWL<7792> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<6> A_IWL<7791> A_IWL<7790> A_IWL<7789> A_IWL<7788> A_IWL<7787> A_IWL<7786> A_IWL<7785> A_IWL<7784> A_IWL<7783> A_IWL<7782> A_IWL<7781> A_IWL<7780> A_IWL<7779> A_IWL<7778> A_IWL<7777> A_IWL<7776> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<5> A_IWL<7775> A_IWL<7774> A_IWL<7773> A_IWL<7772> A_IWL<7771> A_IWL<7770> A_IWL<7769> A_IWL<7768> A_IWL<7767> A_IWL<7766> A_IWL<7765> A_IWL<7764> A_IWL<7763> A_IWL<7762> A_IWL<7761> A_IWL<7760> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<4> A_IWL<7759> A_IWL<7758> A_IWL<7757> A_IWL<7756> A_IWL<7755> A_IWL<7754> A_IWL<7753> A_IWL<7752> A_IWL<7751> A_IWL<7750> A_IWL<7749> A_IWL<7748> A_IWL<7747> A_IWL<7746> A_IWL<7745> A_IWL<7744> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<3> A_IWL<7743> A_IWL<7742> A_IWL<7741> A_IWL<7740> A_IWL<7739> A_IWL<7738> A_IWL<7737> A_IWL<7736> A_IWL<7735> A_IWL<7734> A_IWL<7733> A_IWL<7732> A_IWL<7731> A_IWL<7730> A_IWL<7729> A_IWL<7728> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<2> A_IWL<7727> A_IWL<7726> A_IWL<7725> A_IWL<7724> A_IWL<7723> A_IWL<7722> A_IWL<7721> A_IWL<7720> A_IWL<7719> A_IWL<7718> A_IWL<7717> A_IWL<7716> A_IWL<7715> A_IWL<7714> A_IWL<7713> A_IWL<7712> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<1> A_IWL<7711> A_IWL<7710> A_IWL<7709> A_IWL<7708> A_IWL<7707> A_IWL<7706> A_IWL<7705> A_IWL<7704> A_IWL<7703> A_IWL<7702> A_IWL<7701> A_IWL<7700> A_IWL<7699> A_IWL<7698> A_IWL<7697> A_IWL<7696> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XRAMEDGE_R<0> A_IWL<7695> A_IWL<7694> A_IWL<7693> A_IWL<7692> A_IWL<7691> A_IWL<7690> A_IWL<7689> A_IWL<7688> A_IWL<7687> A_IWL<7686> A_IWL<7685> A_IWL<7684> A_IWL<7683> A_IWL<7682> A_IWL<7681> A_IWL<7680> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_BITKIT_16x2_EDGE_LR
+XCOL<15> A_BLC<31> A_BLC<30> A_BLC_TOP<31> A_BLC_TOP<30> A_BLT<31> A_BLT<30> A_BLT_TOP<31> A_BLT_TOP<30> A_IWL<7679> A_IWL<7678> A_IWL<7677> A_IWL<7676> A_IWL<7675> A_IWL<7674> A_IWL<7673> A_IWL<7672> A_IWL<7671> A_IWL<7670> A_IWL<7669> A_IWL<7668> A_IWL<7667> A_IWL<7666> A_IWL<7665> A_IWL<7664> A_IWL<7663> A_IWL<7662> A_IWL<7661> A_IWL<7660> A_IWL<7659> A_IWL<7658> A_IWL<7657> A_IWL<7656> A_IWL<7655> A_IWL<7654> A_IWL<7653> A_IWL<7652> A_IWL<7651> A_IWL<7650> A_IWL<7649> A_IWL<7648> A_IWL<7647> A_IWL<7646> A_IWL<7645> A_IWL<7644> A_IWL<7643> A_IWL<7642> A_IWL<7641> A_IWL<7640> A_IWL<7639> A_IWL<7638> A_IWL<7637> A_IWL<7636> A_IWL<7635> A_IWL<7634> A_IWL<7633> A_IWL<7632> A_IWL<7631> A_IWL<7630> A_IWL<7629> A_IWL<7628> A_IWL<7627> A_IWL<7626> A_IWL<7625> A_IWL<7624> A_IWL<7623> A_IWL<7622> A_IWL<7621> A_IWL<7620> A_IWL<7619> A_IWL<7618> A_IWL<7617> A_IWL<7616> A_IWL<7615> A_IWL<7614> A_IWL<7613> A_IWL<7612> A_IWL<7611> A_IWL<7610> A_IWL<7609> A_IWL<7608> A_IWL<7607> A_IWL<7606> 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A_IWL<7453> A_IWL<7452> A_IWL<7451> A_IWL<7450> A_IWL<7449> A_IWL<7448> A_IWL<7447> A_IWL<7446> A_IWL<7445> A_IWL<7444> A_IWL<7443> A_IWL<7442> A_IWL<7441> A_IWL<7440> A_IWL<7439> A_IWL<7438> A_IWL<7437> A_IWL<7436> A_IWL<7435> A_IWL<7434> A_IWL<7433> A_IWL<7432> A_IWL<7431> A_IWL<7430> A_IWL<7429> A_IWL<7428> A_IWL<7427> A_IWL<7426> A_IWL<7425> A_IWL<7424> A_IWL<7423> A_IWL<7422> A_IWL<7421> A_IWL<7420> A_IWL<7419> A_IWL<7418> A_IWL<7417> A_IWL<7416> A_IWL<7415> A_IWL<7414> A_IWL<7413> A_IWL<7412> A_IWL<7411> A_IWL<7410> A_IWL<7409> A_IWL<7408> A_IWL<7407> A_IWL<7406> A_IWL<7405> A_IWL<7404> A_IWL<7403> A_IWL<7402> A_IWL<7401> A_IWL<7400> A_IWL<7399> A_IWL<7398> A_IWL<7397> A_IWL<7396> A_IWL<7395> A_IWL<7394> A_IWL<7393> A_IWL<7392> A_IWL<7391> A_IWL<7390> A_IWL<7389> A_IWL<7388> A_IWL<7387> A_IWL<7386> A_IWL<7385> A_IWL<7384> A_IWL<7383> A_IWL<7382> A_IWL<7381> A_IWL<7380> A_IWL<7379> A_IWL<7378> A_IWL<7377> A_IWL<7376> A_IWL<7375> A_IWL<7374> A_IWL<7373> A_IWL<7372> A_IWL<7371> A_IWL<7370> A_IWL<7369> A_IWL<7368> A_IWL<7367> A_IWL<7366> A_IWL<7365> A_IWL<7364> A_IWL<7363> A_IWL<7362> A_IWL<7361> A_IWL<7360> A_IWL<7359> A_IWL<7358> A_IWL<7357> A_IWL<7356> A_IWL<7355> A_IWL<7354> A_IWL<7353> A_IWL<7352> A_IWL<7351> A_IWL<7350> A_IWL<7349> A_IWL<7348> A_IWL<7347> A_IWL<7346> A_IWL<7345> A_IWL<7344> A_IWL<7343> A_IWL<7342> A_IWL<7341> A_IWL<7340> A_IWL<7339> A_IWL<7338> A_IWL<7337> A_IWL<7336> A_IWL<7335> A_IWL<7334> A_IWL<7333> A_IWL<7332> A_IWL<7331> A_IWL<7330> A_IWL<7329> A_IWL<7328> A_IWL<7327> A_IWL<7326> A_IWL<7325> A_IWL<7324> A_IWL<7323> A_IWL<7322> A_IWL<7321> A_IWL<7320> A_IWL<7319> A_IWL<7318> A_IWL<7317> A_IWL<7316> A_IWL<7315> A_IWL<7314> A_IWL<7313> A_IWL<7312> A_IWL<7311> A_IWL<7310> A_IWL<7309> A_IWL<7308> A_IWL<7307> A_IWL<7306> A_IWL<7305> A_IWL<7304> A_IWL<7303> A_IWL<7302> A_IWL<7301> A_IWL<7300> A_IWL<7299> A_IWL<7298> A_IWL<7297> A_IWL<7296> A_IWL<7295> A_IWL<7294> A_IWL<7293> A_IWL<7292> A_IWL<7291> A_IWL<7290> A_IWL<7289> A_IWL<7288> A_IWL<7287> A_IWL<7286> A_IWL<7285> A_IWL<7284> A_IWL<7283> A_IWL<7282> A_IWL<7281> A_IWL<7280> A_IWL<7279> A_IWL<7278> A_IWL<7277> A_IWL<7276> A_IWL<7275> A_IWL<7274> A_IWL<7273> A_IWL<7272> A_IWL<7271> A_IWL<7270> A_IWL<7269> A_IWL<7268> A_IWL<7267> A_IWL<7266> A_IWL<7265> A_IWL<7264> A_IWL<7263> A_IWL<7262> A_IWL<7261> A_IWL<7260> A_IWL<7259> A_IWL<7258> A_IWL<7257> A_IWL<7256> A_IWL<7255> A_IWL<7254> A_IWL<7253> A_IWL<7252> A_IWL<7251> A_IWL<7250> A_IWL<7249> A_IWL<7248> A_IWL<7247> A_IWL<7246> A_IWL<7245> A_IWL<7244> A_IWL<7243> A_IWL<7242> A_IWL<7241> A_IWL<7240> A_IWL<7239> A_IWL<7238> A_IWL<7237> A_IWL<7236> A_IWL<7235> A_IWL<7234> A_IWL<7233> A_IWL<7232> A_IWL<7231> A_IWL<7230> A_IWL<7229> A_IWL<7228> A_IWL<7227> A_IWL<7226> A_IWL<7225> A_IWL<7224> A_IWL<7223> A_IWL<7222> A_IWL<7221> A_IWL<7220> A_IWL<7219> A_IWL<7218> A_IWL<7217> A_IWL<7216> A_IWL<7215> A_IWL<7214> A_IWL<7213> A_IWL<7212> A_IWL<7211> A_IWL<7210> A_IWL<7209> A_IWL<7208> A_IWL<7207> A_IWL<7206> A_IWL<7205> A_IWL<7204> A_IWL<7203> A_IWL<7202> A_IWL<7201> A_IWL<7200> A_IWL<7199> A_IWL<7198> A_IWL<7197> A_IWL<7196> A_IWL<7195> A_IWL<7194> A_IWL<7193> A_IWL<7192> A_IWL<7191> A_IWL<7190> A_IWL<7189> A_IWL<7188> A_IWL<7187> A_IWL<7186> A_IWL<7185> A_IWL<7184> A_IWL<7183> A_IWL<7182> A_IWL<7181> A_IWL<7180> A_IWL<7179> A_IWL<7178> A_IWL<7177> A_IWL<7176> A_IWL<7175> A_IWL<7174> A_IWL<7173> A_IWL<7172> A_IWL<7171> A_IWL<7170> A_IWL<7169> A_IWL<7168> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_COLUMN_pcell_0
+XCOL<13> A_BLC<27> A_BLC<26> A_BLC_TOP<27> A_BLC_TOP<26> A_BLT<27> A_BLT<26> A_BLT_TOP<27> A_BLT_TOP<26> A_IWL<6655> A_IWL<6654> A_IWL<6653> A_IWL<6652> A_IWL<6651> A_IWL<6650> A_IWL<6649> A_IWL<6648> A_IWL<6647> A_IWL<6646> A_IWL<6645> A_IWL<6644> A_IWL<6643> A_IWL<6642> A_IWL<6641> A_IWL<6640> A_IWL<6639> A_IWL<6638> A_IWL<6637> A_IWL<6636> A_IWL<6635> A_IWL<6634> A_IWL<6633> A_IWL<6632> A_IWL<6631> A_IWL<6630> A_IWL<6629> A_IWL<6628> A_IWL<6627> A_IWL<6626> A_IWL<6625> A_IWL<6624> A_IWL<6623> A_IWL<6622> A_IWL<6621> A_IWL<6620> A_IWL<6619> A_IWL<6618> A_IWL<6617> A_IWL<6616> A_IWL<6615> A_IWL<6614> A_IWL<6613> A_IWL<6612> A_IWL<6611> A_IWL<6610> A_IWL<6609> A_IWL<6608> A_IWL<6607> A_IWL<6606> A_IWL<6605> A_IWL<6604> A_IWL<6603> A_IWL<6602> A_IWL<6601> A_IWL<6600> A_IWL<6599> A_IWL<6598> A_IWL<6597> A_IWL<6596> A_IWL<6595> A_IWL<6594> A_IWL<6593> A_IWL<6592> A_IWL<6591> A_IWL<6590> A_IWL<6589> A_IWL<6588> A_IWL<6587> A_IWL<6586> A_IWL<6585> A_IWL<6584> A_IWL<6583> A_IWL<6582> A_IWL<6581> A_IWL<6580> A_IWL<6579> A_IWL<6578> A_IWL<6577> A_IWL<6576> A_IWL<6575> A_IWL<6574> A_IWL<6573> A_IWL<6572> A_IWL<6571> A_IWL<6570> A_IWL<6569> A_IWL<6568> A_IWL<6567> A_IWL<6566> A_IWL<6565> A_IWL<6564> A_IWL<6563> A_IWL<6562> A_IWL<6561> A_IWL<6560> A_IWL<6559> A_IWL<6558> A_IWL<6557> A_IWL<6556> A_IWL<6555> A_IWL<6554> A_IWL<6553> A_IWL<6552> A_IWL<6551> A_IWL<6550> A_IWL<6549> A_IWL<6548> A_IWL<6547> A_IWL<6546> A_IWL<6545> A_IWL<6544> A_IWL<6543> A_IWL<6542> A_IWL<6541> A_IWL<6540> A_IWL<6539> A_IWL<6538> A_IWL<6537> A_IWL<6536> A_IWL<6535> A_IWL<6534> A_IWL<6533> A_IWL<6532> A_IWL<6531> A_IWL<6530> A_IWL<6529> A_IWL<6528> A_IWL<6527> A_IWL<6526> A_IWL<6525> A_IWL<6524> A_IWL<6523> A_IWL<6522> A_IWL<6521> A_IWL<6520> A_IWL<6519> A_IWL<6518> A_IWL<6517> A_IWL<6516> A_IWL<6515> A_IWL<6514> A_IWL<6513> A_IWL<6512> A_IWL<6511> A_IWL<6510> A_IWL<6509> A_IWL<6508> A_IWL<6507> A_IWL<6506> A_IWL<6505> A_IWL<6504> A_IWL<6503> A_IWL<6502> A_IWL<6501> A_IWL<6500> A_IWL<6499> A_IWL<6498> A_IWL<6497> A_IWL<6496> A_IWL<6495> A_IWL<6494> A_IWL<6493> A_IWL<6492> A_IWL<6491> A_IWL<6490> A_IWL<6489> A_IWL<6488> A_IWL<6487> A_IWL<6486> A_IWL<6485> A_IWL<6484> A_IWL<6483> A_IWL<6482> A_IWL<6481> A_IWL<6480> A_IWL<6479> A_IWL<6478> A_IWL<6477> A_IWL<6476> A_IWL<6475> A_IWL<6474> A_IWL<6473> A_IWL<6472> A_IWL<6471> A_IWL<6470> A_IWL<6469> A_IWL<6468> A_IWL<6467> A_IWL<6466> A_IWL<6465> A_IWL<6464> A_IWL<6463> A_IWL<6462> A_IWL<6461> A_IWL<6460> A_IWL<6459> A_IWL<6458> A_IWL<6457> A_IWL<6456> A_IWL<6455> A_IWL<6454> A_IWL<6453> A_IWL<6452> A_IWL<6451> A_IWL<6450> A_IWL<6449> A_IWL<6448> A_IWL<6447> A_IWL<6446> A_IWL<6445> A_IWL<6444> A_IWL<6443> A_IWL<6442> A_IWL<6441> A_IWL<6440> A_IWL<6439> A_IWL<6438> A_IWL<6437> A_IWL<6436> A_IWL<6435> A_IWL<6434> A_IWL<6433> A_IWL<6432> A_IWL<6431> A_IWL<6430> A_IWL<6429> A_IWL<6428> A_IWL<6427> A_IWL<6426> A_IWL<6425> A_IWL<6424> A_IWL<6423> A_IWL<6422> A_IWL<6421> A_IWL<6420> A_IWL<6419> A_IWL<6418> A_IWL<6417> A_IWL<6416> A_IWL<6415> A_IWL<6414> A_IWL<6413> A_IWL<6412> A_IWL<6411> A_IWL<6410> A_IWL<6409> A_IWL<6408> A_IWL<6407> A_IWL<6406> A_IWL<6405> A_IWL<6404> A_IWL<6403> A_IWL<6402> A_IWL<6401> A_IWL<6400> A_IWL<6399> A_IWL<6398> A_IWL<6397> A_IWL<6396> A_IWL<6395> A_IWL<6394> A_IWL<6393> A_IWL<6392> A_IWL<6391> A_IWL<6390> A_IWL<6389> A_IWL<6388> A_IWL<6387> A_IWL<6386> A_IWL<6385> A_IWL<6384> A_IWL<6383> A_IWL<6382> A_IWL<6381> A_IWL<6380> A_IWL<6379> A_IWL<6378> A_IWL<6377> A_IWL<6376> A_IWL<6375> A_IWL<6374> A_IWL<6373> A_IWL<6372> A_IWL<6371> A_IWL<6370> A_IWL<6369> A_IWL<6368> A_IWL<6367> A_IWL<6366> A_IWL<6365> A_IWL<6364> A_IWL<6363> A_IWL<6362> A_IWL<6361> A_IWL<6360> A_IWL<6359> A_IWL<6358> A_IWL<6357> A_IWL<6356> A_IWL<6355> A_IWL<6354> A_IWL<6353> A_IWL<6352> A_IWL<6351> A_IWL<6350> A_IWL<6349> A_IWL<6348> A_IWL<6347> A_IWL<6346> A_IWL<6345> A_IWL<6344> A_IWL<6343> A_IWL<6342> A_IWL<6341> A_IWL<6340> A_IWL<6339> A_IWL<6338> A_IWL<6337> A_IWL<6336> A_IWL<6335> A_IWL<6334> A_IWL<6333> A_IWL<6332> A_IWL<6331> A_IWL<6330> A_IWL<6329> A_IWL<6328> A_IWL<6327> A_IWL<6326> A_IWL<6325> A_IWL<6324> A_IWL<6323> A_IWL<6322> A_IWL<6321> A_IWL<6320> A_IWL<6319> A_IWL<6318> A_IWL<6317> A_IWL<6316> A_IWL<6315> A_IWL<6314> A_IWL<6313> A_IWL<6312> A_IWL<6311> A_IWL<6310> A_IWL<6309> A_IWL<6308> A_IWL<6307> A_IWL<6306> A_IWL<6305> A_IWL<6304> A_IWL<6303> A_IWL<6302> A_IWL<6301> A_IWL<6300> A_IWL<6299> A_IWL<6298> A_IWL<6297> A_IWL<6296> A_IWL<6295> A_IWL<6294> A_IWL<6293> A_IWL<6292> A_IWL<6291> A_IWL<6290> A_IWL<6289> A_IWL<6288> A_IWL<6287> A_IWL<6286> A_IWL<6285> A_IWL<6284> A_IWL<6283> A_IWL<6282> A_IWL<6281> A_IWL<6280> A_IWL<6279> A_IWL<6278> A_IWL<6277> A_IWL<6276> A_IWL<6275> A_IWL<6274> A_IWL<6273> A_IWL<6272> A_IWL<6271> A_IWL<6270> A_IWL<6269> A_IWL<6268> A_IWL<6267> A_IWL<6266> A_IWL<6265> A_IWL<6264> A_IWL<6263> A_IWL<6262> A_IWL<6261> A_IWL<6260> A_IWL<6259> A_IWL<6258> A_IWL<6257> A_IWL<6256> A_IWL<6255> A_IWL<6254> A_IWL<6253> A_IWL<6252> A_IWL<6251> A_IWL<6250> A_IWL<6249> A_IWL<6248> A_IWL<6247> A_IWL<6246> A_IWL<6245> A_IWL<6244> A_IWL<6243> A_IWL<6242> A_IWL<6241> A_IWL<6240> A_IWL<6239> A_IWL<6238> A_IWL<6237> A_IWL<6236> A_IWL<6235> A_IWL<6234> A_IWL<6233> A_IWL<6232> A_IWL<6231> A_IWL<6230> A_IWL<6229> A_IWL<6228> A_IWL<6227> A_IWL<6226> A_IWL<6225> A_IWL<6224> A_IWL<6223> A_IWL<6222> A_IWL<6221> A_IWL<6220> A_IWL<6219> A_IWL<6218> A_IWL<6217> A_IWL<6216> A_IWL<6215> A_IWL<6214> A_IWL<6213> A_IWL<6212> A_IWL<6211> A_IWL<6210> A_IWL<6209> A_IWL<6208> A_IWL<6207> A_IWL<6206> A_IWL<6205> A_IWL<6204> A_IWL<6203> A_IWL<6202> A_IWL<6201> A_IWL<6200> A_IWL<6199> A_IWL<6198> A_IWL<6197> A_IWL<6196> A_IWL<6195> A_IWL<6194> A_IWL<6193> A_IWL<6192> A_IWL<6191> A_IWL<6190> A_IWL<6189> A_IWL<6188> A_IWL<6187> A_IWL<6186> A_IWL<6185> A_IWL<6184> A_IWL<6183> A_IWL<6182> A_IWL<6181> A_IWL<6180> A_IWL<6179> A_IWL<6178> A_IWL<6177> A_IWL<6176> A_IWL<6175> A_IWL<6174> A_IWL<6173> A_IWL<6172> A_IWL<6171> A_IWL<6170> A_IWL<6169> A_IWL<6168> A_IWL<6167> A_IWL<6166> A_IWL<6165> A_IWL<6164> A_IWL<6163> A_IWL<6162> A_IWL<6161> A_IWL<6160> A_IWL<6159> A_IWL<6158> A_IWL<6157> A_IWL<6156> A_IWL<6155> A_IWL<6154> A_IWL<6153> A_IWL<6152> A_IWL<6151> A_IWL<6150> A_IWL<6149> A_IWL<6148> A_IWL<6147> A_IWL<6146> A_IWL<6145> A_IWL<6144> A_IWL<7167> A_IWL<7166> A_IWL<7165> A_IWL<7164> A_IWL<7163> A_IWL<7162> A_IWL<7161> A_IWL<7160> A_IWL<7159> A_IWL<7158> A_IWL<7157> A_IWL<7156> A_IWL<7155> A_IWL<7154> A_IWL<7153> A_IWL<7152> A_IWL<7151> A_IWL<7150> A_IWL<7149> A_IWL<7148> A_IWL<7147> A_IWL<7146> A_IWL<7145> A_IWL<7144> A_IWL<7143> A_IWL<7142> A_IWL<7141> A_IWL<7140> A_IWL<7139> A_IWL<7138> A_IWL<7137> A_IWL<7136> A_IWL<7135> A_IWL<7134> A_IWL<7133> A_IWL<7132> A_IWL<7131> A_IWL<7130> A_IWL<7129> A_IWL<7128> A_IWL<7127> A_IWL<7126> A_IWL<7125> A_IWL<7124> A_IWL<7123> A_IWL<7122> A_IWL<7121> A_IWL<7120> A_IWL<7119> A_IWL<7118> A_IWL<7117> A_IWL<7116> A_IWL<7115> A_IWL<7114> A_IWL<7113> A_IWL<7112> A_IWL<7111> A_IWL<7110> A_IWL<7109> A_IWL<7108> A_IWL<7107> A_IWL<7106> A_IWL<7105> A_IWL<7104> A_IWL<7103> A_IWL<7102> A_IWL<7101> A_IWL<7100> A_IWL<7099> A_IWL<7098> A_IWL<7097> A_IWL<7096> A_IWL<7095> A_IWL<7094> A_IWL<7093> A_IWL<7092> A_IWL<7091> A_IWL<7090> A_IWL<7089> A_IWL<7088> A_IWL<7087> A_IWL<7086> A_IWL<7085> A_IWL<7084> A_IWL<7083> A_IWL<7082> A_IWL<7081> A_IWL<7080> A_IWL<7079> A_IWL<7078> A_IWL<7077> A_IWL<7076> A_IWL<7075> A_IWL<7074> A_IWL<7073> A_IWL<7072> A_IWL<7071> A_IWL<7070> A_IWL<7069> A_IWL<7068> A_IWL<7067> A_IWL<7066> A_IWL<7065> A_IWL<7064> A_IWL<7063> A_IWL<7062> A_IWL<7061> A_IWL<7060> A_IWL<7059> A_IWL<7058> A_IWL<7057> A_IWL<7056> A_IWL<7055> A_IWL<7054> A_IWL<7053> A_IWL<7052> A_IWL<7051> A_IWL<7050> A_IWL<7049> A_IWL<7048> A_IWL<7047> A_IWL<7046> A_IWL<7045> A_IWL<7044> A_IWL<7043> A_IWL<7042> A_IWL<7041> A_IWL<7040> A_IWL<7039> A_IWL<7038> A_IWL<7037> A_IWL<7036> A_IWL<7035> A_IWL<7034> A_IWL<7033> A_IWL<7032> A_IWL<7031> A_IWL<7030> A_IWL<7029> A_IWL<7028> A_IWL<7027> A_IWL<7026> A_IWL<7025> A_IWL<7024> A_IWL<7023> A_IWL<7022> A_IWL<7021> A_IWL<7020> A_IWL<7019> A_IWL<7018> A_IWL<7017> A_IWL<7016> A_IWL<7015> A_IWL<7014> A_IWL<7013> A_IWL<7012> A_IWL<7011> A_IWL<7010> A_IWL<7009> A_IWL<7008> A_IWL<7007> A_IWL<7006> A_IWL<7005> A_IWL<7004> A_IWL<7003> A_IWL<7002> A_IWL<7001> A_IWL<7000> A_IWL<6999> A_IWL<6998> A_IWL<6997> A_IWL<6996> A_IWL<6995> A_IWL<6994> A_IWL<6993> A_IWL<6992> A_IWL<6991> A_IWL<6990> A_IWL<6989> A_IWL<6988> A_IWL<6987> A_IWL<6986> A_IWL<6985> A_IWL<6984> A_IWL<6983> A_IWL<6982> A_IWL<6981> A_IWL<6980> A_IWL<6979> A_IWL<6978> A_IWL<6977> A_IWL<6976> A_IWL<6975> A_IWL<6974> A_IWL<6973> A_IWL<6972> A_IWL<6971> A_IWL<6970> A_IWL<6969> A_IWL<6968> A_IWL<6967> A_IWL<6966> A_IWL<6965> A_IWL<6964> A_IWL<6963> A_IWL<6962> A_IWL<6961> A_IWL<6960> A_IWL<6959> A_IWL<6958> A_IWL<6957> A_IWL<6956> A_IWL<6955> A_IWL<6954> A_IWL<6953> A_IWL<6952> A_IWL<6951> A_IWL<6950> A_IWL<6949> A_IWL<6948> A_IWL<6947> A_IWL<6946> A_IWL<6945> A_IWL<6944> A_IWL<6943> A_IWL<6942> A_IWL<6941> A_IWL<6940> A_IWL<6939> A_IWL<6938> A_IWL<6937> A_IWL<6936> A_IWL<6935> A_IWL<6934> A_IWL<6933> A_IWL<6932> A_IWL<6931> A_IWL<6930> A_IWL<6929> A_IWL<6928> A_IWL<6927> A_IWL<6926> A_IWL<6925> A_IWL<6924> A_IWL<6923> A_IWL<6922> A_IWL<6921> A_IWL<6920> A_IWL<6919> A_IWL<6918> A_IWL<6917> A_IWL<6916> A_IWL<6915> A_IWL<6914> A_IWL<6913> A_IWL<6912> A_IWL<6911> A_IWL<6910> A_IWL<6909> A_IWL<6908> A_IWL<6907> A_IWL<6906> A_IWL<6905> A_IWL<6904> A_IWL<6903> A_IWL<6902> A_IWL<6901> A_IWL<6900> A_IWL<6899> A_IWL<6898> A_IWL<6897> A_IWL<6896> A_IWL<6895> A_IWL<6894> A_IWL<6893> A_IWL<6892> A_IWL<6891> A_IWL<6890> A_IWL<6889> A_IWL<6888> A_IWL<6887> A_IWL<6886> A_IWL<6885> A_IWL<6884> A_IWL<6883> A_IWL<6882> A_IWL<6881> A_IWL<6880> A_IWL<6879> A_IWL<6878> A_IWL<6877> A_IWL<6876> A_IWL<6875> A_IWL<6874> A_IWL<6873> A_IWL<6872> A_IWL<6871> A_IWL<6870> A_IWL<6869> A_IWL<6868> A_IWL<6867> A_IWL<6866> A_IWL<6865> A_IWL<6864> A_IWL<6863> A_IWL<6862> A_IWL<6861> A_IWL<6860> A_IWL<6859> A_IWL<6858> A_IWL<6857> A_IWL<6856> A_IWL<6855> A_IWL<6854> A_IWL<6853> A_IWL<6852> A_IWL<6851> A_IWL<6850> A_IWL<6849> A_IWL<6848> A_IWL<6847> A_IWL<6846> A_IWL<6845> A_IWL<6844> A_IWL<6843> A_IWL<6842> A_IWL<6841> A_IWL<6840> A_IWL<6839> A_IWL<6838> A_IWL<6837> A_IWL<6836> A_IWL<6835> A_IWL<6834> A_IWL<6833> A_IWL<6832> A_IWL<6831> A_IWL<6830> A_IWL<6829> A_IWL<6828> A_IWL<6827> A_IWL<6826> A_IWL<6825> A_IWL<6824> A_IWL<6823> A_IWL<6822> A_IWL<6821> A_IWL<6820> A_IWL<6819> A_IWL<6818> A_IWL<6817> A_IWL<6816> A_IWL<6815> A_IWL<6814> A_IWL<6813> A_IWL<6812> A_IWL<6811> A_IWL<6810> A_IWL<6809> A_IWL<6808> A_IWL<6807> A_IWL<6806> A_IWL<6805> A_IWL<6804> A_IWL<6803> A_IWL<6802> A_IWL<6801> A_IWL<6800> A_IWL<6799> A_IWL<6798> A_IWL<6797> A_IWL<6796> A_IWL<6795> A_IWL<6794> A_IWL<6793> A_IWL<6792> A_IWL<6791> A_IWL<6790> A_IWL<6789> A_IWL<6788> A_IWL<6787> A_IWL<6786> A_IWL<6785> A_IWL<6784> A_IWL<6783> A_IWL<6782> A_IWL<6781> A_IWL<6780> A_IWL<6779> A_IWL<6778> A_IWL<6777> A_IWL<6776> A_IWL<6775> A_IWL<6774> A_IWL<6773> A_IWL<6772> A_IWL<6771> A_IWL<6770> A_IWL<6769> A_IWL<6768> A_IWL<6767> A_IWL<6766> A_IWL<6765> A_IWL<6764> A_IWL<6763> A_IWL<6762> A_IWL<6761> A_IWL<6760> A_IWL<6759> A_IWL<6758> A_IWL<6757> A_IWL<6756> A_IWL<6755> A_IWL<6754> A_IWL<6753> A_IWL<6752> A_IWL<6751> A_IWL<6750> A_IWL<6749> A_IWL<6748> A_IWL<6747> A_IWL<6746> A_IWL<6745> A_IWL<6744> A_IWL<6743> A_IWL<6742> A_IWL<6741> A_IWL<6740> A_IWL<6739> A_IWL<6738> A_IWL<6737> A_IWL<6736> A_IWL<6735> A_IWL<6734> A_IWL<6733> A_IWL<6732> A_IWL<6731> A_IWL<6730> A_IWL<6729> A_IWL<6728> A_IWL<6727> A_IWL<6726> A_IWL<6725> A_IWL<6724> A_IWL<6723> A_IWL<6722> A_IWL<6721> A_IWL<6720> A_IWL<6719> A_IWL<6718> A_IWL<6717> A_IWL<6716> A_IWL<6715> A_IWL<6714> A_IWL<6713> A_IWL<6712> A_IWL<6711> A_IWL<6710> A_IWL<6709> A_IWL<6708> A_IWL<6707> A_IWL<6706> A_IWL<6705> A_IWL<6704> A_IWL<6703> A_IWL<6702> A_IWL<6701> A_IWL<6700> A_IWL<6699> A_IWL<6698> A_IWL<6697> A_IWL<6696> A_IWL<6695> A_IWL<6694> A_IWL<6693> A_IWL<6692> A_IWL<6691> A_IWL<6690> A_IWL<6689> A_IWL<6688> A_IWL<6687> A_IWL<6686> A_IWL<6685> A_IWL<6684> A_IWL<6683> A_IWL<6682> A_IWL<6681> A_IWL<6680> A_IWL<6679> A_IWL<6678> A_IWL<6677> A_IWL<6676> A_IWL<6675> A_IWL<6674> A_IWL<6673> A_IWL<6672> A_IWL<6671> A_IWL<6670> A_IWL<6669> A_IWL<6668> A_IWL<6667> A_IWL<6666> A_IWL<6665> A_IWL<6664> A_IWL<6663> A_IWL<6662> A_IWL<6661> A_IWL<6660> A_IWL<6659> A_IWL<6658> A_IWL<6657> A_IWL<6656> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_COLUMN_pcell_0
+XCOL<12> A_BLC<25> A_BLC<24> A_BLC_TOP<25> A_BLC_TOP<24> A_BLT<25> A_BLT<24> A_BLT_TOP<25> A_BLT_TOP<24> A_IWL<6143> A_IWL<6142> A_IWL<6141> A_IWL<6140> A_IWL<6139> A_IWL<6138> A_IWL<6137> A_IWL<6136> A_IWL<6135> A_IWL<6134> A_IWL<6133> A_IWL<6132> A_IWL<6131> A_IWL<6130> A_IWL<6129> A_IWL<6128> A_IWL<6127> A_IWL<6126> A_IWL<6125> A_IWL<6124> A_IWL<6123> A_IWL<6122> A_IWL<6121> A_IWL<6120> A_IWL<6119> A_IWL<6118> A_IWL<6117> A_IWL<6116> A_IWL<6115> A_IWL<6114> A_IWL<6113> A_IWL<6112> A_IWL<6111> A_IWL<6110> A_IWL<6109> A_IWL<6108> A_IWL<6107> A_IWL<6106> A_IWL<6105> A_IWL<6104> A_IWL<6103> A_IWL<6102> A_IWL<6101> A_IWL<6100> A_IWL<6099> A_IWL<6098> A_IWL<6097> A_IWL<6096> A_IWL<6095> A_IWL<6094> A_IWL<6093> A_IWL<6092> A_IWL<6091> A_IWL<6090> A_IWL<6089> A_IWL<6088> A_IWL<6087> A_IWL<6086> A_IWL<6085> A_IWL<6084> A_IWL<6083> A_IWL<6082> A_IWL<6081> A_IWL<6080> A_IWL<6079> A_IWL<6078> A_IWL<6077> A_IWL<6076> A_IWL<6075> A_IWL<6074> A_IWL<6073> A_IWL<6072> A_IWL<6071> A_IWL<6070> A_IWL<6069> A_IWL<6068> A_IWL<6067> A_IWL<6066> A_IWL<6065> A_IWL<6064> A_IWL<6063> A_IWL<6062> A_IWL<6061> A_IWL<6060> A_IWL<6059> A_IWL<6058> A_IWL<6057> A_IWL<6056> A_IWL<6055> A_IWL<6054> A_IWL<6053> A_IWL<6052> A_IWL<6051> A_IWL<6050> A_IWL<6049> A_IWL<6048> A_IWL<6047> A_IWL<6046> A_IWL<6045> A_IWL<6044> A_IWL<6043> A_IWL<6042> A_IWL<6041> A_IWL<6040> A_IWL<6039> A_IWL<6038> A_IWL<6037> A_IWL<6036> A_IWL<6035> A_IWL<6034> A_IWL<6033> A_IWL<6032> A_IWL<6031> A_IWL<6030> A_IWL<6029> A_IWL<6028> A_IWL<6027> A_IWL<6026> A_IWL<6025> A_IWL<6024> A_IWL<6023> A_IWL<6022> A_IWL<6021> A_IWL<6020> A_IWL<6019> A_IWL<6018> A_IWL<6017> A_IWL<6016> A_IWL<6015> A_IWL<6014> A_IWL<6013> A_IWL<6012> A_IWL<6011> A_IWL<6010> A_IWL<6009> A_IWL<6008> A_IWL<6007> A_IWL<6006> A_IWL<6005> A_IWL<6004> A_IWL<6003> A_IWL<6002> A_IWL<6001> A_IWL<6000> A_IWL<5999> A_IWL<5998> A_IWL<5997> A_IWL<5996> A_IWL<5995> A_IWL<5994> A_IWL<5993> A_IWL<5992> A_IWL<5991> A_IWL<5990> A_IWL<5989> A_IWL<5988> A_IWL<5987> A_IWL<5986> A_IWL<5985> A_IWL<5984> A_IWL<5983> A_IWL<5982> A_IWL<5981> A_IWL<5980> A_IWL<5979> A_IWL<5978> A_IWL<5977> A_IWL<5976> A_IWL<5975> A_IWL<5974> A_IWL<5973> A_IWL<5972> A_IWL<5971> A_IWL<5970> A_IWL<5969> A_IWL<5968> A_IWL<5967> A_IWL<5966> A_IWL<5965> A_IWL<5964> A_IWL<5963> A_IWL<5962> A_IWL<5961> A_IWL<5960> A_IWL<5959> A_IWL<5958> A_IWL<5957> A_IWL<5956> A_IWL<5955> A_IWL<5954> A_IWL<5953> A_IWL<5952> A_IWL<5951> A_IWL<5950> A_IWL<5949> A_IWL<5948> A_IWL<5947> A_IWL<5946> A_IWL<5945> A_IWL<5944> A_IWL<5943> A_IWL<5942> A_IWL<5941> A_IWL<5940> A_IWL<5939> A_IWL<5938> A_IWL<5937> A_IWL<5936> A_IWL<5935> A_IWL<5934> A_IWL<5933> A_IWL<5932> A_IWL<5931> A_IWL<5930> A_IWL<5929> A_IWL<5928> A_IWL<5927> A_IWL<5926> A_IWL<5925> A_IWL<5924> A_IWL<5923> A_IWL<5922> A_IWL<5921> A_IWL<5920> A_IWL<5919> A_IWL<5918> A_IWL<5917> A_IWL<5916> A_IWL<5915> A_IWL<5914> A_IWL<5913> A_IWL<5912> A_IWL<5911> A_IWL<5910> A_IWL<5909> A_IWL<5908> A_IWL<5907> A_IWL<5906> A_IWL<5905> A_IWL<5904> A_IWL<5903> A_IWL<5902> A_IWL<5901> A_IWL<5900> A_IWL<5899> A_IWL<5898> A_IWL<5897> A_IWL<5896> A_IWL<5895> A_IWL<5894> A_IWL<5893> A_IWL<5892> A_IWL<5891> A_IWL<5890> A_IWL<5889> A_IWL<5888> A_IWL<5887> A_IWL<5886> A_IWL<5885> A_IWL<5884> A_IWL<5883> A_IWL<5882> A_IWL<5881> A_IWL<5880> A_IWL<5879> A_IWL<5878> A_IWL<5877> A_IWL<5876> A_IWL<5875> A_IWL<5874> A_IWL<5873> A_IWL<5872> A_IWL<5871> A_IWL<5870> A_IWL<5869> A_IWL<5868> A_IWL<5867> A_IWL<5866> A_IWL<5865> A_IWL<5864> A_IWL<5863> A_IWL<5862> A_IWL<5861> A_IWL<5860> A_IWL<5859> A_IWL<5858> A_IWL<5857> A_IWL<5856> A_IWL<5855> A_IWL<5854> A_IWL<5853> A_IWL<5852> A_IWL<5851> A_IWL<5850> A_IWL<5849> A_IWL<5848> A_IWL<5847> A_IWL<5846> A_IWL<5845> A_IWL<5844> A_IWL<5843> A_IWL<5842> A_IWL<5841> A_IWL<5840> A_IWL<5839> A_IWL<5838> A_IWL<5837> A_IWL<5836> A_IWL<5835> A_IWL<5834> A_IWL<5833> A_IWL<5832> A_IWL<5831> A_IWL<5830> A_IWL<5829> A_IWL<5828> A_IWL<5827> A_IWL<5826> A_IWL<5825> A_IWL<5824> A_IWL<5823> A_IWL<5822> A_IWL<5821> A_IWL<5820> A_IWL<5819> A_IWL<5818> A_IWL<5817> A_IWL<5816> A_IWL<5815> A_IWL<5814> A_IWL<5813> A_IWL<5812> A_IWL<5811> A_IWL<5810> A_IWL<5809> A_IWL<5808> A_IWL<5807> A_IWL<5806> A_IWL<5805> A_IWL<5804> A_IWL<5803> A_IWL<5802> A_IWL<5801> A_IWL<5800> A_IWL<5799> A_IWL<5798> A_IWL<5797> A_IWL<5796> A_IWL<5795> A_IWL<5794> A_IWL<5793> A_IWL<5792> A_IWL<5791> A_IWL<5790> A_IWL<5789> A_IWL<5788> A_IWL<5787> A_IWL<5786> A_IWL<5785> A_IWL<5784> A_IWL<5783> A_IWL<5782> A_IWL<5781> A_IWL<5780> A_IWL<5779> A_IWL<5778> A_IWL<5777> A_IWL<5776> A_IWL<5775> A_IWL<5774> A_IWL<5773> A_IWL<5772> A_IWL<5771> A_IWL<5770> A_IWL<5769> A_IWL<5768> A_IWL<5767> A_IWL<5766> A_IWL<5765> A_IWL<5764> A_IWL<5763> A_IWL<5762> A_IWL<5761> A_IWL<5760> A_IWL<5759> A_IWL<5758> A_IWL<5757> A_IWL<5756> A_IWL<5755> A_IWL<5754> A_IWL<5753> A_IWL<5752> A_IWL<5751> A_IWL<5750> A_IWL<5749> A_IWL<5748> A_IWL<5747> A_IWL<5746> A_IWL<5745> A_IWL<5744> A_IWL<5743> A_IWL<5742> A_IWL<5741> A_IWL<5740> A_IWL<5739> A_IWL<5738> A_IWL<5737> A_IWL<5736> A_IWL<5735> A_IWL<5734> A_IWL<5733> A_IWL<5732> A_IWL<5731> A_IWL<5730> A_IWL<5729> A_IWL<5728> A_IWL<5727> A_IWL<5726> A_IWL<5725> A_IWL<5724> A_IWL<5723> A_IWL<5722> A_IWL<5721> A_IWL<5720> A_IWL<5719> A_IWL<5718> A_IWL<5717> A_IWL<5716> A_IWL<5715> A_IWL<5714> A_IWL<5713> A_IWL<5712> A_IWL<5711> A_IWL<5710> A_IWL<5709> A_IWL<5708> A_IWL<5707> A_IWL<5706> A_IWL<5705> A_IWL<5704> A_IWL<5703> A_IWL<5702> A_IWL<5701> A_IWL<5700> A_IWL<5699> A_IWL<5698> A_IWL<5697> A_IWL<5696> A_IWL<5695> A_IWL<5694> A_IWL<5693> A_IWL<5692> A_IWL<5691> A_IWL<5690> A_IWL<5689> A_IWL<5688> A_IWL<5687> A_IWL<5686> A_IWL<5685> A_IWL<5684> A_IWL<5683> A_IWL<5682> A_IWL<5681> A_IWL<5680> A_IWL<5679> A_IWL<5678> A_IWL<5677> A_IWL<5676> A_IWL<5675> A_IWL<5674> A_IWL<5673> A_IWL<5672> A_IWL<5671> A_IWL<5670> A_IWL<5669> A_IWL<5668> A_IWL<5667> A_IWL<5666> A_IWL<5665> A_IWL<5664> A_IWL<5663> A_IWL<5662> A_IWL<5661> A_IWL<5660> A_IWL<5659> A_IWL<5658> A_IWL<5657> A_IWL<5656> A_IWL<5655> A_IWL<5654> A_IWL<5653> A_IWL<5652> A_IWL<5651> A_IWL<5650> A_IWL<5649> A_IWL<5648> A_IWL<5647> A_IWL<5646> A_IWL<5645> A_IWL<5644> A_IWL<5643> A_IWL<5642> A_IWL<5641> A_IWL<5640> A_IWL<5639> A_IWL<5638> A_IWL<5637> A_IWL<5636> A_IWL<5635> A_IWL<5634> A_IWL<5633> A_IWL<5632> A_IWL<6655> A_IWL<6654> A_IWL<6653> A_IWL<6652> A_IWL<6651> A_IWL<6650> A_IWL<6649> A_IWL<6648> A_IWL<6647> A_IWL<6646> A_IWL<6645> A_IWL<6644> A_IWL<6643> A_IWL<6642> A_IWL<6641> A_IWL<6640> A_IWL<6639> A_IWL<6638> A_IWL<6637> A_IWL<6636> A_IWL<6635> A_IWL<6634> A_IWL<6633> A_IWL<6632> A_IWL<6631> A_IWL<6630> A_IWL<6629> A_IWL<6628> A_IWL<6627> A_IWL<6626> A_IWL<6625> A_IWL<6624> A_IWL<6623> A_IWL<6622> A_IWL<6621> A_IWL<6620> A_IWL<6619> A_IWL<6618> A_IWL<6617> A_IWL<6616> A_IWL<6615> A_IWL<6614> A_IWL<6613> A_IWL<6612> A_IWL<6611> A_IWL<6610> A_IWL<6609> A_IWL<6608> A_IWL<6607> A_IWL<6606> A_IWL<6605> A_IWL<6604> A_IWL<6603> A_IWL<6602> A_IWL<6601> A_IWL<6600> A_IWL<6599> A_IWL<6598> A_IWL<6597> A_IWL<6596> A_IWL<6595> A_IWL<6594> A_IWL<6593> A_IWL<6592> A_IWL<6591> A_IWL<6590> A_IWL<6589> A_IWL<6588> A_IWL<6587> A_IWL<6586> A_IWL<6585> A_IWL<6584> A_IWL<6583> A_IWL<6582> A_IWL<6581> A_IWL<6580> A_IWL<6579> A_IWL<6578> A_IWL<6577> A_IWL<6576> A_IWL<6575> A_IWL<6574> A_IWL<6573> A_IWL<6572> A_IWL<6571> A_IWL<6570> A_IWL<6569> A_IWL<6568> A_IWL<6567> A_IWL<6566> A_IWL<6565> A_IWL<6564> A_IWL<6563> A_IWL<6562> A_IWL<6561> A_IWL<6560> A_IWL<6559> A_IWL<6558> A_IWL<6557> A_IWL<6556> A_IWL<6555> A_IWL<6554> A_IWL<6553> A_IWL<6552> A_IWL<6551> A_IWL<6550> A_IWL<6549> A_IWL<6548> A_IWL<6547> A_IWL<6546> A_IWL<6545> A_IWL<6544> A_IWL<6543> A_IWL<6542> A_IWL<6541> A_IWL<6540> A_IWL<6539> A_IWL<6538> A_IWL<6537> A_IWL<6536> A_IWL<6535> A_IWL<6534> A_IWL<6533> A_IWL<6532> A_IWL<6531> A_IWL<6530> A_IWL<6529> A_IWL<6528> A_IWL<6527> A_IWL<6526> A_IWL<6525> A_IWL<6524> A_IWL<6523> A_IWL<6522> A_IWL<6521> A_IWL<6520> A_IWL<6519> A_IWL<6518> A_IWL<6517> A_IWL<6516> A_IWL<6515> A_IWL<6514> A_IWL<6513> A_IWL<6512> A_IWL<6511> A_IWL<6510> A_IWL<6509> A_IWL<6508> A_IWL<6507> A_IWL<6506> A_IWL<6505> A_IWL<6504> A_IWL<6503> A_IWL<6502> A_IWL<6501> A_IWL<6500> A_IWL<6499> A_IWL<6498> A_IWL<6497> A_IWL<6496> A_IWL<6495> A_IWL<6494> A_IWL<6493> A_IWL<6492> A_IWL<6491> A_IWL<6490> A_IWL<6489> A_IWL<6488> A_IWL<6487> A_IWL<6486> A_IWL<6485> A_IWL<6484> A_IWL<6483> A_IWL<6482> A_IWL<6481> A_IWL<6480> A_IWL<6479> A_IWL<6478> A_IWL<6477> A_IWL<6476> A_IWL<6475> A_IWL<6474> A_IWL<6473> A_IWL<6472> A_IWL<6471> A_IWL<6470> A_IWL<6469> A_IWL<6468> A_IWL<6467> A_IWL<6466> A_IWL<6465> A_IWL<6464> A_IWL<6463> A_IWL<6462> A_IWL<6461> A_IWL<6460> A_IWL<6459> A_IWL<6458> A_IWL<6457> A_IWL<6456> A_IWL<6455> A_IWL<6454> A_IWL<6453> A_IWL<6452> A_IWL<6451> A_IWL<6450> A_IWL<6449> A_IWL<6448> A_IWL<6447> A_IWL<6446> A_IWL<6445> A_IWL<6444> A_IWL<6443> A_IWL<6442> A_IWL<6441> A_IWL<6440> A_IWL<6439> A_IWL<6438> A_IWL<6437> A_IWL<6436> A_IWL<6435> A_IWL<6434> A_IWL<6433> A_IWL<6432> A_IWL<6431> A_IWL<6430> A_IWL<6429> A_IWL<6428> A_IWL<6427> A_IWL<6426> A_IWL<6425> A_IWL<6424> A_IWL<6423> A_IWL<6422> A_IWL<6421> A_IWL<6420> A_IWL<6419> A_IWL<6418> A_IWL<6417> A_IWL<6416> A_IWL<6415> A_IWL<6414> A_IWL<6413> A_IWL<6412> A_IWL<6411> A_IWL<6410> A_IWL<6409> A_IWL<6408> A_IWL<6407> A_IWL<6406> A_IWL<6405> A_IWL<6404> A_IWL<6403> A_IWL<6402> A_IWL<6401> A_IWL<6400> A_IWL<6399> A_IWL<6398> A_IWL<6397> A_IWL<6396> A_IWL<6395> A_IWL<6394> A_IWL<6393> A_IWL<6392> A_IWL<6391> A_IWL<6390> A_IWL<6389> A_IWL<6388> A_IWL<6387> A_IWL<6386> A_IWL<6385> A_IWL<6384> A_IWL<6383> A_IWL<6382> A_IWL<6381> A_IWL<6380> A_IWL<6379> A_IWL<6378> A_IWL<6377> A_IWL<6376> A_IWL<6375> A_IWL<6374> A_IWL<6373> A_IWL<6372> A_IWL<6371> A_IWL<6370> A_IWL<6369> A_IWL<6368> A_IWL<6367> A_IWL<6366> A_IWL<6365> A_IWL<6364> A_IWL<6363> A_IWL<6362> A_IWL<6361> A_IWL<6360> A_IWL<6359> A_IWL<6358> A_IWL<6357> A_IWL<6356> A_IWL<6355> A_IWL<6354> A_IWL<6353> A_IWL<6352> A_IWL<6351> A_IWL<6350> A_IWL<6349> A_IWL<6348> A_IWL<6347> A_IWL<6346> A_IWL<6345> A_IWL<6344> A_IWL<6343> A_IWL<6342> A_IWL<6341> A_IWL<6340> A_IWL<6339> A_IWL<6338> A_IWL<6337> A_IWL<6336> A_IWL<6335> A_IWL<6334> A_IWL<6333> A_IWL<6332> A_IWL<6331> A_IWL<6330> A_IWL<6329> A_IWL<6328> A_IWL<6327> A_IWL<6326> A_IWL<6325> A_IWL<6324> A_IWL<6323> A_IWL<6322> A_IWL<6321> A_IWL<6320> A_IWL<6319> A_IWL<6318> A_IWL<6317> A_IWL<6316> A_IWL<6315> A_IWL<6314> A_IWL<6313> A_IWL<6312> A_IWL<6311> A_IWL<6310> A_IWL<6309> A_IWL<6308> A_IWL<6307> A_IWL<6306> A_IWL<6305> A_IWL<6304> A_IWL<6303> A_IWL<6302> A_IWL<6301> A_IWL<6300> A_IWL<6299> A_IWL<6298> A_IWL<6297> A_IWL<6296> A_IWL<6295> A_IWL<6294> A_IWL<6293> A_IWL<6292> A_IWL<6291> A_IWL<6290> A_IWL<6289> A_IWL<6288> A_IWL<6287> A_IWL<6286> A_IWL<6285> A_IWL<6284> A_IWL<6283> A_IWL<6282> A_IWL<6281> A_IWL<6280> A_IWL<6279> A_IWL<6278> A_IWL<6277> A_IWL<6276> A_IWL<6275> A_IWL<6274> A_IWL<6273> A_IWL<6272> A_IWL<6271> A_IWL<6270> A_IWL<6269> A_IWL<6268> A_IWL<6267> A_IWL<6266> A_IWL<6265> A_IWL<6264> A_IWL<6263> A_IWL<6262> A_IWL<6261> A_IWL<6260> A_IWL<6259> A_IWL<6258> A_IWL<6257> A_IWL<6256> A_IWL<6255> A_IWL<6254> A_IWL<6253> A_IWL<6252> A_IWL<6251> A_IWL<6250> A_IWL<6249> A_IWL<6248> A_IWL<6247> A_IWL<6246> A_IWL<6245> A_IWL<6244> A_IWL<6243> A_IWL<6242> A_IWL<6241> A_IWL<6240> A_IWL<6239> A_IWL<6238> A_IWL<6237> A_IWL<6236> A_IWL<6235> A_IWL<6234> A_IWL<6233> A_IWL<6232> A_IWL<6231> A_IWL<6230> A_IWL<6229> A_IWL<6228> A_IWL<6227> A_IWL<6226> A_IWL<6225> A_IWL<6224> A_IWL<6223> A_IWL<6222> A_IWL<6221> A_IWL<6220> A_IWL<6219> A_IWL<6218> A_IWL<6217> A_IWL<6216> A_IWL<6215> A_IWL<6214> A_IWL<6213> A_IWL<6212> A_IWL<6211> A_IWL<6210> A_IWL<6209> A_IWL<6208> A_IWL<6207> A_IWL<6206> A_IWL<6205> A_IWL<6204> A_IWL<6203> A_IWL<6202> A_IWL<6201> A_IWL<6200> A_IWL<6199> A_IWL<6198> A_IWL<6197> A_IWL<6196> A_IWL<6195> A_IWL<6194> A_IWL<6193> A_IWL<6192> A_IWL<6191> A_IWL<6190> A_IWL<6189> A_IWL<6188> A_IWL<6187> A_IWL<6186> A_IWL<6185> A_IWL<6184> A_IWL<6183> A_IWL<6182> A_IWL<6181> A_IWL<6180> A_IWL<6179> A_IWL<6178> A_IWL<6177> A_IWL<6176> A_IWL<6175> A_IWL<6174> A_IWL<6173> A_IWL<6172> A_IWL<6171> A_IWL<6170> A_IWL<6169> A_IWL<6168> A_IWL<6167> A_IWL<6166> A_IWL<6165> A_IWL<6164> A_IWL<6163> A_IWL<6162> A_IWL<6161> A_IWL<6160> A_IWL<6159> A_IWL<6158> A_IWL<6157> A_IWL<6156> A_IWL<6155> A_IWL<6154> A_IWL<6153> A_IWL<6152> A_IWL<6151> A_IWL<6150> A_IWL<6149> A_IWL<6148> A_IWL<6147> A_IWL<6146> A_IWL<6145> A_IWL<6144> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_COLUMN_pcell_0
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A_IWL<5834> A_IWL<5833> A_IWL<5832> A_IWL<5831> A_IWL<5830> A_IWL<5829> A_IWL<5828> A_IWL<5827> A_IWL<5826> A_IWL<5825> A_IWL<5824> A_IWL<5823> A_IWL<5822> A_IWL<5821> A_IWL<5820> A_IWL<5819> A_IWL<5818> A_IWL<5817> A_IWL<5816> A_IWL<5815> A_IWL<5814> A_IWL<5813> A_IWL<5812> A_IWL<5811> A_IWL<5810> A_IWL<5809> A_IWL<5808> A_IWL<5807> A_IWL<5806> A_IWL<5805> A_IWL<5804> A_IWL<5803> A_IWL<5802> A_IWL<5801> A_IWL<5800> A_IWL<5799> A_IWL<5798> A_IWL<5797> A_IWL<5796> A_IWL<5795> A_IWL<5794> A_IWL<5793> A_IWL<5792> A_IWL<5791> A_IWL<5790> A_IWL<5789> A_IWL<5788> A_IWL<5787> A_IWL<5786> A_IWL<5785> A_IWL<5784> A_IWL<5783> A_IWL<5782> A_IWL<5781> A_IWL<5780> A_IWL<5779> A_IWL<5778> A_IWL<5777> A_IWL<5776> A_IWL<5775> A_IWL<5774> A_IWL<5773> A_IWL<5772> A_IWL<5771> A_IWL<5770> A_IWL<5769> A_IWL<5768> A_IWL<5767> A_IWL<5766> A_IWL<5765> A_IWL<5764> A_IWL<5763> A_IWL<5762> A_IWL<5761> A_IWL<5760> A_IWL<5759> A_IWL<5758> A_IWL<5757> A_IWL<5756> A_IWL<5755> A_IWL<5754> A_IWL<5753> A_IWL<5752> A_IWL<5751> A_IWL<5750> A_IWL<5749> A_IWL<5748> A_IWL<5747> A_IWL<5746> A_IWL<5745> A_IWL<5744> A_IWL<5743> A_IWL<5742> A_IWL<5741> A_IWL<5740> A_IWL<5739> A_IWL<5738> A_IWL<5737> A_IWL<5736> A_IWL<5735> A_IWL<5734> A_IWL<5733> A_IWL<5732> A_IWL<5731> A_IWL<5730> A_IWL<5729> A_IWL<5728> A_IWL<5727> A_IWL<5726> A_IWL<5725> A_IWL<5724> A_IWL<5723> A_IWL<5722> A_IWL<5721> A_IWL<5720> A_IWL<5719> A_IWL<5718> A_IWL<5717> A_IWL<5716> A_IWL<5715> A_IWL<5714> A_IWL<5713> A_IWL<5712> A_IWL<5711> A_IWL<5710> A_IWL<5709> A_IWL<5708> A_IWL<5707> A_IWL<5706> A_IWL<5705> A_IWL<5704> A_IWL<5703> A_IWL<5702> A_IWL<5701> A_IWL<5700> A_IWL<5699> A_IWL<5698> A_IWL<5697> A_IWL<5696> A_IWL<5695> A_IWL<5694> A_IWL<5693> A_IWL<5692> A_IWL<5691> A_IWL<5690> A_IWL<5689> A_IWL<5688> A_IWL<5687> A_IWL<5686> A_IWL<5685> A_IWL<5684> A_IWL<5683> A_IWL<5682> A_IWL<5681> A_IWL<5680> A_IWL<5679> A_IWL<5678> A_IWL<5677> A_IWL<5676> A_IWL<5675> A_IWL<5674> A_IWL<5673> A_IWL<5672> A_IWL<5671> A_IWL<5670> A_IWL<5669> A_IWL<5668> A_IWL<5667> A_IWL<5666> A_IWL<5665> A_IWL<5664> A_IWL<5663> A_IWL<5662> A_IWL<5661> A_IWL<5660> A_IWL<5659> A_IWL<5658> A_IWL<5657> A_IWL<5656> A_IWL<5655> A_IWL<5654> A_IWL<5653> A_IWL<5652> A_IWL<5651> A_IWL<5650> A_IWL<5649> A_IWL<5648> A_IWL<5647> A_IWL<5646> A_IWL<5645> A_IWL<5644> A_IWL<5643> A_IWL<5642> A_IWL<5641> A_IWL<5640> A_IWL<5639> A_IWL<5638> A_IWL<5637> A_IWL<5636> A_IWL<5635> A_IWL<5634> A_IWL<5633> A_IWL<5632> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_COLUMN_pcell_0
+XCOL<10> A_BLC<21> A_BLC<20> A_BLC_TOP<21> A_BLC_TOP<20> A_BLT<21> A_BLT<20> A_BLT_TOP<21> A_BLT_TOP<20> A_IWL<5119> A_IWL<5118> A_IWL<5117> A_IWL<5116> A_IWL<5115> A_IWL<5114> A_IWL<5113> A_IWL<5112> A_IWL<5111> A_IWL<5110> A_IWL<5109> A_IWL<5108> A_IWL<5107> A_IWL<5106> A_IWL<5105> A_IWL<5104> A_IWL<5103> A_IWL<5102> A_IWL<5101> A_IWL<5100> A_IWL<5099> A_IWL<5098> A_IWL<5097> A_IWL<5096> A_IWL<5095> A_IWL<5094> A_IWL<5093> A_IWL<5092> A_IWL<5091> A_IWL<5090> A_IWL<5089> A_IWL<5088> A_IWL<5087> A_IWL<5086> A_IWL<5085> A_IWL<5084> A_IWL<5083> A_IWL<5082> A_IWL<5081> A_IWL<5080> A_IWL<5079> A_IWL<5078> A_IWL<5077> A_IWL<5076> A_IWL<5075> A_IWL<5074> A_IWL<5073> A_IWL<5072> A_IWL<5071> A_IWL<5070> A_IWL<5069> A_IWL<5068> A_IWL<5067> A_IWL<5066> A_IWL<5065> A_IWL<5064> A_IWL<5063> A_IWL<5062> A_IWL<5061> A_IWL<5060> A_IWL<5059> A_IWL<5058> A_IWL<5057> A_IWL<5056> A_IWL<5055> A_IWL<5054> A_IWL<5053> A_IWL<5052> A_IWL<5051> A_IWL<5050> A_IWL<5049> A_IWL<5048> A_IWL<5047> A_IWL<5046> A_IWL<5045> A_IWL<5044> A_IWL<5043> A_IWL<5042> A_IWL<5041> A_IWL<5040> A_IWL<5039> A_IWL<5038> A_IWL<5037> A_IWL<5036> A_IWL<5035> A_IWL<5034> A_IWL<5033> A_IWL<5032> A_IWL<5031> A_IWL<5030> A_IWL<5029> A_IWL<5028> A_IWL<5027> A_IWL<5026> A_IWL<5025> A_IWL<5024> A_IWL<5023> A_IWL<5022> A_IWL<5021> A_IWL<5020> A_IWL<5019> A_IWL<5018> A_IWL<5017> A_IWL<5016> A_IWL<5015> A_IWL<5014> A_IWL<5013> A_IWL<5012> A_IWL<5011> A_IWL<5010> A_IWL<5009> A_IWL<5008> A_IWL<5007> A_IWL<5006> A_IWL<5005> A_IWL<5004> A_IWL<5003> A_IWL<5002> A_IWL<5001> A_IWL<5000> A_IWL<4999> A_IWL<4998> A_IWL<4997> A_IWL<4996> A_IWL<4995> A_IWL<4994> A_IWL<4993> A_IWL<4992> A_IWL<4991> A_IWL<4990> A_IWL<4989> A_IWL<4988> A_IWL<4987> A_IWL<4986> A_IWL<4985> A_IWL<4984> A_IWL<4983> A_IWL<4982> A_IWL<4981> A_IWL<4980> A_IWL<4979> A_IWL<4978> A_IWL<4977> A_IWL<4976> A_IWL<4975> A_IWL<4974> A_IWL<4973> A_IWL<4972> A_IWL<4971> A_IWL<4970> A_IWL<4969> A_IWL<4968> A_IWL<4967> A_IWL<4966> A_IWL<4965> A_IWL<4964> A_IWL<4963> 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A_IWL<4630> A_IWL<4629> A_IWL<4628> A_IWL<4627> A_IWL<4626> A_IWL<4625> A_IWL<4624> A_IWL<4623> A_IWL<4622> A_IWL<4621> A_IWL<4620> A_IWL<4619> A_IWL<4618> A_IWL<4617> A_IWL<4616> A_IWL<4615> A_IWL<4614> A_IWL<4613> A_IWL<4612> A_IWL<4611> A_IWL<4610> A_IWL<4609> A_IWL<4608> A_IWL<5631> A_IWL<5630> A_IWL<5629> A_IWL<5628> A_IWL<5627> A_IWL<5626> A_IWL<5625> A_IWL<5624> A_IWL<5623> A_IWL<5622> A_IWL<5621> A_IWL<5620> A_IWL<5619> A_IWL<5618> A_IWL<5617> A_IWL<5616> A_IWL<5615> A_IWL<5614> A_IWL<5613> A_IWL<5612> A_IWL<5611> A_IWL<5610> A_IWL<5609> A_IWL<5608> A_IWL<5607> A_IWL<5606> A_IWL<5605> A_IWL<5604> A_IWL<5603> A_IWL<5602> A_IWL<5601> A_IWL<5600> A_IWL<5599> A_IWL<5598> A_IWL<5597> A_IWL<5596> A_IWL<5595> A_IWL<5594> A_IWL<5593> A_IWL<5592> A_IWL<5591> A_IWL<5590> A_IWL<5589> A_IWL<5588> A_IWL<5587> A_IWL<5586> A_IWL<5585> A_IWL<5584> A_IWL<5583> A_IWL<5582> A_IWL<5581> A_IWL<5580> A_IWL<5579> A_IWL<5578> A_IWL<5577> A_IWL<5576> A_IWL<5575> A_IWL<5574> A_IWL<5573> A_IWL<5572> A_IWL<5571> A_IWL<5570> A_IWL<5569> A_IWL<5568> A_IWL<5567> A_IWL<5566> A_IWL<5565> A_IWL<5564> A_IWL<5563> A_IWL<5562> A_IWL<5561> A_IWL<5560> A_IWL<5559> A_IWL<5558> A_IWL<5557> A_IWL<5556> A_IWL<5555> A_IWL<5554> A_IWL<5553> A_IWL<5552> A_IWL<5551> A_IWL<5550> A_IWL<5549> A_IWL<5548> A_IWL<5547> A_IWL<5546> A_IWL<5545> A_IWL<5544> A_IWL<5543> A_IWL<5542> A_IWL<5541> A_IWL<5540> A_IWL<5539> A_IWL<5538> A_IWL<5537> A_IWL<5536> A_IWL<5535> A_IWL<5534> A_IWL<5533> A_IWL<5532> A_IWL<5531> A_IWL<5530> A_IWL<5529> A_IWL<5528> A_IWL<5527> A_IWL<5526> A_IWL<5525> A_IWL<5524> A_IWL<5523> A_IWL<5522> A_IWL<5521> A_IWL<5520> A_IWL<5519> A_IWL<5518> A_IWL<5517> A_IWL<5516> A_IWL<5515> A_IWL<5514> A_IWL<5513> A_IWL<5512> A_IWL<5511> A_IWL<5510> A_IWL<5509> A_IWL<5508> A_IWL<5507> A_IWL<5506> A_IWL<5505> A_IWL<5504> A_IWL<5503> A_IWL<5502> A_IWL<5501> A_IWL<5500> A_IWL<5499> A_IWL<5498> A_IWL<5497> A_IWL<5496> A_IWL<5495> A_IWL<5494> A_IWL<5493> A_IWL<5492> A_IWL<5491> A_IWL<5490> A_IWL<5489> A_IWL<5488> A_IWL<5487> A_IWL<5486> A_IWL<5485> A_IWL<5484> A_IWL<5483> A_IWL<5482> A_IWL<5481> A_IWL<5480> A_IWL<5479> A_IWL<5478> A_IWL<5477> A_IWL<5476> A_IWL<5475> A_IWL<5474> A_IWL<5473> A_IWL<5472> A_IWL<5471> A_IWL<5470> A_IWL<5469> A_IWL<5468> A_IWL<5467> A_IWL<5466> A_IWL<5465> A_IWL<5464> A_IWL<5463> A_IWL<5462> A_IWL<5461> A_IWL<5460> A_IWL<5459> A_IWL<5458> A_IWL<5457> A_IWL<5456> A_IWL<5455> A_IWL<5454> A_IWL<5453> A_IWL<5452> A_IWL<5451> A_IWL<5450> A_IWL<5449> A_IWL<5448> A_IWL<5447> A_IWL<5446> A_IWL<5445> A_IWL<5444> A_IWL<5443> A_IWL<5442> A_IWL<5441> A_IWL<5440> A_IWL<5439> A_IWL<5438> A_IWL<5437> A_IWL<5436> A_IWL<5435> A_IWL<5434> A_IWL<5433> A_IWL<5432> A_IWL<5431> A_IWL<5430> A_IWL<5429> A_IWL<5428> A_IWL<5427> A_IWL<5426> A_IWL<5425> A_IWL<5424> A_IWL<5423> A_IWL<5422> A_IWL<5421> A_IWL<5420> A_IWL<5419> A_IWL<5418> A_IWL<5417> A_IWL<5416> A_IWL<5415> A_IWL<5414> A_IWL<5413> A_IWL<5412> A_IWL<5411> A_IWL<5410> A_IWL<5409> A_IWL<5408> A_IWL<5407> A_IWL<5406> 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A_IWL<5156> A_IWL<5155> A_IWL<5154> A_IWL<5153> A_IWL<5152> A_IWL<5151> A_IWL<5150> A_IWL<5149> A_IWL<5148> A_IWL<5147> A_IWL<5146> A_IWL<5145> A_IWL<5144> A_IWL<5143> A_IWL<5142> A_IWL<5141> A_IWL<5140> A_IWL<5139> A_IWL<5138> A_IWL<5137> A_IWL<5136> A_IWL<5135> A_IWL<5134> A_IWL<5133> A_IWL<5132> A_IWL<5131> A_IWL<5130> A_IWL<5129> A_IWL<5128> A_IWL<5127> A_IWL<5126> A_IWL<5125> A_IWL<5124> A_IWL<5123> A_IWL<5122> A_IWL<5121> A_IWL<5120> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_COLUMN_pcell_0
+XCOL<9> A_BLC<19> A_BLC<18> A_BLC_TOP<19> A_BLC_TOP<18> A_BLT<19> A_BLT<18> A_BLT_TOP<19> A_BLT_TOP<18> A_IWL<4607> A_IWL<4606> A_IWL<4605> A_IWL<4604> A_IWL<4603> A_IWL<4602> A_IWL<4601> A_IWL<4600> A_IWL<4599> A_IWL<4598> A_IWL<4597> A_IWL<4596> A_IWL<4595> A_IWL<4594> A_IWL<4593> A_IWL<4592> A_IWL<4591> A_IWL<4590> A_IWL<4589> A_IWL<4588> A_IWL<4587> A_IWL<4586> A_IWL<4585> A_IWL<4584> A_IWL<4583> A_IWL<4582> A_IWL<4581> A_IWL<4580> A_IWL<4579> A_IWL<4578> A_IWL<4577> A_IWL<4576> A_IWL<4575> A_IWL<4574> A_IWL<4573> A_IWL<4572> A_IWL<4571> A_IWL<4570> A_IWL<4569> A_IWL<4568> A_IWL<4567> A_IWL<4566> A_IWL<4565> A_IWL<4564> A_IWL<4563> A_IWL<4562> A_IWL<4561> A_IWL<4560> A_IWL<4559> A_IWL<4558> A_IWL<4557> A_IWL<4556> A_IWL<4555> A_IWL<4554> A_IWL<4553> A_IWL<4552> A_IWL<4551> A_IWL<4550> A_IWL<4549> A_IWL<4548> A_IWL<4547> A_IWL<4546> A_IWL<4545> A_IWL<4544> A_IWL<4543> A_IWL<4542> A_IWL<4541> A_IWL<4540> A_IWL<4539> A_IWL<4538> A_IWL<4537> A_IWL<4536> A_IWL<4535> A_IWL<4534> A_IWL<4533> A_IWL<4532> A_IWL<4531> A_IWL<4530> A_IWL<4529> A_IWL<4528> A_IWL<4527> A_IWL<4526> A_IWL<4525> A_IWL<4524> A_IWL<4523> A_IWL<4522> A_IWL<4521> A_IWL<4520> A_IWL<4519> A_IWL<4518> A_IWL<4517> A_IWL<4516> A_IWL<4515> A_IWL<4514> A_IWL<4513> A_IWL<4512> A_IWL<4511> A_IWL<4510> A_IWL<4509> A_IWL<4508> A_IWL<4507> A_IWL<4506> A_IWL<4505> A_IWL<4504> A_IWL<4503> A_IWL<4502> A_IWL<4501> A_IWL<4500> A_IWL<4499> A_IWL<4498> A_IWL<4497> A_IWL<4496> A_IWL<4495> A_IWL<4494> A_IWL<4493> A_IWL<4492> A_IWL<4491> A_IWL<4490> A_IWL<4489> A_IWL<4488> A_IWL<4487> A_IWL<4486> A_IWL<4485> A_IWL<4484> A_IWL<4483> A_IWL<4482> A_IWL<4481> A_IWL<4480> A_IWL<4479> A_IWL<4478> A_IWL<4477> A_IWL<4476> A_IWL<4475> A_IWL<4474> A_IWL<4473> A_IWL<4472> A_IWL<4471> A_IWL<4470> A_IWL<4469> A_IWL<4468> A_IWL<4467> A_IWL<4466> A_IWL<4465> A_IWL<4464> A_IWL<4463> A_IWL<4462> A_IWL<4461> A_IWL<4460> A_IWL<4459> A_IWL<4458> A_IWL<4457> A_IWL<4456> A_IWL<4455> A_IWL<4454> A_IWL<4453> A_IWL<4452> A_IWL<4451> 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A_IWL<4367> A_IWL<4366> A_IWL<4365> A_IWL<4364> A_IWL<4363> A_IWL<4362> A_IWL<4361> A_IWL<4360> A_IWL<4359> A_IWL<4358> A_IWL<4357> A_IWL<4356> A_IWL<4355> A_IWL<4354> A_IWL<4353> A_IWL<4352> A_IWL<4351> A_IWL<4350> A_IWL<4349> A_IWL<4348> A_IWL<4347> A_IWL<4346> A_IWL<4345> A_IWL<4344> A_IWL<4343> A_IWL<4342> A_IWL<4341> A_IWL<4340> A_IWL<4339> A_IWL<4338> A_IWL<4337> A_IWL<4336> A_IWL<4335> A_IWL<4334> A_IWL<4333> A_IWL<4332> A_IWL<4331> A_IWL<4330> A_IWL<4329> A_IWL<4328> A_IWL<4327> A_IWL<4326> A_IWL<4325> A_IWL<4324> A_IWL<4323> A_IWL<4322> A_IWL<4321> A_IWL<4320> A_IWL<4319> A_IWL<4318> A_IWL<4317> A_IWL<4316> A_IWL<4315> A_IWL<4314> A_IWL<4313> A_IWL<4312> A_IWL<4311> A_IWL<4310> A_IWL<4309> A_IWL<4308> A_IWL<4307> A_IWL<4306> A_IWL<4305> A_IWL<4304> A_IWL<4303> A_IWL<4302> A_IWL<4301> A_IWL<4300> A_IWL<4299> A_IWL<4298> A_IWL<4297> A_IWL<4296> A_IWL<4295> A_IWL<4294> A_IWL<4293> A_IWL<4292> A_IWL<4291> A_IWL<4290> A_IWL<4289> A_IWL<4288> A_IWL<4287> A_IWL<4286> A_IWL<4285> A_IWL<4284> A_IWL<4283> A_IWL<4282> A_IWL<4281> A_IWL<4280> A_IWL<4279> A_IWL<4278> A_IWL<4277> A_IWL<4276> A_IWL<4275> A_IWL<4274> A_IWL<4273> A_IWL<4272> A_IWL<4271> A_IWL<4270> A_IWL<4269> A_IWL<4268> A_IWL<4267> A_IWL<4266> A_IWL<4265> A_IWL<4264> A_IWL<4263> A_IWL<4262> A_IWL<4261> A_IWL<4260> A_IWL<4259> A_IWL<4258> A_IWL<4257> A_IWL<4256> A_IWL<4255> A_IWL<4254> A_IWL<4253> A_IWL<4252> A_IWL<4251> A_IWL<4250> A_IWL<4249> A_IWL<4248> A_IWL<4247> A_IWL<4246> A_IWL<4245> A_IWL<4244> A_IWL<4243> A_IWL<4242> A_IWL<4241> A_IWL<4240> A_IWL<4239> A_IWL<4238> A_IWL<4237> A_IWL<4236> A_IWL<4235> A_IWL<4234> A_IWL<4233> A_IWL<4232> A_IWL<4231> A_IWL<4230> A_IWL<4229> A_IWL<4228> A_IWL<4227> A_IWL<4226> A_IWL<4225> A_IWL<4224> A_IWL<4223> A_IWL<4222> A_IWL<4221> A_IWL<4220> A_IWL<4219> A_IWL<4218> A_IWL<4217> A_IWL<4216> A_IWL<4215> A_IWL<4214> A_IWL<4213> A_IWL<4212> A_IWL<4211> A_IWL<4210> A_IWL<4209> A_IWL<4208> A_IWL<4207> A_IWL<4206> A_IWL<4205> A_IWL<4204> A_IWL<4203> A_IWL<4202> A_IWL<4201> A_IWL<4200> A_IWL<4199> A_IWL<4198> A_IWL<4197> A_IWL<4196> A_IWL<4195> A_IWL<4194> A_IWL<4193> A_IWL<4192> A_IWL<4191> A_IWL<4190> A_IWL<4189> A_IWL<4188> A_IWL<4187> A_IWL<4186> A_IWL<4185> A_IWL<4184> A_IWL<4183> A_IWL<4182> A_IWL<4181> A_IWL<4180> A_IWL<4179> A_IWL<4178> A_IWL<4177> A_IWL<4176> A_IWL<4175> A_IWL<4174> A_IWL<4173> A_IWL<4172> A_IWL<4171> A_IWL<4170> A_IWL<4169> A_IWL<4168> A_IWL<4167> A_IWL<4166> A_IWL<4165> A_IWL<4164> A_IWL<4163> A_IWL<4162> A_IWL<4161> A_IWL<4160> A_IWL<4159> A_IWL<4158> A_IWL<4157> A_IWL<4156> A_IWL<4155> A_IWL<4154> A_IWL<4153> A_IWL<4152> A_IWL<4151> A_IWL<4150> A_IWL<4149> A_IWL<4148> A_IWL<4147> A_IWL<4146> A_IWL<4145> A_IWL<4144> A_IWL<4143> A_IWL<4142> A_IWL<4141> A_IWL<4140> A_IWL<4139> A_IWL<4138> A_IWL<4137> A_IWL<4136> A_IWL<4135> A_IWL<4134> A_IWL<4133> A_IWL<4132> A_IWL<4131> A_IWL<4130> A_IWL<4129> A_IWL<4128> A_IWL<4127> A_IWL<4126> A_IWL<4125> A_IWL<4124> A_IWL<4123> A_IWL<4122> A_IWL<4121> A_IWL<4120> A_IWL<4119> A_IWL<4118> A_IWL<4117> A_IWL<4116> A_IWL<4115> A_IWL<4114> A_IWL<4113> A_IWL<4112> A_IWL<4111> A_IWL<4110> A_IWL<4109> A_IWL<4108> A_IWL<4107> A_IWL<4106> A_IWL<4105> A_IWL<4104> A_IWL<4103> A_IWL<4102> A_IWL<4101> A_IWL<4100> A_IWL<4099> A_IWL<4098> A_IWL<4097> A_IWL<4096> A_IWL<5119> A_IWL<5118> A_IWL<5117> A_IWL<5116> A_IWL<5115> A_IWL<5114> A_IWL<5113> A_IWL<5112> A_IWL<5111> A_IWL<5110> A_IWL<5109> A_IWL<5108> A_IWL<5107> A_IWL<5106> A_IWL<5105> A_IWL<5104> A_IWL<5103> A_IWL<5102> A_IWL<5101> A_IWL<5100> A_IWL<5099> A_IWL<5098> A_IWL<5097> A_IWL<5096> A_IWL<5095> A_IWL<5094> A_IWL<5093> A_IWL<5092> A_IWL<5091> A_IWL<5090> A_IWL<5089> A_IWL<5088> A_IWL<5087> A_IWL<5086> A_IWL<5085> A_IWL<5084> A_IWL<5083> A_IWL<5082> A_IWL<5081> A_IWL<5080> A_IWL<5079> A_IWL<5078> A_IWL<5077> A_IWL<5076> A_IWL<5075> A_IWL<5074> A_IWL<5073> A_IWL<5072> A_IWL<5071> A_IWL<5070> A_IWL<5069> A_IWL<5068> A_IWL<5067> A_IWL<5066> A_IWL<5065> A_IWL<5064> A_IWL<5063> A_IWL<5062> A_IWL<5061> A_IWL<5060> A_IWL<5059> A_IWL<5058> A_IWL<5057> A_IWL<5056> A_IWL<5055> A_IWL<5054> A_IWL<5053> A_IWL<5052> A_IWL<5051> A_IWL<5050> A_IWL<5049> A_IWL<5048> A_IWL<5047> A_IWL<5046> A_IWL<5045> A_IWL<5044> A_IWL<5043> A_IWL<5042> A_IWL<5041> A_IWL<5040> A_IWL<5039> A_IWL<5038> A_IWL<5037> A_IWL<5036> A_IWL<5035> A_IWL<5034> A_IWL<5033> A_IWL<5032> A_IWL<5031> A_IWL<5030> A_IWL<5029> A_IWL<5028> A_IWL<5027> A_IWL<5026> A_IWL<5025> A_IWL<5024> A_IWL<5023> A_IWL<5022> A_IWL<5021> A_IWL<5020> A_IWL<5019> A_IWL<5018> A_IWL<5017> A_IWL<5016> A_IWL<5015> A_IWL<5014> A_IWL<5013> A_IWL<5012> A_IWL<5011> A_IWL<5010> A_IWL<5009> A_IWL<5008> A_IWL<5007> A_IWL<5006> A_IWL<5005> A_IWL<5004> A_IWL<5003> A_IWL<5002> A_IWL<5001> A_IWL<5000> A_IWL<4999> A_IWL<4998> A_IWL<4997> A_IWL<4996> A_IWL<4995> A_IWL<4994> A_IWL<4993> A_IWL<4992> A_IWL<4991> A_IWL<4990> A_IWL<4989> A_IWL<4988> A_IWL<4987> A_IWL<4986> A_IWL<4985> A_IWL<4984> A_IWL<4983> A_IWL<4982> A_IWL<4981> A_IWL<4980> A_IWL<4979> A_IWL<4978> A_IWL<4977> A_IWL<4976> A_IWL<4975> A_IWL<4974> A_IWL<4973> A_IWL<4972> A_IWL<4971> A_IWL<4970> A_IWL<4969> A_IWL<4968> A_IWL<4967> A_IWL<4966> A_IWL<4965> A_IWL<4964> A_IWL<4963> A_IWL<4962> A_IWL<4961> A_IWL<4960> A_IWL<4959> A_IWL<4958> A_IWL<4957> A_IWL<4956> A_IWL<4955> A_IWL<4954> A_IWL<4953> A_IWL<4952> A_IWL<4951> A_IWL<4950> A_IWL<4949> A_IWL<4948> A_IWL<4947> A_IWL<4946> A_IWL<4945> A_IWL<4944> A_IWL<4943> A_IWL<4942> A_IWL<4941> A_IWL<4940> A_IWL<4939> A_IWL<4938> A_IWL<4937> A_IWL<4936> A_IWL<4935> A_IWL<4934> A_IWL<4933> A_IWL<4932> A_IWL<4931> A_IWL<4930> A_IWL<4929> A_IWL<4928> A_IWL<4927> A_IWL<4926> A_IWL<4925> A_IWL<4924> A_IWL<4923> A_IWL<4922> A_IWL<4921> A_IWL<4920> A_IWL<4919> A_IWL<4918> A_IWL<4917> A_IWL<4916> A_IWL<4915> A_IWL<4914> A_IWL<4913> A_IWL<4912> A_IWL<4911> A_IWL<4910> A_IWL<4909> A_IWL<4908> A_IWL<4907> A_IWL<4906> A_IWL<4905> A_IWL<4904> A_IWL<4903> A_IWL<4902> A_IWL<4901> A_IWL<4900> A_IWL<4899> A_IWL<4898> A_IWL<4897> A_IWL<4896> A_IWL<4895> A_IWL<4894> A_IWL<4893> A_IWL<4892> A_IWL<4891> A_IWL<4890> A_IWL<4889> A_IWL<4888> A_IWL<4887> A_IWL<4886> A_IWL<4885> A_IWL<4884> A_IWL<4883> A_IWL<4882> A_IWL<4881> A_IWL<4880> A_IWL<4879> A_IWL<4878> A_IWL<4877> A_IWL<4876> A_IWL<4875> A_IWL<4874> A_IWL<4873> A_IWL<4872> A_IWL<4871> A_IWL<4870> A_IWL<4869> A_IWL<4868> A_IWL<4867> A_IWL<4866> A_IWL<4865> A_IWL<4864> A_IWL<4863> A_IWL<4862> A_IWL<4861> A_IWL<4860> A_IWL<4859> A_IWL<4858> A_IWL<4857> A_IWL<4856> A_IWL<4855> A_IWL<4854> A_IWL<4853> A_IWL<4852> A_IWL<4851> A_IWL<4850> A_IWL<4849> A_IWL<4848> A_IWL<4847> A_IWL<4846> A_IWL<4845> A_IWL<4844> A_IWL<4843> A_IWL<4842> A_IWL<4841> A_IWL<4840> A_IWL<4839> A_IWL<4838> A_IWL<4837> A_IWL<4836> A_IWL<4835> A_IWL<4834> A_IWL<4833> A_IWL<4832> A_IWL<4831> A_IWL<4830> A_IWL<4829> A_IWL<4828> A_IWL<4827> A_IWL<4826> A_IWL<4825> A_IWL<4824> A_IWL<4823> A_IWL<4822> A_IWL<4821> A_IWL<4820> A_IWL<4819> A_IWL<4818> A_IWL<4817> A_IWL<4816> A_IWL<4815> A_IWL<4814> A_IWL<4813> A_IWL<4812> A_IWL<4811> A_IWL<4810> A_IWL<4809> A_IWL<4808> A_IWL<4807> A_IWL<4806> A_IWL<4805> A_IWL<4804> A_IWL<4803> A_IWL<4802> A_IWL<4801> A_IWL<4800> A_IWL<4799> A_IWL<4798> A_IWL<4797> A_IWL<4796> A_IWL<4795> A_IWL<4794> A_IWL<4793> A_IWL<4792> A_IWL<4791> A_IWL<4790> A_IWL<4789> A_IWL<4788> A_IWL<4787> A_IWL<4786> A_IWL<4785> A_IWL<4784> A_IWL<4783> A_IWL<4782> A_IWL<4781> A_IWL<4780> A_IWL<4779> A_IWL<4778> A_IWL<4777> A_IWL<4776> A_IWL<4775> A_IWL<4774> A_IWL<4773> A_IWL<4772> A_IWL<4771> A_IWL<4770> A_IWL<4769> A_IWL<4768> A_IWL<4767> A_IWL<4766> A_IWL<4765> A_IWL<4764> A_IWL<4763> A_IWL<4762> A_IWL<4761> A_IWL<4760> A_IWL<4759> A_IWL<4758> A_IWL<4757> A_IWL<4756> A_IWL<4755> A_IWL<4754> A_IWL<4753> A_IWL<4752> A_IWL<4751> A_IWL<4750> A_IWL<4749> A_IWL<4748> A_IWL<4747> A_IWL<4746> A_IWL<4745> A_IWL<4744> A_IWL<4743> A_IWL<4742> A_IWL<4741> A_IWL<4740> A_IWL<4739> A_IWL<4738> A_IWL<4737> A_IWL<4736> A_IWL<4735> A_IWL<4734> A_IWL<4733> A_IWL<4732> A_IWL<4731> A_IWL<4730> A_IWL<4729> A_IWL<4728> A_IWL<4727> A_IWL<4726> A_IWL<4725> A_IWL<4724> A_IWL<4723> A_IWL<4722> A_IWL<4721> A_IWL<4720> A_IWL<4719> A_IWL<4718> A_IWL<4717> A_IWL<4716> A_IWL<4715> A_IWL<4714> A_IWL<4713> A_IWL<4712> A_IWL<4711> A_IWL<4710> A_IWL<4709> A_IWL<4708> A_IWL<4707> A_IWL<4706> A_IWL<4705> A_IWL<4704> A_IWL<4703> A_IWL<4702> A_IWL<4701> A_IWL<4700> A_IWL<4699> A_IWL<4698> A_IWL<4697> A_IWL<4696> A_IWL<4695> A_IWL<4694> A_IWL<4693> A_IWL<4692> A_IWL<4691> A_IWL<4690> A_IWL<4689> A_IWL<4688> A_IWL<4687> A_IWL<4686> A_IWL<4685> A_IWL<4684> A_IWL<4683> A_IWL<4682> A_IWL<4681> A_IWL<4680> A_IWL<4679> A_IWL<4678> A_IWL<4677> A_IWL<4676> A_IWL<4675> A_IWL<4674> A_IWL<4673> A_IWL<4672> A_IWL<4671> A_IWL<4670> A_IWL<4669> A_IWL<4668> A_IWL<4667> A_IWL<4666> A_IWL<4665> A_IWL<4664> A_IWL<4663> A_IWL<4662> A_IWL<4661> A_IWL<4660> A_IWL<4659> A_IWL<4658> A_IWL<4657> A_IWL<4656> A_IWL<4655> A_IWL<4654> A_IWL<4653> A_IWL<4652> A_IWL<4651> A_IWL<4650> A_IWL<4649> A_IWL<4648> A_IWL<4647> A_IWL<4646> A_IWL<4645> A_IWL<4644> A_IWL<4643> A_IWL<4642> A_IWL<4641> A_IWL<4640> A_IWL<4639> A_IWL<4638> A_IWL<4637> A_IWL<4636> A_IWL<4635> A_IWL<4634> A_IWL<4633> A_IWL<4632> A_IWL<4631> A_IWL<4630> A_IWL<4629> A_IWL<4628> A_IWL<4627> A_IWL<4626> A_IWL<4625> A_IWL<4624> A_IWL<4623> A_IWL<4622> A_IWL<4621> A_IWL<4620> A_IWL<4619> A_IWL<4618> A_IWL<4617> A_IWL<4616> A_IWL<4615> A_IWL<4614> A_IWL<4613> A_IWL<4612> A_IWL<4611> A_IWL<4610> A_IWL<4609> A_IWL<4608> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_COLUMN_pcell_0
+XCOL<8> A_BLC<17> A_BLC<16> A_BLC_TOP<17> A_BLC_TOP<16> A_BLT<17> A_BLT<16> A_BLT_TOP<17> A_BLT_TOP<16> A_IWL<4095> A_IWL<4094> A_IWL<4093> A_IWL<4092> A_IWL<4091> A_IWL<4090> A_IWL<4089> A_IWL<4088> A_IWL<4087> A_IWL<4086> A_IWL<4085> A_IWL<4084> A_IWL<4083> A_IWL<4082> A_IWL<4081> A_IWL<4080> A_IWL<4079> A_IWL<4078> A_IWL<4077> A_IWL<4076> A_IWL<4075> A_IWL<4074> A_IWL<4073> A_IWL<4072> A_IWL<4071> A_IWL<4070> A_IWL<4069> A_IWL<4068> A_IWL<4067> A_IWL<4066> A_IWL<4065> A_IWL<4064> A_IWL<4063> A_IWL<4062> A_IWL<4061> A_IWL<4060> A_IWL<4059> A_IWL<4058> A_IWL<4057> A_IWL<4056> A_IWL<4055> A_IWL<4054> A_IWL<4053> A_IWL<4052> A_IWL<4051> A_IWL<4050> A_IWL<4049> A_IWL<4048> A_IWL<4047> A_IWL<4046> A_IWL<4045> A_IWL<4044> A_IWL<4043> A_IWL<4042> A_IWL<4041> A_IWL<4040> A_IWL<4039> A_IWL<4038> A_IWL<4037> A_IWL<4036> A_IWL<4035> A_IWL<4034> A_IWL<4033> A_IWL<4032> A_IWL<4031> A_IWL<4030> A_IWL<4029> A_IWL<4028> A_IWL<4027> A_IWL<4026> A_IWL<4025> A_IWL<4024> A_IWL<4023> A_IWL<4022> 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A_IWL<4132> A_IWL<4131> A_IWL<4130> A_IWL<4129> A_IWL<4128> A_IWL<4127> A_IWL<4126> A_IWL<4125> A_IWL<4124> A_IWL<4123> A_IWL<4122> A_IWL<4121> A_IWL<4120> A_IWL<4119> A_IWL<4118> A_IWL<4117> A_IWL<4116> A_IWL<4115> A_IWL<4114> A_IWL<4113> A_IWL<4112> A_IWL<4111> A_IWL<4110> A_IWL<4109> A_IWL<4108> A_IWL<4107> A_IWL<4106> A_IWL<4105> A_IWL<4104> A_IWL<4103> A_IWL<4102> A_IWL<4101> A_IWL<4100> A_IWL<4099> A_IWL<4098> A_IWL<4097> A_IWL<4096> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_COLUMN_pcell_0
+XCOL<7> A_BLC<15> A_BLC<14> A_BLC_TOP<15> A_BLC_TOP<14> A_BLT<15> A_BLT<14> A_BLT_TOP<15> A_BLT_TOP<14> A_IWL<3583> A_IWL<3582> A_IWL<3581> A_IWL<3580> A_IWL<3579> A_IWL<3578> A_IWL<3577> A_IWL<3576> A_IWL<3575> A_IWL<3574> A_IWL<3573> A_IWL<3572> A_IWL<3571> A_IWL<3570> A_IWL<3569> A_IWL<3568> A_IWL<3567> A_IWL<3566> A_IWL<3565> A_IWL<3564> A_IWL<3563> A_IWL<3562> A_IWL<3561> A_IWL<3560> A_IWL<3559> A_IWL<3558> A_IWL<3557> A_IWL<3556> A_IWL<3555> A_IWL<3554> A_IWL<3553> A_IWL<3552> A_IWL<3551> A_IWL<3550> A_IWL<3549> A_IWL<3548> A_IWL<3547> A_IWL<3546> A_IWL<3545> A_IWL<3544> A_IWL<3543> A_IWL<3542> A_IWL<3541> A_IWL<3540> A_IWL<3539> A_IWL<3538> A_IWL<3537> A_IWL<3536> A_IWL<3535> A_IWL<3534> A_IWL<3533> A_IWL<3532> A_IWL<3531> A_IWL<3530> A_IWL<3529> A_IWL<3528> A_IWL<3527> A_IWL<3526> A_IWL<3525> A_IWL<3524> A_IWL<3523> A_IWL<3522> A_IWL<3521> A_IWL<3520> A_IWL<3519> A_IWL<3518> A_IWL<3517> A_IWL<3516> A_IWL<3515> A_IWL<3514> A_IWL<3513> A_IWL<3512> A_IWL<3511> A_IWL<3510> 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A_IWL<3177> A_IWL<3176> A_IWL<3175> A_IWL<3174> A_IWL<3173> A_IWL<3172> A_IWL<3171> A_IWL<3170> A_IWL<3169> A_IWL<3168> A_IWL<3167> A_IWL<3166> A_IWL<3165> A_IWL<3164> A_IWL<3163> A_IWL<3162> A_IWL<3161> A_IWL<3160> A_IWL<3159> A_IWL<3158> A_IWL<3157> A_IWL<3156> A_IWL<3155> A_IWL<3154> A_IWL<3153> A_IWL<3152> A_IWL<3151> A_IWL<3150> A_IWL<3149> A_IWL<3148> A_IWL<3147> A_IWL<3146> A_IWL<3145> A_IWL<3144> A_IWL<3143> A_IWL<3142> A_IWL<3141> A_IWL<3140> A_IWL<3139> A_IWL<3138> A_IWL<3137> A_IWL<3136> A_IWL<3135> A_IWL<3134> A_IWL<3133> A_IWL<3132> A_IWL<3131> A_IWL<3130> A_IWL<3129> A_IWL<3128> A_IWL<3127> A_IWL<3126> A_IWL<3125> A_IWL<3124> A_IWL<3123> A_IWL<3122> A_IWL<3121> A_IWL<3120> A_IWL<3119> A_IWL<3118> A_IWL<3117> A_IWL<3116> A_IWL<3115> A_IWL<3114> A_IWL<3113> A_IWL<3112> A_IWL<3111> A_IWL<3110> A_IWL<3109> A_IWL<3108> A_IWL<3107> A_IWL<3106> A_IWL<3105> A_IWL<3104> A_IWL<3103> A_IWL<3102> A_IWL<3101> A_IWL<3100> A_IWL<3099> A_IWL<3098> A_IWL<3097> A_IWL<3096> A_IWL<3095> A_IWL<3094> A_IWL<3093> A_IWL<3092> A_IWL<3091> A_IWL<3090> A_IWL<3089> A_IWL<3088> A_IWL<3087> A_IWL<3086> A_IWL<3085> A_IWL<3084> A_IWL<3083> A_IWL<3082> A_IWL<3081> A_IWL<3080> A_IWL<3079> A_IWL<3078> A_IWL<3077> A_IWL<3076> A_IWL<3075> A_IWL<3074> A_IWL<3073> A_IWL<3072> A_IWL<4095> A_IWL<4094> A_IWL<4093> A_IWL<4092> A_IWL<4091> A_IWL<4090> A_IWL<4089> A_IWL<4088> A_IWL<4087> A_IWL<4086> A_IWL<4085> A_IWL<4084> A_IWL<4083> A_IWL<4082> A_IWL<4081> A_IWL<4080> A_IWL<4079> A_IWL<4078> A_IWL<4077> A_IWL<4076> A_IWL<4075> A_IWL<4074> A_IWL<4073> A_IWL<4072> A_IWL<4071> A_IWL<4070> A_IWL<4069> A_IWL<4068> A_IWL<4067> A_IWL<4066> A_IWL<4065> A_IWL<4064> A_IWL<4063> A_IWL<4062> A_IWL<4061> A_IWL<4060> A_IWL<4059> A_IWL<4058> A_IWL<4057> A_IWL<4056> A_IWL<4055> A_IWL<4054> A_IWL<4053> A_IWL<4052> A_IWL<4051> A_IWL<4050> A_IWL<4049> A_IWL<4048> A_IWL<4047> A_IWL<4046> A_IWL<4045> A_IWL<4044> A_IWL<4043> A_IWL<4042> A_IWL<4041> A_IWL<4040> A_IWL<4039> A_IWL<4038> A_IWL<4037> A_IWL<4036> A_IWL<4035> A_IWL<4034> A_IWL<4033> A_IWL<4032> A_IWL<4031> A_IWL<4030> A_IWL<4029> A_IWL<4028> A_IWL<4027> A_IWL<4026> A_IWL<4025> A_IWL<4024> A_IWL<4023> A_IWL<4022> A_IWL<4021> A_IWL<4020> A_IWL<4019> A_IWL<4018> A_IWL<4017> A_IWL<4016> A_IWL<4015> A_IWL<4014> A_IWL<4013> A_IWL<4012> A_IWL<4011> A_IWL<4010> A_IWL<4009> A_IWL<4008> A_IWL<4007> A_IWL<4006> A_IWL<4005> A_IWL<4004> A_IWL<4003> A_IWL<4002> A_IWL<4001> A_IWL<4000> A_IWL<3999> A_IWL<3998> A_IWL<3997> A_IWL<3996> A_IWL<3995> A_IWL<3994> A_IWL<3993> A_IWL<3992> A_IWL<3991> A_IWL<3990> A_IWL<3989> A_IWL<3988> A_IWL<3987> A_IWL<3986> A_IWL<3985> A_IWL<3984> A_IWL<3983> A_IWL<3982> A_IWL<3981> A_IWL<3980> A_IWL<3979> A_IWL<3978> A_IWL<3977> A_IWL<3976> A_IWL<3975> A_IWL<3974> A_IWL<3973> A_IWL<3972> A_IWL<3971> A_IWL<3970> A_IWL<3969> A_IWL<3968> A_IWL<3967> A_IWL<3966> A_IWL<3965> A_IWL<3964> A_IWL<3963> A_IWL<3962> A_IWL<3961> A_IWL<3960> A_IWL<3959> A_IWL<3958> A_IWL<3957> A_IWL<3956> A_IWL<3955> A_IWL<3954> A_IWL<3953> A_IWL<3952> A_IWL<3951> A_IWL<3950> A_IWL<3949> A_IWL<3948> A_IWL<3947> A_IWL<3946> A_IWL<3945> A_IWL<3944> A_IWL<3943> A_IWL<3942> A_IWL<3941> A_IWL<3940> A_IWL<3939> A_IWL<3938> A_IWL<3937> A_IWL<3936> A_IWL<3935> A_IWL<3934> A_IWL<3933> A_IWL<3932> A_IWL<3931> A_IWL<3930> A_IWL<3929> A_IWL<3928> A_IWL<3927> A_IWL<3926> A_IWL<3925> A_IWL<3924> A_IWL<3923> A_IWL<3922> A_IWL<3921> A_IWL<3920> A_IWL<3919> A_IWL<3918> A_IWL<3917> A_IWL<3916> A_IWL<3915> A_IWL<3914> A_IWL<3913> A_IWL<3912> A_IWL<3911> A_IWL<3910> A_IWL<3909> A_IWL<3908> A_IWL<3907> A_IWL<3906> A_IWL<3905> A_IWL<3904> A_IWL<3903> A_IWL<3902> A_IWL<3901> A_IWL<3900> A_IWL<3899> A_IWL<3898> A_IWL<3897> A_IWL<3896> A_IWL<3895> A_IWL<3894> A_IWL<3893> A_IWL<3892> A_IWL<3891> A_IWL<3890> A_IWL<3889> A_IWL<3888> A_IWL<3887> A_IWL<3886> A_IWL<3885> A_IWL<3884> A_IWL<3883> A_IWL<3882> A_IWL<3881> A_IWL<3880> A_IWL<3879> A_IWL<3878> A_IWL<3877> A_IWL<3876> A_IWL<3875> A_IWL<3874> A_IWL<3873> A_IWL<3872> A_IWL<3871> A_IWL<3870> A_IWL<3869> A_IWL<3868> A_IWL<3867> A_IWL<3866> A_IWL<3865> A_IWL<3864> A_IWL<3863> A_IWL<3862> A_IWL<3861> A_IWL<3860> A_IWL<3859> A_IWL<3858> A_IWL<3857> A_IWL<3856> A_IWL<3855> A_IWL<3854> A_IWL<3853> A_IWL<3852> A_IWL<3851> A_IWL<3850> A_IWL<3849> A_IWL<3848> A_IWL<3847> A_IWL<3846> A_IWL<3845> A_IWL<3844> A_IWL<3843> A_IWL<3842> A_IWL<3841> A_IWL<3840> A_IWL<3839> A_IWL<3838> A_IWL<3837> A_IWL<3836> A_IWL<3835> A_IWL<3834> A_IWL<3833> A_IWL<3832> A_IWL<3831> A_IWL<3830> A_IWL<3829> A_IWL<3828> A_IWL<3827> A_IWL<3826> A_IWL<3825> A_IWL<3824> A_IWL<3823> A_IWL<3822> A_IWL<3821> A_IWL<3820> A_IWL<3819> A_IWL<3818> A_IWL<3817> A_IWL<3816> A_IWL<3815> A_IWL<3814> A_IWL<3813> A_IWL<3812> A_IWL<3811> A_IWL<3810> A_IWL<3809> A_IWL<3808> A_IWL<3807> A_IWL<3806> A_IWL<3805> A_IWL<3804> A_IWL<3803> A_IWL<3802> A_IWL<3801> A_IWL<3800> A_IWL<3799> A_IWL<3798> A_IWL<3797> A_IWL<3796> A_IWL<3795> A_IWL<3794> A_IWL<3793> A_IWL<3792> A_IWL<3791> A_IWL<3790> A_IWL<3789> A_IWL<3788> A_IWL<3787> A_IWL<3786> A_IWL<3785> A_IWL<3784> A_IWL<3783> A_IWL<3782> A_IWL<3781> A_IWL<3780> A_IWL<3779> A_IWL<3778> A_IWL<3777> A_IWL<3776> A_IWL<3775> A_IWL<3774> A_IWL<3773> A_IWL<3772> A_IWL<3771> A_IWL<3770> A_IWL<3769> A_IWL<3768> A_IWL<3767> A_IWL<3766> A_IWL<3765> A_IWL<3764> A_IWL<3763> A_IWL<3762> A_IWL<3761> A_IWL<3760> A_IWL<3759> A_IWL<3758> A_IWL<3757> A_IWL<3756> A_IWL<3755> A_IWL<3754> A_IWL<3753> A_IWL<3752> A_IWL<3751> A_IWL<3750> A_IWL<3749> A_IWL<3748> A_IWL<3747> A_IWL<3746> A_IWL<3745> A_IWL<3744> A_IWL<3743> A_IWL<3742> A_IWL<3741> A_IWL<3740> A_IWL<3739> A_IWL<3738> A_IWL<3737> A_IWL<3736> A_IWL<3735> A_IWL<3734> A_IWL<3733> A_IWL<3732> A_IWL<3731> A_IWL<3730> A_IWL<3729> A_IWL<3728> A_IWL<3727> A_IWL<3726> A_IWL<3725> A_IWL<3724> A_IWL<3723> A_IWL<3722> A_IWL<3721> A_IWL<3720> A_IWL<3719> A_IWL<3718> A_IWL<3717> A_IWL<3716> A_IWL<3715> A_IWL<3714> A_IWL<3713> A_IWL<3712> A_IWL<3711> A_IWL<3710> A_IWL<3709> A_IWL<3708> A_IWL<3707> A_IWL<3706> A_IWL<3705> A_IWL<3704> A_IWL<3703> A_IWL<3702> A_IWL<3701> A_IWL<3700> A_IWL<3699> A_IWL<3698> A_IWL<3697> A_IWL<3696> A_IWL<3695> A_IWL<3694> A_IWL<3693> A_IWL<3692> A_IWL<3691> A_IWL<3690> A_IWL<3689> A_IWL<3688> A_IWL<3687> A_IWL<3686> A_IWL<3685> A_IWL<3684> A_IWL<3683> A_IWL<3682> A_IWL<3681> A_IWL<3680> A_IWL<3679> A_IWL<3678> A_IWL<3677> A_IWL<3676> A_IWL<3675> A_IWL<3674> A_IWL<3673> A_IWL<3672> A_IWL<3671> A_IWL<3670> A_IWL<3669> A_IWL<3668> A_IWL<3667> A_IWL<3666> A_IWL<3665> A_IWL<3664> A_IWL<3663> A_IWL<3662> A_IWL<3661> A_IWL<3660> A_IWL<3659> A_IWL<3658> A_IWL<3657> A_IWL<3656> A_IWL<3655> A_IWL<3654> A_IWL<3653> A_IWL<3652> A_IWL<3651> A_IWL<3650> A_IWL<3649> A_IWL<3648> A_IWL<3647> A_IWL<3646> A_IWL<3645> A_IWL<3644> A_IWL<3643> A_IWL<3642> A_IWL<3641> A_IWL<3640> A_IWL<3639> A_IWL<3638> A_IWL<3637> A_IWL<3636> A_IWL<3635> A_IWL<3634> A_IWL<3633> A_IWL<3632> A_IWL<3631> A_IWL<3630> A_IWL<3629> A_IWL<3628> A_IWL<3627> A_IWL<3626> A_IWL<3625> A_IWL<3624> A_IWL<3623> A_IWL<3622> A_IWL<3621> A_IWL<3620> A_IWL<3619> A_IWL<3618> A_IWL<3617> A_IWL<3616> A_IWL<3615> A_IWL<3614> A_IWL<3613> A_IWL<3612> A_IWL<3611> A_IWL<3610> A_IWL<3609> A_IWL<3608> A_IWL<3607> A_IWL<3606> A_IWL<3605> A_IWL<3604> A_IWL<3603> A_IWL<3602> A_IWL<3601> A_IWL<3600> A_IWL<3599> A_IWL<3598> A_IWL<3597> A_IWL<3596> A_IWL<3595> A_IWL<3594> A_IWL<3593> A_IWL<3592> A_IWL<3591> A_IWL<3590> A_IWL<3589> A_IWL<3588> A_IWL<3587> A_IWL<3586> A_IWL<3585> A_IWL<3584> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_COLUMN_pcell_0
+XCOL<6> A_BLC<13> A_BLC<12> A_BLC_TOP<13> A_BLC_TOP<12> A_BLT<13> A_BLT<12> A_BLT_TOP<13> A_BLT_TOP<12> A_IWL<3071> A_IWL<3070> A_IWL<3069> A_IWL<3068> A_IWL<3067> A_IWL<3066> A_IWL<3065> A_IWL<3064> A_IWL<3063> A_IWL<3062> A_IWL<3061> A_IWL<3060> A_IWL<3059> A_IWL<3058> A_IWL<3057> A_IWL<3056> A_IWL<3055> A_IWL<3054> A_IWL<3053> A_IWL<3052> A_IWL<3051> A_IWL<3050> A_IWL<3049> A_IWL<3048> A_IWL<3047> A_IWL<3046> A_IWL<3045> A_IWL<3044> A_IWL<3043> A_IWL<3042> A_IWL<3041> A_IWL<3040> A_IWL<3039> A_IWL<3038> A_IWL<3037> A_IWL<3036> A_IWL<3035> A_IWL<3034> A_IWL<3033> A_IWL<3032> A_IWL<3031> A_IWL<3030> A_IWL<3029> A_IWL<3028> A_IWL<3027> A_IWL<3026> A_IWL<3025> A_IWL<3024> A_IWL<3023> A_IWL<3022> A_IWL<3021> A_IWL<3020> A_IWL<3019> A_IWL<3018> A_IWL<3017> A_IWL<3016> A_IWL<3015> A_IWL<3014> A_IWL<3013> A_IWL<3012> A_IWL<3011> A_IWL<3010> A_IWL<3009> A_IWL<3008> A_IWL<3007> A_IWL<3006> A_IWL<3005> A_IWL<3004> A_IWL<3003> A_IWL<3002> A_IWL<3001> A_IWL<3000> A_IWL<2999> A_IWL<2998> A_IWL<2997> A_IWL<2996> A_IWL<2995> A_IWL<2994> A_IWL<2993> A_IWL<2992> A_IWL<2991> A_IWL<2990> A_IWL<2989> A_IWL<2988> A_IWL<2987> A_IWL<2986> A_IWL<2985> A_IWL<2984> A_IWL<2983> A_IWL<2982> A_IWL<2981> A_IWL<2980> A_IWL<2979> A_IWL<2978> A_IWL<2977> A_IWL<2976> A_IWL<2975> A_IWL<2974> A_IWL<2973> A_IWL<2972> A_IWL<2971> A_IWL<2970> A_IWL<2969> A_IWL<2968> A_IWL<2967> A_IWL<2966> A_IWL<2965> A_IWL<2964> A_IWL<2963> A_IWL<2962> A_IWL<2961> A_IWL<2960> A_IWL<2959> A_IWL<2958> A_IWL<2957> A_IWL<2956> A_IWL<2955> A_IWL<2954> A_IWL<2953> A_IWL<2952> A_IWL<2951> A_IWL<2950> A_IWL<2949> A_IWL<2948> A_IWL<2947> A_IWL<2946> A_IWL<2945> A_IWL<2944> A_IWL<2943> A_IWL<2942> A_IWL<2941> A_IWL<2940> A_IWL<2939> A_IWL<2938> A_IWL<2937> A_IWL<2936> A_IWL<2935> A_IWL<2934> A_IWL<2933> A_IWL<2932> A_IWL<2931> A_IWL<2930> A_IWL<2929> A_IWL<2928> A_IWL<2927> A_IWL<2926> A_IWL<2925> A_IWL<2924> A_IWL<2923> A_IWL<2922> A_IWL<2921> A_IWL<2920> A_IWL<2919> A_IWL<2918> A_IWL<2917> A_IWL<2916> A_IWL<2915> A_IWL<2914> A_IWL<2913> A_IWL<2912> A_IWL<2911> A_IWL<2910> A_IWL<2909> A_IWL<2908> A_IWL<2907> A_IWL<2906> A_IWL<2905> A_IWL<2904> A_IWL<2903> A_IWL<2902> A_IWL<2901> A_IWL<2900> A_IWL<2899> A_IWL<2898> A_IWL<2897> A_IWL<2896> A_IWL<2895> A_IWL<2894> A_IWL<2893> A_IWL<2892> A_IWL<2891> A_IWL<2890> A_IWL<2889> A_IWL<2888> A_IWL<2887> A_IWL<2886> A_IWL<2885> A_IWL<2884> A_IWL<2883> A_IWL<2882> A_IWL<2881> A_IWL<2880> A_IWL<2879> A_IWL<2878> A_IWL<2877> A_IWL<2876> A_IWL<2875> A_IWL<2874> A_IWL<2873> A_IWL<2872> A_IWL<2871> A_IWL<2870> A_IWL<2869> A_IWL<2868> A_IWL<2867> A_IWL<2866> A_IWL<2865> A_IWL<2864> A_IWL<2863> A_IWL<2862> A_IWL<2861> A_IWL<2860> A_IWL<2859> A_IWL<2858> A_IWL<2857> A_IWL<2856> A_IWL<2855> A_IWL<2854> A_IWL<2853> A_IWL<2852> A_IWL<2851> A_IWL<2850> A_IWL<2849> A_IWL<2848> A_IWL<2847> A_IWL<2846> A_IWL<2845> A_IWL<2844> A_IWL<2843> A_IWL<2842> A_IWL<2841> A_IWL<2840> A_IWL<2839> A_IWL<2838> A_IWL<2837> A_IWL<2836> A_IWL<2835> A_IWL<2834> A_IWL<2833> A_IWL<2832> A_IWL<2831> A_IWL<2830> A_IWL<2829> A_IWL<2828> A_IWL<2827> A_IWL<2826> A_IWL<2825> A_IWL<2824> A_IWL<2823> A_IWL<2822> A_IWL<2821> A_IWL<2820> A_IWL<2819> A_IWL<2818> A_IWL<2817> A_IWL<2816> A_IWL<2815> A_IWL<2814> A_IWL<2813> A_IWL<2812> A_IWL<2811> A_IWL<2810> A_IWL<2809> A_IWL<2808> A_IWL<2807> A_IWL<2806> A_IWL<2805> A_IWL<2804> A_IWL<2803> A_IWL<2802> A_IWL<2801> A_IWL<2800> A_IWL<2799> A_IWL<2798> A_IWL<2797> A_IWL<2796> A_IWL<2795> A_IWL<2794> A_IWL<2793> A_IWL<2792> A_IWL<2791> A_IWL<2790> A_IWL<2789> A_IWL<2788> A_IWL<2787> A_IWL<2786> A_IWL<2785> A_IWL<2784> A_IWL<2783> A_IWL<2782> A_IWL<2781> A_IWL<2780> A_IWL<2779> A_IWL<2778> A_IWL<2777> A_IWL<2776> A_IWL<2775> A_IWL<2774> A_IWL<2773> A_IWL<2772> A_IWL<2771> A_IWL<2770> A_IWL<2769> A_IWL<2768> A_IWL<2767> A_IWL<2766> A_IWL<2765> A_IWL<2764> A_IWL<2763> A_IWL<2762> A_IWL<2761> A_IWL<2760> A_IWL<2759> A_IWL<2758> A_IWL<2757> A_IWL<2756> A_IWL<2755> A_IWL<2754> A_IWL<2753> A_IWL<2752> A_IWL<2751> A_IWL<2750> A_IWL<2749> A_IWL<2748> A_IWL<2747> A_IWL<2746> A_IWL<2745> A_IWL<2744> A_IWL<2743> A_IWL<2742> A_IWL<2741> A_IWL<2740> A_IWL<2739> A_IWL<2738> A_IWL<2737> A_IWL<2736> A_IWL<2735> A_IWL<2734> A_IWL<2733> A_IWL<2732> A_IWL<2731> A_IWL<2730> A_IWL<2729> A_IWL<2728> A_IWL<2727> A_IWL<2726> A_IWL<2725> A_IWL<2724> A_IWL<2723> A_IWL<2722> A_IWL<2721> A_IWL<2720> A_IWL<2719> A_IWL<2718> A_IWL<2717> A_IWL<2716> A_IWL<2715> A_IWL<2714> A_IWL<2713> A_IWL<2712> A_IWL<2711> A_IWL<2710> A_IWL<2709> A_IWL<2708> A_IWL<2707> A_IWL<2706> A_IWL<2705> A_IWL<2704> A_IWL<2703> A_IWL<2702> A_IWL<2701> A_IWL<2700> A_IWL<2699> A_IWL<2698> A_IWL<2697> A_IWL<2696> A_IWL<2695> A_IWL<2694> A_IWL<2693> A_IWL<2692> A_IWL<2691> A_IWL<2690> A_IWL<2689> A_IWL<2688> A_IWL<2687> A_IWL<2686> A_IWL<2685> A_IWL<2684> A_IWL<2683> A_IWL<2682> A_IWL<2681> A_IWL<2680> A_IWL<2679> A_IWL<2678> A_IWL<2677> A_IWL<2676> A_IWL<2675> A_IWL<2674> A_IWL<2673> A_IWL<2672> A_IWL<2671> A_IWL<2670> A_IWL<2669> A_IWL<2668> A_IWL<2667> A_IWL<2666> A_IWL<2665> A_IWL<2664> A_IWL<2663> A_IWL<2662> A_IWL<2661> A_IWL<2660> A_IWL<2659> A_IWL<2658> A_IWL<2657> A_IWL<2656> A_IWL<2655> A_IWL<2654> A_IWL<2653> A_IWL<2652> A_IWL<2651> A_IWL<2650> A_IWL<2649> A_IWL<2648> A_IWL<2647> A_IWL<2646> A_IWL<2645> A_IWL<2644> A_IWL<2643> A_IWL<2642> A_IWL<2641> A_IWL<2640> A_IWL<2639> A_IWL<2638> A_IWL<2637> A_IWL<2636> A_IWL<2635> A_IWL<2634> A_IWL<2633> A_IWL<2632> A_IWL<2631> A_IWL<2630> A_IWL<2629> A_IWL<2628> A_IWL<2627> A_IWL<2626> A_IWL<2625> A_IWL<2624> A_IWL<2623> A_IWL<2622> A_IWL<2621> A_IWL<2620> A_IWL<2619> A_IWL<2618> A_IWL<2617> A_IWL<2616> A_IWL<2615> A_IWL<2614> A_IWL<2613> A_IWL<2612> A_IWL<2611> A_IWL<2610> A_IWL<2609> A_IWL<2608> A_IWL<2607> A_IWL<2606> A_IWL<2605> A_IWL<2604> A_IWL<2603> A_IWL<2602> A_IWL<2601> A_IWL<2600> A_IWL<2599> A_IWL<2598> A_IWL<2597> A_IWL<2596> A_IWL<2595> A_IWL<2594> A_IWL<2593> A_IWL<2592> A_IWL<2591> A_IWL<2590> A_IWL<2589> A_IWL<2588> A_IWL<2587> A_IWL<2586> A_IWL<2585> A_IWL<2584> A_IWL<2583> A_IWL<2582> A_IWL<2581> A_IWL<2580> A_IWL<2579> A_IWL<2578> A_IWL<2577> A_IWL<2576> A_IWL<2575> A_IWL<2574> A_IWL<2573> A_IWL<2572> A_IWL<2571> A_IWL<2570> A_IWL<2569> A_IWL<2568> A_IWL<2567> A_IWL<2566> A_IWL<2565> A_IWL<2564> A_IWL<2563> A_IWL<2562> A_IWL<2561> A_IWL<2560> A_IWL<3583> A_IWL<3582> A_IWL<3581> A_IWL<3580> A_IWL<3579> A_IWL<3578> A_IWL<3577> A_IWL<3576> A_IWL<3575> A_IWL<3574> A_IWL<3573> A_IWL<3572> A_IWL<3571> A_IWL<3570> A_IWL<3569> A_IWL<3568> A_IWL<3567> A_IWL<3566> A_IWL<3565> A_IWL<3564> A_IWL<3563> A_IWL<3562> A_IWL<3561> A_IWL<3560> A_IWL<3559> A_IWL<3558> A_IWL<3557> A_IWL<3556> A_IWL<3555> A_IWL<3554> A_IWL<3553> A_IWL<3552> A_IWL<3551> A_IWL<3550> A_IWL<3549> A_IWL<3548> A_IWL<3547> A_IWL<3546> A_IWL<3545> A_IWL<3544> A_IWL<3543> A_IWL<3542> A_IWL<3541> A_IWL<3540> A_IWL<3539> A_IWL<3538> A_IWL<3537> A_IWL<3536> A_IWL<3535> A_IWL<3534> A_IWL<3533> A_IWL<3532> A_IWL<3531> A_IWL<3530> A_IWL<3529> A_IWL<3528> A_IWL<3527> A_IWL<3526> A_IWL<3525> A_IWL<3524> A_IWL<3523> A_IWL<3522> A_IWL<3521> A_IWL<3520> A_IWL<3519> A_IWL<3518> A_IWL<3517> A_IWL<3516> A_IWL<3515> A_IWL<3514> A_IWL<3513> A_IWL<3512> A_IWL<3511> A_IWL<3510> A_IWL<3509> A_IWL<3508> A_IWL<3507> A_IWL<3506> A_IWL<3505> A_IWL<3504> A_IWL<3503> A_IWL<3502> A_IWL<3501> A_IWL<3500> A_IWL<3499> A_IWL<3498> A_IWL<3497> A_IWL<3496> A_IWL<3495> A_IWL<3494> A_IWL<3493> A_IWL<3492> A_IWL<3491> A_IWL<3490> A_IWL<3489> A_IWL<3488> A_IWL<3487> A_IWL<3486> A_IWL<3485> A_IWL<3484> A_IWL<3483> A_IWL<3482> A_IWL<3481> A_IWL<3480> A_IWL<3479> A_IWL<3478> A_IWL<3477> A_IWL<3476> A_IWL<3475> A_IWL<3474> A_IWL<3473> A_IWL<3472> A_IWL<3471> A_IWL<3470> A_IWL<3469> A_IWL<3468> A_IWL<3467> A_IWL<3466> A_IWL<3465> A_IWL<3464> A_IWL<3463> A_IWL<3462> A_IWL<3461> A_IWL<3460> A_IWL<3459> A_IWL<3458> A_IWL<3457> A_IWL<3456> A_IWL<3455> A_IWL<3454> A_IWL<3453> A_IWL<3452> A_IWL<3451> A_IWL<3450> A_IWL<3449> A_IWL<3448> A_IWL<3447> A_IWL<3446> A_IWL<3445> A_IWL<3444> A_IWL<3443> A_IWL<3442> A_IWL<3441> A_IWL<3440> A_IWL<3439> A_IWL<3438> A_IWL<3437> A_IWL<3436> A_IWL<3435> A_IWL<3434> A_IWL<3433> A_IWL<3432> A_IWL<3431> A_IWL<3430> A_IWL<3429> A_IWL<3428> A_IWL<3427> A_IWL<3426> A_IWL<3425> A_IWL<3424> A_IWL<3423> A_IWL<3422> A_IWL<3421> A_IWL<3420> A_IWL<3419> A_IWL<3418> A_IWL<3417> A_IWL<3416> A_IWL<3415> A_IWL<3414> A_IWL<3413> A_IWL<3412> A_IWL<3411> A_IWL<3410> A_IWL<3409> A_IWL<3408> A_IWL<3407> A_IWL<3406> A_IWL<3405> A_IWL<3404> A_IWL<3403> A_IWL<3402> A_IWL<3401> A_IWL<3400> A_IWL<3399> A_IWL<3398> A_IWL<3397> A_IWL<3396> A_IWL<3395> A_IWL<3394> A_IWL<3393> A_IWL<3392> A_IWL<3391> A_IWL<3390> A_IWL<3389> A_IWL<3388> A_IWL<3387> A_IWL<3386> A_IWL<3385> A_IWL<3384> A_IWL<3383> A_IWL<3382> A_IWL<3381> A_IWL<3380> A_IWL<3379> A_IWL<3378> A_IWL<3377> A_IWL<3376> A_IWL<3375> A_IWL<3374> A_IWL<3373> A_IWL<3372> A_IWL<3371> A_IWL<3370> A_IWL<3369> A_IWL<3368> A_IWL<3367> A_IWL<3366> A_IWL<3365> A_IWL<3364> A_IWL<3363> A_IWL<3362> A_IWL<3361> A_IWL<3360> A_IWL<3359> A_IWL<3358> A_IWL<3357> A_IWL<3356> A_IWL<3355> A_IWL<3354> A_IWL<3353> A_IWL<3352> A_IWL<3351> A_IWL<3350> A_IWL<3349> A_IWL<3348> A_IWL<3347> A_IWL<3346> A_IWL<3345> A_IWL<3344> A_IWL<3343> A_IWL<3342> A_IWL<3341> A_IWL<3340> A_IWL<3339> A_IWL<3338> A_IWL<3337> A_IWL<3336> A_IWL<3335> A_IWL<3334> A_IWL<3333> A_IWL<3332> A_IWL<3331> A_IWL<3330> A_IWL<3329> A_IWL<3328> A_IWL<3327> A_IWL<3326> A_IWL<3325> A_IWL<3324> A_IWL<3323> A_IWL<3322> A_IWL<3321> A_IWL<3320> A_IWL<3319> A_IWL<3318> A_IWL<3317> A_IWL<3316> A_IWL<3315> A_IWL<3314> A_IWL<3313> A_IWL<3312> A_IWL<3311> A_IWL<3310> A_IWL<3309> A_IWL<3308> A_IWL<3307> A_IWL<3306> A_IWL<3305> A_IWL<3304> A_IWL<3303> A_IWL<3302> A_IWL<3301> A_IWL<3300> A_IWL<3299> A_IWL<3298> A_IWL<3297> A_IWL<3296> A_IWL<3295> A_IWL<3294> A_IWL<3293> A_IWL<3292> A_IWL<3291> A_IWL<3290> A_IWL<3289> A_IWL<3288> A_IWL<3287> A_IWL<3286> A_IWL<3285> A_IWL<3284> A_IWL<3283> A_IWL<3282> A_IWL<3281> A_IWL<3280> A_IWL<3279> A_IWL<3278> A_IWL<3277> A_IWL<3276> A_IWL<3275> A_IWL<3274> A_IWL<3273> A_IWL<3272> A_IWL<3271> A_IWL<3270> A_IWL<3269> A_IWL<3268> A_IWL<3267> A_IWL<3266> A_IWL<3265> A_IWL<3264> A_IWL<3263> A_IWL<3262> A_IWL<3261> A_IWL<3260> A_IWL<3259> A_IWL<3258> A_IWL<3257> A_IWL<3256> A_IWL<3255> A_IWL<3254> A_IWL<3253> A_IWL<3252> A_IWL<3251> A_IWL<3250> A_IWL<3249> A_IWL<3248> A_IWL<3247> A_IWL<3246> A_IWL<3245> A_IWL<3244> A_IWL<3243> A_IWL<3242> A_IWL<3241> A_IWL<3240> A_IWL<3239> A_IWL<3238> A_IWL<3237> A_IWL<3236> A_IWL<3235> A_IWL<3234> A_IWL<3233> A_IWL<3232> A_IWL<3231> A_IWL<3230> A_IWL<3229> A_IWL<3228> A_IWL<3227> A_IWL<3226> A_IWL<3225> A_IWL<3224> A_IWL<3223> A_IWL<3222> A_IWL<3221> A_IWL<3220> A_IWL<3219> A_IWL<3218> A_IWL<3217> A_IWL<3216> A_IWL<3215> A_IWL<3214> A_IWL<3213> A_IWL<3212> A_IWL<3211> A_IWL<3210> A_IWL<3209> A_IWL<3208> A_IWL<3207> A_IWL<3206> A_IWL<3205> A_IWL<3204> A_IWL<3203> A_IWL<3202> A_IWL<3201> A_IWL<3200> A_IWL<3199> A_IWL<3198> A_IWL<3197> A_IWL<3196> A_IWL<3195> A_IWL<3194> A_IWL<3193> A_IWL<3192> A_IWL<3191> A_IWL<3190> A_IWL<3189> A_IWL<3188> A_IWL<3187> A_IWL<3186> A_IWL<3185> A_IWL<3184> A_IWL<3183> A_IWL<3182> A_IWL<3181> A_IWL<3180> A_IWL<3179> A_IWL<3178> A_IWL<3177> A_IWL<3176> A_IWL<3175> A_IWL<3174> A_IWL<3173> A_IWL<3172> A_IWL<3171> A_IWL<3170> A_IWL<3169> A_IWL<3168> A_IWL<3167> A_IWL<3166> A_IWL<3165> A_IWL<3164> A_IWL<3163> A_IWL<3162> A_IWL<3161> A_IWL<3160> A_IWL<3159> A_IWL<3158> A_IWL<3157> A_IWL<3156> A_IWL<3155> A_IWL<3154> A_IWL<3153> A_IWL<3152> A_IWL<3151> A_IWL<3150> A_IWL<3149> A_IWL<3148> A_IWL<3147> A_IWL<3146> A_IWL<3145> A_IWL<3144> A_IWL<3143> A_IWL<3142> A_IWL<3141> A_IWL<3140> A_IWL<3139> A_IWL<3138> A_IWL<3137> A_IWL<3136> A_IWL<3135> A_IWL<3134> A_IWL<3133> A_IWL<3132> A_IWL<3131> A_IWL<3130> A_IWL<3129> A_IWL<3128> A_IWL<3127> A_IWL<3126> A_IWL<3125> A_IWL<3124> A_IWL<3123> A_IWL<3122> A_IWL<3121> A_IWL<3120> A_IWL<3119> A_IWL<3118> A_IWL<3117> A_IWL<3116> A_IWL<3115> A_IWL<3114> A_IWL<3113> A_IWL<3112> A_IWL<3111> A_IWL<3110> A_IWL<3109> A_IWL<3108> A_IWL<3107> A_IWL<3106> A_IWL<3105> A_IWL<3104> A_IWL<3103> A_IWL<3102> A_IWL<3101> A_IWL<3100> A_IWL<3099> A_IWL<3098> A_IWL<3097> A_IWL<3096> A_IWL<3095> A_IWL<3094> A_IWL<3093> A_IWL<3092> A_IWL<3091> A_IWL<3090> A_IWL<3089> A_IWL<3088> A_IWL<3087> A_IWL<3086> A_IWL<3085> A_IWL<3084> A_IWL<3083> A_IWL<3082> A_IWL<3081> A_IWL<3080> A_IWL<3079> A_IWL<3078> A_IWL<3077> A_IWL<3076> A_IWL<3075> A_IWL<3074> A_IWL<3073> A_IWL<3072> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_COLUMN_pcell_0
+XCOL<5> A_BLC<11> A_BLC<10> A_BLC_TOP<11> A_BLC_TOP<10> A_BLT<11> A_BLT<10> A_BLT_TOP<11> A_BLT_TOP<10> A_IWL<2559> A_IWL<2558> A_IWL<2557> A_IWL<2556> A_IWL<2555> A_IWL<2554> A_IWL<2553> A_IWL<2552> A_IWL<2551> A_IWL<2550> A_IWL<2549> A_IWL<2548> A_IWL<2547> A_IWL<2546> A_IWL<2545> A_IWL<2544> A_IWL<2543> A_IWL<2542> A_IWL<2541> A_IWL<2540> A_IWL<2539> A_IWL<2538> A_IWL<2537> A_IWL<2536> A_IWL<2535> A_IWL<2534> A_IWL<2533> A_IWL<2532> A_IWL<2531> A_IWL<2530> A_IWL<2529> A_IWL<2528> A_IWL<2527> A_IWL<2526> A_IWL<2525> A_IWL<2524> A_IWL<2523> A_IWL<2522> A_IWL<2521> A_IWL<2520> A_IWL<2519> A_IWL<2518> A_IWL<2517> A_IWL<2516> A_IWL<2515> A_IWL<2514> A_IWL<2513> A_IWL<2512> A_IWL<2511> A_IWL<2510> A_IWL<2509> A_IWL<2508> A_IWL<2507> A_IWL<2506> A_IWL<2505> A_IWL<2504> A_IWL<2503> A_IWL<2502> A_IWL<2501> A_IWL<2500> A_IWL<2499> A_IWL<2498> A_IWL<2497> A_IWL<2496> A_IWL<2495> A_IWL<2494> A_IWL<2493> A_IWL<2492> A_IWL<2491> A_IWL<2490> A_IWL<2489> A_IWL<2488> A_IWL<2487> A_IWL<2486> A_IWL<2485> A_IWL<2484> A_IWL<2483> A_IWL<2482> A_IWL<2481> A_IWL<2480> A_IWL<2479> A_IWL<2478> A_IWL<2477> A_IWL<2476> A_IWL<2475> A_IWL<2474> A_IWL<2473> A_IWL<2472> A_IWL<2471> A_IWL<2470> A_IWL<2469> A_IWL<2468> A_IWL<2467> A_IWL<2466> A_IWL<2465> A_IWL<2464> A_IWL<2463> A_IWL<2462> A_IWL<2461> A_IWL<2460> A_IWL<2459> A_IWL<2458> A_IWL<2457> A_IWL<2456> A_IWL<2455> A_IWL<2454> A_IWL<2453> A_IWL<2452> A_IWL<2451> A_IWL<2450> A_IWL<2449> A_IWL<2448> A_IWL<2447> A_IWL<2446> A_IWL<2445> A_IWL<2444> A_IWL<2443> A_IWL<2442> A_IWL<2441> A_IWL<2440> A_IWL<2439> A_IWL<2438> A_IWL<2437> A_IWL<2436> A_IWL<2435> A_IWL<2434> A_IWL<2433> A_IWL<2432> A_IWL<2431> A_IWL<2430> A_IWL<2429> A_IWL<2428> A_IWL<2427> A_IWL<2426> A_IWL<2425> A_IWL<2424> A_IWL<2423> A_IWL<2422> A_IWL<2421> A_IWL<2420> A_IWL<2419> A_IWL<2418> A_IWL<2417> A_IWL<2416> A_IWL<2415> A_IWL<2414> A_IWL<2413> A_IWL<2412> A_IWL<2411> A_IWL<2410> A_IWL<2409> A_IWL<2408> A_IWL<2407> A_IWL<2406> A_IWL<2405> A_IWL<2404> A_IWL<2403> A_IWL<2402> A_IWL<2401> A_IWL<2400> A_IWL<2399> A_IWL<2398> A_IWL<2397> A_IWL<2396> A_IWL<2395> A_IWL<2394> A_IWL<2393> A_IWL<2392> A_IWL<2391> A_IWL<2390> A_IWL<2389> A_IWL<2388> A_IWL<2387> A_IWL<2386> A_IWL<2385> A_IWL<2384> A_IWL<2383> A_IWL<2382> A_IWL<2381> A_IWL<2380> A_IWL<2379> A_IWL<2378> A_IWL<2377> A_IWL<2376> A_IWL<2375> A_IWL<2374> A_IWL<2373> A_IWL<2372> A_IWL<2371> A_IWL<2370> A_IWL<2369> A_IWL<2368> A_IWL<2367> A_IWL<2366> A_IWL<2365> A_IWL<2364> A_IWL<2363> A_IWL<2362> A_IWL<2361> A_IWL<2360> A_IWL<2359> A_IWL<2358> A_IWL<2357> A_IWL<2356> A_IWL<2355> A_IWL<2354> A_IWL<2353> A_IWL<2352> A_IWL<2351> A_IWL<2350> A_IWL<2349> A_IWL<2348> A_IWL<2347> A_IWL<2346> A_IWL<2345> A_IWL<2344> A_IWL<2343> A_IWL<2342> A_IWL<2341> A_IWL<2340> A_IWL<2339> A_IWL<2338> A_IWL<2337> A_IWL<2336> A_IWL<2335> A_IWL<2334> A_IWL<2333> A_IWL<2332> A_IWL<2331> A_IWL<2330> A_IWL<2329> A_IWL<2328> A_IWL<2327> A_IWL<2326> A_IWL<2325> A_IWL<2324> A_IWL<2323> A_IWL<2322> A_IWL<2321> A_IWL<2320> A_IWL<2319> A_IWL<2318> A_IWL<2317> A_IWL<2316> A_IWL<2315> A_IWL<2314> A_IWL<2313> A_IWL<2312> A_IWL<2311> A_IWL<2310> A_IWL<2309> A_IWL<2308> A_IWL<2307> A_IWL<2306> A_IWL<2305> A_IWL<2304> A_IWL<2303> A_IWL<2302> A_IWL<2301> A_IWL<2300> A_IWL<2299> A_IWL<2298> A_IWL<2297> A_IWL<2296> A_IWL<2295> A_IWL<2294> A_IWL<2293> A_IWL<2292> A_IWL<2291> A_IWL<2290> A_IWL<2289> A_IWL<2288> A_IWL<2287> A_IWL<2286> A_IWL<2285> A_IWL<2284> A_IWL<2283> A_IWL<2282> A_IWL<2281> A_IWL<2280> A_IWL<2279> A_IWL<2278> A_IWL<2277> A_IWL<2276> A_IWL<2275> A_IWL<2274> A_IWL<2273> A_IWL<2272> A_IWL<2271> A_IWL<2270> A_IWL<2269> A_IWL<2268> A_IWL<2267> A_IWL<2266> A_IWL<2265> A_IWL<2264> A_IWL<2263> A_IWL<2262> A_IWL<2261> A_IWL<2260> A_IWL<2259> A_IWL<2258> A_IWL<2257> A_IWL<2256> A_IWL<2255> A_IWL<2254> A_IWL<2253> A_IWL<2252> A_IWL<2251> A_IWL<2250> A_IWL<2249> A_IWL<2248> A_IWL<2247> A_IWL<2246> A_IWL<2245> A_IWL<2244> A_IWL<2243> A_IWL<2242> A_IWL<2241> A_IWL<2240> A_IWL<2239> A_IWL<2238> A_IWL<2237> A_IWL<2236> A_IWL<2235> A_IWL<2234> A_IWL<2233> A_IWL<2232> A_IWL<2231> A_IWL<2230> A_IWL<2229> A_IWL<2228> A_IWL<2227> A_IWL<2226> A_IWL<2225> A_IWL<2224> A_IWL<2223> A_IWL<2222> A_IWL<2221> A_IWL<2220> A_IWL<2219> A_IWL<2218> A_IWL<2217> A_IWL<2216> A_IWL<2215> A_IWL<2214> A_IWL<2213> A_IWL<2212> A_IWL<2211> A_IWL<2210> A_IWL<2209> A_IWL<2208> A_IWL<2207> A_IWL<2206> A_IWL<2205> A_IWL<2204> A_IWL<2203> A_IWL<2202> A_IWL<2201> A_IWL<2200> A_IWL<2199> A_IWL<2198> A_IWL<2197> A_IWL<2196> A_IWL<2195> A_IWL<2194> A_IWL<2193> A_IWL<2192> A_IWL<2191> A_IWL<2190> A_IWL<2189> A_IWL<2188> A_IWL<2187> A_IWL<2186> A_IWL<2185> A_IWL<2184> A_IWL<2183> A_IWL<2182> A_IWL<2181> A_IWL<2180> A_IWL<2179> A_IWL<2178> A_IWL<2177> A_IWL<2176> A_IWL<2175> A_IWL<2174> A_IWL<2173> A_IWL<2172> A_IWL<2171> A_IWL<2170> A_IWL<2169> A_IWL<2168> A_IWL<2167> A_IWL<2166> A_IWL<2165> A_IWL<2164> A_IWL<2163> A_IWL<2162> A_IWL<2161> A_IWL<2160> A_IWL<2159> A_IWL<2158> A_IWL<2157> A_IWL<2156> A_IWL<2155> A_IWL<2154> A_IWL<2153> A_IWL<2152> A_IWL<2151> A_IWL<2150> A_IWL<2149> A_IWL<2148> A_IWL<2147> A_IWL<2146> A_IWL<2145> A_IWL<2144> A_IWL<2143> A_IWL<2142> A_IWL<2141> A_IWL<2140> A_IWL<2139> A_IWL<2138> A_IWL<2137> A_IWL<2136> A_IWL<2135> A_IWL<2134> A_IWL<2133> A_IWL<2132> A_IWL<2131> A_IWL<2130> A_IWL<2129> A_IWL<2128> A_IWL<2127> A_IWL<2126> A_IWL<2125> A_IWL<2124> A_IWL<2123> A_IWL<2122> A_IWL<2121> A_IWL<2120> A_IWL<2119> A_IWL<2118> A_IWL<2117> A_IWL<2116> A_IWL<2115> A_IWL<2114> A_IWL<2113> A_IWL<2112> A_IWL<2111> A_IWL<2110> A_IWL<2109> A_IWL<2108> A_IWL<2107> A_IWL<2106> A_IWL<2105> A_IWL<2104> A_IWL<2103> A_IWL<2102> A_IWL<2101> A_IWL<2100> A_IWL<2099> A_IWL<2098> A_IWL<2097> A_IWL<2096> A_IWL<2095> A_IWL<2094> A_IWL<2093> A_IWL<2092> A_IWL<2091> A_IWL<2090> A_IWL<2089> A_IWL<2088> A_IWL<2087> A_IWL<2086> A_IWL<2085> A_IWL<2084> A_IWL<2083> A_IWL<2082> A_IWL<2081> A_IWL<2080> A_IWL<2079> A_IWL<2078> A_IWL<2077> A_IWL<2076> A_IWL<2075> A_IWL<2074> A_IWL<2073> A_IWL<2072> A_IWL<2071> A_IWL<2070> A_IWL<2069> A_IWL<2068> A_IWL<2067> A_IWL<2066> A_IWL<2065> A_IWL<2064> A_IWL<2063> A_IWL<2062> A_IWL<2061> A_IWL<2060> A_IWL<2059> A_IWL<2058> A_IWL<2057> A_IWL<2056> A_IWL<2055> A_IWL<2054> A_IWL<2053> A_IWL<2052> A_IWL<2051> A_IWL<2050> A_IWL<2049> A_IWL<2048> A_IWL<3071> A_IWL<3070> A_IWL<3069> A_IWL<3068> A_IWL<3067> A_IWL<3066> A_IWL<3065> A_IWL<3064> A_IWL<3063> A_IWL<3062> A_IWL<3061> A_IWL<3060> A_IWL<3059> A_IWL<3058> A_IWL<3057> A_IWL<3056> A_IWL<3055> A_IWL<3054> A_IWL<3053> A_IWL<3052> A_IWL<3051> A_IWL<3050> A_IWL<3049> A_IWL<3048> A_IWL<3047> A_IWL<3046> A_IWL<3045> A_IWL<3044> A_IWL<3043> A_IWL<3042> A_IWL<3041> A_IWL<3040> A_IWL<3039> A_IWL<3038> A_IWL<3037> A_IWL<3036> A_IWL<3035> A_IWL<3034> A_IWL<3033> A_IWL<3032> A_IWL<3031> A_IWL<3030> A_IWL<3029> A_IWL<3028> A_IWL<3027> A_IWL<3026> A_IWL<3025> A_IWL<3024> A_IWL<3023> A_IWL<3022> A_IWL<3021> A_IWL<3020> A_IWL<3019> A_IWL<3018> A_IWL<3017> A_IWL<3016> A_IWL<3015> A_IWL<3014> A_IWL<3013> A_IWL<3012> A_IWL<3011> A_IWL<3010> A_IWL<3009> A_IWL<3008> A_IWL<3007> A_IWL<3006> A_IWL<3005> A_IWL<3004> A_IWL<3003> A_IWL<3002> A_IWL<3001> A_IWL<3000> A_IWL<2999> A_IWL<2998> A_IWL<2997> A_IWL<2996> A_IWL<2995> A_IWL<2994> A_IWL<2993> A_IWL<2992> A_IWL<2991> A_IWL<2990> A_IWL<2989> A_IWL<2988> A_IWL<2987> A_IWL<2986> A_IWL<2985> A_IWL<2984> A_IWL<2983> A_IWL<2982> A_IWL<2981> A_IWL<2980> A_IWL<2979> A_IWL<2978> A_IWL<2977> A_IWL<2976> A_IWL<2975> A_IWL<2974> A_IWL<2973> A_IWL<2972> A_IWL<2971> A_IWL<2970> A_IWL<2969> A_IWL<2968> A_IWL<2967> A_IWL<2966> A_IWL<2965> A_IWL<2964> A_IWL<2963> A_IWL<2962> A_IWL<2961> A_IWL<2960> A_IWL<2959> A_IWL<2958> A_IWL<2957> A_IWL<2956> A_IWL<2955> A_IWL<2954> A_IWL<2953> A_IWL<2952> A_IWL<2951> A_IWL<2950> A_IWL<2949> A_IWL<2948> A_IWL<2947> A_IWL<2946> A_IWL<2945> A_IWL<2944> A_IWL<2943> A_IWL<2942> A_IWL<2941> A_IWL<2940> A_IWL<2939> A_IWL<2938> A_IWL<2937> A_IWL<2936> A_IWL<2935> A_IWL<2934> A_IWL<2933> A_IWL<2932> A_IWL<2931> A_IWL<2930> A_IWL<2929> A_IWL<2928> A_IWL<2927> A_IWL<2926> A_IWL<2925> A_IWL<2924> A_IWL<2923> A_IWL<2922> A_IWL<2921> A_IWL<2920> A_IWL<2919> A_IWL<2918> A_IWL<2917> A_IWL<2916> A_IWL<2915> A_IWL<2914> A_IWL<2913> A_IWL<2912> A_IWL<2911> A_IWL<2910> A_IWL<2909> A_IWL<2908> A_IWL<2907> A_IWL<2906> A_IWL<2905> A_IWL<2904> A_IWL<2903> A_IWL<2902> A_IWL<2901> A_IWL<2900> A_IWL<2899> A_IWL<2898> A_IWL<2897> A_IWL<2896> A_IWL<2895> A_IWL<2894> A_IWL<2893> A_IWL<2892> A_IWL<2891> A_IWL<2890> A_IWL<2889> A_IWL<2888> A_IWL<2887> A_IWL<2886> A_IWL<2885> A_IWL<2884> A_IWL<2883> A_IWL<2882> A_IWL<2881> A_IWL<2880> A_IWL<2879> A_IWL<2878> A_IWL<2877> A_IWL<2876> A_IWL<2875> A_IWL<2874> A_IWL<2873> A_IWL<2872> A_IWL<2871> A_IWL<2870> A_IWL<2869> A_IWL<2868> A_IWL<2867> A_IWL<2866> A_IWL<2865> A_IWL<2864> A_IWL<2863> A_IWL<2862> A_IWL<2861> A_IWL<2860> A_IWL<2859> A_IWL<2858> A_IWL<2857> A_IWL<2856> A_IWL<2855> A_IWL<2854> A_IWL<2853> A_IWL<2852> A_IWL<2851> A_IWL<2850> A_IWL<2849> A_IWL<2848> A_IWL<2847> A_IWL<2846> A_IWL<2845> A_IWL<2844> A_IWL<2843> A_IWL<2842> A_IWL<2841> A_IWL<2840> A_IWL<2839> A_IWL<2838> A_IWL<2837> A_IWL<2836> A_IWL<2835> A_IWL<2834> A_IWL<2833> A_IWL<2832> A_IWL<2831> A_IWL<2830> A_IWL<2829> A_IWL<2828> A_IWL<2827> A_IWL<2826> A_IWL<2825> A_IWL<2824> A_IWL<2823> A_IWL<2822> A_IWL<2821> A_IWL<2820> A_IWL<2819> A_IWL<2818> A_IWL<2817> A_IWL<2816> A_IWL<2815> A_IWL<2814> A_IWL<2813> A_IWL<2812> A_IWL<2811> A_IWL<2810> A_IWL<2809> A_IWL<2808> A_IWL<2807> A_IWL<2806> A_IWL<2805> A_IWL<2804> A_IWL<2803> A_IWL<2802> A_IWL<2801> A_IWL<2800> A_IWL<2799> A_IWL<2798> A_IWL<2797> A_IWL<2796> A_IWL<2795> A_IWL<2794> A_IWL<2793> A_IWL<2792> A_IWL<2791> A_IWL<2790> A_IWL<2789> A_IWL<2788> A_IWL<2787> A_IWL<2786> A_IWL<2785> A_IWL<2784> A_IWL<2783> A_IWL<2782> A_IWL<2781> A_IWL<2780> A_IWL<2779> A_IWL<2778> A_IWL<2777> A_IWL<2776> A_IWL<2775> A_IWL<2774> A_IWL<2773> A_IWL<2772> A_IWL<2771> A_IWL<2770> A_IWL<2769> A_IWL<2768> A_IWL<2767> A_IWL<2766> A_IWL<2765> A_IWL<2764> A_IWL<2763> A_IWL<2762> A_IWL<2761> A_IWL<2760> A_IWL<2759> A_IWL<2758> A_IWL<2757> A_IWL<2756> A_IWL<2755> A_IWL<2754> A_IWL<2753> A_IWL<2752> A_IWL<2751> A_IWL<2750> A_IWL<2749> A_IWL<2748> A_IWL<2747> A_IWL<2746> A_IWL<2745> A_IWL<2744> A_IWL<2743> A_IWL<2742> A_IWL<2741> A_IWL<2740> A_IWL<2739> A_IWL<2738> A_IWL<2737> A_IWL<2736> A_IWL<2735> A_IWL<2734> A_IWL<2733> A_IWL<2732> A_IWL<2731> A_IWL<2730> A_IWL<2729> A_IWL<2728> A_IWL<2727> A_IWL<2726> A_IWL<2725> A_IWL<2724> A_IWL<2723> A_IWL<2722> A_IWL<2721> A_IWL<2720> A_IWL<2719> A_IWL<2718> A_IWL<2717> A_IWL<2716> A_IWL<2715> A_IWL<2714> A_IWL<2713> A_IWL<2712> A_IWL<2711> A_IWL<2710> A_IWL<2709> A_IWL<2708> A_IWL<2707> A_IWL<2706> A_IWL<2705> A_IWL<2704> A_IWL<2703> A_IWL<2702> A_IWL<2701> A_IWL<2700> A_IWL<2699> A_IWL<2698> A_IWL<2697> A_IWL<2696> A_IWL<2695> A_IWL<2694> A_IWL<2693> A_IWL<2692> A_IWL<2691> A_IWL<2690> A_IWL<2689> A_IWL<2688> A_IWL<2687> A_IWL<2686> A_IWL<2685> A_IWL<2684> A_IWL<2683> A_IWL<2682> A_IWL<2681> A_IWL<2680> A_IWL<2679> A_IWL<2678> A_IWL<2677> A_IWL<2676> A_IWL<2675> A_IWL<2674> A_IWL<2673> A_IWL<2672> A_IWL<2671> A_IWL<2670> A_IWL<2669> A_IWL<2668> A_IWL<2667> A_IWL<2666> A_IWL<2665> A_IWL<2664> A_IWL<2663> A_IWL<2662> A_IWL<2661> A_IWL<2660> A_IWL<2659> A_IWL<2658> A_IWL<2657> A_IWL<2656> A_IWL<2655> A_IWL<2654> A_IWL<2653> A_IWL<2652> A_IWL<2651> A_IWL<2650> A_IWL<2649> A_IWL<2648> A_IWL<2647> A_IWL<2646> A_IWL<2645> A_IWL<2644> A_IWL<2643> A_IWL<2642> A_IWL<2641> A_IWL<2640> A_IWL<2639> A_IWL<2638> A_IWL<2637> A_IWL<2636> A_IWL<2635> A_IWL<2634> A_IWL<2633> A_IWL<2632> A_IWL<2631> A_IWL<2630> A_IWL<2629> A_IWL<2628> A_IWL<2627> A_IWL<2626> A_IWL<2625> A_IWL<2624> A_IWL<2623> A_IWL<2622> A_IWL<2621> A_IWL<2620> A_IWL<2619> A_IWL<2618> A_IWL<2617> A_IWL<2616> A_IWL<2615> A_IWL<2614> A_IWL<2613> A_IWL<2612> A_IWL<2611> A_IWL<2610> A_IWL<2609> A_IWL<2608> A_IWL<2607> A_IWL<2606> A_IWL<2605> A_IWL<2604> A_IWL<2603> A_IWL<2602> A_IWL<2601> A_IWL<2600> A_IWL<2599> A_IWL<2598> A_IWL<2597> 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A_IWL<1045> A_IWL<1044> A_IWL<1043> A_IWL<1042> A_IWL<1041> A_IWL<1040> A_IWL<1039> A_IWL<1038> A_IWL<1037> A_IWL<1036> A_IWL<1035> A_IWL<1034> A_IWL<1033> A_IWL<1032> A_IWL<1031> A_IWL<1030> A_IWL<1029> A_IWL<1028> A_IWL<1027> A_IWL<1026> A_IWL<1025> A_IWL<1024> A_IWL<2047> A_IWL<2046> A_IWL<2045> A_IWL<2044> A_IWL<2043> A_IWL<2042> A_IWL<2041> A_IWL<2040> A_IWL<2039> A_IWL<2038> A_IWL<2037> A_IWL<2036> A_IWL<2035> A_IWL<2034> A_IWL<2033> A_IWL<2032> A_IWL<2031> A_IWL<2030> A_IWL<2029> A_IWL<2028> A_IWL<2027> A_IWL<2026> A_IWL<2025> A_IWL<2024> A_IWL<2023> A_IWL<2022> A_IWL<2021> A_IWL<2020> A_IWL<2019> A_IWL<2018> A_IWL<2017> A_IWL<2016> A_IWL<2015> A_IWL<2014> A_IWL<2013> A_IWL<2012> A_IWL<2011> A_IWL<2010> A_IWL<2009> A_IWL<2008> A_IWL<2007> A_IWL<2006> A_IWL<2005> A_IWL<2004> A_IWL<2003> A_IWL<2002> A_IWL<2001> A_IWL<2000> A_IWL<1999> A_IWL<1998> A_IWL<1997> A_IWL<1996> A_IWL<1995> A_IWL<1994> A_IWL<1993> A_IWL<1992> A_IWL<1991> A_IWL<1990> A_IWL<1989> A_IWL<1988> A_IWL<1987> A_IWL<1986> A_IWL<1985> A_IWL<1984> A_IWL<1983> A_IWL<1982> A_IWL<1981> A_IWL<1980> A_IWL<1979> A_IWL<1978> A_IWL<1977> A_IWL<1976> A_IWL<1975> A_IWL<1974> A_IWL<1973> A_IWL<1972> A_IWL<1971> A_IWL<1970> A_IWL<1969> A_IWL<1968> A_IWL<1967> A_IWL<1966> A_IWL<1965> A_IWL<1964> A_IWL<1963> A_IWL<1962> A_IWL<1961> A_IWL<1960> A_IWL<1959> A_IWL<1958> A_IWL<1957> A_IWL<1956> A_IWL<1955> A_IWL<1954> A_IWL<1953> A_IWL<1952> A_IWL<1951> A_IWL<1950> A_IWL<1949> A_IWL<1948> A_IWL<1947> A_IWL<1946> A_IWL<1945> A_IWL<1944> A_IWL<1943> A_IWL<1942> A_IWL<1941> A_IWL<1940> A_IWL<1939> A_IWL<1938> A_IWL<1937> A_IWL<1936> A_IWL<1935> A_IWL<1934> A_IWL<1933> A_IWL<1932> A_IWL<1931> A_IWL<1930> A_IWL<1929> A_IWL<1928> A_IWL<1927> A_IWL<1926> A_IWL<1925> A_IWL<1924> A_IWL<1923> A_IWL<1922> A_IWL<1921> A_IWL<1920> A_IWL<1919> A_IWL<1918> A_IWL<1917> A_IWL<1916> A_IWL<1915> A_IWL<1914> A_IWL<1913> A_IWL<1912> A_IWL<1911> A_IWL<1910> A_IWL<1909> A_IWL<1908> A_IWL<1907> A_IWL<1906> A_IWL<1905> A_IWL<1904> A_IWL<1903> A_IWL<1902> A_IWL<1901> A_IWL<1900> A_IWL<1899> A_IWL<1898> A_IWL<1897> A_IWL<1896> A_IWL<1895> A_IWL<1894> A_IWL<1893> A_IWL<1892> A_IWL<1891> A_IWL<1890> A_IWL<1889> A_IWL<1888> A_IWL<1887> A_IWL<1886> A_IWL<1885> A_IWL<1884> A_IWL<1883> A_IWL<1882> A_IWL<1881> A_IWL<1880> A_IWL<1879> A_IWL<1878> A_IWL<1877> A_IWL<1876> A_IWL<1875> A_IWL<1874> A_IWL<1873> A_IWL<1872> A_IWL<1871> A_IWL<1870> A_IWL<1869> A_IWL<1868> A_IWL<1867> A_IWL<1866> A_IWL<1865> A_IWL<1864> A_IWL<1863> A_IWL<1862> A_IWL<1861> A_IWL<1860> A_IWL<1859> A_IWL<1858> A_IWL<1857> A_IWL<1856> A_IWL<1855> A_IWL<1854> A_IWL<1853> A_IWL<1852> A_IWL<1851> A_IWL<1850> A_IWL<1849> A_IWL<1848> A_IWL<1847> A_IWL<1846> A_IWL<1845> A_IWL<1844> A_IWL<1843> A_IWL<1842> A_IWL<1841> A_IWL<1840> A_IWL<1839> A_IWL<1838> A_IWL<1837> A_IWL<1836> A_IWL<1835> A_IWL<1834> A_IWL<1833> A_IWL<1832> A_IWL<1831> A_IWL<1830> A_IWL<1829> A_IWL<1828> A_IWL<1827> A_IWL<1826> A_IWL<1825> A_IWL<1824> A_IWL<1823> A_IWL<1822> A_IWL<1821> A_IWL<1820> A_IWL<1819> A_IWL<1818> A_IWL<1817> A_IWL<1816> A_IWL<1815> A_IWL<1814> A_IWL<1813> A_IWL<1812> A_IWL<1811> A_IWL<1810> A_IWL<1809> A_IWL<1808> A_IWL<1807> A_IWL<1806> A_IWL<1805> A_IWL<1804> A_IWL<1803> A_IWL<1802> A_IWL<1801> A_IWL<1800> A_IWL<1799> A_IWL<1798> A_IWL<1797> A_IWL<1796> A_IWL<1795> A_IWL<1794> A_IWL<1793> A_IWL<1792> A_IWL<1791> A_IWL<1790> A_IWL<1789> A_IWL<1788> A_IWL<1787> A_IWL<1786> A_IWL<1785> A_IWL<1784> A_IWL<1783> A_IWL<1782> A_IWL<1781> A_IWL<1780> A_IWL<1779> A_IWL<1778> A_IWL<1777> A_IWL<1776> A_IWL<1775> A_IWL<1774> A_IWL<1773> A_IWL<1772> A_IWL<1771> A_IWL<1770> A_IWL<1769> A_IWL<1768> A_IWL<1767> A_IWL<1766> A_IWL<1765> A_IWL<1764> A_IWL<1763> A_IWL<1762> A_IWL<1761> A_IWL<1760> A_IWL<1759> A_IWL<1758> A_IWL<1757> A_IWL<1756> A_IWL<1755> A_IWL<1754> A_IWL<1753> A_IWL<1752> A_IWL<1751> A_IWL<1750> A_IWL<1749> A_IWL<1748> A_IWL<1747> A_IWL<1746> A_IWL<1745> A_IWL<1744> A_IWL<1743> A_IWL<1742> A_IWL<1741> A_IWL<1740> A_IWL<1739> A_IWL<1738> A_IWL<1737> A_IWL<1736> A_IWL<1735> A_IWL<1734> A_IWL<1733> A_IWL<1732> A_IWL<1731> A_IWL<1730> A_IWL<1729> A_IWL<1728> A_IWL<1727> A_IWL<1726> A_IWL<1725> A_IWL<1724> A_IWL<1723> A_IWL<1722> A_IWL<1721> A_IWL<1720> A_IWL<1719> A_IWL<1718> A_IWL<1717> A_IWL<1716> A_IWL<1715> A_IWL<1714> A_IWL<1713> A_IWL<1712> A_IWL<1711> A_IWL<1710> A_IWL<1709> A_IWL<1708> A_IWL<1707> A_IWL<1706> A_IWL<1705> A_IWL<1704> A_IWL<1703> A_IWL<1702> A_IWL<1701> A_IWL<1700> A_IWL<1699> A_IWL<1698> A_IWL<1697> A_IWL<1696> A_IWL<1695> A_IWL<1694> A_IWL<1693> A_IWL<1692> A_IWL<1691> A_IWL<1690> A_IWL<1689> A_IWL<1688> A_IWL<1687> A_IWL<1686> A_IWL<1685> A_IWL<1684> A_IWL<1683> A_IWL<1682> A_IWL<1681> A_IWL<1680> A_IWL<1679> A_IWL<1678> A_IWL<1677> A_IWL<1676> A_IWL<1675> A_IWL<1674> A_IWL<1673> A_IWL<1672> A_IWL<1671> A_IWL<1670> A_IWL<1669> A_IWL<1668> A_IWL<1667> A_IWL<1666> A_IWL<1665> A_IWL<1664> A_IWL<1663> A_IWL<1662> A_IWL<1661> A_IWL<1660> A_IWL<1659> A_IWL<1658> A_IWL<1657> A_IWL<1656> A_IWL<1655> A_IWL<1654> A_IWL<1653> A_IWL<1652> A_IWL<1651> A_IWL<1650> A_IWL<1649> A_IWL<1648> A_IWL<1647> A_IWL<1646> A_IWL<1645> A_IWL<1644> A_IWL<1643> A_IWL<1642> A_IWL<1641> A_IWL<1640> A_IWL<1639> A_IWL<1638> A_IWL<1637> A_IWL<1636> A_IWL<1635> A_IWL<1634> A_IWL<1633> A_IWL<1632> A_IWL<1631> A_IWL<1630> A_IWL<1629> A_IWL<1628> A_IWL<1627> A_IWL<1626> A_IWL<1625> A_IWL<1624> A_IWL<1623> A_IWL<1622> A_IWL<1621> A_IWL<1620> A_IWL<1619> A_IWL<1618> A_IWL<1617> A_IWL<1616> A_IWL<1615> A_IWL<1614> A_IWL<1613> A_IWL<1612> A_IWL<1611> A_IWL<1610> A_IWL<1609> A_IWL<1608> A_IWL<1607> A_IWL<1606> A_IWL<1605> A_IWL<1604> A_IWL<1603> A_IWL<1602> A_IWL<1601> A_IWL<1600> A_IWL<1599> A_IWL<1598> A_IWL<1597> A_IWL<1596> A_IWL<1595> A_IWL<1594> A_IWL<1593> A_IWL<1592> A_IWL<1591> A_IWL<1590> A_IWL<1589> A_IWL<1588> A_IWL<1587> A_IWL<1586> A_IWL<1585> A_IWL<1584> A_IWL<1583> A_IWL<1582> A_IWL<1581> A_IWL<1580> A_IWL<1579> A_IWL<1578> A_IWL<1577> A_IWL<1576> A_IWL<1575> A_IWL<1574> A_IWL<1573> A_IWL<1572> A_IWL<1571> A_IWL<1570> A_IWL<1569> A_IWL<1568> A_IWL<1567> A_IWL<1566> A_IWL<1565> A_IWL<1564> A_IWL<1563> A_IWL<1562> A_IWL<1561> A_IWL<1560> A_IWL<1559> A_IWL<1558> A_IWL<1557> A_IWL<1556> A_IWL<1555> A_IWL<1554> A_IWL<1553> A_IWL<1552> A_IWL<1551> A_IWL<1550> A_IWL<1549> A_IWL<1548> A_IWL<1547> A_IWL<1546> A_IWL<1545> A_IWL<1544> A_IWL<1543> A_IWL<1542> A_IWL<1541> A_IWL<1540> A_IWL<1539> A_IWL<1538> A_IWL<1537> A_IWL<1536> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_COLUMN_pcell_0
+XCOL<2> A_BLC<5> A_BLC<4> A_BLC_TOP<5> A_BLC_TOP<4> A_BLT<5> A_BLT<4> A_BLT_TOP<5> A_BLT_TOP<4> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> A_IWL<1535> A_IWL<1534> A_IWL<1533> A_IWL<1532> A_IWL<1531> A_IWL<1530> A_IWL<1529> A_IWL<1528> A_IWL<1527> A_IWL<1526> A_IWL<1525> A_IWL<1524> A_IWL<1523> A_IWL<1522> A_IWL<1521> A_IWL<1520> A_IWL<1519> A_IWL<1518> A_IWL<1517> A_IWL<1516> A_IWL<1515> A_IWL<1514> A_IWL<1513> A_IWL<1512> A_IWL<1511> A_IWL<1510> A_IWL<1509> A_IWL<1508> A_IWL<1507> A_IWL<1506> A_IWL<1505> A_IWL<1504> A_IWL<1503> A_IWL<1502> A_IWL<1501> A_IWL<1500> A_IWL<1499> A_IWL<1498> A_IWL<1497> A_IWL<1496> A_IWL<1495> A_IWL<1494> A_IWL<1493> A_IWL<1492> A_IWL<1491> A_IWL<1490> A_IWL<1489> A_IWL<1488> A_IWL<1487> A_IWL<1486> A_IWL<1485> A_IWL<1484> A_IWL<1483> A_IWL<1482> A_IWL<1481> A_IWL<1480> A_IWL<1479> A_IWL<1478> A_IWL<1477> A_IWL<1476> A_IWL<1475> A_IWL<1474> A_IWL<1473> A_IWL<1472> A_IWL<1471> A_IWL<1470> A_IWL<1469> A_IWL<1468> A_IWL<1467> A_IWL<1466> A_IWL<1465> A_IWL<1464> A_IWL<1463> A_IWL<1462> A_IWL<1461> A_IWL<1460> A_IWL<1459> A_IWL<1458> A_IWL<1457> A_IWL<1456> A_IWL<1455> A_IWL<1454> A_IWL<1453> A_IWL<1452> A_IWL<1451> A_IWL<1450> A_IWL<1449> A_IWL<1448> A_IWL<1447> A_IWL<1446> A_IWL<1445> A_IWL<1444> A_IWL<1443> A_IWL<1442> A_IWL<1441> A_IWL<1440> A_IWL<1439> A_IWL<1438> A_IWL<1437> A_IWL<1436> A_IWL<1435> A_IWL<1434> A_IWL<1433> A_IWL<1432> A_IWL<1431> A_IWL<1430> A_IWL<1429> A_IWL<1428> A_IWL<1427> A_IWL<1426> A_IWL<1425> A_IWL<1424> A_IWL<1423> A_IWL<1422> A_IWL<1421> A_IWL<1420> A_IWL<1419> A_IWL<1418> A_IWL<1417> A_IWL<1416> A_IWL<1415> A_IWL<1414> A_IWL<1413> A_IWL<1412> A_IWL<1411> A_IWL<1410> A_IWL<1409> A_IWL<1408> A_IWL<1407> A_IWL<1406> A_IWL<1405> A_IWL<1404> A_IWL<1403> A_IWL<1402> A_IWL<1401> A_IWL<1400> A_IWL<1399> A_IWL<1398> A_IWL<1397> A_IWL<1396> A_IWL<1395> A_IWL<1394> A_IWL<1393> A_IWL<1392> A_IWL<1391> A_IWL<1390> A_IWL<1389> A_IWL<1388> A_IWL<1387> A_IWL<1386> A_IWL<1385> A_IWL<1384> A_IWL<1383> A_IWL<1382> A_IWL<1381> A_IWL<1380> A_IWL<1379> A_IWL<1378> A_IWL<1377> A_IWL<1376> A_IWL<1375> A_IWL<1374> A_IWL<1373> A_IWL<1372> A_IWL<1371> A_IWL<1370> A_IWL<1369> A_IWL<1368> A_IWL<1367> A_IWL<1366> A_IWL<1365> A_IWL<1364> A_IWL<1363> A_IWL<1362> A_IWL<1361> A_IWL<1360> A_IWL<1359> A_IWL<1358> A_IWL<1357> A_IWL<1356> A_IWL<1355> A_IWL<1354> A_IWL<1353> A_IWL<1352> A_IWL<1351> A_IWL<1350> A_IWL<1349> A_IWL<1348> A_IWL<1347> A_IWL<1346> A_IWL<1345> A_IWL<1344> A_IWL<1343> A_IWL<1342> A_IWL<1341> A_IWL<1340> A_IWL<1339> A_IWL<1338> A_IWL<1337> A_IWL<1336> A_IWL<1335> A_IWL<1334> A_IWL<1333> A_IWL<1332> A_IWL<1331> A_IWL<1330> A_IWL<1329> A_IWL<1328> A_IWL<1327> A_IWL<1326> A_IWL<1325> A_IWL<1324> A_IWL<1323> A_IWL<1322> A_IWL<1321> A_IWL<1320> A_IWL<1319> A_IWL<1318> A_IWL<1317> A_IWL<1316> A_IWL<1315> A_IWL<1314> A_IWL<1313> A_IWL<1312> A_IWL<1311> A_IWL<1310> A_IWL<1309> A_IWL<1308> A_IWL<1307> A_IWL<1306> A_IWL<1305> A_IWL<1304> A_IWL<1303> A_IWL<1302> A_IWL<1301> A_IWL<1300> A_IWL<1299> A_IWL<1298> A_IWL<1297> A_IWL<1296> A_IWL<1295> A_IWL<1294> A_IWL<1293> A_IWL<1292> A_IWL<1291> A_IWL<1290> A_IWL<1289> A_IWL<1288> A_IWL<1287> A_IWL<1286> A_IWL<1285> A_IWL<1284> A_IWL<1283> A_IWL<1282> A_IWL<1281> A_IWL<1280> A_IWL<1279> A_IWL<1278> A_IWL<1277> A_IWL<1276> A_IWL<1275> A_IWL<1274> A_IWL<1273> A_IWL<1272> A_IWL<1271> A_IWL<1270> A_IWL<1269> A_IWL<1268> A_IWL<1267> A_IWL<1266> A_IWL<1265> A_IWL<1264> A_IWL<1263> A_IWL<1262> A_IWL<1261> A_IWL<1260> A_IWL<1259> A_IWL<1258> A_IWL<1257> A_IWL<1256> A_IWL<1255> A_IWL<1254> A_IWL<1253> A_IWL<1252> A_IWL<1251> A_IWL<1250> A_IWL<1249> A_IWL<1248> A_IWL<1247> A_IWL<1246> A_IWL<1245> A_IWL<1244> A_IWL<1243> A_IWL<1242> A_IWL<1241> A_IWL<1240> A_IWL<1239> A_IWL<1238> A_IWL<1237> A_IWL<1236> A_IWL<1235> A_IWL<1234> A_IWL<1233> A_IWL<1232> A_IWL<1231> A_IWL<1230> A_IWL<1229> A_IWL<1228> A_IWL<1227> A_IWL<1226> A_IWL<1225> A_IWL<1224> A_IWL<1223> A_IWL<1222> A_IWL<1221> A_IWL<1220> A_IWL<1219> A_IWL<1218> A_IWL<1217> A_IWL<1216> A_IWL<1215> A_IWL<1214> A_IWL<1213> A_IWL<1212> A_IWL<1211> A_IWL<1210> A_IWL<1209> A_IWL<1208> A_IWL<1207> A_IWL<1206> A_IWL<1205> A_IWL<1204> A_IWL<1203> A_IWL<1202> A_IWL<1201> A_IWL<1200> A_IWL<1199> A_IWL<1198> A_IWL<1197> A_IWL<1196> A_IWL<1195> A_IWL<1194> A_IWL<1193> A_IWL<1192> A_IWL<1191> A_IWL<1190> A_IWL<1189> A_IWL<1188> A_IWL<1187> A_IWL<1186> A_IWL<1185> A_IWL<1184> A_IWL<1183> A_IWL<1182> A_IWL<1181> A_IWL<1180> A_IWL<1179> A_IWL<1178> A_IWL<1177> A_IWL<1176> A_IWL<1175> A_IWL<1174> A_IWL<1173> A_IWL<1172> A_IWL<1171> A_IWL<1170> A_IWL<1169> A_IWL<1168> A_IWL<1167> A_IWL<1166> A_IWL<1165> A_IWL<1164> A_IWL<1163> A_IWL<1162> A_IWL<1161> A_IWL<1160> A_IWL<1159> A_IWL<1158> A_IWL<1157> A_IWL<1156> A_IWL<1155> A_IWL<1154> A_IWL<1153> A_IWL<1152> A_IWL<1151> A_IWL<1150> A_IWL<1149> A_IWL<1148> A_IWL<1147> A_IWL<1146> A_IWL<1145> A_IWL<1144> A_IWL<1143> A_IWL<1142> A_IWL<1141> A_IWL<1140> A_IWL<1139> A_IWL<1138> A_IWL<1137> A_IWL<1136> A_IWL<1135> A_IWL<1134> A_IWL<1133> A_IWL<1132> A_IWL<1131> A_IWL<1130> A_IWL<1129> A_IWL<1128> A_IWL<1127> A_IWL<1126> A_IWL<1125> A_IWL<1124> A_IWL<1123> A_IWL<1122> A_IWL<1121> A_IWL<1120> A_IWL<1119> A_IWL<1118> A_IWL<1117> A_IWL<1116> A_IWL<1115> A_IWL<1114> A_IWL<1113> A_IWL<1112> A_IWL<1111> A_IWL<1110> A_IWL<1109> A_IWL<1108> A_IWL<1107> A_IWL<1106> A_IWL<1105> A_IWL<1104> A_IWL<1103> A_IWL<1102> A_IWL<1101> A_IWL<1100> A_IWL<1099> A_IWL<1098> A_IWL<1097> A_IWL<1096> A_IWL<1095> A_IWL<1094> A_IWL<1093> A_IWL<1092> A_IWL<1091> A_IWL<1090> A_IWL<1089> A_IWL<1088> A_IWL<1087> A_IWL<1086> A_IWL<1085> A_IWL<1084> A_IWL<1083> A_IWL<1082> A_IWL<1081> A_IWL<1080> A_IWL<1079> A_IWL<1078> A_IWL<1077> A_IWL<1076> A_IWL<1075> A_IWL<1074> A_IWL<1073> A_IWL<1072> A_IWL<1071> A_IWL<1070> A_IWL<1069> A_IWL<1068> A_IWL<1067> A_IWL<1066> A_IWL<1065> A_IWL<1064> A_IWL<1063> A_IWL<1062> A_IWL<1061> A_IWL<1060> A_IWL<1059> A_IWL<1058> A_IWL<1057> A_IWL<1056> A_IWL<1055> A_IWL<1054> A_IWL<1053> A_IWL<1052> A_IWL<1051> A_IWL<1050> A_IWL<1049> A_IWL<1048> A_IWL<1047> A_IWL<1046> A_IWL<1045> A_IWL<1044> A_IWL<1043> A_IWL<1042> A_IWL<1041> A_IWL<1040> A_IWL<1039> A_IWL<1038> A_IWL<1037> A_IWL<1036> A_IWL<1035> A_IWL<1034> A_IWL<1033> A_IWL<1032> A_IWL<1031> A_IWL<1030> A_IWL<1029> A_IWL<1028> A_IWL<1027> A_IWL<1026> A_IWL<1025> A_IWL<1024> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_COLUMN_pcell_0
+XCOL<1> A_BLC<3> A_BLC<2> A_BLC_TOP<3> A_BLC_TOP<2> A_BLT<3> A_BLT<2> A_BLT_TOP<3> A_BLT_TOP<2> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> A_IWL<1023> A_IWL<1022> A_IWL<1021> A_IWL<1020> A_IWL<1019> A_IWL<1018> A_IWL<1017> A_IWL<1016> A_IWL<1015> A_IWL<1014> A_IWL<1013> A_IWL<1012> A_IWL<1011> A_IWL<1010> A_IWL<1009> A_IWL<1008> A_IWL<1007> A_IWL<1006> A_IWL<1005> A_IWL<1004> A_IWL<1003> A_IWL<1002> A_IWL<1001> A_IWL<1000> A_IWL<999> A_IWL<998> A_IWL<997> A_IWL<996> A_IWL<995> A_IWL<994> A_IWL<993> A_IWL<992> A_IWL<991> A_IWL<990> A_IWL<989> A_IWL<988> A_IWL<987> A_IWL<986> A_IWL<985> A_IWL<984> A_IWL<983> A_IWL<982> A_IWL<981> A_IWL<980> A_IWL<979> A_IWL<978> A_IWL<977> A_IWL<976> A_IWL<975> A_IWL<974> A_IWL<973> A_IWL<972> A_IWL<971> A_IWL<970> A_IWL<969> A_IWL<968> A_IWL<967> A_IWL<966> A_IWL<965> A_IWL<964> A_IWL<963> A_IWL<962> A_IWL<961> A_IWL<960> A_IWL<959> A_IWL<958> A_IWL<957> A_IWL<956> A_IWL<955> A_IWL<954> A_IWL<953> A_IWL<952> A_IWL<951> A_IWL<950> A_IWL<949> A_IWL<948> A_IWL<947> A_IWL<946> A_IWL<945> A_IWL<944> A_IWL<943> A_IWL<942> A_IWL<941> A_IWL<940> A_IWL<939> A_IWL<938> A_IWL<937> A_IWL<936> A_IWL<935> A_IWL<934> A_IWL<933> A_IWL<932> A_IWL<931> A_IWL<930> A_IWL<929> A_IWL<928> A_IWL<927> A_IWL<926> A_IWL<925> A_IWL<924> A_IWL<923> A_IWL<922> A_IWL<921> A_IWL<920> A_IWL<919> A_IWL<918> A_IWL<917> A_IWL<916> A_IWL<915> A_IWL<914> A_IWL<913> A_IWL<912> A_IWL<911> A_IWL<910> A_IWL<909> A_IWL<908> A_IWL<907> A_IWL<906> A_IWL<905> A_IWL<904> A_IWL<903> A_IWL<902> A_IWL<901> A_IWL<900> A_IWL<899> A_IWL<898> A_IWL<897> A_IWL<896> A_IWL<895> A_IWL<894> A_IWL<893> A_IWL<892> A_IWL<891> A_IWL<890> A_IWL<889> A_IWL<888> A_IWL<887> A_IWL<886> A_IWL<885> A_IWL<884> A_IWL<883> A_IWL<882> A_IWL<881> A_IWL<880> A_IWL<879> A_IWL<878> A_IWL<877> A_IWL<876> A_IWL<875> A_IWL<874> A_IWL<873> A_IWL<872> A_IWL<871> A_IWL<870> A_IWL<869> A_IWL<868> A_IWL<867> A_IWL<866> A_IWL<865> A_IWL<864> A_IWL<863> A_IWL<862> A_IWL<861> A_IWL<860> A_IWL<859> A_IWL<858> A_IWL<857> A_IWL<856> A_IWL<855> A_IWL<854> A_IWL<853> A_IWL<852> A_IWL<851> A_IWL<850> A_IWL<849> A_IWL<848> A_IWL<847> A_IWL<846> A_IWL<845> A_IWL<844> A_IWL<843> A_IWL<842> A_IWL<841> A_IWL<840> A_IWL<839> A_IWL<838> A_IWL<837> A_IWL<836> A_IWL<835> A_IWL<834> A_IWL<833> A_IWL<832> A_IWL<831> A_IWL<830> A_IWL<829> A_IWL<828> A_IWL<827> A_IWL<826> A_IWL<825> A_IWL<824> A_IWL<823> A_IWL<822> A_IWL<821> A_IWL<820> A_IWL<819> A_IWL<818> A_IWL<817> A_IWL<816> A_IWL<815> A_IWL<814> A_IWL<813> A_IWL<812> A_IWL<811> A_IWL<810> A_IWL<809> A_IWL<808> A_IWL<807> A_IWL<806> A_IWL<805> A_IWL<804> A_IWL<803> A_IWL<802> A_IWL<801> A_IWL<800> A_IWL<799> A_IWL<798> A_IWL<797> A_IWL<796> A_IWL<795> A_IWL<794> A_IWL<793> A_IWL<792> A_IWL<791> A_IWL<790> A_IWL<789> A_IWL<788> A_IWL<787> A_IWL<786> A_IWL<785> A_IWL<784> A_IWL<783> A_IWL<782> A_IWL<781> A_IWL<780> A_IWL<779> A_IWL<778> A_IWL<777> A_IWL<776> A_IWL<775> A_IWL<774> A_IWL<773> A_IWL<772> A_IWL<771> A_IWL<770> A_IWL<769> A_IWL<768> A_IWL<767> A_IWL<766> A_IWL<765> A_IWL<764> A_IWL<763> A_IWL<762> A_IWL<761> A_IWL<760> A_IWL<759> A_IWL<758> A_IWL<757> A_IWL<756> A_IWL<755> A_IWL<754> A_IWL<753> A_IWL<752> A_IWL<751> A_IWL<750> A_IWL<749> A_IWL<748> A_IWL<747> A_IWL<746> A_IWL<745> A_IWL<744> A_IWL<743> A_IWL<742> A_IWL<741> A_IWL<740> A_IWL<739> A_IWL<738> A_IWL<737> A_IWL<736> A_IWL<735> A_IWL<734> A_IWL<733> A_IWL<732> A_IWL<731> A_IWL<730> A_IWL<729> A_IWL<728> A_IWL<727> A_IWL<726> A_IWL<725> A_IWL<724> A_IWL<723> A_IWL<722> A_IWL<721> A_IWL<720> A_IWL<719> A_IWL<718> A_IWL<717> A_IWL<716> A_IWL<715> A_IWL<714> A_IWL<713> A_IWL<712> A_IWL<711> A_IWL<710> A_IWL<709> A_IWL<708> A_IWL<707> A_IWL<706> A_IWL<705> A_IWL<704> A_IWL<703> A_IWL<702> A_IWL<701> A_IWL<700> A_IWL<699> A_IWL<698> A_IWL<697> A_IWL<696> A_IWL<695> A_IWL<694> A_IWL<693> A_IWL<692> A_IWL<691> A_IWL<690> A_IWL<689> A_IWL<688> A_IWL<687> A_IWL<686> A_IWL<685> A_IWL<684> A_IWL<683> A_IWL<682> A_IWL<681> A_IWL<680> A_IWL<679> A_IWL<678> A_IWL<677> A_IWL<676> A_IWL<675> A_IWL<674> A_IWL<673> A_IWL<672> A_IWL<671> A_IWL<670> A_IWL<669> A_IWL<668> A_IWL<667> A_IWL<666> A_IWL<665> A_IWL<664> A_IWL<663> A_IWL<662> A_IWL<661> A_IWL<660> A_IWL<659> A_IWL<658> A_IWL<657> A_IWL<656> A_IWL<655> A_IWL<654> A_IWL<653> A_IWL<652> A_IWL<651> A_IWL<650> A_IWL<649> A_IWL<648> A_IWL<647> A_IWL<646> A_IWL<645> A_IWL<644> A_IWL<643> A_IWL<642> A_IWL<641> A_IWL<640> A_IWL<639> A_IWL<638> A_IWL<637> A_IWL<636> A_IWL<635> A_IWL<634> A_IWL<633> A_IWL<632> A_IWL<631> A_IWL<630> A_IWL<629> A_IWL<628> A_IWL<627> A_IWL<626> A_IWL<625> A_IWL<624> A_IWL<623> A_IWL<622> A_IWL<621> A_IWL<620> A_IWL<619> A_IWL<618> A_IWL<617> A_IWL<616> A_IWL<615> A_IWL<614> A_IWL<613> A_IWL<612> A_IWL<611> A_IWL<610> A_IWL<609> A_IWL<608> A_IWL<607> A_IWL<606> A_IWL<605> A_IWL<604> A_IWL<603> A_IWL<602> A_IWL<601> A_IWL<600> A_IWL<599> A_IWL<598> A_IWL<597> A_IWL<596> A_IWL<595> A_IWL<594> A_IWL<593> A_IWL<592> A_IWL<591> A_IWL<590> A_IWL<589> A_IWL<588> A_IWL<587> A_IWL<586> A_IWL<585> A_IWL<584> A_IWL<583> A_IWL<582> A_IWL<581> A_IWL<580> A_IWL<579> A_IWL<578> A_IWL<577> A_IWL<576> A_IWL<575> A_IWL<574> A_IWL<573> A_IWL<572> A_IWL<571> A_IWL<570> A_IWL<569> A_IWL<568> A_IWL<567> A_IWL<566> A_IWL<565> A_IWL<564> A_IWL<563> A_IWL<562> A_IWL<561> A_IWL<560> A_IWL<559> A_IWL<558> A_IWL<557> A_IWL<556> A_IWL<555> A_IWL<554> A_IWL<553> A_IWL<552> A_IWL<551> A_IWL<550> A_IWL<549> A_IWL<548> A_IWL<547> A_IWL<546> A_IWL<545> A_IWL<544> A_IWL<543> A_IWL<542> A_IWL<541> A_IWL<540> A_IWL<539> A_IWL<538> A_IWL<537> A_IWL<536> A_IWL<535> A_IWL<534> A_IWL<533> A_IWL<532> A_IWL<531> A_IWL<530> A_IWL<529> A_IWL<528> A_IWL<527> A_IWL<526> A_IWL<525> A_IWL<524> A_IWL<523> A_IWL<522> A_IWL<521> A_IWL<520> A_IWL<519> A_IWL<518> A_IWL<517> A_IWL<516> A_IWL<515> A_IWL<514> A_IWL<513> A_IWL<512> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_COLUMN_pcell_0
+XCOL<0> A_BLC<1> A_BLC<0> A_BLC_TOP<1> A_BLC_TOP<0> A_BLT<1> A_BLT<0> A_BLT_TOP<1> A_BLT_TOP<0> A_WL<511> A_WL<510> A_WL<509> A_WL<508> A_WL<507> A_WL<506> A_WL<505> A_WL<504> A_WL<503> A_WL<502> A_WL<501> A_WL<500> A_WL<499> A_WL<498> A_WL<497> A_WL<496> A_WL<495> A_WL<494> A_WL<493> A_WL<492> A_WL<491> A_WL<490> A_WL<489> A_WL<488> A_WL<487> A_WL<486> A_WL<485> A_WL<484> A_WL<483> A_WL<482> A_WL<481> A_WL<480> A_WL<479> A_WL<478> A_WL<477> A_WL<476> A_WL<475> A_WL<474> A_WL<473> A_WL<472> A_WL<471> A_WL<470> A_WL<469> A_WL<468> A_WL<467> A_WL<466> A_WL<465> A_WL<464> A_WL<463> A_WL<462> A_WL<461> A_WL<460> A_WL<459> A_WL<458> A_WL<457> A_WL<456> A_WL<455> A_WL<454> A_WL<453> A_WL<452> A_WL<451> A_WL<450> A_WL<449> A_WL<448> A_WL<447> A_WL<446> A_WL<445> A_WL<444> A_WL<443> A_WL<442> A_WL<441> A_WL<440> A_WL<439> A_WL<438> A_WL<437> A_WL<436> A_WL<435> A_WL<434> A_WL<433> A_WL<432> A_WL<431> A_WL<430> A_WL<429> A_WL<428> A_WL<427> A_WL<426> A_WL<425> A_WL<424> A_WL<423> A_WL<422> A_WL<421> A_WL<420> A_WL<419> A_WL<418> A_WL<417> A_WL<416> A_WL<415> A_WL<414> A_WL<413> A_WL<412> A_WL<411> A_WL<410> A_WL<409> A_WL<408> A_WL<407> A_WL<406> A_WL<405> A_WL<404> A_WL<403> A_WL<402> A_WL<401> A_WL<400> A_WL<399> A_WL<398> A_WL<397> A_WL<396> A_WL<395> A_WL<394> A_WL<393> A_WL<392> A_WL<391> A_WL<390> A_WL<389> A_WL<388> A_WL<387> A_WL<386> A_WL<385> A_WL<384> A_WL<383> A_WL<382> A_WL<381> A_WL<380> A_WL<379> A_WL<378> A_WL<377> A_WL<376> A_WL<375> A_WL<374> A_WL<373> A_WL<372> A_WL<371> A_WL<370> A_WL<369> A_WL<368> A_WL<367> A_WL<366> A_WL<365> A_WL<364> A_WL<363> A_WL<362> A_WL<361> A_WL<360> A_WL<359> A_WL<358> A_WL<357> A_WL<356> A_WL<355> A_WL<354> A_WL<353> A_WL<352> A_WL<351> A_WL<350> A_WL<349> A_WL<348> A_WL<347> A_WL<346> A_WL<345> A_WL<344> A_WL<343> A_WL<342> A_WL<341> A_WL<340> A_WL<339> A_WL<338> A_WL<337> A_WL<336> A_WL<335> A_WL<334> A_WL<333> A_WL<332> A_WL<331> A_WL<330> A_WL<329> A_WL<328> A_WL<327> A_WL<326> A_WL<325> A_WL<324> A_WL<323> A_WL<322> A_WL<321> A_WL<320> A_WL<319> A_WL<318> A_WL<317> A_WL<316> A_WL<315> A_WL<314> A_WL<313> A_WL<312> A_WL<311> A_WL<310> A_WL<309> A_WL<308> A_WL<307> A_WL<306> A_WL<305> A_WL<304> A_WL<303> A_WL<302> A_WL<301> A_WL<300> A_WL<299> A_WL<298> A_WL<297> A_WL<296> A_WL<295> A_WL<294> A_WL<293> A_WL<292> A_WL<291> A_WL<290> A_WL<289> A_WL<288> A_WL<287> A_WL<286> A_WL<285> A_WL<284> A_WL<283> A_WL<282> A_WL<281> A_WL<280> A_WL<279> A_WL<278> A_WL<277> A_WL<276> A_WL<275> A_WL<274> A_WL<273> A_WL<272> A_WL<271> A_WL<270> A_WL<269> A_WL<268> A_WL<267> A_WL<266> A_WL<265> A_WL<264> A_WL<263> A_WL<262> A_WL<261> A_WL<260> A_WL<259> A_WL<258> A_WL<257> A_WL<256> A_WL<255> A_WL<254> A_WL<253> A_WL<252> A_WL<251> A_WL<250> A_WL<249> A_WL<248> A_WL<247> A_WL<246> A_WL<245> A_WL<244> A_WL<243> A_WL<242> A_WL<241> A_WL<240> A_WL<239> A_WL<238> A_WL<237> A_WL<236> A_WL<235> A_WL<234> A_WL<233> A_WL<232> A_WL<231> A_WL<230> A_WL<229> A_WL<228> A_WL<227> A_WL<226> A_WL<225> A_WL<224> A_WL<223> A_WL<222> A_WL<221> A_WL<220> A_WL<219> A_WL<218> A_WL<217> A_WL<216> A_WL<215> A_WL<214> A_WL<213> A_WL<212> A_WL<211> A_WL<210> A_WL<209> A_WL<208> A_WL<207> A_WL<206> A_WL<205> A_WL<204> A_WL<203> A_WL<202> A_WL<201> A_WL<200> A_WL<199> A_WL<198> A_WL<197> A_WL<196> A_WL<195> A_WL<194> A_WL<193> A_WL<192> A_WL<191> A_WL<190> A_WL<189> A_WL<188> A_WL<187> A_WL<186> A_WL<185> A_WL<184> A_WL<183> A_WL<182> A_WL<181> A_WL<180> A_WL<179> A_WL<178> A_WL<177> A_WL<176> A_WL<175> A_WL<174> A_WL<173> A_WL<172> A_WL<171> A_WL<170> A_WL<169> A_WL<168> A_WL<167> A_WL<166> A_WL<165> A_WL<164> A_WL<163> A_WL<162> A_WL<161> A_WL<160> A_WL<159> A_WL<158> A_WL<157> A_WL<156> A_WL<155> A_WL<154> A_WL<153> A_WL<152> A_WL<151> A_WL<150> A_WL<149> A_WL<148> A_WL<147> A_WL<146> A_WL<145> A_WL<144> A_WL<143> A_WL<142> A_WL<141> A_WL<140> A_WL<139> A_WL<138> A_WL<137> A_WL<136> A_WL<135> A_WL<134> A_WL<133> A_WL<132> A_WL<131> A_WL<130> A_WL<129> A_WL<128> A_WL<127> A_WL<126> A_WL<125> A_WL<124> A_WL<123> A_WL<122> A_WL<121> A_WL<120> A_WL<119> A_WL<118> A_WL<117> A_WL<116> A_WL<115> A_WL<114> A_WL<113> A_WL<112> A_WL<111> A_WL<110> A_WL<109> A_WL<108> A_WL<107> A_WL<106> A_WL<105> A_WL<104> A_WL<103> A_WL<102> A_WL<101> A_WL<100> A_WL<99> A_WL<98> A_WL<97> A_WL<96> A_WL<95> A_WL<94> A_WL<93> A_WL<92> A_WL<91> A_WL<90> A_WL<89> A_WL<88> A_WL<87> A_WL<86> A_WL<85> A_WL<84> A_WL<83> A_WL<82> A_WL<81> A_WL<80> A_WL<79> A_WL<78> A_WL<77> A_WL<76> A_WL<75> A_WL<74> A_WL<73> A_WL<72> A_WL<71> A_WL<70> A_WL<69> A_WL<68> A_WL<67> A_WL<66> A_WL<65> A_WL<64> A_WL<63> A_WL<62> A_WL<61> A_WL<60> A_WL<59> A_WL<58> A_WL<57> A_WL<56> A_WL<55> A_WL<54> A_WL<53> A_WL<52> A_WL<51> A_WL<50> A_WL<49> A_WL<48> A_WL<47> A_WL<46> A_WL<45> A_WL<44> A_WL<43> A_WL<42> A_WL<41> A_WL<40> A_WL<39> A_WL<38> A_WL<37> A_WL<36> A_WL<35> A_WL<34> A_WL<33> A_WL<32> A_WL<31> A_WL<30> A_WL<29> A_WL<28> A_WL<27> A_WL<26> A_WL<25> A_WL<24> A_WL<23> A_WL<22> A_WL<21> A_WL<20> A_WL<19> A_WL<18> A_WL<17> A_WL<16> A_WL<15> A_WL<14> A_WL<13> A_WL<12> A_WL<11> A_WL<10> A_WL<9> A_WL<8> A_WL<7> A_WL<6> A_WL<5> A_WL<4> A_WL<3> A_WL<2> A_WL<1> A_WL<0> A_IWL<511> A_IWL<510> A_IWL<509> A_IWL<508> A_IWL<507> A_IWL<506> A_IWL<505> A_IWL<504> A_IWL<503> A_IWL<502> A_IWL<501> A_IWL<500> A_IWL<499> A_IWL<498> A_IWL<497> A_IWL<496> A_IWL<495> A_IWL<494> A_IWL<493> A_IWL<492> A_IWL<491> A_IWL<490> A_IWL<489> A_IWL<488> A_IWL<487> A_IWL<486> A_IWL<485> A_IWL<484> A_IWL<483> A_IWL<482> A_IWL<481> A_IWL<480> A_IWL<479> A_IWL<478> A_IWL<477> A_IWL<476> A_IWL<475> A_IWL<474> A_IWL<473> A_IWL<472> A_IWL<471> A_IWL<470> A_IWL<469> A_IWL<468> A_IWL<467> A_IWL<466> A_IWL<465> A_IWL<464> A_IWL<463> A_IWL<462> A_IWL<461> A_IWL<460> A_IWL<459> A_IWL<458> A_IWL<457> A_IWL<456> A_IWL<455> A_IWL<454> A_IWL<453> A_IWL<452> A_IWL<451> A_IWL<450> A_IWL<449> A_IWL<448> A_IWL<447> A_IWL<446> A_IWL<445> A_IWL<444> A_IWL<443> A_IWL<442> A_IWL<441> A_IWL<440> A_IWL<439> A_IWL<438> A_IWL<437> A_IWL<436> A_IWL<435> A_IWL<434> A_IWL<433> A_IWL<432> A_IWL<431> A_IWL<430> A_IWL<429> A_IWL<428> A_IWL<427> A_IWL<426> A_IWL<425> A_IWL<424> A_IWL<423> A_IWL<422> A_IWL<421> A_IWL<420> A_IWL<419> A_IWL<418> A_IWL<417> A_IWL<416> A_IWL<415> A_IWL<414> A_IWL<413> A_IWL<412> A_IWL<411> A_IWL<410> A_IWL<409> A_IWL<408> A_IWL<407> A_IWL<406> A_IWL<405> A_IWL<404> A_IWL<403> A_IWL<402> A_IWL<401> A_IWL<400> A_IWL<399> A_IWL<398> A_IWL<397> A_IWL<396> A_IWL<395> A_IWL<394> A_IWL<393> A_IWL<392> A_IWL<391> A_IWL<390> A_IWL<389> A_IWL<388> A_IWL<387> A_IWL<386> A_IWL<385> A_IWL<384> A_IWL<383> A_IWL<382> A_IWL<381> A_IWL<380> A_IWL<379> A_IWL<378> A_IWL<377> A_IWL<376> A_IWL<375> A_IWL<374> A_IWL<373> A_IWL<372> A_IWL<371> A_IWL<370> A_IWL<369> A_IWL<368> A_IWL<367> A_IWL<366> A_IWL<365> A_IWL<364> A_IWL<363> A_IWL<362> A_IWL<361> A_IWL<360> A_IWL<359> A_IWL<358> A_IWL<357> A_IWL<356> A_IWL<355> A_IWL<354> A_IWL<353> A_IWL<352> A_IWL<351> A_IWL<350> A_IWL<349> A_IWL<348> A_IWL<347> A_IWL<346> A_IWL<345> A_IWL<344> A_IWL<343> A_IWL<342> A_IWL<341> A_IWL<340> A_IWL<339> A_IWL<338> A_IWL<337> A_IWL<336> A_IWL<335> A_IWL<334> A_IWL<333> A_IWL<332> A_IWL<331> A_IWL<330> A_IWL<329> A_IWL<328> A_IWL<327> A_IWL<326> A_IWL<325> A_IWL<324> A_IWL<323> A_IWL<322> A_IWL<321> A_IWL<320> A_IWL<319> A_IWL<318> A_IWL<317> A_IWL<316> A_IWL<315> A_IWL<314> A_IWL<313> A_IWL<312> A_IWL<311> A_IWL<310> A_IWL<309> A_IWL<308> A_IWL<307> A_IWL<306> A_IWL<305> A_IWL<304> A_IWL<303> A_IWL<302> A_IWL<301> A_IWL<300> A_IWL<299> A_IWL<298> A_IWL<297> A_IWL<296> A_IWL<295> A_IWL<294> A_IWL<293> A_IWL<292> A_IWL<291> A_IWL<290> A_IWL<289> A_IWL<288> A_IWL<287> A_IWL<286> A_IWL<285> A_IWL<284> A_IWL<283> A_IWL<282> A_IWL<281> A_IWL<280> A_IWL<279> A_IWL<278> A_IWL<277> A_IWL<276> A_IWL<275> A_IWL<274> A_IWL<273> A_IWL<272> A_IWL<271> A_IWL<270> A_IWL<269> A_IWL<268> A_IWL<267> A_IWL<266> A_IWL<265> A_IWL<264> A_IWL<263> A_IWL<262> A_IWL<261> A_IWL<260> A_IWL<259> A_IWL<258> A_IWL<257> A_IWL<256> A_IWL<255> A_IWL<254> A_IWL<253> A_IWL<252> A_IWL<251> A_IWL<250> A_IWL<249> A_IWL<248> A_IWL<247> A_IWL<246> A_IWL<245> A_IWL<244> A_IWL<243> A_IWL<242> A_IWL<241> A_IWL<240> A_IWL<239> A_IWL<238> A_IWL<237> A_IWL<236> A_IWL<235> A_IWL<234> A_IWL<233> A_IWL<232> A_IWL<231> A_IWL<230> A_IWL<229> A_IWL<228> A_IWL<227> A_IWL<226> A_IWL<225> A_IWL<224> A_IWL<223> A_IWL<222> A_IWL<221> A_IWL<220> A_IWL<219> A_IWL<218> A_IWL<217> A_IWL<216> A_IWL<215> A_IWL<214> A_IWL<213> A_IWL<212> A_IWL<211> A_IWL<210> A_IWL<209> A_IWL<208> A_IWL<207> A_IWL<206> A_IWL<205> A_IWL<204> A_IWL<203> A_IWL<202> A_IWL<201> A_IWL<200> A_IWL<199> A_IWL<198> A_IWL<197> A_IWL<196> A_IWL<195> A_IWL<194> A_IWL<193> A_IWL<192> A_IWL<191> A_IWL<190> A_IWL<189> A_IWL<188> A_IWL<187> A_IWL<186> A_IWL<185> A_IWL<184> A_IWL<183> A_IWL<182> A_IWL<181> A_IWL<180> A_IWL<179> A_IWL<178> A_IWL<177> A_IWL<176> A_IWL<175> A_IWL<174> A_IWL<173> A_IWL<172> A_IWL<171> A_IWL<170> A_IWL<169> A_IWL<168> A_IWL<167> A_IWL<166> A_IWL<165> A_IWL<164> A_IWL<163> A_IWL<162> A_IWL<161> A_IWL<160> A_IWL<159> A_IWL<158> A_IWL<157> A_IWL<156> A_IWL<155> A_IWL<154> A_IWL<153> A_IWL<152> A_IWL<151> A_IWL<150> A_IWL<149> A_IWL<148> A_IWL<147> A_IWL<146> A_IWL<145> A_IWL<144> A_IWL<143> A_IWL<142> A_IWL<141> A_IWL<140> A_IWL<139> A_IWL<138> A_IWL<137> A_IWL<136> A_IWL<135> A_IWL<134> A_IWL<133> A_IWL<132> A_IWL<131> A_IWL<130> A_IWL<129> A_IWL<128> A_IWL<127> A_IWL<126> A_IWL<125> A_IWL<124> A_IWL<123> A_IWL<122> A_IWL<121> A_IWL<120> A_IWL<119> A_IWL<118> A_IWL<117> A_IWL<116> A_IWL<115> A_IWL<114> A_IWL<113> A_IWL<112> A_IWL<111> A_IWL<110> A_IWL<109> A_IWL<108> A_IWL<107> A_IWL<106> A_IWL<105> A_IWL<104> A_IWL<103> A_IWL<102> A_IWL<101> A_IWL<100> A_IWL<99> A_IWL<98> A_IWL<97> A_IWL<96> A_IWL<95> A_IWL<94> A_IWL<93> A_IWL<92> A_IWL<91> A_IWL<90> A_IWL<89> A_IWL<88> A_IWL<87> A_IWL<86> A_IWL<85> A_IWL<84> A_IWL<83> A_IWL<82> A_IWL<81> A_IWL<80> A_IWL<79> A_IWL<78> A_IWL<77> A_IWL<76> A_IWL<75> A_IWL<74> A_IWL<73> A_IWL<72> A_IWL<71> A_IWL<70> A_IWL<69> A_IWL<68> A_IWL<67> A_IWL<66> A_IWL<65> A_IWL<64> A_IWL<63> A_IWL<62> A_IWL<61> A_IWL<60> A_IWL<59> A_IWL<58> A_IWL<57> A_IWL<56> A_IWL<55> A_IWL<54> A_IWL<53> A_IWL<52> A_IWL<51> A_IWL<50> A_IWL<49> A_IWL<48> A_IWL<47> A_IWL<46> A_IWL<45> A_IWL<44> A_IWL<43> A_IWL<42> A_IWL<41> A_IWL<40> A_IWL<39> A_IWL<38> A_IWL<37> A_IWL<36> A_IWL<35> A_IWL<34> A_IWL<33> A_IWL<32> A_IWL<31> A_IWL<30> A_IWL<29> A_IWL<28> A_IWL<27> A_IWL<26> A_IWL<25> A_IWL<24> A_IWL<23> A_IWL<22> A_IWL<21> A_IWL<20> A_IWL<19> A_IWL<18> A_IWL<17> A_IWL<16> A_IWL<15> A_IWL<14> A_IWL<13> A_IWL<12> A_IWL<11> A_IWL<10> A_IWL<9> A_IWL<8> A_IWL<7> A_IWL<6> A_IWL<5> A_IWL<4> A_IWL<3> A_IWL<2> A_IWL<1> A_IWL<0> VDD_CORE VSS / RM_IHPSG13_4096x8_c3_1P_COLUMN_pcell_0
+.ENDS
+
+
+
+
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_DLY_pcell_2 A Z VDD VSS
+	XIDL<3> D<7> Z VDD VSS / RSC_IHPSG13_CDLYX1 
+	XIDL<2> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1 
+	XIDL<1> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1 
+	XIDM<5> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY 
+	XIDM<4> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY 
+	XIDM<3> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY 
+	XIDM<2> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY 
+	XIDM<1> A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY 
+.ENDS
+
+
+.SUBCKT RM_IHPSG13_4096x8_c3_1P_DLY_pcell_3 A Z VDD VSS
+	XIDL<7> D<7> Z VDD VSS / RSC_IHPSG13_CDLYX1 
+	XIDL<6> D<6> D<7> VDD VSS / RSC_IHPSG13_CDLYX1 
+	XIDL<5> D<5> D<6> VDD VSS / RSC_IHPSG13_CDLYX1 
+	XIDL<4> D<4> D<5> VDD VSS / RSC_IHPSG13_CDLYX1 
+	XIDL<3> D<3> D<4> VDD VSS / RSC_IHPSG13_CDLYX1 
+	XIDL<2> D<2> D<3> VDD VSS / RSC_IHPSG13_CDLYX1 
+	XIDL<1> D<1> D<2> VDD VSS / RSC_IHPSG13_CDLYX1 
+	XIDM A D<1> VDD VSS / RSC_IHPSG13_CDLYX1_DUMMY 
+.ENDS
+
+
+
+.SUBCKT RM_IHPSG13_1P_4096x8_c3_bm_bist A_ADDR<11> A_ADDR<10> A_ADDR<9> A_ADDR<8> A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> A_ADDR<2> A_ADDR<1> A_ADDR<0> A_BIST_ADDR<11> A_BIST_ADDR<10> A_BIST_ADDR<9> A_BIST_ADDR<8> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_ADDR<2> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_BM<7> A_BIST_BM<6> A_BIST_BM<5> A_BIST_BM<4> A_BIST_BM<3> A_BIST_BM<2> A_BIST_BM<1> A_BIST_BM<0> A_BIST_CLK A_BIST_DIN<7> A_BIST_DIN<6> A_BIST_DIN<5> A_BIST_DIN<4> A_BIST_DIN<3> A_BIST_DIN<2> A_BIST_DIN<1> A_BIST_DIN<0> A_BIST_EN A_BIST_MEN A_BIST_REN A_BIST_WEN A_BM<7> A_BM<6> A_BM<5> A_BM<4> A_BM<3> A_BM<2> A_BM<1> A_BM<0> A_CLK A_DIN<7> A_DIN<6> A_DIN<5> A_DIN<4> A_DIN<3> A_DIN<2> A_DIN<1> A_DIN<0> A_DLY A_DOUT<7> A_DOUT<6> A_DOUT<5> A_DOUT<4> A_DOUT<3> A_DOUT<2> A_DOUT<1> A_DOUT<0> A_MEN A_REN A_WEN VDD! VDDARRAY! VSS!
+
+
+XRAM<1> a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> a_wl_r<511> a_wl_r<510> a_wl_r<509> a_wl_r<508> a_wl_r<507> a_wl_r<506> a_wl_r<505> a_wl_r<504> a_wl_r<503> a_wl_r<502> a_wl_r<501> a_wl_r<500> a_wl_r<499> a_wl_r<498> a_wl_r<497> a_wl_r<496> a_wl_r<495> a_wl_r<494> a_wl_r<493> a_wl_r<492> a_wl_r<491> a_wl_r<490> a_wl_r<489> a_wl_r<488> a_wl_r<487> a_wl_r<486> a_wl_r<485> a_wl_r<484> a_wl_r<483> a_wl_r<482> a_wl_r<481> a_wl_r<480> a_wl_r<479> a_wl_r<478> a_wl_r<477> a_wl_r<476> a_wl_r<475> a_wl_r<474> a_wl_r<473> a_wl_r<472> a_wl_r<471> a_wl_r<470> a_wl_r<469> a_wl_r<468> a_wl_r<467> a_wl_r<466> a_wl_r<465> a_wl_r<464> a_wl_r<463> a_wl_r<462> a_wl_r<461> a_wl_r<460> a_wl_r<459> a_wl_r<458> a_wl_r<457> a_wl_r<456> a_wl_r<455> a_wl_r<454> a_wl_r<453> a_wl_r<452> a_wl_r<451> a_wl_r<450> a_wl_r<449> a_wl_r<448> a_wl_r<447> a_wl_r<446> a_wl_r<445> a_wl_r<444> a_wl_r<443> a_wl_r<442> a_wl_r<441> a_wl_r<440> a_wl_r<439> a_wl_r<438> a_wl_r<437> a_wl_r<436> a_wl_r<435> a_wl_r<434> a_wl_r<433> a_wl_r<432> a_wl_r<431> a_wl_r<430> a_wl_r<429> a_wl_r<428> a_wl_r<427> a_wl_r<426> a_wl_r<425> a_wl_r<424> a_wl_r<423> a_wl_r<422> a_wl_r<421> a_wl_r<420> a_wl_r<419> a_wl_r<418> a_wl_r<417> a_wl_r<416> a_wl_r<415> a_wl_r<414> a_wl_r<413> a_wl_r<412> a_wl_r<411> a_wl_r<410> a_wl_r<409> a_wl_r<408> a_wl_r<407> a_wl_r<406> a_wl_r<405> a_wl_r<404> a_wl_r<403> a_wl_r<402> a_wl_r<401> a_wl_r<400> a_wl_r<399> a_wl_r<398> a_wl_r<397> a_wl_r<396> a_wl_r<395> a_wl_r<394> a_wl_r<393> a_wl_r<392> a_wl_r<391> a_wl_r<390> a_wl_r<389> a_wl_r<388> a_wl_r<387> a_wl_r<386> a_wl_r<385> a_wl_r<384> a_wl_r<383> a_wl_r<382> a_wl_r<381> a_wl_r<380> a_wl_r<379> a_wl_r<378> a_wl_r<377> a_wl_r<376> a_wl_r<375> a_wl_r<374> a_wl_r<373> a_wl_r<372> a_wl_r<371> a_wl_r<370> a_wl_r<369> a_wl_r<368> a_wl_r<367> a_wl_r<366> a_wl_r<365> a_wl_r<364> a_wl_r<363> a_wl_r<362> a_wl_r<361> a_wl_r<360> a_wl_r<359> a_wl_r<358> a_wl_r<357> a_wl_r<356> a_wl_r<355> a_wl_r<354> a_wl_r<353> a_wl_r<352> a_wl_r<351> a_wl_r<350> a_wl_r<349> a_wl_r<348> a_wl_r<347> a_wl_r<346> a_wl_r<345> a_wl_r<344> a_wl_r<343> a_wl_r<342> a_wl_r<341> a_wl_r<340> a_wl_r<339> a_wl_r<338> a_wl_r<337> a_wl_r<336> a_wl_r<335> a_wl_r<334> a_wl_r<333> a_wl_r<332> a_wl_r<331> a_wl_r<330> a_wl_r<329> a_wl_r<328> a_wl_r<327> a_wl_r<326> a_wl_r<325> a_wl_r<324> a_wl_r<323> a_wl_r<322> a_wl_r<321> a_wl_r<320> a_wl_r<319> a_wl_r<318> a_wl_r<317> a_wl_r<316> a_wl_r<315> a_wl_r<314> a_wl_r<313> a_wl_r<312> a_wl_r<311> a_wl_r<310> a_wl_r<309> a_wl_r<308> a_wl_r<307> a_wl_r<306> a_wl_r<305> a_wl_r<304> a_wl_r<303> a_wl_r<302> a_wl_r<301> a_wl_r<300> a_wl_r<299> a_wl_r<298> a_wl_r<297> a_wl_r<296> a_wl_r<295> a_wl_r<294> a_wl_r<293> a_wl_r<292> a_wl_r<291> a_wl_r<290> a_wl_r<289> a_wl_r<288> a_wl_r<287> a_wl_r<286> a_wl_r<285> a_wl_r<284> a_wl_r<283> a_wl_r<282> a_wl_r<281> a_wl_r<280> a_wl_r<279> a_wl_r<278> a_wl_r<277> a_wl_r<276> a_wl_r<275> a_wl_r<274> a_wl_r<273> a_wl_r<272> a_wl_r<271> a_wl_r<270> a_wl_r<269> a_wl_r<268> a_wl_r<267> a_wl_r<266> a_wl_r<265> a_wl_r<264> a_wl_r<263> a_wl_r<262> a_wl_r<261> a_wl_r<260> a_wl_r<259> a_wl_r<258> a_wl_r<257> a_wl_r<256> a_wl_r<255> a_wl_r<254> a_wl_r<253> a_wl_r<252> a_wl_r<251> a_wl_r<250> a_wl_r<249> a_wl_r<248> a_wl_r<247> a_wl_r<246> a_wl_r<245> a_wl_r<244> a_wl_r<243> a_wl_r<242> a_wl_r<241> a_wl_r<240> a_wl_r<239> a_wl_r<238> a_wl_r<237> a_wl_r<236> a_wl_r<235> a_wl_r<234> a_wl_r<233> a_wl_r<232> a_wl_r<231> a_wl_r<230> a_wl_r<229> a_wl_r<228> a_wl_r<227> a_wl_r<226> a_wl_r<225> a_wl_r<224> a_wl_r<223> a_wl_r<222> a_wl_r<221> a_wl_r<220> a_wl_r<219> a_wl_r<218> a_wl_r<217> a_wl_r<216> a_wl_r<215> a_wl_r<214> a_wl_r<213> a_wl_r<212> a_wl_r<211> a_wl_r<210> a_wl_r<209> a_wl_r<208> a_wl_r<207> a_wl_r<206> a_wl_r<205> a_wl_r<204> a_wl_r<203> a_wl_r<202> a_wl_r<201> a_wl_r<200> a_wl_r<199> a_wl_r<198> a_wl_r<197> a_wl_r<196> a_wl_r<195> a_wl_r<194> a_wl_r<193> a_wl_r<192> a_wl_r<191> a_wl_r<190> a_wl_r<189> a_wl_r<188> a_wl_r<187> a_wl_r<186> a_wl_r<185> a_wl_r<184> a_wl_r<183> a_wl_r<182> a_wl_r<181> a_wl_r<180> a_wl_r<179> a_wl_r<178> a_wl_r<177> a_wl_r<176> a_wl_r<175> a_wl_r<174> a_wl_r<173> a_wl_r<172> a_wl_r<171> a_wl_r<170> a_wl_r<169> a_wl_r<168> a_wl_r<167> a_wl_r<166> a_wl_r<165> a_wl_r<164> a_wl_r<163> a_wl_r<162> a_wl_r<161> a_wl_r<160> a_wl_r<159> a_wl_r<158> a_wl_r<157> a_wl_r<156> a_wl_r<155> a_wl_r<154> a_wl_r<153> a_wl_r<152> a_wl_r<151> a_wl_r<150> a_wl_r<149> a_wl_r<148> a_wl_r<147> a_wl_r<146> a_wl_r<145> a_wl_r<144> a_wl_r<143> a_wl_r<142> a_wl_r<141> a_wl_r<140> a_wl_r<139> a_wl_r<138> a_wl_r<137> a_wl_r<136> a_wl_r<135> a_wl_r<134> a_wl_r<133> a_wl_r<132> a_wl_r<131> a_wl_r<130> a_wl_r<129> a_wl_r<128> a_wl_r<127> a_wl_r<126> a_wl_r<125> a_wl_r<124> a_wl_r<123> a_wl_r<122> a_wl_r<121> a_wl_r<120> a_wl_r<119> a_wl_r<118> a_wl_r<117> a_wl_r<116> a_wl_r<115> a_wl_r<114> a_wl_r<113> a_wl_r<112> a_wl_r<111> a_wl_r<110> a_wl_r<109> a_wl_r<108> a_wl_r<107> a_wl_r<106> a_wl_r<105> a_wl_r<104> a_wl_r<103> a_wl_r<102> a_wl_r<101> a_wl_r<100> a_wl_r<99> a_wl_r<98> a_wl_r<97> a_wl_r<96> a_wl_r<95> a_wl_r<94> a_wl_r<93> a_wl_r<92> a_wl_r<91> a_wl_r<90> a_wl_r<89> a_wl_r<88> a_wl_r<87> a_wl_r<86> a_wl_r<85> a_wl_r<84> a_wl_r<83> a_wl_r<82> a_wl_r<81> a_wl_r<80> a_wl_r<79> a_wl_r<78> a_wl_r<77> a_wl_r<76> a_wl_r<75> a_wl_r<74> a_wl_r<73> a_wl_r<72> a_wl_r<71> a_wl_r<70> a_wl_r<69> a_wl_r<68> a_wl_r<67> a_wl_r<66> a_wl_r<65> a_wl_r<64> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0> VDDARRAY! VSS! / RM_IHPSG13_4096x8_c3_1P_MATRIX_pcell_1
+XRAM<0> a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> a_wl_l<511> a_wl_l<510> a_wl_l<509> a_wl_l<508> a_wl_l<507> a_wl_l<506> a_wl_l<505> a_wl_l<504> a_wl_l<503> a_wl_l<502> a_wl_l<501> a_wl_l<500> a_wl_l<499> a_wl_l<498> a_wl_l<497> a_wl_l<496> a_wl_l<495> a_wl_l<494> a_wl_l<493> a_wl_l<492> a_wl_l<491> a_wl_l<490> a_wl_l<489> a_wl_l<488> a_wl_l<487> a_wl_l<486> a_wl_l<485> a_wl_l<484> a_wl_l<483> a_wl_l<482> a_wl_l<481> a_wl_l<480> a_wl_l<479> a_wl_l<478> a_wl_l<477> a_wl_l<476> a_wl_l<475> a_wl_l<474> a_wl_l<473> a_wl_l<472> a_wl_l<471> a_wl_l<470> a_wl_l<469> a_wl_l<468> a_wl_l<467> a_wl_l<466> a_wl_l<465> a_wl_l<464> a_wl_l<463> a_wl_l<462> a_wl_l<461> a_wl_l<460> a_wl_l<459> a_wl_l<458> a_wl_l<457> a_wl_l<456> a_wl_l<455> a_wl_l<454> a_wl_l<453> a_wl_l<452> a_wl_l<451> a_wl_l<450> a_wl_l<449> a_wl_l<448> a_wl_l<447> a_wl_l<446> a_wl_l<445> a_wl_l<444> a_wl_l<443> a_wl_l<442> a_wl_l<441> a_wl_l<440> a_wl_l<439> a_wl_l<438> a_wl_l<437> a_wl_l<436> a_wl_l<435> a_wl_l<434> a_wl_l<433> a_wl_l<432> a_wl_l<431> a_wl_l<430> a_wl_l<429> a_wl_l<428> a_wl_l<427> a_wl_l<426> a_wl_l<425> a_wl_l<424> a_wl_l<423> a_wl_l<422> a_wl_l<421> a_wl_l<420> a_wl_l<419> a_wl_l<418> a_wl_l<417> a_wl_l<416> a_wl_l<415> a_wl_l<414> a_wl_l<413> a_wl_l<412> a_wl_l<411> a_wl_l<410> a_wl_l<409> a_wl_l<408> a_wl_l<407> a_wl_l<406> a_wl_l<405> a_wl_l<404> a_wl_l<403> a_wl_l<402> a_wl_l<401> a_wl_l<400> a_wl_l<399> a_wl_l<398> a_wl_l<397> a_wl_l<396> a_wl_l<395> a_wl_l<394> a_wl_l<393> a_wl_l<392> a_wl_l<391> a_wl_l<390> a_wl_l<389> a_wl_l<388> a_wl_l<387> a_wl_l<386> a_wl_l<385> a_wl_l<384> a_wl_l<383> a_wl_l<382> a_wl_l<381> a_wl_l<380> a_wl_l<379> a_wl_l<378> a_wl_l<377> a_wl_l<376> a_wl_l<375> a_wl_l<374> a_wl_l<373> a_wl_l<372> a_wl_l<371> a_wl_l<370> a_wl_l<369> a_wl_l<368> a_wl_l<367> a_wl_l<366> a_wl_l<365> a_wl_l<364> a_wl_l<363> a_wl_l<362> a_wl_l<361> a_wl_l<360> a_wl_l<359> a_wl_l<358> a_wl_l<357> a_wl_l<356> a_wl_l<355> a_wl_l<354> a_wl_l<353> a_wl_l<352> a_wl_l<351> a_wl_l<350> a_wl_l<349> a_wl_l<348> a_wl_l<347> a_wl_l<346> a_wl_l<345> a_wl_l<344> a_wl_l<343> a_wl_l<342> a_wl_l<341> a_wl_l<340> a_wl_l<339> a_wl_l<338> a_wl_l<337> a_wl_l<336> a_wl_l<335> a_wl_l<334> a_wl_l<333> a_wl_l<332> a_wl_l<331> a_wl_l<330> a_wl_l<329> a_wl_l<328> a_wl_l<327> a_wl_l<326> a_wl_l<325> a_wl_l<324> a_wl_l<323> a_wl_l<322> a_wl_l<321> a_wl_l<320> a_wl_l<319> a_wl_l<318> a_wl_l<317> a_wl_l<316> a_wl_l<315> a_wl_l<314> a_wl_l<313> a_wl_l<312> a_wl_l<311> a_wl_l<310> a_wl_l<309> a_wl_l<308> a_wl_l<307> a_wl_l<306> a_wl_l<305> a_wl_l<304> a_wl_l<303> a_wl_l<302> a_wl_l<301> a_wl_l<300> a_wl_l<299> a_wl_l<298> a_wl_l<297> a_wl_l<296> a_wl_l<295> a_wl_l<294> a_wl_l<293> a_wl_l<292> a_wl_l<291> a_wl_l<290> a_wl_l<289> a_wl_l<288> a_wl_l<287> a_wl_l<286> a_wl_l<285> a_wl_l<284> a_wl_l<283> a_wl_l<282> a_wl_l<281> a_wl_l<280> a_wl_l<279> a_wl_l<278> a_wl_l<277> a_wl_l<276> a_wl_l<275> a_wl_l<274> a_wl_l<273> a_wl_l<272> a_wl_l<271> a_wl_l<270> a_wl_l<269> a_wl_l<268> a_wl_l<267> a_wl_l<266> a_wl_l<265> a_wl_l<264> a_wl_l<263> a_wl_l<262> a_wl_l<261> a_wl_l<260> a_wl_l<259> a_wl_l<258> a_wl_l<257> a_wl_l<256> a_wl_l<255> a_wl_l<254> a_wl_l<253> a_wl_l<252> a_wl_l<251> a_wl_l<250> a_wl_l<249> a_wl_l<248> a_wl_l<247> a_wl_l<246> a_wl_l<245> a_wl_l<244> a_wl_l<243> a_wl_l<242> a_wl_l<241> a_wl_l<240> a_wl_l<239> a_wl_l<238> a_wl_l<237> a_wl_l<236> a_wl_l<235> a_wl_l<234> a_wl_l<233> a_wl_l<232> a_wl_l<231> a_wl_l<230> a_wl_l<229> a_wl_l<228> a_wl_l<227> a_wl_l<226> a_wl_l<225> a_wl_l<224> a_wl_l<223> a_wl_l<222> a_wl_l<221> a_wl_l<220> a_wl_l<219> a_wl_l<218> a_wl_l<217> a_wl_l<216> a_wl_l<215> a_wl_l<214> a_wl_l<213> a_wl_l<212> a_wl_l<211> a_wl_l<210> a_wl_l<209> a_wl_l<208> a_wl_l<207> a_wl_l<206> a_wl_l<205> a_wl_l<204> a_wl_l<203> a_wl_l<202> a_wl_l<201> a_wl_l<200> a_wl_l<199> a_wl_l<198> a_wl_l<197> a_wl_l<196> a_wl_l<195> a_wl_l<194> a_wl_l<193> a_wl_l<192> a_wl_l<191> a_wl_l<190> a_wl_l<189> a_wl_l<188> a_wl_l<187> a_wl_l<186> a_wl_l<185> a_wl_l<184> a_wl_l<183> a_wl_l<182> a_wl_l<181> a_wl_l<180> a_wl_l<179> a_wl_l<178> a_wl_l<177> a_wl_l<176> a_wl_l<175> a_wl_l<174> a_wl_l<173> a_wl_l<172> a_wl_l<171> a_wl_l<170> a_wl_l<169> a_wl_l<168> a_wl_l<167> a_wl_l<166> a_wl_l<165> a_wl_l<164> a_wl_l<163> a_wl_l<162> a_wl_l<161> a_wl_l<160> a_wl_l<159> a_wl_l<158> a_wl_l<157> a_wl_l<156> a_wl_l<155> a_wl_l<154> a_wl_l<153> a_wl_l<152> a_wl_l<151> a_wl_l<150> a_wl_l<149> a_wl_l<148> a_wl_l<147> a_wl_l<146> a_wl_l<145> a_wl_l<144> a_wl_l<143> a_wl_l<142> a_wl_l<141> a_wl_l<140> a_wl_l<139> a_wl_l<138> a_wl_l<137> a_wl_l<136> a_wl_l<135> a_wl_l<134> a_wl_l<133> a_wl_l<132> a_wl_l<131> a_wl_l<130> a_wl_l<129> a_wl_l<128> a_wl_l<127> a_wl_l<126> a_wl_l<125> a_wl_l<124> a_wl_l<123> a_wl_l<122> a_wl_l<121> a_wl_l<120> a_wl_l<119> a_wl_l<118> a_wl_l<117> a_wl_l<116> a_wl_l<115> a_wl_l<114> a_wl_l<113> a_wl_l<112> a_wl_l<111> a_wl_l<110> a_wl_l<109> a_wl_l<108> a_wl_l<107> a_wl_l<106> a_wl_l<105> a_wl_l<104> a_wl_l<103> a_wl_l<102> a_wl_l<101> a_wl_l<100> a_wl_l<99> a_wl_l<98> a_wl_l<97> a_wl_l<96> a_wl_l<95> a_wl_l<94> a_wl_l<93> a_wl_l<92> a_wl_l<91> a_wl_l<90> a_wl_l<89> a_wl_l<88> a_wl_l<87> a_wl_l<86> a_wl_l<85> a_wl_l<84> a_wl_l<83> a_wl_l<82> a_wl_l<81> a_wl_l<80> a_wl_l<79> a_wl_l<78> a_wl_l<77> a_wl_l<76> a_wl_l<75> a_wl_l<74> a_wl_l<73> a_wl_l<72> a_wl_l<71> a_wl_l<70> a_wl_l<69> a_wl_l<68> a_wl_l<67> a_wl_l<66> a_wl_l<65> a_wl_l<64> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0> VDDARRAY! VSS! / RM_IHPSG13_4096x8_c3_1P_MATRIX_pcell_1
+
+
+XA_COLDRV<1> a_addr_col<1> a_addr_col<0> a_addr_col_r<1> a_addr_col_r<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> a_dclk a_dclk_p_r<0> a_rclk a_rclk_p_r<0> a_wclk a_wclk_p_r<0> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_COLDRV13X4
+XA_COLDRV<0> a_addr_col<1> a_addr_col<0> a_addr_col_l<1> a_addr_col_l<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> a_dclk a_dclk_p_l<0> a_rclk a_rclk_p_l<0> a_wclk a_wclk_p_l<0> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_COLDRV13X4
+
+
+XA_WLDRV<63> a_wi<511> a_wi<510> a_wi<509> a_wi<508> a_wi<507> a_wi<506> a_wi<505> a_wi<504> a_wi<503> a_wi<502> a_wi<501> a_wi<500> a_wi<499> a_wi<498> a_wi<497> a_wi<496> a_wl_r<511> a_wl_r<510> a_wl_r<509> a_wl_r<508> a_wl_r<507> a_wl_r<506> a_wl_r<505> a_wl_r<504> a_wl_r<503> a_wl_r<502> a_wl_r<501> a_wl_r<500> a_wl_r<499> a_wl_r<498> a_wl_r<497> a_wl_r<496>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<62> a_wi<495> a_wi<494> a_wi<493> a_wi<492> a_wi<491> a_wi<490> a_wi<489> a_wi<488> a_wi<487> a_wi<486> a_wi<485> a_wi<484> a_wi<483> a_wi<482> a_wi<481> a_wi<480> a_wl_r<495> a_wl_r<494> a_wl_r<493> a_wl_r<492> a_wl_r<491> a_wl_r<490> a_wl_r<489> a_wl_r<488> a_wl_r<487> a_wl_r<486> a_wl_r<485> a_wl_r<484> a_wl_r<483> a_wl_r<482> a_wl_r<481> a_wl_r<480>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<61> a_wi<479> a_wi<478> a_wi<477> a_wi<476> a_wi<475> a_wi<474> a_wi<473> a_wi<472> a_wi<471> a_wi<470> a_wi<469> a_wi<468> a_wi<467> a_wi<466> a_wi<465> a_wi<464> a_wl_r<479> a_wl_r<478> a_wl_r<477> a_wl_r<476> a_wl_r<475> a_wl_r<474> a_wl_r<473> a_wl_r<472> a_wl_r<471> a_wl_r<470> a_wl_r<469> a_wl_r<468> a_wl_r<467> a_wl_r<466> a_wl_r<465> a_wl_r<464>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<60> a_wi<463> a_wi<462> a_wi<461> a_wi<460> a_wi<459> a_wi<458> a_wi<457> a_wi<456> a_wi<455> a_wi<454> a_wi<453> a_wi<452> a_wi<451> a_wi<450> a_wi<449> a_wi<448> a_wl_r<463> a_wl_r<462> a_wl_r<461> a_wl_r<460> a_wl_r<459> a_wl_r<458> a_wl_r<457> a_wl_r<456> a_wl_r<455> a_wl_r<454> a_wl_r<453> a_wl_r<452> a_wl_r<451> a_wl_r<450> a_wl_r<449> a_wl_r<448>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<59> a_wi<447> a_wi<446> a_wi<445> a_wi<444> a_wi<443> a_wi<442> a_wi<441> a_wi<440> a_wi<439> a_wi<438> a_wi<437> a_wi<436> a_wi<435> a_wi<434> a_wi<433> a_wi<432> a_wl_r<447> a_wl_r<446> a_wl_r<445> a_wl_r<444> a_wl_r<443> a_wl_r<442> a_wl_r<441> a_wl_r<440> a_wl_r<439> a_wl_r<438> a_wl_r<437> a_wl_r<436> a_wl_r<435> a_wl_r<434> a_wl_r<433> a_wl_r<432>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<58> a_wi<431> a_wi<430> a_wi<429> a_wi<428> a_wi<427> a_wi<426> a_wi<425> a_wi<424> a_wi<423> a_wi<422> a_wi<421> a_wi<420> a_wi<419> a_wi<418> a_wi<417> a_wi<416> a_wl_r<431> a_wl_r<430> a_wl_r<429> a_wl_r<428> a_wl_r<427> a_wl_r<426> a_wl_r<425> a_wl_r<424> a_wl_r<423> a_wl_r<422> a_wl_r<421> a_wl_r<420> a_wl_r<419> a_wl_r<418> a_wl_r<417> a_wl_r<416>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<57> a_wi<415> a_wi<414> a_wi<413> a_wi<412> a_wi<411> a_wi<410> a_wi<409> a_wi<408> a_wi<407> a_wi<406> a_wi<405> a_wi<404> a_wi<403> a_wi<402> a_wi<401> a_wi<400> a_wl_r<415> a_wl_r<414> a_wl_r<413> a_wl_r<412> a_wl_r<411> a_wl_r<410> a_wl_r<409> a_wl_r<408> a_wl_r<407> a_wl_r<406> a_wl_r<405> a_wl_r<404> a_wl_r<403> a_wl_r<402> a_wl_r<401> a_wl_r<400>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<56> a_wi<399> a_wi<398> a_wi<397> a_wi<396> a_wi<395> a_wi<394> a_wi<393> a_wi<392> a_wi<391> a_wi<390> a_wi<389> a_wi<388> a_wi<387> a_wi<386> a_wi<385> a_wi<384> a_wl_r<399> a_wl_r<398> a_wl_r<397> a_wl_r<396> a_wl_r<395> a_wl_r<394> a_wl_r<393> a_wl_r<392> a_wl_r<391> a_wl_r<390> a_wl_r<389> a_wl_r<388> a_wl_r<387> a_wl_r<386> a_wl_r<385> a_wl_r<384>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<55> a_wi<383> a_wi<382> a_wi<381> a_wi<380> a_wi<379> a_wi<378> a_wi<377> a_wi<376> a_wi<375> a_wi<374> a_wi<373> a_wi<372> a_wi<371> a_wi<370> a_wi<369> a_wi<368> a_wl_r<383> a_wl_r<382> a_wl_r<381> a_wl_r<380> a_wl_r<379> a_wl_r<378> a_wl_r<377> a_wl_r<376> a_wl_r<375> a_wl_r<374> a_wl_r<373> a_wl_r<372> a_wl_r<371> a_wl_r<370> a_wl_r<369> a_wl_r<368>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<54> a_wi<367> a_wi<366> a_wi<365> a_wi<364> a_wi<363> a_wi<362> a_wi<361> a_wi<360> a_wi<359> a_wi<358> a_wi<357> a_wi<356> a_wi<355> a_wi<354> a_wi<353> a_wi<352> a_wl_r<367> a_wl_r<366> a_wl_r<365> a_wl_r<364> a_wl_r<363> a_wl_r<362> a_wl_r<361> a_wl_r<360> a_wl_r<359> a_wl_r<358> a_wl_r<357> a_wl_r<356> a_wl_r<355> a_wl_r<354> a_wl_r<353> a_wl_r<352>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<53> a_wi<351> a_wi<350> a_wi<349> a_wi<348> a_wi<347> a_wi<346> a_wi<345> a_wi<344> a_wi<343> a_wi<342> a_wi<341> a_wi<340> a_wi<339> a_wi<338> a_wi<337> a_wi<336> a_wl_r<351> a_wl_r<350> a_wl_r<349> a_wl_r<348> a_wl_r<347> a_wl_r<346> a_wl_r<345> a_wl_r<344> a_wl_r<343> a_wl_r<342> a_wl_r<341> a_wl_r<340> a_wl_r<339> a_wl_r<338> a_wl_r<337> a_wl_r<336>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<52> a_wi<335> a_wi<334> a_wi<333> a_wi<332> a_wi<331> a_wi<330> a_wi<329> a_wi<328> a_wi<327> a_wi<326> a_wi<325> a_wi<324> a_wi<323> a_wi<322> a_wi<321> a_wi<320> a_wl_r<335> a_wl_r<334> a_wl_r<333> a_wl_r<332> a_wl_r<331> a_wl_r<330> a_wl_r<329> a_wl_r<328> a_wl_r<327> a_wl_r<326> a_wl_r<325> a_wl_r<324> a_wl_r<323> a_wl_r<322> a_wl_r<321> a_wl_r<320>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<51> a_wi<319> a_wi<318> a_wi<317> a_wi<316> a_wi<315> a_wi<314> a_wi<313> a_wi<312> a_wi<311> a_wi<310> a_wi<309> a_wi<308> a_wi<307> a_wi<306> a_wi<305> a_wi<304> a_wl_r<319> a_wl_r<318> a_wl_r<317> a_wl_r<316> a_wl_r<315> a_wl_r<314> a_wl_r<313> a_wl_r<312> a_wl_r<311> a_wl_r<310> a_wl_r<309> a_wl_r<308> a_wl_r<307> a_wl_r<306> a_wl_r<305> a_wl_r<304>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<50> a_wi<303> a_wi<302> a_wi<301> a_wi<300> a_wi<299> a_wi<298> a_wi<297> a_wi<296> a_wi<295> a_wi<294> a_wi<293> a_wi<292> a_wi<291> a_wi<290> a_wi<289> a_wi<288> a_wl_r<303> a_wl_r<302> a_wl_r<301> a_wl_r<300> a_wl_r<299> a_wl_r<298> a_wl_r<297> a_wl_r<296> a_wl_r<295> a_wl_r<294> a_wl_r<293> a_wl_r<292> a_wl_r<291> a_wl_r<290> a_wl_r<289> a_wl_r<288>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<49> a_wi<287> a_wi<286> a_wi<285> a_wi<284> a_wi<283> a_wi<282> a_wi<281> a_wi<280> a_wi<279> a_wi<278> a_wi<277> a_wi<276> a_wi<275> a_wi<274> a_wi<273> a_wi<272> a_wl_r<287> a_wl_r<286> a_wl_r<285> a_wl_r<284> a_wl_r<283> a_wl_r<282> a_wl_r<281> a_wl_r<280> a_wl_r<279> a_wl_r<278> a_wl_r<277> a_wl_r<276> a_wl_r<275> a_wl_r<274> a_wl_r<273> a_wl_r<272>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<48> a_wi<271> a_wi<270> a_wi<269> a_wi<268> a_wi<267> a_wi<266> a_wi<265> a_wi<264> a_wi<263> a_wi<262> a_wi<261> a_wi<260> a_wi<259> a_wi<258> a_wi<257> a_wi<256> a_wl_r<271> a_wl_r<270> a_wl_r<269> a_wl_r<268> a_wl_r<267> a_wl_r<266> a_wl_r<265> a_wl_r<264> a_wl_r<263> a_wl_r<262> a_wl_r<261> a_wl_r<260> a_wl_r<259> a_wl_r<258> a_wl_r<257> a_wl_r<256>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<47> a_wi<255> a_wi<254> a_wi<253> a_wi<252> a_wi<251> a_wi<250> a_wi<249> a_wi<248> a_wi<247> a_wi<246> a_wi<245> a_wi<244> a_wi<243> a_wi<242> a_wi<241> a_wi<240> a_wl_r<255> a_wl_r<254> a_wl_r<253> a_wl_r<252> a_wl_r<251> a_wl_r<250> a_wl_r<249> a_wl_r<248> a_wl_r<247> a_wl_r<246> a_wl_r<245> a_wl_r<244> a_wl_r<243> a_wl_r<242> a_wl_r<241> a_wl_r<240>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<46> a_wi<239> a_wi<238> a_wi<237> a_wi<236> a_wi<235> a_wi<234> a_wi<233> a_wi<232> a_wi<231> a_wi<230> a_wi<229> a_wi<228> a_wi<227> a_wi<226> a_wi<225> a_wi<224> a_wl_r<239> a_wl_r<238> a_wl_r<237> a_wl_r<236> a_wl_r<235> a_wl_r<234> a_wl_r<233> a_wl_r<232> a_wl_r<231> a_wl_r<230> a_wl_r<229> a_wl_r<228> a_wl_r<227> a_wl_r<226> a_wl_r<225> a_wl_r<224>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<45> a_wi<223> a_wi<222> a_wi<221> a_wi<220> a_wi<219> a_wi<218> a_wi<217> a_wi<216> a_wi<215> a_wi<214> a_wi<213> a_wi<212> a_wi<211> a_wi<210> a_wi<209> a_wi<208> a_wl_r<223> a_wl_r<222> a_wl_r<221> a_wl_r<220> a_wl_r<219> a_wl_r<218> a_wl_r<217> a_wl_r<216> a_wl_r<215> a_wl_r<214> a_wl_r<213> a_wl_r<212> a_wl_r<211> a_wl_r<210> a_wl_r<209> a_wl_r<208>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<44> a_wi<207> a_wi<206> a_wi<205> a_wi<204> a_wi<203> a_wi<202> a_wi<201> a_wi<200> a_wi<199> a_wi<198> a_wi<197> a_wi<196> a_wi<195> a_wi<194> a_wi<193> a_wi<192> a_wl_r<207> a_wl_r<206> a_wl_r<205> a_wl_r<204> a_wl_r<203> a_wl_r<202> a_wl_r<201> a_wl_r<200> a_wl_r<199> a_wl_r<198> a_wl_r<197> a_wl_r<196> a_wl_r<195> a_wl_r<194> a_wl_r<193> a_wl_r<192>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<43> a_wi<191> a_wi<190> a_wi<189> a_wi<188> a_wi<187> a_wi<186> a_wi<185> a_wi<184> a_wi<183> a_wi<182> a_wi<181> a_wi<180> a_wi<179> a_wi<178> a_wi<177> a_wi<176> a_wl_r<191> a_wl_r<190> a_wl_r<189> a_wl_r<188> a_wl_r<187> a_wl_r<186> a_wl_r<185> a_wl_r<184> a_wl_r<183> a_wl_r<182> a_wl_r<181> a_wl_r<180> a_wl_r<179> a_wl_r<178> a_wl_r<177> a_wl_r<176>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<42> a_wi<175> a_wi<174> a_wi<173> a_wi<172> a_wi<171> a_wi<170> a_wi<169> a_wi<168> a_wi<167> a_wi<166> a_wi<165> a_wi<164> a_wi<163> a_wi<162> a_wi<161> a_wi<160> a_wl_r<175> a_wl_r<174> a_wl_r<173> a_wl_r<172> a_wl_r<171> a_wl_r<170> a_wl_r<169> a_wl_r<168> a_wl_r<167> a_wl_r<166> a_wl_r<165> a_wl_r<164> a_wl_r<163> a_wl_r<162> a_wl_r<161> a_wl_r<160>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<41> a_wi<159> a_wi<158> a_wi<157> a_wi<156> a_wi<155> a_wi<154> a_wi<153> a_wi<152> a_wi<151> a_wi<150> a_wi<149> a_wi<148> a_wi<147> a_wi<146> a_wi<145> a_wi<144> a_wl_r<159> a_wl_r<158> a_wl_r<157> a_wl_r<156> a_wl_r<155> a_wl_r<154> a_wl_r<153> a_wl_r<152> a_wl_r<151> a_wl_r<150> a_wl_r<149> a_wl_r<148> a_wl_r<147> a_wl_r<146> a_wl_r<145> a_wl_r<144>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<40> a_wi<143> a_wi<142> a_wi<141> a_wi<140> a_wi<139> a_wi<138> a_wi<137> a_wi<136> a_wi<135> a_wi<134> a_wi<133> a_wi<132> a_wi<131> a_wi<130> a_wi<129> a_wi<128> a_wl_r<143> a_wl_r<142> a_wl_r<141> a_wl_r<140> a_wl_r<139> a_wl_r<138> a_wl_r<137> a_wl_r<136> a_wl_r<135> a_wl_r<134> a_wl_r<133> a_wl_r<132> a_wl_r<131> a_wl_r<130> a_wl_r<129> a_wl_r<128>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<39> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wl_r<127> a_wl_r<126> a_wl_r<125> a_wl_r<124> a_wl_r<123> a_wl_r<122> a_wl_r<121> a_wl_r<120> a_wl_r<119> a_wl_r<118> a_wl_r<117> a_wl_r<116> a_wl_r<115> a_wl_r<114> a_wl_r<113> a_wl_r<112>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<38> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wl_r<111> a_wl_r<110> a_wl_r<109> a_wl_r<108> a_wl_r<107> a_wl_r<106> a_wl_r<105> a_wl_r<104> a_wl_r<103> a_wl_r<102> a_wl_r<101> a_wl_r<100> a_wl_r<99> a_wl_r<98> a_wl_r<97> a_wl_r<96>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<37> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wl_r<95> a_wl_r<94> a_wl_r<93> a_wl_r<92> a_wl_r<91> a_wl_r<90> a_wl_r<89> a_wl_r<88> a_wl_r<87> a_wl_r<86> a_wl_r<85> a_wl_r<84> a_wl_r<83> a_wl_r<82> a_wl_r<81> a_wl_r<80>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<36> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wl_r<79> a_wl_r<78> a_wl_r<77> a_wl_r<76> a_wl_r<75> a_wl_r<74> a_wl_r<73> a_wl_r<72> a_wl_r<71> a_wl_r<70> a_wl_r<69> a_wl_r<68> a_wl_r<67> a_wl_r<66> a_wl_r<65> a_wl_r<64>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<35> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_r<63> a_wl_r<62> a_wl_r<61> a_wl_r<60> a_wl_r<59> a_wl_r<58> a_wl_r<57> a_wl_r<56> a_wl_r<55> a_wl_r<54> a_wl_r<53> a_wl_r<52> a_wl_r<51> a_wl_r<50> a_wl_r<49> a_wl_r<48>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<34> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_r<47> a_wl_r<46> a_wl_r<45> a_wl_r<44> a_wl_r<43> a_wl_r<42> a_wl_r<41> a_wl_r<40> a_wl_r<39> a_wl_r<38> a_wl_r<37> a_wl_r<36> a_wl_r<35> a_wl_r<34> a_wl_r<33> a_wl_r<32>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<33> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_r<31> a_wl_r<30> a_wl_r<29> a_wl_r<28> a_wl_r<27> a_wl_r<26> a_wl_r<25> a_wl_r<24> a_wl_r<23> a_wl_r<22> a_wl_r<21> a_wl_r<20> a_wl_r<19> a_wl_r<18> a_wl_r<17> a_wl_r<16>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<32> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_r<15> a_wl_r<14> a_wl_r<13> a_wl_r<12> a_wl_r<11> a_wl_r<10> a_wl_r<9> a_wl_r<8> a_wl_r<7> a_wl_r<6> a_wl_r<5> a_wl_r<4> a_wl_r<3> a_wl_r<2> a_wl_r<1> a_wl_r<0>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<31> a_wi<511> a_wi<510> a_wi<509> a_wi<508> a_wi<507> a_wi<506> a_wi<505> a_wi<504> a_wi<503> a_wi<502> a_wi<501> a_wi<500> a_wi<499> a_wi<498> a_wi<497> a_wi<496> a_wl_l<511> a_wl_l<510> a_wl_l<509> a_wl_l<508> a_wl_l<507> a_wl_l<506> a_wl_l<505> a_wl_l<504> a_wl_l<503> a_wl_l<502> a_wl_l<501> a_wl_l<500> a_wl_l<499> a_wl_l<498> a_wl_l<497> a_wl_l<496>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<30> a_wi<495> a_wi<494> a_wi<493> a_wi<492> a_wi<491> a_wi<490> a_wi<489> a_wi<488> a_wi<487> a_wi<486> a_wi<485> a_wi<484> a_wi<483> a_wi<482> a_wi<481> a_wi<480> a_wl_l<495> a_wl_l<494> a_wl_l<493> a_wl_l<492> a_wl_l<491> a_wl_l<490> a_wl_l<489> a_wl_l<488> a_wl_l<487> a_wl_l<486> a_wl_l<485> a_wl_l<484> a_wl_l<483> a_wl_l<482> a_wl_l<481> a_wl_l<480>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<29> a_wi<479> a_wi<478> a_wi<477> a_wi<476> a_wi<475> a_wi<474> a_wi<473> a_wi<472> a_wi<471> a_wi<470> a_wi<469> a_wi<468> a_wi<467> a_wi<466> a_wi<465> a_wi<464> a_wl_l<479> a_wl_l<478> a_wl_l<477> a_wl_l<476> a_wl_l<475> a_wl_l<474> a_wl_l<473> a_wl_l<472> a_wl_l<471> a_wl_l<470> a_wl_l<469> a_wl_l<468> a_wl_l<467> a_wl_l<466> a_wl_l<465> a_wl_l<464>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<28> a_wi<463> a_wi<462> a_wi<461> a_wi<460> a_wi<459> a_wi<458> a_wi<457> a_wi<456> a_wi<455> a_wi<454> a_wi<453> a_wi<452> a_wi<451> a_wi<450> a_wi<449> a_wi<448> a_wl_l<463> a_wl_l<462> a_wl_l<461> a_wl_l<460> a_wl_l<459> a_wl_l<458> a_wl_l<457> a_wl_l<456> a_wl_l<455> a_wl_l<454> a_wl_l<453> a_wl_l<452> a_wl_l<451> a_wl_l<450> a_wl_l<449> a_wl_l<448>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<27> a_wi<447> a_wi<446> a_wi<445> a_wi<444> a_wi<443> a_wi<442> a_wi<441> a_wi<440> a_wi<439> a_wi<438> a_wi<437> a_wi<436> a_wi<435> a_wi<434> a_wi<433> a_wi<432> a_wl_l<447> a_wl_l<446> a_wl_l<445> a_wl_l<444> a_wl_l<443> a_wl_l<442> a_wl_l<441> a_wl_l<440> a_wl_l<439> a_wl_l<438> a_wl_l<437> a_wl_l<436> a_wl_l<435> a_wl_l<434> a_wl_l<433> a_wl_l<432>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<26> a_wi<431> a_wi<430> a_wi<429> a_wi<428> a_wi<427> a_wi<426> a_wi<425> a_wi<424> a_wi<423> a_wi<422> a_wi<421> a_wi<420> a_wi<419> a_wi<418> a_wi<417> a_wi<416> a_wl_l<431> a_wl_l<430> a_wl_l<429> a_wl_l<428> a_wl_l<427> a_wl_l<426> a_wl_l<425> a_wl_l<424> a_wl_l<423> a_wl_l<422> a_wl_l<421> a_wl_l<420> a_wl_l<419> a_wl_l<418> a_wl_l<417> a_wl_l<416>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<25> a_wi<415> a_wi<414> a_wi<413> a_wi<412> a_wi<411> a_wi<410> a_wi<409> a_wi<408> a_wi<407> a_wi<406> a_wi<405> a_wi<404> a_wi<403> a_wi<402> a_wi<401> a_wi<400> a_wl_l<415> a_wl_l<414> a_wl_l<413> a_wl_l<412> a_wl_l<411> a_wl_l<410> a_wl_l<409> a_wl_l<408> a_wl_l<407> a_wl_l<406> a_wl_l<405> a_wl_l<404> a_wl_l<403> a_wl_l<402> a_wl_l<401> a_wl_l<400>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<24> a_wi<399> a_wi<398> a_wi<397> a_wi<396> a_wi<395> a_wi<394> a_wi<393> a_wi<392> a_wi<391> a_wi<390> a_wi<389> a_wi<388> a_wi<387> a_wi<386> a_wi<385> a_wi<384> a_wl_l<399> a_wl_l<398> a_wl_l<397> a_wl_l<396> a_wl_l<395> a_wl_l<394> a_wl_l<393> a_wl_l<392> a_wl_l<391> a_wl_l<390> a_wl_l<389> a_wl_l<388> a_wl_l<387> a_wl_l<386> a_wl_l<385> a_wl_l<384>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<23> a_wi<383> a_wi<382> a_wi<381> a_wi<380> a_wi<379> a_wi<378> a_wi<377> a_wi<376> a_wi<375> a_wi<374> a_wi<373> a_wi<372> a_wi<371> a_wi<370> a_wi<369> a_wi<368> a_wl_l<383> a_wl_l<382> a_wl_l<381> a_wl_l<380> a_wl_l<379> a_wl_l<378> a_wl_l<377> a_wl_l<376> a_wl_l<375> a_wl_l<374> a_wl_l<373> a_wl_l<372> a_wl_l<371> a_wl_l<370> a_wl_l<369> a_wl_l<368>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<22> a_wi<367> a_wi<366> a_wi<365> a_wi<364> a_wi<363> a_wi<362> a_wi<361> a_wi<360> a_wi<359> a_wi<358> a_wi<357> a_wi<356> a_wi<355> a_wi<354> a_wi<353> a_wi<352> a_wl_l<367> a_wl_l<366> a_wl_l<365> a_wl_l<364> a_wl_l<363> a_wl_l<362> a_wl_l<361> a_wl_l<360> a_wl_l<359> a_wl_l<358> a_wl_l<357> a_wl_l<356> a_wl_l<355> a_wl_l<354> a_wl_l<353> a_wl_l<352>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<21> a_wi<351> a_wi<350> a_wi<349> a_wi<348> a_wi<347> a_wi<346> a_wi<345> a_wi<344> a_wi<343> a_wi<342> a_wi<341> a_wi<340> a_wi<339> a_wi<338> a_wi<337> a_wi<336> a_wl_l<351> a_wl_l<350> a_wl_l<349> a_wl_l<348> a_wl_l<347> a_wl_l<346> a_wl_l<345> a_wl_l<344> a_wl_l<343> a_wl_l<342> a_wl_l<341> a_wl_l<340> a_wl_l<339> a_wl_l<338> a_wl_l<337> a_wl_l<336>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<20> a_wi<335> a_wi<334> a_wi<333> a_wi<332> a_wi<331> a_wi<330> a_wi<329> a_wi<328> a_wi<327> a_wi<326> a_wi<325> a_wi<324> a_wi<323> a_wi<322> a_wi<321> a_wi<320> a_wl_l<335> a_wl_l<334> a_wl_l<333> a_wl_l<332> a_wl_l<331> a_wl_l<330> a_wl_l<329> a_wl_l<328> a_wl_l<327> a_wl_l<326> a_wl_l<325> a_wl_l<324> a_wl_l<323> a_wl_l<322> a_wl_l<321> a_wl_l<320>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<19> a_wi<319> a_wi<318> a_wi<317> a_wi<316> a_wi<315> a_wi<314> a_wi<313> a_wi<312> a_wi<311> a_wi<310> a_wi<309> a_wi<308> a_wi<307> a_wi<306> a_wi<305> a_wi<304> a_wl_l<319> a_wl_l<318> a_wl_l<317> a_wl_l<316> a_wl_l<315> a_wl_l<314> a_wl_l<313> a_wl_l<312> a_wl_l<311> a_wl_l<310> a_wl_l<309> a_wl_l<308> a_wl_l<307> a_wl_l<306> a_wl_l<305> a_wl_l<304>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<18> a_wi<303> a_wi<302> a_wi<301> a_wi<300> a_wi<299> a_wi<298> a_wi<297> a_wi<296> a_wi<295> a_wi<294> a_wi<293> a_wi<292> a_wi<291> a_wi<290> a_wi<289> a_wi<288> a_wl_l<303> a_wl_l<302> a_wl_l<301> a_wl_l<300> a_wl_l<299> a_wl_l<298> a_wl_l<297> a_wl_l<296> a_wl_l<295> a_wl_l<294> a_wl_l<293> a_wl_l<292> a_wl_l<291> a_wl_l<290> a_wl_l<289> a_wl_l<288>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<17> a_wi<287> a_wi<286> a_wi<285> a_wi<284> a_wi<283> a_wi<282> a_wi<281> a_wi<280> a_wi<279> a_wi<278> a_wi<277> a_wi<276> a_wi<275> a_wi<274> a_wi<273> a_wi<272> a_wl_l<287> a_wl_l<286> a_wl_l<285> a_wl_l<284> a_wl_l<283> a_wl_l<282> a_wl_l<281> a_wl_l<280> a_wl_l<279> a_wl_l<278> a_wl_l<277> a_wl_l<276> a_wl_l<275> a_wl_l<274> a_wl_l<273> a_wl_l<272>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<16> a_wi<271> a_wi<270> a_wi<269> a_wi<268> a_wi<267> a_wi<266> a_wi<265> a_wi<264> a_wi<263> a_wi<262> a_wi<261> a_wi<260> a_wi<259> a_wi<258> a_wi<257> a_wi<256> a_wl_l<271> a_wl_l<270> a_wl_l<269> a_wl_l<268> a_wl_l<267> a_wl_l<266> a_wl_l<265> a_wl_l<264> a_wl_l<263> a_wl_l<262> a_wl_l<261> a_wl_l<260> a_wl_l<259> a_wl_l<258> a_wl_l<257> a_wl_l<256>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<15> a_wi<255> a_wi<254> a_wi<253> a_wi<252> a_wi<251> a_wi<250> a_wi<249> a_wi<248> a_wi<247> a_wi<246> a_wi<245> a_wi<244> a_wi<243> a_wi<242> a_wi<241> a_wi<240> a_wl_l<255> a_wl_l<254> a_wl_l<253> a_wl_l<252> a_wl_l<251> a_wl_l<250> a_wl_l<249> a_wl_l<248> a_wl_l<247> a_wl_l<246> a_wl_l<245> a_wl_l<244> a_wl_l<243> a_wl_l<242> a_wl_l<241> a_wl_l<240>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<14> a_wi<239> a_wi<238> a_wi<237> a_wi<236> a_wi<235> a_wi<234> a_wi<233> a_wi<232> a_wi<231> a_wi<230> a_wi<229> a_wi<228> a_wi<227> a_wi<226> a_wi<225> a_wi<224> a_wl_l<239> a_wl_l<238> a_wl_l<237> a_wl_l<236> a_wl_l<235> a_wl_l<234> a_wl_l<233> a_wl_l<232> a_wl_l<231> a_wl_l<230> a_wl_l<229> a_wl_l<228> a_wl_l<227> a_wl_l<226> a_wl_l<225> a_wl_l<224>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<13> a_wi<223> a_wi<222> a_wi<221> a_wi<220> a_wi<219> a_wi<218> a_wi<217> a_wi<216> a_wi<215> a_wi<214> a_wi<213> a_wi<212> a_wi<211> a_wi<210> a_wi<209> a_wi<208> a_wl_l<223> a_wl_l<222> a_wl_l<221> a_wl_l<220> a_wl_l<219> a_wl_l<218> a_wl_l<217> a_wl_l<216> a_wl_l<215> a_wl_l<214> a_wl_l<213> a_wl_l<212> a_wl_l<211> a_wl_l<210> a_wl_l<209> a_wl_l<208>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<12> a_wi<207> a_wi<206> a_wi<205> a_wi<204> a_wi<203> a_wi<202> a_wi<201> a_wi<200> a_wi<199> a_wi<198> a_wi<197> a_wi<196> a_wi<195> a_wi<194> a_wi<193> a_wi<192> a_wl_l<207> a_wl_l<206> a_wl_l<205> a_wl_l<204> a_wl_l<203> a_wl_l<202> a_wl_l<201> a_wl_l<200> a_wl_l<199> a_wl_l<198> a_wl_l<197> a_wl_l<196> a_wl_l<195> a_wl_l<194> a_wl_l<193> a_wl_l<192>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<11> a_wi<191> a_wi<190> a_wi<189> a_wi<188> a_wi<187> a_wi<186> a_wi<185> a_wi<184> a_wi<183> a_wi<182> a_wi<181> a_wi<180> a_wi<179> a_wi<178> a_wi<177> a_wi<176> a_wl_l<191> a_wl_l<190> a_wl_l<189> a_wl_l<188> a_wl_l<187> a_wl_l<186> a_wl_l<185> a_wl_l<184> a_wl_l<183> a_wl_l<182> a_wl_l<181> a_wl_l<180> a_wl_l<179> a_wl_l<178> a_wl_l<177> a_wl_l<176>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<10> a_wi<175> a_wi<174> a_wi<173> a_wi<172> a_wi<171> a_wi<170> a_wi<169> a_wi<168> a_wi<167> a_wi<166> a_wi<165> a_wi<164> a_wi<163> a_wi<162> a_wi<161> a_wi<160> a_wl_l<175> a_wl_l<174> a_wl_l<173> a_wl_l<172> a_wl_l<171> a_wl_l<170> a_wl_l<169> a_wl_l<168> a_wl_l<167> a_wl_l<166> a_wl_l<165> a_wl_l<164> a_wl_l<163> a_wl_l<162> a_wl_l<161> a_wl_l<160>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<9> a_wi<159> a_wi<158> a_wi<157> a_wi<156> a_wi<155> a_wi<154> a_wi<153> a_wi<152> a_wi<151> a_wi<150> a_wi<149> a_wi<148> a_wi<147> a_wi<146> a_wi<145> a_wi<144> a_wl_l<159> a_wl_l<158> a_wl_l<157> a_wl_l<156> a_wl_l<155> a_wl_l<154> a_wl_l<153> a_wl_l<152> a_wl_l<151> a_wl_l<150> a_wl_l<149> a_wl_l<148> a_wl_l<147> a_wl_l<146> a_wl_l<145> a_wl_l<144>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<8> a_wi<143> a_wi<142> a_wi<141> a_wi<140> a_wi<139> a_wi<138> a_wi<137> a_wi<136> a_wi<135> a_wi<134> a_wi<133> a_wi<132> a_wi<131> a_wi<130> a_wi<129> a_wi<128> a_wl_l<143> a_wl_l<142> a_wl_l<141> a_wl_l<140> a_wl_l<139> a_wl_l<138> a_wl_l<137> a_wl_l<136> a_wl_l<135> a_wl_l<134> a_wl_l<133> a_wl_l<132> a_wl_l<131> a_wl_l<130> a_wl_l<129> a_wl_l<128>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<7> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wl_l<127> a_wl_l<126> a_wl_l<125> a_wl_l<124> a_wl_l<123> a_wl_l<122> a_wl_l<121> a_wl_l<120> a_wl_l<119> a_wl_l<118> a_wl_l<117> a_wl_l<116> a_wl_l<115> a_wl_l<114> a_wl_l<113> a_wl_l<112>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<6> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wl_l<111> a_wl_l<110> a_wl_l<109> a_wl_l<108> a_wl_l<107> a_wl_l<106> a_wl_l<105> a_wl_l<104> a_wl_l<103> a_wl_l<102> a_wl_l<101> a_wl_l<100> a_wl_l<99> a_wl_l<98> a_wl_l<97> a_wl_l<96>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<5> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wl_l<95> a_wl_l<94> a_wl_l<93> a_wl_l<92> a_wl_l<91> a_wl_l<90> a_wl_l<89> a_wl_l<88> a_wl_l<87> a_wl_l<86> a_wl_l<85> a_wl_l<84> a_wl_l<83> a_wl_l<82> a_wl_l<81> a_wl_l<80>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<4> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wl_l<79> a_wl_l<78> a_wl_l<77> a_wl_l<76> a_wl_l<75> a_wl_l<74> a_wl_l<73> a_wl_l<72> a_wl_l<71> a_wl_l<70> a_wl_l<69> a_wl_l<68> a_wl_l<67> a_wl_l<66> a_wl_l<65> a_wl_l<64>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<3> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wl_l<63> a_wl_l<62> a_wl_l<61> a_wl_l<60> a_wl_l<59> a_wl_l<58> a_wl_l<57> a_wl_l<56> a_wl_l<55> a_wl_l<54> a_wl_l<53> a_wl_l<52> a_wl_l<51> a_wl_l<50> a_wl_l<49> a_wl_l<48>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<2> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wl_l<47> a_wl_l<46> a_wl_l<45> a_wl_l<44> a_wl_l<43> a_wl_l<42> a_wl_l<41> a_wl_l<40> a_wl_l<39> a_wl_l<38> a_wl_l<37> a_wl_l<36> a_wl_l<35> a_wl_l<34> a_wl_l<33> a_wl_l<32>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<1> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wl_l<31> a_wl_l<30> a_wl_l<29> a_wl_l<28> a_wl_l<27> a_wl_l<26> a_wl_l<25> a_wl_l<24> a_wl_l<23> a_wl_l<22> a_wl_l<21> a_wl_l<20> a_wl_l<19> a_wl_l<18> a_wl_l<17> a_wl_l<16>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+XA_WLDRV<0> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> a_wl_l<15> a_wl_l<14> a_wl_l<13> a_wl_l<12> a_wl_l<11> a_wl_l<10> a_wl_l<9> a_wl_l<8> a_wl_l<7> a_wl_l<6> a_wl_l<5> a_wl_l<4> a_wl_l<3> a_wl_l<2> a_wl_l<1> a_wl_l<0>  VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_WLDRV16X4
+
+
+XA_CTRL a_aclk_n A_BIST_CLK A_BIST_MEN A_BIST_EN A_BIST_REN A_BIST_WEN a_tiel A_CLK A_MEN a_dclk a_eclk a_pulse_h a_pulse_l a_pulse a_rclk A_REN a_cs a_wclk A_WEN VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_CTRL
+
+
+XA_ROWDEC a_addr_row<8> a_addr_row<7> a_addr_row<6> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> a_cs a_eclk a_wi<511> a_wi<510> a_wi<509> a_wi<508> a_wi<507> a_wi<506> a_wi<505> a_wi<504> a_wi<503> a_wi<502> a_wi<501> a_wi<500> a_wi<499> a_wi<498> a_wi<497> a_wi<496> a_wi<495> a_wi<494> a_wi<493> a_wi<492> a_wi<491> a_wi<490> a_wi<489> a_wi<488> a_wi<487> a_wi<486> a_wi<485> a_wi<484> a_wi<483> a_wi<482> a_wi<481> a_wi<480> a_wi<479> a_wi<478> a_wi<477> a_wi<476> a_wi<475> a_wi<474> a_wi<473> a_wi<472> a_wi<471> a_wi<470> a_wi<469> a_wi<468> a_wi<467> a_wi<466> a_wi<465> a_wi<464> a_wi<463> a_wi<462> a_wi<461> a_wi<460> a_wi<459> a_wi<458> a_wi<457> a_wi<456> a_wi<455> a_wi<454> a_wi<453> a_wi<452> a_wi<451> a_wi<450> a_wi<449> a_wi<448> a_wi<447> a_wi<446> a_wi<445> a_wi<444> a_wi<443> a_wi<442> a_wi<441> a_wi<440> a_wi<439> a_wi<438> a_wi<437> a_wi<436> a_wi<435> a_wi<434> a_wi<433> a_wi<432> a_wi<431> a_wi<430> a_wi<429> a_wi<428> a_wi<427> a_wi<426> a_wi<425> a_wi<424> a_wi<423> a_wi<422> a_wi<421> a_wi<420> a_wi<419> a_wi<418> a_wi<417> a_wi<416> a_wi<415> a_wi<414> a_wi<413> a_wi<412> a_wi<411> a_wi<410> a_wi<409> a_wi<408> a_wi<407> a_wi<406> a_wi<405> a_wi<404> a_wi<403> a_wi<402> a_wi<401> a_wi<400> a_wi<399> a_wi<398> a_wi<397> a_wi<396> a_wi<395> a_wi<394> a_wi<393> a_wi<392> a_wi<391> a_wi<390> a_wi<389> a_wi<388> a_wi<387> a_wi<386> a_wi<385> a_wi<384> a_wi<383> a_wi<382> a_wi<381> a_wi<380> a_wi<379> a_wi<378> a_wi<377> a_wi<376> a_wi<375> a_wi<374> a_wi<373> a_wi<372> a_wi<371> a_wi<370> a_wi<369> a_wi<368> a_wi<367> a_wi<366> a_wi<365> a_wi<364> a_wi<363> a_wi<362> a_wi<361> a_wi<360> a_wi<359> a_wi<358> a_wi<357> a_wi<356> a_wi<355> a_wi<354> a_wi<353> a_wi<352> a_wi<351> a_wi<350> a_wi<349> a_wi<348> a_wi<347> a_wi<346> a_wi<345> a_wi<344> a_wi<343> a_wi<342> a_wi<341> a_wi<340> a_wi<339> a_wi<338> a_wi<337> a_wi<336> a_wi<335> a_wi<334> a_wi<333> a_wi<332> a_wi<331> a_wi<330> a_wi<329> a_wi<328> a_wi<327> a_wi<326> a_wi<325> a_wi<324> a_wi<323> a_wi<322> a_wi<321> a_wi<320> a_wi<319> a_wi<318> a_wi<317> a_wi<316> a_wi<315> a_wi<314> a_wi<313> a_wi<312> a_wi<311> a_wi<310> a_wi<309> a_wi<308> a_wi<307> a_wi<306> a_wi<305> a_wi<304> a_wi<303> a_wi<302> a_wi<301> a_wi<300> a_wi<299> a_wi<298> a_wi<297> a_wi<296> a_wi<295> a_wi<294> a_wi<293> a_wi<292> a_wi<291> a_wi<290> a_wi<289> a_wi<288> a_wi<287> a_wi<286> a_wi<285> a_wi<284> a_wi<283> a_wi<282> a_wi<281> a_wi<280> a_wi<279> a_wi<278> a_wi<277> a_wi<276> a_wi<275> a_wi<274> a_wi<273> a_wi<272> a_wi<271> a_wi<270> a_wi<269> a_wi<268> a_wi<267> a_wi<266> a_wi<265> a_wi<264> a_wi<263> a_wi<262> a_wi<261> a_wi<260> a_wi<259> a_wi<258> a_wi<257> a_wi<256> a_wi<255> a_wi<254> a_wi<253> a_wi<252> a_wi<251> a_wi<250> a_wi<249> a_wi<248> a_wi<247> a_wi<246> a_wi<245> a_wi<244> a_wi<243> a_wi<242> a_wi<241> a_wi<240> a_wi<239> a_wi<238> a_wi<237> a_wi<236> a_wi<235> a_wi<234> a_wi<233> a_wi<232> a_wi<231> a_wi<230> a_wi<229> a_wi<228> a_wi<227> a_wi<226> a_wi<225> a_wi<224> a_wi<223> a_wi<222> a_wi<221> a_wi<220> a_wi<219> a_wi<218> a_wi<217> a_wi<216> a_wi<215> a_wi<214> a_wi<213> a_wi<212> a_wi<211> a_wi<210> a_wi<209> a_wi<208> a_wi<207> a_wi<206> a_wi<205> a_wi<204> a_wi<203> a_wi<202> a_wi<201> a_wi<200> a_wi<199> a_wi<198> a_wi<197> a_wi<196> a_wi<195> a_wi<194> a_wi<193> a_wi<192> a_wi<191> a_wi<190> a_wi<189> a_wi<188> a_wi<187> a_wi<186> a_wi<185> a_wi<184> a_wi<183> a_wi<182> a_wi<181> a_wi<180> a_wi<179> a_wi<178> a_wi<177> a_wi<176> a_wi<175> a_wi<174> a_wi<173> a_wi<172> a_wi<171> a_wi<170> a_wi<169> a_wi<168> a_wi<167> a_wi<166> a_wi<165> a_wi<164> a_wi<163> a_wi<162> a_wi<161> a_wi<160> a_wi<159> a_wi<158> a_wi<157> a_wi<156> a_wi<155> a_wi<154> a_wi<153> a_wi<152> a_wi<151> a_wi<150> a_wi<149> a_wi<148> a_wi<147> a_wi<146> a_wi<145> a_wi<144> a_wi<143> a_wi<142> a_wi<141> a_wi<140> a_wi<139> a_wi<138> a_wi<137> a_wi<136> a_wi<135> a_wi<134> a_wi<133> a_wi<132> a_wi<131> a_wi<130> a_wi<129> a_wi<128> a_wi<127> a_wi<126> a_wi<125> a_wi<124> a_wi<123> a_wi<122> a_wi<121> a_wi<120> a_wi<119> a_wi<118> a_wi<117> a_wi<116> a_wi<115> a_wi<114> a_wi<113> a_wi<112> a_wi<111> a_wi<110> a_wi<109> a_wi<108> a_wi<107> a_wi<106> a_wi<105> a_wi<104> a_wi<103> a_wi<102> a_wi<101> a_wi<100> a_wi<99> a_wi<98> a_wi<97> a_wi<96> a_wi<95> a_wi<94> a_wi<93> a_wi<92> a_wi<91> a_wi<90> a_wi<89> a_wi<88> a_wi<87> a_wi<86> a_wi<85> a_wi<84> a_wi<83> a_wi<82> a_wi<81> a_wi<80> a_wi<79> a_wi<78> a_wi<77> a_wi<76> a_wi<75> a_wi<74> a_wi<73> a_wi<72> a_wi<71> a_wi<70> a_wi<69> a_wi<68> a_wi<67> a_wi<66> a_wi<65> a_wi<64> a_wi<63> a_wi<62> a_wi<61> a_wi<60> a_wi<59> a_wi<58> a_wi<57> a_wi<56> a_wi<55> a_wi<54> a_wi<53> a_wi<52> a_wi<51> a_wi<50> a_wi<49> a_wi<48> a_wi<47> a_wi<46> a_wi<45> a_wi<44> a_wi<43> a_wi<42> a_wi<41> a_wi<40> a_wi<39> a_wi<38> a_wi<37> a_wi<36> a_wi<35> a_wi<34> a_wi<33> a_wi<32> a_wi<31> a_wi<30> a_wi<29> a_wi<28> a_wi<27> a_wi<26> a_wi<25> a_wi<24> a_wi<23> a_wi<22> a_wi<21> a_wi<20> a_wi<19> a_wi<18> a_wi<17> a_wi<16> a_wi<15> a_wi<14> a_wi<13> a_wi<12> a_wi<11> a_wi<10> a_wi<9> a_wi<8> a_wi<7> a_wi<6> a_wi<5> a_wi<4> a_wi<3> a_wi<2> a_wi<1> a_wi<0> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_ROWDEC9
+XA_ROWREG a_aclk_n A_ADDR<11> A_ADDR<10> A_ADDR<9> A_ADDR<8> A_ADDR<7> A_ADDR<6> A_ADDR<5> A_ADDR<4> A_ADDR<3> a_addr_row<8> a_addr_row<7> a_addr_row<6> a_addr_row<5> a_addr_row<4> a_addr_row<3> a_addr_row<2> a_addr_row<1> a_addr_row<0> A_BIST_ADDR<11> A_BIST_ADDR<10> A_BIST_ADDR<9> A_BIST_ADDR<8> A_BIST_ADDR<7> A_BIST_ADDR<6> A_BIST_ADDR<5> A_BIST_ADDR<4> A_BIST_ADDR<3> A_BIST_EN VDD! VSS!  / RM_IHPSG13_4096x8_c3_1P_ROWREG9
+XA_COLDEC a_aclk_n A_ADDR<2> A_ADDR<1> A_ADDR<0> a_addr_col<1> a_addr_col<0> a_addr_dec<7> a_addr_dec<6> a_addr_dec<5> a_addr_dec<4> a_addr_dec<3> a_addr_dec<2> a_addr_dec<1> a_addr_dec<0> A_BIST_ADDR<2> A_BIST_ADDR<1> A_BIST_ADDR<0> A_BIST_EN VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_COLDEC3
+
+
+XA_DLYH a_pulse a_pulse_h VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_DLY_pcell_2
+XA_DLYL a_pulse_x a_pulse_l VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_DLY_pcell_3
+XA_DLYMUX a_pulse_h A_DLY a_pulse_x VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_DLY_MUX
+
+XCOLCTRL<7> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<7> A_BIST_DIN<7> A_BIST_EN a_blc_r<31> a_blc_r<30> a_blc_r<29> a_blc_r<28> a_blc_r<27> a_blc_r<26> a_blc_r<25> a_blc_r<24> a_blt_r<31> a_blt_r<30> a_blt_r<29> a_blt_r<28> a_blt_r<27> a_blt_r<26> a_blt_r<25> a_blt_r<24> A_BM<7> a_dclk_n_r<3> a_dclk_n_r<4> a_dclk_p_r<3> a_dclk_p_r<4> A_DOUT<7> A_DIN<7> a_rclk_n_r<3> a_rclk_n_r<4> a_rclk_p_r<3> a_rclk_p_r<4> a_tieh<7> a_wclk_n_r<3> a_wclk_n_r<4> a_wclk_p_r<3> a_wclk_p_r<4> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_COLCTRL3
+XCOLCTRL<6> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<6> A_BIST_DIN<6> A_BIST_EN a_blc_r<23> a_blc_r<22> a_blc_r<21> a_blc_r<20> a_blc_r<19> a_blc_r<18> a_blc_r<17> a_blc_r<16> a_blt_r<23> a_blt_r<22> a_blt_r<21> a_blt_r<20> a_blt_r<19> a_blt_r<18> a_blt_r<17> a_blt_r<16> A_BM<6> a_dclk_n_r<2> a_dclk_n_r<3> a_dclk_p_r<2> a_dclk_p_r<3> A_DOUT<6> A_DIN<6> a_rclk_n_r<2> a_rclk_n_r<3> a_rclk_p_r<2> a_rclk_p_r<3> a_tieh<6> a_wclk_n_r<2> a_wclk_n_r<3> a_wclk_p_r<2> a_wclk_p_r<3> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_COLCTRL3
+XCOLCTRL<5> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<5> A_BIST_DIN<5> A_BIST_EN a_blc_r<15> a_blc_r<14> a_blc_r<13> a_blc_r<12> a_blc_r<11> a_blc_r<10> a_blc_r<9> a_blc_r<8> a_blt_r<15> a_blt_r<14> a_blt_r<13> a_blt_r<12> a_blt_r<11> a_blt_r<10> a_blt_r<9> a_blt_r<8> A_BM<5> a_dclk_n_r<1> a_dclk_n_r<2> a_dclk_p_r<1> a_dclk_p_r<2> A_DOUT<5> A_DIN<5> a_rclk_n_r<1> a_rclk_n_r<2> a_rclk_p_r<1> a_rclk_p_r<2> a_tieh<5> a_wclk_n_r<1> a_wclk_n_r<2> a_wclk_p_r<1> a_wclk_p_r<2> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_COLCTRL3
+XCOLCTRL<4> a_addr_dec_r<7> a_addr_dec_r<6> a_addr_dec_r<5> a_addr_dec_r<4> a_addr_dec_r<3> a_addr_dec_r<2> a_addr_dec_r<1> a_addr_dec_r<0> A_BIST_BM<4> A_BIST_DIN<4> A_BIST_EN a_blc_r<7> a_blc_r<6> a_blc_r<5> a_blc_r<4> a_blc_r<3> a_blc_r<2> a_blc_r<1> a_blc_r<0> a_blt_r<7> a_blt_r<6> a_blt_r<5> a_blt_r<4> a_blt_r<3> a_blt_r<2> a_blt_r<1> a_blt_r<0> A_BM<4> a_dclk_n_r<0> a_dclk_n_r<1> a_dclk_p_r<0> a_dclk_p_r<1> A_DOUT<4> A_DIN<4> a_rclk_n_r<0> a_rclk_n_r<1> a_rclk_p_r<0> a_rclk_p_r<1> a_tieh<4> a_wclk_n_r<0> a_wclk_n_r<1> a_wclk_p_r<0> a_wclk_p_r<1> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_COLCTRL3
+XCOLCTRL<3> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<0> A_BIST_DIN<0> A_BIST_EN a_blc_l<31> a_blc_l<30> a_blc_l<29> a_blc_l<28> a_blc_l<27> a_blc_l<26> a_blc_l<25> a_blc_l<24> a_blt_l<31> a_blt_l<30> a_blt_l<29> a_blt_l<28> a_blt_l<27> a_blt_l<26> a_blt_l<25> a_blt_l<24> A_BM<0> a_dclk_n_l<3> a_dclk_n_l<4> a_dclk_p_l<3> a_dclk_p_l<4> A_DOUT<0> A_DIN<0> a_rclk_n_l<3> a_rclk_n_l<4> a_rclk_p_l<3> a_rclk_p_l<4> a_tieh<0> a_wclk_n_l<3> a_wclk_n_l<4> a_wclk_p_l<3> a_wclk_p_l<4> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_COLCTRL3
+XCOLCTRL<2> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<1> A_BIST_DIN<1> A_BIST_EN a_blc_l<23> a_blc_l<22> a_blc_l<21> a_blc_l<20> a_blc_l<19> a_blc_l<18> a_blc_l<17> a_blc_l<16> a_blt_l<23> a_blt_l<22> a_blt_l<21> a_blt_l<20> a_blt_l<19> a_blt_l<18> a_blt_l<17> a_blt_l<16> A_BM<1> a_dclk_n_l<2> a_dclk_n_l<3> a_dclk_p_l<2> a_dclk_p_l<3> A_DOUT<1> A_DIN<1> a_rclk_n_l<2> a_rclk_n_l<3> a_rclk_p_l<2> a_rclk_p_l<3> a_tieh<1> a_wclk_n_l<2> a_wclk_n_l<3> a_wclk_p_l<2> a_wclk_p_l<3> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_COLCTRL3
+XCOLCTRL<1> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<2> A_BIST_DIN<2> A_BIST_EN a_blc_l<15> a_blc_l<14> a_blc_l<13> a_blc_l<12> a_blc_l<11> a_blc_l<10> a_blc_l<9> a_blc_l<8> a_blt_l<15> a_blt_l<14> a_blt_l<13> a_blt_l<12> a_blt_l<11> a_blt_l<10> a_blt_l<9> a_blt_l<8> A_BM<2> a_dclk_n_l<1> a_dclk_n_l<2> a_dclk_p_l<1> a_dclk_p_l<2> A_DOUT<2> A_DIN<2> a_rclk_n_l<1> a_rclk_n_l<2> a_rclk_p_l<1> a_rclk_p_l<2> a_tieh<2> a_wclk_n_l<1> a_wclk_n_l<2> a_wclk_p_l<1> a_wclk_p_l<2> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_COLCTRL3
+XCOLCTRL<0> a_addr_dec_l<7> a_addr_dec_l<6> a_addr_dec_l<5> a_addr_dec_l<4> a_addr_dec_l<3> a_addr_dec_l<2> a_addr_dec_l<1> a_addr_dec_l<0> A_BIST_BM<3> A_BIST_DIN<3> A_BIST_EN a_blc_l<7> a_blc_l<6> a_blc_l<5> a_blc_l<4> a_blc_l<3> a_blc_l<2> a_blc_l<1> a_blc_l<0> a_blt_l<7> a_blt_l<6> a_blt_l<5> a_blt_l<4> a_blt_l<3> a_blt_l<2> a_blt_l<1> a_blt_l<0> A_BM<3> a_dclk_n_l<0> a_dclk_n_l<1> a_dclk_p_l<0> a_dclk_p_l<1> A_DOUT<3> A_DIN<3> a_rclk_n_l<0> a_rclk_n_l<1> a_rclk_p_l<0> a_rclk_p_l<1> a_tieh<3> a_wclk_n_l<0> a_wclk_n_l<1> a_wclk_p_l<0> a_wclk_p_l<1> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_COLCTRL3
+
+
+XDRVFILL4<1> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_COLDRV13_FILL4
+XDRVFILL4<2> VDD! VSS! / RM_IHPSG13_4096x8_c3_1P_COLDRV13_FILL4
+.ENDS
diff --git a/ihp-sg13g2/libs.ref/sg13g2_sram/doc/RM_IHPSG13_1P_1024x16_c2_bm_bist.txt b/ihp-sg13g2/libs.ref/sg13g2_sram/doc/RM_IHPSG13_1P_1024x16_c2_bm_bist.txt
new file mode 100644
index 00000000..6688f9ee
--- /dev/null
+++ b/ihp-sg13g2/libs.ref/sg13g2_sram/doc/RM_IHPSG13_1P_1024x16_c2_bm_bist.txt
@@ -0,0 +1,317 @@
+# ------------------------------------------------------
+#
+#		Copyright 2024 IHP PDK Authors
+#
+#		Licensed under the Apache License, Version 2.0 (the "License");
+#		you may not use this file except in compliance with the License.
+#		You may obtain a copy of the License at
+#		
+#		   https://www.apache.org/licenses/LICENSE-2.0
+#		
+#		Unless required by applicable law or agreed to in writing, software
+#		distributed under the License is distributed on an "AS IS" BASIS,
+#		WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#		See the License for the specific language governing permissions and
+#		limitations under the License.
+#		
+#		Generated on Fri Jul 19 08:58:04 2024		
+#				
+# ------------------------------------------------------ 
+
+
+#################
+D A T A S H E E T
+#################
+
+
+Name             : RM_IHPSG13_1P_1024x16_c2_bm_bist
+Size             : 1024 words x 16 bits
+Column Mux       : 2
+Number of Ports  : 1
+Area (h x w)     : 336.46 x 236.80 = 79673.73 square microns
+
+
+##################
+Introduction
+##################
+
+
+This 1-port macro has a one-cycle data-access.
+For timing information overview have a look at the timing diagrams in the "Timing Diagrams" section below.
+
+
+##################
+Schematic View
+##################
+
+
+                    ________________________________________
+                   |                                        |
+                   |                                        |
+                ---|A_DIN[15:0]                             |
+                ---|A_BM[15:0]                              |
+                ---|A_ADDR[9:0]                             |
+                ---|A_MEN                                   |
+                ---|A_REN                                   |
+                ---|A_WEN                                   |
+                ---|A_CLK                                   |
+                   |                                        |
+                ---|A_BIST_DIN[15:0]                        |
+                ---|A_BIST_BM[15:0]                         |
+                ---|A_BIST_ADDR[9:0]                        |
+                ---|A_BIST_MEN                              |
+                ---|A_BIST_REN                              |
+                ---|A_BIST_WEN                              |
+                ---|A_BIST_CLK                              |
+                   |                                        |
+                ---|A_BIST_EN                               |
+                   |                                        |
+                ---|A_DLY                                   |
+                   |                                        |
+                   |                            A_DOUT[15:0]|---
+                   |                                        |
+                   |________________________________________|
+
+
+###########################
+Macro Interface Signal List
+###########################
+
+
+Signal              Sensitivity                 Logic            Direction     Description
+------              -----------                 -----            ---------     -----------
+A_ADDR[9:0]         Positive Clock Edge         Positive         Input         10 address bits  
+A_DIN[15:0]         Positive Clock Edge         Positive         Input         16 data bits 
+A_BM[15:0]          Positive Clock Edge         Positive         Input         16 bit mask bits   
+A_WEN               Positive Clock Edge         Positive         Input         Write-enable  
+A_MEN               Positive Clock Edge         Positive         Input         Memory enable -> if disabled, the memory is deactivated   
+A_REN               Positive Clock Edge         Positive         Input         Read enable 
+A_CLK               Clock                       Positive         Input         Clock pin   
+A_BIST_DIN[15:0]    Positive Clock Edge         Positive         Input         16 data bits 
+A_BIST_BM[15:0]     Positive Clock Edge         Positive         Input         16 bit mask bits   
+A_BIST_ADDR[9:0]    Positive Clock Edge         Positive         Input         10 address bits for BIST mode  
+A_BIST_WEN          Positive Clock Edge         Positive         Input         BIST Write-enable   
+A_BIST_MEN          Positive Clock Edge         Positive         Input         BIST Memory enable -> if disabled, the memory is deactivated  
+A_BIST_REN          Positive Clock Edge         Positive         Input         BIST Read enable  
+A_BIST_CLK          Clock                       Positive         Input         BIST Clock pin  
+A_BIST_EN           Positive Clock Edge         Positive         Input         BIST Enable pin 
+A_DOUT[15:0]        Positive Clock Edge         Positive         Output        16 data bits, no high impedance function   
+A_DLY               Level                       Positive         Input         Delay setting, adjustment of memory internal timings; recommended setting: Tie to 1
+
+VDD                                                                            Macro support logic supply voltage
+VSS                                                                            Macro support logic ground
+VDDARRAY                                                                       Memory array supply voltage
+----------------------------------------------------------------------------------------------------------------------------------------------------------
+
+
+
+
+###########################
+Operation Tables
+###########################
+
+
+When A_BIST_EN is disabled A_ADDR is used as address input.
+When A_BIST_EN is enabled A_BIST_ADDR is used as address input.
+
+! Note: One cycle before and after A_BIST_EN changes no read, write, or write-through operation is allowed.
+- Set A_MEN and A_BIST_MEN to 0.
+
+A_BIST_EN       A_MEN         A_REN         A_WEN           Operation on Memory
+---------       -----         -----         -----           ----------------------
+    0             0           0 / 1         0 / 1           No Operation
+    0             1             0             0             No Operation
+    0             1             1             0             Read
+    0             1             0             1             Write
+    0             1             1             1             Write-Through
+    1           0 / 1         0 / 1         0 / 1           No Operation
+
+A_BIST_EN    A_BIST_MEN     A_BIST_REN     A_BIST_WEN       Operation on Memory
+---------    ----------     ----------     ----------       ----------------------
+    1             0           0 / 1          0 / 1          No Operation
+    1             1             0              0            No Operation
+    1             1             1              0            Read
+    1             1             0              1            Write
+    1             1             1              1            Write-Through
+    0           0 / 1         0 / 1          0 / 1          No Operation
+
+
+
+
+###########################
+Timing Diagrams
+###########################
+
+
+All timings are identical for BIST mode.
+
+
+                                WRITE                              READ                            WRITE-THROUGH                    NO OPERATION
+
+                                  |-----T_CKH----->|
+     ___________                  | ______________ |                 | _______________                   _______________                  _____________
+ A_CLK          \                 |/              \|                 |/               \                 /               \                /
+                 \_______________/|                |\_______________/|                 \_______________/                 \______________/
+                      |           |                                  |                         |
+                      |<-Tsetup---|                                  |-------T_CLK2DOUT------->|
+     ________________ | __________|__________|___________  _________________________________  _|_______________________________________________________
+ A_ADDR      A_ADDR0 \|/          |          |  A_ADDR1  \/       A_ADDR2                   \/ |        A_ADDR3
+     ________________/|\__________|_________ |___________/\_________________________________/\_|_______________________________________________________
+                      |           |          |                                                 |
+                      |           |---Thold->|                                                 |
+     ________________ | __________|__________|___________  _________________________________  _|_______________________________________________________
+ A_DIN               \|/          |          |  A_D1     \/       don't care                \/ |        A_D3
+     ________________/|\__________|__________|___________/\_________________________________/\_|_______________________________________________________
+                      |           |          |                                                 |
+                      | __________|__________|_________________________________________________|______________________
+ A_MEN                |/          |          |                                                 |                      \
+     ________________/|           |          |                                                 |                       \_______________________________
+                      |           |          |                                                 |
+                      | __________|_________ |                                               __|______________________
+ A_WEN                |/          |         \|                                              /  |                      \
+     ________________/|           |          |\____________________________________________/   |                       \_______________________________
+                      |           |          |                                                 |
+                      |           |          |            _____________________________________|______________________
+ A_REN                |           |          |           /                                     |                      \
+     _________________|___________|__________|__________/                                      |                       \_______________________________
+                      |           |          |                                                 |
+     _________________________________________________________________________________________ | ____________________________________  ________________
+ A_DOUT                            'X'                                                        \|/         MEMORY(A_ADDR2)            \/    A_D3
+     _________________________________________________________________________________________/|\____________________________________/\________________
+                                                                                               |
+     ________________________________________________  __________________________________________________________________________  ____________________
+ A_MEMORY                          'X'               \/          MEMORY(A_ADDR1)=A_D1                                            \/MEMORY(A_ADDR3)=A_D3
+     ________________________________________________/\__________________________________________________________________________/\____________________
+
+
+
+	
+
+
+###########################
+Operating Conditions
+###########################
+
+
++-------------+----------------------+-----------+------+------+-------+
+| Symbol      | Parameter            | Condition | Min  | Max  | Units |
++-------------+----------------------+-----------+------+------+-------+
+| VDD         | Supply Voltage Range | Operating | 1.08 | 1.32 | V     |
+| Temperature |                      | Operating | -55  | 125  | �C    |
+| tCKH        | Min Pulse Width      | Operating | 0.12 | 0.4  | ns    |
++-------------+----------------------+-----------+------+------+-------+
+
+
+
+###########################
+Characterization Corners
+###########################
+
+
++--------------------------+--------------+-----------+-------------+------------------+
+| Operating Condition Name | Model Corner | Condition | Voltage [V] | Temperature [�C] |
++--------------------------+--------------+-----------+-------------+------------------+
+| wc_1d08V_125C            | wc           | working   | 1.08        | 125              |
+| bc_1d32V_m55C            | bc           | working   | 1.32        | -55              |
+| tc_1d20V_25C             | tc           | working   | 1.20        | 25               |
++--------------------------+--------------+-----------+-------------+------------------+
+
+
+
+###########################
+Timing Characteristics
+###########################
+
+
++-------------------+-------------+-----------+---------------+---------------+--------------+-------+
+| Timing            | Timing Type | Direction | wc_1d08V_125C | bc_1d32V_m55C | tc_1d20V_25C | Units |
++-------------------+-------------+-----------+---------------+---------------+--------------+-------+
+| Clock to Data Out | Delay       | Rising    | 7.19e+00      | 2.64e+00      | 4.30e+00     | ns    |
+| Clock to Data Out | Delay       | Falling   | 7.07e+00      | 2.60e+00      | 4.23e+00     | ns    |
+| Data Out          | Transition  | Rising    | 4.08e-02      | 1.62e-02      | 2.59e-02     | ns    |
+| Data Out          | Transition  | Falling   | 3.29e-02      | 1.35e-02      | 2.01e-02     | ns    |
++-------------------+-------------+-----------+---------------+---------------+--------------+-------+
+
+
+
+###########################
+Power Characteristics
+###########################
+
+
+Typical Power Unit : 1e-12 * J/toggle = 1 * uW/MHz
+                            (capacitive_load_unit * voltage_unit^2) per toggle event
+------------------------------------------------------------------------------------------
++---------------------+---------------+---------------+--------------+------------+
+| Power               | wc_1d08V_125C | bc_1d32V_m55C | tc_1d20V_25C | Units      |
++---------------------+---------------+---------------+--------------+------------+
+| Leakage Power       | 1.307e+03     | 4.696e+02     | 1.980e+02    | 1nW        |
+| Total Typical Power | 2.697e+01     | 4.152e+01     | 3.376e+01    | 1 * uW/MHz |
++---------------------+---------------+---------------+--------------+------------+
+
+
+
+#################
+Physical Layout
+#################
+
+
+Metal usage is up to M4. 
+The bottom figure shows the physical layout of the 1024x16_c2 SRAM hard macro with its dimensions.
+Note: Row decoder and interface pin locations as well as location, dimension and number of power rails are approximated.
+
+                                                  236.8 microns
+         <-------------------------------------------------------------------------------------------------------->
+          _________________________________________________________________________________________________________
+       ^ |VDD|    |VDD|     |VDD|     |VDD|      |        |VDD|VDD|        |      |VDD|    |VDD|     |VDD|    |VDD|  ^
+       | |VSS|    |VSS|     |VSS|     |VSS|      |        |VSS|VSS|        |      |VSS|    |VSS|     |VSS|    |VSS|  |
+       | |   |    |   |     |   |     |   |      |        |   |   |        |      |   |    |   |     |   |    |   |  |
+       | |PWR|    |ARR|     |PWR|     |ARR|      | L      |PWR|PWR|      R |      |ARR|    |PWR|     |ARR|    |PWR|  |
+       | |   |    |AY |     |   |     |AY |      |  E     |   |   |     I  |      | YA|    |   |     | YA|    |   |  |
+       | |   |    |   |     |   |     |   |      |   F    |   |   |    G   |      |   |    |   |     |   |    |   |  |
+       | |   |    |PWR|     |   |     |PWR|      |    T   |   |   |   H    |      |PWR|    |   |     |PWR|    |   |  |
+       | |   |    |   |     |   |     |   |      |        |   |   |  T     |      |   |    |   |     |   |    |   |  |
+SRAM   | |   |    |   |     |   |     |   |      |  R     |   |   |     R  |      |   |    |   |     |   |    |   |  |
+Array  | |   |    |   |     |   |     |   |      |   O    |   |   |    O   |      |   |    |   |     |   |    |   |  |336.46 microns
+       | |S  |    |S  |     |S  |     |S  |      |    W   |S  |  S|   W    |      |  S|    |  S|	 |  S|    |  S|  |
+       | | T |    | T |     | T |     | T |      |  D     | T | T |     D  |      | T |    | T |	 | T |    | T |  |
+       | |  R|    |  R|     |  R|     |  R|      |   E    |  R|R  |    E   |      |R  |    |R  |	 |R  |    |R  |  |
+       | | I |    | I |     | I |     | I |      |    C   | I | I |   C    |      | I |    | I |	 | I |    | I |  |
+       | |P  |    |P  |     |P  |     |P  |      |        |P  |  P|        |      |  P|    |  P|	 |  P|    |  P|  |
+       | | E |    | E |     | E |     | E |      |        | E | E |        |      | E |    | E |	 | E |    | E |  |
+       v |__S|____|__S|_____|__S|_____|__S|______|________|__S|S__|________|______|S__|____|S__|_____|S__|____|S__|  |
+       ^ |   |              |   |                |        |   |   |        |               |   |              |   |  |
+       | |___|     ___      |___|      ___       |        |___|___|        |       ___     |___|      ___     |___|  |
+Inter- | |VDD|    |VDD|     |VDD|     |VDD|      |        |VDD|VDD|        |      |VDD|    |VDD|     |VDD|    |VDD|  |
+face   | |VSS|    |VSS|     |VSS|     |VSS|      |        |VSS|VSS|        |      |VSS|    |VSS|     |VSS|    |VSS|  |
+Pins   v |___|____|___|_____|___|_____|___|______|________|___|___|________|______|___|____|___|_____|___|____|___|  v
+
+
+
+Address calculation for BIST_ADDR in BIST modeare identical to ADDR as seen below.
+
+The SRAM macro is physically organized in 2 x 32 horizontal x 1024 vertical bit cells:
+ - Row address pins (MSB..LSB)     : 8;           ya[7:0]     = ADDR[10:2]        
+ - Column address pins (MSB..LSB)  : 2;           xa[1:0]     = ADDR[1:0]         
+ - Data pins (MSB..LSB)            : 16;          xa[15:0]    = DIN[15:0], DOUT[15:0].
+
+The scrambling scheme reads as follows:
+ - X-Address Scrambling: xa[i] = x[i]
+ - Y-Address Scrambling: ya[j] = not(y[j])
+
+Translation from physical (x,y,d) to topological (x,y) addresses:
+  x_topo = f(x_physical, y_physical, d) =
+                    if (d<12)      {d*32+31-x}    
+                    else           {d*32+x}  
+
+  y_topo = f(x_physical, y_physical, d) = y
+
+Note: The left and right sub-arrays are mirrored with respect to the y axis.
+
+Symbol definition:
+xa[0..n], ya[0..m]: externally applied device addresses
+
+x[0..n], y[0..m]:   internal physical addresses (address complete memory words)
+
+x_topo, y_topo:     internal topological addresses (address single bit cells)
+
diff --git a/ihp-sg13g2/libs.ref/sg13g2_sram/doc/RM_IHPSG13_1P_1024x8_c2_bm_bist.txt b/ihp-sg13g2/libs.ref/sg13g2_sram/doc/RM_IHPSG13_1P_1024x8_c2_bm_bist.txt
new file mode 100644
index 00000000..721d3038
--- /dev/null
+++ b/ihp-sg13g2/libs.ref/sg13g2_sram/doc/RM_IHPSG13_1P_1024x8_c2_bm_bist.txt
@@ -0,0 +1,317 @@
+# ------------------------------------------------------
+#
+#		Copyright 2024 IHP PDK Authors
+#
+#		Licensed under the Apache License, Version 2.0 (the "License");
+#		you may not use this file except in compliance with the License.
+#		You may obtain a copy of the License at
+#		
+#		   https://www.apache.org/licenses/LICENSE-2.0
+#		
+#		Unless required by applicable law or agreed to in writing, software
+#		distributed under the License is distributed on an "AS IS" BASIS,
+#		WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#		See the License for the specific language governing permissions and
+#		limitations under the License.
+#		
+#		Generated on Fri Jul 19 09:01:13 2024		
+#				
+# ------------------------------------------------------ 
+
+
+#################
+D A T A S H E E T
+#################
+
+
+Name             : RM_IHPSG13_1P_1024x8_c2_bm_bist
+Size             : 1024 words x 8 bits
+Column Mux       : 2
+Number of Ports  : 1
+Area (h x w)     : 336.46 x 146.88 = 49419.24 square microns
+
+
+##################
+Introduction
+##################
+
+
+This 1-port macro has a one-cycle data-access.
+For timing information overview have a look at the timing diagrams in the "Timing Diagrams" section below.
+
+
+##################
+Schematic View
+##################
+
+
+                    ________________________________________
+                   |                                        |
+                   |                                        |
+                ---|A_DIN[7:0]                              |
+                ---|A_BM[7:0]                               |
+                ---|A_ADDR[9:0]                             |
+                ---|A_MEN                                   |
+                ---|A_REN                                   |
+                ---|A_WEN                                   |
+                ---|A_CLK                                   |
+                   |                                        |
+                ---|A_BIST_DIN[7:0]                         |
+                ---|A_BIST_BM[7:0]                          |
+                ---|A_BIST_ADDR[9:0]                        |
+                ---|A_BIST_MEN                              |
+                ---|A_BIST_REN                              |
+                ---|A_BIST_WEN                              |
+                ---|A_BIST_CLK                              |
+                   |                                        |
+                ---|A_BIST_EN                               |
+                   |                                        |
+                ---|A_DLY                                   |
+                   |                                        |
+                   |                             A_DOUT[7:0]|---
+                   |                                        |
+                   |________________________________________|
+
+
+###########################
+Macro Interface Signal List
+###########################
+
+
+Signal              Sensitivity                 Logic            Direction     Description
+------              -----------                 -----            ---------     -----------
+A_ADDR[9:0]         Positive Clock Edge         Positive         Input         10 address bits  
+A_DIN[7:0]          Positive Clock Edge         Positive         Input         8 data bits 
+A_BM[7:0]           Positive Clock Edge         Positive         Input         8 bit mask bits   
+A_WEN               Positive Clock Edge         Positive         Input         Write-enable  
+A_MEN               Positive Clock Edge         Positive         Input         Memory enable -> if disabled, the memory is deactivated   
+A_REN               Positive Clock Edge         Positive         Input         Read enable 
+A_CLK               Clock                       Positive         Input         Clock pin   
+A_BIST_DIN[7:0]     Positive Clock Edge         Positive         Input         8 data bits 
+A_BIST_BM[7:0]      Positive Clock Edge         Positive         Input         8 bit mask bits   
+A_BIST_ADDR[9:0]    Positive Clock Edge         Positive         Input         10 address bits for BIST mode  
+A_BIST_WEN          Positive Clock Edge         Positive         Input         BIST Write-enable   
+A_BIST_MEN          Positive Clock Edge         Positive         Input         BIST Memory enable -> if disabled, the memory is deactivated  
+A_BIST_REN          Positive Clock Edge         Positive         Input         BIST Read enable  
+A_BIST_CLK          Clock                       Positive         Input         BIST Clock pin  
+A_BIST_EN           Positive Clock Edge         Positive         Input         BIST Enable pin 
+A_DOUT[7:0]         Positive Clock Edge         Positive         Output        8 data bits, no high impedance function   
+A_DLY               Level                       Positive         Input         Delay setting, adjustment of memory internal timings; recommended setting: Tie to 1
+
+VDD                                                                            Macro support logic supply voltage
+VSS                                                                            Macro support logic ground
+VDDARRAY                                                                       Memory array supply voltage
+----------------------------------------------------------------------------------------------------------------------------------------------------------
+
+
+
+
+###########################
+Operation Tables
+###########################
+
+
+When A_BIST_EN is disabled A_ADDR is used as address input.
+When A_BIST_EN is enabled A_BIST_ADDR is used as address input.
+
+! Note: One cycle before and after A_BIST_EN changes no read, write, or write-through operation is allowed.
+- Set A_MEN and A_BIST_MEN to 0.
+
+A_BIST_EN       A_MEN         A_REN         A_WEN           Operation on Memory
+---------       -----         -----         -----           ----------------------
+    0             0           0 / 1         0 / 1           No Operation
+    0             1             0             0             No Operation
+    0             1             1             0             Read
+    0             1             0             1             Write
+    0             1             1             1             Write-Through
+    1           0 / 1         0 / 1         0 / 1           No Operation
+
+A_BIST_EN    A_BIST_MEN     A_BIST_REN     A_BIST_WEN       Operation on Memory
+---------    ----------     ----------     ----------       ----------------------
+    1             0           0 / 1          0 / 1          No Operation
+    1             1             0              0            No Operation
+    1             1             1              0            Read
+    1             1             0              1            Write
+    1             1             1              1            Write-Through
+    0           0 / 1         0 / 1          0 / 1          No Operation
+
+
+
+
+###########################
+Timing Diagrams
+###########################
+
+
+All timings are identical for BIST mode.
+
+
+                                WRITE                              READ                            WRITE-THROUGH                    NO OPERATION
+
+                                  |-----T_CKH----->|
+     ___________                  | ______________ |                 | _______________                   _______________                  _____________
+ A_CLK          \                 |/              \|                 |/               \                 /               \                /
+                 \_______________/|                |\_______________/|                 \_______________/                 \______________/
+                      |           |                                  |                         |
+                      |<-Tsetup---|                                  |-------T_CLK2DOUT------->|
+     ________________ | __________|__________|___________  _________________________________  _|_______________________________________________________
+ A_ADDR      A_ADDR0 \|/          |          |  A_ADDR1  \/       A_ADDR2                   \/ |        A_ADDR3
+     ________________/|\__________|_________ |___________/\_________________________________/\_|_______________________________________________________
+                      |           |          |                                                 |
+                      |           |---Thold->|                                                 |
+     ________________ | __________|__________|___________  _________________________________  _|_______________________________________________________
+ A_DIN               \|/          |          |  A_D1     \/       don't care                \/ |        A_D3
+     ________________/|\__________|__________|___________/\_________________________________/\_|_______________________________________________________
+                      |           |          |                                                 |
+                      | __________|__________|_________________________________________________|______________________
+ A_MEN                |/          |          |                                                 |                      \
+     ________________/|           |          |                                                 |                       \_______________________________
+                      |           |          |                                                 |
+                      | __________|_________ |                                               __|______________________
+ A_WEN                |/          |         \|                                              /  |                      \
+     ________________/|           |          |\____________________________________________/   |                       \_______________________________
+                      |           |          |                                                 |
+                      |           |          |            _____________________________________|______________________
+ A_REN                |           |          |           /                                     |                      \
+     _________________|___________|__________|__________/                                      |                       \_______________________________
+                      |           |          |                                                 |
+     _________________________________________________________________________________________ | ____________________________________  ________________
+ A_DOUT                            'X'                                                        \|/         MEMORY(A_ADDR2)            \/    A_D3
+     _________________________________________________________________________________________/|\____________________________________/\________________
+                                                                                               |
+     ________________________________________________  __________________________________________________________________________  ____________________
+ A_MEMORY                          'X'               \/          MEMORY(A_ADDR1)=A_D1                                            \/MEMORY(A_ADDR3)=A_D3
+     ________________________________________________/\__________________________________________________________________________/\____________________
+
+
+
+	
+
+
+###########################
+Operating Conditions
+###########################
+
+
++-------------+----------------------+-----------+------+------+-------+
+| Symbol      | Parameter            | Condition | Min  | Max  | Units |
++-------------+----------------------+-----------+------+------+-------+
+| VDD         | Supply Voltage Range | Operating | 1.08 | 1.32 | V     |
+| Temperature |                      | Operating | -55  | 125  | �C    |
+| tCKH        | Min Pulse Width      | Operating | 0.12 | 0.4  | ns    |
++-------------+----------------------+-----------+------+------+-------+
+
+
+
+###########################
+Characterization Corners
+###########################
+
+
++--------------------------+--------------+-----------+-------------+------------------+
+| Operating Condition Name | Model Corner | Condition | Voltage [V] | Temperature [�C] |
++--------------------------+--------------+-----------+-------------+------------------+
+| wc_1d08V_125C            | wc           | working   | 1.08        | 125              |
+| bc_1d32V_m55C            | bc           | working   | 1.32        | -55              |
+| tc_1d20V_25C             | tc           | working   | 1.20        | 25               |
++--------------------------+--------------+-----------+-------------+------------------+
+
+
+
+###########################
+Timing Characteristics
+###########################
+
+
++-------------------+-------------+-----------+---------------+---------------+--------------+-------+
+| Timing            | Timing Type | Direction | wc_1d08V_125C | bc_1d32V_m55C | tc_1d20V_25C | Units |
++-------------------+-------------+-----------+---------------+---------------+--------------+-------+
+| Clock to Data Out | Delay       | Rising    | 7.12e+00      | 2.62e+00      | 4.26e+00     | ns    |
+| Clock to Data Out | Delay       | Falling   | 7.01e+00      | 2.58e+00      | 4.19e+00     | ns    |
+| Data Out          | Transition  | Rising    | 4.08e-02      | 1.62e-02      | 2.59e-02     | ns    |
+| Data Out          | Transition  | Falling   | 3.29e-02      | 1.35e-02      | 2.01e-02     | ns    |
++-------------------+-------------+-----------+---------------+---------------+--------------+-------+
+
+
+
+###########################
+Power Characteristics
+###########################
+
+
+Typical Power Unit : 1e-12 * J/toggle = 1 * uW/MHz
+                            (capacitive_load_unit * voltage_unit^2) per toggle event
+------------------------------------------------------------------------------------------
++---------------------+---------------+---------------+--------------+------------+
+| Power               | wc_1d08V_125C | bc_1d32V_m55C | tc_1d20V_25C | Units      |
++---------------------+---------------+---------------+--------------+------------+
+| Leakage Power       | 6.533e+02     | 2.348e+02     | 9.901e+01    | 1nW        |
+| Total Typical Power | 1.580e+01     | 2.415e+01     | 1.970e+01    | 1 * uW/MHz |
++---------------------+---------------+---------------+--------------+------------+
+
+
+
+#################
+Physical Layout
+#################
+
+
+Metal usage is up to M4. 
+The bottom figure shows the physical layout of the 1024x8_c2 SRAM hard macro with its dimensions.
+Note: Row decoder and interface pin locations as well as location, dimension and number of power rails are approximated.
+
+                                                  146.88 microns
+         <-------------------------------------------------------------------------------------------------------->
+          _________________________________________________________________________________________________________
+       ^ |VDD|    |VDD|     |VDD|     |VDD|      |        |VDD|VDD|        |      |VDD|    |VDD|     |VDD|    |VDD|  ^
+       | |VSS|    |VSS|     |VSS|     |VSS|      |        |VSS|VSS|        |      |VSS|    |VSS|     |VSS|    |VSS|  |
+       | |   |    |   |     |   |     |   |      |        |   |   |        |      |   |    |   |     |   |    |   |  |
+       | |PWR|    |ARR|     |PWR|     |ARR|      | L      |PWR|PWR|      R |      |ARR|    |PWR|     |ARR|    |PWR|  |
+       | |   |    |AY |     |   |     |AY |      |  E     |   |   |     I  |      | YA|    |   |     | YA|    |   |  |
+       | |   |    |   |     |   |     |   |      |   F    |   |   |    G   |      |   |    |   |     |   |    |   |  |
+       | |   |    |PWR|     |   |     |PWR|      |    T   |   |   |   H    |      |PWR|    |   |     |PWR|    |   |  |
+       | |   |    |   |     |   |     |   |      |        |   |   |  T     |      |   |    |   |     |   |    |   |  |
+SRAM   | |   |    |   |     |   |     |   |      |  R     |   |   |     R  |      |   |    |   |     |   |    |   |  |
+Array  | |   |    |   |     |   |     |   |      |   O    |   |   |    O   |      |   |    |   |     |   |    |   |  |336.46 microns
+       | |S  |    |S  |     |S  |     |S  |      |    W   |S  |  S|   W    |      |  S|    |  S|	 |  S|    |  S|  |
+       | | T |    | T |     | T |     | T |      |  D     | T | T |     D  |      | T |    | T |	 | T |    | T |  |
+       | |  R|    |  R|     |  R|     |  R|      |   E    |  R|R  |    E   |      |R  |    |R  |	 |R  |    |R  |  |
+       | | I |    | I |     | I |     | I |      |    C   | I | I |   C    |      | I |    | I |	 | I |    | I |  |
+       | |P  |    |P  |     |P  |     |P  |      |        |P  |  P|        |      |  P|    |  P|	 |  P|    |  P|  |
+       | | E |    | E |     | E |     | E |      |        | E | E |        |      | E |    | E |	 | E |    | E |  |
+       v |__S|____|__S|_____|__S|_____|__S|______|________|__S|S__|________|______|S__|____|S__|_____|S__|____|S__|  |
+       ^ |   |              |   |                |        |   |   |        |               |   |              |   |  |
+       | |___|     ___      |___|      ___       |        |___|___|        |       ___     |___|      ___     |___|  |
+Inter- | |VDD|    |VDD|     |VDD|     |VDD|      |        |VDD|VDD|        |      |VDD|    |VDD|     |VDD|    |VDD|  |
+face   | |VSS|    |VSS|     |VSS|     |VSS|      |        |VSS|VSS|        |      |VSS|    |VSS|     |VSS|    |VSS|  |
+Pins   v |___|____|___|_____|___|_____|___|______|________|___|___|________|______|___|____|___|_____|___|____|___|  v
+
+
+
+Address calculation for BIST_ADDR in BIST modeare identical to ADDR as seen below.
+
+The SRAM macro is physically organized in 2 x 16 horizontal x 1024 vertical bit cells:
+ - Row address pins (MSB..LSB)     : 8;           ya[7:0]     = ADDR[10:2]        
+ - Column address pins (MSB..LSB)  : 2;           xa[1:0]     = ADDR[1:0]         
+ - Data pins (MSB..LSB)            : 8;           xa[7:0]     = DIN[7:0], DOUT[7:0].
+
+The scrambling scheme reads as follows:
+ - X-Address Scrambling: xa[i] = x[i]
+ - Y-Address Scrambling: ya[j] = not(y[j])
+
+Translation from physical (x,y,d) to topological (x,y) addresses:
+  x_topo = f(x_physical, y_physical, d) =
+                    if (d<12)      {d*32+31-x}    
+                    else           {d*32+x}  
+
+  y_topo = f(x_physical, y_physical, d) = y
+
+Note: The left and right sub-arrays are mirrored with respect to the y axis.
+
+Symbol definition:
+xa[0..n], ya[0..m]: externally applied device addresses
+
+x[0..n], y[0..m]:   internal physical addresses (address complete memory words)
+
+x_topo, y_topo:     internal topological addresses (address single bit cells)
+
diff --git a/ihp-sg13g2/libs.ref/sg13g2_sram/doc/RM_IHPSG13_1P_4096x16_c3_bm_bist.txt b/ihp-sg13g2/libs.ref/sg13g2_sram/doc/RM_IHPSG13_1P_4096x16_c3_bm_bist.txt
new file mode 100644
index 00000000..d9617234
--- /dev/null
+++ b/ihp-sg13g2/libs.ref/sg13g2_sram/doc/RM_IHPSG13_1P_4096x16_c3_bm_bist.txt
@@ -0,0 +1,317 @@
+# ------------------------------------------------------
+#
+#		Copyright 2024 IHP PDK Authors
+#
+#		Licensed under the Apache License, Version 2.0 (the "License");
+#		you may not use this file except in compliance with the License.
+#		You may obtain a copy of the License at
+#		
+#		   https://www.apache.org/licenses/LICENSE-2.0
+#		
+#		Unless required by applicable law or agreed to in writing, software
+#		distributed under the License is distributed on an "AS IS" BASIS,
+#		WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#		See the License for the specific language governing permissions and
+#		limitations under the License.
+#		
+#		Generated on Fri Jul 12 17:37:35 2024		
+#				
+# ------------------------------------------------------ 
+
+
+#################
+D A T A S H E E T
+#################
+
+
+Name             : RM_IHPSG13_1P_4096x16_c3_bm_bist
+Size             : 4096 words x 16 bits
+Column Mux       : 3
+Number of Ports  : 1
+Area (h x w)     : 618.30 x 416.64 = 257608.51 square microns
+
+
+##################
+Introduction
+##################
+
+
+This 1-port macro has a one-cycle data-access.
+For timing information overview have a look at the timing diagrams in the "Timing Diagrams" section below.
+
+
+##################
+Schematic View
+##################
+
+
+                    ________________________________________
+                   |                                        |
+                   |                                        |
+                ---|A_DIN[15:0]                             |
+                ---|A_BM[15:0]                              |
+                ---|A_ADDR[11:0]                            |
+                ---|A_MEN                                   |
+                ---|A_REN                                   |
+                ---|A_WEN                                   |
+                ---|A_CLK                                   |
+                   |                                        |
+                ---|A_BIST_DIN[15:0]                        |
+                ---|A_BIST_BM[15:0]                         |
+                ---|A_BIST_ADDR[11:0]                       |
+                ---|A_BIST_MEN                              |
+                ---|A_BIST_REN                              |
+                ---|A_BIST_WEN                              |
+                ---|A_BIST_CLK                              |
+                   |                                        |
+                ---|A_BIST_EN                               |
+                   |                                        |
+                ---|A_DLY                                   |
+                   |                                        |
+                   |                            A_DOUT[15:0]|---
+                   |                                        |
+                   |________________________________________|
+
+
+###########################
+Macro Interface Signal List
+###########################
+
+
+Signal              Sensitivity                 Logic            Direction     Description
+------              -----------                 -----            ---------     -----------
+A_ADDR[11:0]        Positive Clock Edge         Positive         Input         12 address bits  
+A_DIN[15:0]         Positive Clock Edge         Positive         Input         16 data bits 
+A_BM[15:0]          Positive Clock Edge         Positive         Input         16 bit mask bits   
+A_WEN               Positive Clock Edge         Positive         Input         Write-enable  
+A_MEN               Positive Clock Edge         Positive         Input         Memory enable -> if disabled, the memory is deactivated   
+A_REN               Positive Clock Edge         Positive         Input         Read enable 
+A_CLK               Clock                       Positive         Input         Clock pin   
+A_BIST_DIN[15:0]    Positive Clock Edge         Positive         Input         16 data bits 
+A_BIST_BM[15:0]     Positive Clock Edge         Positive         Input         16 bit mask bits   
+A_BIST_ADDR[11:0]   Positive Clock Edge         Positive         Input         12 address bits for BIST mode  
+A_BIST_WEN          Positive Clock Edge         Positive         Input         BIST Write-enable   
+A_BIST_MEN          Positive Clock Edge         Positive         Input         BIST Memory enable -> if disabled, the memory is deactivated  
+A_BIST_REN          Positive Clock Edge         Positive         Input         BIST Read enable  
+A_BIST_CLK          Clock                       Positive         Input         BIST Clock pin  
+A_BIST_EN           Positive Clock Edge         Positive         Input         BIST Enable pin 
+A_DOUT[15:0]        Positive Clock Edge         Positive         Output        16 data bits, no high impedance function   
+A_DLY               Level                       Positive         Input         Delay setting, adjustment of memory internal timings; recommended setting: Tie to 1
+
+VDD                                                                            Macro support logic supply voltage
+VSS                                                                            Macro support logic ground
+VDDARRAY                                                                       Memory array supply voltage
+----------------------------------------------------------------------------------------------------------------------------------------------------------
+
+
+
+
+###########################
+Operation Tables
+###########################
+
+
+When A_BIST_EN is disabled A_ADDR is used as address input.
+When A_BIST_EN is enabled A_BIST_ADDR is used as address input.
+
+! Note: One cycle before and after A_BIST_EN changes no read, write, or write-through operation is allowed.
+- Set A_MEN and A_BIST_MEN to 0.
+
+A_BIST_EN       A_MEN         A_REN         A_WEN           Operation on Memory
+---------       -----         -----         -----           ----------------------
+    0             0           0 / 1         0 / 1           No Operation
+    0             1             0             0             No Operation
+    0             1             1             0             Read
+    0             1             0             1             Write
+    0             1             1             1             Write-Through
+    1           0 / 1         0 / 1         0 / 1           No Operation
+
+A_BIST_EN    A_BIST_MEN     A_BIST_REN     A_BIST_WEN       Operation on Memory
+---------    ----------     ----------     ----------       ----------------------
+    1             0           0 / 1          0 / 1          No Operation
+    1             1             0              0            No Operation
+    1             1             1              0            Read
+    1             1             0              1            Write
+    1             1             1              1            Write-Through
+    0           0 / 1         0 / 1          0 / 1          No Operation
+
+
+
+
+###########################
+Timing Diagrams
+###########################
+
+
+All timings are identical for BIST mode.
+
+
+                                WRITE                              READ                            WRITE-THROUGH                    NO OPERATION
+
+                                  |-----T_CKH----->|
+     ___________                  | ______________ |                 | _______________                   _______________                  _____________
+ A_CLK          \                 |/              \|                 |/               \                 /               \                /
+                 \_______________/|                |\_______________/|                 \_______________/                 \______________/
+                      |           |                                  |                         |
+                      |<-Tsetup---|                                  |-------T_CLK2DOUT------->|
+     ________________ | __________|__________|___________  _________________________________  _|_______________________________________________________
+ A_ADDR      A_ADDR0 \|/          |          |  A_ADDR1  \/       A_ADDR2                   \/ |        A_ADDR3
+     ________________/|\__________|_________ |___________/\_________________________________/\_|_______________________________________________________
+                      |           |          |                                                 |
+                      |           |---Thold->|                                                 |
+     ________________ | __________|__________|___________  _________________________________  _|_______________________________________________________
+ A_DIN               \|/          |          |  A_D1     \/       don't care                \/ |        A_D3
+     ________________/|\__________|__________|___________/\_________________________________/\_|_______________________________________________________
+                      |           |          |                                                 |
+                      | __________|__________|_________________________________________________|______________________
+ A_MEN                |/          |          |                                                 |                      \
+     ________________/|           |          |                                                 |                       \_______________________________
+                      |           |          |                                                 |
+                      | __________|_________ |                                               __|______________________
+ A_WEN                |/          |         \|                                              /  |                      \
+     ________________/|           |          |\____________________________________________/   |                       \_______________________________
+                      |           |          |                                                 |
+                      |           |          |            _____________________________________|______________________
+ A_REN                |           |          |           /                                     |                      \
+     _________________|___________|__________|__________/                                      |                       \_______________________________
+                      |           |          |                                                 |
+     _________________________________________________________________________________________ | ____________________________________  ________________
+ A_DOUT                            'X'                                                        \|/         MEMORY(A_ADDR2)            \/    A_D3
+     _________________________________________________________________________________________/|\____________________________________/\________________
+                                                                                               |
+     ________________________________________________  __________________________________________________________________________  ____________________
+ A_MEMORY                          'X'               \/          MEMORY(A_ADDR1)=A_D1                                            \/MEMORY(A_ADDR3)=A_D3
+     ________________________________________________/\__________________________________________________________________________/\____________________
+
+
+
+	
+
+
+###########################
+Operating Conditions
+###########################
+
+
++-------------+----------------------+-----------+------+------+-------+
+| Symbol      | Parameter            | Condition | Min  | Max  | Units |
++-------------+----------------------+-----------+------+------+-------+
+| VDD         | Supply Voltage Range | Operating | 1.08 | 1.32 | V     |
+| Temperature |                      | Operating | -55  | 125  | �C    |
+| tCKH        | Min Pulse Width      | Operating | 0.12 | 0.4  | ns    |
++-------------+----------------------+-----------+------+------+-------+
+
+
+
+###########################
+Characterization Corners
+###########################
+
+
++--------------------------+--------------+-----------+-------------+------------------+
+| Operating Condition Name | Model Corner | Condition | Voltage [V] | Temperature [�C] |
++--------------------------+--------------+-----------+-------------+------------------+
+| wc_1d08V_125C            | wc           | working   | 1.08        | 125              |
+| bc_1d32V_m55C            | bc           | working   | 1.32        | -55              |
+| tc_1d20V_25C             | tc           | working   | 1.20        | 25               |
++--------------------------+--------------+-----------+-------------+------------------+
+
+
+
+###########################
+Timing Characteristics
+###########################
+
+
++-------------------+-------------+-----------+---------------+---------------+--------------+-------+
+| Timing            | Timing Type | Direction | wc_1d08V_125C | bc_1d32V_m55C | tc_1d20V_25C | Units |
++-------------------+-------------+-----------+---------------+---------------+--------------+-------+
+| Clock to Data Out | Delay       | Rising    | 8.95e+00      | 3.31e+00      | 5.37e+00     | ns    |
+| Clock to Data Out | Delay       | Falling   | 8.83e+00      | 3.27e+00      | 5.31e+00     | ns    |
+| Data Out          | Transition  | Rising    | 4.08e-02      | 1.62e-02      | 2.59e-02     | ns    |
+| Data Out          | Transition  | Falling   | 3.29e-02      | 1.35e-02      | 2.01e-02     | ns    |
++-------------------+-------------+-----------+---------------+---------------+--------------+-------+
+
+
+
+###########################
+Power Characteristics
+###########################
+
+
+Typical Power Unit : 1e-12 * J/toggle = 1 * uW/MHz
+                            (capacitive_load_unit * voltage_unit^2) per toggle event
+------------------------------------------------------------------------------------------
++---------------------+---------------+---------------+--------------+------------+
+| Power               | wc_1d08V_125C | bc_1d32V_m55C | tc_1d20V_25C | Units      |
++---------------------+---------------+---------------+--------------+------------+
+| Leakage Power       | 5.226e+03     | 1.878e+03     | 7.921e+02    | 1nW        |
+| Total Typical Power | 5.683e+01     | 8.983e+01     | 7.317e+01    | 1 * uW/MHz |
++---------------------+---------------+---------------+--------------+------------+
+
+
+
+#################
+Physical Layout
+#################
+
+
+Metal usage is up to M4. 
+The bottom figure shows the physical layout of the 4096x16_c3 SRAM hard macro with its dimensions.
+Note: Row decoder and interface pin locations as well as location, dimension and number of power rails are approximated.
+
+                                                  416.64 microns
+         <-------------------------------------------------------------------------------------------------------->
+          _________________________________________________________________________________________________________
+       ^ |VDD|    |VDD|     |VDD|     |VDD|      |        |VDD|VDD|        |      |VDD|    |VDD|     |VDD|    |VDD|  ^
+       | |VSS|    |VSS|     |VSS|     |VSS|      |        |VSS|VSS|        |      |VSS|    |VSS|     |VSS|    |VSS|  |
+       | |   |    |   |     |   |     |   |      |        |   |   |        |      |   |    |   |     |   |    |   |  |
+       | |PWR|    |ARR|     |PWR|     |ARR|      | L      |PWR|PWR|      R |      |ARR|    |PWR|     |ARR|    |PWR|  |
+       | |   |    |AY |     |   |     |AY |      |  E     |   |   |     I  |      | YA|    |   |     | YA|    |   |  |
+       | |   |    |   |     |   |     |   |      |   F    |   |   |    G   |      |   |    |   |     |   |    |   |  |
+       | |   |    |PWR|     |   |     |PWR|      |    T   |   |   |   H    |      |PWR|    |   |     |PWR|    |   |  |
+       | |   |    |   |     |   |     |   |      |        |   |   |  T     |      |   |    |   |     |   |    |   |  |
+SRAM   | |   |    |   |     |   |     |   |      |  R     |   |   |     R  |      |   |    |   |     |   |    |   |  |
+Array  | |   |    |   |     |   |     |   |      |   O    |   |   |    O   |      |   |    |   |     |   |    |   |  |618.3 microns
+       | |S  |    |S  |     |S  |     |S  |      |    W   |S  |  S|   W    |      |  S|    |  S|	 |  S|    |  S|  |
+       | | T |    | T |     | T |     | T |      |  D     | T | T |     D  |      | T |    | T |	 | T |    | T |  |
+       | |  R|    |  R|     |  R|     |  R|      |   E    |  R|R  |    E   |      |R  |    |R  |	 |R  |    |R  |  |
+       | | I |    | I |     | I |     | I |      |    C   | I | I |   C    |      | I |    | I |	 | I |    | I |  |
+       | |P  |    |P  |     |P  |     |P  |      |        |P  |  P|        |      |  P|    |  P|	 |  P|    |  P|  |
+       | | E |    | E |     | E |     | E |      |        | E | E |        |      | E |    | E |	 | E |    | E |  |
+       v |__S|____|__S|_____|__S|_____|__S|______|________|__S|S__|________|______|S__|____|S__|_____|S__|____|S__|  |
+       ^ |   |              |   |                |        |   |   |        |               |   |              |   |  |
+       | |___|     ___      |___|      ___       |        |___|___|        |       ___     |___|      ___     |___|  |
+Inter- | |VDD|    |VDD|     |VDD|     |VDD|      |        |VDD|VDD|        |      |VDD|    |VDD|     |VDD|    |VDD|  |
+face   | |VSS|    |VSS|     |VSS|     |VSS|      |        |VSS|VSS|        |      |VSS|    |VSS|     |VSS|    |VSS|  |
+Pins   v |___|____|___|_____|___|_____|___|______|________|___|___|________|______|___|____|___|_____|___|____|___|  v
+
+
+
+Address calculation for BIST_ADDR in BIST modeare identical to ADDR as seen below.
+
+The SRAM macro is physically organized in 2 x 64 horizontal x 4096 vertical bit cells:
+ - Row address pins (MSB..LSB)     : 9;           ya[8:0]     = ADDR[12:3]        
+ - Column address pins (MSB..LSB)  : 3;           xa[2:0]     = ADDR[2:0]         
+ - Data pins (MSB..LSB)            : 16;          xa[15:0]    = DIN[15:0], DOUT[15:0].
+
+The scrambling scheme reads as follows:
+ - X-Address Scrambling: xa[i] = x[i]
+ - Y-Address Scrambling: ya[j] = not(y[j])
+
+Translation from physical (x,y,d) to topological (x,y) addresses:
+  x_topo = f(x_physical, y_physical, d) =
+                    if (d<12)      {d*32+31-x}    
+                    else           {d*32+x}  
+
+  y_topo = f(x_physical, y_physical, d) = y
+
+Note: The left and right sub-arrays are mirrored with respect to the y axis.
+
+Symbol definition:
+xa[0..n], ya[0..m]: externally applied device addresses
+
+x[0..n], y[0..m]:   internal physical addresses (address complete memory words)
+
+x_topo, y_topo:     internal topological addresses (address single bit cells)
+
diff --git a/ihp-sg13g2/libs.ref/sg13g2_sram/doc/RM_IHPSG13_1P_4096x8_c3_bm_bist.txt b/ihp-sg13g2/libs.ref/sg13g2_sram/doc/RM_IHPSG13_1P_4096x8_c3_bm_bist.txt
new file mode 100644
index 00000000..6e5d669b
--- /dev/null
+++ b/ihp-sg13g2/libs.ref/sg13g2_sram/doc/RM_IHPSG13_1P_4096x8_c3_bm_bist.txt
@@ -0,0 +1,317 @@
+# ------------------------------------------------------
+#
+#		Copyright 2024 IHP PDK Authors
+#
+#		Licensed under the Apache License, Version 2.0 (the "License");
+#		you may not use this file except in compliance with the License.
+#		You may obtain a copy of the License at
+#		
+#		   https://www.apache.org/licenses/LICENSE-2.0
+#		
+#		Unless required by applicable law or agreed to in writing, software
+#		distributed under the License is distributed on an "AS IS" BASIS,
+#		WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#		See the License for the specific language governing permissions and
+#		limitations under the License.
+#		
+#		Generated on Fri Jul 19 08:59:22 2024		
+#				
+# ------------------------------------------------------ 
+
+
+#################
+D A T A S H E E T
+#################
+
+
+Name             : RM_IHPSG13_1P_4096x8_c3_bm_bist
+Size             : 4096 words x 8 bits
+Column Mux       : 3
+Number of Ports  : 1
+Area (h x w)     : 618.30 x 236.80 = 146413.44 square microns
+
+
+##################
+Introduction
+##################
+
+
+This 1-port macro has a one-cycle data-access.
+For timing information overview have a look at the timing diagrams in the "Timing Diagrams" section below.
+
+
+##################
+Schematic View
+##################
+
+
+                    ________________________________________
+                   |                                        |
+                   |                                        |
+                ---|A_DIN[7:0]                              |
+                ---|A_BM[7:0]                               |
+                ---|A_ADDR[11:0]                            |
+                ---|A_MEN                                   |
+                ---|A_REN                                   |
+                ---|A_WEN                                   |
+                ---|A_CLK                                   |
+                   |                                        |
+                ---|A_BIST_DIN[7:0]                         |
+                ---|A_BIST_BM[7:0]                          |
+                ---|A_BIST_ADDR[11:0]                       |
+                ---|A_BIST_MEN                              |
+                ---|A_BIST_REN                              |
+                ---|A_BIST_WEN                              |
+                ---|A_BIST_CLK                              |
+                   |                                        |
+                ---|A_BIST_EN                               |
+                   |                                        |
+                ---|A_DLY                                   |
+                   |                                        |
+                   |                             A_DOUT[7:0]|---
+                   |                                        |
+                   |________________________________________|
+
+
+###########################
+Macro Interface Signal List
+###########################
+
+
+Signal              Sensitivity                 Logic            Direction     Description
+------              -----------                 -----            ---------     -----------
+A_ADDR[11:0]        Positive Clock Edge         Positive         Input         12 address bits  
+A_DIN[7:0]          Positive Clock Edge         Positive         Input         8 data bits 
+A_BM[7:0]           Positive Clock Edge         Positive         Input         8 bit mask bits   
+A_WEN               Positive Clock Edge         Positive         Input         Write-enable  
+A_MEN               Positive Clock Edge         Positive         Input         Memory enable -> if disabled, the memory is deactivated   
+A_REN               Positive Clock Edge         Positive         Input         Read enable 
+A_CLK               Clock                       Positive         Input         Clock pin   
+A_BIST_DIN[7:0]     Positive Clock Edge         Positive         Input         8 data bits 
+A_BIST_BM[7:0]      Positive Clock Edge         Positive         Input         8 bit mask bits   
+A_BIST_ADDR[11:0]   Positive Clock Edge         Positive         Input         12 address bits for BIST mode  
+A_BIST_WEN          Positive Clock Edge         Positive         Input         BIST Write-enable   
+A_BIST_MEN          Positive Clock Edge         Positive         Input         BIST Memory enable -> if disabled, the memory is deactivated  
+A_BIST_REN          Positive Clock Edge         Positive         Input         BIST Read enable  
+A_BIST_CLK          Clock                       Positive         Input         BIST Clock pin  
+A_BIST_EN           Positive Clock Edge         Positive         Input         BIST Enable pin 
+A_DOUT[7:0]         Positive Clock Edge         Positive         Output        8 data bits, no high impedance function   
+A_DLY               Level                       Positive         Input         Delay setting, adjustment of memory internal timings; recommended setting: Tie to 1
+
+VDD                                                                            Macro support logic supply voltage
+VSS                                                                            Macro support logic ground
+VDDARRAY                                                                       Memory array supply voltage
+----------------------------------------------------------------------------------------------------------------------------------------------------------
+
+
+
+
+###########################
+Operation Tables
+###########################
+
+
+When A_BIST_EN is disabled A_ADDR is used as address input.
+When A_BIST_EN is enabled A_BIST_ADDR is used as address input.
+
+! Note: One cycle before and after A_BIST_EN changes no read, write, or write-through operation is allowed.
+- Set A_MEN and A_BIST_MEN to 0.
+
+A_BIST_EN       A_MEN         A_REN         A_WEN           Operation on Memory
+---------       -----         -----         -----           ----------------------
+    0             0           0 / 1         0 / 1           No Operation
+    0             1             0             0             No Operation
+    0             1             1             0             Read
+    0             1             0             1             Write
+    0             1             1             1             Write-Through
+    1           0 / 1         0 / 1         0 / 1           No Operation
+
+A_BIST_EN    A_BIST_MEN     A_BIST_REN     A_BIST_WEN       Operation on Memory
+---------    ----------     ----------     ----------       ----------------------
+    1             0           0 / 1          0 / 1          No Operation
+    1             1             0              0            No Operation
+    1             1             1              0            Read
+    1             1             0              1            Write
+    1             1             1              1            Write-Through
+    0           0 / 1         0 / 1          0 / 1          No Operation
+
+
+
+
+###########################
+Timing Diagrams
+###########################
+
+
+All timings are identical for BIST mode.
+
+
+                                WRITE                              READ                            WRITE-THROUGH                    NO OPERATION
+
+                                  |-----T_CKH----->|
+     ___________                  | ______________ |                 | _______________                   _______________                  _____________
+ A_CLK          \                 |/              \|                 |/               \                 /               \                /
+                 \_______________/|                |\_______________/|                 \_______________/                 \______________/
+                      |           |                                  |                         |
+                      |<-Tsetup---|                                  |-------T_CLK2DOUT------->|
+     ________________ | __________|__________|___________  _________________________________  _|_______________________________________________________
+ A_ADDR      A_ADDR0 \|/          |          |  A_ADDR1  \/       A_ADDR2                   \/ |        A_ADDR3
+     ________________/|\__________|_________ |___________/\_________________________________/\_|_______________________________________________________
+                      |           |          |                                                 |
+                      |           |---Thold->|                                                 |
+     ________________ | __________|__________|___________  _________________________________  _|_______________________________________________________
+ A_DIN               \|/          |          |  A_D1     \/       don't care                \/ |        A_D3
+     ________________/|\__________|__________|___________/\_________________________________/\_|_______________________________________________________
+                      |           |          |                                                 |
+                      | __________|__________|_________________________________________________|______________________
+ A_MEN                |/          |          |                                                 |                      \
+     ________________/|           |          |                                                 |                       \_______________________________
+                      |           |          |                                                 |
+                      | __________|_________ |                                               __|______________________
+ A_WEN                |/          |         \|                                              /  |                      \
+     ________________/|           |          |\____________________________________________/   |                       \_______________________________
+                      |           |          |                                                 |
+                      |           |          |            _____________________________________|______________________
+ A_REN                |           |          |           /                                     |                      \
+     _________________|___________|__________|__________/                                      |                       \_______________________________
+                      |           |          |                                                 |
+     _________________________________________________________________________________________ | ____________________________________  ________________
+ A_DOUT                            'X'                                                        \|/         MEMORY(A_ADDR2)            \/    A_D3
+     _________________________________________________________________________________________/|\____________________________________/\________________
+                                                                                               |
+     ________________________________________________  __________________________________________________________________________  ____________________
+ A_MEMORY                          'X'               \/          MEMORY(A_ADDR1)=A_D1                                            \/MEMORY(A_ADDR3)=A_D3
+     ________________________________________________/\__________________________________________________________________________/\____________________
+
+
+
+	
+
+
+###########################
+Operating Conditions
+###########################
+
+
++-------------+----------------------+-----------+------+------+-------+
+| Symbol      | Parameter            | Condition | Min  | Max  | Units |
++-------------+----------------------+-----------+------+------+-------+
+| VDD         | Supply Voltage Range | Operating | 1.08 | 1.32 | V     |
+| Temperature |                      | Operating | -55  | 125  | �C    |
+| tCKH        | Min Pulse Width      | Operating | 0.12 | 0.4  | ns    |
++-------------+----------------------+-----------+------+------+-------+
+
+
+
+###########################
+Characterization Corners
+###########################
+
+
++--------------------------+--------------+-----------+-------------+------------------+
+| Operating Condition Name | Model Corner | Condition | Voltage [V] | Temperature [�C] |
++--------------------------+--------------+-----------+-------------+------------------+
+| wc_1d08V_125C            | wc           | working   | 1.08        | 125              |
+| bc_1d32V_m55C            | bc           | working   | 1.32        | -55              |
+| tc_1d20V_25C             | tc           | working   | 1.20        | 25               |
++--------------------------+--------------+-----------+-------------+------------------+
+
+
+
+###########################
+Timing Characteristics
+###########################
+
+
++-------------------+-------------+-----------+---------------+---------------+--------------+-------+
+| Timing            | Timing Type | Direction | wc_1d08V_125C | bc_1d32V_m55C | tc_1d20V_25C | Units |
++-------------------+-------------+-----------+---------------+---------------+--------------+-------+
+| Clock to Data Out | Delay       | Rising    | 8.86e+00      | 3.28e+00      | 5.32e+00     | ns    |
+| Clock to Data Out | Delay       | Falling   | 8.75e+00      | 3.24e+00      | 5.25e+00     | ns    |
+| Data Out          | Transition  | Rising    | 4.08e-02      | 1.62e-02      | 2.59e-02     | ns    |
+| Data Out          | Transition  | Falling   | 3.29e-02      | 1.35e-02      | 2.01e-02     | ns    |
++-------------------+-------------+-----------+---------------+---------------+--------------+-------+
+
+
+
+###########################
+Power Characteristics
+###########################
+
+
+Typical Power Unit : 1e-12 * J/toggle = 1 * uW/MHz
+                            (capacitive_load_unit * voltage_unit^2) per toggle event
+------------------------------------------------------------------------------------------
++---------------------+---------------+---------------+--------------+------------+
+| Power               | wc_1d08V_125C | bc_1d32V_m55C | tc_1d20V_25C | Units      |
++---------------------+---------------+---------------+--------------+------------+
+| Leakage Power       | 2.613e+03     | 9.392e+02     | 3.960e+02    | 1nW        |
+| Total Typical Power | 3.225e+01     | 5.081e+01     | 4.110e+01    | 1 * uW/MHz |
++---------------------+---------------+---------------+--------------+------------+
+
+
+
+#################
+Physical Layout
+#################
+
+
+Metal usage is up to M4. 
+The bottom figure shows the physical layout of the 4096x8_c3 SRAM hard macro with its dimensions.
+Note: Row decoder and interface pin locations as well as location, dimension and number of power rails are approximated.
+
+                                                  236.8 microns
+         <-------------------------------------------------------------------------------------------------------->
+          _________________________________________________________________________________________________________
+       ^ |VDD|    |VDD|     |VDD|     |VDD|      |        |VDD|VDD|        |      |VDD|    |VDD|     |VDD|    |VDD|  ^
+       | |VSS|    |VSS|     |VSS|     |VSS|      |        |VSS|VSS|        |      |VSS|    |VSS|     |VSS|    |VSS|  |
+       | |   |    |   |     |   |     |   |      |        |   |   |        |      |   |    |   |     |   |    |   |  |
+       | |PWR|    |ARR|     |PWR|     |ARR|      | L      |PWR|PWR|      R |      |ARR|    |PWR|     |ARR|    |PWR|  |
+       | |   |    |AY |     |   |     |AY |      |  E     |   |   |     I  |      | YA|    |   |     | YA|    |   |  |
+       | |   |    |   |     |   |     |   |      |   F    |   |   |    G   |      |   |    |   |     |   |    |   |  |
+       | |   |    |PWR|     |   |     |PWR|      |    T   |   |   |   H    |      |PWR|    |   |     |PWR|    |   |  |
+       | |   |    |   |     |   |     |   |      |        |   |   |  T     |      |   |    |   |     |   |    |   |  |
+SRAM   | |   |    |   |     |   |     |   |      |  R     |   |   |     R  |      |   |    |   |     |   |    |   |  |
+Array  | |   |    |   |     |   |     |   |      |   O    |   |   |    O   |      |   |    |   |     |   |    |   |  |618.3 microns
+       | |S  |    |S  |     |S  |     |S  |      |    W   |S  |  S|   W    |      |  S|    |  S|	 |  S|    |  S|  |
+       | | T |    | T |     | T |     | T |      |  D     | T | T |     D  |      | T |    | T |	 | T |    | T |  |
+       | |  R|    |  R|     |  R|     |  R|      |   E    |  R|R  |    E   |      |R  |    |R  |	 |R  |    |R  |  |
+       | | I |    | I |     | I |     | I |      |    C   | I | I |   C    |      | I |    | I |	 | I |    | I |  |
+       | |P  |    |P  |     |P  |     |P  |      |        |P  |  P|        |      |  P|    |  P|	 |  P|    |  P|  |
+       | | E |    | E |     | E |     | E |      |        | E | E |        |      | E |    | E |	 | E |    | E |  |
+       v |__S|____|__S|_____|__S|_____|__S|______|________|__S|S__|________|______|S__|____|S__|_____|S__|____|S__|  |
+       ^ |   |              |   |                |        |   |   |        |               |   |              |   |  |
+       | |___|     ___      |___|      ___       |        |___|___|        |       ___     |___|      ___     |___|  |
+Inter- | |VDD|    |VDD|     |VDD|     |VDD|      |        |VDD|VDD|        |      |VDD|    |VDD|     |VDD|    |VDD|  |
+face   | |VSS|    |VSS|     |VSS|     |VSS|      |        |VSS|VSS|        |      |VSS|    |VSS|     |VSS|    |VSS|  |
+Pins   v |___|____|___|_____|___|_____|___|______|________|___|___|________|______|___|____|___|_____|___|____|___|  v
+
+
+
+Address calculation for BIST_ADDR in BIST modeare identical to ADDR as seen below.
+
+The SRAM macro is physically organized in 2 x 32 horizontal x 4096 vertical bit cells:
+ - Row address pins (MSB..LSB)     : 9;           ya[8:0]     = ADDR[12:3]        
+ - Column address pins (MSB..LSB)  : 3;           xa[2:0]     = ADDR[2:0]         
+ - Data pins (MSB..LSB)            : 8;           xa[7:0]     = DIN[7:0], DOUT[7:0].
+
+The scrambling scheme reads as follows:
+ - X-Address Scrambling: xa[i] = x[i]
+ - Y-Address Scrambling: ya[j] = not(y[j])
+
+Translation from physical (x,y,d) to topological (x,y) addresses:
+  x_topo = f(x_physical, y_physical, d) =
+                    if (d<12)      {d*32+31-x}    
+                    else           {d*32+x}  
+
+  y_topo = f(x_physical, y_physical, d) = y
+
+Note: The left and right sub-arrays are mirrored with respect to the y axis.
+
+Symbol definition:
+xa[0..n], ya[0..m]: externally applied device addresses
+
+x[0..n], y[0..m]:   internal physical addresses (address complete memory words)
+
+x_topo, y_topo:     internal topological addresses (address single bit cells)
+
diff --git a/ihp-sg13g2/libs.ref/sg13g2_sram/gds/RM_IHPSG13_1P_1024x16_c2_bm_bist.gds b/ihp-sg13g2/libs.ref/sg13g2_sram/gds/RM_IHPSG13_1P_1024x16_c2_bm_bist.gds
new file mode 100644
index 00000000..67c00161
Binary files /dev/null and b/ihp-sg13g2/libs.ref/sg13g2_sram/gds/RM_IHPSG13_1P_1024x16_c2_bm_bist.gds differ
diff --git a/ihp-sg13g2/libs.ref/sg13g2_sram/gds/RM_IHPSG13_1P_1024x8_c2_bm_bist.gds b/ihp-sg13g2/libs.ref/sg13g2_sram/gds/RM_IHPSG13_1P_1024x8_c2_bm_bist.gds
new file mode 100644
index 00000000..7aca9b13
Binary files /dev/null and b/ihp-sg13g2/libs.ref/sg13g2_sram/gds/RM_IHPSG13_1P_1024x8_c2_bm_bist.gds differ
diff --git a/ihp-sg13g2/libs.ref/sg13g2_sram/gds/RM_IHPSG13_1P_4096x16_c3_bm_bist.gds b/ihp-sg13g2/libs.ref/sg13g2_sram/gds/RM_IHPSG13_1P_4096x16_c3_bm_bist.gds
new file mode 100644
index 00000000..ee71dbb2
Binary files /dev/null and b/ihp-sg13g2/libs.ref/sg13g2_sram/gds/RM_IHPSG13_1P_4096x16_c3_bm_bist.gds differ
diff --git a/ihp-sg13g2/libs.ref/sg13g2_sram/gds/RM_IHPSG13_1P_4096x8_c3_bm_bist.gds b/ihp-sg13g2/libs.ref/sg13g2_sram/gds/RM_IHPSG13_1P_4096x8_c3_bm_bist.gds
new file mode 100644
index 00000000..41536515
Binary files /dev/null and b/ihp-sg13g2/libs.ref/sg13g2_sram/gds/RM_IHPSG13_1P_4096x8_c3_bm_bist.gds differ
diff --git a/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_1024x16_c2_bm_bist.lef b/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_1024x16_c2_bm_bist.lef
new file mode 100644
index 00000000..fa8827f6
--- /dev/null
+++ b/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_1024x16_c2_bm_bist.lef
@@ -0,0 +1,2468 @@
+# ------------------------------------------------------
+#
+#		Copyright 2024 IHP PDK Authors
+#
+#		Licensed under the Apache License, Version 2.0 (the "License");
+#		you may not use this file except in compliance with the License.
+#		You may obtain a copy of the License at
+#		
+#		   https://www.apache.org/licenses/LICENSE-2.0
+#		
+#		Unless required by applicable law or agreed to in writing, software
+#		distributed under the License is distributed on an "AS IS" BASIS,
+#		WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#		See the License for the specific language governing permissions and
+#		limitations under the License.
+#		
+#		Generated on Fri Jul 19 08:58:12 2024		
+#
+# ------------------------------------------------------ 
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+
+MACRO RM_IHPSG13_1P_1024x16_c2_bm_bist
+  CLASS BLOCK ;
+  ORIGIN 0 0 ;
+  FOREIGN RM_IHPSG13_1P_1024x16_c2_bm_bist 0 0 ;
+  SIZE 236.8 BY 336.46 ;
+  SYMMETRY X Y R90 ;
+  PIN A_DIN[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 154.57 0 154.83 0.26 ;
+    END
+  END A_DIN[8]
+  PIN A_DIN[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 81.97 0 82.23 0.26 ;
+    END
+  END A_DIN[7]
+  PIN A_BIST_DIN[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 153.715 0 153.975 0.26 ;
+    END
+  END A_BIST_DIN[8]
+  PIN A_BIST_DIN[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 82.825 0 83.085 0.26 ;
+    END
+  END A_BIST_DIN[7]
+  PIN A_BM[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 146.73 0 146.99 0.26 ;
+    END
+  END A_BM[8]
+  PIN A_BM[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 89.81 0 90.07 0.26 ;
+    END
+  END A_BM[7]
+  PIN A_BIST_BM[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 148.105 0 148.365 0.26 ;
+    END
+  END A_BIST_BM[8]
+  PIN A_BIST_BM[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 88.435 0 88.695 0.26 ;
+    END
+  END A_BIST_BM[7]
+  PIN A_DOUT[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 147.24 0 147.5 0.26 ;
+    END
+  END A_DOUT[8]
+  PIN A_DOUT[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 89.3 0 89.56 0.26 ;
+    END
+  END A_DOUT[7]
+  PIN VSS!
+    DIRECTION INOUT ;
+    USE GROUND ;
+    NETEXPR "vss VSS!" ;
+    PORT
+      LAYER Metal4 ;
+        RECT 224.11 0 226.92 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 212.87 0 215.68 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 201.63 0 204.44 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 190.39 0 193.2 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 179.15 0 181.96 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 167.91 0 170.72 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 156.67 0 159.48 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 145.43 0 148.24 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 135.02 0 137.83 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 124.72 0 127.53 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 109.27 0 112.08 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 98.97 0 101.78 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 88.56 0 91.37 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 77.32 0 80.13 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 66.08 0 68.89 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 54.84 0 57.65 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 43.6 0 46.41 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 32.36 0 35.17 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 21.12 0 23.93 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 9.88 0 12.69 336.46 ;
+    END
+  END VSS!
+  PIN VDD!
+    DIRECTION INOUT ;
+    USE POWER ;
+    NETEXPR "vdd VDD!" ;
+    PORT
+      LAYER Metal4 ;
+        RECT 229.73 0 232.54 38.825 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 218.49 0 221.3 38.825 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 207.25 0 210.06 38.825 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 196.01 0 198.82 38.825 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 184.77 0 187.58 38.825 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 173.53 0 176.34 38.825 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 162.29 0 165.1 38.825 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 151.05 0 153.86 38.825 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 129.87 0 132.68 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 119.57 0 122.38 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 114.42 0 117.23 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 104.12 0 106.93 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 82.94 0 85.75 38.825 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 71.7 0 74.51 38.825 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 60.46 0 63.27 38.825 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 49.22 0 52.03 38.825 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 37.98 0 40.79 38.825 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 26.74 0 29.55 38.825 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 15.5 0 18.31 38.825 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 4.26 0 7.07 38.825 ;
+    END
+  END VDD!
+  PIN VDDARRAY!
+    DIRECTION INOUT ;
+    USE POWER ;
+    NETEXPR "vddarray VDDARRAY!" ;
+    PORT
+      LAYER Metal4 ;
+        RECT 229.73 45.465 232.54 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 218.49 45.465 221.3 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 207.25 45.465 210.06 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 196.01 45.465 198.82 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 184.77 45.465 187.58 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 173.53 45.465 176.34 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 162.29 45.465 165.1 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 151.05 45.465 153.86 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 82.94 45.465 85.75 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 71.7 45.465 74.51 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 60.46 45.465 63.27 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 49.22 45.465 52.03 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 37.98 45.465 40.79 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 26.74 45.465 29.55 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 15.5 45.465 18.31 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 4.26 45.465 7.07 336.46 ;
+    END
+  END VDDARRAY!
+  PIN A_DIN[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 165.81 0 166.07 0.26 ;
+    END
+  END A_DIN[9]
+  PIN A_DIN[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 70.73 0 70.99 0.26 ;
+    END
+  END A_DIN[6]
+  PIN A_BIST_DIN[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 164.955 0 165.215 0.26 ;
+    END
+  END A_BIST_DIN[9]
+  PIN A_BIST_DIN[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 71.585 0 71.845 0.26 ;
+    END
+  END A_BIST_DIN[6]
+  PIN A_BM[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 157.97 0 158.23 0.26 ;
+    END
+  END A_BM[9]
+  PIN A_BM[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 78.57 0 78.83 0.26 ;
+    END
+  END A_BM[6]
+  PIN A_BIST_BM[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 159.345 0 159.605 0.26 ;
+    END
+  END A_BIST_BM[9]
+  PIN A_BIST_BM[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 77.195 0 77.455 0.26 ;
+    END
+  END A_BIST_BM[6]
+  PIN A_DOUT[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 158.48 0 158.74 0.26 ;
+    END
+  END A_DOUT[9]
+  PIN A_DOUT[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 78.06 0 78.32 0.26 ;
+    END
+  END A_DOUT[6]
+  PIN A_DIN[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 177.05 0 177.31 0.26 ;
+    END
+  END A_DIN[10]
+  PIN A_DIN[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 59.49 0 59.75 0.26 ;
+    END
+  END A_DIN[5]
+  PIN A_BIST_DIN[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 176.195 0 176.455 0.26 ;
+    END
+  END A_BIST_DIN[10]
+  PIN A_BIST_DIN[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 60.345 0 60.605 0.26 ;
+    END
+  END A_BIST_DIN[5]
+  PIN A_BM[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 169.21 0 169.47 0.26 ;
+    END
+  END A_BM[10]
+  PIN A_BM[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 67.33 0 67.59 0.26 ;
+    END
+  END A_BM[5]
+  PIN A_BIST_BM[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 170.585 0 170.845 0.26 ;
+    END
+  END A_BIST_BM[10]
+  PIN A_BIST_BM[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 65.955 0 66.215 0.26 ;
+    END
+  END A_BIST_BM[5]
+  PIN A_DOUT[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 169.72 0 169.98 0.26 ;
+    END
+  END A_DOUT[10]
+  PIN A_DOUT[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 66.82 0 67.08 0.26 ;
+    END
+  END A_DOUT[5]
+  PIN A_DIN[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 188.29 0 188.55 0.26 ;
+    END
+  END A_DIN[11]
+  PIN A_DIN[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 48.25 0 48.51 0.26 ;
+    END
+  END A_DIN[4]
+  PIN A_BIST_DIN[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 187.435 0 187.695 0.26 ;
+    END
+  END A_BIST_DIN[11]
+  PIN A_BIST_DIN[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 49.105 0 49.365 0.26 ;
+    END
+  END A_BIST_DIN[4]
+  PIN A_BM[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 180.45 0 180.71 0.26 ;
+    END
+  END A_BM[11]
+  PIN A_BM[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 56.09 0 56.35 0.26 ;
+    END
+  END A_BM[4]
+  PIN A_BIST_BM[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 181.825 0 182.085 0.26 ;
+    END
+  END A_BIST_BM[11]
+  PIN A_BIST_BM[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 54.715 0 54.975 0.26 ;
+    END
+  END A_BIST_BM[4]
+  PIN A_DOUT[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 180.96 0 181.22 0.26 ;
+    END
+  END A_DOUT[11]
+  PIN A_DOUT[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 55.58 0 55.84 0.26 ;
+    END
+  END A_DOUT[4]
+  PIN A_DIN[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 199.53 0 199.79 0.26 ;
+    END
+  END A_DIN[12]
+  PIN A_DIN[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 37.01 0 37.27 0.26 ;
+    END
+  END A_DIN[3]
+  PIN A_BIST_DIN[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 198.675 0 198.935 0.26 ;
+    END
+  END A_BIST_DIN[12]
+  PIN A_BIST_DIN[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 37.865 0 38.125 0.26 ;
+    END
+  END A_BIST_DIN[3]
+  PIN A_BM[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 191.69 0 191.95 0.26 ;
+    END
+  END A_BM[12]
+  PIN A_BM[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 44.85 0 45.11 0.26 ;
+    END
+  END A_BM[3]
+  PIN A_BIST_BM[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 193.065 0 193.325 0.26 ;
+    END
+  END A_BIST_BM[12]
+  PIN A_BIST_BM[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 43.475 0 43.735 0.26 ;
+    END
+  END A_BIST_BM[3]
+  PIN A_DOUT[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 192.2 0 192.46 0.26 ;
+    END
+  END A_DOUT[12]
+  PIN A_DOUT[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 44.34 0 44.6 0.26 ;
+    END
+  END A_DOUT[3]
+  PIN A_DIN[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 210.77 0 211.03 0.26 ;
+    END
+  END A_DIN[13]
+  PIN A_DIN[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 25.77 0 26.03 0.26 ;
+    END
+  END A_DIN[2]
+  PIN A_BIST_DIN[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 209.915 0 210.175 0.26 ;
+    END
+  END A_BIST_DIN[13]
+  PIN A_BIST_DIN[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 26.625 0 26.885 0.26 ;
+    END
+  END A_BIST_DIN[2]
+  PIN A_BM[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 202.93 0 203.19 0.26 ;
+    END
+  END A_BM[13]
+  PIN A_BM[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 33.61 0 33.87 0.26 ;
+    END
+  END A_BM[2]
+  PIN A_BIST_BM[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 204.305 0 204.565 0.26 ;
+    END
+  END A_BIST_BM[13]
+  PIN A_BIST_BM[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 32.235 0 32.495 0.26 ;
+    END
+  END A_BIST_BM[2]
+  PIN A_DOUT[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 203.44 0 203.7 0.26 ;
+    END
+  END A_DOUT[13]
+  PIN A_DOUT[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 33.1 0 33.36 0.26 ;
+    END
+  END A_DOUT[2]
+  PIN A_DIN[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 222.01 0 222.27 0.26 ;
+    END
+  END A_DIN[14]
+  PIN A_DIN[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 14.53 0 14.79 0.26 ;
+    END
+  END A_DIN[1]
+  PIN A_BIST_DIN[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 221.155 0 221.415 0.26 ;
+    END
+  END A_BIST_DIN[14]
+  PIN A_BIST_DIN[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 15.385 0 15.645 0.26 ;
+    END
+  END A_BIST_DIN[1]
+  PIN A_BM[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 214.17 0 214.43 0.26 ;
+    END
+  END A_BM[14]
+  PIN A_BM[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 22.37 0 22.63 0.26 ;
+    END
+  END A_BM[1]
+  PIN A_BIST_BM[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 215.545 0 215.805 0.26 ;
+    END
+  END A_BIST_BM[14]
+  PIN A_BIST_BM[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 20.995 0 21.255 0.26 ;
+    END
+  END A_BIST_BM[1]
+  PIN A_DOUT[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 214.68 0 214.94 0.26 ;
+    END
+  END A_DOUT[14]
+  PIN A_DOUT[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 21.86 0 22.12 0.26 ;
+    END
+  END A_DOUT[1]
+  PIN A_DIN[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 233.25 0 233.51 0.26 ;
+    END
+  END A_DIN[15]
+  PIN A_DIN[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 3.29 0 3.55 0.26 ;
+    END
+  END A_DIN[0]
+  PIN A_BIST_DIN[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 232.395 0 232.655 0.26 ;
+    END
+  END A_BIST_DIN[15]
+  PIN A_BIST_DIN[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 4.145 0 4.405 0.26 ;
+    END
+  END A_BIST_DIN[0]
+  PIN A_BM[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 225.41 0 225.67 0.26 ;
+    END
+  END A_BM[15]
+  PIN A_BM[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 11.13 0 11.39 0.26 ;
+    END
+  END A_BM[0]
+  PIN A_BIST_BM[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 226.785 0 227.045 0.26 ;
+    END
+  END A_BIST_BM[15]
+  PIN A_BIST_BM[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 9.755 0 10.015 0.26 ;
+    END
+  END A_BIST_BM[0]
+  PIN A_DOUT[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 225.92 0 226.18 0.26 ;
+    END
+  END A_DOUT[15]
+  PIN A_DOUT[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 10.62 0 10.88 0.26 ;
+    END
+  END A_DOUT[0]
+  PIN A_ADDR[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 8.9011 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 45.223301 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 114.6 0 114.86 0.26 ;
+    END
+  END A_ADDR[0]
+  PIN A_BIST_ADDR[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 9.6967 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 49.184466 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 119.19 0 119.45 0.26 ;
+    END
+  END A_BIST_ADDR[0]
+  PIN A_ADDR[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 7.774 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 39.656958 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 114.09 0 114.35 0.26 ;
+    END
+  END A_ADDR[1]
+  PIN A_BIST_ADDR[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 8.5696 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 43.618123 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 118.68 0 118.94 0.26 ;
+    END
+  END A_BIST_ADDR[1]
+  PIN A_ADDR[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 10.6327 LAYER Metal2 ;
+    ANTENNAPARTIALMETALAREA 1.5246 LAYER Metal3 ;
+    ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal3 ;
+      ANTENNAMAXAREACAR 9.415982 LAYER Metal3 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 122.25 0 122.51 0.26 ;
+    END
+  END A_ADDR[2]
+  PIN A_BIST_ADDR[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 10.6327 LAYER Metal2 ;
+    ANTENNAPARTIALMETALAREA 1.0962 LAYER Metal3 ;
+    ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal3 ;
+      ANTENNAMAXAREACAR 7.813791 LAYER Metal3 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 122.76 0 123.02 0.26 ;
+    END
+  END A_BIST_ADDR[2]
+  PIN A_ADDR[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 10.6327 LAYER Metal2 ;
+    ANTENNAPARTIALMETALAREA 3.8367 LAYER Metal3 ;
+    ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal3 ;
+      ANTENNAMAXAREACAR 20.927558 LAYER Metal3 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 121.23 0 121.49 0.26 ;
+    END
+  END A_ADDR[3]
+  PIN A_BIST_ADDR[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 10.6327 LAYER Metal2 ;
+    ANTENNAPARTIALMETALAREA 3.5175 LAYER Metal3 ;
+    ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal3 ;
+      ANTENNAMAXAREACAR 19.869057 LAYER Metal3 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 121.74 0 122 0.26 ;
+    END
+  END A_BIST_ADDR[3]
+  PIN A_ADDR[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 12.1979 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 61.63754 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 124.8 0 125.06 0.26 ;
+    END
+  END A_ADDR[4]
+  PIN A_BIST_ADDR[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 11.9327 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 60.317152 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 124.29 0 124.55 0.26 ;
+    END
+  END A_BIST_ADDR[4]
+  PIN A_ADDR[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 13.9269 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 70.245955 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 123.78 0 124.04 0.26 ;
+    END
+  END A_ADDR[5]
+  PIN A_BIST_ADDR[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 13.6617 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 68.925566 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 123.27 0 123.53 0.26 ;
+    END
+  END A_BIST_ADDR[5]
+  PIN A_ADDR[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 10.9525 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 55.436893 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 102.36 0 102.62 0.26 ;
+    END
+  END A_ADDR[6]
+  PIN A_BIST_ADDR[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 10.6771 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 54.065721 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 102.87 0 103.13 0.26 ;
+    END
+  END A_BIST_ADDR[6]
+  PIN A_ADDR[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 12.4163 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 62.724919 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 103.38 0 103.64 0.26 ;
+    END
+  END A_ADDR[7]
+  PIN A_BIST_ADDR[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 12.1511 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 61.404531 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 103.89 0 104.15 0.26 ;
+    END
+  END A_BIST_ADDR[7]
+  PIN A_ADDR[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 10.3675 LAYER Metal2 ;
+    ANTENNAPARTIALMETALAREA 1.5897 LAYER Metal3 ;
+    ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal3 ;
+      ANTENNAMAXAREACAR 9.740105 LAYER Metal3 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 132.45 0 132.71 0.26 ;
+    END
+  END A_ADDR[8]
+  PIN A_BIST_ADDR[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 10.3675 LAYER Metal2 ;
+    ANTENNAPARTIALMETALAREA 1.3755 LAYER Metal3 ;
+    ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal3 ;
+      ANTENNAMAXAREACAR 9.204381 LAYER Metal3 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 132.96 0 133.22 0.26 ;
+    END
+  END A_BIST_ADDR[8]
+  PIN A_ADDR[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 12.2633 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 61.963157 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 127.35 0 127.61 0.26 ;
+    END
+  END A_ADDR[9]
+  PIN A_BIST_ADDR[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 12.0083 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 60.693552 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 127.86 0 128.12 0.26 ;
+    END
+  END A_BIST_ADDR[9]
+  PIN A_CLK
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 4.0547 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 21.093851 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 112.56 0 112.82 0.26 ;
+    END
+  END A_CLK
+  PIN A_REN
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 3.99505 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 20.796863 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 116.13 0 116.39 0.26 ;
+    END
+  END A_REN
+  PIN A_WEN
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 115.62 0 115.88 0.26 ;
+    END
+  END A_WEN
+  PIN A_MEN
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 3.0247 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 15.965646 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 113.07 0 113.33 0.26 ;
+    END
+  END A_MEN
+  PIN A_DLY
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 6.058 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.3367 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 18.532819 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 134.49 0 134.75 0.26 ;
+    END
+  END A_DLY
+  PIN A_BIST_EN
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 3.9871 LAYER Metal2 ;
+    ANTENNAPARTIALMETALAREA 114.62575 LAYER Metal3 ;
+    ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 1.43 LAYER Metal2 ;
+      ANTENNAGATEAREA 16.445 LAYER Metal3 ;
+      ANTENNAMAXAREACAR 3.213636 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 17.242977 LAYER Metal3 ;
+      ANTENNAMAXCUTCAR 0.151469 LAYER Via2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 115.11 0 115.37 0.26 ;
+    END
+  END A_BIST_EN
+  PIN A_BIST_CLK
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 4.1639 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 21.953448 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 111.03 0 111.29 0.26 ;
+    END
+  END A_BIST_CLK
+  PIN A_BIST_REN
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 4.1119 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 21.694548 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 117.66 0 117.92 0.26 ;
+    END
+  END A_BIST_REN
+  PIN A_BIST_WEN
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 2.9051 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 15.686084 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 117.15 0 117.41 0.26 ;
+    END
+  END A_BIST_WEN
+  PIN A_BIST_MEN
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 2.8977 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 15.649241 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 111.54 0 111.8 0.26 ;
+    END
+  END A_BIST_MEN
+  OBS
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+
+END LIBRARY
diff --git a/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_1024x8_c2_bm_bist.lef b/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_1024x8_c2_bm_bist.lef
new file mode 100644
index 00000000..79735c6a
--- /dev/null
+++ b/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_1024x8_c2_bm_bist.lef
@@ -0,0 +1,1548 @@
+# ------------------------------------------------------
+#
+#		Copyright 2024 IHP PDK Authors
+#
+#		Licensed under the Apache License, Version 2.0 (the "License");
+#		you may not use this file except in compliance with the License.
+#		You may obtain a copy of the License at
+#		
+#		   https://www.apache.org/licenses/LICENSE-2.0
+#		
+#		Unless required by applicable law or agreed to in writing, software
+#		distributed under the License is distributed on an "AS IS" BASIS,
+#		WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#		See the License for the specific language governing permissions and
+#		limitations under the License.
+#		
+#		Generated on Fri Jul 19 09:01:22 2024		
+#
+# ------------------------------------------------------ 
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+
+MACRO RM_IHPSG13_1P_1024x8_c2_bm_bist
+  CLASS BLOCK ;
+  ORIGIN 0 0 ;
+  FOREIGN RM_IHPSG13_1P_1024x8_c2_bm_bist 0 0 ;
+  SIZE 146.88 BY 336.46 ;
+  SYMMETRY X Y R90 ;
+  PIN A_DIN[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 109.61 0 109.87 0.26 ;
+    END
+  END A_DIN[4]
+  PIN A_DIN[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 37.01 0 37.27 0.26 ;
+    END
+  END A_DIN[3]
+  PIN A_BIST_DIN[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 108.755 0 109.015 0.26 ;
+    END
+  END A_BIST_DIN[4]
+  PIN A_BIST_DIN[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 37.865 0 38.125 0.26 ;
+    END
+  END A_BIST_DIN[3]
+  PIN A_BM[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 101.77 0 102.03 0.26 ;
+    END
+  END A_BM[4]
+  PIN A_BM[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 44.85 0 45.11 0.26 ;
+    END
+  END A_BM[3]
+  PIN A_BIST_BM[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 103.145 0 103.405 0.26 ;
+    END
+  END A_BIST_BM[4]
+  PIN A_BIST_BM[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 43.475 0 43.735 0.26 ;
+    END
+  END A_BIST_BM[3]
+  PIN A_DOUT[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 102.28 0 102.54 0.26 ;
+    END
+  END A_DOUT[4]
+  PIN A_DOUT[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 44.34 0 44.6 0.26 ;
+    END
+  END A_DOUT[3]
+  PIN VSS!
+    DIRECTION INOUT ;
+    USE GROUND ;
+    NETEXPR "vss VSS!" ;
+    PORT
+      LAYER Metal4 ;
+        RECT 134.19 0 137 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 122.95 0 125.76 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 111.71 0 114.52 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 100.47 0 103.28 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 90.06 0 92.87 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 79.76 0 82.57 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 64.31 0 67.12 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 54.01 0 56.82 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 43.6 0 46.41 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 32.36 0 35.17 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 21.12 0 23.93 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 9.88 0 12.69 336.46 ;
+    END
+  END VSS!
+  PIN VDD!
+    DIRECTION INOUT ;
+    USE POWER ;
+    NETEXPR "vdd VDD!" ;
+    PORT
+      LAYER Metal4 ;
+        RECT 139.81 0 142.62 38.825 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 128.57 0 131.38 38.825 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 117.33 0 120.14 38.825 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 106.09 0 108.9 38.825 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 84.91 0 87.72 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 74.61 0 77.42 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 69.46 0 72.27 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 59.16 0 61.97 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 37.98 0 40.79 38.825 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 26.74 0 29.55 38.825 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 15.5 0 18.31 38.825 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 4.26 0 7.07 38.825 ;
+    END
+  END VDD!
+  PIN VDDARRAY!
+    DIRECTION INOUT ;
+    USE POWER ;
+    NETEXPR "vddarray VDDARRAY!" ;
+    PORT
+      LAYER Metal4 ;
+        RECT 139.81 45.465 142.62 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 128.57 45.465 131.38 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 117.33 45.465 120.14 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 106.09 45.465 108.9 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 37.98 45.465 40.79 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 26.74 45.465 29.55 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 15.5 45.465 18.31 336.46 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 4.26 45.465 7.07 336.46 ;
+    END
+  END VDDARRAY!
+  PIN A_DIN[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 120.85 0 121.11 0.26 ;
+    END
+  END A_DIN[5]
+  PIN A_DIN[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 25.77 0 26.03 0.26 ;
+    END
+  END A_DIN[2]
+  PIN A_BIST_DIN[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 119.995 0 120.255 0.26 ;
+    END
+  END A_BIST_DIN[5]
+  PIN A_BIST_DIN[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 26.625 0 26.885 0.26 ;
+    END
+  END A_BIST_DIN[2]
+  PIN A_BM[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 113.01 0 113.27 0.26 ;
+    END
+  END A_BM[5]
+  PIN A_BM[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 33.61 0 33.87 0.26 ;
+    END
+  END A_BM[2]
+  PIN A_BIST_BM[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 114.385 0 114.645 0.26 ;
+    END
+  END A_BIST_BM[5]
+  PIN A_BIST_BM[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 32.235 0 32.495 0.26 ;
+    END
+  END A_BIST_BM[2]
+  PIN A_DOUT[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 113.52 0 113.78 0.26 ;
+    END
+  END A_DOUT[5]
+  PIN A_DOUT[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 33.1 0 33.36 0.26 ;
+    END
+  END A_DOUT[2]
+  PIN A_DIN[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 132.09 0 132.35 0.26 ;
+    END
+  END A_DIN[6]
+  PIN A_DIN[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 14.53 0 14.79 0.26 ;
+    END
+  END A_DIN[1]
+  PIN A_BIST_DIN[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 131.235 0 131.495 0.26 ;
+    END
+  END A_BIST_DIN[6]
+  PIN A_BIST_DIN[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 15.385 0 15.645 0.26 ;
+    END
+  END A_BIST_DIN[1]
+  PIN A_BM[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 124.25 0 124.51 0.26 ;
+    END
+  END A_BM[6]
+  PIN A_BM[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 22.37 0 22.63 0.26 ;
+    END
+  END A_BM[1]
+  PIN A_BIST_BM[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 125.625 0 125.885 0.26 ;
+    END
+  END A_BIST_BM[6]
+  PIN A_BIST_BM[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 20.995 0 21.255 0.26 ;
+    END
+  END A_BIST_BM[1]
+  PIN A_DOUT[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 124.76 0 125.02 0.26 ;
+    END
+  END A_DOUT[6]
+  PIN A_DOUT[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 21.86 0 22.12 0.26 ;
+    END
+  END A_DOUT[1]
+  PIN A_DIN[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 143.33 0 143.59 0.26 ;
+    END
+  END A_DIN[7]
+  PIN A_DIN[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.794 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.838188 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 3.29 0 3.55 0.26 ;
+    END
+  END A_DIN[0]
+  PIN A_BIST_DIN[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 142.475 0 142.735 0.26 ;
+    END
+  END A_BIST_DIN[7]
+  PIN A_BIST_DIN[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.6263 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.365945 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 4.145 0 4.405 0.26 ;
+    END
+  END A_BIST_DIN[0]
+  PIN A_BM[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 135.49 0 135.75 0.26 ;
+    END
+  END A_BM[7]
+  PIN A_BM[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7215 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.498382 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 11.13 0 11.39 0.26 ;
+    END
+  END A_BM[0]
+  PIN A_BIST_BM[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 136.865 0 137.125 0.26 ;
+    END
+  END A_BIST_BM[7]
+  PIN A_BIST_BM[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7605 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 5.055265 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 9.755 0 10.015 0.26 ;
+    END
+  END A_BIST_BM[0]
+  PIN A_DOUT[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 136 0 136.26 0.26 ;
+    END
+  END A_DOUT[7]
+  PIN A_DOUT[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 3.7095 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 10.62 0 10.88 0.26 ;
+    END
+  END A_DOUT[0]
+  PIN A_ADDR[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 8.9011 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 45.223301 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 69.64 0 69.9 0.26 ;
+    END
+  END A_ADDR[0]
+  PIN A_BIST_ADDR[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 9.6967 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 49.184466 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 74.23 0 74.49 0.26 ;
+    END
+  END A_BIST_ADDR[0]
+  PIN A_ADDR[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 7.774 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 39.656958 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 69.13 0 69.39 0.26 ;
+    END
+  END A_ADDR[1]
+  PIN A_BIST_ADDR[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 8.5696 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 43.618123 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 73.72 0 73.98 0.26 ;
+    END
+  END A_BIST_ADDR[1]
+  PIN A_ADDR[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 10.6327 LAYER Metal2 ;
+    ANTENNAPARTIALMETALAREA 1.5246 LAYER Metal3 ;
+    ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal3 ;
+      ANTENNAMAXAREACAR 9.415982 LAYER Metal3 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 77.29 0 77.55 0.26 ;
+    END
+  END A_ADDR[2]
+  PIN A_BIST_ADDR[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 10.6327 LAYER Metal2 ;
+    ANTENNAPARTIALMETALAREA 1.0962 LAYER Metal3 ;
+    ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal3 ;
+      ANTENNAMAXAREACAR 7.813791 LAYER Metal3 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 77.8 0 78.06 0.26 ;
+    END
+  END A_BIST_ADDR[2]
+  PIN A_ADDR[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 10.6327 LAYER Metal2 ;
+    ANTENNAPARTIALMETALAREA 3.8367 LAYER Metal3 ;
+    ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal3 ;
+      ANTENNAMAXAREACAR 20.927558 LAYER Metal3 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 76.27 0 76.53 0.26 ;
+    END
+  END A_ADDR[3]
+  PIN A_BIST_ADDR[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 10.6327 LAYER Metal2 ;
+    ANTENNAPARTIALMETALAREA 3.5175 LAYER Metal3 ;
+    ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal3 ;
+      ANTENNAMAXAREACAR 19.869057 LAYER Metal3 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 76.78 0 77.04 0.26 ;
+    END
+  END A_BIST_ADDR[3]
+  PIN A_ADDR[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 12.1979 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 61.63754 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 79.84 0 80.1 0.26 ;
+    END
+  END A_ADDR[4]
+  PIN A_BIST_ADDR[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 11.9327 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 60.317152 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 79.33 0 79.59 0.26 ;
+    END
+  END A_BIST_ADDR[4]
+  PIN A_ADDR[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 13.9269 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 70.245955 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 78.82 0 79.08 0.26 ;
+    END
+  END A_ADDR[5]
+  PIN A_BIST_ADDR[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 13.6617 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 68.925566 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 78.31 0 78.57 0.26 ;
+    END
+  END A_BIST_ADDR[5]
+  PIN A_ADDR[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 10.9525 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 55.436893 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 57.4 0 57.66 0.26 ;
+    END
+  END A_ADDR[6]
+  PIN A_BIST_ADDR[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 10.6771 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 54.065721 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 57.91 0 58.17 0.26 ;
+    END
+  END A_BIST_ADDR[6]
+  PIN A_ADDR[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 12.4163 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 62.724919 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 58.42 0 58.68 0.26 ;
+    END
+  END A_ADDR[7]
+  PIN A_BIST_ADDR[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 12.1511 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 61.404531 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 58.93 0 59.19 0.26 ;
+    END
+  END A_BIST_ADDR[7]
+  PIN A_ADDR[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 10.3675 LAYER Metal2 ;
+    ANTENNAPARTIALMETALAREA 1.5897 LAYER Metal3 ;
+    ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal3 ;
+      ANTENNAMAXAREACAR 9.740105 LAYER Metal3 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 87.49 0 87.75 0.26 ;
+    END
+  END A_ADDR[8]
+  PIN A_BIST_ADDR[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 10.3675 LAYER Metal2 ;
+    ANTENNAPARTIALMETALAREA 1.3755 LAYER Metal3 ;
+    ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal3 ;
+      ANTENNAMAXAREACAR 9.204381 LAYER Metal3 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 88 0 88.26 0.26 ;
+    END
+  END A_BIST_ADDR[8]
+  PIN A_ADDR[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 12.2633 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 61.963157 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 82.39 0 82.65 0.26 ;
+    END
+  END A_ADDR[9]
+  PIN A_BIST_ADDR[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 12.0083 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 60.693552 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 82.9 0 83.16 0.26 ;
+    END
+  END A_BIST_ADDR[9]
+  PIN A_CLK
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 4.0547 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 21.093851 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 67.6 0 67.86 0.26 ;
+    END
+  END A_CLK
+  PIN A_REN
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 3.99505 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 20.796863 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 71.17 0 71.43 0.26 ;
+    END
+  END A_REN
+  PIN A_WEN
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 2.8847 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 15.268608 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 70.66 0 70.92 0.26 ;
+    END
+  END A_WEN
+  PIN A_MEN
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 3.0247 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 15.965646 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 68.11 0 68.37 0.26 ;
+    END
+  END A_MEN
+  PIN A_DLY
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 6.058 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.3367 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 18.532819 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 89.53 0 89.79 0.26 ;
+    END
+  END A_DLY
+  PIN A_BIST_EN
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 3.9871 LAYER Metal2 ;
+    ANTENNAPARTIALMETALAREA 70.28015 LAYER Metal3 ;
+    ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 1.43 LAYER Metal2 ;
+      ANTENNAGATEAREA 10.725 LAYER Metal3 ;
+      ANTENNAMAXAREACAR 3.213636 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 16.825655 LAYER Metal3 ;
+      ANTENNAMAXCUTCAR 0.151469 LAYER Via2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 70.15 0 70.41 0.26 ;
+    END
+  END A_BIST_EN
+  PIN A_BIST_CLK
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 4.1639 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 21.953448 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 66.07 0 66.33 0.26 ;
+    END
+  END A_BIST_CLK
+  PIN A_BIST_REN
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 4.1119 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 21.694548 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 72.7 0 72.96 0.26 ;
+    END
+  END A_BIST_REN
+  PIN A_BIST_WEN
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 2.9051 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 15.686084 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 72.19 0 72.45 0.26 ;
+    END
+  END A_BIST_WEN
+  PIN A_BIST_MEN
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 2.8977 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 15.649241 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 66.58 0 66.84 0.26 ;
+    END
+  END A_BIST_MEN
+  OBS
+    LAYER Metal1 ;
+      RECT 0 0 146.88 336.46 ;
+    LAYER Metal2 ;
+      RECT 0.105 45.465 0.305 336.435 ;
+      RECT 1.1 335.705 1.3 336.435 ;
+      RECT 3.29 0.52 3.55 5.16 ;
+      RECT 2.77 4.9 3.55 5.16 ;
+      RECT 2.77 4.9 3.03 6.64 ;
+      RECT 1.92 335.705 2.12 336.435 ;
+      RECT 2.415 335.705 2.615 336.435 ;
+      RECT 2.915 335.705 3.115 336.435 ;
+      RECT 3.415 335.705 3.615 336.435 ;
+      RECT 3.91 335.705 4.11 336.435 ;
+      RECT 4.655 0.17 5.425 0.94 ;
+      RECT 4.655 0.17 4.915 12.9 ;
+      RECT 5.165 0.17 5.425 12.9 ;
+      RECT 4.145 0.52 4.405 5.815 ;
+      RECT 4.73 335.705 4.93 336.435 ;
+      RECT 5.675 0.17 6.445 0.43 ;
+      RECT 5.675 0.17 5.935 11.5 ;
+      RECT 6.185 0.17 6.445 11.5 ;
+      RECT 5.225 335.705 5.425 336.435 ;
+      RECT 5.725 335.705 5.925 336.435 ;
+      RECT 6.225 335.705 6.425 336.435 ;
+      RECT 7.715 0.17 8.485 0.43 ;
+      RECT 7.715 0.17 7.975 10.48 ;
+      RECT 8.225 0.17 8.485 10.99 ;
+      RECT 6.72 335.705 6.92 336.435 ;
+      RECT 7.54 335.705 7.74 336.435 ;
+      RECT 8.735 0.17 9.505 0.94 ;
+      RECT 8.735 0.17 8.995 8.7 ;
+      RECT 9.245 0.17 9.505 12.9 ;
+      RECT 8.035 335.705 8.235 336.435 ;
+      RECT 8.535 335.705 8.735 336.435 ;
+      RECT 9.035 335.705 9.235 336.435 ;
+      RECT 9.53 335.705 9.73 336.435 ;
+      RECT 9.755 0.52 10.015 2.485 ;
+      RECT 10.35 335.705 10.55 336.435 ;
+      RECT 10.62 0.52 10.88 14.11 ;
+      RECT 10.845 335.705 11.045 336.435 ;
+      RECT 11.13 0.52 11.39 2.335 ;
+      RECT 11.345 335.705 11.545 336.435 ;
+      RECT 11.845 335.705 12.045 336.435 ;
+      RECT 12.34 335.705 12.54 336.435 ;
+      RECT 14.53 0.52 14.79 5.16 ;
+      RECT 14.01 4.9 14.79 5.16 ;
+      RECT 14.01 4.9 14.27 6.64 ;
+      RECT 13.16 335.705 13.36 336.435 ;
+      RECT 13.655 335.705 13.855 336.435 ;
+      RECT 14.155 335.705 14.355 336.435 ;
+      RECT 14.655 335.705 14.855 336.435 ;
+      RECT 15.15 335.705 15.35 336.435 ;
+      RECT 15.895 0.17 16.665 0.94 ;
+      RECT 15.895 0.17 16.155 12.9 ;
+      RECT 16.405 0.17 16.665 12.9 ;
+      RECT 15.385 0.52 15.645 5.815 ;
+      RECT 15.97 335.705 16.17 336.435 ;
+      RECT 16.915 0.17 17.685 0.43 ;
+      RECT 16.915 0.17 17.175 11.5 ;
+      RECT 17.425 0.17 17.685 11.5 ;
+      RECT 16.465 335.705 16.665 336.435 ;
+      RECT 16.965 335.705 17.165 336.435 ;
+      RECT 17.465 335.705 17.665 336.435 ;
+      RECT 18.955 0.17 19.725 0.43 ;
+      RECT 18.955 0.17 19.215 10.48 ;
+      RECT 19.465 0.17 19.725 10.99 ;
+      RECT 17.96 335.705 18.16 336.435 ;
+      RECT 18.78 335.705 18.98 336.435 ;
+      RECT 19.975 0.17 20.745 0.94 ;
+      RECT 19.975 0.17 20.235 8.7 ;
+      RECT 20.485 0.17 20.745 12.9 ;
+      RECT 19.275 335.705 19.475 336.435 ;
+      RECT 19.775 335.705 19.975 336.435 ;
+      RECT 20.275 335.705 20.475 336.435 ;
+      RECT 20.77 335.705 20.97 336.435 ;
+      RECT 20.995 0.52 21.255 2.485 ;
+      RECT 21.59 335.705 21.79 336.435 ;
+      RECT 21.86 0.52 22.12 14.11 ;
+      RECT 22.085 335.705 22.285 336.435 ;
+      RECT 22.37 0.52 22.63 2.335 ;
+      RECT 22.585 335.705 22.785 336.435 ;
+      RECT 23.085 335.705 23.285 336.435 ;
+      RECT 23.58 335.705 23.78 336.435 ;
+      RECT 25.77 0.52 26.03 5.16 ;
+      RECT 25.25 4.9 26.03 5.16 ;
+      RECT 25.25 4.9 25.51 6.64 ;
+      RECT 24.4 335.705 24.6 336.435 ;
+      RECT 24.895 335.705 25.095 336.435 ;
+      RECT 25.395 335.705 25.595 336.435 ;
+      RECT 25.895 335.705 26.095 336.435 ;
+      RECT 26.39 335.705 26.59 336.435 ;
+      RECT 27.135 0.17 27.905 0.94 ;
+      RECT 27.135 0.17 27.395 12.9 ;
+      RECT 27.645 0.17 27.905 12.9 ;
+      RECT 26.625 0.52 26.885 5.815 ;
+      RECT 27.21 335.705 27.41 336.435 ;
+      RECT 28.155 0.17 28.925 0.43 ;
+      RECT 28.155 0.17 28.415 11.5 ;
+      RECT 28.665 0.17 28.925 11.5 ;
+      RECT 27.705 335.705 27.905 336.435 ;
+      RECT 28.205 335.705 28.405 336.435 ;
+      RECT 28.705 335.705 28.905 336.435 ;
+      RECT 30.195 0.17 30.965 0.43 ;
+      RECT 30.195 0.17 30.455 10.48 ;
+      RECT 30.705 0.17 30.965 10.99 ;
+      RECT 29.2 335.705 29.4 336.435 ;
+      RECT 30.02 335.705 30.22 336.435 ;
+      RECT 31.215 0.17 31.985 0.94 ;
+      RECT 31.215 0.17 31.475 8.7 ;
+      RECT 31.725 0.17 31.985 12.9 ;
+      RECT 30.515 335.705 30.715 336.435 ;
+      RECT 31.015 335.705 31.215 336.435 ;
+      RECT 31.515 335.705 31.715 336.435 ;
+      RECT 32.01 335.705 32.21 336.435 ;
+      RECT 32.235 0.52 32.495 2.485 ;
+      RECT 32.83 335.705 33.03 336.435 ;
+      RECT 33.1 0.52 33.36 14.11 ;
+      RECT 33.325 335.705 33.525 336.435 ;
+      RECT 33.61 0.52 33.87 2.335 ;
+      RECT 33.825 335.705 34.025 336.435 ;
+      RECT 34.325 335.705 34.525 336.435 ;
+      RECT 34.82 335.705 35.02 336.435 ;
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+      RECT 36.49 4.9 37.27 5.16 ;
+      RECT 36.49 4.9 36.75 6.64 ;
+      RECT 35.64 335.705 35.84 336.435 ;
+      RECT 36.135 335.705 36.335 336.435 ;
+      RECT 36.635 335.705 36.835 336.435 ;
+      RECT 37.135 335.705 37.335 336.435 ;
+      RECT 37.63 335.705 37.83 336.435 ;
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+      RECT 38.375 0.17 38.635 12.9 ;
+      RECT 38.885 0.17 39.145 12.9 ;
+      RECT 37.865 0.52 38.125 5.815 ;
+      RECT 38.45 335.705 38.65 336.435 ;
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+      RECT 39.395 0.17 39.655 11.5 ;
+      RECT 39.905 0.17 40.165 11.5 ;
+      RECT 38.945 335.705 39.145 336.435 ;
+      RECT 39.445 335.705 39.645 336.435 ;
+      RECT 39.945 335.705 40.145 336.435 ;
+      RECT 41.435 0.17 42.205 0.43 ;
+      RECT 41.435 0.17 41.695 10.48 ;
+      RECT 41.945 0.17 42.205 10.99 ;
+      RECT 40.44 335.705 40.64 336.435 ;
+      RECT 41.26 335.705 41.46 336.435 ;
+      RECT 42.455 0.17 43.225 0.94 ;
+      RECT 42.455 0.17 42.715 8.7 ;
+      RECT 42.965 0.17 43.225 12.9 ;
+      RECT 41.755 335.705 41.955 336.435 ;
+      RECT 42.255 335.705 42.455 336.435 ;
+      RECT 42.755 335.705 42.955 336.435 ;
+      RECT 43.25 335.705 43.45 336.435 ;
+      RECT 43.475 0.52 43.735 2.485 ;
+      RECT 44.07 335.705 44.27 336.435 ;
+      RECT 44.34 0.52 44.6 14.11 ;
+      RECT 44.565 335.705 44.765 336.435 ;
+      RECT 44.85 0.52 45.11 2.335 ;
+      RECT 45.065 335.705 45.265 336.435 ;
+      RECT 45.565 335.705 45.765 336.435 ;
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+      RECT 47.555 0.17 47.815 8.7 ;
+      RECT 48.065 0.17 48.325 8.7 ;
+      RECT 48.575 0.17 49.345 0.94 ;
+      RECT 48.575 0.17 48.835 8.7 ;
+      RECT 49.085 0.17 49.345 8.7 ;
+      RECT 49.595 0.17 50.365 0.43 ;
+      RECT 49.595 0.17 49.855 8.7 ;
+      RECT 50.105 0.17 50.365 8.7 ;
+      RECT 50.615 0.17 51.385 0.94 ;
+      RECT 50.615 0.17 50.875 8.7 ;
+      RECT 51.125 0.17 51.385 8.7 ;
+      RECT 51.635 0.17 52.405 0.43 ;
+      RECT 51.635 0.17 51.895 8.7 ;
+      RECT 52.145 0.17 52.405 8.7 ;
+      RECT 52.655 0.17 53.425 0.94 ;
+      RECT 52.655 0.17 52.915 8.7 ;
+      RECT 53.165 0.17 53.425 8.7 ;
+      RECT 46.06 335.705 46.26 336.435 ;
+      RECT 46.88 335.705 47.08 336.435 ;
+      RECT 47.875 335.705 48.075 336.435 ;
+      RECT 55.36 0.17 56.13 0.94 ;
+      RECT 55.36 0.17 55.62 8.7 ;
+      RECT 55.87 0.17 56.13 8.7 ;
+      RECT 53.83 0.3 54.09 8.7 ;
+      RECT 54.34 0 54.6 8.7 ;
+      RECT 54.85 0 55.11 8.7 ;
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+      RECT 141.95 335.705 142.15 336.435 ;
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+      RECT 143.33 0.52 143.59 5.16 ;
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+      RECT 144.76 335.705 144.96 336.435 ;
+      RECT 145.58 335.705 145.78 336.435 ;
+      RECT 146.575 45.465 146.775 336.435 ;
+    LAYER Metal2 SPACING 0.21 ;
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+      RECT 34.13 0 36.75 336.46 ;
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+      RECT 45.37 0 57.15 336.46 ;
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+      RECT 110.13 0 112.75 336.46 ;
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+      RECT 121.37 0 123.99 336.46 ;
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+      RECT 132.61 0 135.23 336.46 ;
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+      RECT 143.85 0 146.88 336.46 ;
+      RECT 0 0.52 146.88 336.46 ;
+      RECT 4.665 0 9.495 336.46 ;
+      RECT 15.905 0 20.735 336.46 ;
+      RECT 27.145 0 31.975 336.46 ;
+      RECT 38.385 0 43.215 336.46 ;
+      RECT 59.44 0 65.81 336.46 ;
+      RECT 74.75 0 76.01 336.46 ;
+      RECT 80.35 0 82.13 336.46 ;
+      RECT 103.665 0 108.495 336.46 ;
+      RECT 114.905 0 119.735 336.46 ;
+      RECT 126.145 0 130.975 336.46 ;
+      RECT 137.385 0 142.215 336.46 ;
+      RECT 67.1 0 67.34 336.46 ;
+      RECT 68.63 0 68.87 336.46 ;
+      RECT 71.69 0 71.93 336.46 ;
+      RECT 73.22 0 73.46 336.46 ;
+      RECT 83.42 0 87.23 336.46 ;
+      RECT 88.52 0 89.27 336.46 ;
+      RECT 0 0 3.03 336.46 ;
+      RECT 4.655 0.17 9.505 336.46 ;
+      RECT 11.65 0 14.27 336.46 ;
+      RECT 15.895 0.17 20.745 336.46 ;
+      RECT 22.89 0 25.51 336.46 ;
+    LAYER Metal3 ;
+      RECT 0 0 146.88 336.46 ;
+    LAYER Metal4 SPACING 0.21 ;
+      RECT 0 39.085 9.62 45.205 ;
+      RECT 0 0 4 336.46 ;
+      RECT 7.33 0 9.62 336.46 ;
+      RECT 12.95 39.085 20.86 45.205 ;
+      RECT 12.95 0 15.24 336.46 ;
+      RECT 18.57 0 20.86 336.46 ;
+      RECT 24.19 39.085 32.1 45.205 ;
+      RECT 24.19 0 26.48 336.46 ;
+      RECT 29.81 0 32.1 336.46 ;
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+      RECT 35.43 0 37.72 336.46 ;
+      RECT 41.05 0 43.34 336.46 ;
+      RECT 46.67 0 53.75 336.46 ;
+      RECT 57.08 0 58.9 336.46 ;
+      RECT 62.23 0 64.05 336.46 ;
+      RECT 67.38 0 69.2 336.46 ;
+      RECT 72.53 0 74.35 336.46 ;
+      RECT 77.68 0 79.5 336.46 ;
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+      RECT 103.54 0 105.83 336.46 ;
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+      RECT 114.78 0 117.07 336.46 ;
+      RECT 120.4 0 122.69 336.46 ;
+      RECT 126.02 39.085 133.93 45.205 ;
+      RECT 126.02 0 128.31 336.46 ;
+      RECT 131.64 0 133.93 336.46 ;
+      RECT 137.26 39.085 146.88 45.205 ;
+      RECT 137.26 0 139.55 336.46 ;
+      RECT 142.88 0 146.88 336.46 ;
+      RECT 82.83 0 84.65 336.46 ;
+      RECT 87.98 0 89.8 336.46 ;
+      RECT 93.13 0 100.21 336.46 ;
+  END
+END RM_IHPSG13_1P_1024x8_c2_bm_bist
+
+END LIBRARY
diff --git a/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_4096x16_c3_bm_bist.lef b/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_4096x16_c3_bm_bist.lef
new file mode 100644
index 00000000..16c930a4
--- /dev/null
+++ b/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_4096x16_c3_bm_bist.lef
@@ -0,0 +1,2934 @@
+# ------------------------------------------------------
+#
+#		Copyright 2024 IHP PDK Authors
+#
+#		Licensed under the Apache License, Version 2.0 (the "License");
+#		you may not use this file except in compliance with the License.
+#		You may obtain a copy of the License at
+#		
+#		   https://www.apache.org/licenses/LICENSE-2.0
+#		
+#		Unless required by applicable law or agreed to in writing, software
+#		distributed under the License is distributed on an "AS IS" BASIS,
+#		WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#		See the License for the specific language governing permissions and
+#		limitations under the License.
+#		
+#		Generated on Fri Jul 12 17:37:54 2024		
+#
+# ------------------------------------------------------ 
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+
+MACRO RM_IHPSG13_1P_4096x16_c3_bm_bist
+  CLASS BLOCK ;
+  ORIGIN 0 0 ;
+  FOREIGN RM_IHPSG13_1P_4096x16_c3_bm_bist 0 0 ;
+  SIZE 416.64 BY 618.3 ;
+  SYMMETRY X Y R90 ;
+  PIN A_DIN[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 245.01 0 245.27 0.26 ;
+    END
+  END A_DIN[8]
+  PIN A_DIN[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 171.37 0 171.63 0.26 ;
+    END
+  END A_DIN[7]
+  PIN A_BIST_DIN[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 243.48 0 243.74 0.26 ;
+    END
+  END A_BIST_DIN[8]
+  PIN A_BIST_DIN[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 172.9 0 173.16 0.26 ;
+    END
+  END A_BIST_DIN[7]
+  PIN A_BM[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 248.89 0 249.15 0.26 ;
+    END
+  END A_BM[8]
+  PIN A_BM[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 167.49 0 167.75 0.26 ;
+    END
+  END A_BM[7]
+  PIN A_BIST_BM[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 250.42 0 250.68 0.26 ;
+    END
+  END A_BIST_BM[8]
+  PIN A_BIST_BM[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 165.96 0 166.22 0.26 ;
+    END
+  END A_BIST_BM[7]
+  PIN A_DOUT[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 249.755 0 250.015 0.26 ;
+    END
+  END A_DOUT[8]
+  PIN A_DOUT[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 166.625 0 166.885 0.26 ;
+    END
+  END A_DOUT[7]
+  PIN VSS!
+    DIRECTION INOUT ;
+    USE GROUND ;
+    NETEXPR "vss VSS!" ;
+    PORT
+      LAYER Metal4 ;
+        RECT 403.95 0 406.76 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 392.71 0 395.52 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 381.47 0 384.28 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 370.23 0 373.04 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 358.99 0 361.8 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 347.75 0 350.56 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 336.51 0 339.32 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 325.27 0 328.08 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 314.03 0 316.84 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 302.79 0 305.6 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 291.55 0 294.36 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 280.31 0 283.12 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 269.07 0 271.88 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 257.83 0 260.64 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 246.59 0 249.4 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 235.35 0 238.16 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 224.94 0 227.75 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 214.64 0 217.45 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 199.19 0 202 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 188.89 0 191.7 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 178.48 0 181.29 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 167.24 0 170.05 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 156 0 158.81 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 144.76 0 147.57 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 133.52 0 136.33 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 122.28 0 125.09 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 111.04 0 113.85 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 99.8 0 102.61 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 88.56 0 91.37 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 77.32 0 80.13 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 66.08 0 68.89 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 54.84 0 57.65 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 43.6 0 46.41 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 32.36 0 35.17 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 21.12 0 23.93 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 9.88 0 12.69 618.3 ;
+    END
+  END VSS!
+  PIN VDD!
+    DIRECTION INOUT ;
+    USE POWER ;
+    NETEXPR "vdd VDD!" ;
+    PORT
+      LAYER Metal4 ;
+        RECT 409.57 0 412.38 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 398.33 0 401.14 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 387.09 0 389.9 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 375.85 0 378.66 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 364.61 0 367.42 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 353.37 0 356.18 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 342.13 0 344.94 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 330.89 0 333.7 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 319.65 0 322.46 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 308.41 0 311.22 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 297.17 0 299.98 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 285.93 0 288.74 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 274.69 0 277.5 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 263.45 0 266.26 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 252.21 0 255.02 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 240.97 0 243.78 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 219.79 0 222.6 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 209.49 0 212.3 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 204.34 0 207.15 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 194.04 0 196.85 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 172.86 0 175.67 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 161.62 0 164.43 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 150.38 0 153.19 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 139.14 0 141.95 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 127.9 0 130.71 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 116.66 0 119.47 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 105.42 0 108.23 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 94.18 0 96.99 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 82.94 0 85.75 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 71.7 0 74.51 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 60.46 0 63.27 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 49.22 0 52.03 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 37.98 0 40.79 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 26.74 0 29.55 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 15.5 0 18.31 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 4.26 0 7.07 30.425 ;
+    END
+  END VDD!
+  PIN VDDARRAY!
+    DIRECTION INOUT ;
+    USE POWER ;
+    NETEXPR "vddarray VDDARRAY!" ;
+    PORT
+      LAYER Metal4 ;
+        RECT 409.57 37.065 412.38 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 398.33 37.065 401.14 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 387.09 37.065 389.9 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 375.85 37.065 378.66 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 364.61 37.065 367.42 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 353.37 37.065 356.18 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 342.13 37.065 344.94 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 330.89 37.065 333.7 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 319.65 37.065 322.46 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 308.41 37.065 311.22 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 297.17 37.065 299.98 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 285.93 37.065 288.74 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 274.69 37.065 277.5 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 263.45 37.065 266.26 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 252.21 37.065 255.02 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 240.97 37.065 243.78 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 172.86 37.065 175.67 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 161.62 37.065 164.43 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 150.38 37.065 153.19 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 139.14 37.065 141.95 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 127.9 37.065 130.71 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 116.66 37.065 119.47 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 105.42 37.065 108.23 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 94.18 37.065 96.99 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 82.94 37.065 85.75 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 71.7 37.065 74.51 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 60.46 37.065 63.27 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 49.22 37.065 52.03 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 37.98 37.065 40.79 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 26.74 37.065 29.55 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 15.5 37.065 18.31 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 4.26 37.065 7.07 618.3 ;
+    END
+  END VDDARRAY!
+  PIN A_DIN[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 267.49 0 267.75 0.26 ;
+    END
+  END A_DIN[9]
+  PIN A_DIN[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 148.89 0 149.15 0.26 ;
+    END
+  END A_DIN[6]
+  PIN A_BIST_DIN[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 265.96 0 266.22 0.26 ;
+    END
+  END A_BIST_DIN[9]
+  PIN A_BIST_DIN[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 150.42 0 150.68 0.26 ;
+    END
+  END A_BIST_DIN[6]
+  PIN A_BM[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 271.37 0 271.63 0.26 ;
+    END
+  END A_BM[9]
+  PIN A_BM[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 145.01 0 145.27 0.26 ;
+    END
+  END A_BM[6]
+  PIN A_BIST_BM[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 272.9 0 273.16 0.26 ;
+    END
+  END A_BIST_BM[9]
+  PIN A_BIST_BM[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 143.48 0 143.74 0.26 ;
+    END
+  END A_BIST_BM[6]
+  PIN A_DOUT[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 272.235 0 272.495 0.26 ;
+    END
+  END A_DOUT[9]
+  PIN A_DOUT[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 144.145 0 144.405 0.26 ;
+    END
+  END A_DOUT[6]
+  PIN A_DIN[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 289.97 0 290.23 0.26 ;
+    END
+  END A_DIN[10]
+  PIN A_DIN[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 126.41 0 126.67 0.26 ;
+    END
+  END A_DIN[5]
+  PIN A_BIST_DIN[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 288.44 0 288.7 0.26 ;
+    END
+  END A_BIST_DIN[10]
+  PIN A_BIST_DIN[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 127.94 0 128.2 0.26 ;
+    END
+  END A_BIST_DIN[5]
+  PIN A_BM[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 293.85 0 294.11 0.26 ;
+    END
+  END A_BM[10]
+  PIN A_BM[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 122.53 0 122.79 0.26 ;
+    END
+  END A_BM[5]
+  PIN A_BIST_BM[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 295.38 0 295.64 0.26 ;
+    END
+  END A_BIST_BM[10]
+  PIN A_BIST_BM[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 121 0 121.26 0.26 ;
+    END
+  END A_BIST_BM[5]
+  PIN A_DOUT[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 294.715 0 294.975 0.26 ;
+    END
+  END A_DOUT[10]
+  PIN A_DOUT[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 121.665 0 121.925 0.26 ;
+    END
+  END A_DOUT[5]
+  PIN A_DIN[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 312.45 0 312.71 0.26 ;
+    END
+  END A_DIN[11]
+  PIN A_DIN[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 103.93 0 104.19 0.26 ;
+    END
+  END A_DIN[4]
+  PIN A_BIST_DIN[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 310.92 0 311.18 0.26 ;
+    END
+  END A_BIST_DIN[11]
+  PIN A_BIST_DIN[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 105.46 0 105.72 0.26 ;
+    END
+  END A_BIST_DIN[4]
+  PIN A_BM[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 316.33 0 316.59 0.26 ;
+    END
+  END A_BM[11]
+  PIN A_BM[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 100.05 0 100.31 0.26 ;
+    END
+  END A_BM[4]
+  PIN A_BIST_BM[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 317.86 0 318.12 0.26 ;
+    END
+  END A_BIST_BM[11]
+  PIN A_BIST_BM[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 98.52 0 98.78 0.26 ;
+    END
+  END A_BIST_BM[4]
+  PIN A_DOUT[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 317.195 0 317.455 0.26 ;
+    END
+  END A_DOUT[11]
+  PIN A_DOUT[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 99.185 0 99.445 0.26 ;
+    END
+  END A_DOUT[4]
+  PIN A_DIN[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 334.93 0 335.19 0.26 ;
+    END
+  END A_DIN[12]
+  PIN A_DIN[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 81.45 0 81.71 0.26 ;
+    END
+  END A_DIN[3]
+  PIN A_BIST_DIN[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 333.4 0 333.66 0.26 ;
+    END
+  END A_BIST_DIN[12]
+  PIN A_BIST_DIN[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 82.98 0 83.24 0.26 ;
+    END
+  END A_BIST_DIN[3]
+  PIN A_BM[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 338.81 0 339.07 0.26 ;
+    END
+  END A_BM[12]
+  PIN A_BM[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 77.57 0 77.83 0.26 ;
+    END
+  END A_BM[3]
+  PIN A_BIST_BM[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 340.34 0 340.6 0.26 ;
+    END
+  END A_BIST_BM[12]
+  PIN A_BIST_BM[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 76.04 0 76.3 0.26 ;
+    END
+  END A_BIST_BM[3]
+  PIN A_DOUT[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 339.675 0 339.935 0.26 ;
+    END
+  END A_DOUT[12]
+  PIN A_DOUT[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 76.705 0 76.965 0.26 ;
+    END
+  END A_DOUT[3]
+  PIN A_DIN[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 357.41 0 357.67 0.26 ;
+    END
+  END A_DIN[13]
+  PIN A_DIN[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 58.97 0 59.23 0.26 ;
+    END
+  END A_DIN[2]
+  PIN A_BIST_DIN[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 355.88 0 356.14 0.26 ;
+    END
+  END A_BIST_DIN[13]
+  PIN A_BIST_DIN[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 60.5 0 60.76 0.26 ;
+    END
+  END A_BIST_DIN[2]
+  PIN A_BM[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 361.29 0 361.55 0.26 ;
+    END
+  END A_BM[13]
+  PIN A_BM[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 55.09 0 55.35 0.26 ;
+    END
+  END A_BM[2]
+  PIN A_BIST_BM[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 362.82 0 363.08 0.26 ;
+    END
+  END A_BIST_BM[13]
+  PIN A_BIST_BM[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 53.56 0 53.82 0.26 ;
+    END
+  END A_BIST_BM[2]
+  PIN A_DOUT[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 362.155 0 362.415 0.26 ;
+    END
+  END A_DOUT[13]
+  PIN A_DOUT[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 54.225 0 54.485 0.26 ;
+    END
+  END A_DOUT[2]
+  PIN A_DIN[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 379.89 0 380.15 0.26 ;
+    END
+  END A_DIN[14]
+  PIN A_DIN[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 36.49 0 36.75 0.26 ;
+    END
+  END A_DIN[1]
+  PIN A_BIST_DIN[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 378.36 0 378.62 0.26 ;
+    END
+  END A_BIST_DIN[14]
+  PIN A_BIST_DIN[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 38.02 0 38.28 0.26 ;
+    END
+  END A_BIST_DIN[1]
+  PIN A_BM[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 383.77 0 384.03 0.26 ;
+    END
+  END A_BM[14]
+  PIN A_BM[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 32.61 0 32.87 0.26 ;
+    END
+  END A_BM[1]
+  PIN A_BIST_BM[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 385.3 0 385.56 0.26 ;
+    END
+  END A_BIST_BM[14]
+  PIN A_BIST_BM[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 31.08 0 31.34 0.26 ;
+    END
+  END A_BIST_BM[1]
+  PIN A_DOUT[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 384.635 0 384.895 0.26 ;
+    END
+  END A_DOUT[14]
+  PIN A_DOUT[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 31.745 0 32.005 0.26 ;
+    END
+  END A_DOUT[1]
+  PIN A_DIN[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 402.37 0 402.63 0.26 ;
+    END
+  END A_DIN[15]
+  PIN A_DIN[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 14.01 0 14.27 0.26 ;
+    END
+  END A_DIN[0]
+  PIN A_BIST_DIN[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 400.84 0 401.1 0.26 ;
+    END
+  END A_BIST_DIN[15]
+  PIN A_BIST_DIN[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 15.54 0 15.8 0.26 ;
+    END
+  END A_BIST_DIN[0]
+  PIN A_BM[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 406.25 0 406.51 0.26 ;
+    END
+  END A_BM[15]
+  PIN A_BM[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 10.13 0 10.39 0.26 ;
+    END
+  END A_BM[0]
+  PIN A_BIST_BM[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 407.78 0 408.04 0.26 ;
+    END
+  END A_BIST_BM[15]
+  PIN A_BIST_BM[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 8.6 0 8.86 0.26 ;
+    END
+  END A_BIST_BM[0]
+  PIN A_DOUT[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 407.115 0 407.375 0.26 ;
+    END
+  END A_DOUT[15]
+  PIN A_DOUT[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 9.265 0 9.525 0.26 ;
+    END
+  END A_DOUT[0]
+  PIN A_ADDR[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 6.7171 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 34.349515 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 204.52 0 204.78 0.26 ;
+    END
+  END A_ADDR[0]
+  PIN A_BIST_ADDR[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 7.5127 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 38.31068 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 209.11 0 209.37 0.26 ;
+    END
+  END A_BIST_ADDR[0]
+  PIN A_ADDR[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 5.59 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 28.783172 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 204.01 0 204.27 0.26 ;
+    END
+  END A_ADDR[1]
+  PIN A_BIST_ADDR[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 6.3856 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 32.744337 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 208.6 0 208.86 0.26 ;
+    END
+  END A_BIST_ADDR[1]
+  PIN A_ADDR[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 6.4519 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 33.029126 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 189.73 0 189.99 0.26 ;
+    END
+  END A_ADDR[2]
+  PIN A_BIST_ADDR[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 6.1867 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 31.708738 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 191.26 0 191.52 0.26 ;
+    END
+  END A_BIST_ADDR[2]
+  PIN A_ADDR[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 8.4487 LAYER Metal2 ;
+    ANTENNAPARTIALMETALAREA 1.5246 LAYER Metal3 ;
+    ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal3 ;
+      ANTENNAMAXAREACAR 9.415982 LAYER Metal3 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 212.17 0 212.43 0.26 ;
+    END
+  END A_ADDR[3]
+  PIN A_BIST_ADDR[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 8.4487 LAYER Metal2 ;
+    ANTENNAPARTIALMETALAREA 1.0962 LAYER Metal3 ;
+    ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal3 ;
+      ANTENNAMAXAREACAR 7.813791 LAYER Metal3 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 212.68 0 212.94 0.26 ;
+    END
+  END A_BIST_ADDR[3]
+  PIN A_ADDR[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 8.4487 LAYER Metal2 ;
+    ANTENNAPARTIALMETALAREA 3.8367 LAYER Metal3 ;
+    ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal3 ;
+      ANTENNAMAXAREACAR 20.927558 LAYER Metal3 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 211.15 0 211.41 0.26 ;
+    END
+  END A_ADDR[4]
+  PIN A_BIST_ADDR[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 8.4487 LAYER Metal2 ;
+    ANTENNAPARTIALMETALAREA 3.5175 LAYER Metal3 ;
+    ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal3 ;
+      ANTENNAMAXAREACAR 19.869057 LAYER Metal3 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 211.66 0 211.92 0.26 ;
+    END
+  END A_BIST_ADDR[4]
+  PIN A_ADDR[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 10.0139 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 50.763754 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 214.72 0 214.98 0.26 ;
+    END
+  END A_ADDR[5]
+  PIN A_BIST_ADDR[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 9.7487 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 49.443366 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 214.21 0 214.47 0.26 ;
+    END
+  END A_BIST_ADDR[5]
+  PIN A_ADDR[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 11.7429 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 59.372168 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 213.7 0 213.96 0.26 ;
+    END
+  END A_ADDR[6]
+  PIN A_BIST_ADDR[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 11.4777 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 58.05178 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 213.19 0 213.45 0.26 ;
+    END
+  END A_BIST_ADDR[6]
+  PIN A_ADDR[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 8.7685 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 44.563107 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 192.28 0 192.54 0.26 ;
+    END
+  END A_ADDR[7]
+  PIN A_BIST_ADDR[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 8.4931 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 43.191934 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 192.79 0 193.05 0.26 ;
+    END
+  END A_BIST_ADDR[7]
+  PIN A_ADDR[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 10.2323 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 51.851133 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 193.3 0 193.56 0.26 ;
+    END
+  END A_ADDR[8]
+  PIN A_BIST_ADDR[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 9.9671 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 50.530744 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 193.81 0 194.07 0.26 ;
+    END
+  END A_BIST_ADDR[8]
+  PIN A_ADDR[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 7.9183 LAYER Metal2 ;
+    ANTENNAPARTIALMETALAREA 1.5897 LAYER Metal3 ;
+    ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal3 ;
+      ANTENNAMAXAREACAR 9.740105 LAYER Metal3 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 222.37 0 222.63 0.26 ;
+    END
+  END A_ADDR[9]
+  PIN A_BIST_ADDR[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 7.9183 LAYER Metal2 ;
+    ANTENNAPARTIALMETALAREA 1.3755 LAYER Metal3 ;
+    ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal3 ;
+      ANTENNAMAXAREACAR 9.204381 LAYER Metal3 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 222.88 0 223.14 0.26 ;
+    END
+  END A_BIST_ADDR[9]
+  PIN A_ADDR[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 10.6097 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 53.730147 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 217.27 0 217.53 0.26 ;
+    END
+  END A_ADDR[10]
+  PIN A_BIST_ADDR[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 10.3547 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 52.460543 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 217.78 0 218.04 0.26 ;
+    END
+  END A_BIST_ADDR[10]
+  PIN A_ADDR[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 8.6359 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 43.902913 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 215.23 0 215.49 0.26 ;
+    END
+  END A_ADDR[11]
+  PIN A_BIST_ADDR[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 8.6359 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 43.902913 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 215.74 0 216 0.26 ;
+    END
+  END A_BIST_ADDR[11]
+  PIN A_CLK
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.8707 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 10.220065 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 202.48 0 202.74 0.26 ;
+    END
+  END A_CLK
+  PIN A_REN
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.81105 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.923077 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 206.05 0 206.31 0.26 ;
+    END
+  END A_REN
+  PIN A_WEN
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 205.54 0 205.8 0.26 ;
+    END
+  END A_WEN
+  PIN A_MEN
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.8407 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 5.09186 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 202.99 0 203.25 0.26 ;
+    END
+  END A_MEN
+  PIN A_DLY
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 3.874 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.3367 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 12.046332 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 224.41 0 224.67 0.26 ;
+    END
+  END A_DLY
+  PIN A_BIST_EN
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.8031 LAYER Metal2 ;
+    ANTENNAPARTIALMETALAREA 119.45135 LAYER Metal3 ;
+    ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 1.43 LAYER Metal2 ;
+      ANTENNAGATEAREA 17.16 LAYER Metal3 ;
+      ANTENNAMAXAREACAR 1.686364 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 13.900125 LAYER Metal3 ;
+      ANTENNAMAXCUTCAR 0.151469 LAYER Via2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 205.03 0 205.29 0.26 ;
+    END
+  END A_BIST_EN
+  PIN A_BIST_CLK
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.9799 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 11.079661 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 200.95 0 201.21 0.26 ;
+    END
+  END A_BIST_CLK
+  PIN A_BIST_REN
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.9279 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 10.820762 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 207.58 0 207.84 0.26 ;
+    END
+  END A_BIST_REN
+  PIN A_BIST_WEN
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7211 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.812298 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 207.07 0 207.33 0.26 ;
+    END
+  END A_BIST_WEN
+  PIN A_BIST_MEN
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7137 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.775454 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 201.46 0 201.72 0.26 ;
+    END
+  END A_BIST_MEN
+  OBS
+    LAYER Metal1 ;
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+    LAYER Metal2 ;
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+      RECT 86.01 0 88.3 618.3 ;
+  END
+END RM_IHPSG13_1P_4096x16_c3_bm_bist
+
+END LIBRARY
diff --git a/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_4096x8_c3_bm_bist.lef b/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_4096x8_c3_bm_bist.lef
new file mode 100644
index 00000000..480ef1d0
--- /dev/null
+++ b/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_4096x8_c3_bm_bist.lef
@@ -0,0 +1,1774 @@
+# ------------------------------------------------------
+#
+#		Copyright 2024 IHP PDK Authors
+#
+#		Licensed under the Apache License, Version 2.0 (the "License");
+#		you may not use this file except in compliance with the License.
+#		You may obtain a copy of the License at
+#		
+#		   https://www.apache.org/licenses/LICENSE-2.0
+#		
+#		Unless required by applicable law or agreed to in writing, software
+#		distributed under the License is distributed on an "AS IS" BASIS,
+#		WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#		See the License for the specific language governing permissions and
+#		limitations under the License.
+#		
+#		Generated on Fri Jul 19 08:59:31 2024		
+#
+# ------------------------------------------------------ 
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+
+MACRO RM_IHPSG13_1P_4096x8_c3_bm_bist
+  CLASS BLOCK ;
+  ORIGIN 0 0 ;
+  FOREIGN RM_IHPSG13_1P_4096x8_c3_bm_bist 0 0 ;
+  SIZE 236.8 BY 618.3 ;
+  SYMMETRY X Y R90 ;
+  PIN A_DIN[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 155.09 0 155.35 0.26 ;
+    END
+  END A_DIN[4]
+  PIN A_DIN[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 81.45 0 81.71 0.26 ;
+    END
+  END A_DIN[3]
+  PIN A_BIST_DIN[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 153.56 0 153.82 0.26 ;
+    END
+  END A_BIST_DIN[4]
+  PIN A_BIST_DIN[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 82.98 0 83.24 0.26 ;
+    END
+  END A_BIST_DIN[3]
+  PIN A_BM[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 158.97 0 159.23 0.26 ;
+    END
+  END A_BM[4]
+  PIN A_BM[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 77.57 0 77.83 0.26 ;
+    END
+  END A_BM[3]
+  PIN A_BIST_BM[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 160.5 0 160.76 0.26 ;
+    END
+  END A_BIST_BM[4]
+  PIN A_BIST_BM[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 76.04 0 76.3 0.26 ;
+    END
+  END A_BIST_BM[3]
+  PIN A_DOUT[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 159.835 0 160.095 0.26 ;
+    END
+  END A_DOUT[4]
+  PIN A_DOUT[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 76.705 0 76.965 0.26 ;
+    END
+  END A_DOUT[3]
+  PIN VSS!
+    DIRECTION INOUT ;
+    USE GROUND ;
+    NETEXPR "vss VSS!" ;
+    PORT
+      LAYER Metal4 ;
+        RECT 224.11 0 226.92 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 212.87 0 215.68 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 201.63 0 204.44 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 190.39 0 193.2 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 179.15 0 181.96 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 167.91 0 170.72 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 156.67 0 159.48 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 145.43 0 148.24 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 135.02 0 137.83 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 124.72 0 127.53 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 109.27 0 112.08 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 98.97 0 101.78 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 88.56 0 91.37 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 77.32 0 80.13 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 66.08 0 68.89 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 54.84 0 57.65 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 43.6 0 46.41 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 32.36 0 35.17 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 21.12 0 23.93 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 9.88 0 12.69 618.3 ;
+    END
+  END VSS!
+  PIN VDD!
+    DIRECTION INOUT ;
+    USE POWER ;
+    NETEXPR "vdd VDD!" ;
+    PORT
+      LAYER Metal4 ;
+        RECT 229.73 0 232.54 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 218.49 0 221.3 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 207.25 0 210.06 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 196.01 0 198.82 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 184.77 0 187.58 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 173.53 0 176.34 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 162.29 0 165.1 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 151.05 0 153.86 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 129.87 0 132.68 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 119.57 0 122.38 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 114.42 0 117.23 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 104.12 0 106.93 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 82.94 0 85.75 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 71.7 0 74.51 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 60.46 0 63.27 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 49.22 0 52.03 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 37.98 0 40.79 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 26.74 0 29.55 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 15.5 0 18.31 30.425 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 4.26 0 7.07 30.425 ;
+    END
+  END VDD!
+  PIN VDDARRAY!
+    DIRECTION INOUT ;
+    USE POWER ;
+    NETEXPR "vddarray VDDARRAY!" ;
+    PORT
+      LAYER Metal4 ;
+        RECT 229.73 37.065 232.54 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 218.49 37.065 221.3 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 207.25 37.065 210.06 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 196.01 37.065 198.82 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 184.77 37.065 187.58 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 173.53 37.065 176.34 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 162.29 37.065 165.1 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 151.05 37.065 153.86 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 82.94 37.065 85.75 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 71.7 37.065 74.51 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 60.46 37.065 63.27 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 49.22 37.065 52.03 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 37.98 37.065 40.79 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 26.74 37.065 29.55 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 15.5 37.065 18.31 618.3 ;
+    END
+    PORT
+      LAYER Metal4 ;
+        RECT 4.26 37.065 7.07 618.3 ;
+    END
+  END VDDARRAY!
+  PIN A_DIN[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 177.57 0 177.83 0.26 ;
+    END
+  END A_DIN[5]
+  PIN A_DIN[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 58.97 0 59.23 0.26 ;
+    END
+  END A_DIN[2]
+  PIN A_BIST_DIN[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 176.04 0 176.3 0.26 ;
+    END
+  END A_BIST_DIN[5]
+  PIN A_BIST_DIN[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 60.5 0 60.76 0.26 ;
+    END
+  END A_BIST_DIN[2]
+  PIN A_BM[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 181.45 0 181.71 0.26 ;
+    END
+  END A_BM[5]
+  PIN A_BM[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 55.09 0 55.35 0.26 ;
+    END
+  END A_BM[2]
+  PIN A_BIST_BM[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 182.98 0 183.24 0.26 ;
+    END
+  END A_BIST_BM[5]
+  PIN A_BIST_BM[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 53.56 0 53.82 0.26 ;
+    END
+  END A_BIST_BM[2]
+  PIN A_DOUT[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 182.315 0 182.575 0.26 ;
+    END
+  END A_DOUT[5]
+  PIN A_DOUT[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 54.225 0 54.485 0.26 ;
+    END
+  END A_DOUT[2]
+  PIN A_DIN[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 200.05 0 200.31 0.26 ;
+    END
+  END A_DIN[6]
+  PIN A_DIN[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 36.49 0 36.75 0.26 ;
+    END
+  END A_DIN[1]
+  PIN A_BIST_DIN[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 198.52 0 198.78 0.26 ;
+    END
+  END A_BIST_DIN[6]
+  PIN A_BIST_DIN[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 38.02 0 38.28 0.26 ;
+    END
+  END A_BIST_DIN[1]
+  PIN A_BM[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 203.93 0 204.19 0.26 ;
+    END
+  END A_BM[6]
+  PIN A_BM[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 32.61 0 32.87 0.26 ;
+    END
+  END A_BM[1]
+  PIN A_BIST_BM[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 205.46 0 205.72 0.26 ;
+    END
+  END A_BIST_BM[6]
+  PIN A_BIST_BM[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 31.08 0 31.34 0.26 ;
+    END
+  END A_BIST_BM[1]
+  PIN A_DOUT[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 204.795 0 205.055 0.26 ;
+    END
+  END A_DOUT[6]
+  PIN A_DOUT[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 31.745 0 32.005 0.26 ;
+    END
+  END A_DOUT[1]
+  PIN A_DIN[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 222.53 0 222.79 0.26 ;
+    END
+  END A_DIN[7]
+  PIN A_DIN[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 14.01 0 14.27 0.26 ;
+    END
+  END A_DIN[0]
+  PIN A_BIST_DIN[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 221 0 221.26 0.26 ;
+    END
+  END A_BIST_DIN[7]
+  PIN A_BIST_DIN[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 15.54 0 15.8 0.26 ;
+    END
+  END A_BIST_DIN[0]
+  PIN A_BM[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 226.41 0 226.67 0.26 ;
+    END
+  END A_BM[7]
+  PIN A_BM[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 10.13 0 10.39 0.26 ;
+    END
+  END A_BM[0]
+  PIN A_BIST_BM[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 227.94 0 228.2 0.26 ;
+    END
+  END A_BIST_BM[7]
+  PIN A_BIST_BM[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 8.6 0 8.86 0.26 ;
+    END
+  END A_BIST_BM[0]
+  PIN A_DOUT[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 227.275 0 227.535 0.26 ;
+    END
+  END A_DOUT[7]
+  PIN A_DOUT[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 2.0345 LAYER Metal2 ;
+    ANTENNADIFFAREA 0.988 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 9.265 0 9.525 0.26 ;
+    END
+  END A_DOUT[0]
+  PIN A_ADDR[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 6.7171 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 34.349515 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 114.6 0 114.86 0.26 ;
+    END
+  END A_ADDR[0]
+  PIN A_BIST_ADDR[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 7.5127 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 38.31068 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 119.19 0 119.45 0.26 ;
+    END
+  END A_BIST_ADDR[0]
+  PIN A_ADDR[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 5.59 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 28.783172 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 114.09 0 114.35 0.26 ;
+    END
+  END A_ADDR[1]
+  PIN A_BIST_ADDR[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 6.3856 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 32.744337 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 118.68 0 118.94 0.26 ;
+    END
+  END A_BIST_ADDR[1]
+  PIN A_ADDR[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 6.4519 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 33.029126 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 99.81 0 100.07 0.26 ;
+    END
+  END A_ADDR[2]
+  PIN A_BIST_ADDR[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 6.1867 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 31.708738 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 101.34 0 101.6 0.26 ;
+    END
+  END A_BIST_ADDR[2]
+  PIN A_ADDR[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 8.4487 LAYER Metal2 ;
+    ANTENNAPARTIALMETALAREA 1.5246 LAYER Metal3 ;
+    ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal3 ;
+      ANTENNAMAXAREACAR 9.415982 LAYER Metal3 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 122.25 0 122.51 0.26 ;
+    END
+  END A_ADDR[3]
+  PIN A_BIST_ADDR[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 8.4487 LAYER Metal2 ;
+    ANTENNAPARTIALMETALAREA 1.0962 LAYER Metal3 ;
+    ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal3 ;
+      ANTENNAMAXAREACAR 7.813791 LAYER Metal3 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 122.76 0 123.02 0.26 ;
+    END
+  END A_BIST_ADDR[3]
+  PIN A_ADDR[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 8.4487 LAYER Metal2 ;
+    ANTENNAPARTIALMETALAREA 3.8367 LAYER Metal3 ;
+    ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal3 ;
+      ANTENNAMAXAREACAR 20.927558 LAYER Metal3 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 121.23 0 121.49 0.26 ;
+    END
+  END A_ADDR[4]
+  PIN A_BIST_ADDR[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 8.4487 LAYER Metal2 ;
+    ANTENNAPARTIALMETALAREA 3.5175 LAYER Metal3 ;
+    ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal3 ;
+      ANTENNAMAXAREACAR 19.869057 LAYER Metal3 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 121.74 0 122 0.26 ;
+    END
+  END A_BIST_ADDR[4]
+  PIN A_ADDR[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 10.0139 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 50.763754 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 124.8 0 125.06 0.26 ;
+    END
+  END A_ADDR[5]
+  PIN A_BIST_ADDR[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 9.7487 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 49.443366 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 124.29 0 124.55 0.26 ;
+    END
+  END A_BIST_ADDR[5]
+  PIN A_ADDR[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 11.7429 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 59.372168 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 123.78 0 124.04 0.26 ;
+    END
+  END A_ADDR[6]
+  PIN A_BIST_ADDR[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 11.4777 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 58.05178 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 123.27 0 123.53 0.26 ;
+    END
+  END A_BIST_ADDR[6]
+  PIN A_ADDR[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 8.7685 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 44.563107 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 102.36 0 102.62 0.26 ;
+    END
+  END A_ADDR[7]
+  PIN A_BIST_ADDR[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 8.4931 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 43.191934 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 102.87 0 103.13 0.26 ;
+    END
+  END A_BIST_ADDR[7]
+  PIN A_ADDR[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 10.2323 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 51.851133 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 103.38 0 103.64 0.26 ;
+    END
+  END A_ADDR[8]
+  PIN A_BIST_ADDR[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 9.9671 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 50.530744 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 103.89 0 104.15 0.26 ;
+    END
+  END A_BIST_ADDR[8]
+  PIN A_ADDR[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 7.9183 LAYER Metal2 ;
+    ANTENNAPARTIALMETALAREA 1.5897 LAYER Metal3 ;
+    ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal3 ;
+      ANTENNAMAXAREACAR 9.740105 LAYER Metal3 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 132.45 0 132.71 0.26 ;
+    END
+  END A_ADDR[9]
+  PIN A_BIST_ADDR[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 7.9183 LAYER Metal2 ;
+    ANTENNAPARTIALMETALAREA 1.3755 LAYER Metal3 ;
+    ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal3 ;
+      ANTENNAMAXAREACAR 9.204381 LAYER Metal3 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 132.96 0 133.22 0.26 ;
+    END
+  END A_BIST_ADDR[9]
+  PIN A_ADDR[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 10.6097 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 53.730147 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 127.35 0 127.61 0.26 ;
+    END
+  END A_ADDR[10]
+  PIN A_BIST_ADDR[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 10.3547 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 52.460543 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 127.86 0 128.12 0.26 ;
+    END
+  END A_BIST_ADDR[10]
+  PIN A_ADDR[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 8.6359 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 43.902913 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 125.31 0 125.57 0.26 ;
+    END
+  END A_ADDR[11]
+  PIN A_BIST_ADDR[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 8.6359 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 43.902913 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 125.82 0 126.08 0.26 ;
+    END
+  END A_BIST_ADDR[11]
+  PIN A_CLK
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.8707 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 10.220065 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 112.56 0 112.82 0.26 ;
+    END
+  END A_CLK
+  PIN A_REN
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.81105 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 9.923077 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 116.13 0 116.39 0.26 ;
+    END
+  END A_REN
+  PIN A_WEN
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7007 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.394822 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 115.62 0 115.88 0.26 ;
+    END
+  END A_WEN
+  PIN A_MEN
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.8407 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 5.09186 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 113.07 0 113.33 0.26 ;
+    END
+  END A_MEN
+  PIN A_DLY
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 3.874 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.3367 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 12.046332 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 134.49 0 134.75 0.26 ;
+    END
+  END A_DLY
+  PIN A_BIST_EN
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.8031 LAYER Metal2 ;
+    ANTENNAPARTIALMETALAREA 72.69295 LAYER Metal3 ;
+    ANTENNAPARTIALCUTAREA 0.0722 LAYER Via2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 1.43 LAYER Metal2 ;
+      ANTENNAGATEAREA 11.44 LAYER Metal3 ;
+      ANTENNAMAXAREACAR 1.686364 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 13.29337 LAYER Metal3 ;
+      ANTENNAMAXCUTCAR 0.151469 LAYER Via2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 115.11 0 115.37 0.26 ;
+    END
+  END A_BIST_EN
+  PIN A_BIST_CLK
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.9799 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 11.079661 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 111.03 0 111.29 0.26 ;
+    END
+  END A_BIST_CLK
+  PIN A_BIST_REN
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 1.9279 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 10.820762 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 117.66 0 117.92 0.26 ;
+    END
+  END A_BIST_REN
+  PIN A_BIST_WEN
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7211 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.812298 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 117.15 0 117.41 0.26 ;
+    END
+  END A_BIST_WEN
+  PIN A_BIST_MEN
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    ANTENNAPARTIALMETALAREA 0.7137 LAYER Metal2 ;
+    ANTENNAMODEL OXIDE1 ;
+      ANTENNAGATEAREA 0.20085 LAYER Metal2 ;
+      ANTENNAMAXAREACAR 4.775454 LAYER Metal2 ;
+    PORT
+      LAYER Metal2 ;
+        RECT 111.54 0 111.8 0.26 ;
+    END
+  END A_BIST_MEN
+  OBS
+    LAYER Metal1 ;
+      RECT 0 0 236.8 618.3 ;
+    LAYER Metal2 ;
+      RECT 0.105 37.065 0.305 618.275 ;
+      RECT 1.1 617.545 1.3 618.275 ;
+      RECT 1.92 617.545 2.12 618.275 ;
+      RECT 2.415 617.545 2.615 618.275 ;
+      RECT 2.915 617.545 3.115 618.275 ;
+      RECT 3.415 617.545 3.615 618.275 ;
+      RECT 3.91 617.545 4.11 618.275 ;
+      RECT 4.73 617.545 4.93 618.275 ;
+      RECT 5.225 617.545 5.425 618.275 ;
+      RECT 5.725 617.545 5.925 618.275 ;
+      RECT 7.225 0.17 7.995 0.43 ;
+      RECT 7.225 0.17 7.485 11.38 ;
+      RECT 7.735 0.17 7.995 17.1 ;
+      RECT 6.225 617.545 6.425 618.275 ;
+      RECT 6.72 617.545 6.92 618.275 ;
+      RECT 7.54 617.545 7.74 618.275 ;
+      RECT 8.035 617.545 8.235 618.275 ;
+      RECT 8.535 617.545 8.735 618.275 ;
+      RECT 8.6 0.52 8.86 2.255 ;
+      RECT 9.035 617.545 9.235 618.275 ;
+      RECT 9.265 0.52 9.525 8.085 ;
+      RECT 9.53 617.545 9.73 618.275 ;
+      RECT 10.13 0.52 10.39 1.5 ;
+      RECT 10.35 617.545 10.55 618.275 ;
+      RECT 10.845 617.545 11.045 618.275 ;
+      RECT 11.345 617.545 11.545 618.275 ;
+      RECT 11.845 617.545 12.045 618.275 ;
+      RECT 12.34 617.545 12.54 618.275 ;
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+      RECT 14.01 0.52 14.27 2.255 ;
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+      RECT 15.15 617.545 15.35 618.275 ;
+      RECT 16.255 0.8 17.025 1.57 ;
+      RECT 16.255 0.3 16.515 13.03 ;
+      RECT 16.765 0.3 17.025 13.03 ;
+      RECT 15.54 0.52 15.8 2.255 ;
+      RECT 15.97 617.545 16.17 618.275 ;
+      RECT 16.465 617.545 16.665 618.275 ;
+      RECT 16.965 617.545 17.165 618.275 ;
+      RECT 17.465 617.545 17.665 618.275 ;
+      RECT 17.96 617.545 18.16 618.275 ;
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+      RECT 20.485 0.17 20.745 13.055 ;
+      RECT 19.275 617.545 19.475 618.275 ;
+      RECT 19.775 617.545 19.975 618.275 ;
+      RECT 20.275 617.545 20.475 618.275 ;
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+      RECT 21.59 617.545 21.79 618.275 ;
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+      RECT 52.29 0 54.58 618.3 ;
+      RECT 46.67 0 48.96 618.3 ;
+      RECT 46.67 30.685 54.58 36.805 ;
+      RECT 41.05 0 43.34 618.3 ;
+      RECT 35.43 0 37.72 618.3 ;
+      RECT 35.43 30.685 43.34 36.805 ;
+      RECT 29.81 0 32.1 618.3 ;
+      RECT 24.19 0 26.48 618.3 ;
+  END
+END RM_IHPSG13_1P_4096x8_c3_bm_bist
+
+END LIBRARY
diff --git a/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_1024x16_c2_bm_bist_fast_1p32V_m55C.lib b/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_1024x16_c2_bm_bist_fast_1p32V_m55C.lib
new file mode 100644
index 00000000..dbe648f0
--- /dev/null
+++ b/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_1024x16_c2_bm_bist_fast_1p32V_m55C.lib
@@ -0,0 +1,1525 @@
+/* ------------------------------------------------------*/
+/**/
+/*		Copyright 2024 IHP PDK Authors*/
+/**/
+/*		Licensed under the Apache License, Version 2.0 (the "License");*/
+/*		you may not use this file except in compliance with the License.*/
+/*		You may obtain a copy of the License at*/
+/*		*/
+/*		   https://www.apache.org/licenses/LICENSE-2.0*/
+/*		*/
+/*		Unless required by applicable law or agreed to in writing, software*/
+/*		distributed under the License is distributed on an "AS IS" BASIS,*/
+/*		WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/
+/*		See the License for the specific language governing permissions and*/
+/*		limitations under the License.*/
+/*		*/
+/*		Generated on Fri Jul 19 08:58:02 2024		*/
+/*				*/
+/* ------------------------------------------------------ */
+library(RM_IHPSG13_1P_1024x16_c2_bm_bist_fast_1p32V_m55C) {	
+	technology (cmos) ;
+	delay_model : table_lookup ;
+	define ("add_pg_pin_to_lib",  "library",  "boolean");
+	add_pg_pin_to_lib : true;
+	voltage_map ( VDD, 1.32);
+	voltage_map ( VDDARRAY, 1.32);
+	voltage_map ( VSS, 0.000000 );
+	
+	date            : "Fri Jul 19 08:58:00 2024" ;
+	comment         : "IHP Microelectronics GmbH, 2024" ;
+	revision        : 1.0.0 ;
+	simulation      : true ;
+	nom_process     : 1 ;
+	nom_temperature : -55 ;
+	nom_voltage     : 1.32 ;
+	
+	operating_conditions("fast_1p32V_m55C"){
+	    process     : 1 ;
+	    temperature : -55 ;
+	    voltage     : 1.32 ;
+	    tree_type   : "balanced_tree" ;
+	}
+	
+	default_operating_conditions  : fast_1p32V_m55C ;
+	default_max_transition        : 1.0 ;
+	default_fanout_load           : 1.0 ;
+	default_inout_pin_cap         : 0.0 ;
+	default_input_pin_cap         : 0.0 ;
+	default_output_pin_cap        : 0.0 ;
+	default_cell_leakage_power    : 0.0 ;
+	default_leakage_power_density : 0.0 ;
+	 
+	slew_lower_threshold_pct_rise : 30 ;
+	slew_upper_threshold_pct_rise : 70 ;
+	input_threshold_pct_fall      : 50 ;
+	output_threshold_pct_fall     : 50 ;
+	input_threshold_pct_rise      : 50 ;
+	output_threshold_pct_rise     : 50 ;
+	slew_lower_threshold_pct_fall : 30 ;
+	slew_upper_threshold_pct_fall : 70 ;
+	slew_derate_from_library      : 0.5;
+	k_volt_cell_leakage_power     : 0.0 ;
+	k_temp_cell_leakage_power     : 0.0 ;
+	k_process_cell_leakage_power  : 0.0 ;
+	k_volt_internal_power         : 0.0 ;
+	k_temp_internal_power         : 0.0 ;
+	k_process_internal_power      : 0.0 ;
+	
+	capacitive_load_unit            (1,pf) ;
+	voltage_unit                  : "1V" ;
+	current_unit                  : "1uA" ;
+	time_unit                     : "1ns" ;
+	leakage_power_unit            : "1nW" ;
+	pulling_resistance_unit       : "1kohm";
+	/*
+	  ------------------------------------------------------------------------------------------
+	  implicit units overview:
+	    cell_area       unit      : "um"
+	    internal_power  unit      : "1e-12 * J/toggle = 1 * uW/MHz"
+	                                (capacitive_load_unit * voltage_unit^2) per toggle event
+	  ------------------------------------------------------------------------------------------
+	*/
+	library_features(report_delay_calculation);
+	define_cell_area (pad_drivers,pad_driver_sites) ;
+	
+	lu_table_template(CLKTRAN_constraint_template) {
+	     variable_1 : constrained_pin_transition;
+	     index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" );
+	}
+	lu_table_template(SRAM_load_template) {
+	     variable_1 : total_output_net_capacitance;
+	     index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" );
+	}
+	lu_table_template(SIG2SRAM_constraint_template) {
+	     variable_1 : related_pin_transition;
+	     variable_2 : constrained_pin_transition;
+	     index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" );
+	     index_2 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" );
+	}
+	
+	lu_table_template(SIG2SRAM_delay_template) {
+	     variable_1 : input_net_transition;
+	     variable_2 : total_output_net_capacitance;
+	     index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" );
+	     index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" );
+	} 
+
+	type (D_15_0) {
+		base_type : array;
+		data_type : bit;
+		bit_width : 16;
+		bit_from  : 15;
+		bit_to    : 0;
+		downto    : true;
+	 }
+
+	type (A_9_0) {
+		base_type : array;
+		data_type : bit;
+		bit_width : 10;
+		bit_from  : 9;
+		bit_to    : 0;
+		downto    : true;
+	 }
+
+cell(RM_IHPSG13_1P_1024x16_c2_bm_bist) {
+pg_pin (VDD) {
+  pg_type : primary_power;
+  voltage_name : VDD;
+}
+pg_pin (VDDARRAY) {
+  pg_type : primary_power;
+  voltage_name : VDDARRAY;
+}
+pg_pin (VSS) {
+  pg_type : primary_ground;
+  voltage_name : VSS;
+}
+
+memory() {
+ type : ram;
+ address_width : 10;
+ word_width : 16;
+}
+
+interface_timing : false;
+bus_naming_style    :   "%s[%d]" ;
+area        : 79673.728 ;
+
+   pin(A_DLY) {
+	   direction       : input ;
+	   capacitance     : 0.00421562 ;
+	   max_transition  : "1" ;
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+		internal_power() {
+		  rise_power("scalar") {
+			 values (0);
+		  }
+		  fall_power("scalar") {
+			 values (0);
+		  }
+	   }
+   }
+
+bus(A_ADDR) {
+   bus_type : A_9_0;
+   direction          : input ;
+   capacitance        : 0.00691085 ;
+    pin(A_ADDR[0]) {
+       capacitance : 0.00562034 ;
+    }
+    pin(A_ADDR[1]) {
+       capacitance : 0.00462655 ;
+    }
+    pin(A_ADDR[2]) {
+       capacitance : 0.00594295 ;
+    }
+    pin(A_ADDR[3]) {
+       capacitance : 0.00723434 ;
+    }
+    pin(A_ADDR[4]) {
+       capacitance : 0.00481603 ;
+    }
+    pin(A_ADDR[5]) {
+       capacitance : 0.00868123 ;
+    }
+    pin(A_ADDR[6]) {
+       capacitance : 0.010187 ;
+    }
+    pin(A_ADDR[7]) {
+       capacitance : 0.00734489 ;
+    }
+    pin(A_ADDR[8]) {
+       capacitance : 0.00904175 ;
+    }
+   max_transition     : "0.38" ;
+   pin(A_ADDR[9:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.2111);
+		}
+		        fall_power("scalar"){
+		 values (0.2703);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0286);
+		}
+		        fall_power("scalar"){
+		 values (0.0026);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "((A_WEN | A_REN)& A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\
+"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\
+"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\
+"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\
+"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\
+"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\
+"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\
+"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\
+"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\
+"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\
+"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\
+"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\
+"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "((A_WEN | A_REN)& A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\
+"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\
+"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\
+"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\
+"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\
+"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\
+"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\
+"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\
+"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\
+"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\
+"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\
+"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\
+"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902");
+		}
+	}
+}
+pin(A_WEN) {
+   direction          : input ;
+   capacitance        : 0.00341384 ;
+   max_transition     : "0.38" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.4060);
+		}
+		        fall_power("scalar"){
+		 values (0.0178);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0063);
+		}
+		        fall_power("scalar"){
+		 values (0.0181);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\
+"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\
+"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\
+"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\
+"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\
+"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\
+"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\
+"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\
+"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\
+"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\
+"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\
+"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\
+"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\
+"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\
+"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\
+"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\
+"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\
+"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\
+"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\
+"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\
+"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\
+"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\
+"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\
+"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\
+"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691");
+		}
+	}
+	}
+pin(A_REN) {
+   direction          : input ;
+   capacitance        : 0.00390661 ;
+   max_transition     : "0.38" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0125);
+		}
+		        fall_power("scalar"){
+		 values (0.0108);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0263);
+		}
+		        fall_power("scalar"){
+		 values (0.0211);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\
+"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\
+"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\
+"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\
+"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\
+"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\
+"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\
+"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\
+"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\
+"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\
+"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\
+"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\
+"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\
+"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\
+"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\
+"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\
+"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\
+"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\
+"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\
+"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\
+"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\
+"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\
+"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\
+"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\
+"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809");
+		}
+	}
+	}
+pin(A_MEN) {
+   direction          : input ;
+   capacitance        : 0.00326046 ;
+   max_transition     : "0.38" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		        rise_power("scalar"){
+		 values (0.1484);
+		}
+		        fall_power("scalar"){
+		 values (0.2101);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\
+"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\
+"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\
+"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\
+"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\
+"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\
+"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\
+"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\
+"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\
+"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\
+"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\
+"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\
+"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\
+"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\
+"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\
+"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\
+"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\
+"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\
+"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\
+"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\
+"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\
+"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\
+"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\
+"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\
+"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691");
+		}
+	}
+	}
+bus(A_BM) {
+   bus_type : D_15_0;
+   direction          : input ;
+   capacitance        : 0.00310985 ;
+   max_transition     : "0.38" ;
+   pin(A_BM[15:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0783);
+		}
+		        fall_power("scalar"){
+		 values (0.0812);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.1034);
+		}
+		        fall_power("scalar"){
+		 values (0.0834);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "(A_WEN & A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.1890,-0.1783,-0.1627,-0.1363,-0.0963,-0.0260,0.1088",\
+"-0.1929,-0.1822,-0.1666,-0.1402,-0.1002,-0.0298,0.1049",\
+"-0.1967,-0.1860,-0.1704,-0.1440,-0.1039,-0.0336,0.1011",\
+"-0.2000,-0.1892,-0.1736,-0.1472,-0.1072,-0.0369,0.0979",\
+"-0.2124,-0.2017,-0.1861,-0.1597,-0.1196,-0.0493,0.0854",\
+"-0.2299,-0.2191,-0.2035,-0.1771,-0.1371,-0.0668,0.0680",\
+"-0.2575,-0.2468,-0.2312,-0.2048,-0.1648,-0.0945,0.0403");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.1666,-0.1558,-0.1422,-0.1148,-0.0777,-0.0055,0.1244",\
+"-0.1705,-0.1597,-0.1461,-0.1187,-0.0816,-0.0093,0.1205",\
+"-0.1743,-0.1635,-0.1498,-0.1225,-0.0854,-0.0131,0.1167",\
+"-0.1775,-0.1668,-0.1531,-0.1258,-0.0887,-0.0164,0.1135",\
+"-0.1900,-0.1792,-0.1656,-0.1382,-0.1011,-0.0288,0.1011",\
+"-0.2074,-0.1967,-0.1830,-0.1557,-0.1186,-0.0463,0.0836",\
+"-0.2351,-0.2243,-0.2107,-0.1833,-0.1462,-0.0739,0.0559");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "(A_WEN & A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2950,0.2833,0.2686,0.2423,0.2022,0.1309,-0.0058",\
+"0.2989,0.2872,0.2725,0.2461,0.2061,0.1348,-0.0019",\
+"0.3027,0.2910,0.2763,0.2499,0.2099,0.1386,0.0019",\
+"0.3059,0.2942,0.2796,0.2532,0.2132,0.1419,0.0052",\
+"0.3184,0.3066,0.2920,0.2656,0.2256,0.1543,0.0176",\
+"0.3358,0.3241,0.3095,0.2831,0.2431,0.1718,0.0351",\
+"0.3635,0.3518,0.3371,0.3108,0.2707,0.1994,0.0627");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2667,0.2569,0.2423,0.2159,0.1788,0.1055,-0.0224",\
+"0.2706,0.2608,0.2461,0.2198,0.1827,0.1094,-0.0185",\
+"0.2744,0.2646,0.2499,0.2236,0.1865,0.1132,-0.0147",\
+"0.2776,0.2678,0.2532,0.2268,0.1897,0.1165,-0.0115",\
+"0.2900,0.2803,0.2656,0.2393,0.2022,0.1289,0.0010",\
+"0.3075,0.2978,0.2831,0.2567,0.2196,0.1464,0.0185",\
+"0.3352,0.3254,0.3108,0.2844,0.2473,0.1740,0.0461");
+		}
+	}
+}
+   pin(A_CLK)  {
+	   direction       : input;
+	   capacitance     : 0.00389386;
+	   max_transition  : "0.38";
+	   clock           : "true" ;
+	   pin_func_type   : active_rising ;
+
+	   timing () {
+		 timing_type : "min_pulse_width";
+		 related_pin : "A_CLK";
+		 rise_constraint("CLKTRAN_constraint_template") {
+		 index_1("0.004,0.38");
+		 values("0.12,0.12");
+		 }
+	   }
+
+	   related_power_pin : VDD;
+	   related_ground_pin : VSS;
+
+	internal_power() {
+		when : "!A_MEN  & !A_WEN & !A_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN  & A_WEN  & !A_REN";
+		        rise_power("scalar"){
+		 values (0.7039);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & A_WEN  & !A_REN";
+		        rise_power("scalar"){
+		 values (40.8199);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & A_WEN  & A_REN";
+		        rise_power("scalar"){
+		 values (41.5232);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & !A_WEN & A_REN";
+		        rise_power("scalar"){
+		 values (33.7892);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN & !A_WEN & A_REN";
+		        rise_power("scalar"){
+		 values (0.4120);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN & A_WEN  & A_REN";
+		        rise_power("scalar"){
+		 values (0.9290);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & !A_WEN & !A_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	}
+   bus(A_DIN) {
+	   bus_type : D_15_0;
+	   direction       : input ;
+	   capacitance     : 0.00387207 ;
+	   memory_write() {
+		   address : A_ADDR ;
+		   clocked_on : A_CLK;
+	   }
+
+	   max_transition  : "0.38" ;
+	   pin(A_DIN[15:0]) {
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0783);
+		}
+		        fall_power("scalar"){
+		 values (0.0812);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.1034);
+		}
+		        fall_power("scalar"){
+		 values (0.0834);
+		}
+	}
+	   }
+	   timing() {
+		 timing_type     : setup_rising;
+		 related_pin     : "A_CLK";
+		 when            : "(A_WEN & A_MEN)";
+		 sdf_cond        : "A_W_ACCESS";
+
+	  rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 values ("-0.1890,-0.1783,-0.1627,-0.1363,-0.0963,-0.0260,0.1088",\
+"-0.1929,-0.1822,-0.1666,-0.1402,-0.1002,-0.0298,0.1049",\
+"-0.1967,-0.1860,-0.1704,-0.1440,-0.1039,-0.0336,0.1011",\
+"-0.2000,-0.1892,-0.1736,-0.1472,-0.1072,-0.0369,0.0979",\
+"-0.2124,-0.2017,-0.1861,-0.1597,-0.1196,-0.0493,0.0854",\
+"-0.2299,-0.2191,-0.2035,-0.1771,-0.1371,-0.0668,0.0680",\
+"-0.2575,-0.2468,-0.2312,-0.2048,-0.1648,-0.0945,0.0403");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 values ("-0.1666,-0.1558,-0.1422,-0.1148,-0.0777,-0.0055,0.1244",\
+"-0.1705,-0.1597,-0.1461,-0.1187,-0.0816,-0.0093,0.1205",\
+"-0.1743,-0.1635,-0.1498,-0.1225,-0.0854,-0.0131,0.1167",\
+"-0.1775,-0.1668,-0.1531,-0.1258,-0.0887,-0.0164,0.1135",\
+"-0.1900,-0.1792,-0.1656,-0.1382,-0.1011,-0.0288,0.1011",\
+"-0.2074,-0.1967,-0.1830,-0.1557,-0.1186,-0.0463,0.0836",\
+"-0.2351,-0.2243,-0.2107,-0.1833,-0.1462,-0.0739,0.0559");
+		 }
+	   }
+
+	   timing() {
+		 timing_type     : hold_rising;
+		 related_pin     : "A_CLK";
+		 when            : "(A_WEN & A_MEN)";
+		 sdf_cond        : "A_W_ACCESS";
+
+	   rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 values ("0.2950,0.2833,0.2686,0.2423,0.2022,0.1309,-0.0058",\
+"0.2989,0.2872,0.2725,0.2461,0.2061,0.1348,-0.0019",\
+"0.3027,0.2910,0.2763,0.2499,0.2099,0.1386,0.0019",\
+"0.3059,0.2942,0.2796,0.2532,0.2132,0.1419,0.0052",\
+"0.3184,0.3066,0.2920,0.2656,0.2256,0.1543,0.0176",\
+"0.3358,0.3241,0.3095,0.2831,0.2431,0.1718,0.0351",\
+"0.3635,0.3518,0.3371,0.3108,0.2707,0.1994,0.0627");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 values ("0.2667,0.2569,0.2423,0.2159,0.1788,0.1055,-0.0224",\
+"0.2706,0.2608,0.2461,0.2198,0.1827,0.1094,-0.0185",\
+"0.2744,0.2646,0.2499,0.2236,0.1865,0.1132,-0.0147",\
+"0.2776,0.2678,0.2532,0.2268,0.1897,0.1165,-0.0115",\
+"0.2900,0.2803,0.2656,0.2393,0.2022,0.1289,0.0010",\
+"0.3075,0.2978,0.2831,0.2567,0.2196,0.1464,0.0185",\
+"0.3352,0.3254,0.3108,0.2844,0.2473,0.1740,0.0461");
+		 }
+	   }
+   }
+
+   pin(A_BIST_EN) {
+	   direction       : input ;
+	   capacitance     : 0.00421562 ;
+	   max_transition  : "1" ;
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+		internal_power() {
+		  rise_power("scalar") {
+			 values (0);
+		  }
+		  fall_power("scalar") {
+			 values (0);
+		  }
+	   }
+   }
+
+bus(A_BIST_ADDR) {
+   bus_type : A_9_0;
+   direction          : input ;
+   capacitance        : 0.00691085 ;
+    pin(A_BIST_ADDR[0]) {
+       capacitance : 0.00562034 ;
+    }
+    pin(A_BIST_ADDR[1]) {
+       capacitance : 0.00462655 ;
+    }
+    pin(A_BIST_ADDR[2]) {
+       capacitance : 0.00594295 ;
+    }
+    pin(A_BIST_ADDR[3]) {
+       capacitance : 0.00723434 ;
+    }
+    pin(A_BIST_ADDR[4]) {
+       capacitance : 0.00481603 ;
+    }
+    pin(A_BIST_ADDR[5]) {
+       capacitance : 0.00868123 ;
+    }
+    pin(A_BIST_ADDR[6]) {
+       capacitance : 0.010187 ;
+    }
+    pin(A_BIST_ADDR[7]) {
+       capacitance : 0.00734489 ;
+    }
+    pin(A_BIST_ADDR[8]) {
+       capacitance : 0.00904175 ;
+    }
+   max_transition     : "0.38" ;
+   pin(A_BIST_ADDR[9:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.2111);
+		}
+		        fall_power("scalar"){
+		 values (0.2703);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0286);
+		}
+		        fall_power("scalar"){
+		 values (0.0026);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\
+"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\
+"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\
+"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\
+"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\
+"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\
+"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\
+"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\
+"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\
+"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\
+"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\
+"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\
+"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\
+"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\
+"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\
+"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\
+"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\
+"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\
+"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\
+"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\
+"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\
+"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\
+"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\
+"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\
+"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902");
+		}
+	}
+}
+pin(A_BIST_WEN) {
+   direction          : input ;
+   capacitance        : 0.00341384 ;
+   max_transition     : "0.38" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.4060);
+		}
+		        fall_power("scalar"){
+		 values (0.0178);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0063);
+		}
+		        fall_power("scalar"){
+		 values (0.0181);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\
+"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\
+"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\
+"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\
+"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\
+"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\
+"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\
+"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\
+"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\
+"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\
+"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\
+"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\
+"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\
+"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\
+"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\
+"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\
+"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\
+"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\
+"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\
+"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\
+"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\
+"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\
+"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\
+"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\
+"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691");
+		}
+	}
+	}
+pin(A_BIST_REN) {
+   direction          : input ;
+   capacitance        : 0.00390661 ;
+   max_transition     : "0.38" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0125);
+		}
+		        fall_power("scalar"){
+		 values (0.0108);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0263);
+		}
+		        fall_power("scalar"){
+		 values (0.0211);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\
+"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\
+"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\
+"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\
+"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\
+"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\
+"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\
+"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\
+"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\
+"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\
+"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\
+"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\
+"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\
+"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\
+"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\
+"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\
+"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\
+"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\
+"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\
+"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\
+"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\
+"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\
+"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\
+"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\
+"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809");
+		}
+	}
+	}
+pin(A_BIST_MEN) {
+   direction          : input ;
+   capacitance        : 0.00326046 ;
+   max_transition     : "0.38" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		        rise_power("scalar"){
+		 values (0.1484);
+		}
+		        fall_power("scalar"){
+		 values (0.2101);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\
+"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\
+"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\
+"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\
+"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\
+"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\
+"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\
+"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\
+"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\
+"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\
+"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\
+"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\
+"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\
+"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\
+"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\
+"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\
+"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\
+"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\
+"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\
+"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\
+"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\
+"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\
+"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\
+"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\
+"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691");
+		}
+	}
+	}
+bus(A_BIST_BM) {
+   bus_type : D_15_0;
+   direction          : input ;
+   capacitance        : 0.00253457 ;
+   max_transition     : "0.38" ;
+   pin(A_BIST_BM[15:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0783);
+		}
+		        fall_power("scalar"){
+		 values (0.0812);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.1034);
+		}
+		        fall_power("scalar"){
+		 values (0.0834);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "(A_BIST_WEN & A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.1890,-0.1783,-0.1627,-0.1363,-0.0963,-0.0260,0.1088",\
+"-0.1929,-0.1822,-0.1666,-0.1402,-0.1002,-0.0298,0.1049",\
+"-0.1967,-0.1860,-0.1704,-0.1440,-0.1039,-0.0336,0.1011",\
+"-0.2000,-0.1892,-0.1736,-0.1472,-0.1072,-0.0369,0.0979",\
+"-0.2124,-0.2017,-0.1861,-0.1597,-0.1196,-0.0493,0.0854",\
+"-0.2299,-0.2191,-0.2035,-0.1771,-0.1371,-0.0668,0.0680",\
+"-0.2575,-0.2468,-0.2312,-0.2048,-0.1648,-0.0945,0.0403");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.1666,-0.1558,-0.1422,-0.1148,-0.0777,-0.0055,0.1244",\
+"-0.1705,-0.1597,-0.1461,-0.1187,-0.0816,-0.0093,0.1205",\
+"-0.1743,-0.1635,-0.1498,-0.1225,-0.0854,-0.0131,0.1167",\
+"-0.1775,-0.1668,-0.1531,-0.1258,-0.0887,-0.0164,0.1135",\
+"-0.1900,-0.1792,-0.1656,-0.1382,-0.1011,-0.0288,0.1011",\
+"-0.2074,-0.1967,-0.1830,-0.1557,-0.1186,-0.0463,0.0836",\
+"-0.2351,-0.2243,-0.2107,-0.1833,-0.1462,-0.0739,0.0559");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "(A_BIST_WEN & A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2950,0.2833,0.2686,0.2423,0.2022,0.1309,-0.0058",\
+"0.2989,0.2872,0.2725,0.2461,0.2061,0.1348,-0.0019",\
+"0.3027,0.2910,0.2763,0.2499,0.2099,0.1386,0.0019",\
+"0.3059,0.2942,0.2796,0.2532,0.2132,0.1419,0.0052",\
+"0.3184,0.3066,0.2920,0.2656,0.2256,0.1543,0.0176",\
+"0.3358,0.3241,0.3095,0.2831,0.2431,0.1718,0.0351",\
+"0.3635,0.3518,0.3371,0.3108,0.2707,0.1994,0.0627");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2667,0.2569,0.2423,0.2159,0.1788,0.1055,-0.0224",\
+"0.2706,0.2608,0.2461,0.2198,0.1827,0.1094,-0.0185",\
+"0.2744,0.2646,0.2499,0.2236,0.1865,0.1132,-0.0147",\
+"0.2776,0.2678,0.2532,0.2268,0.1897,0.1165,-0.0115",\
+"0.2900,0.2803,0.2656,0.2393,0.2022,0.1289,0.0010",\
+"0.3075,0.2978,0.2831,0.2567,0.2196,0.1464,0.0185",\
+"0.3352,0.3254,0.3108,0.2844,0.2473,0.1740,0.0461");
+		}
+	}
+}
+   pin(A_BIST_CLK)  {
+	   direction       : input;
+	   capacitance     : 0.00389386;
+	   max_transition  : "0.38";
+	   clock           : "true" ;
+	   pin_func_type   : active_rising ;
+
+	   timing () {
+		 timing_type : "min_pulse_width";
+		 related_pin : "A_BIST_CLK";
+		 rise_constraint("CLKTRAN_constraint_template") {
+		 index_1("0.004,0.38");
+		 values("0.12,0.12");
+		 }
+	   }
+
+	   related_power_pin : VDD;
+	   related_ground_pin : VSS;
+
+	internal_power() {
+		when : "!A_BIST_MEN  & !A_BIST_WEN & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN  & A_BIST_WEN  & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0.7039);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & A_BIST_WEN  & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (40.8199);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & A_BIST_WEN  & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (41.5232);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & !A_BIST_WEN & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (33.7892);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0.4120);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN & A_BIST_WEN  & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0.9290);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & !A_BIST_WEN & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	}
+   bus(A_BIST_DIN) {
+	   bus_type : D_15_0;
+	   direction       : input ;
+	   capacitance     : 0.00252927 ;
+	   memory_write() {
+		   address : A_BIST_ADDR ;
+		   clocked_on : A_BIST_CLK;
+	   }
+
+	   max_transition  : "0.38" ;
+	   pin(A_BIST_DIN[15:0]) {
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0783);
+		}
+		        fall_power("scalar"){
+		 values (0.0812);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.1034);
+		}
+		        fall_power("scalar"){
+		 values (0.0834);
+		}
+	}
+	   }
+	   timing() {
+		 timing_type     : setup_rising;
+		 related_pin     : "A_BIST_CLK";
+		 when            : "(A_BIST_WEN & A_BIST_MEN)";
+		 sdf_cond        : "A_BIST_W_ACCESS";
+
+	  rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 values ("-0.1890,-0.1783,-0.1627,-0.1363,-0.0963,-0.0260,0.1088",\
+"-0.1929,-0.1822,-0.1666,-0.1402,-0.1002,-0.0298,0.1049",\
+"-0.1967,-0.1860,-0.1704,-0.1440,-0.1039,-0.0336,0.1011",\
+"-0.2000,-0.1892,-0.1736,-0.1472,-0.1072,-0.0369,0.0979",\
+"-0.2124,-0.2017,-0.1861,-0.1597,-0.1196,-0.0493,0.0854",\
+"-0.2299,-0.2191,-0.2035,-0.1771,-0.1371,-0.0668,0.0680",\
+"-0.2575,-0.2468,-0.2312,-0.2048,-0.1648,-0.0945,0.0403");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 values ("-0.1666,-0.1558,-0.1422,-0.1148,-0.0777,-0.0055,0.1244",\
+"-0.1705,-0.1597,-0.1461,-0.1187,-0.0816,-0.0093,0.1205",\
+"-0.1743,-0.1635,-0.1498,-0.1225,-0.0854,-0.0131,0.1167",\
+"-0.1775,-0.1668,-0.1531,-0.1258,-0.0887,-0.0164,0.1135",\
+"-0.1900,-0.1792,-0.1656,-0.1382,-0.1011,-0.0288,0.1011",\
+"-0.2074,-0.1967,-0.1830,-0.1557,-0.1186,-0.0463,0.0836",\
+"-0.2351,-0.2243,-0.2107,-0.1833,-0.1462,-0.0739,0.0559");
+		 }
+	   }
+
+	   timing() {
+		 timing_type     : hold_rising;
+		 related_pin     : "A_BIST_CLK";
+		 when            : "(A_BIST_WEN & A_BIST_MEN)";
+		 sdf_cond        : "A_BIST_W_ACCESS";
+
+	   rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 values ("0.2950,0.2833,0.2686,0.2423,0.2022,0.1309,-0.0058",\
+"0.2989,0.2872,0.2725,0.2461,0.2061,0.1348,-0.0019",\
+"0.3027,0.2910,0.2763,0.2499,0.2099,0.1386,0.0019",\
+"0.3059,0.2942,0.2796,0.2532,0.2132,0.1419,0.0052",\
+"0.3184,0.3066,0.2920,0.2656,0.2256,0.1543,0.0176",\
+"0.3358,0.3241,0.3095,0.2831,0.2431,0.1718,0.0351",\
+"0.3635,0.3518,0.3371,0.3108,0.2707,0.1994,0.0627");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 values ("0.2667,0.2569,0.2423,0.2159,0.1788,0.1055,-0.0224",\
+"0.2706,0.2608,0.2461,0.2198,0.1827,0.1094,-0.0185",\
+"0.2744,0.2646,0.2499,0.2236,0.1865,0.1132,-0.0147",\
+"0.2776,0.2678,0.2532,0.2268,0.1897,0.1165,-0.0115",\
+"0.2900,0.2803,0.2656,0.2393,0.2022,0.1289,0.0010",\
+"0.3075,0.2978,0.2831,0.2567,0.2196,0.1464,0.0185",\
+"0.3352,0.3254,0.3108,0.2844,0.2473,0.1740,0.0461");
+		 }
+	   }
+   }
+
+bus(A_DOUT) {
+
+	   bus_type : D_15_0;
+	   direction       : output ;
+	   capacitance     : 0 ;
+	   max_capacitance  : "6.4e-14" ;
+	   memory_read() {
+		  address : A_ADDR ;
+	   }
+	   pin(A_DOUT[15:0]) {
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+	   internal_power() {
+		  rise_power("scalar") {
+			 values (0);
+		  }
+		  fall_power("scalar") {
+			 values (0);
+		  }
+	   }
+	   }
+	   timing() {
+		 related_pin   : "A_CLK";
+		 timing_type   : rising_edge ;
+		 timing_sense  : non_unate ;
+
+	   cell_rise(SIG2SRAM_delay_template) {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("2.6175,2.6185,2.6234,2.6289,2.6498,2.6733",\
+"2.6247,2.6258,2.6306,2.6361,2.6570,2.6805",\
+"2.6262,2.6272,2.6320,2.6376,2.6585,2.6820",\
+"2.6296,2.6306,2.6354,2.6409,2.6618,2.6853",\
+"2.6424,2.6434,2.6482,2.6537,2.6746,2.6981",\
+"2.6601,2.6612,2.6660,2.6715,2.6924,2.7159",\
+"2.6855,2.6865,2.6914,2.6969,2.7178,2.7413");
+	   }
+	   cell_fall(SIG2SRAM_delay_template) {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("2.5832,2.5841,2.5881,2.5927,2.6098,2.6265",\
+"2.5905,2.5913,2.5954,2.5999,2.6170,2.6337",\
+"2.5919,2.5928,2.5968,2.6014,2.6185,2.6352",\
+"2.5953,2.5961,2.6002,2.6047,2.6218,2.6385",\
+"2.6081,2.6089,2.6130,2.6175,2.6346,2.6513",\
+"2.6259,2.6267,2.6308,2.6353,2.6524,2.6691",\
+"2.6512,2.6521,2.6561,2.6607,2.6778,2.6945");
+	   }
+
+	   rise_transition(SRAM_load_template) {
+		 index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("0.0206,0.0210,0.0265,0.0323,0.0606,0.0955");
+	   }
+	   fall_transition(SRAM_load_template) {
+		 index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("0.0170,0.0177,0.0222,0.0270,0.0451,0.0644");
+	   }
+	}
+}
+cell_leakage_power : 469.5941;
+}
+}
diff --git a/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_1024x16_c2_bm_bist_slow_1p08V_125C.lib b/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_1024x16_c2_bm_bist_slow_1p08V_125C.lib
new file mode 100644
index 00000000..7f909869
--- /dev/null
+++ b/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_1024x16_c2_bm_bist_slow_1p08V_125C.lib
@@ -0,0 +1,1525 @@
+/* ------------------------------------------------------*/
+/**/
+/*		Copyright 2024 IHP PDK Authors*/
+/**/
+/*		Licensed under the Apache License, Version 2.0 (the "License");*/
+/*		you may not use this file except in compliance with the License.*/
+/*		You may obtain a copy of the License at*/
+/*		*/
+/*		   https://www.apache.org/licenses/LICENSE-2.0*/
+/*		*/
+/*		Unless required by applicable law or agreed to in writing, software*/
+/*		distributed under the License is distributed on an "AS IS" BASIS,*/
+/*		WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/
+/*		See the License for the specific language governing permissions and*/
+/*		limitations under the License.*/
+/*		*/
+/*		Generated on Fri Jul 19 08:58:02 2024		*/
+/*				*/
+/* ------------------------------------------------------ */
+library(RM_IHPSG13_1P_1024x16_c2_bm_bist_slow_1p08V_125C) {	
+	technology (cmos) ;
+	delay_model : table_lookup ;
+	define ("add_pg_pin_to_lib",  "library",  "boolean");
+	add_pg_pin_to_lib : true;
+	voltage_map ( VDD, 1.08);
+	voltage_map ( VDDARRAY, 1.08);
+	voltage_map ( VSS, 0.000000 );
+	
+	date            : "Fri Jul 19 08:58:00 2024" ;
+	comment         : "IHP Microelectronics GmbH, 2024" ;
+	revision        : 1.0.0 ;
+	simulation      : true ;
+	nom_process     : 1 ;
+	nom_temperature : 125 ;
+	nom_voltage     : 1.08 ;
+	
+	operating_conditions("slow_1p08V_125C"){
+	    process     : 1 ;
+	    temperature : 125 ;
+	    voltage     : 1.08 ;
+	    tree_type   : "balanced_tree" ;
+	}
+	
+	default_operating_conditions  : slow_1p08V_125C ;
+	default_max_transition        : 1.0 ;
+	default_fanout_load           : 1.0 ;
+	default_inout_pin_cap         : 0.0 ;
+	default_input_pin_cap         : 0.0 ;
+	default_output_pin_cap        : 0.0 ;
+	default_cell_leakage_power    : 0.0 ;
+	default_leakage_power_density : 0.0 ;
+	 
+	slew_lower_threshold_pct_rise : 30 ;
+	slew_upper_threshold_pct_rise : 70 ;
+	input_threshold_pct_fall      : 50 ;
+	output_threshold_pct_fall     : 50 ;
+	input_threshold_pct_rise      : 50 ;
+	output_threshold_pct_rise     : 50 ;
+	slew_lower_threshold_pct_fall : 30 ;
+	slew_upper_threshold_pct_fall : 70 ;
+	slew_derate_from_library      : 0.5;
+	k_volt_cell_leakage_power     : 0.0 ;
+	k_temp_cell_leakage_power     : 0.0 ;
+	k_process_cell_leakage_power  : 0.0 ;
+	k_volt_internal_power         : 0.0 ;
+	k_temp_internal_power         : 0.0 ;
+	k_process_internal_power      : 0.0 ;
+	
+	capacitive_load_unit            (1,pf) ;
+	voltage_unit                  : "1V" ;
+	current_unit                  : "1uA" ;
+	time_unit                     : "1ns" ;
+	leakage_power_unit            : "1nW" ;
+	pulling_resistance_unit       : "1kohm";
+	/*
+	  ------------------------------------------------------------------------------------------
+	  implicit units overview:
+	    cell_area       unit      : "um"
+	    internal_power  unit      : "1e-12 * J/toggle = 1 * uW/MHz"
+	                                (capacitive_load_unit * voltage_unit^2) per toggle event
+	  ------------------------------------------------------------------------------------------
+	*/
+	library_features(report_delay_calculation);
+	define_cell_area (pad_drivers,pad_driver_sites) ;
+	
+	lu_table_template(CLKTRAN_constraint_template) {
+	     variable_1 : constrained_pin_transition;
+	     index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" );
+	}
+	lu_table_template(SRAM_load_template) {
+	     variable_1 : total_output_net_capacitance;
+	     index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" );
+	}
+	lu_table_template(SIG2SRAM_constraint_template) {
+	     variable_1 : related_pin_transition;
+	     variable_2 : constrained_pin_transition;
+	     index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" );
+	     index_2 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" );
+	}
+	
+	lu_table_template(SIG2SRAM_delay_template) {
+	     variable_1 : input_net_transition;
+	     variable_2 : total_output_net_capacitance;
+	     index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" );
+	     index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" );
+	} 
+
+	type (D_15_0) {
+		base_type : array;
+		data_type : bit;
+		bit_width : 16;
+		bit_from  : 15;
+		bit_to    : 0;
+		downto    : true;
+	 }
+
+	type (A_9_0) {
+		base_type : array;
+		data_type : bit;
+		bit_width : 10;
+		bit_from  : 9;
+		bit_to    : 0;
+		downto    : true;
+	 }
+
+cell(RM_IHPSG13_1P_1024x16_c2_bm_bist) {
+pg_pin (VDD) {
+  pg_type : primary_power;
+  voltage_name : VDD;
+}
+pg_pin (VDDARRAY) {
+  pg_type : primary_power;
+  voltage_name : VDDARRAY;
+}
+pg_pin (VSS) {
+  pg_type : primary_ground;
+  voltage_name : VSS;
+}
+
+memory() {
+ type : ram;
+ address_width : 10;
+ word_width : 16;
+}
+
+interface_timing : false;
+bus_naming_style    :   "%s[%d]" ;
+area        : 79673.728 ;
+
+   pin(A_DLY) {
+	   direction       : input ;
+	   capacitance     : 0.00387999 ;
+	   max_transition  : "1" ;
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+		internal_power() {
+		  rise_power("scalar") {
+			 values (0);
+		  }
+		  fall_power("scalar") {
+			 values (0);
+		  }
+	   }
+   }
+
+bus(A_ADDR) {
+   bus_type : A_9_0;
+   direction          : input ;
+   capacitance        : 0.0077013 ;
+    pin(A_ADDR[0]) {
+       capacitance : 0.00625349 ;
+    }
+    pin(A_ADDR[1]) {
+       capacitance : 0.00507435 ;
+    }
+    pin(A_ADDR[2]) {
+       capacitance : 0.00656707 ;
+    }
+    pin(A_ADDR[3]) {
+       capacitance : 0.0083133 ;
+    }
+    pin(A_ADDR[4]) {
+       capacitance : 0.00507219 ;
+    }
+    pin(A_ADDR[5]) {
+       capacitance : 0.00964344 ;
+    }
+    pin(A_ADDR[6]) {
+       capacitance : 0.0119653 ;
+    }
+    pin(A_ADDR[7]) {
+       capacitance : 0.00827606 ;
+    }
+    pin(A_ADDR[8]) {
+       capacitance : 0.0110771 ;
+    }
+   max_transition     : "0.5952" ;
+   pin(A_ADDR[9:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0011);
+		}
+		        fall_power("scalar"){
+		 values (0.0188);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0058);
+		}
+		        fall_power("scalar"){
+		 values (0.0107);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "((A_WEN | A_REN)& A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\
+"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\
+"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\
+"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\
+"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\
+"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\
+"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\
+"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\
+"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\
+"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\
+"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\
+"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\
+"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "((A_WEN | A_REN)& A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3098",\
+"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\
+"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\
+"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\
+"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\
+"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\
+"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\
+"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\
+"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\
+"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\
+"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\
+"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\
+"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004");
+		}
+	}
+}
+pin(A_WEN) {
+   direction          : input ;
+   capacitance        : 0.00313551 ;
+   max_transition     : "0.5952" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0065);
+		}
+		        fall_power("scalar"){
+		 values (0.0066);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0128);
+		}
+		        fall_power("scalar"){
+		 values (0.0293);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\
+"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\
+"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\
+"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\
+"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\
+"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\
+"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\
+"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\
+"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\
+"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\
+"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\
+"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\
+"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\
+"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\
+"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\
+"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\
+"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\
+"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\
+"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\
+"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\
+"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\
+"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\
+"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\
+"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\
+"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879");
+		}
+	}
+	}
+pin(A_REN) {
+   direction          : input ;
+   capacitance        : 0.00381144 ;
+   max_transition     : "0.5952" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0060);
+		}
+		        fall_power("scalar"){
+		 values (0.0027);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0013);
+		}
+		        fall_power("scalar"){
+		 values (0.0021);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\
+"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\
+"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\
+"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\
+"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\
+"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\
+"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\
+"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\
+"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\
+"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\
+"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\
+"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\
+"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\
+"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\
+"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\
+"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\
+"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\
+"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\
+"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\
+"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\
+"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\
+"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\
+"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\
+"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\
+"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113");
+		}
+	}
+	}
+pin(A_MEN) {
+   direction          : input ;
+   capacitance        : 0.00300347 ;
+   max_transition     : "0.5952" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		        rise_power("scalar"){
+		 values (0.0060);
+		}
+		        fall_power("scalar"){
+		 values (0.0099);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\
+"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\
+"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\
+"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\
+"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\
+"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\
+"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\
+"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\
+"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\
+"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\
+"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\
+"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\
+"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\
+"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\
+"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\
+"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\
+"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\
+"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\
+"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\
+"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\
+"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\
+"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\
+"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\
+"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\
+"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918");
+		}
+	}
+	}
+bus(A_BM) {
+   bus_type : D_15_0;
+   direction          : input ;
+   capacitance        : 0.00263802 ;
+   max_transition     : "0.5952" ;
+   pin(A_BM[15:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0368);
+		}
+		        fall_power("scalar"){
+		 values (0.0200);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0452);
+		}
+		        fall_power("scalar"){
+		 values (0.0145);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "(A_WEN & A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.6208,-0.6012,-0.5749,-0.5329,-0.4518,-0.3073,-0.0866",\
+"-0.6288,-0.6093,-0.5829,-0.5409,-0.4599,-0.3153,-0.0946",\
+"-0.6378,-0.6183,-0.5919,-0.5499,-0.4689,-0.3243,-0.1036",\
+"-0.6510,-0.6314,-0.6051,-0.5631,-0.4820,-0.3375,-0.1168",\
+"-0.6752,-0.6557,-0.6293,-0.5874,-0.5063,-0.3618,-0.1411",\
+"-0.7058,-0.6862,-0.6599,-0.6179,-0.5368,-0.3923,-0.1716",\
+"-0.7872,-0.7677,-0.7413,-0.6993,-0.6183,-0.4737,-0.2530");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.5651,-0.5495,-0.5212,-0.4821,-0.4011,-0.2634,-0.0514",\
+"-0.5731,-0.5575,-0.5292,-0.4901,-0.4091,-0.2714,-0.0595",\
+"-0.5822,-0.5665,-0.5382,-0.4991,-0.4181,-0.2804,-0.0685",\
+"-0.5953,-0.5797,-0.5514,-0.5123,-0.4312,-0.2936,-0.0816",\
+"-0.6196,-0.6040,-0.5756,-0.5366,-0.4555,-0.3178,-0.1059",\
+"-0.6501,-0.6345,-0.6061,-0.5671,-0.4860,-0.3483,-0.1364",\
+"-0.7315,-0.7159,-0.6876,-0.6485,-0.5675,-0.4298,-0.2179");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "(A_WEN & A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.7376,0.7161,0.6897,0.6467,0.5676,0.4221,0.1965",\
+"0.7456,0.7241,0.6977,0.6548,0.5757,0.4302,0.2046",\
+"0.7546,0.7331,0.7067,0.6638,0.5847,0.4392,0.2136",\
+"0.7677,0.7463,0.7199,0.6769,0.5978,0.4523,0.2267",\
+"0.7920,0.7705,0.7442,0.7012,0.6221,0.4766,0.2510",\
+"0.8225,0.8010,0.7747,0.7317,0.6526,0.5071,0.2815",\
+"0.9040,0.8825,0.8561,0.8132,0.7341,0.5886,0.3630");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.6692,0.6526,0.6243,0.5803,0.5032,0.3655,0.1555",\
+"0.6772,0.6606,0.6323,0.5884,0.5112,0.3735,0.1636",\
+"0.6862,0.6696,0.6413,0.5974,0.5202,0.3825,0.1726",\
+"0.6994,0.6828,0.6545,0.6105,0.5334,0.3957,0.1857",\
+"0.7237,0.7071,0.6787,0.6348,0.5576,0.4200,0.2100",\
+"0.7542,0.7376,0.7093,0.6653,0.5882,0.4505,0.2405",\
+"0.8356,0.8190,0.7907,0.7468,0.6696,0.5319,0.3220");
+		}
+	}
+}
+   pin(A_CLK)  {
+	   direction       : input;
+	   capacitance     : 0.00378957;
+	   max_transition  : "0.5952";
+	   clock           : "true" ;
+	   pin_func_type   : active_rising ;
+
+	   timing () {
+		 timing_type : "min_pulse_width";
+		 related_pin : "A_CLK";
+		 rise_constraint("CLKTRAN_constraint_template") {
+		 index_1("0.008,0.5952");
+		 values("0.4,0.4");
+		 }
+	   }
+
+	   related_power_pin : VDD;
+	   related_ground_pin : VSS;
+
+	internal_power() {
+		when : "!A_MEN  & !A_WEN & !A_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN  & A_WEN  & !A_REN";
+		        rise_power("scalar"){
+		 values (0.5660);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & A_WEN  & !A_REN";
+		        rise_power("scalar"){
+		 values (25.9369);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & A_WEN  & A_REN";
+		        rise_power("scalar"){
+		 values (26.9678);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & !A_WEN & A_REN";
+		        rise_power("scalar"){
+		 values (20.0971);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN & !A_WEN & A_REN";
+		        rise_power("scalar"){
+		 values (0.3586);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN & A_WEN  & A_REN";
+		        rise_power("scalar"){
+		 values (0.7302);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & !A_WEN & !A_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	}
+   bus(A_DIN) {
+	   bus_type : D_15_0;
+	   direction       : input ;
+	   capacitance     : 0.00358485 ;
+	   memory_write() {
+		   address : A_ADDR ;
+		   clocked_on : A_CLK;
+	   }
+
+	   max_transition  : "0.5952" ;
+	   pin(A_DIN[15:0]) {
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0368);
+		}
+		        fall_power("scalar"){
+		 values (0.0200);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0452);
+		}
+		        fall_power("scalar"){
+		 values (0.0145);
+		}
+	}
+	   }
+	   timing() {
+		 timing_type     : setup_rising;
+		 related_pin     : "A_CLK";
+		 when            : "(A_WEN & A_MEN)";
+		 sdf_cond        : "A_W_ACCESS";
+
+	  rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 values ("-0.6208,-0.6012,-0.5749,-0.5329,-0.4518,-0.3073,-0.0866",\
+"-0.6288,-0.6093,-0.5829,-0.5409,-0.4599,-0.3153,-0.0946",\
+"-0.6378,-0.6183,-0.5919,-0.5499,-0.4689,-0.3243,-0.1036",\
+"-0.6510,-0.6314,-0.6051,-0.5631,-0.4820,-0.3375,-0.1168",\
+"-0.6752,-0.6557,-0.6293,-0.5874,-0.5063,-0.3618,-0.1411",\
+"-0.7058,-0.6862,-0.6599,-0.6179,-0.5368,-0.3923,-0.1716",\
+"-0.7872,-0.7677,-0.7413,-0.6993,-0.6183,-0.4737,-0.2530");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 values ("-0.5651,-0.5495,-0.5212,-0.4821,-0.4011,-0.2634,-0.0514",\
+"-0.5731,-0.5575,-0.5292,-0.4901,-0.4091,-0.2714,-0.0595",\
+"-0.5822,-0.5665,-0.5382,-0.4991,-0.4181,-0.2804,-0.0685",\
+"-0.5953,-0.5797,-0.5514,-0.5123,-0.4312,-0.2936,-0.0816",\
+"-0.6196,-0.6040,-0.5756,-0.5366,-0.4555,-0.3178,-0.1059",\
+"-0.6501,-0.6345,-0.6061,-0.5671,-0.4860,-0.3483,-0.1364",\
+"-0.7315,-0.7159,-0.6876,-0.6485,-0.5675,-0.4298,-0.2179");
+		 }
+	   }
+
+	   timing() {
+		 timing_type     : hold_rising;
+		 related_pin     : "A_CLK";
+		 when            : "(A_WEN & A_MEN)";
+		 sdf_cond        : "A_W_ACCESS";
+
+	   rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 values ("0.7376,0.7161,0.6897,0.6467,0.5676,0.4221,0.1965",\
+"0.7456,0.7241,0.6977,0.6548,0.5757,0.4302,0.2046",\
+"0.7546,0.7331,0.7067,0.6638,0.5847,0.4392,0.2136",\
+"0.7677,0.7463,0.7199,0.6769,0.5978,0.4523,0.2267",\
+"0.7920,0.7705,0.7442,0.7012,0.6221,0.4766,0.2510",\
+"0.8225,0.8010,0.7747,0.7317,0.6526,0.5071,0.2815",\
+"0.9040,0.8825,0.8561,0.8132,0.7341,0.5886,0.3630");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 values ("0.6692,0.6526,0.6243,0.5803,0.5032,0.3655,0.1555",\
+"0.6772,0.6606,0.6323,0.5884,0.5112,0.3735,0.1636",\
+"0.6862,0.6696,0.6413,0.5974,0.5202,0.3825,0.1726",\
+"0.6994,0.6828,0.6545,0.6105,0.5334,0.3957,0.1857",\
+"0.7237,0.7071,0.6787,0.6348,0.5576,0.4200,0.2100",\
+"0.7542,0.7376,0.7093,0.6653,0.5882,0.4505,0.2405",\
+"0.8356,0.8190,0.7907,0.7468,0.6696,0.5319,0.3220");
+		 }
+	   }
+   }
+
+   pin(A_BIST_EN) {
+	   direction       : input ;
+	   capacitance     : 0.00387999 ;
+	   max_transition  : "1" ;
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+		internal_power() {
+		  rise_power("scalar") {
+			 values (0);
+		  }
+		  fall_power("scalar") {
+			 values (0);
+		  }
+	   }
+   }
+
+bus(A_BIST_ADDR) {
+   bus_type : A_9_0;
+   direction          : input ;
+   capacitance        : 0.0077013 ;
+    pin(A_BIST_ADDR[0]) {
+       capacitance : 0.00625349 ;
+    }
+    pin(A_BIST_ADDR[1]) {
+       capacitance : 0.00507435 ;
+    }
+    pin(A_BIST_ADDR[2]) {
+       capacitance : 0.00656707 ;
+    }
+    pin(A_BIST_ADDR[3]) {
+       capacitance : 0.0083133 ;
+    }
+    pin(A_BIST_ADDR[4]) {
+       capacitance : 0.00507219 ;
+    }
+    pin(A_BIST_ADDR[5]) {
+       capacitance : 0.00964344 ;
+    }
+    pin(A_BIST_ADDR[6]) {
+       capacitance : 0.0119653 ;
+    }
+    pin(A_BIST_ADDR[7]) {
+       capacitance : 0.00827606 ;
+    }
+    pin(A_BIST_ADDR[8]) {
+       capacitance : 0.0110771 ;
+    }
+   max_transition     : "0.5952" ;
+   pin(A_BIST_ADDR[9:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0011);
+		}
+		        fall_power("scalar"){
+		 values (0.0188);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0058);
+		}
+		        fall_power("scalar"){
+		 values (0.0107);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\
+"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\
+"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\
+"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\
+"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\
+"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\
+"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\
+"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\
+"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\
+"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\
+"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\
+"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\
+"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3098",\
+"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\
+"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\
+"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\
+"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\
+"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\
+"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\
+"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\
+"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\
+"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\
+"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\
+"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\
+"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004");
+		}
+	}
+}
+pin(A_BIST_WEN) {
+   direction          : input ;
+   capacitance        : 0.00313551 ;
+   max_transition     : "0.5952" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0065);
+		}
+		        fall_power("scalar"){
+		 values (0.0066);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0128);
+		}
+		        fall_power("scalar"){
+		 values (0.0293);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\
+"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\
+"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\
+"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\
+"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\
+"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\
+"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\
+"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\
+"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\
+"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\
+"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\
+"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\
+"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\
+"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\
+"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\
+"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\
+"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\
+"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\
+"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\
+"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\
+"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\
+"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\
+"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\
+"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\
+"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879");
+		}
+	}
+	}
+pin(A_BIST_REN) {
+   direction          : input ;
+   capacitance        : 0.00381144 ;
+   max_transition     : "0.5952" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0060);
+		}
+		        fall_power("scalar"){
+		 values (0.0027);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0013);
+		}
+		        fall_power("scalar"){
+		 values (0.0021);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\
+"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\
+"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\
+"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\
+"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\
+"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\
+"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\
+"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\
+"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\
+"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\
+"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\
+"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\
+"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\
+"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\
+"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\
+"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\
+"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\
+"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\
+"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\
+"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\
+"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\
+"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\
+"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\
+"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\
+"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113");
+		}
+	}
+	}
+pin(A_BIST_MEN) {
+   direction          : input ;
+   capacitance        : 0.00300347 ;
+   max_transition     : "0.5952" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		        rise_power("scalar"){
+		 values (0.0060);
+		}
+		        fall_power("scalar"){
+		 values (0.0099);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\
+"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\
+"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\
+"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\
+"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\
+"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\
+"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\
+"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\
+"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\
+"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\
+"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\
+"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\
+"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\
+"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\
+"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\
+"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\
+"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\
+"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\
+"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\
+"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\
+"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\
+"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\
+"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\
+"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\
+"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918");
+		}
+	}
+	}
+bus(A_BIST_BM) {
+   bus_type : D_15_0;
+   direction          : input ;
+   capacitance        : 0.00225269 ;
+   max_transition     : "0.5952" ;
+   pin(A_BIST_BM[15:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0368);
+		}
+		        fall_power("scalar"){
+		 values (0.0200);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0452);
+		}
+		        fall_power("scalar"){
+		 values (0.0145);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "(A_BIST_WEN & A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.6208,-0.6012,-0.5749,-0.5329,-0.4518,-0.3073,-0.0866",\
+"-0.6288,-0.6093,-0.5829,-0.5409,-0.4599,-0.3153,-0.0946",\
+"-0.6378,-0.6183,-0.5919,-0.5499,-0.4689,-0.3243,-0.1036",\
+"-0.6510,-0.6314,-0.6051,-0.5631,-0.4820,-0.3375,-0.1168",\
+"-0.6752,-0.6557,-0.6293,-0.5874,-0.5063,-0.3618,-0.1411",\
+"-0.7058,-0.6862,-0.6599,-0.6179,-0.5368,-0.3923,-0.1716",\
+"-0.7872,-0.7677,-0.7413,-0.6993,-0.6183,-0.4737,-0.2530");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.5651,-0.5495,-0.5212,-0.4821,-0.4011,-0.2634,-0.0514",\
+"-0.5731,-0.5575,-0.5292,-0.4901,-0.4091,-0.2714,-0.0595",\
+"-0.5822,-0.5665,-0.5382,-0.4991,-0.4181,-0.2804,-0.0685",\
+"-0.5953,-0.5797,-0.5514,-0.5123,-0.4312,-0.2936,-0.0816",\
+"-0.6196,-0.6040,-0.5756,-0.5366,-0.4555,-0.3178,-0.1059",\
+"-0.6501,-0.6345,-0.6061,-0.5671,-0.4860,-0.3483,-0.1364",\
+"-0.7315,-0.7159,-0.6876,-0.6485,-0.5675,-0.4298,-0.2179");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "(A_BIST_WEN & A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.7376,0.7161,0.6897,0.6467,0.5676,0.4221,0.1965",\
+"0.7456,0.7241,0.6977,0.6548,0.5757,0.4302,0.2046",\
+"0.7546,0.7331,0.7067,0.6638,0.5847,0.4392,0.2136",\
+"0.7677,0.7463,0.7199,0.6769,0.5978,0.4523,0.2267",\
+"0.7920,0.7705,0.7442,0.7012,0.6221,0.4766,0.2510",\
+"0.8225,0.8010,0.7747,0.7317,0.6526,0.5071,0.2815",\
+"0.9040,0.8825,0.8561,0.8132,0.7341,0.5886,0.3630");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.6692,0.6526,0.6243,0.5803,0.5032,0.3655,0.1555",\
+"0.6772,0.6606,0.6323,0.5884,0.5112,0.3735,0.1636",\
+"0.6862,0.6696,0.6413,0.5974,0.5202,0.3825,0.1726",\
+"0.6994,0.6828,0.6545,0.6105,0.5334,0.3957,0.1857",\
+"0.7237,0.7071,0.6787,0.6348,0.5576,0.4200,0.2100",\
+"0.7542,0.7376,0.7093,0.6653,0.5882,0.4505,0.2405",\
+"0.8356,0.8190,0.7907,0.7468,0.6696,0.5319,0.3220");
+		}
+	}
+}
+   pin(A_BIST_CLK)  {
+	   direction       : input;
+	   capacitance     : 0.00378957;
+	   max_transition  : "0.5952";
+	   clock           : "true" ;
+	   pin_func_type   : active_rising ;
+
+	   timing () {
+		 timing_type : "min_pulse_width";
+		 related_pin : "A_BIST_CLK";
+		 rise_constraint("CLKTRAN_constraint_template") {
+		 index_1("0.008,0.5952");
+		 values("0.4,0.4");
+		 }
+	   }
+
+	   related_power_pin : VDD;
+	   related_ground_pin : VSS;
+
+	internal_power() {
+		when : "!A_BIST_MEN  & !A_BIST_WEN & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN  & A_BIST_WEN  & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0.5660);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & A_BIST_WEN  & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (25.9369);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & A_BIST_WEN  & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (26.9678);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & !A_BIST_WEN & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (20.0971);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0.3586);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN & A_BIST_WEN  & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0.7302);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & !A_BIST_WEN & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	}
+   bus(A_BIST_DIN) {
+	   bus_type : D_15_0;
+	   direction       : input ;
+	   capacitance     : 0.00226348 ;
+	   memory_write() {
+		   address : A_BIST_ADDR ;
+		   clocked_on : A_BIST_CLK;
+	   }
+
+	   max_transition  : "0.5952" ;
+	   pin(A_BIST_DIN[15:0]) {
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0368);
+		}
+		        fall_power("scalar"){
+		 values (0.0200);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0452);
+		}
+		        fall_power("scalar"){
+		 values (0.0145);
+		}
+	}
+	   }
+	   timing() {
+		 timing_type     : setup_rising;
+		 related_pin     : "A_BIST_CLK";
+		 when            : "(A_BIST_WEN & A_BIST_MEN)";
+		 sdf_cond        : "A_BIST_W_ACCESS";
+
+	  rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 values ("-0.6208,-0.6012,-0.5749,-0.5329,-0.4518,-0.3073,-0.0866",\
+"-0.6288,-0.6093,-0.5829,-0.5409,-0.4599,-0.3153,-0.0946",\
+"-0.6378,-0.6183,-0.5919,-0.5499,-0.4689,-0.3243,-0.1036",\
+"-0.6510,-0.6314,-0.6051,-0.5631,-0.4820,-0.3375,-0.1168",\
+"-0.6752,-0.6557,-0.6293,-0.5874,-0.5063,-0.3618,-0.1411",\
+"-0.7058,-0.6862,-0.6599,-0.6179,-0.5368,-0.3923,-0.1716",\
+"-0.7872,-0.7677,-0.7413,-0.6993,-0.6183,-0.4737,-0.2530");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 values ("-0.5651,-0.5495,-0.5212,-0.4821,-0.4011,-0.2634,-0.0514",\
+"-0.5731,-0.5575,-0.5292,-0.4901,-0.4091,-0.2714,-0.0595",\
+"-0.5822,-0.5665,-0.5382,-0.4991,-0.4181,-0.2804,-0.0685",\
+"-0.5953,-0.5797,-0.5514,-0.5123,-0.4312,-0.2936,-0.0816",\
+"-0.6196,-0.6040,-0.5756,-0.5366,-0.4555,-0.3178,-0.1059",\
+"-0.6501,-0.6345,-0.6061,-0.5671,-0.4860,-0.3483,-0.1364",\
+"-0.7315,-0.7159,-0.6876,-0.6485,-0.5675,-0.4298,-0.2179");
+		 }
+	   }
+
+	   timing() {
+		 timing_type     : hold_rising;
+		 related_pin     : "A_BIST_CLK";
+		 when            : "(A_BIST_WEN & A_BIST_MEN)";
+		 sdf_cond        : "A_BIST_W_ACCESS";
+
+	   rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 values ("0.7376,0.7161,0.6897,0.6467,0.5676,0.4221,0.1965",\
+"0.7456,0.7241,0.6977,0.6548,0.5757,0.4302,0.2046",\
+"0.7546,0.7331,0.7067,0.6638,0.5847,0.4392,0.2136",\
+"0.7677,0.7463,0.7199,0.6769,0.5978,0.4523,0.2267",\
+"0.7920,0.7705,0.7442,0.7012,0.6221,0.4766,0.2510",\
+"0.8225,0.8010,0.7747,0.7317,0.6526,0.5071,0.2815",\
+"0.9040,0.8825,0.8561,0.8132,0.7341,0.5886,0.3630");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 values ("0.6692,0.6526,0.6243,0.5803,0.5032,0.3655,0.1555",\
+"0.6772,0.6606,0.6323,0.5884,0.5112,0.3735,0.1636",\
+"0.6862,0.6696,0.6413,0.5974,0.5202,0.3825,0.1726",\
+"0.6994,0.6828,0.6545,0.6105,0.5334,0.3957,0.1857",\
+"0.7237,0.7071,0.6787,0.6348,0.5576,0.4200,0.2100",\
+"0.7542,0.7376,0.7093,0.6653,0.5882,0.4505,0.2405",\
+"0.8356,0.8190,0.7907,0.7468,0.6696,0.5319,0.3220");
+		 }
+	   }
+   }
+
+bus(A_DOUT) {
+
+	   bus_type : D_15_0;
+	   direction       : output ;
+	   capacitance     : 0 ;
+	   max_capacitance  : "6.4e-14" ;
+	   memory_read() {
+		  address : A_ADDR ;
+	   }
+	   pin(A_DOUT[15:0]) {
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+	   internal_power() {
+		  rise_power("scalar") {
+			 values (0);
+		  }
+		  fall_power("scalar") {
+			 values (0);
+		  }
+	   }
+	   }
+	   timing() {
+		 related_pin   : "A_CLK";
+		 timing_type   : rising_edge ;
+		 timing_sense  : non_unate ;
+
+	   cell_rise(SIG2SRAM_delay_template) {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("7.1160,7.1187,7.1309,7.1451,7.1977,7.2526",\
+"7.1314,7.1341,7.1463,7.1605,7.2131,7.2680",\
+"7.1377,7.1405,7.1526,7.1668,7.2194,7.2744",\
+"7.1584,7.1611,7.1733,7.1875,7.2401,7.2951",\
+"7.1759,7.1786,7.1907,7.2050,7.2575,7.3125",\
+"7.2116,7.2143,7.2265,7.2407,7.2933,7.3483",\
+"7.2820,7.2847,7.2969,7.3111,7.3637,7.4186");
+	   }
+	   cell_fall(SIG2SRAM_delay_template) {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("7.0058,7.0080,7.0177,7.0296,7.0731,7.1168",\
+"7.0212,7.0234,7.0332,7.0450,7.0886,7.1323",\
+"7.0276,7.0297,7.0395,7.0513,7.0949,7.1386",\
+"7.0482,7.0504,7.0602,7.0720,7.1156,7.1593",\
+"7.0657,7.0679,7.0776,7.0895,7.1330,7.1767",\
+"7.1014,7.1036,7.1134,7.1252,7.1688,7.2125",\
+"7.1718,7.1740,7.1838,7.1956,7.2392,7.2829");
+	   }
+
+	   rise_transition(SRAM_load_template) {
+		 index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("0.0560,0.0583,0.0696,0.0816,0.1519,0.2335");
+	   }
+	   fall_transition(SRAM_load_template) {
+		 index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("0.0428,0.0445,0.0538,0.0658,0.1181,0.1751");
+	   }
+	}
+}
+cell_leakage_power : 1306.5882;
+}
+}
diff --git a/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_1024x16_c2_bm_bist_typ_1p20V_25C.lib b/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_1024x16_c2_bm_bist_typ_1p20V_25C.lib
new file mode 100644
index 00000000..258eea0a
--- /dev/null
+++ b/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_1024x16_c2_bm_bist_typ_1p20V_25C.lib
@@ -0,0 +1,1525 @@
+/* ------------------------------------------------------*/
+/**/
+/*		Copyright 2024 IHP PDK Authors*/
+/**/
+/*		Licensed under the Apache License, Version 2.0 (the "License");*/
+/*		you may not use this file except in compliance with the License.*/
+/*		You may obtain a copy of the License at*/
+/*		*/
+/*		   https://www.apache.org/licenses/LICENSE-2.0*/
+/*		*/
+/*		Unless required by applicable law or agreed to in writing, software*/
+/*		distributed under the License is distributed on an "AS IS" BASIS,*/
+/*		WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/
+/*		See the License for the specific language governing permissions and*/
+/*		limitations under the License.*/
+/*		*/
+/*		Generated on Fri Jul 19 08:58:03 2024		*/
+/*				*/
+/* ------------------------------------------------------ */
+library(RM_IHPSG13_1P_1024x16_c2_bm_bist_typ_1p20V_25C) {	
+	technology (cmos) ;
+	delay_model : table_lookup ;
+	define ("add_pg_pin_to_lib",  "library",  "boolean");
+	add_pg_pin_to_lib : true;
+	voltage_map ( VDD, 1.20);
+	voltage_map ( VDDARRAY, 1.20);
+	voltage_map ( VSS, 0.000000 );
+	
+	date            : "Fri Jul 19 08:58:00 2024" ;
+	comment         : "IHP Microelectronics GmbH, 2024" ;
+	revision        : 1.0.0 ;
+	simulation      : true ;
+	nom_process     : 1 ;
+	nom_temperature : 25 ;
+	nom_voltage     : 1.20 ;
+	
+	operating_conditions("typ_1p20V_25C"){
+	    process     : 1 ;
+	    temperature : 25 ;
+	    voltage     : 1.20 ;
+	    tree_type   : "balanced_tree" ;
+	}
+	
+	default_operating_conditions  : typ_1p20V_25C ;
+	default_max_transition        : 1.0 ;
+	default_fanout_load           : 1.0 ;
+	default_inout_pin_cap         : 0.0 ;
+	default_input_pin_cap         : 0.0 ;
+	default_output_pin_cap        : 0.0 ;
+	default_cell_leakage_power    : 0.0 ;
+	default_leakage_power_density : 0.0 ;
+	 
+	slew_lower_threshold_pct_rise : 30 ;
+	slew_upper_threshold_pct_rise : 70 ;
+	input_threshold_pct_fall      : 50 ;
+	output_threshold_pct_fall     : 50 ;
+	input_threshold_pct_rise      : 50 ;
+	output_threshold_pct_rise     : 50 ;
+	slew_lower_threshold_pct_fall : 30 ;
+	slew_upper_threshold_pct_fall : 70 ;
+	slew_derate_from_library      : 0.5;
+	k_volt_cell_leakage_power     : 0.0 ;
+	k_temp_cell_leakage_power     : 0.0 ;
+	k_process_cell_leakage_power  : 0.0 ;
+	k_volt_internal_power         : 0.0 ;
+	k_temp_internal_power         : 0.0 ;
+	k_process_internal_power      : 0.0 ;
+	
+	capacitive_load_unit            (1,pf) ;
+	voltage_unit                  : "1V" ;
+	current_unit                  : "1uA" ;
+	time_unit                     : "1ns" ;
+	leakage_power_unit            : "1nW" ;
+	pulling_resistance_unit       : "1kohm";
+	/*
+	  ------------------------------------------------------------------------------------------
+	  implicit units overview:
+	    cell_area       unit      : "um"
+	    internal_power  unit      : "1e-12 * J/toggle = 1 * uW/MHz"
+	                                (capacitive_load_unit * voltage_unit^2) per toggle event
+	  ------------------------------------------------------------------------------------------
+	*/
+	library_features(report_delay_calculation);
+	define_cell_area (pad_drivers,pad_driver_sites) ;
+	
+	lu_table_template(CLKTRAN_constraint_template) {
+	     variable_1 : constrained_pin_transition;
+	     index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" );
+	}
+	lu_table_template(SRAM_load_template) {
+	     variable_1 : total_output_net_capacitance;
+	     index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" );
+	}
+	lu_table_template(SIG2SRAM_constraint_template) {
+	     variable_1 : related_pin_transition;
+	     variable_2 : constrained_pin_transition;
+	     index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" );
+	     index_2 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" );
+	}
+	
+	lu_table_template(SIG2SRAM_delay_template) {
+	     variable_1 : input_net_transition;
+	     variable_2 : total_output_net_capacitance;
+	     index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" );
+	     index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" );
+	} 
+
+	type (D_15_0) {
+		base_type : array;
+		data_type : bit;
+		bit_width : 16;
+		bit_from  : 15;
+		bit_to    : 0;
+		downto    : true;
+	 }
+
+	type (A_9_0) {
+		base_type : array;
+		data_type : bit;
+		bit_width : 10;
+		bit_from  : 9;
+		bit_to    : 0;
+		downto    : true;
+	 }
+
+cell(RM_IHPSG13_1P_1024x16_c2_bm_bist) {
+pg_pin (VDD) {
+  pg_type : primary_power;
+  voltage_name : VDD;
+}
+pg_pin (VDDARRAY) {
+  pg_type : primary_power;
+  voltage_name : VDDARRAY;
+}
+pg_pin (VSS) {
+  pg_type : primary_ground;
+  voltage_name : VSS;
+}
+
+memory() {
+ type : ram;
+ address_width : 10;
+ word_width : 16;
+}
+
+interface_timing : false;
+bus_naming_style    :   "%s[%d]" ;
+area        : 79673.728 ;
+
+   pin(A_DLY) {
+	   direction       : input ;
+	   capacitance     : 0.00401111 ;
+	   max_transition  : "1" ;
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+		internal_power() {
+		  rise_power("scalar") {
+			 values (0);
+		  }
+		  fall_power("scalar") {
+			 values (0);
+		  }
+	   }
+   }
+
+bus(A_ADDR) {
+   bus_type : A_9_0;
+   direction          : input ;
+   capacitance        : 0.00721489 ;
+    pin(A_ADDR[0]) {
+       capacitance : 0.00593979 ;
+    }
+    pin(A_ADDR[1]) {
+       capacitance : 0.00483009 ;
+    }
+    pin(A_ADDR[2]) {
+       capacitance : 0.006215 ;
+    }
+    pin(A_ADDR[3]) {
+       capacitance : 0.00766726 ;
+    }
+    pin(A_ADDR[4]) {
+       capacitance : 0.00488951 ;
+    }
+    pin(A_ADDR[5]) {
+       capacitance : 0.0091523 ;
+    }
+    pin(A_ADDR[6]) {
+       capacitance : 0.0109212 ;
+    }
+    pin(A_ADDR[7]) {
+       capacitance : 0.00774122 ;
+    }
+    pin(A_ADDR[8]) {
+       capacitance : 0.0101403 ;
+    }
+   max_transition     : "0.476" ;
+   pin(A_ADDR[9:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0120);
+		}
+		        fall_power("scalar"){
+		 values (0.0063);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0204);
+		}
+		        fall_power("scalar"){
+		 values (0.0012);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "((A_WEN | A_REN)& A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\
+"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\
+"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\
+"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\
+"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\
+"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\
+"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\
+"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\
+"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\
+"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\
+"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\
+"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\
+"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "((A_WEN | A_REN)& A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\
+"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\
+"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\
+"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\
+"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\
+"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\
+"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\
+"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\
+"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\
+"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\
+"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\
+"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\
+"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387");
+		}
+	}
+}
+pin(A_WEN) {
+   direction          : input ;
+   capacitance        : 0.00324098 ;
+   max_transition     : "0.476" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0046);
+		}
+		        fall_power("scalar"){
+		 values (0.0039);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0043);
+		}
+		        fall_power("scalar"){
+		 values (0.0040);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\
+"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\
+"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\
+"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\
+"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\
+"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\
+"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\
+"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\
+"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\
+"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\
+"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\
+"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\
+"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\
+"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\
+"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\
+"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\
+"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\
+"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\
+"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\
+"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\
+"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\
+"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\
+"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\
+"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\
+"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512");
+		}
+	}
+	}
+pin(A_REN) {
+   direction          : input ;
+   capacitance        : 0.00381634 ;
+   max_transition     : "0.476" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0061);
+		}
+		        fall_power("scalar"){
+		 values (0.0021);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0062);
+		}
+		        fall_power("scalar"){
+		 values (0.0025);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\
+"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\
+"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\
+"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\
+"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\
+"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\
+"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\
+"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\
+"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\
+"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\
+"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\
+"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\
+"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\
+"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\
+"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\
+"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\
+"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\
+"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\
+"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\
+"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\
+"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\
+"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\
+"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\
+"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\
+"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707");
+		}
+	}
+	}
+pin(A_MEN) {
+   direction          : input ;
+   capacitance        : 0.00309605 ;
+   max_transition     : "0.476" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		        rise_power("scalar"){
+		 values (0.0448);
+		}
+		        fall_power("scalar"){
+		 values (0.0052);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\
+"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\
+"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\
+"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\
+"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\
+"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\
+"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\
+"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\
+"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\
+"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\
+"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\
+"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\
+"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\
+"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\
+"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\
+"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\
+"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\
+"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\
+"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\
+"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\
+"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\
+"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\
+"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\
+"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\
+"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512");
+		}
+	}
+	}
+bus(A_BM) {
+   bus_type : D_15_0;
+   direction          : input ;
+   capacitance        : 0.00285703 ;
+   max_transition     : "0.476" ;
+   pin(A_BM[15:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0592);
+		}
+		        fall_power("scalar"){
+		 values (0.0247);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0603);
+		}
+		        fall_power("scalar"){
+		 values (0.0245);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "(A_WEN & A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.3412,-0.3246,-0.3119,-0.2796,-0.2328,-0.1283,0.0641",\
+"-0.3462,-0.3296,-0.3169,-0.2847,-0.2378,-0.1333,0.0591",\
+"-0.3506,-0.3340,-0.3213,-0.2891,-0.2422,-0.1377,0.0547",\
+"-0.3605,-0.3439,-0.3312,-0.2989,-0.2521,-0.1476,0.0448",\
+"-0.3668,-0.3502,-0.3375,-0.3053,-0.2584,-0.1539,0.0385",\
+"-0.4033,-0.3867,-0.3740,-0.3418,-0.2949,-0.1904,0.0020",\
+"-0.4542,-0.4376,-0.4249,-0.3926,-0.3458,-0.2413,-0.0489");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.3089,-0.2933,-0.2806,-0.2523,-0.2015,-0.1029,0.0758",\
+"-0.3140,-0.2983,-0.2856,-0.2573,-0.2065,-0.1079,0.0708",\
+"-0.3184,-0.3028,-0.2901,-0.2617,-0.2110,-0.1123,0.0664",\
+"-0.3282,-0.3126,-0.2999,-0.2716,-0.2208,-0.1222,0.0565",\
+"-0.3346,-0.3189,-0.3062,-0.2779,-0.2271,-0.1285,0.0502",\
+"-0.3711,-0.3554,-0.3427,-0.3144,-0.2636,-0.1650,0.0137",\
+"-0.4219,-0.4063,-0.3936,-0.3653,-0.3145,-0.2159,-0.0372");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "(A_WEN & A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.4501,0.4345,0.4218,0.3895,0.3407,0.2421,0.0458",\
+"0.4551,0.4395,0.4268,0.3946,0.3457,0.2471,0.0508",\
+"0.4595,0.4439,0.4312,0.3990,0.3502,0.2515,0.0552",\
+"0.4694,0.4537,0.4411,0.4088,0.3600,0.2614,0.0651",\
+"0.4757,0.4601,0.4474,0.4152,0.3663,0.2677,0.0714",\
+"0.5122,0.4966,0.4839,0.4517,0.4028,0.3042,0.1079",\
+"0.5631,0.5475,0.5348,0.5025,0.4537,0.3551,0.1588");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.4100,0.3954,0.3817,0.3534,0.3026,0.2099,0.0214",\
+"0.4151,0.4004,0.3867,0.3584,0.3076,0.2149,0.0264",\
+"0.4195,0.4048,0.3912,0.3628,0.3121,0.2193,0.0308",\
+"0.4293,0.4147,0.4010,0.3727,0.3219,0.2291,0.0407",\
+"0.4357,0.4210,0.4074,0.3790,0.3283,0.2355,0.0470",\
+"0.4722,0.4575,0.4438,0.4155,0.3647,0.2720,0.0835",\
+"0.5230,0.5084,0.4947,0.4664,0.4156,0.3228,0.1344");
+		}
+	}
+}
+   pin(A_CLK)  {
+	   direction       : input;
+	   capacitance     : 0.00380014;
+	   max_transition  : "0.476";
+	   clock           : "true" ;
+	   pin_func_type   : active_rising ;
+
+	   timing () {
+		 timing_type : "min_pulse_width";
+		 related_pin : "A_CLK";
+		 rise_constraint("CLKTRAN_constraint_template") {
+		 index_1("0.0056,0.476");
+		 values("0.21,0.21");
+		 }
+	   }
+
+	   related_power_pin : VDD;
+	   related_ground_pin : VSS;
+
+	internal_power() {
+		when : "!A_MEN  & !A_WEN & !A_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN  & A_WEN  & !A_REN";
+		        rise_power("scalar"){
+		 values (0.5466);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & A_WEN  & !A_REN";
+		        rise_power("scalar"){
+		 values (32.9180);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & A_WEN  & A_REN";
+		        rise_power("scalar"){
+		 values (33.7600);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & !A_WEN & A_REN";
+		        rise_power("scalar"){
+		 values (26.4863);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN & !A_WEN & A_REN";
+		        rise_power("scalar"){
+		 values (0.3253);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN & A_WEN  & A_REN";
+		        rise_power("scalar"){
+		 values (0.7651);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & !A_WEN & !A_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	}
+   bus(A_DIN) {
+	   bus_type : D_15_0;
+	   direction       : input ;
+	   capacitance     : 0.00365723 ;
+	   memory_write() {
+		   address : A_ADDR ;
+		   clocked_on : A_CLK;
+	   }
+
+	   max_transition  : "0.476" ;
+	   pin(A_DIN[15:0]) {
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0592);
+		}
+		        fall_power("scalar"){
+		 values (0.0247);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0603);
+		}
+		        fall_power("scalar"){
+		 values (0.0245);
+		}
+	}
+	   }
+	   timing() {
+		 timing_type     : setup_rising;
+		 related_pin     : "A_CLK";
+		 when            : "(A_WEN & A_MEN)";
+		 sdf_cond        : "A_W_ACCESS";
+
+	  rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 values ("-0.3412,-0.3246,-0.3119,-0.2796,-0.2328,-0.1283,0.0641",\
+"-0.3462,-0.3296,-0.3169,-0.2847,-0.2378,-0.1333,0.0591",\
+"-0.3506,-0.3340,-0.3213,-0.2891,-0.2422,-0.1377,0.0547",\
+"-0.3605,-0.3439,-0.3312,-0.2989,-0.2521,-0.1476,0.0448",\
+"-0.3668,-0.3502,-0.3375,-0.3053,-0.2584,-0.1539,0.0385",\
+"-0.4033,-0.3867,-0.3740,-0.3418,-0.2949,-0.1904,0.0020",\
+"-0.4542,-0.4376,-0.4249,-0.3926,-0.3458,-0.2413,-0.0489");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 values ("-0.3089,-0.2933,-0.2806,-0.2523,-0.2015,-0.1029,0.0758",\
+"-0.3140,-0.2983,-0.2856,-0.2573,-0.2065,-0.1079,0.0708",\
+"-0.3184,-0.3028,-0.2901,-0.2617,-0.2110,-0.1123,0.0664",\
+"-0.3282,-0.3126,-0.2999,-0.2716,-0.2208,-0.1222,0.0565",\
+"-0.3346,-0.3189,-0.3062,-0.2779,-0.2271,-0.1285,0.0502",\
+"-0.3711,-0.3554,-0.3427,-0.3144,-0.2636,-0.1650,0.0137",\
+"-0.4219,-0.4063,-0.3936,-0.3653,-0.3145,-0.2159,-0.0372");
+		 }
+	   }
+
+	   timing() {
+		 timing_type     : hold_rising;
+		 related_pin     : "A_CLK";
+		 when            : "(A_WEN & A_MEN)";
+		 sdf_cond        : "A_W_ACCESS";
+
+	   rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 values ("0.4501,0.4345,0.4218,0.3895,0.3407,0.2421,0.0458",\
+"0.4551,0.4395,0.4268,0.3946,0.3457,0.2471,0.0508",\
+"0.4595,0.4439,0.4312,0.3990,0.3502,0.2515,0.0552",\
+"0.4694,0.4537,0.4411,0.4088,0.3600,0.2614,0.0651",\
+"0.4757,0.4601,0.4474,0.4152,0.3663,0.2677,0.0714",\
+"0.5122,0.4966,0.4839,0.4517,0.4028,0.3042,0.1079",\
+"0.5631,0.5475,0.5348,0.5025,0.4537,0.3551,0.1588");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 values ("0.4100,0.3954,0.3817,0.3534,0.3026,0.2099,0.0214",\
+"0.4151,0.4004,0.3867,0.3584,0.3076,0.2149,0.0264",\
+"0.4195,0.4048,0.3912,0.3628,0.3121,0.2193,0.0308",\
+"0.4293,0.4147,0.4010,0.3727,0.3219,0.2291,0.0407",\
+"0.4357,0.4210,0.4074,0.3790,0.3283,0.2355,0.0470",\
+"0.4722,0.4575,0.4438,0.4155,0.3647,0.2720,0.0835",\
+"0.5230,0.5084,0.4947,0.4664,0.4156,0.3228,0.1344");
+		 }
+	   }
+   }
+
+   pin(A_BIST_EN) {
+	   direction       : input ;
+	   capacitance     : 0.00401111 ;
+	   max_transition  : "1" ;
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+		internal_power() {
+		  rise_power("scalar") {
+			 values (0);
+		  }
+		  fall_power("scalar") {
+			 values (0);
+		  }
+	   }
+   }
+
+bus(A_BIST_ADDR) {
+   bus_type : A_9_0;
+   direction          : input ;
+   capacitance        : 0.00721489 ;
+    pin(A_BIST_ADDR[0]) {
+       capacitance : 0.00593979 ;
+    }
+    pin(A_BIST_ADDR[1]) {
+       capacitance : 0.00483009 ;
+    }
+    pin(A_BIST_ADDR[2]) {
+       capacitance : 0.006215 ;
+    }
+    pin(A_BIST_ADDR[3]) {
+       capacitance : 0.00766726 ;
+    }
+    pin(A_BIST_ADDR[4]) {
+       capacitance : 0.00488951 ;
+    }
+    pin(A_BIST_ADDR[5]) {
+       capacitance : 0.0091523 ;
+    }
+    pin(A_BIST_ADDR[6]) {
+       capacitance : 0.0109212 ;
+    }
+    pin(A_BIST_ADDR[7]) {
+       capacitance : 0.00774122 ;
+    }
+    pin(A_BIST_ADDR[8]) {
+       capacitance : 0.0101403 ;
+    }
+   max_transition     : "0.476" ;
+   pin(A_BIST_ADDR[9:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0120);
+		}
+		        fall_power("scalar"){
+		 values (0.0063);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0204);
+		}
+		        fall_power("scalar"){
+		 values (0.0012);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\
+"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\
+"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\
+"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\
+"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\
+"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\
+"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\
+"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\
+"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\
+"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\
+"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\
+"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\
+"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\
+"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\
+"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\
+"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\
+"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\
+"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\
+"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\
+"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\
+"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\
+"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\
+"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\
+"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\
+"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387");
+		}
+	}
+}
+pin(A_BIST_WEN) {
+   direction          : input ;
+   capacitance        : 0.00324098 ;
+   max_transition     : "0.476" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0046);
+		}
+		        fall_power("scalar"){
+		 values (0.0039);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0043);
+		}
+		        fall_power("scalar"){
+		 values (0.0040);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\
+"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\
+"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\
+"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\
+"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\
+"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\
+"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\
+"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\
+"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\
+"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\
+"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\
+"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\
+"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\
+"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\
+"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\
+"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\
+"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\
+"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\
+"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\
+"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\
+"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\
+"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\
+"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\
+"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\
+"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512");
+		}
+	}
+	}
+pin(A_BIST_REN) {
+   direction          : input ;
+   capacitance        : 0.00381634 ;
+   max_transition     : "0.476" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0061);
+		}
+		        fall_power("scalar"){
+		 values (0.0021);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0062);
+		}
+		        fall_power("scalar"){
+		 values (0.0025);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\
+"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\
+"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\
+"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\
+"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\
+"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\
+"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\
+"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\
+"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\
+"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\
+"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\
+"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\
+"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\
+"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\
+"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\
+"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\
+"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\
+"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\
+"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\
+"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\
+"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\
+"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\
+"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\
+"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\
+"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707");
+		}
+	}
+	}
+pin(A_BIST_MEN) {
+   direction          : input ;
+   capacitance        : 0.00309605 ;
+   max_transition     : "0.476" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		        rise_power("scalar"){
+		 values (0.0448);
+		}
+		        fall_power("scalar"){
+		 values (0.0052);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\
+"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\
+"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\
+"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\
+"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\
+"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\
+"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\
+"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\
+"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\
+"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\
+"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\
+"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\
+"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\
+"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\
+"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\
+"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\
+"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\
+"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\
+"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\
+"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\
+"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\
+"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\
+"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\
+"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\
+"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512");
+		}
+	}
+	}
+bus(A_BIST_BM) {
+   bus_type : D_15_0;
+   direction          : input ;
+   capacitance        : 0.00238379 ;
+   max_transition     : "0.476" ;
+   pin(A_BIST_BM[15:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0592);
+		}
+		        fall_power("scalar"){
+		 values (0.0247);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0603);
+		}
+		        fall_power("scalar"){
+		 values (0.0245);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "(A_BIST_WEN & A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.3412,-0.3246,-0.3119,-0.2796,-0.2328,-0.1283,0.0641",\
+"-0.3462,-0.3296,-0.3169,-0.2847,-0.2378,-0.1333,0.0591",\
+"-0.3506,-0.3340,-0.3213,-0.2891,-0.2422,-0.1377,0.0547",\
+"-0.3605,-0.3439,-0.3312,-0.2989,-0.2521,-0.1476,0.0448",\
+"-0.3668,-0.3502,-0.3375,-0.3053,-0.2584,-0.1539,0.0385",\
+"-0.4033,-0.3867,-0.3740,-0.3418,-0.2949,-0.1904,0.0020",\
+"-0.4542,-0.4376,-0.4249,-0.3926,-0.3458,-0.2413,-0.0489");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.3089,-0.2933,-0.2806,-0.2523,-0.2015,-0.1029,0.0758",\
+"-0.3140,-0.2983,-0.2856,-0.2573,-0.2065,-0.1079,0.0708",\
+"-0.3184,-0.3028,-0.2901,-0.2617,-0.2110,-0.1123,0.0664",\
+"-0.3282,-0.3126,-0.2999,-0.2716,-0.2208,-0.1222,0.0565",\
+"-0.3346,-0.3189,-0.3062,-0.2779,-0.2271,-0.1285,0.0502",\
+"-0.3711,-0.3554,-0.3427,-0.3144,-0.2636,-0.1650,0.0137",\
+"-0.4219,-0.4063,-0.3936,-0.3653,-0.3145,-0.2159,-0.0372");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "(A_BIST_WEN & A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.4501,0.4345,0.4218,0.3895,0.3407,0.2421,0.0458",\
+"0.4551,0.4395,0.4268,0.3946,0.3457,0.2471,0.0508",\
+"0.4595,0.4439,0.4312,0.3990,0.3502,0.2515,0.0552",\
+"0.4694,0.4537,0.4411,0.4088,0.3600,0.2614,0.0651",\
+"0.4757,0.4601,0.4474,0.4152,0.3663,0.2677,0.0714",\
+"0.5122,0.4966,0.4839,0.4517,0.4028,0.3042,0.1079",\
+"0.5631,0.5475,0.5348,0.5025,0.4537,0.3551,0.1588");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.4100,0.3954,0.3817,0.3534,0.3026,0.2099,0.0214",\
+"0.4151,0.4004,0.3867,0.3584,0.3076,0.2149,0.0264",\
+"0.4195,0.4048,0.3912,0.3628,0.3121,0.2193,0.0308",\
+"0.4293,0.4147,0.4010,0.3727,0.3219,0.2291,0.0407",\
+"0.4357,0.4210,0.4074,0.3790,0.3283,0.2355,0.0470",\
+"0.4722,0.4575,0.4438,0.4155,0.3647,0.2720,0.0835",\
+"0.5230,0.5084,0.4947,0.4664,0.4156,0.3228,0.1344");
+		}
+	}
+}
+   pin(A_BIST_CLK)  {
+	   direction       : input;
+	   capacitance     : 0.00380014;
+	   max_transition  : "0.476";
+	   clock           : "true" ;
+	   pin_func_type   : active_rising ;
+
+	   timing () {
+		 timing_type : "min_pulse_width";
+		 related_pin : "A_BIST_CLK";
+		 rise_constraint("CLKTRAN_constraint_template") {
+		 index_1("0.0056,0.476");
+		 values("0.21,0.21");
+		 }
+	   }
+
+	   related_power_pin : VDD;
+	   related_ground_pin : VSS;
+
+	internal_power() {
+		when : "!A_BIST_MEN  & !A_BIST_WEN & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN  & A_BIST_WEN  & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0.5466);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & A_BIST_WEN  & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (32.9180);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & A_BIST_WEN  & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (33.7600);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & !A_BIST_WEN & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (26.4863);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0.3253);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN & A_BIST_WEN  & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0.7651);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & !A_BIST_WEN & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	}
+   bus(A_BIST_DIN) {
+	   bus_type : D_15_0;
+	   direction       : input ;
+	   capacitance     : 0.00233858 ;
+	   memory_write() {
+		   address : A_BIST_ADDR ;
+		   clocked_on : A_BIST_CLK;
+	   }
+
+	   max_transition  : "0.476" ;
+	   pin(A_BIST_DIN[15:0]) {
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0592);
+		}
+		        fall_power("scalar"){
+		 values (0.0247);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0603);
+		}
+		        fall_power("scalar"){
+		 values (0.0245);
+		}
+	}
+	   }
+	   timing() {
+		 timing_type     : setup_rising;
+		 related_pin     : "A_BIST_CLK";
+		 when            : "(A_BIST_WEN & A_BIST_MEN)";
+		 sdf_cond        : "A_BIST_W_ACCESS";
+
+	  rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 values ("-0.3412,-0.3246,-0.3119,-0.2796,-0.2328,-0.1283,0.0641",\
+"-0.3462,-0.3296,-0.3169,-0.2847,-0.2378,-0.1333,0.0591",\
+"-0.3506,-0.3340,-0.3213,-0.2891,-0.2422,-0.1377,0.0547",\
+"-0.3605,-0.3439,-0.3312,-0.2989,-0.2521,-0.1476,0.0448",\
+"-0.3668,-0.3502,-0.3375,-0.3053,-0.2584,-0.1539,0.0385",\
+"-0.4033,-0.3867,-0.3740,-0.3418,-0.2949,-0.1904,0.0020",\
+"-0.4542,-0.4376,-0.4249,-0.3926,-0.3458,-0.2413,-0.0489");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 values ("-0.3089,-0.2933,-0.2806,-0.2523,-0.2015,-0.1029,0.0758",\
+"-0.3140,-0.2983,-0.2856,-0.2573,-0.2065,-0.1079,0.0708",\
+"-0.3184,-0.3028,-0.2901,-0.2617,-0.2110,-0.1123,0.0664",\
+"-0.3282,-0.3126,-0.2999,-0.2716,-0.2208,-0.1222,0.0565",\
+"-0.3346,-0.3189,-0.3062,-0.2779,-0.2271,-0.1285,0.0502",\
+"-0.3711,-0.3554,-0.3427,-0.3144,-0.2636,-0.1650,0.0137",\
+"-0.4219,-0.4063,-0.3936,-0.3653,-0.3145,-0.2159,-0.0372");
+		 }
+	   }
+
+	   timing() {
+		 timing_type     : hold_rising;
+		 related_pin     : "A_BIST_CLK";
+		 when            : "(A_BIST_WEN & A_BIST_MEN)";
+		 sdf_cond        : "A_BIST_W_ACCESS";
+
+	   rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 values ("0.4501,0.4345,0.4218,0.3895,0.3407,0.2421,0.0458",\
+"0.4551,0.4395,0.4268,0.3946,0.3457,0.2471,0.0508",\
+"0.4595,0.4439,0.4312,0.3990,0.3502,0.2515,0.0552",\
+"0.4694,0.4537,0.4411,0.4088,0.3600,0.2614,0.0651",\
+"0.4757,0.4601,0.4474,0.4152,0.3663,0.2677,0.0714",\
+"0.5122,0.4966,0.4839,0.4517,0.4028,0.3042,0.1079",\
+"0.5631,0.5475,0.5348,0.5025,0.4537,0.3551,0.1588");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 values ("0.4100,0.3954,0.3817,0.3534,0.3026,0.2099,0.0214",\
+"0.4151,0.4004,0.3867,0.3584,0.3076,0.2149,0.0264",\
+"0.4195,0.4048,0.3912,0.3628,0.3121,0.2193,0.0308",\
+"0.4293,0.4147,0.4010,0.3727,0.3219,0.2291,0.0407",\
+"0.4357,0.4210,0.4074,0.3790,0.3283,0.2355,0.0470",\
+"0.4722,0.4575,0.4438,0.4155,0.3647,0.2720,0.0835",\
+"0.5230,0.5084,0.4947,0.4664,0.4156,0.3228,0.1344");
+		 }
+	   }
+   }
+
+bus(A_DOUT) {
+
+	   bus_type : D_15_0;
+	   direction       : output ;
+	   capacitance     : 0 ;
+	   max_capacitance  : "6.4e-14" ;
+	   memory_read() {
+		  address : A_ADDR ;
+	   }
+	   pin(A_DOUT[15:0]) {
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+	   internal_power() {
+		  rise_power("scalar") {
+			 values (0);
+		  }
+		  fall_power("scalar") {
+			 values (0);
+		  }
+	   }
+	   }
+	   timing() {
+		 related_pin   : "A_CLK";
+		 timing_type   : rising_edge ;
+		 timing_sense  : non_unate ;
+
+	   cell_rise(SIG2SRAM_delay_template) {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("4.2547,4.2563,4.2639,4.2726,4.3051,4.3409",\
+"4.2648,4.2664,4.2740,4.2828,4.3152,4.3511",\
+"4.2694,4.2710,4.2787,4.2874,4.3198,4.3557",\
+"4.2772,4.2788,4.2865,4.2952,4.3276,4.3635",\
+"4.2847,4.2863,4.2940,4.3027,4.3351,4.3710",\
+"4.3198,4.3214,4.3291,4.3378,4.3702,4.4061",\
+"4.3732,4.3748,4.3824,4.3911,4.4236,4.4594");
+	   }
+	   cell_fall(SIG2SRAM_delay_template) {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("4.1936,4.1949,4.2009,4.2081,4.2346,4.2612",\
+"4.2037,4.2050,4.2110,4.2182,4.2447,4.2713",\
+"4.2083,4.2097,4.2157,4.2228,4.2493,4.2759",\
+"4.2161,4.2175,4.2235,4.2306,4.2571,4.2837",\
+"4.2237,4.2250,4.2310,4.2381,4.2646,4.2913",\
+"4.2587,4.2601,4.2661,4.2732,4.2997,4.3264",\
+"4.3121,4.3134,4.3194,4.3266,4.3531,4.3797");
+	   }
+
+	   rise_transition(SRAM_load_template) {
+		 index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("0.0326,0.0341,0.0428,0.0518,0.0923,0.1492");
+	   }
+	   fall_transition(SRAM_load_template) {
+		 index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("0.0254,0.0265,0.0335,0.0402,0.0707,0.1039");
+	   }
+	}
+}
+cell_leakage_power : 198.0155;
+}
+}
diff --git a/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_1024x8_c2_bm_bist_fast_1p32V_m55C.lib b/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_1024x8_c2_bm_bist_fast_1p32V_m55C.lib
new file mode 100644
index 00000000..1010183c
--- /dev/null
+++ b/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_1024x8_c2_bm_bist_fast_1p32V_m55C.lib
@@ -0,0 +1,1525 @@
+/* ------------------------------------------------------*/
+/**/
+/*		Copyright 2024 IHP PDK Authors*/
+/**/
+/*		Licensed under the Apache License, Version 2.0 (the "License");*/
+/*		you may not use this file except in compliance with the License.*/
+/*		You may obtain a copy of the License at*/
+/*		*/
+/*		   https://www.apache.org/licenses/LICENSE-2.0*/
+/*		*/
+/*		Unless required by applicable law or agreed to in writing, software*/
+/*		distributed under the License is distributed on an "AS IS" BASIS,*/
+/*		WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/
+/*		See the License for the specific language governing permissions and*/
+/*		limitations under the License.*/
+/*		*/
+/*		Generated on Fri Jul 19 09:01:12 2024		*/
+/*				*/
+/* ------------------------------------------------------ */
+library(RM_IHPSG13_1P_1024x8_c2_bm_bist_fast_1p32V_m55C) {	
+	technology (cmos) ;
+	delay_model : table_lookup ;
+	define ("add_pg_pin_to_lib",  "library",  "boolean");
+	add_pg_pin_to_lib : true;
+	voltage_map ( VDD, 1.32);
+	voltage_map ( VDDARRAY, 1.32);
+	voltage_map ( VSS, 0.000000 );
+	
+	date            : "Fri Jul 19 09:01:10 2024" ;
+	comment         : "IHP Microelectronics GmbH, 2024" ;
+	revision        : 1.0.0 ;
+	simulation      : true ;
+	nom_process     : 1 ;
+	nom_temperature : -55 ;
+	nom_voltage     : 1.32 ;
+	
+	operating_conditions("fast_1p32V_m55C"){
+	    process     : 1 ;
+	    temperature : -55 ;
+	    voltage     : 1.32 ;
+	    tree_type   : "balanced_tree" ;
+	}
+	
+	default_operating_conditions  : fast_1p32V_m55C ;
+	default_max_transition        : 1.0 ;
+	default_fanout_load           : 1.0 ;
+	default_inout_pin_cap         : 0.0 ;
+	default_input_pin_cap         : 0.0 ;
+	default_output_pin_cap        : 0.0 ;
+	default_cell_leakage_power    : 0.0 ;
+	default_leakage_power_density : 0.0 ;
+	 
+	slew_lower_threshold_pct_rise : 30 ;
+	slew_upper_threshold_pct_rise : 70 ;
+	input_threshold_pct_fall      : 50 ;
+	output_threshold_pct_fall     : 50 ;
+	input_threshold_pct_rise      : 50 ;
+	output_threshold_pct_rise     : 50 ;
+	slew_lower_threshold_pct_fall : 30 ;
+	slew_upper_threshold_pct_fall : 70 ;
+	slew_derate_from_library      : 0.5;
+	k_volt_cell_leakage_power     : 0.0 ;
+	k_temp_cell_leakage_power     : 0.0 ;
+	k_process_cell_leakage_power  : 0.0 ;
+	k_volt_internal_power         : 0.0 ;
+	k_temp_internal_power         : 0.0 ;
+	k_process_internal_power      : 0.0 ;
+	
+	capacitive_load_unit            (1,pf) ;
+	voltage_unit                  : "1V" ;
+	current_unit                  : "1uA" ;
+	time_unit                     : "1ns" ;
+	leakage_power_unit            : "1nW" ;
+	pulling_resistance_unit       : "1kohm";
+	/*
+	  ------------------------------------------------------------------------------------------
+	  implicit units overview:
+	    cell_area       unit      : "um"
+	    internal_power  unit      : "1e-12 * J/toggle = 1 * uW/MHz"
+	                                (capacitive_load_unit * voltage_unit^2) per toggle event
+	  ------------------------------------------------------------------------------------------
+	*/
+	library_features(report_delay_calculation);
+	define_cell_area (pad_drivers,pad_driver_sites) ;
+	
+	lu_table_template(CLKTRAN_constraint_template) {
+	     variable_1 : constrained_pin_transition;
+	     index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" );
+	}
+	lu_table_template(SRAM_load_template) {
+	     variable_1 : total_output_net_capacitance;
+	     index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" );
+	}
+	lu_table_template(SIG2SRAM_constraint_template) {
+	     variable_1 : related_pin_transition;
+	     variable_2 : constrained_pin_transition;
+	     index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" );
+	     index_2 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" );
+	}
+	
+	lu_table_template(SIG2SRAM_delay_template) {
+	     variable_1 : input_net_transition;
+	     variable_2 : total_output_net_capacitance;
+	     index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" );
+	     index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" );
+	} 
+
+	type (D_7_0) {
+		base_type : array;
+		data_type : bit;
+		bit_width : 8;
+		bit_from  : 7;
+		bit_to    : 0;
+		downto    : true;
+	 }
+
+	type (A_9_0) {
+		base_type : array;
+		data_type : bit;
+		bit_width : 10;
+		bit_from  : 9;
+		bit_to    : 0;
+		downto    : true;
+	 }
+
+cell(RM_IHPSG13_1P_1024x8_c2_bm_bist) {
+pg_pin (VDD) {
+  pg_type : primary_power;
+  voltage_name : VDD;
+}
+pg_pin (VDDARRAY) {
+  pg_type : primary_power;
+  voltage_name : VDDARRAY;
+}
+pg_pin (VSS) {
+  pg_type : primary_ground;
+  voltage_name : VSS;
+}
+
+memory() {
+ type : ram;
+ address_width : 10;
+ word_width : 8;
+}
+
+interface_timing : false;
+bus_naming_style    :   "%s[%d]" ;
+area        : 49419.2448 ;
+
+   pin(A_DLY) {
+	   direction       : input ;
+	   capacitance     : 0.00421562 ;
+	   max_transition  : "1" ;
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+		internal_power() {
+		  rise_power("scalar") {
+			 values (0);
+		  }
+		  fall_power("scalar") {
+			 values (0);
+		  }
+	   }
+   }
+
+bus(A_ADDR) {
+   bus_type : A_9_0;
+   direction          : input ;
+   capacitance        : 0.00691085 ;
+    pin(A_ADDR[0]) {
+       capacitance : 0.00562034 ;
+    }
+    pin(A_ADDR[1]) {
+       capacitance : 0.00462655 ;
+    }
+    pin(A_ADDR[2]) {
+       capacitance : 0.00594295 ;
+    }
+    pin(A_ADDR[3]) {
+       capacitance : 0.00723434 ;
+    }
+    pin(A_ADDR[4]) {
+       capacitance : 0.00481603 ;
+    }
+    pin(A_ADDR[5]) {
+       capacitance : 0.00868123 ;
+    }
+    pin(A_ADDR[6]) {
+       capacitance : 0.010187 ;
+    }
+    pin(A_ADDR[7]) {
+       capacitance : 0.00734489 ;
+    }
+    pin(A_ADDR[8]) {
+       capacitance : 0.00904175 ;
+    }
+   max_transition     : "0.38" ;
+   pin(A_ADDR[9:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0799);
+		}
+		        fall_power("scalar"){
+		 values (0.0925);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0267);
+		}
+		        fall_power("scalar"){
+		 values (0.0027);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "((A_WEN | A_REN)& A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\
+"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\
+"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\
+"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\
+"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\
+"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\
+"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\
+"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\
+"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\
+"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\
+"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\
+"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\
+"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "((A_WEN | A_REN)& A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\
+"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\
+"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\
+"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\
+"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\
+"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\
+"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\
+"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\
+"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\
+"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\
+"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\
+"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\
+"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902");
+		}
+	}
+}
+pin(A_WEN) {
+   direction          : input ;
+   capacitance        : 0.00341384 ;
+   max_transition     : "0.38" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.1397);
+		}
+		        fall_power("scalar"){
+		 values (0.0161);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0060);
+		}
+		        fall_power("scalar"){
+		 values (0.0209);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\
+"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\
+"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\
+"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\
+"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\
+"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\
+"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\
+"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\
+"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\
+"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\
+"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\
+"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\
+"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\
+"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\
+"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\
+"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\
+"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\
+"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\
+"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\
+"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\
+"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\
+"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\
+"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\
+"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\
+"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691");
+		}
+	}
+	}
+pin(A_REN) {
+   direction          : input ;
+   capacitance        : 0.00390661 ;
+   max_transition     : "0.38" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0111);
+		}
+		        fall_power("scalar"){
+		 values (0.0105);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0257);
+		}
+		        fall_power("scalar"){
+		 values (0.0199);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\
+"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\
+"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\
+"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\
+"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\
+"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\
+"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\
+"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\
+"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\
+"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\
+"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\
+"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\
+"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\
+"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\
+"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\
+"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\
+"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\
+"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\
+"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\
+"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\
+"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\
+"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\
+"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\
+"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\
+"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809");
+		}
+	}
+	}
+pin(A_MEN) {
+   direction          : input ;
+   capacitance        : 0.00326046 ;
+   max_transition     : "0.38" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		        rise_power("scalar"){
+		 values (0.0783);
+		}
+		        fall_power("scalar"){
+		 values (0.0772);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\
+"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\
+"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\
+"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\
+"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\
+"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\
+"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\
+"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\
+"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\
+"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\
+"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\
+"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\
+"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\
+"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\
+"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\
+"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\
+"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\
+"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\
+"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\
+"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\
+"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\
+"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\
+"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\
+"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\
+"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691");
+		}
+	}
+	}
+bus(A_BM) {
+   bus_type : D_7_0;
+   direction          : input ;
+   capacitance        : 0.00310985 ;
+   max_transition     : "0.38" ;
+   pin(A_BM[7:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0418);
+		}
+		        fall_power("scalar"){
+		 values (0.0388);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0592);
+		}
+		        fall_power("scalar"){
+		 values (0.0451);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "(A_WEN & A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.1576,-0.1468,-0.1312,-0.1048,-0.0648,0.0055,0.1403",\
+"-0.1615,-0.1507,-0.1351,-0.1087,-0.0687,0.0016,0.1364",\
+"-0.1652,-0.1545,-0.1389,-0.1125,-0.0725,-0.0022,0.1326",\
+"-0.1685,-0.1578,-0.1421,-0.1158,-0.0757,-0.0054,0.1293",\
+"-0.1809,-0.1702,-0.1546,-0.1282,-0.0882,-0.0179,0.1169",\
+"-0.1984,-0.1877,-0.1720,-0.1457,-0.1056,-0.0353,0.0994",\
+"-0.2261,-0.2153,-0.1997,-0.1733,-0.1333,-0.0630,0.0718");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.1351,-0.1244,-0.1107,-0.0834,-0.0462,0.0260,0.1559",\
+"-0.1390,-0.1282,-0.1146,-0.0872,-0.0501,0.0221,0.1520",\
+"-0.1428,-0.1320,-0.1184,-0.0910,-0.0539,0.0183,0.1482",\
+"-0.1460,-0.1353,-0.1216,-0.0943,-0.0572,0.0151,0.1450",\
+"-0.1585,-0.1477,-0.1341,-0.1067,-0.0696,0.0026,0.1325",\
+"-0.1759,-0.1652,-0.1515,-0.1242,-0.0871,-0.0148,0.1151",\
+"-0.2036,-0.1929,-0.1792,-0.1518,-0.1147,-0.0425,0.0874");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "(A_WEN & A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2635,0.2517,0.2371,0.2107,0.1707,0.0994,-0.0373",\
+"0.2673,0.2556,0.2410,0.2146,0.1746,0.1033,-0.0334",\
+"0.2711,0.2594,0.2448,0.2184,0.1784,0.1071,-0.0296",\
+"0.2744,0.2627,0.2480,0.2217,0.1816,0.1103,-0.0264",\
+"0.2868,0.2751,0.2605,0.2341,0.1941,0.1228,-0.0139",\
+"0.3043,0.2926,0.2779,0.2516,0.2115,0.1402,0.0035",\
+"0.3320,0.3202,0.3056,0.2792,0.2392,0.1679,0.0312");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2351,0.2254,0.2107,0.1844,0.1473,0.0740,-0.0539",\
+"0.2390,0.2293,0.2146,0.1882,0.1511,0.0779,-0.0500",\
+"0.2428,0.2331,0.2184,0.1920,0.1549,0.0817,-0.0462",\
+"0.2461,0.2363,0.2217,0.1953,0.1582,0.0849,-0.0430",\
+"0.2585,0.2488,0.2341,0.2077,0.1706,0.0974,-0.0305",\
+"0.2760,0.2662,0.2516,0.2252,0.1881,0.1149,-0.0131",\
+"0.3036,0.2939,0.2792,0.2529,0.2157,0.1425,0.0146");
+		}
+	}
+}
+   pin(A_CLK)  {
+	   direction       : input;
+	   capacitance     : 0.00389386;
+	   max_transition  : "0.38";
+	   clock           : "true" ;
+	   pin_func_type   : active_rising ;
+
+	   timing () {
+		 timing_type : "min_pulse_width";
+		 related_pin : "A_CLK";
+		 rise_constraint("CLKTRAN_constraint_template") {
+		 index_1("0.004,0.38");
+		 values("0.12,0.12");
+		 }
+	   }
+
+	   related_power_pin : VDD;
+	   related_ground_pin : VSS;
+
+	internal_power() {
+		when : "!A_MEN  & !A_WEN & !A_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN  & A_WEN  & !A_REN";
+		        rise_power("scalar"){
+		 values (0.6944);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & A_WEN  & !A_REN";
+		        rise_power("scalar"){
+		 values (24.3582);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & A_WEN  & A_REN";
+		        rise_power("scalar"){
+		 values (24.1537);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & !A_WEN & A_REN";
+		        rise_power("scalar"){
+		 values (19.6992);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN & !A_WEN & A_REN";
+		        rise_power("scalar"){
+		 values (0.4036);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN & A_WEN  & A_REN";
+		        rise_power("scalar"){
+		 values (0.6774);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & !A_WEN & !A_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	}
+   bus(A_DIN) {
+	   bus_type : D_7_0;
+	   direction       : input ;
+	   capacitance     : 0.00387207 ;
+	   memory_write() {
+		   address : A_ADDR ;
+		   clocked_on : A_CLK;
+	   }
+
+	   max_transition  : "0.38" ;
+	   pin(A_DIN[7:0]) {
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0418);
+		}
+		        fall_power("scalar"){
+		 values (0.0388);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0592);
+		}
+		        fall_power("scalar"){
+		 values (0.0451);
+		}
+	}
+	   }
+	   timing() {
+		 timing_type     : setup_rising;
+		 related_pin     : "A_CLK";
+		 when            : "(A_WEN & A_MEN)";
+		 sdf_cond        : "A_W_ACCESS";
+
+	  rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 values ("-0.1576,-0.1468,-0.1312,-0.1048,-0.0648,0.0055,0.1403",\
+"-0.1615,-0.1507,-0.1351,-0.1087,-0.0687,0.0016,0.1364",\
+"-0.1652,-0.1545,-0.1389,-0.1125,-0.0725,-0.0022,0.1326",\
+"-0.1685,-0.1578,-0.1421,-0.1158,-0.0757,-0.0054,0.1293",\
+"-0.1809,-0.1702,-0.1546,-0.1282,-0.0882,-0.0179,0.1169",\
+"-0.1984,-0.1877,-0.1720,-0.1457,-0.1056,-0.0353,0.0994",\
+"-0.2261,-0.2153,-0.1997,-0.1733,-0.1333,-0.0630,0.0718");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 values ("-0.1351,-0.1244,-0.1107,-0.0834,-0.0462,0.0260,0.1559",\
+"-0.1390,-0.1282,-0.1146,-0.0872,-0.0501,0.0221,0.1520",\
+"-0.1428,-0.1320,-0.1184,-0.0910,-0.0539,0.0183,0.1482",\
+"-0.1460,-0.1353,-0.1216,-0.0943,-0.0572,0.0151,0.1450",\
+"-0.1585,-0.1477,-0.1341,-0.1067,-0.0696,0.0026,0.1325",\
+"-0.1759,-0.1652,-0.1515,-0.1242,-0.0871,-0.0148,0.1151",\
+"-0.2036,-0.1929,-0.1792,-0.1518,-0.1147,-0.0425,0.0874");
+		 }
+	   }
+
+	   timing() {
+		 timing_type     : hold_rising;
+		 related_pin     : "A_CLK";
+		 when            : "(A_WEN & A_MEN)";
+		 sdf_cond        : "A_W_ACCESS";
+
+	   rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 values ("0.2635,0.2517,0.2371,0.2107,0.1707,0.0994,-0.0373",\
+"0.2673,0.2556,0.2410,0.2146,0.1746,0.1033,-0.0334",\
+"0.2711,0.2594,0.2448,0.2184,0.1784,0.1071,-0.0296",\
+"0.2744,0.2627,0.2480,0.2217,0.1816,0.1103,-0.0264",\
+"0.2868,0.2751,0.2605,0.2341,0.1941,0.1228,-0.0139",\
+"0.3043,0.2926,0.2779,0.2516,0.2115,0.1402,0.0035",\
+"0.3320,0.3202,0.3056,0.2792,0.2392,0.1679,0.0312");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 values ("0.2351,0.2254,0.2107,0.1844,0.1473,0.0740,-0.0539",\
+"0.2390,0.2293,0.2146,0.1882,0.1511,0.0779,-0.0500",\
+"0.2428,0.2331,0.2184,0.1920,0.1549,0.0817,-0.0462",\
+"0.2461,0.2363,0.2217,0.1953,0.1582,0.0849,-0.0430",\
+"0.2585,0.2488,0.2341,0.2077,0.1706,0.0974,-0.0305",\
+"0.2760,0.2662,0.2516,0.2252,0.1881,0.1149,-0.0131",\
+"0.3036,0.2939,0.2792,0.2529,0.2157,0.1425,0.0146");
+		 }
+	   }
+   }
+
+   pin(A_BIST_EN) {
+	   direction       : input ;
+	   capacitance     : 0.00421562 ;
+	   max_transition  : "1" ;
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+		internal_power() {
+		  rise_power("scalar") {
+			 values (0);
+		  }
+		  fall_power("scalar") {
+			 values (0);
+		  }
+	   }
+   }
+
+bus(A_BIST_ADDR) {
+   bus_type : A_9_0;
+   direction          : input ;
+   capacitance        : 0.00691085 ;
+    pin(A_BIST_ADDR[0]) {
+       capacitance : 0.00562034 ;
+    }
+    pin(A_BIST_ADDR[1]) {
+       capacitance : 0.00462655 ;
+    }
+    pin(A_BIST_ADDR[2]) {
+       capacitance : 0.00594295 ;
+    }
+    pin(A_BIST_ADDR[3]) {
+       capacitance : 0.00723434 ;
+    }
+    pin(A_BIST_ADDR[4]) {
+       capacitance : 0.00481603 ;
+    }
+    pin(A_BIST_ADDR[5]) {
+       capacitance : 0.00868123 ;
+    }
+    pin(A_BIST_ADDR[6]) {
+       capacitance : 0.010187 ;
+    }
+    pin(A_BIST_ADDR[7]) {
+       capacitance : 0.00734489 ;
+    }
+    pin(A_BIST_ADDR[8]) {
+       capacitance : 0.00904175 ;
+    }
+   max_transition     : "0.38" ;
+   pin(A_BIST_ADDR[9:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0799);
+		}
+		        fall_power("scalar"){
+		 values (0.0925);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0267);
+		}
+		        fall_power("scalar"){
+		 values (0.0027);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\
+"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\
+"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\
+"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\
+"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\
+"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\
+"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\
+"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\
+"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\
+"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\
+"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\
+"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\
+"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\
+"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\
+"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\
+"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\
+"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\
+"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\
+"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\
+"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\
+"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\
+"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\
+"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\
+"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\
+"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902");
+		}
+	}
+}
+pin(A_BIST_WEN) {
+   direction          : input ;
+   capacitance        : 0.00341384 ;
+   max_transition     : "0.38" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.1397);
+		}
+		        fall_power("scalar"){
+		 values (0.0161);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0060);
+		}
+		        fall_power("scalar"){
+		 values (0.0209);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\
+"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\
+"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\
+"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\
+"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\
+"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\
+"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\
+"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\
+"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\
+"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\
+"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\
+"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\
+"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\
+"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\
+"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\
+"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\
+"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\
+"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\
+"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\
+"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\
+"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\
+"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\
+"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\
+"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\
+"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691");
+		}
+	}
+	}
+pin(A_BIST_REN) {
+   direction          : input ;
+   capacitance        : 0.00390661 ;
+   max_transition     : "0.38" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0111);
+		}
+		        fall_power("scalar"){
+		 values (0.0105);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0257);
+		}
+		        fall_power("scalar"){
+		 values (0.0199);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\
+"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\
+"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\
+"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\
+"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\
+"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\
+"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\
+"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\
+"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\
+"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\
+"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\
+"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\
+"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\
+"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\
+"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\
+"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\
+"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\
+"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\
+"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\
+"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\
+"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\
+"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\
+"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\
+"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\
+"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809");
+		}
+	}
+	}
+pin(A_BIST_MEN) {
+   direction          : input ;
+   capacitance        : 0.00326046 ;
+   max_transition     : "0.38" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		        rise_power("scalar"){
+		 values (0.0783);
+		}
+		        fall_power("scalar"){
+		 values (0.0772);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\
+"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\
+"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\
+"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\
+"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\
+"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\
+"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\
+"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\
+"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\
+"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\
+"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\
+"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\
+"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\
+"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\
+"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\
+"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\
+"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\
+"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\
+"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\
+"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\
+"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\
+"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\
+"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\
+"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\
+"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691");
+		}
+	}
+	}
+bus(A_BIST_BM) {
+   bus_type : D_7_0;
+   direction          : input ;
+   capacitance        : 0.00253457 ;
+   max_transition     : "0.38" ;
+   pin(A_BIST_BM[7:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0418);
+		}
+		        fall_power("scalar"){
+		 values (0.0388);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0592);
+		}
+		        fall_power("scalar"){
+		 values (0.0451);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "(A_BIST_WEN & A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.1576,-0.1468,-0.1312,-0.1048,-0.0648,0.0055,0.1403",\
+"-0.1615,-0.1507,-0.1351,-0.1087,-0.0687,0.0016,0.1364",\
+"-0.1652,-0.1545,-0.1389,-0.1125,-0.0725,-0.0022,0.1326",\
+"-0.1685,-0.1578,-0.1421,-0.1158,-0.0757,-0.0054,0.1293",\
+"-0.1809,-0.1702,-0.1546,-0.1282,-0.0882,-0.0179,0.1169",\
+"-0.1984,-0.1877,-0.1720,-0.1457,-0.1056,-0.0353,0.0994",\
+"-0.2261,-0.2153,-0.1997,-0.1733,-0.1333,-0.0630,0.0718");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.1351,-0.1244,-0.1107,-0.0834,-0.0462,0.0260,0.1559",\
+"-0.1390,-0.1282,-0.1146,-0.0872,-0.0501,0.0221,0.1520",\
+"-0.1428,-0.1320,-0.1184,-0.0910,-0.0539,0.0183,0.1482",\
+"-0.1460,-0.1353,-0.1216,-0.0943,-0.0572,0.0151,0.1450",\
+"-0.1585,-0.1477,-0.1341,-0.1067,-0.0696,0.0026,0.1325",\
+"-0.1759,-0.1652,-0.1515,-0.1242,-0.0871,-0.0148,0.1151",\
+"-0.2036,-0.1929,-0.1792,-0.1518,-0.1147,-0.0425,0.0874");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "(A_BIST_WEN & A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2635,0.2517,0.2371,0.2107,0.1707,0.0994,-0.0373",\
+"0.2673,0.2556,0.2410,0.2146,0.1746,0.1033,-0.0334",\
+"0.2711,0.2594,0.2448,0.2184,0.1784,0.1071,-0.0296",\
+"0.2744,0.2627,0.2480,0.2217,0.1816,0.1103,-0.0264",\
+"0.2868,0.2751,0.2605,0.2341,0.1941,0.1228,-0.0139",\
+"0.3043,0.2926,0.2779,0.2516,0.2115,0.1402,0.0035",\
+"0.3320,0.3202,0.3056,0.2792,0.2392,0.1679,0.0312");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2351,0.2254,0.2107,0.1844,0.1473,0.0740,-0.0539",\
+"0.2390,0.2293,0.2146,0.1882,0.1511,0.0779,-0.0500",\
+"0.2428,0.2331,0.2184,0.1920,0.1549,0.0817,-0.0462",\
+"0.2461,0.2363,0.2217,0.1953,0.1582,0.0849,-0.0430",\
+"0.2585,0.2488,0.2341,0.2077,0.1706,0.0974,-0.0305",\
+"0.2760,0.2662,0.2516,0.2252,0.1881,0.1149,-0.0131",\
+"0.3036,0.2939,0.2792,0.2529,0.2157,0.1425,0.0146");
+		}
+	}
+}
+   pin(A_BIST_CLK)  {
+	   direction       : input;
+	   capacitance     : 0.00389386;
+	   max_transition  : "0.38";
+	   clock           : "true" ;
+	   pin_func_type   : active_rising ;
+
+	   timing () {
+		 timing_type : "min_pulse_width";
+		 related_pin : "A_BIST_CLK";
+		 rise_constraint("CLKTRAN_constraint_template") {
+		 index_1("0.004,0.38");
+		 values("0.12,0.12");
+		 }
+	   }
+
+	   related_power_pin : VDD;
+	   related_ground_pin : VSS;
+
+	internal_power() {
+		when : "!A_BIST_MEN  & !A_BIST_WEN & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN  & A_BIST_WEN  & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0.6944);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & A_BIST_WEN  & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (24.3582);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & A_BIST_WEN  & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (24.1537);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & !A_BIST_WEN & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (19.6992);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0.4036);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN & A_BIST_WEN  & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0.6774);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & !A_BIST_WEN & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	}
+   bus(A_BIST_DIN) {
+	   bus_type : D_7_0;
+	   direction       : input ;
+	   capacitance     : 0.00252927 ;
+	   memory_write() {
+		   address : A_BIST_ADDR ;
+		   clocked_on : A_BIST_CLK;
+	   }
+
+	   max_transition  : "0.38" ;
+	   pin(A_BIST_DIN[7:0]) {
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0418);
+		}
+		        fall_power("scalar"){
+		 values (0.0388);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0592);
+		}
+		        fall_power("scalar"){
+		 values (0.0451);
+		}
+	}
+	   }
+	   timing() {
+		 timing_type     : setup_rising;
+		 related_pin     : "A_BIST_CLK";
+		 when            : "(A_BIST_WEN & A_BIST_MEN)";
+		 sdf_cond        : "A_BIST_W_ACCESS";
+
+	  rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 values ("-0.1576,-0.1468,-0.1312,-0.1048,-0.0648,0.0055,0.1403",\
+"-0.1615,-0.1507,-0.1351,-0.1087,-0.0687,0.0016,0.1364",\
+"-0.1652,-0.1545,-0.1389,-0.1125,-0.0725,-0.0022,0.1326",\
+"-0.1685,-0.1578,-0.1421,-0.1158,-0.0757,-0.0054,0.1293",\
+"-0.1809,-0.1702,-0.1546,-0.1282,-0.0882,-0.0179,0.1169",\
+"-0.1984,-0.1877,-0.1720,-0.1457,-0.1056,-0.0353,0.0994",\
+"-0.2261,-0.2153,-0.1997,-0.1733,-0.1333,-0.0630,0.0718");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 values ("-0.1351,-0.1244,-0.1107,-0.0834,-0.0462,0.0260,0.1559",\
+"-0.1390,-0.1282,-0.1146,-0.0872,-0.0501,0.0221,0.1520",\
+"-0.1428,-0.1320,-0.1184,-0.0910,-0.0539,0.0183,0.1482",\
+"-0.1460,-0.1353,-0.1216,-0.0943,-0.0572,0.0151,0.1450",\
+"-0.1585,-0.1477,-0.1341,-0.1067,-0.0696,0.0026,0.1325",\
+"-0.1759,-0.1652,-0.1515,-0.1242,-0.0871,-0.0148,0.1151",\
+"-0.2036,-0.1929,-0.1792,-0.1518,-0.1147,-0.0425,0.0874");
+		 }
+	   }
+
+	   timing() {
+		 timing_type     : hold_rising;
+		 related_pin     : "A_BIST_CLK";
+		 when            : "(A_BIST_WEN & A_BIST_MEN)";
+		 sdf_cond        : "A_BIST_W_ACCESS";
+
+	   rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 values ("0.2635,0.2517,0.2371,0.2107,0.1707,0.0994,-0.0373",\
+"0.2673,0.2556,0.2410,0.2146,0.1746,0.1033,-0.0334",\
+"0.2711,0.2594,0.2448,0.2184,0.1784,0.1071,-0.0296",\
+"0.2744,0.2627,0.2480,0.2217,0.1816,0.1103,-0.0264",\
+"0.2868,0.2751,0.2605,0.2341,0.1941,0.1228,-0.0139",\
+"0.3043,0.2926,0.2779,0.2516,0.2115,0.1402,0.0035",\
+"0.3320,0.3202,0.3056,0.2792,0.2392,0.1679,0.0312");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 values ("0.2351,0.2254,0.2107,0.1844,0.1473,0.0740,-0.0539",\
+"0.2390,0.2293,0.2146,0.1882,0.1511,0.0779,-0.0500",\
+"0.2428,0.2331,0.2184,0.1920,0.1549,0.0817,-0.0462",\
+"0.2461,0.2363,0.2217,0.1953,0.1582,0.0849,-0.0430",\
+"0.2585,0.2488,0.2341,0.2077,0.1706,0.0974,-0.0305",\
+"0.2760,0.2662,0.2516,0.2252,0.1881,0.1149,-0.0131",\
+"0.3036,0.2939,0.2792,0.2529,0.2157,0.1425,0.0146");
+		 }
+	   }
+   }
+
+bus(A_DOUT) {
+
+	   bus_type : D_7_0;
+	   direction       : output ;
+	   capacitance     : 0 ;
+	   max_capacitance  : "6.4e-14" ;
+	   memory_read() {
+		  address : A_ADDR ;
+	   }
+	   pin(A_DOUT[7:0]) {
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+	   internal_power() {
+		  rise_power("scalar") {
+			 values (0);
+		  }
+		  fall_power("scalar") {
+			 values (0);
+		  }
+	   }
+	   }
+	   timing() {
+		 related_pin   : "A_CLK";
+		 timing_type   : rising_edge ;
+		 timing_sense  : non_unate ;
+
+	   cell_rise(SIG2SRAM_delay_template) {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("2.5949,2.5959,2.6007,2.6062,2.6271,2.6506",\
+"2.6021,2.6031,2.6079,2.6134,2.6343,2.6578",\
+"2.6036,2.6046,2.6094,2.6149,2.6358,2.6593",\
+"2.6069,2.6079,2.6127,2.6183,2.6392,2.6627",\
+"2.6197,2.6207,2.6256,2.6311,2.6520,2.6755",\
+"2.6375,2.6385,2.6433,2.6488,2.6697,2.6932",\
+"2.6629,2.6639,2.6687,2.6742,2.6951,2.7186");
+	   }
+	   cell_fall(SIG2SRAM_delay_template) {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("2.5606,2.5614,2.5655,2.5700,2.5871,2.6038",\
+"2.5678,2.5687,2.5727,2.5772,2.5943,2.6111",\
+"2.5693,2.5701,2.5742,2.5787,2.5958,2.6125",\
+"2.5726,2.5735,2.5775,2.5821,2.5992,2.6159",\
+"2.5854,2.5863,2.5903,2.5949,2.6120,2.6287",\
+"2.6032,2.6041,2.6081,2.6126,2.6297,2.6465",\
+"2.6286,2.6294,2.6335,2.6380,2.6551,2.6718");
+	   }
+
+	   rise_transition(SRAM_load_template) {
+		 index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("0.0206,0.0210,0.0265,0.0323,0.0606,0.0955");
+	   }
+	   fall_transition(SRAM_load_template) {
+		 index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("0.0170,0.0177,0.0222,0.0270,0.0451,0.0644");
+	   }
+	}
+}
+cell_leakage_power : 234.7971;
+}
+}
diff --git a/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_1024x8_c2_bm_bist_slow_1p08V_125C.lib b/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_1024x8_c2_bm_bist_slow_1p08V_125C.lib
new file mode 100644
index 00000000..66a85022
--- /dev/null
+++ b/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_1024x8_c2_bm_bist_slow_1p08V_125C.lib
@@ -0,0 +1,1525 @@
+/* ------------------------------------------------------*/
+/**/
+/*		Copyright 2024 IHP PDK Authors*/
+/**/
+/*		Licensed under the Apache License, Version 2.0 (the "License");*/
+/*		you may not use this file except in compliance with the License.*/
+/*		You may obtain a copy of the License at*/
+/*		*/
+/*		   https://www.apache.org/licenses/LICENSE-2.0*/
+/*		*/
+/*		Unless required by applicable law or agreed to in writing, software*/
+/*		distributed under the License is distributed on an "AS IS" BASIS,*/
+/*		WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/
+/*		See the License for the specific language governing permissions and*/
+/*		limitations under the License.*/
+/*		*/
+/*		Generated on Fri Jul 19 09:01:11 2024		*/
+/*				*/
+/* ------------------------------------------------------ */
+library(RM_IHPSG13_1P_1024x8_c2_bm_bist_slow_1p08V_125C) {	
+	technology (cmos) ;
+	delay_model : table_lookup ;
+	define ("add_pg_pin_to_lib",  "library",  "boolean");
+	add_pg_pin_to_lib : true;
+	voltage_map ( VDD, 1.08);
+	voltage_map ( VDDARRAY, 1.08);
+	voltage_map ( VSS, 0.000000 );
+	
+	date            : "Fri Jul 19 09:01:10 2024" ;
+	comment         : "IHP Microelectronics GmbH, 2024" ;
+	revision        : 1.0.0 ;
+	simulation      : true ;
+	nom_process     : 1 ;
+	nom_temperature : 125 ;
+	nom_voltage     : 1.08 ;
+	
+	operating_conditions("slow_1p08V_125C"){
+	    process     : 1 ;
+	    temperature : 125 ;
+	    voltage     : 1.08 ;
+	    tree_type   : "balanced_tree" ;
+	}
+	
+	default_operating_conditions  : slow_1p08V_125C ;
+	default_max_transition        : 1.0 ;
+	default_fanout_load           : 1.0 ;
+	default_inout_pin_cap         : 0.0 ;
+	default_input_pin_cap         : 0.0 ;
+	default_output_pin_cap        : 0.0 ;
+	default_cell_leakage_power    : 0.0 ;
+	default_leakage_power_density : 0.0 ;
+	 
+	slew_lower_threshold_pct_rise : 30 ;
+	slew_upper_threshold_pct_rise : 70 ;
+	input_threshold_pct_fall      : 50 ;
+	output_threshold_pct_fall     : 50 ;
+	input_threshold_pct_rise      : 50 ;
+	output_threshold_pct_rise     : 50 ;
+	slew_lower_threshold_pct_fall : 30 ;
+	slew_upper_threshold_pct_fall : 70 ;
+	slew_derate_from_library      : 0.5;
+	k_volt_cell_leakage_power     : 0.0 ;
+	k_temp_cell_leakage_power     : 0.0 ;
+	k_process_cell_leakage_power  : 0.0 ;
+	k_volt_internal_power         : 0.0 ;
+	k_temp_internal_power         : 0.0 ;
+	k_process_internal_power      : 0.0 ;
+	
+	capacitive_load_unit            (1,pf) ;
+	voltage_unit                  : "1V" ;
+	current_unit                  : "1uA" ;
+	time_unit                     : "1ns" ;
+	leakage_power_unit            : "1nW" ;
+	pulling_resistance_unit       : "1kohm";
+	/*
+	  ------------------------------------------------------------------------------------------
+	  implicit units overview:
+	    cell_area       unit      : "um"
+	    internal_power  unit      : "1e-12 * J/toggle = 1 * uW/MHz"
+	                                (capacitive_load_unit * voltage_unit^2) per toggle event
+	  ------------------------------------------------------------------------------------------
+	*/
+	library_features(report_delay_calculation);
+	define_cell_area (pad_drivers,pad_driver_sites) ;
+	
+	lu_table_template(CLKTRAN_constraint_template) {
+	     variable_1 : constrained_pin_transition;
+	     index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" );
+	}
+	lu_table_template(SRAM_load_template) {
+	     variable_1 : total_output_net_capacitance;
+	     index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" );
+	}
+	lu_table_template(SIG2SRAM_constraint_template) {
+	     variable_1 : related_pin_transition;
+	     variable_2 : constrained_pin_transition;
+	     index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" );
+	     index_2 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" );
+	}
+	
+	lu_table_template(SIG2SRAM_delay_template) {
+	     variable_1 : input_net_transition;
+	     variable_2 : total_output_net_capacitance;
+	     index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" );
+	     index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" );
+	} 
+
+	type (D_7_0) {
+		base_type : array;
+		data_type : bit;
+		bit_width : 8;
+		bit_from  : 7;
+		bit_to    : 0;
+		downto    : true;
+	 }
+
+	type (A_9_0) {
+		base_type : array;
+		data_type : bit;
+		bit_width : 10;
+		bit_from  : 9;
+		bit_to    : 0;
+		downto    : true;
+	 }
+
+cell(RM_IHPSG13_1P_1024x8_c2_bm_bist) {
+pg_pin (VDD) {
+  pg_type : primary_power;
+  voltage_name : VDD;
+}
+pg_pin (VDDARRAY) {
+  pg_type : primary_power;
+  voltage_name : VDDARRAY;
+}
+pg_pin (VSS) {
+  pg_type : primary_ground;
+  voltage_name : VSS;
+}
+
+memory() {
+ type : ram;
+ address_width : 10;
+ word_width : 8;
+}
+
+interface_timing : false;
+bus_naming_style    :   "%s[%d]" ;
+area        : 49419.2448 ;
+
+   pin(A_DLY) {
+	   direction       : input ;
+	   capacitance     : 0.00387999 ;
+	   max_transition  : "1" ;
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+		internal_power() {
+		  rise_power("scalar") {
+			 values (0);
+		  }
+		  fall_power("scalar") {
+			 values (0);
+		  }
+	   }
+   }
+
+bus(A_ADDR) {
+   bus_type : A_9_0;
+   direction          : input ;
+   capacitance        : 0.0077013 ;
+    pin(A_ADDR[0]) {
+       capacitance : 0.00625349 ;
+    }
+    pin(A_ADDR[1]) {
+       capacitance : 0.00507435 ;
+    }
+    pin(A_ADDR[2]) {
+       capacitance : 0.00656707 ;
+    }
+    pin(A_ADDR[3]) {
+       capacitance : 0.0083133 ;
+    }
+    pin(A_ADDR[4]) {
+       capacitance : 0.00507219 ;
+    }
+    pin(A_ADDR[5]) {
+       capacitance : 0.00964344 ;
+    }
+    pin(A_ADDR[6]) {
+       capacitance : 0.0119653 ;
+    }
+    pin(A_ADDR[7]) {
+       capacitance : 0.00827606 ;
+    }
+    pin(A_ADDR[8]) {
+       capacitance : 0.0110771 ;
+    }
+   max_transition     : "0.5952" ;
+   pin(A_ADDR[9:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0113);
+		}
+		        fall_power("scalar"){
+		 values (0.0087);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0152);
+		}
+		        fall_power("scalar"){
+		 values (0.0041);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "((A_WEN | A_REN)& A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\
+"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\
+"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\
+"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\
+"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\
+"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\
+"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\
+"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\
+"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\
+"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\
+"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\
+"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\
+"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "((A_WEN | A_REN)& A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3098",\
+"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\
+"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\
+"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\
+"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\
+"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\
+"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\
+"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\
+"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\
+"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\
+"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\
+"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\
+"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004");
+		}
+	}
+}
+pin(A_WEN) {
+   direction          : input ;
+   capacitance        : 0.00313551 ;
+   max_transition     : "0.5952" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0036);
+		}
+		        fall_power("scalar"){
+		 values (0.0007);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0050);
+		}
+		        fall_power("scalar"){
+		 values (0.0003);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\
+"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\
+"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\
+"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\
+"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\
+"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\
+"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\
+"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\
+"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\
+"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\
+"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\
+"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\
+"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\
+"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\
+"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\
+"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\
+"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\
+"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\
+"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\
+"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\
+"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\
+"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\
+"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\
+"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\
+"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879");
+		}
+	}
+	}
+pin(A_REN) {
+   direction          : input ;
+   capacitance        : 0.00381144 ;
+   max_transition     : "0.5952" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0041);
+		}
+		        fall_power("scalar"){
+		 values (0.0015);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0041);
+		}
+		        fall_power("scalar"){
+		 values (0.0013);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\
+"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\
+"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\
+"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\
+"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\
+"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\
+"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\
+"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\
+"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\
+"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\
+"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\
+"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\
+"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\
+"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\
+"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\
+"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\
+"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\
+"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\
+"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\
+"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\
+"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\
+"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\
+"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\
+"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\
+"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113");
+		}
+	}
+	}
+pin(A_MEN) {
+   direction          : input ;
+   capacitance        : 0.00300347 ;
+   max_transition     : "0.5952" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		        rise_power("scalar"){
+		 values (0.0092);
+		}
+		        fall_power("scalar"){
+		 values (0.0002);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\
+"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\
+"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\
+"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\
+"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\
+"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\
+"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\
+"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\
+"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\
+"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\
+"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\
+"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\
+"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\
+"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\
+"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\
+"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\
+"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\
+"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\
+"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\
+"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\
+"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\
+"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\
+"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\
+"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\
+"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918");
+		}
+	}
+	}
+bus(A_BM) {
+   bus_type : D_7_0;
+   direction          : input ;
+   capacitance        : 0.00263802 ;
+   max_transition     : "0.5952" ;
+   pin(A_BM[7:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0236);
+		}
+		        fall_power("scalar"){
+		 values (0.0075);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0230);
+		}
+		        fall_power("scalar"){
+		 values (0.0072);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "(A_WEN & A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.5355,-0.5160,-0.4896,-0.4476,-0.3665,-0.2220,-0.0013",\
+"-0.5435,-0.5240,-0.4976,-0.4556,-0.3746,-0.2300,-0.0093",\
+"-0.5525,-0.5330,-0.5066,-0.4646,-0.3836,-0.2390,-0.0183",\
+"-0.5657,-0.5461,-0.5198,-0.4778,-0.3967,-0.2522,-0.0315",\
+"-0.5899,-0.5704,-0.5440,-0.5021,-0.4210,-0.2765,-0.0558",\
+"-0.6205,-0.6009,-0.5746,-0.5326,-0.4515,-0.3070,-0.0863",\
+"-0.7019,-0.6824,-0.6560,-0.6140,-0.5330,-0.3884,-0.1677");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.4798,-0.4642,-0.4359,-0.3968,-0.3158,-0.1781,0.0339",\
+"-0.4878,-0.4722,-0.4439,-0.4048,-0.3238,-0.1861,0.0258",\
+"-0.4968,-0.4812,-0.4529,-0.4138,-0.3328,-0.1951,0.0168",\
+"-0.5100,-0.4944,-0.4661,-0.4270,-0.3459,-0.2082,0.0037",\
+"-0.5343,-0.5187,-0.4903,-0.4513,-0.3702,-0.2325,-0.0206",\
+"-0.5648,-0.5492,-0.5208,-0.4818,-0.4007,-0.2630,-0.0511",\
+"-0.6462,-0.6306,-0.6023,-0.5632,-0.4822,-0.3445,-0.1326");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "(A_WEN & A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.6521,0.6307,0.6043,0.5613,0.4822,0.3367,0.1111",\
+"0.6602,0.6387,0.6123,0.5693,0.4902,0.3447,0.1192",\
+"0.6692,0.6477,0.6213,0.5784,0.4993,0.3537,0.1282",\
+"0.6823,0.6608,0.6345,0.5915,0.5124,0.3669,0.1413",\
+"0.7066,0.6851,0.6588,0.6158,0.5367,0.3912,0.1656",\
+"0.7371,0.7156,0.6893,0.6463,0.5672,0.4217,0.1961",\
+"0.8186,0.7971,0.7707,0.7278,0.6487,0.5031,0.2776");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.5838,0.5672,0.5389,0.4949,0.4178,0.2801,0.0701",\
+"0.5918,0.5752,0.5469,0.5029,0.4258,0.2881,0.0781",\
+"0.6008,0.5842,0.5559,0.5120,0.4348,0.2971,0.0871",\
+"0.6140,0.5974,0.5690,0.5251,0.4480,0.3103,0.1003",\
+"0.6382,0.6216,0.5933,0.5494,0.4722,0.3345,0.1246",\
+"0.6688,0.6522,0.6238,0.5799,0.5028,0.3650,0.1551",\
+"0.7502,0.7336,0.7053,0.6613,0.5842,0.4465,0.2366");
+		}
+	}
+}
+   pin(A_CLK)  {
+	   direction       : input;
+	   capacitance     : 0.00378957;
+	   max_transition  : "0.5952";
+	   clock           : "true" ;
+	   pin_func_type   : active_rising ;
+
+	   timing () {
+		 timing_type : "min_pulse_width";
+		 related_pin : "A_CLK";
+		 rise_constraint("CLKTRAN_constraint_template") {
+		 index_1("0.008,0.5952");
+		 values("0.4,0.4");
+		 }
+	   }
+
+	   related_power_pin : VDD;
+	   related_ground_pin : VSS;
+
+	internal_power() {
+		when : "!A_MEN  & !A_WEN & !A_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN  & A_WEN  & !A_REN";
+		        rise_power("scalar"){
+		 values (0.5206);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & A_WEN  & !A_REN";
+		        rise_power("scalar"){
+		 values (15.8889);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & A_WEN  & A_REN";
+		        rise_power("scalar"){
+		 values (15.7957);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & !A_WEN & A_REN";
+		        rise_power("scalar"){
+		 values (12.1067);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN & !A_WEN & A_REN";
+		        rise_power("scalar"){
+		 values (0.3170);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN & A_WEN  & A_REN";
+		        rise_power("scalar"){
+		 values (0.5148);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & !A_WEN & !A_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	}
+   bus(A_DIN) {
+	   bus_type : D_7_0;
+	   direction       : input ;
+	   capacitance     : 0.00358485 ;
+	   memory_write() {
+		   address : A_ADDR ;
+		   clocked_on : A_CLK;
+	   }
+
+	   max_transition  : "0.5952" ;
+	   pin(A_DIN[7:0]) {
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0236);
+		}
+		        fall_power("scalar"){
+		 values (0.0075);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0230);
+		}
+		        fall_power("scalar"){
+		 values (0.0072);
+		}
+	}
+	   }
+	   timing() {
+		 timing_type     : setup_rising;
+		 related_pin     : "A_CLK";
+		 when            : "(A_WEN & A_MEN)";
+		 sdf_cond        : "A_W_ACCESS";
+
+	  rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 values ("-0.5355,-0.5160,-0.4896,-0.4476,-0.3665,-0.2220,-0.0013",\
+"-0.5435,-0.5240,-0.4976,-0.4556,-0.3746,-0.2300,-0.0093",\
+"-0.5525,-0.5330,-0.5066,-0.4646,-0.3836,-0.2390,-0.0183",\
+"-0.5657,-0.5461,-0.5198,-0.4778,-0.3967,-0.2522,-0.0315",\
+"-0.5899,-0.5704,-0.5440,-0.5021,-0.4210,-0.2765,-0.0558",\
+"-0.6205,-0.6009,-0.5746,-0.5326,-0.4515,-0.3070,-0.0863",\
+"-0.7019,-0.6824,-0.6560,-0.6140,-0.5330,-0.3884,-0.1677");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 values ("-0.4798,-0.4642,-0.4359,-0.3968,-0.3158,-0.1781,0.0339",\
+"-0.4878,-0.4722,-0.4439,-0.4048,-0.3238,-0.1861,0.0258",\
+"-0.4968,-0.4812,-0.4529,-0.4138,-0.3328,-0.1951,0.0168",\
+"-0.5100,-0.4944,-0.4661,-0.4270,-0.3459,-0.2082,0.0037",\
+"-0.5343,-0.5187,-0.4903,-0.4513,-0.3702,-0.2325,-0.0206",\
+"-0.5648,-0.5492,-0.5208,-0.4818,-0.4007,-0.2630,-0.0511",\
+"-0.6462,-0.6306,-0.6023,-0.5632,-0.4822,-0.3445,-0.1326");
+		 }
+	   }
+
+	   timing() {
+		 timing_type     : hold_rising;
+		 related_pin     : "A_CLK";
+		 when            : "(A_WEN & A_MEN)";
+		 sdf_cond        : "A_W_ACCESS";
+
+	   rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 values ("0.6521,0.6307,0.6043,0.5613,0.4822,0.3367,0.1111",\
+"0.6602,0.6387,0.6123,0.5693,0.4902,0.3447,0.1192",\
+"0.6692,0.6477,0.6213,0.5784,0.4993,0.3537,0.1282",\
+"0.6823,0.6608,0.6345,0.5915,0.5124,0.3669,0.1413",\
+"0.7066,0.6851,0.6588,0.6158,0.5367,0.3912,0.1656",\
+"0.7371,0.7156,0.6893,0.6463,0.5672,0.4217,0.1961",\
+"0.8186,0.7971,0.7707,0.7278,0.6487,0.5031,0.2776");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 values ("0.5838,0.5672,0.5389,0.4949,0.4178,0.2801,0.0701",\
+"0.5918,0.5752,0.5469,0.5029,0.4258,0.2881,0.0781",\
+"0.6008,0.5842,0.5559,0.5120,0.4348,0.2971,0.0871",\
+"0.6140,0.5974,0.5690,0.5251,0.4480,0.3103,0.1003",\
+"0.6382,0.6216,0.5933,0.5494,0.4722,0.3345,0.1246",\
+"0.6688,0.6522,0.6238,0.5799,0.5028,0.3650,0.1551",\
+"0.7502,0.7336,0.7053,0.6613,0.5842,0.4465,0.2366");
+		 }
+	   }
+   }
+
+   pin(A_BIST_EN) {
+	   direction       : input ;
+	   capacitance     : 0.00387999 ;
+	   max_transition  : "1" ;
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+		internal_power() {
+		  rise_power("scalar") {
+			 values (0);
+		  }
+		  fall_power("scalar") {
+			 values (0);
+		  }
+	   }
+   }
+
+bus(A_BIST_ADDR) {
+   bus_type : A_9_0;
+   direction          : input ;
+   capacitance        : 0.0077013 ;
+    pin(A_BIST_ADDR[0]) {
+       capacitance : 0.00625349 ;
+    }
+    pin(A_BIST_ADDR[1]) {
+       capacitance : 0.00507435 ;
+    }
+    pin(A_BIST_ADDR[2]) {
+       capacitance : 0.00656707 ;
+    }
+    pin(A_BIST_ADDR[3]) {
+       capacitance : 0.0083133 ;
+    }
+    pin(A_BIST_ADDR[4]) {
+       capacitance : 0.00507219 ;
+    }
+    pin(A_BIST_ADDR[5]) {
+       capacitance : 0.00964344 ;
+    }
+    pin(A_BIST_ADDR[6]) {
+       capacitance : 0.0119653 ;
+    }
+    pin(A_BIST_ADDR[7]) {
+       capacitance : 0.00827606 ;
+    }
+    pin(A_BIST_ADDR[8]) {
+       capacitance : 0.0110771 ;
+    }
+   max_transition     : "0.5952" ;
+   pin(A_BIST_ADDR[9:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0113);
+		}
+		        fall_power("scalar"){
+		 values (0.0087);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0152);
+		}
+		        fall_power("scalar"){
+		 values (0.0041);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\
+"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\
+"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\
+"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\
+"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\
+"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\
+"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\
+"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\
+"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\
+"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\
+"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\
+"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\
+"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3098",\
+"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\
+"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\
+"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\
+"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\
+"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\
+"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\
+"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\
+"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\
+"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\
+"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\
+"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\
+"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004");
+		}
+	}
+}
+pin(A_BIST_WEN) {
+   direction          : input ;
+   capacitance        : 0.00313551 ;
+   max_transition     : "0.5952" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0036);
+		}
+		        fall_power("scalar"){
+		 values (0.0007);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0050);
+		}
+		        fall_power("scalar"){
+		 values (0.0003);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\
+"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\
+"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\
+"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\
+"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\
+"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\
+"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\
+"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\
+"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\
+"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\
+"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\
+"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\
+"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\
+"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\
+"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\
+"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\
+"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\
+"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\
+"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\
+"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\
+"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\
+"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\
+"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\
+"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\
+"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879");
+		}
+	}
+	}
+pin(A_BIST_REN) {
+   direction          : input ;
+   capacitance        : 0.00381144 ;
+   max_transition     : "0.5952" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0041);
+		}
+		        fall_power("scalar"){
+		 values (0.0015);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0041);
+		}
+		        fall_power("scalar"){
+		 values (0.0013);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\
+"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\
+"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\
+"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\
+"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\
+"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\
+"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\
+"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\
+"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\
+"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\
+"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\
+"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\
+"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\
+"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\
+"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\
+"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\
+"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\
+"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\
+"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\
+"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\
+"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\
+"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\
+"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\
+"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\
+"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113");
+		}
+	}
+	}
+pin(A_BIST_MEN) {
+   direction          : input ;
+   capacitance        : 0.00300347 ;
+   max_transition     : "0.5952" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		        rise_power("scalar"){
+		 values (0.0092);
+		}
+		        fall_power("scalar"){
+		 values (0.0002);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\
+"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\
+"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\
+"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\
+"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\
+"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\
+"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\
+"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\
+"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\
+"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\
+"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\
+"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\
+"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\
+"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\
+"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\
+"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\
+"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\
+"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\
+"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\
+"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\
+"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\
+"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\
+"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\
+"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\
+"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918");
+		}
+	}
+	}
+bus(A_BIST_BM) {
+   bus_type : D_7_0;
+   direction          : input ;
+   capacitance        : 0.00225269 ;
+   max_transition     : "0.5952" ;
+   pin(A_BIST_BM[7:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0236);
+		}
+		        fall_power("scalar"){
+		 values (0.0075);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0230);
+		}
+		        fall_power("scalar"){
+		 values (0.0072);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "(A_BIST_WEN & A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.5355,-0.5160,-0.4896,-0.4476,-0.3665,-0.2220,-0.0013",\
+"-0.5435,-0.5240,-0.4976,-0.4556,-0.3746,-0.2300,-0.0093",\
+"-0.5525,-0.5330,-0.5066,-0.4646,-0.3836,-0.2390,-0.0183",\
+"-0.5657,-0.5461,-0.5198,-0.4778,-0.3967,-0.2522,-0.0315",\
+"-0.5899,-0.5704,-0.5440,-0.5021,-0.4210,-0.2765,-0.0558",\
+"-0.6205,-0.6009,-0.5746,-0.5326,-0.4515,-0.3070,-0.0863",\
+"-0.7019,-0.6824,-0.6560,-0.6140,-0.5330,-0.3884,-0.1677");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.4798,-0.4642,-0.4359,-0.3968,-0.3158,-0.1781,0.0339",\
+"-0.4878,-0.4722,-0.4439,-0.4048,-0.3238,-0.1861,0.0258",\
+"-0.4968,-0.4812,-0.4529,-0.4138,-0.3328,-0.1951,0.0168",\
+"-0.5100,-0.4944,-0.4661,-0.4270,-0.3459,-0.2082,0.0037",\
+"-0.5343,-0.5187,-0.4903,-0.4513,-0.3702,-0.2325,-0.0206",\
+"-0.5648,-0.5492,-0.5208,-0.4818,-0.4007,-0.2630,-0.0511",\
+"-0.6462,-0.6306,-0.6023,-0.5632,-0.4822,-0.3445,-0.1326");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "(A_BIST_WEN & A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.6521,0.6307,0.6043,0.5613,0.4822,0.3367,0.1111",\
+"0.6602,0.6387,0.6123,0.5693,0.4902,0.3447,0.1192",\
+"0.6692,0.6477,0.6213,0.5784,0.4993,0.3537,0.1282",\
+"0.6823,0.6608,0.6345,0.5915,0.5124,0.3669,0.1413",\
+"0.7066,0.6851,0.6588,0.6158,0.5367,0.3912,0.1656",\
+"0.7371,0.7156,0.6893,0.6463,0.5672,0.4217,0.1961",\
+"0.8186,0.7971,0.7707,0.7278,0.6487,0.5031,0.2776");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.5838,0.5672,0.5389,0.4949,0.4178,0.2801,0.0701",\
+"0.5918,0.5752,0.5469,0.5029,0.4258,0.2881,0.0781",\
+"0.6008,0.5842,0.5559,0.5120,0.4348,0.2971,0.0871",\
+"0.6140,0.5974,0.5690,0.5251,0.4480,0.3103,0.1003",\
+"0.6382,0.6216,0.5933,0.5494,0.4722,0.3345,0.1246",\
+"0.6688,0.6522,0.6238,0.5799,0.5028,0.3650,0.1551",\
+"0.7502,0.7336,0.7053,0.6613,0.5842,0.4465,0.2366");
+		}
+	}
+}
+   pin(A_BIST_CLK)  {
+	   direction       : input;
+	   capacitance     : 0.00378957;
+	   max_transition  : "0.5952";
+	   clock           : "true" ;
+	   pin_func_type   : active_rising ;
+
+	   timing () {
+		 timing_type : "min_pulse_width";
+		 related_pin : "A_BIST_CLK";
+		 rise_constraint("CLKTRAN_constraint_template") {
+		 index_1("0.008,0.5952");
+		 values("0.4,0.4");
+		 }
+	   }
+
+	   related_power_pin : VDD;
+	   related_ground_pin : VSS;
+
+	internal_power() {
+		when : "!A_BIST_MEN  & !A_BIST_WEN & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN  & A_BIST_WEN  & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0.5206);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & A_BIST_WEN  & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (15.8889);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & A_BIST_WEN  & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (15.7957);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & !A_BIST_WEN & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (12.1067);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0.3170);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN & A_BIST_WEN  & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0.5148);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & !A_BIST_WEN & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	}
+   bus(A_BIST_DIN) {
+	   bus_type : D_7_0;
+	   direction       : input ;
+	   capacitance     : 0.00226348 ;
+	   memory_write() {
+		   address : A_BIST_ADDR ;
+		   clocked_on : A_BIST_CLK;
+	   }
+
+	   max_transition  : "0.5952" ;
+	   pin(A_BIST_DIN[7:0]) {
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0236);
+		}
+		        fall_power("scalar"){
+		 values (0.0075);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0230);
+		}
+		        fall_power("scalar"){
+		 values (0.0072);
+		}
+	}
+	   }
+	   timing() {
+		 timing_type     : setup_rising;
+		 related_pin     : "A_BIST_CLK";
+		 when            : "(A_BIST_WEN & A_BIST_MEN)";
+		 sdf_cond        : "A_BIST_W_ACCESS";
+
+	  rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 values ("-0.5355,-0.5160,-0.4896,-0.4476,-0.3665,-0.2220,-0.0013",\
+"-0.5435,-0.5240,-0.4976,-0.4556,-0.3746,-0.2300,-0.0093",\
+"-0.5525,-0.5330,-0.5066,-0.4646,-0.3836,-0.2390,-0.0183",\
+"-0.5657,-0.5461,-0.5198,-0.4778,-0.3967,-0.2522,-0.0315",\
+"-0.5899,-0.5704,-0.5440,-0.5021,-0.4210,-0.2765,-0.0558",\
+"-0.6205,-0.6009,-0.5746,-0.5326,-0.4515,-0.3070,-0.0863",\
+"-0.7019,-0.6824,-0.6560,-0.6140,-0.5330,-0.3884,-0.1677");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 values ("-0.4798,-0.4642,-0.4359,-0.3968,-0.3158,-0.1781,0.0339",\
+"-0.4878,-0.4722,-0.4439,-0.4048,-0.3238,-0.1861,0.0258",\
+"-0.4968,-0.4812,-0.4529,-0.4138,-0.3328,-0.1951,0.0168",\
+"-0.5100,-0.4944,-0.4661,-0.4270,-0.3459,-0.2082,0.0037",\
+"-0.5343,-0.5187,-0.4903,-0.4513,-0.3702,-0.2325,-0.0206",\
+"-0.5648,-0.5492,-0.5208,-0.4818,-0.4007,-0.2630,-0.0511",\
+"-0.6462,-0.6306,-0.6023,-0.5632,-0.4822,-0.3445,-0.1326");
+		 }
+	   }
+
+	   timing() {
+		 timing_type     : hold_rising;
+		 related_pin     : "A_BIST_CLK";
+		 when            : "(A_BIST_WEN & A_BIST_MEN)";
+		 sdf_cond        : "A_BIST_W_ACCESS";
+
+	   rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 values ("0.6521,0.6307,0.6043,0.5613,0.4822,0.3367,0.1111",\
+"0.6602,0.6387,0.6123,0.5693,0.4902,0.3447,0.1192",\
+"0.6692,0.6477,0.6213,0.5784,0.4993,0.3537,0.1282",\
+"0.6823,0.6608,0.6345,0.5915,0.5124,0.3669,0.1413",\
+"0.7066,0.6851,0.6588,0.6158,0.5367,0.3912,0.1656",\
+"0.7371,0.7156,0.6893,0.6463,0.5672,0.4217,0.1961",\
+"0.8186,0.7971,0.7707,0.7278,0.6487,0.5031,0.2776");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 values ("0.5838,0.5672,0.5389,0.4949,0.4178,0.2801,0.0701",\
+"0.5918,0.5752,0.5469,0.5029,0.4258,0.2881,0.0781",\
+"0.6008,0.5842,0.5559,0.5120,0.4348,0.2971,0.0871",\
+"0.6140,0.5974,0.5690,0.5251,0.4480,0.3103,0.1003",\
+"0.6382,0.6216,0.5933,0.5494,0.4722,0.3345,0.1246",\
+"0.6688,0.6522,0.6238,0.5799,0.5028,0.3650,0.1551",\
+"0.7502,0.7336,0.7053,0.6613,0.5842,0.4465,0.2366");
+		 }
+	   }
+   }
+
+bus(A_DOUT) {
+
+	   bus_type : D_7_0;
+	   direction       : output ;
+	   capacitance     : 0 ;
+	   max_capacitance  : "6.4e-14" ;
+	   memory_read() {
+		  address : A_ADDR ;
+	   }
+	   pin(A_DOUT[7:0]) {
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+	   internal_power() {
+		  rise_power("scalar") {
+			 values (0);
+		  }
+		  fall_power("scalar") {
+			 values (0);
+		  }
+	   }
+	   }
+	   timing() {
+		 related_pin   : "A_CLK";
+		 timing_type   : rising_edge ;
+		 timing_sense  : non_unate ;
+
+	   cell_rise(SIG2SRAM_delay_template) {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("7.0497,7.0524,7.0646,7.0788,7.1314,7.1863",\
+"7.0651,7.0678,7.0800,7.0942,7.1468,7.2018",\
+"7.0715,7.0742,7.0863,7.1006,7.1531,7.2081",\
+"7.0921,7.0949,7.1070,7.1212,7.1738,7.2288",\
+"7.1096,7.1123,7.1245,7.1387,7.1913,7.2462",\
+"7.1454,7.1481,7.1602,7.1744,7.2270,7.2820",\
+"7.2157,7.2184,7.2306,7.2448,7.2974,7.3524");
+	   }
+	   cell_fall(SIG2SRAM_delay_template) {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("6.9395,6.9417,6.9515,6.9633,7.0068,7.0506",\
+"6.9549,6.9571,6.9669,6.9787,7.0223,7.0660",\
+"6.9613,6.9634,6.9732,6.9850,7.0286,7.0723",\
+"6.9820,6.9841,6.9939,7.0057,7.0493,7.0930",\
+"6.9994,7.0016,7.0113,7.0232,7.0667,7.1105",\
+"7.0352,7.0373,7.0471,7.0589,7.1025,7.1462",\
+"7.1055,7.1077,7.1175,7.1293,7.1729,7.2166");
+	   }
+
+	   rise_transition(SRAM_load_template) {
+		 index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("0.0560,0.0583,0.0696,0.0816,0.1519,0.2335");
+	   }
+	   fall_transition(SRAM_load_template) {
+		 index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("0.0428,0.0445,0.0538,0.0658,0.1181,0.1751");
+	   }
+	}
+}
+cell_leakage_power : 653.2941;
+}
+}
diff --git a/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_1024x8_c2_bm_bist_typ_1p20V_25C.lib b/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_1024x8_c2_bm_bist_typ_1p20V_25C.lib
new file mode 100644
index 00000000..2f551b9b
--- /dev/null
+++ b/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_1024x8_c2_bm_bist_typ_1p20V_25C.lib
@@ -0,0 +1,1525 @@
+/* ------------------------------------------------------*/
+/**/
+/*		Copyright 2024 IHP PDK Authors*/
+/**/
+/*		Licensed under the Apache License, Version 2.0 (the "License");*/
+/*		you may not use this file except in compliance with the License.*/
+/*		You may obtain a copy of the License at*/
+/*		*/
+/*		   https://www.apache.org/licenses/LICENSE-2.0*/
+/*		*/
+/*		Unless required by applicable law or agreed to in writing, software*/
+/*		distributed under the License is distributed on an "AS IS" BASIS,*/
+/*		WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/
+/*		See the License for the specific language governing permissions and*/
+/*		limitations under the License.*/
+/*		*/
+/*		Generated on Fri Jul 19 09:01:13 2024		*/
+/*				*/
+/* ------------------------------------------------------ */
+library(RM_IHPSG13_1P_1024x8_c2_bm_bist_typ_1p20V_25C) {	
+	technology (cmos) ;
+	delay_model : table_lookup ;
+	define ("add_pg_pin_to_lib",  "library",  "boolean");
+	add_pg_pin_to_lib : true;
+	voltage_map ( VDD, 1.20);
+	voltage_map ( VDDARRAY, 1.20);
+	voltage_map ( VSS, 0.000000 );
+	
+	date            : "Fri Jul 19 09:01:10 2024" ;
+	comment         : "IHP Microelectronics GmbH, 2024" ;
+	revision        : 1.0.0 ;
+	simulation      : true ;
+	nom_process     : 1 ;
+	nom_temperature : 25 ;
+	nom_voltage     : 1.20 ;
+	
+	operating_conditions("typ_1p20V_25C"){
+	    process     : 1 ;
+	    temperature : 25 ;
+	    voltage     : 1.20 ;
+	    tree_type   : "balanced_tree" ;
+	}
+	
+	default_operating_conditions  : typ_1p20V_25C ;
+	default_max_transition        : 1.0 ;
+	default_fanout_load           : 1.0 ;
+	default_inout_pin_cap         : 0.0 ;
+	default_input_pin_cap         : 0.0 ;
+	default_output_pin_cap        : 0.0 ;
+	default_cell_leakage_power    : 0.0 ;
+	default_leakage_power_density : 0.0 ;
+	 
+	slew_lower_threshold_pct_rise : 30 ;
+	slew_upper_threshold_pct_rise : 70 ;
+	input_threshold_pct_fall      : 50 ;
+	output_threshold_pct_fall     : 50 ;
+	input_threshold_pct_rise      : 50 ;
+	output_threshold_pct_rise     : 50 ;
+	slew_lower_threshold_pct_fall : 30 ;
+	slew_upper_threshold_pct_fall : 70 ;
+	slew_derate_from_library      : 0.5;
+	k_volt_cell_leakage_power     : 0.0 ;
+	k_temp_cell_leakage_power     : 0.0 ;
+	k_process_cell_leakage_power  : 0.0 ;
+	k_volt_internal_power         : 0.0 ;
+	k_temp_internal_power         : 0.0 ;
+	k_process_internal_power      : 0.0 ;
+	
+	capacitive_load_unit            (1,pf) ;
+	voltage_unit                  : "1V" ;
+	current_unit                  : "1uA" ;
+	time_unit                     : "1ns" ;
+	leakage_power_unit            : "1nW" ;
+	pulling_resistance_unit       : "1kohm";
+	/*
+	  ------------------------------------------------------------------------------------------
+	  implicit units overview:
+	    cell_area       unit      : "um"
+	    internal_power  unit      : "1e-12 * J/toggle = 1 * uW/MHz"
+	                                (capacitive_load_unit * voltage_unit^2) per toggle event
+	  ------------------------------------------------------------------------------------------
+	*/
+	library_features(report_delay_calculation);
+	define_cell_area (pad_drivers,pad_driver_sites) ;
+	
+	lu_table_template(CLKTRAN_constraint_template) {
+	     variable_1 : constrained_pin_transition;
+	     index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" );
+	}
+	lu_table_template(SRAM_load_template) {
+	     variable_1 : total_output_net_capacitance;
+	     index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" );
+	}
+	lu_table_template(SIG2SRAM_constraint_template) {
+	     variable_1 : related_pin_transition;
+	     variable_2 : constrained_pin_transition;
+	     index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" );
+	     index_2 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" );
+	}
+	
+	lu_table_template(SIG2SRAM_delay_template) {
+	     variable_1 : input_net_transition;
+	     variable_2 : total_output_net_capacitance;
+	     index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" );
+	     index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" );
+	} 
+
+	type (D_7_0) {
+		base_type : array;
+		data_type : bit;
+		bit_width : 8;
+		bit_from  : 7;
+		bit_to    : 0;
+		downto    : true;
+	 }
+
+	type (A_9_0) {
+		base_type : array;
+		data_type : bit;
+		bit_width : 10;
+		bit_from  : 9;
+		bit_to    : 0;
+		downto    : true;
+	 }
+
+cell(RM_IHPSG13_1P_1024x8_c2_bm_bist) {
+pg_pin (VDD) {
+  pg_type : primary_power;
+  voltage_name : VDD;
+}
+pg_pin (VDDARRAY) {
+  pg_type : primary_power;
+  voltage_name : VDDARRAY;
+}
+pg_pin (VSS) {
+  pg_type : primary_ground;
+  voltage_name : VSS;
+}
+
+memory() {
+ type : ram;
+ address_width : 10;
+ word_width : 8;
+}
+
+interface_timing : false;
+bus_naming_style    :   "%s[%d]" ;
+area        : 49419.2448 ;
+
+   pin(A_DLY) {
+	   direction       : input ;
+	   capacitance     : 0.00401111 ;
+	   max_transition  : "1" ;
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+		internal_power() {
+		  rise_power("scalar") {
+			 values (0);
+		  }
+		  fall_power("scalar") {
+			 values (0);
+		  }
+	   }
+   }
+
+bus(A_ADDR) {
+   bus_type : A_9_0;
+   direction          : input ;
+   capacitance        : 0.00721489 ;
+    pin(A_ADDR[0]) {
+       capacitance : 0.00593979 ;
+    }
+    pin(A_ADDR[1]) {
+       capacitance : 0.00483009 ;
+    }
+    pin(A_ADDR[2]) {
+       capacitance : 0.006215 ;
+    }
+    pin(A_ADDR[3]) {
+       capacitance : 0.00766726 ;
+    }
+    pin(A_ADDR[4]) {
+       capacitance : 0.00488951 ;
+    }
+    pin(A_ADDR[5]) {
+       capacitance : 0.0091523 ;
+    }
+    pin(A_ADDR[6]) {
+       capacitance : 0.0109212 ;
+    }
+    pin(A_ADDR[7]) {
+       capacitance : 0.00774122 ;
+    }
+    pin(A_ADDR[8]) {
+       capacitance : 0.0101403 ;
+    }
+   max_transition     : "0.476" ;
+   pin(A_ADDR[9:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0122);
+		}
+		        fall_power("scalar"){
+		 values (0.0064);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0205);
+		}
+		        fall_power("scalar"){
+		 values (0.0016);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "((A_WEN | A_REN)& A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\
+"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\
+"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\
+"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\
+"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\
+"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\
+"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\
+"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\
+"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\
+"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\
+"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\
+"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\
+"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "((A_WEN | A_REN)& A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\
+"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\
+"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\
+"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\
+"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\
+"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\
+"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\
+"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\
+"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\
+"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\
+"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\
+"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\
+"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387");
+		}
+	}
+}
+pin(A_WEN) {
+   direction          : input ;
+   capacitance        : 0.00324098 ;
+   max_transition     : "0.476" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0046);
+		}
+		        fall_power("scalar"){
+		 values (0.0038);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0042);
+		}
+		        fall_power("scalar"){
+		 values (0.0038);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\
+"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\
+"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\
+"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\
+"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\
+"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\
+"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\
+"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\
+"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\
+"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\
+"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\
+"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\
+"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\
+"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\
+"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\
+"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\
+"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\
+"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\
+"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\
+"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\
+"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\
+"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\
+"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\
+"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\
+"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512");
+		}
+	}
+	}
+pin(A_REN) {
+   direction          : input ;
+   capacitance        : 0.00381634 ;
+   max_transition     : "0.476" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0061);
+		}
+		        fall_power("scalar"){
+		 values (0.0020);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0062);
+		}
+		        fall_power("scalar"){
+		 values (0.0024);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\
+"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\
+"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\
+"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\
+"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\
+"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\
+"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\
+"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\
+"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\
+"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\
+"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\
+"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\
+"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\
+"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\
+"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\
+"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\
+"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\
+"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\
+"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\
+"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\
+"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\
+"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\
+"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\
+"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\
+"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707");
+		}
+	}
+	}
+pin(A_MEN) {
+   direction          : input ;
+   capacitance        : 0.00309605 ;
+   max_transition     : "0.476" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		        rise_power("scalar"){
+		 values (0.0236);
+		}
+		        fall_power("scalar"){
+		 values (0.0052);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\
+"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\
+"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\
+"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\
+"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\
+"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\
+"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\
+"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\
+"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\
+"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\
+"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\
+"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\
+"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\
+"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\
+"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\
+"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\
+"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\
+"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\
+"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\
+"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\
+"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\
+"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\
+"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\
+"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\
+"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512");
+		}
+	}
+	}
+bus(A_BM) {
+   bus_type : D_7_0;
+   direction          : input ;
+   capacitance        : 0.00285703 ;
+   max_transition     : "0.476" ;
+   pin(A_BM[7:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0299);
+		}
+		        fall_power("scalar"){
+		 values (0.0123);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0317);
+		}
+		        fall_power("scalar"){
+		 values (0.0122);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "(A_WEN & A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.2903,-0.2736,-0.2610,-0.2287,-0.1819,-0.0774,0.1150",\
+"-0.2953,-0.2787,-0.2660,-0.2337,-0.1869,-0.0824,0.1100",\
+"-0.2997,-0.2831,-0.2704,-0.2382,-0.1913,-0.0868,0.1056",\
+"-0.3095,-0.2929,-0.2802,-0.2480,-0.2011,-0.0966,0.0957",\
+"-0.3159,-0.2993,-0.2866,-0.2544,-0.2075,-0.1030,0.0894",\
+"-0.3524,-0.3358,-0.3231,-0.2909,-0.2440,-0.1395,0.0529",\
+"-0.4032,-0.3866,-0.3739,-0.3417,-0.2949,-0.1904,0.0020");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.2580,-0.2424,-0.2297,-0.2014,-0.1506,-0.0520,0.1267",\
+"-0.2630,-0.2474,-0.2347,-0.2064,-0.1556,-0.0570,0.1217",\
+"-0.2675,-0.2518,-0.2391,-0.2108,-0.1600,-0.0614,0.1173",\
+"-0.2773,-0.2617,-0.2490,-0.2207,-0.1699,-0.0713,0.1074",\
+"-0.2837,-0.2680,-0.2553,-0.2270,-0.1762,-0.0776,0.1011",\
+"-0.3201,-0.3045,-0.2918,-0.2635,-0.2127,-0.1141,0.0646",\
+"-0.3710,-0.3554,-0.3427,-0.3144,-0.2636,-0.1650,0.0137");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "(A_WEN & A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.3991,0.3835,0.3708,0.3385,0.2897,0.1911,-0.0052",\
+"0.4041,0.3885,0.3758,0.3435,0.2947,0.1961,-0.0002",\
+"0.4085,0.3929,0.3802,0.3480,0.2992,0.2005,0.0042",\
+"0.4184,0.4027,0.3901,0.3578,0.3090,0.2104,0.0141",\
+"0.4247,0.4091,0.3964,0.3642,0.3153,0.2167,0.0204",\
+"0.4612,0.4456,0.4329,0.4007,0.3518,0.2532,0.0569",\
+"0.5121,0.4965,0.4838,0.4515,0.4027,0.3041,0.1078");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.3590,0.3444,0.3307,0.3024,0.2516,0.1588,-0.0296",\
+"0.3641,0.3494,0.3357,0.3074,0.2566,0.1639,-0.0246",\
+"0.3685,0.3538,0.3402,0.3118,0.2611,0.1683,-0.0202",\
+"0.3783,0.3637,0.3500,0.3217,0.2709,0.1781,-0.0103",\
+"0.3847,0.3700,0.3564,0.3280,0.2773,0.1845,-0.0040",\
+"0.4212,0.4065,0.3928,0.3645,0.3137,0.2210,0.0325",\
+"0.4720,0.4574,0.4437,0.4154,0.3646,0.2718,0.0834");
+		}
+	}
+}
+   pin(A_CLK)  {
+	   direction       : input;
+	   capacitance     : 0.00380014;
+	   max_transition  : "0.476";
+	   clock           : "true" ;
+	   pin_func_type   : active_rising ;
+
+	   timing () {
+		 timing_type : "min_pulse_width";
+		 related_pin : "A_CLK";
+		 rise_constraint("CLKTRAN_constraint_template") {
+		 index_1("0.0056,0.476");
+		 values("0.21,0.21");
+		 }
+	   }
+
+	   related_power_pin : VDD;
+	   related_ground_pin : VSS;
+
+	internal_power() {
+		when : "!A_MEN  & !A_WEN & !A_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN  & A_WEN  & !A_REN";
+		        rise_power("scalar"){
+		 values (0.5550);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & A_WEN  & !A_REN";
+		        rise_power("scalar"){
+		 values (19.9179);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & A_WEN  & A_REN";
+		        rise_power("scalar"){
+		 values (19.7017);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & !A_WEN & A_REN";
+		        rise_power("scalar"){
+		 values (15.5961);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN & !A_WEN & A_REN";
+		        rise_power("scalar"){
+		 values (0.3069);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN & A_WEN  & A_REN";
+		        rise_power("scalar"){
+		 values (0.5410);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & !A_WEN & !A_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	}
+   bus(A_DIN) {
+	   bus_type : D_7_0;
+	   direction       : input ;
+	   capacitance     : 0.00365723 ;
+	   memory_write() {
+		   address : A_ADDR ;
+		   clocked_on : A_CLK;
+	   }
+
+	   max_transition  : "0.476" ;
+	   pin(A_DIN[7:0]) {
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0299);
+		}
+		        fall_power("scalar"){
+		 values (0.0123);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0317);
+		}
+		        fall_power("scalar"){
+		 values (0.0122);
+		}
+	}
+	   }
+	   timing() {
+		 timing_type     : setup_rising;
+		 related_pin     : "A_CLK";
+		 when            : "(A_WEN & A_MEN)";
+		 sdf_cond        : "A_W_ACCESS";
+
+	  rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 values ("-0.2903,-0.2736,-0.2610,-0.2287,-0.1819,-0.0774,0.1150",\
+"-0.2953,-0.2787,-0.2660,-0.2337,-0.1869,-0.0824,0.1100",\
+"-0.2997,-0.2831,-0.2704,-0.2382,-0.1913,-0.0868,0.1056",\
+"-0.3095,-0.2929,-0.2802,-0.2480,-0.2011,-0.0966,0.0957",\
+"-0.3159,-0.2993,-0.2866,-0.2544,-0.2075,-0.1030,0.0894",\
+"-0.3524,-0.3358,-0.3231,-0.2909,-0.2440,-0.1395,0.0529",\
+"-0.4032,-0.3866,-0.3739,-0.3417,-0.2949,-0.1904,0.0020");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 values ("-0.2580,-0.2424,-0.2297,-0.2014,-0.1506,-0.0520,0.1267",\
+"-0.2630,-0.2474,-0.2347,-0.2064,-0.1556,-0.0570,0.1217",\
+"-0.2675,-0.2518,-0.2391,-0.2108,-0.1600,-0.0614,0.1173",\
+"-0.2773,-0.2617,-0.2490,-0.2207,-0.1699,-0.0713,0.1074",\
+"-0.2837,-0.2680,-0.2553,-0.2270,-0.1762,-0.0776,0.1011",\
+"-0.3201,-0.3045,-0.2918,-0.2635,-0.2127,-0.1141,0.0646",\
+"-0.3710,-0.3554,-0.3427,-0.3144,-0.2636,-0.1650,0.0137");
+		 }
+	   }
+
+	   timing() {
+		 timing_type     : hold_rising;
+		 related_pin     : "A_CLK";
+		 when            : "(A_WEN & A_MEN)";
+		 sdf_cond        : "A_W_ACCESS";
+
+	   rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 values ("0.3991,0.3835,0.3708,0.3385,0.2897,0.1911,-0.0052",\
+"0.4041,0.3885,0.3758,0.3435,0.2947,0.1961,-0.0002",\
+"0.4085,0.3929,0.3802,0.3480,0.2992,0.2005,0.0042",\
+"0.4184,0.4027,0.3901,0.3578,0.3090,0.2104,0.0141",\
+"0.4247,0.4091,0.3964,0.3642,0.3153,0.2167,0.0204",\
+"0.4612,0.4456,0.4329,0.4007,0.3518,0.2532,0.0569",\
+"0.5121,0.4965,0.4838,0.4515,0.4027,0.3041,0.1078");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 values ("0.3590,0.3444,0.3307,0.3024,0.2516,0.1588,-0.0296",\
+"0.3641,0.3494,0.3357,0.3074,0.2566,0.1639,-0.0246",\
+"0.3685,0.3538,0.3402,0.3118,0.2611,0.1683,-0.0202",\
+"0.3783,0.3637,0.3500,0.3217,0.2709,0.1781,-0.0103",\
+"0.3847,0.3700,0.3564,0.3280,0.2773,0.1845,-0.0040",\
+"0.4212,0.4065,0.3928,0.3645,0.3137,0.2210,0.0325",\
+"0.4720,0.4574,0.4437,0.4154,0.3646,0.2718,0.0834");
+		 }
+	   }
+   }
+
+   pin(A_BIST_EN) {
+	   direction       : input ;
+	   capacitance     : 0.00401111 ;
+	   max_transition  : "1" ;
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+		internal_power() {
+		  rise_power("scalar") {
+			 values (0);
+		  }
+		  fall_power("scalar") {
+			 values (0);
+		  }
+	   }
+   }
+
+bus(A_BIST_ADDR) {
+   bus_type : A_9_0;
+   direction          : input ;
+   capacitance        : 0.00721489 ;
+    pin(A_BIST_ADDR[0]) {
+       capacitance : 0.00593979 ;
+    }
+    pin(A_BIST_ADDR[1]) {
+       capacitance : 0.00483009 ;
+    }
+    pin(A_BIST_ADDR[2]) {
+       capacitance : 0.006215 ;
+    }
+    pin(A_BIST_ADDR[3]) {
+       capacitance : 0.00766726 ;
+    }
+    pin(A_BIST_ADDR[4]) {
+       capacitance : 0.00488951 ;
+    }
+    pin(A_BIST_ADDR[5]) {
+       capacitance : 0.0091523 ;
+    }
+    pin(A_BIST_ADDR[6]) {
+       capacitance : 0.0109212 ;
+    }
+    pin(A_BIST_ADDR[7]) {
+       capacitance : 0.00774122 ;
+    }
+    pin(A_BIST_ADDR[8]) {
+       capacitance : 0.0101403 ;
+    }
+   max_transition     : "0.476" ;
+   pin(A_BIST_ADDR[9:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0122);
+		}
+		        fall_power("scalar"){
+		 values (0.0064);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0205);
+		}
+		        fall_power("scalar"){
+		 values (0.0016);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\
+"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\
+"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\
+"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\
+"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\
+"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\
+"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\
+"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\
+"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\
+"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\
+"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\
+"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\
+"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\
+"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\
+"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\
+"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\
+"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\
+"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\
+"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\
+"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\
+"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\
+"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\
+"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\
+"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\
+"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387");
+		}
+	}
+}
+pin(A_BIST_WEN) {
+   direction          : input ;
+   capacitance        : 0.00324098 ;
+   max_transition     : "0.476" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0046);
+		}
+		        fall_power("scalar"){
+		 values (0.0038);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0042);
+		}
+		        fall_power("scalar"){
+		 values (0.0038);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\
+"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\
+"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\
+"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\
+"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\
+"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\
+"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\
+"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\
+"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\
+"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\
+"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\
+"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\
+"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\
+"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\
+"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\
+"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\
+"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\
+"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\
+"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\
+"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\
+"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\
+"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\
+"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\
+"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\
+"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512");
+		}
+	}
+	}
+pin(A_BIST_REN) {
+   direction          : input ;
+   capacitance        : 0.00381634 ;
+   max_transition     : "0.476" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0061);
+		}
+		        fall_power("scalar"){
+		 values (0.0020);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0062);
+		}
+		        fall_power("scalar"){
+		 values (0.0024);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\
+"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\
+"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\
+"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\
+"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\
+"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\
+"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\
+"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\
+"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\
+"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\
+"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\
+"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\
+"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\
+"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\
+"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\
+"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\
+"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\
+"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\
+"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\
+"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\
+"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\
+"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\
+"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\
+"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\
+"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707");
+		}
+	}
+	}
+pin(A_BIST_MEN) {
+   direction          : input ;
+   capacitance        : 0.00309605 ;
+   max_transition     : "0.476" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		        rise_power("scalar"){
+		 values (0.0236);
+		}
+		        fall_power("scalar"){
+		 values (0.0052);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\
+"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\
+"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\
+"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\
+"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\
+"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\
+"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\
+"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\
+"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\
+"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\
+"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\
+"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\
+"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\
+"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\
+"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\
+"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\
+"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\
+"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\
+"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\
+"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\
+"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\
+"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\
+"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\
+"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\
+"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512");
+		}
+	}
+	}
+bus(A_BIST_BM) {
+   bus_type : D_7_0;
+   direction          : input ;
+   capacitance        : 0.00238379 ;
+   max_transition     : "0.476" ;
+   pin(A_BIST_BM[7:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0299);
+		}
+		        fall_power("scalar"){
+		 values (0.0123);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0317);
+		}
+		        fall_power("scalar"){
+		 values (0.0122);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "(A_BIST_WEN & A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.2903,-0.2736,-0.2610,-0.2287,-0.1819,-0.0774,0.1150",\
+"-0.2953,-0.2787,-0.2660,-0.2337,-0.1869,-0.0824,0.1100",\
+"-0.2997,-0.2831,-0.2704,-0.2382,-0.1913,-0.0868,0.1056",\
+"-0.3095,-0.2929,-0.2802,-0.2480,-0.2011,-0.0966,0.0957",\
+"-0.3159,-0.2993,-0.2866,-0.2544,-0.2075,-0.1030,0.0894",\
+"-0.3524,-0.3358,-0.3231,-0.2909,-0.2440,-0.1395,0.0529",\
+"-0.4032,-0.3866,-0.3739,-0.3417,-0.2949,-0.1904,0.0020");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.2580,-0.2424,-0.2297,-0.2014,-0.1506,-0.0520,0.1267",\
+"-0.2630,-0.2474,-0.2347,-0.2064,-0.1556,-0.0570,0.1217",\
+"-0.2675,-0.2518,-0.2391,-0.2108,-0.1600,-0.0614,0.1173",\
+"-0.2773,-0.2617,-0.2490,-0.2207,-0.1699,-0.0713,0.1074",\
+"-0.2837,-0.2680,-0.2553,-0.2270,-0.1762,-0.0776,0.1011",\
+"-0.3201,-0.3045,-0.2918,-0.2635,-0.2127,-0.1141,0.0646",\
+"-0.3710,-0.3554,-0.3427,-0.3144,-0.2636,-0.1650,0.0137");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "(A_BIST_WEN & A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.3991,0.3835,0.3708,0.3385,0.2897,0.1911,-0.0052",\
+"0.4041,0.3885,0.3758,0.3435,0.2947,0.1961,-0.0002",\
+"0.4085,0.3929,0.3802,0.3480,0.2992,0.2005,0.0042",\
+"0.4184,0.4027,0.3901,0.3578,0.3090,0.2104,0.0141",\
+"0.4247,0.4091,0.3964,0.3642,0.3153,0.2167,0.0204",\
+"0.4612,0.4456,0.4329,0.4007,0.3518,0.2532,0.0569",\
+"0.5121,0.4965,0.4838,0.4515,0.4027,0.3041,0.1078");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.3590,0.3444,0.3307,0.3024,0.2516,0.1588,-0.0296",\
+"0.3641,0.3494,0.3357,0.3074,0.2566,0.1639,-0.0246",\
+"0.3685,0.3538,0.3402,0.3118,0.2611,0.1683,-0.0202",\
+"0.3783,0.3637,0.3500,0.3217,0.2709,0.1781,-0.0103",\
+"0.3847,0.3700,0.3564,0.3280,0.2773,0.1845,-0.0040",\
+"0.4212,0.4065,0.3928,0.3645,0.3137,0.2210,0.0325",\
+"0.4720,0.4574,0.4437,0.4154,0.3646,0.2718,0.0834");
+		}
+	}
+}
+   pin(A_BIST_CLK)  {
+	   direction       : input;
+	   capacitance     : 0.00380014;
+	   max_transition  : "0.476";
+	   clock           : "true" ;
+	   pin_func_type   : active_rising ;
+
+	   timing () {
+		 timing_type : "min_pulse_width";
+		 related_pin : "A_BIST_CLK";
+		 rise_constraint("CLKTRAN_constraint_template") {
+		 index_1("0.0056,0.476");
+		 values("0.21,0.21");
+		 }
+	   }
+
+	   related_power_pin : VDD;
+	   related_ground_pin : VSS;
+
+	internal_power() {
+		when : "!A_BIST_MEN  & !A_BIST_WEN & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN  & A_BIST_WEN  & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0.5550);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & A_BIST_WEN  & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (19.9179);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & A_BIST_WEN  & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (19.7017);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & !A_BIST_WEN & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (15.5961);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0.3069);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN & A_BIST_WEN  & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0.5410);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & !A_BIST_WEN & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	}
+   bus(A_BIST_DIN) {
+	   bus_type : D_7_0;
+	   direction       : input ;
+	   capacitance     : 0.00233858 ;
+	   memory_write() {
+		   address : A_BIST_ADDR ;
+		   clocked_on : A_BIST_CLK;
+	   }
+
+	   max_transition  : "0.476" ;
+	   pin(A_BIST_DIN[7:0]) {
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0299);
+		}
+		        fall_power("scalar"){
+		 values (0.0123);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0317);
+		}
+		        fall_power("scalar"){
+		 values (0.0122);
+		}
+	}
+	   }
+	   timing() {
+		 timing_type     : setup_rising;
+		 related_pin     : "A_BIST_CLK";
+		 when            : "(A_BIST_WEN & A_BIST_MEN)";
+		 sdf_cond        : "A_BIST_W_ACCESS";
+
+	  rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 values ("-0.2903,-0.2736,-0.2610,-0.2287,-0.1819,-0.0774,0.1150",\
+"-0.2953,-0.2787,-0.2660,-0.2337,-0.1869,-0.0824,0.1100",\
+"-0.2997,-0.2831,-0.2704,-0.2382,-0.1913,-0.0868,0.1056",\
+"-0.3095,-0.2929,-0.2802,-0.2480,-0.2011,-0.0966,0.0957",\
+"-0.3159,-0.2993,-0.2866,-0.2544,-0.2075,-0.1030,0.0894",\
+"-0.3524,-0.3358,-0.3231,-0.2909,-0.2440,-0.1395,0.0529",\
+"-0.4032,-0.3866,-0.3739,-0.3417,-0.2949,-0.1904,0.0020");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 values ("-0.2580,-0.2424,-0.2297,-0.2014,-0.1506,-0.0520,0.1267",\
+"-0.2630,-0.2474,-0.2347,-0.2064,-0.1556,-0.0570,0.1217",\
+"-0.2675,-0.2518,-0.2391,-0.2108,-0.1600,-0.0614,0.1173",\
+"-0.2773,-0.2617,-0.2490,-0.2207,-0.1699,-0.0713,0.1074",\
+"-0.2837,-0.2680,-0.2553,-0.2270,-0.1762,-0.0776,0.1011",\
+"-0.3201,-0.3045,-0.2918,-0.2635,-0.2127,-0.1141,0.0646",\
+"-0.3710,-0.3554,-0.3427,-0.3144,-0.2636,-0.1650,0.0137");
+		 }
+	   }
+
+	   timing() {
+		 timing_type     : hold_rising;
+		 related_pin     : "A_BIST_CLK";
+		 when            : "(A_BIST_WEN & A_BIST_MEN)";
+		 sdf_cond        : "A_BIST_W_ACCESS";
+
+	   rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 values ("0.3991,0.3835,0.3708,0.3385,0.2897,0.1911,-0.0052",\
+"0.4041,0.3885,0.3758,0.3435,0.2947,0.1961,-0.0002",\
+"0.4085,0.3929,0.3802,0.3480,0.2992,0.2005,0.0042",\
+"0.4184,0.4027,0.3901,0.3578,0.3090,0.2104,0.0141",\
+"0.4247,0.4091,0.3964,0.3642,0.3153,0.2167,0.0204",\
+"0.4612,0.4456,0.4329,0.4007,0.3518,0.2532,0.0569",\
+"0.5121,0.4965,0.4838,0.4515,0.4027,0.3041,0.1078");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 values ("0.3590,0.3444,0.3307,0.3024,0.2516,0.1588,-0.0296",\
+"0.3641,0.3494,0.3357,0.3074,0.2566,0.1639,-0.0246",\
+"0.3685,0.3538,0.3402,0.3118,0.2611,0.1683,-0.0202",\
+"0.3783,0.3637,0.3500,0.3217,0.2709,0.1781,-0.0103",\
+"0.3847,0.3700,0.3564,0.3280,0.2773,0.1845,-0.0040",\
+"0.4212,0.4065,0.3928,0.3645,0.3137,0.2210,0.0325",\
+"0.4720,0.4574,0.4437,0.4154,0.3646,0.2718,0.0834");
+		 }
+	   }
+   }
+
+bus(A_DOUT) {
+
+	   bus_type : D_7_0;
+	   direction       : output ;
+	   capacitance     : 0 ;
+	   max_capacitance  : "6.4e-14" ;
+	   memory_read() {
+		  address : A_ADDR ;
+	   }
+	   pin(A_DOUT[7:0]) {
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+	   internal_power() {
+		  rise_power("scalar") {
+			 values (0);
+		  }
+		  fall_power("scalar") {
+			 values (0);
+		  }
+	   }
+	   }
+	   timing() {
+		 related_pin   : "A_CLK";
+		 timing_type   : rising_edge ;
+		 timing_sense  : non_unate ;
+
+	   cell_rise(SIG2SRAM_delay_template) {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("4.2177,4.2193,4.2270,4.2357,4.2681,4.3040",\
+"4.2278,4.2294,4.2371,4.2458,4.2782,4.3141",\
+"4.2324,4.2340,4.2417,4.2504,4.2828,4.3187",\
+"4.2402,4.2418,4.2495,4.2582,4.2906,4.3265",\
+"4.2478,4.2494,4.2570,4.2657,4.2982,4.3340",\
+"4.2828,4.2844,4.2921,4.3008,4.3332,4.3691",\
+"4.3362,4.3378,4.3455,4.3542,4.3866,4.4225");
+	   }
+	   cell_fall(SIG2SRAM_delay_template) {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("4.1566,4.1579,4.1639,4.1711,4.1976,4.2242",\
+"4.1667,4.1681,4.1741,4.1812,4.2077,4.2343",\
+"4.1714,4.1727,4.1787,4.1858,4.2123,4.2390",\
+"4.1792,4.1805,4.1865,4.1936,4.2201,4.2468",\
+"4.1867,4.1880,4.1940,4.2012,4.2277,4.2543",\
+"4.2218,4.2231,4.2291,4.2362,4.2627,4.2894",\
+"4.2751,4.2764,4.2824,4.2896,4.3161,4.3427");
+	   }
+
+	   rise_transition(SRAM_load_template) {
+		 index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("0.0326,0.0341,0.0428,0.0518,0.0923,0.1492");
+	   }
+	   fall_transition(SRAM_load_template) {
+		 index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("0.0254,0.0265,0.0335,0.0402,0.0707,0.1039");
+	   }
+	}
+}
+cell_leakage_power : 99.0077;
+}
+}
diff --git a/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_4096x16_c3_bm_bist_fast_1p32V_m55C.lib b/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_4096x16_c3_bm_bist_fast_1p32V_m55C.lib
new file mode 100644
index 00000000..aafc0b32
--- /dev/null
+++ b/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_4096x16_c3_bm_bist_fast_1p32V_m55C.lib
@@ -0,0 +1,1537 @@
+/* ------------------------------------------------------*/
+/**/
+/*		Copyright 2024 IHP PDK Authors*/
+/**/
+/*		Licensed under the Apache License, Version 2.0 (the "License");*/
+/*		you may not use this file except in compliance with the License.*/
+/*		You may obtain a copy of the License at*/
+/*		*/
+/*		   https://www.apache.org/licenses/LICENSE-2.0*/
+/*		*/
+/*		Unless required by applicable law or agreed to in writing, software*/
+/*		distributed under the License is distributed on an "AS IS" BASIS,*/
+/*		WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/
+/*		See the License for the specific language governing permissions and*/
+/*		limitations under the License.*/
+/*		*/
+/*		Generated on Fri Jul 12 17:37:33 2024		*/
+/*				*/
+/* ------------------------------------------------------ */
+library(RM_IHPSG13_1P_4096x16_c3_bm_bist_fast_1p32V_m55C) {	
+	technology (cmos) ;
+	delay_model : table_lookup ;
+	define ("add_pg_pin_to_lib",  "library",  "boolean");
+	add_pg_pin_to_lib : true;
+	voltage_map ( VDD, 1.32);
+	voltage_map ( VDDARRAY, 1.32);
+	voltage_map ( VSS, 0.000000 );
+	
+	date            : "Fri Jul 12 17:37:29 2024" ;
+	comment         : "IHP Microelectronics GmbH, 2024" ;
+	revision        : 1.0.0 ;
+	simulation      : true ;
+	nom_process     : 1 ;
+	nom_temperature : -55 ;
+	nom_voltage     : 1.32 ;
+	
+	operating_conditions("fast_1p32V_m55C"){
+	    process     : 1 ;
+	    temperature : -55 ;
+	    voltage     : 1.32 ;
+	    tree_type   : "balanced_tree" ;
+	}
+	
+	default_operating_conditions  : fast_1p32V_m55C ;
+	default_max_transition        : 1.0 ;
+	default_fanout_load           : 1.0 ;
+	default_inout_pin_cap         : 0.0 ;
+	default_input_pin_cap         : 0.0 ;
+	default_output_pin_cap        : 0.0 ;
+	default_cell_leakage_power    : 0.0 ;
+	default_leakage_power_density : 0.0 ;
+	 
+	slew_lower_threshold_pct_rise : 30 ;
+	slew_upper_threshold_pct_rise : 70 ;
+	input_threshold_pct_fall      : 50 ;
+	output_threshold_pct_fall     : 50 ;
+	input_threshold_pct_rise      : 50 ;
+	output_threshold_pct_rise     : 50 ;
+	slew_lower_threshold_pct_fall : 30 ;
+	slew_upper_threshold_pct_fall : 70 ;
+	slew_derate_from_library      : 0.5;
+	k_volt_cell_leakage_power     : 0.0 ;
+	k_temp_cell_leakage_power     : 0.0 ;
+	k_process_cell_leakage_power  : 0.0 ;
+	k_volt_internal_power         : 0.0 ;
+	k_temp_internal_power         : 0.0 ;
+	k_process_internal_power      : 0.0 ;
+	
+	capacitive_load_unit            (1,pf) ;
+	voltage_unit                  : "1V" ;
+	current_unit                  : "1uA" ;
+	time_unit                     : "1ns" ;
+	leakage_power_unit            : "1nW" ;
+	pulling_resistance_unit       : "1kohm";
+	/*
+	  ------------------------------------------------------------------------------------------
+	  implicit units overview:
+	    cell_area       unit      : "um"
+	    internal_power  unit      : "1e-12 * J/toggle = 1 * uW/MHz"
+	                                (capacitive_load_unit * voltage_unit^2) per toggle event
+	  ------------------------------------------------------------------------------------------
+	*/
+	library_features(report_delay_calculation);
+	define_cell_area (pad_drivers,pad_driver_sites) ;
+	
+	lu_table_template(CLKTRAN_constraint_template) {
+	     variable_1 : constrained_pin_transition;
+	     index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" );
+	}
+	lu_table_template(SRAM_load_template) {
+	     variable_1 : total_output_net_capacitance;
+	     index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" );
+	}
+	lu_table_template(SIG2SRAM_constraint_template) {
+	     variable_1 : related_pin_transition;
+	     variable_2 : constrained_pin_transition;
+	     index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" );
+	     index_2 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" );
+	}
+	
+	lu_table_template(SIG2SRAM_delay_template) {
+	     variable_1 : input_net_transition;
+	     variable_2 : total_output_net_capacitance;
+	     index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" );
+	     index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" );
+	} 
+
+	type (D_15_0) {
+		base_type : array;
+		data_type : bit;
+		bit_width : 16;
+		bit_from  : 15;
+		bit_to    : 0;
+		downto    : true;
+	 }
+
+	type (A_11_0) {
+		base_type : array;
+		data_type : bit;
+		bit_width : 12;
+		bit_from  : 11;
+		bit_to    : 0;
+		downto    : true;
+	 }
+
+cell(RM_IHPSG13_1P_4096x16_c3_bm_bist) {
+pg_pin (VDD) {
+  pg_type : primary_power;
+  voltage_name : VDD;
+}
+pg_pin (VDDARRAY) {
+  pg_type : primary_power;
+  voltage_name : VDDARRAY;
+}
+pg_pin (VSS) {
+  pg_type : primary_ground;
+  voltage_name : VSS;
+}
+
+memory() {
+ type : ram;
+ address_width : 12;
+ word_width : 16;
+}
+
+interface_timing : false;
+bus_naming_style    :   "%s[%d]" ;
+area        : 257608.512 ;
+
+   pin(A_DLY) {
+	   direction       : input ;
+	   capacitance     : 0.00421562 ;
+	   max_transition  : "1" ;
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+		internal_power() {
+		  rise_power("scalar") {
+			 values (0);
+		  }
+		  fall_power("scalar") {
+			 values (0);
+		  }
+	   }
+   }
+
+bus(A_ADDR) {
+   bus_type : A_11_0;
+   direction          : input ;
+   capacitance        : 0.00691085 ;
+    pin(A_ADDR[0]) {
+       capacitance : 0.00562034 ;
+    }
+    pin(A_ADDR[1]) {
+       capacitance : 0.00462655 ;
+    }
+    pin(A_ADDR[2]) {
+       capacitance : 0.00594295 ;
+    }
+    pin(A_ADDR[3]) {
+       capacitance : 0.00723434 ;
+    }
+    pin(A_ADDR[4]) {
+       capacitance : 0.00481603 ;
+    }
+    pin(A_ADDR[5]) {
+       capacitance : 0.00868123 ;
+    }
+    pin(A_ADDR[6]) {
+       capacitance : 0.010187 ;
+    }
+    pin(A_ADDR[7]) {
+       capacitance : 0.00734489 ;
+    }
+    pin(A_ADDR[8]) {
+       capacitance : 0.00904175 ;
+    }
+    pin(A_ADDR[9]) {
+       capacitance : 0.0074973 ;
+    }
+    pin(A_ADDR[10]) {
+       capacitance : 0.00825659 ;
+    }
+   max_transition     : "0.38" ;
+   pin(A_ADDR[11:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0094);
+		}
+		        fall_power("scalar"){
+		 values (0.0008);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0200);
+		}
+		        fall_power("scalar"){
+		 values (0.0016);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "((A_WEN | A_REN)& A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\
+"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\
+"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\
+"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\
+"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\
+"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\
+"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\
+"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\
+"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\
+"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\
+"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\
+"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\
+"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "((A_WEN | A_REN)& A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\
+"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\
+"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\
+"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\
+"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\
+"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\
+"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\
+"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\
+"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\
+"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\
+"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\
+"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\
+"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902");
+		}
+	}
+}
+pin(A_WEN) {
+   direction          : input ;
+   capacitance        : 0.00341384 ;
+   max_transition     : "0.38" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0068);
+		}
+		        fall_power("scalar"){
+		 values (0.0168);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0045);
+		}
+		        fall_power("scalar"){
+		 values (0.0208);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\
+"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\
+"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\
+"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\
+"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\
+"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\
+"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\
+"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\
+"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\
+"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\
+"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\
+"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\
+"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\
+"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\
+"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\
+"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\
+"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\
+"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\
+"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\
+"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\
+"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\
+"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\
+"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\
+"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\
+"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691");
+		}
+	}
+	}
+pin(A_REN) {
+   direction          : input ;
+   capacitance        : 0.00390661 ;
+   max_transition     : "0.38" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0070);
+		}
+		        fall_power("scalar"){
+		 values (0.0134);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0242);
+		}
+		        fall_power("scalar"){
+		 values (0.0209);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\
+"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\
+"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\
+"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\
+"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\
+"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\
+"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\
+"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\
+"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\
+"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\
+"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\
+"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\
+"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\
+"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\
+"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\
+"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\
+"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\
+"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\
+"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\
+"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\
+"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\
+"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\
+"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\
+"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\
+"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809");
+		}
+	}
+	}
+pin(A_MEN) {
+   direction          : input ;
+   capacitance        : 0.00326046 ;
+   max_transition     : "0.38" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		        rise_power("scalar"){
+		 values (0.1478);
+		}
+		        fall_power("scalar"){
+		 values (0.0124);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\
+"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\
+"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\
+"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\
+"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\
+"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\
+"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\
+"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\
+"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\
+"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\
+"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\
+"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\
+"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\
+"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\
+"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\
+"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\
+"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\
+"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\
+"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\
+"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\
+"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\
+"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\
+"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\
+"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\
+"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691");
+		}
+	}
+	}
+bus(A_BM) {
+   bus_type : D_15_0;
+   direction          : input ;
+   capacitance        : 0.00318267 ;
+   max_transition     : "0.38" ;
+   pin(A_BM[15:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0726);
+		}
+		        fall_power("scalar"){
+		 values (0.0881);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0856);
+		}
+		        fall_power("scalar"){
+		 values (0.0958);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "(A_WEN & A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.2152,-0.2044,-0.1888,-0.1634,-0.1224,-0.0492,0.0856",\
+"-0.2191,-0.2083,-0.1927,-0.1673,-0.1263,-0.0531,0.0817",\
+"-0.2230,-0.2122,-0.1966,-0.1712,-0.1302,-0.0570,0.0778",\
+"-0.2261,-0.2154,-0.1998,-0.1744,-0.1333,-0.0601,0.0747",\
+"-0.2386,-0.2278,-0.2122,-0.1868,-0.1458,-0.0725,0.0622",\
+"-0.2560,-0.2453,-0.2297,-0.2043,-0.1633,-0.0900,0.0447",\
+"-0.2837,-0.2729,-0.2573,-0.2319,-0.1909,-0.1177,0.0171");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.1917,-0.1800,-0.1673,-0.1400,-0.1029,-0.0296,0.0983",\
+"-0.1956,-0.1839,-0.1712,-0.1439,-0.1068,-0.0335,0.0944",\
+"-0.1995,-0.1878,-0.1751,-0.1478,-0.1107,-0.0374,0.0905",\
+"-0.2027,-0.1910,-0.1783,-0.1509,-0.1138,-0.0406,0.0873",\
+"-0.2151,-0.2034,-0.1907,-0.1634,-0.1263,-0.0530,0.0749",\
+"-0.2326,-0.2209,-0.2082,-0.1808,-0.1437,-0.0705,0.0574",\
+"-0.2602,-0.2485,-0.2358,-0.2085,-0.1714,-0.0981,0.0298");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "(A_WEN & A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.3203,0.3105,0.2949,0.2685,0.2314,0.1572,0.0224",\
+"0.3242,0.3144,0.2988,0.2724,0.2353,0.1611,0.0263",\
+"0.3281,0.3183,0.3027,0.2763,0.2392,0.1650,0.0302",\
+"0.3312,0.3215,0.3058,0.2795,0.2424,0.1681,0.0334",\
+"0.3437,0.3339,0.3183,0.2919,0.2548,0.1806,0.0458",\
+"0.3611,0.3514,0.3357,0.3094,0.2723,0.1980,0.0633",\
+"0.3888,0.3790,0.3634,0.3370,0.2999,0.2257,0.0909");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2920,0.2812,0.2676,0.2402,0.2041,0.1318,0.0019",\
+"0.2959,0.2851,0.2715,0.2441,0.2080,0.1357,0.0058",\
+"0.2998,0.2890,0.2754,0.2480,0.2119,0.1396,0.0097",\
+"0.3029,0.2922,0.2785,0.2512,0.2150,0.1428,0.0129",\
+"0.3154,0.3046,0.2909,0.2636,0.2275,0.1552,0.0253",\
+"0.3328,0.3221,0.3084,0.2811,0.2449,0.1727,0.0428",\
+"0.3605,0.3497,0.3361,0.3087,0.2726,0.2003,0.0704");
+		}
+	}
+}
+   pin(A_CLK)  {
+	   direction       : input;
+	   capacitance     : 0.00389386;
+	   max_transition  : "0.38";
+	   clock           : "true" ;
+	   pin_func_type   : active_rising ;
+
+	   timing () {
+		 timing_type : "min_pulse_width";
+		 related_pin : "A_CLK";
+		 rise_constraint("CLKTRAN_constraint_template") {
+		 index_1("0.004,0.38");
+		 values("0.12,0.12");
+		 }
+	   }
+
+	   related_power_pin : VDD;
+	   related_ground_pin : VSS;
+
+	internal_power() {
+		when : "!A_MEN  & !A_WEN & !A_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN  & A_WEN  & !A_REN";
+		        rise_power("scalar"){
+		 values (0.2437);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & A_WEN  & !A_REN";
+		        rise_power("scalar"){
+		 values (92.9376);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & A_WEN  & A_REN";
+		        rise_power("scalar"){
+		 values (89.8350);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & !A_WEN & A_REN";
+		        rise_power("scalar"){
+		 values (72.7475);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN & !A_WEN & A_REN";
+		        rise_power("scalar"){
+		 values (0.5007);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN & A_WEN  & A_REN";
+		        rise_power("scalar"){
+		 values (1.0180);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & !A_WEN & !A_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	}
+   bus(A_DIN) {
+	   bus_type : D_15_0;
+	   direction       : input ;
+	   capacitance     : 0.00332733 ;
+	   memory_write() {
+		   address : A_ADDR ;
+		   clocked_on : A_CLK;
+	   }
+
+	   max_transition  : "0.38" ;
+	   pin(A_DIN[15:0]) {
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0726);
+		}
+		        fall_power("scalar"){
+		 values (0.0881);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0856);
+		}
+		        fall_power("scalar"){
+		 values (0.0958);
+		}
+	}
+	   }
+	   timing() {
+		 timing_type     : setup_rising;
+		 related_pin     : "A_CLK";
+		 when            : "(A_WEN & A_MEN)";
+		 sdf_cond        : "A_W_ACCESS";
+
+	  rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 values ("-0.2152,-0.2044,-0.1888,-0.1634,-0.1224,-0.0492,0.0856",\
+"-0.2191,-0.2083,-0.1927,-0.1673,-0.1263,-0.0531,0.0817",\
+"-0.2230,-0.2122,-0.1966,-0.1712,-0.1302,-0.0570,0.0778",\
+"-0.2261,-0.2154,-0.1998,-0.1744,-0.1333,-0.0601,0.0747",\
+"-0.2386,-0.2278,-0.2122,-0.1868,-0.1458,-0.0725,0.0622",\
+"-0.2560,-0.2453,-0.2297,-0.2043,-0.1633,-0.0900,0.0447",\
+"-0.2837,-0.2729,-0.2573,-0.2319,-0.1909,-0.1177,0.0171");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 values ("-0.1917,-0.1800,-0.1673,-0.1400,-0.1029,-0.0296,0.0983",\
+"-0.1956,-0.1839,-0.1712,-0.1439,-0.1068,-0.0335,0.0944",\
+"-0.1995,-0.1878,-0.1751,-0.1478,-0.1107,-0.0374,0.0905",\
+"-0.2027,-0.1910,-0.1783,-0.1509,-0.1138,-0.0406,0.0873",\
+"-0.2151,-0.2034,-0.1907,-0.1634,-0.1263,-0.0530,0.0749",\
+"-0.2326,-0.2209,-0.2082,-0.1808,-0.1437,-0.0705,0.0574",\
+"-0.2602,-0.2485,-0.2358,-0.2085,-0.1714,-0.0981,0.0298");
+		 }
+	   }
+
+	   timing() {
+		 timing_type     : hold_rising;
+		 related_pin     : "A_CLK";
+		 when            : "(A_WEN & A_MEN)";
+		 sdf_cond        : "A_W_ACCESS";
+
+	   rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 values ("0.3203,0.3105,0.2949,0.2685,0.2314,0.1572,0.0224",\
+"0.3242,0.3144,0.2988,0.2724,0.2353,0.1611,0.0263",\
+"0.3281,0.3183,0.3027,0.2763,0.2392,0.1650,0.0302",\
+"0.3312,0.3215,0.3058,0.2795,0.2424,0.1681,0.0334",\
+"0.3437,0.3339,0.3183,0.2919,0.2548,0.1806,0.0458",\
+"0.3611,0.3514,0.3357,0.3094,0.2723,0.1980,0.0633",\
+"0.3888,0.3790,0.3634,0.3370,0.2999,0.2257,0.0909");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 values ("0.2920,0.2812,0.2676,0.2402,0.2041,0.1318,0.0019",\
+"0.2959,0.2851,0.2715,0.2441,0.2080,0.1357,0.0058",\
+"0.2998,0.2890,0.2754,0.2480,0.2119,0.1396,0.0097",\
+"0.3029,0.2922,0.2785,0.2512,0.2150,0.1428,0.0129",\
+"0.3154,0.3046,0.2909,0.2636,0.2275,0.1552,0.0253",\
+"0.3328,0.3221,0.3084,0.2811,0.2449,0.1727,0.0428",\
+"0.3605,0.3497,0.3361,0.3087,0.2726,0.2003,0.0704");
+		 }
+	   }
+   }
+
+   pin(A_BIST_EN) {
+	   direction       : input ;
+	   capacitance     : 0.00421562 ;
+	   max_transition  : "1" ;
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+		internal_power() {
+		  rise_power("scalar") {
+			 values (0);
+		  }
+		  fall_power("scalar") {
+			 values (0);
+		  }
+	   }
+   }
+
+bus(A_BIST_ADDR) {
+   bus_type : A_11_0;
+   direction          : input ;
+   capacitance        : 0.00691085 ;
+    pin(A_BIST_ADDR[0]) {
+       capacitance : 0.00562034 ;
+    }
+    pin(A_BIST_ADDR[1]) {
+       capacitance : 0.00462655 ;
+    }
+    pin(A_BIST_ADDR[2]) {
+       capacitance : 0.00594295 ;
+    }
+    pin(A_BIST_ADDR[3]) {
+       capacitance : 0.00723434 ;
+    }
+    pin(A_BIST_ADDR[4]) {
+       capacitance : 0.00481603 ;
+    }
+    pin(A_BIST_ADDR[5]) {
+       capacitance : 0.00868123 ;
+    }
+    pin(A_BIST_ADDR[6]) {
+       capacitance : 0.010187 ;
+    }
+    pin(A_BIST_ADDR[7]) {
+       capacitance : 0.00734489 ;
+    }
+    pin(A_BIST_ADDR[8]) {
+       capacitance : 0.00904175 ;
+    }
+    pin(A_BIST_ADDR[9]) {
+       capacitance : 0.0074973 ;
+    }
+    pin(A_BIST_ADDR[10]) {
+       capacitance : 0.00825659 ;
+    }
+   max_transition     : "0.38" ;
+   pin(A_BIST_ADDR[11:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0094);
+		}
+		        fall_power("scalar"){
+		 values (0.0008);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0200);
+		}
+		        fall_power("scalar"){
+		 values (0.0016);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\
+"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\
+"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\
+"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\
+"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\
+"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\
+"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\
+"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\
+"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\
+"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\
+"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\
+"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\
+"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\
+"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\
+"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\
+"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\
+"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\
+"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\
+"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\
+"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\
+"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\
+"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\
+"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\
+"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\
+"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902");
+		}
+	}
+}
+pin(A_BIST_WEN) {
+   direction          : input ;
+   capacitance        : 0.00341384 ;
+   max_transition     : "0.38" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0068);
+		}
+		        fall_power("scalar"){
+		 values (0.0168);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0045);
+		}
+		        fall_power("scalar"){
+		 values (0.0208);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\
+"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\
+"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\
+"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\
+"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\
+"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\
+"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\
+"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\
+"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\
+"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\
+"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\
+"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\
+"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\
+"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\
+"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\
+"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\
+"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\
+"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\
+"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\
+"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\
+"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\
+"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\
+"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\
+"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\
+"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691");
+		}
+	}
+	}
+pin(A_BIST_REN) {
+   direction          : input ;
+   capacitance        : 0.00390661 ;
+   max_transition     : "0.38" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0070);
+		}
+		        fall_power("scalar"){
+		 values (0.0134);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0242);
+		}
+		        fall_power("scalar"){
+		 values (0.0209);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\
+"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\
+"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\
+"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\
+"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\
+"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\
+"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\
+"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\
+"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\
+"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\
+"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\
+"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\
+"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\
+"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\
+"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\
+"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\
+"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\
+"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\
+"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\
+"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\
+"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\
+"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\
+"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\
+"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\
+"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809");
+		}
+	}
+	}
+pin(A_BIST_MEN) {
+   direction          : input ;
+   capacitance        : 0.00326046 ;
+   max_transition     : "0.38" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		        rise_power("scalar"){
+		 values (0.1478);
+		}
+		        fall_power("scalar"){
+		 values (0.0124);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\
+"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\
+"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\
+"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\
+"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\
+"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\
+"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\
+"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\
+"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\
+"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\
+"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\
+"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\
+"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\
+"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\
+"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\
+"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\
+"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\
+"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\
+"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\
+"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\
+"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\
+"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\
+"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\
+"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\
+"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691");
+		}
+	}
+	}
+bus(A_BIST_BM) {
+   bus_type : D_15_0;
+   direction          : input ;
+   capacitance        : 0.00252172 ;
+   max_transition     : "0.38" ;
+   pin(A_BIST_BM[15:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0726);
+		}
+		        fall_power("scalar"){
+		 values (0.0881);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0856);
+		}
+		        fall_power("scalar"){
+		 values (0.0958);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "(A_BIST_WEN & A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.2152,-0.2044,-0.1888,-0.1634,-0.1224,-0.0492,0.0856",\
+"-0.2191,-0.2083,-0.1927,-0.1673,-0.1263,-0.0531,0.0817",\
+"-0.2230,-0.2122,-0.1966,-0.1712,-0.1302,-0.0570,0.0778",\
+"-0.2261,-0.2154,-0.1998,-0.1744,-0.1333,-0.0601,0.0747",\
+"-0.2386,-0.2278,-0.2122,-0.1868,-0.1458,-0.0725,0.0622",\
+"-0.2560,-0.2453,-0.2297,-0.2043,-0.1633,-0.0900,0.0447",\
+"-0.2837,-0.2729,-0.2573,-0.2319,-0.1909,-0.1177,0.0171");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.1917,-0.1800,-0.1673,-0.1400,-0.1029,-0.0296,0.0983",\
+"-0.1956,-0.1839,-0.1712,-0.1439,-0.1068,-0.0335,0.0944",\
+"-0.1995,-0.1878,-0.1751,-0.1478,-0.1107,-0.0374,0.0905",\
+"-0.2027,-0.1910,-0.1783,-0.1509,-0.1138,-0.0406,0.0873",\
+"-0.2151,-0.2034,-0.1907,-0.1634,-0.1263,-0.0530,0.0749",\
+"-0.2326,-0.2209,-0.2082,-0.1808,-0.1437,-0.0705,0.0574",\
+"-0.2602,-0.2485,-0.2358,-0.2085,-0.1714,-0.0981,0.0298");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "(A_BIST_WEN & A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.3203,0.3105,0.2949,0.2685,0.2314,0.1572,0.0224",\
+"0.3242,0.3144,0.2988,0.2724,0.2353,0.1611,0.0263",\
+"0.3281,0.3183,0.3027,0.2763,0.2392,0.1650,0.0302",\
+"0.3312,0.3215,0.3058,0.2795,0.2424,0.1681,0.0334",\
+"0.3437,0.3339,0.3183,0.2919,0.2548,0.1806,0.0458",\
+"0.3611,0.3514,0.3357,0.3094,0.2723,0.1980,0.0633",\
+"0.3888,0.3790,0.3634,0.3370,0.2999,0.2257,0.0909");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2920,0.2812,0.2676,0.2402,0.2041,0.1318,0.0019",\
+"0.2959,0.2851,0.2715,0.2441,0.2080,0.1357,0.0058",\
+"0.2998,0.2890,0.2754,0.2480,0.2119,0.1396,0.0097",\
+"0.3029,0.2922,0.2785,0.2512,0.2150,0.1428,0.0129",\
+"0.3154,0.3046,0.2909,0.2636,0.2275,0.1552,0.0253",\
+"0.3328,0.3221,0.3084,0.2811,0.2449,0.1727,0.0428",\
+"0.3605,0.3497,0.3361,0.3087,0.2726,0.2003,0.0704");
+		}
+	}
+}
+   pin(A_BIST_CLK)  {
+	   direction       : input;
+	   capacitance     : 0.00389386;
+	   max_transition  : "0.38";
+	   clock           : "true" ;
+	   pin_func_type   : active_rising ;
+
+	   timing () {
+		 timing_type : "min_pulse_width";
+		 related_pin : "A_BIST_CLK";
+		 rise_constraint("CLKTRAN_constraint_template") {
+		 index_1("0.004,0.38");
+		 values("0.12,0.12");
+		 }
+	   }
+
+	   related_power_pin : VDD;
+	   related_ground_pin : VSS;
+
+	internal_power() {
+		when : "!A_BIST_MEN  & !A_BIST_WEN & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN  & A_BIST_WEN  & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0.2437);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & A_BIST_WEN  & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (92.9376);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & A_BIST_WEN  & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (89.8350);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & !A_BIST_WEN & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (72.7475);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0.5007);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN & A_BIST_WEN  & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (1.0180);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & !A_BIST_WEN & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	}
+   bus(A_BIST_DIN) {
+	   bus_type : D_15_0;
+	   direction       : input ;
+	   capacitance     : 0.00252023 ;
+	   memory_write() {
+		   address : A_BIST_ADDR ;
+		   clocked_on : A_BIST_CLK;
+	   }
+
+	   max_transition  : "0.38" ;
+	   pin(A_BIST_DIN[15:0]) {
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0726);
+		}
+		        fall_power("scalar"){
+		 values (0.0881);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0856);
+		}
+		        fall_power("scalar"){
+		 values (0.0958);
+		}
+	}
+	   }
+	   timing() {
+		 timing_type     : setup_rising;
+		 related_pin     : "A_BIST_CLK";
+		 when            : "(A_BIST_WEN & A_BIST_MEN)";
+		 sdf_cond        : "A_BIST_W_ACCESS";
+
+	  rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 values ("-0.2152,-0.2044,-0.1888,-0.1634,-0.1224,-0.0492,0.0856",\
+"-0.2191,-0.2083,-0.1927,-0.1673,-0.1263,-0.0531,0.0817",\
+"-0.2230,-0.2122,-0.1966,-0.1712,-0.1302,-0.0570,0.0778",\
+"-0.2261,-0.2154,-0.1998,-0.1744,-0.1333,-0.0601,0.0747",\
+"-0.2386,-0.2278,-0.2122,-0.1868,-0.1458,-0.0725,0.0622",\
+"-0.2560,-0.2453,-0.2297,-0.2043,-0.1633,-0.0900,0.0447",\
+"-0.2837,-0.2729,-0.2573,-0.2319,-0.1909,-0.1177,0.0171");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 values ("-0.1917,-0.1800,-0.1673,-0.1400,-0.1029,-0.0296,0.0983",\
+"-0.1956,-0.1839,-0.1712,-0.1439,-0.1068,-0.0335,0.0944",\
+"-0.1995,-0.1878,-0.1751,-0.1478,-0.1107,-0.0374,0.0905",\
+"-0.2027,-0.1910,-0.1783,-0.1509,-0.1138,-0.0406,0.0873",\
+"-0.2151,-0.2034,-0.1907,-0.1634,-0.1263,-0.0530,0.0749",\
+"-0.2326,-0.2209,-0.2082,-0.1808,-0.1437,-0.0705,0.0574",\
+"-0.2602,-0.2485,-0.2358,-0.2085,-0.1714,-0.0981,0.0298");
+		 }
+	   }
+
+	   timing() {
+		 timing_type     : hold_rising;
+		 related_pin     : "A_BIST_CLK";
+		 when            : "(A_BIST_WEN & A_BIST_MEN)";
+		 sdf_cond        : "A_BIST_W_ACCESS";
+
+	   rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 values ("0.3203,0.3105,0.2949,0.2685,0.2314,0.1572,0.0224",\
+"0.3242,0.3144,0.2988,0.2724,0.2353,0.1611,0.0263",\
+"0.3281,0.3183,0.3027,0.2763,0.2392,0.1650,0.0302",\
+"0.3312,0.3215,0.3058,0.2795,0.2424,0.1681,0.0334",\
+"0.3437,0.3339,0.3183,0.2919,0.2548,0.1806,0.0458",\
+"0.3611,0.3514,0.3357,0.3094,0.2723,0.1980,0.0633",\
+"0.3888,0.3790,0.3634,0.3370,0.2999,0.2257,0.0909");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 values ("0.2920,0.2812,0.2676,0.2402,0.2041,0.1318,0.0019",\
+"0.2959,0.2851,0.2715,0.2441,0.2080,0.1357,0.0058",\
+"0.2998,0.2890,0.2754,0.2480,0.2119,0.1396,0.0097",\
+"0.3029,0.2922,0.2785,0.2512,0.2150,0.1428,0.0129",\
+"0.3154,0.3046,0.2909,0.2636,0.2275,0.1552,0.0253",\
+"0.3328,0.3221,0.3084,0.2811,0.2449,0.1727,0.0428",\
+"0.3605,0.3497,0.3361,0.3087,0.2726,0.2003,0.0704");
+		 }
+	   }
+   }
+
+bus(A_DOUT) {
+
+	   bus_type : D_15_0;
+	   direction       : output ;
+	   capacitance     : 0 ;
+	   max_capacitance  : "6.4e-14" ;
+	   memory_read() {
+		  address : A_ADDR ;
+	   }
+	   pin(A_DOUT[15:0]) {
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+	   internal_power() {
+		  rise_power("scalar") {
+			 values (0);
+		  }
+		  fall_power("scalar") {
+			 values (0);
+		  }
+	   }
+	   }
+	   timing() {
+		 related_pin   : "A_CLK";
+		 timing_type   : rising_edge ;
+		 timing_sense  : non_unate ;
+
+	   cell_rise(SIG2SRAM_delay_template) {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("3.2854,3.2864,3.2912,3.2967,3.3176,3.3411",\
+"3.2918,3.2928,3.2976,3.3032,3.3241,3.3476",\
+"3.2958,3.2968,3.3016,3.3071,3.3280,3.3515",\
+"3.2991,3.3001,3.3049,3.3104,3.3313,3.3548",\
+"3.3077,3.3087,3.3136,3.3191,3.3400,3.3635",\
+"3.3298,3.3309,3.3357,3.3412,3.3621,3.3856",\
+"3.3553,3.3563,3.3612,3.3667,3.3876,3.4111");
+	   }
+	   cell_fall(SIG2SRAM_delay_template) {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("3.2511,3.2520,3.2560,3.2605,3.2776,3.2944",\
+"3.2575,3.2584,3.2624,3.2670,3.2841,3.3008",\
+"3.2615,3.2623,3.2664,3.2709,3.2880,3.3047",\
+"3.2648,3.2657,3.2697,3.2742,3.2913,3.3081",\
+"3.2734,3.2743,3.2783,3.2829,3.3000,3.3167",\
+"3.2956,3.2964,3.3005,3.3050,3.3221,3.3388",\
+"3.3210,3.3219,3.3259,3.3305,3.3476,3.3643");
+	   }
+
+	   rise_transition(SRAM_load_template) {
+		 index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("0.0206,0.0210,0.0265,0.0323,0.0606,0.0955");
+	   }
+	   fall_transition(SRAM_load_template) {
+		 index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("0.0170,0.0177,0.0222,0.0270,0.0451,0.0644");
+	   }
+	}
+}
+cell_leakage_power : 1878.3764;
+}
+}
diff --git a/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_4096x16_c3_bm_bist_slow_1p08V_125C.lib b/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_4096x16_c3_bm_bist_slow_1p08V_125C.lib
new file mode 100644
index 00000000..acf96781
--- /dev/null
+++ b/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_4096x16_c3_bm_bist_slow_1p08V_125C.lib
@@ -0,0 +1,1537 @@
+/* ------------------------------------------------------*/
+/**/
+/*		Copyright 2024 IHP PDK Authors*/
+/**/
+/*		Licensed under the Apache License, Version 2.0 (the "License");*/
+/*		you may not use this file except in compliance with the License.*/
+/*		You may obtain a copy of the License at*/
+/*		*/
+/*		   https://www.apache.org/licenses/LICENSE-2.0*/
+/*		*/
+/*		Unless required by applicable law or agreed to in writing, software*/
+/*		distributed under the License is distributed on an "AS IS" BASIS,*/
+/*		WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/
+/*		See the License for the specific language governing permissions and*/
+/*		limitations under the License.*/
+/*		*/
+/*		Generated on Fri Jul 12 17:37:31 2024		*/
+/*				*/
+/* ------------------------------------------------------ */
+library(RM_IHPSG13_1P_4096x16_c3_bm_bist_slow_1p08V_125C) {	
+	technology (cmos) ;
+	delay_model : table_lookup ;
+	define ("add_pg_pin_to_lib",  "library",  "boolean");
+	add_pg_pin_to_lib : true;
+	voltage_map ( VDD, 1.08);
+	voltage_map ( VDDARRAY, 1.08);
+	voltage_map ( VSS, 0.000000 );
+	
+	date            : "Fri Jul 12 17:37:29 2024" ;
+	comment         : "IHP Microelectronics GmbH, 2024" ;
+	revision        : 1.0.0 ;
+	simulation      : true ;
+	nom_process     : 1 ;
+	nom_temperature : 125 ;
+	nom_voltage     : 1.08 ;
+	
+	operating_conditions("slow_1p08V_125C"){
+	    process     : 1 ;
+	    temperature : 125 ;
+	    voltage     : 1.08 ;
+	    tree_type   : "balanced_tree" ;
+	}
+	
+	default_operating_conditions  : slow_1p08V_125C ;
+	default_max_transition        : 1.0 ;
+	default_fanout_load           : 1.0 ;
+	default_inout_pin_cap         : 0.0 ;
+	default_input_pin_cap         : 0.0 ;
+	default_output_pin_cap        : 0.0 ;
+	default_cell_leakage_power    : 0.0 ;
+	default_leakage_power_density : 0.0 ;
+	 
+	slew_lower_threshold_pct_rise : 30 ;
+	slew_upper_threshold_pct_rise : 70 ;
+	input_threshold_pct_fall      : 50 ;
+	output_threshold_pct_fall     : 50 ;
+	input_threshold_pct_rise      : 50 ;
+	output_threshold_pct_rise     : 50 ;
+	slew_lower_threshold_pct_fall : 30 ;
+	slew_upper_threshold_pct_fall : 70 ;
+	slew_derate_from_library      : 0.5;
+	k_volt_cell_leakage_power     : 0.0 ;
+	k_temp_cell_leakage_power     : 0.0 ;
+	k_process_cell_leakage_power  : 0.0 ;
+	k_volt_internal_power         : 0.0 ;
+	k_temp_internal_power         : 0.0 ;
+	k_process_internal_power      : 0.0 ;
+	
+	capacitive_load_unit            (1,pf) ;
+	voltage_unit                  : "1V" ;
+	current_unit                  : "1uA" ;
+	time_unit                     : "1ns" ;
+	leakage_power_unit            : "1nW" ;
+	pulling_resistance_unit       : "1kohm";
+	/*
+	  ------------------------------------------------------------------------------------------
+	  implicit units overview:
+	    cell_area       unit      : "um"
+	    internal_power  unit      : "1e-12 * J/toggle = 1 * uW/MHz"
+	                                (capacitive_load_unit * voltage_unit^2) per toggle event
+	  ------------------------------------------------------------------------------------------
+	*/
+	library_features(report_delay_calculation);
+	define_cell_area (pad_drivers,pad_driver_sites) ;
+	
+	lu_table_template(CLKTRAN_constraint_template) {
+	     variable_1 : constrained_pin_transition;
+	     index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" );
+	}
+	lu_table_template(SRAM_load_template) {
+	     variable_1 : total_output_net_capacitance;
+	     index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" );
+	}
+	lu_table_template(SIG2SRAM_constraint_template) {
+	     variable_1 : related_pin_transition;
+	     variable_2 : constrained_pin_transition;
+	     index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" );
+	     index_2 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" );
+	}
+	
+	lu_table_template(SIG2SRAM_delay_template) {
+	     variable_1 : input_net_transition;
+	     variable_2 : total_output_net_capacitance;
+	     index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" );
+	     index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" );
+	} 
+
+	type (D_15_0) {
+		base_type : array;
+		data_type : bit;
+		bit_width : 16;
+		bit_from  : 15;
+		bit_to    : 0;
+		downto    : true;
+	 }
+
+	type (A_11_0) {
+		base_type : array;
+		data_type : bit;
+		bit_width : 12;
+		bit_from  : 11;
+		bit_to    : 0;
+		downto    : true;
+	 }
+
+cell(RM_IHPSG13_1P_4096x16_c3_bm_bist) {
+pg_pin (VDD) {
+  pg_type : primary_power;
+  voltage_name : VDD;
+}
+pg_pin (VDDARRAY) {
+  pg_type : primary_power;
+  voltage_name : VDDARRAY;
+}
+pg_pin (VSS) {
+  pg_type : primary_ground;
+  voltage_name : VSS;
+}
+
+memory() {
+ type : ram;
+ address_width : 12;
+ word_width : 16;
+}
+
+interface_timing : false;
+bus_naming_style    :   "%s[%d]" ;
+area        : 257608.512 ;
+
+   pin(A_DLY) {
+	   direction       : input ;
+	   capacitance     : 0.00387999 ;
+	   max_transition  : "1" ;
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+		internal_power() {
+		  rise_power("scalar") {
+			 values (0);
+		  }
+		  fall_power("scalar") {
+			 values (0);
+		  }
+	   }
+   }
+
+bus(A_ADDR) {
+   bus_type : A_11_0;
+   direction          : input ;
+   capacitance        : 0.0077013 ;
+    pin(A_ADDR[0]) {
+       capacitance : 0.00625349 ;
+    }
+    pin(A_ADDR[1]) {
+       capacitance : 0.00507435 ;
+    }
+    pin(A_ADDR[2]) {
+       capacitance : 0.00656707 ;
+    }
+    pin(A_ADDR[3]) {
+       capacitance : 0.0083133 ;
+    }
+    pin(A_ADDR[4]) {
+       capacitance : 0.00507219 ;
+    }
+    pin(A_ADDR[5]) {
+       capacitance : 0.00964344 ;
+    }
+    pin(A_ADDR[6]) {
+       capacitance : 0.0119653 ;
+    }
+    pin(A_ADDR[7]) {
+       capacitance : 0.00827606 ;
+    }
+    pin(A_ADDR[8]) {
+       capacitance : 0.0110771 ;
+    }
+    pin(A_ADDR[9]) {
+       capacitance : 0.00811634 ;
+    }
+    pin(A_ADDR[10]) {
+       capacitance : 0.00916579 ;
+    }
+   max_transition     : "0.5952" ;
+   pin(A_ADDR[11:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0276);
+		}
+		        fall_power("scalar"){
+		 values (0.0166);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0210);
+		}
+		        fall_power("scalar"){
+		 values (0.0037);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "((A_WEN | A_REN)& A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\
+"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\
+"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\
+"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\
+"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\
+"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\
+"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\
+"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\
+"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\
+"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\
+"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\
+"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\
+"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "((A_WEN | A_REN)& A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3098",\
+"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\
+"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\
+"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\
+"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\
+"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\
+"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\
+"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\
+"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\
+"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\
+"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\
+"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\
+"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004");
+		}
+	}
+}
+pin(A_WEN) {
+   direction          : input ;
+   capacitance        : 0.00313551 ;
+   max_transition     : "0.5952" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0235);
+		}
+		        fall_power("scalar"){
+		 values (0.0210);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0049);
+		}
+		        fall_power("scalar"){
+		 values (0.0013);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\
+"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\
+"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\
+"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\
+"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\
+"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\
+"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\
+"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\
+"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\
+"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\
+"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\
+"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\
+"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\
+"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\
+"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\
+"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\
+"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\
+"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\
+"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\
+"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\
+"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\
+"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\
+"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\
+"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\
+"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879");
+		}
+	}
+	}
+pin(A_REN) {
+   direction          : input ;
+   capacitance        : 0.00381144 ;
+   max_transition     : "0.5952" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0239);
+		}
+		        fall_power("scalar"){
+		 values (0.0205);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0037);
+		}
+		        fall_power("scalar"){
+		 values (0.0003);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\
+"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\
+"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\
+"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\
+"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\
+"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\
+"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\
+"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\
+"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\
+"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\
+"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\
+"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\
+"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\
+"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\
+"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\
+"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\
+"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\
+"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\
+"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\
+"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\
+"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\
+"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\
+"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\
+"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\
+"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113");
+		}
+	}
+	}
+pin(A_MEN) {
+   direction          : input ;
+   capacitance        : 0.00300347 ;
+   max_transition     : "0.5952" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		        rise_power("scalar"){
+		 values (0.0853);
+		}
+		        fall_power("scalar"){
+		 values (0.0218);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\
+"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\
+"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\
+"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\
+"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\
+"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\
+"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\
+"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\
+"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\
+"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\
+"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\
+"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\
+"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\
+"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\
+"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\
+"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\
+"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\
+"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\
+"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\
+"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\
+"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\
+"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\
+"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\
+"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\
+"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918");
+		}
+	}
+	}
+bus(A_BM) {
+   bus_type : D_15_0;
+   direction          : input ;
+   capacitance        : 0.00272583 ;
+   max_transition     : "0.5952" ;
+   pin(A_BM[15:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0645);
+		}
+		        fall_power("scalar"){
+		 values (0.0555);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0341);
+		}
+		        fall_power("scalar"){
+		 values (0.0017);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "(A_WEN & A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.7140,-0.6945,-0.6681,-0.6252,-0.5451,-0.3976,-0.1769",\
+"-0.7220,-0.7025,-0.6761,-0.6332,-0.5531,-0.4056,-0.1849",\
+"-0.7321,-0.7126,-0.6862,-0.6433,-0.5632,-0.4157,-0.1950",\
+"-0.7451,-0.7255,-0.6992,-0.6562,-0.5761,-0.4286,-0.2079",\
+"-0.7704,-0.7509,-0.7245,-0.6815,-0.6015,-0.4540,-0.2333",\
+"-0.8126,-0.7931,-0.7667,-0.7237,-0.6437,-0.4962,-0.2755",\
+"-0.8770,-0.8575,-0.8311,-0.7882,-0.7081,-0.5606,-0.3399");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.6496,-0.6301,-0.6037,-0.5656,-0.4826,-0.3459,-0.1340",\
+"-0.6576,-0.6381,-0.6117,-0.5736,-0.4906,-0.3539,-0.1420",\
+"-0.6677,-0.6481,-0.6218,-0.5837,-0.5007,-0.3640,-0.1521",\
+"-0.6806,-0.6611,-0.6347,-0.5966,-0.5136,-0.3769,-0.1650",\
+"-0.7059,-0.6864,-0.6600,-0.6220,-0.5390,-0.4022,-0.1903",\
+"-0.7481,-0.7286,-0.7022,-0.6642,-0.5812,-0.4444,-0.2325",\
+"-0.8126,-0.7930,-0.7667,-0.7286,-0.6456,-0.5089,-0.2969");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "(A_WEN & A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.8263,0.8058,0.7804,0.7374,0.6593,0.5128,0.2901",\
+"0.8343,0.8138,0.7884,0.7454,0.6673,0.5208,0.2981",\
+"0.8444,0.8239,0.7985,0.7555,0.6774,0.5309,0.3082",\
+"0.8573,0.8368,0.8114,0.7684,0.6903,0.5438,0.3211",\
+"0.8826,0.8621,0.8367,0.7938,0.7156,0.5691,0.3465",\
+"0.9248,0.9043,0.8789,0.8360,0.7578,0.6113,0.3887",\
+"0.9892,0.9687,0.9433,0.9004,0.8223,0.6758,0.4531");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.7530,0.7355,0.7071,0.6661,0.5860,0.4483,0.2374",\
+"0.7610,0.7435,0.7151,0.6741,0.5940,0.4563,0.2454",\
+"0.7711,0.7535,0.7252,0.6842,0.6041,0.4664,0.2555",\
+"0.7841,0.7665,0.7381,0.6971,0.6170,0.4794,0.2684",\
+"0.8094,0.7918,0.7635,0.7225,0.6424,0.5047,0.2938",\
+"0.8516,0.8340,0.8057,0.7647,0.6846,0.5469,0.3360",\
+"0.9160,0.8984,0.8701,0.8291,0.7490,0.6113,0.4004");
+		}
+	}
+}
+   pin(A_CLK)  {
+	   direction       : input;
+	   capacitance     : 0.00378957;
+	   max_transition  : "0.5952";
+	   clock           : "true" ;
+	   pin_func_type   : active_rising ;
+
+	   timing () {
+		 timing_type : "min_pulse_width";
+		 related_pin : "A_CLK";
+		 rise_constraint("CLKTRAN_constraint_template") {
+		 index_1("0.008,0.5952");
+		 values("0.4,0.4");
+		 }
+	   }
+
+	   related_power_pin : VDD;
+	   related_ground_pin : VSS;
+
+	internal_power() {
+		when : "!A_MEN  & !A_WEN & !A_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN  & A_WEN  & !A_REN";
+		        rise_power("scalar"){
+		 values (2.4669);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & A_WEN  & !A_REN";
+		        rise_power("scalar"){
+		 values (60.0756);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & A_WEN  & A_REN";
+		        rise_power("scalar"){
+		 values (56.8329);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & !A_WEN & A_REN";
+		        rise_power("scalar"){
+		 values (47.0671);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN & !A_WEN & A_REN";
+		        rise_power("scalar"){
+		 values (0.5979);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN & A_WEN  & A_REN";
+		        rise_power("scalar"){
+		 values (0.9552);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & !A_WEN & !A_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	}
+   bus(A_DIN) {
+	   bus_type : D_15_0;
+	   direction       : input ;
+	   capacitance     : 0.00290547 ;
+	   memory_write() {
+		   address : A_ADDR ;
+		   clocked_on : A_CLK;
+	   }
+
+	   max_transition  : "0.5952" ;
+	   pin(A_DIN[15:0]) {
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0645);
+		}
+		        fall_power("scalar"){
+		 values (0.0555);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0341);
+		}
+		        fall_power("scalar"){
+		 values (0.0017);
+		}
+	}
+	   }
+	   timing() {
+		 timing_type     : setup_rising;
+		 related_pin     : "A_CLK";
+		 when            : "(A_WEN & A_MEN)";
+		 sdf_cond        : "A_W_ACCESS";
+
+	  rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 values ("-0.7140,-0.6945,-0.6681,-0.6252,-0.5451,-0.3976,-0.1769",\
+"-0.7220,-0.7025,-0.6761,-0.6332,-0.5531,-0.4056,-0.1849",\
+"-0.7321,-0.7126,-0.6862,-0.6433,-0.5632,-0.4157,-0.1950",\
+"-0.7451,-0.7255,-0.6992,-0.6562,-0.5761,-0.4286,-0.2079",\
+"-0.7704,-0.7509,-0.7245,-0.6815,-0.6015,-0.4540,-0.2333",\
+"-0.8126,-0.7931,-0.7667,-0.7237,-0.6437,-0.4962,-0.2755",\
+"-0.8770,-0.8575,-0.8311,-0.7882,-0.7081,-0.5606,-0.3399");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 values ("-0.6496,-0.6301,-0.6037,-0.5656,-0.4826,-0.3459,-0.1340",\
+"-0.6576,-0.6381,-0.6117,-0.5736,-0.4906,-0.3539,-0.1420",\
+"-0.6677,-0.6481,-0.6218,-0.5837,-0.5007,-0.3640,-0.1521",\
+"-0.6806,-0.6611,-0.6347,-0.5966,-0.5136,-0.3769,-0.1650",\
+"-0.7059,-0.6864,-0.6600,-0.6220,-0.5390,-0.4022,-0.1903",\
+"-0.7481,-0.7286,-0.7022,-0.6642,-0.5812,-0.4444,-0.2325",\
+"-0.8126,-0.7930,-0.7667,-0.7286,-0.6456,-0.5089,-0.2969");
+		 }
+	   }
+
+	   timing() {
+		 timing_type     : hold_rising;
+		 related_pin     : "A_CLK";
+		 when            : "(A_WEN & A_MEN)";
+		 sdf_cond        : "A_W_ACCESS";
+
+	   rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 values ("0.8263,0.8058,0.7804,0.7374,0.6593,0.5128,0.2901",\
+"0.8343,0.8138,0.7884,0.7454,0.6673,0.5208,0.2981",\
+"0.8444,0.8239,0.7985,0.7555,0.6774,0.5309,0.3082",\
+"0.8573,0.8368,0.8114,0.7684,0.6903,0.5438,0.3211",\
+"0.8826,0.8621,0.8367,0.7938,0.7156,0.5691,0.3465",\
+"0.9248,0.9043,0.8789,0.8360,0.7578,0.6113,0.3887",\
+"0.9892,0.9687,0.9433,0.9004,0.8223,0.6758,0.4531");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 values ("0.7530,0.7355,0.7071,0.6661,0.5860,0.4483,0.2374",\
+"0.7610,0.7435,0.7151,0.6741,0.5940,0.4563,0.2454",\
+"0.7711,0.7535,0.7252,0.6842,0.6041,0.4664,0.2555",\
+"0.7841,0.7665,0.7381,0.6971,0.6170,0.4794,0.2684",\
+"0.8094,0.7918,0.7635,0.7225,0.6424,0.5047,0.2938",\
+"0.8516,0.8340,0.8057,0.7647,0.6846,0.5469,0.3360",\
+"0.9160,0.8984,0.8701,0.8291,0.7490,0.6113,0.4004");
+		 }
+	   }
+   }
+
+   pin(A_BIST_EN) {
+	   direction       : input ;
+	   capacitance     : 0.00387999 ;
+	   max_transition  : "1" ;
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+		internal_power() {
+		  rise_power("scalar") {
+			 values (0);
+		  }
+		  fall_power("scalar") {
+			 values (0);
+		  }
+	   }
+   }
+
+bus(A_BIST_ADDR) {
+   bus_type : A_11_0;
+   direction          : input ;
+   capacitance        : 0.0077013 ;
+    pin(A_BIST_ADDR[0]) {
+       capacitance : 0.00625349 ;
+    }
+    pin(A_BIST_ADDR[1]) {
+       capacitance : 0.00507435 ;
+    }
+    pin(A_BIST_ADDR[2]) {
+       capacitance : 0.00656707 ;
+    }
+    pin(A_BIST_ADDR[3]) {
+       capacitance : 0.0083133 ;
+    }
+    pin(A_BIST_ADDR[4]) {
+       capacitance : 0.00507219 ;
+    }
+    pin(A_BIST_ADDR[5]) {
+       capacitance : 0.00964344 ;
+    }
+    pin(A_BIST_ADDR[6]) {
+       capacitance : 0.0119653 ;
+    }
+    pin(A_BIST_ADDR[7]) {
+       capacitance : 0.00827606 ;
+    }
+    pin(A_BIST_ADDR[8]) {
+       capacitance : 0.0110771 ;
+    }
+    pin(A_BIST_ADDR[9]) {
+       capacitance : 0.00811634 ;
+    }
+    pin(A_BIST_ADDR[10]) {
+       capacitance : 0.00916579 ;
+    }
+   max_transition     : "0.5952" ;
+   pin(A_BIST_ADDR[11:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0276);
+		}
+		        fall_power("scalar"){
+		 values (0.0166);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0210);
+		}
+		        fall_power("scalar"){
+		 values (0.0037);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\
+"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\
+"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\
+"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\
+"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\
+"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\
+"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\
+"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\
+"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\
+"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\
+"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\
+"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\
+"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3098",\
+"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\
+"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\
+"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\
+"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\
+"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\
+"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\
+"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\
+"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\
+"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\
+"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\
+"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\
+"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004");
+		}
+	}
+}
+pin(A_BIST_WEN) {
+   direction          : input ;
+   capacitance        : 0.00313551 ;
+   max_transition     : "0.5952" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0235);
+		}
+		        fall_power("scalar"){
+		 values (0.0210);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0049);
+		}
+		        fall_power("scalar"){
+		 values (0.0013);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\
+"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\
+"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\
+"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\
+"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\
+"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\
+"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\
+"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\
+"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\
+"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\
+"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\
+"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\
+"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\
+"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\
+"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\
+"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\
+"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\
+"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\
+"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\
+"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\
+"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\
+"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\
+"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\
+"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\
+"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879");
+		}
+	}
+	}
+pin(A_BIST_REN) {
+   direction          : input ;
+   capacitance        : 0.00381144 ;
+   max_transition     : "0.5952" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0239);
+		}
+		        fall_power("scalar"){
+		 values (0.0205);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0037);
+		}
+		        fall_power("scalar"){
+		 values (0.0003);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\
+"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\
+"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\
+"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\
+"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\
+"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\
+"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\
+"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\
+"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\
+"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\
+"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\
+"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\
+"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\
+"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\
+"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\
+"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\
+"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\
+"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\
+"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\
+"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\
+"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\
+"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\
+"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\
+"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\
+"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113");
+		}
+	}
+	}
+pin(A_BIST_MEN) {
+   direction          : input ;
+   capacitance        : 0.00300347 ;
+   max_transition     : "0.5952" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		        rise_power("scalar"){
+		 values (0.0853);
+		}
+		        fall_power("scalar"){
+		 values (0.0218);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\
+"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\
+"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\
+"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\
+"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\
+"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\
+"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\
+"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\
+"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\
+"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\
+"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\
+"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\
+"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\
+"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\
+"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\
+"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\
+"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\
+"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\
+"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\
+"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\
+"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\
+"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\
+"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\
+"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\
+"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918");
+		}
+	}
+	}
+bus(A_BIST_BM) {
+   bus_type : D_15_0;
+   direction          : input ;
+   capacitance        : 0.00223339 ;
+   max_transition     : "0.5952" ;
+   pin(A_BIST_BM[15:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0645);
+		}
+		        fall_power("scalar"){
+		 values (0.0555);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0341);
+		}
+		        fall_power("scalar"){
+		 values (0.0017);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "(A_BIST_WEN & A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.7140,-0.6945,-0.6681,-0.6252,-0.5451,-0.3976,-0.1769",\
+"-0.7220,-0.7025,-0.6761,-0.6332,-0.5531,-0.4056,-0.1849",\
+"-0.7321,-0.7126,-0.6862,-0.6433,-0.5632,-0.4157,-0.1950",\
+"-0.7451,-0.7255,-0.6992,-0.6562,-0.5761,-0.4286,-0.2079",\
+"-0.7704,-0.7509,-0.7245,-0.6815,-0.6015,-0.4540,-0.2333",\
+"-0.8126,-0.7931,-0.7667,-0.7237,-0.6437,-0.4962,-0.2755",\
+"-0.8770,-0.8575,-0.8311,-0.7882,-0.7081,-0.5606,-0.3399");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.6496,-0.6301,-0.6037,-0.5656,-0.4826,-0.3459,-0.1340",\
+"-0.6576,-0.6381,-0.6117,-0.5736,-0.4906,-0.3539,-0.1420",\
+"-0.6677,-0.6481,-0.6218,-0.5837,-0.5007,-0.3640,-0.1521",\
+"-0.6806,-0.6611,-0.6347,-0.5966,-0.5136,-0.3769,-0.1650",\
+"-0.7059,-0.6864,-0.6600,-0.6220,-0.5390,-0.4022,-0.1903",\
+"-0.7481,-0.7286,-0.7022,-0.6642,-0.5812,-0.4444,-0.2325",\
+"-0.8126,-0.7930,-0.7667,-0.7286,-0.6456,-0.5089,-0.2969");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "(A_BIST_WEN & A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.8263,0.8058,0.7804,0.7374,0.6593,0.5128,0.2901",\
+"0.8343,0.8138,0.7884,0.7454,0.6673,0.5208,0.2981",\
+"0.8444,0.8239,0.7985,0.7555,0.6774,0.5309,0.3082",\
+"0.8573,0.8368,0.8114,0.7684,0.6903,0.5438,0.3211",\
+"0.8826,0.8621,0.8367,0.7938,0.7156,0.5691,0.3465",\
+"0.9248,0.9043,0.8789,0.8360,0.7578,0.6113,0.3887",\
+"0.9892,0.9687,0.9433,0.9004,0.8223,0.6758,0.4531");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.7530,0.7355,0.7071,0.6661,0.5860,0.4483,0.2374",\
+"0.7610,0.7435,0.7151,0.6741,0.5940,0.4563,0.2454",\
+"0.7711,0.7535,0.7252,0.6842,0.6041,0.4664,0.2555",\
+"0.7841,0.7665,0.7381,0.6971,0.6170,0.4794,0.2684",\
+"0.8094,0.7918,0.7635,0.7225,0.6424,0.5047,0.2938",\
+"0.8516,0.8340,0.8057,0.7647,0.6846,0.5469,0.3360",\
+"0.9160,0.8984,0.8701,0.8291,0.7490,0.6113,0.4004");
+		}
+	}
+}
+   pin(A_BIST_CLK)  {
+	   direction       : input;
+	   capacitance     : 0.00378957;
+	   max_transition  : "0.5952";
+	   clock           : "true" ;
+	   pin_func_type   : active_rising ;
+
+	   timing () {
+		 timing_type : "min_pulse_width";
+		 related_pin : "A_BIST_CLK";
+		 rise_constraint("CLKTRAN_constraint_template") {
+		 index_1("0.008,0.5952");
+		 values("0.4,0.4");
+		 }
+	   }
+
+	   related_power_pin : VDD;
+	   related_ground_pin : VSS;
+
+	internal_power() {
+		when : "!A_BIST_MEN  & !A_BIST_WEN & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN  & A_BIST_WEN  & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (2.4669);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & A_BIST_WEN  & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (60.0756);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & A_BIST_WEN  & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (56.8329);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & !A_BIST_WEN & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (47.0671);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0.5979);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN & A_BIST_WEN  & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0.9552);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & !A_BIST_WEN & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	}
+   bus(A_BIST_DIN) {
+	   bus_type : D_15_0;
+	   direction       : input ;
+	   capacitance     : 0.00223473 ;
+	   memory_write() {
+		   address : A_BIST_ADDR ;
+		   clocked_on : A_BIST_CLK;
+	   }
+
+	   max_transition  : "0.5952" ;
+	   pin(A_BIST_DIN[15:0]) {
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0645);
+		}
+		        fall_power("scalar"){
+		 values (0.0555);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0341);
+		}
+		        fall_power("scalar"){
+		 values (0.0017);
+		}
+	}
+	   }
+	   timing() {
+		 timing_type     : setup_rising;
+		 related_pin     : "A_BIST_CLK";
+		 when            : "(A_BIST_WEN & A_BIST_MEN)";
+		 sdf_cond        : "A_BIST_W_ACCESS";
+
+	  rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 values ("-0.7140,-0.6945,-0.6681,-0.6252,-0.5451,-0.3976,-0.1769",\
+"-0.7220,-0.7025,-0.6761,-0.6332,-0.5531,-0.4056,-0.1849",\
+"-0.7321,-0.7126,-0.6862,-0.6433,-0.5632,-0.4157,-0.1950",\
+"-0.7451,-0.7255,-0.6992,-0.6562,-0.5761,-0.4286,-0.2079",\
+"-0.7704,-0.7509,-0.7245,-0.6815,-0.6015,-0.4540,-0.2333",\
+"-0.8126,-0.7931,-0.7667,-0.7237,-0.6437,-0.4962,-0.2755",\
+"-0.8770,-0.8575,-0.8311,-0.7882,-0.7081,-0.5606,-0.3399");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 values ("-0.6496,-0.6301,-0.6037,-0.5656,-0.4826,-0.3459,-0.1340",\
+"-0.6576,-0.6381,-0.6117,-0.5736,-0.4906,-0.3539,-0.1420",\
+"-0.6677,-0.6481,-0.6218,-0.5837,-0.5007,-0.3640,-0.1521",\
+"-0.6806,-0.6611,-0.6347,-0.5966,-0.5136,-0.3769,-0.1650",\
+"-0.7059,-0.6864,-0.6600,-0.6220,-0.5390,-0.4022,-0.1903",\
+"-0.7481,-0.7286,-0.7022,-0.6642,-0.5812,-0.4444,-0.2325",\
+"-0.8126,-0.7930,-0.7667,-0.7286,-0.6456,-0.5089,-0.2969");
+		 }
+	   }
+
+	   timing() {
+		 timing_type     : hold_rising;
+		 related_pin     : "A_BIST_CLK";
+		 when            : "(A_BIST_WEN & A_BIST_MEN)";
+		 sdf_cond        : "A_BIST_W_ACCESS";
+
+	   rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 values ("0.8263,0.8058,0.7804,0.7374,0.6593,0.5128,0.2901",\
+"0.8343,0.8138,0.7884,0.7454,0.6673,0.5208,0.2981",\
+"0.8444,0.8239,0.7985,0.7555,0.6774,0.5309,0.3082",\
+"0.8573,0.8368,0.8114,0.7684,0.6903,0.5438,0.3211",\
+"0.8826,0.8621,0.8367,0.7938,0.7156,0.5691,0.3465",\
+"0.9248,0.9043,0.8789,0.8360,0.7578,0.6113,0.3887",\
+"0.9892,0.9687,0.9433,0.9004,0.8223,0.6758,0.4531");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 values ("0.7530,0.7355,0.7071,0.6661,0.5860,0.4483,0.2374",\
+"0.7610,0.7435,0.7151,0.6741,0.5940,0.4563,0.2454",\
+"0.7711,0.7535,0.7252,0.6842,0.6041,0.4664,0.2555",\
+"0.7841,0.7665,0.7381,0.6971,0.6170,0.4794,0.2684",\
+"0.8094,0.7918,0.7635,0.7225,0.6424,0.5047,0.2938",\
+"0.8516,0.8340,0.8057,0.7647,0.6846,0.5469,0.3360",\
+"0.9160,0.8984,0.8701,0.8291,0.7490,0.6113,0.4004");
+		 }
+	   }
+   }
+
+bus(A_DOUT) {
+
+	   bus_type : D_15_0;
+	   direction       : output ;
+	   capacitance     : 0 ;
+	   max_capacitance  : "6.4e-14" ;
+	   memory_read() {
+		  address : A_ADDR ;
+	   }
+	   pin(A_DOUT[15:0]) {
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+	   internal_power() {
+		  rise_power("scalar") {
+			 values (0);
+		  }
+		  fall_power("scalar") {
+			 values (0);
+		  }
+	   }
+	   }
+	   timing() {
+		 related_pin   : "A_CLK";
+		 timing_type   : rising_edge ;
+		 timing_sense  : non_unate ;
+
+	   cell_rise(SIG2SRAM_delay_template) {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("8.8937,8.8964,8.9086,8.9228,8.9749,9.0329",\
+"8.9058,8.9085,8.9207,8.9349,8.9870,9.0450",\
+"8.9177,8.9205,8.9327,8.9469,8.9989,9.0569",\
+"8.9199,8.9226,8.9348,8.9490,9.0011,9.0591",\
+"8.9457,8.9484,8.9606,8.9748,9.0269,9.0849",\
+"8.9971,8.9998,9.0120,9.0262,9.0783,9.1363",\
+"9.0539,9.0566,9.0688,9.0830,9.1351,9.1931");
+	   }
+	   cell_fall(SIG2SRAM_delay_template) {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("8.7838,8.7860,8.7956,8.8074,8.8510,8.8947",\
+"8.7959,8.7981,8.8077,8.8195,8.8631,8.9068",\
+"8.8078,8.8100,8.8196,8.8314,8.8750,8.9187",\
+"8.8100,8.8121,8.8217,8.8336,8.8771,8.9209",\
+"8.8358,8.8380,8.8476,8.8594,8.9030,8.9467",\
+"8.8872,8.8893,8.8990,8.9108,8.9543,8.9981",\
+"8.9440,8.9462,8.9558,8.9676,9.0112,9.0549");
+	   }
+
+	   rise_transition(SRAM_load_template) {
+		 index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("0.0560,0.0583,0.0696,0.0816,0.1519,0.2335");
+	   }
+	   fall_transition(SRAM_load_template) {
+		 index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("0.0428,0.0445,0.0538,0.0658,0.1181,0.1751");
+	   }
+	}
+}
+cell_leakage_power : 5226.3526;
+}
+}
diff --git a/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_4096x16_c3_bm_bist_typ_1p20V_25C.lib b/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_4096x16_c3_bm_bist_typ_1p20V_25C.lib
new file mode 100644
index 00000000..86dafef0
--- /dev/null
+++ b/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_4096x16_c3_bm_bist_typ_1p20V_25C.lib
@@ -0,0 +1,1537 @@
+/* ------------------------------------------------------*/
+/**/
+/*		Copyright 2024 IHP PDK Authors*/
+/**/
+/*		Licensed under the Apache License, Version 2.0 (the "License");*/
+/*		you may not use this file except in compliance with the License.*/
+/*		You may obtain a copy of the License at*/
+/*		*/
+/*		   https://www.apache.org/licenses/LICENSE-2.0*/
+/*		*/
+/*		Unless required by applicable law or agreed to in writing, software*/
+/*		distributed under the License is distributed on an "AS IS" BASIS,*/
+/*		WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/
+/*		See the License for the specific language governing permissions and*/
+/*		limitations under the License.*/
+/*		*/
+/*		Generated on Fri Jul 12 17:37:35 2024		*/
+/*				*/
+/* ------------------------------------------------------ */
+library(RM_IHPSG13_1P_4096x16_c3_bm_bist_typ_1p20V_25C) {	
+	technology (cmos) ;
+	delay_model : table_lookup ;
+	define ("add_pg_pin_to_lib",  "library",  "boolean");
+	add_pg_pin_to_lib : true;
+	voltage_map ( VDD, 1.20);
+	voltage_map ( VDDARRAY, 1.20);
+	voltage_map ( VSS, 0.000000 );
+	
+	date            : "Fri Jul 12 17:37:29 2024" ;
+	comment         : "IHP Microelectronics GmbH, 2024" ;
+	revision        : 1.0.0 ;
+	simulation      : true ;
+	nom_process     : 1 ;
+	nom_temperature : 25 ;
+	nom_voltage     : 1.20 ;
+	
+	operating_conditions("typ_1p20V_25C"){
+	    process     : 1 ;
+	    temperature : 25 ;
+	    voltage     : 1.20 ;
+	    tree_type   : "balanced_tree" ;
+	}
+	
+	default_operating_conditions  : typ_1p20V_25C ;
+	default_max_transition        : 1.0 ;
+	default_fanout_load           : 1.0 ;
+	default_inout_pin_cap         : 0.0 ;
+	default_input_pin_cap         : 0.0 ;
+	default_output_pin_cap        : 0.0 ;
+	default_cell_leakage_power    : 0.0 ;
+	default_leakage_power_density : 0.0 ;
+	 
+	slew_lower_threshold_pct_rise : 30 ;
+	slew_upper_threshold_pct_rise : 70 ;
+	input_threshold_pct_fall      : 50 ;
+	output_threshold_pct_fall     : 50 ;
+	input_threshold_pct_rise      : 50 ;
+	output_threshold_pct_rise     : 50 ;
+	slew_lower_threshold_pct_fall : 30 ;
+	slew_upper_threshold_pct_fall : 70 ;
+	slew_derate_from_library      : 0.5;
+	k_volt_cell_leakage_power     : 0.0 ;
+	k_temp_cell_leakage_power     : 0.0 ;
+	k_process_cell_leakage_power  : 0.0 ;
+	k_volt_internal_power         : 0.0 ;
+	k_temp_internal_power         : 0.0 ;
+	k_process_internal_power      : 0.0 ;
+	
+	capacitive_load_unit            (1,pf) ;
+	voltage_unit                  : "1V" ;
+	current_unit                  : "1uA" ;
+	time_unit                     : "1ns" ;
+	leakage_power_unit            : "1nW" ;
+	pulling_resistance_unit       : "1kohm";
+	/*
+	  ------------------------------------------------------------------------------------------
+	  implicit units overview:
+	    cell_area       unit      : "um"
+	    internal_power  unit      : "1e-12 * J/toggle = 1 * uW/MHz"
+	                                (capacitive_load_unit * voltage_unit^2) per toggle event
+	  ------------------------------------------------------------------------------------------
+	*/
+	library_features(report_delay_calculation);
+	define_cell_area (pad_drivers,pad_driver_sites) ;
+	
+	lu_table_template(CLKTRAN_constraint_template) {
+	     variable_1 : constrained_pin_transition;
+	     index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" );
+	}
+	lu_table_template(SRAM_load_template) {
+	     variable_1 : total_output_net_capacitance;
+	     index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" );
+	}
+	lu_table_template(SIG2SRAM_constraint_template) {
+	     variable_1 : related_pin_transition;
+	     variable_2 : constrained_pin_transition;
+	     index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" );
+	     index_2 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" );
+	}
+	
+	lu_table_template(SIG2SRAM_delay_template) {
+	     variable_1 : input_net_transition;
+	     variable_2 : total_output_net_capacitance;
+	     index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" );
+	     index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" );
+	} 
+
+	type (D_15_0) {
+		base_type : array;
+		data_type : bit;
+		bit_width : 16;
+		bit_from  : 15;
+		bit_to    : 0;
+		downto    : true;
+	 }
+
+	type (A_11_0) {
+		base_type : array;
+		data_type : bit;
+		bit_width : 12;
+		bit_from  : 11;
+		bit_to    : 0;
+		downto    : true;
+	 }
+
+cell(RM_IHPSG13_1P_4096x16_c3_bm_bist) {
+pg_pin (VDD) {
+  pg_type : primary_power;
+  voltage_name : VDD;
+}
+pg_pin (VDDARRAY) {
+  pg_type : primary_power;
+  voltage_name : VDDARRAY;
+}
+pg_pin (VSS) {
+  pg_type : primary_ground;
+  voltage_name : VSS;
+}
+
+memory() {
+ type : ram;
+ address_width : 12;
+ word_width : 16;
+}
+
+interface_timing : false;
+bus_naming_style    :   "%s[%d]" ;
+area        : 257608.512 ;
+
+   pin(A_DLY) {
+	   direction       : input ;
+	   capacitance     : 0.00401111 ;
+	   max_transition  : "1" ;
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+		internal_power() {
+		  rise_power("scalar") {
+			 values (0);
+		  }
+		  fall_power("scalar") {
+			 values (0);
+		  }
+	   }
+   }
+
+bus(A_ADDR) {
+   bus_type : A_11_0;
+   direction          : input ;
+   capacitance        : 0.00721489 ;
+    pin(A_ADDR[0]) {
+       capacitance : 0.00593979 ;
+    }
+    pin(A_ADDR[1]) {
+       capacitance : 0.00483009 ;
+    }
+    pin(A_ADDR[2]) {
+       capacitance : 0.006215 ;
+    }
+    pin(A_ADDR[3]) {
+       capacitance : 0.00766726 ;
+    }
+    pin(A_ADDR[4]) {
+       capacitance : 0.00488951 ;
+    }
+    pin(A_ADDR[5]) {
+       capacitance : 0.0091523 ;
+    }
+    pin(A_ADDR[6]) {
+       capacitance : 0.0109212 ;
+    }
+    pin(A_ADDR[7]) {
+       capacitance : 0.00774122 ;
+    }
+    pin(A_ADDR[8]) {
+       capacitance : 0.0101403 ;
+    }
+    pin(A_ADDR[9]) {
+       capacitance : 0.00771605 ;
+    }
+    pin(A_ADDR[10]) {
+       capacitance : 0.00860549 ;
+    }
+   max_transition     : "0.476" ;
+   pin(A_ADDR[11:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0076);
+		}
+		        fall_power("scalar"){
+		 values (0.0017);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0180);
+		}
+		        fall_power("scalar"){
+		 values (0.0031);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "((A_WEN | A_REN)& A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\
+"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\
+"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\
+"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\
+"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\
+"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\
+"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\
+"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\
+"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\
+"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\
+"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\
+"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\
+"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "((A_WEN | A_REN)& A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\
+"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\
+"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\
+"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\
+"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\
+"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\
+"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\
+"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\
+"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\
+"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\
+"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\
+"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\
+"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387");
+		}
+	}
+}
+pin(A_WEN) {
+   direction          : input ;
+   capacitance        : 0.00324098 ;
+   max_transition     : "0.476" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0038);
+		}
+		        fall_power("scalar"){
+		 values (0.0050);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0034);
+		}
+		        fall_power("scalar"){
+		 values (0.0050);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\
+"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\
+"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\
+"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\
+"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\
+"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\
+"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\
+"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\
+"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\
+"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\
+"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\
+"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\
+"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\
+"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\
+"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\
+"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\
+"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\
+"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\
+"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\
+"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\
+"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\
+"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\
+"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\
+"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\
+"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512");
+		}
+	}
+	}
+pin(A_REN) {
+   direction          : input ;
+   capacitance        : 0.00381634 ;
+   max_transition     : "0.476" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0054);
+		}
+		        fall_power("scalar"){
+		 values (0.0036);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0053);
+		}
+		        fall_power("scalar"){
+		 values (0.0036);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\
+"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\
+"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\
+"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\
+"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\
+"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\
+"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\
+"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\
+"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\
+"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\
+"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\
+"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\
+"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\
+"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\
+"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\
+"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\
+"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\
+"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\
+"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\
+"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\
+"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\
+"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\
+"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\
+"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\
+"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707");
+		}
+	}
+	}
+pin(A_MEN) {
+   direction          : input ;
+   capacitance        : 0.00309605 ;
+   max_transition     : "0.476" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		        rise_power("scalar"){
+		 values (0.0457);
+		}
+		        fall_power("scalar"){
+		 values (0.0060);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\
+"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\
+"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\
+"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\
+"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\
+"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\
+"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\
+"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\
+"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\
+"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\
+"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\
+"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\
+"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\
+"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\
+"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\
+"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\
+"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\
+"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\
+"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\
+"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\
+"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\
+"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\
+"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\
+"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\
+"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512");
+		}
+	}
+	}
+bus(A_BM) {
+   bus_type : D_15_0;
+   direction          : input ;
+   capacitance        : 0.00293842 ;
+   max_transition     : "0.476" ;
+   pin(A_BM[15:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0486);
+		}
+		        fall_power("scalar"){
+		 values (0.0390);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0482);
+		}
+		        fall_power("scalar"){
+		 values (0.0381);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "(A_WEN & A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.3928,-0.3771,-0.3635,-0.3312,-0.2844,-0.1799,0.0115",\
+"-0.3978,-0.3821,-0.3685,-0.3362,-0.2894,-0.1849,0.0065",\
+"-0.4022,-0.3866,-0.3729,-0.3407,-0.2939,-0.1894,0.0020",\
+"-0.4120,-0.3964,-0.3827,-0.3505,-0.3036,-0.1991,-0.0077",\
+"-0.4186,-0.4029,-0.3893,-0.3570,-0.3102,-0.2057,-0.0143",\
+"-0.4495,-0.4339,-0.4203,-0.3880,-0.3411,-0.2367,-0.0453",\
+"-0.5056,-0.4899,-0.4762,-0.4440,-0.3971,-0.2927,-0.1012");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.3547,-0.3400,-0.3264,-0.2980,-0.2473,-0.1496,0.0330",\
+"-0.3597,-0.3450,-0.3314,-0.3030,-0.2523,-0.1546,0.0280",\
+"-0.3642,-0.3495,-0.3358,-0.3075,-0.2567,-0.1591,0.0235",\
+"-0.3739,-0.3593,-0.3456,-0.3173,-0.2665,-0.1688,0.0138",\
+"-0.3805,-0.3658,-0.3522,-0.3238,-0.2731,-0.1754,0.0072",\
+"-0.4115,-0.3968,-0.3831,-0.3548,-0.3040,-0.2064,-0.0238",\
+"-0.4675,-0.4528,-0.4391,-0.4108,-0.3600,-0.2624,-0.0798");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "(A_WEN & A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.5019,0.4853,0.4726,0.4404,0.3925,0.2890,0.0966",\
+"0.5069,0.4903,0.4776,0.4454,0.3975,0.2940,0.1016",\
+"0.5114,0.4948,0.4821,0.4499,0.4020,0.2985,0.1061",\
+"0.5211,0.5046,0.4919,0.4596,0.4118,0.3083,0.1159",\
+"0.5277,0.5111,0.4984,0.4662,0.4183,0.3148,0.1224",\
+"0.5587,0.5421,0.5294,0.4972,0.4493,0.3458,0.1534",\
+"0.6147,0.5981,0.5854,0.5532,0.5053,0.4018,0.2094");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.4560,0.4414,0.4277,0.3994,0.3496,0.2568,0.0722",\
+"0.4610,0.4464,0.4327,0.4044,0.3546,0.2618,0.0772",\
+"0.4655,0.4508,0.4372,0.4088,0.3590,0.2663,0.0817",\
+"0.4753,0.4606,0.4469,0.4186,0.3688,0.2760,0.0915",\
+"0.4818,0.4672,0.4535,0.4252,0.3754,0.2826,0.0980",\
+"0.5128,0.4981,0.4845,0.4561,0.4063,0.3136,0.1290",\
+"0.5688,0.5541,0.5405,0.5121,0.4623,0.3696,0.1850");
+		}
+	}
+}
+   pin(A_CLK)  {
+	   direction       : input;
+	   capacitance     : 0.00380014;
+	   max_transition  : "0.476";
+	   clock           : "true" ;
+	   pin_func_type   : active_rising ;
+
+	   timing () {
+		 timing_type : "min_pulse_width";
+		 related_pin : "A_CLK";
+		 rise_constraint("CLKTRAN_constraint_template") {
+		 index_1("0.0056,0.476");
+		 values("0.21,0.21");
+		 }
+	   }
+
+	   related_power_pin : VDD;
+	   related_ground_pin : VSS;
+
+	internal_power() {
+		when : "!A_MEN  & !A_WEN & !A_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN  & A_WEN  & !A_REN";
+		        rise_power("scalar"){
+		 values (1.6932);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & A_WEN  & !A_REN";
+		        rise_power("scalar"){
+		 values (72.4898);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & A_WEN  & A_REN";
+		        rise_power("scalar"){
+		 values (73.1657);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & !A_WEN & A_REN";
+		        rise_power("scalar"){
+		 values (58.6440);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN & !A_WEN & A_REN";
+		        rise_power("scalar"){
+		 values (0.3446);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN & A_WEN  & A_REN";
+		        rise_power("scalar"){
+		 values (0.7709);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & !A_WEN & !A_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	}
+   bus(A_DIN) {
+	   bus_type : D_15_0;
+	   direction       : input ;
+	   capacitance     : 0.0030602 ;
+	   memory_write() {
+		   address : A_ADDR ;
+		   clocked_on : A_CLK;
+	   }
+
+	   max_transition  : "0.476" ;
+	   pin(A_DIN[15:0]) {
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0486);
+		}
+		        fall_power("scalar"){
+		 values (0.0390);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0482);
+		}
+		        fall_power("scalar"){
+		 values (0.0381);
+		}
+	}
+	   }
+	   timing() {
+		 timing_type     : setup_rising;
+		 related_pin     : "A_CLK";
+		 when            : "(A_WEN & A_MEN)";
+		 sdf_cond        : "A_W_ACCESS";
+
+	  rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 values ("-0.3928,-0.3771,-0.3635,-0.3312,-0.2844,-0.1799,0.0115",\
+"-0.3978,-0.3821,-0.3685,-0.3362,-0.2894,-0.1849,0.0065",\
+"-0.4022,-0.3866,-0.3729,-0.3407,-0.2939,-0.1894,0.0020",\
+"-0.4120,-0.3964,-0.3827,-0.3505,-0.3036,-0.1991,-0.0077",\
+"-0.4186,-0.4029,-0.3893,-0.3570,-0.3102,-0.2057,-0.0143",\
+"-0.4495,-0.4339,-0.4203,-0.3880,-0.3411,-0.2367,-0.0453",\
+"-0.5056,-0.4899,-0.4762,-0.4440,-0.3971,-0.2927,-0.1012");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 values ("-0.3547,-0.3400,-0.3264,-0.2980,-0.2473,-0.1496,0.0330",\
+"-0.3597,-0.3450,-0.3314,-0.3030,-0.2523,-0.1546,0.0280",\
+"-0.3642,-0.3495,-0.3358,-0.3075,-0.2567,-0.1591,0.0235",\
+"-0.3739,-0.3593,-0.3456,-0.3173,-0.2665,-0.1688,0.0138",\
+"-0.3805,-0.3658,-0.3522,-0.3238,-0.2731,-0.1754,0.0072",\
+"-0.4115,-0.3968,-0.3831,-0.3548,-0.3040,-0.2064,-0.0238",\
+"-0.4675,-0.4528,-0.4391,-0.4108,-0.3600,-0.2624,-0.0798");
+		 }
+	   }
+
+	   timing() {
+		 timing_type     : hold_rising;
+		 related_pin     : "A_CLK";
+		 when            : "(A_WEN & A_MEN)";
+		 sdf_cond        : "A_W_ACCESS";
+
+	   rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 values ("0.5019,0.4853,0.4726,0.4404,0.3925,0.2890,0.0966",\
+"0.5069,0.4903,0.4776,0.4454,0.3975,0.2940,0.1016",\
+"0.5114,0.4948,0.4821,0.4499,0.4020,0.2985,0.1061",\
+"0.5211,0.5046,0.4919,0.4596,0.4118,0.3083,0.1159",\
+"0.5277,0.5111,0.4984,0.4662,0.4183,0.3148,0.1224",\
+"0.5587,0.5421,0.5294,0.4972,0.4493,0.3458,0.1534",\
+"0.6147,0.5981,0.5854,0.5532,0.5053,0.4018,0.2094");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 values ("0.4560,0.4414,0.4277,0.3994,0.3496,0.2568,0.0722",\
+"0.4610,0.4464,0.4327,0.4044,0.3546,0.2618,0.0772",\
+"0.4655,0.4508,0.4372,0.4088,0.3590,0.2663,0.0817",\
+"0.4753,0.4606,0.4469,0.4186,0.3688,0.2760,0.0915",\
+"0.4818,0.4672,0.4535,0.4252,0.3754,0.2826,0.0980",\
+"0.5128,0.4981,0.4845,0.4561,0.4063,0.3136,0.1290",\
+"0.5688,0.5541,0.5405,0.5121,0.4623,0.3696,0.1850");
+		 }
+	   }
+   }
+
+   pin(A_BIST_EN) {
+	   direction       : input ;
+	   capacitance     : 0.00401111 ;
+	   max_transition  : "1" ;
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+		internal_power() {
+		  rise_power("scalar") {
+			 values (0);
+		  }
+		  fall_power("scalar") {
+			 values (0);
+		  }
+	   }
+   }
+
+bus(A_BIST_ADDR) {
+   bus_type : A_11_0;
+   direction          : input ;
+   capacitance        : 0.00721489 ;
+    pin(A_BIST_ADDR[0]) {
+       capacitance : 0.00593979 ;
+    }
+    pin(A_BIST_ADDR[1]) {
+       capacitance : 0.00483009 ;
+    }
+    pin(A_BIST_ADDR[2]) {
+       capacitance : 0.006215 ;
+    }
+    pin(A_BIST_ADDR[3]) {
+       capacitance : 0.00766726 ;
+    }
+    pin(A_BIST_ADDR[4]) {
+       capacitance : 0.00488951 ;
+    }
+    pin(A_BIST_ADDR[5]) {
+       capacitance : 0.0091523 ;
+    }
+    pin(A_BIST_ADDR[6]) {
+       capacitance : 0.0109212 ;
+    }
+    pin(A_BIST_ADDR[7]) {
+       capacitance : 0.00774122 ;
+    }
+    pin(A_BIST_ADDR[8]) {
+       capacitance : 0.0101403 ;
+    }
+    pin(A_BIST_ADDR[9]) {
+       capacitance : 0.00771605 ;
+    }
+    pin(A_BIST_ADDR[10]) {
+       capacitance : 0.00860549 ;
+    }
+   max_transition     : "0.476" ;
+   pin(A_BIST_ADDR[11:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0076);
+		}
+		        fall_power("scalar"){
+		 values (0.0017);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0180);
+		}
+		        fall_power("scalar"){
+		 values (0.0031);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\
+"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\
+"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\
+"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\
+"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\
+"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\
+"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\
+"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\
+"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\
+"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\
+"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\
+"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\
+"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\
+"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\
+"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\
+"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\
+"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\
+"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\
+"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\
+"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\
+"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\
+"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\
+"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\
+"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\
+"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387");
+		}
+	}
+}
+pin(A_BIST_WEN) {
+   direction          : input ;
+   capacitance        : 0.00324098 ;
+   max_transition     : "0.476" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0038);
+		}
+		        fall_power("scalar"){
+		 values (0.0050);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0034);
+		}
+		        fall_power("scalar"){
+		 values (0.0050);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\
+"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\
+"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\
+"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\
+"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\
+"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\
+"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\
+"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\
+"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\
+"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\
+"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\
+"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\
+"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\
+"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\
+"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\
+"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\
+"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\
+"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\
+"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\
+"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\
+"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\
+"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\
+"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\
+"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\
+"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512");
+		}
+	}
+	}
+pin(A_BIST_REN) {
+   direction          : input ;
+   capacitance        : 0.00381634 ;
+   max_transition     : "0.476" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0054);
+		}
+		        fall_power("scalar"){
+		 values (0.0036);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0053);
+		}
+		        fall_power("scalar"){
+		 values (0.0036);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\
+"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\
+"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\
+"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\
+"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\
+"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\
+"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\
+"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\
+"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\
+"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\
+"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\
+"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\
+"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\
+"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\
+"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\
+"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\
+"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\
+"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\
+"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\
+"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\
+"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\
+"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\
+"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\
+"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\
+"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707");
+		}
+	}
+	}
+pin(A_BIST_MEN) {
+   direction          : input ;
+   capacitance        : 0.00309605 ;
+   max_transition     : "0.476" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		        rise_power("scalar"){
+		 values (0.0457);
+		}
+		        fall_power("scalar"){
+		 values (0.0060);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\
+"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\
+"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\
+"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\
+"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\
+"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\
+"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\
+"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\
+"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\
+"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\
+"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\
+"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\
+"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\
+"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\
+"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\
+"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\
+"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\
+"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\
+"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\
+"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\
+"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\
+"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\
+"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\
+"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\
+"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512");
+		}
+	}
+	}
+bus(A_BIST_BM) {
+   bus_type : D_15_0;
+   direction          : input ;
+   capacitance        : 0.00236845 ;
+   max_transition     : "0.476" ;
+   pin(A_BIST_BM[15:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0486);
+		}
+		        fall_power("scalar"){
+		 values (0.0390);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0482);
+		}
+		        fall_power("scalar"){
+		 values (0.0381);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "(A_BIST_WEN & A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.3928,-0.3771,-0.3635,-0.3312,-0.2844,-0.1799,0.0115",\
+"-0.3978,-0.3821,-0.3685,-0.3362,-0.2894,-0.1849,0.0065",\
+"-0.4022,-0.3866,-0.3729,-0.3407,-0.2939,-0.1894,0.0020",\
+"-0.4120,-0.3964,-0.3827,-0.3505,-0.3036,-0.1991,-0.0077",\
+"-0.4186,-0.4029,-0.3893,-0.3570,-0.3102,-0.2057,-0.0143",\
+"-0.4495,-0.4339,-0.4203,-0.3880,-0.3411,-0.2367,-0.0453",\
+"-0.5056,-0.4899,-0.4762,-0.4440,-0.3971,-0.2927,-0.1012");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.3547,-0.3400,-0.3264,-0.2980,-0.2473,-0.1496,0.0330",\
+"-0.3597,-0.3450,-0.3314,-0.3030,-0.2523,-0.1546,0.0280",\
+"-0.3642,-0.3495,-0.3358,-0.3075,-0.2567,-0.1591,0.0235",\
+"-0.3739,-0.3593,-0.3456,-0.3173,-0.2665,-0.1688,0.0138",\
+"-0.3805,-0.3658,-0.3522,-0.3238,-0.2731,-0.1754,0.0072",\
+"-0.4115,-0.3968,-0.3831,-0.3548,-0.3040,-0.2064,-0.0238",\
+"-0.4675,-0.4528,-0.4391,-0.4108,-0.3600,-0.2624,-0.0798");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "(A_BIST_WEN & A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.5019,0.4853,0.4726,0.4404,0.3925,0.2890,0.0966",\
+"0.5069,0.4903,0.4776,0.4454,0.3975,0.2940,0.1016",\
+"0.5114,0.4948,0.4821,0.4499,0.4020,0.2985,0.1061",\
+"0.5211,0.5046,0.4919,0.4596,0.4118,0.3083,0.1159",\
+"0.5277,0.5111,0.4984,0.4662,0.4183,0.3148,0.1224",\
+"0.5587,0.5421,0.5294,0.4972,0.4493,0.3458,0.1534",\
+"0.6147,0.5981,0.5854,0.5532,0.5053,0.4018,0.2094");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.4560,0.4414,0.4277,0.3994,0.3496,0.2568,0.0722",\
+"0.4610,0.4464,0.4327,0.4044,0.3546,0.2618,0.0772",\
+"0.4655,0.4508,0.4372,0.4088,0.3590,0.2663,0.0817",\
+"0.4753,0.4606,0.4469,0.4186,0.3688,0.2760,0.0915",\
+"0.4818,0.4672,0.4535,0.4252,0.3754,0.2826,0.0980",\
+"0.5128,0.4981,0.4845,0.4561,0.4063,0.3136,0.1290",\
+"0.5688,0.5541,0.5405,0.5121,0.4623,0.3696,0.1850");
+		}
+	}
+}
+   pin(A_BIST_CLK)  {
+	   direction       : input;
+	   capacitance     : 0.00380014;
+	   max_transition  : "0.476";
+	   clock           : "true" ;
+	   pin_func_type   : active_rising ;
+
+	   timing () {
+		 timing_type : "min_pulse_width";
+		 related_pin : "A_BIST_CLK";
+		 rise_constraint("CLKTRAN_constraint_template") {
+		 index_1("0.0056,0.476");
+		 values("0.21,0.21");
+		 }
+	   }
+
+	   related_power_pin : VDD;
+	   related_ground_pin : VSS;
+
+	internal_power() {
+		when : "!A_BIST_MEN  & !A_BIST_WEN & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN  & A_BIST_WEN  & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (1.6932);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & A_BIST_WEN  & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (72.4898);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & A_BIST_WEN  & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (73.1657);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & !A_BIST_WEN & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (58.6440);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0.3446);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN & A_BIST_WEN  & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0.7709);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & !A_BIST_WEN & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	}
+   bus(A_BIST_DIN) {
+	   bus_type : D_15_0;
+	   direction       : input ;
+	   capacitance     : 0.00232602 ;
+	   memory_write() {
+		   address : A_BIST_ADDR ;
+		   clocked_on : A_BIST_CLK;
+	   }
+
+	   max_transition  : "0.476" ;
+	   pin(A_BIST_DIN[15:0]) {
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0486);
+		}
+		        fall_power("scalar"){
+		 values (0.0390);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0482);
+		}
+		        fall_power("scalar"){
+		 values (0.0381);
+		}
+	}
+	   }
+	   timing() {
+		 timing_type     : setup_rising;
+		 related_pin     : "A_BIST_CLK";
+		 when            : "(A_BIST_WEN & A_BIST_MEN)";
+		 sdf_cond        : "A_BIST_W_ACCESS";
+
+	  rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 values ("-0.3928,-0.3771,-0.3635,-0.3312,-0.2844,-0.1799,0.0115",\
+"-0.3978,-0.3821,-0.3685,-0.3362,-0.2894,-0.1849,0.0065",\
+"-0.4022,-0.3866,-0.3729,-0.3407,-0.2939,-0.1894,0.0020",\
+"-0.4120,-0.3964,-0.3827,-0.3505,-0.3036,-0.1991,-0.0077",\
+"-0.4186,-0.4029,-0.3893,-0.3570,-0.3102,-0.2057,-0.0143",\
+"-0.4495,-0.4339,-0.4203,-0.3880,-0.3411,-0.2367,-0.0453",\
+"-0.5056,-0.4899,-0.4762,-0.4440,-0.3971,-0.2927,-0.1012");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 values ("-0.3547,-0.3400,-0.3264,-0.2980,-0.2473,-0.1496,0.0330",\
+"-0.3597,-0.3450,-0.3314,-0.3030,-0.2523,-0.1546,0.0280",\
+"-0.3642,-0.3495,-0.3358,-0.3075,-0.2567,-0.1591,0.0235",\
+"-0.3739,-0.3593,-0.3456,-0.3173,-0.2665,-0.1688,0.0138",\
+"-0.3805,-0.3658,-0.3522,-0.3238,-0.2731,-0.1754,0.0072",\
+"-0.4115,-0.3968,-0.3831,-0.3548,-0.3040,-0.2064,-0.0238",\
+"-0.4675,-0.4528,-0.4391,-0.4108,-0.3600,-0.2624,-0.0798");
+		 }
+	   }
+
+	   timing() {
+		 timing_type     : hold_rising;
+		 related_pin     : "A_BIST_CLK";
+		 when            : "(A_BIST_WEN & A_BIST_MEN)";
+		 sdf_cond        : "A_BIST_W_ACCESS";
+
+	   rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 values ("0.5019,0.4853,0.4726,0.4404,0.3925,0.2890,0.0966",\
+"0.5069,0.4903,0.4776,0.4454,0.3975,0.2940,0.1016",\
+"0.5114,0.4948,0.4821,0.4499,0.4020,0.2985,0.1061",\
+"0.5211,0.5046,0.4919,0.4596,0.4118,0.3083,0.1159",\
+"0.5277,0.5111,0.4984,0.4662,0.4183,0.3148,0.1224",\
+"0.5587,0.5421,0.5294,0.4972,0.4493,0.3458,0.1534",\
+"0.6147,0.5981,0.5854,0.5532,0.5053,0.4018,0.2094");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 values ("0.4560,0.4414,0.4277,0.3994,0.3496,0.2568,0.0722",\
+"0.4610,0.4464,0.4327,0.4044,0.3546,0.2618,0.0772",\
+"0.4655,0.4508,0.4372,0.4088,0.3590,0.2663,0.0817",\
+"0.4753,0.4606,0.4469,0.4186,0.3688,0.2760,0.0915",\
+"0.4818,0.4672,0.4535,0.4252,0.3754,0.2826,0.0980",\
+"0.5128,0.4981,0.4845,0.4561,0.4063,0.3136,0.1290",\
+"0.5688,0.5541,0.5405,0.5121,0.4623,0.3696,0.1850");
+		 }
+	   }
+   }
+
+bus(A_DOUT) {
+
+	   bus_type : D_15_0;
+	   direction       : output ;
+	   capacitance     : 0 ;
+	   max_capacitance  : "6.4e-14" ;
+	   memory_read() {
+		  address : A_ADDR ;
+	   }
+	   pin(A_DOUT[15:0]) {
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+	   internal_power() {
+		  rise_power("scalar") {
+			 values (0);
+		  }
+		  fall_power("scalar") {
+			 values (0);
+		  }
+	   }
+	   }
+	   timing() {
+		 related_pin   : "A_CLK";
+		 timing_type   : rising_edge ;
+		 timing_sense  : non_unate ;
+
+	   cell_rise(SIG2SRAM_delay_template) {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("5.3293,5.3309,5.3386,5.3473,5.3797,5.4156",\
+"5.3405,5.3421,5.3498,5.3585,5.3909,5.4268",\
+"5.3392,5.3408,5.3484,5.3571,5.3896,5.4254",\
+"5.3522,5.3538,5.3615,5.3702,5.4026,5.4385",\
+"5.3600,5.3616,5.3693,5.3780,5.4104,5.4463",\
+"5.3926,5.3942,5.4018,5.4105,5.4430,5.4788",\
+"5.4465,5.4481,5.4558,5.4645,5.4969,5.5328");
+	   }
+	   cell_fall(SIG2SRAM_delay_template) {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("5.2683,5.2696,5.2756,5.2827,5.3092,5.3359",\
+"5.2794,5.2808,5.2868,5.2939,5.3204,5.3471",\
+"5.2781,5.2794,5.2854,5.2926,5.3191,5.3457",\
+"5.2912,5.2925,5.2985,5.3056,5.3321,5.3588",\
+"5.2989,5.3002,5.3062,5.3134,5.3399,5.3665",\
+"5.3315,5.3328,5.3388,5.3460,5.3725,5.3991",\
+"5.3854,5.3868,5.3928,5.3999,5.4264,5.4530");
+	   }
+
+	   rise_transition(SRAM_load_template) {
+		 index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("0.0326,0.0341,0.0428,0.0518,0.0923,0.1492");
+	   }
+	   fall_transition(SRAM_load_template) {
+		 index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("0.0254,0.0265,0.0335,0.0402,0.0707,0.1039");
+	   }
+	}
+}
+cell_leakage_power : 792.0620;
+}
+}
diff --git a/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_4096x8_c3_bm_bist_fast_1p32V_m55C.lib b/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_4096x8_c3_bm_bist_fast_1p32V_m55C.lib
new file mode 100644
index 00000000..4aff53a0
--- /dev/null
+++ b/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_4096x8_c3_bm_bist_fast_1p32V_m55C.lib
@@ -0,0 +1,1537 @@
+/* ------------------------------------------------------*/
+/**/
+/*		Copyright 2024 IHP PDK Authors*/
+/**/
+/*		Licensed under the Apache License, Version 2.0 (the "License");*/
+/*		you may not use this file except in compliance with the License.*/
+/*		You may obtain a copy of the License at*/
+/*		*/
+/*		   https://www.apache.org/licenses/LICENSE-2.0*/
+/*		*/
+/*		Unless required by applicable law or agreed to in writing, software*/
+/*		distributed under the License is distributed on an "AS IS" BASIS,*/
+/*		WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/
+/*		See the License for the specific language governing permissions and*/
+/*		limitations under the License.*/
+/*		*/
+/*		Generated on Fri Jul 19 08:59:21 2024		*/
+/*				*/
+/* ------------------------------------------------------ */
+library(RM_IHPSG13_1P_4096x8_c3_bm_bist_fast_1p32V_m55C) {	
+	technology (cmos) ;
+	delay_model : table_lookup ;
+	define ("add_pg_pin_to_lib",  "library",  "boolean");
+	add_pg_pin_to_lib : true;
+	voltage_map ( VDD, 1.32);
+	voltage_map ( VDDARRAY, 1.32);
+	voltage_map ( VSS, 0.000000 );
+	
+	date            : "Fri Jul 19 08:59:19 2024" ;
+	comment         : "IHP Microelectronics GmbH, 2024" ;
+	revision        : 1.0.0 ;
+	simulation      : true ;
+	nom_process     : 1 ;
+	nom_temperature : -55 ;
+	nom_voltage     : 1.32 ;
+	
+	operating_conditions("fast_1p32V_m55C"){
+	    process     : 1 ;
+	    temperature : -55 ;
+	    voltage     : 1.32 ;
+	    tree_type   : "balanced_tree" ;
+	}
+	
+	default_operating_conditions  : fast_1p32V_m55C ;
+	default_max_transition        : 1.0 ;
+	default_fanout_load           : 1.0 ;
+	default_inout_pin_cap         : 0.0 ;
+	default_input_pin_cap         : 0.0 ;
+	default_output_pin_cap        : 0.0 ;
+	default_cell_leakage_power    : 0.0 ;
+	default_leakage_power_density : 0.0 ;
+	 
+	slew_lower_threshold_pct_rise : 30 ;
+	slew_upper_threshold_pct_rise : 70 ;
+	input_threshold_pct_fall      : 50 ;
+	output_threshold_pct_fall     : 50 ;
+	input_threshold_pct_rise      : 50 ;
+	output_threshold_pct_rise     : 50 ;
+	slew_lower_threshold_pct_fall : 30 ;
+	slew_upper_threshold_pct_fall : 70 ;
+	slew_derate_from_library      : 0.5;
+	k_volt_cell_leakage_power     : 0.0 ;
+	k_temp_cell_leakage_power     : 0.0 ;
+	k_process_cell_leakage_power  : 0.0 ;
+	k_volt_internal_power         : 0.0 ;
+	k_temp_internal_power         : 0.0 ;
+	k_process_internal_power      : 0.0 ;
+	
+	capacitive_load_unit            (1,pf) ;
+	voltage_unit                  : "1V" ;
+	current_unit                  : "1uA" ;
+	time_unit                     : "1ns" ;
+	leakage_power_unit            : "1nW" ;
+	pulling_resistance_unit       : "1kohm";
+	/*
+	  ------------------------------------------------------------------------------------------
+	  implicit units overview:
+	    cell_area       unit      : "um"
+	    internal_power  unit      : "1e-12 * J/toggle = 1 * uW/MHz"
+	                                (capacitive_load_unit * voltage_unit^2) per toggle event
+	  ------------------------------------------------------------------------------------------
+	*/
+	library_features(report_delay_calculation);
+	define_cell_area (pad_drivers,pad_driver_sites) ;
+	
+	lu_table_template(CLKTRAN_constraint_template) {
+	     variable_1 : constrained_pin_transition;
+	     index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" );
+	}
+	lu_table_template(SRAM_load_template) {
+	     variable_1 : total_output_net_capacitance;
+	     index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" );
+	}
+	lu_table_template(SIG2SRAM_constraint_template) {
+	     variable_1 : related_pin_transition;
+	     variable_2 : constrained_pin_transition;
+	     index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" );
+	     index_2 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" );
+	}
+	
+	lu_table_template(SIG2SRAM_delay_template) {
+	     variable_1 : input_net_transition;
+	     variable_2 : total_output_net_capacitance;
+	     index_1 ( "0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800" );
+	     index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" );
+	} 
+
+	type (D_7_0) {
+		base_type : array;
+		data_type : bit;
+		bit_width : 8;
+		bit_from  : 7;
+		bit_to    : 0;
+		downto    : true;
+	 }
+
+	type (A_11_0) {
+		base_type : array;
+		data_type : bit;
+		bit_width : 12;
+		bit_from  : 11;
+		bit_to    : 0;
+		downto    : true;
+	 }
+
+cell(RM_IHPSG13_1P_4096x8_c3_bm_bist) {
+pg_pin (VDD) {
+  pg_type : primary_power;
+  voltage_name : VDD;
+}
+pg_pin (VDDARRAY) {
+  pg_type : primary_power;
+  voltage_name : VDDARRAY;
+}
+pg_pin (VSS) {
+  pg_type : primary_ground;
+  voltage_name : VSS;
+}
+
+memory() {
+ type : ram;
+ address_width : 12;
+ word_width : 8;
+}
+
+interface_timing : false;
+bus_naming_style    :   "%s[%d]" ;
+area        : 146413.44 ;
+
+   pin(A_DLY) {
+	   direction       : input ;
+	   capacitance     : 0.00421562 ;
+	   max_transition  : "1" ;
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+		internal_power() {
+		  rise_power("scalar") {
+			 values (0);
+		  }
+		  fall_power("scalar") {
+			 values (0);
+		  }
+	   }
+   }
+
+bus(A_ADDR) {
+   bus_type : A_11_0;
+   direction          : input ;
+   capacitance        : 0.00691085 ;
+    pin(A_ADDR[0]) {
+       capacitance : 0.00562034 ;
+    }
+    pin(A_ADDR[1]) {
+       capacitance : 0.00462655 ;
+    }
+    pin(A_ADDR[2]) {
+       capacitance : 0.00594295 ;
+    }
+    pin(A_ADDR[3]) {
+       capacitance : 0.00723434 ;
+    }
+    pin(A_ADDR[4]) {
+       capacitance : 0.00481603 ;
+    }
+    pin(A_ADDR[5]) {
+       capacitance : 0.00868123 ;
+    }
+    pin(A_ADDR[6]) {
+       capacitance : 0.010187 ;
+    }
+    pin(A_ADDR[7]) {
+       capacitance : 0.00734489 ;
+    }
+    pin(A_ADDR[8]) {
+       capacitance : 0.00904175 ;
+    }
+    pin(A_ADDR[9]) {
+       capacitance : 0.0074973 ;
+    }
+    pin(A_ADDR[10]) {
+       capacitance : 0.00825659 ;
+    }
+   max_transition     : "0.38" ;
+   pin(A_ADDR[11:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0093);
+		}
+		        fall_power("scalar"){
+		 values (0.0011);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0215);
+		}
+		        fall_power("scalar"){
+		 values (0.0018);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "((A_WEN | A_REN)& A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\
+"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\
+"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\
+"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\
+"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\
+"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\
+"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\
+"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\
+"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\
+"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\
+"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\
+"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\
+"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "((A_WEN | A_REN)& A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\
+"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\
+"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\
+"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\
+"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\
+"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\
+"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\
+"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\
+"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\
+"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\
+"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\
+"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\
+"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902");
+		}
+	}
+}
+pin(A_WEN) {
+   direction          : input ;
+   capacitance        : 0.00341384 ;
+   max_transition     : "0.38" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0072);
+		}
+		        fall_power("scalar"){
+		 values (0.0165);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0048);
+		}
+		        fall_power("scalar"){
+		 values (0.0225);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\
+"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\
+"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\
+"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\
+"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\
+"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\
+"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\
+"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\
+"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\
+"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\
+"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\
+"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\
+"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\
+"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\
+"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\
+"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\
+"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\
+"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\
+"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\
+"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\
+"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\
+"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\
+"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\
+"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\
+"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691");
+		}
+	}
+	}
+pin(A_REN) {
+   direction          : input ;
+   capacitance        : 0.00390661 ;
+   max_transition     : "0.38" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0093);
+		}
+		        fall_power("scalar"){
+		 values (0.0121);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0244);
+		}
+		        fall_power("scalar"){
+		 values (0.0205);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\
+"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\
+"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\
+"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\
+"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\
+"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\
+"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\
+"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\
+"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\
+"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\
+"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\
+"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\
+"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\
+"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\
+"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\
+"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\
+"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\
+"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\
+"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\
+"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\
+"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\
+"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\
+"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\
+"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\
+"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809");
+		}
+	}
+	}
+pin(A_MEN) {
+   direction          : input ;
+   capacitance        : 0.00326046 ;
+   max_transition     : "0.38" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		        rise_power("scalar"){
+		 values (0.0754);
+		}
+		        fall_power("scalar"){
+		 values (0.0123);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\
+"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\
+"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\
+"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\
+"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\
+"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\
+"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\
+"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\
+"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\
+"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\
+"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\
+"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\
+"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\
+"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\
+"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\
+"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\
+"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\
+"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\
+"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\
+"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\
+"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\
+"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\
+"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\
+"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\
+"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691");
+		}
+	}
+	}
+bus(A_BM) {
+   bus_type : D_7_0;
+   direction          : input ;
+   capacitance        : 0.00318267 ;
+   max_transition     : "0.38" ;
+   pin(A_BM[7:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0378);
+		}
+		        fall_power("scalar"){
+		 values (0.0440);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0522);
+		}
+		        fall_power("scalar"){
+		 values (0.0514);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "(A_WEN & A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.1741,-0.1633,-0.1477,-0.1223,-0.0813,-0.0080,0.1267",\
+"-0.1779,-0.1672,-0.1516,-0.1262,-0.0852,-0.0119,0.1228",\
+"-0.1818,-0.1711,-0.1555,-0.1301,-0.0891,-0.0158,0.1189",\
+"-0.1850,-0.1742,-0.1586,-0.1332,-0.0922,-0.0190,0.1158",\
+"-0.1974,-0.1867,-0.1711,-0.1457,-0.1047,-0.0314,0.1033",\
+"-0.2149,-0.2041,-0.1885,-0.1631,-0.1221,-0.0489,0.0859",\
+"-0.2425,-0.2318,-0.2162,-0.1908,-0.1498,-0.0765,0.0582");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.1506,-0.1389,-0.1262,-0.0989,-0.0617,0.0115,0.1394",\
+"-0.1545,-0.1428,-0.1301,-0.1027,-0.0656,0.0076,0.1355",\
+"-0.1584,-0.1467,-0.1340,-0.1067,-0.0695,0.0037,0.1316",\
+"-0.1615,-0.1498,-0.1371,-0.1098,-0.0727,0.0006,0.1285",\
+"-0.1740,-0.1623,-0.1496,-0.1222,-0.0851,-0.0119,0.1160",\
+"-0.1915,-0.1797,-0.1670,-0.1397,-0.1026,-0.0293,0.0986",\
+"-0.2191,-0.2074,-0.1947,-0.1673,-0.1302,-0.0570,0.0709");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "(A_WEN & A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2790,0.2693,0.2536,0.2273,0.1902,0.1160,-0.0188",\
+"0.2829,0.2732,0.2575,0.2312,0.1941,0.1198,-0.0149",\
+"0.2868,0.2771,0.2614,0.2351,0.1980,0.1237,-0.0110",\
+"0.2900,0.2802,0.2646,0.2382,0.2011,0.1269,-0.0079",\
+"0.3024,0.2926,0.2770,0.2507,0.2135,0.1393,0.0046",\
+"0.3199,0.3101,0.2945,0.2681,0.2310,0.1568,0.0220",\
+"0.3475,0.3378,0.3221,0.2958,0.2587,0.1845,0.0497");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2507,0.2400,0.2263,0.1990,0.1628,0.0906,-0.0393",\
+"0.2546,0.2439,0.2302,0.2028,0.1667,0.0944,-0.0354",\
+"0.2585,0.2478,0.2341,0.2068,0.1706,0.0984,-0.0315",\
+"0.2617,0.2509,0.2372,0.2099,0.1738,0.1015,-0.0284",\
+"0.2741,0.2633,0.2497,0.2223,0.1862,0.1139,-0.0159",\
+"0.2916,0.2808,0.2671,0.2398,0.2037,0.1314,0.0015",\
+"0.3192,0.3085,0.2948,0.2675,0.2313,0.1591,0.0292");
+		}
+	}
+}
+   pin(A_CLK)  {
+	   direction       : input;
+	   capacitance     : 0.00389386;
+	   max_transition  : "0.38";
+	   clock           : "true" ;
+	   pin_func_type   : active_rising ;
+
+	   timing () {
+		 timing_type : "min_pulse_width";
+		 related_pin : "A_CLK";
+		 rise_constraint("CLKTRAN_constraint_template") {
+		 index_1("0.004,0.38");
+		 values("0.12,0.12");
+		 }
+	   }
+
+	   related_power_pin : VDD;
+	   related_ground_pin : VSS;
+
+	internal_power() {
+		when : "!A_MEN  & !A_WEN & !A_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN  & A_WEN  & !A_REN";
+		        rise_power("scalar"){
+		 values (0.8242);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & A_WEN  & !A_REN";
+		        rise_power("scalar"){
+		 values (53.0853);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & A_WEN  & A_REN";
+		        rise_power("scalar"){
+		 values (50.8144);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & !A_WEN & A_REN";
+		        rise_power("scalar"){
+		 values (42.3390);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN & !A_WEN & A_REN";
+		        rise_power("scalar"){
+		 values (0.4507);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN & A_WEN  & A_REN";
+		        rise_power("scalar"){
+		 values (0.7118);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & !A_WEN & !A_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	}
+   bus(A_DIN) {
+	   bus_type : D_7_0;
+	   direction       : input ;
+	   capacitance     : 0.00332733 ;
+	   memory_write() {
+		   address : A_ADDR ;
+		   clocked_on : A_CLK;
+	   }
+
+	   max_transition  : "0.38" ;
+	   pin(A_DIN[7:0]) {
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0378);
+		}
+		        fall_power("scalar"){
+		 values (0.0440);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0522);
+		}
+		        fall_power("scalar"){
+		 values (0.0514);
+		}
+	}
+	   }
+	   timing() {
+		 timing_type     : setup_rising;
+		 related_pin     : "A_CLK";
+		 when            : "(A_WEN & A_MEN)";
+		 sdf_cond        : "A_W_ACCESS";
+
+	  rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 values ("-0.1741,-0.1633,-0.1477,-0.1223,-0.0813,-0.0080,0.1267",\
+"-0.1779,-0.1672,-0.1516,-0.1262,-0.0852,-0.0119,0.1228",\
+"-0.1818,-0.1711,-0.1555,-0.1301,-0.0891,-0.0158,0.1189",\
+"-0.1850,-0.1742,-0.1586,-0.1332,-0.0922,-0.0190,0.1158",\
+"-0.1974,-0.1867,-0.1711,-0.1457,-0.1047,-0.0314,0.1033",\
+"-0.2149,-0.2041,-0.1885,-0.1631,-0.1221,-0.0489,0.0859",\
+"-0.2425,-0.2318,-0.2162,-0.1908,-0.1498,-0.0765,0.0582");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 values ("-0.1506,-0.1389,-0.1262,-0.0989,-0.0617,0.0115,0.1394",\
+"-0.1545,-0.1428,-0.1301,-0.1027,-0.0656,0.0076,0.1355",\
+"-0.1584,-0.1467,-0.1340,-0.1067,-0.0695,0.0037,0.1316",\
+"-0.1615,-0.1498,-0.1371,-0.1098,-0.0727,0.0006,0.1285",\
+"-0.1740,-0.1623,-0.1496,-0.1222,-0.0851,-0.0119,0.1160",\
+"-0.1915,-0.1797,-0.1670,-0.1397,-0.1026,-0.0293,0.0986",\
+"-0.2191,-0.2074,-0.1947,-0.1673,-0.1302,-0.0570,0.0709");
+		 }
+	   }
+
+	   timing() {
+		 timing_type     : hold_rising;
+		 related_pin     : "A_CLK";
+		 when            : "(A_WEN & A_MEN)";
+		 sdf_cond        : "A_W_ACCESS";
+
+	   rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 values ("0.2790,0.2693,0.2536,0.2273,0.1902,0.1160,-0.0188",\
+"0.2829,0.2732,0.2575,0.2312,0.1941,0.1198,-0.0149",\
+"0.2868,0.2771,0.2614,0.2351,0.1980,0.1237,-0.0110",\
+"0.2900,0.2802,0.2646,0.2382,0.2011,0.1269,-0.0079",\
+"0.3024,0.2926,0.2770,0.2507,0.2135,0.1393,0.0046",\
+"0.3199,0.3101,0.2945,0.2681,0.2310,0.1568,0.0220",\
+"0.3475,0.3378,0.3221,0.2958,0.2587,0.1845,0.0497");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 values ("0.2507,0.2400,0.2263,0.1990,0.1628,0.0906,-0.0393",\
+"0.2546,0.2439,0.2302,0.2028,0.1667,0.0944,-0.0354",\
+"0.2585,0.2478,0.2341,0.2068,0.1706,0.0984,-0.0315",\
+"0.2617,0.2509,0.2372,0.2099,0.1738,0.1015,-0.0284",\
+"0.2741,0.2633,0.2497,0.2223,0.1862,0.1139,-0.0159",\
+"0.2916,0.2808,0.2671,0.2398,0.2037,0.1314,0.0015",\
+"0.3192,0.3085,0.2948,0.2675,0.2313,0.1591,0.0292");
+		 }
+	   }
+   }
+
+   pin(A_BIST_EN) {
+	   direction       : input ;
+	   capacitance     : 0.00421562 ;
+	   max_transition  : "1" ;
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+		internal_power() {
+		  rise_power("scalar") {
+			 values (0);
+		  }
+		  fall_power("scalar") {
+			 values (0);
+		  }
+	   }
+   }
+
+bus(A_BIST_ADDR) {
+   bus_type : A_11_0;
+   direction          : input ;
+   capacitance        : 0.00691085 ;
+    pin(A_BIST_ADDR[0]) {
+       capacitance : 0.00562034 ;
+    }
+    pin(A_BIST_ADDR[1]) {
+       capacitance : 0.00462655 ;
+    }
+    pin(A_BIST_ADDR[2]) {
+       capacitance : 0.00594295 ;
+    }
+    pin(A_BIST_ADDR[3]) {
+       capacitance : 0.00723434 ;
+    }
+    pin(A_BIST_ADDR[4]) {
+       capacitance : 0.00481603 ;
+    }
+    pin(A_BIST_ADDR[5]) {
+       capacitance : 0.00868123 ;
+    }
+    pin(A_BIST_ADDR[6]) {
+       capacitance : 0.010187 ;
+    }
+    pin(A_BIST_ADDR[7]) {
+       capacitance : 0.00734489 ;
+    }
+    pin(A_BIST_ADDR[8]) {
+       capacitance : 0.00904175 ;
+    }
+    pin(A_BIST_ADDR[9]) {
+       capacitance : 0.0074973 ;
+    }
+    pin(A_BIST_ADDR[10]) {
+       capacitance : 0.00825659 ;
+    }
+   max_transition     : "0.38" ;
+   pin(A_BIST_ADDR[11:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0093);
+		}
+		        fall_power("scalar"){
+		 values (0.0011);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0215);
+		}
+		        fall_power("scalar"){
+		 values (0.0018);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.2371,-0.2215,-0.2098,-0.1824,-0.1434,-0.0691,0.0676",\
+"-0.2449,-0.2332,-0.2176,-0.1902,-0.1551,-0.0770,0.0559",\
+"-0.2605,-0.2488,-0.2332,-0.2059,-0.1707,-0.0965,0.0441",\
+"-0.2879,-0.2723,-0.2605,-0.2332,-0.1941,-0.1199,0.0168",\
+"-0.3230,-0.3113,-0.2996,-0.2723,-0.2332,-0.1590,-0.0184",\
+"-0.4012,-0.3895,-0.3738,-0.3465,-0.3074,-0.2332,-0.0965",\
+"-0.5379,-0.5262,-0.5105,-0.4832,-0.4480,-0.3699,-0.2332");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.1785,-0.1707,-0.1551,-0.1277,-0.0887,-0.0184,0.1145",\
+"-0.1902,-0.1785,-0.1629,-0.1355,-0.1004,-0.0262,0.1027",\
+"-0.2059,-0.1941,-0.1785,-0.1512,-0.1160,-0.0418,0.0871",\
+"-0.2293,-0.2176,-0.2059,-0.1785,-0.1434,-0.0691,0.0598",\
+"-0.2684,-0.2566,-0.2449,-0.2176,-0.1824,-0.1082,0.0207",\
+"-0.3465,-0.3348,-0.3191,-0.2918,-0.2566,-0.1824,-0.0535",\
+"-0.4832,-0.4715,-0.4559,-0.4324,-0.3934,-0.3191,-0.1902");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.3410,0.3293,0.3137,0.2863,0.2473,0.1730,0.0324",\
+"0.3488,0.3371,0.3215,0.2941,0.2590,0.1809,0.0480",\
+"0.3684,0.3527,0.3371,0.3098,0.2746,0.1965,0.0598",\
+"0.3918,0.3762,0.3645,0.3371,0.2980,0.2238,0.0871",\
+"0.4309,0.4152,0.4035,0.3762,0.3371,0.2629,0.1223",\
+"0.5051,0.4934,0.4777,0.4504,0.4113,0.3371,0.1965",\
+"0.6418,0.6262,0.6145,0.5871,0.5520,0.4738,0.3332");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2824,0.2707,0.2551,0.2277,0.1926,0.1184,-0.0105",\
+"0.2902,0.2785,0.2668,0.2395,0.2043,0.1301,0.0012",\
+"0.3059,0.2941,0.2824,0.2551,0.2199,0.1457,0.0168",\
+"0.3332,0.3215,0.3059,0.2785,0.2434,0.1691,0.0402",\
+"0.3723,0.3605,0.3449,0.3176,0.2824,0.2121,0.0793",\
+"0.4465,0.4348,0.4230,0.3918,0.3566,0.2824,0.1535",\
+"0.5832,0.5715,0.5598,0.5324,0.4934,0.4191,0.2902");
+		}
+	}
+}
+pin(A_BIST_WEN) {
+   direction          : input ;
+   capacitance        : 0.00341384 ;
+   max_transition     : "0.38" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0072);
+		}
+		        fall_power("scalar"){
+		 values (0.0165);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0048);
+		}
+		        fall_power("scalar"){
+		 values (0.0225);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1418,0.1496,0.1652,0.1887,0.2316,0.3059,0.4465",\
+"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\
+"0.1145,0.1262,0.1379,0.1652,0.2043,0.2785,0.4191",\
+"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\
+"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3527",\
+"-0.0262,-0.0145,0.0012,0.0246,0.0676,0.1379,0.2785",\
+"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1418");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2082,0.2160,0.2316,0.2590,0.2941,0.3684,0.5012",\
+"0.1926,0.2043,0.2199,0.2473,0.2824,0.3566,0.4895",\
+"0.1770,0.1887,0.2043,0.2316,0.2668,0.3410,0.4777",\
+"0.1535,0.1652,0.1770,0.2043,0.2395,0.3137,0.4504",\
+"0.1145,0.1262,0.1379,0.1652,0.2043,0.2746,0.4113",\
+"0.0402,0.0520,0.0676,0.0910,0.1262,0.2004,0.3332",\
+"-0.0965,-0.0848,-0.0730,-0.0457,-0.0066,0.0637,0.2004");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1770,0.1652,0.1496,0.1223,0.0793,0.0090,-0.1316",\
+"0.1848,0.1730,0.1574,0.1301,0.0910,0.0168,-0.1199",\
+"0.2004,0.1887,0.1770,0.1496,0.1066,0.0363,-0.1043",\
+"0.2277,0.2160,0.2004,0.1730,0.1340,0.0598,-0.0809",\
+"0.2668,0.2551,0.2395,0.2121,0.1730,0.0988,-0.0418",\
+"0.3410,0.3293,0.3137,0.2863,0.2434,0.1730,0.0324",\
+"0.4816,0.4699,0.4543,0.4230,0.3801,0.3098,0.1730");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1613,0.1496,0.1379,0.1066,0.0715,0.0012,-0.1355",\
+"0.1730,0.1613,0.1457,0.1184,0.0832,0.0129,-0.1238",\
+"0.1887,0.1770,0.1613,0.1340,0.0988,0.0246,-0.1121",\
+"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\
+"0.2512,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0457",\
+"0.3254,0.3176,0.3020,0.2746,0.2355,0.1652,0.0324",\
+"0.4660,0.4543,0.4387,0.4113,0.3723,0.3020,0.1691");
+		}
+	}
+	}
+pin(A_BIST_REN) {
+   direction          : input ;
+   capacitance        : 0.00390661 ;
+   max_transition     : "0.38" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0093);
+		}
+		        fall_power("scalar"){
+		 values (0.0121);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0244);
+		}
+		        fall_power("scalar"){
+		 values (0.0205);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.0027,0.0090,0.0246,0.0520,0.0910,0.1613,0.3020",\
+"-0.0105,0.0012,0.0129,0.0363,0.0793,0.1535,0.2902",\
+"-0.0262,-0.0145,-0.0027,0.0246,0.0637,0.1379,0.2785",\
+"-0.0535,-0.0418,-0.0262,0.0012,0.0363,0.1105,0.2512",\
+"-0.0926,-0.0809,-0.0652,-0.0418,-0.0027,0.0715,0.2121",\
+"-0.1668,-0.1551,-0.1395,-0.1082,-0.0770,-0.0027,0.1379",\
+"-0.3035,-0.2918,-0.2762,-0.2488,-0.2137,-0.1434,-0.0027");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.0832,0.0949,0.1105,0.1379,0.1730,0.2473,0.3801",\
+"0.0754,0.0832,0.0988,0.1223,0.1613,0.2355,0.3684",\
+"0.0598,0.0676,0.0832,0.1066,0.1457,0.2121,0.3527",\
+"0.0324,0.0441,0.0598,0.0871,0.1223,0.1926,0.3293",\
+"-0.0066,0.0051,0.0168,0.0480,0.0832,0.1535,0.2902",\
+"-0.0809,-0.0691,-0.0574,-0.0301,0.0090,0.0832,0.2121",\
+"-0.2176,-0.2059,-0.1941,-0.1668,-0.1277,-0.0574,0.0793");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1160",\
+"0.1965,0.1848,0.1730,0.1457,0.1027,0.0324,-0.1082",\
+"0.2160,0.2004,0.1887,0.1613,0.1184,0.0480,-0.0926",\
+"0.2395,0.2277,0.2121,0.1848,0.1457,0.0715,-0.0652",\
+"0.2785,0.2668,0.2512,0.2238,0.1848,0.1105,-0.0262",\
+"0.3527,0.3410,0.3254,0.2980,0.2551,0.1848,0.0480",\
+"0.4934,0.4816,0.4660,0.4387,0.3957,0.3254,0.1887");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1730,0.1613,0.1496,0.1184,0.0793,0.0129,-0.1238",\
+"0.1848,0.1730,0.1574,0.1301,0.0910,0.0207,-0.1121",\
+"0.2004,0.1887,0.1730,0.1457,0.1066,0.0363,-0.1004",\
+"0.2238,0.2121,0.2004,0.1691,0.1340,0.0598,-0.0730",\
+"0.2629,0.2512,0.2395,0.2121,0.1691,0.0988,-0.0340",\
+"0.3371,0.3254,0.3137,0.2863,0.2434,0.1730,0.0402",\
+"0.4777,0.4660,0.4504,0.4230,0.3840,0.3137,0.1809");
+		}
+	}
+	}
+pin(A_BIST_MEN) {
+   direction          : input ;
+   capacitance        : 0.00326046 ;
+   max_transition     : "0.38" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		        rise_power("scalar"){
+		 values (0.0754);
+		}
+		        fall_power("scalar"){
+		 values (0.0123);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1418,0.1496,0.1652,0.1926,0.2316,0.3059,0.4465",\
+"0.1301,0.1379,0.1535,0.1809,0.2199,0.2941,0.4348",\
+"0.1145,0.1262,0.1418,0.1652,0.2043,0.2785,0.4191",\
+"0.0871,0.0949,0.1105,0.1379,0.1770,0.2512,0.3879",\
+"0.0480,0.0598,0.0754,0.0988,0.1379,0.2082,0.3488",\
+"-0.0262,-0.0145,0.0012,0.0285,0.0676,0.1379,0.2785",\
+"-0.1668,-0.1551,-0.1395,-0.1121,-0.0730,0.0012,0.1379");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2082,0.2199,0.2316,0.2590,0.2980,0.3723,0.5051",\
+"0.1965,0.2082,0.2199,0.2473,0.2863,0.3605,0.4934",\
+"0.1809,0.1926,0.2043,0.2316,0.2707,0.3449,0.4777",\
+"0.1574,0.1691,0.1809,0.2082,0.2434,0.3176,0.4543",\
+"0.1145,0.1262,0.1418,0.1691,0.2043,0.2785,0.4113",\
+"0.0441,0.0559,0.0676,0.0949,0.1301,0.2004,0.3332",\
+"-0.0965,-0.0848,-0.0691,-0.0418,-0.0066,0.0676,0.2004");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1770,0.1652,0.1535,0.1262,0.0832,0.0129,-0.1277",\
+"0.1887,0.1770,0.1613,0.1340,0.0949,0.0207,-0.1199",\
+"0.2043,0.1926,0.1770,0.1496,0.1105,0.0363,-0.1043",\
+"0.2277,0.2160,0.2043,0.1770,0.1379,0.0598,-0.0770",\
+"0.2668,0.2551,0.2434,0.2160,0.1730,0.0988,-0.0379",\
+"0.3449,0.3332,0.3176,0.2902,0.2473,0.1730,0.0363",\
+"0.4816,0.4699,0.4543,0.4270,0.3840,0.3098,0.1770");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.1613,0.1496,0.1379,0.1105,0.0715,0.0012,-0.1355",\
+"0.1730,0.1613,0.1496,0.1184,0.0832,0.0129,-0.1238",\
+"0.1887,0.1770,0.1652,0.1340,0.0988,0.0285,-0.1121",\
+"0.2121,0.2043,0.1887,0.1613,0.1223,0.0520,-0.0848",\
+"0.2551,0.2434,0.2277,0.2004,0.1613,0.0910,-0.0418",\
+"0.3293,0.3176,0.3020,0.2746,0.2395,0.1652,0.0324",\
+"0.4660,0.4543,0.4426,0.4113,0.3762,0.3020,0.1691");
+		}
+	}
+	}
+bus(A_BIST_BM) {
+   bus_type : D_7_0;
+   direction          : input ;
+   capacitance        : 0.00252172 ;
+   max_transition     : "0.38" ;
+   pin(A_BIST_BM[7:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0378);
+		}
+		        fall_power("scalar"){
+		 values (0.0440);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0522);
+		}
+		        fall_power("scalar"){
+		 values (0.0514);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "(A_BIST_WEN & A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.1741,-0.1633,-0.1477,-0.1223,-0.0813,-0.0080,0.1267",\
+"-0.1779,-0.1672,-0.1516,-0.1262,-0.0852,-0.0119,0.1228",\
+"-0.1818,-0.1711,-0.1555,-0.1301,-0.0891,-0.0158,0.1189",\
+"-0.1850,-0.1742,-0.1586,-0.1332,-0.0922,-0.0190,0.1158",\
+"-0.1974,-0.1867,-0.1711,-0.1457,-0.1047,-0.0314,0.1033",\
+"-0.2149,-0.2041,-0.1885,-0.1631,-0.1221,-0.0489,0.0859",\
+"-0.2425,-0.2318,-0.2162,-0.1908,-0.1498,-0.0765,0.0582");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("-0.1506,-0.1389,-0.1262,-0.0989,-0.0617,0.0115,0.1394",\
+"-0.1545,-0.1428,-0.1301,-0.1027,-0.0656,0.0076,0.1355",\
+"-0.1584,-0.1467,-0.1340,-0.1067,-0.0695,0.0037,0.1316",\
+"-0.1615,-0.1498,-0.1371,-0.1098,-0.0727,0.0006,0.1285",\
+"-0.1740,-0.1623,-0.1496,-0.1222,-0.0851,-0.0119,0.1160",\
+"-0.1915,-0.1797,-0.1670,-0.1397,-0.1026,-0.0293,0.0986",\
+"-0.2191,-0.2074,-0.1947,-0.1673,-0.1302,-0.0570,0.0709");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "(A_BIST_WEN & A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2790,0.2693,0.2536,0.2273,0.1902,0.1160,-0.0188",\
+"0.2829,0.2732,0.2575,0.2312,0.1941,0.1198,-0.0149",\
+"0.2868,0.2771,0.2614,0.2351,0.1980,0.1237,-0.0110",\
+"0.2900,0.2802,0.2646,0.2382,0.2011,0.1269,-0.0079",\
+"0.3024,0.2926,0.2770,0.2507,0.2135,0.1393,0.0046",\
+"0.3199,0.3101,0.2945,0.2681,0.2310,0.1568,0.0220",\
+"0.3475,0.3378,0.3221,0.2958,0.2587,0.1845,0.0497");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		values ("0.2507,0.2400,0.2263,0.1990,0.1628,0.0906,-0.0393",\
+"0.2546,0.2439,0.2302,0.2028,0.1667,0.0944,-0.0354",\
+"0.2585,0.2478,0.2341,0.2068,0.1706,0.0984,-0.0315",\
+"0.2617,0.2509,0.2372,0.2099,0.1738,0.1015,-0.0284",\
+"0.2741,0.2633,0.2497,0.2223,0.1862,0.1139,-0.0159",\
+"0.2916,0.2808,0.2671,0.2398,0.2037,0.1314,0.0015",\
+"0.3192,0.3085,0.2948,0.2675,0.2313,0.1591,0.0292");
+		}
+	}
+}
+   pin(A_BIST_CLK)  {
+	   direction       : input;
+	   capacitance     : 0.00389386;
+	   max_transition  : "0.38";
+	   clock           : "true" ;
+	   pin_func_type   : active_rising ;
+
+	   timing () {
+		 timing_type : "min_pulse_width";
+		 related_pin : "A_BIST_CLK";
+		 rise_constraint("CLKTRAN_constraint_template") {
+		 index_1("0.004,0.38");
+		 values("0.12,0.12");
+		 }
+	   }
+
+	   related_power_pin : VDD;
+	   related_ground_pin : VSS;
+
+	internal_power() {
+		when : "!A_BIST_MEN  & !A_BIST_WEN & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN  & A_BIST_WEN  & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0.8242);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & A_BIST_WEN  & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (53.0853);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & A_BIST_WEN  & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (50.8144);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & !A_BIST_WEN & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (42.3390);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0.4507);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN & A_BIST_WEN  & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0.7118);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & !A_BIST_WEN & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	}
+   bus(A_BIST_DIN) {
+	   bus_type : D_7_0;
+	   direction       : input ;
+	   capacitance     : 0.00252023 ;
+	   memory_write() {
+		   address : A_BIST_ADDR ;
+		   clocked_on : A_BIST_CLK;
+	   }
+
+	   max_transition  : "0.38" ;
+	   pin(A_BIST_DIN[7:0]) {
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0378);
+		}
+		        fall_power("scalar"){
+		 values (0.0440);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0522);
+		}
+		        fall_power("scalar"){
+		 values (0.0514);
+		}
+	}
+	   }
+	   timing() {
+		 timing_type     : setup_rising;
+		 related_pin     : "A_BIST_CLK";
+		 when            : "(A_BIST_WEN & A_BIST_MEN)";
+		 sdf_cond        : "A_BIST_W_ACCESS";
+
+	  rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 values ("-0.1741,-0.1633,-0.1477,-0.1223,-0.0813,-0.0080,0.1267",\
+"-0.1779,-0.1672,-0.1516,-0.1262,-0.0852,-0.0119,0.1228",\
+"-0.1818,-0.1711,-0.1555,-0.1301,-0.0891,-0.0158,0.1189",\
+"-0.1850,-0.1742,-0.1586,-0.1332,-0.0922,-0.0190,0.1158",\
+"-0.1974,-0.1867,-0.1711,-0.1457,-0.1047,-0.0314,0.1033",\
+"-0.2149,-0.2041,-0.1885,-0.1631,-0.1221,-0.0489,0.0859",\
+"-0.2425,-0.2318,-0.2162,-0.1908,-0.1498,-0.0765,0.0582");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 values ("-0.1506,-0.1389,-0.1262,-0.0989,-0.0617,0.0115,0.1394",\
+"-0.1545,-0.1428,-0.1301,-0.1027,-0.0656,0.0076,0.1355",\
+"-0.1584,-0.1467,-0.1340,-0.1067,-0.0695,0.0037,0.1316",\
+"-0.1615,-0.1498,-0.1371,-0.1098,-0.0727,0.0006,0.1285",\
+"-0.1740,-0.1623,-0.1496,-0.1222,-0.0851,-0.0119,0.1160",\
+"-0.1915,-0.1797,-0.1670,-0.1397,-0.1026,-0.0293,0.0986",\
+"-0.2191,-0.2074,-0.1947,-0.1673,-0.1302,-0.0570,0.0709");
+		 }
+	   }
+
+	   timing() {
+		 timing_type     : hold_rising;
+		 related_pin     : "A_BIST_CLK";
+		 when            : "(A_BIST_WEN & A_BIST_MEN)";
+		 sdf_cond        : "A_BIST_W_ACCESS";
+
+	   rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 values ("0.2790,0.2693,0.2536,0.2273,0.1902,0.1160,-0.0188",\
+"0.2829,0.2732,0.2575,0.2312,0.1941,0.1198,-0.0149",\
+"0.2868,0.2771,0.2614,0.2351,0.1980,0.1237,-0.0110",\
+"0.2900,0.2802,0.2646,0.2382,0.2011,0.1269,-0.0079",\
+"0.3024,0.2926,0.2770,0.2507,0.2135,0.1393,0.0046",\
+"0.3199,0.3101,0.2945,0.2681,0.2310,0.1568,0.0220",\
+"0.3475,0.3378,0.3221,0.2958,0.2587,0.1845,0.0497");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 values ("0.2507,0.2400,0.2263,0.1990,0.1628,0.0906,-0.0393",\
+"0.2546,0.2439,0.2302,0.2028,0.1667,0.0944,-0.0354",\
+"0.2585,0.2478,0.2341,0.2068,0.1706,0.0984,-0.0315",\
+"0.2617,0.2509,0.2372,0.2099,0.1738,0.1015,-0.0284",\
+"0.2741,0.2633,0.2497,0.2223,0.1862,0.1139,-0.0159",\
+"0.2916,0.2808,0.2671,0.2398,0.2037,0.1314,0.0015",\
+"0.3192,0.3085,0.2948,0.2675,0.2313,0.1591,0.0292");
+		 }
+	   }
+   }
+
+bus(A_DOUT) {
+
+	   bus_type : D_7_0;
+	   direction       : output ;
+	   capacitance     : 0 ;
+	   max_capacitance  : "6.4e-14" ;
+	   memory_read() {
+		  address : A_ADDR ;
+	   }
+	   pin(A_DOUT[7:0]) {
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+	   internal_power() {
+		  rise_power("scalar") {
+			 values (0);
+		  }
+		  fall_power("scalar") {
+			 values (0);
+		  }
+	   }
+	   }
+	   timing() {
+		 related_pin   : "A_CLK";
+		 timing_type   : rising_edge ;
+		 timing_sense  : non_unate ;
+
+	   cell_rise(SIG2SRAM_delay_template) {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("3.2551,3.2561,3.2609,3.2664,3.2873,3.3108",\
+"3.2615,3.2625,3.2673,3.2729,3.2938,3.3173",\
+"3.2655,3.2665,3.2713,3.2768,3.2977,3.3212",\
+"3.2688,3.2698,3.2746,3.2801,3.3010,3.3245",\
+"3.2774,3.2784,3.2832,3.2888,3.3097,3.3332",\
+"3.2995,3.3005,3.3054,3.3109,3.3318,3.3553",\
+"3.3250,3.3260,3.3308,3.3364,3.3573,3.3808");
+	   }
+	   cell_fall(SIG2SRAM_delay_template) {
+		 index_1("0.0040,0.0176,0.0344,0.0656,0.1120,0.2016,0.3800");
+		 index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("3.2208,3.2216,3.2257,3.2302,3.2473,3.2640",\
+"3.2272,3.2281,3.2321,3.2367,3.2538,3.2705",\
+"3.2312,3.2320,3.2361,3.2406,3.2577,3.2744",\
+"3.2345,3.2353,3.2394,3.2439,3.2610,3.2777",\
+"3.2431,3.2440,3.2480,3.2526,3.2697,3.2864",\
+"3.2652,3.2661,3.2701,3.2747,3.2918,3.3085",\
+"3.2907,3.2916,3.2956,3.3002,3.3173,3.3340");
+	   }
+
+	   rise_transition(SRAM_load_template) {
+		 index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("0.0206,0.0210,0.0265,0.0323,0.0606,0.0955");
+	   }
+	   fall_transition(SRAM_load_template) {
+		 index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("0.0170,0.0177,0.0222,0.0270,0.0451,0.0644");
+	   }
+	}
+}
+cell_leakage_power : 939.1882;
+}
+}
diff --git a/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_4096x8_c3_bm_bist_slow_1p08V_125C.lib b/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_4096x8_c3_bm_bist_slow_1p08V_125C.lib
new file mode 100644
index 00000000..236e4866
--- /dev/null
+++ b/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_4096x8_c3_bm_bist_slow_1p08V_125C.lib
@@ -0,0 +1,1537 @@
+/* ------------------------------------------------------*/
+/**/
+/*		Copyright 2024 IHP PDK Authors*/
+/**/
+/*		Licensed under the Apache License, Version 2.0 (the "License");*/
+/*		you may not use this file except in compliance with the License.*/
+/*		You may obtain a copy of the License at*/
+/*		*/
+/*		   https://www.apache.org/licenses/LICENSE-2.0*/
+/*		*/
+/*		Unless required by applicable law or agreed to in writing, software*/
+/*		distributed under the License is distributed on an "AS IS" BASIS,*/
+/*		WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/
+/*		See the License for the specific language governing permissions and*/
+/*		limitations under the License.*/
+/*		*/
+/*		Generated on Fri Jul 19 08:59:20 2024		*/
+/*				*/
+/* ------------------------------------------------------ */
+library(RM_IHPSG13_1P_4096x8_c3_bm_bist_slow_1p08V_125C) {	
+	technology (cmos) ;
+	delay_model : table_lookup ;
+	define ("add_pg_pin_to_lib",  "library",  "boolean");
+	add_pg_pin_to_lib : true;
+	voltage_map ( VDD, 1.08);
+	voltage_map ( VDDARRAY, 1.08);
+	voltage_map ( VSS, 0.000000 );
+	
+	date            : "Fri Jul 19 08:59:19 2024" ;
+	comment         : "IHP Microelectronics GmbH, 2024" ;
+	revision        : 1.0.0 ;
+	simulation      : true ;
+	nom_process     : 1 ;
+	nom_temperature : 125 ;
+	nom_voltage     : 1.08 ;
+	
+	operating_conditions("slow_1p08V_125C"){
+	    process     : 1 ;
+	    temperature : 125 ;
+	    voltage     : 1.08 ;
+	    tree_type   : "balanced_tree" ;
+	}
+	
+	default_operating_conditions  : slow_1p08V_125C ;
+	default_max_transition        : 1.0 ;
+	default_fanout_load           : 1.0 ;
+	default_inout_pin_cap         : 0.0 ;
+	default_input_pin_cap         : 0.0 ;
+	default_output_pin_cap        : 0.0 ;
+	default_cell_leakage_power    : 0.0 ;
+	default_leakage_power_density : 0.0 ;
+	 
+	slew_lower_threshold_pct_rise : 30 ;
+	slew_upper_threshold_pct_rise : 70 ;
+	input_threshold_pct_fall      : 50 ;
+	output_threshold_pct_fall     : 50 ;
+	input_threshold_pct_rise      : 50 ;
+	output_threshold_pct_rise     : 50 ;
+	slew_lower_threshold_pct_fall : 30 ;
+	slew_upper_threshold_pct_fall : 70 ;
+	slew_derate_from_library      : 0.5;
+	k_volt_cell_leakage_power     : 0.0 ;
+	k_temp_cell_leakage_power     : 0.0 ;
+	k_process_cell_leakage_power  : 0.0 ;
+	k_volt_internal_power         : 0.0 ;
+	k_temp_internal_power         : 0.0 ;
+	k_process_internal_power      : 0.0 ;
+	
+	capacitive_load_unit            (1,pf) ;
+	voltage_unit                  : "1V" ;
+	current_unit                  : "1uA" ;
+	time_unit                     : "1ns" ;
+	leakage_power_unit            : "1nW" ;
+	pulling_resistance_unit       : "1kohm";
+	/*
+	  ------------------------------------------------------------------------------------------
+	  implicit units overview:
+	    cell_area       unit      : "um"
+	    internal_power  unit      : "1e-12 * J/toggle = 1 * uW/MHz"
+	                                (capacitive_load_unit * voltage_unit^2) per toggle event
+	  ------------------------------------------------------------------------------------------
+	*/
+	library_features(report_delay_calculation);
+	define_cell_area (pad_drivers,pad_driver_sites) ;
+	
+	lu_table_template(CLKTRAN_constraint_template) {
+	     variable_1 : constrained_pin_transition;
+	     index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" );
+	}
+	lu_table_template(SRAM_load_template) {
+	     variable_1 : total_output_net_capacitance;
+	     index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" );
+	}
+	lu_table_template(SIG2SRAM_constraint_template) {
+	     variable_1 : related_pin_transition;
+	     variable_2 : constrained_pin_transition;
+	     index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" );
+	     index_2 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" );
+	}
+	
+	lu_table_template(SIG2SRAM_delay_template) {
+	     variable_1 : input_net_transition;
+	     variable_2 : total_output_net_capacitance;
+	     index_1 ( "0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952" );
+	     index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" );
+	} 
+
+	type (D_7_0) {
+		base_type : array;
+		data_type : bit;
+		bit_width : 8;
+		bit_from  : 7;
+		bit_to    : 0;
+		downto    : true;
+	 }
+
+	type (A_11_0) {
+		base_type : array;
+		data_type : bit;
+		bit_width : 12;
+		bit_from  : 11;
+		bit_to    : 0;
+		downto    : true;
+	 }
+
+cell(RM_IHPSG13_1P_4096x8_c3_bm_bist) {
+pg_pin (VDD) {
+  pg_type : primary_power;
+  voltage_name : VDD;
+}
+pg_pin (VDDARRAY) {
+  pg_type : primary_power;
+  voltage_name : VDDARRAY;
+}
+pg_pin (VSS) {
+  pg_type : primary_ground;
+  voltage_name : VSS;
+}
+
+memory() {
+ type : ram;
+ address_width : 12;
+ word_width : 8;
+}
+
+interface_timing : false;
+bus_naming_style    :   "%s[%d]" ;
+area        : 146413.44 ;
+
+   pin(A_DLY) {
+	   direction       : input ;
+	   capacitance     : 0.00387999 ;
+	   max_transition  : "1" ;
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+		internal_power() {
+		  rise_power("scalar") {
+			 values (0);
+		  }
+		  fall_power("scalar") {
+			 values (0);
+		  }
+	   }
+   }
+
+bus(A_ADDR) {
+   bus_type : A_11_0;
+   direction          : input ;
+   capacitance        : 0.0077013 ;
+    pin(A_ADDR[0]) {
+       capacitance : 0.00625349 ;
+    }
+    pin(A_ADDR[1]) {
+       capacitance : 0.00507435 ;
+    }
+    pin(A_ADDR[2]) {
+       capacitance : 0.00656707 ;
+    }
+    pin(A_ADDR[3]) {
+       capacitance : 0.0083133 ;
+    }
+    pin(A_ADDR[4]) {
+       capacitance : 0.00507219 ;
+    }
+    pin(A_ADDR[5]) {
+       capacitance : 0.00964344 ;
+    }
+    pin(A_ADDR[6]) {
+       capacitance : 0.0119653 ;
+    }
+    pin(A_ADDR[7]) {
+       capacitance : 0.00827606 ;
+    }
+    pin(A_ADDR[8]) {
+       capacitance : 0.0110771 ;
+    }
+    pin(A_ADDR[9]) {
+       capacitance : 0.00811634 ;
+    }
+    pin(A_ADDR[10]) {
+       capacitance : 0.00916579 ;
+    }
+   max_transition     : "0.5952" ;
+   pin(A_ADDR[11:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0172);
+		}
+		        fall_power("scalar"){
+		 values (0.0062);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0149);
+		}
+		        fall_power("scalar"){
+		 values (0.0018);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "((A_WEN | A_REN)& A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\
+"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\
+"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\
+"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\
+"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\
+"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\
+"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\
+"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\
+"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\
+"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\
+"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\
+"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\
+"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "((A_WEN | A_REN)& A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3098",\
+"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\
+"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\
+"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\
+"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\
+"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\
+"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\
+"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\
+"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\
+"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\
+"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\
+"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\
+"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004");
+		}
+	}
+}
+pin(A_WEN) {
+   direction          : input ;
+   capacitance        : 0.00313551 ;
+   max_transition     : "0.5952" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0130);
+		}
+		        fall_power("scalar"){
+		 values (0.0107);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0044);
+		}
+		        fall_power("scalar"){
+		 values (0.0010);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\
+"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\
+"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\
+"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\
+"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\
+"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\
+"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\
+"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\
+"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\
+"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\
+"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\
+"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\
+"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\
+"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\
+"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\
+"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\
+"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\
+"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\
+"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\
+"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\
+"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\
+"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\
+"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\
+"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\
+"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879");
+		}
+	}
+	}
+pin(A_REN) {
+   direction          : input ;
+   capacitance        : 0.00381144 ;
+   max_transition     : "0.5952" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0135);
+		}
+		        fall_power("scalar"){
+		 values (0.0100);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0034);
+		}
+		        fall_power("scalar"){
+		 values (0.0000);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\
+"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\
+"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\
+"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\
+"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\
+"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\
+"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\
+"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\
+"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\
+"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\
+"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\
+"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\
+"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\
+"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\
+"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\
+"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\
+"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\
+"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\
+"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\
+"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\
+"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\
+"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\
+"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\
+"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\
+"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113");
+		}
+	}
+	}
+pin(A_MEN) {
+   direction          : input ;
+   capacitance        : 0.00300347 ;
+   max_transition     : "0.5952" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		        rise_power("scalar"){
+		 values (0.0422);
+		}
+		        fall_power("scalar"){
+		 values (0.0114);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\
+"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\
+"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\
+"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\
+"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\
+"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\
+"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\
+"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\
+"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\
+"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\
+"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\
+"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\
+"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\
+"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\
+"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\
+"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\
+"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\
+"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\
+"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\
+"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\
+"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\
+"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\
+"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\
+"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\
+"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918");
+		}
+	}
+	}
+bus(A_BM) {
+   bus_type : D_7_0;
+   direction          : input ;
+   capacitance        : 0.00272583 ;
+   max_transition     : "0.5952" ;
+   pin(A_BM[7:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0335);
+		}
+		        fall_power("scalar"){
+		 values (0.0287);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0174);
+		}
+		        fall_power("scalar"){
+		 values (0.0008);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "(A_WEN & A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.5971,-0.5776,-0.5512,-0.5083,-0.4282,-0.2807,-0.0600",\
+"-0.6051,-0.5856,-0.5592,-0.5163,-0.4362,-0.2887,-0.0680",\
+"-0.6152,-0.5957,-0.5693,-0.5263,-0.4463,-0.2988,-0.0781",\
+"-0.6281,-0.6086,-0.5822,-0.5393,-0.4592,-0.3117,-0.0910",\
+"-0.6535,-0.6339,-0.6076,-0.5646,-0.4845,-0.3371,-0.1164",\
+"-0.6957,-0.6761,-0.6498,-0.6068,-0.5267,-0.3793,-0.1586",\
+"-0.7601,-0.7406,-0.7142,-0.6712,-0.5911,-0.4437,-0.2230");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.5327,-0.5131,-0.4868,-0.4487,-0.3657,-0.2290,-0.0170",\
+"-0.5407,-0.5211,-0.4948,-0.4567,-0.3737,-0.2370,-0.0250",\
+"-0.5508,-0.5312,-0.5049,-0.4668,-0.3838,-0.2470,-0.0351",\
+"-0.5637,-0.5441,-0.5178,-0.4797,-0.3967,-0.2600,-0.0481",\
+"-0.5890,-0.5695,-0.5431,-0.5050,-0.4220,-0.2853,-0.0734",\
+"-0.6312,-0.6117,-0.5853,-0.5472,-0.4642,-0.3275,-0.1156",\
+"-0.6956,-0.6761,-0.6497,-0.6117,-0.5286,-0.3919,-0.1800");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "(A_WEN & A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.7091,0.6886,0.6632,0.6202,0.5421,0.3956,0.1729",\
+"0.7171,0.6966,0.6712,0.6282,0.5501,0.4036,0.1809",\
+"0.7272,0.7067,0.6813,0.6383,0.5602,0.4137,0.1910",\
+"0.7401,0.7196,0.6942,0.6512,0.5731,0.4266,0.2039",\
+"0.7654,0.7449,0.7195,0.6766,0.5984,0.4519,0.2293",\
+"0.8076,0.7871,0.7617,0.7188,0.6406,0.4941,0.2715",\
+"0.8720,0.8515,0.8261,0.7832,0.7050,0.5586,0.3359");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.6358,0.6182,0.5899,0.5489,0.4688,0.3311,0.1202",\
+"0.6438,0.6262,0.5979,0.5569,0.4768,0.3391,0.1282",\
+"0.6539,0.6363,0.6080,0.5670,0.4869,0.3492,0.1383",\
+"0.6668,0.6493,0.6209,0.5799,0.4998,0.3621,0.1512",\
+"0.6922,0.6746,0.6463,0.6053,0.5252,0.3875,0.1766",\
+"0.7344,0.7168,0.6885,0.6475,0.5674,0.4297,0.2188",\
+"0.7988,0.7812,0.7529,0.7119,0.6318,0.4941,0.2832");
+		}
+	}
+}
+   pin(A_CLK)  {
+	   direction       : input;
+	   capacitance     : 0.00378957;
+	   max_transition  : "0.5952";
+	   clock           : "true" ;
+	   pin_func_type   : active_rising ;
+
+	   timing () {
+		 timing_type : "min_pulse_width";
+		 related_pin : "A_CLK";
+		 rise_constraint("CLKTRAN_constraint_template") {
+		 index_1("0.008,0.5952");
+		 values("0.4,0.4");
+		 }
+	   }
+
+	   related_power_pin : VDD;
+	   related_ground_pin : VSS;
+
+	internal_power() {
+		when : "!A_MEN  & !A_WEN & !A_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN  & A_WEN  & !A_REN";
+		        rise_power("scalar"){
+		 values (1.5263);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & A_WEN  & !A_REN";
+		        rise_power("scalar"){
+		 values (34.4339);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & A_WEN  & A_REN";
+		        rise_power("scalar"){
+		 values (32.2541);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & !A_WEN & A_REN";
+		        rise_power("scalar"){
+		 values (26.8612);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN & !A_WEN & A_REN";
+		        rise_power("scalar"){
+		 values (0.4582);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN & A_WEN  & A_REN";
+		        rise_power("scalar"){
+		 values (0.6428);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & !A_WEN & !A_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	}
+   bus(A_DIN) {
+	   bus_type : D_7_0;
+	   direction       : input ;
+	   capacitance     : 0.00290547 ;
+	   memory_write() {
+		   address : A_ADDR ;
+		   clocked_on : A_CLK;
+	   }
+
+	   max_transition  : "0.5952" ;
+	   pin(A_DIN[7:0]) {
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0335);
+		}
+		        fall_power("scalar"){
+		 values (0.0287);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0174);
+		}
+		        fall_power("scalar"){
+		 values (0.0008);
+		}
+	}
+	   }
+	   timing() {
+		 timing_type     : setup_rising;
+		 related_pin     : "A_CLK";
+		 when            : "(A_WEN & A_MEN)";
+		 sdf_cond        : "A_W_ACCESS";
+
+	  rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 values ("-0.5971,-0.5776,-0.5512,-0.5083,-0.4282,-0.2807,-0.0600",\
+"-0.6051,-0.5856,-0.5592,-0.5163,-0.4362,-0.2887,-0.0680",\
+"-0.6152,-0.5957,-0.5693,-0.5263,-0.4463,-0.2988,-0.0781",\
+"-0.6281,-0.6086,-0.5822,-0.5393,-0.4592,-0.3117,-0.0910",\
+"-0.6535,-0.6339,-0.6076,-0.5646,-0.4845,-0.3371,-0.1164",\
+"-0.6957,-0.6761,-0.6498,-0.6068,-0.5267,-0.3793,-0.1586",\
+"-0.7601,-0.7406,-0.7142,-0.6712,-0.5911,-0.4437,-0.2230");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 values ("-0.5327,-0.5131,-0.4868,-0.4487,-0.3657,-0.2290,-0.0170",\
+"-0.5407,-0.5211,-0.4948,-0.4567,-0.3737,-0.2370,-0.0250",\
+"-0.5508,-0.5312,-0.5049,-0.4668,-0.3838,-0.2470,-0.0351",\
+"-0.5637,-0.5441,-0.5178,-0.4797,-0.3967,-0.2600,-0.0481",\
+"-0.5890,-0.5695,-0.5431,-0.5050,-0.4220,-0.2853,-0.0734",\
+"-0.6312,-0.6117,-0.5853,-0.5472,-0.4642,-0.3275,-0.1156",\
+"-0.6956,-0.6761,-0.6497,-0.6117,-0.5286,-0.3919,-0.1800");
+		 }
+	   }
+
+	   timing() {
+		 timing_type     : hold_rising;
+		 related_pin     : "A_CLK";
+		 when            : "(A_WEN & A_MEN)";
+		 sdf_cond        : "A_W_ACCESS";
+
+	   rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 values ("0.7091,0.6886,0.6632,0.6202,0.5421,0.3956,0.1729",\
+"0.7171,0.6966,0.6712,0.6282,0.5501,0.4036,0.1809",\
+"0.7272,0.7067,0.6813,0.6383,0.5602,0.4137,0.1910",\
+"0.7401,0.7196,0.6942,0.6512,0.5731,0.4266,0.2039",\
+"0.7654,0.7449,0.7195,0.6766,0.5984,0.4519,0.2293",\
+"0.8076,0.7871,0.7617,0.7188,0.6406,0.4941,0.2715",\
+"0.8720,0.8515,0.8261,0.7832,0.7050,0.5586,0.3359");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 values ("0.6358,0.6182,0.5899,0.5489,0.4688,0.3311,0.1202",\
+"0.6438,0.6262,0.5979,0.5569,0.4768,0.3391,0.1282",\
+"0.6539,0.6363,0.6080,0.5670,0.4869,0.3492,0.1383",\
+"0.6668,0.6493,0.6209,0.5799,0.4998,0.3621,0.1512",\
+"0.6922,0.6746,0.6463,0.6053,0.5252,0.3875,0.1766",\
+"0.7344,0.7168,0.6885,0.6475,0.5674,0.4297,0.2188",\
+"0.7988,0.7812,0.7529,0.7119,0.6318,0.4941,0.2832");
+		 }
+	   }
+   }
+
+   pin(A_BIST_EN) {
+	   direction       : input ;
+	   capacitance     : 0.00387999 ;
+	   max_transition  : "1" ;
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+		internal_power() {
+		  rise_power("scalar") {
+			 values (0);
+		  }
+		  fall_power("scalar") {
+			 values (0);
+		  }
+	   }
+   }
+
+bus(A_BIST_ADDR) {
+   bus_type : A_11_0;
+   direction          : input ;
+   capacitance        : 0.0077013 ;
+    pin(A_BIST_ADDR[0]) {
+       capacitance : 0.00625349 ;
+    }
+    pin(A_BIST_ADDR[1]) {
+       capacitance : 0.00507435 ;
+    }
+    pin(A_BIST_ADDR[2]) {
+       capacitance : 0.00656707 ;
+    }
+    pin(A_BIST_ADDR[3]) {
+       capacitance : 0.0083133 ;
+    }
+    pin(A_BIST_ADDR[4]) {
+       capacitance : 0.00507219 ;
+    }
+    pin(A_BIST_ADDR[5]) {
+       capacitance : 0.00964344 ;
+    }
+    pin(A_BIST_ADDR[6]) {
+       capacitance : 0.0119653 ;
+    }
+    pin(A_BIST_ADDR[7]) {
+       capacitance : 0.00827606 ;
+    }
+    pin(A_BIST_ADDR[8]) {
+       capacitance : 0.0110771 ;
+    }
+    pin(A_BIST_ADDR[9]) {
+       capacitance : 0.00811634 ;
+    }
+    pin(A_BIST_ADDR[10]) {
+       capacitance : 0.00916579 ;
+    }
+   max_transition     : "0.5952" ;
+   pin(A_BIST_ADDR[11:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0172);
+		}
+		        fall_power("scalar"){
+		 values (0.0062);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0149);
+		}
+		        fall_power("scalar"){
+		 values (0.0018);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.7371,-0.7176,-0.6863,-0.6434,-0.5652,-0.4168,-0.1980",\
+"-0.7566,-0.7371,-0.7059,-0.6629,-0.5848,-0.4363,-0.2137",\
+"-0.7879,-0.7645,-0.7332,-0.6902,-0.6121,-0.4637,-0.2449",\
+"-0.8309,-0.8074,-0.7762,-0.7332,-0.6551,-0.5066,-0.2879",\
+"-0.9051,-0.8895,-0.8543,-0.8113,-0.7332,-0.5887,-0.3660",\
+"-1.0418,-1.0262,-0.9949,-0.9480,-0.8699,-0.7293,-0.5027",\
+"-1.2684,-1.2449,-1.2176,-1.1707,-1.0965,-0.9480,-0.7293");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.5926,-0.5730,-0.5418,-0.4988,-0.4246,-0.2879,-0.0730",\
+"-0.6121,-0.5926,-0.5613,-0.5223,-0.4441,-0.3074,-0.0887",\
+"-0.6395,-0.6199,-0.5926,-0.5496,-0.4715,-0.3348,-0.1160",\
+"-0.6863,-0.6668,-0.6355,-0.5965,-0.5184,-0.3777,-0.1590",\
+"-0.7605,-0.7410,-0.7137,-0.6746,-0.5926,-0.4559,-0.2410",\
+"-0.9012,-0.8816,-0.8504,-0.8113,-0.7332,-0.5926,-0.3895",\
+"-1.1238,-1.1043,-1.0769,-1.0379,-0.9559,-0.8191,-0.6004");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.8488,0.8293,0.7980,0.7551,0.6730,0.5285,0.3098",\
+"0.8684,0.8488,0.8176,0.7746,0.6926,0.5480,0.3254",\
+"0.8996,0.8801,0.8449,0.8020,0.7238,0.5754,0.3527",\
+"0.9426,0.9191,0.8918,0.8488,0.7668,0.6223,0.3996",\
+"1.0168,1.0012,0.9699,0.9230,0.8449,0.7004,0.4777",\
+"1.1574,1.1379,1.1105,1.0598,0.9816,0.8371,0.6184",\
+"1.3801,1.3605,1.3254,1.2980,1.2043,1.0637,0.8371");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.6965,0.6770,0.6496,0.6066,0.5246,0.3918,0.1730",\
+"0.7160,0.6965,0.6652,0.6262,0.5441,0.4113,0.1965",\
+"0.7473,0.7277,0.6965,0.6535,0.5754,0.4426,0.2238",\
+"0.7863,0.7707,0.7395,0.7004,0.6223,0.4855,0.2629",\
+"0.8684,0.8449,0.8176,0.7785,0.7004,0.5637,0.3449",\
+"1.0051,0.9855,0.9855,0.9113,0.8332,0.7004,0.4895",\
+"1.2277,1.2082,1.1809,1.1379,1.0598,0.9230,0.7004");
+		}
+	}
+}
+pin(A_BIST_WEN) {
+   direction          : input ;
+   capacitance        : 0.00313551 ;
+   max_transition     : "0.5952" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0130);
+		}
+		        fall_power("scalar"){
+		 values (0.0107);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0044);
+		}
+		        fall_power("scalar"){
+		 values (0.0010);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3137,0.3332,0.3605,0.4035,0.4816,0.6223,0.8488",\
+"0.2980,0.3176,0.3410,0.3840,0.4660,0.6027,0.8293",\
+"0.2629,0.2824,0.3098,0.3527,0.4348,0.5754,0.7980",\
+"0.2199,0.2395,0.2668,0.3098,0.3918,0.5324,0.7590",\
+"0.1418,0.1613,0.1887,0.2316,0.3137,0.4348,0.6730",\
+"0.0012,0.0207,0.0520,0.0910,0.1730,0.3098,0.5285",\
+"-0.2215,-0.2020,-0.1746,-0.1277,-0.0496,0.0910,0.3098");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.4504,0.4699,0.4973,0.5324,0.6027,0.7355,0.9699",\
+"0.4309,0.4504,0.4777,0.5129,0.5910,0.7160,0.9504",\
+"0.3996,0.4191,0.4465,0.4816,0.5520,0.6848,0.9191",\
+"0.3605,0.3762,0.4035,0.4387,0.5168,0.6418,0.8723",\
+"0.2785,0.2980,0.3215,0.3605,0.4348,0.5637,0.7980",\
+"0.1379,0.1574,0.1809,0.2199,0.2980,0.4309,0.6457",\
+"-0.0809,-0.0613,-0.0340,0.0051,0.0832,0.2160,0.4191");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3723,0.3527,0.3215,0.2785,0.1965,0.0559,-0.1668",\
+"0.3918,0.3723,0.3449,0.2980,0.2160,0.0754,-0.1473",\
+"0.4152,0.3996,0.3684,0.3254,0.2434,0.1066,-0.1199",\
+"0.4621,0.4465,0.4152,0.3723,0.2863,0.1496,-0.0730",\
+"0.5324,0.5207,0.4895,0.4465,0.3645,0.2199,0.0051",\
+"0.6770,0.6535,0.6301,0.5832,0.5090,0.3605,0.1418",\
+"0.9035,0.8879,0.8566,0.8137,0.7316,0.5871,0.3684");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3762,0.3566,0.3293,0.2863,0.2043,0.0676,-0.1434",\
+"0.3957,0.3762,0.3488,0.3059,0.2238,0.0871,-0.1199",\
+"0.4230,0.4035,0.3723,0.3332,0.2512,0.1184,-0.0965",\
+"0.4660,0.4465,0.4191,0.3762,0.2941,0.1613,-0.0496",\
+"0.5324,0.5168,0.4973,0.4543,0.3723,0.2316,0.0285",\
+"0.6809,0.6613,0.6340,0.5910,0.5129,0.3645,0.1652",\
+"0.9113,0.8918,0.8605,0.8176,0.7395,0.5988,0.3879");
+		}
+	}
+	}
+pin(A_BIST_REN) {
+   direction          : input ;
+   capacitance        : 0.00381144 ;
+   max_transition     : "0.5952" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0135);
+		}
+		        fall_power("scalar"){
+		 values (0.0100);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0034);
+		}
+		        fall_power("scalar"){
+		 values (0.0000);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.0770,-0.0574,-0.0262,0.0168,0.0949,0.2355,0.4582",\
+"-0.0965,-0.0770,-0.0457,-0.0027,0.0754,0.2160,0.4387",\
+"-0.1199,-0.1004,-0.0730,-0.0262,0.0520,0.1887,0.4113",\
+"-0.1590,-0.1434,-0.1160,-0.0730,0.0051,0.1457,0.3645",\
+"-0.2449,-0.2254,-0.1941,-0.1473,-0.0770,0.0676,0.2863",\
+"-0.3816,-0.3699,-0.3387,-0.2801,-0.2215,-0.0770,0.1457",\
+"-0.6121,-0.5926,-0.5613,-0.5145,-0.4363,-0.2996,-0.0730");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.1262,0.1457,0.1691,0.2121,0.2824,0.4191,0.6457",\
+"0.1105,0.1262,0.1496,0.1887,0.2629,0.3996,0.6262",\
+"0.0793,0.0949,0.1223,0.1652,0.2395,0.3684,0.5949",\
+"0.0363,0.0559,0.0793,0.1223,0.2004,0.3410,0.5520",\
+"-0.0457,-0.0262,0.0012,0.0441,0.1301,0.2629,0.4738",\
+"-0.1902,-0.1746,-0.1434,-0.1043,-0.0184,0.1223,0.3332",\
+"-0.4129,-0.3934,-0.3660,-0.3230,-0.2449,-0.1043,0.1105");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.4113,0.3918,0.3645,0.3176,0.2395,0.0988,-0.1238",\
+"0.4309,0.4113,0.3840,0.3371,0.2590,0.1184,-0.1043",\
+"0.4582,0.4387,0.4113,0.3645,0.2824,0.1457,-0.0770",\
+"0.5051,0.4816,0.4543,0.4074,0.3293,0.1887,-0.0340",\
+"0.5715,0.5598,0.5324,0.4895,0.4035,0.2512,0.0441",\
+"0.7043,0.7004,0.6730,0.6262,0.5402,0.3957,0.1809",\
+"0.9387,0.9270,0.8957,0.8527,0.7746,0.6262,0.4074");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.4152,0.3918,0.3645,0.3215,0.2395,0.1027,-0.1082",\
+"0.4309,0.4113,0.3801,0.3410,0.2590,0.1223,-0.0926",\
+"0.4582,0.4387,0.4074,0.3684,0.2863,0.1496,-0.0613",\
+"0.5012,0.4816,0.4504,0.4074,0.3293,0.1887,-0.0145",\
+"0.5715,0.5559,0.5285,0.4816,0.3996,0.2512,0.0598",\
+"0.7160,0.7004,0.6691,0.6262,0.5520,0.4035,0.2004",\
+"0.9387,0.9191,0.8957,0.8488,0.7707,0.6262,0.4113");
+		}
+	}
+	}
+pin(A_BIST_MEN) {
+   direction          : input ;
+   capacitance        : 0.00300347 ;
+   max_transition     : "0.5952" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		        rise_power("scalar"){
+		 values (0.0422);
+		}
+		        fall_power("scalar"){
+		 values (0.0114);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3215,0.3449,0.3684,0.4113,0.4895,0.6301,0.8527",\
+"0.3059,0.3254,0.3527,0.3957,0.4738,0.6145,0.8371",\
+"0.2746,0.2941,0.3215,0.3645,0.4426,0.5871,0.8059",\
+"0.2316,0.2512,0.2785,0.3215,0.3996,0.5402,0.7629",\
+"0.1496,0.1730,0.1965,0.2395,0.3215,0.4660,0.6848",\
+"0.0090,0.0285,0.0598,0.1027,0.1809,0.3176,0.5402",\
+"-0.2098,-0.1902,-0.1668,-0.1199,-0.0418,0.0988,0.3137");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.4582,0.4738,0.5012,0.5363,0.6145,0.7395,0.9738",\
+"0.4387,0.4543,0.4816,0.5207,0.5910,0.7199,0.9582",\
+"0.4035,0.4230,0.4504,0.4855,0.5637,0.6887,0.9230",\
+"0.3645,0.3840,0.4074,0.4465,0.5285,0.6496,0.8840",\
+"0.2824,0.3020,0.3254,0.3645,0.4465,0.5715,0.7980",\
+"0.1418,0.1613,0.1887,0.2238,0.3020,0.4309,0.6496",\
+"-0.0770,-0.0574,-0.0301,0.0090,0.0910,0.2238,0.4191");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3762,0.3605,0.3293,0.2863,0.2043,0.0637,-0.1629",\
+"0.3996,0.3801,0.3488,0.3020,0.2238,0.0832,-0.1395",\
+"0.4230,0.4074,0.3723,0.3293,0.2473,0.1105,-0.1121",\
+"0.4621,0.4465,0.4152,0.3762,0.2941,0.1535,-0.0691",\
+"0.5441,0.5285,0.4973,0.4465,0.3684,0.2316,0.0090",\
+"0.6848,0.6652,0.6301,0.5910,0.5129,0.3605,0.1496",\
+"0.9074,0.8918,0.8566,0.8215,0.7395,0.5910,0.3723");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.3762,0.3605,0.3332,0.2863,0.2043,0.0715,-0.1395",\
+"0.3996,0.3762,0.3488,0.3059,0.2238,0.0910,-0.1199",\
+"0.4270,0.4035,0.3762,0.3332,0.2512,0.1184,-0.0965",\
+"0.4699,0.4504,0.4191,0.3762,0.2941,0.1613,-0.0496",\
+"0.5441,0.5285,0.4973,0.4543,0.3762,0.2355,0.0324",\
+"0.6770,0.6613,0.6340,0.5949,0.5207,0.3762,0.1652",\
+"0.9074,0.8918,0.8605,0.8176,0.7395,0.6027,0.3918");
+		}
+	}
+	}
+bus(A_BIST_BM) {
+   bus_type : D_7_0;
+   direction          : input ;
+   capacitance        : 0.00223339 ;
+   max_transition     : "0.5952" ;
+   pin(A_BIST_BM[7:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0335);
+		}
+		        fall_power("scalar"){
+		 values (0.0287);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0174);
+		}
+		        fall_power("scalar"){
+		 values (0.0008);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "(A_BIST_WEN & A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.5971,-0.5776,-0.5512,-0.5083,-0.4282,-0.2807,-0.0600",\
+"-0.6051,-0.5856,-0.5592,-0.5163,-0.4362,-0.2887,-0.0680",\
+"-0.6152,-0.5957,-0.5693,-0.5263,-0.4463,-0.2988,-0.0781",\
+"-0.6281,-0.6086,-0.5822,-0.5393,-0.4592,-0.3117,-0.0910",\
+"-0.6535,-0.6339,-0.6076,-0.5646,-0.4845,-0.3371,-0.1164",\
+"-0.6957,-0.6761,-0.6498,-0.6068,-0.5267,-0.3793,-0.1586",\
+"-0.7601,-0.7406,-0.7142,-0.6712,-0.5911,-0.4437,-0.2230");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("-0.5327,-0.5131,-0.4868,-0.4487,-0.3657,-0.2290,-0.0170",\
+"-0.5407,-0.5211,-0.4948,-0.4567,-0.3737,-0.2370,-0.0250",\
+"-0.5508,-0.5312,-0.5049,-0.4668,-0.3838,-0.2470,-0.0351",\
+"-0.5637,-0.5441,-0.5178,-0.4797,-0.3967,-0.2600,-0.0481",\
+"-0.5890,-0.5695,-0.5431,-0.5050,-0.4220,-0.2853,-0.0734",\
+"-0.6312,-0.6117,-0.5853,-0.5472,-0.4642,-0.3275,-0.1156",\
+"-0.6956,-0.6761,-0.6497,-0.6117,-0.5286,-0.3919,-0.1800");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "(A_BIST_WEN & A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.7091,0.6886,0.6632,0.6202,0.5421,0.3956,0.1729",\
+"0.7171,0.6966,0.6712,0.6282,0.5501,0.4036,0.1809",\
+"0.7272,0.7067,0.6813,0.6383,0.5602,0.4137,0.1910",\
+"0.7401,0.7196,0.6942,0.6512,0.5731,0.4266,0.2039",\
+"0.7654,0.7449,0.7195,0.6766,0.5984,0.4519,0.2293",\
+"0.8076,0.7871,0.7617,0.7188,0.6406,0.4941,0.2715",\
+"0.8720,0.8515,0.8261,0.7832,0.7050,0.5586,0.3359");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		values ("0.6358,0.6182,0.5899,0.5489,0.4688,0.3311,0.1202",\
+"0.6438,0.6262,0.5979,0.5569,0.4768,0.3391,0.1282",\
+"0.6539,0.6363,0.6080,0.5670,0.4869,0.3492,0.1383",\
+"0.6668,0.6493,0.6209,0.5799,0.4998,0.3621,0.1512",\
+"0.6922,0.6746,0.6463,0.6053,0.5252,0.3875,0.1766",\
+"0.7344,0.7168,0.6885,0.6475,0.5674,0.4297,0.2188",\
+"0.7988,0.7812,0.7529,0.7119,0.6318,0.4941,0.2832");
+		}
+	}
+}
+   pin(A_BIST_CLK)  {
+	   direction       : input;
+	   capacitance     : 0.00378957;
+	   max_transition  : "0.5952";
+	   clock           : "true" ;
+	   pin_func_type   : active_rising ;
+
+	   timing () {
+		 timing_type : "min_pulse_width";
+		 related_pin : "A_BIST_CLK";
+		 rise_constraint("CLKTRAN_constraint_template") {
+		 index_1("0.008,0.5952");
+		 values("0.4,0.4");
+		 }
+	   }
+
+	   related_power_pin : VDD;
+	   related_ground_pin : VSS;
+
+	internal_power() {
+		when : "!A_BIST_MEN  & !A_BIST_WEN & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN  & A_BIST_WEN  & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (1.5263);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & A_BIST_WEN  & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (34.4339);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & A_BIST_WEN  & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (32.2541);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & !A_BIST_WEN & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (26.8612);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0.4582);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN & A_BIST_WEN  & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0.6428);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & !A_BIST_WEN & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	}
+   bus(A_BIST_DIN) {
+	   bus_type : D_7_0;
+	   direction       : input ;
+	   capacitance     : 0.00223473 ;
+	   memory_write() {
+		   address : A_BIST_ADDR ;
+		   clocked_on : A_BIST_CLK;
+	   }
+
+	   max_transition  : "0.5952" ;
+	   pin(A_BIST_DIN[7:0]) {
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0335);
+		}
+		        fall_power("scalar"){
+		 values (0.0287);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0174);
+		}
+		        fall_power("scalar"){
+		 values (0.0008);
+		}
+	}
+	   }
+	   timing() {
+		 timing_type     : setup_rising;
+		 related_pin     : "A_BIST_CLK";
+		 when            : "(A_BIST_WEN & A_BIST_MEN)";
+		 sdf_cond        : "A_BIST_W_ACCESS";
+
+	  rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 values ("-0.5971,-0.5776,-0.5512,-0.5083,-0.4282,-0.2807,-0.0600",\
+"-0.6051,-0.5856,-0.5592,-0.5163,-0.4362,-0.2887,-0.0680",\
+"-0.6152,-0.5957,-0.5693,-0.5263,-0.4463,-0.2988,-0.0781",\
+"-0.6281,-0.6086,-0.5822,-0.5393,-0.4592,-0.3117,-0.0910",\
+"-0.6535,-0.6339,-0.6076,-0.5646,-0.4845,-0.3371,-0.1164",\
+"-0.6957,-0.6761,-0.6498,-0.6068,-0.5267,-0.3793,-0.1586",\
+"-0.7601,-0.7406,-0.7142,-0.6712,-0.5911,-0.4437,-0.2230");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 values ("-0.5327,-0.5131,-0.4868,-0.4487,-0.3657,-0.2290,-0.0170",\
+"-0.5407,-0.5211,-0.4948,-0.4567,-0.3737,-0.2370,-0.0250",\
+"-0.5508,-0.5312,-0.5049,-0.4668,-0.3838,-0.2470,-0.0351",\
+"-0.5637,-0.5441,-0.5178,-0.4797,-0.3967,-0.2600,-0.0481",\
+"-0.5890,-0.5695,-0.5431,-0.5050,-0.4220,-0.2853,-0.0734",\
+"-0.6312,-0.6117,-0.5853,-0.5472,-0.4642,-0.3275,-0.1156",\
+"-0.6956,-0.6761,-0.6497,-0.6117,-0.5286,-0.3919,-0.1800");
+		 }
+	   }
+
+	   timing() {
+		 timing_type     : hold_rising;
+		 related_pin     : "A_BIST_CLK";
+		 when            : "(A_BIST_WEN & A_BIST_MEN)";
+		 sdf_cond        : "A_BIST_W_ACCESS";
+
+	   rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 values ("0.7091,0.6886,0.6632,0.6202,0.5421,0.3956,0.1729",\
+"0.7171,0.6966,0.6712,0.6282,0.5501,0.4036,0.1809",\
+"0.7272,0.7067,0.6813,0.6383,0.5602,0.4137,0.1910",\
+"0.7401,0.7196,0.6942,0.6512,0.5731,0.4266,0.2039",\
+"0.7654,0.7449,0.7195,0.6766,0.5984,0.4519,0.2293",\
+"0.8076,0.7871,0.7617,0.7188,0.6406,0.4941,0.2715",\
+"0.8720,0.8515,0.8261,0.7832,0.7050,0.5586,0.3359");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 values ("0.6358,0.6182,0.5899,0.5489,0.4688,0.3311,0.1202",\
+"0.6438,0.6262,0.5979,0.5569,0.4768,0.3391,0.1282",\
+"0.6539,0.6363,0.6080,0.5670,0.4869,0.3492,0.1383",\
+"0.6668,0.6493,0.6209,0.5799,0.4998,0.3621,0.1512",\
+"0.6922,0.6746,0.6463,0.6053,0.5252,0.3875,0.1766",\
+"0.7344,0.7168,0.6885,0.6475,0.5674,0.4297,0.2188",\
+"0.7988,0.7812,0.7529,0.7119,0.6318,0.4941,0.2832");
+		 }
+	   }
+   }
+
+bus(A_DOUT) {
+
+	   bus_type : D_7_0;
+	   direction       : output ;
+	   capacitance     : 0 ;
+	   max_capacitance  : "6.4e-14" ;
+	   memory_read() {
+		  address : A_ADDR ;
+	   }
+	   pin(A_DOUT[7:0]) {
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+	   internal_power() {
+		  rise_power("scalar") {
+			 values (0);
+		  }
+		  fall_power("scalar") {
+			 values (0);
+		  }
+	   }
+	   }
+	   timing() {
+		 related_pin   : "A_CLK";
+		 timing_type   : rising_edge ;
+		 timing_sense  : non_unate ;
+
+	   cell_rise(SIG2SRAM_delay_template) {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("8.8071,8.8098,8.8220,8.8362,8.8882,8.9463",\
+"8.8192,8.8219,8.8341,8.8483,8.9004,8.9584",\
+"8.8311,8.8338,8.8460,8.8602,8.9123,8.9703",\
+"8.8332,8.8360,8.8482,8.8624,8.9144,8.9724",\
+"8.8591,8.8618,8.8740,8.8882,8.9402,8.9983",\
+"8.9105,8.9132,8.9254,8.9396,8.9916,9.0497",\
+"8.9673,8.9700,8.9822,8.9964,9.0485,9.1065");
+	   }
+	   cell_fall(SIG2SRAM_delay_template) {
+		 index_1("0.0080,0.0288,0.0616,0.1072,0.1920,0.3496,0.5952");
+		 index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("8.6972,8.6993,8.7089,8.7207,8.7643,8.8081",\
+"8.7093,8.7114,8.7210,8.7328,8.7764,8.8202",\
+"8.7212,8.7233,8.7330,8.7448,8.7883,8.8321",\
+"8.7233,8.7255,8.7351,8.7469,8.7905,8.8342",\
+"8.7491,8.7513,8.7609,8.7727,8.8163,8.8600",\
+"8.8005,8.8027,8.8123,8.8241,8.8677,8.9114",\
+"8.8574,8.8595,8.8691,8.8809,8.9245,8.9683");
+	   }
+
+	   rise_transition(SRAM_load_template) {
+		 index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("0.0560,0.0583,0.0696,0.0816,0.1519,0.2335");
+	   }
+	   fall_transition(SRAM_load_template) {
+		 index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("0.0428,0.0445,0.0538,0.0658,0.1181,0.1751");
+	   }
+	}
+}
+cell_leakage_power : 2613.1763;
+}
+}
diff --git a/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_4096x8_c3_bm_bist_typ_1p20V_25C.lib b/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_4096x8_c3_bm_bist_typ_1p20V_25C.lib
new file mode 100644
index 00000000..0dd7037c
--- /dev/null
+++ b/ihp-sg13g2/libs.ref/sg13g2_sram/lib/RM_IHPSG13_1P_4096x8_c3_bm_bist_typ_1p20V_25C.lib
@@ -0,0 +1,1537 @@
+/* ------------------------------------------------------*/
+/**/
+/*		Copyright 2024 IHP PDK Authors*/
+/**/
+/*		Licensed under the Apache License, Version 2.0 (the "License");*/
+/*		you may not use this file except in compliance with the License.*/
+/*		You may obtain a copy of the License at*/
+/*		*/
+/*		   https://www.apache.org/licenses/LICENSE-2.0*/
+/*		*/
+/*		Unless required by applicable law or agreed to in writing, software*/
+/*		distributed under the License is distributed on an "AS IS" BASIS,*/
+/*		WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.*/
+/*		See the License for the specific language governing permissions and*/
+/*		limitations under the License.*/
+/*		*/
+/*		Generated on Fri Jul 19 08:59:22 2024		*/
+/*				*/
+/* ------------------------------------------------------ */
+library(RM_IHPSG13_1P_4096x8_c3_bm_bist_typ_1p20V_25C) {	
+	technology (cmos) ;
+	delay_model : table_lookup ;
+	define ("add_pg_pin_to_lib",  "library",  "boolean");
+	add_pg_pin_to_lib : true;
+	voltage_map ( VDD, 1.20);
+	voltage_map ( VDDARRAY, 1.20);
+	voltage_map ( VSS, 0.000000 );
+	
+	date            : "Fri Jul 19 08:59:19 2024" ;
+	comment         : "IHP Microelectronics GmbH, 2024" ;
+	revision        : 1.0.0 ;
+	simulation      : true ;
+	nom_process     : 1 ;
+	nom_temperature : 25 ;
+	nom_voltage     : 1.20 ;
+	
+	operating_conditions("typ_1p20V_25C"){
+	    process     : 1 ;
+	    temperature : 25 ;
+	    voltage     : 1.20 ;
+	    tree_type   : "balanced_tree" ;
+	}
+	
+	default_operating_conditions  : typ_1p20V_25C ;
+	default_max_transition        : 1.0 ;
+	default_fanout_load           : 1.0 ;
+	default_inout_pin_cap         : 0.0 ;
+	default_input_pin_cap         : 0.0 ;
+	default_output_pin_cap        : 0.0 ;
+	default_cell_leakage_power    : 0.0 ;
+	default_leakage_power_density : 0.0 ;
+	 
+	slew_lower_threshold_pct_rise : 30 ;
+	slew_upper_threshold_pct_rise : 70 ;
+	input_threshold_pct_fall      : 50 ;
+	output_threshold_pct_fall     : 50 ;
+	input_threshold_pct_rise      : 50 ;
+	output_threshold_pct_rise     : 50 ;
+	slew_lower_threshold_pct_fall : 30 ;
+	slew_upper_threshold_pct_fall : 70 ;
+	slew_derate_from_library      : 0.5;
+	k_volt_cell_leakage_power     : 0.0 ;
+	k_temp_cell_leakage_power     : 0.0 ;
+	k_process_cell_leakage_power  : 0.0 ;
+	k_volt_internal_power         : 0.0 ;
+	k_temp_internal_power         : 0.0 ;
+	k_process_internal_power      : 0.0 ;
+	
+	capacitive_load_unit            (1,pf) ;
+	voltage_unit                  : "1V" ;
+	current_unit                  : "1uA" ;
+	time_unit                     : "1ns" ;
+	leakage_power_unit            : "1nW" ;
+	pulling_resistance_unit       : "1kohm";
+	/*
+	  ------------------------------------------------------------------------------------------
+	  implicit units overview:
+	    cell_area       unit      : "um"
+	    internal_power  unit      : "1e-12 * J/toggle = 1 * uW/MHz"
+	                                (capacitive_load_unit * voltage_unit^2) per toggle event
+	  ------------------------------------------------------------------------------------------
+	*/
+	library_features(report_delay_calculation);
+	define_cell_area (pad_drivers,pad_driver_sites) ;
+	
+	lu_table_template(CLKTRAN_constraint_template) {
+	     variable_1 : constrained_pin_transition;
+	     index_1 ( "0.010, 0.050, 0.200, 0.400, 1.000" );
+	}
+	lu_table_template(SRAM_load_template) {
+	     variable_1 : total_output_net_capacitance;
+	     index_1 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" );
+	}
+	lu_table_template(SIG2SRAM_constraint_template) {
+	     variable_1 : related_pin_transition;
+	     variable_2 : constrained_pin_transition;
+	     index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" );
+	     index_2 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" );
+	}
+	
+	lu_table_template(SIG2SRAM_delay_template) {
+	     variable_1 : input_net_transition;
+	     variable_2 : total_output_net_capacitance;
+	     index_1 ( "0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760" );
+	     index_2 ( "0.0008,0.0014,0.0051,0.0100,0.0339,0.0640" );
+	} 
+
+	type (D_7_0) {
+		base_type : array;
+		data_type : bit;
+		bit_width : 8;
+		bit_from  : 7;
+		bit_to    : 0;
+		downto    : true;
+	 }
+
+	type (A_11_0) {
+		base_type : array;
+		data_type : bit;
+		bit_width : 12;
+		bit_from  : 11;
+		bit_to    : 0;
+		downto    : true;
+	 }
+
+cell(RM_IHPSG13_1P_4096x8_c3_bm_bist) {
+pg_pin (VDD) {
+  pg_type : primary_power;
+  voltage_name : VDD;
+}
+pg_pin (VDDARRAY) {
+  pg_type : primary_power;
+  voltage_name : VDDARRAY;
+}
+pg_pin (VSS) {
+  pg_type : primary_ground;
+  voltage_name : VSS;
+}
+
+memory() {
+ type : ram;
+ address_width : 12;
+ word_width : 8;
+}
+
+interface_timing : false;
+bus_naming_style    :   "%s[%d]" ;
+area        : 146413.44 ;
+
+   pin(A_DLY) {
+	   direction       : input ;
+	   capacitance     : 0.00401111 ;
+	   max_transition  : "1" ;
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+		internal_power() {
+		  rise_power("scalar") {
+			 values (0);
+		  }
+		  fall_power("scalar") {
+			 values (0);
+		  }
+	   }
+   }
+
+bus(A_ADDR) {
+   bus_type : A_11_0;
+   direction          : input ;
+   capacitance        : 0.00721489 ;
+    pin(A_ADDR[0]) {
+       capacitance : 0.00593979 ;
+    }
+    pin(A_ADDR[1]) {
+       capacitance : 0.00483009 ;
+    }
+    pin(A_ADDR[2]) {
+       capacitance : 0.006215 ;
+    }
+    pin(A_ADDR[3]) {
+       capacitance : 0.00766726 ;
+    }
+    pin(A_ADDR[4]) {
+       capacitance : 0.00488951 ;
+    }
+    pin(A_ADDR[5]) {
+       capacitance : 0.0091523 ;
+    }
+    pin(A_ADDR[6]) {
+       capacitance : 0.0109212 ;
+    }
+    pin(A_ADDR[7]) {
+       capacitance : 0.00774122 ;
+    }
+    pin(A_ADDR[8]) {
+       capacitance : 0.0101403 ;
+    }
+    pin(A_ADDR[9]) {
+       capacitance : 0.00771605 ;
+    }
+    pin(A_ADDR[10]) {
+       capacitance : 0.00860549 ;
+    }
+   max_transition     : "0.476" ;
+   pin(A_ADDR[11:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0077);
+		}
+		        fall_power("scalar"){
+		 values (0.0018);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0163);
+		}
+		        fall_power("scalar"){
+		 values (0.0029);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "((A_WEN | A_REN)& A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\
+"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\
+"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\
+"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\
+"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\
+"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\
+"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\
+"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\
+"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\
+"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\
+"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\
+"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\
+"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "((A_WEN | A_REN)& A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\
+"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\
+"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\
+"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\
+"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\
+"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\
+"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\
+"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\
+"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\
+"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\
+"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\
+"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\
+"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387");
+		}
+	}
+}
+pin(A_WEN) {
+   direction          : input ;
+   capacitance        : 0.00324098 ;
+   max_transition     : "0.476" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0038);
+		}
+		        fall_power("scalar"){
+		 values (0.0049);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0032);
+		}
+		        fall_power("scalar"){
+		 values (0.0048);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\
+"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\
+"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\
+"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\
+"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\
+"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\
+"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\
+"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\
+"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\
+"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\
+"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\
+"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\
+"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\
+"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\
+"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\
+"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\
+"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\
+"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\
+"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\
+"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\
+"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\
+"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\
+"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\
+"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\
+"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512");
+		}
+	}
+	}
+pin(A_REN) {
+   direction          : input ;
+   capacitance        : 0.00381634 ;
+   max_transition     : "0.476" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0055);
+		}
+		        fall_power("scalar"){
+		 values (0.0032);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0052);
+		}
+		        fall_power("scalar"){
+		 values (0.0035);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\
+"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\
+"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\
+"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\
+"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\
+"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\
+"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\
+"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\
+"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\
+"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\
+"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\
+"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\
+"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "A_MEN"
+		sdf_cond        : "A_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\
+"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\
+"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\
+"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\
+"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\
+"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\
+"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\
+"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\
+"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\
+"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\
+"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\
+"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\
+"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707");
+		}
+	}
+	}
+pin(A_MEN) {
+   direction          : input ;
+   capacitance        : 0.00309605 ;
+   max_transition     : "0.476" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		        rise_power("scalar"){
+		 values (0.0234);
+		}
+		        fall_power("scalar"){
+		 values (0.0060);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\
+"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\
+"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\
+"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\
+"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\
+"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\
+"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\
+"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\
+"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\
+"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\
+"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\
+"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\
+"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\
+"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\
+"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\
+"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\
+"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\
+"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\
+"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\
+"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\
+"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\
+"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\
+"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\
+"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\
+"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512");
+		}
+	}
+	}
+bus(A_BM) {
+   bus_type : D_7_0;
+   direction          : input ;
+   capacitance        : 0.00293842 ;
+   max_transition     : "0.476" ;
+   pin(A_BM[7:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0242);
+		}
+		        fall_power("scalar"){
+		 values (0.0193);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0257);
+		}
+		        fall_power("scalar"){
+		 values (0.0191);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_CLK";
+		when            : "(A_WEN & A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.3243,-0.3086,-0.2950,-0.2627,-0.2159,-0.1114,0.0800",\
+"-0.3293,-0.3136,-0.3000,-0.2677,-0.2209,-0.1164,0.0750",\
+"-0.3338,-0.3181,-0.3045,-0.2722,-0.2254,-0.1209,0.0705",\
+"-0.3435,-0.3279,-0.3142,-0.2820,-0.2351,-0.1306,0.0608",\
+"-0.3501,-0.3345,-0.3208,-0.2886,-0.2417,-0.1372,0.0542",\
+"-0.3811,-0.3654,-0.3518,-0.3195,-0.2727,-0.1682,0.0232",\
+"-0.4371,-0.4214,-0.4078,-0.3755,-0.3287,-0.2242,-0.0328");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.2862,-0.2715,-0.2579,-0.2295,-0.1788,-0.0811,0.1015",\
+"-0.2912,-0.2765,-0.2629,-0.2345,-0.1838,-0.0861,0.0965",\
+"-0.2957,-0.2810,-0.2673,-0.2390,-0.1882,-0.0906,0.0920",\
+"-0.3054,-0.2908,-0.2771,-0.2488,-0.1980,-0.1004,0.0823",\
+"-0.3120,-0.2974,-0.2837,-0.2554,-0.2046,-0.1069,0.0757",\
+"-0.3430,-0.3283,-0.3147,-0.2863,-0.2356,-0.1379,0.0447",\
+"-0.3990,-0.3843,-0.3706,-0.3423,-0.2915,-0.1939,-0.0113");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_CLK";
+		when            : "(A_WEN & A_MEN)"
+		sdf_cond        : "A_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.4332,0.4166,0.4039,0.3717,0.3238,0.2203,0.0279",\
+"0.4382,0.4216,0.4089,0.3767,0.3288,0.2253,0.0330",\
+"0.4427,0.4261,0.4134,0.3812,0.3333,0.2298,0.0374",\
+"0.4525,0.4359,0.4232,0.3909,0.3431,0.2396,0.0472",\
+"0.4590,0.4424,0.4297,0.3975,0.3496,0.2461,0.0538",\
+"0.4900,0.4734,0.4607,0.4285,0.3806,0.2771,0.0847",\
+"0.5460,0.5294,0.5167,0.4845,0.4366,0.3331,0.1407");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.3873,0.3727,0.3590,0.3307,0.2809,0.1881,0.0035",\
+"0.3923,0.3777,0.3640,0.3357,0.2859,0.1931,0.0085",\
+"0.3968,0.3822,0.3685,0.3402,0.2904,0.1976,0.0130",\
+"0.4066,0.3919,0.3782,0.3499,0.3001,0.2073,0.0228",\
+"0.4131,0.3985,0.3848,0.3565,0.3067,0.2139,0.0293",\
+"0.4441,0.4295,0.4158,0.3875,0.3377,0.2449,0.0603",\
+"0.5001,0.4855,0.4718,0.4435,0.3937,0.3009,0.1163");
+		}
+	}
+}
+   pin(A_CLK)  {
+	   direction       : input;
+	   capacitance     : 0.00380014;
+	   max_transition  : "0.476";
+	   clock           : "true" ;
+	   pin_func_type   : active_rising ;
+
+	   timing () {
+		 timing_type : "min_pulse_width";
+		 related_pin : "A_CLK";
+		 rise_constraint("CLKTRAN_constraint_template") {
+		 index_1("0.0056,0.476");
+		 values("0.21,0.21");
+		 }
+	   }
+
+	   related_power_pin : VDD;
+	   related_ground_pin : VSS;
+
+	internal_power() {
+		when : "!A_MEN  & !A_WEN & !A_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN  & A_WEN  & !A_REN";
+		        rise_power("scalar"){
+		 values (1.1525);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & A_WEN  & !A_REN";
+		        rise_power("scalar"){
+		 values (42.2119);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & A_WEN  & A_REN";
+		        rise_power("scalar"){
+		 values (41.0961);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & !A_WEN & A_REN";
+		        rise_power("scalar"){
+		 values (33.7167);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN & !A_WEN & A_REN";
+		        rise_power("scalar"){
+		 values (0.3256);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN & A_WEN  & A_REN";
+		        rise_power("scalar"){
+		 values (0.5445);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_MEN  & !A_WEN & !A_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	}
+   bus(A_DIN) {
+	   bus_type : D_7_0;
+	   direction       : input ;
+	   capacitance     : 0.0030602 ;
+	   memory_write() {
+		   address : A_ADDR ;
+		   clocked_on : A_CLK;
+	   }
+
+	   max_transition  : "0.476" ;
+	   pin(A_DIN[7:0]) {
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+	internal_power() {
+		when : "A_MEN";
+		        rise_power("scalar"){
+		 values (0.0242);
+		}
+		        fall_power("scalar"){
+		 values (0.0193);
+		}
+	}
+	internal_power() {
+		when : "!A_MEN";
+		        rise_power("scalar"){
+		 values (0.0257);
+		}
+		        fall_power("scalar"){
+		 values (0.0191);
+		}
+	}
+	   }
+	   timing() {
+		 timing_type     : setup_rising;
+		 related_pin     : "A_CLK";
+		 when            : "(A_WEN & A_MEN)";
+		 sdf_cond        : "A_W_ACCESS";
+
+	  rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 values ("-0.3243,-0.3086,-0.2950,-0.2627,-0.2159,-0.1114,0.0800",\
+"-0.3293,-0.3136,-0.3000,-0.2677,-0.2209,-0.1164,0.0750",\
+"-0.3338,-0.3181,-0.3045,-0.2722,-0.2254,-0.1209,0.0705",\
+"-0.3435,-0.3279,-0.3142,-0.2820,-0.2351,-0.1306,0.0608",\
+"-0.3501,-0.3345,-0.3208,-0.2886,-0.2417,-0.1372,0.0542",\
+"-0.3811,-0.3654,-0.3518,-0.3195,-0.2727,-0.1682,0.0232",\
+"-0.4371,-0.4214,-0.4078,-0.3755,-0.3287,-0.2242,-0.0328");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 values ("-0.2862,-0.2715,-0.2579,-0.2295,-0.1788,-0.0811,0.1015",\
+"-0.2912,-0.2765,-0.2629,-0.2345,-0.1838,-0.0861,0.0965",\
+"-0.2957,-0.2810,-0.2673,-0.2390,-0.1882,-0.0906,0.0920",\
+"-0.3054,-0.2908,-0.2771,-0.2488,-0.1980,-0.1004,0.0823",\
+"-0.3120,-0.2974,-0.2837,-0.2554,-0.2046,-0.1069,0.0757",\
+"-0.3430,-0.3283,-0.3147,-0.2863,-0.2356,-0.1379,0.0447",\
+"-0.3990,-0.3843,-0.3706,-0.3423,-0.2915,-0.1939,-0.0113");
+		 }
+	   }
+
+	   timing() {
+		 timing_type     : hold_rising;
+		 related_pin     : "A_CLK";
+		 when            : "(A_WEN & A_MEN)";
+		 sdf_cond        : "A_W_ACCESS";
+
+	   rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 values ("0.4332,0.4166,0.4039,0.3717,0.3238,0.2203,0.0279",\
+"0.4382,0.4216,0.4089,0.3767,0.3288,0.2253,0.0330",\
+"0.4427,0.4261,0.4134,0.3812,0.3333,0.2298,0.0374",\
+"0.4525,0.4359,0.4232,0.3909,0.3431,0.2396,0.0472",\
+"0.4590,0.4424,0.4297,0.3975,0.3496,0.2461,0.0538",\
+"0.4900,0.4734,0.4607,0.4285,0.3806,0.2771,0.0847",\
+"0.5460,0.5294,0.5167,0.4845,0.4366,0.3331,0.1407");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 values ("0.3873,0.3727,0.3590,0.3307,0.2809,0.1881,0.0035",\
+"0.3923,0.3777,0.3640,0.3357,0.2859,0.1931,0.0085",\
+"0.3968,0.3822,0.3685,0.3402,0.2904,0.1976,0.0130",\
+"0.4066,0.3919,0.3782,0.3499,0.3001,0.2073,0.0228",\
+"0.4131,0.3985,0.3848,0.3565,0.3067,0.2139,0.0293",\
+"0.4441,0.4295,0.4158,0.3875,0.3377,0.2449,0.0603",\
+"0.5001,0.4855,0.4718,0.4435,0.3937,0.3009,0.1163");
+		 }
+	   }
+   }
+
+   pin(A_BIST_EN) {
+	   direction       : input ;
+	   capacitance     : 0.00401111 ;
+	   max_transition  : "1" ;
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+		internal_power() {
+		  rise_power("scalar") {
+			 values (0);
+		  }
+		  fall_power("scalar") {
+			 values (0);
+		  }
+	   }
+   }
+
+bus(A_BIST_ADDR) {
+   bus_type : A_11_0;
+   direction          : input ;
+   capacitance        : 0.00721489 ;
+    pin(A_BIST_ADDR[0]) {
+       capacitance : 0.00593979 ;
+    }
+    pin(A_BIST_ADDR[1]) {
+       capacitance : 0.00483009 ;
+    }
+    pin(A_BIST_ADDR[2]) {
+       capacitance : 0.006215 ;
+    }
+    pin(A_BIST_ADDR[3]) {
+       capacitance : 0.00766726 ;
+    }
+    pin(A_BIST_ADDR[4]) {
+       capacitance : 0.00488951 ;
+    }
+    pin(A_BIST_ADDR[5]) {
+       capacitance : 0.0091523 ;
+    }
+    pin(A_BIST_ADDR[6]) {
+       capacitance : 0.0109212 ;
+    }
+    pin(A_BIST_ADDR[7]) {
+       capacitance : 0.00774122 ;
+    }
+    pin(A_BIST_ADDR[8]) {
+       capacitance : 0.0101403 ;
+    }
+    pin(A_BIST_ADDR[9]) {
+       capacitance : 0.00771605 ;
+    }
+    pin(A_BIST_ADDR[10]) {
+       capacitance : 0.00860549 ;
+    }
+   max_transition     : "0.476" ;
+   pin(A_BIST_ADDR[11:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0077);
+		}
+		        fall_power("scalar"){
+		 values (0.0018);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0163);
+		}
+		        fall_power("scalar"){
+		 values (0.0029);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.4168,-0.3973,-0.3855,-0.3543,-0.3074,-0.2020,-0.0027",\
+"-0.4324,-0.4129,-0.4012,-0.3699,-0.3191,-0.2176,-0.0184",\
+"-0.4441,-0.4285,-0.4129,-0.3816,-0.3309,-0.2293,-0.0301",\
+"-0.4793,-0.4598,-0.4441,-0.4129,-0.3660,-0.2645,-0.0652",\
+"-0.5223,-0.5066,-0.4910,-0.4598,-0.4129,-0.3074,-0.1121",\
+"-0.6199,-0.6082,-0.5926,-0.5613,-0.5145,-0.4129,-0.2137",\
+"-0.8191,-0.8074,-0.7840,-0.7566,-0.7098,-0.6082,-0.4051");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.3309,-0.3113,-0.2996,-0.2684,-0.2176,-0.1238,0.0637",\
+"-0.3465,-0.3309,-0.3152,-0.2840,-0.2332,-0.1395,0.0480",\
+"-0.3582,-0.3426,-0.3270,-0.2996,-0.2488,-0.1512,0.0324",\
+"-0.3895,-0.3738,-0.3582,-0.3309,-0.2801,-0.1863,0.0051",\
+"-0.4363,-0.4207,-0.4051,-0.3777,-0.3230,-0.2293,-0.0379",\
+"-0.5379,-0.5223,-0.5066,-0.4793,-0.4285,-0.3309,-0.1434",\
+"-0.7332,-0.7176,-0.7020,-0.6746,-0.6238,-0.5262,-0.3387");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "((A_BIST_WEN | A_BIST_REN)& A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.5246,0.5051,0.4895,0.4582,0.4113,0.3059,0.1066",\
+"0.5402,0.5207,0.5051,0.4777,0.4270,0.3215,0.1223",\
+"0.5520,0.5324,0.5168,0.4895,0.4387,0.3371,0.1340",\
+"0.5832,0.5676,0.5520,0.5207,0.4738,0.3684,0.1691",\
+"0.6301,0.6105,0.5949,0.5676,0.5168,0.4113,0.2160",\
+"0.7316,0.7121,0.7004,0.6691,0.6223,0.5168,0.3176",\
+"0.9270,0.9230,0.8957,0.8645,0.8137,0.7121,0.5168");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.4309,0.4152,0.4035,0.3684,0.3215,0.2277,0.0363",\
+"0.4465,0.4309,0.4152,0.3879,0.3371,0.2395,0.0559",\
+"0.4582,0.4426,0.4309,0.3996,0.3488,0.2551,0.0715",\
+"0.4934,0.4777,0.4621,0.4348,0.3840,0.2863,0.0988",\
+"0.5363,0.5207,0.5051,0.4777,0.4270,0.3332,0.1418",\
+"0.6379,0.6262,0.6105,0.5793,0.5324,0.4348,0.2434",\
+"0.8332,0.8215,0.8059,0.7707,0.7238,0.6301,0.4387");
+		}
+	}
+}
+pin(A_BIST_WEN) {
+   direction          : input ;
+   capacitance        : 0.00324098 ;
+   max_transition     : "0.476" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0038);
+		}
+		        fall_power("scalar"){
+		 values (0.0049);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0032);
+		}
+		        fall_power("scalar"){
+		 values (0.0048);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2043,0.2199,0.2316,0.2629,0.3059,0.4113,0.6066",\
+"0.1887,0.2043,0.2160,0.2473,0.2941,0.3957,0.5949",\
+"0.1691,0.1848,0.2004,0.2316,0.2785,0.3801,0.5754",\
+"0.1379,0.1574,0.1691,0.2004,0.2473,0.3527,0.5480",\
+"0.0910,0.1066,0.1223,0.1535,0.2004,0.2980,0.4973",\
+"-0.0105,0.0051,0.0207,0.0520,0.0949,0.2004,0.3957",\
+"-0.2059,-0.1902,-0.1746,-0.1473,-0.1004,0.0051,0.2004");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2941,0.3098,0.3215,0.3488,0.4035,0.4973,0.6887",\
+"0.2785,0.2941,0.3059,0.3332,0.3840,0.4816,0.6691",\
+"0.2629,0.2785,0.2902,0.3176,0.3684,0.4660,0.6535",\
+"0.2316,0.2473,0.2590,0.2863,0.3410,0.4348,0.6262",\
+"0.1848,0.2004,0.2121,0.2395,0.2902,0.3879,0.5754",\
+"0.0832,0.0988,0.1105,0.1379,0.1809,0.2746,0.4699",\
+"-0.1121,-0.0965,-0.0848,-0.0535,-0.0066,0.0910,0.2824");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2473,0.2316,0.2160,0.1887,0.1379,0.0363,-0.1629",\
+"0.2629,0.2473,0.2316,0.2043,0.1535,0.0520,-0.1473",\
+"0.2785,0.2590,0.2434,0.2160,0.1652,0.0676,-0.1355",\
+"0.3098,0.2941,0.2785,0.2473,0.1965,0.0910,-0.1043",\
+"0.3527,0.3371,0.3215,0.2941,0.2434,0.1418,-0.0574",\
+"0.4582,0.4426,0.4270,0.3957,0.3488,0.2434,0.0480",\
+"0.6535,0.6379,0.6184,0.5910,0.5402,0.4426,0.2434");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\
+"0.2551,0.2395,0.2277,0.1965,0.1457,0.0480,-0.1395",\
+"0.2668,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\
+"0.3020,0.2863,0.2707,0.2395,0.1887,0.0910,-0.0965",\
+"0.3449,0.3293,0.3176,0.2863,0.2355,0.1379,-0.0496",\
+"0.4504,0.4348,0.4191,0.3879,0.3371,0.2395,0.0559",\
+"0.6457,0.6301,0.6145,0.5871,0.5324,0.4309,0.2512");
+		}
+	}
+	}
+pin(A_BIST_REN) {
+   direction          : input ;
+   capacitance        : 0.00381634 ;
+   max_transition     : "0.476" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0055);
+		}
+		        fall_power("scalar"){
+		 values (0.0032);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0052);
+		}
+		        fall_power("scalar"){
+		 values (0.0035);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.0301,-0.0145,0.0012,0.0324,0.0793,0.1809,0.3762",\
+"-0.0457,-0.0301,-0.0145,0.0168,0.0637,0.1613,0.3605",\
+"-0.0574,-0.0418,-0.0262,0.0051,0.0520,0.1496,0.3449",\
+"-0.0926,-0.0730,-0.0574,-0.0262,0.0207,0.1184,0.3137",\
+"-0.1395,-0.1238,-0.1082,-0.0770,-0.0301,0.0715,0.2707",\
+"-0.2410,-0.2254,-0.2098,-0.1746,-0.1355,-0.0340,0.1652",\
+"-0.4402,-0.4207,-0.4051,-0.3738,-0.3270,-0.2293,-0.0340");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.0988,0.1145,0.1262,0.1535,0.2043,0.3020,0.4855",\
+"0.0832,0.0988,0.1105,0.1418,0.1848,0.2824,0.4738",\
+"0.0676,0.0832,0.0949,0.1262,0.1730,0.2668,0.4621",\
+"0.0402,0.0559,0.0676,0.0988,0.1457,0.2434,0.4191",\
+"-0.0105,0.0012,0.0168,0.0480,0.0988,0.1965,0.3840",\
+"-0.1160,-0.0965,-0.0848,-0.0535,-0.0066,0.0988,0.2824",\
+"-0.3113,-0.2957,-0.2801,-0.2527,-0.2059,-0.1043,0.0832");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "A_BIST_MEN"
+		sdf_cond        : "A_BIST_MEN"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2707,0.2551,0.2395,0.2121,0.1613,0.0598,-0.1395",\
+"0.2863,0.2707,0.2551,0.2238,0.1730,0.0715,-0.1238",\
+"0.2980,0.2824,0.2668,0.2395,0.1887,0.0871,-0.1121",\
+"0.3332,0.3176,0.3020,0.2707,0.2199,0.1184,-0.0809",\
+"0.3762,0.3605,0.3449,0.3176,0.2668,0.1613,-0.0340",\
+"0.4816,0.4621,0.4504,0.4191,0.3723,0.2629,0.0715",\
+"0.6770,0.6613,0.6418,0.6184,0.5637,0.4699,0.2629");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2590,0.2434,0.2316,0.2004,0.1457,0.0520,-0.1355",\
+"0.2746,0.2590,0.2434,0.2160,0.1613,0.0676,-0.1199",\
+"0.2863,0.2707,0.2590,0.2277,0.1730,0.0832,-0.1082",\
+"0.3215,0.3059,0.2902,0.2590,0.2082,0.1105,-0.0770",\
+"0.3645,0.3488,0.3332,0.3059,0.2551,0.1535,-0.0340",\
+"0.4699,0.4543,0.4387,0.4074,0.3605,0.2551,0.0715",\
+"0.6652,0.6496,0.6340,0.6027,0.5520,0.4621,0.2707");
+		}
+	}
+	}
+pin(A_BIST_MEN) {
+   direction          : input ;
+   capacitance        : 0.00309605 ;
+   max_transition     : "0.476" ;
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		        rise_power("scalar"){
+		 values (0.0234);
+		}
+		        fall_power("scalar"){
+		 values (0.0060);
+		}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2043,0.2199,0.2316,0.2668,0.3098,0.4152,0.6066",\
+"0.1887,0.2043,0.2199,0.2512,0.2941,0.3996,0.5949",\
+"0.1730,0.1887,0.2043,0.2355,0.2824,0.3840,0.5793",\
+"0.1418,0.1574,0.1730,0.2043,0.2512,0.3566,0.5480",\
+"0.0949,0.1105,0.1262,0.1574,0.2043,0.3020,0.5051",\
+"-0.0066,0.0090,0.0246,0.0520,0.0988,0.2043,0.3996",\
+"-0.2020,-0.1863,-0.1746,-0.1434,-0.0965,0.0090,0.2082");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2980,0.3137,0.3254,0.3527,0.4035,0.5012,0.6887",\
+"0.2824,0.2980,0.3098,0.3371,0.3879,0.4855,0.6730",\
+"0.2668,0.2824,0.2941,0.3215,0.3723,0.4699,0.6574",\
+"0.2355,0.2473,0.2629,0.2902,0.3410,0.4387,0.6262",\
+"0.1887,0.2004,0.2160,0.2395,0.2941,0.3918,0.5793",\
+"0.0871,0.1027,0.1145,0.1418,0.1848,0.2746,0.4816",\
+"-0.1082,-0.0965,-0.0809,-0.0496,-0.0027,0.0949,0.2863");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2512,0.2355,0.2199,0.1926,0.1418,0.0402,-0.1590",\
+"0.2668,0.2512,0.2355,0.2082,0.1574,0.0559,-0.1434",\
+"0.2824,0.2629,0.2512,0.2199,0.1691,0.0715,-0.1316",\
+"0.3137,0.2980,0.2824,0.2512,0.2004,0.0988,-0.0965",\
+"0.3566,0.3410,0.3254,0.2980,0.2473,0.1418,-0.0535",\
+"0.4621,0.4426,0.4309,0.3996,0.3527,0.2473,0.0520",\
+"0.6574,0.6418,0.6262,0.5949,0.5441,0.4465,0.2473");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.2395,0.2238,0.2121,0.1809,0.1301,0.0324,-0.1551",\
+"0.2551,0.2434,0.2277,0.1965,0.1457,0.0480,-0.1395",\
+"0.2707,0.2551,0.2395,0.2082,0.1574,0.0637,-0.1277",\
+"0.3020,0.2863,0.2707,0.2434,0.1926,0.0910,-0.0965",\
+"0.3449,0.3332,0.3176,0.2863,0.2355,0.1379,-0.0496",\
+"0.4504,0.4348,0.4230,0.3918,0.3410,0.2434,0.0559",\
+"0.6457,0.6301,0.6145,0.5910,0.5324,0.4387,0.2512");
+		}
+	}
+	}
+bus(A_BIST_BM) {
+   bus_type : D_7_0;
+   direction          : input ;
+   capacitance        : 0.00236845 ;
+   max_transition     : "0.476" ;
+   pin(A_BIST_BM[7:0]) {
+   related_power_pin  : VDD;
+   related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0242);
+		}
+		        fall_power("scalar"){
+		 values (0.0193);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0257);
+		}
+		        fall_power("scalar"){
+		 values (0.0191);
+		}
+	}
+	}
+	timing() {
+		timing_type     : setup_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "(A_BIST_WEN & A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.3243,-0.3086,-0.2950,-0.2627,-0.2159,-0.1114,0.0800",\
+"-0.3293,-0.3136,-0.3000,-0.2677,-0.2209,-0.1164,0.0750",\
+"-0.3338,-0.3181,-0.3045,-0.2722,-0.2254,-0.1209,0.0705",\
+"-0.3435,-0.3279,-0.3142,-0.2820,-0.2351,-0.1306,0.0608",\
+"-0.3501,-0.3345,-0.3208,-0.2886,-0.2417,-0.1372,0.0542",\
+"-0.3811,-0.3654,-0.3518,-0.3195,-0.2727,-0.1682,0.0232",\
+"-0.4371,-0.4214,-0.4078,-0.3755,-0.3287,-0.2242,-0.0328");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("-0.2862,-0.2715,-0.2579,-0.2295,-0.1788,-0.0811,0.1015",\
+"-0.2912,-0.2765,-0.2629,-0.2345,-0.1838,-0.0861,0.0965",\
+"-0.2957,-0.2810,-0.2673,-0.2390,-0.1882,-0.0906,0.0920",\
+"-0.3054,-0.2908,-0.2771,-0.2488,-0.1980,-0.1004,0.0823",\
+"-0.3120,-0.2974,-0.2837,-0.2554,-0.2046,-0.1069,0.0757",\
+"-0.3430,-0.3283,-0.3147,-0.2863,-0.2356,-0.1379,0.0447",\
+"-0.3990,-0.3843,-0.3706,-0.3423,-0.2915,-0.1939,-0.0113");
+		}
+	}
+
+
+	timing() {
+		timing_type     : hold_rising;
+		related_pin     : "A_BIST_CLK";
+		when            : "(A_BIST_WEN & A_BIST_MEN)"
+		sdf_cond        : "A_BIST_RW_ACCESS"
+
+		rise_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.4332,0.4166,0.4039,0.3717,0.3238,0.2203,0.0279",\
+"0.4382,0.4216,0.4089,0.3767,0.3288,0.2253,0.0330",\
+"0.4427,0.4261,0.4134,0.3812,0.3333,0.2298,0.0374",\
+"0.4525,0.4359,0.4232,0.3909,0.3431,0.2396,0.0472",\
+"0.4590,0.4424,0.4297,0.3975,0.3496,0.2461,0.0538",\
+"0.4900,0.4734,0.4607,0.4285,0.3806,0.2771,0.0847",\
+"0.5460,0.5294,0.5167,0.4845,0.4366,0.3331,0.1407");
+		}
+
+		fall_constraint("SIG2SRAM_constraint_template") {
+		index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		values ("0.3873,0.3727,0.3590,0.3307,0.2809,0.1881,0.0035",\
+"0.3923,0.3777,0.3640,0.3357,0.2859,0.1931,0.0085",\
+"0.3968,0.3822,0.3685,0.3402,0.2904,0.1976,0.0130",\
+"0.4066,0.3919,0.3782,0.3499,0.3001,0.2073,0.0228",\
+"0.4131,0.3985,0.3848,0.3565,0.3067,0.2139,0.0293",\
+"0.4441,0.4295,0.4158,0.3875,0.3377,0.2449,0.0603",\
+"0.5001,0.4855,0.4718,0.4435,0.3937,0.3009,0.1163");
+		}
+	}
+}
+   pin(A_BIST_CLK)  {
+	   direction       : input;
+	   capacitance     : 0.00380014;
+	   max_transition  : "0.476";
+	   clock           : "true" ;
+	   pin_func_type   : active_rising ;
+
+	   timing () {
+		 timing_type : "min_pulse_width";
+		 related_pin : "A_BIST_CLK";
+		 rise_constraint("CLKTRAN_constraint_template") {
+		 index_1("0.0056,0.476");
+		 values("0.21,0.21");
+		 }
+	   }
+
+	   related_power_pin : VDD;
+	   related_ground_pin : VSS;
+
+	internal_power() {
+		when : "!A_BIST_MEN  & !A_BIST_WEN & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN  & A_BIST_WEN  & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (1.1525);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & A_BIST_WEN  & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (42.2119);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & A_BIST_WEN  & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (41.0961);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & !A_BIST_WEN & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (33.7167);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN & !A_BIST_WEN & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0.3256);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN & A_BIST_WEN  & A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0.5445);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	internal_power() {
+		when : "A_BIST_MEN  & !A_BIST_WEN & !A_BIST_REN";
+		        rise_power("scalar"){
+		 values (0);
+		}
+		        fall_power("scalar"){
+		 values (0);
+		}
+	}
+	}
+   bus(A_BIST_DIN) {
+	   bus_type : D_7_0;
+	   direction       : input ;
+	   capacitance     : 0.00232602 ;
+	   memory_write() {
+		   address : A_BIST_ADDR ;
+		   clocked_on : A_BIST_CLK;
+	   }
+
+	   max_transition  : "0.476" ;
+	   pin(A_BIST_DIN[7:0]) {
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+	internal_power() {
+		when : "A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0242);
+		}
+		        fall_power("scalar"){
+		 values (0.0193);
+		}
+	}
+	internal_power() {
+		when : "!A_BIST_MEN";
+		        rise_power("scalar"){
+		 values (0.0257);
+		}
+		        fall_power("scalar"){
+		 values (0.0191);
+		}
+	}
+	   }
+	   timing() {
+		 timing_type     : setup_rising;
+		 related_pin     : "A_BIST_CLK";
+		 when            : "(A_BIST_WEN & A_BIST_MEN)";
+		 sdf_cond        : "A_BIST_W_ACCESS";
+
+	  rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 values ("-0.3243,-0.3086,-0.2950,-0.2627,-0.2159,-0.1114,0.0800",\
+"-0.3293,-0.3136,-0.3000,-0.2677,-0.2209,-0.1164,0.0750",\
+"-0.3338,-0.3181,-0.3045,-0.2722,-0.2254,-0.1209,0.0705",\
+"-0.3435,-0.3279,-0.3142,-0.2820,-0.2351,-0.1306,0.0608",\
+"-0.3501,-0.3345,-0.3208,-0.2886,-0.2417,-0.1372,0.0542",\
+"-0.3811,-0.3654,-0.3518,-0.3195,-0.2727,-0.1682,0.0232",\
+"-0.4371,-0.4214,-0.4078,-0.3755,-0.3287,-0.2242,-0.0328");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 values ("-0.2862,-0.2715,-0.2579,-0.2295,-0.1788,-0.0811,0.1015",\
+"-0.2912,-0.2765,-0.2629,-0.2345,-0.1838,-0.0861,0.0965",\
+"-0.2957,-0.2810,-0.2673,-0.2390,-0.1882,-0.0906,0.0920",\
+"-0.3054,-0.2908,-0.2771,-0.2488,-0.1980,-0.1004,0.0823",\
+"-0.3120,-0.2974,-0.2837,-0.2554,-0.2046,-0.1069,0.0757",\
+"-0.3430,-0.3283,-0.3147,-0.2863,-0.2356,-0.1379,0.0447",\
+"-0.3990,-0.3843,-0.3706,-0.3423,-0.2915,-0.1939,-0.0113");
+		 }
+	   }
+
+	   timing() {
+		 timing_type     : hold_rising;
+		 related_pin     : "A_BIST_CLK";
+		 when            : "(A_BIST_WEN & A_BIST_MEN)";
+		 sdf_cond        : "A_BIST_W_ACCESS";
+
+	   rise_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 values ("0.4332,0.4166,0.4039,0.3717,0.3238,0.2203,0.0279",\
+"0.4382,0.4216,0.4089,0.3767,0.3288,0.2253,0.0330",\
+"0.4427,0.4261,0.4134,0.3812,0.3333,0.2298,0.0374",\
+"0.4525,0.4359,0.4232,0.3909,0.3431,0.2396,0.0472",\
+"0.4590,0.4424,0.4297,0.3975,0.3496,0.2461,0.0538",\
+"0.4900,0.4734,0.4607,0.4285,0.3806,0.2771,0.0847",\
+"0.5460,0.5294,0.5167,0.4845,0.4366,0.3331,0.1407");
+		 }
+
+	   fall_constraint("SIG2SRAM_constraint_template") {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 values ("0.3873,0.3727,0.3590,0.3307,0.2809,0.1881,0.0035",\
+"0.3923,0.3777,0.3640,0.3357,0.2859,0.1931,0.0085",\
+"0.3968,0.3822,0.3685,0.3402,0.2904,0.1976,0.0130",\
+"0.4066,0.3919,0.3782,0.3499,0.3001,0.2073,0.0228",\
+"0.4131,0.3985,0.3848,0.3565,0.3067,0.2139,0.0293",\
+"0.4441,0.4295,0.4158,0.3875,0.3377,0.2449,0.0603",\
+"0.5001,0.4855,0.4718,0.4435,0.3937,0.3009,0.1163");
+		 }
+	   }
+   }
+
+bus(A_DOUT) {
+
+	   bus_type : D_7_0;
+	   direction       : output ;
+	   capacitance     : 0 ;
+	   max_capacitance  : "6.4e-14" ;
+	   memory_read() {
+		  address : A_ADDR ;
+	   }
+	   pin(A_DOUT[7:0]) {
+		 related_power_pin : VDD;
+		 related_ground_pin : VSS;
+	   internal_power() {
+		  rise_power("scalar") {
+			 values (0);
+		  }
+		  fall_power("scalar") {
+			 values (0);
+		  }
+	   }
+	   }
+	   timing() {
+		 related_pin   : "A_CLK";
+		 timing_type   : rising_edge ;
+		 timing_sense  : non_unate ;
+
+	   cell_rise(SIG2SRAM_delay_template) {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("5.2741,5.2757,5.2834,5.2921,5.3245,5.3604",\
+"5.2853,5.2869,5.2946,5.3033,5.3357,5.3716",\
+"5.2840,5.2856,5.2932,5.3019,5.3344,5.3702",\
+"5.2970,5.2986,5.3063,5.3150,5.3474,5.3833",\
+"5.3048,5.3064,5.3141,5.3228,5.3552,5.3911",\
+"5.3374,5.3390,5.3466,5.3553,5.3878,5.4236",\
+"5.3913,5.3929,5.4006,5.4093,5.4417,5.4776");
+	   }
+	   cell_fall(SIG2SRAM_delay_template) {
+		 index_1("0.0056,0.0232,0.0400,0.0728,0.1280,0.2440,0.4760");
+		 index_2("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("5.2131,5.2144,5.2204,5.2275,5.2540,5.2807",\
+"5.2242,5.2256,5.2316,5.2387,5.2652,5.2918",\
+"5.2229,5.2242,5.2302,5.2374,5.2639,5.2905",\
+"5.2359,5.2373,5.2433,5.2504,5.2769,5.3036",\
+"5.2437,5.2450,5.2510,5.2582,5.2847,5.3113",\
+"5.2763,5.2776,5.2836,5.2908,5.3173,5.3439",\
+"5.3302,5.3315,5.3375,5.3447,5.3712,5.3978");
+	   }
+
+	   rise_transition(SRAM_load_template) {
+		 index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("0.0326,0.0341,0.0428,0.0518,0.0923,0.1492");
+	   }
+	   fall_transition(SRAM_load_template) {
+		 index_1("0.0008,0.0014,0.0051,0.0100,0.0339,0.0640");
+		 values ("0.0254,0.0265,0.0335,0.0402,0.0707,0.1039");
+	   }
+	}
+}
+cell_leakage_power : 396.0310;
+}
+}
diff --git a/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_1024x16_c2_bm_bist.v b/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_1024x16_c2_bm_bist.v
new file mode 100644
index 00000000..9f324fba
--- /dev/null
+++ b/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_1024x16_c2_bm_bist.v
@@ -0,0 +1,175 @@
+// ------------------------------------------------------
+//
+//		Copyright 2024 IHP PDK Authors
+//
+//		Licensed under the Apache License, Version 2.0 (the "License");
+//		you may not use this file except in compliance with the License.
+//		You may obtain a copy of the License at
+//		
+//		   https://www.apache.org/licenses/LICENSE-2.0
+//		
+//		Unless required by applicable law or agreed to in writing, software
+//		distributed under the License is distributed on an "AS IS" BASIS,
+//		WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+//		See the License for the specific language governing permissions and
+//		limitations under the License.
+//		
+//		Generated on Fri Jul 19 08:58:12 2024		
+//
+// ------------------------------------------------------ 
+`celldefine
+module RM_IHPSG13_1P_1024x16_c2_bm_bist (
+    A_CLK,
+    A_MEN,
+    A_WEN,
+    A_REN,
+    A_ADDR,
+    A_DIN,
+    A_DLY,
+    A_DOUT,
+    A_BM,
+    A_BIST_CLK,
+    A_BIST_EN,
+    A_BIST_MEN,
+    A_BIST_WEN,
+    A_BIST_REN,
+    A_BIST_ADDR,
+    A_BIST_DIN,
+    A_BIST_BM
+);
+
+    input A_CLK;
+    input A_MEN;
+    input A_WEN;
+    input A_REN;
+    input [9:0] A_ADDR;
+    input [15:0] A_DIN;
+    input A_DLY;
+    output [15:0] A_DOUT;
+    input [15:0] A_BM;
+    input A_BIST_CLK;
+    input A_BIST_EN;
+    input A_BIST_MEN;
+    input A_BIST_WEN;
+    input A_BIST_REN;
+    input [9:0] A_BIST_ADDR;
+    input [15:0] A_BIST_DIN;
+    input [15:0] A_BIST_BM;
+
+
+`ifdef FUNCTIONAL  //  functional //
+
+
+    SRAM_1P_behavioral_bm_bist #(
+	.P_DATA_WIDTH(16),
+	.P_ADDR_WIDTH(10)
+	) i_SRAM_1P_behavioral_bm_bist (
+                    .A_CLK(A_CLK),
+                    .A_MEN(A_MEN),
+                    .A_WEN(A_WEN),
+                    .A_REN(A_REN),
+                    .A_ADDR(A_ADDR),
+                    .A_DLY(A_DLY),
+                    .A_DIN(A_DIN),
+                    .A_DOUT(A_DOUT), 
+                    .A_BM(A_BM), 
+                    .A_BIST_CLK(A_BIST_CLK),
+                    .A_BIST_EN(A_BIST_EN),
+                    .A_BIST_MEN(A_BIST_MEN),
+                    .A_BIST_WEN(A_BIST_WEN),
+                    .A_BIST_REN(A_BIST_REN),
+                    .A_BIST_ADDR(A_BIST_ADDR),
+                    .A_BIST_DIN(A_BIST_DIN), 
+                    .A_BIST_BM(A_BIST_BM)
+		);
+
+`else
+
+    wire A_CLK_DELAY;
+    wire A_MEN_DELAY;
+    wire A_WEN_DELAY;
+    wire A_REN_DELAY;
+    wire [9:0] A_ADDR_DELAY;
+    wire [15:0] A_DIN_DELAY;
+    wire [15:0] A_BM_DELAY;
+    wire A_BIST_CLK_DELAY;
+    wire A_BIST_MEN_DELAY;
+    wire A_BIST_WEN_DELAY;
+    wire A_BIST_REN_DELAY;
+    wire [9:0] A_BIST_ADDR_DELAY;
+    wire [15:0] A_BIST_DIN_DELAY;
+    wire [15:0] A_BIST_BM_DELAY;
+
+    reg notifier;
+
+    wire A_RW_ACCESS = (A_WEN || A_REN) && A_MEN;
+    wire A_W_ACCESS  = A_WEN && A_MEN;
+    wire A_BIST_RW_ACCESS = (A_BIST_WEN || A_BIST_REN) && A_BIST_MEN;
+    wire A_BIST_W_ACCESS  = A_BIST_WEN && A_BIST_MEN;
+
+
+
+    SRAM_1P_behavioral_bm_bist #(
+	.P_DATA_WIDTH(16),
+	.P_ADDR_WIDTH(10)
+	) i_SRAM_1P_behavioral_bm_bist (
+                    .A_CLK(A_CLK_DELAY),
+                    .A_MEN(A_MEN_DELAY),
+                    .A_WEN(A_WEN_DELAY),
+                    .A_REN(A_REN_DELAY),
+                    .A_ADDR(A_ADDR_DELAY),
+                    .A_DLY(A_DLY),
+                    .A_DIN(A_DIN_DELAY),
+                    .A_DOUT(A_DOUT), 
+                    .A_BM(A_BM_DELAY), 
+                    .A_BIST_CLK(A_BIST_CLK_DELAY),
+                    .A_BIST_EN(A_BIST_EN),
+                    .A_BIST_MEN(A_BIST_MEN_DELAY),
+                    .A_BIST_WEN(A_BIST_WEN_DELAY),
+                    .A_BIST_REN(A_BIST_REN_DELAY),
+                    .A_BIST_ADDR(A_BIST_ADDR_DELAY),
+                    .A_BIST_DIN(A_BIST_DIN_DELAY), 
+                    .A_BIST_BM(A_BIST_BM_DELAY)
+		);
+
+
+    specify
+
+      (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0);
+      $width(posedge A_CLK, 1.0,0,notifier);
+      $setuphold(posedge A_CLK &&& A_MEN, posedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY);
+      $setuphold(posedge A_CLK &&& A_MEN, posedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY);
+      $setuphold(posedge A_CLK &&& A_MEN, posedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY);
+      $setuphold(posedge A_CLK &&& A_MEN, negedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY);
+      $setuphold(posedge A_CLK &&& A_MEN, negedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY);
+      $setuphold(posedge A_CLK &&& A_MEN, negedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY);
+      $setuphold(posedge A_CLK &&& A_RW_ACCESS, posedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY);
+      $setuphold(posedge A_CLK &&& A_RW_ACCESS, negedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY);
+
+      $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY);
+      $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY);
+      $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY);
+      $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY);
+      (posedge A_BIST_CLK *> (A_DOUT : A_BIST_DIN)) = (1.0, 1.0);
+      $width(posedge A_BIST_CLK, 1.0,0,notifier);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, posedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, negedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY);
+
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY);
+
+
+    endspecify
+
+`endif
+
+endmodule
+`endcelldefine
\ No newline at end of file
diff --git a/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_1024x8_c2_bm_bist.v b/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_1024x8_c2_bm_bist.v
new file mode 100644
index 00000000..94a7d0ae
--- /dev/null
+++ b/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_1024x8_c2_bm_bist.v
@@ -0,0 +1,175 @@
+// ------------------------------------------------------
+//
+//		Copyright 2024 IHP PDK Authors
+//
+//		Licensed under the Apache License, Version 2.0 (the "License");
+//		you may not use this file except in compliance with the License.
+//		You may obtain a copy of the License at
+//		
+//		   https://www.apache.org/licenses/LICENSE-2.0
+//		
+//		Unless required by applicable law or agreed to in writing, software
+//		distributed under the License is distributed on an "AS IS" BASIS,
+//		WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+//		See the License for the specific language governing permissions and
+//		limitations under the License.
+//		
+//		Generated on Fri Jul 19 09:01:22 2024		
+//
+// ------------------------------------------------------ 
+`celldefine
+module RM_IHPSG13_1P_1024x8_c2_bm_bist (
+    A_CLK,
+    A_MEN,
+    A_WEN,
+    A_REN,
+    A_ADDR,
+    A_DIN,
+    A_DLY,
+    A_DOUT,
+    A_BM,
+    A_BIST_CLK,
+    A_BIST_EN,
+    A_BIST_MEN,
+    A_BIST_WEN,
+    A_BIST_REN,
+    A_BIST_ADDR,
+    A_BIST_DIN,
+    A_BIST_BM
+);
+
+    input A_CLK;
+    input A_MEN;
+    input A_WEN;
+    input A_REN;
+    input [9:0] A_ADDR;
+    input [7:0] A_DIN;
+    input A_DLY;
+    output [7:0] A_DOUT;
+    input [7:0] A_BM;
+    input A_BIST_CLK;
+    input A_BIST_EN;
+    input A_BIST_MEN;
+    input A_BIST_WEN;
+    input A_BIST_REN;
+    input [9:0] A_BIST_ADDR;
+    input [7:0] A_BIST_DIN;
+    input [7:0] A_BIST_BM;
+
+
+`ifdef FUNCTIONAL  //  functional //
+
+
+    SRAM_1P_behavioral_bm_bist #(
+	.P_DATA_WIDTH(8),
+	.P_ADDR_WIDTH(10)
+	) i_SRAM_1P_behavioral_bm_bist (
+                    .A_CLK(A_CLK),
+                    .A_MEN(A_MEN),
+                    .A_WEN(A_WEN),
+                    .A_REN(A_REN),
+                    .A_ADDR(A_ADDR),
+                    .A_DLY(A_DLY),
+                    .A_DIN(A_DIN),
+                    .A_DOUT(A_DOUT), 
+                    .A_BM(A_BM), 
+                    .A_BIST_CLK(A_BIST_CLK),
+                    .A_BIST_EN(A_BIST_EN),
+                    .A_BIST_MEN(A_BIST_MEN),
+                    .A_BIST_WEN(A_BIST_WEN),
+                    .A_BIST_REN(A_BIST_REN),
+                    .A_BIST_ADDR(A_BIST_ADDR),
+                    .A_BIST_DIN(A_BIST_DIN), 
+                    .A_BIST_BM(A_BIST_BM)
+		);
+
+`else
+
+    wire A_CLK_DELAY;
+    wire A_MEN_DELAY;
+    wire A_WEN_DELAY;
+    wire A_REN_DELAY;
+    wire [9:0] A_ADDR_DELAY;
+    wire [7:0] A_DIN_DELAY;
+    wire [7:0] A_BM_DELAY;
+    wire A_BIST_CLK_DELAY;
+    wire A_BIST_MEN_DELAY;
+    wire A_BIST_WEN_DELAY;
+    wire A_BIST_REN_DELAY;
+    wire [9:0] A_BIST_ADDR_DELAY;
+    wire [7:0] A_BIST_DIN_DELAY;
+    wire [7:0] A_BIST_BM_DELAY;
+
+    reg notifier;
+
+    wire A_RW_ACCESS = (A_WEN || A_REN) && A_MEN;
+    wire A_W_ACCESS  = A_WEN && A_MEN;
+    wire A_BIST_RW_ACCESS = (A_BIST_WEN || A_BIST_REN) && A_BIST_MEN;
+    wire A_BIST_W_ACCESS  = A_BIST_WEN && A_BIST_MEN;
+
+
+
+    SRAM_1P_behavioral_bm_bist #(
+	.P_DATA_WIDTH(8),
+	.P_ADDR_WIDTH(10)
+	) i_SRAM_1P_behavioral_bm_bist (
+                    .A_CLK(A_CLK_DELAY),
+                    .A_MEN(A_MEN_DELAY),
+                    .A_WEN(A_WEN_DELAY),
+                    .A_REN(A_REN_DELAY),
+                    .A_ADDR(A_ADDR_DELAY),
+                    .A_DLY(A_DLY),
+                    .A_DIN(A_DIN_DELAY),
+                    .A_DOUT(A_DOUT), 
+                    .A_BM(A_BM_DELAY), 
+                    .A_BIST_CLK(A_BIST_CLK_DELAY),
+                    .A_BIST_EN(A_BIST_EN),
+                    .A_BIST_MEN(A_BIST_MEN_DELAY),
+                    .A_BIST_WEN(A_BIST_WEN_DELAY),
+                    .A_BIST_REN(A_BIST_REN_DELAY),
+                    .A_BIST_ADDR(A_BIST_ADDR_DELAY),
+                    .A_BIST_DIN(A_BIST_DIN_DELAY), 
+                    .A_BIST_BM(A_BIST_BM_DELAY)
+		);
+
+
+    specify
+
+      (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0);
+      $width(posedge A_CLK, 1.0,0,notifier);
+      $setuphold(posedge A_CLK &&& A_MEN, posedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY);
+      $setuphold(posedge A_CLK &&& A_MEN, posedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY);
+      $setuphold(posedge A_CLK &&& A_MEN, posedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY);
+      $setuphold(posedge A_CLK &&& A_MEN, negedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY);
+      $setuphold(posedge A_CLK &&& A_MEN, negedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY);
+      $setuphold(posedge A_CLK &&& A_MEN, negedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY);
+      $setuphold(posedge A_CLK &&& A_RW_ACCESS, posedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY);
+      $setuphold(posedge A_CLK &&& A_RW_ACCESS, negedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY);
+
+      $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY);
+      $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY);
+      $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY);
+      $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY);
+      (posedge A_BIST_CLK *> (A_DOUT : A_BIST_DIN)) = (1.0, 1.0);
+      $width(posedge A_BIST_CLK, 1.0,0,notifier);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, posedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, negedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY);
+
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY);
+
+
+    endspecify
+
+`endif
+
+endmodule
+`endcelldefine
\ No newline at end of file
diff --git a/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_4096x16_c3_bm_bist.v b/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_4096x16_c3_bm_bist.v
new file mode 100644
index 00000000..0a96fc04
--- /dev/null
+++ b/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_4096x16_c3_bm_bist.v
@@ -0,0 +1,175 @@
+// ------------------------------------------------------
+//
+//		Copyright 2024 IHP PDK Authors
+//
+//		Licensed under the Apache License, Version 2.0 (the "License");
+//		you may not use this file except in compliance with the License.
+//		You may obtain a copy of the License at
+//		
+//		   https://www.apache.org/licenses/LICENSE-2.0
+//		
+//		Unless required by applicable law or agreed to in writing, software
+//		distributed under the License is distributed on an "AS IS" BASIS,
+//		WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+//		See the License for the specific language governing permissions and
+//		limitations under the License.
+//		
+//		Generated on Fri Jul 12 17:37:43 2024		
+//
+// ------------------------------------------------------ 
+`celldefine
+module RM_IHPSG13_1P_4096x16_c3_bm_bist (
+    A_CLK,
+    A_MEN,
+    A_WEN,
+    A_REN,
+    A_ADDR,
+    A_DIN,
+    A_DLY,
+    A_DOUT,
+    A_BM,
+    A_BIST_CLK,
+    A_BIST_EN,
+    A_BIST_MEN,
+    A_BIST_WEN,
+    A_BIST_REN,
+    A_BIST_ADDR,
+    A_BIST_DIN,
+    A_BIST_BM
+);
+
+    input A_CLK;
+    input A_MEN;
+    input A_WEN;
+    input A_REN;
+    input [11:0] A_ADDR;
+    input [15:0] A_DIN;
+    input A_DLY;
+    output [15:0] A_DOUT;
+    input [15:0] A_BM;
+    input A_BIST_CLK;
+    input A_BIST_EN;
+    input A_BIST_MEN;
+    input A_BIST_WEN;
+    input A_BIST_REN;
+    input [11:0] A_BIST_ADDR;
+    input [15:0] A_BIST_DIN;
+    input [15:0] A_BIST_BM;
+
+
+`ifdef FUNCTIONAL  //  functional //
+
+
+    SRAM_1P_behavioral_bm_bist #(
+	.P_DATA_WIDTH(16),
+	.P_ADDR_WIDTH(12)
+	) i_SRAM_1P_behavioral_bm_bist (
+                    .A_CLK(A_CLK),
+                    .A_MEN(A_MEN),
+                    .A_WEN(A_WEN),
+                    .A_REN(A_REN),
+                    .A_ADDR(A_ADDR),
+                    .A_DLY(A_DLY),
+                    .A_DIN(A_DIN),
+                    .A_DOUT(A_DOUT), 
+                    .A_BM(A_BM), 
+                    .A_BIST_CLK(A_BIST_CLK),
+                    .A_BIST_EN(A_BIST_EN),
+                    .A_BIST_MEN(A_BIST_MEN),
+                    .A_BIST_WEN(A_BIST_WEN),
+                    .A_BIST_REN(A_BIST_REN),
+                    .A_BIST_ADDR(A_BIST_ADDR),
+                    .A_BIST_DIN(A_BIST_DIN), 
+                    .A_BIST_BM(A_BIST_BM)
+		);
+
+`else
+
+    wire A_CLK_DELAY;
+    wire A_MEN_DELAY;
+    wire A_WEN_DELAY;
+    wire A_REN_DELAY;
+    wire [11:0] A_ADDR_DELAY;
+    wire [15:0] A_DIN_DELAY;
+    wire [15:0] A_BM_DELAY;
+    wire A_BIST_CLK_DELAY;
+    wire A_BIST_MEN_DELAY;
+    wire A_BIST_WEN_DELAY;
+    wire A_BIST_REN_DELAY;
+    wire [11:0] A_BIST_ADDR_DELAY;
+    wire [15:0] A_BIST_DIN_DELAY;
+    wire [15:0] A_BIST_BM_DELAY;
+
+    reg notifier;
+
+    wire A_RW_ACCESS = (A_WEN || A_REN) && A_MEN;
+    wire A_W_ACCESS  = A_WEN && A_MEN;
+    wire A_BIST_RW_ACCESS = (A_BIST_WEN || A_BIST_REN) && A_BIST_MEN;
+    wire A_BIST_W_ACCESS  = A_BIST_WEN && A_BIST_MEN;
+
+
+
+    SRAM_1P_behavioral_bm_bist #(
+	.P_DATA_WIDTH(16),
+	.P_ADDR_WIDTH(12)
+	) i_SRAM_1P_behavioral_bm_bist (
+                    .A_CLK(A_CLK_DELAY),
+                    .A_MEN(A_MEN_DELAY),
+                    .A_WEN(A_WEN_DELAY),
+                    .A_REN(A_REN_DELAY),
+                    .A_ADDR(A_ADDR_DELAY),
+                    .A_DLY(A_DLY),
+                    .A_DIN(A_DIN_DELAY),
+                    .A_DOUT(A_DOUT), 
+                    .A_BM(A_BM_DELAY), 
+                    .A_BIST_CLK(A_BIST_CLK_DELAY),
+                    .A_BIST_EN(A_BIST_EN),
+                    .A_BIST_MEN(A_BIST_MEN_DELAY),
+                    .A_BIST_WEN(A_BIST_WEN_DELAY),
+                    .A_BIST_REN(A_BIST_REN_DELAY),
+                    .A_BIST_ADDR(A_BIST_ADDR_DELAY),
+                    .A_BIST_DIN(A_BIST_DIN_DELAY), 
+                    .A_BIST_BM(A_BIST_BM_DELAY)
+		);
+
+
+    specify
+
+      (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0);
+      $width(posedge A_CLK, 1.0,0,notifier);
+      $setuphold(posedge A_CLK &&& A_MEN, posedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY);
+      $setuphold(posedge A_CLK &&& A_MEN, posedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY);
+      $setuphold(posedge A_CLK &&& A_MEN, posedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY);
+      $setuphold(posedge A_CLK &&& A_MEN, negedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY);
+      $setuphold(posedge A_CLK &&& A_MEN, negedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY);
+      $setuphold(posedge A_CLK &&& A_MEN, negedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY);
+      $setuphold(posedge A_CLK &&& A_RW_ACCESS, posedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY);
+      $setuphold(posedge A_CLK &&& A_RW_ACCESS, negedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY);
+
+      $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY);
+      $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY);
+      $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY);
+      $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY);
+      (posedge A_BIST_CLK *> (A_DOUT : A_BIST_DIN)) = (1.0, 1.0);
+      $width(posedge A_BIST_CLK, 1.0,0,notifier);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, posedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, negedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY);
+
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY);
+
+
+    endspecify
+
+`endif
+
+endmodule
+`endcelldefine
\ No newline at end of file
diff --git a/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_4096x8_c3_bm_bist.v b/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_4096x8_c3_bm_bist.v
new file mode 100644
index 00000000..af3029d5
--- /dev/null
+++ b/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_4096x8_c3_bm_bist.v
@@ -0,0 +1,175 @@
+// ------------------------------------------------------
+//
+//		Copyright 2024 IHP PDK Authors
+//
+//		Licensed under the Apache License, Version 2.0 (the "License");
+//		you may not use this file except in compliance with the License.
+//		You may obtain a copy of the License at
+//		
+//		   https://www.apache.org/licenses/LICENSE-2.0
+//		
+//		Unless required by applicable law or agreed to in writing, software
+//		distributed under the License is distributed on an "AS IS" BASIS,
+//		WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+//		See the License for the specific language governing permissions and
+//		limitations under the License.
+//		
+//		Generated on Fri Jul 19 08:59:30 2024		
+//
+// ------------------------------------------------------ 
+`celldefine
+module RM_IHPSG13_1P_4096x8_c3_bm_bist (
+    A_CLK,
+    A_MEN,
+    A_WEN,
+    A_REN,
+    A_ADDR,
+    A_DIN,
+    A_DLY,
+    A_DOUT,
+    A_BM,
+    A_BIST_CLK,
+    A_BIST_EN,
+    A_BIST_MEN,
+    A_BIST_WEN,
+    A_BIST_REN,
+    A_BIST_ADDR,
+    A_BIST_DIN,
+    A_BIST_BM
+);
+
+    input A_CLK;
+    input A_MEN;
+    input A_WEN;
+    input A_REN;
+    input [11:0] A_ADDR;
+    input [7:0] A_DIN;
+    input A_DLY;
+    output [7:0] A_DOUT;
+    input [7:0] A_BM;
+    input A_BIST_CLK;
+    input A_BIST_EN;
+    input A_BIST_MEN;
+    input A_BIST_WEN;
+    input A_BIST_REN;
+    input [11:0] A_BIST_ADDR;
+    input [7:0] A_BIST_DIN;
+    input [7:0] A_BIST_BM;
+
+
+`ifdef FUNCTIONAL  //  functional //
+
+
+    SRAM_1P_behavioral_bm_bist #(
+	.P_DATA_WIDTH(8),
+	.P_ADDR_WIDTH(12)
+	) i_SRAM_1P_behavioral_bm_bist (
+                    .A_CLK(A_CLK),
+                    .A_MEN(A_MEN),
+                    .A_WEN(A_WEN),
+                    .A_REN(A_REN),
+                    .A_ADDR(A_ADDR),
+                    .A_DLY(A_DLY),
+                    .A_DIN(A_DIN),
+                    .A_DOUT(A_DOUT), 
+                    .A_BM(A_BM), 
+                    .A_BIST_CLK(A_BIST_CLK),
+                    .A_BIST_EN(A_BIST_EN),
+                    .A_BIST_MEN(A_BIST_MEN),
+                    .A_BIST_WEN(A_BIST_WEN),
+                    .A_BIST_REN(A_BIST_REN),
+                    .A_BIST_ADDR(A_BIST_ADDR),
+                    .A_BIST_DIN(A_BIST_DIN), 
+                    .A_BIST_BM(A_BIST_BM)
+		);
+
+`else
+
+    wire A_CLK_DELAY;
+    wire A_MEN_DELAY;
+    wire A_WEN_DELAY;
+    wire A_REN_DELAY;
+    wire [11:0] A_ADDR_DELAY;
+    wire [7:0] A_DIN_DELAY;
+    wire [7:0] A_BM_DELAY;
+    wire A_BIST_CLK_DELAY;
+    wire A_BIST_MEN_DELAY;
+    wire A_BIST_WEN_DELAY;
+    wire A_BIST_REN_DELAY;
+    wire [11:0] A_BIST_ADDR_DELAY;
+    wire [7:0] A_BIST_DIN_DELAY;
+    wire [7:0] A_BIST_BM_DELAY;
+
+    reg notifier;
+
+    wire A_RW_ACCESS = (A_WEN || A_REN) && A_MEN;
+    wire A_W_ACCESS  = A_WEN && A_MEN;
+    wire A_BIST_RW_ACCESS = (A_BIST_WEN || A_BIST_REN) && A_BIST_MEN;
+    wire A_BIST_W_ACCESS  = A_BIST_WEN && A_BIST_MEN;
+
+
+
+    SRAM_1P_behavioral_bm_bist #(
+	.P_DATA_WIDTH(8),
+	.P_ADDR_WIDTH(12)
+	) i_SRAM_1P_behavioral_bm_bist (
+                    .A_CLK(A_CLK_DELAY),
+                    .A_MEN(A_MEN_DELAY),
+                    .A_WEN(A_WEN_DELAY),
+                    .A_REN(A_REN_DELAY),
+                    .A_ADDR(A_ADDR_DELAY),
+                    .A_DLY(A_DLY),
+                    .A_DIN(A_DIN_DELAY),
+                    .A_DOUT(A_DOUT), 
+                    .A_BM(A_BM_DELAY), 
+                    .A_BIST_CLK(A_BIST_CLK_DELAY),
+                    .A_BIST_EN(A_BIST_EN),
+                    .A_BIST_MEN(A_BIST_MEN_DELAY),
+                    .A_BIST_WEN(A_BIST_WEN_DELAY),
+                    .A_BIST_REN(A_BIST_REN_DELAY),
+                    .A_BIST_ADDR(A_BIST_ADDR_DELAY),
+                    .A_BIST_DIN(A_BIST_DIN_DELAY), 
+                    .A_BIST_BM(A_BIST_BM_DELAY)
+		);
+
+
+    specify
+
+      (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0);
+      $width(posedge A_CLK, 1.0,0,notifier);
+      $setuphold(posedge A_CLK &&& A_MEN, posedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY);
+      $setuphold(posedge A_CLK &&& A_MEN, posedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY);
+      $setuphold(posedge A_CLK &&& A_MEN, posedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY);
+      $setuphold(posedge A_CLK &&& A_MEN, negedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY);
+      $setuphold(posedge A_CLK &&& A_MEN, negedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY);
+      $setuphold(posedge A_CLK &&& A_MEN, negedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY);
+      $setuphold(posedge A_CLK &&& A_RW_ACCESS, posedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY);
+      $setuphold(posedge A_CLK &&& A_RW_ACCESS, negedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY);
+
+      $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY);
+      $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY);
+      $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY);
+      $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY);
+      (posedge A_BIST_CLK *> (A_DOUT : A_BIST_DIN)) = (1.0, 1.0);
+      $width(posedge A_BIST_CLK, 1.0,0,notifier);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, posedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, negedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY);
+
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY);
+      $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY);
+
+
+    endspecify
+
+`endif
+
+endmodule
+`endcelldefine
\ No newline at end of file
diff --git a/ihp-sg13g2/libs.ref/sg13g2_stdcell/lef/sg13g2_stdcell.lef b/ihp-sg13g2/libs.ref/sg13g2_stdcell/lef/sg13g2_stdcell.lef
index 01c62c6e..cf28f6ae 100644
--- a/ihp-sg13g2/libs.ref/sg13g2_stdcell/lef/sg13g2_stdcell.lef
+++ b/ihp-sg13g2/libs.ref/sg13g2_stdcell/lef/sg13g2_stdcell.lef
@@ -4524,7 +4524,7 @@ MACRO sg13g2_nand2b_1
   SITE CoreSite ;
   PIN Y
     DIRECTION OUTPUT ;
-    USE ANALOG ;
+    USE SIGNAL ;
     ANTENNADIFFAREA 0.6772 LAYER Metal1 ;
     PORT
       LAYER Metal1 ;
@@ -4536,7 +4536,7 @@ MACRO sg13g2_nand2b_1
   END Y
   PIN B
     DIRECTION INPUT ;
-    USE ANALOG ;
+    USE SIGNAL ;
     ANTENNAMODEL OXIDE1 ;
       ANTENNAGATEAREA 0.2418 LAYER Metal1 ;
     PORT
@@ -4546,7 +4546,7 @@ MACRO sg13g2_nand2b_1
   END B
   PIN A_N
     DIRECTION INPUT ;
-    USE ANALOG ;
+    USE SIGNAL ;
     ANTENNAMODEL OXIDE1 ;
       ANTENNAGATEAREA 0.1807 LAYER Metal1 ;
     PORT
@@ -5692,7 +5692,7 @@ MACRO sg13g2_or2_1
   END X
   PIN B
     DIRECTION INPUT ;
-    USE ANALOG ;
+    USE SIGNAL ;
     ANTENNAMODEL OXIDE1 ;
       ANTENNAGATEAREA 0.1807 LAYER Metal1 ;
     PORT
@@ -5703,7 +5703,7 @@ MACRO sg13g2_or2_1
   END B
   PIN A
     DIRECTION INPUT ;
-    USE ANALOG ;
+    USE SIGNAL ;
     ANTENNAMODEL OXIDE1 ;
       ANTENNAGATEAREA 0.1807 LAYER Metal1 ;
     PORT
@@ -5769,7 +5769,7 @@ MACRO sg13g2_or2_2
   END X
   PIN B
     DIRECTION INPUT ;
-    USE ANALOG ;
+    USE SIGNAL ;
     ANTENNAMODEL OXIDE1 ;
       ANTENNAGATEAREA 0.1807 LAYER Metal1 ;
     PORT
@@ -5780,7 +5780,7 @@ MACRO sg13g2_or2_2
   END B
   PIN A
     DIRECTION INPUT ;
-    USE ANALOG ;
+    USE SIGNAL ;
     ANTENNAMODEL OXIDE1 ;
       ANTENNAGATEAREA 0.1807 LAYER Metal1 ;
     PORT
diff --git a/ihp-sg13g2/libs.tech/digital b/ihp-sg13g2/libs.tech/digital
new file mode 160000
index 00000000..9a6e7c9d
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/digital
@@ -0,0 +1 @@
+Subproject commit 9a6e7c9d404f9f4334513a24788aa8454918d400
diff --git a/ihp-sg13g2/libs.tech/klayout/python/cni/box.py b/ihp-sg13g2/libs.tech/klayout/python/cni/box.py
deleted file mode 100644
index cc596e19..00000000
--- a/ihp-sg13g2/libs.tech/klayout/python/cni/box.py
+++ /dev/null
@@ -1,327 +0,0 @@
-########################################################################
-#
-# Copyright 2024 IHP PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#    https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-########################################################################
-
-from cni.constants import *
-from cni.location import *
-from cni.point import *
-from cni.namemapper import *
-from cni.transform import *
-
-import pya
-
-class Box(object):
-
-    def __init__(self, l = INT_MAX, b = INT_MAX, r = INT_MIN, t = INT_MIN):
-        self.box = pya.DBox(l, b, r, t)
-
-    def abut(dir, refBox, align = True):
-        raise Exception("Not implemented yet!")
-
-    def alignEdge(dir, refBox, refDir=None, offset=None):
-        raise Exception("Not implemented yet!")
-
-    def alignEdgeToCoord(dir, coord):
-        raise Exception("Not implemented yet!")
-
-    def alignEdgeToPoint(dir, point):
-        raise Exception("Not implemented yet!")
-
-    def alignLocation(loc, refBox, refLoc=None, offset=None):
-        raise Exception("Not implemented yet!")
-
-    def alignLocationToPoint(loc, pt):
-        raise Exception("Not implemented yet!")
-
-    def centerCenter():
-        raise Exception("Not implemented yet!")
-
-    def centerLeft():
-        raise Exception("Not implemented yet!")
-
-    def centerRight():
-        raise Exception("Not implemented yet!")
-
-    def clone(self, nameMap : NameMapper = NameMapper(), netMap : NameMapper = NameMapper()):
-        return Box(self.box.left, self.box.bottom, self.box.right, self.box.top)
-
-    def contains(box, incEdges = True):
-        raise Exception("Not implemented yet!")
-
-    def containsPoint(p, incEdges = True):
-        raise Exception("Not implemented yet!")
-
-    def destroy(self):
-        if not self.box._destroyed():
-            import cni.shape
-            cni.shape.Shape.getCell().shapes(self.__rect.getShape().layer).erase(self.__rect.getShape())
-            self.box._destroy()
-        else:
-            pya.Logger.warn(f"Box.destroy: already destroyed!")
-
-    def expand(coord):
-        raise Exception("Not implemented yet!")
-
-    def expandDir(dir, coord):
-        raise Exception("Not implemented yet!")
-
-    def expandForMinArea(dir, minArea, grid = None):
-        raise Exception("Not implemented yet!")
-
-    def expandForMinWidth(dir, minWidth, grid = None):
-        raise Exception("Not implemented yet!")
-
-    def expandToGrid(grid, dir = None):
-        raise Exception("Not implemented yet!")
-
-    def fix(self):
-        # is that function supposed for normalize the order?
-        return self
-
-    def getArea():
-        raise Exception("Not implemented yet!")
-
-    def getCenter():
-        raise Exception("Not implemented yet!")
-
-    def getCenterX():
-        raise Exception("Not implemented yet!")
-
-    def getCenterY():
-        raise Exception("Not implemented yet!")
-
-    def getCoord(dir):
-        raise Exception("Not implemented yet!")
-
-    def getDimension(dir):
-        raise Exception("Not implemented yet!")
-
-    def getHeight(self):
-        return self.box.top - self.box.bottom
-
-    def getLeft():
-        raise Exception("Not implemented yet!")
-
-    def getLocationPoint(loc):
-        raise Exception("Not implemented yet!")
-
-    def getLocationPoint(dir):
-        raise Exception("Not implemented yet!")
-
-    def getPoints():
-        raise Exception("Not implemented yet!")
-
-    def getRange(dir):
-        raise Exception("Not implemented yet!")
-
-    def getRangeX():
-        raise Exception("Not implemented yet!")
-
-    def getRangeY():
-        raise Exception("Not implemented yet!")
-
-    def getRight():
-        raise Exception("Not implemented yet!")
-
-    def getSpacing(dir, refBox):
-        raise Exception("Not implemented yet!")
-
-    def getTop():
-        raise Exception("Not implemented yet!")
-
-    def getWidth(self):
-        return self.box.right - self.box.left
-
-    def hasNoArea():
-        raise Exception("Not implemented yet!")
-
-    def init():
-        raise Exception("Not implemented yet!")
-
-    def intersect(box):
-        raise Exception("Not implemented yet!")
-
-    def intersect(box, dir):
-        raise Exception("Not implemented yet!")
-
-    def isInverted():
-        raise Exception("Not implemented yet!")
-
-    def isNormal():
-        raise Exception("Not implemented yet!")
-
-    def limit(point):
-        raise Exception("Not implemented yet!")
-
-    def lowerCenter():
-        raise Exception("Not implemented yet!")
-
-    def lowerLeft(self):
-        return Point(self.box.left, self.box.bottom)
-
-    def lowerRight():
-        raise Exception("Not implemented yet!")
-
-    def merge(box, dir):
-        raise Exception("Not implemented yet!")
-
-    def mergePoint(p):
-        raise Exception("Not implemented yet!")
-
-    def mirrorX(yCoord = 0):
-        raise Exception("Not implemented yet!")
-
-    def mirrorY(xCoord = 0):
-        raise Exception("Not implemented yet!")
-
-    def moveBy(self, dx: float, dy: float) -> None:
-        movedBox = pya.DTrans(dx, dy) * self.box
-        import cni.shape
-        shape = cni.shape.Shape.getCell().shapes(self.__rect._shape.layer).insert(movedBox)
-        self.destroy()
-        self.__rect._shape = shape
-        self.box = movedBox
-
-    def moveTo(destination, loc = Location.CENTER_CENTER):
-        raise Exception("Not implemented yet!")
-
-    def moveTowards(dir, d):
-        raise Exception("Not implemented yet!")
-
-    def overlaps(box, incEdges = True):
-        raise Exception("Not implemented yet!")
-
-    def place(dir, refBox, distance, align = True):
-        raise Exception("Not implemented yet!")
-
-    def removeRegion(box):
-        raise Exception("Not implemented yet!")
-
-    def rotate90(origin = None):
-        raise Exception("Not implemented yet!")
-
-    def rotate180(origin = None):
-        raise Exception("Not implemented yet!")
-
-    def rotate270(origin = None):
-        raise Exception("Not implemented yet!")
-
-    def set(b):
-        raise Exception("Not implemented yet!")
-
-    def set(b, dir = None):
-        raise Exception("Not implemented yet!")
-
-    def set(lowerLeft, upperRight):
-        raise Exception("Not implemented yet!")
-
-    def set(left, bottom, right, top):
-        raise Exception("Not implemented yet!")
-
-    def setBottom(v):
-        raise Exception("Not implemented yet!")
-
-    def setCenter(point):
-        raise Exception("Not implemented yet!")
-
-    def setCenterY(v):
-        raise Exception("Not implemented yet!")
-
-    def setCoord(dir, coord):
-        raise Exception("Not implemented yet!")
-
-    def setDimension(coord, dir):
-        raise Exception("Not implemented yet!")
-
-    def setBottom(v):
-        raise Exception("Not implemented yet!")
-
-    def setHeight(height):
-        raise Exception("Not implemented yet!")
-
-    def setLocationPoint(loc, pt):
-        raise Exception("Not implemented yet!")
-
-    def setRange(dir, range):
-        raise Exception("Not implemented yet!")
-
-    def setRangeX(range):
-        raise Exception("Not implemented yet!")
-
-    def setRangeY(range):
-        raise Exception("Not implemented yet!")
-
-    def setRect(self, rect):
-        self.__rect = rect
-
-    def setRight(v):
-        raise Exception("Not implemented yet!")
-
-    def setTop(v):
-        raise Exception("Not implemented yet!")
-
-    def setWidth(width):
-        raise Exception("Not implemented yet!")
-
-    def snap(grid, snapType = None):
-        raise Exception("Not implemented yet!")
-
-    def snapX(grid, snapType = None):
-        raise Exception("Not implemented yet!")
-
-    def snapY(grid, snapType = None):
-        raise Exception("Not implemented yet!")
-
-    def snapTowards(grid, dir):
-        raise Exception("Not implemented yet!")
-
-    def transform(self, transform: Transform) -> None:
-        if self.__rect is None:
-            raise Exception("No rect set for box!")
-
-        transformedBox = self.box.transformed(transform.transform)
-        import cni.shape
-        shape = cni.shape.Shape.getCell().shapes(self.__rect._shape.layer).insert(transformedBox)
-        self.destroy()
-        self.__rect._shape = shape
-        self.box = transformedBox
-
-    def upperCenter():
-        raise Exception("Not implemented yet!")
-
-    def upperLeft():
-        raise Exception("Not implemented yet!")
-
-    def upperRight(self):
-        return Point(self.box.right, self.box.top)
-
-    @property
-    def bottom(self):
-        return self.box.bottom
-
-    @property
-    def left(self):
-        return self.box.left
-
-    @property
-    def right(self):
-        return self.box.right
-
-    @property
-    def top(self):
-        return self.box.top
-
diff --git a/ihp-sg13g2/libs.tech/klayout/python/cni/constants.py b/ihp-sg13g2/libs.tech/klayout/python/cni/constants.py
deleted file mode 100644
index 66ada205..00000000
--- a/ihp-sg13g2/libs.tech/klayout/python/cni/constants.py
+++ /dev/null
@@ -1,25 +0,0 @@
-########################################################################
-#
-# Copyright 2024 IHP PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#    https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-########################################################################
-
-import sys
-
-REJECT = 1
-ACCEPT = 2
-USE_DEFAULT = 3
-INT_MAX = sys.maxsize
-INT_MIN = -sys.maxsize-1
diff --git a/ihp-sg13g2/libs.tech/klayout/python/cni/dlo.py b/ihp-sg13g2/libs.tech/klayout/python/cni/dlo.py
deleted file mode 100644
index feec0cf8..00000000
--- a/ihp-sg13g2/libs.tech/klayout/python/cni/dlo.py
+++ /dev/null
@@ -1,182 +0,0 @@
-########################################################################
-#
-# Copyright 2024 IHP PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#    https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-########################################################################
-
-from __future__ import annotations
-
-from cni.constants import *
-from cni.numeric import *
-from cni.orientation import *
-from cni.location import *
-from cni.layer import *
-from cni.pathstyle import *
-from cni.signaltype import *
-from cni.termtype import *
-from cni.font import *
-from cni.point import *
-from cni.pointlist import *
-from cni.box import *
-from cni.shape import *
-from cni.text import *
-from cni.polygon import *
-from cni.dlogen import *
-from cni.transform import *
-from cni.instance import *
-from cni.paramarray import *
-
-import pya
-import sys
-
-class ChoiceConstraint(list):
-
-    def __init__(self, choices, action = REJECT):
-        super().__init__(choices)
-
-
-class RangeConstraint:
-
-    def __init__(self, low, high, resolution = None, action = REJECT):
-        self.low = low
-        self.high = high
-        self.resolution = resolution
-        self.action = action
-
-        if low is not None:
-            if not isinstance(low, (int, float)):
-                raise Exception(f"Invalid RangeConstraint: low type: '{type(low)})'")
-
-        if high is not None:
-            if not isinstance(high, (int, float)):
-                raise Exception(f"Invalid RangeConstraint: high type: '{type(high)})'")
-
-        if low is not None and high is not None and low > high:
-            raise Exception(f"Invalid RangeConstraint: {low}(low) > {high}(high)")
-
-        if action is not None and type(action) is not int:
-            raise Exception(f"Invalid RangeConstraint: action type: '{type(action)})'")
-
-
-class PyCellContext(object):
-
-    # stack of PyCellContext for cell hierarchy
-    _pyCellContexts = []
-
-    @classmethod
-    def getCurrentPyCellContext(cls) -> PyCellContext:
-        if len(cls._pyCellContexts) == 0:
-            raise Exception("No current PyCellContext")
-        return cls._pyCellContexts[-1]
-
-    def __init__(self, tech, cell):
-        PyCellContext._pyCellContexts.append(self)
-        self._tech = tech
-        self._cell = cell
-
-    def __enter__(self):
-        Layer.layout = self._cell.layout()
-
-    def __exit__(self, *params):
-        PyCellContext._pyCellContexts.pop()
-        Layer.layout = None
-        self._cell = None
-        self._tech = None
-
-    @property
-    def cell(self):
-        if self._cell is None:
-            raise Exception("Cell not set!")
-        return self._cell
-
-    @property
-    def tech(self):
-        if self._tech is None:
-            raise Exception("Tech not set!")
-        return self._tech
-
-    @property
-    def layout(self):
-        if self._cell is None:
-            raise Exception("Layout not set!")
-        return self._cell.layout()
-
-
-class PCellWrapper(pya.PCellDeclaration):
-
-    def __init__(self, impl, tech):
-        super(PCellWrapper, self).__init__()
-
-        self.impl = impl
-        self.impl.setTech(tech)
-        self.tech = tech
-
-        Tech.techInUse = tech.getTechParams()['libName']
-
-        self.param_decls = []
-
-        # NOTE: the PCellWrapper acts as the "specs" object
-        type(impl).defineParamSpecs(self)
-
-    def __call__(self, name, value, description = None, constraint = None):
-        # NOTE: this is calles from inside defineParamSpecs as we
-        # supply the "specs" object through self.
-
-        if type(value) is float:
-            value_type = pya.PCellParameterDeclaration.TypeDouble
-        elif type(value) is int:
-            value_type = pya.PCellParameterDeclaration.TypeInt
-        elif type(value) is str:
-            value_type = pya.PCellParameterDeclaration.TypeString
-        else:
-            print(f"Invalid parameter type for parameter {name} (value is {repr(value)})")
-            assert(False)
-
-        param_decl = pya.PCellParameterDeclaration(name, value_type, description, value)
-
-        if type(constraint) is ChoiceConstraint:
-            for v in constraint:
-                param_decl.add_choice(repr(v), v)
-        elif type(constraint) is RangeConstraint:
-            if constraint.action is REJECT:
-                if constraint.low is not None:
-                    param_decl.min_value = constraint.low
-                if constraint.high is not None:
-                    param_decl.max_value = constraint.high
-
-        self.param_decls.append(param_decl)
-
-    def get_parameters(self):
-        return self.param_decls
-
-    def params_as_hash(self,parameters):
-        params = {}
-        for i in range(0, len(self.param_decls)):
-            params[self.param_decls[i].name] = parameters[i]
-        return params
-
-    def display_text(self, parameters):
-        params = self.params_as_hash(parameters)
-        # TODO: form a display string from "important" parameters in a class-specific fashion
-        return self.name() + " (...)"
-
-    def produce(self, layout, layers, parameters, cell):
-        params = self.params_as_hash(parameters)
-
-        with (PyCellContext(self.tech, cell)):
-            self.impl.setupParams(params)
-            self.impl.genLayout()
-
-
diff --git a/ihp-sg13g2/libs.tech/klayout/python/cni/dlogen.py b/ihp-sg13g2/libs.tech/klayout/python/cni/dlogen.py
deleted file mode 100644
index c1adabaf..00000000
--- a/ihp-sg13g2/libs.tech/klayout/python/cni/dlogen.py
+++ /dev/null
@@ -1,109 +0,0 @@
-########################################################################
-#
-# Copyright 2024 IHP PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#    https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-########################################################################
-
-from cni.rect import *
-from cni.dlo import *
-from cni.grouping import *
-
-import pya
-
-class Dlo(object):
-
-    def __init__(self, libName, cellName, viewName='layout', viewType=None):
-        pass
-
-    @classmethod
-    def exists(cls, dloName : str) -> bool:
-        """
-        Returns True if the dloName Dlo design object exists, and False
-        otherwise. The dloName is a string of the form “<libName>/<cellName>/<viewName>”.
-        If <viewName> is not specified, then the default value “layout” will be used.
-
-        :param dloName: name of dlo object
-        :type dloName: str
-        :return: wether cell exists
-        :rtype: bool
-
-        """
-        libName = ''
-        cellName = ''
-        viewName = 'layout'
-
-        strings = dloName.split('/')
-
-        if len(strings) >= 1:
-            libName = strings[0]
-        if len(strings) >= 2:
-            cellName = strings[1]
-        if len(strings) >= 3:
-            viewName = strings[2]
-
-        if libName == '':
-            pya.Logger.warn(f"Dlo.exists: no libName given!")
-            return False
-
-        if cellName == '':
-            pya.Logger.warn(f"Dlo.exists: no cellName given!")
-            return False
-
-        if viewName == '':
-            pya.Logger.warn(f"Dlo.exists: no viewName given!")
-            return False
-
-        lib = pya.Library.library_by_name(libName)
-        if lib is None:
-            pya.Logger.warn(f"Dlo.exists: library '{libName}' don't exists!")
-            return False
-
-        if viewName != 'layout':
-            pya.Logger.warn(f"Dlo.exists: view '{viewName}' not exists in library {libName}!")
-            return False
-
-        if not lib.layout().has_cell(cellName):
-            pya.Logger.warn(f"Dlo.exists: cell '{cellName}' don't exists in library '{libName}'!")
-            return False
-
-        return True
-
-
-class DloGen(Dlo):
-
-    _libName = ''
-
-    def __init__(self):
-        self.tech = None
-        self.props = {}
-
-    @classmethod
-    def setLibName(cls, libName: str) -> None:
-        cls._libName = libName
-
-    @classmethod
-    def getLibName(cls) -> str:
-        if cls._libName == '':
-            raise Exception("Library name not set!")
-        return cls._libName
-
-    def setTech(self, tech):
-        self.tech = tech
-
-    def addPin(self, name, label, box, layer):
-        # simply creates a shape - needs to support other shape types?
-        Rect(layer, box)
-
-
diff --git a/ihp-sg13g2/libs.tech/klayout/python/cni/font.py b/ihp-sg13g2/libs.tech/klayout/python/cni/font.py
deleted file mode 100644
index 6fd7fb5a..00000000
--- a/ihp-sg13g2/libs.tech/klayout/python/cni/font.py
+++ /dev/null
@@ -1,39 +0,0 @@
-########################################################################
-#
-# Copyright 2024 IHP PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#    https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-########################################################################
-
-from cni.location import *
-from cni.orientation import *
-
-class Font(object):
-    EURO_STYLE = 1
-    FIXED = 2
-    GOTHIC = 3
-    MATH = 4
-    MIL_SPEC = 5
-    ROMAN = 6
-    SCRIPT = 7
-    STICK = 8
-    SWEDISH = 9
-
-    @classmethod
-    def getMembers(cls):
-        return [cls.EURO_STYLE, cls.FIXED, cls.GOTHIC, cls.MATH, cls.MIL_SPEC, cls.ROMAN, cls.SCRIPT, cls.STICK, sls.SWEDISH]
-
-    def calcBBox(self, text, origin, height, location=Location.UPPER_LEFT, orient=Orientation.R0, overbar=False):
-        raise Exception("Not implemented yet!")
-
diff --git a/ihp-sg13g2/libs.tech/klayout/python/cni/geo.py b/ihp-sg13g2/libs.tech/klayout/python/cni/geo.py
deleted file mode 100644
index 9b10bc2f..00000000
--- a/ihp-sg13g2/libs.tech/klayout/python/cni/geo.py
+++ /dev/null
@@ -1,86 +0,0 @@
-########################################################################
-#
-# Copyright 2024 IHP PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#    https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-########################################################################
-
-from __future__ import annotations
-from cni.grouping import *
-from cni.pointlist import PointList
-from cni.point import Point
-from cni.polygon import Polygon
-from cni.dlo import Tech
-
-import pya
-
-def fgOr(components1: ulist[PhysicalComponent], components2: ulist[PhysicalComponent], resultLayer: Layer) -> Grouping:
-    """
-    Performs a logical OR operation for lists of physical components comps1
-    and comps2, by selecting those polygon areas which are in either list of physical
-    components. The resulting merged polygon shapes are generated on the resultLayer layer.
-    In addition, these polygon shapes are used to create a Grouping object, which is the return
-    value for this method.
-
-    :param components1: first list of physical component derived objects
-    :type components1: list of PhysicalCompent
-    :param components2: second list of physical component derived objects
-    :type components2: list of PhysicalCompent
-    :param resultLayer: layer where resulting shapes will be generated on
-    :type resultLayer: Layer
-    :return: grouping object
-    :rtype: Grouping
-
-    """
-    region1 = pya.Region()
-    region2 = pya.Region()
-
-    [component.addToRegion(region1) for component in components1]
-    [component.addToRegion(region2) for component in components2]
-
-    orRegion = region1.or_(region2).merge()
-
-    grouping = Grouping()
-
-    for poly in orRegion.each():
-        pointList = PointList()
-        for point in poly.to_simple_polygon().to_dtype(Tech.get(Tech.techInUse).dataBaseUnits).each_point():
-            pointList.append(Point(point.x, point.y))
-
-        polygon = Polygon(resultLayer, pointList)
-        grouping.add(polygon)
-
-    return grouping
-
-
-def fgAnd():
-  # TODO: implement
-  pass
-
-
-def fgXor():
-  # TODO: implement
-  pass
-
-
-def fgNot():
-  # TODO: implement
-  pass
-
-
-def fgMerge():
-  # TODO: implement
-  pass
-
-
diff --git a/ihp-sg13g2/libs.tech/klayout/python/cni/grouping.py b/ihp-sg13g2/libs.tech/klayout/python/cni/grouping.py
deleted file mode 100644
index a7ddc775..00000000
--- a/ihp-sg13g2/libs.tech/klayout/python/cni/grouping.py
+++ /dev/null
@@ -1,64 +0,0 @@
-########################################################################
-#
-# Copyright 2024 IHP PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#    https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-########################################################################
-
-from __future__ import annotations
-from cni.physicalComponent import *
-import pya
-import sys
-
-class Grouping(PhysicalComponent):
-
-    def __init__(self, name: str = "", components: PhysicalComponent = None):
-        self._name = name
-        self._components = []
-
-        if components is not None:
-            self._components.add(components)
-
-    def add(self, components: PhysicalComponent) -> None:
-        if type(components) is not list:
-            self._components.append(components)
-        else:
-            self._components.extend(components)
-
-    def addToRegion(self, region: pya.Region):
-        [component.addToRegion(region) for component in self._components]
-
-    def clone(self, nameMap : NameMapper = NameMapper(), netMap : NameMapper = NameMapper()):
-        components = []
-        [components.append(component.clone()) for component in self._components]
-        return Grouping(self._name, components)
-
-    def destroy(self):
-        [component.destroy() for component in self._components]
-        self._components.clear()
-
-    def getComps(self) -> list:
-        return self._components
-
-    def getComp(self, index: int) -> PhysicalComponent:
-        return self._components[index]
-
-    def moveBy(self, dx: float, dy: float) -> None:
-        [component.moveBy(dx, dy) for component in self._components]
-
-    def toString(self):
-        [component.toString() for component in self._components]
-
-    def transform(self, transform: Transform) -> None:
-        [component.transform(transform) for component in self._components]
diff --git a/ihp-sg13g2/libs.tech/klayout/python/cni/instance.py b/ihp-sg13g2/libs.tech/klayout/python/cni/instance.py
deleted file mode 100644
index 2ae91b8d..00000000
--- a/ihp-sg13g2/libs.tech/klayout/python/cni/instance.py
+++ /dev/null
@@ -1,138 +0,0 @@
-########################################################################
-#
-# Copyright 2024 IHP PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#    https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-########################################################################
-
-from __future__ import annotations
-from cni.physicalComponent import *
-from cni.paramarray import *
-from cni.shape import *
-from cni.orientation import *
-import pya
-import sys
-
-class Instance():
-    """
-    Creates an Instance object, where the dloName parameter specifies the Klayout name to be
-    used for this Instance object. The dloName parameter is a string of the form
-    “libName/cellName/viewName”, where the libName and the viewName are optional. If the libName
-    is not specified, then the library name associated with the current DloGen is used; if the
-    viewName is not specified, then the default viewName is used (currently “layout”).
-
-    :param dloName: name of dlo object
-    :type dloName: str
-
-    """
-
-    def __init__(self, dloName: str):
-        self._instance = None
-
-        libName = ''
-        cellName = ''
-        viewName = ''
-
-        strings = dloName.split('/')
-
-        if len(strings) >= 1:
-            libName = strings[0]
-        if len(strings) >= 2:
-            cellName = strings[1]
-        if len(strings) >= 3:
-            viewName = strings[2]
-
-        if libName == '':
-            libName = dloGen.getLibName()
-
-        if cellName == '':
-            raise Exception("No cellName given!")
-
-        if viewName == '':
-            viewName = 'layout'
-
-        lib = pya.Library.library_by_name(libName)
-        if lib is None:
-            raise Exception(f"Library '{libName}' don't exists!")
-
-        if viewName != 'layout':
-            raise Exception(f"View '{viewName}' not exists in library {libName}!")
-
-        cell = lib.layout().cell(cellName)
-        if cell is None:
-            raise Exception(f"Cell '{cellName}' don't exists in library '{libName}'!")
-
-        self._instance = Shape.getCell().insert(pya.DCellInstArray(cell, pya.DTrans()))
-
-    def getParams(self) -> ParamArray:
-        """
-        Returns the ParamArray which provides the explicit parameters and values which were used
-        when this Instance object was created.
-
-        :return: array of parameters
-        :rtype: ParamArray
-
-        """
-        return Shape.getCell().pcell_parameters_by_name(self._instance)
-
-    def setParams(self, params: ParamArray) -> None:
-        """
-        Uses the passed ParamArray params to set the parameter values for this Instance.
-
-        :param params: parameters to set
-        :type params: ParamArray
-
-        """
-        return Shape.getCell().change_pcell_parameters(self._instance, params)
-
-    def setOrientation(self, orientation: Orientation) -> None:
-        """
-        Sets the orientation for this Instance.
-
-        :param orientation: orientation to set
-        :type orientation: Orientation
-
-        """
-        match orientation:
-            case Orientation.R0:
-                transform = pya.DTrans(0, False)
-            case Orientation.R90:
-                transform = pya.DTrans(90, False)
-            case Orientation.R180:
-                transform = pya.DTrans(180, False)
-            case Orientation.R270:
-                transform = pya.DTrans(270, False)
-            case Orientation.MYR90:
-                transform = pya.DTrans(90, False) * pya.DTrans.M90
-            case Orientation.MXR90:
-                transform = pya.DTrans(90, True)
-            case Orientation.MY:
-                transform = pya.DTrans(0, False) * pya.DTrans.M90
-            case Orientation.MX:
-                transform = pya.DTrans(0, True)
-            case _:
-                raise Exception(f"Unknown orientation '{orientation}'")
-
-        Shape.getCell().transform(self._instance, transform)
-
-    def setOrigin(self, point: Point) -> None:
-        """
-        Sets the Point point parameter to be the origin for this Instance.
-
-        :param point: origin to set
-        :type point: Point
-
-        """
-        Shape.getCell().transform(self._instance, pya.DTrans(point.x, point.y))
-
diff --git a/ihp-sg13g2/libs.tech/klayout/python/cni/layer.py b/ihp-sg13g2/libs.tech/klayout/python/cni/layer.py
deleted file mode 100644
index bb92b9c4..00000000
--- a/ihp-sg13g2/libs.tech/klayout/python/cni/layer.py
+++ /dev/null
@@ -1,92 +0,0 @@
-########################################################################
-#
-# Copyright 2024 IHP PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#    https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-########################################################################
-
-class Layer(object):
-
-    tech = None
-    layout = None
-
-    def __init__(self, name, purpose = None):
-        namePurpose = name if purpose is None else name + "." + purpose
-        import cni.dlo
-        layer, datatype = cni.dlo.PyCellContext.getCurrentPyCellContext().tech.stream_layers()[namePurpose]
-
-        self._name = namePurpose
-        self._number = cni.dlo.PyCellContext.getCurrentPyCellContext().layout.layer(layer, datatype, namePurpose)
-        self._purposeName = "" if purpose is None else purpose
-
-    def getAttrs(self):
-        raise Exception("Not implemented yet!")
-
-    def getGridResolution(self):
-        raise Exception("Not implemented yet!")
-
-    def getLayerAbove(self):
-        raise Exception("Not implemented yet!")
-
-    def getLayerAbove(self, layerMaterial):
-        raise Exception("Not implemented yet!")
-
-    def getLayerBelow(self):
-        raise Exception("Not implemented yet!")
-
-    def getLayerBelow(self, layerMaterial):
-        raise Exception("Not implemented yet!")
-
-    def getLayerName(self):
-        return self._name
-
-    def getLayerNumber(self):
-        return self._number
-
-    def getMaterial(self):
-        raise Exception("Not implemented yet!")
-
-    def getPurposeName(self):
-        raise Exception("Not implemented yet!")
-
-    def getPurposeNumber(self):
-        raise Exception("Not implemented yet!")
-
-    def getRoutingDir(self):
-        raise Exception("Not implemented yet!")
-
-    def isAbove(self, layer):
-        raise Exception("Not implemented yet!")
-
-    def isMaskLayer(self):
-        raise Exception("Not implemented yet!")
-
-    @property
-    def name(self):
-        return self._name
-
-    @property
-    def number(self):
-        return self._number
-
-    @property
-    def purposeName(self):
-        return self._purposeName
-
-    @property
-    def purposeNumber(self):
-        raise Exception("Not implemented yet!")
-
-
-
diff --git a/ihp-sg13g2/libs.tech/klayout/python/cni/location.py b/ihp-sg13g2/libs.tech/klayout/python/cni/location.py
deleted file mode 100644
index 28c21061..00000000
--- a/ihp-sg13g2/libs.tech/klayout/python/cni/location.py
+++ /dev/null
@@ -1,50 +0,0 @@
-########################################################################
-#
-# Copyright 2024 IHP PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#    https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-########################################################################
-
-class Location(object):
-
-    LOWER_LEFT = 1
-    CENTER_LEFT = 2
-    UPPER_LEFT = 3
-    LOWER_CENTER = 4
-    CENTER_CENTER = 5
-    UPPER_CENTER = 6
-    LOWER_RIGHT = 7
-    CENTER_RIGHT = 8
-    UPPER_RIGHT = 9
-
-    def mirrorX(self):
-        raise Exception("Not implemented yet!")
-
-    def mirrorY(self):
-        raise Exception("Not implemented yet!")
-
-    def rotate90(self):
-        raise Exception("Not implemented yet!")
-
-    def rotate180(self):
-        raise Exception("Not implemented yet!")
-
-    def rotate270(self):
-        raise Exception("Not implemented yet!")
-
-    def transform(self, transform):
-        raise Exception("Not implemented yet!")
-
-
-
diff --git a/ihp-sg13g2/libs.tech/klayout/python/cni/namemapper.py b/ihp-sg13g2/libs.tech/klayout/python/cni/namemapper.py
deleted file mode 100644
index 6ed7221a..00000000
--- a/ihp-sg13g2/libs.tech/klayout/python/cni/namemapper.py
+++ /dev/null
@@ -1,25 +0,0 @@
-########################################################################
-#
-# Copyright 2024 IHP PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#    https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-########################################################################
-
-class NameMapper(object):
-
-    def __init__(self, obj: object = None):
-        if obj is not None:
-            raise Exception("Not implemented yet!")
-
-        self._object = obj
diff --git a/ihp-sg13g2/libs.tech/klayout/python/cni/numeric.py b/ihp-sg13g2/libs.tech/klayout/python/cni/numeric.py
deleted file mode 100644
index e276265e..00000000
--- a/ihp-sg13g2/libs.tech/klayout/python/cni/numeric.py
+++ /dev/null
@@ -1,182 +0,0 @@
-########################################################################
-#
-# Copyright 2024 IHP PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#    https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-########################################################################
-
-import re
-
-class Numeric(float):
-    """
-    The Numeric class is used to create a floating point number from a string
-    representation, such as “10ns”. This string representation is composed of two parts: 1) a
-    number part and 2) a scale factor part. Thus, this Numeric class can be used to represent a
-    floating point number as a floating point number along with a scaling factor. Since this
-    Numeric class is derived from the base Python float class, it can be used just like a
-    regular floating point number in any numerical computation.\n
-    The number part of this Numeric class string representation can be any valid Python
-    integer or floating point number; this Python floating point number can be represented
-    using standard scientific notation, such as “1.23e-4”. The scaling factor part of this
-    Numeric class string representation must be one of the following pre-defined scaling
-    factor string values:
-
-    +---------------+------------------+-------------+
-    |  Character    |  Name            |  Multiplier |
-    +===============+==================+=============+
-    |  Y            |  Yotta           |  1e24       |
-    +---------------+------------------+-------------+
-    |  Z            |  Zetta           |  1e21       |
-    +---------------+------------------+-------------+
-    |  E            |  Exa             |  1e18       |
-    +---------------+------------------+-------------+
-    |  P            |  Peta            |  1e15       |
-    +---------------+------------------+-------------+
-    |  T            |  Tera            |  1e12       |
-    +---------------+------------------+-------------+
-    |  G            |  Giga            |  1e09       |
-    +---------------+------------------+-------------+
-    |  M            |  Mega            |  1e06       |
-    +---------------+------------------+-------------+
-    |  K or k       |  Kilo            |  1e03       |
-    +---------------+------------------+-------------+
-    |  ‘’           |  no scale factor |  1.0        |
-    +---------------+------------------+-------------+
-    |  %            |  percent         |  1e-2       |
-    +---------------+------------------+-------------+
-    |  c            |  centi           |  1e-2       |
-    +---------------+------------------+-------------+
-    |  m            |  milli           |  1e-3       |
-    +---------------+------------------+-------------+
-    |  u            |  micron          |  1e-6       |
-    +---------------+------------------+-------------+
-    |  n            |  nano            |  1e-9       |
-    +---------------+------------------+-------------+
-    |  p            |  pico            |  1e-12      |
-    +---------------+------------------+-------------+
-    |  f            |  femto           |  1e-15      |
-    +---------------+------------------+-------------+
-    |  a            |  atto            |  1e-18      |
-    +---------------+------------------+-------------+
-    |  z            |  zepto           |  1e-21      |
-    +---------------+------------------+-------------+
-    |  y            |  yocto           |  1e-24      |
-    +---------------+------------------+-------------+
-
-    Note that any characters after the first character in the scaling factor are simply ignored.
-    Thus, the scaling factor “mVolt” is the same as “m”. This capability can be used to create
-    more descriptive scaling factors.
-
-    Numeric(int | float | string) – creates a Numeric object, based upon the specified number
-    or string. The string must be a string of the form <number><scaleFactor>, where the
-    <scaleFactor> is one of the pre-defined scaling factors in the above table of scaling factor
-    strings. That is, this string representation must be composed of a number part and a
-    scaling factor part, where the scaling factor is a pre-defined scaling factor string.
-
-    """
-
-    _scaleFactors = "yzafpnumc%kKMGTPEZY"
-
-    def __new__(cls, value):
-        """
-        Numeric(int | float | string) – creates a Numeric object, based upon the specified number
-        or string. The string must be a string of the form <number><scaleFactor>, where the
-        <scaleFactor> is one of the pre-defined scaling factors in the above table of scaling factor
-        strings. That is, this string representation must be composed of a number part and a
-        scaling factor part, where the scaling factor is a pre-defined scaling factor string.
-
-        """
-        calcValue, numberPart, scaleFactor = cls._calcValue(value)
-        instance = super().__new__(cls, calcValue)
-        instance._scaleFactor = scaleFactor
-        instance._numberPart = numberPart
-        return instance
-
-    @classmethod
-    def _calcValue(cls, value):
-        number = 0
-        exp = 0
-        numberPart = value
-        scaleFactor = ""
-
-        if type(value) is float or type(value) is int or type(value) is Numeric:
-            return float(value), numberPart, scaleFactor
-
-        match = re.fullmatch(r'([0-9.+\-e]+)([' + cls._scaleFactors + r'])?(\S*)?', value)
-
-        if match:
-            numberPart = match.group(1)
-
-            if match.group(2) != None:
-                scale = match.group(2)
-                scaleFactor = scale;
-
-                if scale == "c" or scale == "%":
-                    exp = -2
-                else:
-                    if scale == "k":
-                        scale = "K"
-
-                    exp = -1
-
-                    for i in cls._scaleFactors.replace('c', '').replace('%', ' ').replace('k', ''):
-                        exp += 1
-                        if i is scale:
-                            break
-
-                    exp = (exp - 8) * 3
-
-        try:
-            number = float(numberPart)
-        except:
-            raise ValueError
-
-        return number * (10**exp), numberPart, scaleFactor
-
-    def scaleFormat(self, scaleFactor = None):
-        """
-        Returns the floating point number formatted
-        using the specified scaleFactor scaling value. If this scaleFactor parameter is not
-        specified, then the floating point number is returned using the scale factor which was
-        used when the Numeric class object was created.
-
-        :param scaleFactor: Optional scaling factor to use.
-        :type scaleFactor: string or None
-        :return: new scaled Numeric object
-        :rtype: Numeric
-
-        """
-        if scaleFactor is not None:
-            if type(scaleFactor) is str:
-                calcValue, numberPart, scaleFactor = Numeric._calcValue(self._numberPart + scaleFactor)
-                return calcValue
-        else:
-            return self
-
-    @property
-    def scaleFactor(self):
-        """
-        The default (original) scale factor
-
-        """
-        return self._scaleFactor
-
-    @property
-    def scale_factors(self):
-        """
-        List of all available scaling factors, along with their values
-
-        """
-        return [*Numeric._scaleFactors]
-
diff --git a/ihp-sg13g2/libs.tech/klayout/python/cni/orientation.py b/ihp-sg13g2/libs.tech/klayout/python/cni/orientation.py
deleted file mode 100644
index 08a282dd..00000000
--- a/ihp-sg13g2/libs.tech/klayout/python/cni/orientation.py
+++ /dev/null
@@ -1,37 +0,0 @@
-########################################################################
-#
-# Copyright 2024 IHP PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#    https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-########################################################################
-
-class Orientation(object):
-    # TODO: this better should match KLayout's transformation code for
-    # easy porting
-    R0 = 0
-    R90 = 1
-    R180 = 2
-    R270 = 3
-    MY = 4
-    MYR90 = 5
-    MX = 6
-    MXR90 = 7
-
-    def concat(self, other):
-        raise Exception("Not implemented yet!")
-
-    def getRelativeOrient(self, other):
-        raise Exception("Not implemented yet!")
-
-
diff --git a/ihp-sg13g2/libs.tech/klayout/python/cni/pathstyle.py b/ihp-sg13g2/libs.tech/klayout/python/cni/pathstyle.py
deleted file mode 100644
index e79b438c..00000000
--- a/ihp-sg13g2/libs.tech/klayout/python/cni/pathstyle.py
+++ /dev/null
@@ -1,24 +0,0 @@
-########################################################################
-#
-# Copyright 2024 IHP PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#    https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-########################################################################
-
-class PathStyle(object):
-    TRUNCATE = 1
-    EXTEND = 2
-    ROUND = 3
-    VARIABLE = 4
-
diff --git a/ihp-sg13g2/libs.tech/klayout/python/cni/physicalComponent.py b/ihp-sg13g2/libs.tech/klayout/python/cni/physicalComponent.py
deleted file mode 100644
index db424919..00000000
--- a/ihp-sg13g2/libs.tech/klayout/python/cni/physicalComponent.py
+++ /dev/null
@@ -1,71 +0,0 @@
-########################################################################
-#
-# Copyright 2024 IHP PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#    https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-########################################################################
-
-from __future__ import annotations
-from abc import ABC, abstractmethod
-from cni.ulist import *
-from cni.namemapper import NameMapper
-from cni.transform import Transform
-
-import pya
-
-class PhysicalComponent(ABC):
-
-    @abstractmethod
-    def addToRegion(self, region: pya.Region):
-        pass
-
-    @abstractmethod
-    def clone(self, nameMap : NameMapper = NameMapper(), netMap : NameMapper = NameMapper()):
-        pass
-
-    def fgOr(self, component: PhysicalComponent, resultLayer: Layer) -> Grouping:
-        """
-        Performs a logical or operation for this physical component and another physical component,
-        by selecting those polygon areas which are in either physical component. The resulting
-        merged polygon shapes are generated on the resultLayer layer. In addition, these polygon
-        shapes are used to create a Grouping object, which is the return value for this method.
-
-        :param component: physical component derived object
-        :type component: PhysicalCompent
-        :param resultLayer: layer where resulting shapes will be generated on
-        :type resultLayer: Layer
-        :return: grouping object
-        :rtype: Grouping
-
-        """
-        components1 = ulist[PhysicalComponent]()
-        components1.append(self)
-
-        components2 = ulist[PhysicalComponent]()
-        components2.append(component)
-
-        import cni.geo
-        return cni.geo.fgOr(components1, components2, resultLayer)
-
-    @abstractmethod
-    def destroy(self):
-        pass
-
-    @abstractmethod
-    def moveBy(self, dx: float, dy: float) -> None:
-        pass
-
-    @abstractmethod
-    def transform(self, transform: Transform) -> None:
-        pass
diff --git a/ihp-sg13g2/libs.tech/klayout/python/cni/point.py b/ihp-sg13g2/libs.tech/klayout/python/cni/point.py
deleted file mode 100644
index de02e117..00000000
--- a/ihp-sg13g2/libs.tech/klayout/python/cni/point.py
+++ /dev/null
@@ -1,144 +0,0 @@
-########################################################################
-#
-# Copyright 2024 IHP PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#    https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-########################################################################
-
-import pya
-
-import math
-
-class Point(object):
-    def __init__(self, x, y):
-        self.point = pya.DPoint(x, y)
-
-    @classmethod
-    def areColinearPoints(cls, p1, p2, p3):
-        """
-        Returns True if these three points are colinear or coincident, and returns False otherwise.
-
-        :param p1: first point.
-        :type p1: Point
-        :param p2: second point.
-        :type p2: Point
-        :param p3: third point.
-        :type p3: Point
-        :return: whether all three points are collinear or coincident
-        :rtype: boolean
-
-        """
-        triangleArea = 0.5 * abs(
-                (p1.point.x * (p2.point.y - p3.point.y)) +
-                (p2.point.x * (p3.point.y - p1.point.y)) +
-                (p3.point.x * (p1.point.y - p2.point.y)))
-        return math.isclose(0.0, triangleArea) or (p1 == p2 and p2 == p3)
-
-    def copy(self):
-        raise Exception("Not implemented yet!")
-
-    def getCoord(self, dir):
-        raise Exception("Not implemented yet!")
-
-    def getSpacing(self, dir, refPoint):
-        raise Exception("Not implemented yet!")
-
-    def getX(self):
-        return self.point.x
-
-    def getY(self):
-        return self.point.y
-
-    def invalid(self):
-        raise Exception("Not implemented yet!")
-
-    def isBetween(self, a, b):
-        raise Exception("Not implemented yet!")
-
-    def isValid(self, ):
-        raise Exception("Not implemented yet!")
-
-    def place(self, dir, refPoint, distance, align = True):
-        raise Exception("Not implemented yet!")
-
-    def set(self, p):
-        raise Exception("Not implemented yet!")
-
-    def set(self, _x, _y):
-        raise Exception("Not implemented yet!")
-
-    def setCoord(self, dir, coord):
-        raise Exception("Not implemented yet!")
-
-    def setX(self, x):
-        self.point.x = x
-
-    def setY(self, y):
-        self.point.y = y
-
-    def snap(self, grid, snapType=None):
-        raise Exception("Not implemented yet!")
-
-    def snapX(self, grid, snapType=None):
-        raise Exception("Not implemented yet!")
-
-    def snapY(self, grid, snapType=None):
-        raise Exception("Not implemented yet!")
-
-    def snapTowards(self, grid, dir):
-        raise Exception("Not implemented yet!")
-
-    def toDiagAxes(self):
-        raise Exception("Not implemented yet!")
-
-    def toOrthogAxes(self):
-        raise Exception("Not implemented yet!")
-
-    def transform(self, trans):
-        raise Exception("Not implemented yet!")
-
-    def __eq__(self, other):
-        return self.point == other.point
-
-    @property
-    def x(self):
-        """
-        Returns the value of the x-coordinate for this point
-
-        """
-        return self.point.x
-
-    @x.setter
-    def x(self, value):
-        """
-        Sets the value of the x-coordinate for this point
-
-        """
-        self.point.x = value
-
-    @property
-    def y(self):
-        """
-        Returns the value of the y-coordinate for this point
-
-        """
-        return self.point.y
-
-    @y.setter
-    def y(self, value):
-        """
-        Sets the value of the y-coordinate for this point
-
-        """
-        self.point.y = value
diff --git a/ihp-sg13g2/libs.tech/klayout/python/cni/pointlist.py b/ihp-sg13g2/libs.tech/klayout/python/cni/pointlist.py
deleted file mode 100644
index 68e12be3..00000000
--- a/ihp-sg13g2/libs.tech/klayout/python/cni/pointlist.py
+++ /dev/null
@@ -1,87 +0,0 @@
-########################################################################
-#
-# Copyright 2024 IHP PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#    https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-########################################################################
-
-from __future__ import annotations
-
-from cni.point import *
-from cni.ulist import *
-
-class PointList(ulist[Point]):
-
-    def __init__(self, items = None) -> None:
-        super().__init__(items)
-
-    def compress(self, isClose = True) -> PointList:
-        """
-        Compresses this PointList, by removing any extra (coincident and/or collinear) points from
-        this PointList. The optional isClosed parameter is used to indicate whether this set of
-        points is meant to represent a closed shape or not. If all points are collinear, then the
-        first and last points will be the result of compressing this PointList. If the first and
-        last points are coincident, then only the first point is returned
-
-        :param isClose: Whether represented shape is closed
-        :type p1: boolean
-        :return: see description above
-        :rtype: PointList
-        """
-
-        if len(self) < 3:
-            return self
-
-        if self[0] == self[-1]:
-            firstPointList = []
-            firstPointList.append(self[0])
-            self = firstPointList
-            return self
-
-        pairUniqueList = []
-        [pairUniqueList.append(value) for index, value in enumerate(self) if index == 0 or value != self[index-1]]
-
-        nonColinearList = []
-        for index, value in enumerate(pairUniqueList):
-            if index == 0 or index == len(pairUniqueList)-1:
-                nonColinearList.append(value)
-            else:
-                if not Point.areColinearPoints(pairUniqueList[index-1], value, pairUniqueList[index+1]):
-                    nonColinearList.append(value)
-
-        self = nonColinearList
-        return self
-
-    def containsPoint(self, point: Point) -> bool:
-        # Jordan point in polygon test
-        numVertices = len(self)
-        x, y = point.x, point.y
-        isInside = False
-
-        p1 = self[0]
-
-        for i in range(1, numVertices + 1):
-            p2 = self[i % numVertices]
-
-            if y > min(p1.y, p2.y):
-                if y <= max(p1.y, p2.y):
-                    if x <= max(p1.x, p2.x):
-                        x_intersection = (y - p1.y) * (p2.x - p1.x) / (p2.y - p1.y) + p1.x
-
-                        if p1.x == p2.x or x <= x_intersection:
-                            isInside = not isInside
-
-            p1 = p2
-
-        return isInside
diff --git a/ihp-sg13g2/libs.tech/klayout/python/cni/polygon.py b/ihp-sg13g2/libs.tech/klayout/python/cni/polygon.py
deleted file mode 100644
index 1819f5f4..00000000
--- a/ihp-sg13g2/libs.tech/klayout/python/cni/polygon.py
+++ /dev/null
@@ -1,85 +0,0 @@
-########################################################################
-#
-# Copyright 2024 IHP PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#    https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-########################################################################
-
-from functools import singledispatchmethod
-from cni.shape import *
-from cni.layer import *
-from cni.pointlist import *
-from cni.tech import Tech
-
-import pya
-
-class Polygon(Shape):
-
-    @singledispatchmethod
-    def __init__(self, arg1, arg2 = None):
-        pass
-
-    @__init__.register
-    def _(self, arg1: Layer, arg2: PointList) -> None:
-        pyaPoints = []
-        [pyaPoints.append(point.point) for point in arg2]
-
-        self._polygon = pya.DSimplePolygon(pyaPoints, True)
-        super().__init__(self._polygon.bbox())
-        self.set_shape(Shape.getCell().shapes(arg1.number).insert(self._polygon))
-
-    @__init__.register
-    def _(self, arg1: pya.DSimplePolygon, arg2: int) -> None:
-        self._polygon = arg1
-        super().__init__(self._polygon.bbox())
-        self.set_shape(Shape.getCell().shapes(arg2).insert(self._polygon))
-
-    def addToRegion(self, region: pya.Region):
-        region.insert(self._polygon.to_itype(Tech.get(Tech.techInUse).dataBaseUnits))
-
-    def clone(self, nameMap : NameMapper = NameMapper(), netMap : NameMapper = NameMapper()):
-        dup = self._polygon.dup();
-        polygon = Polygon(dup, self.getShape().layer)
-        return polygon
-
-    def destroy(self):
-        if not self._polygon._destroyed():
-            Shape.getCell().shapes(self.getShape().layer).erase(self.getShape())
-            self._polygon._destroy()
-        else:
-            pya.Logger.warn(f"Polygon.destroy: already destroyed!")
-
-    def getPoints(self) -> PointList:
-        pointList = PointList()
-        [pointList.append(Point(point.x, point.y)) for point in self._polygon.each_point()]
-        return pointList
-
-    def moveBy(self, dx: float, dy: float) -> None:
-        movedPolygon = (pya.DTrans(float(dx), float(dy)) * self._polygon).to_itype(Tech.get(Tech.techInUse).
-            dataBaseUnits).to_simple_polygon().to_dtype(Tech.get(Tech.techInUse).dataBaseUnits)
-        shape = Shape.getCell().shapes(self._shape.layer).insert(movedPolygon)
-        self.destroy()
-        self._polygon = movedPolygon
-        self.set_shape(shape)
-
-    def toString(self) -> str:
-        return "Polygon: {}".format(self._polygon.to_s())
-
-    def transform(self, transform: Transform) -> None:
-        transformedPolygon = self._polygon.transformed(transform.transform)
-        shape = Shape.getCell().shapes(self.getShape().layer).insert(transformedPolygon)
-        self.destroy()
-        self._polygon = transformedPolygon
-        self.set_shape(shape)
-
diff --git a/ihp-sg13g2/libs.tech/klayout/python/cni/rect.py b/ihp-sg13g2/libs.tech/klayout/python/cni/rect.py
deleted file mode 100644
index 8070e138..00000000
--- a/ihp-sg13g2/libs.tech/klayout/python/cni/rect.py
+++ /dev/null
@@ -1,67 +0,0 @@
-########################################################################
-#
-# Copyright 2024 IHP PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#    https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-########################################################################
-
-from cni.shape import *
-from cni.box import Box
-from cni.layer import Layer
-from cni.tech import Tech
-
-class Rect(Shape):
-
-    def __init__(self, layer: Layer, box: Box):
-        self._box = box
-        self._layer = layer
-
-        super().__init__(box)
-        shape = Shape.getCell().shapes(layer.number).insert(box.box)
-        self.set_shape(shape)
-        self._box.setRect(self)
-
-    def addToRegion(self, region: pya.Region):
-        region.insert(self._box.box.to_itype(Tech.get(Tech.techInUse).dataBaseUnits))
-
-    def clone(self, nameMap : NameMapper = NameMapper(), netMap : NameMapper = NameMapper()):
-        return Rect(self._layer, self._box.clone(nameMap, netMap))
-
-    def destroy(self):
-        self._box.destroy()
-
-    def moveBy(self, dx: float, dy: float) -> None:
-        self._box.moveBy(dx, dy)
-
-    def toString(self) -> str:
-        return "Rect: {}".format(self._box.box.to_s())
-
-    def transform(self, transform: Transform) -> None:
-        self._box.transform(transform)
-
-    @property
-    def bottom(self):
-        return self._box.bottom
-
-    @property
-    def left(self):
-        return self._box.left
-
-    @property
-    def right(self):
-        return self._box.right
-
-    @property
-    def top(self):
-        return self._box.top
diff --git a/ihp-sg13g2/libs.tech/klayout/python/cni/shape.py b/ihp-sg13g2/libs.tech/klayout/python/cni/shape.py
deleted file mode 100644
index 487eba24..00000000
--- a/ihp-sg13g2/libs.tech/klayout/python/cni/shape.py
+++ /dev/null
@@ -1,44 +0,0 @@
-########################################################################
-#
-# Copyright 2024 IHP PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#    https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-########################################################################
-
-from __future__ import annotations
-from cni.box import *
-from cni.physicalComponent import *
-import pya
-
-class Shape(PhysicalComponent):
-
-    @classmethod
-    def getCell(cls) -> pya.Cell:
-        import cni.dlo
-        return cni.dlo.PyCellContext.getCurrentPyCellContext().cell
-
-    def __init__(self, bbox = None):
-        self._shape = None
-        self._bbox = bbox
-
-    def set_shape(self, shape: Shape):
-        self._shape = shape
-
-    def getShape(self):
-        if self._shape is None:
-            raise Exception(f"Shape.getShape no shape set {hex(id(self))}: {hex(id(self._shape))}")
-        return self._shape
-
-    def getBBox(self):
-        return Box(self._bbox.box.left, self._bbox.box.bottom, self._bbox.box.right, self._bbox.box.top)
diff --git a/ihp-sg13g2/libs.tech/klayout/python/cni/signaltype.py b/ihp-sg13g2/libs.tech/klayout/python/cni/signaltype.py
deleted file mode 100644
index 3d4e27d9..00000000
--- a/ihp-sg13g2/libs.tech/klayout/python/cni/signaltype.py
+++ /dev/null
@@ -1,30 +0,0 @@
-########################################################################
-#
-# Copyright 2024 IHP PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#    https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-########################################################################
-
-class SignalType(object):
-    SIGNAL = 1
-    POWER = 2
-    GROUND = 3
-    CLOCK = 4
-    TIEOFF = 5
-    TIEHI = 6
-    TIELO = 7
-    ANALOG = 8
-    SCAN = 9
-    RESET = 10
-
diff --git a/ihp-sg13g2/libs.tech/klayout/python/cni/tech.py b/ihp-sg13g2/libs.tech/klayout/python/cni/tech.py
deleted file mode 100644
index bc52009a..00000000
--- a/ihp-sg13g2/libs.tech/klayout/python/cni/tech.py
+++ /dev/null
@@ -1,34 +0,0 @@
-########################################################################
-#
-# Copyright 2024 IHP PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#    https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-########################################################################
-
-
-class TechImpl(object):
-    pass
-
-
-class Tech(object):
-
-    techsByName = {}
-    techInUse = ""
-
-    def register(tech):
-        Tech.techsByName[tech.name()] = tech
-
-    def get(name):
-        return Tech.techsByName[name]
-
diff --git a/ihp-sg13g2/libs.tech/klayout/python/cni/termtype.py b/ihp-sg13g2/libs.tech/klayout/python/cni/termtype.py
deleted file mode 100644
index 04242b6c..00000000
--- a/ihp-sg13g2/libs.tech/klayout/python/cni/termtype.py
+++ /dev/null
@@ -1,27 +0,0 @@
-########################################################################
-#
-# Copyright 2024 IHP PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#    https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-########################################################################
-
-class TermType(object):
-    INPUT = 1
-    OUTPUT = 2
-    INPUT_OUTPUT = 3
-    SWITCH = 4
-    JUMPER = 5
-    UNUSED = 6
-    TRISTATE = 7
-
diff --git a/ihp-sg13g2/libs.tech/klayout/python/cni/text.py b/ihp-sg13g2/libs.tech/klayout/python/cni/text.py
deleted file mode 100644
index 46ee01d7..00000000
--- a/ihp-sg13g2/libs.tech/klayout/python/cni/text.py
+++ /dev/null
@@ -1,75 +0,0 @@
-########################################################################
-#
-# Copyright 2024 IHP PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#    https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-########################################################################
-
-from cni.box import *
-from cni.shape import *
-from cni.rect import *
-
-import pya
-
-class Text(Shape):
-
-    def __init__(self, layer, text, point, size):
-        # TODO: size
-        text = pya.DText(text, pya.DTrans(point.getX(), point.getY()), 1, 0)
-
-        self._text = text
-        self._layer = layer
-
-        self.set_shape(Shape.getCell().shapes(layer.number).insert(text))
-        super().__init__(Box(text.bbox().left, text.bbox().bottom, text.bbox().right, text.bbox().top))
-
-    def addToRegion(self, region: pya.Region):
-        region.insert(self._text)
-
-    def clone(self, nameMap : NameMapper = NameMapper(), netMap : NameMapper = NameMapper()):
-        return Text(self._layer, self._text.dup())
-
-    def destroy(self):
-        if not self._text._destroyed():
-            Shape.getCell().shapes(self.getShape().layer).erase(self.getShape())
-            self._text._destroy()
-        else:
-            pya.Logger.warn(f"Text.destroy: already destroyed!")
-
-    def moveBy(self, dx: float, dy: float) -> None:
-        movedText = (pya.DTrans(float(dx), float(dy)) * self._text)
-        shape = Shape.getCell().shapes(self._shape.layer).insert(movedText)
-        self.destroy()
-        self._polygon = movedPolygon
-        self.set_shape(shape)
-
-    def setAlignment(self, align):
-        # TODO
-        pass
-
-    def setOrientation(self, orient):
-        # TODO
-        pass
-
-    def setDrafting(self, drafting):
-        # TODO
-        pass
-
-    def transform(self, transform: Transform) -> None:
-        transformedText = self._text.transformed(transform.transform)
-        shape = Shape.getCell().shapes(self.getShape().layer).insert(transformedText)
-        self.destroy()
-        self._text = transformedText
-        self.set_shape(shape)
-
diff --git a/ihp-sg13g2/libs.tech/klayout/python/cni/transform.py b/ihp-sg13g2/libs.tech/klayout/python/cni/transform.py
deleted file mode 100644
index 4aad4067..00000000
--- a/ihp-sg13g2/libs.tech/klayout/python/cni/transform.py
+++ /dev/null
@@ -1,139 +0,0 @@
-########################################################################
-#
-# Copyright 2024 IHP PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#    https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-########################################################################
-
-from __future__ import annotations
-from functools import singledispatchmethod
-from cni.orientation import *
-from cni.point import *
-from cni.orientation import *
-
-import pya
-
-class Transform(object):
-    """
-    The Transform class provides the ability to implement two-dimensional
-    transformations, consisting of orientation changes (rotations and mirroring about the
-    coordinate axes), translation (offsets in the X and Y directions), and magnification of the
-    X and Y coordinates, with the operations performed in the following order:
-        1. Rotation/Mirroring
-        2. Translation
-        3. Magnification
-    When rotation operations are performed on an object in the layout design, it is important
-    to note that it may be necessary to first translate the object to the origin of the DLO
-    coordinate system, apply the rotation operation, and then translate the object back to its
-    original location. This would be necessary, because the center of rotation is the origin of
-    the coordinate system, not the center of the object. With this approach, the object will be
-    rotated about the center of the object. Otherwise, the resulting rotation may not produce
-    the expected results. In order to more easily handle this situation, the rotate() methods
-    are provided by this Transform class.
-
-    Creation:\n
-    The Transform object can be directly created using the desired x and y coordinate values
-    for the translation operation, the desired orientation value, and the desired magnification
-    value. The individual x and y coordinate values can be specified, or the corresponding
-    Point object can be used instead. Thus, this Transform object can be created using either
-    of the following forms:
-
-    Transform(Coord x, Coord y, Orientation o=R0, double mag=1.0)\n
-    Transform(Point offset, Orientation o=R0, double mag=1.0)
-
-    If these values are not specified, then default values will be generated and used.
-
-    """
-    @singledispatchmethod
-    def __init__(self, arg1, arg2, arg3, arg4 = None):
-        pass
-
-    @__init__.register
-    def _(self, arg1: float, arg2: float, arg3: Orientation = Orientation.R0, arg4: float = 1.0):
-        self._internalInit(arg1, arg2, arg3, arg4)
-
-    @__init__.register
-    def _(self, arg1: int, arg2: float, arg3: Orientation = Orientation.R0, arg4: float = 1.0):
-        self._internalInit(arg1, arg2, arg3, arg4)
-
-    @__init__.register
-    def _(self, arg1: Point, arg2: Orientation = Orientation.R0, arg3 : float = 1.0):
-        self._internalInit(arg1.x, arg1.y, arg2, arg3)
-
-    def _internalInit(self, x: float, y: float, orientation: Orientation, magnification: float) -> None:
-        self._x = x
-        self._y = y
-        self._orientation = orientation
-        self._mag = magnification
-
-        match orientation:
-            case Orientation.R0:
-                self._transform = pya.DCplxTrans(magnification, 0, False, x, y)
-            case Orientation.R90:
-                self._transform = pya.DCplxTrans(magnification, 90, False, x, y)
-            case Orientation.R180:
-                self._transform = pya.DCplxTrans(magnification, 180, False, x, y)
-            case Orientation.R270:
-                self._transform = pya.DCplxTrans(magnification, 270, False, x, y)
-            case Orientation.MYR90:
-                self._transform = pya.DCplxTrans(magnification, 90, False, x, y) * pya.DCplxTrans.M90
-            case Orientation.MXR90:
-                self._transform = pya.DCplxTrans(magnification, 90, True, x, y)
-            case Orientation.MY:
-                self._transform = pya.DCplxTrans(magnification, 0, False, x, y) * pya.DCplxTrans.M90
-            case Orientation.MX:
-                self._transform = pya.DCplxTrans(magnification, 0, True, x, y)
-            case _:
-                raise Exception(f"Unknown orientation '{orientation}'")
-
-    @property
-    def transform(self):
-        """
-        returns the internal transform representation
-
-        """
-        return self._transform
-
-    @property
-    def xOffset(self):
-        """
-        returns the x-coordinate value of the offset for this Transform
-
-        """
-        return self._x
-
-    @property
-    def yOffset(self):
-        """
-        returns the y-coordinate value of the offset for this Transform
-
-        """
-        return self._y
-
-    @property
-    def mag(self):
-        """
-        returns the magnification value for this Transform
-
-        """
-        return self._mag
-
-    @property
-    def orientation(self):
-        """
-        returns the orientation value for this Transform
-
-        """
-        return self._orientation
-
diff --git a/ihp-sg13g2/libs.tech/klayout/python/cni/ulist.py b/ihp-sg13g2/libs.tech/klayout/python/cni/ulist.py
deleted file mode 100644
index b4563778..00000000
--- a/ihp-sg13g2/libs.tech/klayout/python/cni/ulist.py
+++ /dev/null
@@ -1,31 +0,0 @@
-########################################################################
-#
-# Copyright 2024 IHP PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#    https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-########################################################################
-
-from typing import TypeVar, Generic
-
-T = TypeVar('T')
-
-class ulist(list[T]):
-
-    def __init__(self, items = None) -> None:
-        if items is not None:
-            super().__init__(items)
-
-    def append(self, item) -> None:
-        super().append(item)
-
diff --git a/ihp-sg13g2/libs.tech/klayout/python/doc/pycell4klayout.pdf b/ihp-sg13g2/libs.tech/klayout/python/doc/pycell4klayout.pdf
deleted file mode 100644
index a7961b7a..00000000
Binary files a/ihp-sg13g2/libs.tech/klayout/python/doc/pycell4klayout.pdf and /dev/null differ
diff --git a/ihp-sg13g2/libs.tech/klayout/python/pycell4klayout-api b/ihp-sg13g2/libs.tech/klayout/python/pycell4klayout-api
new file mode 160000
index 00000000..6dc3d13d
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/python/pycell4klayout-api
@@ -0,0 +1 @@
+Subproject commit 6dc3d13d8a82eb82e16858c34cb37f8f06af5e1a
diff --git a/ihp-sg13g2/libs.tech/klayout/python/pypreprocessor b/ihp-sg13g2/libs.tech/klayout/python/pypreprocessor
new file mode 160000
index 00000000..6ddd5783
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/python/pypreprocessor
@@ -0,0 +1 @@
+Subproject commit 6ddd5783365718c41eb69bce4428358ace4d1fa2
diff --git a/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/__init__.py b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/__init__.py
index ffe7f1c5..15360072 100644
--- a/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/__init__.py
+++ b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/__init__.py
@@ -20,40 +20,219 @@
 import os
 import sys
 
-from cni.dlo import Tech
+from cni.tech import Tech
 from cni.dlo import PCellWrapper
 
 # Creates the SG13_dev technology
 from .sg13_tech import *
 
-# Defines the IHP PCells
-from .ihp import nmos_code
-from .ihp import pmos_code
-from .ihp import cmim_code
-from .ihp import rsil_code
-from .ihp import rhigh_code
-from .ihp import rppd_code
-from .ihp import sealring_code
-from .ihp import npn13G2_base_code
-from .ihp import npn13G2_code
+from pypreprocessor.pypreprocessor import preprocessor as preProcessor
 
+import pya
+
+import os
+import io
+import sys
+import inspect
+import re
+import importlib
+import importlib.util
+import pathlib
+import tempfile
+import traceback
+
+moduleNames = [
+        'nmos_code',
+        'nmosHV_code',
+        'pmos_code',
+        'pmosHV_code',
+        'cmim_code',
+        'rsil_code',
+        'rhigh_code',
+        'rppd_code',
+        'sealring_code',
+        'npn13G2_base_code',
+        'npn13G2_code',
+        'npn13G2L_code',
+        'npn13G2V_code',
+        'inductor2_code',
+        'inductor2_sc_code',
+        'inductor2_sp_code',
+        'inductor3_code',
+        'inductor3_sc_code',
+        'inductor3_sp_code',
+        'dantenna_code',
+        'dpantenna_code'
+]
+
+def getProcessNames():
+    processNames = []
+    maxDepth = 10
+
+    if sys.platform.startswith('win'):
+        process = pya.QProcess()
+        powershellCmd = (
+            "Get-CimInstance Win32_Process | "
+            "Select-Object ProcessId, ParentProcessId, Name | "
+            "Format-Table -HideTableHeaders"
+        )
+        process.start("powershell", ["-Command", powershellCmd])
+        process.waitForFinished()
+        output = process.readAllStandardOutput().decode()
+
+        # Parse the output into a list of tuples (pid, ppid, name)
+        processList = []
+        for line in output.splitlines():
+            parts = line.split()
+            if len(parts) >= 3:
+                pid = int(parts[0])
+                ppid = int(parts[1])
+                name = ' '.join(parts[2:])
+                processList.append((pid, ppid, name))
+
+        processDict = {pid: (ppid, name) for pid, ppid, name in processList}
+        currentPid = os.getpid()
+
+        while currentPid in processDict and maxDepth > 0:
+            maxDepth -= 1
+            ppid, name = processDict[currentPid]
+            processNames.append(name.lower())
+            if ppid == currentPid or ppid == 0:
+                break
+            currentPid = ppid
+
+    else:
+        import psutil
+
+        parent = None
+
+        p = psutil.Process()
+        with p.oneshot():
+            processNames.append(p.name().lower())
+            parent = p.parent()
+
+        while parent is not None and maxDepth > 0:
+            maxDepth -= 1
+            with parent.oneshot():
+                processNames.append(parent.name().lower())
+                parent = parent.parent()
+
+    return processNames
+
+
+"""
+Support for 'conditional compilation' in a C-style manner of PyCell code:
+
+#ifdef name
+    ...some_code...
+#else
+    ...some_other_code...
+#endif
+
+The #ifdef-block is executed (name is considered as defined) if
+  1. An environment variable 'name' can be found case-insentive, or
+  2. The name can be found case-insentive as part of a process name of the process chain beginnig at
+     the current process upwards through all parent processes.
+otherwise the #else-block is executed
+
+The current process chain will be dumped if the environment variable 'IHP_PYCELL_LIB_PRINT_PROCESS_TREE'
+is set.
+
+The list of names which are used in an #ifdef-statement and are considered as 'defined' will be dumped
+if the environment variable 'IHP_PYCELL_LIB_PRINT_DEFINES_SET' is set.
+
+"""
 class PyCellLib(pya.Library):
     def __init__(self):
-        self.description = "SG13_dev"
+        self.description = "IHP SG13G2 Pcells"
 
         tech = Tech.get('SG13_dev')
 
-        # TODO: instead of explicitly creating the PCells here we could
-        # use introspection to collect the classes defined
-        self.layout().register_pcell("nmos", PCellWrapper(nmos_code.nmos(), tech))
-        self.layout().register_pcell("pmos", PCellWrapper(pmos_code.pmos(), tech))
-        self.layout().register_pcell("cmim", PCellWrapper(cmim_code.cmim(), tech))
-        self.layout().register_pcell("rsil", PCellWrapper(rsil_code.rsil(), tech))
-        self.layout().register_pcell("rhigh", PCellWrapper(rhigh_code.rhigh(), tech))
-        self.layout().register_pcell("rppd", PCellWrapper(rppd_code.rppd(), tech))
-        self.layout().register_pcell("sealring", PCellWrapper(sealring_code.sealring(), tech))
-        self.layout().register_pcell("npn13G2_base", PCellWrapper(npn13G2_base_code.npn13G2_base(), tech))
-        self.layout().register_pcell("npn13G2", PCellWrapper(npn13G2_code.npn13G2(), tech))
+        processNames = getProcessNames()
+
+        if os.getenv('IHP_PYCELL_LIB_PRINT_PROCESS_TREE') is not None:
+            processChain = ''
+            isFirst = True
+            for processName in reversed(processNames):
+                if not isFirst:
+                    processChain += ' <- '
+                processChain += "'" + processName + "'"
+                isFirst = False
+            print(f'Current process chain: {processChain}')
+
+        module = importlib.import_module(f"{__name__}.ihp.pypreprocessor")
+        preProcessor = getattr(module, "preprocessor")
+
+        definesSetToPrint = []
+
+        for moduleName in moduleNames:
+            defines = []
+            definesSet = []
+
+            modulePath = os.path.join(os.path.dirname(__file__), 'ihp', f"{moduleName}.py")
+            moduleFile = io.open(modulePath, 'r', encoding=sys.stdin.encoding)
+
+            try:
+                for line in moduleFile:
+                    match = re.match(r'^#ifdef\s+\w+', line)
+                    if match:
+                        splittedLine = line.split()
+                        for i, define in enumerate(splittedLine):
+                            if i % 2 == 1:
+                                if define not in defines:
+                                    defines.append(define)
+
+            finally:
+                moduleFile.close()
+
+            envs = []
+            for env in os.environ:
+                envs.append(env.lower())
+
+            for define in defines:
+                locDefine = define.lower()
+                for processName in processNames:
+                    if processName.find(locDefine) != -1:
+                        definesSet.append(define)
+                else:
+                    if locDefine in envs:
+                        definesSet.append(define)
+
+            for defineSet in definesSet:
+                definesSetToPrint.append(defineSet)
+
+            modulePreProcPath = None
+
+            if len(defines) > 0:
+                modulePreProcPath = os.path.join(tempfile.gettempdir(), f"{moduleName}_pre.py")
+
+                pyPreProcessor = preProcessor(modulePath, modulePreProcPath, definesSet, removeMeta=False, resume=True, run=False)
+                pyPreProcessor.parse()
+
+                spec = importlib.util.spec_from_file_location(f"{__name__}.ihp.{moduleName}", modulePreProcPath)
+                module = importlib.util.module_from_spec(spec)
+                sys.modules[moduleName] = module
+
+                try:
+                    spec.loader.exec_module(module)
+                except:
+                    trace = traceback.format_exc().splitlines()
+                    for line in trace:
+                        print(line.replace(modulePreProcPath, modulePath))
+
+                    sys.exit(1)
+
+                os.remove(modulePreProcPath)
+            else:
+                module = importlib.import_module(f"{__name__}.ihp." + moduleName)
+
+            match = re.fullmatch(r'^(\S+)_code$', moduleName)
+            if match:
+                func = getattr(module, f"{match.group(1)}")
+                self.layout().register_pcell(match.group(1), PCellWrapper(func(), tech, modulePreProcPath, modulePath))
+
+        if os.getenv('IHP_PYCELL_LIB_PRINT_DEFINES_SET') is not None:
+            print(f"Current defines set: {definesSetToPrint}")
 
         self.register("SG13_dev")
 
diff --git a/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/dantenna_code.py b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/dantenna_code.py
new file mode 100644
index 00000000..372de78f
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/dantenna_code.py
@@ -0,0 +1,100 @@
+__version__ = "$Revision: #3 $"
+
+from cni.dlo import *
+from .geometry import *
+from .utility_functions import *
+
+import math
+
+
+class dantenna(DloGen):
+
+    @classmethod
+    def defineParamSpecs(self, specs):
+        techparams = specs.tech.getTechParams()
+
+        CDFVersion = techparams['CDFVersion']
+        model = techparams['dantenna_model']
+        defL = techparams['dantenna_defL']
+        defW = techparams['dantenna_defW']
+
+        specs('cdf_version', CDFVersion, 'CDF Version')
+        specs('Display', 'Selected', 'Display', ChoiceConstraint(['All', 'Selected']))
+        specs('model', model, 'Model name')
+        specs('Calculate', 'a', 'Calculate', ChoiceConstraint(['a', 'w', 'l', 'w&l']))
+
+        specs('w', defW, 'Width')
+        specs('l', defL, 'Length')
+        specs('a', eng_string(CbDiodeCalc('a', 0, Numeric(defL), Numeric(defW), 'dantenna'), 3), 'Device area')
+        specs('p', eng_string(CbDiodeCalc('p', 0, Numeric(defL), Numeric(defW), 'dantenna'), 3), 'Device perimeter')
+
+        specs('addRecLayer', 't', 'Add Recognition Layer', ChoiceConstraint(['t', 'f']))
+        specs('bn', 'sub!', 'Bulk node connection')
+        specs('off', False, 'Device initially off')
+        specs('Vd', '', 'Initial diode voltage')
+        specs('perim', '', 'Junction perimeter factor')
+        specs('m', '1', 'Multiplier')
+        specs('trise', '', 'Temp rise from ambient')
+        specs('region', ' ', 'Estimated operating region', ChoiceConstraint([' ', 'off', 'on']))
+        specs('dtemp', '', 'Temperature difference')
+        specs('mode', 'No', 'Linearized Region', ChoiceConstraint(['Yes', 'No']))
+
+    def setupParams(self, params):
+        # process parameter values entered by user
+        self.w = Numeric(params['w']) * 1e6
+        self.l = Numeric(params['l']) * 1e6
+        self.addRecLayer = params['addRecLayer']
+
+    def genLayout(self):
+        w = self.w
+        l = self.l
+        addRecLayer = self.addRecLayer
+
+        self.techparams = self.tech.getTechParams()
+        epsilon = self.techparams['epsilon1']
+
+        typ = 'N'
+        metall_layer = Layer('Metal1')
+        ndiff_layer = Layer('Activ')
+        pdiff_layer = Layer('Activ')
+        pdiffx_layer = Layer('pSD')
+        cont_layer = Layer('Cont')
+        diods_layer = Layer('Recog', 'diode')
+        textlayer = Layer('TEXT', 'drawing')
+
+        cont_size = self.techparams['Cnt_a']
+        cont_dist = self.techparams['Cnt_b']
+        cont_diff_over = self.techparams['Cnt_c']
+        pdiffx_over = self.techparams['pSD_c']
+        wmin = Numeric(self.techparams['dantenna_minW']) * 1e6
+        lmin = Numeric(self.techparams['dantenna_minL']) * 1e6
+        diods_over = Numeric(self.techparams['dantenna_dov']) * 1e6
+
+        dbReplaceProp(self, 'pin#', 2)
+
+        if w < wmin - epsilon:
+            w = wmin
+            hiGetAttention()
+            print('W < ' + str(wmin))
+
+        if l < lmin - epsilon:
+            l = lmin
+            hiGetAttention()
+            print('L < ' + str(lmin))
+
+        dbCreateLabel(self, textlayer, Point(w / 2, l / 2), 'dant', 'centerCenter', 'R0', Font.EURO_STYLE, 0.2)
+
+        bBox = DrawContArray(self, cont_layer, Box(0, 0, w, l), cont_size, cont_dist, cont_diff_over)
+
+        dbCreateRect(self, metall_layer, bBox)
+
+        MkPin(self, 'MINUS', 1, bBox, metall_layer)
+
+        if typ == 'N':
+            dbCreateRect(self, ndiff_layer, Box(0, 0, w, l))
+        else:
+            dbCreateRect(self, pdiff_layer, Box(0, 0, w, l))
+            dbCreateRect(self, pdiffx_layer, Box(-pdiffx_over, -pdiffx_over, w + pdiffx_over, l + pdiffx_over))
+
+        if addRecLayer == 't':
+            dbCreateRect(self, diods_layer, Box(-diods_over, -diods_over, w + diods_over, l + diods_over))
\ No newline at end of file
diff --git a/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/dpantenna_code.py b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/dpantenna_code.py
new file mode 100644
index 00000000..fd138f33
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/dpantenna_code.py
@@ -0,0 +1,97 @@
+__version__ = '$Revision: #3 $'
+
+from cni.dlo import *
+from .geometry import *
+from .utility_functions import *
+
+import math
+
+
+class dpantenna(DloGen):
+
+    @classmethod
+    def defineParamSpecs(self, specs):
+        techparams = specs.tech.getTechParams()
+
+        CDFVersion = techparams['CDFVersion']
+        model = techparams['dpantenna_model']
+        defL = techparams['dpantenna_defL']
+        defW = techparams['dpantenna_defW']
+
+        specs('cdf_version', CDFVersion, 'CDF Version')
+        specs('Display', 'Selected', 'Display', ChoiceConstraint(['All', 'Selected']))
+        specs('model', model, 'Model name')
+        specs('Calculate', 'a', 'Calculate', ChoiceConstraint(['a', 'w', 'l', 'w&l']))
+
+        specs('w', defW, 'Width')
+        specs('l', defL, 'Length')
+        specs('a', eng_string(CbDiodeCalc('a', 0, Numeric(defL), Numeric(defW), 'dantenna'), 3), 'Device area')
+        specs('p', eng_string(CbDiodeCalc('p', 0, Numeric(defL), Numeric(defW), 'dantenna'), 3), 'Device perimeter')
+
+        specs('addRecLayer', 't', 'Add Recognition Layer', ChoiceConstraint(['t', 'f']))
+        specs('off', False, 'Device initially off')
+        specs('Vd', '', 'Initial diode voltage')
+        specs('perim', '', 'Junction perimeter factor')
+        specs('m', '1', 'Multiplier')
+        specs('trise', '', 'Temp rise from ambient')
+        specs('region', ' ', 'Estimated operating region', ChoiceConstraint([' ', 'off', 'on']))
+        specs('dtemp', '', 'Temperature difference')
+        specs('mode', 'No', 'Linearized Region', ChoiceConstraint(['Yes', 'No']))
+
+    def setupParams(self, params):
+        # process parameter values entered by user
+        self.w = Numeric(params['w']) * 1e6
+        self.l = Numeric(params['l']) * 1e6
+        self.addRecLayer = params['addRecLayer']
+
+    def genLayout(self):
+        w = self.w
+        l = self.l
+        addRecLayer = self.addRecLayer
+
+        self.techparams = self.tech.getTechParams()
+        self.epsilon = self.techparams['epsilon1']
+
+        metall_layer = Layer('Metal1')
+        pdiff_layer = Layer('Activ')
+        pdiffx_layer = Layer('pSD')
+        cont_layer = Layer('Cont')
+        diods_layer = Layer('Recog', 'diode')
+        text_layer = Layer('TEXT')
+        nwell_layer = Layer('NWell')
+        cont_size = self.techparams['Cnt_a']
+        cont_dist = self.techparams['Cnt_b']
+        cont_diff_over = self.techparams['Cnt_c']
+        pdiffx_over = self.techparams['pSD_c']
+        wmin = Numeric(self.techparams['dpantenna_minW']) * 1e6
+        lmin = Numeric(self.techparams['dpantenna_minL']) * 1e6
+        diods_over = Numeric(self.techparams['dpantenna_dov']) * 1e6
+        NW_c = self.techparams['NW_c']
+
+        dbReplaceProp(self, 'pin#', 2)
+
+        if w < wmin - self.epsilon:
+            w = wmin
+            hiGetAttention()
+            print('W < ' + str(wmin))
+
+        if l < lmin - self.epsilon:
+            l = lmin
+            hiGetAttention()
+            print('L < ' + str(lmin))
+
+        dbCreateLabel(self, text_layer, Point(w / 2, l / 2), 'dpant', 'centerCenter', 'R0', Font.EURO_STYLE, 0.2)
+
+        bBox = DrawContArray(self, cont_layer, Box(0, 0, w, l), cont_size, cont_dist, cont_diff_over)
+
+        dbCreateRect(self, metall_layer, bBox)
+
+        MkPin(self, 'MINUS', 1, bBox, metall_layer)
+
+        pdiffRect = dbCreateRect(self, pdiff_layer, Box(0, 0, w, l))
+        dbCreateRect(self, pdiffx_layer, Box(-pdiffx_over, -pdiffx_over, w + pdiffx_over, l + pdiffx_over))
+
+        if addRecLayer == 't':
+            dbCreateRect(self, diods_layer, Box(-diods_over, -diods_over, w + diods_over, l + diods_over))
+
+        dbLayerSize(nwell_layer, [pdiffRect], NW_c)
diff --git a/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/geometry.py b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/geometry.py
index 9599b053..1867bfb7 100644
--- a/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/geometry.py
+++ b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/geometry.py
@@ -23,7 +23,6 @@
 from cni.geo import fgAnd
 from cni.geo import fgXor
 from cni.geo import fgNot
-from cni.geo import fgMerge
 from .utility_functions import *
 from math import *
 
@@ -118,7 +117,6 @@ def dbLayerAndList(layerId, shapes):
 def dbLayerXor(layerId, id1, id2):
     if type(layerId) == str :
         layerId = Layer(layerId)
-
     xorId = id1.fgXor(id2, layerId)
 
     return xorId
@@ -126,13 +124,11 @@ def dbLayerXor(layerId, id1, id2):
 #***********************************************************************************************************************
 # dbLayerXorList
 #***********************************************************************************************************************
-def dbLayerXorList(layerId, shapes):
+def dbLayerXorList(layerId, shapes1, shapes2):
     if type(layerId) == str :
         layerId = Layer(layerId)
 
-    xorId = shapes[0]
-    for id in shapes[1:] :
-        xorId = fgXor(xorId, id, layerId)
+    xorId = fgXor(ulist(shapes1), ulist(shapes2), layerId)
 
     return xorId
 
@@ -173,9 +169,12 @@ def dbLayerMerge(self, layerId):
     return mergeId
 
 #***********************************************************************************************************************
-# dbCopyShape
+# dbLayerSize
 #***********************************************************************************************************************
-def dbLayerSize(self, layerId, shapes, size, numPoints, grid = 0) :
+def dbLayerSize(layerId, shapes, size, grid = 0) :
+    if type(layerId) == str :
+        layerId = Layer(layerId)
+
     for id in shapes :
         id.fgSize(ShapeFilter(), size, layerId, grid)
 
diff --git a/ihp-sg13g2/libs.tech/pycell/inductor2_code.py b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/inductor2_code.py
similarity index 90%
rename from ihp-sg13g2/libs.tech/pycell/inductor2_code.py
rename to ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/inductor2_code.py
index 071b6137..c66e95e0 100644
--- a/ihp-sg13g2/libs.tech/pycell/inductor2_code.py
+++ b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/inductor2_code.py
@@ -1,13 +1,13 @@
 ########################################################################
 #
-# Copyright 2023 IHP PDK Authors
-# 
+# Copyright 2024 IHP PDK Authors
+#
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
 # You may obtain a copy of the License at
-# 
+#
 #    https://www.apache.org/licenses/LICENSE-2.0
-# 
+#
 # Unless required by applicable law or agreed to in writing, software
 # distributed under the License is distributed on an "AS IS" BASIS,
 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -17,10 +17,10 @@
 ########################################################################
 __version__ = '$Revision: #3 $'
 
-from inductors_code import *
-    
+from .inductors_code import *
+
 class inductor2(inductors):
-    
+
     DMIN = '15.48u'
     NR = 1
     model = 'inductor2'
diff --git a/ihp-sg13g2/libs.tech/pycell/inductor2_sc_code.py b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/inductor2_sc_code.py
similarity index 90%
rename from ihp-sg13g2/libs.tech/pycell/inductor2_sc_code.py
rename to ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/inductor2_sc_code.py
index a2f19f0e..82e3b122 100644
--- a/ihp-sg13g2/libs.tech/pycell/inductor2_sc_code.py
+++ b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/inductor2_sc_code.py
@@ -1,13 +1,13 @@
 ########################################################################
 #
-# Copyright 2023 IHP PDK Authors
-# 
+# Copyright 2024 IHP PDK Authors
+#
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
 # You may obtain a copy of the License at
-# 
+#
 #    https://www.apache.org/licenses/LICENSE-2.0
-# 
+#
 # Unless required by applicable law or agreed to in writing, software
 # distributed under the License is distributed on an "AS IS" BASIS,
 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -17,10 +17,10 @@
 ########################################################################
 __version__ = '$Revision: #3 $'
 
-from inductors_code import *
-    
+from .inductors_code import *
+
 class inductor2_sc(inductors):
-    
+
     DMIN = '15.48u'
     NR = 1
     model = 'inductor2_sc'
diff --git a/ihp-sg13g2/libs.tech/pycell/inductor2_sp_code.py b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/inductor2_sp_code.py
similarity index 90%
rename from ihp-sg13g2/libs.tech/pycell/inductor2_sp_code.py
rename to ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/inductor2_sp_code.py
index f9f44c1c..0e5d584c 100644
--- a/ihp-sg13g2/libs.tech/pycell/inductor2_sp_code.py
+++ b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/inductor2_sp_code.py
@@ -1,13 +1,13 @@
 ########################################################################
 #
-# Copyright 2023 IHP PDK Authors
-# 
+# Copyright 2024 IHP PDK Authors
+#
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
 # You may obtain a copy of the License at
-# 
+#
 #    https://www.apache.org/licenses/LICENSE-2.0
-# 
+#
 # Unless required by applicable law or agreed to in writing, software
 # distributed under the License is distributed on an "AS IS" BASIS,
 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -17,9 +17,9 @@
 ########################################################################
 __version__ = '$Revision: #3 $'
 
-from inductors_code import *
-    
+from .inductors_code import *
+
 class inductor2_sp(inductors):
-    
+
     DMIN = '15.48u'
     model = 'inductor2_sp'
diff --git a/ihp-sg13g2/libs.tech/pycell/inductor3_code.py b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/inductor3_code.py
similarity index 90%
rename from ihp-sg13g2/libs.tech/pycell/inductor3_code.py
rename to ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/inductor3_code.py
index 75d69e9d..a0685fb2 100644
--- a/ihp-sg13g2/libs.tech/pycell/inductor3_code.py
+++ b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/inductor3_code.py
@@ -1,13 +1,13 @@
 ########################################################################
 #
-# Copyright 2023 IHP PDK Authors
-# 
+# Copyright 2024 IHP PDK Authors
+#
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
 # You may obtain a copy of the License at
-# 
+#
 #    https://www.apache.org/licenses/LICENSE-2.0
-# 
+#
 # Unless required by applicable law or agreed to in writing, software
 # distributed under the License is distributed on an "AS IS" BASIS,
 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -17,10 +17,10 @@
 ########################################################################
 __version__ = '$Revision: #3 $'
 
-from inductors_code import *
-    
+from .inductors_code import *
+
 class inductor3(inductors):
-    
+
     DMIN = '25.84u'
     NR = 2
     model = 'inductor3'
diff --git a/ihp-sg13g2/libs.tech/pycell/inductor3_sc_code.py b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/inductor3_sc_code.py
similarity index 90%
rename from ihp-sg13g2/libs.tech/pycell/inductor3_sc_code.py
rename to ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/inductor3_sc_code.py
index b33fd717..0c7413b3 100644
--- a/ihp-sg13g2/libs.tech/pycell/inductor3_sc_code.py
+++ b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/inductor3_sc_code.py
@@ -1,13 +1,13 @@
 ########################################################################
 #
-# Copyright 2023 IHP PDK Authors
-# 
+# Copyright 2024 IHP PDK Authors
+#
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
 # You may obtain a copy of the License at
-# 
+#
 #    https://www.apache.org/licenses/LICENSE-2.0
-# 
+#
 # Unless required by applicable law or agreed to in writing, software
 # distributed under the License is distributed on an "AS IS" BASIS,
 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -17,10 +17,10 @@
 ########################################################################
 __version__ = '$Revision: #3 $'
 
-from inductors_code import *
-    
+from .inductors_code import *
+
 class inductor3_sc(inductors):
-    
+
     DMIN = '25.84u'
     NR = 2
     model = 'inductor3_sc'
diff --git a/ihp-sg13g2/libs.tech/pycell/inductor3_sp_code.py b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/inductor3_sp_code.py
similarity index 90%
rename from ihp-sg13g2/libs.tech/pycell/inductor3_sp_code.py
rename to ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/inductor3_sp_code.py
index 7de61657..93495b0f 100644
--- a/ihp-sg13g2/libs.tech/pycell/inductor3_sp_code.py
+++ b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/inductor3_sp_code.py
@@ -1,13 +1,13 @@
 ########################################################################
 #
-# Copyright 2023 IHP PDK Authors
-# 
+# Copyright 2024 IHP PDK Authors
+#
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
 # You may obtain a copy of the License at
-# 
+#
 #    https://www.apache.org/licenses/LICENSE-2.0
-# 
+#
 # Unless required by applicable law or agreed to in writing, software
 # distributed under the License is distributed on an "AS IS" BASIS,
 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -17,9 +17,9 @@
 ########################################################################
 __version__ = '$Revision: #3 $'
 
-from inductors_code import *
-    
+from .inductors_code import *
+
 class inductor3_sp(inductors):
-    
+
     DMIN = '25.84u'
     model = 'inductor3_sp'
diff --git a/ihp-sg13g2/libs.tech/pycell/inductors_code.py b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/inductors_code.py
similarity index 92%
rename from ihp-sg13g2/libs.tech/pycell/inductors_code.py
rename to ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/inductors_code.py
index 99e6dec0..67ee2808 100644
--- a/ihp-sg13g2/libs.tech/pycell/inductors_code.py
+++ b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/inductors_code.py
@@ -1,13 +1,13 @@
 ########################################################################
 #
-# Copyright 2023 IHP PDK Authors
-# 
+# Copyright 2024 IHP PDK Authors
+#
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
 # You may obtain a copy of the License at
-# 
+#
 #    https://www.apache.org/licenses/LICENSE-2.0
-# 
+#
 # Unless required by applicable law or agreed to in writing, software
 # distributed under the License is distributed on an "AS IS" BASIS,
 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -18,21 +18,21 @@
 __version__ = '$Revision: #3 $'
 
 from cni.dlo import *
-from geometry import *
-from utility_functions import *
+from .geometry import *
+from .utility_functions import *
 
 import math
-    
+
 class inductors(DloGen):
 
-    @classmethod        
+    @classmethod
     def defineParamSpecs(self, specs):
         techparams = specs.tech.getTechParams()
-        
+
         CDFVersion = techparams['CDFVersion']
-        
-        defS = '2.1u'  
-        defW = '2u'    
+
+        defS = '2.1u'
+        defW = '2u'
         minS = defS
         minW = defW
         if 'inductor2' in self.model :
@@ -47,16 +47,16 @@ def defineParamSpecs(self, specs):
             defL     = '221.5pH'
             defR     = '1.386'
             model    = 'inductor3'
-    
+
         grid  = techparams['grid']
         minDf = inductor_minD(2, 2.1, defNr_t, grid)
         minD  = str(minDf)+'u'
         defD  = minD
-        
+
         specs('cdf_version', CDFVersion, 'CDF Version')
         specs('Display', 'Selected', 'Display', ChoiceConstraint(['All', 'Selected']))
         specs('model', self.model, 'Model name')
-        
+
         specs('w', defW, 'Width')
         specs('s', defS, 'Space')
         specs('d', self.DMIN, 'The distance in the center of the inductor')
@@ -65,10 +65,10 @@ def defineParamSpecs(self, specs):
         specs('nr_r', defNr_t, 'The number of turns')
         specs('blockqrc', True, 'Block QRC layer')
         specs('subE', False, 'Substrate Etching')
-        
+
         specs('lEstim', defL, 'Inductance (estim.)')
         specs('rEstim', defR, 'Resistance (estim.)')
-        
+
         specs('Wmin', minW, 'Wmin')
         specs('Smin', minS, 'Smin')
         specs('Dmin', self.DMIN, 'Dmin')
@@ -98,14 +98,14 @@ def genLayout(self):
         nr_r = self.nr_r
         blockqrc = self.blockqrc
         subE = self.subE
-        
+
         cellName = self.__class__.__name__
-            
+
         w = GridFix(Numeric(w)*5e5)*2
         s = GridFix(Numeric(s)*1e6)
         d = GridFix(Numeric(d)*5e5)*2
         d1 = d
-        
+
         # layers
         TM2 = Layer('TopMetal2', 'drawing')
         TM1 = Layer('TopMetal1', 'drawing')
@@ -123,83 +123,83 @@ def genLayout(self):
         NoTMet2Filler = Layer('TopMetal2', 'nofill')
         NoRCX = Layer('NoRCX', 'drawing')
         substrateE = Layer('LBE', 'drawing')
-        
+
         self.techparams = self.tech.getTechParams()
         self.epsilon = self.techparams['epsilon1']
         #tech_libName = self.techparams['libName']
         #grid = self.tech.getGridResolution()
-        
+
         nr_vias = round((w+0.06)/1.96-0.5)
-        
+
         var = 1+sqrt(2)
         grid = 0.01
         d_min = inductor_minD(w, s, nr_r, grid)
         if d < d_min :
             d = d_min
-            
+
         lat_sm = GridFix(d/(2*var))*2
         lat_big = GridFix((d+2*w)/var)
         cateta_sm = (d-lat_sm)/2
         cateta_big = GridFix((d+2*w)/(var*sqrt(2)))
-        
+
         type2 = '2' in cellName
         type3 = '3' in cellName
         typesc = '_sc' in cellName
-        
+
         if type3 :
             pathPoints = PointList([Point(0, -1), Point(0, 30)])
             dbCreatePath(self, TM2, pathPoints, w);
             dbCreateLabel(self, Layer('TEXT', 'drawing'), Point(0, 0), 'LC', 'centerCenter', 'R0', Font.EURO_STYLE, w/2)
             pcInst = dbCreateRect(self, TM2p, Box(-w/2, -1, w/2, 1))
             pcPin = dbCreatePin(self, 'LC', pcInst)
-            
-        x1 = GridFix(lat_sm/2)-w      
+
+        x1 = GridFix(lat_sm/2)-w
         y1 = 30-w/2
         x2 = GridFix(lat_big/2)
         x = x1+(x2-x1)/2
         y2 = nr_r*w+(nr_r-1)*s+30-w
         x_cross = GridFix(w/sqrt(2)+s/2)
-        d_via_cross = GridFix(s*0.4143)+grid          
+        d_via_cross = GridFix(s*0.4143)+grid
         d1_via_cross = GridFix(w*0.4143)+grid
         x_via = x_cross+d_via_cross+grid
-        
+
         if type3 or (not oddp(nr_r)) :
             dbCreateRect(self, TM2, Box(-x_via, 30, x_via, w+30))
             if type2 :
                 dbCreateRect(self, IND, Box(-w/2-grid, 30-grid, w/2+grid, 30+w+grid))
                 dbCreateLabel(self, Layer('TEXT', 'drawing'), Point(0, w/2+30), 'L2_TM2', 'centerCenter', 'R0', Font.EURO_STYLE, w/6)
-                
-            
+
+
         lat_big2 = d1_via_cross+grid
         if (nr_r == 2) or (nr_r == 1) :
             if type3 :
                 x1_via = s+w/2+0.5+(w-nr_vias*0.9-(nr_vias-1)*1.06-1)/2
             else :
                 x1_via = s/2+0.5+(w-nr_vias*0.9-(nr_vias-1)*1.06-1)/2
-                
+
         else :
             x1_via = x_via+s+w+0.5+(w-nr_vias*0.9-(nr_vias-1)*1.06-1)/2
-            
+
         y1_via = y2+0.5+(w-nr_vias*0.9-(nr_vias-1)*1.06-1)/2
-        
+
         if nr_r !=  1 :
             for pcIndex1 in range(int(nr_vias)) :
                 for pcIndex2 in range(int(nr_vias)) :
                     dbCreateRect(self, TV2, Box(x1_via, y1_via, x1_via+0.9, y1_via+0.9))
                     dbCreateRect(self, TV2, Box(-x1_via, y1_via, -(x1_via+0.9), y1_via+0.9))
                     x1_via = x1_via+1.96
-                    
+
                 if nr_r ==  2 :
                     if type3 :
                         x1_via = s+w/2+0.5+(w-nr_vias*0.9-(nr_vias-1)*1.06-1)/2
                     else :
                         x1_via = s/2+0.5+(w-nr_vias*0.9-(nr_vias-1)*1.06-1)/2
-                        
+
                 else :
                     x1_via = x_via+s+w+0.5+(w-nr_vias*0.9-(nr_vias-1)*1.06-1)/2
-                    
+
                 y1_via = y1_via+1.96
-                
+
         for pcIndexX in range(nr_r) :
             if pcIndexX == 0 :
                 if (nr_r == 2) or (nr_r == 1) :
@@ -217,24 +217,24 @@ def genLayout(self):
                         polyPoints2 = PointList([Point(-s/2, y2), Point(-s/2, y2+w), Point(-lat_sm/2, y2+w), Point(-d/2, y2+w+cateta_sm), Point(-d/2, y2+w+cateta_sm+lat_sm), Point(-lat_sm/2, y2+w+d),
                                                  Point(-x_via, y2+w+d), Point(-x_via, y2+w*2+d), Point(-lat_sm/2-d1_via_cross, y2+d+2*w), Point(-(d+2*w)/2, y2+w+cateta_sm+lat_sm+d1_via_cross),
                                                  Point(-(d+2*w)/2, y2+w+cateta_sm-d1_via_cross), Point(-lat_sm/2-d1_via_cross, y2)])
-                        
+
                 else :
                     polyPoints1 = PointList([Point(x_via+s+w, y2), Point(x_via+s+w, y2+w), Point(lat_sm/2, y2+w), Point(d/2, y2+w+cateta_sm), Point(d/2, y2+w+cateta_sm+lat_sm), Point(lat_sm/2, y2+w+d),
-                                             Point(x_via, y2+w+d), Point(x_via, y2+w*2+d), Point(lat_sm/2+d1_via_cross, y2+d+2*w), Point((d+2*w)/2, y2+w+cateta_sm+lat_sm+d1_via_cross), 
+                                             Point(x_via, y2+w+d), Point(x_via, y2+w*2+d), Point(lat_sm/2+d1_via_cross, y2+d+2*w), Point((d+2*w)/2, y2+w+cateta_sm+lat_sm+d1_via_cross),
                                              Point((d+2*w)/2, y2+w+cateta_sm-d1_via_cross), Point(lat_sm/2+d1_via_cross, y2)])
-                    polyPoints2 = PointList([Point(-x_via-s-w, y2), Point(-x_via-s-w, y2+w), Point(-lat_sm/2, y2+w), Point(-d/2, y2+w+cateta_sm), Point(-d/2, y2+w+cateta_sm+lat_sm), Point(-lat_sm/2, y2+w+d), 
-                                             Point(-x_via, y2+w+d), Point(-x_via, y2+w*2+d), Point(-lat_sm/2-d1_via_cross, y2+d+2*w), Point(-(d+2*w)/2, y2+w+cateta_sm+lat_sm+d1_via_cross), 
+                    polyPoints2 = PointList([Point(-x_via-s-w, y2), Point(-x_via-s-w, y2+w), Point(-lat_sm/2, y2+w), Point(-d/2, y2+w+cateta_sm), Point(-d/2, y2+w+cateta_sm+lat_sm), Point(-lat_sm/2, y2+w+d),
+                                             Point(-x_via, y2+w+d), Point(-x_via, y2+w*2+d), Point(-lat_sm/2-d1_via_cross, y2+d+2*w), Point(-(d+2*w)/2, y2+w+cateta_sm+lat_sm+d1_via_cross),
                                              Point(-(d+2*w)/2, y2+w+cateta_sm-d1_via_cross), Point(-lat_sm/2-d1_via_cross, y2)])
-                    
+
             else :
-                polyPoints1 = PointList([Point(x1, y2), Point(x1, y2+w), Point(lat_sm/2, y2+w), Point(d/2, y2+w+cateta_sm), Point(d/2, y2+w+cateta_sm+lat_sm), Point(lat_sm/2, y2+w+d), Point(x_via, y2+w+d), 
+                polyPoints1 = PointList([Point(x1, y2), Point(x1, y2+w), Point(lat_sm/2, y2+w), Point(d/2, y2+w+cateta_sm), Point(d/2, y2+w+cateta_sm+lat_sm), Point(lat_sm/2, y2+w+d), Point(x_via, y2+w+d),
                                          Point(x_via, y2+w*2+d), Point(lat_sm/2+d1_via_cross, y2+d+2*w), Point((d+2*w)/2, y2+w+cateta_sm+lat_sm+d1_via_cross), Point((d+2*w)/2, y2+w+cateta_sm-d1_via_cross), Point(lat_sm/2+d1_via_cross, y2)])
                 polyPoints2 = PointList([Point(-x1, y2), Point(-x1, y2+w), Point(-lat_sm/2, y2+w), Point(-d/2, y2+w+cateta_sm), Point(-d/2, y2+w+cateta_sm+lat_sm), Point(-lat_sm/2, y2+w+d), Point(-x_via, y2+w+d),
                                          Point(-x_via, y2+w*2+d), Point(-lat_sm/2-d1_via_cross, y2+d+2*w), Point(-(d+2*w)/2, y2+w+cateta_sm+lat_sm+d1_via_cross), Point(-(d+2*w)/2, y2+w+cateta_sm-d1_via_cross), Point(-lat_sm/2-d1_via_cross, y2)])
-                
+
             dbCreatePolygon(self, TM2, polyPoints1)
             dbCreatePolygon(self, TM2, polyPoints2)
-            
+
             # potential stopper left and right
             if type3 and pcIndexX == nr_r-1 :
                 x_mid = d/2+w/2
@@ -243,45 +243,45 @@ def genLayout(self):
                 dbCreateLabel(self, Layer('TEXT', 'drawing'), Point(x_mid, y_mid), 'L2_TM2', 'centerCenter', 'R0', Font.EURO_STYLE, w/6)
                 lh = eng_string(Numeric(l)*0.5, 3)
                 rh = eng_string(Numeric(r)*0.5, 3)
-                
+
                 if cellName == 'inductor3' :
                     dbCreateLabel(self, Layer('TEXT', 'drawing'), Point(x_mid, y_mid+w/3), 'l='+lh, 'centerCenter', 'R0', Font.EURO_STYLE, w/6)
                     dbCreateLabel(self, Layer('TEXT', 'drawing'), Point(x_mid, y_mid-w/3), 'r='+rh, 'centerCenter', 'R0', Font.EURO_STYLE, w/6)
-                    
+
                 if cellName == 'inductor3_sc' :
                     dbCreateLabel(self, Layer('TEXT', 'drawing'), Point(x_mid, y_mid-w/3), 'model='+model, 'centerCenter', 'R0', Font.EURO_STYLE, w/6)
-                    
+
                 x_mid = -d/2-w/2
                 dbCreateRect(self, IND, Box(-d/2+grid, y_mid-w/2, -(d+2*w)/2-grid, y_mid+w/2))
                 dbCreateLabel(self, Layer('TEXT', 'drawing'), Point(x_mid, y_mid), 'L2_TM2', 'centerCenter', 'R0', Font.EURO_STYLE, w/6)
-               
+
                 if cellName == 'inductor3' :
                     dbCreateLabel(self, Layer('TEXT', 'drawing'), Point(x_mid, y_mid+w/3), 'l='+lh, 'centerCenter', 'R0', Font.EURO_STYLE, w/6)
                     dbCreateLabel(self, Layer('TEXT', 'drawing'), Point(x_mid, y_mid-w/3), 'r='+rh, 'centerCenter', 'R0', Font.EURO_STYLE, w/6)
-                    
+
                 if cellName == 'inductor3_sc' :
                     dbCreateLabel(self, Layer('TEXT', 'drawing'), Point(x_mid, y_mid-w/3), 'model='+model, 'centerCenter', 'R0', Font.EURO_STYLE, w/6)
-                    
-                
+
+
             if evenp(pcIndexX) :
                 if type2 and (oddp(nr_r) and (pcIndexX == nr_r-1)) :
                     polyPoints4 = PointList([Point(x_via, y2+w+d), Point(x_via, y2+w*2+d), Point(-x_via, y2+w*2+d), Point(-x_via, y2+w+d)])
                     dbCreatePolygon(self, TM2, polyPoints4)
                     dbCreateRect(self, IND, Box(-w/2-grid, y2+w*2+d+grid, w/2+grid, y2+w+d-grid))
                     dbCreateLabel(self, Layer('TEXT', 'drawing'), Point(0, y2+w+w/2+d), 'L2_TM2', 'centerCenter', 'R0', Font.EURO_STYLE, w/6)
-                    
+
                     if cellName == 'inductor2' :
                         dbCreateLabel(self, Layer('TEXT', 'drawing'), Point(0, y2+w+w/2+d+w/3), 'l='+l, 'centerCenter', 'R0', Font.EURO_STYLE, w/6)
                         dbCreateLabel(self, Layer('TEXT', 'drawing'), Point(0, y2+w+w/2+d-w/3), 'r='+r, 'centerCenter', 'R0', Font.EURO_STYLE, w/6)
-                        
+
                     if cellName == 'inductor2_sc' :
                         dbCreateLabel(self, Layer('TEXT', 'drawing'), Point(0, y2+w+w/2+d-w/3), 'model='+model, 'centerCenter', 'R0', Font.EURO_STYLE, w/6)
-                        
+
                 else :
-                    polyPoints3 = PointList([Point(x_via+w, y2+w+d), Point(x_via+w, y2+w*2+d), Point(x_cross, y2+w*2+d), Point(x_cross-(w+s+2*grid), y2+w*3+s+d+2*grid), Point(-x_via-w, y2+w*3+s+d+2*grid), 
+                    polyPoints3 = PointList([Point(x_via+w, y2+w+d), Point(x_via+w, y2+w*2+d), Point(x_cross, y2+w*2+d), Point(x_cross-(w+s+2*grid), y2+w*3+s+d+2*grid), Point(-x_via-w, y2+w*3+s+d+2*grid),
                                              Point(-x_via-w, y2+w*2+s+d+2*grid), Point(-x_cross, y2+w*2+s+d+2*grid), Point(w+s+2*grid-x_cross, y2+w+d)])
                     dbCreatePolygon(self, TM1, polyPoints3)
-                    polyPoints3 = PointList([Point(-x_via, y2+w+d), Point(-x_via, y2+w*2+d), Point(-x_cross, y2+w*2+d), Point(w+s+2*grid-x_cross, y2+w*3+s+d+2*grid), Point(x_via, y2+w*3+s+d+2*grid), 
+                    polyPoints3 = PointList([Point(-x_via, y2+w+d), Point(-x_via, y2+w*2+d), Point(-x_cross, y2+w*2+d), Point(w+s+2*grid-x_cross, y2+w*3+s+d+2*grid), Point(x_via, y2+w*3+s+d+2*grid),
                                              Point(x_via, y2+w*2+s+d+2*grid), Point(x_cross+3*grid, y2+w*2+s+d+2*grid), Point(x_cross-(w+s-grid), y2+w+d)])
                     dbCreatePolygon(self, TM2, polyPoints3)
                     x1_via = x_via+0.5+(w-nr_vias*0.9-(nr_vias-1)*1.06-1)/2
@@ -291,15 +291,15 @@ def genLayout(self):
                             dbCreateRect(self, TV2, Box( x1_via, y1_via,       x1_via+0.9,  y1_via+0.9))
                             dbCreateRect(self, TV2, Box(-x1_via, y1_via+s+w, -(x1_via+0.9), y1_via+0.9+s+w))
                             x1_via = x1_via+1.96
-                            
+
                         x1_via = x_via+0.5+(w-nr_vias*0.9-(nr_vias-1)*1.06-1)/2
                         y1_via = y1_via+1.96
-                        
+
                 if pcIndexX != 0 :
-                    polyPoints3 = PointList([Point(x_via, y2), Point(x_via, y2+w), Point(x_cross+grid, y2+w), Point(x_cross-(w+s)+grid, y2+w*2+s), Point(-x_via, y2+w*2+s), 
+                    polyPoints3 = PointList([Point(x_via, y2), Point(x_via, y2+w), Point(x_cross+grid, y2+w), Point(x_cross-(w+s)+grid, y2+w*2+s), Point(-x_via, y2+w*2+s),
                                              Point(-x_via, y2+w+s), Point(-x_cross, y2+w+s), Point(-x_cross+w+s, y2)])
                     dbCreatePolygon(self, TM2, polyPoints3)
-                    polyPoints3 = PointList([Point(-x_via-w, y2), Point(-x_via-w, y2+w), Point(-x_cross-grid, y2+w), Point(-x_cross+w+s-grid, y2+w*2+s), Point(x_via+w+grid, y2+w*2+s), 
+                    polyPoints3 = PointList([Point(-x_via-w, y2), Point(-x_via-w, y2+w), Point(-x_cross-grid, y2+w), Point(-x_cross+w+s-grid, y2+w*2+s), Point(x_via+w+grid, y2+w*2+s),
                                              Point(x_via+w+grid, y2+w+s), Point(x_cross, y2+w+s), Point(x_cross-(w+s), y2)])
                     dbCreatePolygon(self, TM1, polyPoints3)
                     x1_via = x_via+grid+0.5+(w-nr_vias*0.9-(nr_vias-1)*1.06-1)/2
@@ -309,18 +309,18 @@ def genLayout(self):
                             dbCreateRect(self, TV2, Box(x1_via, y1_via, x1_via+0.9, y1_via+0.9))
                             dbCreateRect(self, TV2, Box(-x1_via+grid, y1_via-s-w, -(x1_via-grid+0.9), y1_via+0.9-s-w))
                             x1_via = x1_via+1.96
-                            
+
                         x1_via = x_via+grid+0.5+(w-nr_vias*0.9-(nr_vias-1)*1.06-1)/2
                         y1_via = y1_via+1.96
-                        
+
             y2 = y2-w-s
             x1 = x_via
             d = d+2*(s+w+grid)
-            lat_sm = GridFix(d/(2*var))*2       
+            lat_sm = GridFix(d/(2*var))*2
             lat_big = GridFix((d+2*w)/var)
             cateta_sm = (d-lat_sm)/2
             cateta_big = GridFix((d+2*w)/(var*sqrt(2)))
-            
+
         if type2 :
             if (nr_r == 2) or (nr_r == 1) :
                 x1 = (w+s)/2
@@ -331,7 +331,7 @@ def genLayout(self):
                 x1 = w+s
             else :
                 x1 = x1+w/2+s+w
-                
+
         pathPoints1 = PointList([Point(x1, -1), Point(x1, nr_r*w+(nr_r-1)*s+30)])
         pathPoints2 = PointList([Point(-x1, -1),Point( -x1, nr_r*w+(nr_r-1)*s+30)])
         if type2 and (nr_r == 1) :
@@ -344,22 +344,22 @@ def genLayout(self):
             dbCreatePath(self, TM1, pathPoints2, w);
             pcInst1 = dbCreateRect(self, TM1p, Box(x1-w/2, -1, x1+w/2, 1))
             pcInst2 = dbCreateRect(self, TM1p, Box(-x1-w/2, -1, -x1+w/2, 1))
-           
+
         pcPin = dbCreatePin(self, 'LB', pcInst1)
         dbCreateLabel(self, Layer('TEXT', 'drawing'), Point(x1, 0), 'LB', 'centerCenter', 'R0', Font.EURO_STYLE, w/2)
         pcPin = dbCreatePin(self, 'LA', pcInst2)
         dbCreateLabel(self, Layer('TEXT', 'drawing'), Point(-x1, 0), 'LA', 'centerCenter', 'R0', Font.EURO_STYLE, w/2)
-        
+
         dbCreateLabel(self, Layer('TEXT', 'drawing'), Point(0, y2+cateta_sm/2+lat_sm), cellName, 'centerCenter', 'R0', Font.EURO_STYLE, w)
-        
+
         y2 = 0
         d = d-2*s+2*30
-        lat_sm = GridFix(d/(2*var))*2 
+        lat_sm = GridFix(d/(2*var))*2
         lat_big = GridFix((d+2*w)/var)
         cateta_sm = (d-lat_sm)/2
         cateta_big = GridFix((d+2*w)/(var*sqrt(2)))
-        
-        polyPoints1 = PointList([Point(lat_sm/2, y2), Point(d/2, y2+cateta_sm), Point(d/2, y2+cateta_sm+lat_sm), Point(lat_sm/2, y2+d), Point(-lat_sm/2, y2+d), 
+
+        polyPoints1 = PointList([Point(lat_sm/2, y2), Point(d/2, y2+cateta_sm), Point(d/2, y2+cateta_sm+lat_sm), Point(lat_sm/2, y2+d), Point(-lat_sm/2, y2+d),
                                  Point(-d/2, y2+cateta_sm+lat_sm), Point(-d/2, y2+cateta_sm), Point(-lat_sm/2, y2)])
         dbCreatePolygon(self, PWellBlock, polyPoints1)
         dbCreatePolygon(self, NoActFiller, polyPoints1)
@@ -367,16 +367,16 @@ def genLayout(self):
         dbCreatePolygon(self, NoMet1Filler, polyPoints1)
         dbCreatePolygon(self, NoMet2Filler, polyPoints1)
         dbCreatePolygon(self, NoMet3Filler, polyPoints1)
-            
+
         dbCreatePolygon(self, NoTMet1Filler, polyPoints1)
         dbCreatePolygon(self, NoTMet2Filler, polyPoints1)
-        
+
         if blockqrc :
             dbCreatePolygon(self, NoRCX, polyPoints1)
-            
+
         if subE :
             dbCreatePolygon(self, substrateE, polyPoints1)
-            
+
         y2 = 2*nr_r*w+2*(nr_r-1)*s
         d = d1
-        
+
diff --git a/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/nmosHV_code.py b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/nmosHV_code.py
new file mode 100644
index 00000000..d8adedc1
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/nmosHV_code.py
@@ -0,0 +1,240 @@
+########################################################################
+#
+# Copyright 2023 IHP PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#    https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+########################################################################
+__version__ = "$Revision: #3 $"
+
+from cni.dlo import *
+from .thermal import *
+from .geometry import *
+from .utility_functions import *
+
+import math
+
+class nmosHV(DloGen):
+
+    @classmethod
+    def defineParamSpecs(cls, specs):
+        techparams  = specs.tech.getTechParams()
+
+        CDFVersion  = techparams['CDFVersion']
+        model       = 'sg13_hv_nmos'
+        defL        = techparams['nmosHV_defL']
+        defW        = techparams['nmosHV_defW']
+        defNG       = techparams['nmosHV_defNG']
+        minL        = techparams['nmosHV_minL']
+        minW        = techparams['nmosHV_minW']
+
+        specs('cdf_version', CDFVersion, 'CDF Version')
+        specs('Display', 'Selected', 'Display', ChoiceConstraint(['All', 'Selected']))
+        specs('model', model, 'Model name')
+
+        specs('w', defW, 'Width')
+        specs('ws', eng_string(Numeric(defW)/Numeric(defNG)), 'SingleWidth')
+        specs('l', defL, 'Length')
+        specs('Wmin', minW, 'Wmin')
+        specs('Lmin', minL, 'Lmin')
+        specs('ng', defNG, 'Number of Gates')
+
+        specs('m', '1', 'Multiplier')
+        specs('trise', '', 'Temp rise from ambient')
+
+    def setupParams(self, params):
+
+        self.w = Numeric(params['w'])*1e6
+        self.ng = int(params['ng'])
+        self.l = Numeric(params['l'])*1e6
+
+    def genLayout(self):
+        w = self.w
+        ng = self.ng
+        l = self.l
+
+        techparams = self.tech.getTechParams()
+        self.techparams = techparams
+        self.epsilon = techparams['epsilon1']
+
+        Cell = self.__class__.__name__
+        typ = 'N'
+        hv = True
+
+        # *************************************************************************
+        # *
+        # * Cell Properties
+        # *
+        # ************************************************************************
+        dbReplaceProp(self, 'ivCellType', 'graphic')
+        dbReplaceProp(self, 'viewSubType', 'maskLayoutParamCell')
+        dbReplaceProp(self, 'instNamePrefix', 'M')
+        dbReplaceProp(self, 'function', 'transistor')
+        dbReplaceProp(self, 'pcellVersion', '$Revision: 1.0 $')
+        dbReplaceProp(self, 'pin#', 5)
+
+        # *************************************************************************
+        # *
+        # * Layer Definitions
+        # *
+        # ************************************************************************
+
+        metall_layer = Layer('Metal1')
+        metall_layer_pin = Layer('Metal1', 'pin')
+        ndiff_layer = Layer('Activ')
+        poly_layer = Layer('GatPoly')
+        poly_layer_pin = Layer('GatPoly', 'pin')
+        locint_layer = Layer('Cont')
+        text_layer = Layer('TEXT', 'drawing')
+        tgo_layer = Layer('ThickGateOx')
+
+        # *************************************************************************
+        # *
+        # * Generic Design Rule Definitions
+        # *
+        # ************************************************************************
+        epsilon = techparams['epsilon1']
+        endcap = techparams['M1_c1']
+        cont_size = techparams['Cnt_a']
+        cont_dist = techparams['Cnt_b']
+        cont_Activ_overRec = techparams['Cnt_c']
+        cont_metall_over = techparams['M1_c']
+        gatpoly_Activ_over = techparams['Gat_c']
+        gatpoly_cont_dist = techparams['Cnt_f']
+        smallw_gatpoly_cont_dist = cont_Activ_overRec + techparams['Gat_d']
+        contActMin = 2 * cont_Activ_overRec + cont_size
+
+        thGateOxGat = techparams['TGO_c']
+        thGateOxAct = techparams['TGO_a']
+
+        dbReplaceProp(self, 'pin#', 5)
+
+        ng = fix(ng + epsilon)
+
+        w = w / ng
+        w = GridFix(w)
+        l = GridFix(l)
+
+        # *************************************************************************
+        # *
+        # * Main body of code
+        # *
+        # ************************************************************************
+
+        if endcap < cont_metall_over:
+            endcap = cont_metall_over
+        if w < contActMin - epsilon:  # adjust size of Gate to S/D contact region due to corner
+            gatpoly_cont_dist = smallw_gatpoly_cont_dist
+
+        if hv:
+            labelhv = 'HV'
+        else:
+            labelhv = ''
+
+        xdiff_beg = 0
+        ydiff_beg = 0
+        ydiff_end = w
+
+        xanz = fix((w - 2 * cont_Activ_overRec + cont_dist) / (cont_size + cont_dist) + epsilon)
+        w1 = xanz * (cont_size + cont_dist) - cont_dist + cont_Activ_overRec + cont_Activ_overRec
+        xoffset = (w - w1) / 2
+        xoffset = GridFix(xoffset)
+        diffoffset = 0
+        if w < contActMin:
+            xoffset = 0
+            diffoffset = (contActMin - w) / 2
+            diffoffset = Snap(diffoffset)
+
+        # get the number of contacts
+        lcon = w - 2 * cont_Activ_overRec
+        distc = cont_size + cont_dist
+        ncont = fix((w - 2 * cont_Activ_overRec + cont_dist) / (cont_size + cont_dist) + epsilon)
+        if zerop(ncont):
+            ncont = 1
+
+        diff_cont_offset = GridFix((w - 2 * cont_Activ_overRec - ncont * cont_size - (ncont - 1) * cont_dist) / 2)
+
+        # draw the cont row
+        xcont_beg = xdiff_beg + cont_Activ_overRec
+        ycont_beg = ydiff_beg + cont_Activ_overRec
+        ycont_cnt = ycont_beg + diffoffset + diff_cont_offset
+        xcont_end = xcont_beg + cont_size
+
+        # draw Metal rect
+        # calculate bot and top cont position
+        yMet1 = ycont_cnt - endcap
+        yMet2 = ycont_cnt + cont_size + (ncont - 1) * distc + endcap
+        # is metal1 overlapping Activ?
+        yMet1 = min(yMet1, ydiff_beg + diffoffset)
+        yMet2 = max(yMet2, ydiff_end + diffoffset)
+        dbCreateRect(self, metall_layer, Box(xcont_beg - cont_metall_over, yMet1, xcont_end + cont_metall_over, yMet2))
+
+        # draw contacts and Metall
+        contactArray(self, 0, locint_layer, xcont_beg, ydiff_beg, xcont_end, ydiff_end + diffoffset * 2, 0,
+                     cont_Activ_overRec, cont_size, cont_dist)
+
+        MkPin(self, 'S', 3, Box(xcont_beg - cont_metall_over, yMet1, xcont_end + cont_metall_over, yMet2),
+              metall_layer_pin)
+
+        # draw source diffusion
+        dbCreateRect(self, ndiff_layer, Box(xcont_beg - cont_Activ_overRec, ycont_beg - cont_Activ_overRec,
+                                            xcont_end + cont_Activ_overRec, ycont_beg + cont_size + cont_Activ_overRec))
+
+        for i in range(1, ng + 1):
+            # draw the poly line
+            xpoly_beg = xcont_end + gatpoly_cont_dist
+            ypoly_beg = ydiff_beg - gatpoly_Activ_over
+            xpoly_end = xpoly_beg + l
+            ypoly_end = ydiff_end + gatpoly_Activ_over
+            dbCreateRect(self, poly_layer, Box(xpoly_beg, ypoly_beg + diffoffset, xpoly_end, ypoly_end + diffoffset))
+
+            ihpAddThermalMosLayer(self, Box(xpoly_beg, ypoly_beg + diffoffset, xpoly_end, ypoly_end + diffoffset), True,
+                                  Cell)
+
+            if i == 1:
+                dbCreateLabel(self, text_layer,
+                              Point((xpoly_beg + xpoly_end) / 2, (ypoly_beg + ypoly_end) / 2 + diffoffset), 'nmos'+labelhv,
+                              'centerCenter', 'R90', Font.EURO_STYLE, 0.1)
+
+            if onep(i):
+                MkPin(self, 'G', 2, Box(xpoly_beg, ypoly_beg + diffoffset, xpoly_end, ypoly_end + diffoffset),
+                      poly_layer_pin)
+
+            # draw the second cont row
+            xcont_beg = xpoly_end + gatpoly_cont_dist
+            ycont_beg = ydiff_beg + cont_Activ_overRec
+            ycont_cnt = ycont_beg + diffoffset + diff_cont_offset
+            xcont_end = xcont_beg + cont_size
+            dbCreateRect(self, metall_layer,
+                         Box(xcont_beg - cont_metall_over, yMet1, xcont_end + cont_metall_over, yMet2))
+
+            contactArray(self, 0, locint_layer, xcont_beg, ydiff_beg, xcont_end, ydiff_end + diffoffset * 2, 0,
+                         cont_Activ_overRec, cont_size, cont_dist)
+
+            if onep(i):
+                MkPin(self, 'D', 1, Box(xcont_beg - cont_metall_over, yMet1, xcont_end + cont_metall_over, yMet2),
+                      metall_layer_pin)
+
+            # draw drain diffusion
+            dbCreateRect(self, ndiff_layer, Box(xcont_beg - cont_Activ_overRec, ycont_beg - cont_Activ_overRec,
+                                                xcont_end + cont_Activ_overRec,
+                                                ycont_beg + cont_size + cont_Activ_overRec))
+
+        # now finish drawing the diffusion
+        xdiff_end = xcont_end + cont_Activ_overRec
+        dbCreateRect(self, ndiff_layer, Box(xdiff_beg, ydiff_beg + diffoffset, xdiff_end, ydiff_end + diffoffset))
+
+        if hv:
+            dbCreateRect(self, tgo_layer,
+                         Box(xdiff_beg - thGateOxAct, ydiff_beg - gatpoly_Activ_over - thGateOxGat,
+                             xdiff_end + thGateOxAct, ydiff_end + gatpoly_Activ_over + thGateOxGat))
\ No newline at end of file
diff --git a/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/nmos_code.py b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/nmos_code.py
index 04ed2e23..7dedb1e9 100644
--- a/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/nmos_code.py
+++ b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/nmos_code.py
@@ -1,13 +1,13 @@
 ########################################################################
 #
-# Copyright 2023 IHP PDK Authors
-# 
+# Copyright 2024 IHP PDK Authors
+#
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
 # You may obtain a copy of the License at
-# 
+#
 #    https://www.apache.org/licenses/LICENSE-2.0
-# 
+#
 # Unless required by applicable law or agreed to in writing, software
 # distributed under the License is distributed on an "AS IS" BASIS,
 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -30,7 +30,7 @@ class nmos(DloGen):
     @classmethod
     def defineParamSpecs(cls, specs):
         techparams = specs.tech.getTechParams()
-        
+
         CDFVersion = techparams['CDFVersion']
         model      = 'sg13_lv_nmos'
         defL       = techparams['nmos_defL']
@@ -38,18 +38,18 @@ def defineParamSpecs(cls, specs):
         defNG      = techparams['nmos_defNG']
         minL       = techparams['nmos_minL']
         minW       = techparams['nmos_minW']
-        
+
         specs('cdf_version', CDFVersion, 'CDF Version')
         specs('Display', 'Selected', 'Display', ChoiceConstraint(['All', 'Selected']))
         specs('model', model, 'Model name')
-        
+
         specs('w' ,   defW, 'Width')
         specs('ws',   eng_string(Numeric(defW)/Numeric(defNG)), 'SingleWidth')
         specs('l' ,   defL, 'Length')
         specs('Wmin', minW, 'Wmin')
         specs('Lmin', minL, 'Lmin')
         specs('ng',   defNG, 'Number of Gates')
-        
+
         specs('m', '1', 'Multiplier')
         specs('trise', '', 'Temp rise from ambient')
 
@@ -67,9 +67,9 @@ def genLayout(self):
         techparams      = self.tech.getTechParams()
         self.techparams = techparams
         self.epsilon    = techparams['epsilon1']
-        
+
         Cell = self.__class__.__name__
-        
+
         #*************************************************************************
         #*
         #* Cell Properties
@@ -81,7 +81,7 @@ def genLayout(self):
         dbReplaceProp(self, 'function', 'transistor')
         dbReplaceProp(self, 'pcellVersion', '$Revision: 1.0 $')
         dbReplaceProp(self, 'pin#', 5)
-        
+
         #*************************************************************************
         #*
         #* Layer Definitions
@@ -111,30 +111,30 @@ def genLayout(self):
         gatpoly_cont_dist = techparams['Cnt_f']
         smallw_gatpoly_cont_dist = cont_Activ_overRec+techparams['Gat_d']
         contActMin = 2*cont_Activ_overRec+cont_size
-        
+
         dbReplaceProp(self, 'pin#', 5)
-        
+
         ng = fix(ng+epsilon)
-        
+
         w = w/ng
         w = GridFix(w)
         l = GridFix(l)
-        
+
         #*************************************************************************
         #*
         #* Main body of code
         #*
         #************************************************************************
-        
+
         if endcap < cont_metall_over :
             endcap = cont_metall_over
         if w < contActMin-epsilon :   #  adjust size of Gate to S/D contact region due to corner
             gatpoly_cont_dist = smallw_gatpoly_cont_dist
-        
+
         xdiff_beg = 0
         ydiff_beg = 0
         ydiff_end = w
-            
+
         xanz = fix((w-2*cont_Activ_overRec+cont_dist)/(cont_size+cont_dist)+epsilon)
         w1 = xanz*(cont_size+cont_dist)-cont_dist+cont_Activ_overRec+cont_Activ_overRec
         xoffset = (w-w1)/2
@@ -144,22 +144,22 @@ def genLayout(self):
             xoffset = 0
             diffoffset = (contActMin-w)/2
             diffoffset = Snap(diffoffset)
-            
+
         # get the number of contacts
         lcon = w-2*cont_Activ_overRec
         distc = cont_size+cont_dist
         ncont = fix((w-2*cont_Activ_overRec+cont_dist)/(cont_size+cont_dist)+epsilon)
         if zerop(ncont) :
             ncont = 1
-            
+
         diff_cont_offset = GridFix((w-2*cont_Activ_overRec-ncont*cont_size-(ncont-1)*cont_dist)/2)
-        
+
         # draw the cont row
         xcont_beg = xdiff_beg+cont_Activ_overRec
         ycont_beg = ydiff_beg+cont_Activ_overRec
         ycont_cnt = ycont_beg+diffoffset+diff_cont_offset
         xcont_end = xcont_beg+cont_size
-        
+
         # draw Metal rect
         # calculate bot and top cont position
         yMet1 = ycont_cnt-endcap
@@ -168,16 +168,16 @@ def genLayout(self):
         yMet1 = min(yMet1, ydiff_beg+diffoffset)
         yMet2 = max(yMet2, ydiff_end+diffoffset)
         dbCreateRect(self, metall_layer, Box(xcont_beg-cont_metall_over, yMet1, xcont_end+cont_metall_over, yMet2))
-        
+
         # draw contacts and Metall
         contactArray(self, 0, locint_layer, xcont_beg, ydiff_beg, xcont_end, ydiff_end+diffoffset*2, 0, cont_Activ_overRec, cont_size, cont_dist)
-        
+
         MkPin(self, 'S', 3, Box(xcont_beg-cont_metall_over, yMet1, xcont_end+cont_metall_over, yMet2), metall_layer_pin)
-        
+
         # draw source diffusion
         dbCreateRect(self, ndiff_layer, Box(xcont_beg-cont_Activ_overRec, ycont_beg-cont_Activ_overRec,
                                             xcont_end+cont_Activ_overRec, ycont_beg+cont_size+cont_Activ_overRec))
-            
+
         for i in range(1, ng+1) :
             # draw the poly line
             xpoly_beg = xcont_end+gatpoly_cont_dist
@@ -185,32 +185,32 @@ def genLayout(self):
             xpoly_end = xpoly_beg+l
             ypoly_end = ydiff_end+gatpoly_Activ_over
             dbCreateRect(self, poly_layer, Box(xpoly_beg, ypoly_beg+diffoffset, xpoly_end, ypoly_end+diffoffset))
-            
+
             ihpAddThermalMosLayer(self, Box(xpoly_beg, ypoly_beg+diffoffset, xpoly_end, ypoly_end+diffoffset), True, Cell)
-                
+
             if i == 1 :
                 dbCreateLabel(self, text_layer, Point((xpoly_beg+xpoly_end)/2, (ypoly_beg+ypoly_end)/2+diffoffset), 'nmos', 'centerCenter', 'R90', Font.EURO_STYLE, 0.1)
-            
+
             if onep(i) :
                 MkPin(self, 'G', 2, Box(xpoly_beg, ypoly_beg+diffoffset, xpoly_end, ypoly_end+diffoffset), poly_layer_pin)
-                
+
             # draw the second cont row
             xcont_beg = xpoly_end+gatpoly_cont_dist
             ycont_beg = ydiff_beg+cont_Activ_overRec
             ycont_cnt = ycont_beg+diffoffset+diff_cont_offset
             xcont_end = xcont_beg+cont_size
             dbCreateRect(self, metall_layer, Box(xcont_beg-cont_metall_over, yMet1, xcont_end+cont_metall_over, yMet2))
-            
+
             contactArray(self, 0, locint_layer, xcont_beg, ydiff_beg, xcont_end, ydiff_end+diffoffset*2, 0, cont_Activ_overRec, cont_size, cont_dist)
-            
+
             if onep(i) :
                 MkPin(self, 'D', 1, Box(xcont_beg-cont_metall_over, yMet1, xcont_end+cont_metall_over, yMet2), metall_layer_pin)
-            
+
             # draw drain diffusion
             dbCreateRect(self, ndiff_layer, Box(xcont_beg-cont_Activ_overRec, ycont_beg-cont_Activ_overRec,
                                                 xcont_end+cont_Activ_overRec, ycont_beg+cont_size+cont_Activ_overRec))
-            
+
         # now finish drawing the diffusion
         xdiff_end = xcont_end+cont_Activ_overRec
         dbCreateRect(self, ndiff_layer, Box(xdiff_beg, ydiff_beg+diffoffset, xdiff_end, ydiff_end+diffoffset))
-            
+
diff --git a/ihp-sg13g2/libs.tech/pycell/npn13G2L_code.py b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/npn13G2L_code.py
similarity index 82%
rename from ihp-sg13g2/libs.tech/pycell/npn13G2L_code.py
rename to ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/npn13G2L_code.py
index 1b9af42c..65dc3d16 100644
--- a/ihp-sg13g2/libs.tech/pycell/npn13G2L_code.py
+++ b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/npn13G2L_code.py
@@ -1,13 +1,13 @@
 ########################################################################
 #
-# Copyright 2023 IHP PDK Authors
-# 
+# Copyright 2024 IHP PDK Authors
+#
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
 # You may obtain a copy of the License at
-# 
+#
 #    https://www.apache.org/licenses/LICENSE-2.0
-# 
+#
 # Unless required by applicable law or agreed to in writing, software
 # distributed under the License is distributed on an "AS IS" BASIS,
 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -18,39 +18,38 @@
 __version__ = '$Revision: #3 $'
 
 from cni.dlo import *
-from geometry import *
-from thermal import *
-from utility_functions import *
+from .geometry import *
+from .thermal import *
+from .utility_functions import *
 
 import math
 
 class npn13G2L(DloGen):
 
     @classmethod
-    def defineParamSpecs(cls, specs):   
+    def defineParamSpecs(cls, specs):
         techparams = specs.tech.getTechParams()
-        
+
         CDFVersion = techparams['CDFVersion']
         model      = techparams['npn13G2L_model']
-        
+
         specs('cdf_version', CDFVersion, 'CDF Version')
         specs('Display', 'Selected', 'Display', ChoiceConstraint(['All', 'Selected']))
         specs('model', model, 'Model name')
-        
-        specs('Nx', 1, 'x-Multiplier', RangeConstraint(1, 4))
-        specs('Ny', 1, 'y-Multiplier', ChoiceConstraint([1]))
+
+        specs('Nx', 2, 'x-Multiplier', RangeConstraint(1, 4))
         specs('le', '1.0u', "Emitter Length")
         specs('we', '0.07u', "Emitter Width")
-        
+
         specs('Icmax', '2.6m', 'Ic,max@Uce=2V (50%@0.5V)')
         specs('Iarea', '2.6m', 'Ic,max/squm@Uce=2V')
         specs('area', '1', 'Area Factor')
         specs('bn', 'sub!', 'Bulk node connection')
-        specs('Vbe', '', 'Base-emitter voltag')
+        specs('Vbe', '', 'Base-emitter voltage')
         specs('Vce', '', 'Collector-emitter voltage')
         specs('m', '1', 'Multiplier')
         specs('trise', '', 'Temp rise from ambient')
-        
+
     def setupParams(self, params):
         # process parameter values entered by user
         self.params = params
@@ -82,36 +81,37 @@ def genLayout(self):
         Bas_Metal1_width = 0.16
         Emi_Metal1_enc_vert = 0.2
         Emi_Metal1_enc_hori = 0.095
-        
+
         Cell = self.__class__.__name__
-        
+
         le = Numeric(le)*1e6
         Nx = Numeric(Nx)
         we = Numeric(we)*1e6
-        
+
         pcPurpose = 'drawing'
-        
+
         id = dbCreateRect(self,Layer('EmWind', 'drawing'), Box(emWindOrigin_x, emWindOrigin_y, emWindOrigin_x + we, emWindOrigin_y + le))
-        
-        ihpAddThermalBjtLayer(self, Box((emWindOrigin_x - 0.05), (emWindOrigin_y - 0.05), (emWindOrigin_x + we + 0.05), (emWindOrigin_y + le + 0.05)), True, Cell)
-        
         groupId = list()
         groupId.append(id)
-        
+
+        id = ihpAddThermalBjtLayer(self, Box((emWindOrigin_x - 0.05), (emWindOrigin_y - 0.05), (emWindOrigin_x + we + 0.05), (emWindOrigin_y + le + 0.05)), True, Cell)
+        groupId.append(id)
+
+        masks = Grouping()
+
         outer  = dbCreateRect(self, Layer('Activ', 'drawing'), Box(emWindOrigin_x - Activ_enc_hori, emWindOrigin_y - Activ_enc_vert, emWindOrigin_x + we + Activ_enc_hori, emWindOrigin_y + le + Activ_enc_vert))
         inner  = dbCreateRect(self, Layer('Activ', 'mask'),    Box(emWindOrigin_x - 0.705, emWindOrigin_y - Activ_enc_vert, emWindOrigin_x - Emi_Metal1_enc_hori, emWindOrigin_y + le + Activ_enc_vert))
+        masks.add(inner)
         inner1 = dbCreateRect(self, Layer('Activ', 'mask'),    Box(emWindOrigin_x + we + 0.705, emWindOrigin_y - Activ_enc_vert, emWindOrigin_x +we + Emi_Metal1_enc_hori, emWindOrigin_y + le + Activ_enc_vert))
-        
-        id = dbLayerXor(Layer('Activ', 'drawing'), outer, inner)
-        id = dbLayerXor(Layer('Activ', 'drawing'), id, inner1)
-        
+        masks.add(inner1)
+
+        id = dbLayerXor(Layer('Activ', 'drawing'), outer, masks)
         for item in id :
             groupId.append(item)
-            
         dbDeleteObject(outer)
         groupId.append(inner)
         groupId.append(inner1)
-        
+
         # Draw contacts & Via
         id = dbCreateRect(self, Layer('Via1', 'drawing'), Box(3.805, 3, 3.995, 3.2+le))
         groupId.append(id)
@@ -121,21 +121,21 @@ def genLayout(self):
         groupId.append(id)
         id = dbCreateRect(self, Layer('Cont', 'drawing'), Box(4.96, 2.95, 5.12, 3.25+le))
         groupId.append(id)
-        
+
         cont_cnt = fix((le+0.21)/(0.16+0.18))
-        
+
         id = dbCreateRect(self, Layer('Cont', 'drawing'), Box(3.385, 2.89, 3.545, 3.05))
         groupId.append(id)
         for cnt in range(cont_cnt) :
             id = dbCopyShape(id, Point(0, 0.34), 'R0')
             groupId.append(id)
-            
+
         id = dbCreateRect(self, Layer('Cont', 'drawing'), Box(4.255, 2.89, 4.415, 3.05))
         groupId.append(id)
         for cnt in range(cont_cnt) :
             id = dbCopyShape(id, Point(0, 0.34), 'R0')
             groupId.append(id)
-            
+
         # Metals
         # Metal Path upwards
         # Collector
@@ -144,41 +144,45 @@ def genLayout(self):
         id = dbCreateRect(self, Layer('Metal1', 'drawing'), Box(emWindOrigin_x + we + Col_Metal1_distance, 2.82, emWindOrigin_x + we + Col_Metal1_distance + Col_Metal1_width, 4.1 + le))
         groupId.append(id)
         id = dbCreateRect(self, Layer('Metal1', 'drawing'), Box(emWindOrigin_x - Col_Metal1_distance - Col_Metal1_width, 4.1 + le, emWindOrigin_x + we + Col_Metal1_distance + Col_Metal1_width, 4.1 + le + 0.65))
+        id.col = True
         groupId.append(id)
-        
+
         # Basis
         id = dbCreateRect(self, Layer('Metal1', 'drawing'), Box(emWindOrigin_x - Bas_Metal1_distance, 2.1, emWindOrigin_x - Bas_Metal1_distance - Bas_Metal1_width, 3.38+le))
         groupId.append(id)
         id = dbCreateRect(self, Layer('Metal1', 'drawing'), Box(emWindOrigin_x + we + Bas_Metal1_distance, 2.1, emWindOrigin_x + we + Bas_Metal1_distance + Bas_Metal1_width, 3.38+le))
         groupId.append(id)
-        id = dbCreateRect(self, Layer('Metal2', 'drawing'), Box(emWindOrigin_x - Bas_Metal1_distance - Bas_Metal1_width, 1.45, emWindOrigin_x + we + Bas_Metal1_distance + Bas_Metal1_width, 2.1))
+        id = dbCreateRect(self, Layer('Metal1', 'drawing'), Box(emWindOrigin_x - Bas_Metal1_distance - Bas_Metal1_width, 1.45, emWindOrigin_x + we + Bas_Metal1_distance + Bas_Metal1_width, 2.1))
+        id.base = True
         groupId.append(id)
-        
+
         # Emitter
         id = dbCreateRect(self, Layer('Metal1', 'drawing'), Box(emWindOrigin_x - Emi_Metal1_enc_hori, emWindOrigin_y - Emi_Metal1_enc_vert, emWindOrigin_x + we + Emi_Metal1_enc_hori, emWindOrigin_y + le + Emi_Metal1_enc_vert))
         groupId.append(id)
         id = dbCreateRect(self, Layer('Metal2', 'drawing'), Box(emWindOrigin_x - Col_Metal1_distance  - Col_Metal1_width, 2.9, emWindOrigin_x + Col_Metal1_distance + Col_Metal1_width + we, 3.3+le))
+        id.emi = True
         groupId.append(id)
-        
+
         # Draw Guardring
         pcLayer = 'TRANS'
         dbCreateRect(self, Layer('TRANS', 'drawing'), Box(0.9, 0.9, 6.9+((Nx-1)*2.8), 5.3+le))
-        
+
         pcLayer = 'pSD'
         outer = dbCreateRect(self, Layer('pSD', 'drawing'), Box(0, 0, 7.8+((Nx-1)*2.8), 6.2+le))
+        inner = dbCreateRect(self, Layer('pSD', 'drawing'), Box(0.9, 0.9, 7.8-0.9+((Nx-1)*2.8), 6.2-0.9+le))
         dbLayerXor(pcLayer, outer, inner)
         dbDeleteObject(outer)
         dbDeleteObject(inner)
-        
+
         pcLayer = 'Activ'
         outer = dbCreateRect(self, Layer(pcLayer, pcPurpose), Box(0.2, 0.2, 7.6+((Nx-1)*2.8), 6.0+le))
         inner = dbCreateRect(self, Layer(pcLayer, pcPurpose), Box(0.7, 0.7, (7.6-0.5)+((Nx-1)*2.8), 6.0-0.5+le))
         dbLayerXor(pcLayer, outer, inner)
         dbDeleteObject(outer)
         dbDeleteObject(inner)
-        
+
         pcLayer = 'TEXT'
-        pcLabelText = 'Ae={Ae}um2'.format(Ae=Nx*1*le*we);
+        pcLabelText = 'Ae={0:d}*{1:d}*{2:.2f}*{3:.2f}'.format(int(Nx), 1, le, we)
         pcLabelHeight = 0.35
         pcInst = dbCreateLabel(self, Layer('TEXT', 'drawing'), Point(1.5, 1.0), pcLabelText, 'lowerLeft', 'R90', Font.EURO_STYLE, pcLabelHeight)
         pcInst.setDrafting(True)
@@ -186,15 +190,25 @@ def genLayout(self):
         pcLabelHeight = 0.35
         pcInst = dbCreateLabel(self, Layer('TEXT', 'drawing'), Point(1.75, 1.0), pcLabelText, 'lowerLeft', 'R0', Font.EURO_STYLE, pcLabelHeight)
         pcInst.setDrafting(True)
-        
-        if Nx > 1 :
+
+        if self.Nx > 1 :
             id = dbCreateRect(self, Layer('Metal1', 'drawing'), Box(4.415, 1.45, 6.185, 2.1))
-            for cnt in range(1, Nx) :
+            id.base = True
+            for cnt in range(1, self.Nx) :
                 groupId = ihpCopyFig(groupId, Point(2.8, 0), 'R0')
-                if cnt != Nx-1 :
+                if cnt != self.Nx-1 :
                     id = dbCopyShape(id, Point(2.8, 0), 'R0')
-                    
-        MkPin(self, 'C', 1, Box((emWindOrigin_x-Col_Metal1_distance-Col_Metal1_width), (4.1+le), (emWindOrigin_x+we+Col_Metal1_distance+Col_Metal1_width), (4.1+le+0.65)), 'Metal1')
-        MkPin(self, 'B', 2, Box((emWindOrigin_x-Bas_Metal1_distance-Bas_Metal1_width), 1.45, (emWindOrigin_x+we+Bas_Metal1_distance+Bas_Metal1_width), 2.1), 'Metal1')
-        MkPin(self, 'E', 3, Box((emWindOrigin_x-Col_Metal1_distance-Col_Metal1_width), 2.9, (emWindOrigin_x+Col_Metal1_distance+Col_Metal1_width+we), (3.3+le)), 'Metal2')
-        
+
+
+        groupCol = Grouping();
+        [groupCol.add(id) for id in self.getShapes() if id.col]
+
+        groupBase = Grouping();
+        [groupBase.add(id) for id in self.getShapes() if id.base]
+
+        groupEmi = Grouping();
+        [groupEmi.add(id) for id in self.getShapes() if id.emi]
+
+        MkPin(self, 'C', 1, groupCol.getBBox(), 'Metal1')
+        MkPin(self, 'B', 2, groupBase.getBBox(), 'Metal1')
+        MkPin(self, 'E', 3, groupEmi.getBBox(), 'Metal2')
diff --git a/ihp-sg13g2/libs.tech/pycell/npn13G2V_code.py b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/npn13G2V_code.py
similarity index 83%
rename from ihp-sg13g2/libs.tech/pycell/npn13G2V_code.py
rename to ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/npn13G2V_code.py
index 21ec6fce..fbe87562 100644
--- a/ihp-sg13g2/libs.tech/pycell/npn13G2V_code.py
+++ b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/npn13G2V_code.py
@@ -1,13 +1,13 @@
 ########################################################################
 #
-# Copyright 2023 IHP PDK Authors
-# 
+# Copyright 2024 IHP PDK Authors
+#
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
 # You may obtain a copy of the License at
-# 
+#
 #    https://www.apache.org/licenses/LICENSE-2.0
-# 
+#
 # Unless required by applicable law or agreed to in writing, software
 # distributed under the License is distributed on an "AS IS" BASIS,
 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -18,9 +18,9 @@
 __version__ = "$Revision: #3 $"
 
 from cni.dlo import *
-from geometry import *
-from thermal import *
-from utility_functions import *
+from .geometry import *
+from .thermal import *
+from .utility_functions import *
 
 import math
 
@@ -29,24 +29,23 @@ class npn13G2V(DloGen):
     @classmethod
     def defineParamSpecs(cls, specs):
         techparams = specs.tech.getTechParams()
-        
+
         CDFVersion = techparams['CDFVersion']
         model      = techparams['npn13G2V_model']
-        
+
         specs('cdf_version', CDFVersion, 'CDF Version')
         specs('Display', 'Selected', 'Display', ChoiceConstraint(['All', 'Selected']))
         specs('model', model, 'Model name')
-        
-        specs('Nx', 1, 'x-Multiplier', RangeConstraint(1, 8))
-        specs('Ny', 1, 'y-Multiplier', ChoiceConstraint([1]))
+
+        specs('Nx', 2, 'x-Multiplier', RangeConstraint(1, 8))
         specs('le', '1.0u', "Emitter Length")
         specs('we', '0.12u', "Emitter Width")
-        
+
         specs('Icmax', '0.41m', 'Ic,max@Uce=2V (50%@0.5V)')
         specs('Iarea', '0.41m', 'Ic,max/squm@Uce=2V')
         specs('area', '1', 'Area Factor')
         specs('bn', 'sub!', 'Bulk node connection')
-        specs('Vbe', '', 'Base-emitter voltag')
+        specs('Vbe', '', 'Base-emitter voltage')
         specs('Vce', '', 'Collector-emitter voltage')
         specs('m', '1', 'Multiplier')
         specs('trise', '', 'Temp rise from ambient')
@@ -73,7 +72,7 @@ def genLayout(self):
         Bas_Metal1_width = 0.17
         Emi_Metal1_enc_vert = 0.28
         Emi_Metal1_enc_hori = 0.07
-        
+
         Cell = self.__class__.__name__
 
         techparams = self.tech.getTechParams()
@@ -91,7 +90,7 @@ def genLayout(self):
         dbReplaceProp(self, 'function', 'transistor')
         dbReplaceProp(self, 'pcellVersion', '$Revision: 1.0 $')
         dbReplaceProp(self, 'pin#', 4)
-        
+
         #*************************************************************************
         #
         # Pcell layers Definitions
@@ -107,7 +106,7 @@ def genLayout(self):
         l_trans   = Layer('TRANS', 'drawing')
         l_pSD     = Layer('pSD', 'drawing')
         l_text    = Layer('TEXT', 'drawing')
-        
+
         #*************************************************************************
         #
         # Generic Design Rule Definitions
@@ -116,7 +115,7 @@ def genLayout(self):
         Via1Width = techparams['V1_a']
         Via1Space = techparams['V1_b']
         m1EncVia1 = techparams['V1_c']
-        
+
         #*************************************************************************
         #
         # Main body of code
@@ -125,27 +124,28 @@ def genLayout(self):
         le = Numeric(le)*1e6
         Nx = Numeric(Nx)
         we = Numeric(we)*1e6
-        
+
         id = dbCreateRect(self, l_EmWiHV, Box(emWindOrigin_x, emWindOrigin_y, emWindOrigin_x + we, emWindOrigin_y + le))
-        
-        ihpAddThermalBjtLayer(self, Box(emWindOrigin_x - 0.05, emWindOrigin_y - 0.05, emWindOrigin_x + we + 0.05, emWindOrigin_y + le + 0.05), True, Cell)
-        
+
         groupId = list()
         groupId.append(id)
-        
+
+        id =  ihpAddThermalBjtLayer(self, Box(emWindOrigin_x - 0.05, emWindOrigin_y - 0.05, emWindOrigin_x + we + 0.05, emWindOrigin_y + le + 0.05), True, Cell)
+        groupId.append(id)
+
         outer = dbCreateRect(self, l_act, Box(emWindOrigin_x - Activ_enc_hori, emWindOrigin_y - Activ_enc_vert, emWindOrigin_x + we + Activ_enc_hori, emWindOrigin_y + le + Activ_enc_vert))
         inner = dbCreateRect(self, l_actMask, Box(emWindOrigin_x - 0.705, emWindOrigin_y - Activ_enc_vert, emWindOrigin_x - Emi_Metal1_enc_hori, emWindOrigin_y + le + Activ_enc_vert))
         inner1 = dbCreateRect(self, l_actMask, Box(emWindOrigin_x + we + 0.705, emWindOrigin_y - Activ_enc_vert, emWindOrigin_x +we + Emi_Metal1_enc_hori, emWindOrigin_y + le + Activ_enc_vert))
-         
-        id = dbLayerXorList(l_act, [outer, inner, inner1])
-        
+
+        id = dbLayerXorList(l_act, [outer], [inner, inner1])
+
         for item in id :
             groupId.append(item)
-            
+
         dbDeleteObject(outer)
         groupId.append(inner)
         groupId.append(inner1)
-        
+
         # Metals
         # Metal Path upwards
         # Collector
@@ -154,102 +154,113 @@ def genLayout(self):
         id = dbCreateRect(self, l_met1, Box(emWindOrigin_x+we+Col_Metal1_distance, 2.82, emWindOrigin_x+we+Col_Metal1_distance+Col_Metal1_width, 4.1+le))
         groupId.append(id)
         id = dbCreateRect(self, l_met1, Box(emWindOrigin_x - Col_Metal1_distance - Col_Metal1_width, 4.1 + le, emWindOrigin_x + we + Col_Metal1_distance + Col_Metal1_width, 4.1 + le + 0.65))
+        id.col = True
         groupId.append(id)
-        
-        # Basis  
+
+        # Basis
         id = dbCreateRect(self, l_met1, Box(emWindOrigin_x-Bas_Metal1_distance, 2.1, emWindOrigin_x-Bas_Metal1_distance-Bas_Metal1_width, 3.38+le))
         groupId.append(id)
         id = dbCreateRect(self, l_met1, Box(emWindOrigin_x+we+Bas_Metal1_distance, 2.1, emWindOrigin_x+we+Bas_Metal1_distance+Bas_Metal1_width, 3.38+le))
         groupId.append(id)
         id = dbCreateRect(self, l_met1, Box(emWindOrigin_x-Bas_Metal1_distance-Bas_Metal1_width, 1.45, emWindOrigin_x+we+Bas_Metal1_distance+Bas_Metal1_width, 2.1))
+        id.base = True
         groupId.append(id)
-        
+
         # Emitter
         emMet1 = dbCreateRect(self, l_met1, Box(emWindOrigin_x - Emi_Metal1_enc_hori, emWindOrigin_y - Emi_Metal1_enc_vert, emWindOrigin_x + we + Emi_Metal1_enc_hori, emWindOrigin_y + le + Emi_Metal1_enc_vert))
         groupId.append(emMet1)
         id = dbCreateRect(self, l_met2, Box(emWindOrigin_x-Col_Metal1_distance-Col_Metal1_width, 2.82, emWindOrigin_x+Col_Metal1_distance+Col_Metal1_width+we, 3.38+le))
+        id.emi = True
         groupId.append(id)
-        
+
         #; Draw contacts & Via
         via_cnt = int((le+0.46)/(0.19+0.22))
         id = dbCreateRect(self, l_via1, Box(3.775, 2.87, 3.965, 3.06))
-        
+
         bbx= emMet1.bbox
         # 0.5 is Y offset on bottom
         viaColumn = via_cnt*Via1Width+(via_cnt-1)*Via1Space+(Via1Width+Via1Space)+0.05+m1EncVia1
         if bbx.getHeight() < viaColumn :
             via_cnt -= 1
-            
+
         groupId.append(id)
-        
+
         for cnt in range(via_cnt) :
             id = dbCopyShape(id, Point(0, 0.41), 'R0')
             groupId.append(id)
-            
+
         id = dbCreateRect(self, l_cont, Box(3.79, 3.04, 3.95, 3.16+le))
         groupId.append(id)
-        
-        cont_cnt = int((le+0.21)/(0.16+0.18))
-        
+
+        cont_cnt = fix((le+0.21)/(0.16+0.18))
+
         id = dbCreateRect(self, l_cont, Box(2.8, 2.89, 2.96, 3.05))
         groupId.append(id)
-        
+
         for cnt in range(cont_cnt) :
             id = dbCopyShape(id, Point(0, 0.34), 'R0')
             groupId.append(id)
-            
+
         id = dbCreateRect(self, l_cont, Box(3.35, 2.89, 3.51, 3.05))
         groupId.append(id)
         for cnt in range(cont_cnt) :
             id = dbCopyShape(id, Point(0, 0.34), 'R0')
             groupId.append(id)
-            
+
         id = dbCreateRect(self, l_cont, Box(4.23, 2.89, 4.39, 3.05))
         groupId.append(id)
-        for cnt in range(1, cont_cnt) :
+        for cnt in range(cont_cnt) :
             id = dbCopyShape(id, Point(0, 0.34), 'R0')
             groupId.append(id)
-            
+
         id = dbCreateRect(self, l_cont, Box(4.78, 2.89, 4.94, 3.05))
         groupId.append(id)
         for cnt in range(cont_cnt) :
             id = dbCopyShape(id, Point(0, 0.34), 'R0')
             groupId.append(id)
-            
+
         # Draw Guardring
-        
+
         dbCreateRect(self, l_trans, Box(0.9, 0.9, 6.84+((Nx-1)*2.34), 5.3+le))
         outer = dbCreateRect(self, l_pSD, Box(0, 0, 7.74+((Nx-1)*2.34), 6.2+le))
         inner = dbCreateRect(self, l_pSD, Box(0.9, 0.9, (7.74-0.9)+((Nx-1)*2.34), 6.2-0.9+le))
         dbLayerXor(l_pSD, outer, inner)
         dbDeleteObject(outer)
         dbDeleteObject(inner)
-        
+
         outer = dbCreateRect(self, l_act, Box(0.2, 0.2, 7.54+((Nx-1)*2.34), 6.0+le))
         inner = dbCreateRect(self, l_act, Box(0.7, 0.7, (7.54-0.5)+((Nx-1)*2.34), 6.0-0.5+le))
         dbLayerXor(l_act, outer, inner)
         dbDeleteObject(outer)
         dbDeleteObject(inner)
-        
-        pcLabelText = 'Ae={Ae:.4f}um2'.format(Ae=Nx*le*we);
+
+        pcLabelText = 'Ae={0:d}*{1:.2f}*{2:.2f}'.format(int(Nx), le, we)
         pcLabelHeight = 0.35
         pcInst = dbCreateLabel(self, l_text, Point(1.5, 1.0), pcLabelText, 'lowerLeft', 'R90', Font.EURO_STYLE, pcLabelHeight)
         pcInst.setDrafting(True)
-        
+
         pcLabelText = Cell
         pcLabelHeight = 0.35
         pcInst = dbCreateLabel(self, l_text, Point(1.75, 1.0), pcLabelText, 'lowerLeft', 'R0', Font.EURO_STYLE, pcLabelHeight)
         pcInst.setDrafting(True)
-        
-        if Nx > 1 :
+
+        if self.Nx > 1 :
             id = dbCreateRect(self, l_met1, Box(4.395, 1.45, 5.685, 2.1))
-            for cnt in range(Nx) :
-                groupId = ihpCopyFig(groupId, self, Box(2.34, 0), 'R0')
-                if cnt != Nx-1 :
-                    id = dbCopyShape(id, self, Layer(2.34, 0), 'R0')
-                    
-            
-        MkPin(self, 'C', 1, Box((emWindOrigin_x-Col_Metal1_distance-Col_Metal1_width), (4.1+le), (emWindOrigin_x+we+Col_Metal1_distance+Col_Metal1_width), (4.1+le+0.65)), 'Metal1')
-        MkPin(self, 'B', 2, Box((emWindOrigin_x-Bas_Metal1_distance-Bas_Metal1_width), 1.45, (emWindOrigin_x+we+Bas_Metal1_distance+Bas_Metal1_width), 2.1), 'Metal1')
-        MkPin(self, 'E', 3, Box((emWindOrigin_x-Col_Metal1_distance-Col_Metal1_width), 2.82, (emWindOrigin_x+Col_Metal1_distance+Col_Metal1_width+we), (3.38+le)), 'Metal2')
-    
+            for cnt in range(1, self.Nx) :
+                groupId = ihpCopyFig(groupId, Point(2.34, 0), 'R0')
+                if cnt != self.Nx-1 :
+                    id = dbCopyShape(id, Point(2.34, 0), 'R0')
+
+        groupCol = Grouping();
+        [groupCol.add(id) for id in self.getShapes() if id.col]
+
+        groupBase = Grouping();
+        [groupBase.add(id) for id in self.getShapes() if id.base]
+
+        groupEmi = Grouping();
+        [groupEmi.add(id) for id in self.getShapes() if id.emi]
+
+        MkPin(self, 'C', 1, groupCol.getBBox(), 'Metal1')
+        MkPin(self, 'B', 2, groupBase.getBBox(), 'Metal1')
+        MkPin(self, 'E', 3, groupEmi.getBBox(), 'Metal2')
+
diff --git a/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/npn13G2_base_code.py b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/npn13G2_base_code.py
index a47e215b..1840318f 100644
--- a/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/npn13G2_base_code.py
+++ b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/npn13G2_base_code.py
@@ -83,27 +83,24 @@ def genLayout(self):
 
         stepX = 1.85
         stretchX = stepX*(Nx-1)
+        
         bipwinxoffset = ((2 * (bipwinx - 0.04)) / 2)
         empolyxoffset = ((2 * (empolyx - 0.15)) / 2)
         baspolyxoffset = ((2 * (baspolyx - 0.3)) / 2)
         STIoffset = ((2 * (STI - 0.44)) / 2)
         bipwinyoffset = ((2 * (bipwiny - 0.1)) / 2)
         empolyyoffset = ((2 * (empolyy - 0.18)) / 2)
-        nSDBlockShift = 0.43 - le
-        leoffset = 0
-        if le <  0.5 :
-            pcStepY = 0.41
-            yOffset = 0.20
-        else :
-            pcStepY = 0.41
-            yOffset = 0.20
-
-        if we <=  0.9 :
-            pcRepeatY = 3
-        else :
-            pcRepeatY = 4
+        
+        nSDBlockShift = 0.43 - le # 23.07.09: needed to draw nSDBlock shorter in small pCell
+        
+        # 28.02.07: In the moment only le=48 and le=84 is possible. So use an if to get the right values
+        leoffset = 0 # ((le - 0.07) / 2)  # 03.04.08: moved here
+        
+        pcStepY = 0.41
+        yOffset = 0.20
 
         pcRepeatY = 4
+
         if Nx >  1 :
             CMetY1 = -1.01 - we/2 - leoffset - bipwinyoffset - empolyyoffset
             CMetY2 = -0.57 - we/2 - leoffset - bipwinyoffset - empolyyoffset
@@ -113,39 +110,61 @@ def genLayout(self):
 
         pcPurpose = 'drawing'
         for pcIndexX in range(int(math.floor(Nx))) :
-            pcLayer = Layer('Via1')
+            # loop for generate the given number of vias in variable pcRepeatY
+            # two vias are generated per loop
             for pcIndexY in range(int((math.floor(pcRepeatY)))) :
-                pcInst = dbCreateRect(self, Layer('Via1', 'drawing'), Box((stepX*pcIndexX)-0.3, ((-0.30-yOffset-leoffset-bipwinyoffset-empolyyoffset)+(pcIndexY*pcStepY))-0.2, (stepX*pcIndexX)-0.11, ((-0.11-yOffset-leoffset-bipwinyoffset-empolyyoffset)+(pcIndexY*pcStepY))-0.2))
-                pcInst = dbCreateRect(self, Layer('Via1', 'drawing'), Box((stepX*pcIndexX)+0.11, ((-0.3-yOffset-leoffset-bipwinyoffset-empolyyoffset)+(pcIndexY*pcStepY))-0.2, (stepX*pcIndexX)+0.3, ((-0.11-yOffset-leoffset-bipwinyoffset-empolyyoffset)+(pcIndexY*pcStepY))-0.2))
+                # via on left side 
+                pcInst = dbCreateRect(self, Layer('Via1', pcPurpose),
+                                      Box((stepX*pcIndexX)-0.3,  (( -0.3-yOffset-leoffset-bipwinyoffset-empolyyoffset)+(pcIndexY*pcStepY))-0.2,
+                                          (stepX*pcIndexX)-0.11, ((-0.11-yOffset-leoffset-bipwinyoffset-empolyyoffset)+(pcIndexY*pcStepY))-0.2))
+                # via on right side
+                pcInst = dbCreateRect(self, Layer('Via1', pcPurpose),
+                                      Box((stepX*pcIndexX)+0.11, ((-0.3-yOffset-leoffset-bipwinyoffset-empolyyoffset)+(pcIndexY*pcStepY))-0.2,
+                                          (stepX*pcIndexX)+0.3, ((-0.11-yOffset-leoffset-bipwinyoffset-empolyyoffset)+(pcIndexY*pcStepY))-0.2))
 
-            pcLayer = Layer('Metal1')
-            pcInst = dbCreateRect(self, Layer('Metal1', 'drawing'), Box(stepX*pcIndexX-0.35, (-0.32-we/2-leoffset-bipwinyoffset-empolyyoffset), stepX*pcIndexX+0.35, (0.335+we/2+leoffset+bipwinyoffset+empolyyoffset)))
-            pcLayer = Layer('Cont')
-            pcInst = dbCreateRect(self, Layer('Cont', 'drawing'), Box(stepX*pcIndexX-0.79-le/2, (-0.76-we/2-leoffset-bipwinyoffset-empolyyoffset), stepX*pcIndexX+0.79+le/2, (-0.6-we/2-leoffset-bipwinyoffset-empolyyoffset)))
-            pcInst = dbCreateRect(self, Layer('Cont', 'drawing'), Box(stepX*pcIndexX-0.76, (0.77+we/2-leoffset-bipwinyoffset-empolyyoffset), stepX*pcIndexX+0.76, (0.61+we/2-leoffset-bipwinyoffset-empolyyoffset)))
-            pcLayer = Layer('EmWind')
-            pcInst = dbCreateRect(self, Layer('EmWind', 'drawing'), Box(stepX*pcIndexX-le/2, (-we/2-leoffset), stepX*pcIndexX+le/2, (we/2+leoffset)))
+            pcLayer = 'Metal1'
+            pcInst = dbCreateRect(self, Layer(pcLayer, pcPurpose), Box(stepX*pcIndexX-0.35, (-0.32-we/2-leoffset-bipwinyoffset-empolyyoffset), stepX*pcIndexX+0.35, (0.335+we/2+leoffset+bipwinyoffset+empolyyoffset)))
+            
+            pcLayer = 'Cont'
+            pcInst = dbCreateRect(self, Layer(pcLayer, pcPurpose), Box(stepX*pcIndexX-0.79-le/2, (-0.76-we/2-leoffset-bipwinyoffset-empolyyoffset), stepX*pcIndexX+0.79+le/2, (-0.6-we/2-leoffset-bipwinyoffset-empolyyoffset)))
+            pcInst = dbCreateRect(self, Layer(pcLayer, pcPurpose), Box(stepX*pcIndexX-0.76, (0.77+we/2-leoffset-bipwinyoffset-empolyyoffset), stepX*pcIndexX+0.76, (0.61+we/2-leoffset-bipwinyoffset-empolyyoffset)))
+            
+            pcLayer = 'EmWind'
+            pcInst = dbCreateRect(self, Layer(pcLayer, pcPurpose), Box(stepX*pcIndexX-le/2, (-we/2-leoffset), stepX*pcIndexX+le/2, (we/2+leoffset)))
 
             #ihpAddThermalBjtLayer(pcCellView, Box((stepX*pcIndexX-le/2)-0.05, , -we/2 - leoffset, -0.05, (stepX*pcIndexX+le/2)+0.05, , we/2 + leoffset, +0.05), t, Cell)
-            pcInst = dbCreateRect(self, Layer('EmWind', 'drawing'), Box(stepX*pcIndexX-le/2, (-we/2-leoffset), stepX*pcIndexX+le/2, (we/2+leoffset)))
-            pcLayer = Layer('Activ')
+            
+            pcLayer = 'Activ'
             xl = stepX*pcIndexX-0.06
             xh = xl+0.12
             yl = -0.24-leoffset
             yh = -yl
-            pcInst = dbCreatePolygon(self, Layer('Activ', 'mask'), PointList([Point(xh+0.865, yl-0.74), Point(xl-0.865, yl-0.74), Point(xl-0.865, yh+0.38), Point(xl-0.385, yh+0.38), Point(xl-0.175, yh+0.59), Point(xh+0.175, yh+0.59), Point(xh+0.385, yh+0.38), Point(xh+0.865, yh+0.38)]))
-            pcLayer = Layer('Activ')
-            pcInst = dbCreateRect(self, Layer('Activ', 'drawing'), Box((stepX*pcIndexX-0.89-le/2-empolyxoffset-baspolyxoffset-STIoffset), (-0.83-we/2-leoffset-bipwinyoffset-empolyyoffset), (stepX*pcIndexX+0.89+le/2+empolyxoffset+baspolyxoffset+STIoffset), (-0.89-we/2+0.36-leoffset-bipwinyoffset-empolyyoffset)))
-            pcLayer = Layer('nSD')
-            pcInst = dbCreatePolygon(self, Layer('nSD', 'block'), PointList([Point((stepX * pcIndexX + 0.94 + le/2 + empolyxoffset + baspolyxoffset + STIoffset), (1.98 + we/2 + leoffset + bipwinyoffset + empolyyoffset)), Point((stepX * pcIndexX + 0.94 + le/2 + empolyxoffset + baspolyxoffset + STIoffset), (0.45 + we/2 + leoffset + bipwinyoffset + empolyyoffset)), Point((stepX * pcIndexX + 0.52 + le/2 + empolyxoffset + baspolyxoffset + STIoffset), (0.03 + we/2 + leoffset + bipwinyoffset + empolyyoffset)), Point((stepX * pcIndexX + 0.52 + le/2 + empolyxoffset + baspolyxoffset + STIoffset), ( - 0.6 - we/2 + leoffset + bipwinyoffset + empolyyoffset + nSDBlockShift)), Point((stepX * pcIndexX + 0.27 + le/2 + empolyxoffset + baspolyxoffset + STIoffset), (- 0.85 - we/2 + leoffset + bipwinyoffset + empolyyoffset + nSDBlockShift)), Point((stepX * pcIndexX - 0.27 - le/2 - empolyxoffset - baspolyxoffset - STIoffset), (- 0.85 - we/2 + leoffset + bipwinyoffset + empolyyoffset + nSDBlockShift)), Point((stepX * pcIndexX - 0.52 - le/2 - empolyxoffset - baspolyxoffset - STIoffset), (- 0.6 - we/2 + leoffset + bipwinyoffset + empolyyoffset + nSDBlockShift)), Point((stepX * pcIndexX - 0.52 - le/2 - empolyxoffset - baspolyxoffset - STIoffset), (0.03 + we/2 + leoffset + bipwinyoffset + empolyyoffset) ), Point((stepX * pcIndexX - 0.94 - le/2 - empolyxoffset - baspolyxoffset - STIoffset), (0.45 + we/2 + leoffset + bipwinyoffset + empolyyoffset)), Point((stepX * pcIndexX - 0.94 - le/2 - empolyxoffset - baspolyxoffset - STIoffset), (1.98 + we/2 + leoffset + bipwinyoffset + empolyyoffset))]))
+            pcInst = dbCreatePolygon(self, Layer(pcLayer, 'mask'), PointList([Point(xh+0.865, yl-0.74), Point(xl-0.865, yl-0.74), Point(xl-0.865, yh+0.38), Point(xl-0.385, yh+0.38), Point(xl-0.175, yh+0.59), Point(xh+0.175, yh+0.59), Point(xh+0.385, yh+0.38), Point(xh+0.865, yh+0.38)]))
+            
+            pcInst = dbCreateRect(self, Layer(pcLayer, pcPurpose), Box((stepX*pcIndexX-0.89-le/2-empolyxoffset-baspolyxoffset-STIoffset), (-0.83-we/2-leoffset-bipwinyoffset-empolyyoffset), (stepX*pcIndexX+0.89+le/2+empolyxoffset+baspolyxoffset+STIoffset), (-0.89-we/2+0.36-leoffset-bipwinyoffset-empolyyoffset)))
+            
+            pcLayer ='nSD'
+            pcInst = dbCreatePolygon(self, Layer(pcLayer, 'block'),
+                     PointList([Point((stepX * pcIndexX + 0.94 + le/2 + empolyxoffset + baspolyxoffset + STIoffset), (1.98 + we/2 + leoffset + bipwinyoffset + empolyyoffset)),
+                                Point((stepX * pcIndexX + 0.94 + le/2 + empolyxoffset + baspolyxoffset + STIoffset), (0.45 + we/2 + leoffset + bipwinyoffset + empolyyoffset)),
+                                Point((stepX * pcIndexX + 0.52 + le/2 + empolyxoffset + baspolyxoffset + STIoffset), (0.03 + we/2 + leoffset + bipwinyoffset + empolyyoffset)),
+                                Point((stepX * pcIndexX + 0.52 + le/2 + empolyxoffset + baspolyxoffset + STIoffset), (-0.6 - we/2 + leoffset + bipwinyoffset + empolyyoffset + nSDBlockShift)),
+                                Point((stepX * pcIndexX + 0.27 + le/2 + empolyxoffset + baspolyxoffset + STIoffset), (-0.85 - we/2 + leoffset + bipwinyoffset + empolyyoffset + nSDBlockShift)),
+                                Point((stepX * pcIndexX - 0.27 - le/2 - empolyxoffset - baspolyxoffset - STIoffset), (-0.85 - we/2 + leoffset + bipwinyoffset + empolyyoffset + nSDBlockShift)),
+                                Point((stepX * pcIndexX - 0.52 - le/2 - empolyxoffset - baspolyxoffset - STIoffset), (-0.6 - we/2 + leoffset + bipwinyoffset + empolyyoffset + nSDBlockShift)),
+                                Point((stepX * pcIndexX - 0.52 - le/2 - empolyxoffset - baspolyxoffset - STIoffset), (0.03 + we/2 + leoffset + bipwinyoffset + empolyyoffset) ),
+                                Point((stepX * pcIndexX - 0.94 - le/2 - empolyxoffset - baspolyxoffset - STIoffset), (0.45 + we/2 + leoffset + bipwinyoffset + empolyyoffset)),
+                                Point((stepX * pcIndexX - 0.94 - le/2 - empolyxoffset - baspolyxoffset - STIoffset), (1.98 + we/2 + leoffset + bipwinyoffset + empolyyoffset))]))
 
-        pcLayer = Layer('Metal1')
-        pcInst = dbCreateRect(self, Layer('Metal1', 'drawing'), Box(-0.89-le/2, CMetY1, stretchX+0.89+le/2, CMetY2))
-        pcInst = dbCreateRect(self, Layer('Metal1', 'drawing'), Box(-0.94-le/2, (0.57+we/2+leoffset+bipwinyoffset+empolyyoffset), stretchX+0.94+le/2, (0.81+we/2+leoffset+bipwinyoffset+empolyyoffset)))
-        pcLayer = Layer('Metal2')
-        pcInst = dbCreateRect(self, Layer('Metal2', 'drawing'), Box(-0.89-le/2, (-0.32-we/2-leoffset-bipwinyoffset-empolyyoffset), stretchX+0.89+le/2, (0.335+we/2+leoffset+bipwinyoffset+empolyyoffset)))
-        pcLayer = Layer('TEXT')
+        pcLayer = 'Metal1'
+        pcInst = dbCreateRect(self, Layer(pcLayer, pcPurpose), Box(-0.89-le/2, CMetY1, stretchX+0.89+le/2, CMetY2))
+        pcInst = dbCreateRect(self, Layer(pcLayer, pcPurpose), Box(-0.94-le/2, (0.57+we/2+leoffset+bipwinyoffset+empolyyoffset), stretchX+0.94+le/2, (0.81+we/2+leoffset+bipwinyoffset+empolyyoffset)))
+        
+        pcLayer = 'Metal2'
+        pcInst = dbCreateRect(self, Layer(pcLayer, pcPurpose), Box(-0.89-le/2, (-0.32-we/2-leoffset-bipwinyoffset-empolyyoffset), stretchX+0.89+le/2, (0.335+we/2+leoffset+bipwinyoffset+empolyyoffset)))
+        
+        pcLayer = 'TEXT'
         pcLabelText = self.Text
         pcLabelHeight = 0.35
-        pcInst = dbCreateLabel(self, Layer('TEXT', 'drawing'), Point(0.015, (-1.86 - we/2 - leoffset - bipwinyoffset - empolyyoffset)), pcLabelText, 'centerCenter', 'R0', Font.EURO_STYLE, pcLabelHeight)
+        pcInst = dbCreateLabel(self, Layer(pcLayer, pcPurpose), Point(0.015, (-1.86 - we/2 - leoffset - bipwinyoffset - empolyyoffset)), pcLabelText, 'centerCenter', 'R0', Font.EURO_STYLE, pcLabelHeight)
         pcInst.setDrafting(True)
diff --git a/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/npn13G2_code.py b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/npn13G2_code.py
index 3e4c12cd..133cd305 100644
--- a/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/npn13G2_code.py
+++ b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/npn13G2_code.py
@@ -42,7 +42,7 @@ def defineParamSpecs(cls, specs):
         specs('le', '0.9u', "Emitter Length")
         specs('we', '0.07u', "Emitter Width")
         specs('STI', '0.44u', 'STI')
-        specs('baspolyx', '0.30u', 'baspolyx')
+        specs('baspolyx', '0.3u', 'baspolyx')
         specs('bipwinx', '0.07u', 'bipwinx')
         specs('bipwiny', '0.1u', 'bipwiny')
         specs('empolyx', '0.15u', 'empolyx')
@@ -52,7 +52,7 @@ def defineParamSpecs(cls, specs):
         specs('Iarea', '3m', 'Ic,max/squm@Uce=2V')
         specs('area', '1', 'Area Factor')
         specs('bn', 'sub!', 'Bulk node connection')
-        specs('Vbe', '', 'Base-emitter voltag')
+        specs('Vbe', '', 'Base-emitter voltage')
         specs('Vce', '', 'Collector-emitter voltage')
         specs('m', '1', 'Multiplier')
         specs('trise', '', 'Temp rise from ambient')
@@ -96,37 +96,38 @@ def genLayout(self):
         le = Numeric(le)*1e6
         we = Numeric(we)*1e6
 
-        a = le
+        tmp = le
         le = we
-        we = a
+        we = tmp
+        
         ActivShift = 0.01
         ActivShift = 0.0
-        PWellBlockShift = -0.01
+        
+        # for multiplied npn: le has to be bigger
         stepX = 1.85
         stretchX = stepX*(Nx-1)
         bipwinyoffset = (2 * (bipwiny - 0.1) - 0) / 2
         empolyyoffset = (2 * (empolyy - 0.18)) / 2
 
-        if le <  0.5 :
-            leoffset = 0
-        else :
-            leoffset = 0
-
+        leoffset = 0 # ((le - 0.07) / 2)
+        
         name = self.masterLib + '/' + self.masterCell +'/' + self.masterView
+        # Draw inner part as a subCell
         if Dlo.exists(name) :
             pcMaster = Instance(name)
             params = pcMaster.getParams()
-            params['le'] = self.le
+            params['le'] = self.we
             params['Nx'] = self.Nx
-            params['we'] = self.we
+            params['we'] = self.le
             pcMaster.setParams(params)
             pcMaster.setOrientation(strToOrient(self.masterOrient))
             pcMaster.setOrigin(Point(0, 0))
         else :
             print('(OA) Design "' + name + '" was not found')
 
-        pcLayer = 'TRANS'
         pcPurpose = 'drawing'
+        
+        pcLayer = 'TRANS'
         dbCreatePolygon(self, Layer(pcLayer, pcPurpose), PointList([Point(stretchX+2.45, (2.43 + we/2 + leoffset + bipwinyoffset + empolyyoffset)),
                                                                     Point(-2.45, (2.43 + we/2 + leoffset + bipwinyoffset + empolyyoffset)),
                                                                     Point(-2.45, (-1.98 - we/2 - leoffset - bipwinyoffset - empolyyoffset)),
@@ -162,7 +163,7 @@ def genLayout(self):
         MkPin(self, 'E', 3, Box(-0.71-le/2, (0.32+we/2+leoffset+bipwinyoffset+empolyyoffset), stretchX+0.71+le/2, (-0.335-we/2-leoffset-bipwinyoffset-empolyyoffset)), Layer('Metal2', 'pin'))
 
         pcLayer = 'TEXT'
-        pcLabelText = 'Ae={Ae}um2'.format(Ae=Nx*Ny*le*we)
+        pcLabelText = 'Ae={0:d}*{1:d}*{2:.2f}*{3:.2f}'.format(int(Nx), int(Ny), le, we)
         pcLabelHeight = 0.35
         pcInst = dbCreateLabel(self, Layer(pcLayer, pcPurpose), Point(-1.977, -2.546), pcLabelText, 'lowerLeft', 'R90', Font.EURO_STYLE, pcLabelHeight)
         #setSGq(pcInst, "normalLabel", labelType)
diff --git a/ihp-sg13g2/libs.tech/pycell/pmos_code.py b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/pmosHV_code.py
similarity index 64%
rename from ihp-sg13g2/libs.tech/pycell/pmos_code.py
rename to ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/pmosHV_code.py
index 03c25cdc..32180f88 100644
--- a/ihp-sg13g2/libs.tech/pycell/pmos_code.py
+++ b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/pmosHV_code.py
@@ -1,13 +1,13 @@
 ########################################################################
 #
 # Copyright 2023 IHP PDK Authors
-# 
+#
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
 # You may obtain a copy of the License at
-# 
+#
 #    https://www.apache.org/licenses/LICENSE-2.0
-# 
+#
 # Unless required by applicable law or agreed to in writing, software
 # distributed under the License is distributed on an "AS IS" BASIS,
 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -18,37 +18,39 @@
 __version__ = '$Revision: #3 $'
 
 from cni.dlo import *
-from geometry import *
-from thermal import *
-from utility_functions import *
+from .geometry import *
+from .thermal import *
+from .utility_functions import *
 
 import math
 
-class pmos(DloGen):
+class pmosHV(DloGen):
 
     @classmethod
     def defineParamSpecs(self, specs):
         techparams = specs.tech.getTechParams()
-        
+
         CDFVersion = techparams['CDFVersion']
-        model      = 'sg13_lv_pmos'
-        defL       = techparams['pmos_defL']
-        defW       = techparams['pmos_defW']
-        defNG      = techparams['pmos_defNG']
-        minL       = techparams['pmos_minL']
-        minW       = techparams['pmos_minW']
-        
+        model      = 'sg13_hv_pmos'
+        defL       = techparams['pmosHV_defL']
+        defW       = techparams['pmosHV_defW']
+        defNG      = techparams['pmosHV_defNG']
+        minL       = techparams['pmosHV_minL']
+        minW       = techparams['pmosHV_minW']
+
         specs('cdf_version', CDFVersion, 'CDF Version')
         specs('Display', 'Selected', 'Display', ChoiceConstraint(['All', 'Selected']))
         specs('model', model, 'Model name')
-        
+
         specs('w' ,   defW, 'Width')
+
+        test = Numeric(defW)
         specs('ws',   eng_string(Numeric(defW)/Numeric(defNG)), 'SingleWidth')
         specs('l' ,   defL, 'Length')
         specs('Wmin', minW, 'Wmin')
         specs('Lmin', minL, 'Lmin')
         specs('ng',   defNG, 'Number of Gates')
-        
+
         specs('m', '1', 'Multiplier')
         specs('trise', '', 'Temp rise from ambient')
 
@@ -63,79 +65,72 @@ def genLayout(self):
         self.grid = self.tech.getGridResolution()
         self.techparams = self.tech.getTechParams()
         self.epsilon = self.techparams['epsilon1']
-        
+
         w = self.w
         ng = self.ng
         l = self.l
 
-        typ = 'P'
-        hv = False
-        
         ndiff_layer = Layer('Activ', 'drawing')     # 1
         pdiff_layer = Layer('Activ', 'drawing')     # 1
         poly_layer = Layer('GatPoly', 'drawing')    # 5
+        poly_layer_pin = Layer('GatPoly', 'pin')
         locint_layer = Layer('Cont', 'drawing')     # 6
-        metall_layer = Layer('Metal1', 'drawing')   # 8 
-        pdiffx_layer = Layer('pSD', 'drawing')      # 14 
+        metall_layer = Layer('Metal1', 'drawing')   # 8
+        metall_layer_pin = Layer('Metal1', 'pin')
+        pdiffx_layer = Layer('pSD', 'drawing')      # 14
         well_layer = Layer('NWell', 'drawing')      # 31
         tgo_layer = Layer('ThickGateOx', 'drawing') # 44
-        textlayer = Layer('TEXT', 'drawing')        # 63
-        
+        text_layer = Layer('TEXT', 'drawing')        # 63
+
         endcap = self.techparams['M1_c1']
         cont_size = self.techparams['Cnt_a']
         cont_dist = self.techparams['Cnt_b']
         cont_Activ_overRec = self.techparams['Cnt_c']
         cont_metall_over = self.techparams['M1_c']
-        psd_pActiv_over = self.techparams['pSD_c']
-        nwell_pActiv_over = self.techparams['NW_c']
-        gatpoly_Activ_over = self.techparams['Gat_c']
+        psd_pActiv_over = self.techparams['pSD_c']    # pSD enc. of p+-Activ in nwell
+        nwell_pActiv_over = self.techparams['NW_c1']  # NWell enc. of pActiv
+        gatpoly_Activ_over = self.techparams['Gat_c'] # poly overlap of Activ (endcap)
         gatpoly_cont_dist = self.techparams['Cnt_f']
-        smallw_gatpoly_cont_dist = cont_Activ_overRec+self.techparams['Gat_d']
-        psd_PFET_over = self.techparams['pSD_i']
-        pdiffx_poly_over_orth = 0.48
-        wmin = Numeric(self.techparams['pmos_minW'])
-        lmin = Numeric(self.techparams['pmos_minL'])
-        contActMin = 2*cont_Activ_overRec+cont_size 
-        thGateOxGat = self.techparams['TGO_c']
-        thGateOxAct = self.techparams['TGO_a']
+        smallw_gatpoly_cont_dist = cont_Activ_overRec+self.techparams['Gat_d'] # for w < contActMin -> poly dogbone sep. to gate
+        psd_PFET_over = self.techparams['pSD_i1']     # pSD enc. of Gate
+        
+        wmin = Numeric(self.techparams['pmosHV_minW'])
+        lmin = Numeric(self.techparams['pmosHV_minL'])
+        contActMin = 2*cont_Activ_overRec+cont_size
+        thGateOxGat = self.techparams['TGO_c'] # Overlay over GatPoly
+        thGateOxAct = self.techparams['TGO_a'] # Overlay over Active
 
         dbReplaceProp(self, 'pin#', 5)
-        
+
         w = w*1e6;
         l = l*1e6;
         ng = math.floor(Numeric(ng)+self.epsilon)
         w = w/ng
         w = GridFix(w)
         l = GridFix(l)
-        
-        # additional Text for label
-        if hv :
-            labelhv = 'HV'
-        else :
-            labelhv = ''
-            
+
         if w < contActMin-self.epsilon :
             gatpoly_cont_dist = smallw_gatpoly_cont_dist
-            
+
         xdiff_beg = 0
         ydiff_beg = 0
         ydiff_end = w
-        
+
         if w < wmin-self.epsilon :
             hiGetAttention()
             print('Width < '+str(wmin))
             w = wmin
-            
+
         if l < lmin-self.epsilon :
             hiGetAttention()
             print('Length < '+str(lmin))
             l = lmin
-            
+
         if ng < 1 :
             hiGetAttention()
             print('Minimum one finger')
             ng = 1
-            
+
         xanz = math.floor((w-2*cont_Activ_overRec+cont_dist)/(cont_size+cont_dist)+self.epsilon)
         w1 = xanz*(cont_size+cont_dist)-cont_dist+cont_Activ_overRec+cont_Activ_overRec
         xoffset = (w-w1)/2
@@ -145,26 +140,26 @@ def genLayout(self):
             xoffset = 0
             diffoffset = (contActMin-w)/2
             diffoffset = Snap(diffoffset)
-        
-        # get the number of contacts    
+
+        # get the number of contacts
         lcon = w-2*cont_Activ_overRec
         distc = cont_size+cont_dist
         ncont = math.floor((lcon+cont_dist-2*endcap)/distc + self.epsilon)
         if zerop(ncont) :
             ncont = 1
-            
+
         diff_cont_offset = GridFix((w-2*cont_Activ_overRec-ncont*cont_size-(ncont-1)*cont_dist)/2)
-        
+
         # draw the cont row
         xcont_beg = xdiff_beg+cont_Activ_overRec
         ycont_beg = ydiff_beg+cont_Activ_overRec
         ycont_cnt = ycont_beg+diffoffset+diff_cont_offset
         xcont_end = xcont_beg+cont_size
-        
+
         # draw contacts
         # LI and Metall
         contactArray(self, 0, locint_layer, xcont_beg, ydiff_beg, xcont_end, ydiff_end+diffoffset*2, 0, cont_Activ_overRec, cont_size, cont_dist)
-        
+
         # 30.01.08 GGa added block
         # draw Metal rect
         # calculate bot and top cont position
@@ -175,73 +170,80 @@ def genLayout(self):
         yMet2 = max(yMet2, ydiff_end+diffoffset)
 
         dbCreateRect(self, metall_layer, Box(xcont_beg-cont_metall_over, yMet1, xcont_end+cont_metall_over, yMet2))
-        
+
         if w > contActMin :
-            MkPin(self, 'S', 3, Box(xcont_beg-cont_metall_over, yMet1, xcont_end+cont_metall_over, yMet2), metall_layer)
+            MkPin(self, 'S', 3, Box(xcont_beg-cont_metall_over, yMet1, xcont_end+cont_metall_over, yMet2), metall_layer_pin)
         else :
-            MkPin(self, 'S', 3, Box(xcont_beg-cont_metall_over, yMet1, xcont_end+cont_metall_over, yMet2), metall_layer)
-            
-        if typ == 'N' :
-            dbCreateRect(self, ndiff_layer, Box(xcont_beg-cont_Activ_overRec, ycont_beg-cont_Activ_overRec, xcont_end+cont_Activ_overRec, ycont_beg+cont_size+cont_Activ_overRec))
-        else :  # typ == 'P'
-            dbCreateRect(self, pdiff_layer, Box(xcont_beg-cont_Activ_overRec, ycont_beg-cont_Activ_overRec, xcont_end+cont_Activ_overRec, ycont_beg+cont_size+cont_Activ_overRec))
-            
+            MkPin(self, 'S', 3, Box(xcont_beg-cont_metall_over, yMet1, xcont_end+cont_metall_over, yMet2), metall_layer_pin)
+
+        dbCreateRect(self, pdiff_layer, Box(xcont_beg-cont_Activ_overRec, ycont_beg-cont_Activ_overRec, xcont_end+cont_Activ_overRec, ycont_beg+cont_size+cont_Activ_overRec))
+
         for i in range(1, int(ng)+1) :
             # draw the poly line
             xpoly_beg = xcont_end+gatpoly_cont_dist
             ypoly_beg = ydiff_beg-gatpoly_Activ_over
             xpoly_end = xpoly_beg+l
             ypoly_end = ydiff_end+gatpoly_Activ_over
-            
+
             dbCreateRect(self, poly_layer, Box(xpoly_beg, ypoly_beg+diffoffset, xpoly_end, ypoly_end+diffoffset))
-            
+
             ihpAddThermalMosLayer(self, Box(xpoly_beg, ypoly_beg+diffoffset, xpoly_end, ypoly_end+diffoffset), True, 'pmos')
-            
+
             if i == 1 :
-                dbCreateLabel(self, textlayer, Point((xpoly_beg+xpoly_end)/2, (ypoly_beg+ypoly_end)/2+diffoffset), 'pmos'+labelhv, 'centerCenter', 'R90', Font.EURO_STYLE, 0.1)
-                
+                dbCreateLabel(self, text_layer, Point((xpoly_beg+xpoly_end)/2, (ypoly_beg+ypoly_end)/2+diffoffset), 'pmosHV', 'centerCenter', 'R90', Font.EURO_STYLE, 0.1)
+
             if onep(i) :
-                MkPin(self, 'G', 2, Box(xpoly_beg, ypoly_beg+diffoffset, xpoly_end, ypoly_end+diffoffset), poly_layer)
-            
-            # draw the second cont row    
+                MkPin(self, 'G', 2, Box(xpoly_beg, ypoly_beg+diffoffset, xpoly_end, ypoly_end+diffoffset), poly_layer_pin)
+
+            # draw the second cont row
             xcont_beg = xpoly_end+gatpoly_cont_dist
             ycont_beg = ydiff_beg+cont_Activ_overRec
             ycont_cnt = ycont_beg+diffoffset+diff_cont_offset
             xcont_end = xcont_beg+cont_size
-            
+
             dbCreateRect(self, metall_layer, Box(xcont_beg-cont_metall_over, yMet1, xcont_end+cont_metall_over, yMet2))
             # draw contacts
             # LI and Metall
             contactArray(self, 0, locint_layer, xcont_beg, ydiff_beg, xcont_end, ydiff_end+diffoffset*2, 0, cont_Activ_overRec, cont_size, cont_dist)
-            
+
             if onep(i) :
                 if w > contActMin :
-                    MkPin(self, 'D', 1, Box(xcont_beg-cont_metall_over, yMet1, xcont_end+cont_metall_over, yMet2), metall_layer)
+                    MkPin(self, 'D', 1, Box(xcont_beg-cont_metall_over, yMet1, xcont_end+cont_metall_over, yMet2), metall_layer_pin)
                 else :
-                    MkPin(self, 'D', 1, Box(xcont_beg-cont_metall_over, yMet1, xcont_end+cont_metall_over, yMet2), metall_layer)
-                    
-                
-            if typ == 'N' :
-                dbCreateRect(self, ndiff_layer, Box(xcont_beg-cont_Activ_overRec, ycont_beg-cont_Activ_overRec, xcont_end+cont_Activ_overRec, ycont_beg+cont_size+cont_Activ_overRec))
-            else :
-                dbCreateRect(self, pdiff_layer, Box(xcont_beg-cont_Activ_overRec, ycont_beg-cont_Activ_overRec, xcont_end+cont_Activ_overRec, ycont_beg+cont_size+cont_Activ_overRec))
+                    MkPin(self, 'D', 1, Box(xcont_beg-cont_metall_over, yMet1, xcont_end+cont_metall_over, yMet2), metall_layer_pin)
+
+
+            dbCreateRect(self, pdiff_layer, Box(xcont_beg-cont_Activ_overRec, ycont_beg-cont_Activ_overRec, xcont_end+cont_Activ_overRec, ycont_beg+cont_size+cont_Activ_overRec))
         # for i 1 ng
-                 
-        # now finish drawing the diffusion   
+
+        # now finish drawing the diffusion
         xdiff_end = xcont_end+cont_Activ_overRec
-        if typ == 'N' :
-            dbCreateRect(self, ndiff_layer, Box(xdiff_beg, ydiff_beg+diffoffset, xdiff_end, ydiff_end+diffoffset))
-        else :
-            dbCreateRect(self, pdiff_layer,  Box(xdiff_beg, ydiff_beg+diffoffset, xdiff_end, ydiff_end+diffoffset))
-            dbCreateRect(self, pdiffx_layer, Box(xdiff_beg-psd_pActiv_over, ypoly_beg-psd_PFET_over+gatpoly_Activ_over+diffoffset, xdiff_end+psd_pActiv_over, ypoly_end+psd_PFET_over-gatpoly_Activ_over+diffoffset))
-            # draw minimum nWell
-            nwell_offset = max(0, GridFix((contActMin-w)/2+0.5*self.grid))
-            dbCreateRect(self, well_layer, Box(xdiff_beg-nwell_pActiv_over, ydiff_beg-nwell_pActiv_over+diffoffset-nwell_offset, xdiff_end+nwell_pActiv_over, ydiff_end+nwell_pActiv_over+diffoffset+nwell_offset))
-         
-        # B-Pin   
-        MkPin(self, 'B', 4, Box(xcont_beg-cont_Activ_overRec, ycont_beg-cont_Activ_overRec, xcont_end+cont_Activ_overRec, ycont_beg+cont_size+cont_Activ_overRec), Layer('Substrate', 'drawing'))
         
-        # draw Thick Gate Oxide
-        if hv :
-            dbCreateRect(self, Layer('ThickGateOx', 'drawing'), Box(xdiff_beg-thGateOxAct, ydiff_beg-gatpoly_Activ_over-thGateOxGat, xdiff_end+thGateOxAct, ydiff_end+gatpoly_Activ_over+thGateOxGat))
+        dbCreateRect(self, pdiff_layer,  Box(xdiff_beg, ydiff_beg+diffoffset, xdiff_end, ydiff_end+diffoffset))
+        dbCreateRect(self, pdiffx_layer, Box(xdiff_beg-psd_pActiv_over, ypoly_beg-psd_PFET_over+gatpoly_Activ_over+diffoffset, xdiff_end+psd_pActiv_over, ypoly_end+psd_PFET_over-gatpoly_Activ_over+diffoffset))
+        
+        # draw minimum nWell
+        nwell_offset = max(0, GridFix((contActMin-w)/2+0.5*self.grid))
+        dbCreateRect(self, well_layer, Box(xdiff_beg-nwell_pActiv_over, ydiff_beg-nwell_pActiv_over+diffoffset-nwell_offset,
+                                           xdiff_end+nwell_pActiv_over, ydiff_end+nwell_pActiv_over+diffoffset+nwell_offset))
+
+        # B-Pin
+        MkPin(self, 'B', 4, Box(xcont_beg-cont_Activ_overRec, ycont_beg-cont_Activ_overRec, xcont_end+cont_Activ_overRec, ycont_beg+cont_size+cont_Activ_overRec), Layer('Substrate', 'drawing'))
 
+        # draw Thick Gate Oxide
+        
+        # first get standard values
+        x1 = xdiff_beg-thGateOxAct
+        x2 = xdiff_end+thGateOxAct
+        y1 = ydiff_beg-gatpoly_Activ_over-thGateOxGat
+        y2 = ydiff_end+gatpoly_Activ_over+thGateOxGat
+        # now check, if NWell is drawn bigger
+        if nwell_pActiv_over > thGateOxAct :
+            x1 = xdiff_beg-nwell_pActiv_over
+            x2 = xdiff_end+nwell_pActiv_over
+        if (nwell_pActiv_over+diffoffset-nwell_offset) > (gatpoly_Activ_over-thGateOxGat) :
+            y1 = ydiff_beg-nwell_pActiv_over+diffoffset-nwell_offset
+            y2 = ydiff_end+nwell_pActiv_over+diffoffset+nwell_offset
+        
+        dbCreateRect(self, tgo_layer, Box(x1, y1, x2, y2))
+        
diff --git a/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/pypreprocessor.py b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/pypreprocessor.py
new file mode 120000
index 00000000..0f55d982
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/pypreprocessor.py
@@ -0,0 +1 @@
+../../pypreprocessor/pypreprocessor/__init__.py
\ No newline at end of file
diff --git a/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/sealring_code.py b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/sealring_code.py
index 9e6029ca..559def7d 100644
--- a/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/sealring_code.py
+++ b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/sealring_code.py
@@ -189,3 +189,8 @@ def genLayout(self):
         # EdgeSeal box around sealring
         dbCreateRect(self, Layer('EdgeSeal', 'boundary'),
             Box(edgeBox_startx, edgeBox_starty, w, l))
+            
+        # Creating text label w/ area for device registration
+        sealringArea = (l * w) / 1e12 # mm2
+        pcLabelText = 'Device registration size: x={0:.1f} um ; y={1:.1f} um\nCalculated area: {2:.1e} sq mm'.format(l, w, sealringArea)
+        pcInst = dbCreateLabel(self, Layer('TEXT', 'drawing'), Point(5.0, 5.0), pcLabelText, 'lowerLeft', 'R0', Font.EURO_STYLE, 5.0)
diff --git a/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/utility_functions.py b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/utility_functions.py
index a716fdc1..f4c83cbb 100644
--- a/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/utility_functions.py
+++ b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/ihp/utility_functions.py
@@ -351,8 +351,8 @@ def strToAlignt(value):
     if value == 'upperCenter' :
         return Location.UPPER_CENTER
 
-    if value == 'lowerCenter' :
-        return Location.LOWER_CENTER
+    if value == 'lowerRight' :
+        return Location.LOWER_RIGHT
 
     if value == 'centerRight' :
         return Location.CENTER_RIGHT
diff --git a/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/sg13g2_tech.json b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/sg13g2_tech.json
index bbc72377..de7d4262 100644
--- a/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/sg13g2_tech.json
+++ b/ihp-sg13g2/libs.tech/klayout/python/sg13g2_pycell_lib/sg13g2_tech.json
@@ -905,304 +905,5 @@
         "sealring_complete_edgeBox": "25u"
     },
     "Layers": {
-        "Activ":            "1, 0",
-        "Activ.drawing":    "1, 0",
-        "Activ.label":      "1, 1",
-        "Activ.pin":        "1, 2",
-        "Activ.net":        "1, 3",
-        "Activ.boundary":   "1, 4",
-        "Activ.lvs":        "1, 19",
-        "Activ.mask":       "1, 20",
-        "Activ.filler":     "1, 22",
-        "Activ.nofill":     "1, 23",
-        "Activ.OPC":        "1, 26",
-        "Activ.iOPC":       "1, 27",
-        "Activ.noqrc":      "1, 28",
-
-        "GatPoly":          "5, 0",
-        "GatPoly.drawing":  "5, 0",
-        "GatPoly.label":    "5, 1",
-        "GatPoly.pin":      "5, 2",
-        "GatPoly.net":      "5, 3",
-        "GatPoly.boundary": "5, 4",
-        "GatPoly.track":    "5, 5",
-        "GatPoly.filler":   "5, 22",
-        "GatPoly.nofill":   "5, 23",
-        "GatPoly.OPC":      "5, 26",
-        "GatPoly.iOPC":     "5, 27",
-        "GatPoly.noqrc":    "5, 28",
-
-        "Cont":             "6, 0",
-        "Cont.drawing":     "6, 0",
-        "Cont.grid":        "6, 1",
-        "Cont.blockage":    "6, 2",
-        "Cont.net":         "6, 3",
-        "Cont.boundary":    "6, 4",
-        "Cont.OPC":         "6, 26",
-
-        "nSD":              "7, 0",
-        "nSD.drawing":      "7, 0",
-        "nSD.block":        "7, 21",
-
-        "Metal1":           "8, 0",
-        "Metal1.drawing":   "8, 0",
-        "Metal1.label":     "8, 1",
-        "Metal1.pin":       "8, 2",
-        "Metal1.net":       "8, 3",
-        "Metal1.boundary":  "8, 4",
-        "Metal1.track":     "8, 5",
-        "Metal1.grid":      "8, 6",
-        "Metal1.blockage":  "8, 7",
-        "Metal1.mask":      "8, 20",
-        "Metal1.filler":    "8, 22",
-        "Metal1.nofill":    "8, 23",
-        "Metal1.slit":      "8, 24",
-        "Metal1.text":      "8, 25",
-        "Metal1.OPC":       "8, 26",
-        "Metal1.noqrc":     "8, 28",
-        "Metal1.res":       "8, 29",
-        "Metal1.iprobe":    "8, 33",
-        "Metal1.diffprb":   "8, 34",
-
-        "Passiv":           "9, 0",
-        "Passiv.drawing":   "9, 0",
-        "Passiv.label":     "9, 1",
-        "Passiv.pin":       "9, 2",
-        "Passiv.net":       "9, 3",
-        "Passiv.boundary":  "9, 4",
-        "Passiv.pdl":       "9, 40",
-        "Passiv.sbump":     "9, 36",
-        "Passiv.pillar":    "9, 35",
-
-        "Metal2":           "10, 0",
-        "Metal2.drawing":   "10, 0",
-        "Metal2.label":     "10, 1",
-        "Metal2.pin":       "10, 2",
-        "Metal2.net":       "10, 3",
-        "Metal2.boundary":  "10, 4",
-        "Metal2.track":     "10, 5",
-        "Metal2.grid":      "10, 6",
-        "Metal2.blockage":  "10, 7",
-        "Metal2.mask":      "10, 20",
-        "Metal2.filler":    "10, 22",
-        "Metal2.nofill":    "10, 23",
-        "Metal2.slit":      "10, 24",
-        "Metal2.text":      "10, 25",
-        "Metal2.OPC":       "10, 26",
-        "Metal2.noqrc":     "10, 28",
-        "Metal2.res":       "10, 29",
-        "Metal2.iprobe":    "10, 33",
-        "Metal2.diffprb":   "10, 34",
-
-        "pSD":              "14, 0",
-        "pSD.drawing":      "14, 0",
-
-        "Via1":             "19, 0",
-        "Via1.drawing":     "19, 0",
-        "Via1.grid":        "19, 1",
-        "Via1.blockage":    "19, 2",
-        "Via1.net":         "19, 3",
-        "Via1.boundary":    "19, 4",
-
-        "RES":              "24, 0",
-        "RES.drawing":      "24, 0",
-        "RES.label":        "24, 1",
-
-        "TRANS":            "26, 0",
-        "TRANS.drawing":    "26, 0",
-        
-        "SalBlock":			"28, 0",
-
-        "Via2":             "29, 0",
-        "Via2.drawing":     "29, 0",
-        "Via2.grid":        "29, 1",
-        "Via2.blockage":    "29, 2",
-        "Via2.net":         "29, 3",
-        "Via2.boundary":    "29, 4",
-
-        "Metal3":           "30, 0",
-        "Metal3.drawing":   "30, 0",
-        "Metal3.label":     "30, 1",
-        "Metal3.pin":       "30, 2",
-        "Metal3.net":       "30, 3",
-        "Metal3.boundary":  "30, 4",
-        "Metal3.track":     "30, 5",
-        "Metal3.grid":      "30, 6",
-        "Metal3.blockage":  "30, 7",
-        "Metal3.mask":      "30, 20",
-        "Metal3.filler":    "30, 22",
-        "Metal3.nofill":    "30, 23",
-        "Metal3.slit":      "30, 24",
-        "Metal3.text":      "30, 25",
-        "Metal3.OPC":       "30, 26",
-        "Metal3.noqrc":     "30, 28",
-        "Metal3.res":       "30, 29",
-        "Metal3.iprobe":    "30, 33",
-        "Metal3.diffprb":   "30, 34",
-
-        "NWell":            "31, 0",
-        "NWell.drawing":    "31, 0",
-        "NWell.label":      "31, 1",
-        "NWell.pin":        "31, 2",
-        "NWell.net":        "31, 3",
-        "NWell.boundary":   "31, 4",
-
-        "nBuLay":           "32, 0",
-        "nBuLay.drawing":   "32, 0",
-        "nBuLay.label":     "32, 1",
-        "nBuLay.pin":       "32, 2",
-        "nBuLay.net":       "32, 3",
-        "nBuLay.boundary":  "32, 4",
-        "nBuLay.blockage":  "32, 21",
-
-        "EmWind":           "33, 0",
-        "EmWind.drawing":   "33, 0",
-        "EmWind.OPC":       "33, 26",
-
-        "MIM":              "36, 0",
-        "MIM.drawing":      "36, 0",
-        "MIM.net":          "36, 3",
-        "MIM.boundary":     "36, 4",
-
-        "EdgeSeal":         "39, 0",
-        "EdgeSeal.drawing": "39, 0",
-        "EdgeSeal.boundary":  "39, 4",
-
-        "Substrate":        "40, 0",
-        "Substrate.drawing":  "40, 0",
-        "Substrate.text":   "40, 25",
-
-        "ThickGateOx":      "44, 0",
-        "ThickGateOx.drawing":  "44, 0",
-
-        "Via3":             "49, 0",
-        "Via3.drawing":     "49, 0",
-        "Via3.grid":        "49, 1",
-        "Via3.blockage":    "49, 2",
-        "Via3.net":         "49, 3",
-        "Via3.boundary":    "49, 4",
-
-        "Metal4":           "50, 0",
-        "Metal4.drawing":   "50, 0",
-        "Metal4.label":     "50, 1",
-        "Metal4.pin":       "50, 2",
-        "Metal4.net":       "50, 3",
-        "Metal4.boundary":  "50, 4",
-        "Metal4.track":     "50, 5",
-        "Metal4.grid":      "50, 6",
-        "Metal4.blockage":  "50, 7",
-        "Metal4.mask":      "50, 20",
-        "Metal4.filler":    "50, 22",
-        "Metal4.nofill":    "50, 23",
-        "Metal4.slit":      "50, 24",
-        "Metal4.text":      "50, 25",
-        "Metal4.OPC":       "50, 26",
-        "Metal4.noqrc":     "50, 28",
-        "Metal4.res":       "50, 29",
-        "Metal4.iprobe":    "50, 33",
-        "Metal4.diffprb":   "50, 34",
-
-        "HeatTrans":        "51, 0",
-        "HeatTrans.drawing": "51, 0",
-        
-        "HeatRes":        "52, 0",
-        "HeatRes.drawing": "52, 0",
-
-        "TEXT":             "63, 0",
-        "TEXT.drawing":     "63, 0",
-
-        "Via4":             "66, 0",
-        "Via4.drawing":     "66, 0",
-        "Via4.grid":        "66, 1",
-        "Via4.blockage":    "66, 2",
-        "Via4.net":         "66, 3",
-        "Via4.boundary":    "66, 4",
-
-        "Metal5":           "67, 0",
-        "Metal5.drawing":   "67, 0",
-        "Metal5.label":     "67, 1",
-        "Metal5.pin":       "67, 2",
-        "Metal5.net":       "67, 3",
-        "Metal5.boundary":  "67, 4",
-        "Metal5.track":     "67, 5",
-        "Metal5.grid":      "67, 6",
-        "Metal5.blockage":  "67, 7",
-        "Metal5.mask":      "67, 20",
-        "Metal5.filler":    "67, 22",
-        "Metal5.nofill":    "67, 23",
-        "Metal5.slit":      "67, 24",
-        "Metal5.text":      "67, 25",
-        "Metal5.OPC":       "67, 26",
-        "Metal5.noqrc":     "67, 28",
-        "Metal5.res":       "67, 29",
-        "Metal5.iprobe":    "67, 33",
-        "Metal5.diffprb":   "67, 34",
-
-        "EXTBlock":         "111, 0",
-        "EXTBlock.drawing": "111, 0",
-
-        "TopVia1":             "125, 0",
-        "TopVia1.drawing":     "125, 0",
-        "TopVia1.grid":        "125, 1",
-        "TopVia1.blockage":    "125, 2",
-        "TopVia1.net":         "125, 3",
-        "TopVia1.boundary":    "125, 4",
-
-        "TopMetal1":           "126, 0",
-        "TopMetal1.drawing":   "126, 0",
-        "TopMetal1.label":     "126, 1",
-        "TopMetal1.pin":       "126, 2",
-        "TopMetal1.net":       "126, 3",
-        "TopMetal1.boundary":  "126, 4",
-        "TopMetal1.track":     "126, 5",
-        "TopMetal1.grid":      "126, 6",
-        "TopMetal1.blockage":  "126, 7",
-        "TopMetal1.mask":      "126, 20",
-        "TopMetal1.filler":    "126, 22",
-        "TopMetal1.nofill":    "126, 23",
-        "TopMetal1.slit":      "126, 24",
-        "TopMetal1.text":      "126, 25",
-        "TopMetal1.OPC":       "126, 26",
-        "TopMetal1.noqrc":     "126, 28",
-        "TopMetal1.res":       "126, 29",
-        "TopMetal1.iprobe":    "126, 33",
-        "TopMetal1.diffprb":   "126, 34",
-
-        "PolyRes":             "128, 0",
-        "PolyRes.drawing":     "128, 0",
-        "PolyRes.label":       "128, 1",
-        "PolyRes.pin":         "128, 2",
-        "PolyRes.net":         "128, 3",
-        "PolyRes.boundary":    "128, 4",
-
-        "Vmim":                "129, 0",
-        "Vmim.drawing":        "129, 0",
-
-        "TopVia2":             "133, 0",
-        "TopVia2.drawing":     "133, 0",
-        "TopVia2.grid":        "133, 1",
-        "TopVia2.blockage":    "133, 2",
-        "TopVia2.net":         "133, 3",
-        "TopVia2.boundary":    "133, 4",
-
-        "TopMetal2":           "134, 0",
-        "TopMetal2.drawing":   "134, 0",
-        "TopMetal2.label":     "134, 1",
-        "TopMetal2.pin":       "134, 2",
-        "TopMetal2.net":       "134, 3",
-        "TopMetal2.boundary":  "134, 4",
-        "TopMetal2.track":     "134, 5",
-        "TopMetal2.grid":      "134, 6",
-        "TopMetal2.blockage":  "134, 7",
-        "TopMetal2.mask":      "134, 20",
-        "TopMetal2.filler":    "134, 22",
-        "TopMetal2.nofill":    "134, 23",
-        "TopMetal2.slit":      "134, 24",
-        "TopMetal2.text":      "134, 25",
-        "TopMetal2.OPC":       "134, 26",
-        "TopMetal2.noqrc":     "134, 28",
-        "TopMetal2.res":       "134, 29",
-        "TopMetal2.iprobe":    "134, 33",
-        "TopMetal2.diffprb":   "134, 34"
     }
 }
diff --git a/ihp-sg13g2/libs.tech/klayout/sg13g2_tests/pycell_test.py b/ihp-sg13g2/libs.tech/klayout/sg13g2_tests/pycell_test.py
index 85dd85b5..e44a2b99 100644
--- a/ihp-sg13g2/libs.tech/klayout/sg13g2_tests/pycell_test.py
+++ b/ihp-sg13g2/libs.tech/klayout/sg13g2_tests/pycell_test.py
@@ -25,26 +25,51 @@
 #
 # KLAYOUT_PATH=$(pwd)/.. klayout ihp-pycells.gds -e
 
-ly = pya.Layout()
+layout = pya.Layout()
 
-pcellNmos = ly.create_cell("nmos", "SG13_dev", { "l": 0.350e-6, "w": 6e-6, "ng": 3 })
-pcellPmos = ly.create_cell("pmos", "SG13_dev", { "l": 0.350e-6, "w": 6e-6, "ng": 3 })
-pcellCmim = ly.create_cell("cmim", "SG13_dev", {})
-pcellSealring = ly.create_cell("sealring", "SG13_dev", {})
-pcellNpn13G2Base = ly.create_cell("npn13G2_base", "SG13_dev", {})
-pcellNpn13G2 = ly.create_cell("npn13G2", "SG13_dev", {})
+pcellNmos = layout.create_cell("nmos", "SG13_dev", { "l": 0.350e-6, "w": 6e-6, "ng": 3 })
+pcellPmos = layout.create_cell("pmos", "SG13_dev", { "l": 0.350e-6, "w": 6e-6, "ng": 3 })
+pcellCmim = layout.create_cell("cmim", "SG13_dev", {})
+pcellSealring = layout.create_cell("sealring", "SG13_dev", {})
+pcellNpn13G2Base = layout.create_cell("npn13G2_base", "SG13_dev", {})
+pcellNpn13G2 = layout.create_cell("npn13G2", "SG13_dev", {})
+pcellNpn13G2L = layout.create_cell("npn13G2L", "SG13_dev", {})
+pcellNpn13G2V = layout.create_cell("npn13G2V", "SG13_dev", {})
+pcellRsil = layout.create_cell("rsil", "SG13_dev", {})
+pcellRhigh = layout.create_cell("rhigh", "SG13_dev", {})
+pcellRppd = layout.create_cell("rppd", "SG13_dev", {})
+pcellInductor2 = layout.create_cell("inductor2", "SG13_dev", {})
+pcellInductor2_sc = layout.create_cell("inductor2_sc", "SG13_dev", {})
+pcellInductor2_sp = layout.create_cell("inductor2_sp", "SG13_dev", {})
+pcellInductor3 = layout.create_cell("inductor3", "SG13_dev", {})
+pcellInductor3_sc = layout.create_cell("inductor3_sc", "SG13_dev", {})
+pcellInductor3_sp = layout.create_cell("inductor3_sp", "SG13_dev", {})
+pcellDAntenna = layout.create_cell("dantenna", "SG13_dev", {})
+pcellDPAntenna = layout.create_cell("dpantenna", "SG13_dev", {})
 
-#pcell = ly.create_cell("rsil", "SG13_dev", { "l": "3e-6", "w": "6e-6", "b": 1, "ps": "1e-6", "R": "1e-6"})
+top = layout.create_cell("TOP")
 
-top = ly.create_cell("TOP")
 top.insert(pya.DCellInstArray(pcellNmos, pya.DTrans()))
-top.insert(pya.DCellInstArray(pcellPmos, pya.DTrans(pya.DVector(3, 0))))
-top.insert(pya.DCellInstArray(pcellCmim, pya.DTrans(pya.DVector(0, -9))))
-top.insert(pya.DCellInstArray(pcellSealring, pya.DTrans(pya.DVector(50, -9))))
-top.insert(pya.DCellInstArray(pcellNpn13G2, pya.DTrans(pya.DVector(3, 8))))
+top.insert(pya.DCellInstArray(pcellPmos, pya.DTrans(pya.DVector(4, 0))))
+top.insert(pya.DCellInstArray(pcellNpn13G2, pya.DTrans(pya.DVector(11, 3.1))))
+top.insert(pya.DCellInstArray(pcellNpn13G2L, pya.DTrans(pya.DVector(16, -0.3))))
+top.insert(pya.DCellInstArray(pcellNpn13G2V, pya.DTrans(pya.DVector(25, -0.3))))
+top.insert(pya.DCellInstArray(pcellRhigh, pya.DTrans(pya.DVector(36, 0.2))))
+top.insert(pya.DCellInstArray(pcellRppd, pya.DTrans(pya.DVector(38, 0.2))))
+top.insert(pya.DCellInstArray(pcellRsil, pya.DTrans(pya.DVector(40, 0.2))))
+top.insert(pya.DCellInstArray(pcellCmim, pya.DTrans(pya.DVector(43, 0.2))))
+top.insert(pya.DCellInstArray(pcellDAntenna, pya.DTrans(pya.DVector(52, -0.3))))
+top.insert(pya.DCellInstArray(pcellDPAntenna, pya.DTrans(pya.DVector(54, 0))))
+top.insert(pya.DCellInstArray(pcellInductor2, pya.DTrans(pya.DVector(40, -85))))
+top.insert(pya.DCellInstArray(pcellInductor2_sc, pya.DTrans(pya.DVector(125, -85))))
+top.insert(pya.DCellInstArray(pcellInductor2_sp, pya.DTrans(pya.DVector(210, -85))))
+top.insert(pya.DCellInstArray(pcellInductor3, pya.DTrans(pya.DVector(49, -190))))
+top.insert(pya.DCellInstArray(pcellInductor3_sc, pya.DTrans(pya.DVector(152, -190))))
+top.insert(pya.DCellInstArray(pcellInductor3_sp, pya.DTrans(pya.DVector(255, -190))))
+top.insert(pya.DCellInstArray(pcellSealring, pya.DTrans(pya.DVector(310, -190))))
 
 output = "SG13_dev.gds"
-ly.write(output)
+layout.write(output)
 
 print("IHP PyCells layout written to: " + output)
 
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/drc/MissingRules_maximal.md b/ihp-sg13g2/libs.tech/klayout/tech/drc/MissingRules_maximal.md
index cd239ee6..8e516cd0 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/drc/MissingRules_maximal.md
+++ b/ihp-sg13g2/libs.tech/klayout/tech/drc/MissingRules_maximal.md
@@ -1,246 +1,153 @@
 # Missing Rules
 
-- NW.b
-- NW.b1
-- NW.c
-- NW.c1
-- NW.d
-- NW.e
-- NW.e1
-- NW.f
-- NW.f1
-- PWB.d
-- PWB.e
-- PWB.e1
-- PWB.f
-- PWB.f1
-- NBL.b
-- NBL.c
-- NBL.d
-- NBL.e
-- NBL.f
-- NBLB.c
-- Act.c
-- Act.e
-- AFil.c
-- AFil.c1
-- AFil.d
-- AFil.e
-- AFil.i
-- AFil.j
-- TGO.a
-- TGO.b
-- TGO.c
-- TGO.d
-- Gat.a1
-- Gat.a2
-- Gat.a3
-- Gat.a4
-- Gat.c
-- Gat.g
-- GFil.e
-- GFil.i
-- pSD.c
-- pSD.c1
-- pSD.f
-- pSD.g
-- pSD.i
-- pSD.i1
-- pSD.l
-- pSD.m
-- pSD.n
-- nSDB.c
-- nSDB.d
-- nSDB.e
-- Sal.c
-- Cnt.c
-- Cnt.d
-- Cnt.e
-- Cnt.g1
-- Cnt.g2
-- CntB.a
-- CntB.b1
-- CntB.c
-- CntB.d
-- CntB.g2
-- CntB.h1
-- M1.c1
-- M1.e
-- M1.f
-- M1.g
-- M1.i
-- M2.c
-- M2.c1
-- M2.e
-- M2.f
-- M2.g
-- M2.i
-- M3.c
-- M3.c1
-- M3.e
-- M3.f
-- M3.g
-- M3.i
-- M4.c
-- M4.c1
-- M4.e
-- M4.f
-- M4.g
-- M4.i
-- M5.c
-- M5.c1
-- M5.e
-- M5.f
-- M5.g
-- M5.i
-- M1Fil.a2
-- M2Fil.a2
-- M3Fil.a2
-- M4Fil.a2
-- M5Fil.a2
-- V1.c
-- V1.c1
-- V2.c
-- V2.c1
-- V3.c
-- V3.c1
-- V4.c
-- V4.c1
-- TV1.c
-- TV1.d
-- TM1Fil.a1
-- TV2.c
-- TV2.d
-- TM2.bR
-- TM2Fil.a1
-- Pas.c
-- npnG2.a
-- npnG2.b
-- npnG2.c
-- npnG2.d
-- npnG2.d1
-- npnG2.d2
-- npnG2.e
-- npnG2.f
-- npn13G2.bR
-- npn13G2L.cR
-- npn13G2V.cR
-- Rsil.a
-- Rsil.c
-- Rsil.d
-- Rsil.e
-- Rppd.a
-- Rppd.b
-- Rppd.c
-- Rppd.d
-- Rppd.e
-- Rhi.b
-- Rhi.c
-- Rhi.d
-- Rhi.e
-- nmosi.b
-- nmosi.e1
-- nmosi.e2
-- Sdiod.a
-- Sdiod.b
-- Sdiod.c
-- Sdiod.d
-- Sdiod.e
-- Pad.eR
-- Pad.fR
-- Pad.gR
-- Pad.i
-- Padb.a
-- Padb.b
-- Padb.c
-- Padb.d
-- Padb.e
-- Padb.f
-- Padc.a
-- Padc.c
-- Padc.e
-- Padc.f
-- Seal.b
-- Seal.d
-- Seal.f
-- Seal.k
-- Seal.l
-- Seal.m
-- MIM.c
-- MIM.d
-- MIM.gR
-- Ant.a
-- Ant.b
-- Ant.c
-- Ant.d
-- Ant.e
-- Ant.f
-- Ant.g
-- LU.a
-- LU.b
-- LU.c
-- LU.c1
-- LU.d
-- LU.d1
-- Slt.b.M1
-- Slt.c.M1
-- Slt.e1
-- Slt.f.M1
-- Slt.b.M2
-- Slt.c.M2
-- Slt.f.M2
-- Slt.b.M3
-- Slt.c.M3
-- Slt.f.M3
-- Slt.b.M4
-- Slt.c.M4
-- Slt.f.M4
-- Slt.b.M5
-- Slt.c.M5
-- Slt.f.M5
-- Slt.g.M5
-- Slt.b.TM1
-- Slt.c.TM1
-- Slt.f.TM1
-- Slt.g.TM1
-- Slt.b.TM2
-- Slt.c.TM2
-- Slt.f.TM2
-- Slt.i.M1
-- Slt.i.M2
-- Slt.i.M3
-- Slt.i.M4
-- Slt.i.M5
-- Slt.i.TM1
-- Slt.i.TM2
-- NW.c1.dig
-- NW.e1.dig
-- Cnt.c.Digi
-- NW.c.SRAM
-- NW.d.SRAM
-- Act.c.SRAM
-- Gat.c.SRAM
-- pSD.g.SRAM
-- pSD.i.SRAM
-- Cnt.c.SRAM
-- Cnt.d.SRAM
-- Cnt.g2.SRAM
-- M1.c1.SRAM
-- M1.i.SRAM
-- M2.c1.SRAM
-- M3.c1.SRAM
-- M4.c1.SRAM
-- M5.c1.SRAM
-- V1.c1.SRAM
-- V2.c1.SRAM
-- V3.c1.SRAM
-- V4.c1.SRAM
-- TSV_G.a
-- TSV_G.b
-- TSV_G.c
-- TSV_G.d
-- TSV_G.e
-- TSV_G.f
-- TSV_G.g
-- TSV_G.i
-- TSV_G.j
+| Name        | Description                                                                                                                    |
+| ----------- | ------------------------------------------------------------------------------------------------------------------------------ |
+| NW.b        | Min. NWell space or notch (same net). NWell regions separated by less than this value will be merged.                          |
+| NW.b1       | Min. PWell width between NWell regions (different net) (Note 3)                                                                |
+| NW.c        | Min. NWell enclosure of P+Activ not inside ThickGateOx                                                                         |
+| NW.c1       | Min. NWell enclosure of P+Activ inside ThickGateOx                                                                             |
+| NW.d        | Min. NWell space to external N+Activ not inside ThickGateOx                                                                    |
+| NW.e        | Min. NWell enclosure of NWell tie surrounded entirely by NWell in N+Activ not inside ThickGateOx                               |
+| NW.e1       | Min. NWell enclosure of NWell tie surrounded entirely by NWell in N+Activ inside ThickGateOx                                   |
+| PWB.d       | Min. PWell:block overlap of NWell                                                                                              |
+| PWB.e       | Min. PWell:block space to (N+Activ not inside ThickGateOx) in PWell                                                            |
+| PWB.e1      | Min. PWell:block space to (N+Activ inside ThickGateOx) in PWell                                                                |
+| PWB.f       | Min. PWell:block space to (P+Activ not inside ThickGateOx) in PWell                                                            |
+| PWB.f1      | Min. PWell:block space to (P+Activ inside ThickGateOx) in PWell                                                                |
+| NBL.b       | Min. nBuLay space or notch (same net)                                                                                          |
+| NBL.c       | Min. PWell width between nBuLay regions (different net) (Note 1)                                                               |
+| NBL.d       | Min. PWell width between nBuLay and NWell (different net) (Note 1)                                                             |
+| NBL.e       | Min. nBuLay space to unrelated N+Activ                                                                                         |
+| NBL.f       | Min. nBuLay space to unrelated P+Activ                                                                                         |
+| Act.c       | Min. Activ drain/source extension                                                                                              |
+| AFil.c      | Min. Activ:filler space to Cont, GatPoly                                                                                       |
+| AFil.c1     | Min. Activ:filler space to Activ                                                                                               |
+| AFil.d      | Min. Activ:filler space to NWell, nBuLay                                                                                       |
+| AFil.e      | Min. Activ:filler space to TRANS                                                                                               |
+| AFil.i      | Min. Activ:filler space to edges of PWell:block                                                                                |
+| AFil.j      | Min. nSD:block and SalBlock enclosure of Activ:filler inside PWell:block                                                       |
+| Gat.a1      | Min. GatPoly width for channel length of 1.2 V NFET                                                                            |
+| Gat.a2      | Min. GatPoly width for channel length of 1.2 V PFET                                                                            |
+| Gat.g       | Min. GatPoly width for 45-degree bent shapes if the bend GatPoly length is > 0.39 µm                                           |
+| GFil.e      | Min. GatPoly:filler space to NWell, nBuLay                                                                                     |
+| GFil.i      | Max. GatPoly:nofill area (µm²)                                                                                                 |
+| pSD.c1      | Min. pSD enclosure of P+Activ in PWell                                                                                         |
+| nSDB.d      | Min. nSD:block overlap of pSD (Note 1)                                                                                         |
+| Cnt.c       | Min. Activ enclosure of Cont                                                                                                   |
+| Cnt.d       | Min. GatPoly enclosure of Cont                                                                                                 |
+| Cnt.e       | Min. Cont on GatPoly space to Activ                                                                                            |
+| Cnt.g1      | Min. pSD space to Cont on nSD-Activ                                                                                            |
+| Cnt.g2      | Min. pSD overlap of Cont on pSD-Activ                                                                                          |
+| CntB.b1     | Min. ContBar space with common run > 5 µm                                                                                      |
+| CntB.c      | Min. Activ enclosure of ContBar                                                                                                |
+| CntB.d      | Min. GatPoly enclosure of ContBar                                                                                              |
+| CntB.h1     | Min. Metal1 enclosure of ContBar                                                                                               |
+| M1.e        | Min. space of Metal1 lines if, at least one line is wider than 0.3 µm and the parallel run is more than 1.0 µm                 |
+| M1.f        | Min. space of Metal1 lines if, at least one line is wider than 10.0 µm and the parallel run is more than 10.0 µm               |
+| M1.g        | Min. 45-degree bent Metal1 width if the bent metal length is > 0.5 µm                                                          |
+| M1.i        | Min. space of Metal1 lines of which at least one is bent by 45-degree                                                          |
+| M2.e        | Min. space of Metal2 lines if, at least one line is wider than 0.39 µm and the parallel run is more than 1.0 µm                |
+| M2.f        | Min. space of Metal2 lines if, at least one line is wider than 10.0 µm and the parallel run is more than 10.0 µm               |
+| M2.g        | Min. 45-degree bent Metal2 width if the bent metal length is > 0.5 µm                                                          |
+| M2.i        | Min. space of Metal2 lines of which at least one is bent by 45-degree                                                          |
+| M3.e        | Min. space of Metal3 lines if, at least one line is wider than 0.39 µm and the parallel run is more than 1.0 µm                |
+| M3.f        | Min. space of Metal3 lines if, at least one line is wider than 10.0 µm and the parallel run is more than 10.0 µm               |
+| M3.g        | Min. 45-degree bent Metal3 width if the bent metal length is > 0.5 µm                                                          |
+| M3.i        | Min. space of Metal3 lines of which at least one is bent by 45-degree                                                          |
+| M4.e        | Min. space of Metal4 lines if, at least one line is wider than 0.39 µm and the parallel run is more than 1.0 µm                |
+| M4.f        | Min. space of Metal4 lines if, at least one line is wider than 10.0 µm and the parallel run is more than 10.0 µm               |
+| M4.g        | Min. 45-degree bent Metal4 width if the bent metal length is > 0.5 µm                                                          |
+| M4.i        | Min. space of Metal4 lines of which at least one is bent by 45-degree                                                          |
+| M5.e        | Min. space of Metal5 lines if, at least one line is wider than 0.39 µm and the parallel run is more than 1.0 µm                |
+| M5.f        | Min. space of Metal5 lines if, at least one line is wider than 10.0 µm and the parallel run is more than 10.0 µm               |
+| M5.g        | Min. 45-degree bent Metal5 width if the bent metal length is > 0.5 µm                                                          |
+| M5.i        | Min. space of Metal5 lines of which at least one is bent by 45-degree                                                          |
+| M1Fil.a2    | Max. Metal1:filler width                                                                                                       |
+| M2Fil.a2    | Max. Metal2:filler width                                                                                                       |
+| M3Fil.a2    | Max. Metal3:filler width                                                                                                       |
+| M4Fil.a2    | Max. Metal4:filler width                                                                                                       |
+| M5Fil.a2    | Max. Metal5:filler width                                                                                                       |
+| V1.c        | Min. Metal1 enclosure of Via1                                                                                                  |
+| V2.c        | Min. Metal2 enclosure of Via2                                                                                                  |
+| V3.c        | Min. Metal3 enclosure of Via3                                                                                                  |
+| V4.c        | Min. Metal4 enclosure of Via4                                                                                                  |
+| TV1.c       | Min. Metal5 enclosure of TopVia1                                                                                               |
+| TV1.d       | Min. TopMetal1 enclosure of TopVia1                                                                                            |
+| TM1Fil.a1   | Max. TopMetal1:filler width                                                                                                    |
+| TV2.c       | Min. TopMetal1 enclosure of TopVia2                                                                                            |
+| TV2.d       | Min. TopMetal2 enclosure of TopVia2                                                                                            |
+| TM2.bR      | Min. space of TopMetal2 lines if, at least one line is wider than 5.0 µm and the parallel run is more than 50.0 µm (Note 1, 2) |
+| TM2Fil.a1   | Max. TopMetal2:filler width                                                                                                    |
+| Pas.c       | Min. TopMetal2 enclosure of Passiv (Note 1)                                                                                    |
+| npnG2.a     | NPN Substrate-Tie = Activ AND pSD                                                                                              |
+| npnG2.b     | NPN Substrate-Tie must enclose TRANS                                                                                           |
+| npnG2.c     | pSD enclosure of Activ inside NPN Substrate-Tie                                                                                |
+| npnG2.d     | Min. unrelated N+Activ, NWell, PWell:block, nBuLay, nSD:block space to TRANS                                                   |
+| npnG2.d1    | Min. unrelated GatPoly space to TRANS                                                                                          |
+| npnG2.d2    | Min. unrelated SalBlock space to TRANS                                                                                         |
+| npnG2.e     | Min. unrelated Cont space to TRANS                                                                                             |
+| npnG2.f     | NPN Substrate-Ties are allowed to overlap each other                                                                           |
+| npn13G2.bR  | Max. recommended total number of npn13G2 emitters per chip                                                                     |
+| npn13G2L.cR | Max. recommended total number of npn13G2L emitters per chip                                                                    |
+| npn13G2V.cR | Max. recommended total number of npn13G2V emitters per chip                                                                    |
+| Rppd.d      | Min. EXTBlock enclosure of GatPoly                                                                                             |
+| Rhi.e       | Min. EXTBlock enclosure of GatPoly                                                                                             |
+| nmosi.e1    | A separate Iso-PWell contact unabutted to a nmosi device is not allowed                                                        |
+| nmosi.e2    | nmosi unabutted to an Iso-PWell-Activ tie is not allowed                                                                       |
+| Sdiod.d     | Min. and max. ContBar width inside nBuLay                                                                                      |
+| Sdiod.e     | Min. and max. ContBar length inside nBuLay                                                                                     |
+| Pad.eR      | Min. recommended Metal(n), TopMetal1, TopMetal2 exit width                                                                     |
+| Pad.fR      | Min. recommended Metal(n), TopMetal1, TopMetal2 exit length                                                                    |
+| Pad.i       | dfpad without TopMetal2 not allowed                                                                                            |
+| Padb.a      | SBumpPad size                                                                                                                  |
+| Padb.b      | Min. SBumpPad space                                                                                                            |
+| Padb.c      | Min. TopMetal2 (within dfpad) enclosure of SBumpPad                                                                            |
+| Padb.d      | Min. SBumpPad space to EdgeSeal                                                                                                |
+| Padb.e      | Min. SBumpPad pitch (Note 1)                                                                                                   |
+| Padb.f      | Allowed passivation opening shape (Note 1)                                                                                     |
+| Padc.a      | CuPillarPad size                                                                                                               |
+| Padc.c      | Min. TopMetal2 (within dfpad) enclosure of CuPillarPad                                                                         |
+| Padc.e      | Min. CuPillarPad pitch (Note 1)                                                                                                |
+| Padc.f      | Allowed passivation opening shape (Note 1)                                                                                     |
+| Seal.b      | Min. Activ space to EdgeSeal-Activ, EdgeSeal-pSD, EdgeSeal-Metal(n=1-5), EdgeSeal-TopMetal1, EdgeSeal-TopMetal2                |
+| Seal.d      | Min. EdgeSeal-Activ enclosure of EdgeSeal-Cont, EdgeSeal-Metal(n=1-5), EdgeSeal-TopMetal1, EdgeSeal-TopMetal2 ring             |
+| Seal.f      | Min. Passiv ring outside of sealring space to EdgeSeal-Activ, EdgeSeal-Metal(n=1-5), EdgeSeal-TopMetal1, EdgeSeal-TopMetal2    |
+| Seal.k      | Min. EdgeSeal 45-degree corner length (Note 1)                                                                                 |
+| Seal.l      | No structures outside sealring boundary allowed                                                                                |
+| Seal.m      | Only one sealring per chip allowed (Note 1)                                                                                    |
+| MIM.c       | Min. Metal5 enclosure of MIM                                                                                                   |
+| MIM.d       | Min. MIM enclosure of TopVia1                                                                                                  |
+| MIM.gR      | Max. recommended total MIM area per chip (µm²)                                                                                 |
+| Ant.a       | Max. ratio of GatPoly over field oxide area to connected Gate area                                                             |
+| Ant.b       | Max. ratio of cumulative metal area (from Metal1 to TopMetal2) to connected Gate area (without protection diode)               |
+| Ant.c       | Max. ratio of Cont area to connected Gate area                                                                                 |
+| Ant.d       | Max. ratio of cumulative via area (from Via1 to TopVia2) to connected Gate area (without protection diode)                     |
+| Ant.e       | Max. ratio of cumulative metal area (from Metal1 to TopMetal2) to connected Gate area (with protection diode)                  |
+| Ant.f       | Max. ratio of cumulative via area (from Via1 to TopVia2) to connected Gate area (with protection diode)                        |
+| Ant.g       | Size of protection diode (µm²) (Note 4)                                                                                        |
+| LU.b        | Max. space from any portion of N+Activ inside PWell to an pSD-PWell tie                                                        |
+| Slt.e1      | No slits required on MIM                                                                                                       |
+| Slt.i.M1    | Min. Metal1:slit density for any Metal1 plate bigger than 35 µm x 35 µm [%]                                                    |
+| Slt.i.M2    | Min. Metal2:slit density for any Metal2 plate bigger than 35 µm x 35 µm [%]                                                    |
+| Slt.i.M3    | Min. Metal3:slit density for any Metal3 plate bigger than 35 µm x 35 µm [%]                                                    |
+| Slt.i.M4    | Min. Metal4:slit density for any Metal4 plate bigger than 35 µm x 35 µm [%]                                                    |
+| Slt.i.M5    | Min. Metal5:slit density for any Metal5 plate bigger than 35 µm x 35 µm [%]                                                    |
+| Slt.i.TM1   | Min. TopMetal1:slit density for any TopMetal1 plate bigger than 35 µm x 35 µm [%]                                              |
+| Slt.i.TM2   | Min. TopMetal2:slit density for any TopMetal2 plate bigger than 35 µm x 35 µm [%]                                              |
+| NW.c1.dig   | Min. NWell enclosure of P+Activ inside ThickGateOx                                                                             |
+| NW.e1.dig   | Min. NWell enclosure of NWell tie surrounded entirely by NWell in N+Activ inside ThickGateOx                                   |
+| Cnt.c.Digi  | Min. Activ enclosure of Cont                                                                                                   |
+| NW.c.SRAM   | Min. NWell enclosure of P+Activ not inside ThickGateOx                                                                         |
+| NW.d.SRAM   | Min. NWell space to external N+Activ not inside ThickGateOx                                                                    |
+| Act.c.SRAM  | Min. Activ drain/source extension                                                                                              |
+| Cnt.c.SRAM  | Min. Activ enclosure of Cont                                                                                                   |
+| Cnt.d.SRAM  | Min. GatPoly enclosure of Cont                                                                                                 |
+| Cnt.g2.SRAM | Min. pSD overlap of Cont on pSD-Activ                                                                                          |
+| M1.i.SRAM   | Min. space of Metal1 lines of which at least one is bent by 45-degree                                                          |
+| V1.c1.SRAM  | Min. Metal1 endcap enclosure of Via1                                                                                           |
+| V2.c1.SRAM  | Min. Metal2 endcap enclosure of Via2                                                                                           |
+| V3.c1.SRAM  | Min. Metal3 endcap enclosure of Via3                                                                                           |
+| V4.c1.SRAM  | Min. Metal4 endcap enclosure of Via4                                                                                           |
+| TSV_G.b     | Min. and max. DeepVia width                                                                                                    |
+| TSV_G.c     | DeepVia ring diameter                                                                                                          |
+| TSV_G.e     | Min. DeepVia space to Activ, Activ:filler, GatPoly, GatPoly:filler and Cont                                                    |
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/drc/README.md b/ihp-sg13g2/libs.tech/klayout/tech/drc/README.md
index 18ae0ca6..9d80cad4 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/drc/README.md
+++ b/ihp-sg13g2/libs.tech/klayout/tech/drc/README.md
@@ -1,4 +1,2 @@
 **Minimum Rule Set** - [README](README_minimal.md)  
 **Maximum Rule Set** - [README](README_maximal.md), [MissingRules](MissingRules_maximal.md)  
-> **NOTE**: Starting with this version the rule names are extracted from the OpenPDK DRM PDF.
-> The extraction algorithm will be updated to include the 'values' in the next version of rule deck.
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/drc/README_maximal.md b/ihp-sg13g2/libs.tech/klayout/tech/drc/README_maximal.md
index 87999f0b..6730b15b 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/drc/README_maximal.md
+++ b/ihp-sg13g2/libs.tech/klayout/tech/drc/README_maximal.md
@@ -6,30 +6,41 @@ List of available DRC rules:
 | ------------------------ | --------------------------------------------------------------------------------------- |
 | NW.a                     | Min. NWell width                                                                        |
 | NW.d1                    | Min. NWell space to external N+Activ inside ThickGateOx                                 |
+| NW.f                     | Min. NWell space to substrate tie in P+Activ not inside ThickGateOx                     |
+| NW.f1                    | Min. NWell space to substrate tie in P+Activ inside ThickGateOx                         |
 | PWB.a                    | Min. PWell:block width                                                                  |
 | PWB.b                    | Min. PWell:block space or notch                                                         |
 | PWB.c                    | Min. PWell:block space to unrelated NWell                                               |
 | NBL.a                    | Min. nBuLay width                                                                       |
 | NBLB.a                   | Min. nBuLay:block width                                                                 |
 | NBLB.b                   | Min. nBuLay:block space or notch                                                        |
+| NBLB.c                   | Min. nBuLay enclosure of nBuLay:block                                                   |
 | NBLB.d                   | Min. nBuLay:block space to unrelated nBuLay                                             |
 | Act.a                    | Min. Activ width                                                                        |
 | Act.b                    | Min. Activ space or notch                                                               |
-| Act.d                    | Min. Activ area (�m�)                                                                   |
+| Act.d                    | Min. Activ area (µm²)                                                                   |
+| Act.e                    | Min. Activ enclosed area (µm²)                                                          |
 | AFil.a                   | Max. Activ:filler width                                                                 |
 | AFil.a1                  | Min. Activ:filler width                                                                 |
 | AFil.b                   | Min. Activ:filler space                                                                 |
 | AFil.g                   | Min. global Activ density [%]                                                           |
 | AFil.g1                  | Max. global Activ density [%]                                                           |
-| AFil.g2                  | Min. Activ coverage ratio for any 800 x 800 �m� chip area [%]                           |
-| AFil.g3                  | Max. Activ coverage ratio for any 800 x 800 �m� chip area [%]                           |
+| AFil.g2                  | Min. Activ coverage ratio for any 800 x 800 µm² chip area [%]                           |
+| AFil.g3                  | Max. Activ coverage ratio for any 800 x 800 µm² chip area [%]                           |
+| TGO.a                    | Min. ThickGateOx extension over Activ                                                   |
+| TGO.b                    | Min. space between ThickGateOx and Activ outside thick gate oxide region                |
+| TGO.c                    | Min. ThickGateOx extension over GatPoly over Activ                                      |
+| TGO.d                    | Min. space between ThickGateOx and GatPoly over Activ outside thick gate oxide region   |
 | TGO.e                    | Min. ThickGateOx space (merge if less than this value)                                  |
 | TGO.f                    | Min. ThickGateOx width                                                                  |
 | Gat.a                    | Min. GatPoly width                                                                      |
+| Gat.a3                   | Min. GatPoly width for channel length of 3.3 V NFET                                     |
+| Gat.a4                   | Min. GatPoly width for channel length of 3.3 V PFET                                     |
 | Gat.b                    | Min. GatPoly space or notch                                                             |
 | Gat.b1                   | Min. space between unrelated 3.3 V GatPoly over Activ regions                           |
+| Gat.c                    | Min. GatPoly extension over Activ (end cap)                                             |
 | Gat.d                    | Min. GatPoly space to Activ                                                             |
-| Gat.e                    | Min. GatPoly area (�m�)                                                                 |
+| Gat.e                    | Min. GatPoly area (µm²)                                                                 |
 | Gat.f                    | 45-degree and 90-degree angles for GatPoly on Activ area are not allowed                |
 | GFil.a                   | Max. GatPoly:filler width                                                               |
 | GFil.b                   | Min. GatPoly:filler width                                                               |
@@ -45,19 +56,30 @@ List of available DRC rules:
 | GFil.j                   | Min. GatPoly:filler extension over Activ:filler (end cap)                               |
 | pSD.a                    | Min. pSD width                                                                          |
 | pSD.b                    | Min. pSD space or notch (Note 1)                                                        |
+| pSD.c                    | Min. pSD enclosure of P+Activ in NWell                                                  |
 | pSD.d                    | Min. pSD space to unrelated N+Activ in PWell                                            |
 | pSD.d1                   | Min. pSD space to N+Activ in NWell                                                      |
 | pSD.e                    | Min. pSD overlap of Activ at one position when forming abutted substrate tie (Note 2)   |
+| pSD.f                    | Min. Activ extension over pSD at one position when forming abutted NWell tie (Note 2)   |
+| pSD.g                    | Min. N+Activ or P+Activ area (µm²) when forming abutted tie (Note 2)                    |
+| pSD.i                    | Min. pSD enclosure of PFET gate not inside ThickGateOx                                  |
+| pSD.i1                   | Min. pSD enclosure of PFET gate inside ThickGateOx                                      |
 | pSD.j                    | Min. pSD space to NFET gate not inside ThickGateOx                                      |
 | pSD.j1                   | Min. pSD space to NFET gate inside ThickGateOx                                          |
-| pSD.k                    | Min. pSD area (�m�)                                                                     |
+| pSD.k                    | Min. pSD area (µm²)                                                                     |
+| pSD.l                    | Min. pSD enclosed area (µm²)                                                            |
+| pSD.m                    | Min. pSD space to n-type poly resistors                                                 |
+| pSD.n                    | Min. pSD enclosure of p-type poly resistors                                             |
 | nSDB.a                   | Min. nSD:block width                                                                    |
 | nSDB.b                   | Min. nSD:block space or notch                                                           |
+| nSDB.c                   | Min. nSD:block space to unrelated pSD                                                   |
+| nSDB.e                   | Min. nSD:block space to Cont (Note 2)                                                   |
 | EXT.a                    | Min. EXTBlock width                                                                     |
 | EXT.b                    | Min. EXTBlock space or notch                                                            |
 | EXT.c                    | Min. EXTBlock space to pSD                                                              |
 | Sal.a                    | Min. SalBlock width                                                                     |
 | Sal.b                    | Min. SalBlock space or notch                                                            |
+| Sal.c                    | Min. SalBlock extension over Activ or GatPoly                                           |
 | Sal.d                    | Min. SalBlock space to unrelated Activ or GatPoly                                       |
 | Sal.e                    | Min. SalBlock space to Cont                                                             |
 | Cnt.a                    | Min. and max. Cont width                                                                |
@@ -67,6 +89,7 @@ List of available DRC rules:
 | Cnt.g                    | Cont must be within Activ or GatPoly                                                    |
 | Cnt.h                    | Cont must be covered with Metal1                                                        |
 | Cnt.j                    | Cont on GatPoly over Activ is not allowed                                               |
+| CntB.a                   | Min. and max. ContBar width                                                             |
 | CntB.a1                  | Min. ContBar length                                                                     |
 | CntB.b                   | Min. ContBar space                                                                      |
 | CntB.b2                  | Min. ContBar space to Cont                                                              |
@@ -74,76 +97,90 @@ List of available DRC rules:
 | CntB.f                   | Min. ContBar on Activ space to GatPoly                                                  |
 | CntB.g                   | ContBar must be within Activ or GatPoly                                                 |
 | CntB.g1                  | Min. pSD space to ContBar on nSD-Activ                                                  |
+| CntB.g2                  | Min. pSD overlap of ContBar on pSD-Activ                                                |
 | CntB.h                   | ContBar must be covered with Metal1                                                     |
 | CntB.j                   | ContBar on GatPoly over Activ is not allowed                                            |
 | M1.a                     | Min. Metal1 width                                                                       |
 | M1.b                     | Min. Metal1 space or notch                                                              |
 | M1.c                     | Min. Metal1 enclosure of Cont                                                           |
-| M1.d                     | Min. Metal1 area (�m�)                                                                  |
+| M1.c1                    | Min. Metal1 endcap enclosure of Cont (Note 1)                                           |
+| M1.d                     | Min. Metal1 area (µm²)                                                                  |
 | M1.j                     | Min. global Metal1 density [%]                                                          |
 | M1.k                     | Max. global Metal1 density [%]                                                          |
 | M2.a                     | Min. Metal2 width                                                                       |
 | M2.b                     | Min. Metal2 space or notch                                                              |
-| M2.d                     | Min. Metal2 area (�m�)                                                                  |
+| M2.c                     | Min. Metal2 enclosure of Via1                                                           |
+| M2.c1                    | Min. Metal2 endcap enclosure of Via1 (Note 1)                                           |
+| M2.d                     | Min. Metal2 area (µm²)                                                                  |
 | M2.j                     | Min. global Metal2 density [%]                                                          |
 | M2.k                     | Max. global Metal2 density [%]                                                          |
 | M3.a                     | Min. Metal3 width                                                                       |
 | M3.b                     | Min. Metal3 space or notch                                                              |
-| M3.d                     | Min. Metal3 area (�m�)                                                                  |
+| M3.c                     | Min. Metal3 enclosure of Via2                                                           |
+| M3.c1                    | Min. Metal3 endcap enclosure of Via2 (Note 1)                                           |
+| M3.d                     | Min. Metal3 area (µm²)                                                                  |
 | M3.j                     | Min. global Metal3 density [%]                                                          |
 | M3.k                     | Max. global Metal3 density [%]                                                          |
 | M4.a                     | Min. Metal4 width                                                                       |
 | M4.b                     | Min. Metal4 space or notch                                                              |
-| M4.d                     | Min. Metal4 area (�m�)                                                                  |
+| M4.c                     | Min. Metal4 enclosure of Via3                                                           |
+| M4.c1                    | Min. Metal4 endcap enclosure of Via3 (Note 1)                                           |
+| M4.d                     | Min. Metal4 area (µm²)                                                                  |
 | M4.j                     | Min. global Metal4 density [%]                                                          |
 | M4.k                     | Max. global Metal4 density [%]                                                          |
 | M5.a                     | Min. Metal5 width                                                                       |
 | M5.b                     | Min. Metal5 space or notch                                                              |
-| M5.d                     | Min. Metal5 area (�m�)                                                                  |
+| M5.c                     | Min. Metal5 enclosure of Via4                                                           |
+| M5.c1                    | Min. Metal5 endcap enclosure of Via4 (Note 1)                                           |
+| M5.d                     | Min. Metal5 area (µm²)                                                                  |
 | M5.j                     | Min. global Metal5 density [%]                                                          |
 | M5.k                     | Max. global Metal5 density [%]                                                          |
 | M1Fil.a1                 | Min. Metal1:filler width                                                                |
 | M1Fil.b                  | Min. Metal1:filler space                                                                |
 | M1Fil.c                  | Min. Metal1:filler space to Metal1                                                      |
 | M1Fil.d                  | Min. Metal1:filler space to TRANS                                                       |
-| M1Fil.h                  | Min. Metal1 and Metal1:filler coverage ratio for any 800 x 800 �m� chip area [%]        |
-| M1Fil.k                  | Max. Metal1 and Metal1:filler coverage ratio for any 800 x 800 �m� chip area [%]        |
+| M1Fil.h                  | Min. Metal1 and Metal1:filler coverage ratio for any 800 x 800 µm² chip area [%]        |
+| M1Fil.k                  | Max. Metal1 and Metal1:filler coverage ratio for any 800 x 800 µm² chip area [%]        |
 | M2Fil.a1                 | Min. Metal2:filler width                                                                |
 | M2Fil.b                  | Min. Metal2:filler space                                                                |
 | M2Fil.c                  | Min. Metal2:filler space to Metal2                                                      |
 | M2Fil.d                  | Min. Metal2:filler space to TRANS                                                       |
-| M2Fil.h                  | Min. Metal2 and Metal2:filler coverage ratio for any 800 x 800 �m� chip area [%]        |
-| M2Fil.k                  | Max. Metal2 and Metal2:filler coverage ratio for any 800 x 800 �m� chip area [%]        |
+| M2Fil.h                  | Min. Metal2 and Metal2:filler coverage ratio for any 800 x 800 µm² chip area [%]        |
+| M2Fil.k                  | Max. Metal2 and Metal2:filler coverage ratio for any 800 x 800 µm² chip area [%]        |
 | M3Fil.a1                 | Min. Metal3:filler width                                                                |
 | M3Fil.b                  | Min. Metal3:filler space                                                                |
 | M3Fil.c                  | Min. Metal3:filler space to Metal3                                                      |
 | M3Fil.d                  | Min. Metal3:filler space to TRANS                                                       |
-| M3Fil.h                  | Min. Metal3 and Metal3:filler coverage ratio for any 800 x 800 �m� chip area [%]        |
-| M3Fil.k                  | Max. Metal3 and Metal3:filler coverage ratio for any 800 x 800 �m� chip area [%]        |
+| M3Fil.h                  | Min. Metal3 and Metal3:filler coverage ratio for any 800 x 800 µm² chip area [%]        |
+| M3Fil.k                  | Max. Metal3 and Metal3:filler coverage ratio for any 800 x 800 µm² chip area [%]        |
 | M4Fil.a1                 | Min. Metal4:filler width                                                                |
 | M4Fil.b                  | Min. Metal4:filler space                                                                |
 | M4Fil.c                  | Min. Metal4:filler space to Metal4                                                      |
 | M4Fil.d                  | Min. Metal4:filler space to TRANS                                                       |
-| M4Fil.h                  | Min. Metal4 and Metal4:filler coverage ratio for any 800 x 800 �m� chip area [%]        |
-| M4Fil.k                  | Max. Metal4 and Metal4:filler coverage ratio for any 800 x 800 �m� chip area [%]        |
+| M4Fil.h                  | Min. Metal4 and Metal4:filler coverage ratio for any 800 x 800 µm² chip area [%]        |
+| M4Fil.k                  | Max. Metal4 and Metal4:filler coverage ratio for any 800 x 800 µm² chip area [%]        |
 | M5Fil.a1                 | Min. Metal5:filler width                                                                |
 | M5Fil.b                  | Min. Metal5:filler space                                                                |
 | M5Fil.c                  | Min. Metal5:filler space to Metal5                                                      |
 | M5Fil.d                  | Min. Metal5:filler space to TRANS                                                       |
-| M5Fil.h                  | Min. Metal5 and Metal5:filler coverage ratio for any 800 x 800 �m� chip area [%]        |
-| M5Fil.k                  | Max. Metal5 and Metal5:filler coverage ratio for any 800 x 800 �m� chip area [%]        |
+| M5Fil.h                  | Min. Metal5 and Metal5:filler coverage ratio for any 800 x 800 µm² chip area [%]        |
+| M5Fil.k                  | Max. Metal5 and Metal5:filler coverage ratio for any 800 x 800 µm² chip area [%]        |
 | V1.a                     | Min. and max. Via1 width                                                                |
 | V1.b                     | Min. Via1 space                                                                         |
 | V1.b1                    | Min. Via1 space in an array of more than 3 rows and more then 3 columns (Note 1)        |
+| V1.c1                    | Min. Metal1 endcap enclosure of Via1 (Note 2)                                           |
 | V2.a                     | Min. and max. Via2 width                                                                |
 | V2.b                     | Min. Via2 space                                                                         |
 | V2.b1                    | Min. Via2 space in an array of more than 3 rows and more then 3 columns (Note 1)        |
+| V2.c1                    | Min. Metal2 endcap enclosure of Via2 (Note 2)                                           |
 | V3.a                     | Min. and max. Via3 width                                                                |
 | V3.b                     | Min. Via3 space                                                                         |
 | V3.b1                    | Min. Via3 space in an array of more than 3 rows and more then 3 columns (Note 1)        |
+| V3.c1                    | Min. Metal3 endcap enclosure of Via3 (Note 2)                                           |
 | V4.a                     | Min. and max. Via4 width                                                                |
 | V4.b                     | Min. Via4 space                                                                         |
 | V4.b1                    | Min. Via4 space in an array of more than 3 rows and more then 3 columns (Note 1)        |
+| V4.c1                    | Min. Metal4 endcap enclosure of Via4 (Note 2)                                           |
 | TV1.a                    | Min. and max. TopVia1 width                                                             |
 | TV1.b                    | Min. TopVia1 space                                                                      |
 | TM1.a                    | Min. TopMetal1 width                                                                    |
@@ -171,20 +208,36 @@ List of available DRC rules:
 | npn13G2L.b               | Max. npn13G2L emitter length                                                            |
 | npn13G2V.a               | Min. npn13G2V emitter length                                                            |
 | npn13G2V.b               | Max. npn13G2V emitter length                                                            |
+| Rsil.a                   | Min. GatPoly width                                                                      |
 | Rsil.b                   | Min. RES space to Cont                                                                  |
+| Rsil.c                   | Min. RES extension over GatPoly                                                         |
+| Rsil.d                   | Min. pSD space to GatPoly                                                               |
+| Rsil.e                   | Min. EXTBlock enclosure of GatPoly                                                      |
 | Rsil.f                   | Min. RES length                                                                         |
+| Rppd.a                   | Min. GatPoly width                                                                      |
+| Rppd.b                   | Min. pSD enclosure of GatPoly                                                           |
+| Rppd.c                   | Min. and max. SalBlock space to Cont                                                    |
+| Rppd.e                   | Min. SalBlock length                                                                    |
 | Rhi.a                    | Min. GatPoly width                                                                      |
+| Rhi.b                    | pSD and nSD are identical (Note 1)                                                      |
+| Rhi.c                    | Min. pSD and nSD enclosure of GatPoly                                                   |
+| Rhi.d                    | Min. and max. SalBlock space to Cont                                                    |
 | Rhi.f                    | Min. SalBlock length                                                                    |
+| nmosi.b                  | Min. nBuLay enclosure of Iso-PWell-Activ (Note 1)                                       |
 | nmosi.c                  | Min. NWell space to Iso-PWell-Activ                                                     |
 | nmosi.d                  | Min. NWell-nBuLay width forming an unbroken ring around any Iso-PWell-Activ (Note 2)    |
 | nmosi.f                  | Min. nSD:block width to separate ptap in nmosi                                          |
 | nmosi.g                  | Min. SalBlock overlap of nSD:block over Activ                                           |
+| Sdiod.a                  | Min. and max. PWell:block enclosure of ContBar                                          |
+| Sdiod.b                  | Min. and max. nSD:block enclosure of ContBar                                            |
+| Sdiod.c                  | Min. and max. SalBlock enclosure of ContBar                                             |
 | Pad.aR                   | Min. recommended Pad width                                                              |
 | Pad.a1                   | Max. Pad width                                                                          |
 | Pad.bR                   | Min. recommended Pad space                                                              |
 | Pad.d                    | Min. Pad space to EdgeSeal                                                              |
 | Pad.dR                   | Min. recommended Pad to EdgeSeal space (Note 1)                                         |
 | Pad.d1R                  | Min. recommended Pad to Activ (inside chip area) space                                  |
+| Pad.gR                   | TopMetal1 (within dfpad) enclosure of TopVia2                                           |
 | Pad.jR                   | No devices under Pad allowed (Note 2)                                                   |
 | Pad.kR                   | TopVia2 under Pad not allowed (Note 3)                                                  |
 | Padc.b                   | Min. CuPillarPad space                                                                  |
@@ -209,29 +262,57 @@ List of available DRC rules:
 | MIM.a                    | Min. MIM width                                                                          |
 | MIM.b                    | Min. MIM space                                                                          |
 | MIM.e                    | Min. TopMetal1 space to MIM                                                             |
-| MIM.f                    | Min. MIM area per MIM device (�m�)                                                      |
-| MIM.g                    | Max. MIM area per MIM device (�m�)                                                      |
+| MIM.f                    | Min. MIM area per MIM device (µm²)                                                      |
+| MIM.g                    | Max. MIM area per MIM device (µm²)                                                      |
 | MIM.h                    | TopVia1 must be over MIM                                                                |
+| LU.a                     | Max. space from any portion of P+Activ inside NWell to an nSD-NWell tie                 |
+| LU.c                     | Max. extension of an abutted NWell tie beyond Cont                                      |
+| LU.c1                    | Max. extension of an abutted substrate tie beyond Cont                                  |
+| LU.d                     | Max. extension of NWell tie Activ tie beyond Cont                                       |
+| LU.d1                    | Max. extension of an substrate tie Activ beyond Cont                                    |
 | Slt.a.M1                 | Min. Metal1:slit width                                                                  |
+| Slt.b.M1                 | Max. Metal1:slit width                                                                  |
+| Slt.c.M1                 | Max. Metal1 width without requiring a slit                                              |
 | Slt.e.M1                 | No slits required on bond pads                                                          |
+| Slt.f.M1                 | Min. Metal1 enclosure of Metal1:slit                                                    |
 | Slt.h1                   | Min. Metal1:slit space to Cont and Via1                                                 |
 | Slt.a.M2                 | Min. Metal2:slit width                                                                  |
+| Slt.b.M2                 | Max. Metal2:slit width                                                                  |
+| Slt.c.M2                 | Max. Metal2 width without requiring a slit                                              |
 | Slt.e.M2                 | No slits required on bond pads                                                          |
+| Slt.f.M2                 | Min. Metal2 enclosure of Metal2:slit                                                    |
 | Slt.h2.M2                | Min. Metal2:slit space to Via1 and Via2                                                 |
 | Slt.a.M3                 | Min. Metal3:slit width                                                                  |
+| Slt.b.M3                 | Max. Metal3:slit width                                                                  |
+| Slt.c.M3                 | Max. Metal3 width without requiring a slit                                              |
 | Slt.e.M3                 | No slits required on bond pads                                                          |
+| Slt.f.M3                 | Min. Metal3 enclosure of Metal2:slit                                                    |
 | Slt.h2.M3                | Min. Metal3:slit space to Via2 and Via3                                                 |
 | Slt.a.M4                 | Min. Metal4:slit width                                                                  |
+| Slt.b.M4                 | Max. Metal4:slit width                                                                  |
+| Slt.c.M4                 | Max. Metal4 width without requiring a slit                                              |
 | Slt.e.M4                 | No slits required on bond pads                                                          |
+| Slt.f.M4                 | Min. Metal4 enclosure of Metal4:slit                                                    |
 | Slt.h2.M4                | Min. Metal4:slit space to Via3 and Via4                                                 |
 | Slt.a.M5                 | Min. Metal5:slit width                                                                  |
+| Slt.b.M5                 | Max. Metal5:slit width                                                                  |
+| Slt.c.M5                 | Max. Metal5 width without requiring a slit                                              |
 | Slt.e.M5                 | No slits required on bond pads                                                          |
+| Slt.f.M5                 | Min. Metal5 enclosure of Metal5:slit                                                    |
+| Slt.g.M5                 | Min. Metal5:slit and TopMetal1:slit space to MIM                                        |
 | Slt.h2.M5                | Min. Metal5:slit space to Via4 and Via5                                                 |
 | Slt.a.TM1                | Min. TopMetal1:slit width                                                               |
+| Slt.b.TM1                | Max. TopMetal1:slit width                                                               |
+| Slt.c.TM1                | Max. TopMetal1 width without requiring a slit                                           |
 | Slt.e.TM1                | No slits required on bond pads                                                          |
+| Slt.f.TM1                | Min. TopMetal1 enclosure of TopMetal1:slit                                              |
+| Slt.g.TM1                | Min. Metal5:slit and TopMetal1:slit space to MIM                                        |
 | Slt.h3                   | Min. TopMetal1:slit space to TopVia1 and TopVia2                                        |
 | Slt.a.TM2                | Min. TopMetal2:slit width                                                               |
+| Slt.b.TM2                | Max. TopMetal2:slit width                                                               |
+| Slt.c.TM2                | Max. TopMetal2 width without requiring a slit                                           |
 | Slt.e.TM2                | No slits required on bond pads                                                          |
+| Slt.f.TM2                | Min. TopMetal2 enclosure of TopMetal2:slit                                              |
 | Slt.h4                   | Min. TopMetal2:slit space to TopVia2                                                    |
 | Pin.a                    | Min. Activ enclosure of Activ:pin                                                       |
 | Pin.b                    | Min. GatPoly enclosure of GatPoly:pin                                                   |
@@ -246,19 +327,27 @@ List of available DRC rules:
 | NW.f1.dig                | Min. NWell space to substrate tie in P+Activ inside ThickGateOx                         |
 | Gat.a.SRAM               | Min. GatPoly width                                                                      |
 | Gat.b.SRAM               | Min. GatPoly space or notch                                                             |
+| Gat.c.SRAM               | Min. GatPoly extension over Activ (end cap)                                             |
 | Gat.d.SRAM               | Min. GatPoly space to Activ                                                             |
 | pSD.e.SRAM               | Min. pSD overlap of Activ when forming abutted substrate tie                            |
+| pSD.g.SRAM               | Min. N+Activ or P+Activ width when forming abutted tie                                  |
+| pSD.i.SRAM               | Min. pSD enclosure of PFET gate not inside ThickGateOx                                  |
 | pSD.j.SRAM               | Min. pSD space to NFET gate not inside ThickGateOx                                      |
 | Cnt.f.SRAM               | Min. Cont on Activ space to GatPoly                                                     |
 | M1.b.SRAM                | Min. Metal1 space or notch                                                              |
+| M1.c1.SRAM               | Min. Metal1 endcap enclosure of Cont                                                    |
 | M2.b.SRAM                | Min. Metal2 space or notch                                                              |
+| M2.c1.SRAM               | Min. Metal2 endcap enclosure of Via1                                                    |
 | M3.b.SRAM                | Min. Metal3 space or notch                                                              |
+| M3.c1.SRAM               | Min. Metal3 endcap enclosure of Via2                                                    |
 | M4.b.SRAM                | Min. Metal4 space or notch                                                              |
+| M4.c1.SRAM               | Min. Metal4 endcap enclosure of Via3                                                    |
 | M5.b.SRAM                | Min. Metal5 space or notch                                                              |
+| M5.c1.SRAM               | Min. Metal5 endcap enclosure of Via4                                                    |
 | LBE.a                    | Min. LBE width                                                                          |
 | LBE.b                    | Max. LBE width                                                                          |
-| LBE.b1                   | Max. LBE area (�m�)                                                                     |
-| LBE.b2                   | Min. LBE area (�m�)                                                                     |
+| LBE.b1                   | Max. LBE area (µm²)                                                                     |
+| LBE.b2                   | Min. LBE area (µm²)                                                                     |
 | LBE.c                    | Min. LBE space or notch                                                                 |
 | LBE.d                    | Min. LBE space to inner edge of EdgeSeal                                                |
 | LBE.e.dfPad              | Min. LBE space to dfpad and Passiv                                                      |
@@ -266,6 +355,12 @@ List of available DRC rules:
 | LBE.f                    | Min. LBE space to Activ                                                                 |
 | LBE.h                    | No LBE ring allowed                                                                     |
 | LBE.i                    | Max. global LBE density [%]                                                             |
+| TSV_G.a                  | DeepVia has to be a ring structure                                                      |
+| TSV_G.d                  | Min. DeepVia space                                                                      |
+| TSV_G.f                  | Min. PWell:block enclosure of DeepVia                                                   |
+| TSV_G.g                  | Min. Metal1 enclosure of DeepVia ring structure                                         |
+| TSV_G.i                  | Max. global DeepVia density [%]                                                         |
+| TSV_G.j                  | Max. DeepVia coverage ratio for any 500.0 x 500.0 µm² chip area [%]                     |
 | forbidden.BiWind         | Forbidden drawn layer BiWind on GDS layer 3/0                                           |
 | forbidden.PEmWind        | Forbidden drawn layer PEmWind on GDS layer 11/0                                         |
 | forbidden.BasPoly        | Forbidden drawn layer BasPoly on GDS layer 13/0                                         |
@@ -349,4 +444,4 @@ List of available DRC rules:
 | OffGrid.dfpad_sbump      | dfpad_sbump is off-grid                                                                 |
 | OffGrid.DeepVia          | DeepVia is off-grid                                                                     |
 | OffGrid.LBE              | LBE is off-grid                                                                         |
-| OffGrid.PolyRes          | PolyRes is off-grid                                                                     |
\ No newline at end of file
+| OffGrid.PolyRes          | PolyRes is off-grid                                                                     |
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/drc/sg13g2.lydrc b/ihp-sg13g2/libs.tech/klayout/tech/drc/sg13g2.lydrc
deleted file mode 100644
index 4238b0c0..00000000
--- a/ihp-sg13g2/libs.tech/klayout/tech/drc/sg13g2.lydrc
+++ /dev/null
@@ -1,766 +0,0 @@
-<?xml version='1.0' encoding='utf-8'?>
-<!--
- Copyright 2023 IHP PDK Authors
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
-     https://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
--->
-<klayout-macro>
- <description />
- <version />
- <category>drc</category>
- <prolog />
- <epilog />
- <doc />
- <autorun>false</autorun>
- <autorun-early>false</autorun-early>
- <shortcut />
- <show-in-menu>true</show-in-menu>
- <group-name>drc_scripts</group-name>
- <menu-path>tools_menu.drc.end</menu-path>
- <interpreter>dsl</interpreter>
- <dsl-interpreter-name>drc-dsl-xml</dsl-interpreter-name>
- <text>
-application = RBA::Application.instance
-main_window = application.main_window
-if main_window
-    curr_layout_view = main_window.current_view()
-    unless curr_layout_view
-        layout_path = RBA::FileDialog::ask_open_file_name("Chose your layout file.", ".", "GDSII files (*.GDS *.gds *.GDS.gz *.gds.gz *.GDS2 *.gds2 *.GDS2.gz *.gds2.gz);; All files (*)")
-        main_window.load_layout(layout_path, 1)
-        curr_layout_view = main_window.current_view()
-    end
-    active_cellname = RBA::CellView::active.cell_name
-else
-    puts "DRC: batch mode"
-    if $cell
-        active_cellname = $cell
-        puts "Active cell: " + active_cellname
-    else
-        raise("ERROR: 'cell' script variable must be defined on cmd line")
-    end
-end
-active_layout = RBA::CellView::active.layout
-
-source(active_layout, active_cellname)
-if active_layout.dbu != 0.001
-    puts "WARNING: Layout dbu value (" + active_layout.dbu.to_s + " ) deviates from rule file dbu value (0.001). This will scale the layout and may not be intended."
-end
-report("design rules: sg13g2 | layout cell: " + active_cellname, "sg13g2_#{active_cellname}.lyrdb", active_cellname)
-
-deep
-
-# Initial definitions of control flow variables
-conditional_enabled = {}
-conditional_enabled[:density] = true
-conditional_enabled[:sanityRules] = true
-
-class DRC::DRCLayer
-    def ext_and(other)
-        self_min_coherence_state = self.data.min_coherence?
-        other_min_coherence_state =  other.data.min_coherence?
-        self.data.min_coherence = true
-        other.data.min_coherence = true
-        output_layer = self &amp; other
-        self.data.min_coherence = self_min_coherence_state
-        other.data.min_coherence = other_min_coherence_state
-        return output_layer
-    end
-
-    def ext_area(constraint)
-        output_layer = self.dup
-        constraint.each do |expression|
-            output_layer.data.min_coherence = true
-            relation = expression[0]
-            value = expression[1].to_i
-            if relation == "&gt;"
-                output_layer = output_layer.with_area((value + 1), nil)
-            elsif relation == "&lt;"
-                output_layer = output_layer.with_area(nil, value)
-            elsif relation == "=="
-                output_layer = output_layer.with_area(value)
-            elsif relation == "!="
-                output_layer = output_layer.without_area(value)
-            elsif relation == "&gt;="
-                output_layer = output_layer.with_area(value, nil)
-            elsif relation == "&lt;="
-                output_layer = output_layer.with_area(nil, (value + 1))
-            else
-                raise "invalid expression"
-            end
-        end
-        return output_layer
-    end
-
-    def ext_constraint_satisfied(value, constraint)
-        output_bool = true
-        constraint.each do |expression|
-            if expression[0] == "&gt;"
-                output_bool = output_bool &amp;&amp; (value &gt; expression[1])
-            elsif expression[0] == "&lt;"
-                output_bool = output_bool &amp;&amp; (value &lt; expression[1])
-            elsif expression[0] == "=="
-                output_bool = output_bool &amp;&amp; (value == expression[1])
-            elsif expression[0] == "!="
-               output_bool = output_bool &amp;&amp; (value != expression[1])
-            elsif expression[0] == "&gt;="
-                output_bool = output_bool &amp;&amp; (value &gt;= expression[1])
-            elsif expression[0] == "&lt;="
-                output_bool = output_bool &amp;&amp; (value &lt;= expression[1])
-            else
-                raise "invalid expression"
-            end
-        end
-        return output_bool
-    end
-
-    def ext_covering(other)
-        self_min_coherence_state = self.data.min_coherence?
-        other_min_coherence_state =  other.data.min_coherence?
-        self.data.min_coherence = true
-        other.data.min_coherence = true
-        output_layer = self.covering(other.inside(self))
-        self.data.min_coherence = self_min_coherence_state
-        other.data.min_coherence = other_min_coherence_state
-        return output_layer
-    end
-
-    def ext_not(other)
-        self_min_coherence_state = self.data.min_coherence?
-        other_min_coherence_state =  other.data.min_coherence?
-        self.data.min_coherence = true
-        other.data.min_coherence = true
-        output_layer = self - other
-        self.data.min_coherence = self_min_coherence_state
-        other.data.min_coherence = other_min_coherence_state
-        return output_layer
-    end
-
-    def ext_or(other)
-        self_min_coherence_state = self.data.min_coherence?
-        other_min_coherence_state =  other.data.min_coherence?
-        self.data.min_coherence = true
-        other.data.min_coherence = true
-        output_layer = self | other
-        self.data.min_coherence = self_min_coherence_state
-        other.data.min_coherence = other_min_coherence_state
-        return output_layer
-    end
-
-    def ext_rectangles(axis_aligned = false, use_bbox = false, constraint1 = nil, constraint2 = nil, aspect_ratio_constraint = nil, inverted: false)
-        self_min_coherence_state = self.data.min_coherence?
-        self.data.min_coherence = true
-        if ( ( constraint1 &amp;&amp; ( !constraint2 || constraint1.length() &gt; 1 || constraint1[0][0] != "==") ) ||
-             ( constraint2 &amp;&amp; ( constraint2.length() &gt; 1 || constraint2[0][0] != "==" ) ) ||
-             ( constraint1 &amp;&amp; constraint2 &amp;&amp; constraint1[0][1] != constraint2[0][1] ) )
-            raise "ext_rectangle: unsupported options"
-        end
-        square = constraint1 ? true : false
-        shape_filter =
-            if use_bbox
-                @engine.extents
-            elsif axis_aligned
-                @engine.rectangles
-            else
-                @engine.if_all((@engine.corners == 270).count == 4, @engine.corners.count == 4)
-            end
-        if square
-            if use_bbox
-                shape_filter = @engine.if_all((@engine.extents.length == constraint1[0][1]).count == 4)
-            else
-                square_filter = (@engine.length == constraint1[0][1]).count == 4
-                shape_filter = @engine.if_all(shape_filter, square_filter)
-            end
-        end
-        if inverted
-            output_layer = self.drc(! shape_filter)
-        else
-            output_layer = self.drc(shape_filter)
-        end
-        self.data.min_coherence = self_min_coherence_state
-        return output_layer
-    end
-
-    def ext_ring
-        holes = self.holes
-        hulls = self.hulls
-        covering = hulls.covering(holes)
-        result = covering.and(self)
-        return result
-    end
-
-    def ext_interacting_with_text(text_layer_number, text)
-        text_layer = @engine.labels(text_layer_number)
-        initial_merged_semantics = self.data.merged_semantics?
-        self.data.merged_semantics = false
-        result = self.interacting(text_layer.texts(text))
-        self.data.merged_semantics = initial_merged_semantics
-        return result
-    end
-
-    def ext_with_density(range, *args)
-        if self.is_empty?
-            return DRC::DRCLayer::new(@engine, RBA::Region::new())
-        end
-        origin = 'cc'
-        tile_size = nil
-        tile_step = nil
-        arguments = [range]
-        args.each do |a|
-            if a.is_a?(DRC::DRCTileSize)
-                tile_size = a
-                arguments.push(tile_size)
-            elsif a.is_a?(DRC::DRCTileStep)
-                tile_step = a
-                arguments.push(tile_step)
-            elsif a.is_a?(String)
-                origin = a
-            else
-                raise "argument error"
-            end
-        end
-        bbox = @engine.extent.bbox
-        if origin == 'll'
-            origin_x = bbox.left
-            origin_y = bbox.bottom
-            tile_origin = DRC::DRCTileOrigin::new(origin_x, origin_y)
-            arguments.push(tile_origin)
-        elsif origin != 'cc'
-            raise "Unkown origin: 'cc' or 'll' expected"
-        end
-        if tile_size
-            return self.with_density(*arguments)
-        else
-            tile_size = DRC::DRCTileSize::new(bbox.width, bbox.height)
-            tile_count = DRC::DRCTileCount::new(1,2)
-            enlarged_bbox = bbox.enlarged(1.1).to_itype(@engine.dbu)
-            boundary_layer = DRC::DRCLayer::new(@engine, RBA::Region::new(enlarged_bbox))
-            tile_boundary = DRC::DRCTileBoundary::new(boundary_layer)
-            result = self.with_density(*arguments, tile_size, tile_count, tile_boundary)
-            return result.raw.overlapping(DRC::DRCLayer::new(@engine, RBA::Region::new(bbox.to_itype(@engine.dbu))))
-        end
-    end
-end
-NWell_org = source.polygons("31/0")
-NWell_pin_org = source.polygons("31/2")
-Activ_org = source.polygons("1/0")
-Activ_pin_org = source.polygons("1/2")
-Activ_filler_org = source.polygons("1/22")
-ThickGateOx_org = source.polygons("44/0")
-GatPoly_org = source.polygons("5/0")
-GatPoly_pin_org = source.polygons("5/2")
-GatPoly_filler_org = source.polygons("5/22")
-Cont_org = source.polygons("6/0")
-Metal1_org = source.polygons("8/0")
-Metal1_pin_org = source.polygons("8/2")
-Metal1_filler_org = source.polygons("8/22")
-Metal1_slit_org = source.polygons("8/24")
-Via1_org = source.polygons("19/0")
-Metal2_org = source.polygons("10/0")
-Metal2_pin_org = source.polygons("10/2")
-Metal2_filler_org = source.polygons("10/22")
-Metal2_slit_org = source.polygons("10/24")
-Via2_org = source.polygons("29/0")
-Metal3_org = source.polygons("30/0")
-Metal3_pin_org = source.polygons("30/2")
-Metal3_filler_org = source.polygons("30/22")
-Metal3_slit_org = source.polygons("30/24")
-Via3_org = source.polygons("49/0")
-Metal4_org = source.polygons("50/0")
-Metal4_pin_org = source.polygons("50/2")
-Metal4_filler_org = source.polygons("50/22")
-Metal4_slit_org = source.polygons("50/24")
-Via4_org = source.polygons("66/0")
-Metal5_org = source.polygons("67/0")
-Metal5_pin_org = source.polygons("67/2")
-Metal5_filler_org = source.polygons("67/22")
-Metal5_slit_org = source.polygons("67/24")
-TopVia1_org = source.polygons("125/0")
-TopMetal1_org = source.polygons("126/0")
-TopMetal1_pin_org = source.polygons("126/2")
-TopMetal1_filler_org = source.polygons("126/22")
-TopMetal1_slit_org = source.polygons("126/24")
-Vmim_org = source.polygons("129/0")
-TopVia2_org = source.polygons("133/0")
-TopMetal2_org = source.polygons("134/0")
-TopMetal2_pin_org = source.polygons("134/2")
-TopMetal2_filler_org = source.polygons("134/22")
-TopMetal2_slit_org = source.polygons("134/24")
-Passiv_org = source.polygons("9/0")
-EdgeSeal_org = source.polygons("39/0")
-BiWind_org = source.polygons("3/0")
-PEmWind_org = source.polygons("11/0")
-BasPoly_org = source.polygons("13/0")
-DeepCo_org = source.polygons("35/0")
-PEmPoly_org = source.polygons("53/0", "70/0")
-EmPoly_org = source.polygons("55/0")
-LDMOS_org = source.polygons("57/0")
-PBiWind_org = source.polygons("58/0")
-Flash_org = source.polygons("71/0")
-ColWind_org = source.polygons("139/0")
-SRAM_org = source.polygons("25/0")
-TRANS_org = source.polygons("26/0")
-NoDRC = source.polygons("62/0")
-LBE_org = source.polygons("157/0")
-NWell = NWell_org.ext_not(NoDRC)
-Activ = Activ_org.ext_not(NoDRC)
-ThickGateOx = ThickGateOx_org.ext_not(NoDRC)
-GatPoly = GatPoly_org.ext_not(NoDRC)
-Cont = Cont_org.ext_not(NoDRC)
-ActFiller = Activ_filler_org.ext_not(NoDRC)
-GatFiller = GatPoly_filler_org.ext_not(NoDRC)
-Activ_pin = Activ_pin_org.ext_not(NoDRC)
-GatPoly_pin = GatPoly_pin_org.ext_not(NoDRC)
-NWell_pin = NWell_pin_org.ext_not(NoDRC)
-Metal1 = Metal1_org.ext_not(NoDRC)
-Via1 = Via1_org.ext_not(NoDRC)
-Metal2 = Metal2_org.ext_not(NoDRC)
-Via2 = Via2_org.ext_not(NoDRC)
-Metal3 = Metal3_org.ext_not(NoDRC)
-Via3 = Via3_org.ext_not(NoDRC)
-Metal4 = Metal4_org.ext_not(NoDRC)
-Via4 = Via4_org.ext_not(NoDRC)
-Metal5 = Metal5_org.ext_not(NoDRC)
-Vmim = Vmim_org.ext_not(NoDRC)
-TopMetal1 = TopMetal1_org.ext_not(NoDRC)
-TopVia2 = TopVia2_org.ext_not(NoDRC)
-TopMetal2 = TopMetal2_org.ext_not(NoDRC)
-Passiv = Passiv_org.ext_not(NoDRC)
-EdgeSeal = EdgeSeal_org.ext_not(NoDRC)
-M1Filler = Metal1_filler_org.ext_not(NoDRC)
-M2Filler = Metal2_filler_org.ext_not(NoDRC)
-M3Filler = Metal3_filler_org.ext_not(NoDRC)
-M4Filler = Metal4_filler_org.ext_not(NoDRC)
-M5Filler = Metal5_filler_org.ext_not(NoDRC)
-TopMet1Filler = TopMetal1_filler_org.ext_not(NoDRC)
-TopMet2Filler = TopMetal2_filler_org.ext_not(NoDRC)
-M1Slit = Metal1_slit_org.ext_not(NoDRC)
-M2Slit = Metal2_slit_org.ext_not(NoDRC)
-M3Slit = Metal3_slit_org.ext_not(NoDRC)
-M4Slit = Metal4_slit_org.ext_not(NoDRC)
-M5Slit = Metal5_slit_org.ext_not(NoDRC)
-TopMet1Slit = TopMetal1_slit_org.ext_not(NoDRC)
-TopMet2Slit = TopMetal2_slit_org.ext_not(NoDRC)
-Metal1_pin = Metal1_pin_org.ext_not(NoDRC)
-Metal2_pin = Metal2_pin_org.ext_not(NoDRC)
-Metal3_pin = Metal3_pin_org.ext_not(NoDRC)
-Metal4_pin = Metal4_pin_org.ext_not(NoDRC)
-Metal5_pin = Metal5_pin_org.ext_not(NoDRC)
-TopMetal1_pin = TopMetal1_pin_org.ext_not(NoDRC)
-TopMetal2_pin = TopMetal2_pin_org.ext_not(NoDRC)
-TRANS = TRANS_org.ext_not(NoDRC)
-SRAM = SRAM_org.ext_not(NoDRC)
-LBE = LBE_org.ext_not(NoDRC)
-TopVia1 = NoDRC.ext_or(Vmim_org).ext_or(TopVia1_org.ext_not(NoDRC))
-Activ_Act_a = Activ.width(150)
-ThickGateOx_TGO_f = ThickGateOx.width(860)
-Cont_SQ = Cont.ext_rectangles(true, false, [["==", 160]], [["==", 160]], nil)
-ContBar = Cont.ext_area([["&gt;", (0.16*0.16)*1000.0*1000.0]])
-Act_density = ActFiller.ext_or(Activ)
-Gat_density = GatFiller.ext_or(GatPoly)
-Act_Nsram = Activ.ext_not(SRAM)
-GP_Nsram = GatPoly.ext_not(SRAM)
-M1_Nsram = Metal1.ext_not(SRAM)
-M2_Nsram = Metal2.ext_not(SRAM)
-M3_Nsram = Metal3.ext_not(SRAM)
-M4_Nsram = Metal4.ext_not(SRAM)
-M5_Nsram = Metal5.ext_not(SRAM)
-M1_density = M1Filler.ext_or(Metal1).ext_not(M1Slit)
-M2_density = M2Filler.ext_or(Metal2).ext_not(M2Slit)
-M3_density = M3Filler.ext_or(Metal3).ext_not(M3Slit)
-M4_density = M4Filler.ext_or(Metal4).ext_not(M4Slit)
-M5_density = M5Filler.ext_or(Metal5).ext_not(M5Slit)
-TM1_density = TopMet1Filler.ext_or(TopMetal1).ext_not(TopMet1Slit)
-TM2_density = TopMet2Filler.ext_or(TopMetal2).ext_not(TopMet2Slit)
-emi2Pin = Metal2_pin.ext_and(TRANS).ext_interacting_with_text(63, "E")
-GP_Nsram_Gat_a = GP_Nsram.width(130)
-GP_Nsram_Gat_b = GP_Nsram.space(180)
-transG2L = TRANS.ext_interacting_with_text(63, "npn13G2L").ext_covering(emi2Pin)
-
--&gt; do
-    Activ_Act_a.dup
-end.().output("Act.a", "Min. Activ width = 0.15")
-
--&gt; do
-    Act_Nsram.space(210)
-end.().output("Act.b", "Act.b: Min. Activ space or notch = 0.21")
-
--&gt; do
-    ThickGateOx_TGO_f.dup
-end.().output("TGO.f", "Min. ThickGateOx width = 0.86")
-
--&gt; do
-    GP_Nsram_Gat_a.dup
-end.().output("Gat.a", "Min GatPoly width = 0.13")
-
--&gt; do
-    GP_Nsram_Gat_b.dup
-end.().output("Gat.b", "Min. GatPoly space or notch = 0.18")
-
--&gt; do
-    GP_Nsram.separation(Act_Nsram, 70)
-end.().output("Gat.d", "Min. GatPoly to Activ space = 0.07")
-
--&gt; do
-    Cont.merged(true, 0).outside(EdgeSeal).ext_not(ContBar.ext_or(Cont_SQ))
-end.().output("Cnt.a", "Min.and max. size of Cont = 0.16")
-
--&gt; do
-    Cont.merged(true, 0).outside(EdgeSeal).space(180)
-end.().output("Cnt.b", "Min. Cont space = 0.18")
-
--&gt; do
-    Passiv.width(2100)
-end.().output("Pas.a", "Min. Passiv width = 2.10")
-
--&gt; do
-    Passiv.space(3500)
-end.().output("Pas.b", "Min. Passiv space or notch = 3.50")
-
--&gt; do
-    Metal1.width(160)
-end.().output("M1.a", "Min. width of Metal1 = 0.16")
-
--&gt; do
-    M1_Nsram.space(180)
-end.().output("M1.b", "Min. Metal1 space or notch = 0.18")
-
--&gt; do
-    Metal2.width(200)
-end.().output("M2.a", "Min. width of Metal2 = 0.2")
-
--&gt; do
-    M2_Nsram.space(210)
-end.().output("M2.b", "Min. Metal2 space or notch = 0.21")
-
--&gt; do
-    Metal3.width(200)
-end.().output("M3.a", "Min. width of Metal3 = 0.2")
-
--&gt; do
-    M3_Nsram.space(210)
-end.().output("M3.b", "Min. Metal3 space or notch = 0.21")
-
--&gt; do
-    Metal4.width(200)
-end.().output("M4.a", "Min. width of Metal4 = 0.2")
-
--&gt; do
-    M4_Nsram.space(210)
-end.().output("M4.b", "Min. Metal4 space or notch = 0.21")
-
--&gt; do
-    Metal5.width(200)
-end.().output("M5.a", "Min. width of Metal5 = 0.2")
-
--&gt; do
-    M5_Nsram.space(210)
-end.().output("M5.b", "Min. Metal5 space or notch = 0.21")
-
--&gt; do
-    Via1.ext_not(EdgeSeal).merged(true, 0).outside(transG2L).ext_rectangles(false, false, [["==", 190]], [["==", 190]], nil, inverted: true)
-end.().output("Via1.a", "Via1.a: Min. and Maxi. size of Via1 = 0.19")
-
--&gt; do
-    Via1.ext_not(EdgeSeal).space(220)
-end.().output("Via1.b", "Via1.b: Min. Via1 space = 0.22")
-
--&gt; do
-    Via2.ext_not(EdgeSeal).merged(true, 0).outside(transG2L).ext_rectangles(false, false, [["==", 190]], [["==", 190]], nil, inverted: true)
-end.().output("Via2.a", "Via2.a: Min. and Maxi. size of Via2 = 0.19")
-
--&gt; do
-    Via2.ext_not(EdgeSeal).space(220)
-end.().output("Via2.b", "Via2.b: Min. Via2 space = 0.22")
-
--&gt; do
-    Via3.ext_not(EdgeSeal).merged(true, 0).outside(transG2L).ext_rectangles(false, false, [["==", 190]], [["==", 190]], nil, inverted: true)
-end.().output("Via3.a", "Via3.a: Min. and Maxi. size of Via3 = 0.19")
-
--&gt; do
-    Via3.ext_not(EdgeSeal).space(220)
-end.().output("Via3.b", "Via3.b: Min. Via3 space = 0.22")
-
--&gt; do
-    Via4.ext_not(EdgeSeal).merged(true, 0).outside(transG2L).ext_rectangles(false, false, [["==", 190]], [["==", 190]], nil, inverted: true)
-end.().output("Via4.a", "Via4.a: Min. and Maxi. size of Via4 = 0.19")
-
--&gt; do
-    Via4.ext_not(EdgeSeal).space(220)
-end.().output("Via4.b", "Via4.b: Min. Via4 space = 0.22")
-
--&gt; do
-    Vmim.ext_or(TopVia1.ext_not(EdgeSeal)).ext_rectangles(false, false, [["==", 420]], [["==", 420]], nil, inverted: true)
-end.().output("TV1.a", "Min.and Max. TopVia1 (µm²) = 0.42")
-
--&gt; do
-    TopVia1.ext_or(Vmim).space(420)
-end.().output("TV1.b", "Min. TopVia1 space = 0.42")
-
--&gt; do
-    TopMetal1.width(1640)
-end.().output("TM1.a", "Min. width of TopMetal1 = 1.64")
-
--&gt; do
-    TopMetal1.space(1640)
-end.().output("TM1.b", "Min. TopMetal1 space or notch = 1.64")
-
--&gt; do
-    TopMetal2.width(2000)
-end.().output("TM2.a", "Min. width of TopMetal2 = 2.0")
-
--&gt; do
-    TopMetal2.space(2000)
-end.().output("TM2.b", "Min. TopMetal2 space or notch = 2.0")
-
--&gt; do
-    TopVia2.ext_not(EdgeSeal).ext_rectangles(false, false, [["==", 900]], [["==", 900]], nil, inverted: true)
-end.().output("TV2.a", "Min.and Max. TopVia2 = 0.90")
-
--&gt; do
-    TopVia2.space(1060)
-end.().output("TV2.b", "Min. TopVia2 space = 1.06")
-
-if conditional_enabled[:density]
-	
-	-&gt; do
-	    Act_density.ext_with_density(0.0 .. 0.35, 'll')
-	end.().output("aFil.g", "Min. global Activ coverage = 35.0 %")
-	
-	-&gt; do
-	    Act_density.ext_with_density(0.55 .. 1.0, 'll')
-	end.().output("aFil.g1", "Max. global Activ coverage = 55.0 %")
-	
-	-&gt; do
-	    Act_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0), tile_step(400.0))
-	end.().output("aFil.g2", "Min. Active coverage ratio for any 800 x 800 µm² chip area = 25.0 %")
-	
-	-&gt; do
-	    Act_density.ext_with_density(0.65 .. 1.0, 'll', tile_size(800.0), tile_step(400.0))
-	end.().output("aFil.g3", "Max. Active coverage ratio for any 800 x 800 µm² chip area = 65.0 %")
-	
-	-&gt; do
-	    Gat_density.ext_with_density(0.0 .. 0.15, 'll')
-	end.().output("GFil.g", "Min. global GatPoly density [%] = 15.0")
-	
-	-&gt; do
-	    M1_density.ext_with_density(0.0 .. 0.35, 'll')
-	end.().output("M1.j", "Min. global Metal1 density [%] = 35.0")
-	
-	-&gt; do
-	    M1_density.ext_with_density(0.6 .. 1.0, 'll')
-	end.().output("M1.k", "Max. global Metal1 density [%] = 60.0")
-	
-	-&gt; do
-	    M2_density.ext_with_density(0.0 .. 0.35, 'll')
-	end.().output("M2.j", "Min. global Metal2 density [%] = 35.0")
-	
-	-&gt; do
-	    M2_density.ext_with_density(0.6 .. 1.0, 'll')
-	end.().output("M2.k", "Max. global Metal2 density [%] = 60.0")
-	
-	-&gt; do
-	    M3_density.ext_with_density(0.0 .. 0.35, 'll')
-	end.().output("M3.j", "Min. global Metal3 density [%] = 35.0")
-	
-	-&gt; do
-	    M3_density.ext_with_density(0.6 .. 1.0, 'll')
-	end.().output("M3.k", "Max. global Metal3 density [%] = 60.0")
-	
-	-&gt; do
-	    M4_density.ext_with_density(0.0 .. 0.35, 'll')
-	end.().output("M4.j", "Min. global Metal4 density [%] = 35.0")
-	
-	-&gt; do
-	    M4_density.ext_with_density(0.6 .. 1.0, 'll')
-	end.().output("M4.k", "Max. global Metal4 density [%] = 60.0")
-	
-	-&gt; do
-	    M5_density.ext_with_density(0.0 .. 0.35, 'll')
-	end.().output("M5.j", "Min. global Metal5 density [%] = 35.0")
-	
-	-&gt; do
-	    M5_density.ext_with_density(0.6 .. 1.0, 'll')
-	end.().output("M5.k", "Max. global Metal5 density [%] = 60.0")
-	
-	-&gt; do
-	    M1_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0), tile_step(400.0))
-	end.().output("M1Fil.h", "Min. Metal coverage MM1Filler ratio for any 800 x 800 µm² chip area [%] = 25.0")
-	
-	-&gt; do
-	    M1_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0), tile_step(400.0))
-	end.().output("M1Fil.k", "Max. Metal coverage MM1Filler ratio for any 800 x 800 µm² chip area [%] = 75.0")
-	
-	-&gt; do
-	    M2_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0), tile_step(400.0))
-	end.().output("M2Fil.h", "Min. Metal coverage MM2Filler ratio for any 800 x 800 µm² chip area [%] = 25.0")
-	
-	-&gt; do
-	    M2_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0), tile_step(400.0))
-	end.().output("M2Fil.k", "Max. Metal coverage MM2Filler ratio for any 800 x 800 µm² chip area [%] = 75.0")
-	
-	-&gt; do
-	    M3_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0), tile_step(400.0))
-	end.().output("M3Fil.h", "Min. Metal coverage MM3Filler ratio for any 800 x 800 µm² chip area [%] = 25.0")
-	
-	-&gt; do
-	    M3_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0), tile_step(400.0))
-	end.().output("M3Fil.k", "Max. Metal coverage MM3Filler ratio for any 800 x 800 µm² chip area [%] = 75.0")
-	
-	-&gt; do
-	    M4_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0), tile_step(400.0))
-	end.().output("M4Fil.h", "Min. Metal coverage MM4Filler ratio for any 800 x 800 µm² chip area [%] = 25.0")
-	
-	-&gt; do
-	    M4_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0), tile_step(400.0))
-	end.().output("M4Fil.k", "Max. Metal coverage MM4Filler ratio for any 800 x 800 µm² chip area [%] = 75.0")
-	
-	-&gt; do
-	    M5_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0), tile_step(400.0))
-	end.().output("M5Fil.h", "Min. Metal coverage MM5Filler ratio for any 800 x 800 µm² chip area [%] = 25.0")
-	
-	-&gt; do
-	    M5_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0), tile_step(400.0))
-	end.().output("M5Fil.k", "Max. Metal coverage MM5Filler ratio for any 800 x 800 µm² chip area [%] = 75.0")
-	
-	-&gt; do
-	    TM1_density.ext_with_density(0.0 .. 0.25, 'll')
-	end.().output("TM1.c", "Min. global TopMetal1 density [%] = 25.00")
-	
-	-&gt; do
-	    TM1_density.ext_with_density(0.7 .. 1.0, 'll')
-	end.().output("TM1.d", "Max. global TopMetal1 density [%] = 70.00")
-	
-	-&gt; do
-	    TM2_density.ext_with_density(0.0 .. 0.25, 'll')
-	end.().output("TM2.c", "Min. global TopMetal1 density [%] = 25.0")
-	
-	-&gt; do
-	    TM2_density.ext_with_density(0.7 .. 1.0, 'll')
-	end.().output("TM2.c1", "Max. global TopMetal1 density [%] = 70.0")
-	
-	-&gt; do
-	    LBE.ext_with_density(0.2 .. 1.0, 'll')
-	end.().output("LBE.i", "Max. global LBE density [%] = 20.0 %")
-
-end
-
-if conditional_enabled[:sanityRules]
-	
-	-&gt; do
-	    Activ_pin.ext_not(Activ)
-	end.().output("forbidden.a", "Activ enclosure of Activ_pin = 0.0")
-	
-	-&gt; do
-	    GatPoly_pin.ext_not(GatPoly)
-	end.().output("forbidden.b", "GatPoly enclosure of GatPoly_pin = 0.0")
-	
-	-&gt; do
-	    NWell_pin.ext_not(NWell)
-	end.().output("forbidden.c", "NWell enclosure of NWell_pin = 0.0")
-	
-	-&gt; do
-	    Metal1_pin.ext_not(Metal1)
-	end.().output("forbidden.d", "Metal1 enclosure of Metal1_pin = 0.0")
-	
-	-&gt; do
-	    Metal2_pin.ext_not(Metal2)
-	end.().output("forbidden.f.M1", "Metal2 enclosure of Metal2_pin = 0.0")
-	
-	-&gt; do
-	    Metal3_pin.ext_not(Metal3)
-	end.().output("forbidden.f.M2", "Metal3 enclosure of Metal3_pin = 0.0")
-	
-	-&gt; do
-	    Metal4_pin.ext_not(Metal4)
-	end.().output("forbidden.f.M3", "Metal4 enclosure of Metal4_pin = 0.0")
-	
-	-&gt; do
-	    Metal5_pin.ext_not(Metal5)
-	end.().output("forbidden.f.M4", "Metal5 enclosure of Metal5_pin = 0.0")
-	
-	-&gt; do
-	    TopMetal1_pin.ext_not(TopMetal1)
-	end.().output("forbidden.f.M5", "TopMetal1 enclosure of TopMetal1_pin = 0.0")
-	
-	-&gt; do
-	    TopMetal2_pin.ext_not(TopMetal2)
-	end.().output("forbidden.f.MT1", "TopMetal2 enclosure of TopMetal2_pin = 0.0")
-	
-	-&gt; do
-	    BiWind_org.dup
-	end.().output("forbidden.Biwind", "Biwind forbidden layer in 0.13um designs")
-	
-	-&gt; do
-	    PEmWind_org.dup
-	end.().output("forbidden.PEmWind", "PEmWind forbidden layer in 0.13um designs")
-	
-	-&gt; do
-	    BasPoly_org.dup
-	end.().output("forbidden.BasPoly", "BasPoly forbidden layer in 0.13um designs")
-	
-	-&gt; do
-	    DeepCo_org.dup
-	end.().output("forbidden.DeepCo", "DeepCo forbidden layer in 0.13um designs")
-	
-	-&gt; do
-	    PEmPoly_org.dup
-	end.().output("forbidden.PEmPoly", "PEmPoly forbidden layer in 0.13um designs")
-	
-	-&gt; do
-	    EmPoly_org.dup
-	end.().output("forbidden.EmPoly", "EmPoly forbidden layer in 0.13um designs")
-	
-	-&gt; do
-	    LDMOS_org.dup
-	end.().output("forbidden.LDMOS", "LDMOS forbidden layer in 0.13um designs")
-	
-	-&gt; do
-	    PBiWind_org.dup
-	end.().output("forbidden.PBiWind", "PBiWind forbidden layer in 0.13um designs")
-	
-	-&gt; do
-	    Flash_org.dup
-	end.().output("forbidden.Flash", "Flash forbidden layer in 0.13um designs")
-	
-	-&gt; do
-	    ColWind_org.dup
-	end.().output("forbidden.ColWind", "ColWind forbidden layer in 0.13um designs")
-
-end
-
--&gt; do
-    LBE.width(100000)
-end.().output("LBE.a", "LBE.a: Min. width of LBE = 100.0")
-
--&gt; do
-    LBE.drc(width &gt; 1500000)
-end.().output("LBE.b", "LBE.b: Max. width of LBE = 1500.0")
-
--&gt; do
-    LBE.ext_area([["&gt;", 250000.0*1000.0*1000.0]])
-end.().output("LBE.b1", "LBE.b1: Max allowed LBE area = 250000.0")
-
--&gt; do
-    LBE.space(100000)
-end.().output("LBE.c", "LBE.c: Min. LBE space or notch = 100.0")
-
--&gt; (;lbe_in_seal) do
-    lbe_in_seal = LBE.merged(true, 0).inside(EdgeSeal.holes.merge)
-    lbe_in_seal.separation(EdgeSeal, 150000)
-end.().output("LBE.d", "LBE.d: Min. space of LBE to inner edge of Edge Seal = 150.0")
-
--&gt; do
-    LBE.ext_ring.dup
-end.().output("LBE.h", "LBE.h: No LBE ring allowed")
-</text>
-</klayout-macro>
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/drc/sg13g2_maximal.lydrc b/ihp-sg13g2/libs.tech/klayout/tech/drc/sg13g2_maximal.lydrc
index 40a9590e..435f9147 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/drc/sg13g2_maximal.lydrc
+++ b/ihp-sg13g2/libs.tech/klayout/tech/drc/sg13g2_maximal.lydrc
@@ -30,49 +30,49 @@
  <interpreter>dsl</interpreter>
  <dsl-interpreter-name>drc-dsl-xml</dsl-interpreter-name>
  <text># Supported variables that can be set using "-rd &lt;name&gt;=&lt;value&gt;" on the command line:
-# logfile - path to the log file [default: no log file]
-# gdsfile - path to the GDS layout to check (required in batch mode)
-# cell    - name of the cell to check (required in batch mode)
-# outfile - path to the report database [default: sg13g2_maximal.lyrdb in the script directory]
+# log_file    - path to the log file [default: no log file]
+# in_gds      - path to the GDS layout to check (required in batch mode)
+# cell        - name of the cell to check
+# report_file - path to the report database [default: sg13g2_maximal.lyrdb in the script directory]
 
 # to set logfile: -rd logfile="sg13g2_maximal.log"
-if $logfile
-    log_file($logfile)
+if $log_file
+    log_file($log_file)
 end
 
 application = RBA::Application.instance
 main_window = application.main_window
-if main_window
+if main_window and not $in_gds
     curr_layout_view = main_window.current_view()
     unless curr_layout_view
         layout_path = RBA::FileDialog::ask_open_file_name("Chose your layout file.", ".", "GDSII files (*.GDS *.gds *.GDS.gz *.gds.gz *.GDS2 *.gds2 *.GDS2.gz *.gds2.gz);; All files (*)")
+        unless layout_path
+            return
+        end
         main_window.load_layout(layout_path, 1)
         curr_layout_view = main_window.current_view()
     end
+    active_layout = RBA::CellView::active.layout
     active_cellname = RBA::CellView::active.cell_name
+    source(active_layout, active_cellname)
 else
     log("DRC: batch mode")
+    # to set input layout: -rd in_gds="path to GDS file"
     # to set cell: -rd cell="topcell"
     if $cell
         active_cellname = $cell
         log("Active cell: " + active_cellname)
+        source($in_gds, active_cellname)
+        active_layout = source.layout
     else
-        raise("'cell' script variable must be defined on command line")
+        source($in_gds)
+        active_layout = source.layout
+        active_cellname = source.cell_name
     end
 end
 
-active_layout = RBA::CellView::active.layout
-
-unless active_layout or $gdsfile
-    raise("layout file must be defined on command line or via 'gdsfile' script variable")
-end
-
-# to set input layout: -rd gdsfile="path to GDS file"
-if $gdsfile
-    source($gdsfile, active_cellname)
-    active_layout = source.layout
-else
-    source(active_layout, active_cellname)
+unless active_layout or $in_gds
+    raise("layout file must be defined on command line or via 'in_gds' script variable")
 end
 
 if active_layout.dbu != 0.001
@@ -80,14 +80,30 @@ if active_layout.dbu != 0.001
 end
 
 report_file = __dir__ + "/sg13g2_maximal.lyrdb"
-# to set report file: -rd outfile="sg13g2_maximal.lyrdb"
-if $outfile
-    report_file = File.expand_path($outfile)
+# to set report file: -rd report_file="sg13g2_maximal.lyrdb"
+if $report_file
+    report_file = File.expand_path($report_file)
 end
+
 report("design rules: sg13g2_maximal | layout cell: " + active_cellname, report_file)
 
 deep
 
+$drc_error_count = 0
+
+class DRC::DRCLayer
+    unless method_defined?(:original_output)
+        alias_method :original_output, :output
+    end
+
+    def output(*args)
+        count = self.count()
+        $drc_error_count += count
+        puts("Rule %s: %d error(s)" % [args[0], count])
+        original_output(*args)
+    end
+end
+
 # Initial definitions of control flow variables
 # Strings from the command line have to be converted
 if defined? $offGrid
@@ -116,6 +132,110 @@ else
     $sanityRules = true
 end
 
+class DRC::DRCEngine
+    def find_intersecting_edges_errors(dbu_value,
+                                       error_edge_pairs_90,
+                                       error_edge_pairs_180,
+                                       inverse_error_edge_pairs_90 = nil,
+                                       inverse_error_edge_pairs_180 = nil,
+                                       options = {})
+        consider_intersecting_edges   = options.fetch(:consider_intersecting_edges, false)
+        consider_touch_points         = options.fetch(:consider_touch_points, false)
+        ignore_non_axis_aligned_edges = options.fetch(:ignore_non_axis_aligned_edges, false)
+        min_angle                     = options.fetch(:min_angle, 0)
+        max_angle                     = options.fetch(:max_angle, 90)
+        include_min_angle             = options.fetch(:include_min_angle, true)
+        include_max_angle             = options.fetch(:include_max_angle, false)
+        area_of_right_angle = dbu_value**2/2
+        errors_ep = RBA::EdgePairs::new()
+        touch_point_errors_ep = RBA::EdgePairs::new()
+        intersecting_edges_errors_ep = RBA::EdgePairs::new()
+        intersecting_edges_error_candidates = Hash.new()
+        no_touch_point_error = Hash.new()
+        error_edge_pairs_90.data.each do |edge_pair|
+            ip = nil
+            if edge_pair.first.p1 == edge_pair.second.p1 or
+               edge_pair.first.p1 == edge_pair.second.p2
+                ip = edge_pair.first.p1
+            elsif edge_pair.first.p2 == edge_pair.second.p1 or
+                  edge_pair.first.p2 == edge_pair.second.p2
+                ip = edge_pair.first.p2
+            else
+                ip = edge_pair.first.intersection_point(edge_pair.second)
+            end
+            if ip
+                intersecting_edges_error_candidates[ip] = edge_pair
+                if !edge_pair.first.is_degenerate? and !edge_pair.second.is_degenerate?
+                    if (edge_pair.first.contains?(edge_pair.second.p1) and
+                       edge_pair.first.contains?(edge_pair.second.p2)) or
+                       (edge_pair.second.contains?(edge_pair.first.p1) and
+                       edge_pair.second.contains?(edge_pair.first.p2))
+                        no_touch_point_error[ip] = true
+                    end
+                end
+            end
+        end
+        if consider_intersecting_edges or consider_touch_points
+            touch_point_candidates = Hash.new()
+            touch_point_errors = Hash.new()
+            if inverse_error_edge_pairs_90 and inverse_error_edge_pairs_180
+                (inverse_error_edge_pairs_90 + inverse_error_edge_pairs_180).data.each do |edge_pair|
+                    ip = edge_pair.first.intersection_point(edge_pair.second)
+                    if ip
+                        if touch_point_candidates[ip]
+                            touch_point_errors[ip] = true
+                            touch_point_candidates.delete(ip)
+                        elsif !no_touch_point_error[ip]
+                            touch_point_candidates[ip] = edge_pair
+                        end
+                    end
+                end
+            end
+            touch_point_candidates = Hash.new()
+            (error_edge_pairs_90 + error_edge_pairs_180).data.each do |edge_pair|
+                ip = nil
+                if edge_pair.first.p1 == edge_pair.second.p1 or
+                   edge_pair.first.p1 == edge_pair.second.p2
+                    ip = edge_pair.first.p1
+                elsif edge_pair.first.p2 == edge_pair.second.p1 or
+                      edge_pair.first.p2 == edge_pair.second.p2
+                    ip = edge_pair.first.p2
+                end
+                if ip
+                    if edge_pair.area == area_of_right_angle or max_angle == 180
+                        intersecting_edges_error_candidates[ip] = edge_pair
+                    end
+                    if touch_point_errors[ip]
+                        touch_point_errors_ep.insert(edge_pair)
+                        intersecting_edges_error_candidates.delete(ip)
+                    elsif touch_point_candidates[ip]
+                        touch_point_errors_ep.insert(edge_pair)
+                        touch_point_errors_ep.insert(touch_point_candidates[ip])
+                        touch_point_candidates.delete(ip)
+                        intersecting_edges_error_candidates.delete(ip)
+                    elsif !no_touch_point_error[ip]
+                        touch_point_candidates[ip] = edge_pair
+                    end
+                end
+            end
+            if consider_intersecting_edges
+                intersecting_edges_errors_ep = RBA::EdgePairs::new(intersecting_edges_error_candidates.values)
+                if max_angle != 180
+                    intersecting_edges_errors_ep = intersecting_edges_errors_ep.with_internal_angle(min_angle, max_angle, false, include_min_angle, include_max_angle)
+                end
+                errors_ep = errors_ep + intersecting_edges_errors_ep
+            end
+        end
+        if ignore_non_axis_aligned_edges
+            errors_ep = errors_ep.with_angle_both(RBA::Edges::OrthoEdges, false)
+        end
+        if consider_touch_points
+            errors_ep = errors_ep + touch_point_errors_ep
+        end
+        return DRC::DRCLayer::new(self, errors_ep)
+    end
+end
+
 class DRC::DRCLayer
     def ext_and(other)
         self_min_coherence_state = self.data.min_coherence?
@@ -128,31 +248,149 @@ class DRC::DRCLayer
         return output_layer
     end
 
-    def ext_area(constraint)
-        output_layer = self.dup
+    def ext_with_angle(constraint)
+        if self.polygons?
+            self_min_coherence_state = self.data.min_coherence?
+            self.data.min_coherence = true
+            self_edges = self.edges
+            self.data.min_coherence = self_min_coherence_state
+        else
+            self_edges = self
+        end
+        lower_bound = nil
+        upper_bound = nil
+        output_layer = nil
+        constraint.each do |expression|
+            relation = expression[0]
+            value = expression[1]
+            if relation == "&gt;"
+                lower_bound = value + 1e-6
+            elsif relation == "&lt;"
+                upper_bound = value
+            elsif relation == "=="
+                output_layer = self_edges.with_angle(value)
+                if value &gt; 0 and value &lt; 90
+                    output_layer += self_edges.with_angle(-value)
+                end
+            elsif relation == "!="
+                output_layer = self_edges.without_angle(value)
+                if value &gt; 0 and value &lt; 90
+                    output_layer += self_edges.without_angle(-value)
+                end
+            elsif relation == "&gt;="
+                lower_bound = value
+            elsif relation == "&lt;="
+                upper_bound = value + 1e-6
+            else
+                raise "invalid expression"
+            end
+        end
+        if lower_bound or upper_bound
+            output_layer = self_edges.with_angle(lower_bound, upper_bound)
+            output_layer += self_edges.with_angle(-upper_bound, -lower_bound)
+        end
+        return output_layer
+    end
+
+    def ext_with_area(constraint)
+        lower_bound = nil
+        upper_bound = nil
+        output_layer = nil
+        self_min_coherence_state = self.data.min_coherence?
+        self.data.min_coherence = true
         constraint.each do |expression|
-            output_layer.data.min_coherence = true
             relation = expression[0]
             value = expression[1]
             if relation == "&gt;"
-                output_layer = output_layer.with_area((value + @engine.dbu), nil)
+                lower_bound = value + 1e-6
             elsif relation == "&lt;"
-                output_layer = output_layer.with_area(nil, value)
+                upper_bound = value
             elsif relation == "=="
-                output_layer = output_layer.with_area(value)
+                output_layer = self.with_area(value)
             elsif relation == "!="
-                output_layer = output_layer.without_area(value)
+                output_layer = self.without_area(value)
             elsif relation == "&gt;="
-                output_layer = output_layer.with_area(value, nil)
+                lower_bound = value
             elsif relation == "&lt;="
-                output_layer = output_layer.with_area(nil, (value + @engine.dbu))
+                upper_bound = value + 1e-6
             else
                 raise "invalid expression"
             end
         end
+        if lower_bound or upper_bound
+            output_layer = self.with_area(lower_bound, upper_bound)
+        end
+        self.data.min_coherence = self_min_coherence_state
         return output_layer
     end
 
+    def ext_coincident_part(other, outside: false, inverted: false)
+        if outside and !inverted and self.polygons? and other.polygons?
+            return self.separation(other, 1).first_edges
+        end
+        if self.polygons?
+            self_min_coherence_state = self.data.min_coherence?
+            self.data.min_coherence = true
+            self_edges = self.edges
+            self.data.min_coherence = self_min_coherence_state
+        else
+            self_edges = self
+        end
+        if other.polygons?
+            other_min_coherence_state = other.data.min_coherence?
+            other.data.min_coherence = true
+            other_edges = other.edges
+            other.data.min_coherence = other_min_coherence_state
+        else
+            other_edges = other
+        end
+        if outside
+            if inverted
+                return self_edges.not(self_edges.separation(other_edges, 1).first_edges)
+            else
+                return self_edges.separation(other_edges, 1).first_edges
+            end
+        else
+            if inverted
+                return self_edges.not(other_edges)
+            else
+                return self_edges.and(other_edges)
+            end
+        end
+    end
+
+    def ext_coincident_edges(other, outside: false, consider_touch_points: false)
+        if self.polygons?
+            self_min_coherence_state = self.data.min_coherence?
+            self.data.min_coherence = true
+            self_edges = self.edges
+            self.data.min_coherence = self_min_coherence_state
+        else
+            self_edges = self
+        end
+        if other.polygons?
+            other_min_coherence_state = other.data.min_coherence?
+            other.data.min_coherence = true
+            other_edges = other.edges
+            other.data.min_coherence = other_min_coherence_state
+        else
+            other_edges = other
+        end
+        if outside
+            if consider_touch_points
+                return self_edges.not_outside(self_edges.separation(other_edges, 1, @engine.whole_edges).first_edges)
+            else
+                return self_edges.not_outside(self_edges.separation(other_edges, 1, @engine.whole_edges, @engine.without_touching_corners).first_edges)
+            end
+        else
+            if consider_touch_points
+                raise "not implemented"
+            else
+                return met1_edges.not_outside(self_edges &amp; other_edges)
+            end
+        end
+    end
+
     def ext_constraint_satisfied(value, constraint)
         output_bool = true
         constraint.each do |expression|
@@ -175,6 +413,21 @@ class DRC::DRCLayer
         return output_bool
     end
 
+    def ext_overlapping(other, constraint = [])
+        self_min_coherence_state = self.data.min_coherence?
+        other_min_coherence_state =  other.data.min_coherence?
+        self.data.min_coherence = true
+        other.data.min_coherence = true
+        overlap_filter = @engine.overlapping(other.not_inside(self))
+        constraint.each do |expression|
+            overlap_filter = overlap_filter.public_send(expression[0], expression[1])
+        end
+        output_layer = self.drc(@engine.if_all(overlap_filter, ! @engine.inside(other)))
+        self.data.min_coherence = self_min_coherence_state
+        other.data.min_coherence = other_min_coherence_state
+        return output_layer
+    end
+
     def ext_covering(other)
         self_min_coherence_state = self.data.min_coherence?
         other_min_coherence_state =  other.data.min_coherence?
@@ -191,7 +444,7 @@ class DRC::DRCLayer
         other_min_coherence_state =  other.data.min_coherence?
         self.data.min_coherence = true
         other.data.min_coherence = true
-        output_layer = self.enclosed(other, value)
+        output_layer = self.enclosed(other, value, @engine.projection)
         self.data.min_coherence = self_min_coherence_state
         other.data.min_coherence = other_min_coherence_state
         if polygon_output
@@ -201,12 +454,123 @@ class DRC::DRCLayer
         end
     end
 
-    def ext_fast_separation(other, value, polygon_output: false)
+    def ext_extended(outside = 0, inside = 0)
+        if self.polygons?
+            self_min_coherence_state = self.data.min_coherence?
+            self.data.min_coherence = true
+            edge_layer = self.edges
+            self.data.min_coherence = self_min_coherence_state
+        else
+            edge_layer = self
+        end
+        return edge_layer.extended(:out =&gt; outside, :in =&gt; inside).merge(true, 0)
+    end
+
+    def ext_extents
+        self_min_coherence_state = self.data.min_coherence?
+        self.data.min_coherence = true
+        output_layer = self.extents.merge(true, 0)
+        self.data.min_coherence = self_min_coherence_state
+        return output_layer
+    end
+
+    def ext_separation_at_intersecting_edges(other,
+                                             value,
+                                             metric=RBA::Region::Euclidian,
+                                             consider_intersecting_edges=false,
+                                             consider_touch_points=false,
+                                             ignore_non_axis_aligned_edges=false,
+                                             min_angle=0,
+                                             max_angle=90,
+                                             include_min_angle=true,
+                                             include_max_angle=false,
+                                             polygons=false)
         self_min_coherence_state = self.data.min_coherence?
         other_min_coherence_state =  other.data.min_coherence?
         self.data.min_coherence = true
         other.data.min_coherence = true
-        output_layer = self.separation(other, value)
+        if metric.is_a?(DRC::DRCMetrics)
+            metric = metric.value
+        end
+        if value.is_a? Float
+            dbu_value = (value/1.dbu).round
+        else
+            dbu_value = value
+        end
+        error_edge_pairs_90 = DRC::DRCLayer::new(@engine,
+            self.data.separation_check(other.data, dbu_value, false, metric, 90, 1, nil))
+        error_edge_pairs_180 = DRC::DRCLayer::new(@engine,
+            self.data.separation_check(other.data, dbu_value, false, metric, 180, nil, 1))
+        width_error_edge_pairs_90 = DRC::DRCLayer::new(@engine,
+            self.data.width_check(dbu_value, false, metric, 90, 1, nil) +
+            other.data.width_check(dbu_value, false, metric, 90, 1, nil))
+        width_error_edge_pairs_180 = DRC::DRCLayer::new(@engine,
+            self.data.width_check(dbu_value, false, metric, 180, nil, 1) +
+            other.data.width_check(dbu_value, false, metric, 180, nil, 1))
+        separation_errors = @engine.find_intersecting_edges_errors(
+            dbu_value,
+            error_edge_pairs_90,
+            error_edge_pairs_180,
+            width_error_edge_pairs_90,
+            width_error_edge_pairs_180,
+            {
+                consider_intersecting_edges: consider_intersecting_edges,
+                consider_touch_points: consider_touch_points,
+                ignore_non_axis_aligned_edges: ignore_non_axis_aligned_edges,
+                min_angle: min_angle,
+                max_angle: max_angle,
+                include_min_angle: include_min_angle,
+                include_max_angle: include_max_angle
+            }
+        )
+        self.data.min_coherence = self_min_coherence_state
+        other.data.min_coherence = other_min_coherence_state
+        if polygons
+            return separation_errors.polygons.merge(true, 0)
+        else
+            return separation_errors
+        end
+    end
+
+    def ext_fast_separation(other,
+                            value,
+                            metric: @engine.euclidian,
+                            consider_intersecting_edges: true,
+                            consider_touch_points: true,
+                            ignore_non_axis_aligned_edges: false,
+                            min_angle: 0,
+                            max_angle: 90,
+                            include_min_angle: true,
+                            include_max_angle: false,
+                            polygon_output: false)
+        self_min_coherence_state = self.data.min_coherence?
+        other_min_coherence_state =  other.data.min_coherence?
+        self.data.min_coherence = true
+        other.data.min_coherence = true
+        output_layer = self.separation(other, value, metric, @engine.angle_limit(max_angle))
+        if !consider_intersecting_edges and !consider_touch_points
+            output_layer = output_layer.with_distance(1, nil)
+            if ignore_non_axis_aligned_edges
+                output_layer = output_layer.with_angle(@engine.ortho, @engine.both)
+            end
+        elsif consider_intersecting_edges ^ consider_touch_points
+            intersecting_edges_errors = output_layer.with_distance(0).edges
+            candidate_layer1 = self.interacting(intersecting_edges_errors)
+            candidate_layer2 = other.interacting(intersecting_edges_errors)
+            output_layer = output_layer.with_distance(1, nil)
+            output_layer = output_layer + candidate_layer1.ext_separation_at_intersecting_edges(
+                candidate_layer2,
+                value,
+                metric,
+                consider_intersecting_edges,
+                consider_touch_points,
+                ignore_non_axis_aligned_edges,
+                min_angle,
+                max_angle,
+                include_min_angle,
+                include_max_angle,
+                false)
+        end
         self.data.min_coherence = self_min_coherence_state
         other.data.min_coherence = other_min_coherence_state
         if polygon_output
@@ -216,7 +580,23 @@ class DRC::DRCLayer
         end
     end
 
-    def ext_interacting(other, constraint=nil)
+    def ext_inside_part(other, inverted: false)
+        if self.polygons?
+            self_min_coherence_state = self.data.min_coherence?
+            self.data.min_coherence = true
+            edge_layer = self.edges
+            self.data.min_coherence = self_min_coherence_state
+        else
+            edge_layer = self
+        end
+        if inverted
+            return edge_layer.outside_part(other.merged(true, 0))
+        else
+            return edge_layer.inside_part(other.merged(true, 0))
+        end
+    end
+
+    def ext_interacting(other, constraint=nil, inverted: false)
         self_min_coherence_state = self.data.min_coherence?
         other_min_coherence_state =  other.data.min_coherence?
         self.data.min_coherence = true
@@ -224,20 +604,155 @@ class DRC::DRCLayer
         overlap_filter = @engine.secondary(other).overlapping(@engine.primary)
         if not constraint
             touch_filter = @engine.secondary(other).outside(@engine.primary).edges &amp; @engine.primary
-            output_layer = self.drc(@engine.if_any(overlap_filter, touch_filter))
+            if inverted
+                output_layer = self.drc(@engine.if_none(overlap_filter, touch_filter))
+            else
+                output_layer = self.drc(@engine.if_any(overlap_filter, touch_filter))
+            end
         else
             touch_filter = (@engine.secondary(other).outside(@engine.primary).edges &amp; @engine.primary).polygons(0.1.um).merged
             filter = (overlap_filter + touch_filter).count
             constraint.each do |expression|
                 filter = filter.public_send(expression[0], expression[1])
             end
-            output_layer = self.drc(@engine.if_any(filter))
+            if inverted
+                output_layer = self.drc(@engine.if_none(filter))
+            else
+                output_layer = self.drc(@engine.if_any(filter))
+            end
         end
         self.data.min_coherence = self_min_coherence_state
         other.data.min_coherence = other_min_coherence_state
         return output_layer
     end
 
+    def ext_overlap_at_intersecting_edges(other,
+                                          value,
+                                          metric=RBA::Region::Euclidian,
+                                          consider_intersecting_edges=false,
+                                          consider_touch_points=false,
+                                          ignore_non_axis_aligned_edges=false,
+                                          min_angle=0,
+                                          max_angle=90,
+                                          include_min_angle=true,
+                                          include_max_angle=false,
+                                          polygons=false)
+        self_min_coherence_state = self.data.min_coherence?
+        other_min_coherence_state =  other.data.min_coherence?
+        self.data.min_coherence = true
+        other.data.min_coherence = true
+        if metric.is_a?(DRC::DRCMetrics)
+            metric = metric.value
+        end
+        if value.is_a? Float
+            dbu_value = (value/1.dbu).round
+        else
+            dbu_value = value
+        end
+        error_edge_pairs_90 = DRC::DRCLayer::new(@engine,
+            self.data.overlap_check(other.data, dbu_value, false, metric, 90, 1, nil))
+        error_edge_pairs_180 = DRC::DRCLayer::new(@engine,
+            self.data.overlap_check(other.data, dbu_value, false, metric, 180, nil, 1))
+        overlap_errors = @engine.find_intersecting_edges_errors(
+            dbu_value,
+            error_edge_pairs_90,
+            error_edge_pairs_180,
+            nil,
+            nil,
+            {
+                consider_intersecting_edges: consider_intersecting_edges,
+                consider_touch_points: consider_touch_points,
+                ignore_non_axis_aligned_edges: ignore_non_axis_aligned_edges,
+                min_angle: min_angle,
+                max_angle: max_angle,
+                include_min_angle: include_min_angle,
+                include_max_angle: include_max_angle
+            }
+        )
+        self.data.min_coherence = self_min_coherence_state
+        other.data.min_coherence = other_min_coherence_state
+        if polygons
+            return overlap_errors.polygons.merge(true, 0)
+        else
+            return overlap_errors
+        end
+    end
+
+    def ext_fast_overlap(other,
+                         value,
+                         metric: @engine.euclidian,
+                         consider_intersecting_edges: true,
+                         consider_touch_points: true,
+                         ignore_non_axis_aligned_edges: false,
+                         min_angle: 0,
+                         max_angle: 90,
+                         include_min_angle: true,
+                         include_max_angle: false,
+                         polygon_output: false)
+        if self.polygons?
+            self_min_coherence_state = self.data.min_coherence?
+            self.data.min_coherence = true
+        end
+        if other.polygons?
+            other_min_coherence_state =  other.data.min_coherence?
+            other.data.min_coherence = true
+        end
+        if self.polygons? and other.polygons?
+            output_layer = self.overlap(other, value)
+        else
+            if self.polygons?
+                self_edges = self.edges
+            else
+                self_edges = self
+            end
+            if other.polygons?
+                other_edges = other.edges
+            else
+                other_edges = other
+            end
+            output_layer = self_edges.overlap(other_edges, value)
+        end
+        if !consider_intersecting_edges and !consider_touch_points
+            output_layer = output_layer.with_distance(1, nil)
+            if ignore_non_axis_aligned_edges
+                output_layer = output_layer.with_angle(@engine.ortho, @engine.both)
+            end
+        elsif consider_intersecting_edges ^ consider_touch_points
+            intersecting_edges_errors = output_layer.with_distance(0).edges
+            candidate_layer1 = self.interacting(intersecting_edges_errors)
+            candidate_layer2 = other.interacting(intersecting_edges_errors)
+            output_layer = output_layer.with_distance(1, nil)
+            output_layer = output_layer + candidate_layer1.ext_overlap_at_intersecting_edges(
+                candidate_layer2,
+                value,
+                metric,
+                consider_intersecting_edges,
+                consider_touch_points,
+                ignore_non_axis_aligned_edges,
+                min_angle,
+                max_angle,
+                include_min_angle,
+                include_max_angle,
+                false)
+        end
+        if self.polygons?
+            self.data.min_coherence = self_min_coherence_state
+        end
+        if other.polygons?
+            other.data.min_coherence = other_min_coherence_state
+        end
+        if polygon_output
+            return output_layer.polygons.merge(true, 0)
+        else
+            return output_layer
+        end
+    end
+
+    def ext_with_coincident_edges(other)
+        coincident_edges = self.edges &amp; other
+        return self.interacting(coincident_edges)
+    end
+
     def ext_with_length(constraint)
         if self.polygons?
             self_min_coherence_state = self.data.min_coherence?
@@ -278,12 +793,18 @@ class DRC::DRCLayer
         return output_layer
     end
 
-    def ext_or(other)
+    def ext_or(other, *further_layers)
         self_min_coherence_state = self.data.min_coherence?
         other_min_coherence_state =  other.data.min_coherence?
         self.data.min_coherence = true
         other.data.min_coherence = true
         output_layer = self.join(other)
+        further_layers.each do |further_layer|
+            further_layer_min_coherence_state = further_layer.data.min_coherence?
+            further_layer.data.min_coherence = true
+            output_layer = output_layer.join(further_layer)
+            further_layer.data.min_coherence = further_layer_min_coherence_state
+        end
         self.data.min_coherence = self_min_coherence_state
         other.data.min_coherence = other_min_coherence_state
         return output_layer
@@ -323,10 +844,87 @@ class DRC::DRCLayer
         return output_layer
     end
 
-    def ext_fast_space(value, polygon_output: false)
+    def ext_space_at_intersecting_edges(value,
+                                        metric=RBA::Region::Euclidian,
+                                        consider_intersecting_edges=false,
+                                        consider_touch_points=false,
+                                        ignore_non_axis_aligned_edges=false,
+                                        min_angle=0,
+                                        max_angle=90,
+                                        include_min_angle=true,
+                                        include_max_angle=false,
+                                        polygons=false)
         self_min_coherence_state = self.data.min_coherence?
         self.data.min_coherence = true
-        output_layer = self.space(value)
+        if metric.is_a?(DRC::DRCMetrics)
+            metric = metric.value
+        end
+        if value.is_a? Float
+            dbu_value = (value/1.dbu).round
+        else
+            dbu_value = value
+        end
+        error_edge_pairs_90 = DRC::DRCLayer::new(@engine, self.data.space_check(dbu_value, false, metric, 90, 1, nil))
+        error_edge_pairs_180 = DRC::DRCLayer::new(@engine, self.data.space_check(dbu_value, false, metric, 180, nil, 1))
+        width_error_edge_pairs_90 = DRC::DRCLayer::new(@engine, self.data.width_check(dbu_value, false, metric, 90, 1, nil))
+        width_error_edge_pairs_180 = DRC::DRCLayer::new(@engine, self.data.width_check(dbu_value, false, metric, 180, nil, 1))
+        space_errors = @engine.find_intersecting_edges_errors(
+            dbu_value,
+            error_edge_pairs_90,
+            error_edge_pairs_180,
+            width_error_edge_pairs_90,
+            width_error_edge_pairs_180,
+            {
+                consider_intersecting_edges: consider_intersecting_edges,
+                consider_touch_points: consider_touch_points,
+                ignore_non_axis_aligned_edges: ignore_non_axis_aligned_edges,
+                min_angle: min_angle,
+                max_angle: max_angle,
+                include_min_angle: include_min_angle,
+                include_max_angle: include_max_angle
+            }
+        )
+        self.data.min_coherence = self_min_coherence_state
+        if polygons
+            return space_errors.polygons.merge(true, 0)
+        else
+            return space_errors
+        end
+    end
+
+    def ext_fast_space(value,
+                       metric: @engine.euclidian,
+                       consider_intersecting_edges: true,
+                       consider_touch_points: true,
+                       ignore_non_axis_aligned_edges: false,
+                       min_angle: 0,
+                       max_angle: 90,
+                       include_min_angle: true,
+                       include_max_angle: false,
+                       polygon_output: false)
+        self_min_coherence_state = self.data.min_coherence?
+        self.data.min_coherence = true
+        output_layer = self.space(value, metric, @engine.angle_limit(max_angle))
+        if !consider_intersecting_edges and !consider_touch_points
+            output_layer = output_layer.with_distance(1, nil)
+            if ignore_non_axis_aligned_edges
+                output_layer = output_layer.with_angle(@engine.ortho, @engine.both)
+            end
+        elsif consider_intersecting_edges ^ consider_touch_points
+            candidate_layer = self.interacting(output_layer.with_distance(0).edges)
+            output_layer = output_layer.with_distance(1, nil)
+            output_layer = output_layer + candidate_layer.ext_space_at_intersecting_edges(
+                value,
+                metric,
+                consider_intersecting_edges,
+                consider_touch_points,
+                ignore_non_axis_aligned_edges,
+                min_angle,
+                max_angle,
+                include_min_angle,
+                include_max_angle,
+                false)
+        end
         self.data.min_coherence = self_min_coherence_state
         if polygon_output
             return output_layer.polygons.merge(true, 0)
@@ -335,11 +933,93 @@ class DRC::DRCLayer
         end
     end
 
-    def ext_fast_width(value, polygon_output: false)
+    def ext_width_at_intersecting_edges(value,
+                  metric=RBA::Region::Euclidian,
+                  consider_intersecting_edges=false,
+                  consider_touch_points=false,
+                  ignore_non_axis_aligned_edges=false,
+                  min_angle=0,
+                  max_angle=90,
+                  include_min_angle=true,
+                  include_max_angle=false,
+                  polygons=false)
         self_min_coherence_state = self.data.min_coherence?
         self.data.min_coherence = true
-        output_layer = self.width(value)
+        if metric.is_a?(DRC::DRCMetrics)
+            metric = metric.value
+        end
+        if value.is_a? Float
+            dbu_value = (value/1.dbu).round
+        else
+            dbu_value = value
+        end
+        error_edge_pairs_90 = DRC::DRCLayer::new(@engine, self.data.width_check(dbu_value, false, metric, 90, 1, nil))
+        error_edge_pairs_180 = DRC::DRCLayer::new(@engine, self.data.width_check(dbu_value, false, metric, 180, nil, 1))
+        space_error_edge_pairs_90 = DRC::DRCLayer::new(@engine, self.data.space_check(dbu_value, false, metric, 90, 1, nil))
+        space_error_edge_pairs_180 = DRC::DRCLayer::new(@engine, self.data.space_check(dbu_value, false, metric, 180, nil, 1))
+        width_errors = @engine.find_intersecting_edges_errors(
+            dbu_value,
+            error_edge_pairs_90,
+            error_edge_pairs_180,
+            space_error_edge_pairs_90,
+            space_error_edge_pairs_180,
+            {
+                consider_intersecting_edges: consider_intersecting_edges,
+                consider_touch_points: consider_touch_points,
+                ignore_non_axis_aligned_edges: ignore_non_axis_aligned_edges,
+                min_angle: min_angle,
+                max_angle: max_angle,
+                include_min_angle: include_min_angle,
+                include_max_angle: include_max_angle
+            }
+        )
         self.data.min_coherence = self_min_coherence_state
+        if polygons
+            return width_errors.polygons.merge(true, 0)
+        else
+            return width_errors
+        end
+    end
+
+    def ext_fast_width(value,
+                       metric: @engine.euclidian,
+                       consider_intersecting_edges: true,
+                       consider_touch_points: true,
+                       ignore_non_axis_aligned_edges: false,
+                       min_angle: 0,
+                       max_angle: 90,
+                       include_min_angle: true,
+                       include_max_angle: false,
+                       polygon_output: false)
+        if self.polygons?
+            self_min_coherence_state = self.data.min_coherence?
+            self.data.min_coherence = true
+            self_edges = self.edges
+            self.data.min_coherence = self_min_coherence_state
+        else
+            self_edges = self
+        end
+        output_layer = self_edges.width(value, metric, @engine.angle_limit(max_angle))
+        if !consider_intersecting_edges and !consider_touch_points
+            output_layer = output_layer.with_distance(1, nil)
+            if ignore_non_axis_aligned_edges
+                output_layer = output_layer.with_angle(@engine.ortho, @engine.both)
+            end
+        elsif consider_intersecting_edges ^ consider_touch_points
+            candidate_layer = self.interacting(output_layer.with_distance(0).edges)
+            output_layer = output_layer.with_distance(1, nil)
+            output_layer = output_layer + candidate_layer.ext_width_at_intersecting_edges(
+                value,
+                metric,
+                consider_intersecting_edges,
+                consider_touch_points,
+                ignore_non_axis_aligned_edges,
+                min_angle,
+                max_angle,
+                include_min_angle,
+                include_max_angle,
+                false)
+        end
         if polygon_output
             return output_layer.polygons.merge(true, 0)
         else
@@ -347,6 +1027,19 @@ class DRC::DRCLayer
         end
     end
 
+    def ext_enlarge_inside(other, distance, step)
+        enlarged_layer = self.dup
+        num_steps = (distance / step + 0.5).to_i
+        for i in 1..num_steps
+            enlarged_layer = enlarged_layer.sized(step, @engine.acute_limit) &amp; other
+        end
+        rest = distance - num_steps * step
+        if rest &gt; 1.dbu
+            enlarged_layer = enlarged_layer.sized(rest, @engine.acute_limit) &amp; other
+        end
+        return enlarged_layer
+    end
+
     def ext_touching(other, constraint = [["&gt;", 0]])
         self_min_coherence_state = self.data.min_coherence?
         other_min_coherence_state =  other.data.min_coherence?
@@ -366,14 +1059,6 @@ class DRC::DRCLayer
         return output_layer
     end
 
-    def ext_ring
-        holes = self.holes
-        hulls = self.hulls
-        covering = hulls.covering(holes)
-        result = covering.and(self)
-        return result
-    end
-
     def ext_interacting_with_text(text_layer, text)
         if text_layer.is_a? Integer
             text_layer = @engine.labels(text_layer)
@@ -415,20 +1100,26 @@ class DRC::DRCLayer
         if origin == 'll'
             origin_x = bbox.left
             origin_y = bbox.bottom
+            if tile_size and tile_step and (tile_size.get[0] != tile_step.get[0] or tile_size.get[1] != tile_step.get[1])
+              origin_x = bbox.left + tile_step.get[0]/2
+              origin_y = bbox.bottom + tile_step.get[1]/2
+            end
             tile_origin = DRC::DRCTileOrigin::new(origin_x, origin_y)
             arguments.push(tile_origin)
         elsif origin != 'cc'
             raise "Unknown origin: 'cc' or 'll' expected"
         end
         if tile_size
-            return merged_layer.with_density(*arguments)
+            boundary_layer = DRC::DRCLayer::new(@engine, RBA::Region::new(bbox.to_itype(@engine.dbu)))
+            tile_boundary = DRC::DRCTileBoundary::new(boundary_layer)
+            return merged_layer.with_density(*arguments, tile_boundary, @engine.padding_ignore)
         else
             tile_size = DRC::DRCTileSize::new(bbox.width, bbox.height)
             tile_count = DRC::DRCTileCount::new(1,2)
             enlarged_bbox = bbox.enlarged(1.1).to_itype(@engine.dbu)
             boundary_layer = DRC::DRCLayer::new(@engine, RBA::Region::new(enlarged_bbox))
             tile_boundary = DRC::DRCTileBoundary::new(boundary_layer)
-            result = merged_layer.with_density(*arguments, tile_size, tile_count, tile_boundary)
+            result = merged_layer.with_density(*arguments, tile_size, tile_count, tile_boundary, @engine.padding_ignore)
             return result.raw.overlapping(DRC::DRCLayer::new(@engine, RBA::Region::new(bbox.to_itype(@engine.dbu))))
         end
     end
@@ -536,37 +1227,47 @@ if $sanityRules
 	Flash = source.polygons("71/0")
 end
 
-Activ_Act_a = Activ.ext_fast_width(150)
-Activ_Act_d = Activ.ext_area([["&lt;", 0.122]])
+Activ_Act_a = Activ.ext_fast_width(0.15.um)
+Activ_Act_d = Activ.ext_with_area([["&lt;", 0.122.um2]])
+nmosi_relevant_activ = Activ.ext_or(Activ_mask)
 Act_density = Activ.ext_or(Activ_filler)
 GP_or_Act = Activ.ext_or(GatPoly)
 Gate = Activ.ext_and(GatPoly)
-GatPoly_Gat_e = GatPoly.ext_area([["&lt;", 0.09]])
+Act_connect = Activ.ext_not(GatPoly)
+GatPoly_Gat_e = GatPoly.ext_with_area([["&lt;", 0.09.um2]])
 Gat_density = GatPoly.ext_or(GatPoly_filler)
-Cont_SQ = Cont.ext_rectangles(true, false, [["==", 160]], [["==", 160]], nil)
-ContBar = Cont.ext_area([["&gt;", 0.16*0.16]])
-selring_pass = Passiv.ext_ring
-Passiv_Pad_a1 = Passiv.drc((width(projection) &gt; 150000).polygons)
-pSD_pSD_a = pSD.ext_fast_width(310)
-pSD_pSD_k = pSD.ext_area([["&lt;", 0.25]])
+Cont_SQ = Cont.ext_rectangles(true, false, [["==", 0.16.um]], [["==", 0.16.um]], nil)
+ContBar = Cont.ext_with_area([["&gt;", (0.16*0.16).um2]])
+Activ_and_nSD_block = Activ.ext_and(nSD_block)
+selring_pass = Passiv.with_holes
+Passiv_Pad_a1 = Passiv.drc((width(projection) &gt; 150.0.um).polygons)
+X2 = nSD_block.ext_or(pSD)
+pSD_not_nSD = nSD.ext_not(pSD)
+subst_tie_hole = (pSD.holes - pSD.with_holes).without_holes
+pSD_pSD_a = pSD.ext_fast_width(0.31.um)
+pSD_pSD_k = pSD.ext_with_area([["&lt;", 0.25.um2]])
 Act_Nsram = Activ.ext_not(SRAM)
 pSD_Nsram = pSD.ext_not(SRAM)
 GP_Nsram = GatPoly.ext_not(SRAM)
 Cont_Nsram = Cont.ext_not(SRAM)
+V1_Nsram = Via1.ext_not(SRAM)
 M1_Nsram = Metal1.ext_not(SRAM)
 M2_Nsram = Metal2.ext_not(SRAM)
 M2_SRAM = Metal2.ext_and(SRAM)
+V2_Nsram = Via2.ext_not(SRAM)
 M3_Nsram = Metal3.ext_not(SRAM)
 M3_SRAM = Metal3.ext_and(SRAM)
-lNw_a1 = NWell.ext_and(RES)
-NWell_NW_a = NWell.ext_fast_width(620)
+Act_NWell = Activ.ext_and(NWell)
+NWell_NW_a = NWell.ext_fast_width(0.62.um)
 NWell_nBuLay = NWell.ext_and(nBuLay)
-nBuLay_block_NBLB_a = nBuLay_block.ext_fast_width(1500)
-MIM_Mim_a = MIM.ext_fast_width(1140, polygon_output: true)
-MIM_Mim_f = MIM.ext_area([["&lt;", 1.3]])
-sealring = EdgeSeal.ext_ring
+isoPWell = nBuLay.ext_not(NWell)
+nBuLay_block_NBLB_a = nBuLay_block.ext_fast_width(1.5.um)
+nBuLay_nBuLay_block_enc_tmp = nBuLay_block.ext_fast_enclosed(nBuLay, 1.0.um, polygon_output: true)
+nBuLay_nBuLay_block_enc_tmp2 = nBuLay_block.ext_overlapping(nBuLay)
+MIM_Mim_a = MIM.ext_fast_width(1.14.um, consider_intersecting_edges: false, polygon_output: true)
+MIM_Mim_f = MIM.ext_with_area([["&lt;", 1.3.um2]])
+sealring = EdgeSeal.with_holes
 Act_EdgeSeal = Activ.ext_and(EdgeSeal)
-Activ_edgA1_in = Activ.ext_and(EdgeSeal)
 Act_Not_EdgeSeal = Activ.ext_not(EdgeSeal)
 pSD_edgA1_in = pSD.ext_and(EdgeSeal)
 Metal1_edgA1_in = Metal1.ext_and(EdgeSeal)
@@ -574,315 +1275,627 @@ Metal2_edgA1_in = Metal2.ext_and(EdgeSeal)
 Metal3_edgA1_in = Metal3.ext_and(EdgeSeal)
 Cont_edgC1_in = Cont.ext_and(EdgeSeal)
 Via1_edgC1_in = Via1.ext_and(EdgeSeal)
+Via1_edgC1_out = Via1.ext_not(EdgeSeal)
 Via2_edgC1_in = Via2.ext_and(EdgeSeal)
+Via2_edgC1_out = Via2.ext_not(EdgeSeal)
+Cont_outside_EdgeSeal = Cont.outside(EdgeSeal)
+Metal1_outside_EdgeSeal = Metal1.outside(EdgeSeal)
+Metal2_outside_EdgeSeal = Metal2.outside(EdgeSeal)
+Metal3_outside_EdgeSeal = Metal3.outside(EdgeSeal)
 Passiv_dfpad = Passiv.ext_and(dfpad)
-pad = dfpad.merged(true, 0).not_outside(Passiv)
+pad = dfpad.not_outside(Passiv)
 cupPad_candidat = Passiv.ext_and(dfpad_pillar)
-ThickGateOx_TGO_e = ThickGateOx.ext_fast_space(860, polygon_output: true)
-ThickGateOx_TGO_f = ThickGateOx.ext_fast_width(860, polygon_output: true)
-PWell_block_PWB_a = PWell_block.ext_fast_width(620)
-PWell_block_PWB_b = PWell_block.ext_fast_space(620, polygon_output: true)
+dfpad_all = dfpad.ext_or(dfpad_pillar, dfpad_sbump)
+ThickGateOx_TGO_e = ThickGateOx.ext_fast_space(0.86.um, consider_intersecting_edges: false, polygon_output: true)
+ThickGateOx_TGO_f = ThickGateOx.ext_fast_width(0.86.um, consider_intersecting_edges: false, polygon_output: true)
+X1 = NWell.ext_or(PWell_block)
+PWell_block_PWB_a = PWell_block.ext_fast_width(0.62.um)
+PWell_block_PWB_b = PWell_block.ext_fast_space(0.62.um, consider_intersecting_edges: false, polygon_output: true)
+V3_Nsram = Via3.ext_not(SRAM)
 Via3_edgC1_in = Via3.ext_and(EdgeSeal)
+Via3_edgC1_out = Via3.ext_not(EdgeSeal)
 M4_Nsram = Metal4.ext_not(SRAM)
 M4_SRAM = Metal4.ext_and(SRAM)
 Metal4_edgA1_in = Metal4.ext_and(EdgeSeal)
+Metal4_outside_EdgeSeal = Metal4.outside(EdgeSeal)
+V4_Nsram = Via4.ext_not(SRAM)
 Via4_edgC1_in = Via4.ext_and(EdgeSeal)
+Via4_edgC1_out = Via4.ext_not(EdgeSeal)
 M5_Nsram = Metal5.ext_not(SRAM)
 M5_SRAM = Metal5.ext_and(SRAM)
+belowTopMetaln_dfpad = Metal5.ext_and(dfpad)
 Metal5_edgA1_in = Metal5.ext_and(EdgeSeal)
+Metal5_outside_EdgeSeal = Metal5.outside(EdgeSeal)
+Metal5_slit_MIM_Slt_g_M5_sep_tmp1 = Metal5_slit.ext_fast_separation(MIM, 0.6.um, consider_intersecting_edges: false, consider_touch_points: false, polygon_output: true)
+Metal5_slit_MIM_Slt_g_M5_sep_tmp2 = MIM.ext_coincident_edges(Metal5_slit, outside: true, consider_touch_points: true)
+Metal5_slit_MIM_Slt_g_M5_sep_tmp5 = Metal5_slit.ext_and(MIM)
 scr1 = Recog_esd.ext_interacting_with_text(TEXT_0, "scr1")
+nmoscl_2 = Recog_esd.ext_interacting_with_text(TEXT_0, "nmoscl_2")
+nmoscl_4 = Recog_esd.ext_interacting_with_text(TEXT_0, "nmoscl_4")
+Rhigh_recognition_0 = EXTBlock.ext_and(pSD)
 TopVia1_edgC1_in = TopVia1.ext_and(EdgeSeal)
+TopVia1_edgC1_out = TopVia1.ext_not(EdgeSeal)
 TopMetal1_edgA1_in = TopMetal1.ext_and(EdgeSeal)
+TopMetal1_slit_MIM_Slt_g_TM1_sep_tmp1 = TopMetal1_slit.ext_fast_separation(MIM, 0.6.um, consider_intersecting_edges: false, consider_touch_points: false, polygon_output: true)
+TopMetal1_slit_MIM_Slt_g_TM1_sep_tmp2 = MIM.ext_coincident_edges(TopMetal1_slit, outside: true, consider_touch_points: true)
+TopMetal1_slit_MIM_Slt_g_TM1_sep_tmp5 = TopMetal1_slit.ext_and(MIM)
 GatPoly_res = GatPoly.ext_or(PolyRes)
+TopVia1_or_Vmim = TopVia1.ext_or(Vmim)
 TopVia2_edgC1_in = TopVia2.ext_and(EdgeSeal)
+TopVia2_edgC1_out = TopVia2.ext_not(EdgeSeal)
 TopMetal2_edgA1_in = TopMetal2.ext_and(EdgeSeal)
+holes_TopMetal2 = TopMetal2.holes.merge
+tsv_tmp2 = (DeepVia.holes - DeepVia.with_holes).without_holes.outside(DeepVia)
+bad_tsv = DeepVia.without_holes
 M1_density = Metal1.ext_or(Metal1_filler).ext_not(Metal1_slit)
 M2_density = Metal2.ext_or(Metal2_filler).ext_not(Metal2_slit)
-DigiBnd_ring = DigiBnd.merged(true, 0).size(0.01, acute_limit).merge(true, 0).ext_not(DigiBnd)
+DigiBnd_ring = DigiBnd.sized(0.01.um, acute_limit).ext_not(DigiBnd)
 emi2Pin = Metal2_pin.ext_and(TRANS).ext_interacting_with_text(TEXT_0, "E")
 M3_density = Metal3.ext_or(Metal3_filler).ext_not(Metal3_slit)
-nBuLayGen_sized = NWell.merged(true, 0).size(-1+1.to_f/2, acute_limit).merge(true, 0).merged(true, 0).size(1.to_f/2, acute_limit).merge(true, 0)
-Iso_PWell_Act = Activ.ext_and(nBuLay).ext_not(NWell.ext_or(PWell_block))
-PWellBlock_relatedNWell_0 = NWell.merged(true, 0).not_inside(PWell_block).ext_interacting(PWell_block)
+nBuLayGen_sized = NWell.sized((-1+1.to_f/2).um, acute_limit).sized((1.to_f/2).um, acute_limit)
+Act_out_ThickGateOx = Activ.ext_not(Activ.ext_interacting(ThickGateOx))
+PWellBlock_relatedNWell_0 = NWell.not_inside(PWell_block).ext_interacting(PWell_block)
 M4_density = Metal4.ext_or(Metal4_filler).ext_not(Metal4_slit)
 M5_density = Metal5.ext_or(Metal5_filler).ext_not(Metal5_slit)
 SalBlock_not_nSDBlock_not_esd = SalBlock.ext_not(Recog_esd.ext_or(nSD_block))
 TM1_density = TopMetal1.ext_or(TopMetal1_filler).ext_not(TopMetal1_slit)
 TM2_density = TopMetal2.ext_or(TopMetal2_filler).ext_not(TopMetal2_slit)
-GP_mosHV = Gate.merged(true, 0).not_outside(ThickGateOx)
+GP_mosHV = Gate.not_outside(ThickGateOx)
+GP_out_ThickGateOx = Gate.outside(ThickGateOx)
+size_Cont = Cont.ext_enlarge_inside(Act_connect, 6.0.um, 0.21.um)
 Cont_Act = Cont_SQ.ext_and(Activ)
 Cont_not_M1 = Cont_SQ.ext_not(Metal1)
 Cont_Act_GP = Cont_SQ.ext_and(Gate)
-CntB_a1_error = ContBar.ext_area([["&lt;", 0.16*0.34]])
+CntB_a1_error = ContBar.ext_with_area([["&lt;", (0.16*0.34).um2]])
 ContBar_GP = ContBar.ext_and(GatPoly)
 ContBar_Act = ContBar.ext_and(Activ)
 ContBar_not_M1 = ContBar.ext_not(Metal1)
 ContBar_Act_GP = ContBar.ext_and(Gate)
-nSD_drv = nSD.ext_or(Activ.ext_not(nSD_block.ext_or(pSD)))
+ContBar_outside_TRANS = ContBar.outside(TRANS)
+dschottky_1 = Activ_and_nSD_block.ext_and(nBuLay)
+dpin_0 = BasPoly.ext_and(Activ).ext_and(BiWind).ext_and(nSD_block)
+nSD_not_pSD = pSD_not_nSD.dup
+subst_tie_hole_w_npn = subst_tie_hole.ext_interacting_with_text(TEXT_0, "npn*")
+pSDL_enc_area = subst_tie_hole.ext_not(pSD)
 Act_SRAM = Activ.ext_not(Act_Nsram)
 pSD_SRAM = pSD.ext_not(pSD_Nsram)
+pSDHV_Nsram = pSD_Nsram.inside(ThickGateOx)
 GP_SRAM = GatPoly.ext_not(GP_Nsram)
-GP_Nsram_Gat_a = GP_Nsram.ext_fast_width(130, polygon_output: true)
-GP_Nsram_Gat_b = GP_Nsram.ext_fast_space(180, polygon_output: true)
+GP_Nsram_Gat_a = GP_Nsram.ext_fast_width(0.13.um, consider_intersecting_edges: false, polygon_output: true)
+GP_Nsram_Gat_b = GP_Nsram.ext_fast_space(0.18.um, consider_intersecting_edges: false, polygon_output: true)
+Cont_SRAM = Cont.ext_not(Cont_Nsram)
+V1_SRAM = Via1.ext_not(V1_Nsram)
+V1_Nsram_outside_EdgeSeal = V1_Nsram.outside(EdgeSeal)
 M1_SRAM = Metal1.ext_not(M1_Nsram)
 npnMPA_0 = nBuLay.ext_and(Activ.ext_and(SalBlock.ext_and(nSD_block)))
-lNw_a1_NW_a1 = lNw_a1.ext_fast_width(1800)
+V2_SRAM = Via2.ext_not(V2_Nsram)
+V2_Nsram_outside_EdgeSeal = V2_Nsram.outside(EdgeSeal)
+nBuLay_nBuLay_block_enc_tmp3 = nBuLay_nBuLay_block_enc_tmp + nBuLay_nBuLay_block_enc_tmp2
 Act_EdgeSeal_not_HRACT = Act_EdgeSeal.ext_not(Recog)
-Cont_not_Act_GP = Cont_SQ.ext_not(GP_or_Act).merged(true, 0).outside(TRANS)
-ContBar_not_Act_GP = ContBar.ext_not(GP_or_Act).merged(true, 0).outside(TRANS)
+Activ_edgA1_in = Act_EdgeSeal.dup
+Metal1_slit_not_pad = Metal1_slit.ext_not(pad)
+Metal2_slit_not_pad = Metal2_slit.ext_not(pad)
+Metal3_slit_not_pad = Metal3_slit.ext_not(pad)
+Metal4_slit_not_pad = Metal4_slit.ext_not(pad)
+Metal5_slit_not_pad = Metal5_slit.ext_not(pad)
+TopMetal1_slit_not_pad = TopMetal1_slit.ext_not(pad)
+TopMetal2_slit_not_pad = TopMetal2_slit.ext_not(pad)
+Recog_or_dfpad_all = Recog.ext_or(dfpad_all)
+Recog_or_MIM_or_dfpad_all = MIM.ext_or(Recog, dfpad_all)
+Iso_PWell_Act = Activ.ext_and(nBuLay).ext_not(X1)
+V3_SRAM = Via3.ext_not(V3_Nsram)
+V3_Nsram_outside_EdgeSeal = V3_Nsram.outside(EdgeSeal)
+V4_SRAM = Via4.ext_not(V4_Nsram)
+V4_Nsram_outside_EdgeSeal = V4_Nsram.outside(EdgeSeal)
+cmim_a = MIM.not_outside(Metal5).not_outside(TopMetal1).not_outside(Vmim)
+Metal5_slit_MIM_Slt_g_M5_sep_tmp3 = Metal5_slit.ext_with_coincident_edges(Metal5_slit_MIM_Slt_g_M5_sep_tmp2)
+nmoscl = nmoscl_2.ext_or(nmoscl_4)
+Rhigh_recognition_1 = Rhigh_recognition_0.ext_and(nSD)
+TopMetal1_slit_MIM_Slt_g_TM1_sep_tmp3 = TopMetal1_slit.ext_with_coincident_edges(TopMetal1_slit_MIM_Slt_g_TM1_sep_tmp2)
+temp_layer_1 = MIM.ext_covering(TopVia1_or_Vmim)
+temp_layer_6 = TopMetal2.ext_or(holes_TopMetal2)
+tsv = DeepVia.with_holes.ext_not(bad_tsv)
+Cont_not_Act_GP = Cont_SQ.ext_not(GP_or_Act).outside(TRANS)
+ContBar_not_Act_GP = ContBar.ext_not(GP_or_Act).outside(TRANS)
+nSD_drv = nSD.ext_or(Activ.ext_not(X2))
+X2_Extent = X2.ext_extents.sized(0.001.um, acute_limit)
 transG2 = TRANS.ext_interacting_with_text(TEXT_0, "npn13G2").ext_covering(emi2Pin)
+transG2C = TRANS.ext_interacting_with_text(TEXT_0, "npn13G2C").ext_covering(emi2Pin)
 transG2L = TRANS.ext_interacting_with_text(TEXT_0, "npn13G2L").ext_covering(emi2Pin)
 transG2V = TRANS.ext_interacting_with_text(TEXT_0, "npn13G2V").ext_covering(emi2Pin)
 nBuLayGen = nBuLayGen_sized.ext_not(nBuLay_block)
-nSDBlock_Iso_PWell_Act = nSD_block.merged(true, 0).not_outside(Iso_PWell_Act)
-SalBlock_Iso_PWell_Act = SalBlock.merged(true, 0).not_outside(Iso_PWell_Act)
-PWellBlock_relatedNWell = PWellBlock_relatedNWell_0.ext_or(NWell.merged(true, 0).inside(PWell_block))
-GP_mosHV_Gat_b1 = GP_mosHV.ext_fast_space(250, polygon_output: true)
-seal_passiv = selring_pass.ext_interacting(selring_pass.holes.merge.merged(true, 0).not_outside(sealring))
-NAct = Activ.ext_and(nSD_drv)
-pSD_nSD = pSD.ext_and(nSD_drv)
+ThickGateOx_Act_out_ThickGateOx_TGO_b_sep_tmp1 = ThickGateOx.ext_fast_separation(Act_out_ThickGateOx, 0.27.um, consider_intersecting_edges: false, consider_touch_points: false, polygon_output: true)
+ThickGateOx_Act_out_ThickGateOx_TGO_b_sep_tmp2 = Act_out_ThickGateOx.ext_coincident_edges(ThickGateOx, outside: true, consider_touch_points: true)
+ThickGateOx_Act_out_ThickGateOx_TGO_b_sep_tmp5 = ThickGateOx.ext_and(Act_out_ThickGateOx)
+PWellBlock_relatedNWell = PWellBlock_relatedNWell_0.ext_or(NWell.inside(PWell_block))
+Rppd_0 = GatPoly_res.ext_and(pSD).ext_and(SalBlock_not_nSDBlock_not_esd)
+tsv_fill = DeepVia.ext_or(tsv_tmp2).ext_not(bad_tsv)
+GP_mosHV_Gat_b1 = GP_mosHV.ext_fast_space(0.25.um, consider_intersecting_edges: false, polygon_output: true)
+ThickGateOx_GP_out_ThickGateOx_TGO_d_sep_tmp1 = ThickGateOx.ext_fast_separation(GP_out_ThickGateOx, 0.34.um, consider_intersecting_edges: false, consider_touch_points: false, polygon_output: true)
+ThickGateOx_GP_out_ThickGateOx_TGO_d_sep_tmp2 = GP_out_ThickGateOx.ext_coincident_edges(ThickGateOx, outside: true, consider_touch_points: true)
+ThickGateOx_GP_out_ThickGateOx_TGO_d_sep_tmp5 = ThickGateOx.ext_and(GP_out_ThickGateOx)
+dschottky_2 = dschottky_1.sized(1.12.um, acute_limit)
+seal_passiv = selring_pass.ext_interacting(selring_pass.holes.merge.not_outside(sealring))
+dpin_1 = dpin_0.sized(1.12.um, acute_limit)
+pSD_not_nSD_or_nSD_not_pSD = nSD_not_pSD.ext_or(pSD_not_nSD)
+pSDL_enc_area_pSD_l = pSDL_enc_area.ext_with_area([["&lt;", 0.25.um2]])
 DigiBnd_hole = DigiBnd.ext_or(DigiBnd_ring.holes.merge)
-GP_SRAM_Gat_a_SRAM = GP_SRAM.ext_fast_width(130, polygon_output: true)
-GP_SRAM_Gat_b_SRAM = GP_SRAM.ext_fast_space(149, polygon_output: true)
+GP_SRAM_Gat_a_SRAM = GP_SRAM.ext_fast_width(0.13.um, consider_intersecting_edges: false, polygon_output: true)
+GP_SRAM_Gat_b_SRAM = GP_SRAM.ext_fast_space(0.149.um, consider_intersecting_edges: false, polygon_output: true)
+V1_SRAM_outside_EdgeSeal = V1_SRAM.outside(EdgeSeal)
+M1_SRAM_outside_EdgeSeal = M1_SRAM.outside(EdgeSeal)
 npnMPA = npnMPA_0.ext_interacting_with_text(TEXT_0, "npnMPA")
-schottky_nbl_rec = nBuLay.ext_not(NWell).merged(true, 0).not_outside(SalBlock).merged(true, 0).not_outside(nSD_block).merged(true, 0).not_outside(Recog_diode).merged(true, 0).not_outside(ThickGateOx)
-emit_npn13G2 = EmWind.merged(true, 0).inside(transG2)
-emit_npn13G2L = EmWind.merged(true, 0).inside(transG2L)
-emit_npn13G2V = EmWind.merged(true, 0).inside(transG2V)
+V2_SRAM_outside_EdgeSeal = V2_SRAM.outside(EdgeSeal)
+nBuLay_nBuLay_block_enc_tmp6 = nBuLay_nBuLay_block_enc_tmp3.dup
+sltc_M1 = Metal1.ext_not(Recog_or_dfpad_all)
+sltc_M2 = Metal2.ext_not(Recog_or_dfpad_all)
+sltc_M3 = Metal3.ext_not(Recog_or_dfpad_all)
+sltc_M4 = Metal4.ext_not(Recog_or_dfpad_all)
+sltc_TM2 = TopMetal2.ext_not(Recog_or_dfpad_all)
+sltc_M5 = Metal5.ext_not(Recog_or_MIM_or_dfpad_all)
+sltc_TM1 = TopMetal1.ext_not(Recog_or_MIM_or_dfpad_all)
+nSDBlock_Iso_PWell_Act = nSD_block.not_outside(Iso_PWell_Act)
+SalBlock_Iso_PWell_Act = SalBlock.not_outside(Iso_PWell_Act)
+V3_SRAM_outside_EdgeSeal = V3_SRAM.outside(EdgeSeal)
+V4_SRAM_outside_EdgeSeal = V4_SRAM.outside(EdgeSeal)
+rfcmim_a = cmim_a.not_outside(PWell_block.ext_interacting_with_text(TEXT_0, "rfcmim"))
+Metal5_slit_MIM_Slt_g_M5_sep_tmp4 = Metal5_slit_MIM_Slt_g_M5_sep_tmp1 + Metal5_slit_MIM_Slt_g_M5_sep_tmp3
+Rhigh_recognition = Rhigh_recognition_1.ext_covering(GatPoly)
+TopMetal1_slit_MIM_Slt_g_TM1_sep_tmp4 = TopMetal1_slit_MIM_Slt_g_TM1_sep_tmp1 + TopMetal1_slit_MIM_Slt_g_TM1_sep_tmp3
+Rsil_all = GatPoly_res.ext_and(RES).ext_and(EXTBlock).ext_interacting(SalBlock, inverted: true)
+NAct = Activ.ext_and(nSD_drv)
+pSD_nSD = pSD.ext_and(nSD_drv)
+Y2 = X2_Extent.ext_not(X2)
+emit_npn13G2 = EmWind.inside(transG2)
+emit_npn13G2L = EmWind.inside(transG2L)
+trans_bip = transG2.ext_or(transG2C, transG2L, transG2V)
+emit_npn13G2V = EmWind.inside(transG2V)
 nBuLayGen_nBuLay = nBuLay.ext_or(nBuLayGen)
+schottky_nbl_rec = isoPWell.not_outside(SalBlock).not_outside(nSD_block).not_outside(Recog_diode).not_outside(ThickGateOx)
+ThickGateOx_Act_out_ThickGateOx_TGO_b_sep_tmp3 = ThickGateOx.ext_with_coincident_edges(ThickGateOx_Act_out_ThickGateOx_TGO_b_sep_tmp2)
 PWellBlock_unrelatedNWell = NWell.ext_not(PWellBlock_relatedNWell)
-NGate = Gate.merged(true, 0).not_outside(NAct)
+tsvOutRing = tsv_fill.ext_extents
+tsv_fill_TSV_G_d = tsv_fill.ext_fast_space(25.0.um, consider_intersecting_edges: false, polygon_output: true)
+ThickGateOx_GP_out_ThickGateOx_TGO_d_sep_tmp3 = ThickGateOx.ext_with_coincident_edges(ThickGateOx_GP_out_ThickGateOx_TGO_d_sep_tmp2)
+dschottky_3 = dschottky_2.ext_and(PWell_block)
+dpin = dpin_1.ext_and(PWell_block)
+Rppd_all = Rppd_0.ext_interacting(Activ.ext_or(nSD_drv), inverted: true)
+nBuLay_nBuLay_block_enc = nBuLay_nBuLay_block_enc_tmp6.dup
+Metal5_slit_MIM_Slt_g_M5_sep_tmp6 = Metal5_slit_MIM_Slt_g_M5_sep_tmp4 + Metal5_slit_MIM_Slt_g_M5_sep_tmp5
+Rhigh_identical_nsd_psd_edge = pSD_not_nSD_or_nSD_not_pSD.ext_coincident_part(Rhigh_recognition, outside: true)
+TopMetal1_slit_MIM_Slt_g_TM1_sep_tmp6 = TopMetal1_slit_MIM_Slt_g_TM1_sep_tmp4 + TopMetal1_slit_MIM_Slt_g_TM1_sep_tmp5
+rsil_gatpoly = GatPoly_res.not_outside(Rsil_all)
+Rsil_all_not_interact_NWell = Rsil_all.ext_interacting(NWell, inverted: true)
+NGate = Gate.not_outside(NAct)
 PAct = Activ.ext_not(NAct)
+PAct_connect = Act_connect.ext_not(NAct)
 NActLV = NAct.ext_not(ThickGateOx)
-NAct_NWell = NAct.ext_and(NWell.ext_or(PWell_block))
+NAct_NWell = NAct.ext_and(X1)
+sal_nActiv = NAct.ext_not(SalBlock)
 ContBar_NAct = ContBar.ext_and(NAct)
+Cont_not_outside_NAct = Cont.not_outside(NAct)
+nBuLayGen_nBuLay_NBL_a = nBuLayGen_nBuLay.ext_fast_width(1.0.um)
+ThickGateOx_Act_out_ThickGateOx_TGO_b_sep_tmp4 = ThickGateOx_Act_out_ThickGateOx_TGO_b_sep_tmp1 + ThickGateOx_Act_out_ThickGateOx_TGO_b_sep_tmp3
+rfcmim = PWell_block.not_outside(rfcmim_a).sized(0.65.um, acute_limit)
+PWell_block_tsvOutRing_enc_tmp = tsvOutRing.ext_fast_enclosed(PWell_block, 2.5.um, polygon_output: true)
+PWell_block_tsvOutRing_enc_tmp2 = tsvOutRing.ext_overlapping(PWell_block)
+Metal1_tsvOutRing_enc_tmp = tsvOutRing.ext_fast_enclosed(Metal1, 1.5.um, polygon_output: true)
+Metal1_tsvOutRing_enc_tmp2 = tsvOutRing.ext_overlapping(Metal1)
+ThickGateOx_GP_out_ThickGateOx_TGO_d_sep_tmp4 = ThickGateOx_GP_out_ThickGateOx_TGO_d_sep_tmp1 + ThickGateOx_GP_out_ThickGateOx_TGO_d_sep_tmp3
+dschottky = dschottky_3.ext_not(dpin)
+SalBlock_Rppd = SalBlock.ext_and(Rppd_all)
+Rppd_all_enclosure_pSD = Rppd_all.ext_fast_enclosed(pSD, 0.18.um, polygon_output: true)
 Rhigh_a = GatPoly_res.ext_and(pSD_nSD).ext_and(SalBlock_not_nSDBlock_not_esd)
-nBuLayGen_nBuLay_NBL_a = nBuLayGen_nBuLay.ext_fast_width(1000)
 schottky_nbl1_nw = NWell.ext_interacting(NWell.holes.merge.ext_covering(schottky_nbl_rec))
-PAct_NWell = PAct.ext_and(NWell.ext_or(PWell_block))
+schottky_nw1_rect = NWell.not_outside(nSD_block).ext_interacting(schottky_nbl_rec, inverted: true).ext_and(Recog_diode)
+Metal5_slit_MIM_Slt_g_M5_sep_tmp9 = Metal5_slit_MIM_Slt_g_M5_sep_tmp6.dup
+Rhigh_identical_nsd_psd = pSD_not_nSD_or_nSD_not_pSD.ext_with_coincident_edges(Rhigh_identical_nsd_psd_edge)
+TopMetal1_slit_MIM_Slt_g_TM1_sep_tmp9 = TopMetal1_slit_MIM_Slt_g_TM1_sep_tmp6.dup
+Rsil = Rsil_all_not_interact_NWell.ext_interacting(nBuLay, inverted: true)
+PGate = Gate.outside(NGate)
+PAct_NWell = PAct.ext_and(X1)
+ContBar_PAct = ContBar.ext_and(PAct)
+Cont_not_outside_PAct = Cont.not_outside(PAct)
 NActHV = NAct.ext_not(NActLV)
 NAct_PWell = NAct.ext_not(NAct_NWell)
-SVaricap_gate_0 = NGate.merged(true, 0).not_outside(NWell).merged(true, 0).not_outside(nBuLay)
+WellContDev = NAct_NWell.ext_interacting_with_text(TEXT_0, "well")
+NAct_NWell_not_Gate = NAct_NWell.ext_not(Gate)
+sal_nactive = sal_nActiv.dup
+Rppd_Cont = EXTBlock.ext_covering(Rppd_all).ext_and(Cont)
+n_tie = NWell.ext_and(Activ.ext_and(Y2)).ext_not(SalBlock)
+ThickGateOx_Act_out_ThickGateOx_TGO_b_sep_tmp6 = ThickGateOx_Act_out_ThickGateOx_TGO_b_sep_tmp4 + ThickGateOx_Act_out_ThickGateOx_TGO_b_sep_tmp5
+PWell_block_tsvOutRing_enc_tmp3 = PWell_block_tsvOutRing_enc_tmp + PWell_block_tsvOutRing_enc_tmp2
+Metal1_tsvOutRing_enc_tmp3 = Metal1_tsvOutRing_enc_tmp + Metal1_tsvOutRing_enc_tmp2
+ThickGateOx_GP_out_ThickGateOx_TGO_d_sep_tmp6 = ThickGateOx_GP_out_ThickGateOx_TGO_d_sep_tmp4 + ThickGateOx_GP_out_ThickGateOx_TGO_d_sep_tmp5
+SVaricap_gate_0 = NGate.not_outside(NWell).not_outside(nBuLay)
+GP_Rhigh_extended = GatPoly_res.ext_covering(Rhigh_a)
 SalBlock_Rhigh = SalBlock.ext_and(Rhigh_a)
-schottky_nbl1 = schottky_nbl1_nw.merged(true, 0).size(1.36, acute_limit).merge(true, 0)
+schottky_nbl1 = schottky_nbl1_nw.sized(1.36.um, acute_limit)
+Metal5_slit_MIM_Slt_g_M5_sep_tmp11 = Metal5_slit_MIM_Slt_g_M5_sep_tmp9.dup
+TopMetal1_slit_MIM_Slt_g_TM1_sep_tmp11 = TopMetal1_slit_MIM_Slt_g_TM1_sep_tmp9.dup
+GP_Rsil_extended = GatPoly_res.ext_covering(Rsil)
 PAct_PWell = PAct.ext_not(PAct_NWell)
-NActHV_digi = NActHV.merged(true, 0).not_outside(DigiBnd_hole)
-SVaricap_text = Activ.merged(true, 0).not_outside(SVaricap_gate_0).ext_interacting_with_text(TEXT_0, "SVaricap")
+Abut_NWell_Tie_Edge = NAct_NWell.ext_coincident_part(PAct_NWell, outside: true)
+MVaricap = PWell_block.ext_and(NWell.sized(1.0.um, acute_limit)).not_outside(GatPoly).not_outside(nBuLay).not_outside(PAct).not_outside(NAct).ext_interacting_with_text(TEXT_0, "MVaricap")
+NActHV_digi = NActHV.not_outside(DigiBnd_hole)
+abut_tie_edge_NWell = NAct_NWell_not_Gate.ext_coincident_part(PAct_NWell, outside: true)
+ntaparea = sal_nactive.ext_and(NWell)
+Rhigh_Cont = EXTBlock.ext_covering(Rhigh_a).ext_and(Cont)
+hard_n_tie = n_tie.ext_covering(Cont)
+schottky_nw1_sized = schottky_nw1_rect.sized(1.36.um, acute_limit).ext_and(ThickGateOx)
+ThickGateOx_Act_out_ThickGateOx_TGO_b_sep_tmp9 = ThickGateOx_Act_out_ThickGateOx_TGO_b_sep_tmp6.dup
+PWell_block_tsvOutRing_enc_tmp6 = PWell_block_tsvOutRing_enc_tmp3.dup
+Metal1_tsvOutRing_enc_tmp6 = Metal1_tsvOutRing_enc_tmp3.dup
+ThickGateOx_GP_out_ThickGateOx_TGO_d_sep_tmp9 = ThickGateOx_GP_out_ThickGateOx_TGO_d_sep_tmp6.dup
+SVaricap_poly = GatPoly.not_outside(SVaricap_gate_0)
+NWell_Tie = NAct_NWell.ext_not(WellContDev.ext_or(SalBlock.ext_or(TRANS)))
+schottky_pwb = schottky_nbl1.ext_and(PWell_block)
+schottky_nSDBlock = schottky_nbl1.ext_and(nSD_block)
+schottky_salblock = schottky_nbl1.ext_and(SalBlock)
+schottky_contbar = schottky_nbl1.ext_and(ContBar)
+scr1_or_schottky_nbl1 = schottky_nbl1.ext_or(scr1)
+Metal5_slit_MIM_Slt_g_M5_sep = Metal5_slit_MIM_Slt_g_M5_sep_tmp11.dup
+TopMetal1_slit_MIM_Slt_g_TM1_sep = TopMetal1_slit_MIM_Slt_g_TM1_sep_tmp11.dup
+GP_Rsil_extended_external_pSD = GP_Rsil_extended.ext_fast_separation(pSD, 0.18.um)
+SVaricap_text = Activ.not_outside(SVaricap_gate_0).ext_interacting_with_text(TEXT_0, "SVaricap")
 PAct_PWellLV = PAct_PWell.ext_not(ThickGateOx)
+cmim_tie = PAct_PWell.not_outside(rfcmim)
+Abut_PWell_Tie_Edge = PAct_PWell.ext_coincident_part(NAct_PWell, outside: true)
+BJT_ring_a = PAct_PWell.with_holes
+PAct_PWell_not_Gate = PAct_PWell.ext_not(Gate)
+Abut_NWell_Tie = NAct_NWell.ext_with_coincident_edges(Abut_NWell_Tie_Edge)
 NActHV_ana = NActHV.ext_not(NActHV_digi)
-SVaricap = NWell.merged(true, 0).not_outside(SVaricap_text)
+soft_n_tie = n_tie.ext_not(hard_n_tie)
+schottky_nbl1_b = PAct_connect.not_outside(schottky_nbl1).ext_not(schottky_nbl1)
+schottky_nw1 = schottky_nw1_sized.ext_interacting_with_text(TEXT_0, "schottky_nw1")
+ThickGateOx_Act_out_ThickGateOx_TGO_b_sep_tmp11 = ThickGateOx_Act_out_ThickGateOx_TGO_b_sep_tmp9.dup
+PWell_block_tsvOutRing_enc = PWell_block_tsvOutRing_enc_tmp6.dup
+Metal1_tsvOutRing_enc = Metal1_tsvOutRing_enc_tmp6.dup
+ThickGateOx_GP_out_ThickGateOx_TGO_d_sep_tmp11 = ThickGateOx_GP_out_ThickGateOx_TGO_d_sep_tmp9.dup
+MOSvaricap = MVaricap.ext_or(SVaricap_poly)
+SubContDev_basic = PAct_PWell.ext_interacting_with_text(TEXT_0, "sub!").ext_not(Recog_esd)
+NwellRing_innermost = NWell_Tie.holes.merge.outside(NWell_Tie)
+ntap = ntaparea.ext_covering(Cont.ext_and(ntaparea))
+SVaricap = NWell.not_outside(SVaricap_text)
 PAct_PWellHV = PAct_PWell.ext_not(PAct_PWellLV)
-PAct_PWellHV_digi = PAct_PWellHV.merged(true, 0).not_outside(DigiBnd_hole)
+Abut_PWell_Tie = PAct_PWell.ext_with_coincident_edges(Abut_PWell_Tie_Edge)
+abut_tie_edge_PWell = PAct_PWell_not_Gate.ext_coincident_part(NAct_PWell, outside: true)
+Abut_NWell_Tie_PAct = PAct.ext_interacting(Abut_NWell_Tie)
+nsdb_exlcDev = dschottky.ext_or(schottky_nbl1, schottky_nw1, trans_bip)
+schottky_nbl1_or_schottky_nw1 = schottky_nbl1.ext_or(schottky_nw1)
+ThickGateOx_Act_out_ThickGateOx_TGO_b_sep = ThickGateOx_Act_out_ThickGateOx_TGO_b_sep_tmp11.dup
+ThickGateOx_GP_out_ThickGateOx_TGO_d_sep = ThickGateOx_GP_out_ThickGateOx_TGO_d_sep_tmp11.dup
+SubContDev = SubContDev_basic.ext_interacting(nBuLay, inverted: true)
+SubContDev_iso = SubContDev_basic.not_outside(nBuLay)
+PGate_inside_NwellRing = PGate.not_outside(NwellRing_innermost)
+NwellRing_edge = NWell_Tie.ext_coincident_part(NwellRing_innermost, outside: true)
+all_ntie = ntap.ext_or(soft_n_tie)
+schottky_nw1_b = PAct_connect.not_outside(schottky_nw1).ext_not(schottky_nw1)
+pSD_c_tmp1 = pSD.outside(SVaricap)
+devExclud = Recog_diode.ext_or(SVaricap, nmoscl_2, nmoscl_4, npnMPA, schottky_nbl1, scr1, subst_tie_hole_w_npn, trans_bip)
+SVaricap_or_schottky_nbl1 = SVaricap.ext_or(schottky_nbl1)
+NGate_outside_SVaricap = NGate.outside(SVaricap)
+PAct_PWellHV_digi = PAct_PWellHV.not_outside(DigiBnd_hole)
+Abut_PWell_Tie_NAct = NAct.ext_interacting(Abut_PWell_Tie)
+Abut_NWell_Tie_Cont = Cont.inside(Abut_NWell_Tie_PAct)
+SVaricap_Tie = PAct_PWell.not_outside(Activ.not_outside(SVaricap))
+NwellRing = NWell_Tie.ext_with_coincident_edges(NwellRing_edge)
+PAct_PWellHV_ana = PAct_PWellHV.ext_not(PAct_PWellHV_digi)
+Abut_PWell_Tie_Cont = Cont.inside(Abut_PWell_Tie_NAct)
+PWell_Tie_w_rf = PAct_PWell.ext_not(Recog_esd.ext_or(SalBlock, SubContDev, SubContDev_iso, cmim_tie, schottky_nbl1, schottky_nbl1_b, schottky_nw1, schottky_nw1_b))
+Holes_NwellRing = NwellRing.holes.merge
+PwellRing_innermost = PWell_Tie_w_rf.holes.merge.outside(PWell_Tie_w_rf)
+NoHoles_NwellRing = Holes_NwellRing.ext_or(NwellRing)
+NGate_inside_PwellRing = NGate.not_outside(PwellRing_innermost)
+PwellRing_edge = PWell_Tie_w_rf.ext_coincident_part(PwellRing_innermost, outside: true)
+rfNwellRing = NoHoles_NwellRing.ext_interacting_with_text(TEXT_0, "rfpmos*")
+PwellRing = PWell_Tie_w_rf.ext_with_coincident_edges(PwellRing_edge)
+rfpmos_all = PGate_inside_NwellRing.not_outside(rfNwellRing)
+Holes_PwellRing = PwellRing.holes.merge
+NoHoles_PwellRing = Holes_PwellRing.ext_or(PwellRing)
+pmosHV = PGate.ext_or(rfpmos_all).ext_not(MOSvaricap).not_outside(ThickGateOx)
+rfPwellRing = NoHoles_PwellRing.ext_interacting_with_text(TEXT_0, "rfnmos*")
+pnpMPARing = NoHoles_PwellRing.ext_interacting_with_text(TEXT_0, "pnpMPA")
+rfnmos_all = NGate_inside_PwellRing.not_outside(rfPwellRing)
+pnpMPA = PAct_NWell.not_outside(nBuLay).not_outside(pnpMPARing)
+BJT_hole = (BJT_ring_a.holes - BJT_ring_a.with_holes).without_holes.ext_covering(TRANS.ext_or(pnpMPA))
+nmosHV = NGate.ext_or(rfnmos_all).ext_not(MOSvaricap).not_outside(ThickGateOx)
+BJT_ring = BJT_ring_a.ext_interacting(BJT_hole)
+PWell_Tie_wo_varicap_abut = PAct_PWell.ext_interacting(Abut_PWell_Tie.ext_or(BJT_ring, SVaricap_Tie), inverted: true)
 -&gt; do
     NWell_NW_a.dup
-end.().output("NW.a", "Min. NWell width")
+end.().output("NW.a", "Min. NWell width = 0.62")
+-&gt; do
+    NWell.ext_fast_separation(NActHV_ana, 0.62.um)
+end.().output("NW.d1", "Min. NWell space to external N+Activ inside ThickGateOx = 0.62")
+-&gt; (;x, y) do
+    x = PAct_PWellLV.ext_coincident_edges(SVaricap, outside: true)
+    y = PAct_PWellLV.ext_with_coincident_edges(x)
+    NWell.ext_fast_separation(PAct_PWellLV.ext_not(y), 0.24.um)
+end.().output("NW.f", "Min. NWell space to substrate tie in P+Activ not inside ThickGateOx = 0.24")
 -&gt; do
-    NWell.ext_fast_separation(NActHV_ana, 620)
-end.().output("NW.d1", "Min. NWell space to external N+Activ inside ThickGateOx")
+    NWell.ext_fast_separation(PAct_PWellHV_ana.ext_interacting(SVaricap, inverted: true), 0.62.um)
+end.().output("NW.f1", "Min. NWell space to substrate tie in P+Activ inside ThickGateOx = 0.62")
 -&gt; do
     PWell_block_PWB_a.dup
-end.().output("PWB.a", "Min. PWell:block width")
+end.().output("PWB.a", "Min. PWell:block width = 0.62")
 -&gt; do
     PWell_block_PWB_b.dup
-end.().output("PWB.b", "Min. PWell:block space or notch")
+end.().output("PWB.b", "Min. PWell:block space or notch = 0.62")
 -&gt; do
-    PWellBlock_unrelatedNWell.ext_fast_separation(PWell_block, 620)
-end.().output("PWB.c", "Min. PWell:block space to unrelated NWell")
+    PWellBlock_unrelatedNWell.ext_fast_separation(PWell_block, 0.62.um, consider_touch_points: false, include_min_angle: false)
+end.().output("PWB.c", "Min. PWell:block space to unrelated NWell = 0.62")
 -&gt; do
     nBuLayGen_nBuLay_NBL_a.dup
-end.().output("NBL.a", "Min. nBuLay width")
+end.().output("NBL.a", "Min. nBuLay width = 1.00")
 -&gt; do
     nBuLay_block_NBLB_a.dup
-end.().output("NBLB.a", "Min. nBuLay:block width")
+end.().output("NBLB.a", "Min. nBuLay:block width = 1.50")
 -&gt; do
-    nBuLay_block.ext_fast_space(1000)
-end.().output("NBLB.b", "Min. nBuLay:block space or notch")
+    nBuLay_block.ext_fast_space(1.0.um)
+end.().output("NBLB.b", "Min. nBuLay:block space or notch = 1.00")
 -&gt; do
-    nBuLay_block.ext_fast_separation(nBuLay, 1500)
-end.().output("NBLB.d", "Min. nBuLay:block space to unrelated nBuLay")
+    nBuLay_nBuLay_block_enc.dup
+end.().output("NBLB.c", "Min. nBuLay enclosure of nBuLay:block = 1.00")
+-&gt; do
+    nBuLay_block.ext_fast_separation(nBuLay, 1.5.um, consider_touch_points: false)
+end.().output("NBLB.d", "Min. nBuLay:block space to unrelated nBuLay = 1.50")
 -&gt; do
     Activ_Act_a.dup
-end.().output("Act.a", "Min. Activ width")
+end.().output("Act.a", "Min. Activ width = 0.15")
 -&gt; do
-    Act_Nsram.ext_fast_space(210)
-end.().output("Act.b", "Min. Activ space or notch")
+    Act_Nsram.ext_fast_space(0.21.um)
+end.().output("Act.b", "Min. Activ space or notch = 0.21")
 -&gt; do
     Activ_Act_d.dup
-end.().output("Act.d", "Min. Activ area (µm²)")
+end.().output("Act.d", "Min. Activ area (µm²) = 0.122")
+-&gt; do
+    (Activ.holes - Activ.with_holes).without_holes.ext_not(Activ).ext_with_area([["&lt;", 0.15.um2]])
+end.().output("Act.e", "Min. Activ enclosed area (µm²) = 0.15")
 
 if $filler
 	-&gt; do
-	    Activ_filler.drc((width(projection) &gt; 5000).polygons)
-	end.().output("AFil.a", "Max. Activ:filler width")
+	    Activ_filler.drc((width(projection) &gt; 5.0.um).polygons)
+	end.().output("AFil.a", "Max. Activ:filler width = 5.00")
 	-&gt; do
-	    Activ_filler.ext_fast_width(1000)
-	end.().output("AFil.a1", "Min. Activ:filler width")
+	    Activ_filler.ext_fast_width(1.0.um)
+	end.().output("AFil.a1", "Min. Activ:filler width = 1.00")
 	-&gt; do
-	    Activ_filler.ext_fast_space(1000)
-	end.().output("AFil.b", "Min. Activ:filler space")
+	    Activ_filler.ext_fast_space(0.42.um)
+	end.().output("AFil.b", "Min. Activ:filler space = 0.42")
 end
 
 
 if $density
 	-&gt; do
 	    Act_density.ext_with_density(0.0 .. 0.35, 'll')
-	end.().output("AFil.g", "Min. global Activ density [%]")
+	end.().output("AFil.g", "Min. global Activ density [%] = 35.00")
 	-&gt; do
 	    Act_density.ext_with_density(0.55 .. 1.0, 'll')
-	end.().output("AFil.g1", "Max. global Activ density [%]")
+	end.().output("AFil.g1", "Max. global Activ density [%] = 55.00")
 	-&gt; do
-	    Act_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0), tile_step(400.0))
-	end.().output("AFil.g2", "Min. Activ coverage ratio for any 800 x 800 µm² chip area [%]")
+	    Act_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0.um), tile_step(400.0.um))
+	end.().output("AFil.g2", "Min. Activ coverage ratio for any 800 x 800 µm² chip area [%] = 25.00")
 	-&gt; do
-	    Act_density.ext_with_density(0.65 .. 1.0, 'll', tile_size(800.0), tile_step(400.0))
-	end.().output("AFil.g3", "Max. Activ coverage ratio for any 800 x 800 µm² chip area [%]")
+	    Act_density.ext_with_density(0.65 .. 1.0, 'll', tile_size(800.0.um), tile_step(400.0.um))
+	end.().output("AFil.g3", "Max. Activ coverage ratio for any 800 x 800 µm² chip area [%] = 65.00")
 end
 
+-&gt; do
+    Activ.ext_fast_enclosed(ThickGateOx, 0.27.um, polygon_output: true)
+end.().output("TGO.a", "Min. ThickGateOx extension over Activ = 0.27")
+-&gt; do
+    ThickGateOx_Act_out_ThickGateOx_TGO_b_sep.dup
+end.().output("TGO.b", "Min. space between ThickGateOx and Activ outside thick gate oxide region = 0.27")
+-&gt; (;a) do
+    a = Gate.ext_fast_enclosed(ThickGateOx, 0.34.um, polygon_output: true)
+    a.ext_and(Activ)
+end.().output("TGO.c", "Min. ThickGateOx extension over GatPoly over Activ = 0.34")
+-&gt; do
+    ThickGateOx_GP_out_ThickGateOx_TGO_d_sep.dup
+end.().output("TGO.d", "Min. space between ThickGateOx and GatPoly over Activ outside thick gate oxide region = 0.34")
 -&gt; do
     ThickGateOx_TGO_e.dup
-end.().output("TGO.e", "Min. ThickGateOx space (merge if less than this value)")
+end.().output("TGO.e", "Min. ThickGateOx space (merge if less than this value) = 0.86")
 -&gt; do
     ThickGateOx_TGO_f.dup
-end.().output("TGO.f", "Min. ThickGateOx width")
+end.().output("TGO.f", "Min. ThickGateOx width = 0.86")
 -&gt; do
     GP_Nsram_Gat_a.dup
-end.().output("Gat.a", "Min. GatPoly width")
+end.().output("Gat.a", "Min. GatPoly width = 0.13")
+-&gt; (;a) do
+    a = Activ.ext_not(nmosHV).ext_interacting(nmosHV).ext_fast_space(0.45.um, metric: projection, consider_touch_points: false, include_max_angle: true, polygon_output: true)
+    a.ext_and(Activ).outside(nmoscl.ext_or(scr1))
+end.().output("Gat.a3", "Min. GatPoly width for channel length of 3.3 V NFET = 0.45")
+-&gt; (;b) do
+    b = Activ.ext_not(pmosHV).ext_interacting(pmosHV).ext_fast_space(0.4.um, metric: projection, consider_touch_points: false, include_max_angle: true, polygon_output: true)
+    b.ext_and(Activ)
+end.().output("Gat.a4", "Min. GatPoly width for channel length of 3.3 V PFET = 0.4")
 -&gt; do
     GP_Nsram_Gat_b.dup
-end.().output("Gat.b", "Min. GatPoly space or notch")
+end.().output("Gat.b", "Min. GatPoly space or notch = 0.18")
 -&gt; do
     GP_mosHV_Gat_b1.dup
-end.().output("Gat.b1", "Min. space between unrelated 3.3 V GatPoly over Activ regions")
+end.().output("Gat.b1", "Min. space between unrelated 3.3 V GatPoly over Activ regions = 0.25")
 -&gt; do
-    GP_Nsram.ext_fast_separation(Act_Nsram, 70)
-end.().output("Gat.d", "Min. GatPoly space to Activ")
+    [ Activ.ext_fast_enclosed(GP_Nsram, 0.18.um, polygon_output: true),
+      Activ.ext_fast_enclosed(GatPoly_filler, 0.18.um, polygon_output: true),
+      GatPoly.inside(Activ)
+    ].each { |result| result.output("Gat.c", "Min. GatPoly extension over Activ (end cap) = 0.18") }
+end.()
+-&gt; do
+    GP_Nsram.ext_fast_separation(Act_Nsram, 0.07.um)
+end.().output("Gat.d", "Min. GatPoly space to Activ = 0.07")
 -&gt; do
     GatPoly_Gat_e.dup
-end.().output("Gat.e", "Min. GatPoly area (µm²)")
+end.().output("Gat.e", "Min. GatPoly area (µm²) = 0.09")
 -&gt; do
-    GatPoly.ext_and(Activ).ext_not(SVaricap).ext_rectangles(true, false, nil, nil, nil, inverted: true)
+    Gate.ext_not(SVaricap).ext_rectangles(true, false, nil, nil, nil, inverted: true)
 end.().output("Gat.f", "45-degree and 90-degree angles for GatPoly on Activ area are not allowed")
 
 if $filler
 	-&gt; do
-	    GatPoly_filler.drc((width(projection) &gt; 5000).polygons)
-	end.().output("GFil.a", "Max. GatPoly:filler width")
+	    GatPoly_filler.drc((width(projection) &gt; 5.0.um).polygons)
+	end.().output("GFil.a", "Max. GatPoly:filler width = 5.00")
 	-&gt; do
-	    GatPoly_filler.ext_fast_width(700)
-	end.().output("GFil.b", "Min. GatPoly:filler width")
+	    GatPoly_filler.ext_fast_width(0.7.um, consider_touch_points: false)
+	end.().output("GFil.b", "Min. GatPoly:filler width = 0.70")
 	-&gt; do
-	    GatPoly_filler.ext_fast_space(800)
-	end.().output("GFil.c", "Min. GatPoly:filler space")
+	    GatPoly_filler.ext_fast_space(0.8.um)
+	end.().output("GFil.c", "Min. GatPoly:filler space = 0.80")
 	-&gt; do
-	    Activ.ext_fast_separation(GatPoly_filler, 1100)
-	end.().output("GFil.d.Activ", "Min. GatPoly:filler space to Activ")
+	    Activ.ext_fast_separation(GatPoly_filler, 1.1.um, max_angle: 180)
+	end.().output("GFil.d.Activ", "Min. GatPoly:filler space to Activ = 1.10")
 	-&gt; do
-	    GatPoly.ext_fast_separation(GatPoly_filler, 1100)
-	end.().output("GFil.d.GatPoly", "Min. GatPoly:filler space to GatPoly")
+	    GatPoly.ext_fast_separation(GatPoly_filler, 1.1.um, max_angle: 180)
+	end.().output("GFil.d.GatPoly", "Min. GatPoly:filler space to GatPoly = 1.10")
 	-&gt; do
-	    Cont.ext_fast_separation(GatPoly_filler, 1100)
-	end.().output("GFil.d.Cont", "Min. GatPoly:filler space to Cont")
+	    Cont.ext_fast_separation(GatPoly_filler, 1.1.um, max_angle: 180)
+	end.().output("GFil.d.Cont", "Min. GatPoly:filler space to Cont = 1.10")
 	-&gt; do
-	    pSD.ext_fast_separation(GatPoly_filler, 1100)
-	end.().output("GFil.d.pSD", "Min. GatPoly:filler space to pSD")
+	    pSD.ext_fast_separation(GatPoly_filler, 1.1.um, max_angle: 180)
+	end.().output("GFil.d.pSD", "Min. GatPoly:filler space to pSD = 1.10")
 	-&gt; do
-	    nSD_block.ext_fast_separation(GatPoly_filler, 1100)
-	end.().output("GFil.d.nSD_block", "Min. GatPoly:filler space to nSD:block")
+	    nSD_block.ext_fast_separation(GatPoly_filler, 1.1.um, max_angle: 180)
+	end.().output("GFil.d.nSD_block", "Min. GatPoly:filler space to nSD:block = 1.10")
 	-&gt; do
-	    SalBlock.ext_fast_separation(GatPoly_filler, 1100)
-	end.().output("GFil.d.SalBlock", "Min. GatPoly:filler space to SalBlock")
+	    SalBlock.ext_fast_separation(GatPoly_filler, 1.1.um, max_angle: 180)
+	end.().output("GFil.d.SalBlock", "Min. GatPoly:filler space to SalBlock = 1.10")
 	-&gt; do
-	    GatPoly_filler.ext_fast_separation(TRANS, 1100)
-	end.().output("GFil.f", "Min. GatPoly:filler space to TRANS")
+	    GatPoly_filler.ext_fast_separation(TRANS, 1.1.um)
+	end.().output("GFil.f", "Min. GatPoly:filler space to TRANS = 1.10")
 end
 
 
 if $density
 	-&gt; do
 	    Gat_density.ext_with_density(0.0 .. 0.15, 'll')
-	end.().output("GFil.g", "Min. global GatPoly density [%]")
+	end.().output("GFil.g", "Min. global GatPoly density [%] = 15.00")
 end
 
 
 if $filler
 	-&gt; do
-	    GatPoly_nofill.ext_fast_space(20000)
-	end.().output("GFil.j", "Min. GatPoly:filler extension over Activ:filler (end cap)")
+	    GatPoly_nofill.ext_fast_space(20.um)
+	end.().output("GFil.j", "Min. GatPoly:filler extension over Activ:filler (end cap) = 0.18")
 end
 
 -&gt; do
     pSD_pSD_a.dup
-end.().output("pSD.a", "Min. pSD width")
+end.().output("pSD.a", "Min. pSD width = 0.31")
+-&gt; do
+    pSD.ext_fast_space(0.31.um)
+end.().output("pSD.b", "Min. pSD space or notch (Note 1) = 0.31")
 -&gt; do
-    pSD.ext_fast_space(310)
-end.().output("pSD.b", "Min. pSD space or notch (Note 1)")
+    Act_NWell.ext_fast_enclosed(pSD_c_tmp1, 0.18.um, polygon_output: true)
+end.().output("pSD.c", "Min. pSD enclosure of P+Activ in NWell = 0.18")
 -&gt; do
-    pSD.ext_fast_separation(NAct_PWell, 180)
-end.().output("pSD.d", "Min. pSD space to unrelated N+Activ in PWell")
+    pSD.ext_fast_separation(NAct_PWell, 0.18.um, consider_intersecting_edges: false)
+end.().output("pSD.d", "Min. pSD space to unrelated N+Activ in PWell = 0.18")
 -&gt; do
-    pSD.ext_fast_separation(NAct_NWell, 30)
-end.().output("pSD.d1", "Min. pSD space to N+Activ in NWell")
+    pSD.ext_fast_separation(NAct_NWell, 0.03.um, consider_intersecting_edges: false)
+end.().output("pSD.d1", "Min. pSD space to N+Activ in NWell = 0.03")
 -&gt; (;layA, layB, layC, layD) do
-    layA = Activ.ext_not(SRAM).merged(true, 0).not_inside(pSD).ext_interacting(pSD)
-    layB = layA.ext_and(pSD).merged(true, 0).outside(SVaricap)
-    layC = layB.ext_fast_width(300, polygon_output: true)
+    layA = Act_Nsram.not_inside(pSD).ext_interacting(pSD)
+    layB = layA.ext_and(pSD).outside(SVaricap)
+    layC = layB.ext_fast_width(0.3.um, metric: projection, consider_intersecting_edges: false, consider_touch_points: false, polygon_output: true)
     layD = layC.ext_covering(layB)
     layD.dup
-end.().output("pSD.e", "Min. pSD overlap of Activ at one position when forming abutted substrate tie (Note 2)")
+end.().output("pSD.e", "Min. pSD overlap of Activ at one position when forming abutted substrate tie (Note 2) = 0.30")
+-&gt; (;abuttedNTAP, bad_region, good_region) do
+    abuttedNTAP = NAct_NWell.ext_interacting(PAct_NWell)
+    bad_region = abuttedNTAP.ext_coincident_part(PAct_NWell, outside: true).ext_fast_overlap(NAct_NWell, 0.3.um, metric: projection, consider_intersecting_edges: false, consider_touch_points: false, polygon_output: true)
+    good_region = abuttedNTAP.ext_not(bad_region)
+    abuttedNTAP.outside(good_region)
+end.().output("pSD.f", "Min. Activ extension over pSD at one position when forming abutted NWell tie (Note 2) = 0.30")
+-&gt; (;x, y) do
+    x = NAct_NWell_not_Gate.ext_interacting(SVaricap_or_schottky_nbl1, inverted: true).outside(SRAM)
+    y = PAct_PWell_not_Gate.ext_interacting(SVaricap_or_schottky_nbl1, inverted: true).outside(SRAM)
+    [ x.ext_interacting(Gate, inverted: true).ext_with_area([["&lt;", 0.09.um2]]),
+      y.ext_interacting(Gate, inverted: true).ext_with_area([["&lt;", 0.09.um2]])
+    ].each { |result| result.output("pSD.g", "Min. N+Activ or P+Activ area (µm²) when forming abutted tie (Note 2) = 0.09") }
+end.()
+-&gt; do
+    PGate.ext_fast_enclosed(pSD_Nsram, 0.3.um, polygon_output: true)
+end.().output("pSD.i", "Min. pSD enclosure of PFET gate not inside ThickGateOx = 0.30")
+-&gt; do
+    PGate.ext_fast_enclosed(pSDHV_Nsram, 0.4.um, polygon_output: true)
+end.().output("pSD.i1", "Min. pSD enclosure of PFET gate inside ThickGateOx = 0.40")
+-&gt; do
+    pSD_Nsram.ext_fast_separation(NGate_outside_SVaricap, 0.3.um)
+end.().output("pSD.j", "Min. pSD space to NFET gate not inside ThickGateOx = 0.30")
+-&gt; do
+    pSD_Nsram.ext_fast_separation(NGate_outside_SVaricap.inside(ThickGateOx), 0.4.um)
+end.().output("pSD.j1", "Min. pSD space to NFET gate inside ThickGateOx = 0.40")
 -&gt; do
-    pSD_Nsram.ext_fast_separation(NGate.merged(true, 0).outside(SVaricap), 300)
-end.().output("pSD.j", "Min. pSD space to NFET gate not inside ThickGateOx")
+    pSD_pSD_k.dup
+end.().output("pSD.k", "Min. pSD area (µm²) = 0.25")
 -&gt; do
-    pSD_Nsram.ext_fast_separation(NGate.merged(true, 0).outside(SVaricap).merged(true, 0).inside(ThickGateOx), 400)
-end.().output("pSD.j1", "Min. pSD space to NFET gate inside ThickGateOx")
+    pSDL_enc_area_pSD_l.dup
+end.().output("pSD.l", "Min. pSD enclosed area (µm²) = 0.25")
 -&gt; do
-    pSD_pSD_k.dup
-end.().output("pSD.k", "Min. pSD area (µm²)")
+    GP_Rsil_extended_external_pSD.dup
+end.().output("pSD.m", "Min. pSD space to n-type poly resistors = 0.18")
+-&gt; do
+    Rppd_all_enclosure_pSD.dup
+end.().output("pSD.n", "Min. pSD enclosure of p-type poly resistors = 0.18")
 -&gt; do
-    nSD_block.ext_fast_width(310)
-end.().output("nSDB.a", "Min. nSD:block width")
+    nSD_block.ext_fast_width(0.31.um)
+end.().output("nSDB.a", "Min. nSD:block width = 0.31")
 -&gt; do
-    nSD_block.ext_fast_space(310)
-end.().output("nSDB.b", "Min. nSD:block space or notch")
+    nSD_block.ext_fast_space(0.31.um)
+end.().output("nSDB.b", "Min. nSD:block space or notch = 0.31")
 -&gt; do
-    EXTBlock.ext_fast_width(310)
-end.().output("EXT.a", "Min. EXTBlock width")
+    nSD_block.ext_fast_separation(pSD.ext_interacting(nSD_block, inverted: true), 0.31.um, consider_touch_points: false)
+end.().output("nSDB.c", "Min. nSD:block space to unrelated pSD = 0.31")
 -&gt; do
-    EXTBlock.ext_fast_space(310)
-end.().output("EXT.b", "Min. EXTBlock space or notch")
+    Cont.outside(nsdb_exlcDev).ext_and(nSD_block)
+end.().output("nSDB.e", "Min. nSD:block space to Cont (Note 2) = 0.00")
 -&gt; do
-    EXTBlock.ext_fast_separation(pSD, 310)
-end.().output("EXT.c", "Min. EXTBlock space to pSD")
+    EXTBlock.ext_fast_width(0.31.um)
+end.().output("EXT.a", "Min. EXTBlock width = 0.31")
 -&gt; do
-    SalBlock.ext_fast_width(420)
-end.().output("Sal.a", "Min. SalBlock width")
+    EXTBlock.ext_fast_space(0.31.um)
+end.().output("EXT.b", "Min. EXTBlock space or notch = 0.31")
 -&gt; do
-    SalBlock.ext_fast_space(420)
-end.().output("Sal.b", "Min. SalBlock space or notch")
+    EXTBlock.ext_fast_separation(pSD, 0.31.um)
+end.().output("EXT.c", "Min. EXTBlock space to pSD = 0.31")
 -&gt; do
-    SalBlock.ext_fast_separation(GatPoly.ext_or(PolyRes), 200)
-    SalBlock.ext_fast_separation(Activ.ext_or(Activ_mask), 200)
-end.().output("Sal.d", "Min. SalBlock space to unrelated Activ or GatPoly")
+    SalBlock.ext_fast_width(0.42.um)
+end.().output("Sal.a", "Min. SalBlock width = 0.42")
 -&gt; do
-    SalBlock.ext_fast_separation(Cont, 200)
-end.().output("Sal.e", "Min. SalBlock space to Cont")
+    SalBlock.ext_fast_space(0.42.um)
+end.().output("Sal.b", "Min. SalBlock space or notch = 0.42")
 -&gt; do
-    Cont.merged(true, 0).outside(EdgeSeal).ext_not(ContBar.ext_or(Cont_SQ))
-end.().output("Cnt.a", "Min. and max. Cont width")
+    [ GatPoly_res.ext_fast_enclosed(SalBlock, 0.2.um, polygon_output: true),
+      Activ.ext_fast_enclosed(SalBlock, 0.2.um, polygon_output: true)
+    ].each { |result| result.output("Sal.c", "Min. SalBlock extension over Activ or GatPoly = 0.20") }
+end.()
 -&gt; do
-    Cont.merged(true, 0).outside(EdgeSeal).ext_fast_space(180)
-end.().output("Cnt.b", "Min. Cont space")
+    [ SalBlock.ext_fast_separation(GatPoly_res, 0.2.um, consider_touch_points: false),
+      SalBlock.ext_fast_separation(nmosi_relevant_activ, 0.2.um, consider_touch_points: false)
+    ].each { |result| result.output("Sal.d", "Min. SalBlock space to unrelated Activ or GatPoly = 0.20") }
+end.()
+-&gt; do
+    SalBlock.ext_fast_separation(Cont, 0.2.um)
+end.().output("Sal.e", "Min. SalBlock space to Cont = 0.20")
+-&gt; do
+    Cont_outside_EdgeSeal.ext_not(ContBar.ext_or(Cont_SQ))
+end.().output("Cnt.a", "Min. and max. Cont width = 0.16")
+-&gt; do
+    Cont_outside_EdgeSeal.ext_fast_space(0.18.um, consider_intersecting_edges: false)
+end.().output("Cnt.b", "Min. Cont space = 0.18")
 -&gt; (;x1, viaLargeArray, viaInLargeArray, viaInLargeArray_error, badViaLine) do
-    x1 = Cont.merged(true, 0).size(0.20*0.5, acute_limit).merge(true, 0).size(-0.20*0.5, acute_limit).merge(true, 0)
-    viaLargeArray = x1.merged(true, 0).size(-(5*0.16)+(3*0.18)/2-0.001, acute_limit).merge(true, 0).size((5*0.16)+(3*0.18)/2-0.001, acute_limit).merge(true, 0)
-    viaInLargeArray = Cont.merged(true, 0).inside(viaLargeArray)
-    viaInLargeArray_error = viaInLargeArray.merged(true, 0).size(0.20/2-0.001, acute_limit).merge(true, 0).size(-0.20/2-0.001, acute_limit).merge(true, 0)
+    x1 = Cont.sized((0.20*0.5).um, acute_limit).sized(-(0.20*0.5).um, acute_limit)
+    viaLargeArray = x1.sized(-((5*0.16)+(3*0.18)/2-0.001).um, acute_limit).sized(((5*0.16)+(3*0.18)/2-0.001).um, acute_limit)
+    viaInLargeArray = Cont.inside(viaLargeArray)
+    viaInLargeArray_error = viaInLargeArray.sized((0.20/2-0.001).um, acute_limit).sized(-(0.20/2-0.001).um, acute_limit)
     badViaLine = viaInLargeArray_error.ext_not(viaInLargeArray)
     badViaLine.ext_rectangles(inverted: true)
-end.().output("Cnt.b1", "Min. Cont space in a contact array of more than 4 rows and more then 4 columns (Note 1)")
+end.().output("Cnt.b1", "Min. Cont space in a contact array of more than 4 rows and more then 4 columns (Note 1) = 0.20")
 -&gt; do
-    Cont_Act.ext_not(SVaricap).ext_fast_separation(GP_Nsram, 110)
-end.().output("Cnt.f", "Min. Cont on Activ space to GatPoly")
+    Cont_Act.ext_not(SVaricap).ext_fast_separation(GP_Nsram, 0.11.um)
+end.().output("Cnt.f", "Min. Cont on Activ space to GatPoly = 0.11")
 -&gt; do
     Cont_not_Act_GP.dup
 end.().output("Cnt.g", "Cont must be within Activ or GatPoly")
@@ -892,27 +1905,35 @@ end.().output("Cnt.h", "Cont must be covered with Metal1")
 -&gt; do
     Cont_Act_GP.ext_not(SVaricap)
 end.().output("Cnt.j", "Cont on GatPoly over Activ is not allowed")
+-&gt; do
+    [ ContBar.outside(EdgeSeal).ext_not(schottky_nbl1_or_schottky_nw1).ext_fast_width(0.16.um),
+      Cont_outside_EdgeSeal.ext_not(schottky_nbl1_or_schottky_nw1).drc((width(projection) &gt; 0.16.um).polygons)
+    ].each { |result| result.output("CntB.a", "Min. and max. ContBar width = 0.16") }
+end.()
 -&gt; do
     CntB_a1_error.dup
-end.().output("CntB.a1", "Min. ContBar length")
+end.().output("CntB.a1", "Min. ContBar length = 0.34")
 -&gt; do
-    ContBar.merged(true, 0).outside(TRANS).ext_fast_space(280)
-end.().output("CntB.b", "Min. ContBar space")
+    ContBar_outside_TRANS.ext_fast_space(0.28.um)
+end.().output("CntB.b", "Min. ContBar space = 0.28")
 -&gt; do
-    ContBar.ext_fast_separation(Cont_SQ, 220)
-end.().output("CntB.b2", "Min. ContBar space to Cont")
+    ContBar.ext_fast_separation(Cont_SQ, 0.22.um)
+end.().output("CntB.b2", "Min. ContBar space to Cont = 0.22")
 -&gt; do
-    ContBar_GP.ext_fast_separation(Activ, 140)
-end.().output("CntB.e", "Min. ContBar on GatPoly space to Activ")
+    ContBar_GP.ext_fast_separation(Activ, 0.14.um)
+end.().output("CntB.e", "Min. ContBar on GatPoly space to Activ = 0.14")
 -&gt; do
-    ContBar_Act.ext_fast_separation(GatPoly, 110)
-end.().output("CntB.f", "Min. ContBar on Activ space to GatPoly")
+    ContBar_Act.ext_fast_separation(GatPoly, 0.11.um)
+end.().output("CntB.f", "Min. ContBar on Activ space to GatPoly = 0.11")
 -&gt; do
     ContBar_not_Act_GP.dup
 end.().output("CntB.g", "ContBar must be within Activ or GatPoly")
 -&gt; do
-    pSD.ext_fast_separation(ContBar_NAct, 90, polygon_output: true)
-end.().output("CntB.g1", "Min. pSD space to ContBar on nSD-Activ")
+    pSD.ext_fast_separation(ContBar_NAct, 0.09.um, max_angle: 0, include_max_angle: true, polygon_output: true)
+end.().output("CntB.g1", "Min. pSD space to ContBar on nSD-Activ = 0.09")
+-&gt; do
+    ContBar_PAct.ext_fast_enclosed(pSD, 0.09.um, polygon_output: true)
+end.().output("CntB.g2", "Min. pSD overlap of ContBar on pSD-Activ = 0.09")
 -&gt; do
     ContBar_not_M1.dup
 end.().output("CntB.h", "ContBar must be covered with Metal1")
@@ -920,751 +1941,1082 @@ end.().output("CntB.h", "ContBar must be covered with Metal1")
     ContBar_Act_GP.dup
 end.().output("CntB.j", "ContBar on GatPoly over Activ is not allowed")
 -&gt; do
-    Metal1.ext_fast_width(160)
-end.().output("M1.a", "Min. Metal1 width")
+    Metal1.ext_fast_width(0.16.um)
+end.().output("M1.a", "Min. Metal1 width = 0.16")
 -&gt; do
-    M1_Nsram.ext_fast_space(180)
-end.().output("M1.b", "Min. Metal1 space or notch")
+    M1_Nsram.ext_fast_space(0.18.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true)
+end.().output("M1.b", "Min. Metal1 space or notch = 0.18")
 -&gt; do
     Cont_Nsram.ext_not(M1_Nsram)
-end.().output("M1.c", "Min. Metal1 enclosure of Cont")
+end.().output("M1.c", "Min. Metal1 enclosure of Cont = 0.00")
 -&gt; do
-    Metal1.merged(true, 0).outside(EdgeSeal).ext_area([["&lt;", 0.09]])
-end.().output("M1.d", "Min. Metal1 area (µm²)")
+    Cont_Nsram.outside(EdgeSeal).drc(if_any(
+        !rectangles,
+        primary-secondary(Metal1_outside_EdgeSeal),
+        ((enclosed(Metal1_outside_EdgeSeal, projection, whole_edges, one_side_allowed, two_opposite_sides_allowed) &lt; 0.05.um))))
+end.().output("M1.c1", "Min. Metal1 endcap enclosure of Cont (Note 1) = 0.05")
+-&gt; do
+    Metal1_outside_EdgeSeal.ext_with_area([["&lt;", 0.09.um2]])
+end.().output("M1.d", "Min. Metal1 area (µm²) = 0.09")
 
 if $density
 	-&gt; do
 	    M1_density.ext_with_density(0.0 .. 0.35, 'll')
-	end.().output("M1.j", "Min. global Metal1 density [%]")
+	end.().output("M1.j", "Min. global Metal1 density [%] = 35.0")
 	-&gt; do
 	    M1_density.ext_with_density(0.6 .. 1.0, 'll')
-	end.().output("M1.k", "Max. global Metal1 density [%]")
+	end.().output("M1.k", "Max. global Metal1 density [%] = 60.0")
 end
 
 -&gt; do
-    Metal2.ext_fast_width(200)
-end.().output("M2.a", "Min. Metal2 width")
+    Metal2.ext_fast_width(0.2.um)
+end.().output("M2.a", "Min. Metal2 width = 0.20")
+-&gt; do
+    M2_Nsram.ext_fast_space(0.21.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true)
+end.().output("M2.b", "Min. Metal2 space or notch = 0.21")
 -&gt; do
-    M2_Nsram.ext_fast_space(210)
-end.().output("M2.b", "Min. Metal2 space or notch")
+    Via1.outside(EdgeSeal).ext_fast_enclosed(Metal2_outside_EdgeSeal, 0.005.um, polygon_output: true)
+end.().output("M2.c", "Min. Metal2 enclosure of Via1 = 0.005")
 -&gt; do
-    Metal2.merged(true, 0).outside(EdgeSeal).ext_area([["&lt;", 0.144]])
-end.().output("M2.d", "Min. Metal2 area (µm²)")
+    V1_Nsram_outside_EdgeSeal.drc(if_any(
+        !rectangles,
+        primary-secondary(Metal2_outside_EdgeSeal),
+        ((enclosed(Metal2_outside_EdgeSeal, projection, whole_edges, one_side_allowed, two_opposite_sides_allowed) &lt; 0.05.um))))
+end.().output("M2.c1", "Min. Metal2 endcap enclosure of Via1 (Note 1) = 0.05")
+-&gt; do
+    Metal2_outside_EdgeSeal.ext_with_area([["&lt;", 0.144.um2]])
+end.().output("M2.d", "Min. Metal2 area (µm²) = 0.144")
 
 if $density
 	-&gt; do
 	    M2_density.ext_with_density(0.0 .. 0.35, 'll')
-	end.().output("M2.j", "Min. global Metal2 density [%]")
+	end.().output("M2.j", "Min. global Metal2 density [%] = 35.00")
 	-&gt; do
 	    M2_density.ext_with_density(0.6 .. 1.0, 'll')
-	end.().output("M2.k", "Max. global Metal2 density [%]")
+	end.().output("M2.k", "Max. global Metal2 density [%] = 60.00")
 end
 
 -&gt; do
-    Metal3.ext_fast_width(200)
-end.().output("M3.a", "Min. Metal3 width")
+    Metal3.ext_fast_width(0.2.um)
+end.().output("M3.a", "Min. Metal3 width = 0.20")
+-&gt; do
+    M3_Nsram.ext_fast_space(0.21.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true)
+end.().output("M3.b", "Min. Metal3 space or notch = 0.21")
 -&gt; do
-    M3_Nsram.ext_fast_space(210)
-end.().output("M3.b", "Min. Metal3 space or notch")
+    Via2.outside(EdgeSeal).ext_fast_enclosed(Metal3_outside_EdgeSeal, 0.005.um, polygon_output: true)
+end.().output("M3.c", "Min. Metal3 enclosure of Via2 = 0.005")
 -&gt; do
-    Metal3.merged(true, 0).outside(EdgeSeal).ext_area([["&lt;", 0.144]])
-end.().output("M3.d", "Min. Metal3 area (µm²)")
+    V2_Nsram_outside_EdgeSeal.drc(if_any(
+        !rectangles,
+        primary-secondary(Metal3_outside_EdgeSeal),
+        ((enclosed(Metal3_outside_EdgeSeal, projection, whole_edges, one_side_allowed, two_opposite_sides_allowed) &lt; 0.05.um))))
+end.().output("M3.c1", "Min. Metal3 endcap enclosure of Via2 (Note 1) = 0.05")
+-&gt; do
+    Metal3_outside_EdgeSeal.ext_with_area([["&lt;", 0.144.um2]])
+end.().output("M3.d", "Min. Metal3 area (µm²) = 0.144")
 
 if $density
 	-&gt; do
 	    M3_density.ext_with_density(0.0 .. 0.35, 'll')
-	end.().output("M3.j", "Min. global Metal3 density [%]")
+	end.().output("M3.j", "Min. global Metal3 density [%] = 35.00")
 	-&gt; do
 	    M3_density.ext_with_density(0.6 .. 1.0, 'll')
-	end.().output("M3.k", "Max. global Metal3 density [%]")
+	end.().output("M3.k", "Max. global Metal3 density [%] = 60.00")
 end
 
 -&gt; do
-    Metal4.ext_fast_width(200)
-end.().output("M4.a", "Min. Metal4 width")
+    Metal4.ext_fast_width(0.2.um)
+end.().output("M4.a", "Min. Metal4 width = 0.20")
+-&gt; do
+    M4_Nsram.ext_fast_space(0.21.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true)
+end.().output("M4.b", "Min. Metal4 space or notch = 0.21")
+-&gt; do
+    Via3.outside(EdgeSeal).ext_fast_enclosed(Metal4_outside_EdgeSeal, 0.005.um, polygon_output: true)
+end.().output("M4.c", "Min. Metal4 enclosure of Via3 = 0.005")
 -&gt; do
-    M4_Nsram.ext_fast_space(210)
-end.().output("M4.b", "Min. Metal4 space or notch")
+    V3_Nsram_outside_EdgeSeal.drc(if_any(
+        !rectangles,
+        primary-secondary(Metal4_outside_EdgeSeal),
+        ((enclosed(Metal4_outside_EdgeSeal, projection, whole_edges, one_side_allowed, two_opposite_sides_allowed) &lt; 0.05.um))))
+end.().output("M4.c1", "Min. Metal4 endcap enclosure of Via3 (Note 1) = 0.05")
 -&gt; do
-    Metal4.merged(true, 0).outside(EdgeSeal).ext_area([["&lt;", 0.144]])
-end.().output("M4.d", "Min. Metal4 area (µm²)")
+    Metal4_outside_EdgeSeal.ext_with_area([["&lt;", 0.144.um2]])
+end.().output("M4.d", "Min. Metal4 area (µm²) = 0.144")
 
 if $density
 	-&gt; do
 	    M4_density.ext_with_density(0.0 .. 0.35, 'll')
-	end.().output("M4.j", "Min. global Metal4 density [%]")
+	end.().output("M4.j", "Min. global Metal4 density [%] = 35.00")
 	-&gt; do
 	    M4_density.ext_with_density(0.6 .. 1.0, 'll')
-	end.().output("M4.k", "Max. global Metal4 density [%]")
+	end.().output("M4.k", "Max. global Metal4 density [%] = 60.00")
 end
 
 -&gt; do
-    Metal5.ext_fast_width(200)
-end.().output("M5.a", "Min. Metal5 width")
+    Metal5.ext_fast_width(0.2.um)
+end.().output("M5.a", "Min. Metal5 width = 0.20")
+-&gt; do
+    M5_Nsram.ext_fast_space(0.21.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true)
+end.().output("M5.b", "Min. Metal5 space or notch = 0.21")
+-&gt; do
+    Via4.outside(EdgeSeal).ext_fast_enclosed(Metal5_outside_EdgeSeal, 0.005.um, polygon_output: true)
+end.().output("M5.c", "Min. Metal5 enclosure of Via4 = 0.005")
 -&gt; do
-    M5_Nsram.ext_fast_space(210)
-end.().output("M5.b", "Min. Metal5 space or notch")
+    V4_Nsram_outside_EdgeSeal.drc(if_any(
+        !rectangles,
+        primary-secondary(Metal5_outside_EdgeSeal),
+        ((enclosed(Metal5_outside_EdgeSeal, projection, whole_edges, one_side_allowed, two_opposite_sides_allowed) &lt; 0.05.um))))
+end.().output("M5.c1", "Min. Metal5 endcap enclosure of Via4 (Note 1) = 0.05")
 -&gt; do
-    Metal5.merged(true, 0).outside(EdgeSeal).ext_area([["&lt;", 0.144]])
-end.().output("M5.d", "Min. Metal5 area (µm²)")
+    Metal5_outside_EdgeSeal.ext_with_area([["&lt;", 0.144.um2]])
+end.().output("M5.d", "Min. Metal5 area (µm²) = 0.144")
 
 if $density
 	-&gt; do
 	    M5_density.ext_with_density(0.0 .. 0.35, 'll')
-	end.().output("M5.j", "Min. global Metal5 density [%]")
+	end.().output("M5.j", "Min. global Metal5 density [%] = 35.00")
 	-&gt; do
 	    M5_density.ext_with_density(0.6 .. 1.0, 'll')
-	end.().output("M5.k", "Max. global Metal5 density [%]")
+	end.().output("M5.k", "Max. global Metal5 density [%] = 60.00")
 end
 
 
 if $filler
 	-&gt; do
-	    Metal1_filler.ext_fast_width(1000)
-	end.().output("M1Fil.a1", "Min. Metal1:filler width")
+	    Metal1_filler.ext_fast_width(1.0.um)
+	end.().output("M1Fil.a1", "Min. Metal1:filler width = 1.00")
 	-&gt; do
-	    Metal1_filler.ext_fast_space(600)
-	end.().output("M1Fil.b", "Min. Metal1:filler space")
+	    Metal1_filler.ext_fast_space(0.6.um)
+	end.().output("M1Fil.b", "Min. Metal1:filler space = 0.42")
 	-&gt; do
-	    Metal1_filler.ext_fast_separation(Metal1, 420)
-	end.().output("M1Fil.c", "Min. Metal1:filler space to Metal1")
+	    Metal1_filler.ext_fast_separation(Metal1, 0.42.um)
+	end.().output("M1Fil.c", "Min. Metal1:filler space to Metal1 = 0.42")
 	-&gt; do
-	    Metal1_filler.ext_fast_separation(TRANS, 1000)
-	end.().output("M1Fil.d", "Min. Metal1:filler space to TRANS")
+	    Metal1_filler.ext_fast_separation(TRANS, 1.0.um)
+	end.().output("M1Fil.d", "Min. Metal1:filler space to TRANS = 1.00")
 end
 
 
 if $density
 	-&gt; do
-	    M1_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0), tile_step(400.0))
-	end.().output("M1Fil.h", "Min. Metal1 and Metal1:filler coverage ratio for any 800 x 800 µm² chip area [%]")
+	    M1_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0.um), tile_step(400.0.um))
+	end.().output("M1Fil.h", "Min. Metal1 and Metal1:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00")
 	-&gt; do
-	    M1_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0), tile_step(400.0))
-	end.().output("M1Fil.k", "Max. Metal1 and Metal1:filler coverage ratio for any 800 x 800 µm² chip area [%]")
+	    M1_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0.um), tile_step(400.0.um))
+	end.().output("M1Fil.k", "Max. Metal1 and Metal1:filler coverage ratio for any 800 x 800 µm² chip area [%] = 75.00")
 end
 
 
 if $filler
 	-&gt; do
-	    Metal2_filler.ext_fast_width(1000)
-	end.().output("M2Fil.a1", "Min. Metal2:filler width")
+	    Metal2_filler.ext_fast_width(1.0.um)
+	end.().output("M2Fil.a1", "Min. Metal2:filler width = 1.00")
 	-&gt; do
-	    Metal2_filler.ext_fast_space(600)
-	end.().output("M2Fil.b", "Min. Metal2:filler space")
+	    Metal2_filler.ext_fast_space(0.6.um)
+	end.().output("M2Fil.b", "Min. Metal2:filler space = 0.42")
 	-&gt; do
-	    Metal2_filler.ext_fast_separation(Metal2, 420)
-	end.().output("M2Fil.c", "Min. Metal2:filler space to Metal2")
+	    Metal2_filler.ext_fast_separation(Metal2, 0.42.um)
+	end.().output("M2Fil.c", "Min. Metal2:filler space to Metal2 = 0.42")
 	-&gt; do
-	    Metal2_filler.ext_fast_separation(TRANS, 1000)
-	end.().output("M2Fil.d", "Min. Metal2:filler space to TRANS")
+	    Metal2_filler.ext_fast_separation(TRANS, 1.0.um)
+	end.().output("M2Fil.d", "Min. Metal2:filler space to TRANS = 1.00")
 end
 
 
 if $density
 	-&gt; do
-	    M2_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0), tile_step(400.0))
-	end.().output("M2Fil.h", "Min. Metal2 and Metal2:filler coverage ratio for any 800 x 800 µm² chip area [%]")
+	    M2_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0.um), tile_step(400.0.um))
+	end.().output("M2Fil.h", "Min. Metal2 and Metal2:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00")
 	-&gt; do
-	    M2_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0), tile_step(400.0))
-	end.().output("M2Fil.k", "Max. Metal2 and Metal2:filler coverage ratio for any 800 x 800 µm² chip area [%]")
+	    M2_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0.um), tile_step(400.0.um))
+	end.().output("M2Fil.k", "Max. Metal2 and Metal2:filler coverage ratio for any 800 x 800 µm² chip area [%] = 75.00")
 end
 
 
 if $filler
 	-&gt; do
-	    Metal3_filler.ext_fast_width(1000)
-	end.().output("M3Fil.a1", "Min. Metal3:filler width")
+	    Metal3_filler.ext_fast_width(1.0.um)
+	end.().output("M3Fil.a1", "Min. Metal3:filler width = 1.00")
 	-&gt; do
-	    Metal3_filler.ext_fast_space(600)
-	end.().output("M3Fil.b", "Min. Metal3:filler space")
+	    Metal3_filler.ext_fast_space(0.6.um)
+	end.().output("M3Fil.b", "Min. Metal3:filler space = 0.42")
 	-&gt; do
-	    Metal3_filler.ext_fast_separation(Metal3, 420)
-	end.().output("M3Fil.c", "Min. Metal3:filler space to Metal3")
+	    Metal3_filler.ext_fast_separation(Metal3, 0.42.um)
+	end.().output("M3Fil.c", "Min. Metal3:filler space to Metal3 = 0.42")
 	-&gt; do
-	    Metal3_filler.ext_fast_separation(TRANS, 1000)
-	end.().output("M3Fil.d", "Min. Metal3:filler space to TRANS")
+	    Metal3_filler.ext_fast_separation(TRANS, 1.0.um)
+	end.().output("M3Fil.d", "Min. Metal3:filler space to TRANS = 1.00")
 end
 
 
 if $density
 	-&gt; do
-	    M3_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0), tile_step(400.0))
-	end.().output("M3Fil.h", "Min. Metal3 and Metal3:filler coverage ratio for any 800 x 800 µm² chip area [%]")
+	    M3_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0.um), tile_step(400.0.um))
+	end.().output("M3Fil.h", "Min. Metal3 and Metal3:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00")
 	-&gt; do
-	    M3_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0), tile_step(400.0))
-	end.().output("M3Fil.k", "Max. Metal3 and Metal3:filler coverage ratio for any 800 x 800 µm² chip area [%]")
+	    M3_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0.um), tile_step(400.0.um))
+	end.().output("M3Fil.k", "Max. Metal3 and Metal3:filler coverage ratio for any 800 x 800 µm² chip area [%] = 75.00")
 end
 
 
 if $filler
 	-&gt; do
-	    Metal4_filler.ext_fast_width(1000)
-	end.().output("M4Fil.a1", "Min. Metal4:filler width")
+	    Metal4_filler.ext_fast_width(1.0.um)
+	end.().output("M4Fil.a1", "Min. Metal4:filler width = 1.00")
 	-&gt; do
-	    Metal4_filler.ext_fast_space(600)
-	end.().output("M4Fil.b", "Min. Metal4:filler space")
+	    Metal4_filler.ext_fast_space(0.6.um)
+	end.().output("M4Fil.b", "Min. Metal4:filler space = 0.42")
 	-&gt; do
-	    Metal4_filler.ext_fast_separation(Metal4, 420)
-	end.().output("M4Fil.c", "Min. Metal4:filler space to Metal4")
+	    Metal4_filler.ext_fast_separation(Metal4, 0.42.um)
+	end.().output("M4Fil.c", "Min. Metal4:filler space to Metal4 = 0.42")
 	-&gt; do
-	    Metal4_filler.ext_fast_separation(TRANS, 1000)
-	end.().output("M4Fil.d", "Min. Metal4:filler space to TRANS")
+	    Metal4_filler.ext_fast_separation(TRANS, 1.0.um)
+	end.().output("M4Fil.d", "Min. Metal4:filler space to TRANS = 1.00")
 end
 
 
 if $density
 	-&gt; do
-	    M4_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0), tile_step(400.0))
-	end.().output("M4Fil.h", "Min. Metal4 and Metal4:filler coverage ratio for any 800 x 800 µm² chip area [%]")
+	    M4_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0.um), tile_step(400.0.um))
+	end.().output("M4Fil.h", "Min. Metal4 and Metal4:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00")
 	-&gt; do
-	    M4_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0), tile_step(400.0))
-	end.().output("M4Fil.k", "Max. Metal4 and Metal4:filler coverage ratio for any 800 x 800 µm² chip area [%]")
+	    M4_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0.um), tile_step(400.0.um))
+	end.().output("M4Fil.k", "Max. Metal4 and Metal4:filler coverage ratio for any 800 x 800 µm² chip area [%] = 75.00")
 end
 
 
 if $filler
 	-&gt; do
-	    Metal5_filler.ext_fast_width(1000)
-	end.().output("M5Fil.a1", "Min. Metal5:filler width")
+	    Metal5_filler.ext_fast_width(1.0.um)
+	end.().output("M5Fil.a1", "Min. Metal5:filler width = 1.00")
 	-&gt; do
-	    Metal5_filler.ext_fast_space(600)
-	end.().output("M5Fil.b", "Min. Metal5:filler space")
+	    Metal5_filler.ext_fast_space(0.6.um)
+	end.().output("M5Fil.b", "Min. Metal5:filler space = 0.42")
 	-&gt; do
-	    Metal5_filler.ext_fast_separation(Metal5, 420)
-	end.().output("M5Fil.c", "Min. Metal5:filler space to Metal5")
+	    Metal5_filler.ext_fast_separation(Metal5, 0.42.um)
+	end.().output("M5Fil.c", "Min. Metal5:filler space to Metal5 = 0.42")
 	-&gt; do
-	    Metal5_filler.ext_fast_separation(TRANS, 1000)
-	end.().output("M5Fil.d", "Min. Metal5:filler space to TRANS")
+	    Metal5_filler.ext_fast_separation(TRANS, 1.0.um)
+	end.().output("M5Fil.d", "Min. Metal5:filler space to TRANS = 1.00")
 end
 
 
 if $density
 	-&gt; do
-	    M5_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0), tile_step(400.0))
-	end.().output("M5Fil.h", "Min. Metal5 and Metal5:filler coverage ratio for any 800 x 800 µm² chip area [%]")
+	    M5_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0.um), tile_step(400.0.um))
+	end.().output("M5Fil.h", "Min. Metal5 and Metal5:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00")
 	-&gt; do
-	    M5_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0), tile_step(400.0))
-	end.().output("M5Fil.k", "Max. Metal5 and Metal5:filler coverage ratio for any 800 x 800 µm² chip area [%]")
+	    M5_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0.um), tile_step(400.0.um))
+	end.().output("M5Fil.k", "Max. Metal5 and Metal5:filler coverage ratio for any 800 x 800 µm² chip area [%] = 75.00")
 end
 
 -&gt; do
-    Via1.ext_not(EdgeSeal).merged(true, 0).outside(transG2L).ext_rectangles(false, false, [["==", 190]], [["==", 190]], nil, inverted: true)
-end.().output("V1.a", "Min. and max. Via1 width")
+    Via1_edgC1_out.outside(transG2L).ext_rectangles(false, false, [["==", 0.19.um]], [["==", 0.19.um]], nil, inverted: true)
+end.().output("V1.a", "Min. and max. Via1 width = 0.19")
 -&gt; do
-    Via1.ext_not(EdgeSeal).ext_fast_space(220)
-end.().output("V1.b", "Min. Via1 space")
+    Via1_edgC1_out.ext_fast_space(0.22.um, consider_intersecting_edges: false)
+end.().output("V1.b", "Min. Via1 space = 0.22")
 -&gt; (;via1NoES, x1, via1Array, via1In, via1BigArray, via1SepErr_1, via1SepErr_2) do
-    via1NoES = Via1.ext_not(EdgeSeal)
-    x1 = via1NoES.merged(true, 0).size(0.29*0.5, acute_limit).merge(true, 0).size(-0.29*0.5, acute_limit).merge(true, 0)
-    via1Array = x1.merged(true, 0).size(-((4*0.19+3*0.22)-0.05)*0.5, acute_limit).merge(true, 0).size(((4*0.19+3*0.22)-0.05)*0.5, acute_limit).merge(true, 0)
-    via1In = via1NoES.merged(true, 0).inside(via1Array)
-    via1BigArray = via1In.merged(true, 0).size(0.143, acute_limit).merge(true, 0).size(-0.143, acute_limit).merge(true, 0)
+    via1NoES = Via1_edgC1_out.dup
+    x1 = via1NoES.sized((0.29*0.5).um, acute_limit).sized(-(0.29*0.5).um, acute_limit)
+    via1Array = x1.sized(-(((4*0.19+3*0.22)-0.05)*0.5).um, acute_limit).sized((((4*0.19+3*0.22)-0.05)*0.5).um, acute_limit)
+    via1In = via1NoES.inside(via1Array)
+    via1BigArray = via1In.sized(0.143.um, acute_limit).sized(-0.143.um, acute_limit)
     via1SepErr_1 = via1BigArray.ext_not(via1In)
     via1SepErr_2 = via1SepErr_1.ext_not(via1SepErr_1.ext_rectangles)
     via1SepErr_2.ext_or(via1In.ext_touching(via1SepErr_2))
-end.().output("V1.b1", "Min. Via1 space in an array of more than 3 rows and more then 3 columns (Note 1)")
--&gt; do
-    Via2.ext_not(EdgeSeal).merged(true, 0).outside(transG2L).ext_rectangles(false, false, [["==", 190]], [["==", 190]], nil, inverted: true)
-end.().output("V2.a", "Min. and max. Via2 width")
--&gt; do
-    Via2.ext_not(EdgeSeal).ext_fast_space(220)
-end.().output("V2.b", "Min. Via2 space")
+end.().output("V1.b1", "Min. Via1 space in an array of more than 3 rows and more then 3 columns (Note 1) = 0.29")
+-&gt; (;x) do
+    x = V1_Nsram_outside_EdgeSeal.ext_rectangles(false, false, [["==", 0.19.um]], [["==", 0.19.um]], nil)
+    x.drc(if_any(
+        !rectangles,
+        primary-secondary(Metal1_outside_EdgeSeal),
+        (if_any(enclosed(Metal1_outside_EdgeSeal) &lt; 0.01.um, enclosed(Metal1_outside_EdgeSeal, projection, whole_edges, one_side_allowed, two_opposite_sides_allowed) &lt; 0.05.um))))
+end.().output("V1.c1", "Min. Metal1 endcap enclosure of Via1 (Note 2) = 0.05")
+-&gt; do
+    Via2_edgC1_out.outside(transG2L).ext_rectangles(false, false, [["==", 0.19.um]], [["==", 0.19.um]], nil, inverted: true)
+end.().output("V2.a", "Min. and max. Via2 width = 0.19")
+-&gt; do
+    Via2_edgC1_out.ext_fast_space(0.22.um, consider_intersecting_edges: false)
+end.().output("V2.b", "Min. Via2 space = 0.22")
 -&gt; (;via2NoES, x1, via2Array, via2In, via2BigArray, via2SepErr_1, via2SepErr_2) do
-    via2NoES = Via2.ext_not(EdgeSeal)
-    x1 = via2NoES.merged(true, 0).size(0.29*0.5, acute_limit).merge(true, 0).size(-0.29*0.5, acute_limit).merge(true, 0)
-    via2Array = x1.merged(true, 0).size(-((4*0.19+3*0.22)-0.05)*0.5, acute_limit).merge(true, 0).size(((4*0.19+3*0.22)-0.05)*0.5, acute_limit).merge(true, 0)
-    via2In = via2NoES.merged(true, 0).inside(via2Array)
-    via2BigArray = via2In.merged(true, 0).size(0.143, acute_limit).merge(true, 0).size(-0.143, acute_limit).merge(true, 0)
+    via2NoES = Via2_edgC1_out.dup
+    x1 = via2NoES.sized((0.29*0.5).um, acute_limit).sized(-(0.29*0.5).um, acute_limit)
+    via2Array = x1.sized(-(((4*0.19+3*0.22)-0.05)*0.5).um, acute_limit).sized((((4*0.19+3*0.22)-0.05)*0.5).um, acute_limit)
+    via2In = via2NoES.inside(via2Array)
+    via2BigArray = via2In.sized(0.143.um, acute_limit).sized(-0.143.um, acute_limit)
     via2SepErr_1 = via2BigArray.ext_not(via2In)
     via2SepErr_2 = via2SepErr_1.ext_not(via2SepErr_1.ext_rectangles)
     via2SepErr_2.ext_or(via2In.ext_touching(via2SepErr_2))
-end.().output("V2.b1", "Min. Via2 space in an array of more than 3 rows and more then 3 columns (Note 1)")
--&gt; do
-    Via3.ext_not(EdgeSeal).merged(true, 0).outside(transG2L).ext_rectangles(false, false, [["==", 190]], [["==", 190]], nil, inverted: true)
-end.().output("V3.a", "Min. and max. Via3 width")
--&gt; do
-    Via3.ext_not(EdgeSeal).ext_fast_space(220)
-end.().output("V3.b", "Min. Via3 space")
+end.().output("V2.b1", "Min. Via2 space in an array of more than 3 rows and more then 3 columns (Note 1) = 0.29")
+-&gt; (;x) do
+    x = V2_Nsram_outside_EdgeSeal.ext_rectangles(false, false, [["==", 0.19.um]], [["==", 0.19.um]], nil)
+    x.drc(if_any(
+        !rectangles,
+        primary-secondary(Metal2_outside_EdgeSeal),
+        (if_any(enclosed(Metal2_outside_EdgeSeal) &lt; 0.005.um, enclosed(Metal2_outside_EdgeSeal, projection, whole_edges, one_side_allowed, two_opposite_sides_allowed) &lt; 0.05.um))))
+end.().output("V2.c1", "Min. Metal2 endcap enclosure of Via2 (Note 2) = 0.05")
+-&gt; do
+    Via3_edgC1_out.outside(transG2L).ext_rectangles(false, false, [["==", 0.19.um]], [["==", 0.19.um]], nil, inverted: true)
+end.().output("V3.a", "Min. and max. Via3 width = 0.19")
+-&gt; do
+    Via3_edgC1_out.ext_fast_space(0.22.um, consider_intersecting_edges: false)
+end.().output("V3.b", "Min. Via3 space = 0.22")
 -&gt; (;via3NoES, x1, via3Array, via3In, via3BigArray, via3SepErr_1, via3SepErr_2) do
-    via3NoES = Via3.ext_not(EdgeSeal)
-    x1 = via3NoES.merged(true, 0).size(0.29*0.5, acute_limit).merge(true, 0).size(-0.29*0.5, acute_limit).merge(true, 0)
-    via3Array = x1.merged(true, 0).size(-((4*0.19+3*0.22)-0.05)*0.5, acute_limit).merge(true, 0).size(((4*0.19+3*0.22)-0.05)*0.5, acute_limit).merge(true, 0)
-    via3In = via3NoES.merged(true, 0).inside(via3Array)
-    via3BigArray = via3In.merged(true, 0).size(0.143, acute_limit).merge(true, 0).size(-0.143, acute_limit).merge(true, 0)
+    via3NoES = Via3_edgC1_out.dup
+    x1 = via3NoES.sized((0.29*0.5).um, acute_limit).sized(-(0.29*0.5).um, acute_limit)
+    via3Array = x1.sized(-(((4*0.19+3*0.22)-0.05)*0.5).um, acute_limit).sized((((4*0.19+3*0.22)-0.05)*0.5).um, acute_limit)
+    via3In = via3NoES.inside(via3Array)
+    via3BigArray = via3In.sized(0.143.um, acute_limit).sized(-0.143.um, acute_limit)
     via3SepErr_1 = via3BigArray.ext_not(via3In)
     via3SepErr_2 = via3SepErr_1.ext_not(via3SepErr_1.ext_rectangles)
     via3SepErr_2.ext_or(via3In.ext_touching(via3SepErr_2))
-end.().output("V3.b1", "Min. Via3 space in an array of more than 3 rows and more then 3 columns (Note 1)")
--&gt; do
-    Via4.ext_not(EdgeSeal).merged(true, 0).outside(transG2L).ext_rectangles(false, false, [["==", 190]], [["==", 190]], nil, inverted: true)
-end.().output("V4.a", "Min. and max. Via4 width")
--&gt; do
-    Via4.ext_not(EdgeSeal).ext_fast_space(220)
-end.().output("V4.b", "Min. Via4 space")
+end.().output("V3.b1", "Min. Via3 space in an array of more than 3 rows and more then 3 columns (Note 1) = 0.29")
+-&gt; (;x) do
+    x = V3_Nsram_outside_EdgeSeal.ext_rectangles(false, false, [["==", 0.19.um]], [["==", 0.19.um]], nil)
+    x.drc(if_any(
+        !rectangles,
+        primary-secondary(Metal3_outside_EdgeSeal),
+        (if_any(enclosed(Metal3_outside_EdgeSeal) &lt; 0.005.um, enclosed(Metal3_outside_EdgeSeal, projection, whole_edges, one_side_allowed, two_opposite_sides_allowed) &lt; 0.05.um))))
+end.().output("V3.c1", "Min. Metal3 endcap enclosure of Via3 (Note 2) = 0.05")
+-&gt; do
+    Via4_edgC1_out.outside(transG2L).ext_rectangles(false, false, [["==", 0.19.um]], [["==", 0.19.um]], nil, inverted: true)
+end.().output("V4.a", "Min. and max. Via4 width = 0.19")
+-&gt; do
+    Via4_edgC1_out.ext_fast_space(0.22.um, consider_intersecting_edges: false)
+end.().output("V4.b", "Min. Via4 space = 0.22")
 -&gt; (;via4NoES, x1, via4Array, via4In, via4BigArray, via4SepErr_1, via4SepErr_2) do
-    via4NoES = Via4.ext_not(EdgeSeal)
-    x1 = via4NoES.merged(true, 0).size(0.29*0.5, acute_limit).merge(true, 0).size(-0.29*0.5, acute_limit).merge(true, 0)
-    via4Array = x1.merged(true, 0).size(-((4*0.19+3*0.22)-0.05)*0.5, acute_limit).merge(true, 0).size(((4*0.19+3*0.22)-0.05)*0.5, acute_limit).merge(true, 0)
-    via4In = via4NoES.merged(true, 0).inside(via4Array)
-    via4BigArray = via4In.merged(true, 0).size(0.143, acute_limit).merge(true, 0).size(-0.143, acute_limit).merge(true, 0)
+    via4NoES = Via4_edgC1_out.dup
+    x1 = via4NoES.sized((0.29*0.5).um, acute_limit).sized(-(0.29*0.5).um, acute_limit)
+    via4Array = x1.sized(-(((4*0.19+3*0.22)-0.05)*0.5).um, acute_limit).sized((((4*0.19+3*0.22)-0.05)*0.5).um, acute_limit)
+    via4In = via4NoES.inside(via4Array)
+    via4BigArray = via4In.sized(0.143.um, acute_limit).sized(-0.143.um, acute_limit)
     via4SepErr_1 = via4BigArray.ext_not(via4In)
     via4SepErr_2 = via4SepErr_1.ext_not(via4SepErr_1.ext_rectangles)
     via4SepErr_2.ext_or(via4In.ext_touching(via4SepErr_2))
-end.().output("V4.b1", "Min. Via4 space in an array of more than 3 rows and more then 3 columns (Note 1)")
+end.().output("V4.b1", "Min. Via4 space in an array of more than 3 rows and more then 3 columns (Note 1) = 0.29")
+-&gt; (;x) do
+    x = V4_Nsram_outside_EdgeSeal.ext_rectangles(false, false, [["==", 0.19.um]], [["==", 0.19.um]], nil)
+    x.drc(if_any(
+        !rectangles,
+        primary-secondary(Metal4_outside_EdgeSeal),
+        (if_any(enclosed(Metal4_outside_EdgeSeal) &lt; 0.005.um, enclosed(Metal4_outside_EdgeSeal, projection, whole_edges, one_side_allowed, two_opposite_sides_allowed) &lt; 0.05.um))))
+end.().output("V4.c1", "Min. Metal4 endcap enclosure of Via4 (Note 2) = 0.05")
 -&gt; do
-    Vmim.ext_or(TopVia1.ext_not(EdgeSeal)).ext_rectangles(false, false, [["==", 420]], [["==", 420]], nil, inverted: true)
-end.().output("TV1.a", "Min. and max. TopVia1 width")
+    TopVia1_edgC1_out.ext_or(Vmim).ext_rectangles(false, false, [["==", 0.42.um]], [["==", 0.42.um]], nil, inverted: true)
+end.().output("TV1.a", "Min. and max. TopVia1 width = 0.42")
 -&gt; do
-    TopVia1.ext_or(Vmim).ext_fast_space(420)
-end.().output("TV1.b", "Min. TopVia1 space")
+    TopVia1_or_Vmim.ext_fast_space(0.42.um)
+end.().output("TV1.b", "Min. TopVia1 space = 0.42")
 -&gt; do
-    TopMetal1.ext_fast_width(1640)
-end.().output("TM1.a", "Min. TopMetal1 width")
+    TopMetal1.ext_fast_width(1.64.um)
+end.().output("TM1.a", "Min. TopMetal1 width = 1.64")
 -&gt; do
-    TopMetal1.ext_fast_space(1640)
-end.().output("TM1.b", "Min. TopMetal1 space or notch")
+    TopMetal1.ext_fast_space(1.64.um)
+end.().output("TM1.b", "Min. TopMetal1 space or notch = 1.64")
 
 if $density
 	-&gt; do
 	    TM1_density.ext_with_density(0.0 .. 0.25, 'll')
-	end.().output("TM1.c", "Min. global TopMetal1 density [%]")
+	end.().output("TM1.c", "Min. global TopMetal1 density [%] = 25.00")
 	-&gt; do
 	    TM1_density.ext_with_density(0.7 .. 1.0, 'll')
-	end.().output("TM1.d", "Max. global TopMetal1 density [%]")
+	end.().output("TM1.d", "Max. global TopMetal1 density [%] = 70.00")
 end
 
 
 if $filler
 	-&gt; do
-	    TopMetal1_filler.ext_fast_width(5000)
-	end.().output("TM1Fil.a", "Min. TopMetal1:filler width")
+	    TopMetal1_filler.ext_fast_width(5.0.um)
+	end.().output("TM1Fil.a", "Min. TopMetal1:filler width = 5.00")
 	-&gt; do
-	    TopMetal1_filler.ext_fast_space(3000)
-	end.().output("TM1Fil.b", "Min. TopMetal1:filler space")
+	    TopMetal1_filler.ext_fast_space(3.0.um)
+	end.().output("TM1Fil.b", "Min. TopMetal1:filler space = 3.00")
 	-&gt; do
-	    TopMetal1_filler.ext_fast_separation(TopMetal1, 3000)
-	end.().output("TM1Fil.c", "Min. TopMetal1:filler space to TopMetal1")
+	    TopMetal1_filler.ext_fast_separation(TopMetal1, 3.0.um)
+	end.().output("TM1Fil.c", "Min. TopMetal1:filler space to TopMetal1 = 3.00")
 	-&gt; do
-	    TopMetal1_filler.ext_fast_separation(TRANS, 4900)
-	end.().output("TM1Fil.d", "Min. TopMetal1:filler space to TRANS")
+	    TopMetal1_filler.ext_fast_separation(TRANS, 4.9.um)
+	end.().output("TM1Fil.d", "Min. TopMetal1:filler space to TRANS = 4.90")
 end
 
 -&gt; do
-    TopVia2.ext_not(EdgeSeal).ext_rectangles(false, false, [["==", 900]], [["==", 900]], nil, inverted: true)
-end.().output("TV2.a", "Min. and max. TopVia2 width")
+    TopVia2_edgC1_out.ext_rectangles(false, false, [["==", 0.9.um]], [["==", 0.9.um]], nil, inverted: true)
+end.().output("TV2.a", "Min. and max. TopVia2 width = 0.90")
 -&gt; do
-    TopVia2.ext_fast_space(1060)
-end.().output("TV2.b", "Min. TopVia2 space")
+    TopVia2.ext_fast_space(1.06.um)
+end.().output("TV2.b", "Min. TopVia2 space = 1.06")
 -&gt; do
-    TopMetal2.ext_fast_width(2000)
-end.().output("TM2.a", "Min. TopMetal2 width")
+    TopMetal2.ext_fast_width(2.0.um)
+end.().output("TM2.a", "Min. TopMetal2 width = 2.00")
 -&gt; do
-    TopMetal2.ext_fast_space(2000)
-end.().output("TM2.b", "Min. TopMetal2 space or notch")
+    TopMetal2.ext_fast_space(2.0.um)
+end.().output("TM2.b", "Min. TopMetal2 space or notch = 2.00")
 
 if $density
 	-&gt; do
 	    TM2_density.ext_with_density(0.0 .. 0.25, 'll')
-	end.().output("TM2.c", "Min. global TopMetal2 density [%]")
+	end.().output("TM2.c", "Min. global TopMetal2 density [%] = 25.00")
 	-&gt; do
 	    TM2_density.ext_with_density(0.7 .. 1.0, 'll')
-	end.().output("TM2.d", "Max. global TopMetal2 density [%]")
+	end.().output("TM2.d", "Max. global TopMetal2 density [%] = 70.00")
 end
 
 
 if $filler
 	-&gt; do
-	    TopMetal2_filler.ext_fast_width(5000)
-	end.().output("TM2Fil.a", "Min. TopMetal2:filler width")
+	    TopMetal2_filler.ext_fast_width(5.0.um)
+	end.().output("TM2Fil.a", "Min. TopMetal2:filler width = 5.00")
 	-&gt; do
-	    TopMetal2_filler.ext_fast_space(3000)
-	end.().output("TM2Fil.b", "Min. TopMetal2:filler space")
+	    TopMetal2_filler.ext_fast_space(3.0.um)
+	end.().output("TM2Fil.b", "Min. TopMetal2:filler space = 3.00")
 	-&gt; do
-	    TopMetal2_filler.ext_fast_separation(TopMetal2, 3000)
-	end.().output("TM2Fil.c", "Min. TopMetal2:filler space to TopMetal2")
+	    TopMetal2_filler.ext_fast_separation(TopMetal2, 3.0.um)
+	end.().output("TM2Fil.c", "Min. TopMetal2:filler space to TopMetal2 = 3.00")
 	-&gt; do
-	    TopMetal2_filler.ext_fast_separation(TRANS, 4900)
-	end.().output("TM2Fil.d", "Min. TopMetal2:filler space to TRANS")
+	    TopMetal2_filler.ext_fast_separation(TRANS, 4.9.um)
+	end.().output("TM2Fil.d", "Min. TopMetal2:filler space to TRANS = 4.90")
 end
 
 -&gt; do
-    Passiv.ext_fast_width(2100)
-end.().output("Pas.a", "Min. Passiv width")
+    Passiv.ext_fast_width(2.1.um)
+end.().output("Pas.a", "Min. Passiv width = 2.10")
+-&gt; do
+    Passiv.ext_fast_space(3.5.um)
+end.().output("Pas.b", "Min. Passiv space or notch = 3.50")
+-&gt; do
+    emit_npn13G2.ext_with_length([["&gt;", 0.07.um], ["&lt;", 0.9.um]])
+end.().output("npn13G2.a", "Min. and max. npn13G2 emitter length = 0.90")
+-&gt; do
+    emit_npn13G2L.ext_with_length([["&gt;", 0.07.um], ["&lt;", 1.0.um]])
+end.().output("npn13G2L.a", "Min. npn13G2L emitter length = 1.00")
+-&gt; do
+    emit_npn13G2L.ext_with_length([["&gt;", 2.5.um]])
+end.().output("npn13G2L.b", "Max. npn13G2L emitter length = 2.50")
+-&gt; do
+    emit_npn13G2V.ext_with_length([["&gt;", 0.12.um], ["&lt;", 1.0.um]])
+end.().output("npn13G2V.a", "Min. npn13G2V emitter length = 1.00")
+-&gt; do
+    emit_npn13G2V.ext_with_length([["&gt;", 5.0.um]])
+end.().output("npn13G2V.b", "Max. npn13G2V emitter length = 5.00")
+-&gt; do
+    Rsil_all.ext_fast_width(0.5.um)
+end.().output("Rsil.a", "Min. GatPoly width = 0.50")
+-&gt; do
+    RES.ext_fast_separation(Cont, 0.12.um)
+end.().output("Rsil.b", "Min. RES space to Cont = 0.12")
+-&gt; (;x) do
+    x = rsil_gatpoly.ext_fast_enclosed(RES, 1.0.um, polygon_output: true)
+    x.outside(Cont)
+end.().output("Rsil.c", "Min. RES extension over GatPoly = 0.00")
 -&gt; do
-    Passiv.ext_fast_space(3500)
-end.().output("Pas.b", "Min. Passiv space or notch")
+    GP_Rsil_extended_external_pSD.dup
+end.().output("Rsil.d", "Min. pSD space to GatPoly = 0.18")
 -&gt; do
-    emit_npn13G2.ext_with_length([["&gt;", 70], ["&lt;", 900]])
-end.().output("npn13G2.a", "Min. and max. npn13G2 emitter length")
+    GP_Rsil_extended.ext_fast_enclosed(EXTBlock, 0.18.um, polygon_output: true)
+end.().output("Rsil.e", "Min. EXTBlock enclosure of GatPoly = 0.18")
 -&gt; do
-    emit_npn13G2L.ext_with_length([["&gt;", 70], ["&lt;", 1000]])
-end.().output("npn13G2L.a", "Min. npn13G2L emitter length")
+    RES.ext_fast_width(0.5.um)
+end.().output("Rsil.f", "Min. RES length = 0.50")
 -&gt; do
-    emit_npn13G2L.ext_with_length([["&gt;", 2500]])
-end.().output("npn13G2L.b", "Max. npn13G2L emitter length")
+    Rppd_all.ext_fast_width(0.5.um)
+end.().output("Rppd.a", "Min. GatPoly width = 0.50")
 -&gt; do
-    emit_npn13G2V.ext_with_length([["&gt;", 120], ["&lt;", 1000]])
-end.().output("npn13G2V.a", "Min. npn13G2V emitter length")
+    Rppd_all_enclosure_pSD.dup
+end.().output("Rppd.b", "Min. pSD enclosure of GatPoly = 0.18")
+-&gt; (;x) do
+    x = SalBlock_Rppd.ext_extended(0.2.um, 0.2.um)
+    [ Rppd_Cont.ext_fast_separation(SalBlock_Rppd, 0.2.um),
+      Rppd_Cont.ext_interacting(x, inverted: true)
+    ].each { |result| result.output("Rppd.c", "Min. and max. SalBlock space to Cont = 0.20") }
+end.()
 -&gt; do
-    emit_npn13G2V.ext_with_length([["&gt;", 5000]])
-end.().output("npn13G2V.b", "Max. npn13G2V emitter length")
+    SalBlock_Rppd.ext_fast_width(0.5.um)
+end.().output("Rppd.e", "Min. SalBlock length = 0.50")
 -&gt; do
-    RES.ext_fast_separation(Cont, 120)
-end.().output("Rsil.b", "Min. RES space to Cont")
+    Rhigh_a.ext_fast_width(0.5.um)
+end.().output("Rhi.a", "Min. GatPoly width = 0.50")
 -&gt; do
-    RES.ext_fast_width(500)
-end.().output("Rsil.f", "Min. RES length")
+    Rhigh_identical_nsd_psd.dup
+end.().output("Rhi.b", "pSD and nSD are identical (Note 1)")
 -&gt; do
-    Rhigh_a.ext_fast_width(500)
-end.().output("Rhi.a", "Min. GatPoly width")
+    GP_Rhigh_extended.ext_fast_enclosed(pSD_nSD, 0.18.um, polygon_output: true)
+end.().output("Rhi.c", "Min. pSD and nSD enclosure of GatPoly = 0.18")
+-&gt; (;x) do
+    x = SalBlock_Rhigh.ext_extended(0.2.um, 0.2.um)
+    [ Rhigh_Cont.ext_fast_separation(SalBlock_Rhigh, 0.2.um),
+      Rhigh_Cont.ext_interacting(x, inverted: true)
+    ].each { |result| result.output("Rhi.d", "Min. and max. SalBlock space to Cont = 0.20") }
+end.()
 -&gt; do
-    SalBlock_Rhigh.ext_fast_width(500)
-end.().output("Rhi.f", "Min. SalBlock length")
+    SalBlock_Rhigh.ext_fast_width(0.5.um)
+end.().output("Rhi.f", "Min. SalBlock length = 0.50")
 -&gt; do
-    Iso_PWell_Act.ext_not(schottky_nbl1.ext_or(scr1)).ext_fast_separation(NWell.ext_ring, 390)
-end.().output("nmosi.c", "Min. NWell space to Iso-PWell-Activ")
+    Iso_PWell_Act.outside(schottky_nbl1).ext_fast_enclosed(nBuLay, 1.24.um, polygon_output: true)
+end.().output("nmosi.b", "Min. nBuLay enclosure of Iso-PWell-Activ (Note 1) = 1.24")
 -&gt; do
-    NWell_nBuLay.ext_fast_width(620)
-end.().output("nmosi.d", "Min. NWell-nBuLay width forming an unbroken ring around any Iso-PWell-Activ (Note 2)")
+    Iso_PWell_Act.ext_not(scr1_or_schottky_nbl1).ext_fast_separation(NWell.with_holes, 0.39.um, max_angle: 180)
+end.().output("nmosi.c", "Min. NWell space to Iso-PWell-Activ = 0.39")
 -&gt; do
-    nSDBlock_Iso_PWell_Act.ext_fast_width(620)
-end.().output("nmosi.f", "Min. nSD:block width to separate ptap in nmosi")
+    NWell_nBuLay.ext_fast_width(0.62.um)
+end.().output("nmosi.d", "Min. NWell-nBuLay width forming an unbroken ring around any Iso-PWell-Activ (Note 2) = 0.62")
+-&gt; do
+    nSDBlock_Iso_PWell_Act.ext_fast_width(0.62.um)
+end.().output("nmosi.f", "Min. nSD:block width to separate ptap in nmosi = 0.62")
 -&gt; (;tmp, x1) do
-    tmp = SalBlock_Iso_PWell_Act.ext_not(schottky_nbl1.ext_or(scr1))
-    x1 = nSDBlock_Iso_PWell_Act.ext_fast_enclosed(tmp.ext_not(tmp.ext_covering(npnMPA)), 150, polygon_output: true)
+    tmp = SalBlock_Iso_PWell_Act.ext_not(scr1_or_schottky_nbl1)
+    x1 = nSDBlock_Iso_PWell_Act.ext_fast_enclosed(tmp.ext_not(tmp.ext_covering(npnMPA)), 0.15.um, polygon_output: true)
     x1.ext_and(Activ)
-end.().output("nmosi.g", "Min. SalBlock overlap of nSD:block over Activ")
+end.().output("nmosi.g", "Min. SalBlock overlap of nSD:block over Activ = 0.15")
+-&gt; do
+    schottky_contbar.ext_fast_enclosed(schottky_pwb, 0.25.um, polygon_output: true)
+end.().output("Sdiod.a", "Min. and max. PWell:block enclosure of ContBar = 0.25")
+-&gt; do
+    schottky_contbar.ext_fast_enclosed(schottky_nSDBlock, 0.4.um, polygon_output: true)
+end.().output("Sdiod.b", "Min. and max. nSD:block enclosure of ContBar = 0.40")
+-&gt; do
+    schottky_contbar.ext_fast_enclosed(schottky_salblock, 0.45.um, polygon_output: true)
+end.().output("Sdiod.c", "Min. and max. SalBlock enclosure of ContBar = 0.45")
 
 if not $noRecommendedRules
 	-&gt; do
-	    Passiv_dfpad.ext_fast_width(30000)
-	end.().output("Pad.aR", "Min. recommended Pad width")
+	    Passiv_dfpad.ext_fast_width(30.0.um)
+	end.().output("Pad.aR", "Min. recommended Pad width = 30.00")
 end
 
 -&gt; do
     Passiv_Pad_a1.dup
-end.().output("Pad.a1", "Max. Pad width")
+end.().output("Pad.a1", "Max. Pad width = 150.00")
 
 if not $noRecommendedRules
 	-&gt; do
-	    Passiv_dfpad.ext_fast_space(8400)
-	end.().output("Pad.bR", "Min. recommended Pad space")
+	    Passiv_dfpad.ext_fast_space(8.4.um)
+	end.().output("Pad.bR", "Min. recommended Pad space = 8.40")
 end
 
 -&gt; do
-    Passiv_dfpad.ext_fast_separation(Act_EdgeSeal_not_HRACT, 7500)
-end.().output("Pad.d", "Min. Pad space to EdgeSeal")
+    Passiv_dfpad.ext_fast_separation(Act_EdgeSeal_not_HRACT, 7.5.um)
+end.().output("Pad.d", "Min. Pad space to EdgeSeal = 7.50")
 
 if not $noRecommendedRules
 	-&gt; do
-	    Passiv_dfpad.ext_fast_separation(Act_EdgeSeal_not_HRACT, 25000)
-	end.().output("Pad.dR", "Min. recommended Pad to EdgeSeal space (Note 1)")
+	    Passiv_dfpad.ext_fast_separation(Act_EdgeSeal_not_HRACT, 25.0.um)
+	end.().output("Pad.dR", "Min. recommended Pad to EdgeSeal space (Note 1) = 25.00")
+	-&gt; do
+	    Passiv_dfpad.ext_fast_separation(Act_Not_EdgeSeal, 11.2.um)
+	end.().output("Pad.d1R", "Min. recommended Pad to Activ (inside chip area) space = 11.20")
 	-&gt; do
-	    Passiv_dfpad.ext_fast_separation(Act_Not_EdgeSeal, 11200)
-	end.().output("Pad.d1R", "Min. recommended Pad to Activ (inside chip area) space")
+	    TopVia2.ext_fast_enclosed(belowTopMetaln_dfpad, 1.4.um, polygon_output: true)
+	end.().output("Pad.gR", "TopMetal1 (within dfpad) enclosure of TopVia2 = 1.40")
 	-&gt; do
-	    MIM.ext_and(Passiv_dfpad)
-	    GatPoly.ext_and(Activ).ext_and(Passiv_dfpad)
-	end.().output("Pad.jR", "No devices under Pad allowed (Note 2)")
+	    [ MIM.ext_and(Passiv_dfpad),
+	      Gate.ext_and(Passiv_dfpad)
+	    ].each { |result| result.output("Pad.jR", "No devices under Pad allowed (Note 2)") }
+	end.()
 	-&gt; do
-	    TopVia2.merged(true, 0).inside(Passiv_dfpad)
+	    TopVia2.inside(Passiv_dfpad)
 	end.().output("Pad.kR", "TopVia2 under Pad not allowed (Note 3)")
 end
 
 -&gt; do
-    cupPad_candidat.ext_fast_space(45000, polygon_output: true)
-end.().output("Padc.b", "Min. CuPillarPad space")
+    cupPad_candidat.ext_fast_space(45.0.um, polygon_output: true)
+end.().output("Padc.b", "Min. CuPillarPad space = Table 6.1")
 -&gt; do
-    cupPad_candidat.ext_fast_separation(Act_EdgeSeal_not_HRACT, 30000, polygon_output: true)
-end.().output("Padc.d", "Min. CuPillarPad space to EdgeSeal")
+    cupPad_candidat.ext_fast_separation(Act_EdgeSeal_not_HRACT, 30.0.um, consider_touch_points: false, polygon_output: true)
+end.().output("Padc.d", "Min. CuPillarPad space to EdgeSeal = 30.00")
 -&gt; do
-    Activ_edgA1_in.ext_fast_width(3500)
-end.().output("Seal.a_Activ", "Min. EdgeSeal-Activ width")
+    Activ_edgA1_in.ext_fast_width(3.5.um, metric: projection, include_max_angle: true)
+end.().output("Seal.a_Activ", "Min. EdgeSeal-Activ width = 3.50")
 -&gt; do
-    pSD_edgA1_in.ext_fast_width(3500)
-end.().output("Seal.a_pSD", "Min. EdgeSeal-pSD width")
+    pSD_edgA1_in.ext_fast_width(3.5.um, metric: projection, include_max_angle: true)
+end.().output("Seal.a_pSD", "Min. EdgeSeal-pSD width = 3.50")
 -&gt; do
-    Metal1_edgA1_in.ext_fast_width(3500)
-end.().output("Seal.a_Metal1", "Min. EdgeSeal-Metal1 width")
+    Metal1_edgA1_in.ext_fast_width(3.5.um, metric: projection, include_max_angle: true)
+end.().output("Seal.a_Metal1", "Min. EdgeSeal-Metal1 width = 3.50")
 -&gt; do
-    Metal2_edgA1_in.ext_fast_width(3500)
-end.().output("Seal.a_Metal2", "Min. EdgeSeal-Metal2 width")
+    Metal2_edgA1_in.ext_fast_width(3.5.um, metric: projection, include_max_angle: true)
+end.().output("Seal.a_Metal2", "Min. EdgeSeal-Metal2 width = 3.50")
 -&gt; do
-    Metal3_edgA1_in.ext_fast_width(3500)
-end.().output("Seal.a_Metal3", "Min. EdgeSeal-Metal3 width")
+    Metal3_edgA1_in.ext_fast_width(3.5.um, metric: projection, include_max_angle: true)
+end.().output("Seal.a_Metal3", "Min. EdgeSeal-Metal3 width = 3.50")
 -&gt; do
-    Metal4_edgA1_in.ext_fast_width(3500)
-end.().output("Seal.a_Metal4", "Min. EdgeSeal-Metal4 width")
+    Metal4_edgA1_in.ext_fast_width(3.5.um, metric: projection, include_max_angle: true)
+end.().output("Seal.a_Metal4", "Min. EdgeSeal-Metal4 width = 3.50")
 -&gt; do
-    Metal5_edgA1_in.ext_fast_width(3500)
-end.().output("Seal.a_Metal5", "Min. EdgeSeal-Metal5 width")
+    Metal5_edgA1_in.ext_fast_width(3.5.um, metric: projection, include_max_angle: true)
+end.().output("Seal.a_Metal5", "Min. EdgeSeal-Metal5 width = 3.50")
 -&gt; do
-    TopMetal1_edgA1_in.ext_fast_width(3500)
-end.().output("Seal.a_TopMetal1", "Min. EdgeSeal-TopMetal1 width")
+    TopMetal1_edgA1_in.ext_fast_width(3.5.um, metric: projection, include_max_angle: true)
+end.().output("Seal.a_TopMetal1", "Min. EdgeSeal-TopMetal1 width = 3.50")
 -&gt; do
-    TopMetal2_edgA1_in.ext_fast_width(3500)
-end.().output("Seal.a_TopMetal2", "Min. EdgeSeal-TopMetal2 width")
+    TopMetal2_edgA1_in.ext_fast_width(3.5.um, metric: projection, include_max_angle: true)
+end.().output("Seal.a_TopMetal2", "Min. EdgeSeal-TopMetal2 width = 3.50")
 -&gt; do
-    Cont_edgC1_in.ext_fast_width(160)
-    Cont_edgC1_in.drc((width(projection) &gt; 160).polygons)
-end.().output("Seal.c", "EdgeSeal-Cont ring width")
+    [ Cont_edgC1_in.ext_fast_width(0.16.um),
+      Cont_edgC1_in.drc((width(projection) &gt; 0.16.um).polygons)
+    ].each { |result| result.output("Seal.c", "EdgeSeal-Cont ring width = 0.16") }
+end.()
 -&gt; do
-    Via1_edgC1_in.ext_fast_width(190)
-    Via1_edgC1_in.drc((width(projection) &gt; 190).polygons)
-end.().output("Seal.c1.Via1", "EdgeSeal-Via1 ring width")
+    [ Via1_edgC1_in.ext_fast_width(0.19.um),
+      Via1_edgC1_in.drc((width(projection) &gt; 0.19.um).polygons)
+    ].each { |result| result.output("Seal.c1.Via1", "EdgeSeal-Via1 ring width = 0.19") }
+end.()
 -&gt; do
-    Via2_edgC1_in.ext_fast_width(190)
-    Via2_edgC1_in.drc((width(projection) &gt; 190).polygons)
-end.().output("Seal.c1.Via2", "EdgeSeal-Via2 ring width")
+    [ Via2_edgC1_in.ext_fast_width(0.19.um),
+      Via2_edgC1_in.drc((width(projection) &gt; 0.19.um).polygons)
+    ].each { |result| result.output("Seal.c1.Via2", "EdgeSeal-Via2 ring width = 0.19") }
+end.()
 -&gt; do
-    Via3_edgC1_in.ext_fast_width(190)
-    Via3_edgC1_in.drc((width(projection) &gt; 190).polygons)
-end.().output("Seal.c1.Via3", "EdgeSeal-Via3 ring width")
+    [ Via3_edgC1_in.ext_fast_width(0.19.um),
+      Via3_edgC1_in.drc((width(projection) &gt; 0.19.um).polygons)
+    ].each { |result| result.output("Seal.c1.Via3", "EdgeSeal-Via3 ring width = 0.19") }
+end.()
 -&gt; do
-    Via4_edgC1_in.ext_fast_width(190)
-    Via4_edgC1_in.drc((width(projection) &gt; 190).polygons)
-end.().output("Seal.c1.Via4", "EdgeSeal-Via4 ring width")
+    [ Via4_edgC1_in.ext_fast_width(0.19.um),
+      Via4_edgC1_in.drc((width(projection) &gt; 0.19.um).polygons)
+    ].each { |result| result.output("Seal.c1.Via4", "EdgeSeal-Via4 ring width = 0.19") }
+end.()
 -&gt; do
-    TopVia1_edgC1_in.ext_fast_width(420)
-    TopVia1_edgC1_in.drc((width(projection) &gt; 420).polygons)
-end.().output("Seal.c2", "EdgeSeal-TopVia1 ring width")
+    [ TopVia1_edgC1_in.ext_fast_width(0.42.um),
+      TopVia1_edgC1_in.drc((width(projection) &gt; 0.42.um).polygons)
+    ].each { |result| result.output("Seal.c2", "EdgeSeal-TopVia1 ring width = 0.42") }
+end.()
 -&gt; do
-    TopVia2_edgC1_in.ext_fast_width(900)
-    TopVia2_edgC1_in.drc((width(projection) &gt; 900).polygons)
-end.().output("Seal.c3", "EdgeSeal-TopVia2 ring width")
+    [ TopVia2_edgC1_in.ext_fast_width(0.9.um),
+      TopVia2_edgC1_in.drc((width(projection) &gt; 0.9.um).polygons)
+    ].each { |result| result.output("Seal.c3", "EdgeSeal-TopVia2 ring width = 0.90") }
+end.()
 -&gt; do
-    seal_passiv.ext_fast_width(4200)
-end.().output("Seal.e", "Min. Passiv ring width outside of sealring")
+    seal_passiv.ext_fast_width(4.2.um)
+end.().output("Seal.e", "Min. Passiv ring width outside of sealring = 4.20")
 -&gt; do
     MIM_Mim_a.dup
-end.().output("MIM.a", "Min. MIM width")
+end.().output("MIM.a", "Min. MIM width = 1.14")
 -&gt; do
-    MIM.ext_fast_space(600)
-end.().output("MIM.b", "Min. MIM space")
+    MIM.ext_fast_space(0.6.um)
+end.().output("MIM.b", "Min. MIM space = 0.60")
 -&gt; do
-    TopMetal1.ext_fast_separation(MIM, 600)
-end.().output("MIM.e", "Min. TopMetal1 space to MIM")
+    TopMetal1.ext_fast_separation(MIM, 0.6.um)
+end.().output("MIM.e", "Min. TopMetal1 space to MIM = 0.60")
 -&gt; do
     MIM_Mim_f.dup
-end.().output("MIM.f", "Min. MIM area per MIM device (µm²)")
+end.().output("MIM.f", "Min. MIM area per MIM device (µm²) = 1.30")
 -&gt; do
-    MIM.ext_area([["&gt;", 5625.0]])
-end.().output("MIM.g", "Max. MIM area per MIM device (µm²)")
+    MIM.ext_with_area([["&gt;", 5625.0.um2]])
+end.().output("MIM.g", "Max. MIM area per MIM device (µm²) = 5625.00")
 -&gt; do
-    MIM.ext_not(MIM.ext_covering(TopVia1.ext_or(Vmim)))
+    MIM.ext_not(temp_layer_1)
 end.().output("MIM.h", "TopVia1 must be over MIM")
--&gt; do
-    Metal1_slit.ext_not(pad).ext_fast_width(2800)
-end.().output("Slt.a.M1", "Min. Metal1:slit width")
+-&gt; (;x) do
+    x = all_ntie.ext_enlarge_inside(NWell, 20.0.um, 0.1.um)
+    PAct_NWell.ext_not(x).outside(devExclud)
+end.().output("LU.a", "Max. space from any portion of P+Activ inside NWell to an nSD-NWell tie = 20.00")
+-&gt; (;sizedA, drcErrA, drcErrA_Edge, drcErrA_Poly) do
+    sizedA = Abut_NWell_Tie_Cont.ext_enlarge_inside(Act_connect.ext_interacting(Gate), 6.0.um, 0.21.um).ext_interacting(Cont_not_outside_NAct, inverted: true)
+    drcErrA = Abut_NWell_Tie.ext_not(sizedA)
+    drcErrA_Edge = drcErrA.ext_coincident_part(sizedA, outside: true)
+    drcErrA_Poly = drcErrA.ext_with_coincident_edges(drcErrA_Edge)
+    drcErrA_Poly.ext_interacting(Cont_not_outside_NAct, inverted: true)
+end.().output("LU.c", "Max. extension of an abutted NWell tie beyond Cont = 6.00")
+-&gt; (;sizedA, drcErrA, drcErrA_Edge, drcErrA_Poly) do
+    sizedA = Abut_PWell_Tie_Cont.ext_enlarge_inside(Act_connect, 6.0.um, 0.21.um).ext_interacting(Cont_not_outside_PAct, inverted: true)
+    drcErrA = Abut_PWell_Tie.ext_not(sizedA)
+    drcErrA_Edge = drcErrA.ext_coincident_part(sizedA, outside: true)
+    drcErrA_Poly = drcErrA.ext_with_coincident_edges(drcErrA_Edge)
+    drcErrA_Poly.ext_interacting(Cont_not_outside_PAct, inverted: true)
+end.().output("LU.c1", "Max. extension of an abutted substrate tie beyond Cont = 6.00")
+-&gt; (;sizedA, tmp, drcErrA, drcErrA_Edge) do
+    sizedA = size_Cont.dup
+    tmp = NAct_NWell.outside(scr1).ext_interacting(Activ.ext_interacting(GatPoly), inverted: true)
+    drcErrA = tmp.ext_not(sizedA)
+    drcErrA_Edge = drcErrA.ext_coincident_part(sizedA, outside: true)
+    drcErrA.ext_with_coincident_edges(drcErrA_Edge)
+end.().output("LU.d", "Max. extension of NWell tie Activ tie beyond Cont = 6.00")
+-&gt; (;sizedA, drcErrA, drcErrA_Edge) do
+    sizedA = Cont.ext_enlarge_inside(Act_connect, 6.0.um, 0.21.um)
+    drcErrA = PWell_Tie_wo_varicap_abut.ext_not(sizedA).ext_not(GatPoly)
+    drcErrA_Edge = drcErrA.ext_coincident_part(sizedA, outside: true)
+    drcErrA.ext_with_coincident_edges(drcErrA_Edge)
+end.().output("LU.d1", "Max. extension of an substrate tie Activ beyond Cont = 6.00")
+-&gt; do
+    Metal1_slit_not_pad.ext_fast_width(2.8.um)
+end.().output("Slt.a.M1", "Min. Metal1:slit width = 2.80")
+-&gt; (;tmp) do
+    tmp = Metal1_slit_not_pad.ext_with_length([["&gt;", 20.0.um]])
+    Metal1_slit.ext_with_coincident_edges(tmp)
+end.().output("Slt.b.M1", "Max. Metal1:slit width = 20.00")
+-&gt; (;m1mitSlots, m1_L1, m1_L2) do
+    m1mitSlots = sltc_M1.ext_not(Metal1_slit)
+    m1_L1 = m1mitSlots.sized(-3.0.um, acute_limit)
+    m1_L2 = m1_L1.sized(-12.0.um, acute_limit)
+    m1_L2.sized(15.0.um, acute_limit)
+end.().output("Slt.c.M1", "Max. Metal1 width without requiring a slit = 30.00")
 -&gt; do
     Metal1_slit.ext_and(pad)
 end.().output("Slt.e.M1", "No slits required on bond pads")
 -&gt; do
-    Metal1_slit.ext_not(pad).ext_fast_separation(Cont, 300)
-    Metal1_slit.ext_not(pad).ext_fast_separation(Via1, 300)
-end.().output("Slt.h1", "Min. Metal1:slit space to Cont and Via1")
--&gt; do
-    Metal2_slit.ext_not(pad).ext_fast_width(2800)
-end.().output("Slt.a.M2", "Min. Metal2:slit width")
+    Metal1_slit_not_pad.ext_fast_enclosed(Metal1, 1.0.um, polygon_output: true)
+end.().output("Slt.f.M1", "Min. Metal1 enclosure of Metal1:slit = 1.00")
+-&gt; do
+    [ Metal1_slit_not_pad.ext_fast_separation(Cont, 0.3.um),
+      Metal1_slit_not_pad.ext_fast_separation(Via1, 0.3.um)
+    ].each { |result| result.output("Slt.h1", "Min. Metal1:slit space to Cont and Via1 = 0.30") }
+end.()
+-&gt; do
+    Metal2_slit_not_pad.ext_fast_width(2.8.um)
+end.().output("Slt.a.M2", "Min. Metal2:slit width = 2.80")
+-&gt; (;tmp) do
+    tmp = Metal2_slit_not_pad.ext_with_length([["&gt;", 20.0.um]])
+    Metal2_slit.ext_with_coincident_edges(tmp)
+end.().output("Slt.b.M2", "Max. Metal2:slit width = 20.00")
+-&gt; (;m2mitSlots, m2_L1, m2_L2) do
+    m2mitSlots = sltc_M2.ext_not(Metal2_slit)
+    m2_L1 = m2mitSlots.sized(-3.0.um, acute_limit)
+    m2_L2 = m2_L1.sized(-12.0.um, acute_limit)
+    m2_L2.sized(15.0.um, acute_limit)
+end.().output("Slt.c.M2", "Max. Metal2 width without requiring a slit = 30.00")
 -&gt; do
     Metal2_slit.ext_and(pad)
 end.().output("Slt.e.M2", "No slits required on bond pads")
 -&gt; do
-    Metal2_slit.ext_not(pad).ext_fast_separation(Via1, 300)
-    Metal2_slit.ext_not(pad).ext_fast_separation(Via2, 300)
-end.().output("Slt.h2.M2", "Min. Metal2:slit space to Via1 and Via2")
--&gt; do
-    Metal3_slit.ext_not(pad).ext_fast_width(2800)
-end.().output("Slt.a.M3", "Min. Metal3:slit width")
+    Metal2_slit_not_pad.ext_fast_enclosed(Metal2, 1.0.um, polygon_output: true)
+end.().output("Slt.f.M2", "Min. Metal2 enclosure of Metal2:slit = 1.00")
+-&gt; do
+    [ Metal2_slit_not_pad.ext_fast_separation(Via1, 0.3.um),
+      Metal2_slit_not_pad.ext_fast_separation(Via2, 0.3.um)
+    ].each { |result| result.output("Slt.h2.M2", "Min. Metal2:slit space to Via1 and Via2 = 0.30") }
+end.()
+-&gt; do
+    Metal3_slit_not_pad.ext_fast_width(2.8.um)
+end.().output("Slt.a.M3", "Min. Metal3:slit width = 2.80")
+-&gt; (;tmp) do
+    tmp = Metal3_slit_not_pad.ext_with_length([["&gt;", 20.0.um]])
+    Metal3_slit.ext_with_coincident_edges(tmp)
+end.().output("Slt.b.M3", "Max. Metal3:slit width = 20.00")
+-&gt; (;m3mitSlots, m3_L1, m3_L2) do
+    m3mitSlots = sltc_M3.ext_not(Metal3_slit)
+    m3_L1 = m3mitSlots.sized(-3.0.um, acute_limit)
+    m3_L2 = m3_L1.sized(-12.0.um, acute_limit)
+    m3_L2.sized(15.0.um, acute_limit)
+end.().output("Slt.c.M3", "Max. Metal3 width without requiring a slit = 30.00")
 -&gt; do
     Metal3_slit.ext_and(pad)
 end.().output("Slt.e.M3", "No slits required on bond pads")
 -&gt; do
-    Metal3_slit.ext_not(pad).ext_fast_separation(Via2, 300)
-    Metal3_slit.ext_not(pad).ext_fast_separation(Via3, 300)
-end.().output("Slt.h2.M3", "Min. Metal3:slit space to Via2 and Via3")
--&gt; do
-    Metal4_slit.ext_not(pad).ext_fast_width(2800)
-end.().output("Slt.a.M4", "Min. Metal4:slit width")
+    Metal3_slit_not_pad.ext_fast_enclosed(Metal3, 1.0.um, polygon_output: true)
+end.().output("Slt.f.M3", "Min. Metal3 enclosure of Metal2:slit = 1.00")
+-&gt; do
+    [ Metal3_slit_not_pad.ext_fast_separation(Via2, 0.3.um),
+      Metal3_slit_not_pad.ext_fast_separation(Via3, 0.3.um)
+    ].each { |result| result.output("Slt.h2.M3", "Min. Metal3:slit space to Via2 and Via3 = 0.30") }
+end.()
+-&gt; do
+    Metal4_slit_not_pad.ext_fast_width(2.8.um)
+end.().output("Slt.a.M4", "Min. Metal4:slit width = 2.80")
+-&gt; (;tmp) do
+    tmp = Metal4_slit_not_pad.ext_with_length([["&gt;", 20.0.um]])
+    Metal4_slit.ext_with_coincident_edges(tmp)
+end.().output("Slt.b.M4", "Max. Metal4:slit width = 20.00")
+-&gt; (;m4mitSlots, m4_L1, m4_L2) do
+    m4mitSlots = sltc_M4.ext_not(Metal4_slit)
+    m4_L1 = m4mitSlots.sized(-3.0.um, acute_limit)
+    m4_L2 = m4_L1.sized(-12.0.um, acute_limit)
+    m4_L2.sized(15.0.um, acute_limit)
+end.().output("Slt.c.M4", "Max. Metal4 width without requiring a slit = 30.00")
 -&gt; do
     Metal4_slit.ext_and(pad)
 end.().output("Slt.e.M4", "No slits required on bond pads")
 -&gt; do
-    Metal4_slit.ext_not(pad).ext_fast_separation(Via3, 300)
-    Metal4_slit.ext_not(pad).ext_fast_separation(Via4, 300)
-end.().output("Slt.h2.M4", "Min. Metal4:slit space to Via3 and Via4")
--&gt; do
-    Metal5_slit.ext_not(pad).ext_fast_width(2800)
-end.().output("Slt.a.M5", "Min. Metal5:slit width")
+    Metal4_slit_not_pad.ext_fast_enclosed(Metal4, 1.0.um, polygon_output: true)
+end.().output("Slt.f.M4", "Min. Metal4 enclosure of Metal4:slit = 1.00")
+-&gt; do
+    [ Metal4_slit_not_pad.ext_fast_separation(Via3, 0.3.um),
+      Metal4_slit_not_pad.ext_fast_separation(Via4, 0.3.um)
+    ].each { |result| result.output("Slt.h2.M4", "Min. Metal4:slit space to Via3 and Via4 = 0.30") }
+end.()
+-&gt; do
+    Metal5_slit_not_pad.ext_fast_width(2.8.um)
+end.().output("Slt.a.M5", "Min. Metal5:slit width = 2.80")
+-&gt; (;tmp) do
+    tmp = Metal5_slit_not_pad.ext_with_length([["&gt;", 20.0.um]])
+    Metal5_slit.ext_with_coincident_edges(tmp)
+end.().output("Slt.b.M5", "Max. Metal5:slit width = 20.00")
+-&gt; (;m5mitSlots, m5_L1, m5_L2) do
+    m5mitSlots = sltc_M5.ext_not(Metal5_slit)
+    m5_L1 = m5mitSlots.sized(-3.0.um, acute_limit)
+    m5_L2 = m5_L1.sized(-12.0.um, acute_limit)
+    m5_L2.sized(15.0.um, acute_limit)
+end.().output("Slt.c.M5", "Max. Metal5 width without requiring a slit = 30.00")
 -&gt; do
     Metal5_slit.ext_and(pad)
 end.().output("Slt.e.M5", "No slits required on bond pads")
 -&gt; do
-    Metal5_slit.ext_not(pad).ext_fast_separation(Via4, 300)
-    Metal5_slit.ext_not(pad).ext_fast_separation(TopVia1, 300)
-end.().output("Slt.h2.M5", "Min. Metal5:slit space to Via4 and Via5")
--&gt; do
-    TopMetal1_slit.ext_not(pad).ext_fast_width(2800)
-end.().output("Slt.a.TM1", "Min. TopMetal1:slit width")
+    Metal5_slit_not_pad.ext_fast_enclosed(Metal5, 1.0.um, polygon_output: true)
+end.().output("Slt.f.M5", "Min. Metal5 enclosure of Metal5:slit = 1.00")
+-&gt; do
+    Metal5_slit_MIM_Slt_g_M5_sep.dup
+end.().output("Slt.g.M5", "Min. Metal5:slit and TopMetal1:slit space to MIM = 0.60")
+-&gt; do
+    [ Metal5_slit_not_pad.ext_fast_separation(Via4, 0.3.um),
+      Metal5_slit_not_pad.ext_fast_separation(TopVia1, 0.3.um)
+    ].each { |result| result.output("Slt.h2.M5", "Min. Metal5:slit space to Via4 and Via5 = 0.30") }
+end.()
+-&gt; do
+    TopMetal1_slit_not_pad.ext_fast_width(2.8.um)
+end.().output("Slt.a.TM1", "Min. TopMetal1:slit width = 2.80")
+-&gt; (;tmp) do
+    tmp = TopMetal1_slit_not_pad.ext_with_length([["&gt;", 20.0.um]])
+    TopMetal1_slit.ext_with_coincident_edges(tmp)
+end.().output("Slt.b.TM1", "Max. TopMetal1:slit width = 20.00")
+-&gt; (;tM1mitSlots, tM1_L1, tM1_L2) do
+    tM1mitSlots = sltc_TM1.ext_not(TopMetal1_slit)
+    tM1_L1 = tM1mitSlots.sized(-3.0.um, acute_limit)
+    tM1_L2 = tM1_L1.sized(-12.0.um, acute_limit)
+    tM1_L2.sized(15.0.um, acute_limit)
+end.().output("Slt.c.TM1", "Max. TopMetal1 width without requiring a slit = 30.00")
 -&gt; do
     TopMetal1_slit.ext_and(pad)
 end.().output("Slt.e.TM1", "No slits required on bond pads")
 -&gt; do
-    TopMetal1_slit.ext_not(pad).ext_fast_separation(TopVia1, 1000)
-end.().output("Slt.h3", "Min. TopMetal1:slit space to TopVia1 and TopVia2")
+    TopMetal1_slit_not_pad.ext_fast_enclosed(TopMetal1, 1.0.um, polygon_output: true)
+end.().output("Slt.f.TM1", "Min. TopMetal1 enclosure of TopMetal1:slit = 1.00")
+-&gt; do
+    TopMetal1_slit_MIM_Slt_g_TM1_sep.dup
+end.().output("Slt.g.TM1", "Min. Metal5:slit and TopMetal1:slit space to MIM = 0.60")
+-&gt; do
+    TopMetal1_slit_not_pad.ext_fast_separation(TopVia1, 1.0.um)
+end.().output("Slt.h3", "Min. TopMetal1:slit space to TopVia1 and TopVia2 = 1.00")
 -&gt; do
-    TopMetal2_slit.ext_not(pad).ext_fast_width(2800)
-end.().output("Slt.a.TM2", "Min. TopMetal2:slit width")
+    TopMetal2_slit_not_pad.ext_fast_width(2.8.um)
+end.().output("Slt.a.TM2", "Min. TopMetal2:slit width = 2.80")
+-&gt; (;tmp) do
+    tmp = TopMetal2_slit_not_pad.ext_with_length([["&gt;", 20.0.um]])
+    TopMetal2_slit.ext_with_coincident_edges(tmp)
+end.().output("Slt.b.TM2", "Max. TopMetal2:slit width = 20.00")
+-&gt; (;tM2mitSlots, tM2_L1, tM2_L2) do
+    tM2mitSlots = sltc_TM2.ext_not(TopMetal2_slit)
+    tM2_L1 = tM2mitSlots.sized(-3.0.um, acute_limit)
+    tM2_L2 = tM2_L1.sized(-12.0.um, acute_limit)
+    tM2_L2.sized(15.0.um, acute_limit)
+end.().output("Slt.c.TM2", "Max. TopMetal2 width without requiring a slit = 30.00")
 -&gt; do
     TopMetal2_slit.ext_and(pad)
 end.().output("Slt.e.TM2", "No slits required on bond pads")
 -&gt; do
-    TopMetal2_slit.ext_not(pad).ext_fast_separation(TopVia2, 1000)
-end.().output("Slt.h4", "Min. TopMetal2:slit space to TopVia2")
+    TopMetal2_slit_not_pad.ext_fast_enclosed(TopMetal2, 1.0.um, polygon_output: true)
+end.().output("Slt.f.TM2", "Min. TopMetal2 enclosure of TopMetal2:slit = 1.00")
+-&gt; do
+    TopMetal2_slit_not_pad.ext_fast_separation(TopVia2, 1.0.um)
+end.().output("Slt.h4", "Min. TopMetal2:slit space to TopVia2 = 1.00")
 
 if $sanityRules
 	-&gt; do
 	    Activ_pin.ext_not(Activ)
-	end.().output("Pin.a", "Min. Activ enclosure of Activ:pin")
+	end.().output("Pin.a", "Min. Activ enclosure of Activ:pin = 0.00")
 	-&gt; do
 	    GatPoly_pin.ext_not(GatPoly)
-	end.().output("Pin.b", "Min. GatPoly enclosure of GatPoly:pin")
+	end.().output("Pin.b", "Min. GatPoly enclosure of GatPoly:pin = 0.00")
 	-&gt; do
 	    Metal1_pin.ext_not(Metal1)
-	end.().output("Pin.e", "Min. Metal1 enclosure of Metal1:pin")
+	end.().output("Pin.e", "Min. Metal1 enclosure of Metal1:pin = 0.00")
 	-&gt; do
 	    Metal2_pin.ext_not(Metal2)
-	end.().output("Pin.f.M2", "Min. Metal2 enclosure of Metal2:pin")
+	end.().output("Pin.f.M2", "Min. Metal2 enclosure of Metal2:pin = 0.00")
 	-&gt; do
 	    Metal3_pin.ext_not(Metal3)
-	end.().output("Pin.f.M3", "Min. Metal3 enclosure of Metal3:pin")
+	end.().output("Pin.f.M3", "Min. Metal3 enclosure of Metal3:pin = 0.00")
 	-&gt; do
 	    Metal4_pin.ext_not(Metal4)
-	end.().output("Pin.f.M4", "Min. Metal4 enclosure of Metal4:pin")
+	end.().output("Pin.f.M4", "Min. Metal4 enclosure of Metal4:pin = 0.00")
 	-&gt; do
 	    Metal5_pin.ext_not(Metal5)
-	end.().output("Pin.f.M5", "Min. Metal5 enclosure of Metal5:pin")
+	end.().output("Pin.f.M5", "Min. Metal5 enclosure of Metal5:pin = 0.00")
 	-&gt; do
 	    TopMetal1_pin.ext_not(TopMetal1)
-	end.().output("Pin.g", "Min. TopMetal1 enclosure of TopMetal1:pin")
+	end.().output("Pin.g", "Min. TopMetal1 enclosure of TopMetal1:pin = 0.00")
 	-&gt; do
 	    TopMetal2_pin.ext_not(TopMetal2)
-	end.().output("Pin.h", "Min. TopMetal2 enclosure of TopMetal2:pin")
+	end.().output("Pin.h", "Min. TopMetal2 enclosure of TopMetal2:pin = 0.00")
 end
 
 -&gt; do
-    NWell.ext_fast_separation(NActHV_digi, 310)
-end.().output("NW.d1.dig", "Min. NWell space to external N+Activ inside ThickGateOx")
+    NWell.ext_fast_separation(NActHV_digi, 0.31.um)
+end.().output("NW.d1.dig", "Min. NWell space to external N+Activ inside ThickGateOx = 0.31")
 -&gt; do
-    NWell.ext_fast_separation(PAct_PWellHV_digi, 240)
-end.().output("NW.f1.dig", "Min. NWell space to substrate tie in P+Activ inside ThickGateOx")
+    NWell.ext_fast_separation(PAct_PWellHV_digi, 0.24.um)
+end.().output("NW.f1.dig", "Min. NWell space to substrate tie in P+Activ inside ThickGateOx = 0.24")
 -&gt; do
     GP_SRAM_Gat_a_SRAM.dup
-end.().output("Gat.a.SRAM", "Min. GatPoly width")
+end.().output("Gat.a.SRAM", "Min. GatPoly width = 0.069")
 -&gt; do
     GP_SRAM_Gat_b_SRAM.dup
-end.().output("Gat.b.SRAM", "Min. GatPoly space or notch")
+end.().output("Gat.b.SRAM", "Min. GatPoly space or notch = 0.149")
+-&gt; do
+    Activ.ext_fast_enclosed(GP_SRAM, 0.079.um, polygon_output: true)
+end.().output("Gat.c.SRAM", "Min. GatPoly extension over Activ (end cap) = 0.079")
 -&gt; do
-    GP_SRAM.ext_fast_separation(Act_SRAM, 29)
-end.().output("Gat.d.SRAM", "Min. GatPoly space to Activ")
+    GP_SRAM.ext_fast_separation(Act_SRAM, 0.029.um)
+end.().output("Gat.d.SRAM", "Min. GatPoly space to Activ = 0.029")
 -&gt; (;layA, layB, layC, layD) do
-    layA = Activ.ext_and(SRAM).merged(true, 0).not_inside(pSD).ext_interacting(pSD)
+    layA = Activ.ext_and(SRAM).not_inside(pSD).ext_interacting(pSD)
     layB = layA.ext_and(pSD)
-    layC = layB.ext_fast_width(280, polygon_output: true)
+    layC = layB.ext_fast_width(0.28.um, metric: projection, consider_intersecting_edges: false, consider_touch_points: false, polygon_output: true)
     layD = layC.ext_covering(layB)
     layD.dup
-end.().output("pSD.e.SRAM", "Min. pSD overlap of Activ when forming abutted substrate tie")
--&gt; do
-    pSD_SRAM.ext_fast_separation(NGate.merged(true, 0).outside(SVaricap), 239)
-end.().output("pSD.j.SRAM", "Min. pSD space to NFET gate not inside ThickGateOx")
--&gt; do
-    Cont_Act.ext_fast_separation(GP_SRAM, 59)
-end.().output("Cnt.f.SRAM", "Min. Cont on Activ space to GatPoly")
--&gt; do
-    M1_SRAM.ext_fast_space(159)
-end.().output("M1.b.SRAM", "Min. Metal1 space or notch")
--&gt; do
-    M2_SRAM.ext_fast_space(169)
-end.().output("M2.b.SRAM", "Min. Metal2 space or notch")
--&gt; do
-    M3_SRAM.ext_fast_space(169)
-end.().output("M3.b.SRAM", "Min. Metal3 space or notch")
--&gt; do
-    M4_SRAM.ext_fast_space(169)
-end.().output("M4.b.SRAM", "Min. Metal4 space or notch")
--&gt; do
-    M5_SRAM.ext_fast_space(169)
-end.().output("M5.b.SRAM", "Min. Metal5 space or notch")
--&gt; do
-    LBE.ext_fast_width(100000)
-end.().output("LBE.a", "Min. LBE width")
--&gt; do
-    LBE.drc((width(projection) &gt; 1500000).polygons)
-end.().output("LBE.b", "Max. LBE width")
--&gt; do
-    LBE.ext_area([["&gt;", 250000.0]])
-end.().output("LBE.b1", "Max. LBE area (µm²)")
--&gt; do
-    LBE.ext_area([["&lt;", 250000.0]])
-end.().output("LBE.b2", "Min. LBE area (µm²)")
--&gt; do
-    LBE.ext_fast_space(100000)
-end.().output("LBE.c", "Min. LBE space or notch")
+end.().output("pSD.e.SRAM", "Min. pSD overlap of Activ when forming abutted substrate tie = 0.28")
+-&gt; (;x, y) do
+    x = abut_tie_edge_NWell.ext_inside_part(SRAM)
+    y = abut_tie_edge_PWell.ext_inside_part(SRAM)
+    [ x.ext_with_length([["&lt;", 0.15.um]]),
+      y.ext_with_length([["&lt;", 0.15.um]])
+    ].each { |result| result.output("pSD.g.SRAM", "Min. N+Activ or P+Activ width when forming abutted tie = 0.15") }
+end.()
+-&gt; do
+    PGate.ext_fast_enclosed(pSD_SRAM, 0.068.um, polygon_output: true)
+end.().output("pSD.i.SRAM", "Min. pSD enclosure of PFET gate not inside ThickGateOx = 0.068")
+-&gt; do
+    pSD_SRAM.ext_fast_separation(NGate_outside_SVaricap, 0.239.um)
+end.().output("pSD.j.SRAM", "Min. pSD space to NFET gate not inside ThickGateOx = 0.239")
+-&gt; do
+    Cont_Act.ext_fast_separation(GP_SRAM, 0.059.um)
+end.().output("Cnt.f.SRAM", "Min. Cont on Activ space to GatPoly = 0.059")
+-&gt; do
+    M1_SRAM.ext_fast_space(0.159.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true)
+end.().output("M1.b.SRAM", "Min. Metal1 space or notch = 0.159")
+-&gt; do
+    Cont_SRAM.outside(EdgeSeal).drc(if_any(
+        !rectangles,
+        primary-secondary(M1_SRAM_outside_EdgeSeal),
+        ((enclosed(M1_SRAM_outside_EdgeSeal, projection, whole_edges, one_side_allowed, two_opposite_sides_allowed) &lt; 0.005.um))))
+end.().output("M1.c1.SRAM", "Min. Metal1 endcap enclosure of Cont = 0.005")
+-&gt; do
+    M2_SRAM.ext_fast_space(0.169.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true)
+end.().output("M2.b.SRAM", "Min. Metal2 space or notch = 0.169")
+-&gt; do
+    V1_SRAM_outside_EdgeSeal.drc(if_any(
+        !rectangles,
+        primary-secondary(M2_SRAM.outside(EdgeSeal)),
+        ((enclosed(M2_SRAM.outside(EdgeSeal), projection, whole_edges, one_side_allowed, two_opposite_sides_allowed) &lt; 0.02.um))))
+end.().output("M2.c1.SRAM", "Min. Metal2 endcap enclosure of Via1 = 0.02")
+-&gt; do
+    M3_SRAM.ext_fast_space(0.169.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true)
+end.().output("M3.b.SRAM", "Min. Metal3 space or notch = 0.169")
+-&gt; do
+    V2_SRAM_outside_EdgeSeal.drc(if_any(
+        !rectangles,
+        primary-secondary(M3_SRAM.outside(EdgeSeal)),
+        ((enclosed(M3_SRAM.outside(EdgeSeal), projection, whole_edges, one_side_allowed, two_opposite_sides_allowed) &lt; 0.02.um))))
+end.().output("M3.c1.SRAM", "Min. Metal3 endcap enclosure of Via2 = 0.02")
+-&gt; do
+    M4_SRAM.ext_fast_space(0.169.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true)
+end.().output("M4.b.SRAM", "Min. Metal4 space or notch = 0.169")
+-&gt; do
+    V3_SRAM_outside_EdgeSeal.drc(if_any(
+        !rectangles,
+        primary-secondary(M4_SRAM.outside(EdgeSeal)),
+        ((enclosed(M4_SRAM.outside(EdgeSeal), projection, whole_edges, one_side_allowed, two_opposite_sides_allowed) &lt; 0.02.um))))
+end.().output("M4.c1.SRAM", "Min. Metal4 endcap enclosure of Via3 = 0.02")
+-&gt; do
+    M5_SRAM.ext_fast_space(0.169.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true)
+end.().output("M5.b.SRAM", "Min. Metal5 space or notch = 0.169")
+-&gt; do
+    V4_SRAM_outside_EdgeSeal.drc(if_any(
+        !rectangles,
+        primary-secondary(M5_SRAM.outside(EdgeSeal)),
+        ((enclosed(M5_SRAM.outside(EdgeSeal), projection, whole_edges, one_side_allowed, two_opposite_sides_allowed) &lt; 0.02.um))))
+end.().output("M5.c1.SRAM", "Min. Metal5 endcap enclosure of Via4 = 0.02")
+-&gt; do
+    LBE.ext_fast_width(100.0.um)
+end.().output("LBE.a", "Min. LBE width = 100.00")
+-&gt; do
+    LBE.drc((width(projection) &gt; 1500.0.um).polygons)
+end.().output("LBE.b", "Max. LBE width = 1500.00")
+-&gt; do
+    LBE.ext_with_area([["&gt;", 250000.0.um2]])
+end.().output("LBE.b1", "Max. LBE area (µm²) = 250000.00")
+-&gt; do
+    LBE.ext_with_area([["&lt;", 250000.0.um2]])
+end.().output("LBE.b2", "Min. LBE area (µm²) = 30000.00")
+-&gt; do
+    LBE.ext_fast_space(100.0.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true)
+end.().output("LBE.c", "Min. LBE space or notch = 100.00")
 -&gt; (;lbe_in_seal) do
-    lbe_in_seal = LBE.merged(true, 0).inside(EdgeSeal.holes.merge)
-    lbe_in_seal.ext_fast_separation(EdgeSeal, 150000)
-end.().output("LBE.d", "Min. LBE space to inner edge of EdgeSeal")
+    lbe_in_seal = LBE.inside(EdgeSeal.holes.merge)
+    lbe_in_seal.ext_fast_separation(EdgeSeal, 150.0.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true)
+end.().output("LBE.d", "Min. LBE space to inner edge of EdgeSeal = 150.00")
 -&gt; do
-    LBE.ext_fast_separation(dfpad, 50000)
-end.().output("LBE.e.dfPad", "Min. LBE space to dfpad and Passiv")
+    LBE.ext_fast_separation(dfpad, 50.0.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true)
+end.().output("LBE.e.dfPad", "Min. LBE space to dfpad and Passiv = 50.00")
 -&gt; do
-    LBE.ext_fast_separation(Passiv, 50000)
-end.().output("LBE.e.Passiv", "Min. LBE space to dfpad and Passiv")
+    LBE.ext_fast_separation(Passiv, 50.0.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true)
+end.().output("LBE.e.Passiv", "Min. LBE space to dfpad and Passiv = 50.00")
 -&gt; do
-    LBE.ext_fast_separation(Activ, 30000)
-end.().output("LBE.f", "Min. LBE space to Activ")
+    LBE.ext_fast_separation(Activ, 30.0.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true)
+end.().output("LBE.f", "Min. LBE space to Activ = 30.00")
 -&gt; do
-    LBE.ext_ring.dup
+    LBE.with_holes.dup
 end.().output("LBE.h", "No LBE ring allowed")
 
 if $density
 	-&gt; do
 	    LBE.ext_with_density(0.2 .. 1.0, 'll')
-	end.().output("LBE.i", "Max. global LBE density [%]")
+	end.().output("LBE.i", "Max. global LBE density [%] = 20.00")
+end
+
+-&gt; do
+    bad_tsv.dup
+end.().output("TSV_G.a", "DeepVia has to be a ring structure")
+-&gt; do
+    tsv_fill_TSV_G_d.dup
+end.().output("TSV_G.d", "Min. DeepVia space = 25.00")
+-&gt; do
+    PWell_block_tsvOutRing_enc.dup
+end.().output("TSV_G.f", "Min. PWell:block enclosure of DeepVia = 2.50")
+-&gt; do
+    Metal1_tsvOutRing_enc.dup
+end.().output("TSV_G.g", "Min. Metal1 enclosure of DeepVia ring structure = 1.50")
+
+if $checkDensityRules
+	-&gt; do
+	    tsv.ext_with_density(0.0 .. 0.0001, 'll')
+	end.().output("TSV_G.i", "Max. global DeepVia density [%] = 1.00")
+	-&gt; do
+	    tsv.ext_with_density(0.001 .. 1.0, 'll')
+	end.().output("TSV_G.j", "Max. DeepVia coverage ratio for any 500.0 x 500.0 µm² chip area [%] = 10.00")
 end
 
 
 if $sanityRules
 	-&gt; do
 	    BiWind.dup
-	end.().output("forbidden.BiWind", "Forbidden drawn layer BiWind on GDS layer 3/0")
+	end.().output("forbidden.BiWind", "Forbidden drawn layer BiWind on GDS layer 3/0 = 3/0")
 	-&gt; do
 	    PEmWind.dup
-	end.().output("forbidden.PEmWind", "Forbidden drawn layer PEmWind on GDS layer 11/0")
+	end.().output("forbidden.PEmWind", "Forbidden drawn layer PEmWind on GDS layer 11/0 = 11/0")
 	-&gt; do
 	    BasPoly.dup
-	end.().output("forbidden.BasPoly", "Forbidden drawn layer BasPoly on GDS layer 13/0")
+	end.().output("forbidden.BasPoly", "Forbidden drawn layer BasPoly on GDS layer 13/0 = 13/0")
 	-&gt; do
 	    DeepCo.dup
-	end.().output("forbidden.DeepCo", "Forbidden drawn layer DeepCo on GDS layer 35/0")
+	end.().output("forbidden.DeepCo", "Forbidden drawn layer DeepCo on GDS layer 35/0 = 35/0")
 	-&gt; do
 	    PEmPoly.dup
-	end.().output("forbidden.PEmPoly", "Forbidden drawn layer PEmPoly on GDS layer 53/0")
+	end.().output("forbidden.PEmPoly", "Forbidden drawn layer PEmPoly on GDS layer 53/0 = 53/0")
 	-&gt; do
 	    EmPoly.dup
-	end.().output("forbidden.EmPoly", "Forbidden gen./drawn layer EmPoly on GDS layer 53/0")
+	end.().output("forbidden.EmPoly", "Forbidden gen./drawn layer EmPoly on GDS layer 53/0 = 53/0")
 	-&gt; do
 	    LDMOS.dup
-	end.().output("forbidden.LDMOS", "Forbidden drawn layer LDMOS on GDS layer 57/0")
+	end.().output("forbidden.LDMOS", "Forbidden drawn layer LDMOS on GDS layer 57/0 = 57/0")
 	-&gt; do
 	    PBiWind.dup
-	end.().output("forbidden.PBiWind", "Forbidden drawn layer PBiWind on GDS layer 58/0")
+	end.().output("forbidden.PBiWind", "Forbidden drawn layer PBiWind on GDS layer 58/0 = 58/0")
 	-&gt; do
 	    Flash.dup
-	end.().output("forbidden.Flash", "Forbidden drawn layer Flash on GDS layer 71/0")
+	end.().output("forbidden.Flash", "Forbidden drawn layer Flash on GDS layer 71/0 = 71/0")
 	-&gt; do
 	    ColWind.dup
-	end.().output("forbidden.ColWind", "Forbidden drawn layer ColWind on GDS layer 139/0")
+	end.().output("forbidden.ColWind", "Forbidden drawn layer ColWind on GDS layer 139/0 = 139/0")
 end
 
 
@@ -1892,5 +3244,7 @@ if $offGrid
 	    PolyRes.ongrid(5)
 	end.().output("OffGrid.PolyRes", "PolyRes is off-grid")
 end
+
+puts("Number of DRC errors: #{$drc_error_count}")
 </text>
 </klayout-macro>
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/drc/sg13g2_minimal.lydrc b/ihp-sg13g2/libs.tech/klayout/tech/drc/sg13g2_minimal.lydrc
index 287b8ee3..89de48a4 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/drc/sg13g2_minimal.lydrc
+++ b/ihp-sg13g2/libs.tech/klayout/tech/drc/sg13g2_minimal.lydrc
@@ -30,49 +30,49 @@
  <interpreter>dsl</interpreter>
  <dsl-interpreter-name>drc-dsl-xml</dsl-interpreter-name>
  <text># Supported variables that can be set using "-rd &lt;name&gt;=&lt;value&gt;" on the command line:
-# logfile - path to the log file [default: no log file]
-# gdsfile - path to the GDS layout to check (required in batch mode)
-# cell    - name of the cell to check (required in batch mode)
-# outfile - path to the report database [default: sg13g2_minimal.lyrdb in the script directory]
+# log_file    - path to the log file [default: no log file]
+# in_gds      - path to the GDS layout to check (required in batch mode)
+# cell        - name of the cell to check
+# report_file - path to the report database [default: sg13g2_minimal.lyrdb in the script directory]
 
 # to set logfile: -rd logfile="sg13g2_minimal.log"
-if $logfile
-    log_file($logfile)
+if $log_file
+    log_file($log_file)
 end
 
 application = RBA::Application.instance
 main_window = application.main_window
-if main_window
+if main_window and not $in_gds
     curr_layout_view = main_window.current_view()
     unless curr_layout_view
         layout_path = RBA::FileDialog::ask_open_file_name("Chose your layout file.", ".", "GDSII files (*.GDS *.gds *.GDS.gz *.gds.gz *.GDS2 *.gds2 *.GDS2.gz *.gds2.gz);; All files (*)")
+        unless layout_path
+            return
+        end
         main_window.load_layout(layout_path, 1)
         curr_layout_view = main_window.current_view()
     end
+    active_layout = RBA::CellView::active.layout
     active_cellname = RBA::CellView::active.cell_name
+    source(active_layout, active_cellname)
 else
     log("DRC: batch mode")
+    # to set input layout: -rd in_gds="path to GDS file"
     # to set cell: -rd cell="topcell"
     if $cell
         active_cellname = $cell
         log("Active cell: " + active_cellname)
+        source($in_gds, active_cellname)
+        active_layout = source.layout
     else
-        raise("'cell' script variable must be defined on command line")
+        source($in_gds)
+        active_layout = source.layout
+        active_cellname = source.cell_name
     end
 end
 
-active_layout = RBA::CellView::active.layout
-
-unless active_layout or $gdsfile
-    raise("layout file must be defined on command line or via 'gdsfile' script variable")
-end
-
-# to set input layout: -rd gdsfile="path to GDS file"
-if $gdsfile
-    source($gdsfile, active_cellname)
-    active_layout = source.layout
-else
-    source(active_layout, active_cellname)
+unless active_layout or $in_gds
+    raise("layout file must be defined on command line or via 'in_gds' script variable")
 end
 
 if active_layout.dbu != 0.001
@@ -80,14 +80,30 @@ if active_layout.dbu != 0.001
 end
 
 report_file = __dir__ + "/sg13g2_minimal.lyrdb"
-# to set report file: -rd outfile="sg13g2_minimal.lyrdb"
-if $outfile
-    report_file = File.expand_path($outfile)
+# to set report file: -rd report_file="sg13g2_minimal.lyrdb"
+if $report_file
+    report_file = File.expand_path($report_file)
 end
+
 report("design rules: sg13g2_minimal | layout cell: " + active_cellname, report_file)
 
 deep
 
+$drc_error_count = 0
+
+class DRC::DRCLayer
+    unless method_defined?(:original_output)
+        alias_method :original_output, :output
+    end
+
+    def output(*args)
+        count = self.count()
+        $drc_error_count += count
+        puts("Rule %s: %d error(s)" % [args[0], count])
+        original_output(*args)
+    end
+end
+
 # Initial definitions of control flow variables
 # Strings from the command line have to be converted
 if defined? $density
@@ -101,6 +117,110 @@ else
     $sanityRules = true
 end
 
+class DRC::DRCEngine
+    def find_intersecting_edges_errors(dbu_value,
+                                       error_edge_pairs_90,
+                                       error_edge_pairs_180,
+                                       inverse_error_edge_pairs_90 = nil,
+                                       inverse_error_edge_pairs_180 = nil,
+                                       options = {})
+        consider_intersecting_edges   = options.fetch(:consider_intersecting_edges, false)
+        consider_touch_points         = options.fetch(:consider_touch_points, false)
+        ignore_non_axis_aligned_edges = options.fetch(:ignore_non_axis_aligned_edges, false)
+        min_angle                     = options.fetch(:min_angle, 0)
+        max_angle                     = options.fetch(:max_angle, 90)
+        include_min_angle             = options.fetch(:include_min_angle, true)
+        include_max_angle             = options.fetch(:include_max_angle, false)
+        area_of_right_angle = dbu_value**2/2
+        errors_ep = RBA::EdgePairs::new()
+        touch_point_errors_ep = RBA::EdgePairs::new()
+        intersecting_edges_errors_ep = RBA::EdgePairs::new()
+        intersecting_edges_error_candidates = Hash.new()
+        no_touch_point_error = Hash.new()
+        error_edge_pairs_90.data.each do |edge_pair|
+            ip = nil
+            if edge_pair.first.p1 == edge_pair.second.p1 or
+               edge_pair.first.p1 == edge_pair.second.p2
+                ip = edge_pair.first.p1
+            elsif edge_pair.first.p2 == edge_pair.second.p1 or
+                  edge_pair.first.p2 == edge_pair.second.p2
+                ip = edge_pair.first.p2
+            else
+                ip = edge_pair.first.intersection_point(edge_pair.second)
+            end
+            if ip
+                intersecting_edges_error_candidates[ip] = edge_pair
+                if !edge_pair.first.is_degenerate? and !edge_pair.second.is_degenerate?
+                    if (edge_pair.first.contains?(edge_pair.second.p1) and
+                       edge_pair.first.contains?(edge_pair.second.p2)) or
+                       (edge_pair.second.contains?(edge_pair.first.p1) and
+                       edge_pair.second.contains?(edge_pair.first.p2))
+                        no_touch_point_error[ip] = true
+                    end
+                end
+            end
+        end
+        if consider_intersecting_edges or consider_touch_points
+            touch_point_candidates = Hash.new()
+            touch_point_errors = Hash.new()
+            if inverse_error_edge_pairs_90 and inverse_error_edge_pairs_180
+                (inverse_error_edge_pairs_90 + inverse_error_edge_pairs_180).data.each do |edge_pair|
+                    ip = edge_pair.first.intersection_point(edge_pair.second)
+                    if ip
+                        if touch_point_candidates[ip]
+                            touch_point_errors[ip] = true
+                            touch_point_candidates.delete(ip)
+                        elsif !no_touch_point_error[ip]
+                            touch_point_candidates[ip] = edge_pair
+                        end
+                    end
+                end
+            end
+            touch_point_candidates = Hash.new()
+            (error_edge_pairs_90 + error_edge_pairs_180).data.each do |edge_pair|
+                ip = nil
+                if edge_pair.first.p1 == edge_pair.second.p1 or
+                   edge_pair.first.p1 == edge_pair.second.p2
+                    ip = edge_pair.first.p1
+                elsif edge_pair.first.p2 == edge_pair.second.p1 or
+                      edge_pair.first.p2 == edge_pair.second.p2
+                    ip = edge_pair.first.p2
+                end
+                if ip
+                    if edge_pair.area == area_of_right_angle or max_angle == 180
+                        intersecting_edges_error_candidates[ip] = edge_pair
+                    end
+                    if touch_point_errors[ip]
+                        touch_point_errors_ep.insert(edge_pair)
+                        intersecting_edges_error_candidates.delete(ip)
+                    elsif touch_point_candidates[ip]
+                        touch_point_errors_ep.insert(edge_pair)
+                        touch_point_errors_ep.insert(touch_point_candidates[ip])
+                        touch_point_candidates.delete(ip)
+                        intersecting_edges_error_candidates.delete(ip)
+                    elsif !no_touch_point_error[ip]
+                        touch_point_candidates[ip] = edge_pair
+                    end
+                end
+            end
+            if consider_intersecting_edges
+                intersecting_edges_errors_ep = RBA::EdgePairs::new(intersecting_edges_error_candidates.values)
+                if max_angle != 180
+                    intersecting_edges_errors_ep = intersecting_edges_errors_ep.with_internal_angle(min_angle, max_angle, false, include_min_angle, include_max_angle)
+                end
+                errors_ep = errors_ep + intersecting_edges_errors_ep
+            end
+        end
+        if ignore_non_axis_aligned_edges
+            errors_ep = errors_ep.with_angle_both(RBA::Edges::OrthoEdges, false)
+        end
+        if consider_touch_points
+            errors_ep = errors_ep + touch_point_errors_ep
+        end
+        return DRC::DRCLayer::new(self, errors_ep)
+    end
+end
+
 class DRC::DRCLayer
     def ext_and(other)
         self_min_coherence_state = self.data.min_coherence?
@@ -113,28 +233,35 @@ class DRC::DRCLayer
         return output_layer
     end
 
-    def ext_area(constraint)
-        output_layer = self.dup
+    def ext_with_area(constraint)
+        lower_bound = nil
+        upper_bound = nil
+        output_layer = nil
+        self_min_coherence_state = self.data.min_coherence?
+        self.data.min_coherence = true
         constraint.each do |expression|
-            output_layer.data.min_coherence = true
             relation = expression[0]
             value = expression[1]
             if relation == "&gt;"
-                output_layer = output_layer.with_area((value + @engine.dbu), nil)
+                lower_bound = value + 1e-6
             elsif relation == "&lt;"
-                output_layer = output_layer.with_area(nil, value)
+                upper_bound = value
             elsif relation == "=="
-                output_layer = output_layer.with_area(value)
+                output_layer = self.with_area(value)
             elsif relation == "!="
-                output_layer = output_layer.without_area(value)
+                output_layer = self.without_area(value)
             elsif relation == "&gt;="
-                output_layer = output_layer.with_area(value, nil)
+                lower_bound = value
             elsif relation == "&lt;="
-                output_layer = output_layer.with_area(nil, (value + @engine.dbu))
+                upper_bound = value + 1e-6
             else
                 raise "invalid expression"
             end
         end
+        if lower_bound or upper_bound
+            output_layer = self.with_area(lower_bound, upper_bound)
+        end
+        self.data.min_coherence = self_min_coherence_state
         return output_layer
     end
 
@@ -171,12 +298,103 @@ class DRC::DRCLayer
         return output_layer
     end
 
-    def ext_fast_separation(other, value, polygon_output: false)
+    def ext_separation_at_intersecting_edges(other,
+                                             value,
+                                             metric=RBA::Region::Euclidian,
+                                             consider_intersecting_edges=false,
+                                             consider_touch_points=false,
+                                             ignore_non_axis_aligned_edges=false,
+                                             min_angle=0,
+                                             max_angle=90,
+                                             include_min_angle=true,
+                                             include_max_angle=false,
+                                             polygons=false)
         self_min_coherence_state = self.data.min_coherence?
         other_min_coherence_state =  other.data.min_coherence?
         self.data.min_coherence = true
         other.data.min_coherence = true
-        output_layer = self.separation(other, value)
+        if metric.is_a?(DRC::DRCMetrics)
+            metric = metric.value
+        end
+        if value.is_a? Float
+            dbu_value = (value/1.dbu).round
+        else
+            dbu_value = value
+        end
+        error_edge_pairs_90 = DRC::DRCLayer::new(@engine,
+            self.data.separation_check(other.data, dbu_value, false, metric, 90, 1, nil))
+        error_edge_pairs_180 = DRC::DRCLayer::new(@engine,
+            self.data.separation_check(other.data, dbu_value, false, metric, 180, nil, 1))
+        width_error_edge_pairs_90 = DRC::DRCLayer::new(@engine,
+            self.data.width_check(dbu_value, false, metric, 90, 1, nil) +
+            other.data.width_check(dbu_value, false, metric, 90, 1, nil))
+        width_error_edge_pairs_180 = DRC::DRCLayer::new(@engine,
+            self.data.width_check(dbu_value, false, metric, 180, nil, 1) +
+            other.data.width_check(dbu_value, false, metric, 180, nil, 1))
+        separation_errors = @engine.find_intersecting_edges_errors(
+            dbu_value,
+            error_edge_pairs_90,
+            error_edge_pairs_180,
+            width_error_edge_pairs_90,
+            width_error_edge_pairs_180,
+            {
+                consider_intersecting_edges: consider_intersecting_edges,
+                consider_touch_points: consider_touch_points,
+                ignore_non_axis_aligned_edges: ignore_non_axis_aligned_edges,
+                min_angle: min_angle,
+                max_angle: max_angle,
+                include_min_angle: include_min_angle,
+                include_max_angle: include_max_angle
+            }
+        )
+        self.data.min_coherence = self_min_coherence_state
+        other.data.min_coherence = other_min_coherence_state
+        if polygons
+            return separation_errors.polygons.merge(true, 0)
+        else
+            return separation_errors
+        end
+    end
+
+    def ext_fast_separation(other,
+                            value,
+                            metric: @engine.euclidian,
+                            consider_intersecting_edges: true,
+                            consider_touch_points: true,
+                            ignore_non_axis_aligned_edges: false,
+                            min_angle: 0,
+                            max_angle: 90,
+                            include_min_angle: true,
+                            include_max_angle: false,
+                            polygon_output: false)
+        self_min_coherence_state = self.data.min_coherence?
+        other_min_coherence_state =  other.data.min_coherence?
+        self.data.min_coherence = true
+        other.data.min_coherence = true
+        output_layer = self.separation(other, value, metric, @engine.angle_limit(max_angle))
+        if !consider_intersecting_edges and !consider_touch_points
+            output_layer = output_layer.with_distance(1, nil)
+            if ignore_non_axis_aligned_edges
+                output_layer = output_layer.with_angle(@engine.ortho, @engine.both)
+            end
+        elsif consider_intersecting_edges ^ consider_touch_points
+            intersecting_edges_errors = output_layer.with_distance(0).edges
+            candidate_layer1 = self.interacting(intersecting_edges_errors)
+            candidate_layer2 = other.interacting(intersecting_edges_errors)
+            output_layer = output_layer.with_distance(1, nil)
+            output_layer = output_layer + candidate_layer1.ext_separation_at_intersecting_edges(
+                candidate_layer2,
+                value,
+                metric,
+                consider_intersecting_edges,
+                consider_touch_points,
+                ignore_non_axis_aligned_edges,
+                min_angle,
+                max_angle,
+                include_min_angle,
+                include_max_angle,
+                false)
+        end
         self.data.min_coherence = self_min_coherence_state
         other.data.min_coherence = other_min_coherence_state
         if polygon_output
@@ -197,12 +415,18 @@ class DRC::DRCLayer
         return output_layer
     end
 
-    def ext_or(other)
+    def ext_or(other, *further_layers)
         self_min_coherence_state = self.data.min_coherence?
         other_min_coherence_state =  other.data.min_coherence?
         self.data.min_coherence = true
         other.data.min_coherence = true
         output_layer = self.join(other)
+        further_layers.each do |further_layer|
+            further_layer_min_coherence_state = further_layer.data.min_coherence?
+            further_layer.data.min_coherence = true
+            output_layer = output_layer.join(further_layer)
+            further_layer.data.min_coherence = further_layer_min_coherence_state
+        end
         self.data.min_coherence = self_min_coherence_state
         other.data.min_coherence = other_min_coherence_state
         return output_layer
@@ -242,10 +466,87 @@ class DRC::DRCLayer
         return output_layer
     end
 
-    def ext_fast_space(value, polygon_output: false)
+    def ext_space_at_intersecting_edges(value,
+                                        metric=RBA::Region::Euclidian,
+                                        consider_intersecting_edges=false,
+                                        consider_touch_points=false,
+                                        ignore_non_axis_aligned_edges=false,
+                                        min_angle=0,
+                                        max_angle=90,
+                                        include_min_angle=true,
+                                        include_max_angle=false,
+                                        polygons=false)
+        self_min_coherence_state = self.data.min_coherence?
+        self.data.min_coherence = true
+        if metric.is_a?(DRC::DRCMetrics)
+            metric = metric.value
+        end
+        if value.is_a? Float
+            dbu_value = (value/1.dbu).round
+        else
+            dbu_value = value
+        end
+        error_edge_pairs_90 = DRC::DRCLayer::new(@engine, self.data.space_check(dbu_value, false, metric, 90, 1, nil))
+        error_edge_pairs_180 = DRC::DRCLayer::new(@engine, self.data.space_check(dbu_value, false, metric, 180, nil, 1))
+        width_error_edge_pairs_90 = DRC::DRCLayer::new(@engine, self.data.width_check(dbu_value, false, metric, 90, 1, nil))
+        width_error_edge_pairs_180 = DRC::DRCLayer::new(@engine, self.data.width_check(dbu_value, false, metric, 180, nil, 1))
+        space_errors = @engine.find_intersecting_edges_errors(
+            dbu_value,
+            error_edge_pairs_90,
+            error_edge_pairs_180,
+            width_error_edge_pairs_90,
+            width_error_edge_pairs_180,
+            {
+                consider_intersecting_edges: consider_intersecting_edges,
+                consider_touch_points: consider_touch_points,
+                ignore_non_axis_aligned_edges: ignore_non_axis_aligned_edges,
+                min_angle: min_angle,
+                max_angle: max_angle,
+                include_min_angle: include_min_angle,
+                include_max_angle: include_max_angle
+            }
+        )
+        self.data.min_coherence = self_min_coherence_state
+        if polygons
+            return space_errors.polygons.merge(true, 0)
+        else
+            return space_errors
+        end
+    end
+
+    def ext_fast_space(value,
+                       metric: @engine.euclidian,
+                       consider_intersecting_edges: true,
+                       consider_touch_points: true,
+                       ignore_non_axis_aligned_edges: false,
+                       min_angle: 0,
+                       max_angle: 90,
+                       include_min_angle: true,
+                       include_max_angle: false,
+                       polygon_output: false)
         self_min_coherence_state = self.data.min_coherence?
         self.data.min_coherence = true
-        output_layer = self.space(value)
+        output_layer = self.space(value, metric, @engine.angle_limit(max_angle))
+        if !consider_intersecting_edges and !consider_touch_points
+            output_layer = output_layer.with_distance(1, nil)
+            if ignore_non_axis_aligned_edges
+                output_layer = output_layer.with_angle(@engine.ortho, @engine.both)
+            end
+        elsif consider_intersecting_edges ^ consider_touch_points
+            candidate_layer = self.interacting(output_layer.with_distance(0).edges)
+            output_layer = output_layer.with_distance(1, nil)
+            output_layer = output_layer + candidate_layer.ext_space_at_intersecting_edges(
+                value,
+                metric,
+                consider_intersecting_edges,
+                consider_touch_points,
+                ignore_non_axis_aligned_edges,
+                min_angle,
+                max_angle,
+                include_min_angle,
+                include_max_angle,
+                false)
+        end
         self.data.min_coherence = self_min_coherence_state
         if polygon_output
             return output_layer.polygons.merge(true, 0)
@@ -254,11 +555,93 @@ class DRC::DRCLayer
         end
     end
 
-    def ext_fast_width(value, polygon_output: false)
+    def ext_width_at_intersecting_edges(value,
+                  metric=RBA::Region::Euclidian,
+                  consider_intersecting_edges=false,
+                  consider_touch_points=false,
+                  ignore_non_axis_aligned_edges=false,
+                  min_angle=0,
+                  max_angle=90,
+                  include_min_angle=true,
+                  include_max_angle=false,
+                  polygons=false)
         self_min_coherence_state = self.data.min_coherence?
         self.data.min_coherence = true
-        output_layer = self.width(value)
+        if metric.is_a?(DRC::DRCMetrics)
+            metric = metric.value
+        end
+        if value.is_a? Float
+            dbu_value = (value/1.dbu).round
+        else
+            dbu_value = value
+        end
+        error_edge_pairs_90 = DRC::DRCLayer::new(@engine, self.data.width_check(dbu_value, false, metric, 90, 1, nil))
+        error_edge_pairs_180 = DRC::DRCLayer::new(@engine, self.data.width_check(dbu_value, false, metric, 180, nil, 1))
+        space_error_edge_pairs_90 = DRC::DRCLayer::new(@engine, self.data.space_check(dbu_value, false, metric, 90, 1, nil))
+        space_error_edge_pairs_180 = DRC::DRCLayer::new(@engine, self.data.space_check(dbu_value, false, metric, 180, nil, 1))
+        width_errors = @engine.find_intersecting_edges_errors(
+            dbu_value,
+            error_edge_pairs_90,
+            error_edge_pairs_180,
+            space_error_edge_pairs_90,
+            space_error_edge_pairs_180,
+            {
+                consider_intersecting_edges: consider_intersecting_edges,
+                consider_touch_points: consider_touch_points,
+                ignore_non_axis_aligned_edges: ignore_non_axis_aligned_edges,
+                min_angle: min_angle,
+                max_angle: max_angle,
+                include_min_angle: include_min_angle,
+                include_max_angle: include_max_angle
+            }
+        )
         self.data.min_coherence = self_min_coherence_state
+        if polygons
+            return width_errors.polygons.merge(true, 0)
+        else
+            return width_errors
+        end
+    end
+
+    def ext_fast_width(value,
+                       metric: @engine.euclidian,
+                       consider_intersecting_edges: true,
+                       consider_touch_points: true,
+                       ignore_non_axis_aligned_edges: false,
+                       min_angle: 0,
+                       max_angle: 90,
+                       include_min_angle: true,
+                       include_max_angle: false,
+                       polygon_output: false)
+        if self.polygons?
+            self_min_coherence_state = self.data.min_coherence?
+            self.data.min_coherence = true
+            self_edges = self.edges
+            self.data.min_coherence = self_min_coherence_state
+        else
+            self_edges = self
+        end
+        output_layer = self_edges.width(value, metric, @engine.angle_limit(max_angle))
+        if !consider_intersecting_edges and !consider_touch_points
+            output_layer = output_layer.with_distance(1, nil)
+            if ignore_non_axis_aligned_edges
+                output_layer = output_layer.with_angle(@engine.ortho, @engine.both)
+            end
+        elsif consider_intersecting_edges ^ consider_touch_points
+            candidate_layer = self.interacting(output_layer.with_distance(0).edges)
+            output_layer = output_layer.with_distance(1, nil)
+            output_layer = output_layer + candidate_layer.ext_width_at_intersecting_edges(
+                value,
+                metric,
+                consider_intersecting_edges,
+                consider_touch_points,
+                ignore_non_axis_aligned_edges,
+                min_angle,
+                max_angle,
+                include_min_angle,
+                include_max_angle,
+                false)
+        end
         if polygon_output
             return output_layer.polygons.merge(true, 0)
         else
@@ -266,14 +649,6 @@ class DRC::DRCLayer
         end
     end
 
-    def ext_ring
-        holes = self.holes
-        hulls = self.hulls
-        covering = hulls.covering(holes)
-        result = covering.and(self)
-        return result
-    end
-
     def ext_interacting_with_text(text_layer, text)
         if text_layer.is_a? Integer
             text_layer = @engine.labels(text_layer)
@@ -315,20 +690,26 @@ class DRC::DRCLayer
         if origin == 'll'
             origin_x = bbox.left
             origin_y = bbox.bottom
+            if tile_size and tile_step and (tile_size.get[0] != tile_step.get[0] or tile_size.get[1] != tile_step.get[1])
+              origin_x = bbox.left + tile_step.get[0]/2
+              origin_y = bbox.bottom + tile_step.get[1]/2
+            end
             tile_origin = DRC::DRCTileOrigin::new(origin_x, origin_y)
             arguments.push(tile_origin)
         elsif origin != 'cc'
             raise "Unknown origin: 'cc' or 'll' expected"
         end
         if tile_size
-            return merged_layer.with_density(*arguments)
+            boundary_layer = DRC::DRCLayer::new(@engine, RBA::Region::new(bbox.to_itype(@engine.dbu)))
+            tile_boundary = DRC::DRCTileBoundary::new(boundary_layer)
+            return merged_layer.with_density(*arguments, tile_boundary, @engine.padding_ignore)
         else
             tile_size = DRC::DRCTileSize::new(bbox.width, bbox.height)
             tile_count = DRC::DRCTileCount::new(1,2)
             enlarged_bbox = bbox.enlarged(1.1).to_itype(@engine.dbu)
             boundary_layer = DRC::DRCLayer::new(@engine, RBA::Region::new(enlarged_bbox))
             tile_boundary = DRC::DRCTileBoundary::new(boundary_layer)
-            result = merged_layer.with_density(*arguments, tile_size, tile_count, tile_boundary)
+            result = merged_layer.with_density(*arguments, tile_size, tile_count, tile_boundary, @engine.padding_ignore)
             return result.raw.overlapping(DRC::DRCLayer::new(@engine, RBA::Region::new(bbox.to_itype(@engine.dbu))))
         end
     end
@@ -360,8 +741,6 @@ Metal3 = source.polygons("30/0")
 Metal3_pin = source.polygons("30/2")
 Metal3_filler = source.polygons("30/22")
 Metal3_slit = source.polygons("30/24")
-NWell = source.polygons("31/0")
-NWell_pin = source.polygons("31/2")
 DeepCo = source.polygons("35/0")
 EdgeSeal = source.polygons("39/0")
 ThickGateOx = source.polygons("44/0")
@@ -399,19 +778,27 @@ if $sanityRules
 	Flash = source.polygons("71/0")
 end
 
-Activ_Act_a = Activ.ext_fast_width(150)
+Activ_Act_a = Activ.ext_fast_width(0.15.um)
 Act_density = Activ.ext_or(Activ_filler)
 Gat_density = GatPoly.ext_or(GatPoly_filler)
-Cont_SQ = Cont.ext_rectangles(true, false, [["==", 160]], [["==", 160]], nil)
-ContBar = Cont.ext_area([["&gt;", 0.16*0.16]])
+Cont_SQ = Cont.ext_rectangles(true, false, [["==", 0.16.um]], [["==", 0.16.um]], nil)
+ContBar = Cont.ext_with_area([["&gt;", (0.16*0.16).um2]])
 Act_Nsram = Activ.ext_not(SRAM)
 GP_Nsram = GatPoly.ext_not(SRAM)
 M1_Nsram = Metal1.ext_not(SRAM)
 M2_Nsram = Metal2.ext_not(SRAM)
 M3_Nsram = Metal3.ext_not(SRAM)
-ThickGateOx_TGO_f = ThickGateOx.ext_fast_width(860, polygon_output: true)
+Via1_edgC1_out = Via1.ext_not(EdgeSeal)
+Via2_edgC1_out = Via2.ext_not(EdgeSeal)
+Cont_outside_EdgeSeal = Cont.outside(EdgeSeal)
+ThickGateOx_TGO_f = ThickGateOx.ext_fast_width(0.86.um, consider_intersecting_edges: false, polygon_output: true)
+Via3_edgC1_out = Via3.ext_not(EdgeSeal)
 M4_Nsram = Metal4.ext_not(SRAM)
+Via4_edgC1_out = Via4.ext_not(EdgeSeal)
 M5_Nsram = Metal5.ext_not(SRAM)
+TopVia1_edgC1_out = TopVia1.ext_not(EdgeSeal)
+TopVia1_or_Vmim = TopVia1.ext_or(Vmim)
+TopVia2_edgC1_out = TopVia2.ext_not(EdgeSeal)
 M1_density = Metal1.ext_or(Metal1_filler).ext_not(Metal1_slit)
 M2_density = Metal2.ext_or(Metal2_filler).ext_not(Metal2_slit)
 emi2Pin = Metal2_pin.ext_and(TRANS).ext_interacting_with_text(TEXT_0, "E")
@@ -420,329 +807,331 @@ M4_density = Metal4.ext_or(Metal4_filler).ext_not(Metal4_slit)
 M5_density = Metal5.ext_or(Metal5_filler).ext_not(Metal5_slit)
 TM1_density = TopMetal1.ext_or(TopMetal1_filler).ext_not(TopMetal1_slit)
 TM2_density = TopMetal2.ext_or(TopMetal2_filler).ext_not(TopMetal2_slit)
-GP_Nsram_Gat_a = GP_Nsram.ext_fast_width(130, polygon_output: true)
-GP_Nsram_Gat_b = GP_Nsram.ext_fast_space(180, polygon_output: true)
+GP_Nsram_Gat_a = GP_Nsram.ext_fast_width(0.13.um, consider_intersecting_edges: false, polygon_output: true)
+GP_Nsram_Gat_b = GP_Nsram.ext_fast_space(0.18.um, consider_intersecting_edges: false, polygon_output: true)
 transG2L = TRANS.ext_interacting_with_text(TEXT_0, "npn13G2L").ext_covering(emi2Pin)
 -&gt; do
     Activ_Act_a.dup
-end.().output("Act.a", "Min. Activ width")
+end.().output("Act.a", "Min. Activ width = 0.15")
 -&gt; do
-    Act_Nsram.ext_fast_space(210)
-end.().output("Act.b", "Min. Activ space or notch")
+    Act_Nsram.ext_fast_space(0.21.um)
+end.().output("Act.b", "Min. Activ space or notch = 0.21")
 
 if $density
 	-&gt; do
 	    Act_density.ext_with_density(0.0 .. 0.35, 'll')
-	end.().output("AFil.g", "Min. global Activ density [%]")
+	end.().output("AFil.g", "Min. global Activ density [%] = 35.00")
 	-&gt; do
 	    Act_density.ext_with_density(0.55 .. 1.0, 'll')
-	end.().output("AFil.g1", "Max. global Activ density [%]")
+	end.().output("AFil.g1", "Max. global Activ density [%] = 55.00")
 	-&gt; do
-	    Act_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0), tile_step(400.0))
-	end.().output("AFil.g2", "Min. Activ coverage ratio for any 800 x 800 µm² chip area [%]")
+	    Act_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0.um), tile_step(400.0.um))
+	end.().output("AFil.g2", "Min. Activ coverage ratio for any 800 x 800 µm² chip area [%] = 25.00")
 	-&gt; do
-	    Act_density.ext_with_density(0.65 .. 1.0, 'll', tile_size(800.0), tile_step(400.0))
-	end.().output("AFil.g3", "Max. Activ coverage ratio for any 800 x 800 µm² chip area [%]")
+	    Act_density.ext_with_density(0.65 .. 1.0, 'll', tile_size(800.0.um), tile_step(400.0.um))
+	end.().output("AFil.g3", "Max. Activ coverage ratio for any 800 x 800 µm² chip area [%] = 65.00")
 end
 
 -&gt; do
     ThickGateOx_TGO_f.dup
-end.().output("TGO.f", "Min. ThickGateOx width")
+end.().output("TGO.f", "Min. ThickGateOx width = 0.86")
 -&gt; do
     GP_Nsram_Gat_a.dup
-end.().output("Gat.a", "Min. GatPoly width")
+end.().output("Gat.a", "Min. GatPoly width = 0.13")
 -&gt; do
     GP_Nsram_Gat_b.dup
-end.().output("Gat.b", "Min. GatPoly space or notch")
+end.().output("Gat.b", "Min. GatPoly space or notch = 0.18")
 -&gt; do
-    GP_Nsram.ext_fast_separation(Act_Nsram, 70)
-end.().output("Gat.d", "Min. GatPoly space to Activ")
+    GP_Nsram.ext_fast_separation(Act_Nsram, 0.07.um)
+end.().output("Gat.d", "Min. GatPoly space to Activ = 0.07")
 
 if $density
 	-&gt; do
 	    Gat_density.ext_with_density(0.0 .. 0.15, 'll')
-	end.().output("GFil.g", "Min. global GatPoly density [%]")
+	end.().output("GFil.g", "Min. global GatPoly density [%] = 15.00")
 end
 
 -&gt; do
-    Cont.merged(true, 0).outside(EdgeSeal).ext_not(ContBar.ext_or(Cont_SQ))
-end.().output("Cnt.a", "Min. and max. Cont width")
+    Cont_outside_EdgeSeal.ext_not(ContBar.ext_or(Cont_SQ))
+end.().output("Cnt.a", "Min. and max. Cont width = 0.16")
 -&gt; do
-    Cont.merged(true, 0).outside(EdgeSeal).ext_fast_space(180)
-end.().output("Cnt.b", "Min. Cont space")
+    Cont_outside_EdgeSeal.ext_fast_space(0.18.um, consider_intersecting_edges: false)
+end.().output("Cnt.b", "Min. Cont space = 0.18")
 -&gt; do
-    Metal1.ext_fast_width(160)
-end.().output("M1.a", "Min. Metal1 width")
+    Metal1.ext_fast_width(0.16.um)
+end.().output("M1.a", "Min. Metal1 width = 0.16")
 -&gt; do
-    M1_Nsram.ext_fast_space(180)
-end.().output("M1.b", "Min. Metal1 space or notch")
+    M1_Nsram.ext_fast_space(0.18.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true)
+end.().output("M1.b", "Min. Metal1 space or notch = 0.18")
 
 if $density
 	-&gt; do
 	    M1_density.ext_with_density(0.0 .. 0.35, 'll')
-	end.().output("M1.j", "Min. global Metal1 density [%]")
+	end.().output("M1.j", "Min. global Metal1 density [%] = 35.0")
 	-&gt; do
 	    M1_density.ext_with_density(0.6 .. 1.0, 'll')
-	end.().output("M1.k", "Max. global Metal1 density [%]")
+	end.().output("M1.k", "Max. global Metal1 density [%] = 60.0")
 end
 
 -&gt; do
-    Metal2.ext_fast_width(200)
-end.().output("M2.a", "Min. Metal2 width")
+    Metal2.ext_fast_width(0.2.um)
+end.().output("M2.a", "Min. Metal2 width = 0.20")
 -&gt; do
-    M2_Nsram.ext_fast_space(210)
-end.().output("M2.b", "Min. Metal2 space or notch")
+    M2_Nsram.ext_fast_space(0.21.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true)
+end.().output("M2.b", "Min. Metal2 space or notch = 0.21")
 
 if $density
 	-&gt; do
 	    M2_density.ext_with_density(0.0 .. 0.35, 'll')
-	end.().output("M2.j", "Min. global Metal2 density [%]")
+	end.().output("M2.j", "Min. global Metal2 density [%] = 35.00")
 	-&gt; do
 	    M2_density.ext_with_density(0.6 .. 1.0, 'll')
-	end.().output("M2.k", "Max. global Metal2 density [%]")
+	end.().output("M2.k", "Max. global Metal2 density [%] = 60.00")
 end
 
 -&gt; do
-    Metal3.ext_fast_width(200)
-end.().output("M3.a", "Min. Metal3 width")
+    Metal3.ext_fast_width(0.2.um)
+end.().output("M3.a", "Min. Metal3 width = 0.20")
 -&gt; do
-    M3_Nsram.ext_fast_space(210)
-end.().output("M3.b", "Min. Metal3 space or notch")
+    M3_Nsram.ext_fast_space(0.21.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true)
+end.().output("M3.b", "Min. Metal3 space or notch = 0.21")
 
 if $density
 	-&gt; do
 	    M3_density.ext_with_density(0.0 .. 0.35, 'll')
-	end.().output("M3.j", "Min. global Metal3 density [%]")
+	end.().output("M3.j", "Min. global Metal3 density [%] = 35.00")
 	-&gt; do
 	    M3_density.ext_with_density(0.6 .. 1.0, 'll')
-	end.().output("M3.k", "Max. global Metal3 density [%]")
+	end.().output("M3.k", "Max. global Metal3 density [%] = 60.00")
 end
 
 -&gt; do
-    Metal4.ext_fast_width(200)
-end.().output("M4.a", "Min. Metal4 width")
+    Metal4.ext_fast_width(0.2.um)
+end.().output("M4.a", "Min. Metal4 width = 0.20")
 -&gt; do
-    M4_Nsram.ext_fast_space(210)
-end.().output("M4.b", "Min. Metal4 space or notch")
+    M4_Nsram.ext_fast_space(0.21.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true)
+end.().output("M4.b", "Min. Metal4 space or notch = 0.21")
 
 if $density
 	-&gt; do
 	    M4_density.ext_with_density(0.0 .. 0.35, 'll')
-	end.().output("M4.j", "Min. global Metal4 density [%]")
+	end.().output("M4.j", "Min. global Metal4 density [%] = 35.00")
 	-&gt; do
 	    M4_density.ext_with_density(0.6 .. 1.0, 'll')
-	end.().output("M4.k", "Max. global Metal4 density [%]")
+	end.().output("M4.k", "Max. global Metal4 density [%] = 60.00")
 end
 
 -&gt; do
-    Metal5.ext_fast_width(200)
-end.().output("M5.a", "Min. Metal5 width")
+    Metal5.ext_fast_width(0.2.um)
+end.().output("M5.a", "Min. Metal5 width = 0.20")
 -&gt; do
-    M5_Nsram.ext_fast_space(210)
-end.().output("M5.b", "Min. Metal5 space or notch")
+    M5_Nsram.ext_fast_space(0.21.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true)
+end.().output("M5.b", "Min. Metal5 space or notch = 0.21")
 
 if $density
 	-&gt; do
 	    M5_density.ext_with_density(0.0 .. 0.35, 'll')
-	end.().output("M5.j", "Min. global Metal5 density [%]")
+	end.().output("M5.j", "Min. global Metal5 density [%] = 35.00")
 	-&gt; do
 	    M5_density.ext_with_density(0.6 .. 1.0, 'll')
-	end.().output("M5.k", "Max. global Metal5 density [%]")
+	end.().output("M5.k", "Max. global Metal5 density [%] = 60.00")
 	-&gt; do
-	    M1_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0), tile_step(400.0))
-	end.().output("M1Fil.h", "Min. Metal1 and Metal1:filler coverage ratio for any 800 x 800 µm² chip area [%]")
+	    M1_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0.um), tile_step(400.0.um))
+	end.().output("M1Fil.h", "Min. Metal1 and Metal1:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00")
 	-&gt; do
-	    M1_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0), tile_step(400.0))
-	end.().output("M1Fil.k", "Max. Metal1 and Metal1:filler coverage ratio for any 800 x 800 µm² chip area [%]")
+	    M1_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0.um), tile_step(400.0.um))
+	end.().output("M1Fil.k", "Max. Metal1 and Metal1:filler coverage ratio for any 800 x 800 µm² chip area [%] = 75.00")
 	-&gt; do
-	    M2_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0), tile_step(400.0))
-	end.().output("M2Fil.h", "Min. Metal2 and Metal2:filler coverage ratio for any 800 x 800 µm² chip area [%]")
+	    M2_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0.um), tile_step(400.0.um))
+	end.().output("M2Fil.h", "Min. Metal2 and Metal2:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00")
 	-&gt; do
-	    M2_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0), tile_step(400.0))
-	end.().output("M2Fil.k", "Max. Metal2 and Metal2:filler coverage ratio for any 800 x 800 µm² chip area [%]")
+	    M2_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0.um), tile_step(400.0.um))
+	end.().output("M2Fil.k", "Max. Metal2 and Metal2:filler coverage ratio for any 800 x 800 µm² chip area [%] = 75.00")
 	-&gt; do
-	    M3_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0), tile_step(400.0))
-	end.().output("M3Fil.h", "Min. Metal3 and Metal3:filler coverage ratio for any 800 x 800 µm² chip area [%]")
+	    M3_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0.um), tile_step(400.0.um))
+	end.().output("M3Fil.h", "Min. Metal3 and Metal3:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00")
 	-&gt; do
-	    M3_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0), tile_step(400.0))
-	end.().output("M3Fil.k", "Max. Metal3 and Metal3:filler coverage ratio for any 800 x 800 µm² chip area [%]")
+	    M3_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0.um), tile_step(400.0.um))
+	end.().output("M3Fil.k", "Max. Metal3 and Metal3:filler coverage ratio for any 800 x 800 µm² chip area [%] = 75.00")
 	-&gt; do
-	    M4_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0), tile_step(400.0))
-	end.().output("M4Fil.h", "Min. Metal4 and Metal4:filler coverage ratio for any 800 x 800 µm² chip area [%]")
+	    M4_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0.um), tile_step(400.0.um))
+	end.().output("M4Fil.h", "Min. Metal4 and Metal4:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00")
 	-&gt; do
-	    M4_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0), tile_step(400.0))
-	end.().output("M4Fil.k", "Max. Metal4 and Metal4:filler coverage ratio for any 800 x 800 µm² chip area [%]")
+	    M4_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0.um), tile_step(400.0.um))
+	end.().output("M4Fil.k", "Max. Metal4 and Metal4:filler coverage ratio for any 800 x 800 µm² chip area [%] = 75.00")
 	-&gt; do
-	    M5_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0), tile_step(400.0))
-	end.().output("M5Fil.h", "Min. Metal5 and Metal5:filler coverage ratio for any 800 x 800 µm² chip area [%]")
+	    M5_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0.um), tile_step(400.0.um))
+	end.().output("M5Fil.h", "Min. Metal5 and Metal5:filler coverage ratio for any 800 x 800 µm² chip area [%] = 25.00")
 	-&gt; do
-	    M5_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0), tile_step(400.0))
-	end.().output("M5Fil.k", "Max. Metal5 and Metal5:filler coverage ratio for any 800 x 800 µm² chip area [%]")
+	    M5_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0.um), tile_step(400.0.um))
+	end.().output("M5Fil.k", "Max. Metal5 and Metal5:filler coverage ratio for any 800 x 800 µm² chip area [%] = 75.00")
 end
 
 -&gt; do
-    Via1.ext_not(EdgeSeal).merged(true, 0).outside(transG2L).ext_rectangles(false, false, [["==", 190]], [["==", 190]], nil, inverted: true)
-end.().output("V1.a", "Min. and max. Via1 width")
+    Via1_edgC1_out.outside(transG2L).ext_rectangles(false, false, [["==", 0.19.um]], [["==", 0.19.um]], nil, inverted: true)
+end.().output("V1.a", "Min. and max. Via1 width = 0.19")
 -&gt; do
-    Via1.ext_not(EdgeSeal).ext_fast_space(220)
-end.().output("V1.b", "Min. Via1 space")
+    Via1_edgC1_out.ext_fast_space(0.22.um, consider_intersecting_edges: false)
+end.().output("V1.b", "Min. Via1 space = 0.22")
 -&gt; do
-    Via2.ext_not(EdgeSeal).merged(true, 0).outside(transG2L).ext_rectangles(false, false, [["==", 190]], [["==", 190]], nil, inverted: true)
-end.().output("V2.a", "Min. and max. Via2 width")
+    Via2_edgC1_out.outside(transG2L).ext_rectangles(false, false, [["==", 0.19.um]], [["==", 0.19.um]], nil, inverted: true)
+end.().output("V2.a", "Min. and max. Via2 width = 0.19")
 -&gt; do
-    Via2.ext_not(EdgeSeal).ext_fast_space(220)
-end.().output("V2.b", "Min. Via2 space")
+    Via2_edgC1_out.ext_fast_space(0.22.um, consider_intersecting_edges: false)
+end.().output("V2.b", "Min. Via2 space = 0.22")
 -&gt; do
-    Via3.ext_not(EdgeSeal).merged(true, 0).outside(transG2L).ext_rectangles(false, false, [["==", 190]], [["==", 190]], nil, inverted: true)
-end.().output("V3.a", "Min. and max. Via3 width")
+    Via3_edgC1_out.outside(transG2L).ext_rectangles(false, false, [["==", 0.19.um]], [["==", 0.19.um]], nil, inverted: true)
+end.().output("V3.a", "Min. and max. Via3 width = 0.19")
 -&gt; do
-    Via3.ext_not(EdgeSeal).ext_fast_space(220)
-end.().output("V3.b", "Min. Via3 space")
+    Via3_edgC1_out.ext_fast_space(0.22.um, consider_intersecting_edges: false)
+end.().output("V3.b", "Min. Via3 space = 0.22")
 -&gt; do
-    Via4.ext_not(EdgeSeal).merged(true, 0).outside(transG2L).ext_rectangles(false, false, [["==", 190]], [["==", 190]], nil, inverted: true)
-end.().output("V4.a", "Min. and max. Via4 width")
+    Via4_edgC1_out.outside(transG2L).ext_rectangles(false, false, [["==", 0.19.um]], [["==", 0.19.um]], nil, inverted: true)
+end.().output("V4.a", "Min. and max. Via4 width = 0.19")
 -&gt; do
-    Via4.ext_not(EdgeSeal).ext_fast_space(220)
-end.().output("V4.b", "Min. Via4 space")
+    Via4_edgC1_out.ext_fast_space(0.22.um, consider_intersecting_edges: false)
+end.().output("V4.b", "Min. Via4 space = 0.22")
 -&gt; do
-    Vmim.ext_or(TopVia1.ext_not(EdgeSeal)).ext_rectangles(false, false, [["==", 420]], [["==", 420]], nil, inverted: true)
-end.().output("TV1.a", "Min. and max. TopVia1 width")
+    TopVia1_edgC1_out.ext_or(Vmim).ext_rectangles(false, false, [["==", 0.42.um]], [["==", 0.42.um]], nil, inverted: true)
+end.().output("TV1.a", "Min. and max. TopVia1 width = 0.42")
 -&gt; do
-    TopVia1.ext_or(Vmim).ext_fast_space(420)
-end.().output("TV1.b", "Min. TopVia1 space")
+    TopVia1_or_Vmim.ext_fast_space(0.42.um)
+end.().output("TV1.b", "Min. TopVia1 space = 0.42")
 -&gt; do
-    TopMetal1.ext_fast_width(1640)
-end.().output("TM1.a", "Min. TopMetal1 width")
+    TopMetal1.ext_fast_width(1.64.um)
+end.().output("TM1.a", "Min. TopMetal1 width = 1.64")
 -&gt; do
-    TopMetal1.ext_fast_space(1640)
-end.().output("TM1.b", "Min. TopMetal1 space or notch")
+    TopMetal1.ext_fast_space(1.64.um)
+end.().output("TM1.b", "Min. TopMetal1 space or notch = 1.64")
 
 if $density
 	-&gt; do
 	    TM1_density.ext_with_density(0.0 .. 0.25, 'll')
-	end.().output("TM1.c", "Min. global TopMetal1 density [%]")
+	end.().output("TM1.c", "Min. global TopMetal1 density [%] = 25.00")
 	-&gt; do
 	    TM1_density.ext_with_density(0.7 .. 1.0, 'll')
-	end.().output("TM1.d", "Max. global TopMetal1 density [%]")
+	end.().output("TM1.d", "Max. global TopMetal1 density [%] = 70.00")
 end
 
 -&gt; do
-    TopVia2.ext_not(EdgeSeal).ext_rectangles(false, false, [["==", 900]], [["==", 900]], nil, inverted: true)
-end.().output("TV2.a", "Min. and max. TopVia2 width")
+    TopVia2_edgC1_out.ext_rectangles(false, false, [["==", 0.9.um]], [["==", 0.9.um]], nil, inverted: true)
+end.().output("TV2.a", "Min. and max. TopVia2 width = 0.90")
 -&gt; do
-    TopVia2.ext_fast_space(1060)
-end.().output("TV2.b", "Min. TopVia2 space")
+    TopVia2.ext_fast_space(1.06.um)
+end.().output("TV2.b", "Min. TopVia2 space = 1.06")
 -&gt; do
-    TopMetal2.ext_fast_width(2000)
-end.().output("TM2.a", "Min. TopMetal2 width")
+    TopMetal2.ext_fast_width(2.0.um)
+end.().output("TM2.a", "Min. TopMetal2 width = 2.00")
 -&gt; do
-    TopMetal2.ext_fast_space(2000)
-end.().output("TM2.b", "Min. TopMetal2 space or notch")
+    TopMetal2.ext_fast_space(2.0.um)
+end.().output("TM2.b", "Min. TopMetal2 space or notch = 2.00")
 
 if $density
 	-&gt; do
 	    TM2_density.ext_with_density(0.0 .. 0.25, 'll')
-	end.().output("TM2.c", "Min. global TopMetal2 density [%]")
+	end.().output("TM2.c", "Min. global TopMetal2 density [%] = 25.00")
 	-&gt; do
 	    TM2_density.ext_with_density(0.7 .. 1.0, 'll')
-	end.().output("TM2.d", "Max. global TopMetal2 density [%]")
+	end.().output("TM2.d", "Max. global TopMetal2 density [%] = 70.00")
 end
 
 -&gt; do
-    Passiv.ext_fast_width(2100)
-end.().output("Pas.a", "Min. Passiv width")
+    Passiv.ext_fast_width(2.1.um)
+end.().output("Pas.a", "Min. Passiv width = 2.10")
 -&gt; do
-    Passiv.ext_fast_space(3500)
-end.().output("Pas.b", "Min. Passiv space or notch")
+    Passiv.ext_fast_space(3.5.um)
+end.().output("Pas.b", "Min. Passiv space or notch = 3.50")
 
 if $sanityRules
 	-&gt; do
 	    Activ_pin.ext_not(Activ)
-	end.().output("Pin.a", "Min. Activ enclosure of Activ:pin")
+	end.().output("Pin.a", "Min. Activ enclosure of Activ:pin = 0.00")
 	-&gt; do
 	    GatPoly_pin.ext_not(GatPoly)
-	end.().output("Pin.b", "Min. GatPoly enclosure of GatPoly:pin")
+	end.().output("Pin.b", "Min. GatPoly enclosure of GatPoly:pin = 0.00")
 	-&gt; do
 	    Metal1_pin.ext_not(Metal1)
-	end.().output("Pin.e", "Min. Metal1 enclosure of Metal1:pin")
+	end.().output("Pin.e", "Min. Metal1 enclosure of Metal1:pin = 0.00")
 	-&gt; do
 	    Metal2_pin.ext_not(Metal2)
-	end.().output("Pin.f.M2", "Min. Metal2 enclosure of Metal2:pin")
+	end.().output("Pin.f.M2", "Min. Metal2 enclosure of Metal2:pin = 0.00")
 	-&gt; do
 	    Metal3_pin.ext_not(Metal3)
-	end.().output("Pin.f.M3", "Min. Metal3 enclosure of Metal3:pin")
+	end.().output("Pin.f.M3", "Min. Metal3 enclosure of Metal3:pin = 0.00")
 	-&gt; do
 	    Metal4_pin.ext_not(Metal4)
-	end.().output("Pin.f.M4", "Min. Metal4 enclosure of Metal4:pin")
+	end.().output("Pin.f.M4", "Min. Metal4 enclosure of Metal4:pin = 0.00")
 	-&gt; do
 	    Metal5_pin.ext_not(Metal5)
-	end.().output("Pin.f.M5", "Min. Metal5 enclosure of Metal5:pin")
+	end.().output("Pin.f.M5", "Min. Metal5 enclosure of Metal5:pin = 0.00")
 	-&gt; do
 	    TopMetal1_pin.ext_not(TopMetal1)
-	end.().output("Pin.g", "Min. TopMetal1 enclosure of TopMetal1:pin")
+	end.().output("Pin.g", "Min. TopMetal1 enclosure of TopMetal1:pin = 0.00")
 	-&gt; do
 	    TopMetal2_pin.ext_not(TopMetal2)
-	end.().output("Pin.h", "Min. TopMetal2 enclosure of TopMetal2:pin")
+	end.().output("Pin.h", "Min. TopMetal2 enclosure of TopMetal2:pin = 0.00")
 end
 
 -&gt; do
-    LBE.ext_fast_width(100000)
-end.().output("LBE.a", "Min. LBE width")
+    LBE.ext_fast_width(100.0.um)
+end.().output("LBE.a", "Min. LBE width = 100.00")
 -&gt; do
-    LBE.drc((width(projection) &gt; 1500000).polygons)
-end.().output("LBE.b", "Max. LBE width")
+    LBE.drc((width(projection) &gt; 1500.0.um).polygons)
+end.().output("LBE.b", "Max. LBE width = 1500.00")
 -&gt; do
-    LBE.ext_area([["&gt;", 250000.0]])
-end.().output("LBE.b1", "Max. LBE area (µm²)")
+    LBE.ext_with_area([["&gt;", 250000.0.um2]])
+end.().output("LBE.b1", "Max. LBE area (µm²) = 250000.00")
 -&gt; do
-    LBE.ext_fast_space(100000)
-end.().output("LBE.c", "Min. LBE space or notch")
+    LBE.ext_fast_space(100.0.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true)
+end.().output("LBE.c", "Min. LBE space or notch = 100.00")
 -&gt; (;lbe_in_seal) do
-    lbe_in_seal = LBE.merged(true, 0).inside(EdgeSeal.holes.merge)
-    lbe_in_seal.ext_fast_separation(EdgeSeal, 150000)
-end.().output("LBE.d", "Min. LBE space to inner edge of EdgeSeal")
+    lbe_in_seal = LBE.inside(EdgeSeal.holes.merge)
+    lbe_in_seal.ext_fast_separation(EdgeSeal, 150.0.um, consider_intersecting_edges: false, ignore_non_axis_aligned_edges: true)
+end.().output("LBE.d", "Min. LBE space to inner edge of EdgeSeal = 150.00")
 -&gt; do
-    LBE.ext_ring.dup
+    LBE.with_holes.dup
 end.().output("LBE.h", "No LBE ring allowed")
 
 if $density
 	-&gt; do
 	    LBE.ext_with_density(0.2 .. 1.0, 'll')
-	end.().output("LBE.i", "Max. global LBE density [%]")
+	end.().output("LBE.i", "Max. global LBE density [%] = 20.00")
 end
 
 
 if $sanityRules
 	-&gt; do
 	    BiWind.dup
-	end.().output("forbidden.BiWind", "Forbidden drawn layer BiWind on GDS layer 3/0")
+	end.().output("forbidden.BiWind", "Forbidden drawn layer BiWind on GDS layer 3/0 = 3/0")
 	-&gt; do
 	    PEmWind.dup
-	end.().output("forbidden.PEmWind", "Forbidden drawn layer PEmWind on GDS layer 11/0")
+	end.().output("forbidden.PEmWind", "Forbidden drawn layer PEmWind on GDS layer 11/0 = 11/0")
 	-&gt; do
 	    BasPoly.dup
-	end.().output("forbidden.BasPoly", "Forbidden drawn layer BasPoly on GDS layer 13/0")
+	end.().output("forbidden.BasPoly", "Forbidden drawn layer BasPoly on GDS layer 13/0 = 13/0")
 	-&gt; do
 	    DeepCo.dup
-	end.().output("forbidden.DeepCo", "Forbidden drawn layer DeepCo on GDS layer 35/0")
+	end.().output("forbidden.DeepCo", "Forbidden drawn layer DeepCo on GDS layer 35/0 = 35/0")
 	-&gt; do
 	    PEmPoly.dup
-	end.().output("forbidden.PEmPoly", "Forbidden drawn layer PEmPoly on GDS layer 53/0")
+	end.().output("forbidden.PEmPoly", "Forbidden drawn layer PEmPoly on GDS layer 53/0 = 53/0")
 	-&gt; do
 	    EmPoly.dup
-	end.().output("forbidden.EmPoly", "Forbidden gen./drawn layer EmPoly on GDS layer 53/0")
+	end.().output("forbidden.EmPoly", "Forbidden gen./drawn layer EmPoly on GDS layer 53/0 = 53/0")
 	-&gt; do
 	    LDMOS.dup
-	end.().output("forbidden.LDMOS", "Forbidden drawn layer LDMOS on GDS layer 57/0")
+	end.().output("forbidden.LDMOS", "Forbidden drawn layer LDMOS on GDS layer 57/0 = 57/0")
 	-&gt; do
 	    PBiWind.dup
-	end.().output("forbidden.PBiWind", "Forbidden drawn layer PBiWind on GDS layer 58/0")
+	end.().output("forbidden.PBiWind", "Forbidden drawn layer PBiWind on GDS layer 58/0 = 58/0")
 	-&gt; do
 	    Flash.dup
-	end.().output("forbidden.Flash", "Forbidden drawn layer Flash on GDS layer 71/0")
+	end.().output("forbidden.Flash", "Forbidden drawn layer Flash on GDS layer 71/0 = 71/0")
 	-&gt; do
 	    ColWind.dup
-	end.().output("forbidden.ColWind", "Forbidden drawn layer ColWind on GDS layer 139/0")
+	end.().output("forbidden.ColWind", "Forbidden drawn layer ColWind on GDS layer 139/0 = 139/0")
 end
+
+puts("Number of DRC errors: #{$drc_error_count}")
 </text>
 </klayout-macro>
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/custom_writer.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/custom_writer.lvs
index 09c33fe6..d066459f 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/custom_writer.lvs
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/custom_writer.lvs
@@ -50,17 +50,32 @@ class CustomWriter < RBA::NetlistSpiceWriterDelegate
     "#{terminals.join(' ')} "
   end
 
-  # Generate parameters with given keys
-  def generate_parameters(device, *keys)
-    parameters = keys.map { |key| "#{key}=#{device.parameter(key)}" }
-    parameters.join(' ')
+  # Determine the unit for each parameter
+  def get_unit(key)
+    case key
+    when 'W', 'L', 'w', 'wfeed', 'l', 's', 'd', 'ps'
+      'u'  # micrometers
+    when 'AS', 'AD', 'AE', 'AB', 'AC', 'A'
+      'p'  # picometers (these are areas um^2)
+    when 'PS', 'PD', 'PE', 'PB', 'PC', 'P', 'Perim'
+      'u'  # micrometers (perimeters)
+    else
+      ''  # no unit
+    end
   end
 
   # Generate default parameters for the device
   def generate_default_parameters(device, device_class)
     parameters = device_class.parameter_definitions.map do |pd|
-      format('%<name>s=%<value>.12g', name: pd.name, value: device.parameter(pd.id))
+      unit = get_unit(pd.name)
+      value = device.parameter(pd.id)
+      if value && value > 0
+        format('%<name>s=%<value>.12g%<unit>s', name: pd.name, value: value, unit: unit)
+      elsif value
+        format('%<name>s=%<value>.12g', name: pd.name, value: value)
+      end
     end
-    parameters.join(' ')
+    # Use compact to remove any nil values
+    parameters.compact.join(' ')
   end
 end
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/devices_connections.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/devices_connections.lvs
index 186f0aec..e95b932b 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/devices_connections.lvs
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/devices_connections.lvs
@@ -21,7 +21,7 @@
 #------------ DEVICES CONNECTIVITY --------------
 #================================================
 
-logger.info('Starting GF180 LVS connectivity setup')
+logger.info('Starting SG13G2 LVS connectivity setup')
 
 #================================
 # ----- GENERAL CONNECTIONS -----
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/esd_connections.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/esd_connections.lvs
index 7c37e0a5..6a0c5cb9 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/esd_connections.lvs
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/esd_connections.lvs
@@ -17,9 +17,9 @@
 # SPDX-License-Identifier: Apache-2.0
 #==========================================================================
 
-#================================
-# ---- RESISTOR CONNECTIONS -----
-#================================
+#===============================
+# ------ ESD CONNECTIONS -------
+#===============================
 
 logger.info('Starting ESD CONNECTIONS')
 
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/esd_derivations.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/esd_derivations.lvs
index bd78b0ff..94e81af9 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/esd_derivations.lvs
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/esd_derivations.lvs
@@ -18,7 +18,7 @@
 #==========================================================================
 
 #================================
-# ---- MOS-SAB DERIVATIONS ------
+# ------- ESD DERIVATIONS -------
 #================================
 
 logger.info('Starting ESD DERIVATIONS')
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/esd_extraction.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/esd_extraction.lvs
index 585281ee..3e502961 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/esd_extraction.lvs
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/esd_extraction.lvs
@@ -18,7 +18,7 @@
 #==========================================================================
 
 #================================
-# ----- MOS-SAB EXTRACTION ------
+# ------- ESD DERIVATIONS -------
 #================================
 
 logger.info('Starting ESD EXTRACTION')
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/general_connections.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/general_connections.lvs
index c279ed68..cf3ea988 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/general_connections.lvs
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/general_connections.lvs
@@ -21,7 +21,7 @@
 # ----- GENERAL CONNECTIONS -----
 #================================
 
-logger.info('Starting GF180 LVS connectivity setup (Inter-layer)')
+logger.info('Starting SG13G2 LVS connectivity setup (Inter-layer)')
 
 # Inter-layer
 connect(pwell_sub, pwell)
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/layers_definitions.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/layers_definitions.lvs
index e6cf6ba5..0d7cb466 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/layers_definitions.lvs
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/layers_definitions.lvs
@@ -32,19 +32,12 @@ def get_polygons(lay_no, lay_dt)
   end
 end
 
-nodrc_drw = get_polygons(62, 0)
-count = nodrc_drw.count()
-logger.info("nodrc_drw has #{count} polygons")
-polygons_count += count
-
 activ_drw = get_polygons(1, 0)
-activ_drw = activ_drw.not(nodrc_drw)
 count = activ_drw.count()
 logger.info("activ_drw has #{count} polygons")
 polygons_count += count
 
 activ_filler = get_polygons(1, 22)
-activ_filler = activ_filler.not(nodrc_drw)
 count = activ_filler.count()
 logger.info("activ_filler has #{count} polygons")
 polygons_count += count
@@ -55,61 +48,51 @@ count = activ.count()
 logger.info("activ has #{count} polygons")
 
 activ_pin = get_polygons(1, 2)
-activ_pin = activ_pin.not(nodrc_drw)
 count = activ_pin.count()
 logger.info("activ_pin has #{count} polygons")
 polygons_count += count
 
 activ_mask = get_polygons(1, 20)
-activ_mask = activ_mask.not(nodrc_drw)
 count = activ_mask.count()
 logger.info("activ_mask has #{count} polygons")
 polygons_count += count
 
 activ_nofill = get_polygons(1, 23)
-activ_nofill = activ_nofill.not(nodrc_drw)
 count = activ_nofill.count()
 logger.info("activ_nofill has #{count} polygons")
 polygons_count += count
 
 activ_OPC = get_polygons(1, 26)
-activ_OPC = activ_OPC.not(nodrc_drw)
 count = activ_OPC.count()
 logger.info("activ_OPC has #{count} polygons")
 polygons_count += count
 
 activ_iOPC = get_polygons(1, 27)
-activ_iOPC = activ_iOPC.not(nodrc_drw)
 count = activ_iOPC.count()
 logger.info("activ_iOPC has #{count} polygons")
 polygons_count += count
 
 activ_noqrc = get_polygons(1, 28)
-activ_noqrc = activ_noqrc.not(nodrc_drw)
 count = activ_noqrc.count()
 logger.info("activ_noqrc has #{count} polygons")
 polygons_count += count
 
 biwind_drw = get_polygons(3, 0)
-biwind_drw = biwind_drw.not(nodrc_drw)
 count = biwind_drw.count()
 logger.info("biwind_drw has #{count} polygons")
 polygons_count += count
 
 biwind_OPC = get_polygons(3, 26)
-biwind_OPC = biwind_OPC.not(nodrc_drw)
 count = biwind_OPC.count()
 logger.info("biwind_OPC has #{count} polygons")
 polygons_count += count
 
 gatpoly_drw = get_polygons(5, 0)
-gatpoly_drw = gatpoly_drw.not(nodrc_drw)
 count = gatpoly_drw.count()
 logger.info("gatpoly_drw has #{count} polygons")
 polygons_count += count
 
 gatpoly_filler = get_polygons(5, 22)
-gatpoly_filler = gatpoly_filler.not(nodrc_drw)
 count = gatpoly_filler.count()
 logger.info("gatpoly_filler has #{count} polygons")
 polygons_count += count
@@ -120,73 +103,61 @@ count = gatpoly.count()
 logger.info("gatpoly has #{count} polygons")
 
 gatpoly_pin = get_polygons(5, 2)
-gatpoly_pin = gatpoly_pin.not(nodrc_drw)
 count = gatpoly_pin.count()
 logger.info("gatpoly_pin has #{count} polygons")
 polygons_count += count
 
 gatpoly_nofill = get_polygons(5, 23)
-gatpoly_nofill = gatpoly_nofill.not(nodrc_drw)
 count = gatpoly_nofill.count()
 logger.info("gatpoly_nofill has #{count} polygons")
 polygons_count += count
 
 gatpoly_OPC = get_polygons(5, 26)
-gatpoly_OPC = gatpoly_OPC.not(nodrc_drw)
 count = gatpoly_OPC.count()
 logger.info("gatpoly_OPC has #{count} polygons")
 polygons_count += count
 
 gatpoly_iOPC = get_polygons(5, 27)
-gatpoly_iOPC = gatpoly_iOPC.not(nodrc_drw)
 count = gatpoly_iOPC.count()
 logger.info("gatpoly_iOPC has #{count} polygons")
 polygons_count += count
 
 gatpoly_noqrc = get_polygons(5, 28)
-gatpoly_noqrc = gatpoly_noqrc.not(nodrc_drw)
 count = gatpoly_noqrc.count()
 logger.info("gatpoly_noqrc has #{count} polygons")
 polygons_count += count
 
 cont_drw = get_polygons(6, 0)
-cont_drw = cont_drw.not(nodrc_drw)
 count = cont_drw.count()
 logger.info("cont_drw has #{count} polygons")
 polygons_count += count
 
 cont_OPC = get_polygons(6, 26)
-cont_OPC = cont_OPC.not(nodrc_drw)
 count = cont_OPC.count()
 logger.info("cont_OPC has #{count} polygons")
 polygons_count += count
 
 nsd_drw  = get_polygons(7, 0)
-nsd_drw = nsd_drw.not(nodrc_drw)
 count = nsd_drw.count()
 logger.info("nsd_drw has #{count} polygons")
 polygons_count += count
 
 nsd_block = get_polygons(7, 21)
-nsd_block = nsd_block.not(nodrc_drw)
 count = nsd_block.count()
 logger.info("nsd_block has #{count} polygons")
 polygons_count += count
 
 metal1_drw = get_polygons(8, 0)
-metal1_drw = metal1_drw.not(nodrc_drw)
 count = metal1_drw.count()
 logger.info("metal1_drw has #{count} polygons")
 polygons_count += count
 
 metal1_filler = get_polygons(8, 22)
-metal1_filler = metal1_filler.not(nodrc_drw)
 count = metal1_filler.count()
 logger.info("metal1_filler has #{count} polygons")
 polygons_count += count
 
 metal1_slit = get_polygons(8, 24)
-metal1_slit = metal1_slit.not(nodrc_drw)
 count = metal1_slit.count()
 logger.info("metal1_slit has #{count} polygons")
 polygons_count += count
@@ -197,103 +168,86 @@ count = metal1.count()
 logger.info("metal1 has #{count} polygons")
 
 metal1_pin = get_polygons(8, 2)
-metal1_pin = metal1_pin.not(nodrc_drw)
 count = metal1_pin.count()
 logger.info("metal1_pin has #{count} polygons")
 polygons_count += count
 
 metal1_mask = get_polygons(8, 20)
-metal1_mask = metal1_mask.not(nodrc_drw)
 count = metal1_mask.count()
 logger.info("metal1_mask has #{count} polygons")
 polygons_count += count
 
 metal1_nofill = get_polygons(8, 23)
-metal1_nofill = metal1_nofill.not(nodrc_drw)
 count = metal1_nofill.count()
 logger.info("metal1_nofill has #{count} polygons")
 polygons_count += count
 
 metal1_text = labels(8, 25)
-metal1_text = metal1_text.not(nodrc_drw)
 count = metal1_text.count()
 logger.info("metal1_text has #{count} polygons")
 polygons_count += count
 
 metal1_OPC = get_polygons(8, 26)
-metal1_OPC = metal1_OPC.not(nodrc_drw)
 count = metal1_OPC.count()
 logger.info("metal1_OPC has #{count} polygons")
 polygons_count += count
 
 metal1_noqrc = get_polygons(8, 28)
-metal1_noqrc = metal1_noqrc.not(nodrc_drw)
 count = metal1_noqrc.count()
 logger.info("metal1_noqrc has #{count} polygons")
 polygons_count += count
 
 metal1_res = get_polygons(8, 29)
-metal1_res = metal1_res.not(nodrc_drw)
 count = metal1_res.count()
 logger.info("metal1_res has #{count} polygons")
 polygons_count += count
 
 metal1_iprobe = get_polygons(8, 33)
-metal1_iprobe = metal1_iprobe.not(nodrc_drw)
 count = metal1_iprobe.count()
 logger.info("metal1_iprobe has #{count} polygons")
 polygons_count += count
 
 metal1_diffprb = get_polygons(8, 34)
-metal1_diffprb = metal1_diffprb.not(nodrc_drw)
 count = metal1_diffprb.count()
 logger.info("metal1_diffprb has #{count} polygons")
 polygons_count += count
 
 passiv_drw = get_polygons(9, 0)
-passiv_drw = passiv_drw.not(nodrc_drw)
 count = passiv_drw.count()
 logger.info("passiv_drw has #{count} polygons")
 polygons_count += count
 
 passiv_pin = get_polygons(9, 2)
-passiv_pin = passiv_pin.not(nodrc_drw)
 count = passiv_pin.count()
 logger.info("passiv_pin has #{count} polygons")
 polygons_count += count
 
 passiv_sbump = get_polygons(9, 36)
-passiv_sbump = passiv_sbump.not(nodrc_drw)
 count = passiv_sbump.count()
 logger.info("passiv_sbump has #{count} polygons")
 polygons_count += count
 
 passiv_pillar = get_polygons(9, 35)
-passiv_pillar = passiv_pillar.not(nodrc_drw)
 count = passiv_pillar.count()
 logger.info("passiv_pillar has #{count} polygons")
 polygons_count += count
 
 passiv_pdl = get_polygons(9, 40)
-passiv_pdl = passiv_pdl.not(nodrc_drw)
 count = passiv_pdl.count()
 logger.info("passiv_pdl has #{count} polygons")
 polygons_count += count
 
 metal2_drw = get_polygons(10, 0)
-metal2_drw = metal2_drw.not(nodrc_drw)
 count = metal2_drw.count()
 logger.info("metal2_drw has #{count} polygons")
 polygons_count += count
 
 metal2_filler = get_polygons(10, 22)
-metal2_filler = metal2_filler.not(nodrc_drw)
 count = metal2_filler.count()
 logger.info("metal2_filler has #{count} polygons")
 polygons_count += count
 
 metal2_slit = get_polygons(10, 24)
-metal2_slit = metal2_slit.not(nodrc_drw)
 count = metal2_slit.count()
 logger.info("metal2_slit has #{count} polygons")
 polygons_count += count
@@ -304,235 +258,196 @@ count = metal2.count()
 logger.info("metal2 has #{count} polygons")
 
 metal2_pin = get_polygons(10, 2)
-metal2_pin = metal2_pin.not(nodrc_drw)
 count = metal2_pin.count()
 logger.info("metal2_pin has #{count} polygons")
 polygons_count += count
 
 metal2_mask = get_polygons(10, 20)
-metal2_mask = metal2_mask.not(nodrc_drw)
 count = metal2_mask.count()
 logger.info("metal2_mask has #{count} polygons")
 polygons_count += count
 
 metal2_nofill = get_polygons(10, 23)
-metal2_nofill = metal2_nofill.not(nodrc_drw)
 count = metal2_nofill.count()
 logger.info("metal2_nofill has #{count} polygons")
 polygons_count += count
 
 metal2_text = labels(10, 25)
-metal2_text = metal2_text.not(nodrc_drw)
 count = metal2_text.count()
 logger.info("metal2_text has #{count} polygons")
 polygons_count += count
 
 metal2_OPC = get_polygons(10, 26)
-metal2_OPC = metal2_OPC.not(nodrc_drw)
 count = metal2_OPC.count()
 logger.info("metal2_OPC has #{count} polygons")
 polygons_count += count
 
 metal2_noqrc = get_polygons(10, 28)
-metal2_noqrc = metal2_noqrc.not(nodrc_drw)
 count = metal2_noqrc.count()
 logger.info("metal2_noqrc has #{count} polygons")
 polygons_count += count
 
 metal2_res = get_polygons(10, 29)
-metal2_res = metal2_res.not(nodrc_drw)
 count = metal2_res.count()
 logger.info("metal2_res has #{count} polygons")
 polygons_count += count
 
 metal2_iprobe = get_polygons(10, 33)
-metal2_iprobe = metal2_iprobe.not(nodrc_drw)
 count = metal2_iprobe.count()
 logger.info("metal2_iprobe has #{count} polygons")
 polygons_count += count
 
 metal2_diffprb = get_polygons(10, 34)
-metal2_diffprb = metal2_diffprb.not(nodrc_drw)
 count = metal2_diffprb.count()
 logger.info("metal2_diffprb has #{count} polygons")
 polygons_count += count
 
 baspoly_drw = get_polygons(13, 0)
-baspoly_drw = baspoly_drw.not(nodrc_drw)
 count = baspoly_drw.count()
 logger.info("baspoly_drw has #{count} polygons")
 polygons_count += count
 
 baspoly_pin = get_polygons(13, 2)
-baspoly_pin = baspoly_pin.not(nodrc_drw)
 count = baspoly_pin.count()
 logger.info("baspoly_pin has #{count} polygons")
 polygons_count += count
 
 psd_drw  = get_polygons(14, 0)
-psd_drw = psd_drw.not(nodrc_drw)
 count = psd_drw.count()
 logger.info("psd_drw has #{count} polygons")
 polygons_count += count
 
 nldb_drw = get_polygons(15, 0)
-nldb_drw = nldb_drw.not(nodrc_drw)
 count = nldb_drw.count()
 logger.info("nldb_drw has #{count} polygons")
 polygons_count += count
 
 digibnd_drw = get_polygons(16, 0)
-digibnd_drw = digibnd_drw.not(nodrc_drw)
 count = digibnd_drw.count()
 logger.info("digibnd_drw has #{count} polygons")
 polygons_count += count
 
 via1_drw = get_polygons(19, 0)
-via1_drw = via1_drw.not(nodrc_drw)
 count = via1_drw.count()
 logger.info("via1_drw has #{count} polygons")
 polygons_count += count
 
 backmetal1_drw = get_polygons(20, 0)
-backmetal1_drw = backmetal1_drw.not(nodrc_drw)
 count = backmetal1_drw.count()
 logger.info("backmetal1_drw has #{count} polygons")
 polygons_count += count
 
 backmetal1_pin = get_polygons(20, 2)
-backmetal1_pin = backmetal1_pin.not(nodrc_drw)
 count = backmetal1_pin.count()
 logger.info("backmetal1_pin has #{count} polygons")
 polygons_count += count
 
 backmetal1_mask = get_polygons(20, 20)
-backmetal1_mask = backmetal1_mask.not(nodrc_drw)
 count = backmetal1_mask.count()
 logger.info("backmetal1_mask has #{count} polygons")
 polygons_count += count
 
 backmetal1_filler = get_polygons(20, 22)
-backmetal1_filler = backmetal1_filler.not(nodrc_drw)
 count = backmetal1_filler.count()
 logger.info("backmetal1_filler has #{count} polygons")
 polygons_count += count
 
 backmetal1_nofill = get_polygons(20, 23)
-backmetal1_nofill = backmetal1_nofill.not(nodrc_drw)
 count = backmetal1_nofill.count()
 logger.info("backmetal1_nofill has #{count} polygons")
 polygons_count += count
 
 backmetal1_slit = get_polygons(20, 24)
-backmetal1_slit = backmetal1_slit.not(nodrc_drw)
 count = backmetal1_slit.count()
 logger.info("backmetal1_slit has #{count} polygons")
 polygons_count += count
 
 backmetal1_text = labels(20, 25)
-backmetal1_text = backmetal1_text.not(nodrc_drw)
 count = backmetal1_text.count()
 logger.info("backmetal1_text has #{count} polygons")
 polygons_count += count
 
 backmetal1_OPC = get_polygons(20, 26)
-backmetal1_OPC = backmetal1_OPC.not(nodrc_drw)
 count = backmetal1_OPC.count()
 logger.info("backmetal1_OPC has #{count} polygons")
 polygons_count += count
 
 backmetal1_noqrc = get_polygons(20, 28)
-backmetal1_noqrc = backmetal1_noqrc.not(nodrc_drw)
 count = backmetal1_noqrc.count()
 logger.info("backmetal1_noqrc has #{count} polygons")
 polygons_count += count
 
 backmetal1_res = get_polygons(20, 29)
-backmetal1_res = backmetal1_res.not(nodrc_drw)
 count = backmetal1_res.count()
 logger.info("backmetal1_res has #{count} polygons")
 polygons_count += count
 
 backmetal1_iprobe = get_polygons(20, 33)
-backmetal1_iprobe = backmetal1_iprobe.not(nodrc_drw)
 count = backmetal1_iprobe.count()
 logger.info("backmetal1_iprobe has #{count} polygons")
 polygons_count += count
 
 backmetal1_diffprb = get_polygons(20, 34)
-backmetal1_diffprb = backmetal1_diffprb.not(nodrc_drw)
 count = backmetal1_diffprb.count()
 logger.info("backmetal1_diffprb has #{count} polygons")
 polygons_count += count
 
 backpassiv_drw = get_polygons(23, 0)
-backpassiv_drw = backpassiv_drw.not(nodrc_drw)
 count = backpassiv_drw.count()
 logger.info("backpassiv_drw has #{count} polygons")
 polygons_count += count
 
 res_drw  = get_polygons(24, 0)
-res_drw = res_drw.not(nodrc_drw)
 count = res_drw.count()
 logger.info("res_drw has #{count} polygons")
 polygons_count += count
 
 sram_drw = get_polygons(25, 0)
-sram_drw = sram_drw.not(nodrc_drw)
 count = sram_drw.count()
 logger.info("sram_drw has #{count} polygons")
 polygons_count += count
 
 trans_drw = get_polygons(26, 0)
-trans_drw = trans_drw.not(nodrc_drw)
 count = trans_drw.count()
 logger.info("trans_drw has #{count} polygons")
 polygons_count += count
 
 ind_drw  = get_polygons(27, 0)
-ind_drw = ind_drw.not(nodrc_drw)
 count = ind_drw.count()
 logger.info("ind_drw has #{count} polygons")
 polygons_count += count
 
 ind_pin  = get_polygons(27, 2)
-ind_pin = ind_pin.not(nodrc_drw)
 count = ind_pin.count()
 logger.info("ind_pin has #{count} polygons")
 polygons_count += count
 
 ind_text = labels(27, 25)
-ind_text = ind_text.not(nodrc_drw)
 count = ind_text.count()
 logger.info("ind_text has #{count} polygons")
 polygons_count += count
 
 salblock_drw = get_polygons(28, 0)
-salblock_drw = salblock_drw.not(nodrc_drw)
 count = salblock_drw.count()
 logger.info("salblock_drw has #{count} polygons")
 polygons_count += count
 
 via2_drw = get_polygons(29, 0)
-via2_drw = via2_drw.not(nodrc_drw)
 count = via2_drw.count()
 logger.info("via2_drw has #{count} polygons")
 polygons_count += count
 
 metal3_drw = get_polygons(30, 0)
-metal3_drw = metal3_drw.not(nodrc_drw)
 count = metal3_drw.count()
 logger.info("metal3_drw has #{count} polygons")
 polygons_count += count
 
 metal3_filler = get_polygons(30, 22)
-metal3_filler = metal3_filler.not(nodrc_drw)
 count = metal3_filler.count()
 logger.info("metal3_filler has #{count} polygons")
 polygons_count += count
 
 metal3_slit = get_polygons(30, 24)
-metal3_slit = metal3_slit.not(nodrc_drw)
 count = metal3_slit.count()
 logger.info("metal3_slit has #{count} polygons")
 polygons_count += count
@@ -543,205 +458,171 @@ count = metal3.count()
 logger.info("metal3 has #{count} polygons")
 
 metal3_pin = get_polygons(30, 2)
-metal3_pin = metal3_pin.not(nodrc_drw)
 count = metal3_pin.count()
 logger.info("metal3_pin has #{count} polygons")
 polygons_count += count
 
 metal3_mask = get_polygons(30, 20)
-metal3_mask = metal3_mask.not(nodrc_drw)
 count = metal3_mask.count()
 logger.info("metal3_mask has #{count} polygons")
 polygons_count += count
 
 metal3_nofill = get_polygons(30, 23)
-metal3_nofill = metal3_nofill.not(nodrc_drw)
 count = metal3_nofill.count()
 logger.info("metal3_nofill has #{count} polygons")
 polygons_count += count
 
 metal3_text = labels(30, 25)
-metal3_text = metal3_text.not(nodrc_drw)
 count = metal3_text.count()
 logger.info("metal3_text has #{count} polygons")
 polygons_count += count
 
 metal3_OPC = get_polygons(30, 26)
-metal3_OPC = metal3_OPC.not(nodrc_drw)
 count = metal3_OPC.count()
 logger.info("metal3_OPC has #{count} polygons")
 polygons_count += count
 
 metal3_noqrc = get_polygons(30, 28)
-metal3_noqrc = metal3_noqrc.not(nodrc_drw)
 count = metal3_noqrc.count()
 logger.info("metal3_noqrc has #{count} polygons")
 polygons_count += count
 
 metal3_res = get_polygons(30, 29)
-metal3_res = metal3_res.not(nodrc_drw)
 count = metal3_res.count()
 logger.info("metal3_res has #{count} polygons")
 polygons_count += count
 
 metal3_iprobe = get_polygons(30, 33)
-metal3_iprobe = metal3_iprobe.not(nodrc_drw)
 count = metal3_iprobe.count()
 logger.info("metal3_iprobe has #{count} polygons")
 polygons_count += count
 
 metal3_diffprb = get_polygons(30, 34)
-metal3_diffprb = metal3_diffprb.not(nodrc_drw)
 count = metal3_diffprb.count()
 logger.info("metal3_diffprb has #{count} polygons")
 polygons_count += count
 
 nwell_drw = get_polygons(31, 0)
-nwell_drw = nwell_drw.not(nodrc_drw)
 count = nwell_drw.count()
 logger.info("nwell_drw has #{count} polygons")
 polygons_count += count
 
 nwell_pin = get_polygons(31, 2)
-nwell_pin = nwell_pin.not(nodrc_drw)
 count = nwell_pin.count()
 logger.info("nwell_pin has #{count} polygons")
 polygons_count += count
 
 nbulay_drw = get_polygons(32, 0)
-nbulay_drw = nbulay_drw.not(nodrc_drw)
 count = nbulay_drw.count()
 logger.info("nbulay_drw has #{count} polygons")
 polygons_count += count
 
 nbulay_pin = get_polygons(32, 2)
-nbulay_pin = nbulay_pin.not(nodrc_drw)
 count = nbulay_pin.count()
 logger.info("nbulay_pin has #{count} polygons")
 polygons_count += count
 
 nbulay_block = get_polygons(32, 21)
-nbulay_block = nbulay_block.not(nodrc_drw)
 count = nbulay_block.count()
 logger.info("nbulay_block has #{count} polygons")
 polygons_count += count
 
 emwind_drw = get_polygons(33, 0)
-emwind_drw = emwind_drw.not(nodrc_drw)
 count = emwind_drw.count()
 logger.info("emwind_drw has #{count} polygons")
 polygons_count += count
 
 emwind_OPC = get_polygons(33, 26)
-emwind_OPC = emwind_OPC.not(nodrc_drw)
 count = emwind_OPC.count()
 logger.info("emwind_OPC has #{count} polygons")
 polygons_count += count
 
 deepco_drw = get_polygons(35, 0)
-deepco_drw = deepco_drw.not(nodrc_drw)
 count = deepco_drw.count()
 logger.info("deepco_drw has #{count} polygons")
 polygons_count += count
 
 mim_drw  = get_polygons(36, 0)
-mim_drw = mim_drw.not(nodrc_drw)
 count = mim_drw.count()
 logger.info("mim_drw has #{count} polygons")
 polygons_count += count
 
 edgeseal_drw = get_polygons(39, 0)
-edgeseal_drw = edgeseal_drw.not(nodrc_drw)
 count = edgeseal_drw.count()
 logger.info("edgeseal_drw has #{count} polygons")
 polygons_count += count
 
 substrate_drw = get_polygons(40, 0)
-substrate_drw = substrate_drw.not(nodrc_drw)
 count = substrate_drw.count()
 logger.info("substrate_drw has #{count} polygons")
 polygons_count += count
 
 substrate_text = labels(40, 25)
-substrate_text = substrate_text.not(nodrc_drw)
 count = substrate_text.count()
 logger.info("substrate_text has #{count} polygons")
 polygons_count += count
 
 dfpad_drw = get_polygons(41, 0)
-dfpad_drw = dfpad_drw.not(nodrc_drw)
 count = dfpad_drw.count()
 logger.info("dfpad_drw has #{count} polygons")
 polygons_count += count
 
 dfpad_pillar = get_polygons(41, 35)
-dfpad_pillar = dfpad_pillar.not(nodrc_drw)
 count = dfpad_pillar.count()
 logger.info("dfpad_pillar has #{count} polygons")
 polygons_count += count
 
 dfpad_sbump = get_polygons(41, 36)
-dfpad_sbump = dfpad_sbump.not(nodrc_drw)
 count = dfpad_sbump.count()
 logger.info("dfpad_sbump has #{count} polygons")
 polygons_count += count
 
 thickgateox_drw = get_polygons(44, 0)
-thickgateox_drw = thickgateox_drw.not(nodrc_drw)
 count = thickgateox_drw.count()
 logger.info("thickgateox_drw has #{count} polygons")
 polygons_count += count
 
 pldb_drw = get_polygons(45, 0)
-pldb_drw = pldb_drw.not(nodrc_drw)
 count = pldb_drw.count()
 logger.info("pldb_drw has #{count} polygons")
 polygons_count += count
 
 pwell_drw = get_polygons(46, 0)
-pwell_drw = pwell_drw.not(nodrc_drw)
 count = pwell_drw.count()
 logger.info("pwell_drw has #{count} polygons")
 polygons_count += count
 
 pwell_pin = get_polygons(46, 2)
-pwell_pin = pwell_pin.not(nodrc_drw)
 count = pwell_pin.count()
 logger.info("pwell_pin has #{count} polygons")
 polygons_count += count
 
 pwell_block = get_polygons(46, 21)
-pwell_block = pwell_block.not(nodrc_drw)
 count = pwell_block.count()
 logger.info("pwell_block has #{count} polygons")
 polygons_count += count
 
 ic_drw   = get_polygons(48, 0)
-ic_drw = ic_drw.not(nodrc_drw)
 count = ic_drw.count()
 logger.info("ic_drw has #{count} polygons")
 polygons_count += count
 
 via3_drw = get_polygons(49, 0)
-via3_drw = via3_drw.not(nodrc_drw)
 count = via3_drw.count()
 logger.info("via3_drw has #{count} polygons")
 polygons_count += count
 
 metal4_drw = get_polygons(50, 0)
-metal4_drw = metal4_drw.not(nodrc_drw)
 count = metal4_drw.count()
 logger.info("metal4_drw has #{count} polygons")
 polygons_count += count
 
 metal4_filler = get_polygons(50, 22)
-metal4_filler = metal4_filler.not(nodrc_drw)
 count = metal4_filler.count()
 logger.info("metal4_filler has #{count} polygons")
 polygons_count += count
 
 metal4_slit = get_polygons(50, 24)
-metal4_slit = metal4_slit.not(nodrc_drw)
 count = metal4_slit.count()
 logger.info("metal4_slit has #{count} polygons")
 polygons_count += count
@@ -752,115 +633,96 @@ count = metal4.count()
 logger.info("metal4 has #{count} polygons")
 
 metal4_pin = get_polygons(50, 2)
-metal4_pin = metal4_pin.not(nodrc_drw)
 count = metal4_pin.count()
 logger.info("metal4_pin has #{count} polygons")
 polygons_count += count
 
 metal4_mask = get_polygons(50, 20)
-metal4_mask = metal4_mask.not(nodrc_drw)
 count = metal4_mask.count()
 logger.info("metal4_mask has #{count} polygons")
 polygons_count += count
 
 metal4_nofill = get_polygons(50, 23)
-metal4_nofill = metal4_nofill.not(nodrc_drw)
 count = metal4_nofill.count()
 logger.info("metal4_nofill has #{count} polygons")
 polygons_count += count
 
 metal4_text = labels(50, 25)
-metal4_text = metal4_text.not(nodrc_drw)
 count = metal4_text.count()
 logger.info("metal4_text has #{count} polygons")
 polygons_count += count
 
 metal4_OPC = get_polygons(50, 26)
-metal4_OPC = metal4_OPC.not(nodrc_drw)
 count = metal4_OPC.count()
 logger.info("metal4_OPC has #{count} polygons")
 polygons_count += count
 
 metal4_noqrc = get_polygons(50, 28)
-metal4_noqrc = metal4_noqrc.not(nodrc_drw)
 count = metal4_noqrc.count()
 logger.info("metal4_noqrc has #{count} polygons")
 polygons_count += count
 
 metal4_res = get_polygons(50, 29)
-metal4_res = metal4_res.not(nodrc_drw)
 count = metal4_res.count()
 logger.info("metal4_res has #{count} polygons")
 polygons_count += count
 
 metal4_iprobe = get_polygons(50, 33)
-metal4_iprobe = metal4_iprobe.not(nodrc_drw)
 count = metal4_iprobe.count()
 logger.info("metal4_iprobe has #{count} polygons")
 polygons_count += count
 
 metal4_diffprb = get_polygons(50, 34)
-metal4_diffprb = metal4_diffprb.not(nodrc_drw)
 count = metal4_diffprb.count()
 logger.info("metal4_diffprb has #{count} polygons")
 polygons_count += count
 
 heattrans_drw = get_polygons(51, 0)
-heattrans_drw = heattrans_drw.not(nodrc_drw)
 count = heattrans_drw.count()
 logger.info("heattrans_drw has #{count} polygons")
 polygons_count += count
 
 heatres_drw = get_polygons(52, 0)
-heatres_drw = heatres_drw.not(nodrc_drw)
 count = heatres_drw.count()
 logger.info("heatres_drw has #{count} polygons")
 polygons_count += count
 
 fbe_drw  = get_polygons(54, 0)
-fbe_drw = fbe_drw.not(nodrc_drw)
 count = fbe_drw.count()
 logger.info("fbe_drw has #{count} polygons")
 polygons_count += count
 
 empoly_drw = get_polygons(55, 0)
-empoly_drw = empoly_drw.not(nodrc_drw)
 count = empoly_drw.count()
 logger.info("empoly_drw has #{count} polygons")
 polygons_count += count
 
 digisub_drw = get_polygons(60, 0)
-digisub_drw = digisub_drw.not(nodrc_drw)
 count = digisub_drw.count()
 logger.info("digisub_drw has #{count} polygons")
 polygons_count += count
 
 text_drw = labels(63, 0)
-text_drw = text_drw.not(nodrc_drw)
 count = text_drw.count()
 logger.info("text_drw has #{count} polygons")
 polygons_count += count
 
 via4_drw = get_polygons(66, 0)
-via4_drw = via4_drw.not(nodrc_drw)
 count = via4_drw.count()
 logger.info("via4_drw has #{count} polygons")
 polygons_count += count
 
 metal5_drw = get_polygons(67, 0)
-metal5_drw = metal5_drw.not(nodrc_drw)
 count = metal5_drw.count()
 logger.info("metal5_drw has #{count} polygons")
 polygons_count += count
 
 metal5_filler = get_polygons(67, 22)
-metal5_filler = metal5_filler.not(nodrc_drw)
 count = metal5_filler.count()
 logger.info("metal5_filler has #{count} polygons")
 polygons_count += count
 
 metal5_slit = get_polygons(67, 24)
-metal5_slit = metal5_slit.not(nodrc_drw)
 count = metal5_slit.count()
 logger.info("metal5_slit has #{count} polygons")
 polygons_count += count
@@ -871,457 +733,381 @@ count = metal5.count()
 logger.info("metal5 has #{count} polygons")
 
 metal5_pin = get_polygons(67, 2)
-metal5_pin = metal5_pin.not(nodrc_drw)
 count = metal5_pin.count()
 logger.info("metal5_pin has #{count} polygons")
 polygons_count += count
 
 metal5_mask = get_polygons(67, 20)
-metal5_mask = metal5_mask.not(nodrc_drw)
 count = metal5_mask.count()
 logger.info("metal5_mask has #{count} polygons")
 polygons_count += count
 
 metal5_nofill = get_polygons(67, 23)
-metal5_nofill = metal5_nofill.not(nodrc_drw)
 count = metal5_nofill.count()
 logger.info("metal5_nofill has #{count} polygons")
 polygons_count += count
 
 metal5_text = labels(67, 25)
-metal5_text = metal5_text.not(nodrc_drw)
 count = metal5_text.count()
 logger.info("metal5_text has #{count} polygons")
 polygons_count += count
 
 metal5_OPC = get_polygons(67, 26)
-metal5_OPC = metal5_OPC.not(nodrc_drw)
 count = metal5_OPC.count()
 logger.info("metal5_OPC has #{count} polygons")
 polygons_count += count
 
 metal5_noqrc = get_polygons(67, 28)
-metal5_noqrc = metal5_noqrc.not(nodrc_drw)
 count = metal5_noqrc.count()
 logger.info("metal5_noqrc has #{count} polygons")
 polygons_count += count
 
 metal5_res = get_polygons(67, 29)
-metal5_res = metal5_res.not(nodrc_drw)
 count = metal5_res.count()
 logger.info("metal5_res has #{count} polygons")
 polygons_count += count
 
 metal5_iprobe = get_polygons(67, 33)
-metal5_iprobe = metal5_iprobe.not(nodrc_drw)
 count = metal5_iprobe.count()
 logger.info("metal5_iprobe has #{count} polygons")
 polygons_count += count
 
 metal5_diffprb = get_polygons(67, 34)
-metal5_diffprb = metal5_diffprb.not(nodrc_drw)
 count = metal5_diffprb.count()
 logger.info("metal5_diffprb has #{count} polygons")
 polygons_count += count
 
 radhard_drw = get_polygons(68, 0)
-radhard_drw = radhard_drw.not(nodrc_drw)
 count = radhard_drw.count()
 logger.info("radhard_drw has #{count} polygons")
 polygons_count += count
 
 memcap_drw = get_polygons(69, 0)
-memcap_drw = memcap_drw.not(nodrc_drw)
 count = memcap_drw.count()
 logger.info("memcap_drw has #{count} polygons")
 polygons_count += count
 
 varicap_drw = get_polygons(70, 0)
-varicap_drw = varicap_drw.not(nodrc_drw)
 count = varicap_drw.count()
 logger.info("varicap_drw has #{count} polygons")
 polygons_count += count
 
 intbondvia_drw = get_polygons(72, 0)
-intbondvia_drw = intbondvia_drw.not(nodrc_drw)
 count = intbondvia_drw.count()
 logger.info("intbondvia_drw has #{count} polygons")
 polygons_count += count
 
 intbondmet_drw = get_polygons(73, 0)
-intbondmet_drw = intbondmet_drw.not(nodrc_drw)
 count = intbondmet_drw.count()
 logger.info("intbondmet_drw has #{count} polygons")
 polygons_count += count
 
 devbondvia_drw = get_polygons(74, 0)
-devbondvia_drw = devbondvia_drw.not(nodrc_drw)
 count = devbondvia_drw.count()
 logger.info("devbondvia_drw has #{count} polygons")
 polygons_count += count
 
 devbondmet_drw = get_polygons(75, 0)
-devbondmet_drw = devbondmet_drw.not(nodrc_drw)
 count = devbondmet_drw.count()
 logger.info("devbondmet_drw has #{count} polygons")
 polygons_count += count
 
 devtrench_drw = get_polygons(76, 0)
-devtrench_drw = devtrench_drw.not(nodrc_drw)
 count = devtrench_drw.count()
 logger.info("devtrench_drw has #{count} polygons")
 polygons_count += count
 
 redist_drw = get_polygons(77, 0)
-redist_drw = redist_drw.not(nodrc_drw)
 count = redist_drw.count()
 logger.info("redist_drw has #{count} polygons")
 polygons_count += count
 
 graphbot_drw = get_polygons(78, 0)
-graphbot_drw = graphbot_drw.not(nodrc_drw)
 count = graphbot_drw.count()
 logger.info("graphbot_drw has #{count} polygons")
 polygons_count += count
 
 graphtop_drw = get_polygons(79, 0)
-graphtop_drw = graphtop_drw.not(nodrc_drw)
 count = graphtop_drw.count()
 logger.info("graphtop_drw has #{count} polygons")
 polygons_count += count
 
 antvia1_drw = get_polygons(83, 0)
-antvia1_drw = antvia1_drw.not(nodrc_drw)
 count = antvia1_drw.count()
 logger.info("antvia1_drw has #{count} polygons")
 polygons_count += count
 
 antmetal2_drw = get_polygons(84, 0)
-antmetal2_drw = antmetal2_drw.not(nodrc_drw)
 count = antmetal2_drw.count()
 logger.info("antmetal2_drw has #{count} polygons")
 polygons_count += count
 
 graphcont_drw = get_polygons(85, 0)
-graphcont_drw = graphcont_drw.not(nodrc_drw)
 count = graphcont_drw.count()
 logger.info("graphcont_drw has #{count} polygons")
 polygons_count += count
 
 siwg_drw = get_polygons(86, 0)
-siwg_drw = siwg_drw.not(nodrc_drw)
 count = siwg_drw.count()
 logger.info("siwg_drw has #{count} polygons")
 polygons_count += count
 
 siwg_filler = get_polygons(86, 22)
-siwg_filler = siwg_filler.not(nodrc_drw)
 count = siwg_filler.count()
 logger.info("siwg_filler has #{count} polygons")
 polygons_count += count
 
 siwg_nofill = get_polygons(86, 23)
-siwg_nofill = siwg_nofill.not(nodrc_drw)
 count = siwg_nofill.count()
 logger.info("siwg_nofill has #{count} polygons")
 polygons_count += count
 
 sigrating_drw = get_polygons(87, 0)
-sigrating_drw = sigrating_drw.not(nodrc_drw)
 count = sigrating_drw.count()
 logger.info("sigrating_drw has #{count} polygons")
 polygons_count += count
 
 singrating_drw = get_polygons(88, 0)
-singrating_drw = singrating_drw.not(nodrc_drw)
 count = singrating_drw.count()
 logger.info("singrating_drw has #{count} polygons")
 polygons_count += count
 
 graphpas_drw = get_polygons(89, 0)
-graphpas_drw = graphpas_drw.not(nodrc_drw)
 count = graphpas_drw.count()
 logger.info("graphpas_drw has #{count} polygons")
 polygons_count += count
 
 emwind3_drw = get_polygons(90, 0)
-emwind3_drw = emwind3_drw.not(nodrc_drw)
 count = emwind3_drw.count()
 logger.info("emwind3_drw has #{count} polygons")
 polygons_count += count
 
 emwihv3_drw = get_polygons(91, 0)
-emwihv3_drw = emwihv3_drw.not(nodrc_drw)
 count = emwihv3_drw.count()
 logger.info("emwihv3_drw has #{count} polygons")
 polygons_count += count
 
 redbulay_drw = get_polygons(92, 0)
-redbulay_drw = redbulay_drw.not(nodrc_drw)
 count = redbulay_drw.count()
 logger.info("redbulay_drw has #{count} polygons")
 polygons_count += count
 
 smos_drw = get_polygons(93, 0)
-smos_drw = smos_drw.not(nodrc_drw)
 count = smos_drw.count()
 logger.info("smos_drw has #{count} polygons")
 polygons_count += count
 
 graphpad_drw = get_polygons(97, 0)
-graphpad_drw = graphpad_drw.not(nodrc_drw)
 count = graphpad_drw.count()
 logger.info("graphpad_drw has #{count} polygons")
 polygons_count += count
 
 polimide_drw = get_polygons(98, 0)
-polimide_drw = polimide_drw.not(nodrc_drw)
 count = polimide_drw.count()
 logger.info("polimide_drw has #{count} polygons")
 polygons_count += count
 
 polimide_pin = get_polygons(98, 2)
-polimide_pin = polimide_pin.not(nodrc_drw)
 count = polimide_pin.count()
 logger.info("polimide_pin has #{count} polygons")
 polygons_count += count
 
 recog_drw = get_polygons(99, 0)
-recog_drw = recog_drw.not(nodrc_drw)
 count = recog_drw.count()
 logger.info("recog_drw has #{count} polygons")
 polygons_count += count
 
 recog_pin = get_polygons(99, 2)
-recog_pin = recog_pin.not(nodrc_drw)
 count = recog_pin.count()
 logger.info("recog_pin has #{count} polygons")
 polygons_count += count
 
 recog_esd = get_polygons(99, 30)
-recog_esd = recog_esd.not(nodrc_drw)
 count = recog_esd.count()
 logger.info("recog_esd has #{count} polygons")
 polygons_count += count
 
 recog_diode = get_polygons(99, 31)
-recog_diode = recog_diode.not(nodrc_drw)
 count = recog_diode.count()
 logger.info("recog_diode has #{count} polygons")
 polygons_count += count
 
 recog_tsv = get_polygons(99, 32)
-recog_tsv = recog_tsv.not(nodrc_drw)
 count = recog_tsv.count()
 logger.info("recog_tsv has #{count} polygons")
 polygons_count += count
 
 recog_iprobe = get_polygons(99, 33)
-recog_iprobe = recog_iprobe.not(nodrc_drw)
 count = recog_iprobe.count()
 logger.info("recog_iprobe has #{count} polygons")
 polygons_count += count
 
 recog_diffprb = get_polygons(99, 34)
-recog_diffprb = recog_diffprb.not(nodrc_drw)
 count = recog_diffprb.count()
 logger.info("recog_diffprb has #{count} polygons")
 polygons_count += count
 
 recog_pillar = get_polygons(99, 35)
-recog_pillar = recog_pillar.not(nodrc_drw)
 count = recog_pillar.count()
 logger.info("recog_pillar has #{count} polygons")
 polygons_count += count
 
 recog_sbump = get_polygons(99, 36)
-recog_sbump = recog_sbump.not(nodrc_drw)
 count = recog_sbump.count()
 logger.info("recog_sbump has #{count} polygons")
 polygons_count += count
 
 recog_otp = get_polygons(99, 37)
-recog_otp = recog_otp.not(nodrc_drw)
 count = recog_otp.count()
 logger.info("recog_otp has #{count} polygons")
 polygons_count += count
 
 recog_pdiode = get_polygons(99, 38)
-recog_pdiode = recog_pdiode.not(nodrc_drw)
 count = recog_pdiode.count()
 logger.info("recog_pdiode has #{count} polygons")
 polygons_count += count
 
 recog_mom = get_polygons(99, 39)
-recog_mom = recog_mom.not(nodrc_drw)
 count = recog_mom.count()
 logger.info("recog_mom has #{count} polygons")
 polygons_count += count
 
 recog_pcm = get_polygons(99, 100)
-recog_pcm = recog_pcm.not(nodrc_drw)
 count = recog_pcm.count()
 logger.info("recog_pcm has #{count} polygons")
 polygons_count += count
 
 colopen_drw = get_polygons(101, 0)
-colopen_drw = colopen_drw.not(nodrc_drw)
 count = colopen_drw.count()
 logger.info("colopen_drw has #{count} polygons")
 polygons_count += count
 
 graphmetal1_drw = get_polygons(109, 0)
-graphmetal1_drw = graphmetal1_drw.not(nodrc_drw)
 count = graphmetal1_drw.count()
 logger.info("graphmetal1_drw has #{count} polygons")
 polygons_count += count
 
 graphmetal1_filler = get_polygons(109, 22)
-graphmetal1_filler = graphmetal1_filler.not(nodrc_drw)
 count = graphmetal1_filler.count()
 logger.info("graphmetal1_filler has #{count} polygons")
 polygons_count += count
 
 graphmetal1_nofill = get_polygons(109, 23)
-graphmetal1_nofill = graphmetal1_nofill.not(nodrc_drw)
 count = graphmetal1_nofill.count()
 logger.info("graphmetal1_nofill has #{count} polygons")
 polygons_count += count
 
 graphmetal1_slit = get_polygons(109, 24)
-graphmetal1_slit = graphmetal1_slit.not(nodrc_drw)
 count = graphmetal1_slit.count()
 logger.info("graphmetal1_slit has #{count} polygons")
 polygons_count += count
 
 graphmetal1_OPC = get_polygons(109, 26)
-graphmetal1_OPC = graphmetal1_OPC.not(nodrc_drw)
 count = graphmetal1_OPC.count()
 logger.info("graphmetal1_OPC has #{count} polygons")
 polygons_count += count
 
 graphmet1l_drw = get_polygons(110, 0)
-graphmet1l_drw = graphmet1l_drw.not(nodrc_drw)
 count = graphmet1l_drw.count()
 logger.info("graphmet1l_drw has #{count} polygons")
 polygons_count += count
 
 graphmet1l_filler = get_polygons(110, 22)
-graphmet1l_filler = graphmet1l_filler.not(nodrc_drw)
 count = graphmet1l_filler.count()
 logger.info("graphmet1l_filler has #{count} polygons")
 polygons_count += count
 
 graphmet1l_nofill = get_polygons(110, 23)
-graphmet1l_nofill = graphmet1l_nofill.not(nodrc_drw)
 count = graphmet1l_nofill.count()
 logger.info("graphmet1l_nofill has #{count} polygons")
 polygons_count += count
 
 graphmet1l_slit = get_polygons(110, 24)
-graphmet1l_slit = graphmet1l_slit.not(nodrc_drw)
 count = graphmet1l_slit.count()
 logger.info("graphmet1l_slit has #{count} polygons")
 polygons_count += count
 
 graphmet1l_OPC = get_polygons(110, 26)
-graphmet1l_OPC = graphmet1l_OPC.not(nodrc_drw)
 count = graphmet1l_OPC.count()
 logger.info("graphmet1l_OPC has #{count} polygons")
 polygons_count += count
 
 extblock_drw = get_polygons(111, 0)
-extblock_drw = extblock_drw.not(nodrc_drw)
 count = extblock_drw.count()
 logger.info("extblock_drw has #{count} polygons")
 polygons_count += count
 
 nldd_drw = get_polygons(112, 0)
-nldd_drw = nldd_drw.not(nodrc_drw)
 count = nldd_drw.count()
 logger.info("nldd_drw has #{count} polygons")
 polygons_count += count
 
 pldd_drw = get_polygons(113, 0)
-pldd_drw = pldd_drw.not(nodrc_drw)
 count = pldd_drw.count()
 logger.info("pldd_drw has #{count} polygons")
 polygons_count += count
 
 next_drw = get_polygons(114, 0)
-next_drw = next_drw.not(nodrc_drw)
 count = next_drw.count()
 logger.info("next_drw has #{count} polygons")
 polygons_count += count
 
 pext_drw = get_polygons(115, 0)
-pext_drw = pext_drw.not(nodrc_drw)
 count = pext_drw.count()
 logger.info("pext_drw has #{count} polygons")
 polygons_count += count
 
 nexthv_drw = get_polygons(116, 0)
-nexthv_drw = nexthv_drw.not(nodrc_drw)
 count = nexthv_drw.count()
 logger.info("nexthv_drw has #{count} polygons")
 polygons_count += count
 
 pexthv_drw = get_polygons(117, 0)
-pexthv_drw = pexthv_drw.not(nodrc_drw)
 count = pexthv_drw.count()
 logger.info("pexthv_drw has #{count} polygons")
 polygons_count += count
 
 graphgate_drw = get_polygons(118, 0)
-graphgate_drw = graphgate_drw.not(nodrc_drw)
 count = graphgate_drw.count()
 logger.info("graphgate_drw has #{count} polygons")
 polygons_count += count
 
 sinwg_drw = get_polygons(119, 0)
-sinwg_drw = sinwg_drw.not(nodrc_drw)
 count = sinwg_drw.count()
 logger.info("sinwg_drw has #{count} polygons")
 polygons_count += count
 
 sinwg_filler = get_polygons(119, 22)
-sinwg_filler = sinwg_filler.not(nodrc_drw)
 count = sinwg_filler.count()
 logger.info("sinwg_filler has #{count} polygons")
 polygons_count += count
 
 sinwg_nofill = get_polygons(119, 23)
-sinwg_nofill = sinwg_nofill.not(nodrc_drw)
 count = sinwg_nofill.count()
 logger.info("sinwg_nofill has #{count} polygons")
 polygons_count += count
 
 mempad_drw = get_polygons(124, 0)
-mempad_drw = mempad_drw.not(nodrc_drw)
 count = mempad_drw.count()
 logger.info("mempad_drw has #{count} polygons")
 polygons_count += count
 
 topvia1_drw = get_polygons(125, 0)
-topvia1_drw = topvia1_drw.not(nodrc_drw)
 count = topvia1_drw.count()
 logger.info("topvia1_drw has #{count} polygons")
 polygons_count += count
 
 topmetal1_drw = get_polygons(126, 0)
-topmetal1_drw = topmetal1_drw.not(nodrc_drw)
 count = topmetal1_drw.count()
 logger.info("topmetal1_drw has #{count} polygons")
 polygons_count += count
 
 topmetal1_filler = get_polygons(126, 22)
-topmetal1_filler = topmetal1_filler.not(nodrc_drw)
 count = topmetal1_filler.count()
 logger.info("topmetal1_filler has #{count} polygons")
 polygons_count += count
 
 topmetal1_slit = get_polygons(126, 24)
-topmetal1_slit = topmetal1_slit.not(nodrc_drw)
 count = topmetal1_slit.count()
 logger.info("topmetal1_slit has #{count} polygons")
 polygons_count += count
@@ -1332,109 +1118,91 @@ count = topmetal1.count()
 logger.info("topmetal1 has #{count} polygons")
 
 topmetal1_pin = get_polygons(126, 2)
-topmetal1_pin = topmetal1_pin.not(nodrc_drw)
 count = topmetal1_pin.count()
 logger.info("topmetal1_pin has #{count} polygons")
 polygons_count += count
 
 topmetal1_mask = get_polygons(126, 20)
-topmetal1_mask = topmetal1_mask.not(nodrc_drw)
 count = topmetal1_mask.count()
 logger.info("topmetal1_mask has #{count} polygons")
 polygons_count += count
 
 topmetal1_nofill = get_polygons(126, 23)
-topmetal1_nofill = topmetal1_nofill.not(nodrc_drw)
 count = topmetal1_nofill.count()
 logger.info("topmetal1_nofill has #{count} polygons")
 polygons_count += count
 
 topmetal1_text = labels(126, 25)
-topmetal1_text = topmetal1_text.not(nodrc_drw)
 count = topmetal1_text.count()
 logger.info("topmetal1_text has #{count} polygons")
 polygons_count += count
 
 topmetal1_noqrc = get_polygons(126, 28)
-topmetal1_noqrc = topmetal1_noqrc.not(nodrc_drw)
 count = topmetal1_noqrc.count()
 logger.info("topmetal1_noqrc has #{count} polygons")
 polygons_count += count
 
 topmetal1_res = get_polygons(126, 29)
-topmetal1_res = topmetal1_res.not(nodrc_drw)
 count = topmetal1_res.count()
 logger.info("topmetal1_res has #{count} polygons")
 polygons_count += count
 
 topmetal1_iprobe = get_polygons(126, 33)
-topmetal1_iprobe = topmetal1_iprobe.not(nodrc_drw)
 count = topmetal1_iprobe.count()
 logger.info("topmetal1_iprobe has #{count} polygons")
 polygons_count += count
 
 topmetal1_diffprb = get_polygons(126, 34)
-topmetal1_diffprb = topmetal1_diffprb.not(nodrc_drw)
 count = topmetal1_diffprb.count()
 logger.info("topmetal1_diffprb has #{count} polygons")
 polygons_count += count
 
 inldpwl_drw = get_polygons(127, 0)
-inldpwl_drw = inldpwl_drw.not(nodrc_drw)
 count = inldpwl_drw.count()
 logger.info("inldpwl_drw has #{count} polygons")
 polygons_count += count
 
 polyres_drw = get_polygons(128, 0)
-polyres_drw = polyres_drw.not(nodrc_drw)
 count = polyres_drw.count()
 logger.info("polyres_drw has #{count} polygons")
 polygons_count += count
 
 polyres_pin = get_polygons(128, 2)
-polyres_pin = polyres_pin.not(nodrc_drw)
 count = polyres_pin.count()
 logger.info("polyres_pin has #{count} polygons")
 polygons_count += count
 
 vmim_drw = get_polygons(129, 0)
-vmim_drw = vmim_drw.not(nodrc_drw)
 count = vmim_drw.count()
 logger.info("vmim_drw has #{count} polygons")
 polygons_count += count
 
 nbulaycut_drw = get_polygons(131, 0)
-nbulaycut_drw = nbulaycut_drw.not(nodrc_drw)
 count = nbulaycut_drw.count()
 logger.info("nbulaycut_drw has #{count} polygons")
 polygons_count += count
 
 antmetal1_drw = get_polygons(132, 0)
-antmetal1_drw = antmetal1_drw.not(nodrc_drw)
 count = antmetal1_drw.count()
 logger.info("antmetal1_drw has #{count} polygons")
 polygons_count += count
 
 topvia2_drw = get_polygons(133, 0)
-topvia2_drw = topvia2_drw.not(nodrc_drw)
 count = topvia2_drw.count()
 logger.info("topvia2_drw has #{count} polygons")
 polygons_count += count
 
 topmetal2_drw = get_polygons(134, 0)
-topmetal2_drw = topmetal2_drw.not(nodrc_drw)
 count = topmetal2_drw.count()
 logger.info("topmetal2_drw has #{count} polygons")
 polygons_count += count
 
 topmetal2_filler = get_polygons(134, 22)
-topmetal2_filler = topmetal2_filler.not(nodrc_drw)
 count = topmetal2_filler.count()
 logger.info("topmetal2_filler has #{count} polygons")
 polygons_count += count
 
 topmetal2_slit = get_polygons(134, 24)
-topmetal2_slit = topmetal2_slit.not(nodrc_drw)
 count = topmetal2_slit.count()
 logger.info("topmetal2_slit has #{count} polygons")
 polygons_count += count
@@ -1445,409 +1213,341 @@ count = topmetal2.count()
 logger.info("topmetal2 has #{count} polygons")
 
 topmetal2_pin = get_polygons(134, 2)
-topmetal2_pin = topmetal2_pin.not(nodrc_drw)
 count = topmetal2_pin.count()
 logger.info("topmetal2_pin has #{count} polygons")
 polygons_count += count
 
 topmetal2_mask = get_polygons(134, 20)
-topmetal2_mask = topmetal2_mask.not(nodrc_drw)
 count = topmetal2_mask.count()
 logger.info("topmetal2_mask has #{count} polygons")
 polygons_count += count
 
 topmetal2_nofill = get_polygons(134, 23)
-topmetal2_nofill = topmetal2_nofill.not(nodrc_drw)
 count = topmetal2_nofill.count()
 logger.info("topmetal2_nofill has #{count} polygons")
 polygons_count += count
 
 topmetal2_text = labels(134, 25)
-topmetal2_text = topmetal2_text.not(nodrc_drw)
 count = topmetal2_text.count()
 logger.info("topmetal2_text has #{count} polygons")
 polygons_count += count
 
 topmetal2_noqrc = get_polygons(134, 28)
-topmetal2_noqrc = topmetal2_noqrc.not(nodrc_drw)
 count = topmetal2_noqrc.count()
 logger.info("topmetal2_noqrc has #{count} polygons")
 polygons_count += count
 
 topmetal2_res = get_polygons(134, 29)
-topmetal2_res = topmetal2_res.not(nodrc_drw)
 count = topmetal2_res.count()
 logger.info("topmetal2_res has #{count} polygons")
 polygons_count += count
 
 topmetal2_iprobe = get_polygons(134, 33)
-topmetal2_iprobe = topmetal2_iprobe.not(nodrc_drw)
 count = topmetal2_iprobe.count()
 logger.info("topmetal2_iprobe has #{count} polygons")
 polygons_count += count
 
 topmetal2_diffprb = get_polygons(134, 34)
-topmetal2_diffprb = topmetal2_diffprb.not(nodrc_drw)
 count = topmetal2_diffprb.count()
 logger.info("topmetal2_diffprb has #{count} polygons")
 polygons_count += count
 
 snsring_drw = get_polygons(135, 0)
-snsring_drw = snsring_drw.not(nodrc_drw)
 count = snsring_drw.count()
 logger.info("snsring_drw has #{count} polygons")
 polygons_count += count
 
 sensor_drw = get_polygons(136, 0)
-sensor_drw = sensor_drw.not(nodrc_drw)
 count = sensor_drw.count()
 logger.info("sensor_drw has #{count} polygons")
 polygons_count += count
 
 snsarms_drw = get_polygons(137, 0)
-snsarms_drw = snsarms_drw.not(nodrc_drw)
 count = snsarms_drw.count()
 logger.info("snsarms_drw has #{count} polygons")
 polygons_count += count
 
 snscmosvia_drw = get_polygons(138, 0)
-snscmosvia_drw = snscmosvia_drw.not(nodrc_drw)
 count = snscmosvia_drw.count()
 logger.info("snscmosvia_drw has #{count} polygons")
 polygons_count += count
 
 colwind_drw = get_polygons(139, 0)
-colwind_drw = colwind_drw.not(nodrc_drw)
 count = colwind_drw.count()
 logger.info("colwind_drw has #{count} polygons")
 polygons_count += count
 
 flm_drw  = get_polygons(142, 0)
-flm_drw = flm_drw.not(nodrc_drw)
 count = flm_drw.count()
 logger.info("flm_drw has #{count} polygons")
 polygons_count += count
 
 hafniumox_drw = get_polygons(143, 0)
-hafniumox_drw = hafniumox_drw.not(nodrc_drw)
 count = hafniumox_drw.count()
 logger.info("hafniumox_drw has #{count} polygons")
 polygons_count += count
 
 memvia_drw = get_polygons(145, 0)
-memvia_drw = memvia_drw.not(nodrc_drw)
 count = memvia_drw.count()
 logger.info("memvia_drw has #{count} polygons")
 polygons_count += count
 
 thinfilmres_drw = get_polygons(146, 0)
-thinfilmres_drw = thinfilmres_drw.not(nodrc_drw)
 count = thinfilmres_drw.count()
 logger.info("thinfilmres_drw has #{count} polygons")
 polygons_count += count
 
 rfmem_drw = get_polygons(147, 0)
-rfmem_drw = rfmem_drw.not(nodrc_drw)
 count = rfmem_drw.count()
 logger.info("rfmem_drw has #{count} polygons")
 polygons_count += count
 
 norcx_drw = get_polygons(148, 0)
-norcx_drw = norcx_drw.not(nodrc_drw)
 count = norcx_drw.count()
 logger.info("norcx_drw has #{count} polygons")
 polygons_count += count
 
 norcx_m2m3 = get_polygons(148, 41)
-norcx_m2m3 = norcx_m2m3.not(nodrc_drw)
 count = norcx_m2m3.count()
 logger.info("norcx_m2m3 has #{count} polygons")
 polygons_count += count
 
 norcx_m2m4 = get_polygons(148, 42)
-norcx_m2m4 = norcx_m2m4.not(nodrc_drw)
 count = norcx_m2m4.count()
 logger.info("norcx_m2m4 has #{count} polygons")
 polygons_count += count
 
 norcx_m2m5 = get_polygons(148, 43)
-norcx_m2m5 = norcx_m2m5.not(nodrc_drw)
 count = norcx_m2m5.count()
 logger.info("norcx_m2m5 has #{count} polygons")
 polygons_count += count
 
 norcx_m2tm1 = get_polygons(148, 44)
-norcx_m2tm1 = norcx_m2tm1.not(nodrc_drw)
 count = norcx_m2tm1.count()
 logger.info("norcx_m2tm1 has #{count} polygons")
 polygons_count += count
 
 norcx_m2tm2 = get_polygons(148, 45)
-norcx_m2tm2 = norcx_m2tm2.not(nodrc_drw)
 count = norcx_m2tm2.count()
 logger.info("norcx_m2tm2 has #{count} polygons")
 polygons_count += count
 
 norcx_m3m4 = get_polygons(148, 46)
-norcx_m3m4 = norcx_m3m4.not(nodrc_drw)
 count = norcx_m3m4.count()
 logger.info("norcx_m3m4 has #{count} polygons")
 polygons_count += count
 
 norcx_m3m5 = get_polygons(148, 47)
-norcx_m3m5 = norcx_m3m5.not(nodrc_drw)
 count = norcx_m3m5.count()
 logger.info("norcx_m3m5 has #{count} polygons")
 polygons_count += count
 
 norcx_m3tm1 = get_polygons(148, 48)
-norcx_m3tm1 = norcx_m3tm1.not(nodrc_drw)
 count = norcx_m3tm1.count()
 logger.info("norcx_m3tm1 has #{count} polygons")
 polygons_count += count
 
 norcx_m3tm2 = get_polygons(148, 49)
-norcx_m3tm2 = norcx_m3tm2.not(nodrc_drw)
 count = norcx_m3tm2.count()
 logger.info("norcx_m3tm2 has #{count} polygons")
 polygons_count += count
 
 norcx_m4m5 = get_polygons(148, 50)
-norcx_m4m5 = norcx_m4m5.not(nodrc_drw)
 count = norcx_m4m5.count()
 logger.info("norcx_m4m5 has #{count} polygons")
 polygons_count += count
 
 norcx_m4tm1 = get_polygons(148, 51)
-norcx_m4tm1 = norcx_m4tm1.not(nodrc_drw)
 count = norcx_m4tm1.count()
 logger.info("norcx_m4tm1 has #{count} polygons")
 polygons_count += count
 
 norcx_m4tm2 = get_polygons(148, 52)
-norcx_m4tm2 = norcx_m4tm2.not(nodrc_drw)
 count = norcx_m4tm2.count()
 logger.info("norcx_m4tm2 has #{count} polygons")
 polygons_count += count
 
 norcx_m5tm1 = get_polygons(148, 53)
-norcx_m5tm1 = norcx_m5tm1.not(nodrc_drw)
 count = norcx_m5tm1.count()
 logger.info("norcx_m5tm1 has #{count} polygons")
 polygons_count += count
 
 norcx_m5tm2 = get_polygons(148, 54)
-norcx_m5tm2 = norcx_m5tm2.not(nodrc_drw)
 count = norcx_m5tm2.count()
 logger.info("norcx_m5tm2 has #{count} polygons")
 polygons_count += count
 
 norcx_tm1tm2 = get_polygons(148, 55)
-norcx_tm1tm2 = norcx_tm1tm2.not(nodrc_drw)
 count = norcx_tm1tm2.count()
 logger.info("norcx_tm1tm2 has #{count} polygons")
 polygons_count += count
 
 norcx_m1sub = get_polygons(148, 123)
-norcx_m1sub = norcx_m1sub.not(nodrc_drw)
 count = norcx_m1sub.count()
 logger.info("norcx_m1sub has #{count} polygons")
 polygons_count += count
 
 norcx_m2sub = get_polygons(148, 124)
-norcx_m2sub = norcx_m2sub.not(nodrc_drw)
 count = norcx_m2sub.count()
 logger.info("norcx_m2sub has #{count} polygons")
 polygons_count += count
 
 norcx_m3sub = get_polygons(148, 125)
-norcx_m3sub = norcx_m3sub.not(nodrc_drw)
 count = norcx_m3sub.count()
 logger.info("norcx_m3sub has #{count} polygons")
 polygons_count += count
 
 norcx_m4sub = get_polygons(148, 126)
-norcx_m4sub = norcx_m4sub.not(nodrc_drw)
 count = norcx_m4sub.count()
 logger.info("norcx_m4sub has #{count} polygons")
 polygons_count += count
 
 norcx_m5sub = get_polygons(148, 127)
-norcx_m5sub = norcx_m5sub.not(nodrc_drw)
 count = norcx_m5sub.count()
 logger.info("norcx_m5sub has #{count} polygons")
 polygons_count += count
 
 norcx_tm1sub = get_polygons(148, 300)
-norcx_tm1sub = norcx_tm1sub.not(nodrc_drw)
 count = norcx_tm1sub.count()
 logger.info("norcx_tm1sub has #{count} polygons")
 polygons_count += count
 
 norcx_tm2sub = get_polygons(148, 301)
-norcx_tm2sub = norcx_tm2sub.not(nodrc_drw)
 count = norcx_tm2sub.count()
 logger.info("norcx_tm2sub has #{count} polygons")
 polygons_count += count
 
 snsbotvia_drw = get_polygons(149, 0)
-snsbotvia_drw = snsbotvia_drw.not(nodrc_drw)
 count = snsbotvia_drw.count()
 logger.info("snsbotvia_drw has #{count} polygons")
 polygons_count += count
 
 snstopvia_drw = get_polygons(151, 0)
-snstopvia_drw = snstopvia_drw.not(nodrc_drw)
 count = snstopvia_drw.count()
 logger.info("snstopvia_drw has #{count} polygons")
 polygons_count += count
 
 deepvia_drw = get_polygons(152, 0)
-deepvia_drw = deepvia_drw.not(nodrc_drw)
 count = deepvia_drw.count()
 logger.info("deepvia_drw has #{count} polygons")
 polygons_count += count
 
 fgetch_drw = get_polygons(153, 0)
-fgetch_drw = fgetch_drw.not(nodrc_drw)
 count = fgetch_drw.count()
 logger.info("fgetch_drw has #{count} polygons")
 polygons_count += count
 
 ctrgat_drw = get_polygons(154, 0)
-ctrgat_drw = ctrgat_drw.not(nodrc_drw)
 count = ctrgat_drw.count()
 logger.info("ctrgat_drw has #{count} polygons")
 polygons_count += count
 
 fgimp_drw = get_polygons(155, 0)
-fgimp_drw = fgimp_drw.not(nodrc_drw)
 count = fgimp_drw.count()
 logger.info("fgimp_drw has #{count} polygons")
 polygons_count += count
 
 emwihv_drw = get_polygons(156, 0)
-emwihv_drw = emwihv_drw.not(nodrc_drw)
 count = emwihv_drw.count()
 logger.info("emwihv_drw has #{count} polygons")
 polygons_count += count
 
 lbe_drw  = get_polygons(157, 0)
-lbe_drw = lbe_drw.not(nodrc_drw)
 count = lbe_drw.count()
 logger.info("lbe_drw has #{count} polygons")
 polygons_count += count
 
 alcustop_drw = get_polygons(159, 0)
-alcustop_drw = alcustop_drw.not(nodrc_drw)
 count = alcustop_drw.count()
 logger.info("alcustop_drw has #{count} polygons")
 polygons_count += count
 
 nometfiller_drw = get_polygons(160, 0)
-nometfiller_drw = nometfiller_drw.not(nodrc_drw)
 count = nometfiller_drw.count()
 logger.info("nometfiller_drw has #{count} polygons")
 polygons_count += count
 
 prboundary_drw = get_polygons(189, 0)
-prboundary_drw = prboundary_drw.not(nodrc_drw)
 count = prboundary_drw.count()
 logger.info("prboundary_drw has #{count} polygons")
 polygons_count += count
 
 exchange0_drw = get_polygons(190, 0)
-exchange0_drw = exchange0_drw.not(nodrc_drw)
 count = exchange0_drw.count()
 logger.info("exchange0_drw has #{count} polygons")
 polygons_count += count
 
 exchange0_pin = get_polygons(190, 2)
-exchange0_pin = exchange0_pin.not(nodrc_drw)
 count = exchange0_pin.count()
 logger.info("exchange0_pin has #{count} polygons")
 polygons_count += count
 
 exchange0_text = labels(190, 25)
-exchange0_text = exchange0_text.not(nodrc_drw)
 count = exchange0_text.count()
 logger.info("exchange0_text has #{count} polygons")
 polygons_count += count
 
 exchange1_drw = get_polygons(191, 0)
-exchange1_drw = exchange1_drw.not(nodrc_drw)
 count = exchange1_drw.count()
 logger.info("exchange1_drw has #{count} polygons")
 polygons_count += count
 
 exchange1_pin = get_polygons(191, 2)
-exchange1_pin = exchange1_pin.not(nodrc_drw)
 count = exchange1_pin.count()
 logger.info("exchange1_pin has #{count} polygons")
 polygons_count += count
 
 exchange1_text = labels(191, 25)
-exchange1_text = exchange1_text.not(nodrc_drw)
 count = exchange1_text.count()
 logger.info("exchange1_text has #{count} polygons")
 polygons_count += count
 
 exchange2_drw = get_polygons(192, 0)
-exchange2_drw = exchange2_drw.not(nodrc_drw)
 count = exchange2_drw.count()
 logger.info("exchange2_drw has #{count} polygons")
 polygons_count += count
 
 exchange2_pin = get_polygons(192, 2)
-exchange2_pin = exchange2_pin.not(nodrc_drw)
 count = exchange2_pin.count()
 logger.info("exchange2_pin has #{count} polygons")
 polygons_count += count
 
 exchange2_text = labels(192, 25)
-exchange2_text = exchange2_text.not(nodrc_drw)
 count = exchange2_text.count()
 logger.info("exchange2_text has #{count} polygons")
 polygons_count += count
 
 exchange3_drw = get_polygons(193, 0)
-exchange3_drw = exchange3_drw.not(nodrc_drw)
 count = exchange3_drw.count()
 logger.info("exchange3_drw has #{count} polygons")
 polygons_count += count
 
 exchange3_pin = get_polygons(193, 2)
-exchange3_pin = exchange3_pin.not(nodrc_drw)
 count = exchange3_pin.count()
 logger.info("exchange3_pin has #{count} polygons")
 polygons_count += count
 
 exchange3_text = labels(193, 25)
-exchange3_text = exchange3_text.not(nodrc_drw)
 count = exchange3_text.count()
 logger.info("exchange3_text has #{count} polygons")
 polygons_count += count
 
 exchange4_drw = get_polygons(194, 0)
-exchange4_drw = exchange4_drw.not(nodrc_drw)
 count = exchange4_drw.count()
 logger.info("exchange4_drw has #{count} polygons")
 polygons_count += count
 
 exchange4_pin = get_polygons(194, 2)
-exchange4_pin = exchange4_pin.not(nodrc_drw)
 count = exchange4_pin.count()
 logger.info("exchange4_pin has #{count} polygons")
 polygons_count += count
 
 exchange4_text = labels(194, 25)
-exchange4_text = exchange4_text.not(nodrc_drw)
 count = exchange4_text.count()
 logger.info("exchange4_text has #{count} polygons")
 polygons_count += count
 
 isonwell_drw = get_polygons(257, 0)
-isonwell_drw = isonwell_drw.not(nodrc_drw)
 count = isonwell_drw.count()
 logger.info("isonwell_drw has #{count} polygons")
 polygons_count += count
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/tap_extraction.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/tap_extraction.lvs
index d6cc82db..aab8d7d4 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/tap_extraction.lvs
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/tap_extraction.lvs
@@ -18,7 +18,7 @@
 #==========================================================================
 
 #================================
-# ------ EFUSE EXTRACTIONS ------
+# ------- TAPS EXTRACTIONS ------
 #================================
 
 logger.info('Starting Taps EXTRACTION')
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/sg13g2_full.lylvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/sg13g2_full.lylvs
new file mode 100644
index 00000000..7b7b4b27
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/sg13g2_full.lylvs
@@ -0,0 +1,4687 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!--
+#==========================================================================
+# Copyright 2024 IHP PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#    https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+#==========================================================================
+
+# For batch mode run:
+
+  ## klayout -b -r sg13g2_full.lylvs -rd in_gds=<layout_path> -rd cdl_file=<schematic_path> -rd report_file=<report_path> -rd target_netlist=<extracted_netlist_path> <options> 
+
+  ## Example : klayout -b -r sg13g2_full.lylvs -rd in_gds=sg13_lv_nmos.gds -rd cdl_file=sg13_lv_nmos.cdl -rd report_file=sg13_lv_nmos.lvsdb -rd target_netlist=sg13_lv_nmos_extracted.cir -rd run_mode=deep -rd no_net_names=false -rd spice_comments=false -rd net_only=false -rd top_lvl_pins=false -rd no_simplify=false -rd no_series_res=false -rd no_parallel_res=false -rd combine_devices=false -rd purge=false -rd purge_nets=false -rd verbose=false -rd topcell=sg13_lv_nmos
+
+-->
+
+<klayout-macro>
+ <description>Run Klayout LVS</description>
+ <version>0.1</version>
+ <category>lvs</category>
+ <prolog/>
+ <epilog/>
+ <doc/>
+ <autorun>false</autorun>
+ <autorun-early>false</autorun-early>
+ <priority>0</priority>
+ <shortcut/>
+ <show-in-menu>true</show-in-menu>
+ <group-name>Run Klayout LVS</group-name>
+ <menu-path>tools_menu.lvs.end</menu-path>
+ <interpreter>dsl</interpreter>
+ <dsl-interpreter-name>lvs-dsl-xml</dsl-interpreter-name>
+ <text>
+ <![CDATA[
+#===========================================================================================================
+# ------------------------------------------ SG13G2 LVS RULE DECK ------------------------------------------
+#===========================================================================================================
+
+require 'time'
+require 'logger'
+require 'etc'
+
+exec_start_time = Time.now
+
+logger = Logger.new($stdout)
+
+def get_memory_usage
+  if Gem.win_platform?
+    # Cross-platform memory usage retrieval
+    require 'win32ole'
+    wmi = WIN32OLE.connect("winmgmts://")
+    processes = wmi.ExecQuery("select * from Win32_Process where ProcessId = #{Process.pid}")
+    process = processes.each.next # Get the first result
+    "#{process.WorkingSetSize.to_i / 1024} KB"
+  else
+    `ps -o rss= -p #{Process.pid}`.strip + " KB"
+  end
+end
+
+logger.formatter = proc do |_severity, datetime, _progname, msg|
+  "#{datetime}: Memory Usage (" + get_memory_usage + ") : #{msg}\n"
+end
+
+#================================================
+#----------------- FILE SETUP -------------------
+#================================================
+
+logger.info("Starting running SG13G2 Klayout LVS runset on #{$in_gds}")
+logger.info("Ruby Version for klayout: #{RUBY_VERSION}")
+
+if $in_gds
+  if $topcell
+    source($in_gds, $topcell)
+  else
+    source($in_gds)
+  end
+end
+
+logger.info('Loading database to memory is complete.')
+
+if $report_file
+  logger.info("SG13G2 Klayout LVS runset output at: #{$report_file}")
+  report_lvs($report_file)
+else
+  layout_dir = Pathname.new(RBA::CellView.active.filename).parent.realpath
+  report_path = layout_dir.join("#{source.cell_name}.lvsdb").to_s
+  logger.info("SG13G2 Klayout LVS runset output at default location: #{source.cell_name}.lvsdb")
+  report_lvs($report_path)
+end
+
+#================================================
+#------------------ SWITCHES --------------------
+#================================================
+
+logger.info('Evaluate switches.')
+
+def bool_check?(obj)
+  obj.to_s.downcase == 'true'
+end
+
+#=== NET NAMES OPTION ===
+# true: use net names instead of numbers
+# false: use numbers for nets
+SPICE_WITH_NET_NAMES = !bool_check?($no_net_names)
+
+logger.info("Extracted netlist with net names: #{SPICE_WITH_NET_NAMES}")
+
+#=== COMMENTS OPTION ===
+# true: put in comments with details
+# false: no comments
+SPICE_WITH_COMMENTS = bool_check?($spice_comments)
+
+logger.info("Extracted netlist with comments in details: #{SPICE_WITH_COMMENTS}")
+
+# NET_ONLY
+NET_ONLY = bool_check?($net_only)
+
+logger.info("Selected NET_ONLY option: #{NET_ONLY}")
+
+# TOP_LVL_PINS
+TOP_LVL_PINS = bool_check?($top_lvl_pins)
+
+logger.info("Selected TOP_LVL_PINS option: #{TOP_LVL_PINS}")
+
+# COMBINE
+COMBINE_DEVICES = bool_check?($combine_devices)
+
+logger.info("Selected COMBINE DEVICES option: #{COMBINE_DEVICES}")
+
+# PURGE
+PURGE = bool_check?($purge)
+
+logger.info("Selected PURGE option: #{PURGE}")
+
+# PURGE_NETS
+PURGE_NETS = bool_check?($purge_nets)
+
+logger.info("Selected PURGE_NETS option: #{PURGE_NETS}")
+
+# SIMPLIFY
+SIMPLIFY = !bool_check?($no_simplify)
+
+logger.info("Selected SIMPLIFY option: #{SIMPLIFY}")
+
+# SIMPLIFY
+SERIES_RES = !bool_check?($no_series_res)
+
+logger.info("Selected SERIES_RES option: #{SERIES_RES}")
+
+# SIMPLIFY
+PARALLEL_RES = !bool_check?($no_parallel_res)
+
+logger.info("Selected PARALLEL_RES option: #{PARALLEL_RES}")
+
+#=== PRINT DETAILS ===
+logger.info("Verbose mode: #{$verbose}")
+if $verbose == 'true'
+  verbose(true)
+else
+  verbose(false)
+end
+
+# === RUN MODE ===
+case $run_mode
+when 'deep'
+  #=== HIER MODE ===
+  deep
+  logger.info('deep  mode is enabled.')
+else
+  #=== FLAT MODE ===
+  flat
+  logger.info('flat  mode is enabled.')
+end
+
+# === Tech Switches ===
+
+#================================================
+# --------------- CUSTOM CLASSES ----------------
+#================================================
+
+$logger = logger
+$unit = dbu
+
+#=============== UTILS ===============
+# Method to convert glob pattern to a case-insensitive glob-style pattern
+def glob_to_case_insensitive_glob(glob)
+  wildcards = ['*', '?']
+
+  pattern = glob.chars.map do |c|
+    if c =~ /[A-Za-z]/
+      "[#{c.upcase}#{c.downcase}]"
+    elsif wildcards.include?(c)
+      c  # Keep wildcard characters as they are
+    else
+      Regexp.escape(c)
+    end
+  end.join
+  
+  pattern
+end
+
+#================================================
+# ---------------- CUSTOM READER ----------------
+#================================================
+
+# Custom reader for subcircuit models
+class CustomReader < RBA::NetlistSpiceReaderDelegate
+  # Cleanup sch for R, C elements
+  def clean_sch(line, element)
+    # Extracting parameters with values
+    valid_params = line.scan(/\b\w+\s*=\s*\S+\b/)
+
+    case element
+    when 'R'
+      # For 2 term res [<nets> <model> <params>]
+      num_terms = 3
+    when 'C'
+      # Determine number of terms based on component type
+      num_terms =
+        if line.downcase.include?('varicap')
+          5
+        elsif line.downcase.include?('rfcmim')
+          4
+        else
+          3
+        end
+    end
+    line_no_param = line.split(' ').take(num_terms).join(' ')
+    "#{line_no_param.strip} #{valid_params.join(' ')}"
+  end
+
+  # Override parse_element method to handle exceptions gracefully
+  def parse_element(line, element)
+    # clean line
+    line = line.delete('[]$\\/')
+
+    # Prep sch for R, C
+    line = clean_sch(line, element) if %w[R C].include?(element)
+
+    super
+  rescue StandardError
+    case element
+    when 'C'
+      if line.downcase.include?('varicap')
+        super(line.to_s, 'M')
+      elsif line.downcase.include?('rfcmim')
+        super(line.to_s, 'Q')
+      else
+        super("#{line} C=1e-18", element)
+      end
+    when 'R'
+      super("#{line} R=0", element)
+    when 'D'
+      if line.downcase.include?('diodev') || line.downcase.include?('schottky')
+        super(line.to_s, 'Q')
+      else
+        super(line.to_s, element)
+      end
+    when 'L'
+      if line.downcase.include?('inductor3')
+        super("#{line} L=0", 'M')
+      else
+        super("#{line} L=0", element)
+      end
+    else
+      super
+    end
+  end
+
+  # Override the element method to handle different types of elements
+  def element(circuit, ele, name, model, value, nets, params)
+    if CUSTOM_READER.include?(ele)
+      process_device(ele, circuit, name, model, nets, params)
+    else
+      super
+    end
+    true
+  end
+
+  private
+
+  # Process device element
+  def process_device(ele, circuit, name, model, nets, params)
+    cls = circuit.netlist.device_class_by_name(model)
+    cls ||= create_device_class(ele, circuit, model, nets.size)
+
+    device = circuit.create_device(cls, name)
+    connect_terminals(ele, device, model, nets)
+    map_params(ele, device, model, params)
+  end
+
+  # Create or retrieve the device class based on the element type, model name, and number of nets.
+  #
+  # @param ele [String] The type of element (C, R, Q, L).
+  # @param circuit [Circuit] The circuit object to which the device class will be added.
+  # @param model [String] The model name of the device class.
+  # @param num_nets [Integer] The number of nets the device class should have.
+  # @return [RBA::DeviceClass] The created or retrieved device class.
+  def create_device_class(ele, circuit, model, num_nets)
+    cls = case ele
+          when 'M' then RBA::DeviceClassMOS4Transistor.new
+          when 'C' then create_capacitor(model, num_nets)
+          when 'R' then create_resistor(model, num_nets)
+          when 'Q' then create_bjt(model, num_nets)
+          when 'L' then DeviceCustomInd.new(model, num_nets - 1)
+          when 'D' then create_diode(model)
+          else
+            return super
+          end
+
+    cls.name = model
+    circuit.netlist.add(cls)
+    cls
+  end
+
+  # Create a capacitor device class.
+  def create_capacitor(model, num_nets)
+    if model.downcase.include?('varicap')
+      raise ArgumentError, 'Varicap should have 4 nodes, please recheck' unless num_nets == 4
+
+      DeviceCustomVaractor.new(model, num_nets - 1)
+    else
+      raise ArgumentError, 'Capacitor should have 2 or 3 nodes, please recheck' unless [2, 3].include?(num_nets)
+
+      DeviceCustomMIM.new(model)
+
+    end
+  end
+
+  # Create a diode device class.
+  def create_diode(model)
+    if model.downcase.include?('diodev') || model.downcase.include?('schottky')
+      Esd3Term.new
+    elsif model.downcase.include?('nmoscl')
+      Esd2Term.new
+    else
+      EnDiode.new
+    end
+  end
+
+  # Create a resistor device class.
+  def create_resistor(model, num_nets)
+    if RES_DEV.any? { |res| model.downcase.start_with?(res) }
+      DeviceCustomRes.new(model, num_nets)
+    elsif num_nets == 2 && model.downcase.include?('tap')
+      RBA::DeviceClassDiode.new
+    elsif num_nets == 2
+      RBA::DeviceClassResistor.new
+    elsif num_nets == 3
+      RBA::DeviceClassResistorWithBulk.new
+    else
+      raise ArgumentError, 'Resistor should have two or three nodes, please recheck'
+    end
+  end
+
+  # Create a bjt device class.
+  def create_bjt(model, _num_nets)
+    if model.downcase.include?('pnp')
+      CustomBJT3.new
+    else
+      CustomBJT4.new
+    end
+  end
+
+  # Connect device terminals based on element type, device, model, and nets.
+  #
+  # @param ele [String] The type of element (C, R, Q).
+  # @param device [RBA::Device] The device object to which terminals will be connected.
+  # @param model [String] The model name of the device.
+  # @param nets [Array<String>] Array of net names to which terminals will be connected.
+  def connect_terminals(ele, device, model, nets)
+    term_list = terminal_list_for_element(ele, model, nets)
+
+    term_list.each_with_index do |t, index|
+      device.connect_terminal(t, nets[index])
+    end
+  end
+
+  # Determine terminal list based on element type, model, and nets.
+  def terminal_list_for_element(ele, model, nets)
+    case ele
+    when 'M'
+      %w[D G S B]
+    when 'Q'
+      model.downcase.include?('pnp') ? %w[C B E] : %w[C B E S]
+    when 'C'
+      model.downcase.include?('varicap') ? gen_term_with_sub(model, nets.size) : gen_mim_terms(model)
+    when 'R'
+      if RES_DEV.any? { |res| model.downcase.start_with?(res) }
+        gen_term_names(model, nets.size)
+      elsif model.downcase.include?('tap')
+        %w[C A]
+      else
+        nets.size == 3 ? %w[A B W] : %w[A B]
+      end
+    when 'D'
+      if model.downcase.include?('diodevdd')
+        %w[B E C]
+      elsif model.downcase.include?('diodevss')
+        %w[C E B]
+      elsif model.downcase.include?('schottky')
+        %w[E B C]
+      elsif model.downcase.include?('nmoscl')
+        %w[C A]
+      else
+        %w[A C]
+      end
+    when 'L'
+      gen_term_with_sub(model, nets.size)
+    else
+      gen_term_names(model, nets.size)
+    end
+  end
+
+  # Generate terminal names based on model and the number of nets.
+  def gen_term_names(model, size)
+    (0...size).map { |i| "#{model}_#{i + 1}" }
+  end
+
+  # Generate terminal names based on model and the number of nets.
+  def gen_mim_terms(model)
+    terms = %w[mim_top mim_btm]
+
+    return terms unless model.downcase.include?('rfcmim')
+
+    terms << 'mim_sub' # Add sub terminal
+    terms
+  end
+
+  # Generate terminal names based on model and the number of nets.
+  def gen_term_with_sub(model, size)
+    terms = (0...size - 1).map { |i| "#{model}_#{i + 1}" }
+    terms << "#{model}_sub" # Add sub terminal
+  end
+
+  # Map parameters based on the model type.
+  #
+  # @param ele [String] The type of element (M, C, R, Q, L, D).
+  # @param device [RBA::Device] The device object to which parameters will be mapped.
+  # @param model [String] The model name of the device.
+  # @param params [Hash] Hash containing parameter values.
+  def map_params(ele, device, model, params)
+    case ele
+    when 'M'
+      map_mos_params(device, params)
+    when 'Q'
+      map_bjt_params(device, model, params)
+    when 'C'
+      map_capacitor_params(device, model, params)
+    when 'R'
+      map_resistor_params(device, model, params)
+    when 'D'
+      map_diode_params(device, model, params)
+    when 'L'
+      map_inductor_params(device, params)
+    else
+      raise ArgumentError, "#{ele} device with model #{model} is not supported, please recheck"
+    end
+  end
+
+  # Map parameters for mos devices.
+  def map_mos_params(device, params)
+    device.set_parameter('W', (params['W'] || 0.0) * (params['M'] || 1.0) * 1e6)
+    device.set_parameter('L', (params['L'] || 0.0) * 1e6)
+  end
+
+  # Map parameters for a BJT device.
+  def map_bjt_params(device, model, params)
+    if model.downcase.include?('pnp')
+      device.set_parameter('AE', (params['A'] || ((params['W'] || 0.0) * (params['L'] || 0.0))) * 1e12)
+      device.set_parameter('PE', (params['P'] || (((params['W'] || 0.0) + (params['L'] || 0.0)) * 2)) * 1e6)
+    else
+      device.set_parameter('AE', (params['AE'] || ((params['WE'] || 0.0) * (params['LE'] || 0.0))) * 1e12)
+      device.set_parameter('PE', (params['PE'] || (((params['WE'] || 0.0) + (params['LE'] || 0.0)) * 2)) * 1e6)
+    end
+    device.set_parameter('NE', params['M'] || params['NE'] || 1.0)
+    device.set_parameter('m',  params['M'] || params['NE'] || 1.0)
+  end
+
+  # Map parameters for a diode device.
+  def map_diode_params(device, model, params)
+    unless model.downcase.include?('diodev') || model.downcase.include?('schottky') || model.downcase.include?('nmoscl')
+      device.set_parameter('A', (params['A'] || ((params['W'] || 0.0) * (params['L'] || 0.0))) * 1e12)
+      device.set_parameter('P', (params['P'] || (((params['W'] || 0.0) + (params['L'] || 0.0)) * 2)) * 1e6)
+    end
+    device.set_parameter('m', params['M'] || 1.0)
+  end
+
+  # Map parameters for a capacitor device.
+  def map_capacitor_params(device, model, params)
+    device.set_parameter('w', (params['W'] || 0.0) * 1e6)
+    device.set_parameter('l', (params['L'] || 0.0) * 1e6)
+    device.set_parameter('m', params['M'] || params['MF'] || 1.0) if model.downcase.include?('cap_cmim')
+
+    if model.downcase.include?('mim')
+      device.set_parameter('A', (params['A'] || ((params['W'] || 0.0) * (params['L'] || 0.0))) * 1e12)
+      device.set_parameter('P', (params['P'] || (((params['W'] || 0.0) + (params['L'] || 0.0)) * 2)) * 1e6)
+    end
+    return unless model.downcase.include?('rfcmim')
+
+    device.set_parameter('wfeed', (params['WFEED'] || 0.0) * 1e6)
+  end
+
+  # Map parameters for a resistor device.
+  def map_resistor_params(device, model, params)
+    if model.downcase.include?('tap')
+      device.set_parameter('A', (params['A'] || ((params['W'] || 0.0) * (params['L'] || 0.0))) * 1e12)
+      device.set_parameter('P',
+                           (params['P'] || params['PERIM'] || (((params['W'] || 0.0) + (params['L'] || 0.0)) * 2)) * 1e6)
+    elsif RES_DEV.any? { |res| model.downcase.start_with?(res) }
+      device.set_parameter('w', (params['W'] || 0.0) * 1e6)
+      device.set_parameter('l', (params['L'] || 0.0) * 1e6)
+      device.set_parameter('ps', (params['PS'] || 0.0) * 1e6)
+      device.set_parameter('b', params['B'] || 0.0)
+      device.set_parameter('m', params['M'] || 1.0)
+    else
+      device.set_parameter('W', (params['W'] || params['WIDTH'] || 0.0) * (params['M'] || 1.0) * 1e6)
+      device.set_parameter('L', (params['L'] || params['LENGTH'] || 0.0) * (params['S'] || 1.0) * 1e6)
+      device.set_parameter('R', (params['R'] || 0.0) * (params['S'] || 1.0) / (params['M'] || 1.0))
+    end
+  end
+
+  # Map parameters for an inductor device.
+  def map_inductor_params(device, params)
+    device.set_parameter('w', (params['W'] || 0.0) * 1e6)
+    device.set_parameter('s', (params['S'] || 0.0) * 1e6)
+    device.set_parameter('d', (params['D'] || 0.0) * 1e6)
+    device.set_parameter('nr_r', params['NR_R'] || 0.0)
+  end
+end
+
+#================================================
+# ---------------- CUSTOM WRITER ----------------
+#================================================
+
+#==============================
+# --------- Varaibles ---------
+#==============================
+
+# Prefix for each device
+PREFIX_MAP = {
+  'sg13_lv_nmos' => 'M',
+  'sg13_hv_nmos' => 'M',
+  'sg13_lv_pmos' => 'M',
+  'sg13_hv_pmos' => 'M',
+  'rfnmos' => 'M',
+  'rfnmosHV' => 'M',
+  'rfpmos' => 'M',
+  'rfpmosHV' => 'M',
+  'npn13G2' => 'Q',
+  'npn13G2L' => 'Q',
+  'npn13G2V' => 'Q',
+  'pnpMPA' => 'Q',
+  'dantenna' => 'D',
+  'dpantenna' => 'D',
+  'schottky_nbl1' => 'D',
+  'rsil' => 'R',
+  'rppd' => 'R',
+  'rhigh' => 'R',
+  'lvsres' => 'R',
+  'SVaricap' => 'C',
+  'cap_cmim' => 'C',
+  'rfcmim' => 'C',
+  'diodevss_4kv' => 'D',
+  'diodevss_2kv' => 'D',
+  'diodevdd_4kv' => 'D',
+  'diodevdd_2kv' => 'D',
+  'idiodevss_4kv' => 'D',
+  'idiodevss_2kv' => 'D',
+  'idiodevdd_4kv' => 'D',
+  'idiodevdd_2kv' => 'D',
+  'nmoscl_2' => 'D',
+  'nmoscl_4' => 'D',
+  'ptap1' => 'R',
+  'ntap1' => 'R',
+  'inductor2' => 'L',
+  'inductor3' => 'L'
+}.freeze
+
+# Prefix for devices will be customized
+CUSTOM_READER = %w[M C R Q L D].freeze
+
+# List of poly-resistors
+RES_DEV = ['rsil', 'rppd', 'rhigh']
+
+# Custom writer for SPICE netlists
+class CustomWriter < RBA::NetlistSpiceWriterDelegate
+  # Write device to SPICE format
+  # @param device [RBA::Device] The device to be written
+  def write_device(device)
+    device_class = device.device_class
+    str = generate_device_prefix(device, device_class)
+    str += generate_device_terminals(device, device_class)
+    str += "#{device_class.name} "
+    str += generate_default_parameters(device, device_class)
+    emit_line(str)
+  end
+
+  private
+
+  # Generate device prefix using the global prefix map
+  def generate_device_prefix(device, device_class)
+    prefix = PREFIX_MAP[device_class.name] || device.id.to_s
+    "#{prefix}#{device.expanded_name} "
+  end
+
+  # Generate device terminals
+  def generate_device_terminals(device, device_class)
+    terminals = device_class.terminal_definitions.map do |td|
+      net_to_string(device.net_for_terminal(td.id))
+    end
+    "#{terminals.join(' ')} "
+  end
+
+  # Determine the unit for each parameter
+  def get_unit(key)
+    case key
+    when 'W', 'L', 'w', 'wfeed', 'l', 's', 'd', 'ps'
+      'u'  # micrometers
+    when 'AS', 'AD', 'AE', 'AB', 'AC', 'A'
+      'p'  # picometers (these are areas um^2)
+    when 'PS', 'PD', 'PE', 'PB', 'PC', 'P', 'Perim'
+      'u'  # micrometers (perimeters)
+    else
+      ''  # no unit
+    end
+  end
+
+  # Generate default parameters for the device
+  def generate_default_parameters(device, device_class)
+    parameters = device_class.parameter_definitions.map do |pd|
+      unit = get_unit(pd.name)
+      value = device.parameter(pd.id)
+      if value && value > 0
+        format('%<name>s=%<value>.12g%<unit>s', name: pd.name, value: value, unit: unit)
+      elsif value
+        format('%<name>s=%<value>.12g', name: pd.name, value: value)
+      end
+    end
+    # Use compact to remove any nil values
+    parameters.compact.join(' ')
+  end
+end
+
+#================================================
+# --------------- CUSTOM DEVICES ----------------
+#================================================
+
+# common methods
+module DeviceClassMethods
+  private
+
+  def add_parameters(*names)
+    names.each { |name| add_parameter(RBA::DeviceParameterDefinition.new(name)) }
+  end
+
+  def add_terminals(name, num, sub_en)
+    (1..num).each do |i|
+      terminal_name = "#{name}_#{i}"
+      ter = add_terminal(RBA::DeviceTerminalDefinition.new(terminal_name))
+      ter.name = terminal_name
+    end
+    return unless sub_en == 1
+
+    terminal_name = "#{name}_sub"
+    ter = add_terminal(RBA::DeviceTerminalDefinition.new(terminal_name))
+    ter.name = terminal_name
+  end
+end
+
+# res-custom device calss
+class DeviceCustomRes < RBA::DeviceClassResistor
+  include DeviceClassMethods
+
+  def initialize(name, num)
+    # clear terminals and parameters of resistor class
+    clear_parameters
+    clear_terminals
+
+    add_parameters('w', 'l', 'ps', 'b')
+    add_parameter(RBA::DeviceParameterDefinition.new('m', 'multiplier', 1, true))
+
+    if SERIES_RES || PARALLEL_RES
+      self.combiner = RESDeviceCombiner.new
+    else
+      self.combiner =nil
+    end
+
+    add_terminals(name, num, 0)
+  end
+end
+
+# BJT-3term device calss
+class CustomBJT3 < RBA::DeviceClassBJT3Transistor
+
+  def initialize
+    super
+    add_parameter(RBA::DeviceParameterDefinition.new('m', 'multiplier', 1, true))
+    self.combiner = BJTDeviceCombiner.new
+
+    enable_parameter('AE', true)
+    enable_parameter('PE', true)
+    enable_parameter('NE', true)
+  end
+end
+
+# BJT-4term device calss
+class CustomBJT4 < RBA::DeviceClassBJT4Transistor
+  include DeviceClassMethods
+
+  def initialize
+    super
+    add_parameter(RBA::DeviceParameterDefinition.new('m', 'multiplier', 1, true))
+    self.combiner = BJTDeviceCombiner.new
+
+    enable_parameter('AE', true)
+    enable_parameter('PE', true)
+    enable_parameter('NE', true)
+  end
+end
+
+# inductor device calss
+class DeviceCustomInd < RBA::DeviceClassInductor
+  include DeviceClassMethods
+
+  def initialize(name, num)
+    # clear terminals and parameters of class
+    clear_parameters
+    clear_terminals
+    clear_equivalent_terminal_ids
+
+    add_parameters('w', 's', 'd', 'nr_r')
+    add_terminals(name, num, 1)
+
+    # 5% tolerance for w,s,d:
+    equal_ind_parameters = RBA::EqualDeviceParameters::new(parameter_id('w'), 0.0, 0.05)
+    equal_ind_parameters += RBA::EqualDeviceParameters::new(parameter_id('s'), 0.0, 0.05)
+    equal_ind_parameters += RBA::EqualDeviceParameters::new(parameter_id('d'), 0.0, 0.05)
+    # applies the compare delegate:
+    self.equal_parameters = equal_ind_parameters
+
+    self.combiner = nil
+    self.supports_serial_combination=false
+    self.supports_parallel_combination=false
+  end
+end
+
+# Varactor-custom device calss
+class DeviceCustomVaractor < RBA::DeviceClassCapacitorWithBulk
+  include DeviceClassMethods
+
+  def initialize(name, num)
+    # clear terminals and parameters of resistor class
+    clear_parameters
+    clear_terminals
+
+    add_parameters('w', 'l')
+    add_terminals(name, num, 1)
+  end
+end
+
+# res-2term device calss
+class RES2 < RBA::DeviceClassResistor
+  def initialize
+    super
+    enable_parameter('W', true)
+    enable_parameter('L', true)
+    enable_parameter('R', false)
+  end
+end
+
+# Diode device class
+class EnDiode < RBA::DeviceClassDiode
+  def initialize
+    
+    # 1% tolerance for A,P:
+    equal_diode_parameters = RBA::EqualDeviceParameters::new(parameter_id('A'), 0.0, 0.01)
+    equal_diode_parameters += RBA::EqualDeviceParameters::new(parameter_id('P'), 0.0, 0.01)
+    # applies the compare delegate:
+    self.equal_parameters = equal_diode_parameters
+
+    # combiner
+    self.combiner = DiodeDeviceCombiner.new
+    self.supports_serial_combination=true
+    self.supports_parallel_combination=true
+
+    add_parameter(RBA::DeviceParameterDefinition.new('m', 'multiplier', 1, true))
+    enable_parameter('A', true)
+    enable_parameter('P', true)
+    enable_parameter('m', true)
+  end
+end
+
+# schottky device class
+class CustomSchottky < RBA::DeviceClassBJT3Transistor
+  def initialize
+    super
+    clear_parameters
+    add_parameter(RBA::DeviceParameterDefinition.new('m', 'multiplier', 1, true))
+
+    self.combiner = SchottckyDeviceCombiner.new
+  end
+end
+
+# Taps device class
+class CustomTap < RBA::DeviceClassDiode
+  def initialize
+    super
+    clear_parameters
+    add_parameter(RBA::DeviceParameterDefinition.new('A', 'Area', 0, true))
+    add_parameter(RBA::DeviceParameterDefinition.new('P', 'Perimeter', 0, true))
+    enable_parameter('A', true)
+    enable_parameter('P', true)
+  end
+end
+
+# ESD-3term device class
+class Esd3Term < RBA::DeviceClassBJT3Transistor
+  def initialize
+    super
+    clear_parameters
+    add_parameter(RBA::DeviceParameterDefinition.new('m', 'area', 1, true))
+    enable_parameter('m', true)
+  end
+end
+
+# ESD-2term device class
+class Esd2Term < RBA::DeviceClassDiode
+  def initialize
+    super
+    clear_parameters
+    add_parameter(RBA::DeviceParameterDefinition.new('m', 'area', 1, true))
+    enable_parameter('m', true)
+  end
+end
+
+#================================================
+# -------------- CUSTOM COMBINER ----------------
+#================================================
+
+# common methods
+module DeviceCombinerMethods
+  private
+
+  # A helper function to check whether two nets are the same
+  def same_net(a, b, name)
+    a_net = a.net_for_terminal(name)
+    b_net = b.net_for_terminal(name)
+
+    # same polarity
+    same_po = a_net.expanded_name == b_net.expanded_name if a_net && b_net
+    a_net && b_net && same_po
+  end
+
+  # A helper function to check whether two device connected in parallel
+  def supp_parallel(a, b, net1, net2)
+    a_net1 = a.net_for_terminal(net1)
+    a_net2 = a.net_for_terminal(net2)
+    b_net1 = b.net_for_terminal(net1)
+    b_net2 = b.net_for_terminal(net2)
+
+    return false unless a_net1 && b_net1 && a_net2 && b_net2
+
+    same_po = a_net1.expanded_name == b_net1.expanded_name && a_net2.expanded_name == b_net2.expanded_name
+    diff_po = a_net1.expanded_name == b_net2.expanded_name && a_net2.expanded_name == b_net1.expanded_name
+
+    same_po || diff_po
+  end
+
+  # A helper function to check whether two device connected in series
+  def supp_series(a, b, net1, net2)
+    a_net1 = a.net_for_terminal(net1)
+    a_net2 = a.net_for_terminal(net2)
+    b_net1 = b.net_for_terminal(net1)
+    b_net2 = b.net_for_terminal(net2)
+
+    return false unless a_net1 && b_net1 && a_net2 && b_net2
+
+    series_con_a1 = a_net1.expanded_name == b_net1.expanded_name || a_net1.expanded_name == b_net2.expanded_name
+    series_con_a2 = a_net2.expanded_name == b_net1.expanded_name || a_net2.expanded_name == b_net2.expanded_name
+    series_con = series_con_a1 || series_con_a2
+
+    # Reroute terminal connections based on cluster IDs
+    if series_con_a1
+      if a_net1.expanded_name == b_net1.expanded_name
+        a.connect_terminal(0, b_net2)
+      else
+        a.connect_terminal(0, b_net1)
+      end
+    end
+
+    if series_con_a2
+      if a_net2.expanded_name == b_net1.expanded_name
+        a.connect_terminal(1, b_net2)
+      else
+        a.connect_terminal(1, b_net1)
+      end
+    end
+
+    series_con
+  end
+
+  # A helper function to check whether two parameters have approximately the same value
+  def same_parameter(a, b, name)
+    (a.parameter(name) - b.parameter(name)).abs < 1e-9
+  end
+end
+
+class MIMCAPNDeviceCombiner < RBA::GenericDeviceCombiner
+  include DeviceCombinerMethods
+
+  # Method to check and perform device combination
+  def combine_devices(a, b)
+    # Check if both devices have the same net
+    return false unless same_net(a, b, 'mim_top') && same_net(a, b, 'mim_btm')
+
+    # Check if parameters are the same
+    return false unless same_parameter(a, b, 'w') && same_parameter(a, b, 'l')
+
+    # Combine by summing up 'm' parameter
+    a.set_parameter('m', a.parameter('m') + b.parameter('m'))
+
+    # Disconnect the second device and let the system clean it up
+    b.disconnect_terminal('mim_top')
+    b.disconnect_terminal('mim_btm')
+
+    # Disconnect mim_sub terminal if present and model name includes 'rfcmim'
+    b.disconnect_terminal('mim_sub') if b.name.downcase.include?('rfcmim')
+
+    true
+  end
+end
+
+class DiodeDeviceCombiner < RBA::GenericDeviceCombiner
+  include DeviceCombinerMethods
+
+  # Method to check and perform device combination
+  def combine_devices(a, b)
+    # Check if both devices have the same net
+    return false unless same_net(a, b, 'A') && same_net(a, b, 'C')
+
+    # Check if parameters are the same
+    return false unless same_parameter(a, b, 'A') && same_parameter(a, b, 'P')
+
+    # Combine by summing up 'm' parameter
+    a.set_parameter('m', a.parameter('m') + b.parameter('m'))
+
+    # Disconnect the second device and let the system clean it up
+    b.disconnect_terminal('A')
+    b.disconnect_terminal('C')
+
+    true
+  end
+end
+
+class BJTDeviceCombiner < RBA::GenericDeviceCombiner
+  include DeviceCombinerMethods
+
+  # Method to check and perform device combination
+  def combine_devices(a, b)
+    bjt3_nets = %w[C B E]
+    bjt4_nets = %w[C B E S]
+
+    # Determine the correct nets based on device type (assuming PNP or NPN)
+    bjt_nets = a.device_class.name.downcase.include?('pnp') ? bjt3_nets : bjt4_nets
+
+    # Check if terminals have the same net
+    return false unless bjt_nets.all? { |net| same_net(a, b, net) }
+
+    # Check if parameters are the same
+    return false unless %w[AE PE].all? { |param| same_parameter(a, b, param) }
+
+    # Combine parameters
+    a.set_parameter('m', a.parameter('m') + b.parameter('m'))
+    a.set_parameter('NE', a.parameter('NE') + b.parameter('NE'))
+
+    # Disconnect the second device and let the system clean it up
+    bjt_nets.each { |term| b.disconnect_terminal(term) }
+
+    true
+  end
+end
+
+class RESDeviceCombiner < RBA::GenericDeviceCombiner
+  include DeviceCombinerMethods
+
+  # Method to check and perform device combination
+  def combine_devices(a, b)
+    res_nets = [0, 1] # Using id instead of names
+
+    # Check if same parameters
+
+    # Check if terminals series or parallel (With same params)
+    if supp_parallel(a, b, 0, 1)
+      return false unless PARALLEL_RES
+      return false unless %w[w l ps b].all? { |param| same_parameter(a, b, param) }
+
+      a.set_parameter('m', a.parameter('m') + b.parameter('m'))
+    elsif supp_series(a, b, 0, 1)
+      return false unless SERIES_RES
+      return false unless %w[w ps b m].all? { |param| same_parameter(a, b, param) }
+
+      a.set_parameter('l', a.parameter('l') + b.parameter('l'))
+    else
+      return false
+    end
+
+    # Disconnect the second device and let the system clean it up
+    res_nets.each { |term| b.disconnect_terminal(term) }
+
+    true
+  end
+end
+
+#================================================
+# -------------- CUSTOM EXTRACTOR ---------------
+#================================================
+
+# === GeneralNTerminalExtractor ===
+class GeneralNTerminalExtractor < RBA::GenericDeviceExtractor
+  # Extraction of N terminal devices - General Class
+
+  def initialize(name, num)
+    # Initialize the extractor with a device name and number of terminals.
+    #
+    # Args:
+    #   name (String): The name of the device.
+    #   num (Integer): Number of terminals.
+    create
+    self.name = name
+    @num = num
+    @name = name
+  end
+
+  def setup
+    # Set up layers and register device class for extraction.
+    define_layers
+    # Register device class for extraction.
+    if RES_DEV.any? { |res| name.downcase.start_with?(res) }
+      @reg_dev = DeviceCustomRes.new(name, @num)
+    elsif name.downcase.include?('varicap')
+      @reg_dev = DeviceCustomVaractor.new(name, @num)
+    elsif name.downcase.start_with?('ind')
+      @reg_dev = DeviceCustomInd.new(name, @num)
+    else
+      raise ArgumentError, "Custom-Class for #{name} device is not supported yet, please recheck"
+    end
+    register_device_class(@reg_dev)
+  end
+
+  def get_connectivity(_layout, layers)
+    # Establish connectivity between layers.
+    #
+    # Args:
+    #   _layout: Layout object (unused).
+    #   layers (Array): Array of layer objects.
+    #
+    # Returns:
+    #   Connectivity object representing the connections between layers.
+    dev = layers[0]
+    ports = layers[1]
+    meas_mk = layers[2]
+    dev_mk = layers[3]
+
+    conn = RBA::Connectivity.new
+    conn.connect(dev, dev)
+    conn.connect(dev, dev_mk)
+    conn.connect(dev, meas_mk)
+    conn.connect(ports, dev_mk)
+    conn.connect(meas_mk, dev_mk)
+
+    # Sub connection for some devices
+    if name.downcase.start_with?('ind') || name.downcase.include?('varicap')
+      sub_mk = layers[4]
+      conn.connect(sub_mk, dev_mk)
+    end
+
+    conn
+  end
+
+  def extract_devices(layer_geometry)
+    # Extract devices based on layer geometry.
+    #
+    # Args:
+    #   layer_geometry (Array): Array of layer geometries.
+    dev, ports, meas_mk, dev_mk, sub_mk = layer_geometry
+
+    dev_mk.merged.each do |region|
+      if ports.size != @num
+        $logger.info("#{@name} device terminals (#{@num}) don't touch device marker correctly")
+        $logger.info("No. of ports exist for #{@name} is #{ports.size}, should be #{@num}")
+      else
+        device = create_device
+        set_device_parameters(device, region, dev, ports, meas_mk, dev_mk)
+        define_and_sort_terminals(device, ports, sub_mk)
+      end
+    end
+  end
+
+  private
+
+  def define_layers
+    # Define layers for extraction.
+    define_layer('core', 'core Layer')
+    define_layer('ports', 'Connect Terminal')
+    define_layer('meas_mk', 'Measuring parameters marker')
+    define_layer('dev_mk', 'Device Marker')
+    # Define sub layer for some devices
+    if name.downcase.start_with?('ind') || name.downcase.include?('varicap')
+      define_layer('sub_mk', 'Substrate Marker')
+    end
+  end
+
+  def set_device_parameters(device, region, dev, ports, meas_mk, dev_mk)
+    # Set device parameters based on device type.
+    #
+    # Args:
+    #   device: Device object to set parameters for.
+    #   region: Region representing the measured region.
+    #   dev: Device layer object.
+    #   ports: ports layer object.
+    #   meas_mk: Measuring marker layer object.
+    #   dev_mk: main marker layer object.
+    #
+    # Returns:
+    #   None
+
+    if RES_DEV.any? { |res| name.downcase.start_with?(res) }
+      width, length, poly_sp, bends = calc_res_params(dev, ports, meas_mk)
+      device.set_parameter('w', width * $unit)
+      device.set_parameter('l', length * $unit)
+      device.set_parameter('ps', poly_sp * $unit)
+      device.set_parameter('b', bends)
+
+    elsif name.downcase.include?('varicap')
+      width, length = calc_varicap_params(dev, ports, meas_mk, dev_mk)
+      device.set_parameter('w', width * $unit)
+      device.set_parameter('l', length * $unit)
+
+    elsif name.downcase.start_with?('ind')
+      width, space, diameter, no_turns = calc_ind_params(dev, ports, meas_mk, dev_mk, region)
+      device.set_parameter('w', width * $unit)
+      device.set_parameter('s', space * $unit)
+      device.set_parameter('d', diameter * $unit)
+      device.set_parameter('nr_r', no_turns)
+    end
+  end
+
+  def calc_res_params(dev, ports, meas_mk)
+    # Width
+    width_edges = dev.edges.and(ports.edges)
+    width = get_uniq_length(width_edges)
+
+    # Length
+    length_edges = dev.edges.interacting(width_edges).not(width_edges)
+    length, _ = get_min_max_length(length_edges)
+
+    # Bends
+    corners = meas_mk.interacting(dev).corners.not_interacting(ports).count
+    bends = corners / 4
+
+    # poly_space between bends
+    if bends.positive?
+      poly_sp_polygon = meas_mk.interacting(dev)
+      poly_sp = get_notch_min(poly_sp_polygon, 10 * length)
+      length = length + width
+    end
+
+    # Default values
+    width ||= 0
+    length ||= 0
+    poly_sp ||= 0
+    bends ||= 0
+
+    [width, length, poly_sp, bends]
+  end
+
+  def calc_varicap_params(dev, _ports, meas_mk, _dev_mk)
+    # Width & Length
+    width_edges = dev.edges.not_interacting(meas_mk.edges)
+    length, width = get_min_max_length(width_edges)
+
+    # Default values
+    width ||= 0
+    length ||= 0
+
+    [width, length]
+  end
+
+  def calc_ind_params(dev, ports, meas_mk, dev_mk, region)
+    # Get upper limit for width, space
+    _, max_mk_len = get_min_max_length(dev_mk.edges)
+
+    # Width
+    meas_sel = meas_mk.merged & region
+    width = get_width_val(meas_sel, max_mk_len)
+
+    # space
+    space = get_space_val(meas_sel, max_mk_len)
+
+    # Turns
+    # Calc steps used for no. of turns:
+    # step1: Get count of inductor metal (catch if we have more 1)
+    # Step2: For more than 1 turns, get number of holes
+    # Step3: Turns = 1 + (holes - 1)/2 
+    no_turns_init = meas_mk.merged.count
+    no_turns = no_turns_init
+
+    ## Old implementation
+    # if no_turns_init == 1
+    #   no_turns = no_turns_init
+    # else
+    #   no_turns_pre1 = dev.merged.holes.count
+    #   no_turns_pre2 = (no_turns_pre1 - 1) / 2
+    #   no_turns = 1 + no_turns_pre2.ceil
+    # end
+
+    # Diameter
+    # Calc steps used for diameter:
+    # step1: Get extent of the inductor core
+    # step2: Exclude edges that touch inductor pins
+    # step3: Get length of the remaining edge (Outer diameter)
+    # step4: Get internal diameter --> din = dout - ((turns -1) * 2s) - (turns * w)
+    diam_extents = dev.extents.edges
+    diam_edge_exc = diam_extents.interacting(ports)
+    diam_edge = diam_extents.not_interacting(diam_edge_exc)
+    diameter = diam_edge.length
+    diameter = diameter - (2 * (no_turns - 1) * space) - (2 * no_turns * width)
+    diameter = diameter.negative? ? 0 : diameter
+
+    # Default values
+    width ||= 0
+    space ||= 0
+    diameter ||= 0
+    no_turns ||= 1
+
+    [width, space, diameter, no_turns]
+  end
+
+  def define_and_sort_terminals(device, ports, sub_mk)
+    # Define and sort terminals based on location.
+    #
+    # Args:
+    #   device: Device object to define terminals for.
+    #   ports: Contact layer object containing terminals.
+    #   sub_mk: substrate marker layer object.
+    #
+    # Returns:
+    #   None
+
+    # If none of the substrings match, sorted_ports remains the result of sort_polygons(ports)
+    substrings = %w[varicap]
+
+    # Initialize sorted_ports with a default value
+    sorted_ports = nil
+
+    # Iterate over each substring
+    substrings.each do |substring|
+      if name.include?(substring)
+        sorted_ports = ports
+        break # Exit loop if a match is found
+      end
+    end
+
+    # If none of the substrings match, sorted_ports remains the result of sort_polygons(ports)
+    sorted_ports ||= sort_polygons(ports)
+
+    # Define sub if exist (should be defined before other terminals)
+    if name.downcase.start_with?('ind') || name.downcase.include?('varicap')
+      if sub_mk.is_empty?
+        $logger.info("Sub terminal for #{@name} device doesn't exist, please recheck")
+        return nil
+      else
+        define_terminal(device, @reg_dev.terminal_id("#{name}_sub"), 4, sub_mk[0])
+      end
+    end
+
+    # Defination main terminals
+    (1..@num).each do |i|
+      define_terminal(device, @reg_dev.terminal_id("#{name}_#{i}"), 1, sorted_ports[i - 1])
+    end
+  end
+
+  def sort_polygons(polygons)
+    # Sort polygons points.
+    #
+    # Args:
+    #   polygons: Polygons to sort.
+    #
+    # Returns:
+    #   Sorted polygons.
+    #
+    # Note:
+    #   This function sorts the points of the input polygons to be ordered as expected.
+    #   It takes an array of polygons and returns the sorted array.
+    #   The sorting is based on the x-coordinate of the first point of each polygon.
+    con_polygons = []
+
+    polygons.merged.each do |ports_pl|
+      con_edges = []
+      ports_pl.each_edge do |con_ed|
+        con_edges.append([con_ed.x1, con_ed.y1])
+        con_edges.append([con_ed.x2, con_ed.y2])
+      end
+      con_polygons.append(con_edges.uniq)
+    end
+    sorted_ports_polygons = con_polygons.sort_by(&:first)
+    sorted_ports = []
+    sorted_ports_polygons.each do |sorted_pl|
+      ports_pl = RBA::DPolygon.new([RBA::DPoint.new(sorted_pl[0][0], sorted_pl[0][1]),
+                                    RBA::DPoint.new(sorted_pl[1][0], sorted_pl[1][1]),
+                                    RBA::DPoint.new(sorted_pl[2][0], sorted_pl[2][1]),
+                                    RBA::DPoint.new(sorted_pl[3][0], sorted_pl[3][1])])
+      sorted_ports.append(ports_pl)
+    end
+
+    sorted_ports
+  end
+
+  def get_uniq_length(sel_edges)
+    # Extract uniqe length value for some selected edges
+    lengths = []
+    sel_edges.each do |edge|
+      lengths << edge.length
+    end
+    lengths.uniq!
+    lengths.size == 1 ? lengths[0] : 0.0
+  end
+
+  def get_sep_val(sel_edges, sep_edges, sep_val)
+    # Extract distance between edges for separation check
+    proj = RBA::Metrics::Projection
+    sep_paris = sel_edges.separation_check(sep_edges, sep_val, proj)
+    sep_values = []
+    sep_paris.each do |edge|
+      sep_values << edge.distance
+    end
+    sep_values.min
+  end
+
+  def get_space_val(sel_polygon, sep_val)
+    # Extract distance between edges for space check
+    proj = RBA::Metrics::Projection
+    space_paris = sel_polygon.space_check(sep_val, proj)
+    space_values = []
+    space_paris.each do |edge|
+      space_values << edge.distance
+    end
+    space_values.min
+  end
+
+  def get_width_val(sel_polygon, width_val)
+    # intra-polygon spacing check
+    proj = RBA::Metrics::Projection
+    width_paris = sel_polygon.width_check(width_val, metrics: proj, min_projection: 10)
+    width_values = []
+    width_paris.each do |edge|
+      width_values << edge.distance
+    end
+    # Group the array elements by their occurrences
+    width_values = width_values.reject(&:zero?)
+
+    width_values.min
+  end
+
+  def get_notch_min(sel_polygon, sep_val)
+    # intra-polygon spacing check
+    proj = RBA::Metrics::Projection
+    space_paris = sel_polygon.notch_check(sep_val, proj)
+    space_values = []
+    space_paris.each do |edge|
+      space_values << edge.distance
+    end
+    space_values.min
+  end
+
+  def get_notch_max(sel_polygon, sep_val)
+    # intra-polygon spacing check
+    proj = RBA::Metrics::Projection
+    space_paris = sel_polygon.notch_check(sep_val, proj)
+    space_values = []
+    space_paris.each do |edge|
+      space_values << edge.distance
+    end
+    space_values.max
+  end
+
+  def get_min_max_length(sel_edges)
+    # Extract max length value for some selected edges
+    lengths = []
+    sel_edges.each do |edge|
+      lengths << edge.length
+    end
+    lengths.minmax
+  end
+end
+
+#========= CUSTOM MIM-EXTRACTOR =========
+
+#================================================
+# --------------- CUSTOM DEVICES ----------------
+#================================================
+
+# MIM-custom device calss
+class DeviceCustomMIM < RBA::DeviceClassCapacitor
+  def initialize(name)
+    # clear terminals and parameters of resistor class
+    clear_parameters
+    clear_terminals
+    clear_equivalent_terminal_ids
+
+    # Adding params
+    add_parameter(RBA::DeviceParameterDefinition.new('w', 'width', 0, false))
+    add_parameter(RBA::DeviceParameterDefinition.new('l', 'length', 0, false))
+    add_parameter(RBA::DeviceParameterDefinition.new('A', 'area', 0, true))
+    add_parameter(RBA::DeviceParameterDefinition.new('P', 'perimeter', 0, true))
+    add_parameter(RBA::DeviceParameterDefinition.new('m', 'multiplier', 1, true))
+
+    # Adding terminals
+    ter1 = add_terminal(RBA::DeviceTerminalDefinition.new("mim_top"))
+    ter2 = add_terminal(RBA::DeviceTerminalDefinition.new("mim_btm"))
+    ter1.name = "mim_top"
+    ter2.name = "mim_btm"
+
+    # Adding extra param & terminal for rfcmim
+    return unless name.downcase.include?('rfcmim')
+
+    add_parameter(RBA::DeviceParameterDefinition.new('wfeed', 'feed width', 0, true))
+    sub_ter = add_terminal(RBA::DeviceTerminalDefinition.new("mim_sub"))
+    sub_ter.name = "mim_sub"
+  end
+end
+
+# === MIMCAPExtractor ===
+class MIMCAPExtractor < RBA::GenericDeviceExtractor
+  # Extraction of N terminal devices - General Class
+
+  def initialize(name)
+    # Initialize the extractor with a device name and number of terminals.
+    #
+    # Args:
+    #   name (String): The name of the device.
+
+    self.name = name
+    @name = name
+  end
+
+  def setup
+    # Set up layers and register device class for extraction.
+    define_layers
+    # Register device class for extraction.
+    @reg_dev = DeviceCustomMIM.new(name)
+
+    # Disable combination for rfcmim
+    if name.downcase.include?('rfcmim')
+      @reg_dev.combiner = nil 
+    else
+      @reg_dev.combiner = MIMCAPNDeviceCombiner.new
+    end
+    register_device_class(@reg_dev)
+  end
+
+  def get_connectivity(_layout, layers)
+    # Establish connectivity between layers.
+    #
+    # Args:
+    #   _layout: Layout object (unused).
+    #   layers (Array): Array of layer objects.
+    #
+    # Returns:
+    #   Connectivity object representing the connections between layers.
+    dev = layers[0]
+    top_mim = layers[1]
+    btm_mim = layers[2]
+    dev_mk = layers[3]
+    meas_mk = layers[4]
+
+    conn = RBA::Connectivity.new
+    conn.connect(dev, dev)
+    conn.connect(dev, dev_mk)
+    conn.connect(dev, meas_mk)
+    conn.connect(top_mim, dev_mk)
+    conn.connect(btm_mim, dev_mk)
+
+    # Sub connection for rfcmim
+    if name.downcase.include?('rfcmim')
+      sub_mk = layers[5]
+      conn.connect(sub_mk, dev_mk)
+    end
+
+    conn
+  end
+
+  def extract_devices(layer_geometry)
+    # Extract devices based on layer geometry.
+    #
+    # Args:
+    #   layer_geometry (Array): Array of layer geometries.
+    dev, top_mim, btm_mim, dev_mk, meas_mk, sub_mk = layer_geometry
+
+    dev_mk.merged.each do |_region|
+      if top_mim.size != 1
+        $logger.info("No. of ports exist for #{@name} topmetal is #{top_mim.size}, should be 1")
+      elsif btm_mim.size != 1
+        $logger.info("No. of ports exist for #{@name} btmmetal is #{btm_mim.size}, should be 1")
+      else
+        device = create_device
+        set_device_parameters(device, dev, dev_mk, meas_mk)
+        define_terminals(device, top_mim, btm_mim, sub_mk)
+      end
+    end
+  end
+
+  private
+
+  def define_layers
+    # Define layers for extraction.
+    define_layer('core', 'core Layer')
+    define_layer('top_mim', 'Connect Terminal for top mim')
+    define_layer('btm_mim', 'Connect Terminal for btm mim')
+    define_layer('dev_mk', 'Device Marker')
+    define_layer('meas_mk', 'Measuring parameters marker')
+
+    # Define sub layer for some devices
+    return unless name.downcase.include?('rfcmim')
+
+    define_layer('sub_mk', 'Substrate layer')
+  end
+
+  def set_device_parameters(device, dev, dev_mk, meas_mk)
+    # Set device parameters based on device type.
+    #
+    # Args:
+    #   device: Device object to set parameters for.
+    #   dev: Device layer object.
+    #   dev_mk: device marker layer object.
+    #   meas_mk: meas marker layer object.
+    #
+    # Returns:
+    #   None
+
+    width, length, wfeed = calc_cmim_params(dev, dev_mk, meas_mk)
+
+    if name.downcase.include?('rfcmim')
+      device.set_parameter('l', width * $unit)
+      device.set_parameter('w', length * $unit)
+      device.set_parameter('wfeed', wfeed * $unit)
+    else
+      device.set_parameter('w', width * $unit)
+      device.set_parameter('l', length * $unit)
+    end
+    device.set_parameter('A', width * length * $unit * $unit)
+    device.set_parameter('P', (width + length) * 2 * $unit)
+
+  end
+
+  def calc_cmim_params(dev, dev_mk, meas_mk)
+    # Width & Length
+    dev_edges = dev.edges
+    width_edges = dev_edges.with_angle(0, false)
+    len_edges = dev_edges.not(width_edges)
+    width = get_uniq_length(width_edges)
+    length = get_uniq_length(len_edges)
+
+    # Wfeed
+    wfeed_edges = meas_mk.edges.and(dev_mk.edges)
+    wfeed = get_uniq_length(wfeed_edges)
+  
+    # Default values
+    width ||= 0
+    length ||= 0
+    wfeed ||= 0
+
+    [width, length, wfeed]
+  end
+
+  def define_terminals(device, top_mim, btm_mim, sub_mk)
+    # Define terminals based on location.
+    #
+    # Args:
+    #   device: Device object to define terminals for.
+    #   top_mim: Contact layer object containing mim top metal.
+    #   top_mim: Contact layer object containing mim btm metal.
+    #   sub_mk: substrate marker layer object.
+    #
+    # Returns:
+    #   None
+
+    # Define sub if exist (should be defined before other terminals)
+    if name.downcase.include?('rfcmim')
+      if sub_mk.is_empty?
+        $logger.info("Sub terminal for #{@name} device doesn't exist, please recheck")
+        return nil
+      else
+        define_terminal(device, @reg_dev.terminal_id("mim_sub"), 5, sub_mk[0])
+      end
+    end
+
+    # Defination main terminals
+    define_terminal(device, @reg_dev.terminal_id("mim_top"), 1, top_mim[0])
+    define_terminal(device, @reg_dev.terminal_id("mim_btm"), 2, btm_mim[0])
+  end
+
+  def get_min_max_length(sel_edges)
+    # Extract max length value for some selected edges
+    lengths = []
+    sel_edges.each do |edge|
+      lengths << edge.length
+    end
+    lengths.minmax
+  end
+
+  def get_uniq_length(sel_edges)
+    # Extract uniqe length value for some selected edges
+    lengths = []
+    sel_edges.each do |edge|
+      lengths << edge.length
+    end
+    lengths.uniq!
+    lengths.size == 1 ? lengths[0] : 0.0
+  end
+end
+
+#================================================
+# --------------- END OF CLASSES ----------------
+#================================================
+
+# Instantiate a reader using the new delegate
+reader = RBA::NetlistSpiceReader.new(CustomReader.new)
+
+#=== GET NETLIST ===
+unless NET_ONLY
+  if $cdl_file
+    schematic($cdl_file, reader)
+    logger.info("Netlist file: #{$cdl_file}")
+  else
+    exts = %w[spice cdl cir]
+    candidates = exts.map { |ext| "#{source.cell_name}.#{ext}" }
+    netlists = candidates.select { |f| File.exist?(f) }
+    if netlists.empty?
+      error("Netlist not found, tried: #{candidates}")
+    else
+      schematic(netlists[0], reader)
+      logger.info("Netlist file: #{netlists[0]}")
+    end
+  end
+end
+
+# Instantiate a writer using the new delegate
+custom_spice_writer = RBA::NetlistSpiceWriter.new(CustomWriter.new)
+custom_spice_writer.use_net_names = SPICE_WITH_NET_NAMES
+custom_spice_writer.with_comments = SPICE_WITH_COMMENTS
+
+if $target_netlist
+  logger.info("LVS extracted netlist at: #{$target_netlist}")
+  target_netlist($target_netlist, custom_spice_writer,
+                 "Extracted by KLayout with SG13G2 LVS runset on : #{Time.now.strftime('%d/%m/%Y %H:%M')}")
+else
+  layout_dir = Pathname.new(RBA::CellView.active.filename).parent.realpath
+  netlist_path = layout_dir.join("#{source.cell_name}_extracted.cir")
+  target_netlist(netlist_path.to_s, custom_spice_writer,
+                 "Extracted by KLayout with SG13G2 LVS runset on : #{Time.now.strftime('%d/%m/%Y %H:%M')}")
+  logger.info("SG13G2 Klayout LVS extracted netlist file at: #{source.cell_name}_extracted.cir")
+end
+
+#================================================
+#------------- LAYERS DEFINITIONS ---------------
+#================================================
+
+polygons_count = 0
+logger.info('Read in polygons from layers.')
+
+def get_polygons(lay_no, lay_dt)
+  if $run_mode == 'deep'
+    polygons(lay_no, lay_dt)
+  else
+    polygons(lay_no, lay_dt).merged
+  end
+end
+
+activ_drw = get_polygons(1, 0)
+count = activ_drw.count()
+logger.info("activ_drw has #{count} polygons")
+polygons_count += count
+
+activ_filler = get_polygons(1, 22)
+count = activ_filler.count()
+logger.info("activ_filler has #{count} polygons")
+polygons_count += count
+
+# activ org
+activ = activ_drw.join(activ_filler)
+count = activ.count()
+logger.info("activ has #{count} polygons")
+
+activ_pin = get_polygons(1, 2)
+count = activ_pin.count()
+logger.info("activ_pin has #{count} polygons")
+polygons_count += count
+
+activ_mask = get_polygons(1, 20)
+count = activ_mask.count()
+logger.info("activ_mask has #{count} polygons")
+polygons_count += count
+
+activ_nofill = get_polygons(1, 23)
+count = activ_nofill.count()
+logger.info("activ_nofill has #{count} polygons")
+polygons_count += count
+
+activ_OPC = get_polygons(1, 26)
+count = activ_OPC.count()
+logger.info("activ_OPC has #{count} polygons")
+polygons_count += count
+
+activ_iOPC = get_polygons(1, 27)
+count = activ_iOPC.count()
+logger.info("activ_iOPC has #{count} polygons")
+polygons_count += count
+
+activ_noqrc = get_polygons(1, 28)
+count = activ_noqrc.count()
+logger.info("activ_noqrc has #{count} polygons")
+polygons_count += count
+
+biwind_drw = get_polygons(3, 0)
+count = biwind_drw.count()
+logger.info("biwind_drw has #{count} polygons")
+polygons_count += count
+
+biwind_OPC = get_polygons(3, 26)
+count = biwind_OPC.count()
+logger.info("biwind_OPC has #{count} polygons")
+polygons_count += count
+
+gatpoly_drw = get_polygons(5, 0)
+count = gatpoly_drw.count()
+logger.info("gatpoly_drw has #{count} polygons")
+polygons_count += count
+
+gatpoly_filler = get_polygons(5, 22)
+count = gatpoly_filler.count()
+logger.info("gatpoly_filler has #{count} polygons")
+polygons_count += count
+
+# gatpoly org
+gatpoly = gatpoly_drw.join(gatpoly_filler)
+count = gatpoly.count()
+logger.info("gatpoly has #{count} polygons")
+
+gatpoly_pin = get_polygons(5, 2)
+count = gatpoly_pin.count()
+logger.info("gatpoly_pin has #{count} polygons")
+polygons_count += count
+
+gatpoly_nofill = get_polygons(5, 23)
+count = gatpoly_nofill.count()
+logger.info("gatpoly_nofill has #{count} polygons")
+polygons_count += count
+
+gatpoly_OPC = get_polygons(5, 26)
+count = gatpoly_OPC.count()
+logger.info("gatpoly_OPC has #{count} polygons")
+polygons_count += count
+
+gatpoly_iOPC = get_polygons(5, 27)
+count = gatpoly_iOPC.count()
+logger.info("gatpoly_iOPC has #{count} polygons")
+polygons_count += count
+
+gatpoly_noqrc = get_polygons(5, 28)
+count = gatpoly_noqrc.count()
+logger.info("gatpoly_noqrc has #{count} polygons")
+polygons_count += count
+
+cont_drw = get_polygons(6, 0)
+count = cont_drw.count()
+logger.info("cont_drw has #{count} polygons")
+polygons_count += count
+
+cont_OPC = get_polygons(6, 26)
+count = cont_OPC.count()
+logger.info("cont_OPC has #{count} polygons")
+polygons_count += count
+
+nsd_drw  = get_polygons(7, 0)
+count = nsd_drw.count()
+logger.info("nsd_drw has #{count} polygons")
+polygons_count += count
+
+nsd_block = get_polygons(7, 21)
+count = nsd_block.count()
+logger.info("nsd_block has #{count} polygons")
+polygons_count += count
+
+metal1_drw = get_polygons(8, 0)
+count = metal1_drw.count()
+logger.info("metal1_drw has #{count} polygons")
+polygons_count += count
+
+metal1_filler = get_polygons(8, 22)
+count = metal1_filler.count()
+logger.info("metal1_filler has #{count} polygons")
+polygons_count += count
+
+metal1_slit = get_polygons(8, 24)
+count = metal1_slit.count()
+logger.info("metal1_slit has #{count} polygons")
+polygons_count += count
+
+# metal1 org
+metal1 = metal1_drw.join(metal1_filler).not(metal1_slit)
+count = metal1.count()
+logger.info("metal1 has #{count} polygons")
+
+metal1_pin = get_polygons(8, 2)
+count = metal1_pin.count()
+logger.info("metal1_pin has #{count} polygons")
+polygons_count += count
+
+metal1_mask = get_polygons(8, 20)
+count = metal1_mask.count()
+logger.info("metal1_mask has #{count} polygons")
+polygons_count += count
+
+metal1_nofill = get_polygons(8, 23)
+count = metal1_nofill.count()
+logger.info("metal1_nofill has #{count} polygons")
+polygons_count += count
+
+metal1_text = labels(8, 25)
+count = metal1_text.count()
+logger.info("metal1_text has #{count} polygons")
+polygons_count += count
+
+metal1_OPC = get_polygons(8, 26)
+count = metal1_OPC.count()
+logger.info("metal1_OPC has #{count} polygons")
+polygons_count += count
+
+metal1_noqrc = get_polygons(8, 28)
+count = metal1_noqrc.count()
+logger.info("metal1_noqrc has #{count} polygons")
+polygons_count += count
+
+metal1_res = get_polygons(8, 29)
+count = metal1_res.count()
+logger.info("metal1_res has #{count} polygons")
+polygons_count += count
+
+metal1_iprobe = get_polygons(8, 33)
+count = metal1_iprobe.count()
+logger.info("metal1_iprobe has #{count} polygons")
+polygons_count += count
+
+metal1_diffprb = get_polygons(8, 34)
+count = metal1_diffprb.count()
+logger.info("metal1_diffprb has #{count} polygons")
+polygons_count += count
+
+passiv_drw = get_polygons(9, 0)
+count = passiv_drw.count()
+logger.info("passiv_drw has #{count} polygons")
+polygons_count += count
+
+passiv_pin = get_polygons(9, 2)
+count = passiv_pin.count()
+logger.info("passiv_pin has #{count} polygons")
+polygons_count += count
+
+passiv_sbump = get_polygons(9, 36)
+count = passiv_sbump.count()
+logger.info("passiv_sbump has #{count} polygons")
+polygons_count += count
+
+passiv_pillar = get_polygons(9, 35)
+count = passiv_pillar.count()
+logger.info("passiv_pillar has #{count} polygons")
+polygons_count += count
+
+passiv_pdl = get_polygons(9, 40)
+count = passiv_pdl.count()
+logger.info("passiv_pdl has #{count} polygons")
+polygons_count += count
+
+metal2_drw = get_polygons(10, 0)
+count = metal2_drw.count()
+logger.info("metal2_drw has #{count} polygons")
+polygons_count += count
+
+metal2_filler = get_polygons(10, 22)
+count = metal2_filler.count()
+logger.info("metal2_filler has #{count} polygons")
+polygons_count += count
+
+metal2_slit = get_polygons(10, 24)
+count = metal2_slit.count()
+logger.info("metal2_slit has #{count} polygons")
+polygons_count += count
+
+# metal2 org
+metal2 = metal2_drw.join(metal2_filler).not(metal2_slit)
+count = metal2.count()
+logger.info("metal2 has #{count} polygons")
+
+metal2_pin = get_polygons(10, 2)
+count = metal2_pin.count()
+logger.info("metal2_pin has #{count} polygons")
+polygons_count += count
+
+metal2_mask = get_polygons(10, 20)
+count = metal2_mask.count()
+logger.info("metal2_mask has #{count} polygons")
+polygons_count += count
+
+metal2_nofill = get_polygons(10, 23)
+count = metal2_nofill.count()
+logger.info("metal2_nofill has #{count} polygons")
+polygons_count += count
+
+metal2_text = labels(10, 25)
+count = metal2_text.count()
+logger.info("metal2_text has #{count} polygons")
+polygons_count += count
+
+metal2_OPC = get_polygons(10, 26)
+count = metal2_OPC.count()
+logger.info("metal2_OPC has #{count} polygons")
+polygons_count += count
+
+metal2_noqrc = get_polygons(10, 28)
+count = metal2_noqrc.count()
+logger.info("metal2_noqrc has #{count} polygons")
+polygons_count += count
+
+metal2_res = get_polygons(10, 29)
+count = metal2_res.count()
+logger.info("metal2_res has #{count} polygons")
+polygons_count += count
+
+metal2_iprobe = get_polygons(10, 33)
+count = metal2_iprobe.count()
+logger.info("metal2_iprobe has #{count} polygons")
+polygons_count += count
+
+metal2_diffprb = get_polygons(10, 34)
+count = metal2_diffprb.count()
+logger.info("metal2_diffprb has #{count} polygons")
+polygons_count += count
+
+baspoly_drw = get_polygons(13, 0)
+count = baspoly_drw.count()
+logger.info("baspoly_drw has #{count} polygons")
+polygons_count += count
+
+baspoly_pin = get_polygons(13, 2)
+count = baspoly_pin.count()
+logger.info("baspoly_pin has #{count} polygons")
+polygons_count += count
+
+psd_drw  = get_polygons(14, 0)
+count = psd_drw.count()
+logger.info("psd_drw has #{count} polygons")
+polygons_count += count
+
+nldb_drw = get_polygons(15, 0)
+count = nldb_drw.count()
+logger.info("nldb_drw has #{count} polygons")
+polygons_count += count
+
+digibnd_drw = get_polygons(16, 0)
+count = digibnd_drw.count()
+logger.info("digibnd_drw has #{count} polygons")
+polygons_count += count
+
+via1_drw = get_polygons(19, 0)
+count = via1_drw.count()
+logger.info("via1_drw has #{count} polygons")
+polygons_count += count
+
+backmetal1_drw = get_polygons(20, 0)
+count = backmetal1_drw.count()
+logger.info("backmetal1_drw has #{count} polygons")
+polygons_count += count
+
+backmetal1_pin = get_polygons(20, 2)
+count = backmetal1_pin.count()
+logger.info("backmetal1_pin has #{count} polygons")
+polygons_count += count
+
+backmetal1_mask = get_polygons(20, 20)
+count = backmetal1_mask.count()
+logger.info("backmetal1_mask has #{count} polygons")
+polygons_count += count
+
+backmetal1_filler = get_polygons(20, 22)
+count = backmetal1_filler.count()
+logger.info("backmetal1_filler has #{count} polygons")
+polygons_count += count
+
+backmetal1_nofill = get_polygons(20, 23)
+count = backmetal1_nofill.count()
+logger.info("backmetal1_nofill has #{count} polygons")
+polygons_count += count
+
+backmetal1_slit = get_polygons(20, 24)
+count = backmetal1_slit.count()
+logger.info("backmetal1_slit has #{count} polygons")
+polygons_count += count
+
+backmetal1_text = labels(20, 25)
+count = backmetal1_text.count()
+logger.info("backmetal1_text has #{count} polygons")
+polygons_count += count
+
+backmetal1_OPC = get_polygons(20, 26)
+count = backmetal1_OPC.count()
+logger.info("backmetal1_OPC has #{count} polygons")
+polygons_count += count
+
+backmetal1_noqrc = get_polygons(20, 28)
+count = backmetal1_noqrc.count()
+logger.info("backmetal1_noqrc has #{count} polygons")
+polygons_count += count
+
+backmetal1_res = get_polygons(20, 29)
+count = backmetal1_res.count()
+logger.info("backmetal1_res has #{count} polygons")
+polygons_count += count
+
+backmetal1_iprobe = get_polygons(20, 33)
+count = backmetal1_iprobe.count()
+logger.info("backmetal1_iprobe has #{count} polygons")
+polygons_count += count
+
+backmetal1_diffprb = get_polygons(20, 34)
+count = backmetal1_diffprb.count()
+logger.info("backmetal1_diffprb has #{count} polygons")
+polygons_count += count
+
+backpassiv_drw = get_polygons(23, 0)
+count = backpassiv_drw.count()
+logger.info("backpassiv_drw has #{count} polygons")
+polygons_count += count
+
+res_drw  = get_polygons(24, 0)
+count = res_drw.count()
+logger.info("res_drw has #{count} polygons")
+polygons_count += count
+
+sram_drw = get_polygons(25, 0)
+count = sram_drw.count()
+logger.info("sram_drw has #{count} polygons")
+polygons_count += count
+
+trans_drw = get_polygons(26, 0)
+count = trans_drw.count()
+logger.info("trans_drw has #{count} polygons")
+polygons_count += count
+
+ind_drw  = get_polygons(27, 0)
+count = ind_drw.count()
+logger.info("ind_drw has #{count} polygons")
+polygons_count += count
+
+ind_pin  = get_polygons(27, 2)
+count = ind_pin.count()
+logger.info("ind_pin has #{count} polygons")
+polygons_count += count
+
+ind_text = labels(27, 25)
+count = ind_text.count()
+logger.info("ind_text has #{count} polygons")
+polygons_count += count
+
+salblock_drw = get_polygons(28, 0)
+count = salblock_drw.count()
+logger.info("salblock_drw has #{count} polygons")
+polygons_count += count
+
+via2_drw = get_polygons(29, 0)
+count = via2_drw.count()
+logger.info("via2_drw has #{count} polygons")
+polygons_count += count
+
+metal3_drw = get_polygons(30, 0)
+count = metal3_drw.count()
+logger.info("metal3_drw has #{count} polygons")
+polygons_count += count
+
+metal3_filler = get_polygons(30, 22)
+count = metal3_filler.count()
+logger.info("metal3_filler has #{count} polygons")
+polygons_count += count
+
+metal3_slit = get_polygons(30, 24)
+count = metal3_slit.count()
+logger.info("metal3_slit has #{count} polygons")
+polygons_count += count
+
+# metal3 org
+metal3 = metal3_drw.join(metal3_filler).not(metal3_slit)
+count = metal3.count()
+logger.info("metal3 has #{count} polygons")
+
+metal3_pin = get_polygons(30, 2)
+count = metal3_pin.count()
+logger.info("metal3_pin has #{count} polygons")
+polygons_count += count
+
+metal3_mask = get_polygons(30, 20)
+count = metal3_mask.count()
+logger.info("metal3_mask has #{count} polygons")
+polygons_count += count
+
+metal3_nofill = get_polygons(30, 23)
+count = metal3_nofill.count()
+logger.info("metal3_nofill has #{count} polygons")
+polygons_count += count
+
+metal3_text = labels(30, 25)
+count = metal3_text.count()
+logger.info("metal3_text has #{count} polygons")
+polygons_count += count
+
+metal3_OPC = get_polygons(30, 26)
+count = metal3_OPC.count()
+logger.info("metal3_OPC has #{count} polygons")
+polygons_count += count
+
+metal3_noqrc = get_polygons(30, 28)
+count = metal3_noqrc.count()
+logger.info("metal3_noqrc has #{count} polygons")
+polygons_count += count
+
+metal3_res = get_polygons(30, 29)
+count = metal3_res.count()
+logger.info("metal3_res has #{count} polygons")
+polygons_count += count
+
+metal3_iprobe = get_polygons(30, 33)
+count = metal3_iprobe.count()
+logger.info("metal3_iprobe has #{count} polygons")
+polygons_count += count
+
+metal3_diffprb = get_polygons(30, 34)
+count = metal3_diffprb.count()
+logger.info("metal3_diffprb has #{count} polygons")
+polygons_count += count
+
+nwell_drw = get_polygons(31, 0)
+count = nwell_drw.count()
+logger.info("nwell_drw has #{count} polygons")
+polygons_count += count
+
+nwell_pin = get_polygons(31, 2)
+count = nwell_pin.count()
+logger.info("nwell_pin has #{count} polygons")
+polygons_count += count
+
+nbulay_drw = get_polygons(32, 0)
+count = nbulay_drw.count()
+logger.info("nbulay_drw has #{count} polygons")
+polygons_count += count
+
+nbulay_pin = get_polygons(32, 2)
+count = nbulay_pin.count()
+logger.info("nbulay_pin has #{count} polygons")
+polygons_count += count
+
+nbulay_block = get_polygons(32, 21)
+count = nbulay_block.count()
+logger.info("nbulay_block has #{count} polygons")
+polygons_count += count
+
+emwind_drw = get_polygons(33, 0)
+count = emwind_drw.count()
+logger.info("emwind_drw has #{count} polygons")
+polygons_count += count
+
+emwind_OPC = get_polygons(33, 26)
+count = emwind_OPC.count()
+logger.info("emwind_OPC has #{count} polygons")
+polygons_count += count
+
+deepco_drw = get_polygons(35, 0)
+count = deepco_drw.count()
+logger.info("deepco_drw has #{count} polygons")
+polygons_count += count
+
+mim_drw  = get_polygons(36, 0)
+count = mim_drw.count()
+logger.info("mim_drw has #{count} polygons")
+polygons_count += count
+
+edgeseal_drw = get_polygons(39, 0)
+count = edgeseal_drw.count()
+logger.info("edgeseal_drw has #{count} polygons")
+polygons_count += count
+
+substrate_drw = get_polygons(40, 0)
+count = substrate_drw.count()
+logger.info("substrate_drw has #{count} polygons")
+polygons_count += count
+
+substrate_text = labels(40, 25)
+count = substrate_text.count()
+logger.info("substrate_text has #{count} polygons")
+polygons_count += count
+
+dfpad_drw = get_polygons(41, 0)
+count = dfpad_drw.count()
+logger.info("dfpad_drw has #{count} polygons")
+polygons_count += count
+
+dfpad_pillar = get_polygons(41, 35)
+count = dfpad_pillar.count()
+logger.info("dfpad_pillar has #{count} polygons")
+polygons_count += count
+
+dfpad_sbump = get_polygons(41, 36)
+count = dfpad_sbump.count()
+logger.info("dfpad_sbump has #{count} polygons")
+polygons_count += count
+
+thickgateox_drw = get_polygons(44, 0)
+count = thickgateox_drw.count()
+logger.info("thickgateox_drw has #{count} polygons")
+polygons_count += count
+
+pldb_drw = get_polygons(45, 0)
+count = pldb_drw.count()
+logger.info("pldb_drw has #{count} polygons")
+polygons_count += count
+
+pwell_drw = get_polygons(46, 0)
+count = pwell_drw.count()
+logger.info("pwell_drw has #{count} polygons")
+polygons_count += count
+
+pwell_pin = get_polygons(46, 2)
+count = pwell_pin.count()
+logger.info("pwell_pin has #{count} polygons")
+polygons_count += count
+
+pwell_block = get_polygons(46, 21)
+count = pwell_block.count()
+logger.info("pwell_block has #{count} polygons")
+polygons_count += count
+
+ic_drw   = get_polygons(48, 0)
+count = ic_drw.count()
+logger.info("ic_drw has #{count} polygons")
+polygons_count += count
+
+via3_drw = get_polygons(49, 0)
+count = via3_drw.count()
+logger.info("via3_drw has #{count} polygons")
+polygons_count += count
+
+metal4_drw = get_polygons(50, 0)
+count = metal4_drw.count()
+logger.info("metal4_drw has #{count} polygons")
+polygons_count += count
+
+metal4_filler = get_polygons(50, 22)
+count = metal4_filler.count()
+logger.info("metal4_filler has #{count} polygons")
+polygons_count += count
+
+metal4_slit = get_polygons(50, 24)
+count = metal4_slit.count()
+logger.info("metal4_slit has #{count} polygons")
+polygons_count += count
+
+# metal4 org
+metal4 = metal4_drw.join(metal4_filler).not(metal4_slit)
+count = metal4.count()
+logger.info("metal4 has #{count} polygons")
+
+metal4_pin = get_polygons(50, 2)
+count = metal4_pin.count()
+logger.info("metal4_pin has #{count} polygons")
+polygons_count += count
+
+metal4_mask = get_polygons(50, 20)
+count = metal4_mask.count()
+logger.info("metal4_mask has #{count} polygons")
+polygons_count += count
+
+metal4_nofill = get_polygons(50, 23)
+count = metal4_nofill.count()
+logger.info("metal4_nofill has #{count} polygons")
+polygons_count += count
+
+metal4_text = labels(50, 25)
+count = metal4_text.count()
+logger.info("metal4_text has #{count} polygons")
+polygons_count += count
+
+metal4_OPC = get_polygons(50, 26)
+count = metal4_OPC.count()
+logger.info("metal4_OPC has #{count} polygons")
+polygons_count += count
+
+metal4_noqrc = get_polygons(50, 28)
+count = metal4_noqrc.count()
+logger.info("metal4_noqrc has #{count} polygons")
+polygons_count += count
+
+metal4_res = get_polygons(50, 29)
+count = metal4_res.count()
+logger.info("metal4_res has #{count} polygons")
+polygons_count += count
+
+metal4_iprobe = get_polygons(50, 33)
+count = metal4_iprobe.count()
+logger.info("metal4_iprobe has #{count} polygons")
+polygons_count += count
+
+metal4_diffprb = get_polygons(50, 34)
+count = metal4_diffprb.count()
+logger.info("metal4_diffprb has #{count} polygons")
+polygons_count += count
+
+heattrans_drw = get_polygons(51, 0)
+count = heattrans_drw.count()
+logger.info("heattrans_drw has #{count} polygons")
+polygons_count += count
+
+heatres_drw = get_polygons(52, 0)
+count = heatres_drw.count()
+logger.info("heatres_drw has #{count} polygons")
+polygons_count += count
+
+fbe_drw  = get_polygons(54, 0)
+count = fbe_drw.count()
+logger.info("fbe_drw has #{count} polygons")
+polygons_count += count
+
+empoly_drw = get_polygons(55, 0)
+count = empoly_drw.count()
+logger.info("empoly_drw has #{count} polygons")
+polygons_count += count
+
+digisub_drw = get_polygons(60, 0)
+count = digisub_drw.count()
+logger.info("digisub_drw has #{count} polygons")
+polygons_count += count
+
+text_drw = labels(63, 0)
+count = text_drw.count()
+logger.info("text_drw has #{count} polygons")
+polygons_count += count
+
+via4_drw = get_polygons(66, 0)
+count = via4_drw.count()
+logger.info("via4_drw has #{count} polygons")
+polygons_count += count
+
+metal5_drw = get_polygons(67, 0)
+count = metal5_drw.count()
+logger.info("metal5_drw has #{count} polygons")
+polygons_count += count
+
+metal5_filler = get_polygons(67, 22)
+count = metal5_filler.count()
+logger.info("metal5_filler has #{count} polygons")
+polygons_count += count
+
+metal5_slit = get_polygons(67, 24)
+count = metal5_slit.count()
+logger.info("metal5_slit has #{count} polygons")
+polygons_count += count
+
+# metal5 org
+metal5 = metal5_drw.join(metal5_filler).not(metal5_slit)
+count = metal5.count()
+logger.info("metal5 has #{count} polygons")
+
+metal5_pin = get_polygons(67, 2)
+count = metal5_pin.count()
+logger.info("metal5_pin has #{count} polygons")
+polygons_count += count
+
+metal5_mask = get_polygons(67, 20)
+count = metal5_mask.count()
+logger.info("metal5_mask has #{count} polygons")
+polygons_count += count
+
+metal5_nofill = get_polygons(67, 23)
+count = metal5_nofill.count()
+logger.info("metal5_nofill has #{count} polygons")
+polygons_count += count
+
+metal5_text = labels(67, 25)
+count = metal5_text.count()
+logger.info("metal5_text has #{count} polygons")
+polygons_count += count
+
+metal5_OPC = get_polygons(67, 26)
+count = metal5_OPC.count()
+logger.info("metal5_OPC has #{count} polygons")
+polygons_count += count
+
+metal5_noqrc = get_polygons(67, 28)
+count = metal5_noqrc.count()
+logger.info("metal5_noqrc has #{count} polygons")
+polygons_count += count
+
+metal5_res = get_polygons(67, 29)
+count = metal5_res.count()
+logger.info("metal5_res has #{count} polygons")
+polygons_count += count
+
+metal5_iprobe = get_polygons(67, 33)
+count = metal5_iprobe.count()
+logger.info("metal5_iprobe has #{count} polygons")
+polygons_count += count
+
+metal5_diffprb = get_polygons(67, 34)
+count = metal5_diffprb.count()
+logger.info("metal5_diffprb has #{count} polygons")
+polygons_count += count
+
+radhard_drw = get_polygons(68, 0)
+count = radhard_drw.count()
+logger.info("radhard_drw has #{count} polygons")
+polygons_count += count
+
+memcap_drw = get_polygons(69, 0)
+count = memcap_drw.count()
+logger.info("memcap_drw has #{count} polygons")
+polygons_count += count
+
+varicap_drw = get_polygons(70, 0)
+count = varicap_drw.count()
+logger.info("varicap_drw has #{count} polygons")
+polygons_count += count
+
+intbondvia_drw = get_polygons(72, 0)
+count = intbondvia_drw.count()
+logger.info("intbondvia_drw has #{count} polygons")
+polygons_count += count
+
+intbondmet_drw = get_polygons(73, 0)
+count = intbondmet_drw.count()
+logger.info("intbondmet_drw has #{count} polygons")
+polygons_count += count
+
+devbondvia_drw = get_polygons(74, 0)
+count = devbondvia_drw.count()
+logger.info("devbondvia_drw has #{count} polygons")
+polygons_count += count
+
+devbondmet_drw = get_polygons(75, 0)
+count = devbondmet_drw.count()
+logger.info("devbondmet_drw has #{count} polygons")
+polygons_count += count
+
+devtrench_drw = get_polygons(76, 0)
+count = devtrench_drw.count()
+logger.info("devtrench_drw has #{count} polygons")
+polygons_count += count
+
+redist_drw = get_polygons(77, 0)
+count = redist_drw.count()
+logger.info("redist_drw has #{count} polygons")
+polygons_count += count
+
+graphbot_drw = get_polygons(78, 0)
+count = graphbot_drw.count()
+logger.info("graphbot_drw has #{count} polygons")
+polygons_count += count
+
+graphtop_drw = get_polygons(79, 0)
+count = graphtop_drw.count()
+logger.info("graphtop_drw has #{count} polygons")
+polygons_count += count
+
+antvia1_drw = get_polygons(83, 0)
+count = antvia1_drw.count()
+logger.info("antvia1_drw has #{count} polygons")
+polygons_count += count
+
+antmetal2_drw = get_polygons(84, 0)
+count = antmetal2_drw.count()
+logger.info("antmetal2_drw has #{count} polygons")
+polygons_count += count
+
+graphcont_drw = get_polygons(85, 0)
+count = graphcont_drw.count()
+logger.info("graphcont_drw has #{count} polygons")
+polygons_count += count
+
+siwg_drw = get_polygons(86, 0)
+count = siwg_drw.count()
+logger.info("siwg_drw has #{count} polygons")
+polygons_count += count
+
+siwg_filler = get_polygons(86, 22)
+count = siwg_filler.count()
+logger.info("siwg_filler has #{count} polygons")
+polygons_count += count
+
+siwg_nofill = get_polygons(86, 23)
+count = siwg_nofill.count()
+logger.info("siwg_nofill has #{count} polygons")
+polygons_count += count
+
+sigrating_drw = get_polygons(87, 0)
+count = sigrating_drw.count()
+logger.info("sigrating_drw has #{count} polygons")
+polygons_count += count
+
+singrating_drw = get_polygons(88, 0)
+count = singrating_drw.count()
+logger.info("singrating_drw has #{count} polygons")
+polygons_count += count
+
+graphpas_drw = get_polygons(89, 0)
+count = graphpas_drw.count()
+logger.info("graphpas_drw has #{count} polygons")
+polygons_count += count
+
+emwind3_drw = get_polygons(90, 0)
+count = emwind3_drw.count()
+logger.info("emwind3_drw has #{count} polygons")
+polygons_count += count
+
+emwihv3_drw = get_polygons(91, 0)
+count = emwihv3_drw.count()
+logger.info("emwihv3_drw has #{count} polygons")
+polygons_count += count
+
+redbulay_drw = get_polygons(92, 0)
+count = redbulay_drw.count()
+logger.info("redbulay_drw has #{count} polygons")
+polygons_count += count
+
+smos_drw = get_polygons(93, 0)
+count = smos_drw.count()
+logger.info("smos_drw has #{count} polygons")
+polygons_count += count
+
+graphpad_drw = get_polygons(97, 0)
+count = graphpad_drw.count()
+logger.info("graphpad_drw has #{count} polygons")
+polygons_count += count
+
+polimide_drw = get_polygons(98, 0)
+count = polimide_drw.count()
+logger.info("polimide_drw has #{count} polygons")
+polygons_count += count
+
+polimide_pin = get_polygons(98, 2)
+count = polimide_pin.count()
+logger.info("polimide_pin has #{count} polygons")
+polygons_count += count
+
+recog_drw = get_polygons(99, 0)
+count = recog_drw.count()
+logger.info("recog_drw has #{count} polygons")
+polygons_count += count
+
+recog_pin = get_polygons(99, 2)
+count = recog_pin.count()
+logger.info("recog_pin has #{count} polygons")
+polygons_count += count
+
+recog_esd = get_polygons(99, 30)
+count = recog_esd.count()
+logger.info("recog_esd has #{count} polygons")
+polygons_count += count
+
+recog_diode = get_polygons(99, 31)
+count = recog_diode.count()
+logger.info("recog_diode has #{count} polygons")
+polygons_count += count
+
+recog_tsv = get_polygons(99, 32)
+count = recog_tsv.count()
+logger.info("recog_tsv has #{count} polygons")
+polygons_count += count
+
+recog_iprobe = get_polygons(99, 33)
+count = recog_iprobe.count()
+logger.info("recog_iprobe has #{count} polygons")
+polygons_count += count
+
+recog_diffprb = get_polygons(99, 34)
+count = recog_diffprb.count()
+logger.info("recog_diffprb has #{count} polygons")
+polygons_count += count
+
+recog_pillar = get_polygons(99, 35)
+count = recog_pillar.count()
+logger.info("recog_pillar has #{count} polygons")
+polygons_count += count
+
+recog_sbump = get_polygons(99, 36)
+count = recog_sbump.count()
+logger.info("recog_sbump has #{count} polygons")
+polygons_count += count
+
+recog_otp = get_polygons(99, 37)
+count = recog_otp.count()
+logger.info("recog_otp has #{count} polygons")
+polygons_count += count
+
+recog_pdiode = get_polygons(99, 38)
+count = recog_pdiode.count()
+logger.info("recog_pdiode has #{count} polygons")
+polygons_count += count
+
+recog_mom = get_polygons(99, 39)
+count = recog_mom.count()
+logger.info("recog_mom has #{count} polygons")
+polygons_count += count
+
+recog_pcm = get_polygons(99, 100)
+count = recog_pcm.count()
+logger.info("recog_pcm has #{count} polygons")
+polygons_count += count
+
+colopen_drw = get_polygons(101, 0)
+count = colopen_drw.count()
+logger.info("colopen_drw has #{count} polygons")
+polygons_count += count
+
+graphmetal1_drw = get_polygons(109, 0)
+count = graphmetal1_drw.count()
+logger.info("graphmetal1_drw has #{count} polygons")
+polygons_count += count
+
+graphmetal1_filler = get_polygons(109, 22)
+count = graphmetal1_filler.count()
+logger.info("graphmetal1_filler has #{count} polygons")
+polygons_count += count
+
+graphmetal1_nofill = get_polygons(109, 23)
+count = graphmetal1_nofill.count()
+logger.info("graphmetal1_nofill has #{count} polygons")
+polygons_count += count
+
+graphmetal1_slit = get_polygons(109, 24)
+count = graphmetal1_slit.count()
+logger.info("graphmetal1_slit has #{count} polygons")
+polygons_count += count
+
+graphmetal1_OPC = get_polygons(109, 26)
+count = graphmetal1_OPC.count()
+logger.info("graphmetal1_OPC has #{count} polygons")
+polygons_count += count
+
+graphmet1l_drw = get_polygons(110, 0)
+count = graphmet1l_drw.count()
+logger.info("graphmet1l_drw has #{count} polygons")
+polygons_count += count
+
+graphmet1l_filler = get_polygons(110, 22)
+count = graphmet1l_filler.count()
+logger.info("graphmet1l_filler has #{count} polygons")
+polygons_count += count
+
+graphmet1l_nofill = get_polygons(110, 23)
+count = graphmet1l_nofill.count()
+logger.info("graphmet1l_nofill has #{count} polygons")
+polygons_count += count
+
+graphmet1l_slit = get_polygons(110, 24)
+count = graphmet1l_slit.count()
+logger.info("graphmet1l_slit has #{count} polygons")
+polygons_count += count
+
+graphmet1l_OPC = get_polygons(110, 26)
+count = graphmet1l_OPC.count()
+logger.info("graphmet1l_OPC has #{count} polygons")
+polygons_count += count
+
+extblock_drw = get_polygons(111, 0)
+count = extblock_drw.count()
+logger.info("extblock_drw has #{count} polygons")
+polygons_count += count
+
+nldd_drw = get_polygons(112, 0)
+count = nldd_drw.count()
+logger.info("nldd_drw has #{count} polygons")
+polygons_count += count
+
+pldd_drw = get_polygons(113, 0)
+count = pldd_drw.count()
+logger.info("pldd_drw has #{count} polygons")
+polygons_count += count
+
+next_drw = get_polygons(114, 0)
+count = next_drw.count()
+logger.info("next_drw has #{count} polygons")
+polygons_count += count
+
+pext_drw = get_polygons(115, 0)
+count = pext_drw.count()
+logger.info("pext_drw has #{count} polygons")
+polygons_count += count
+
+nexthv_drw = get_polygons(116, 0)
+count = nexthv_drw.count()
+logger.info("nexthv_drw has #{count} polygons")
+polygons_count += count
+
+pexthv_drw = get_polygons(117, 0)
+count = pexthv_drw.count()
+logger.info("pexthv_drw has #{count} polygons")
+polygons_count += count
+
+graphgate_drw = get_polygons(118, 0)
+count = graphgate_drw.count()
+logger.info("graphgate_drw has #{count} polygons")
+polygons_count += count
+
+sinwg_drw = get_polygons(119, 0)
+count = sinwg_drw.count()
+logger.info("sinwg_drw has #{count} polygons")
+polygons_count += count
+
+sinwg_filler = get_polygons(119, 22)
+count = sinwg_filler.count()
+logger.info("sinwg_filler has #{count} polygons")
+polygons_count += count
+
+sinwg_nofill = get_polygons(119, 23)
+count = sinwg_nofill.count()
+logger.info("sinwg_nofill has #{count} polygons")
+polygons_count += count
+
+mempad_drw = get_polygons(124, 0)
+count = mempad_drw.count()
+logger.info("mempad_drw has #{count} polygons")
+polygons_count += count
+
+topvia1_drw = get_polygons(125, 0)
+count = topvia1_drw.count()
+logger.info("topvia1_drw has #{count} polygons")
+polygons_count += count
+
+topmetal1_drw = get_polygons(126, 0)
+count = topmetal1_drw.count()
+logger.info("topmetal1_drw has #{count} polygons")
+polygons_count += count
+
+topmetal1_filler = get_polygons(126, 22)
+count = topmetal1_filler.count()
+logger.info("topmetal1_filler has #{count} polygons")
+polygons_count += count
+
+topmetal1_slit = get_polygons(126, 24)
+count = topmetal1_slit.count()
+logger.info("topmetal1_slit has #{count} polygons")
+polygons_count += count
+
+# topmetal1 org
+topmetal1 = topmetal1_drw.join(topmetal1_filler).not(topmetal1_slit)
+count = topmetal1.count()
+logger.info("topmetal1 has #{count} polygons")
+
+topmetal1_pin = get_polygons(126, 2)
+count = topmetal1_pin.count()
+logger.info("topmetal1_pin has #{count} polygons")
+polygons_count += count
+
+topmetal1_mask = get_polygons(126, 20)
+count = topmetal1_mask.count()
+logger.info("topmetal1_mask has #{count} polygons")
+polygons_count += count
+
+topmetal1_nofill = get_polygons(126, 23)
+count = topmetal1_nofill.count()
+logger.info("topmetal1_nofill has #{count} polygons")
+polygons_count += count
+
+topmetal1_text = labels(126, 25)
+count = topmetal1_text.count()
+logger.info("topmetal1_text has #{count} polygons")
+polygons_count += count
+
+topmetal1_noqrc = get_polygons(126, 28)
+count = topmetal1_noqrc.count()
+logger.info("topmetal1_noqrc has #{count} polygons")
+polygons_count += count
+
+topmetal1_res = get_polygons(126, 29)
+count = topmetal1_res.count()
+logger.info("topmetal1_res has #{count} polygons")
+polygons_count += count
+
+topmetal1_iprobe = get_polygons(126, 33)
+count = topmetal1_iprobe.count()
+logger.info("topmetal1_iprobe has #{count} polygons")
+polygons_count += count
+
+topmetal1_diffprb = get_polygons(126, 34)
+count = topmetal1_diffprb.count()
+logger.info("topmetal1_diffprb has #{count} polygons")
+polygons_count += count
+
+inldpwl_drw = get_polygons(127, 0)
+count = inldpwl_drw.count()
+logger.info("inldpwl_drw has #{count} polygons")
+polygons_count += count
+
+polyres_drw = get_polygons(128, 0)
+count = polyres_drw.count()
+logger.info("polyres_drw has #{count} polygons")
+polygons_count += count
+
+polyres_pin = get_polygons(128, 2)
+count = polyres_pin.count()
+logger.info("polyres_pin has #{count} polygons")
+polygons_count += count
+
+vmim_drw = get_polygons(129, 0)
+count = vmim_drw.count()
+logger.info("vmim_drw has #{count} polygons")
+polygons_count += count
+
+nbulaycut_drw = get_polygons(131, 0)
+count = nbulaycut_drw.count()
+logger.info("nbulaycut_drw has #{count} polygons")
+polygons_count += count
+
+antmetal1_drw = get_polygons(132, 0)
+count = antmetal1_drw.count()
+logger.info("antmetal1_drw has #{count} polygons")
+polygons_count += count
+
+topvia2_drw = get_polygons(133, 0)
+count = topvia2_drw.count()
+logger.info("topvia2_drw has #{count} polygons")
+polygons_count += count
+
+topmetal2_drw = get_polygons(134, 0)
+count = topmetal2_drw.count()
+logger.info("topmetal2_drw has #{count} polygons")
+polygons_count += count
+
+topmetal2_filler = get_polygons(134, 22)
+count = topmetal2_filler.count()
+logger.info("topmetal2_filler has #{count} polygons")
+polygons_count += count
+
+topmetal2_slit = get_polygons(134, 24)
+count = topmetal2_slit.count()
+logger.info("topmetal2_slit has #{count} polygons")
+polygons_count += count
+
+# topmetal2 org
+topmetal2 = topmetal2_drw.join(topmetal2_filler).not(topmetal2_slit)
+count = topmetal2.count()
+logger.info("topmetal2 has #{count} polygons")
+
+topmetal2_pin = get_polygons(134, 2)
+count = topmetal2_pin.count()
+logger.info("topmetal2_pin has #{count} polygons")
+polygons_count += count
+
+topmetal2_mask = get_polygons(134, 20)
+count = topmetal2_mask.count()
+logger.info("topmetal2_mask has #{count} polygons")
+polygons_count += count
+
+topmetal2_nofill = get_polygons(134, 23)
+count = topmetal2_nofill.count()
+logger.info("topmetal2_nofill has #{count} polygons")
+polygons_count += count
+
+topmetal2_text = labels(134, 25)
+count = topmetal2_text.count()
+logger.info("topmetal2_text has #{count} polygons")
+polygons_count += count
+
+topmetal2_noqrc = get_polygons(134, 28)
+count = topmetal2_noqrc.count()
+logger.info("topmetal2_noqrc has #{count} polygons")
+polygons_count += count
+
+topmetal2_res = get_polygons(134, 29)
+count = topmetal2_res.count()
+logger.info("topmetal2_res has #{count} polygons")
+polygons_count += count
+
+topmetal2_iprobe = get_polygons(134, 33)
+count = topmetal2_iprobe.count()
+logger.info("topmetal2_iprobe has #{count} polygons")
+polygons_count += count
+
+topmetal2_diffprb = get_polygons(134, 34)
+count = topmetal2_diffprb.count()
+logger.info("topmetal2_diffprb has #{count} polygons")
+polygons_count += count
+
+snsring_drw = get_polygons(135, 0)
+count = snsring_drw.count()
+logger.info("snsring_drw has #{count} polygons")
+polygons_count += count
+
+sensor_drw = get_polygons(136, 0)
+count = sensor_drw.count()
+logger.info("sensor_drw has #{count} polygons")
+polygons_count += count
+
+snsarms_drw = get_polygons(137, 0)
+count = snsarms_drw.count()
+logger.info("snsarms_drw has #{count} polygons")
+polygons_count += count
+
+snscmosvia_drw = get_polygons(138, 0)
+count = snscmosvia_drw.count()
+logger.info("snscmosvia_drw has #{count} polygons")
+polygons_count += count
+
+colwind_drw = get_polygons(139, 0)
+count = colwind_drw.count()
+logger.info("colwind_drw has #{count} polygons")
+polygons_count += count
+
+flm_drw  = get_polygons(142, 0)
+count = flm_drw.count()
+logger.info("flm_drw has #{count} polygons")
+polygons_count += count
+
+hafniumox_drw = get_polygons(143, 0)
+count = hafniumox_drw.count()
+logger.info("hafniumox_drw has #{count} polygons")
+polygons_count += count
+
+memvia_drw = get_polygons(145, 0)
+count = memvia_drw.count()
+logger.info("memvia_drw has #{count} polygons")
+polygons_count += count
+
+thinfilmres_drw = get_polygons(146, 0)
+count = thinfilmres_drw.count()
+logger.info("thinfilmres_drw has #{count} polygons")
+polygons_count += count
+
+rfmem_drw = get_polygons(147, 0)
+count = rfmem_drw.count()
+logger.info("rfmem_drw has #{count} polygons")
+polygons_count += count
+
+norcx_drw = get_polygons(148, 0)
+count = norcx_drw.count()
+logger.info("norcx_drw has #{count} polygons")
+polygons_count += count
+
+norcx_m2m3 = get_polygons(148, 41)
+count = norcx_m2m3.count()
+logger.info("norcx_m2m3 has #{count} polygons")
+polygons_count += count
+
+norcx_m2m4 = get_polygons(148, 42)
+count = norcx_m2m4.count()
+logger.info("norcx_m2m4 has #{count} polygons")
+polygons_count += count
+
+norcx_m2m5 = get_polygons(148, 43)
+count = norcx_m2m5.count()
+logger.info("norcx_m2m5 has #{count} polygons")
+polygons_count += count
+
+norcx_m2tm1 = get_polygons(148, 44)
+count = norcx_m2tm1.count()
+logger.info("norcx_m2tm1 has #{count} polygons")
+polygons_count += count
+
+norcx_m2tm2 = get_polygons(148, 45)
+count = norcx_m2tm2.count()
+logger.info("norcx_m2tm2 has #{count} polygons")
+polygons_count += count
+
+norcx_m3m4 = get_polygons(148, 46)
+count = norcx_m3m4.count()
+logger.info("norcx_m3m4 has #{count} polygons")
+polygons_count += count
+
+norcx_m3m5 = get_polygons(148, 47)
+count = norcx_m3m5.count()
+logger.info("norcx_m3m5 has #{count} polygons")
+polygons_count += count
+
+norcx_m3tm1 = get_polygons(148, 48)
+count = norcx_m3tm1.count()
+logger.info("norcx_m3tm1 has #{count} polygons")
+polygons_count += count
+
+norcx_m3tm2 = get_polygons(148, 49)
+count = norcx_m3tm2.count()
+logger.info("norcx_m3tm2 has #{count} polygons")
+polygons_count += count
+
+norcx_m4m5 = get_polygons(148, 50)
+count = norcx_m4m5.count()
+logger.info("norcx_m4m5 has #{count} polygons")
+polygons_count += count
+
+norcx_m4tm1 = get_polygons(148, 51)
+count = norcx_m4tm1.count()
+logger.info("norcx_m4tm1 has #{count} polygons")
+polygons_count += count
+
+norcx_m4tm2 = get_polygons(148, 52)
+count = norcx_m4tm2.count()
+logger.info("norcx_m4tm2 has #{count} polygons")
+polygons_count += count
+
+norcx_m5tm1 = get_polygons(148, 53)
+count = norcx_m5tm1.count()
+logger.info("norcx_m5tm1 has #{count} polygons")
+polygons_count += count
+
+norcx_m5tm2 = get_polygons(148, 54)
+count = norcx_m5tm2.count()
+logger.info("norcx_m5tm2 has #{count} polygons")
+polygons_count += count
+
+norcx_tm1tm2 = get_polygons(148, 55)
+count = norcx_tm1tm2.count()
+logger.info("norcx_tm1tm2 has #{count} polygons")
+polygons_count += count
+
+norcx_m1sub = get_polygons(148, 123)
+count = norcx_m1sub.count()
+logger.info("norcx_m1sub has #{count} polygons")
+polygons_count += count
+
+norcx_m2sub = get_polygons(148, 124)
+count = norcx_m2sub.count()
+logger.info("norcx_m2sub has #{count} polygons")
+polygons_count += count
+
+norcx_m3sub = get_polygons(148, 125)
+count = norcx_m3sub.count()
+logger.info("norcx_m3sub has #{count} polygons")
+polygons_count += count
+
+norcx_m4sub = get_polygons(148, 126)
+count = norcx_m4sub.count()
+logger.info("norcx_m4sub has #{count} polygons")
+polygons_count += count
+
+norcx_m5sub = get_polygons(148, 127)
+count = norcx_m5sub.count()
+logger.info("norcx_m5sub has #{count} polygons")
+polygons_count += count
+
+norcx_tm1sub = get_polygons(148, 300)
+count = norcx_tm1sub.count()
+logger.info("norcx_tm1sub has #{count} polygons")
+polygons_count += count
+
+norcx_tm2sub = get_polygons(148, 301)
+count = norcx_tm2sub.count()
+logger.info("norcx_tm2sub has #{count} polygons")
+polygons_count += count
+
+snsbotvia_drw = get_polygons(149, 0)
+count = snsbotvia_drw.count()
+logger.info("snsbotvia_drw has #{count} polygons")
+polygons_count += count
+
+snstopvia_drw = get_polygons(151, 0)
+count = snstopvia_drw.count()
+logger.info("snstopvia_drw has #{count} polygons")
+polygons_count += count
+
+deepvia_drw = get_polygons(152, 0)
+count = deepvia_drw.count()
+logger.info("deepvia_drw has #{count} polygons")
+polygons_count += count
+
+fgetch_drw = get_polygons(153, 0)
+count = fgetch_drw.count()
+logger.info("fgetch_drw has #{count} polygons")
+polygons_count += count
+
+ctrgat_drw = get_polygons(154, 0)
+count = ctrgat_drw.count()
+logger.info("ctrgat_drw has #{count} polygons")
+polygons_count += count
+
+fgimp_drw = get_polygons(155, 0)
+count = fgimp_drw.count()
+logger.info("fgimp_drw has #{count} polygons")
+polygons_count += count
+
+emwihv_drw = get_polygons(156, 0)
+count = emwihv_drw.count()
+logger.info("emwihv_drw has #{count} polygons")
+polygons_count += count
+
+lbe_drw  = get_polygons(157, 0)
+count = lbe_drw.count()
+logger.info("lbe_drw has #{count} polygons")
+polygons_count += count
+
+alcustop_drw = get_polygons(159, 0)
+count = alcustop_drw.count()
+logger.info("alcustop_drw has #{count} polygons")
+polygons_count += count
+
+nometfiller_drw = get_polygons(160, 0)
+count = nometfiller_drw.count()
+logger.info("nometfiller_drw has #{count} polygons")
+polygons_count += count
+
+prboundary_drw = get_polygons(189, 0)
+count = prboundary_drw.count()
+logger.info("prboundary_drw has #{count} polygons")
+polygons_count += count
+
+exchange0_drw = get_polygons(190, 0)
+count = exchange0_drw.count()
+logger.info("exchange0_drw has #{count} polygons")
+polygons_count += count
+
+exchange0_pin = get_polygons(190, 2)
+count = exchange0_pin.count()
+logger.info("exchange0_pin has #{count} polygons")
+polygons_count += count
+
+exchange0_text = labels(190, 25)
+count = exchange0_text.count()
+logger.info("exchange0_text has #{count} polygons")
+polygons_count += count
+
+exchange1_drw = get_polygons(191, 0)
+count = exchange1_drw.count()
+logger.info("exchange1_drw has #{count} polygons")
+polygons_count += count
+
+exchange1_pin = get_polygons(191, 2)
+count = exchange1_pin.count()
+logger.info("exchange1_pin has #{count} polygons")
+polygons_count += count
+
+exchange1_text = labels(191, 25)
+count = exchange1_text.count()
+logger.info("exchange1_text has #{count} polygons")
+polygons_count += count
+
+exchange2_drw = get_polygons(192, 0)
+count = exchange2_drw.count()
+logger.info("exchange2_drw has #{count} polygons")
+polygons_count += count
+
+exchange2_pin = get_polygons(192, 2)
+count = exchange2_pin.count()
+logger.info("exchange2_pin has #{count} polygons")
+polygons_count += count
+
+exchange2_text = labels(192, 25)
+count = exchange2_text.count()
+logger.info("exchange2_text has #{count} polygons")
+polygons_count += count
+
+exchange3_drw = get_polygons(193, 0)
+count = exchange3_drw.count()
+logger.info("exchange3_drw has #{count} polygons")
+polygons_count += count
+
+exchange3_pin = get_polygons(193, 2)
+count = exchange3_pin.count()
+logger.info("exchange3_pin has #{count} polygons")
+polygons_count += count
+
+exchange3_text = labels(193, 25)
+count = exchange3_text.count()
+logger.info("exchange3_text has #{count} polygons")
+polygons_count += count
+
+exchange4_drw = get_polygons(194, 0)
+count = exchange4_drw.count()
+logger.info("exchange4_drw has #{count} polygons")
+polygons_count += count
+
+exchange4_pin = get_polygons(194, 2)
+count = exchange4_pin.count()
+logger.info("exchange4_pin has #{count} polygons")
+polygons_count += count
+
+exchange4_text = labels(194, 25)
+count = exchange4_text.count()
+logger.info("exchange4_text has #{count} polygons")
+polygons_count += count
+
+isonwell_drw = get_polygons(257, 0)
+count = isonwell_drw.count()
+logger.info("isonwell_drw has #{count} polygons")
+polygons_count += count
+
+logger.info("Total no. of polygons in the design is #{polygons_count}")
+
+#================================================================
+#------------------------- MAIN RUNSET --------------------------
+#================================================================
+
+logger.info('Starting SG13G2 LVS runset')
+
+#================================================
+#------------- LAYERS DERIVATIONS ---------------
+#================================================
+
+logger.info('Starting base layers derivations')
+
+#==================================
+# ------ GENERAL DERIVATIONS ------
+#==================================
+
+logger.info('Starting general LVS derivations')
+
+#=== Global Layers ===
+# === CHIP ===
+CHIP = case $run_mode
+when 'deep'
+  extent('*')
+else
+  #=== FLAT MODE ===
+  extent.sized(0.0)
+end
+
+# === General Derivations ===
+# nwell
+nwell_iso = nwell_drw.and(nbulay_drw)
+nwell_holes = nwell_drw.holes.not(nwell_drw)
+
+# pwell
+pwell_allowed = CHIP.not(pwell_block)
+digisub_gap = digisub_drw.not(digisub_drw.sized(-1.nm))
+pwell = pwell_allowed.not(nwell_drw).not(digisub_gap)
+
+# General pwell
+pwell_sub = pwell_allowed.not(digisub_drw).not(nbulay_drw.interacting(nwell_holes))
+
+# n & p activ
+nactiv  = activ.not(psd_drw.join(nsd_block))
+pactiv  = activ.and(psd_drw)
+
+# res/cap exclusion
+res_mk        = polyres_drw.join(res_drw)
+poly_con      = gatpoly.not(res_mk)
+metal1_con    = metal1.not(metal1_res)
+metal2_con    = metal2.not(metal2_res)
+metal3_con    = metal3.not(metal3_res)
+metal4_con    = metal4.not(metal4_res)
+metal5_con    = metal5.not(metal5_res)
+topmetal1_con = topmetal1.not(topmetal1_res).not(ind_drw)
+topmetal2_con = topmetal2.not(topmetal2_res).not(ind_drw)
+
+# Gate FETs
+tgate   = gatpoly.and(activ).not(res_mk)
+ngate   = nactiv.and(tgate)
+pgate   = pactiv.and(tgate)
+ngate_lv_base = ngate.not(thickgateox_drw)
+pgate_lv_base = pgate.not(thickgateox_drw)
+ngate_hv_base = ngate.and(thickgateox_drw)
+pgate_hv_base = pgate.and(thickgateox_drw)
+
+# S/D FETs
+nsd_fet = nactiv.not(nwell_drw).interacting(ngate).not(ngate).not_interacting(res_mk)
+psd_fet = pactiv.and(nwell_drw).interacting(pgate).not(pgate).not_interacting(res_mk)
+
+
+# n1/p1 taps labels
+well_patt = glob_to_case_insensitive_glob("well")
+sub_patt = glob_to_case_insensitive_glob("sub!")
+
+ntap1_lbl = text_drw.texts(well_patt)
+ntap1_mk = nwell_drw.interacting(ntap1_lbl)
+
+ptap1_lbl = text_drw.texts(sub_patt)
+ptap1_mk = substrate_drw.and(pwell).interacting(ptap1_lbl)
+
+# n & p taps (short connections)
+ntap = nactiv.and(nwell_drw).not(recog_diode).not(gatpoly).not(ntap1_mk)
+ptap = pactiv.and(pwell).not(ptap1_mk).not(recog_diode).not(gatpoly)
+ptap_holes = ptap.holes
+ntap_holes = ntap.holes
+
+# S/D (salicide)
+nsd_sal = nsd_fet.not(salblock_drw)
+psd_sal = psd_fet.not(salblock_drw)
+
+# n & p taps (salicide)
+ntap_sal = ntap.not(salblock_drw)
+ptap_sal = ptap.not(salblock_drw)
+
+# n/p SD abutted with n/p taps (salicide)
+nsd_ptap_abutt = nsd_sal.edges.and(ptap_sal.edges).extended(:in => 1.nm, :out => 1.nm)
+psd_ntap_abutt = psd_sal.edges.and(ntap_sal.edges).extended(:in => 1.nm, :out => 1.nm)
+
+#==================================
+# ------ MOSFET DERIVATIONS -------
+#==================================
+
+logger.info('Starting MOSFET DERIVATIONS')
+
+mos_exclude = pwell_block.join(nsd_drw).join(trans_drw)
+                .join(emwind_drw).join(emwihv_drw).join(salblock_drw)
+                .join(polyres_drw).join(extblock_drw).join(res_drw)
+                .join(activ_mask).join(recog_diode).join(recog_esd)
+                .join(ind_drw).join(ind_pin).join(ind_drw)
+                .join(substrate_drw).join(nsd_block)
+
+# ==== General FETs & RF-FETs =====
+
+rfnmos_exc = nwell_drw.join(psd_drw).join(mos_exclude)
+rfpmos_exc = pwell.join(nwell_holes).join(mos_exclude)
+
+# Get case insensitive patterns for FETs
+rfnmos_patt = glob_to_case_insensitive_glob("rfnmos")
+rfnmoshv_patt = glob_to_case_insensitive_glob("rfnmosHV")
+
+rfpmos_patt = glob_to_case_insensitive_glob("rfpmos")
+rfpmoshv_patt = glob_to_case_insensitive_glob("rfpmosHV")
+
+rfnmos_mk_gen = ptap.join(ptap_holes)
+rfnmos_mk = rfnmos_mk_gen.interacting(text_drw.texts(rfnmos_patt))
+rfnmoshv_mk = rfnmos_mk_gen.interacting(text_drw.texts(rfnmoshv_patt))
+
+rfpmos_mk_gen = ntap.join(ntap_holes)
+rfpmos_mk = rfpmos_mk_gen.interacting(text_drw.texts(rfpmos_patt))
+rfpmoshv_mk = rfpmos_mk_gen.interacting(text_drw.texts(rfpmoshv_patt))
+
+# ==============
+# ---- NMOS ----
+# ==============
+
+logger.info('Starting NMOS DERIVATIONS')
+
+# for regular FETs
+nmos_exc = rfnmos_exc.join(rfnmos_mk)
+nmoshv_exc = rfnmos_exc.join(rfnmoshv_mk)
+
+# nmos - LV
+ngate_lv = ngate_lv_base.not(nmos_exc)
+
+# nmos - HV
+ngate_hv = ngate_hv_base.not(nmoshv_exc)
+
+# ==============
+# ---- PMOS ----
+# ==============
+
+logger.info('Starting PMOS DERIVATIONS')
+
+# for regular FETs
+pmos_exc = rfpmos_exc.join(rfpmos_mk)
+pmoshv_exc = rfpmos_exc.join(rfpmoshv_mk)
+
+# pmos - LV
+pgate_lv = pgate_lv_base.not(pmos_exc)
+
+# pmos - HV
+pgate_hv = pgate_hv_base.not(pmoshv_exc)
+
+#==================================
+# ----- RF-MOSFET DERIVATIONS -----
+#==================================
+
+logger.info('Starting RF-MOSFET DERIVATIONS')
+
+# ===============
+# --- RF-NMOS ---
+# ===============
+
+logger.info('Starting RF-NMOS DERIVATIONS')
+
+
+# rfnmos - LV
+rfngate_lv = ngate_lv_base.and(rfnmos_mk).not(rfnmos_exc)
+
+# rfnmos - HV
+rfngate_hv = ngate_hv_base.and(rfnmoshv_mk).not(rfnmos_exc)
+
+# ===============
+# --- RF-PMOS ---
+# ===============
+
+logger.info('Starting RF-PMOS DERIVATIONS')
+
+# rfpmos - LV
+rfpgate_lv = pgate_lv_base.and(rfpmos_mk).not(rfpmos_exc)
+
+# rfpmos - HV
+rfpgate_hv = pgate_hv_base.and(rfpmoshv_mk).not(rfpmos_exc)
+
+#================================
+# ------ BJT DERIVATIONS --------
+#================================
+
+logger.info('Starting BJT DERIVATIONS')
+
+# =============
+# ---- NPN ----
+# =============
+
+logger.info('Starting NPN-BJT DERIVATIONS')
+
+bjt_exclude = gatpoly.join(pwell_block).join(nsd_drw)
+                .join(salblock_drw).join(polyres_drw).join(extblock_drw)
+                .join(res_drw).join(recog_diode).join(recog_esd)
+                .join(ind_drw).join(ind_pin).join(substrate_drw)
+
+npn_exclude = nwell_drw.join(psd_drw).join(nbulay_drw).join(bjt_exclude)
+
+# ---------- General NPN ----------
+npn_mk = trans_drw.and(pwell).and(ptap_holes)
+npn_c_exc = emwind_drw.join(emwihv_drw).join(activ_mask)
+            .join(nsd_block).join(npn_exclude)
+npn_b_exc = emwind_drw.join(emwihv_drw).join(npn_exclude)
+npn_sub = npn_mk.not(npn_exclude)
+npn_dev = activ.join(activ_mask).and(npn_mk)
+
+# ---------- npn13G2 ----------
+# npn13G2 exclusion layers
+npn13G2_e_exc = activ.join(emwihv_drw).join(npn_exclude)
+npn13G2_b_exc = npn_b_exc.join(activ_mask)
+
+# npn13G2 nodes
+npn13G2_e_ = emwind_drw.and(activ_mask).and(nsd_block).and(npn_mk).not(npn13G2_e_exc)
+# npn13G2 is a fixed device (0.07um X 0.9um)
+npn13G2_e_pin = npn13G2_e_.with_bbox_min(0.07.um).with_bbox_max(0.9.um).with_area(0.063.um)
+npn13G2_b_pin = nsd_block.and(npn_mk).not(npn13G2_b_exc)
+npn13G2_c_pin = activ.and(npn_mk).not_overlapping(npn_c_exc)
+
+npn13G2_dev = npn_dev.join(nsd_block).extents.covering(npn13G2_e_pin).covering(npn13G2_b_pin).covering(npn13G2_c_pin)
+npn13G2_c = npn13G2_dev.sized(-1.nm)
+npn13G2_tc = npn13G2_dev.not(npn13G2_c).interacting(npn13G2_c_pin)
+npn13G2_b = npn13G2_dev.not(npn13G2_c_pin)
+npn13G2_tb = npn13G2_b.not(npn13G2_e_pin).merged
+npn13G2_e = npn13G2_e_pin
+npn13G2_te = npn13G2_e
+
+# ---------- npn13G2L ----------
+# npn13G2L exclusion layers
+npn13G2l_e_exc = activ_mask.join(nsd_block).join(emwihv_drw).join(npn_exclude)
+npn13G2l_b_exc = npn_b_exc.join(activ).join(nsd_block)
+
+# npn13G2L nodes
+npn13G2l_e_ = emwind_drw.and(activ).and(npn_mk).not(npn13G2l_e_exc)
+# npn13G2L has fixed width (0.07um), Length could vary from 1:2.5 um
+npn13G2l_e_pin = npn13G2l_e_.with_bbox_min(0.07.um).with_bbox_max(1.um, 2.5.um).with_area(0.07.um, 0.175.um)
+npn13G2l_b_pin = activ_mask.and(npn_mk).not(npn13G2l_b_exc)
+npn13G2l_c_pin = npn13G2_c_pin
+
+npn13G2l_dev = npn_dev.covering(npn13G2l_e_pin).covering(npn13G2l_b_pin).covering(npn13G2l_c_pin)
+npn13G2l_c = npn13G2l_dev.sized(1.nm)
+npn13G2l_tc = npn13G2l_c.not(npn13G2l_dev).interacting(npn13G2l_c_pin)
+npn13G2l_b = npn13G2l_dev.not(npn13G2l_c_pin)
+npn13G2l_tb = npn13G2l_b.not(npn13G2l_e_pin).merged
+npn13G2l_e = npn13G2l_e_pin
+npn13G2l_te = npn13G2l_e
+
+# # ---------- npn13G2V ----------
+# npn13G2V exclusion layers
+npn13G2v_e_exc = activ_mask.join(nsd_block).join(emwind_drw).join(npn_exclude)
+
+# npn13G2V nodes
+npn13G2v_e_ = emwihv_drw.and(activ).and(npn_mk).not(npn13G2v_e_exc)
+# npn13G2L has fixed width (0.12um), Length could vary from 1:5 um
+npn13G2v_e_pin = npn13G2v_e_.with_bbox_min(0.12.um).with_bbox_max(1.um, 5.um).with_area(0.12.um, 0.6.um)
+npn13G2v_b_pin = npn13G2l_b_pin
+npn13G2v_c_pin = npn13G2l_c_pin
+
+npn13G2v_dev = npn_dev.covering(npn13G2v_e_pin).covering(npn13G2v_b_pin).covering(npn13G2v_c_pin)
+npn13G2v_c = npn13G2v_dev.sized(1.nm)
+npn13G2v_tc = npn13G2v_c.not(npn13G2v_dev).interacting(npn13G2v_c_pin)
+npn13G2v_b = npn13G2v_dev.not(npn13G2v_c_pin)
+npn13G2v_tb = npn13G2v_b.not(npn13G2v_e_pin).merged
+npn13G2v_e = npn13G2v_e_pin
+npn13G2v_te = npn13G2v_e
+
+# =============
+# ---- PNP ----
+# =============
+
+logger.info('Starting PNP-BJT DERIVATIONS')
+
+pnp_exclude = trans_drw.join(emwind_drw)
+                .join(emwihv_drw).join(nsd_block).join(bjt_exclude)
+
+pnp_mk = ptap_holes.not(pnp_exclude)
+
+# pnp general nodes DERIVATIONS
+pnp_e = pactiv.and(pnp_mk).and(nwell_iso)
+pnp_b = nactiv.and(pnp_mk).and(nwell_iso)
+pnp_c = ptap.interacting(pnp_mk).not(pnp_exclude)
+
+# pnp_mpa nodes DERIVATIONS
+pnp_mpa_e = pnp_e.and(pnp_b.extents).and(pnp_c.extents)
+pnp_mpa_b = pnp_b.interacting(pnp_b.extents.interacting(pnp_mpa_e))
+pnp_mpa_c = pnp_c.interacting(pnp_c.extents.interacting(pnp_mpa_e))
+
+#================================
+# ----- DIODE DERIVATIONS -------
+#================================
+
+logger.info('Starting DIODE DERIVATIONS')
+
+diode_exclude = gatpoly.join(nsd_drw).join(trans_drw)
+                .join(emwind_drw).join(emwihv_drw).join(polyres_drw)
+                .join(extblock_drw).join(res_drw).join(activ_mask)
+                .join(recog_esd).join(ind_drw).join(ind_pin)
+                .join(substrate_drw)
+
+antenna_d_exc = pwell_block.join(salblock_drw)
+                .join(nsd_block).join(diode_exclude)
+
+antenna_d_mk = recog_diode.not(antenna_d_exc)
+
+# ==== dantenna diode ====
+dantenna_n = activ.and(antenna_d_mk).not(psd_drw).not(nwell_drw)
+dantenna_p = pwell.and(antenna_d_mk).covering(dantenna_n)
+
+# ==== dpantenna diode ====
+dpantenna_p = pactiv.and(antenna_d_mk)
+dpantenna_n = nwell_drw.covering(dpantenna_p)
+
+# ==== schottky_nbl1 diode ====
+schottky_mk = recog_diode.and(thickgateox_drw).not(diode_exclude)
+                .and(pwell_block).and(ptap_holes).and(nbulay_drw)
+                .and(salblock_drw).and(nsd_block).and(nwell_holes)
+                .not(psd_drw).not(pwell).not(diode_exclude)
+
+schottcky_p_ = cont_drw.and(activ).and(metal1_con)
+                .and(schottky_mk)
+
+# schottky_nbl1 is a fixed device (0.3um X 1.0 um)
+schottcky_p = schottcky_p_.with_bbox_min(0.3.um).with_bbox_max(1.0.um)
+# Using box with area 1x1 to be used as a reference to (m)
+schottcky_p_1x1 = schottcky_p.middle(as_boxes).sized(0.499.um)
+
+schottcky_n = nsd_block.and(activ).covering(schottcky_p)
+
+# define port for schottcky
+schottcky_n_port = activ.interacting(nwell_iso).interacting(schottcky_n).not(schottcky_n.sized(-1.nm))
+schottcky_n_con = cont_drw.and(schottcky_n_port).not_interacting(schottcky_p)
+schottcky_sub = ptap.extents.covering(schottcky_p).covering(schottcky_n)
+
+#================================
+# ---- RESISTOR DERIVATIONS -----
+#================================
+
+logger.info('Starting RESISTOR DERIVATIONS')
+
+polyres_exclude = activ.join(pwell_block).join(nsd_block)
+                    .join(nbulay_drw).join(thickgateox_drw).join(trans_drw)
+                    .join(emwind_drw).join(emwihv_drw).join(activ_mask)
+                    .join(recog_diode).join(recog_esd).join(ind_drw)
+                    .join(ind_pin).join(substrate_drw)
+
+# ==============
+# ---- POLY ----
+# ==============
+
+## polyres
+polyres_mk = polyres_drw.and(extblock_drw).interacting(gatpoly).not(polyres_exclude)
+
+## rhigh
+rhigh_res = polyres_mk.and(psd_drw).and(nsd_drw).and(salblock_drw)
+rhigh_ports = gatpoly.interacting(rhigh_res).not(rhigh_res)
+
+## rppd
+rppd_res = polyres_mk.and(psd_drw).and(salblock_drw).not(nsd_block).not(nsd_drw)
+rppd_ports = gatpoly.interacting(rppd_res).not(rppd_res)
+
+## rsil
+rsil_exc = psd_drw.join(salblock_drw).join(nsd_drw).join(nsd_block)
+rsil_res = polyres_mk.and(res_drw).not(rsil_exc)
+rsil_ports = gatpoly.interacting(rsil_res).not(rsil_res)
+
+# ===============
+# ---- METAL ----
+# ===============
+
+# res_metal1
+res_metal1 = metal1.and(metal1_res)
+
+# res_metal2
+res_metal2 = metal2.and(metal2_res)
+
+# res_metal3
+res_metal3 = metal3.and(metal3_res)
+
+# res_metal4
+res_metal4 = metal4.and(metal4_res)
+
+# res_metal5
+res_metal5 = metal5.and(metal5_res)
+
+# res_topmetal1
+res_topmetal1 = topmetal1.and(topmetal1_res)
+
+# res_topmetal2
+res_topmetal2 = topmetal2.and(topmetal2_res)
+
+#==================================
+# -------- CAP DERIVATIONS --------
+#==================================
+
+logger.info('Starting CAP DERIVATIONS')
+
+rfmimcap_exc = ind_drw.join(ind_pin)
+
+# === MIMCAP ===
+mimcap_exclude = pwell_block.join(rfmimcap_exc)
+
+mim_top = mim_drw.overlapping(topmetal1_con).and(metal5_con)
+mim_btm = metal5_con.and(mim_drw).sized(0.6.um)
+mim_via = vmim_drw.join(topvia1_drw).and(mim_drw)
+topvia1_n_cap = topvia1_drw.not(mim_via)
+
+# === cap_cmim ===
+cmim_top = mim_top.not(mimcap_exclude)
+cmim_btm = mim_btm.covering(cmim_top)
+cmim_dev = mim_drw.covering(cmim_top).and(cmim_btm)
+
+# === rfcmim ===
+rfmim_area = pwell_block.interacting(mim_drw)
+rfmim_top = mim_top.and(rfmim_area).not(rfmimcap_exc)
+rfmim_btm = mim_btm.and(rfmim_area).covering(rfmim_top)
+rfmim_dev = mim_drw.covering(rfmim_top).and(rfmim_btm)
+rfmim_sub = ptap.extents.interacting(rfmim_area)
+rfmeas_mk = metal5_con.overlapping(rfmim_btm).and(rfmim_area)
+
+# === svaricap ===
+cap_exc = nsd_drw.join(trans_drw).join(emwind_drw)
+            .join(emwihv_drw).join(salblock_drw).join(polyres_drw)
+            .join(extblock_drw).join(res_drw).join(activ_mask)
+            .join(recog_diode).join(recog_esd).join(ind_drw)
+            .join(ind_pin).join(substrate_drw)
+
+varicap_exc = pwell.join(pwell_block).join(nwell_holes).join(cap_exc)
+
+varicap_core = ngate_hv_base.and(nwell_iso).not(varicap_exc)
+varicap_diff_port = nactiv.interacting(varicap_core).not(varicap_core)
+                    .and(nwell_iso).not(varicap_exc).sized(-1.nm)
+varicap_poly_port = gatpoly.interacting(varicap_core)
+varicap_ports = varicap_poly_port.join(varicap_diff_port)
+varicap_sub = ptap.and(thickgateox_drw)
+varicap_dev_mk = thickgateox_drw.covering(varicap_core).interacting(varicap_ports)
+
+#================================
+# ------ ESD DERIVATIONS --------
+#================================
+
+logger.info('Starting ESD DERIVATIONS')
+
+# General
+esd_exclude = nsd_block.join(nsd_drw).join(trans_drw)
+                .join(emwind_drw).join(emwihv_drw).join(polyres_drw)
+                .join(extblock_drw).join(res_drw).join(substrate_drw)
+                .join(ind_drw).join(ind_pin)
+
+esd_exc_d = gatpoly.join(thickgateox_drw).join(salblock_drw)
+            .join(esd_exclude)
+
+idiodevdd_exc = esd_exc_d.join(nwell_holes)
+diodevdd_exc = idiodevdd_exc.join(nbulay_drw).join(pwell_block)
+
+idiodevss_exc = esd_exc_d.join(nwell_drw.not_interacting(nwell_holes))
+                .join(pwell_block)
+diodevss_exc = idiodevss_exc.join(nbulay_drw)
+
+nw_diode = nwell_drw.not_interacting(pwell_block)
+nw_idiode = nwell_iso.interacting(pwell_block)
+
+#======================
+# ----- diode-ESD -----
+#======================
+
+# diodevdd_2kv
+diodevdd_2kv_e = pactiv.and(nw_diode).and(recog_esd).not(diodevdd_exc)
+diodevdd_2kv_e_1x1 = diodevdd_2kv_e.middle.sized(0.499.um)
+diodevdd_2kv_b_ = nactiv.and(nw_diode).and(recog_esd).not(diodevdd_exc)
+diodevdd_2kv_b = diodevdd_2kv_b_.interacting(diodevdd_2kv_b_.extents.interacting(diodevdd_2kv_e, 1, 1))
+diodevdd_2kv_tb = cont_drw.and(diodevdd_2kv_b).not_interacting(diodevdd_2kv_e)
+diodevdd_2kv_c_ = pactiv.and(pwell).and(recog_esd).not(diodevdd_exc)
+diodevdd_2kv_c = diodevdd_2kv_c_.interacting(diodevdd_2kv_c_.extents.interacting(diodevdd_2kv_b, 1, 1))
+
+# diodevdd_4kv
+diodevdd_4kv_b = diodevdd_2kv_b_.interacting(diodevdd_2kv_b_.extents.interacting(diodevdd_2kv_e, 2, 2))
+diodevdd_4kv_c = diodevdd_2kv_c_.interacting(diodevdd_2kv_c_.extents.interacting(diodevdd_4kv_b, 1, 1))
+diodevdd_4kv_e = diodevdd_4kv_b.extents.sized(-0.15.um)
+diodevdd_4kv_e_1x1 = diodevdd_4kv_e.middle.sized(0.499.um)
+diodevdd_4kv_te = cont_drw.and(diodevdd_2kv_e).not_interacting(diodevdd_4kv_b)
+diodevdd_4kv_tb = cont_drw.and(diodevdd_4kv_b).not_interacting(diodevdd_2kv_e)
+
+# diodevss_2kv
+diodevss_2kv_e = nactiv.and(pwell).and(recog_esd).not(diodevss_exc)
+diodevss_2kv_e_1x1 = diodevss_2kv_e.middle.sized(0.499.um)
+diodevss_2kv_b_ = pactiv.and(pwell).and(recog_esd).not(diodevss_exc)
+diodevss_2kv_b = diodevss_2kv_b_.interacting(diodevss_2kv_b_.extents.interacting(diodevss_2kv_e, 1, 1))
+diodevss_2kv_tb = cont_drw.and(diodevss_2kv_b).not_interacting(diodevss_2kv_e)
+diodevss_2kv_c_ = nactiv.and(nw_diode).and(recog_esd).not(diodevss_exc)
+diodevss_2kv_c = diodevss_2kv_c_.interacting(diodevss_2kv_c_.extents.interacting(diodevss_2kv_b, 1, 1))
+
+# diodevss_4kv
+diodevss_4kv_b = diodevss_2kv_b_.interacting(diodevss_2kv_b_.extents.interacting(diodevss_2kv_e, 2, 2))
+diodevss_4kv_c = diodevss_2kv_c_.interacting(diodevss_2kv_c_.extents.interacting(diodevss_4kv_b, 1, 1))
+diodevss_4kv_e = diodevss_4kv_b.extents.sized(-0.15.um)
+diodevss_4kv_e_1x1 = diodevss_4kv_e.middle.sized(0.499.um)
+diodevss_4kv_te = cont_drw.and(diodevss_2kv_e).not_interacting(diodevss_4kv_b)
+diodevss_4kv_tb = cont_drw.and(diodevss_4kv_b).not_interacting(diodevss_2kv_e)
+
+#=======================
+# ----- idiode-ESD -----
+#=======================
+
+# idiodevdd_2kv
+idiodevdd_2kv_e = pactiv.and(nw_idiode).and(recog_esd).not(idiodevdd_exc)
+idiodevdd_2kv_e_1x1 = idiodevdd_2kv_e.middle.sized(0.499.um)
+idiodevdd_2kv_b_ = nactiv.and(nw_idiode).and(recog_esd).not(idiodevdd_exc)
+idiodevdd_2kv_b = idiodevdd_2kv_b_.interacting(idiodevdd_2kv_b_.extents.interacting(idiodevdd_2kv_e, 1, 1))
+idiodevdd_2kv_tb = cont_drw.and(idiodevdd_2kv_b).not_interacting(idiodevdd_2kv_e)
+idiodevdd_2kv_c_ = pactiv.and(pwell).and(recog_esd).not(idiodevdd_exc)
+idiodevdd_2kv_c = idiodevdd_2kv_c_.interacting(idiodevdd_2kv_c_.extents.interacting(idiodevdd_2kv_b, 1, 1))
+
+# idiodevdd_4kv
+idiodevdd_4kv_b = idiodevdd_2kv_b_.interacting(idiodevdd_2kv_b_.extents.interacting(idiodevdd_2kv_e, 2, 2))
+idiodevdd_4kv_c = idiodevdd_2kv_c_.interacting(idiodevdd_2kv_c_.extents.interacting(idiodevdd_4kv_b, 1, 1))
+idiodevdd_4kv_e = idiodevdd_4kv_b.extents.sized(-0.15.um)
+idiodevdd_4kv_e_1x1 = idiodevdd_4kv_e.middle.sized(0.499.um)
+idiodevdd_4kv_te = cont_drw.and(idiodevdd_2kv_e).not_interacting(idiodevdd_4kv_b)
+idiodevdd_4kv_tb = cont_drw.and(idiodevdd_4kv_b).not_interacting(idiodevdd_2kv_e)
+
+# idiodevss_2kv
+idiodevss_2kv_e = nactiv.and(pwell).and(nbulay_drw).and(recog_esd).not(idiodevss_exc)
+idiodevss_2kv_e_1x1 = idiodevss_2kv_e.middle.sized(0.499.um)
+idiodevss_2kv_b_ = pactiv.and(pwell).and(nbulay_drw).and(recog_esd).not(idiodevss_exc)
+idiodevss_2kv_b = idiodevss_2kv_b_.interacting(idiodevss_2kv_b_.extents.interacting(idiodevss_2kv_e, 1, 1))
+idiodevss_2kv_tb = cont_drw.and(idiodevss_2kv_b).not_interacting(idiodevss_2kv_e)
+idiodevss_2kv_c_ = nactiv.and(nwell_iso).and(recog_esd).not(idiodevss_exc)
+idiodevss_2kv_c = idiodevss_2kv_c_.interacting(idiodevss_2kv_c_.extents.interacting(idiodevss_2kv_b, 1, 1))
+
+# idiodevss_4kv
+idiodevss_4kv_b = idiodevss_2kv_b_.interacting(idiodevss_2kv_b_.extents.interacting(idiodevss_2kv_e, 2, 2))
+idiodevss_4kv_c = idiodevss_2kv_c_.interacting(idiodevss_2kv_c_.extents.interacting(idiodevss_4kv_b, 1, 1))
+idiodevss_4kv_e = idiodevss_4kv_b.extents.sized(-0.15.um)
+idiodevss_4kv_e_1x1 = idiodevss_4kv_e.middle.sized(0.499.um)
+idiodevss_4kv_te = cont_drw.and(idiodevss_2kv_e).not_interacting(idiodevss_4kv_b)
+idiodevss_4kv_tb = cont_drw.and(idiodevss_4kv_b).not_interacting(idiodevss_2kv_e)
+
+#======================
+# ----- MOSCL-ESD -----
+#======================
+
+nmoscl_exc = esd_exclude.join(pwell_block)
+
+# nmoscl_2
+nmoscl_2_patt = glob_to_case_insensitive_glob("nmoscl_2")
+
+gate_moscl = ngate_hv_base.and(salblock_drw).and(nbulay_drw)
+nmoscl_2_n_ = recog_esd.interacting(text_drw.texts(nmoscl_2_patt))
+nmoscl_2_n = nmoscl_2_n_.interacting(gate_moscl, 12)
+nmoscl_2_n_port = nwell_drw.and(nmoscl_2_n)
+nmoscl_2_p_ = ptap.and(nbulay_drw).inside(nmoscl_2_n_)
+# Using box with area 1x1 to be used as a reference to (m)
+nmoscl_2_p =nmoscl_2_p_.middle(as_boxes).sized(0.499.um)
+
+# nmoscl_4
+nmoscl_4_patt = glob_to_case_insensitive_glob("nmoscl_4")
+
+gate_moscl = ngate_hv_base.and(salblock_drw).and(nbulay_drw)
+nmoscl_4_n_ = recog_esd.interacting(text_drw.texts(nmoscl_4_patt))
+nmoscl_4_n = nmoscl_4_n_.interacting(gate_moscl, 24)
+nmoscl_4_n_port = nwell_drw.and(nmoscl_4_n)
+nmoscl_4_p_ = ptap.and(nbulay_drw).inside(nmoscl_4_n_)
+# Using box with area 1x1 to be used as a reference to (m)
+nmoscl_4_p =nmoscl_4_p_.middle(as_boxes).sized(0.499.um)
+
+#===============================
+# ---- Inductor DERIVATIONS ----
+#===============================
+
+logger.info('Starting Inductor DERIVATIONS')
+
+ind_exc = gatpoly.join(nsd_drw).join(nbulay_drw)
+            .join(thickgateox_drw).join(emwind_drw).join(emwihv_drw)
+            .join(salblock_drw).join(polyres_drw).join(mim_drw)
+            .join(extblock_drw).join(res_drw).join(activ_mask)
+            .join(recog_diode).join(recog_esd).join(substrate_drw)
+
+# General
+la_patt = glob_to_case_insensitive_glob("LA")
+lb_patt = glob_to_case_insensitive_glob("LB")
+lc_patt = glob_to_case_insensitive_glob("LC")
+ind2_patt = glob_to_case_insensitive_glob("inductor2*")
+ind3_patt = glob_to_case_insensitive_glob("inductor3*")
+
+ind_edges = ind_drw.edges
+ind_core_ = topmetal2.join(topmetal1).and(ind_drw).merged.not(ind_exc)
+ind_ports_ = ind_pin.and(ind_core_).interacting(ind_edges)
+ind_port_la = ind_ports_.interacting(ind_text.texts(la_patt))
+ind_la_tm1 = ind_port_la.and(topmetal1)
+ind_port_lb = ind_ports_.interacting(ind_text.texts(lb_patt))
+ind_lb_tm1 = ind_port_lb.and(topmetal1)
+ind_port_lc = ind_ports_.interacting(ind_text.texts(lc_patt))
+ind_lc_tm2 = ind_port_lc.and(topmetal2)
+
+# inductor2
+ind2_ports = ind_port_la.join(ind_port_lb)
+ind2_core = ind_core_.interacting(ind_port_la, 1).interacting(ind_port_lb, 1)
+ind2_mk_ = ind_drw.interacting(text_drw.texts(ind2_patt))
+ind2_mk = ind2_mk_.interacting(ind2_core).interacting(ind2_ports).not_interacting(ind_port_lc)
+ind2_sub1 = pwell.and(ind_drw).interacting(ind2_core)
+ind2_sub2 = pwell_block.and(ind_drw).interacting(ind2_core).sized(1.nm)
+ind2_well = nwell_drw.and(ind_drw).interacting(ind2_core).sized(-1.nm)
+ind2_sub = ind2_sub1.join(ind2_sub2).join(ind2_well)
+# inductor3
+ind3_ports = ind_la_tm1.join(ind_lb_tm1).join(ind_lc_tm2)
+ind3_core = ind_core_.interacting(ind_lb_tm1, 1).interacting(ind_lb_tm1, 1).interacting(ind_lc_tm2, 1)
+ind3_mk_ = ind_drw.interacting(text_drw.texts(ind3_patt))
+ind3_mk = ind3_mk_.interacting(ind3_core).interacting(ind3_ports)
+ind3_sub1 = pwell.and(ind_drw).interacting(ind3_core)
+ind3_sub2 = pwell_block.and(ind_drw).interacting(ind3_core).sized(1.nm)
+ind3_well = nwell_drw.and(ind_drw).interacting(ind3_core).sized(-1.nm)
+ind3_sub = ind3_sub1.join(ind3_sub2).join(ind3_well)
+
+#===============================
+# ------ Taps DERIVATIONS ------
+#===============================
+
+logger.info('Starting Taps DERIVATIONS')
+
+taps_exclude = gatpoly.join(nsd_drw).join(trans_drw)
+                .join(emwind_drw).join(emwihv_drw).join(salblock_drw)
+                .join(polyres_drw).join(extblock_drw).join(res_drw)
+                .join(activ_mask).join(recog_diode).join(recog_esd)
+                .join(ind_drw).join(ind_pin)
+
+# === ntap1 ===
+ntap1_exc = pwell.join(psd_drw).join(taps_exclude)
+
+ntap1_tie = nactiv.and(ntap1_mk).extents.not(ntap1_exc)
+ntap1_well = ntap1_mk.covering(ntap1_tie)
+
+# === ptap1 ===
+ptap1_exc = nwell_drw.join(taps_exclude)
+
+ptap1_tie = pactiv.and(ptap1_mk).extents.not(ptap1_exc)
+ptap1_sub = pwell.covering(ptap1_tie)
+
+#================================================
+#------------ DEVICES CONNECTIVITY --------------
+#================================================
+
+logger.info('Starting GF180 LVS connectivity setup')
+
+#================================
+# ----- GENERAL CONNECTIONS -----
+#================================
+
+logger.info('Starting GF180 LVS connectivity setup (Inter-layer)')
+
+# Inter-layer
+connect(pwell_sub, pwell)
+connect(pwell, ptap)
+connect(nwell_drw, ntap)
+connect(ntap, cont_drw)
+connect(ptap, cont_drw)
+connect(poly_con, cont_drw)
+connect(nsd_fet, cont_drw)
+connect(psd_fet, cont_drw)
+connect(cont_drw, metal1_con)
+connect(metal1_con, via1_drw)
+connect(via1_drw, metal2_con)
+connect(metal2_con, via2_drw)
+connect(via2_drw, metal3_con)
+connect(metal3_con, via3_drw)
+connect(via3_drw, metal4_con)
+connect(metal4_con, via4_drw)
+connect(via4_drw, metal5_con)
+connect(metal5_con, topvia1_n_cap)
+connect(topvia1_n_cap, topmetal1_con)
+connect(topmetal1_con, topvia2_drw)
+connect(topvia2_drw, topmetal2_con)
+
+# salicide connection 
+connect(nsd_fet, nsd_ptap_abutt)
+connect(nsd_ptap_abutt, ptap)
+connect(psd_fet, psd_ntap_abutt)
+connect(psd_ntap_abutt, ntap)
+
+# Attaching labels
+connect(metal1_con, metal1_text)
+connect(metal2_con, metal2_text)
+connect(metal3_con, metal3_text)
+connect(metal4_con, metal4_text)
+connect(metal5_con, metal5_text)
+connect(topmetal1_con, topmetal1_text)
+connect(topmetal2_con, topmetal2_text)
+
+logger.info('Starting SG13G2 LVS connectivity setup (Global)')
+
+#================================
+# ----- MOSFET CONNECTIONS ------
+#================================
+
+logger.info('Starting LVS MOSFET CONNECTIONS')
+# Covered in general connections
+
+#================================
+# ---- RF-MOSFET CONNECTIONS ----
+#================================
+
+logger.info('Starting LVS RF-MOSFET CONNECTIONS')
+# Covered in general connections
+
+#================================
+# ------ BJT CONNECTIONS --------
+#================================
+
+logger.info('Starting LVS BJT CONNECTIONS')
+
+# =============
+# ---- NPN ----
+# =============
+
+# General
+connect(npn_sub, pwell)
+
+# npn13G2 nodes connections
+connect(npn13G2_te, npn13G2_e_pin)
+connect(npn13G2_tc, npn13G2_c_pin)
+connect(npn13G2_tb, npn13G2_b_pin)
+connect(npn13G2_e_pin, cont_drw)
+connect(npn13G2_c_pin, cont_drw)
+connect(npn13G2_b_pin, cont_drw)
+connect(npn_sub, pwell)
+connect(npn13G2_e_pin, emwind_drw)
+connect(emwind_drw, metal1_con)
+
+# npn13G2L nodes connections
+connect(npn13G2l_te, npn13G2l_e_pin)
+connect(npn13G2l_tc, npn13G2l_c_pin)
+connect(npn13G2l_tb, npn13G2l_b_pin)
+connect(npn13G2l_e_pin, cont_drw)
+connect(npn13G2l_c_pin, cont_drw)
+connect(npn13G2l_b_pin, cont_drw)
+connect(npn_sub, pwell)
+
+# npn13G2V nodes connections
+connect(npn13G2v_te, npn13G2v_e_pin)
+connect(npn13G2v_tc, npn13G2v_c_pin)
+connect(npn13G2v_tb, npn13G2v_b_pin)
+connect(npn13G2v_e_pin, cont_drw)
+connect(npn13G2v_c_pin, cont_drw)
+connect(npn13G2v_b_pin, cont_drw)
+connect(npn_sub, pwell)
+
+# =============
+# ---- PNP ----
+# =============
+
+# pnp_mpa nodes connections
+connect(pnp_mpa_e, cont_drw)
+connect(pnp_mpa_b, cont_drw)
+connect(pnp_mpa_c, cont_drw)
+
+#================================
+# ----- DIODE CONNECTIONS -------
+#================================
+
+logger.info('Starting LVS DIODE CONNECTIONS')
+
+# dantenna diode
+connect(dantenna_n, cont_drw)
+connect(dantenna_p, pwell)
+
+# dantenna diode
+connect(dpantenna_n, nwell_drw)
+connect(dpantenna_p, cont_drw)
+
+# dantenna diode
+connect(schottcky_p_1x1, schottcky_p)
+connect(schottcky_p, metal1_con)
+connect(schottcky_n, schottcky_n_port)
+connect(schottcky_n_port, schottcky_n_con)
+connect(schottcky_n_con, metal1_con)
+
+#================================
+# ------- RES CONNECTIONS -------
+#================================
+
+logger.info('Starting RESISTOR CONNECTIONS')
+
+# === rsil ===
+connect(rsil_ports, cont_drw)
+
+# === rppd ===
+connect(rppd_ports, cont_drw)
+
+# === rhigh ===
+connect(rhigh_ports, cont_drw)
+
+# === Metal Res ===
+# Added in general connections
+
+#==================================
+# -------- CAP CONNECTIONS --------
+#==================================
+
+logger.info('Starting LVS CAP CONNECTIONS')
+
+# === cap_mim ===
+connect(cmim_btm, metal5_con)
+connect(cmim_top, mim_via)
+connect(mim_via, topmetal1_con)
+
+# === rfcmim ===
+connect(rfmim_btm, metal5_con)
+connect(rfmim_top, mim_via)
+connect(rfmim_sub, ptap)
+
+# === svarivap ===
+connect(varicap_ports, cont_drw)
+connect(varicap_ports, text_drw)
+connect(varicap_sub, ptap)
+
+#================================
+# ------- ESD CONNECTIONS -------
+#================================
+
+logger.info('Starting ESD CONNECTIONS')
+
+#======================
+# ----- diode-ESD -----
+#======================
+
+# diodevdd_2kv
+connect(diodevdd_2kv_e_1x1, diodevdd_2kv_e)
+connect(diodevdd_2kv_e, cont_drw)
+connect(diodevdd_2kv_b, diodevdd_2kv_tb)
+connect(diodevdd_2kv_tb, cont_drw)
+connect(diodevdd_2kv_c, cont_drw)
+
+# diodevdd_4kv
+connect(diodevdd_4kv_e_1x1, diodevdd_4kv_e)
+connect(diodevdd_4kv_e, diodevdd_4kv_te)
+connect(diodevdd_4kv_te, cont_drw)
+connect(diodevdd_4kv_b, diodevdd_4kv_tb)
+connect(diodevdd_4kv_tb, cont_drw)
+connect(diodevdd_4kv_c, cont_drw)
+
+# diodevss_2kv
+connect(diodevss_2kv_e_1x1, diodevss_2kv_e)
+connect(diodevss_2kv_e, cont_drw)
+connect(diodevss_2kv_b, diodevss_2kv_tb)
+connect(diodevss_2kv_tb, cont_drw)
+connect(diodevss_2kv_c, cont_drw)
+
+# diodevss_4kv
+connect(diodevss_4kv_e_1x1, diodevss_4kv_e)
+connect(diodevss_4kv_e, diodevss_4kv_te)
+connect(diodevss_4kv_te, cont_drw)
+connect(diodevss_4kv_b, diodevss_4kv_tb)
+connect(diodevss_4kv_tb, cont_drw)
+connect(diodevss_4kv_c, cont_drw)
+
+#=======================
+# ----- idiode-ESD -----
+#=======================
+
+# idiodevdd_2kv
+connect(idiodevdd_2kv_e_1x1, idiodevdd_2kv_e)
+connect(idiodevdd_2kv_e, cont_drw)
+connect(idiodevdd_2kv_b, idiodevdd_2kv_tb)
+connect(idiodevdd_2kv_tb, cont_drw)
+connect(idiodevdd_2kv_c, cont_drw)
+
+# idiodevdd_4kv
+connect(idiodevdd_4kv_e_1x1, idiodevdd_4kv_e)
+connect(idiodevdd_4kv_e, idiodevdd_4kv_te)
+connect(idiodevdd_4kv_te, cont_drw)
+connect(idiodevdd_4kv_b, idiodevdd_4kv_tb)
+connect(idiodevdd_4kv_tb, cont_drw)
+connect(idiodevdd_4kv_c, cont_drw)
+
+# idiodevss_2kv
+connect(idiodevss_2kv_e_1x1, idiodevss_2kv_e)
+connect(idiodevss_2kv_e, cont_drw)
+connect(idiodevss_2kv_b, idiodevss_2kv_tb)
+connect(idiodevss_2kv_tb, cont_drw)
+connect(idiodevss_2kv_c, cont_drw)
+
+# idiodevss_4kv
+connect(idiodevss_4kv_e_1x1, idiodevss_4kv_e)
+connect(idiodevss_4kv_e, idiodevss_4kv_te)
+connect(idiodevss_4kv_te, cont_drw)
+connect(idiodevss_4kv_b, idiodevss_4kv_tb)
+connect(idiodevss_4kv_tb, cont_drw)
+connect(idiodevss_4kv_c, cont_drw)
+
+#======================
+# ----- MOSCL-ESD -----
+#======================
+
+# nmoscl_2
+connect(nmoscl_2_n, nmoscl_2_n_port)
+connect(nmoscl_2_n_port, cont_drw)
+connect(nmoscl_2_p, nmoscl_2_p_)
+connect(nmoscl_2_p_, ptap)
+
+# nmoscl_4
+connect(nmoscl_4_n, nmoscl_4_n_port)
+connect(nmoscl_4_n_port, cont_drw)
+connect(nmoscl_4_p, nmoscl_4_p_)
+connect(nmoscl_4_p_, ptap)
+
+#=================================
+# ----- Inductor CONNECTIONS -----
+#=================================
+
+logger.info('Starting Inductor CONNECTIONS')
+
+# ind2
+connect(ind2_ports, ind_pin)
+connect(ind_pin, ind_text)
+connect(ind_pin, topmetal2_con)
+connect(ind2_sub, pwell)
+connect(ind2_sub, nwell_drw)
+
+# ind3
+connect(ind3_ports, ind_pin)
+connect(ind_pin, topmetal1_con)
+connect(ind3_sub, pwell)
+connect(ind3_sub, nwell_drw)
+
+#================================
+# ------- Taps CONNECTIONS ------
+#================================
+
+logger.info('Starting LVS Taps CONNECTIONS')
+
+# ntap1
+connect(ntap1_tie, cont_drw)
+connect(ntap1_well, nwell_drw)
+
+# ptap1
+connect(ptap1_tie, cont_drw)
+connect(ptap1_sub, pwell)
+
+#================================================
+#------------- DEVICES EXTRACTION ---------------
+#================================================
+
+logger.info('Starting SG13G2 LVS DEVICES EXTRACTION')
+
+#================================
+# ----- MOSFET EXTRACTION -------
+#================================
+
+logger.info('Starting MOSFET EXTRACTION')
+
+# ==============
+# ---- NMOS ----
+# ==============
+
+
+logger.info('Starting NMOS EXTRACTION')
+
+# nmos - LV
+logger.info('Extraction of NMOS-LV transistor')
+extract_devices(mos4('sg13_lv_nmos'),
+                { 'SD' => nsd_fet,
+                  'G' => ngate_lv,
+                  'tS' => nsd_fet,
+                  'tD' => nsd_fet,
+                  'tG' => poly_con,
+                  'W' => pwell })
+
+# nmos - HV
+logger.info('Extraction of NMOS-HV transistor')
+extract_devices(mos4('sg13_hv_nmos'),
+                { 'SD' => nsd_fet,
+                  'G' => ngate_hv,
+                  'tS' => nsd_fet,
+                  'tD' => nsd_fet,
+                  'tG' => poly_con,
+                  'W' => pwell })
+
+# ==============
+# ---- PMOS ----
+# ==============
+
+logger.info('Starting PMOS EXTRACTION')
+
+# pmos - LV
+logger.info('Extraction of PMOS-LV transistor')
+extract_devices(mos4('sg13_lv_pmos'),
+                { 'SD' => psd_fet,
+                  'G' => pgate_lv,
+                  'tS' => psd_fet,
+                  'tD' => psd_fet,
+                  'tG' => poly_con,
+                  'W' => nwell_drw })
+
+# pmos - HV
+logger.info('Extraction of PMOS-HV transistor')
+extract_devices(mos4('sg13_hv_pmos'),
+                { 'SD' => psd_fet,
+                  'G' => pgate_hv,
+                  'tS' => psd_fet,
+                  'tD' => psd_fet,
+                  'tG' => poly_con,
+                  'W' => nwell_drw })
+
+#================================
+# ---- RF-MOSFET EXTRACTION -----
+#================================
+
+logger.info('Starting RF-MOSFET EXTRACTION')
+
+# ===============
+# --- RF-NMOS ---
+# ===============
+
+# rfnmos - LV
+logger.info('Extraction of RF-NMOS-LV transistor')
+extract_devices(mos4('rfnmos'),
+                { 'SD' => nsd_fet,
+                  'G' => rfngate_lv,
+                  'W' => pwell,
+                  'tS' => nsd_fet,
+                  'tD' => nsd_fet,
+                  'tG' => poly_con,
+                  'tW' => ptap,
+                })
+
+# rfnmos - HV
+logger.info('Extraction of RF-NMOS-HV transistor')
+extract_devices(mos4('rfnmoshv'),
+                { 'SD' => nsd_fet,
+                  'G' => rfngate_hv,
+                  'W' => pwell,
+                  'tS' => nsd_fet,
+                  'tD' => nsd_fet,
+                  'tG' => poly_con,
+                  'tW' => ptap,
+                })
+
+# ===============
+# --- RF-PMOS ---
+# ===============
+
+# rfpmos - LV
+logger.info('Extraction of RF-PMOS-LV transistor')
+extract_devices(mos4('rfpmos'),
+                { 'SD' => psd_fet,
+                  'G' => rfpgate_lv,
+                  'tS' => psd_fet,
+                  'tD' => psd_fet,
+                  'tG' => poly_con,
+                  'W' => nwell_drw,
+                  'tW' => ntap,
+                })
+
+# rfpmos - HV
+logger.info('Extraction of RF-PMOS-HV transistor')
+extract_devices(mos4('rfpmoshv'),
+                { 'SD' => psd_fet,
+                  'G' => rfpgate_hv,
+                  'tS' => psd_fet,
+                  'tD' => psd_fet,
+                  'tG' => poly_con,
+                  'W' => nwell_drw,
+                  'tW' => ntap,
+                })
+
+#================================
+# ------- BJT EXTRACTION --------
+#================================
+
+logger.info('Starting BJT EXTRACTION')
+
+# =============
+# ---- NPN ----
+# =============
+
+logger.info('Starting NPN-BJT EXTRACTION')
+
+logger.info('Extraction of npn13G2 BJT transistor')
+extract_devices(bjt4('npn13G2', CustomBJT4), {
+                  'C' => npn13G2_c,
+                  'B' => npn13G2_b,
+                  'E' => npn13G2_e,
+                  'S' => npn_sub,
+                  'tC' => npn13G2_tc,
+                  'tB' => npn13G2_tb,
+                  'tE' => npn13G2_te,
+                  'tS' => npn_sub
+                })
+
+logger.info('Extraction of npn13G2L BJT transistor')
+extract_devices(bjt4('npn13G2l', CustomBJT4), {
+                  'C' => npn13G2l_c,
+                  'B' => npn13G2l_b,
+                  'E' => npn13G2l_e,
+                  'S' => npn_sub,
+                  'tC' => npn13G2l_tc,
+                  'tB' => npn13G2l_tb,
+                  'tE' => npn13G2l_te,
+                  'tS' => npn_sub
+                })
+
+logger.info('Extraction of npn13G2V BJT transistor')
+extract_devices(bjt4('npn13G2v', CustomBJT4), {
+                  'C' => npn13G2v_c,
+                  'B' => npn13G2v_b,
+                  'E' => npn13G2v_e,
+                  'S' => npn_sub,
+                  'tC' => npn13G2v_tc,
+                  'tB' => npn13G2v_tb,
+                  'tE' => npn13G2v_te,
+                  'tS' => npn_sub
+                })
+
+# =============
+# ---- PNP ----
+# =============
+
+logger.info('Starting PNP-BJT EXTRACTION')
+
+# pnp_mpa BJT
+logger.info('Extracting pnpMPA BJT')
+extract_devices(bjt3('pnpMPA', CustomBJT3), { 'C' => pnp_mpa_c.extents,
+                                  'B' => pnp_mpa_b.extents,
+                                  'E' => pnp_mpa_e,
+                                  'tC' => pnp_mpa_c,
+                                  'tB' => pnp_mpa_b,
+                                  'tE' => pnp_mpa_e })
+
+#================================
+# ------ DIODE EXTRACTION -------
+#================================
+
+logger.info('Starting DIODE EXTRACTION')
+
+# dantenna diode
+logger.info('Extracting dantenna diode')
+extract_devices(diode('dantenna', EnDiode), { 'N' => dantenna_n, 'P' => dantenna_p })
+
+# dpantenna diode
+logger.info('Extracting dpantenna diode')
+extract_devices(diode('dpantenna', EnDiode), { 'N' => dpantenna_n, 'P' => dpantenna_p })
+
+# schottky_nbl1 diode
+logger.info('Extracting schottky_nbl1 diode')
+extract_devices(bjt3('schottky_nbl1', Esd3Term), { 'C' => schottcky_sub,
+                                                   'B' => schottcky_n_port.extents,
+                                                   'E' => schottcky_p_1x1,
+                                                   'tC' => ptap,
+                                                   'tB' => schottcky_n_port,
+                                                   'tE' => schottcky_p_1x1 })
+
+#================================
+# ---- RESISTOR EXTRACTIONS -----
+#================================
+
+logger.info('Starting RESISTOR EXTRACTION')
+
+# ==============
+# ---- POLY ----
+# ==============
+
+# rsil
+logger.info('Extracting rsil resistor')
+extract_devices(GeneralNTerminalExtractor.new('rsil', 2), {
+                  'core' => rsil_res,
+                  'ports' => rsil_ports,
+                  'meas_mk' => polyres_drw,
+                  'dev_mk' => polyres_drw.interacting(rsil_res),
+                  'sub_mk' => pwell.join(nwell_drw)
+                })
+# rppd
+logger.info('Extracting rppd resistor')
+extract_devices(GeneralNTerminalExtractor.new('rppd', 2), {
+                  'core' => rppd_res,
+                  'ports' => rppd_ports,
+                  'meas_mk' => polyres_drw,
+                  'dev_mk' => polyres_drw.interacting(rppd_res),
+                  'sub_mk' => pwell.join(nwell_drw)
+                })
+
+# rhigh
+logger.info('Extracting rhigh resistor')
+extract_devices(GeneralNTerminalExtractor.new('rhigh', 2), {
+                  'core' => rhigh_res,
+                  'ports' => rhigh_ports,
+                  'meas_mk' => polyres_drw,
+                  'dev_mk' => polyres_drw.interacting(rhigh_res),
+                  'sub_mk' => pwell.join(nwell_drw)
+                })
+
+# ===============
+# ---- METAL ----
+# ===============
+
+# RM1
+logger.info('Extracting res_metal1 resistor')
+extract_devices(resistor('res_metal1', 1.0, RES2), { 'R' => res_metal1, 'C' => metal1_con })
+
+# RM2
+logger.info('Extracting res_metal2 resistor')
+extract_devices(resistor('res_metal2', 1.0, RES2), { 'R' => res_metal2, 'C' => metal2_con })
+
+# RM3
+logger.info('Extracting res_metal3 resistor')
+extract_devices(resistor('res_metal3', 1.0, RES2), { 'R' => res_metal3, 'C' => metal3_con })
+
+# RM4
+logger.info('Extracting res_metal4 resistor')
+extract_devices(resistor('res_metal4', 1.0, RES2), { 'R' => res_metal4, 'C' => metal4_con })
+
+# RM5
+logger.info('Extracting res_metal5 resistor')
+extract_devices(resistor('res_metal5', 1.0, RES2), { 'R' => res_metal5, 'C' => metal5_con })
+
+# RTM1
+logger.info('Extracting res_topmetal1 resistor')
+extract_devices(resistor('res_topmetal1', 1.0, RES2), { 'R' => res_topmetal1, 'C' => topmetal1_con })
+
+# RTM2
+logger.info('Extracting res_topmetal2 resistor')
+extract_devices(resistor('res_topmetal2', 1.0, RES2), { 'R' => res_topmetal2, 'C' => topmetal2_con })
+
+#==================================
+# --------- CAP EXTRACTION --------
+#==================================
+
+logger.info('Starting CAP EXTRACTION')
+
+# === cap_cmim ===
+logger.info('Extracting cap_cmim device')
+extract_devices(MIMCAPExtractor.new('cap_cmim'), {
+                  'core' => cmim_top,
+                  'top_mim' => cmim_top,
+                  'btm_mim' => cmim_btm,
+                  'meas_mk' => cmim_dev,
+                  'dev_mk' => cmim_dev,
+                })
+
+# === rfcmim ===
+logger.info('Extracting rfcmim device')
+extract_devices(MIMCAPExtractor.new('rfcmim'), {
+                  'core' => rfmim_top,
+                  'top_mim' => rfmim_top,
+                  'btm_mim' => rfmim_btm,
+                  'dev_mk' => rfmim_area.covering(rfmim_dev),
+                  'meas_mk' => rfmeas_mk,
+                  'sub_mk' => rfmim_sub,
+                })
+
+# === svaricap ===
+logger.info('Extracting sg13_hv_svaricap varactor')
+extract_devices(GeneralNTerminalExtractor.new('sg13_hv_svaricap', 3), {
+                  'core' => varicap_core,
+                  'ports' => varicap_ports,
+                  'meas_mk' => activ,
+                  'dev_mk' => varicap_dev_mk,
+                  'sub_mk' => varicap_sub
+                })
+
+#================================
+# ------- ESD EXTRACTION --------
+#================================
+
+logger.info('Starting ESD EXTRACTION')
+
+#======================
+# ----- diode-ESD -----
+#======================
+
+# diodevdd_2kv
+logger.info('Extracting diodevdd_2kv ESD device')
+extract_devices(bjt3('diodevdd_2kv', Esd3Term), { 'C' => diodevdd_2kv_c.extents,
+                                                  'B' => diodevdd_2kv_b.extents,
+                                                  'E' => diodevdd_2kv_e_1x1,
+                                                  'tC' => diodevdd_2kv_c,
+                                                  'tB' => diodevdd_2kv_b,
+                                                  'tE' => diodevdd_2kv_e_1x1 })
+
+# diodevdd_4kv
+logger.info('Extracting diodevdd_4kv ESD device')
+extract_devices(bjt3('diodevdd_4kv', Esd3Term), { 'C' => diodevdd_4kv_c.extents,
+                                                  'B' => diodevdd_4kv_b.extents,
+                                                  'E' => diodevdd_4kv_e_1x1,
+                                                  'tC' => diodevdd_4kv_c,
+                                                  'tB' => diodevdd_4kv_b,
+                                                  'tE' => diodevdd_4kv_e_1x1 })
+
+# diodevss_2kv
+logger.info('Extracting diodevss_2kv ESD device')
+extract_devices(bjt3('diodevss_2kv', Esd3Term), { 'C' => diodevss_2kv_c.extents,
+                                                  'B' => diodevss_2kv_b.extents,
+                                                  'E' => diodevss_2kv_e_1x1,
+                                                  'tC' => diodevss_2kv_c,
+                                                  'tB' => diodevss_2kv_b,
+                                                  'tE' => diodevss_2kv_e_1x1 })
+
+# diodevss_4kv
+logger.info('Extracting diodevss_4kv ESD device')
+extract_devices(bjt3('diodevss_4kv', Esd3Term), { 'C' => diodevss_4kv_c.extents,
+                                                  'B' => diodevss_4kv_b.extents,
+                                                  'E' => diodevss_4kv_e_1x1,
+                                                  'tC' => diodevss_4kv_c,
+                                                  'tB' => diodevss_4kv_b,
+                                                  'tE' => diodevss_4kv_e_1x1 })
+
+#=======================
+# ----- idiode-ESD -----
+#=======================
+
+# idiodevdd_2kv
+logger.info('Extracting idiodevdd_2kv ESD device')
+extract_devices(bjt3('idiodevdd_2kv', Esd3Term), { 'C' => idiodevdd_2kv_c.extents,
+                                                   'B' => idiodevdd_2kv_b.extents,
+                                                   'E' => idiodevdd_2kv_e_1x1,
+                                                   'tC' => idiodevdd_2kv_c,
+                                                   'tB' => idiodevdd_2kv_b,
+                                                   'tE' => idiodevdd_2kv_e_1x1 })
+
+# idiodevdd_4kv
+logger.info('Extracting idiodevdd_4kv ESD device')
+extract_devices(bjt3('idiodevdd_4kv', Esd3Term), { 'C' => idiodevdd_4kv_c.extents,
+                                                   'B' => idiodevdd_4kv_b.extents,
+                                                   'E' => idiodevdd_4kv_e_1x1,
+                                                   'tC' => idiodevdd_4kv_c,
+                                                   'tB' => idiodevdd_4kv_b,
+                                                   'tE' => idiodevdd_4kv_e_1x1 })
+
+# idiodevss_2kv
+logger.info('Extracting idiodevss_2kv ESD device')
+extract_devices(bjt3('idiodevss_2kv', Esd3Term), { 'C' => idiodevss_2kv_c.extents,
+                                                   'B' => idiodevss_2kv_b.extents,
+                                                   'E' => idiodevss_2kv_e_1x1,
+                                                   'tC' => idiodevss_2kv_c,
+                                                   'tB' => idiodevss_2kv_b,
+                                                   'tE' => idiodevss_2kv_e_1x1 })
+
+# idiodevss_4kv
+logger.info('Extracting idiodevss_4kv ESD device')
+extract_devices(bjt3('idiodevss_4kv', Esd3Term), { 'C' => idiodevss_4kv_c.extents,
+                                                   'B' => idiodevss_4kv_b.extents,
+                                                   'E' => idiodevss_4kv_e_1x1,
+                                                   'tC' => idiodevss_4kv_c,
+                                                   'tB' => idiodevss_4kv_b,
+                                                   'tE' => idiodevss_4kv_e_1x1 })
+
+#======================
+# ----- MOSCL-ESD -----
+#======================
+
+# nmoscl_2
+logger.info('Extracting nmoscl_2 ESD device')
+extract_devices(diode('nmoscl_2', Esd2Term), { 'N' => nmoscl_2_n, 'P' => nmoscl_2_p })
+
+# nmoscl_4
+logger.info('Extracting nmoscl_4 ESD device')
+extract_devices(diode('nmoscl_4', Esd2Term), { 'N' => nmoscl_4_n, 'P' => nmoscl_4_p })
+
+#=================================
+# ----- Inductor EXTRACTIONS -----
+#=================================
+
+logger.info('Starting Inductor EXTRACTION')
+
+# ind2
+logger.info('Extracting Inductor2 device')
+extract_devices(GeneralNTerminalExtractor.new('inductor', 2), {
+                  'core' => ind2_core,
+                  'ports' => ind2_ports,
+                  'meas_mk' => topmetal2.and(ind2_core),
+                  'dev_mk' => ind2_mk,
+                  'sub_mk' => ind2_sub
+                })
+
+# ind3
+logger.info('Extracting Inductor3 device')
+extract_devices(GeneralNTerminalExtractor.new('inductor3', 3), {
+                  'core' => ind3_core,
+                  'ports' => ind3_ports,
+                  'meas_mk' => topmetal2.and(ind3_core),
+                  'dev_mk' => ind3_mk,
+                  'sub_mk' => ind3_sub
+                })
+
+#================================
+# ------- Taps EXTRACTIONS ------
+#================================
+
+logger.info('Starting Taps EXTRACTION')
+
+# ntap1
+logger.info('Extracting ntap1 device')
+extract_devices(diode('ntap1', CustomTap), { 'N' => ntap1_tie, 'P' => ntap1_well })
+
+# ptap1
+logger.info('Extracting ptap1 device')
+extract_devices(diode('ptap1', CustomTap), { 'N' => ptap1_tie, 'P' => ptap1_sub })
+
+#==================================================
+# ------------ COMPARISON PREPARATIONS ------------
+#==================================================
+
+logger.info('Starting SG13G2 LVS Options Preparations')
+
+# === Extract Netlist Only ===
+netlist if NET_ONLY
+return if NET_ONLY
+
+# === Aligns the extracted netlist vs. the schematic ===
+logger.info('Starting SG13G2 LVS Alignment')
+align
+
+#=== NETLIST OPTIONS ===
+logger.info('Starting SG13G2 LVS Simplification')
+# SIMPLIFY
+netlist.simplify if SIMPLIFY
+schematic.simplify if SIMPLIFY
+
+# TOP_LVL_PINS
+netlist.make_top_level_pins if TOP_LVL_PINS
+schematic.make_top_level_pins if TOP_LVL_PINS
+
+# COMBINE_DEVICES
+netlist.combine_devices if COMBINE_DEVICES
+schematic.combine_devices if COMBINE_DEVICES
+
+# PURGE
+netlist.purge if PURGE
+schematic.purge if PURGE
+
+# PURGE_NETS
+netlist.purge_nets if PURGE_NETS
+schematic.purge_nets if PURGE_NETS
+
+#=== IGNORE EXTREME VALUES ===
+max_res(1e9)
+min_caps(1e-18)
+
+# === COMPARISON === 
+logger.info('Starting SG13G2 LVS Comparison')
+compare
+
+#================================================
+#------------- COMPARISON RESULTS ---------------
+#================================================
+
+if !compare
+  logger.info('xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx')
+  logger.error("ERROR : Netlists don't match")
+  logger.info('xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx')
+else
+  logger.info('==========================================')
+  logger.info('INFO : Congratulations! Netlists match.')
+  logger.info('==========================================')
+end
+
+exec_end_time = Time.now
+run_time = exec_end_time - exec_start_time
+logger.info(format('LVS Total Run time %f seconds', run_time))
+ ]]>
+</text>
+</klayout-macro>
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/Makefile b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/Makefile
index 2809a23c..050941d1 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/Makefile
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/Makefile
@@ -32,7 +32,9 @@ test-LVS: test-LVS-switch  test-LVS-main
 #=================================
 
 .ONESHELL:
-test-LVS-main: test-LVS-MOS test-LVS-RFMOS test-LVS-BJT test-LVS-DIODE test-LVS-RES test-LVS-CAP test-LVS-ESD test-LVS-IND test-LVS-TAP
+test-LVS-main:
+	@echo "========== LVS-$* testing =========="
+	@ python3 run_regression.py
 
 .ONESHELL:
 test-LVS-%:
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/macros/lvs_options.yml b/ihp-sg13g2/libs.tech/klayout/tech/macros/lvs_options.yml
index 747ede76..e8577832 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/macros/lvs_options.yml
+++ b/ihp-sg13g2/libs.tech/klayout/tech/macros/lvs_options.yml
@@ -1,7 +1,7 @@
 ---
 netlist: ''
 top_cell: ''
-run_mode: deep
+run_mode: flat
 no_net_names: false
 spice_comments: false
 net_only: false
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/macros/sg13g2_density_report.lym b/ihp-sg13g2/libs.tech/klayout/tech/macros/sg13g2_density_report.lym
new file mode 100644
index 00000000..0cc144f4
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/macros/sg13g2_density_report.lym
@@ -0,0 +1,166 @@
+<?xml version="1.0" encoding="utf-8"?>
+<klayout-macro>
+ <description>Density Report</description>
+ <version>0.1</version>
+ <category>misc</category>
+ <prolog/>
+ <epilog/>
+ <doc/>
+ <autorun>false</autorun>
+ <autorun-early>false</autorun-early>
+ <priority>0</priority>
+ <shortcut/>
+ <show-in-menu>true</show-in-menu>
+ <group-name>Run Density Report</group-name>
+ <menu-path>sg13g2_menu&gt;end("SG13G2 PDK").end</menu-path>
+ <interpreter>dsl</interpreter>
+ <dsl-interpreter-name>drc-dsl-xml</dsl-interpreter-name>
+ <text># layer inputs
+
+###################### Layer assignment #######################
+
+# total area limited by prBoundary
+# HACK: use 235/4 since we currently have no prBoundary (189/0) drawn
+prBoundary = input("235/4")
+
+
+# Activ
+activ_draw = input("1/0")
+activ_fill = input("1/22")
+
+# GatPoly
+GatPoly_draw = input("5/0")
+GatPoly_fill = input("5/22")
+
+# metal1
+metal1_draw = input("8/0")
+metal1_fill = input("8/22")
+
+# metal2
+metal2_draw = input("10/0")
+metal2_fill = input("10/22")
+
+# metal3
+metal3_draw = input("30/0")
+metal3_fill = input("30/22")
+
+# metal4
+metal4_draw = input("50/0")
+metal4_fill = input("50/22")
+
+# metal5
+metal5_draw = input("67/0")
+metal5_fill = input("67/22")
+
+# TopMetal1
+TopMetal1_draw = input("126/0")
+TopMetal1_fill = input("126/22")
+
+# TopMetal2
+TopMetal2_draw = input("134/0")
+TopMetal2_fill = input("134/22")
+
+
+###################### area calculation ########################
+
+# total
+area_total = prBoundary.area.round(3)
+
+# Activ
+area_activ_fill = activ_fill.area.round(3)
+area_activ_draw = activ_draw.area.round(3)
+area_activ  = area_activ_fill + area_activ_draw
+tf_activ = (area_activ/area_total*100.0).round(3)
+
+# GatPoly
+area_GatPoly_fill = GatPoly_fill.area.round(3)
+area_GatPoly_draw = GatPoly_draw.area.round(3)
+area_GatPoly  = area_GatPoly_fill + area_GatPoly_draw
+tf_GatPoly = (area_GatPoly/area_total*100.0).round(3)
+
+# metal 1
+area_metal1_fill = metal1_fill.area.round(3)
+area_metal1_draw = metal1_draw.area.round(3)
+area_metal1  = area_metal1_fill + area_metal1_draw
+tf_metal1 = (area_metal1/area_total*100.0).round(3)
+
+# metal 2
+area_metal2_fill = metal2_fill.area.round(3)
+area_metal2_draw = metal2_draw.area.round(3)
+area_metal2  = area_metal2_fill + area_metal2_draw
+tf_metal2 = (area_metal2/area_total*100.0).round(3)
+
+# metal 3
+area_metal3_fill = metal3_fill.area.round(3)
+area_metal3_draw = metal3_draw.area.round(3)
+area_metal3  = area_metal3_fill + area_metal3_draw
+tf_metal3 = (area_metal3/area_total*100.0).round(3)
+
+# metal 4
+area_metal4_fill = metal4_fill.area.round(3)
+area_metal4_draw = metal4_draw.area.round(3)
+area_metal4  = area_metal4_fill + area_metal4_draw
+tf_metal4 = (area_metal4/area_total*100.0).round(3)
+
+# metal 5
+area_metal5_fill = metal5_fill.area.round(3)
+area_metal5_draw = metal5_draw.area.round(3)
+area_metal5  = area_metal5_fill + area_metal5_draw
+tf_metal5 = (area_metal5/area_total*100.0).round(3)
+
+# TopMetal 1
+area_TopMetal1_fill = TopMetal1_fill.area.round(3)
+area_TopMetal1_draw = TopMetal1_draw.area.round(3)
+area_TopMetal1  = area_TopMetal1_fill + area_TopMetal1_draw
+tf_TopMetal1 = (area_TopMetal1/area_total*100.0).round(3)
+
+# TopMetal 2
+area_TopMetal2_fill = TopMetal2_fill.area.round(3)
+area_TopMetal2_draw = TopMetal2_draw.area.round(3)
+area_TopMetal2  = area_TopMetal2_fill + area_TopMetal2_draw
+tf_TopMetal2 = (area_TopMetal2/area_total*100.0).round(3)
+
+
+# output
+puts "Layer areas and percetages"
+puts "------------------------------------------------\n\n"
+
+puts "Total Area = #{area_total}um^2\n\n"
+
+# Activ
+puts "Activ Area = #{area_activ}um^2"
+puts "Activ %    = #{tf_activ}% Min = 35 Max = 55\n\n"
+
+# GatPoly
+puts "GatPoly Area = #{area_GatPoly}um^2"
+puts "GatPoly %    = #{tf_GatPoly}% Min = 15\n\n"
+
+# metal 1
+puts "Metal1 Area = #{area_metal1}um^2"
+puts "Metal1 %    = #{tf_metal1}% Min = 35 Max = 60\n\n"
+
+# metal 2
+puts "Metal2 Area = #{area_metal2}um^2"
+puts "Metal2 %    = #{tf_metal2}% Min = 35 Max = 60\n\n"
+
+# metal 3
+puts "Metal3 Area = #{area_metal3}um^2"
+puts "Metal3 %    = #{tf_metal3}% Min = 35 Max = 60\n\n"
+
+# metal 4
+puts "Metal4 Area = #{area_metal4}um^2"
+puts "Metal4 %    = #{tf_metal4}% Min = 35 Max = 60\n\n"
+
+# metal 5
+puts "Metal5 Area = #{area_metal5}um^2"
+puts "Metal5 %    = #{tf_metal5}% Min = 35 Max = 60\n\n"
+
+# TopMetal 1
+puts "TopMetal1 Area = #{area_TopMetal1}um^2"
+puts "TopMetal1 %    = #{tf_TopMetal1}% Min = 25 Max = 70\n\n"
+
+# TopMetal 2
+puts "TopMetal2 Area = #{area_TopMetal2}um^2"
+puts "TopMetal2 %    = #{tf_TopMetal2}% Min = 25 Max = 70\n\n"
+</text>
+</klayout-macro>
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/pymacros/autorun.lym b/ihp-sg13g2/libs.tech/klayout/tech/pymacros/autorun.lym
index b2fc2eb1..cd543844 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/pymacros/autorun.lym
+++ b/ihp-sg13g2/libs.tech/klayout/tech/pymacros/autorun.lym
@@ -32,6 +32,10 @@
  <text>
 # This file only serves to bootstrap sg13g2_pycell_lib.
 # Everything else is done inside this module's __init__.py.
+import sys
+import os
+sys.path.append(os.path.join(os.path.dirname(__file__), '..', '..', 'python/'))
+sys.path.append(os.path.join(os.path.dirname(__file__), '..', '..', 'python/pycell4klayout-api/source/python/'))
 import sg13g2_pycell_lib
 </text>
 </klayout-macro>
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/scripts/sealring.py b/ihp-sg13g2/libs.tech/klayout/tech/scripts/sealring.py
new file mode 100644
index 00000000..1dcf83da
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/scripts/sealring.py
@@ -0,0 +1,70 @@
+"""Module to automatically generate a sealring and create a new GDS file. Can be used in
+Klayout's batch mode. For example:
+
+klayout -n sg13g2 -zz -r sealring.py \
+        -rd width=1300.0 -rd height=1300.0 -rd output=macros/sealring.gds.gz
+
+"""
+# pylint: disable=import-error
+import pathlib
+import sys
+import re
+import pya
+import klayout.db
+
+LIB = 'SG13_dev'
+PCELL = 'sealring'
+
+def generate_sealring(width: float, heigth: float, output: str):
+    """Function to create a new layout, add the sealring PCell to sealring_top
+    and save it somewhere on the filesystem.
+
+    :param width: Width (X-Axis) of the sealring.
+    :type width: float
+    :param height: Heigth (Y-Axis) of the sealring.
+    :type heigth: float
+    :param output: Path and name of the file where the sealring should be written to.
+    :type output: str
+
+    """
+    layout = klayout.db.Layout(True)
+    layout.dbu = 0.001
+
+    lib = pya.Library.library_by_name(LIB)
+    pcell_decl = lib.layout().pcell_declaration(PCELL)
+
+    # Remove space around the sealring from width/height arguments.
+    params = pcell_decl.params_as_hash(pcell_decl.get_parameters())
+    edge_box = float(re.sub('[a-zA-Z]+', '', params['edgeBox'].default))
+    width = float(width) - edge_box * 2
+    heigth = float(heigth) - edge_box * 2
+
+    top_cell = layout.cell(layout.add_cell("sealring_top"))
+    pcell = layout.add_pcell_variant(lib, pcell_decl.id(), {'w': f'{width}u', 'l': f'{heigth}u'})
+    layout.cell(pcell)
+    top_cell.insert(klayout.db.CellInstArray(pcell, klayout.db.Trans()))
+
+    # Create directory where the sealring should be written to.
+    pathlib.Path(output).parent.mkdir(parents=True, exist_ok=True)
+
+    layout.write(output)
+
+try:
+    width
+except NameError:
+    print("Missing width argument. Please define '-rd width=<width>'")
+    sys.exit(1)
+
+try:
+    height
+except NameError:
+    print("Missing height argument. Please define '-rd height=<height>'")
+    sys.exit(1)
+
+try:
+    output
+except NameError:
+    print("Missing output argument. Please define '-rd output=<path-to-sealring>'")
+    sys.exit(1)
+
+generate_sealring(width, height, output) # pylint: disable=undefined-variable
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/sg13g2.lyt b/ihp-sg13g2/libs.tech/klayout/tech/sg13g2.lyt
index dccddc67..488e57bf 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/sg13g2.lyt
+++ b/ihp-sg13g2/libs.tech/klayout/tech/sg13g2.lyt
@@ -20,6 +20,7 @@
  <original-base-path></original-base-path>
  <layer-properties_file>sg13g2.lyp</layer-properties_file>
  <add-other-layers>true</add-other-layers>
+ <default-grids>0.01,0.005!</default-grids>
  <reader-options>
   <gds2>
    <box-mode>1</box-mode>
@@ -82,8 +83,8 @@
    <read-lef-with-def>true</read-lef-with-def>
    <macro-resolution-mode>default</macro-resolution-mode>
    <separate-groups>false</separate-groups>
-   <map-file/>
-   <lef-files>merged.lef</lef-files> 
+   <map-file>sg13g2.map</map-file>
+   <lef-files></lef-files>
   </lefdef>
   <mebes>
    <invert>false</invert>
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/sg13g2.map b/ihp-sg13g2/libs.tech/klayout/tech/sg13g2.map
new file mode 100644
index 00000000..26143741
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/sg13g2.map
@@ -0,0 +1,154 @@
+#************************************************************************#
+#************************************************************************#
+# File		: sg13g2.map
+# DATE		: September 28, 2022
+#*************************************************************************
+#************************************************************************* 
+#                                                                         
+# Copyright 2023 IHP PDK Authors                                         
+#                                                                       
+# Licensed under the Apache License, Version 2.0 (the "License");       
+# you may not use this file except in compliance with the License.      
+# You may obtain a copy of the License at                                     
+#                                                                             
+#     https://www.apache.org/licenses/LICENSE-2.0                             
+#                                                                             
+# Unless required by applicable law or agreed to in writing, software         
+# distributed under the License is distributed on an "AS IS" BASIS,           
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.    
+# See the License for the specific language governing permissions and         
+# limitations under the License.                                              
+#                                                                             
+#************************************************************************* 
+#-------------------------------------------------------------------------
+# EDI Stream layer mapping table for SG13
+# Version: 1.0 
+# Date: 22 Aug 2023
+# Use only in combination with valid GDSII data of all used blocks!
+#-------------------------------------------------------------------------
+#EDI Layer Name	  EDI Layer Type   GDS Layer Number   GDS Layer Type
+#==============	  ==============   ================   ==============
+
+Metal1		NET			8		0
+Metal1		SPNET		8		0
+Metal1		PIN			8		2
+Metal1		LEFPIN		8		2
+Metal1		FILL		8		22
+Metal1		LEFOBS		8		4
+Metal1		VIA			8		0
+
+#NAME		Metal1/NET		20		0
+#NAME		Metal1/SPNET	20		0
+NAME		Metal1/PIN		8		25
+#NAME		Metal1/LEFPIN	20		0
+
+Via1		PIN		19		0
+Via1		LEFPIN	19		0
+Via1		VIA		19		0
+
+Metal2		NET		10		0
+Metal2		SPNET	10		0
+Metal2		PIN		10		2
+Metal2		LEFPIN	10		2
+Metal2		FILL	10		22
+Metal2		VIA		10		0
+Metal2		LEFOBS	10		4
+
+#NAME		Metal2/NET		21		0
+#NAME		Metal2/SPNET	21		0
+NAME		Metal2/PIN		10		25
+#NAME		Metal2/LEFPIN	21		0
+
+Via2		PIN		29		0
+Via2		LEFPIN	29		0
+Via2		VIA		29		0
+
+
+Metal3		NET		30		0
+Metal3		SPNET	30		0
+Metal3		PIN		30		2
+Metal3		LEFPIN	30		2
+Metal3		FILL	30		22
+Metal3		VIA		30		0
+Metal3		LEFOBS	30		4
+
+#NAME		Metal3/NET		22		0
+#NAME		Metal3/SPNET	22		0
+NAME		Metal3/PIN		30		25
+#NAME		Metal3/LEFPIN	22		0
+
+Via3		PIN		49		0
+Via3		LEFPIN	49		0
+Via3		VIA		49		0
+
+
+Metal4		NET		50		0
+Metal4		SPNET	50		0
+Metal4		PIN		50		2
+Metal4		LEFPIN	50		2
+Metal4		FILL	50		22
+Metal4		VIA		50		0
+Metal4		LEFOBS	50		4
+
+#NAME		Metal4/NET		23		0
+#NAME		Metal4/SPNET	23		0
+NAME		Metal4/PIN		50		25
+#NAME		Metal4/LEFPIN	23		0
+
+Via4		PIN		66		0
+Via4		LEFPIN	66		0
+Via4		VIA		66		0
+
+
+Metal5		NET		67		0
+Metal5		SPNET	67		0
+Metal5		PIN		67		2
+Metal5		LEFPIN	67		2
+Metal5		FILL	67		22
+Metal5		VIA		67		0
+Metal5		LEFOBS	67		4
+
+#NAME		Metal5/NET		70		0
+#NAME		Metal5/SPNET	70		0
+NAME		Metal5/PIN		67		25
+#NAME		Metal5/LEFPIN	70		0
+
+TopVia1		PIN		125		0
+TopVia1		LEFPIN	125		0
+TopVia1		VIA		125		0
+
+TopMetal1		NET		126		0
+TopMetal1		SPNET	126		0
+TopMetal1		PIN		126		2
+TopMetal1		LEFPIN	126		2
+TopMetal1		FILL	126		22
+TopMetal1		VIA		126		0
+TopMetal1		LEFOBS	126		4
+
+#NAME		TopMetal1/NET		130		0
+#NAME		TopMetal1/SPNET		130		0
+NAME		TopMetal1/PIN		126		25
+#NAME		TopMetal1/LEFPIN	130		0
+
+TopVia2		PIN		133		0
+TopVia2		LEFPIN		133		0
+TopVia2		VIA		133		0
+
+TopMetal2		NET		134		0
+TopMetal2		SPNET	134		0
+TopMetal2		PIN		134		2
+TopMetal2		LEFPIN	134		2
+TopMetal2		FILL	134		22
+TopMetal2		VIA		134		0
+TopMetal2		LEFOBS	135		4
+
+#NAME		TopMetal2/NET		137		0
+#NAME		TopMetal2/SPNET		137		0
+NAME		TopMetal2/PIN		134		25
+#NAME		TopMetal2/LEFPIN	137		0
+
+NAME		COMP		63		0
+
+COMP		ALL		235		0
+
+DIEAREA		ALL		235		4
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/xsect/README.md b/ihp-sg13g2/libs.tech/klayout/tech/xsect/README.md
new file mode 100644
index 00000000..5d1b70f6
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/xsect/README.md
@@ -0,0 +1,15 @@
+# KLayout cross-section
+> ⚠️ **Current status**: BEOL + MIM
+
+How to use:
+- install 'xsection' KLayout package
+- restart KLayout
+- 'XSection x.x Scripts' menu item should appear in at the end of 'Tools' dropdown menu
+- open the needed layout
+- draw a 'ruler' where you want to check the cross-section view
+- run 'XSection x.x Scripts'->'Xsection: Active Technology'
+- a new layout named 'XSECTION' is created and set to active
+- load special `cross_section.lyp` layer property file
+- check results, now you should have smth like below:
+
+![xsection](https://github.com/user-attachments/assets/4adb5fe0-40cc-4f3e-8f7b-e73eb3c5d9a2)
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/xsect/cross_section.lyp b/ihp-sg13g2/libs.tech/klayout/tech/xsect/cross_section.lyp
new file mode 100644
index 00000000..b30c6272
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/xsect/cross_section.lyp
@@ -0,0 +1,523 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!--
+ Copyright 2024 IHP PDK Authors
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+     https://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+-->
+<layer-properties>
+ <properties>
+  <expanded>false</expanded>
+  <frame-color>#606060</frame-color>
+  <fill-color>#606060</fill-color>
+  <frame-brightness>0</frame-brightness>
+  <fill-brightness>0</fill-brightness>
+  <dither-pattern>I3</dither-pattern>
+  <line-style/>
+  <valid>true</valid>
+  <visible>true</visible>
+  <transparent>false</transparent>
+  <width>1</width>
+  <marked>false</marked>
+  <xfill>false</xfill>
+  <animation>0</animation>
+  <name>sub</name>
+  <source>300/0@1</source>
+ </properties>
+ <properties>
+  <expanded>false</expanded>
+  <frame-color>#80fffb</frame-color>
+  <fill-color>#80fffb</fill-color>
+  <frame-brightness>0</frame-brightness>
+  <fill-brightness>0</fill-brightness>
+  <dither-pattern>I3</dither-pattern>
+  <line-style/>
+  <valid>true</valid>
+  <visible>true</visible>
+  <transparent>false</transparent>
+  <width>1</width>
+  <marked>false</marked>
+  <xfill>false</xfill>
+  <animation>0</animation>
+  <name>imd0</name>
+  <source>302/0@1</source>
+ </properties>
+ <properties>
+  <expanded>false</expanded>
+  <frame-color>#80fffb</frame-color>
+  <fill-color>#80fffb</fill-color>
+  <frame-brightness>0</frame-brightness>
+  <fill-brightness>0</fill-brightness>
+  <dither-pattern>I3</dither-pattern>
+  <line-style/>
+  <valid>true</valid>
+  <visible>true</visible>
+  <transparent>false</transparent>
+  <width>1</width>
+  <marked>false</marked>
+  <xfill>false</xfill>
+  <animation>0</animation>
+  <name>imd1</name>
+  <source>303/0@1</source>
+ </properties>
+ <properties>
+  <expanded>false</expanded>
+  <frame-color>#80fffb</frame-color>
+  <fill-color>#80fffb</fill-color>
+  <frame-brightness>0</frame-brightness>
+  <fill-brightness>0</fill-brightness>
+  <dither-pattern>I3</dither-pattern>
+  <line-style/>
+  <valid>true</valid>
+  <visible>true</visible>
+  <transparent>false</transparent>
+  <width>1</width>
+  <marked>false</marked>
+  <xfill>false</xfill>
+  <animation>0</animation>
+  <name>imd2</name>
+  <source>304/0@1</source>
+ </properties>
+ <properties>
+  <expanded>false</expanded>
+  <frame-color>#80fffb</frame-color>
+  <fill-color>#80fffb</fill-color>
+  <frame-brightness>0</frame-brightness>
+  <fill-brightness>0</fill-brightness>
+  <dither-pattern>I3</dither-pattern>
+  <line-style/>
+  <valid>true</valid>
+  <visible>true</visible>
+  <transparent>false</transparent>
+  <width>1</width>
+  <marked>false</marked>
+  <xfill>false</xfill>
+  <animation>0</animation>
+  <name>imd3</name>
+  <source>305/0@1</source>
+ </properties>
+ <properties>
+  <expanded>false</expanded>
+  <frame-color>#80fffb</frame-color>
+  <fill-color>#80fffb</fill-color>
+  <frame-brightness>0</frame-brightness>
+  <fill-brightness>0</fill-brightness>
+  <dither-pattern>I3</dither-pattern>
+  <line-style/>
+  <valid>true</valid>
+  <visible>true</visible>
+  <transparent>false</transparent>
+  <width>1</width>
+  <marked>false</marked>
+  <xfill>false</xfill>
+  <animation>0</animation>
+  <name>imd4</name>
+  <source>306/0@1</source>
+ </properties>
+ <properties>
+  <expanded>false</expanded>
+  <frame-color>#80fffb</frame-color>
+  <fill-color>#80fffb</fill-color>
+  <frame-brightness>0</frame-brightness>
+  <fill-brightness>0</fill-brightness>
+  <dither-pattern>I3</dither-pattern>
+  <line-style/>
+  <valid>true</valid>
+  <visible>true</visible>
+  <transparent>false</transparent>
+  <width>1</width>
+  <marked>false</marked>
+  <xfill>false</xfill>
+  <animation>0</animation>
+  <name>imd5</name>
+  <source>307/0@1</source>
+ </properties>
+ <properties>
+  <expanded>false</expanded>
+  <frame-color>#80fffb</frame-color>
+  <fill-color>#80fffb</fill-color>
+  <frame-brightness>0</frame-brightness>
+  <fill-brightness>0</fill-brightness>
+  <dither-pattern>I3</dither-pattern>
+  <line-style/>
+  <valid>true</valid>
+  <visible>true</visible>
+  <transparent>false</transparent>
+  <width>1</width>
+  <marked>false</marked>
+  <xfill>false</xfill>
+  <animation>0</animation>
+  <name>imd6</name>
+  <source>308/0@1</source>
+ </properties>
+ <properties>
+  <expanded>false</expanded>
+  <frame-color>#80fffb</frame-color>
+  <fill-color>#80fffb</fill-color>
+  <frame-brightness>0</frame-brightness>
+  <fill-brightness>0</fill-brightness>
+  <dither-pattern>I3</dither-pattern>
+  <line-style/>
+  <valid>true</valid>
+  <visible>true</visible>
+  <transparent>false</transparent>
+  <width>1</width>
+  <marked>false</marked>
+  <xfill>false</xfill>
+  <animation>0</animation>
+  <name>passi1</name>
+  <source>309/0@1</source>
+ </properties>
+ <properties>
+  <expanded>false</expanded>
+  <frame-color>#c0c0c0</frame-color>
+  <fill-color>#c0c0c0</fill-color>
+  <frame-brightness>0</frame-brightness>
+  <fill-brightness>0</fill-brightness>
+  <dither-pattern>I3</dither-pattern>
+  <line-style/>
+  <valid>true</valid>
+  <visible>true</visible>
+  <transparent>false</transparent>
+  <width>1</width>
+  <marked>false</marked>
+  <xfill>false</xfill>
+  <animation>0</animation>
+  <name>passi2</name>
+  <source>310/0@1</source>
+ </properties>
+ <properties>
+  <expanded>false</expanded>
+  <frame-color>#ff0000</frame-color>
+  <fill-color>#ff0000</fill-color>
+  <frame-brightness>0</frame-brightness>
+  <fill-brightness>0</fill-brightness>
+  <dither-pattern>I3</dither-pattern>
+  <line-style/>
+  <valid>true</valid>
+  <visible>true</visible>
+  <transparent>false</transparent>
+  <width>1</width>
+  <marked>false</marked>
+  <xfill>false</xfill>
+  <animation>0</animation>
+  <name>mim_dielectric</name>
+  <source>311/0@1</source>
+ </properties>
+ <properties>
+  <expanded>false</expanded>
+  <frame-color>#00ff00</frame-color>
+  <fill-color>#00ff00</fill-color>
+  <frame-brightness>0</frame-brightness>
+  <fill-brightness>0</fill-brightness>
+  <dither-pattern>I12</dither-pattern>
+  <line-style/>
+  <valid>true</valid>
+  <visible>true</visible>
+  <transparent>false</transparent>
+  <width>1</width>
+  <marked>false</marked>
+  <xfill>false</xfill>
+  <animation>0</animation>
+  <name>ACTIV</name>
+  <source>400/0@1</source>
+ </properties>
+ <properties>
+  <expanded>false</expanded>
+  <frame-color>#39bfff</frame-color>
+  <fill-color>#39bfff</fill-color>
+  <frame-brightness>0</frame-brightness>
+  <fill-brightness>0</fill-brightness>
+  <dither-pattern>I12</dither-pattern>
+  <line-style/>
+  <valid>true</valid>
+  <visible>true</visible>
+  <transparent>false</transparent>
+  <width>1</width>
+  <marked>false</marked>
+  <xfill>false</xfill>
+  <animation>0</animation>
+  <name>METAL1</name>
+  <source>401/0@1</source>
+ </properties>
+ <properties>
+  <expanded>false</expanded>
+  <frame-color>#ccccd9</frame-color>
+  <fill-color>#ccccd9</fill-color>
+  <frame-brightness>0</frame-brightness>
+  <fill-brightness>0</fill-brightness>
+  <dither-pattern>I12</dither-pattern>
+  <line-style/>
+  <valid>true</valid>
+  <visible>true</visible>
+  <transparent>false</transparent>
+  <width>1</width>
+  <marked>false</marked>
+  <xfill>false</xfill>
+  <animation>0</animation>
+  <name>METAL2</name>
+  <source>402/0@1</source>
+ </properties>
+ <properties>
+  <expanded>false</expanded>
+  <frame-color>#d80000</frame-color>
+  <fill-color>#d80000</fill-color>
+  <frame-brightness>0</frame-brightness>
+  <fill-brightness>0</fill-brightness>
+  <dither-pattern>I12</dither-pattern>
+  <line-style/>
+  <valid>true</valid>
+  <visible>true</visible>
+  <transparent>false</transparent>
+  <width>1</width>
+  <marked>false</marked>
+  <xfill>false</xfill>
+  <animation>0</animation>
+  <name>METAL3</name>
+  <source>403/0@1</source>
+ </properties>
+ <properties>
+  <expanded>false</expanded>
+  <frame-color>#93e837</frame-color>
+  <fill-color>#93e837</fill-color>
+  <frame-brightness>0</frame-brightness>
+  <fill-brightness>0</fill-brightness>
+  <dither-pattern>I12</dither-pattern>
+  <line-style/>
+  <valid>true</valid>
+  <visible>true</visible>
+  <transparent>false</transparent>
+  <width>1</width>
+  <marked>false</marked>
+  <xfill>false</xfill>
+  <animation>0</animation>
+  <name>METAL4</name>
+  <source>404/0@1</source>
+ </properties>
+ <properties>
+  <expanded>false</expanded>
+  <frame-color>#dcd146</frame-color>
+  <fill-color>#dcd146</fill-color>
+  <frame-brightness>0</frame-brightness>
+  <fill-brightness>0</fill-brightness>
+  <dither-pattern>I12</dither-pattern>
+  <line-style/>
+  <valid>true</valid>
+  <visible>true</visible>
+  <transparent>false</transparent>
+  <width>1</width>
+  <marked>false</marked>
+  <xfill>false</xfill>
+  <animation>0</animation>
+  <name>METAL5</name>
+  <source>405/0@1</source>
+ </properties>
+ <properties>
+  <expanded>false</expanded>
+  <frame-color>#ffe6bf</frame-color>
+  <fill-color>#ffe6bf</fill-color>
+  <frame-brightness>0</frame-brightness>
+  <fill-brightness>0</fill-brightness>
+  <dither-pattern>I12</dither-pattern>
+  <line-style/>
+  <valid>true</valid>
+  <visible>true</visible>
+  <transparent>false</transparent>
+  <width>1</width>
+  <marked>false</marked>
+  <xfill>false</xfill>
+  <animation>0</animation>
+  <name>TOPMETAL1</name>
+  <source>406/0@1</source>
+ </properties>
+ <properties>
+  <expanded>false</expanded>
+  <frame-color>#ff8000</frame-color>
+  <fill-color>#ff8000</fill-color>
+  <frame-brightness>0</frame-brightness>
+  <fill-brightness>0</fill-brightness>
+  <dither-pattern>I12</dither-pattern>
+  <line-style/>
+  <valid>true</valid>
+  <visible>true</visible>
+  <transparent>false</transparent>
+  <width>1</width>
+  <marked>false</marked>
+  <xfill>false</xfill>
+  <animation>0</animation>
+  <name>TOPMETAL2</name>
+  <source>407/0@1</source>
+ </properties>
+ <properties>
+  <expanded>false</expanded>
+  <frame-color>#268c6b</frame-color>
+  <fill-color>#268c6b</fill-color>
+  <frame-brightness>0</frame-brightness>
+  <fill-brightness>0</fill-brightness>
+  <dither-pattern>I12</dither-pattern>
+  <line-style/>
+  <valid>true</valid>
+  <visible>true</visible>
+  <transparent>false</transparent>
+  <width>1</width>
+  <marked>false</marked>
+  <xfill>false</xfill>
+  <animation>0</animation>
+  <name>MIM</name>
+  <source>408/0@1</source>
+ </properties>
+ <properties>
+  <expanded>false</expanded>
+  <frame-color>#00ffff</frame-color>
+  <fill-color>#00ffff</fill-color>
+  <frame-brightness>0</frame-brightness>
+  <fill-brightness>0</fill-brightness>
+  <dither-pattern>I2</dither-pattern>
+  <line-style/>
+  <valid>true</valid>
+  <visible>true</visible>
+  <transparent>false</transparent>
+  <width>1</width>
+  <marked>false</marked>
+  <xfill>false</xfill>
+  <animation>0</animation>
+  <name>CONT</name>
+  <source>500/0@1</source>
+ </properties>
+ <properties>
+  <expanded>false</expanded>
+  <frame-color>#ccccff</frame-color>
+  <fill-color>#ccccff</fill-color>
+  <frame-brightness>0</frame-brightness>
+  <fill-brightness>0</fill-brightness>
+  <dither-pattern>I2</dither-pattern>
+  <line-style/>
+  <valid>true</valid>
+  <visible>true</visible>
+  <transparent>false</transparent>
+  <width>1</width>
+  <marked>false</marked>
+  <xfill>false</xfill>
+  <animation>0</animation>
+  <name>VIA1</name>
+  <source>501/0@1</source>
+ </properties>
+ <properties>
+  <expanded>false</expanded>
+  <frame-color>#ff3736</frame-color>
+  <fill-color>#ff3736</fill-color>
+  <frame-brightness>0</frame-brightness>
+  <fill-brightness>0</fill-brightness>
+  <dither-pattern>I2</dither-pattern>
+  <line-style/>
+  <valid>true</valid>
+  <visible>true</visible>
+  <transparent>false</transparent>
+  <width>1</width>
+  <marked>false</marked>
+  <xfill>false</xfill>
+  <animation>0</animation>
+  <name>VIA2</name>
+  <source>502/0@1</source>
+ </properties>
+ <properties>
+  <expanded>false</expanded>
+  <frame-color>#9ba940</frame-color>
+  <fill-color>#9ba940</fill-color>
+  <frame-brightness>0</frame-brightness>
+  <fill-brightness>0</fill-brightness>
+  <dither-pattern>I2</dither-pattern>
+  <line-style/>
+  <valid>true</valid>
+  <visible>true</visible>
+  <transparent>false</transparent>
+  <width>1</width>
+  <marked>false</marked>
+  <xfill>false</xfill>
+  <animation>0</animation>
+  <name>VIA3</name>
+  <source>503/0@1</source>
+ </properties>
+ <properties>
+  <expanded>false</expanded>
+  <frame-color>#deac5e</frame-color>
+  <fill-color>#deac5e</fill-color>
+  <frame-brightness>0</frame-brightness>
+  <fill-brightness>0</fill-brightness>
+  <dither-pattern>I2</dither-pattern>
+  <line-style/>
+  <valid>true</valid>
+  <visible>true</visible>
+  <transparent>false</transparent>
+  <width>1</width>
+  <marked>false</marked>
+  <xfill>false</xfill>
+  <animation>0</animation>
+  <name>VIA4</name>
+  <source>504/0@1</source>
+ </properties>
+ <properties>
+  <expanded>false</expanded>
+  <frame-color>#ffe6bf</frame-color>
+  <fill-color>#ffe6bf</fill-color>
+  <frame-brightness>0</frame-brightness>
+  <fill-brightness>0</fill-brightness>
+  <dither-pattern>I2</dither-pattern>
+  <line-style/>
+  <valid>true</valid>
+  <visible>true</visible>
+  <transparent>false</transparent>
+  <width>1</width>
+  <marked>false</marked>
+  <xfill>false</xfill>
+  <animation>0</animation>
+  <name>TOPVIA1</name>
+  <source>505/0@1</source>
+ </properties>
+ <properties>
+  <expanded>false</expanded>
+  <frame-color>#ff8000</frame-color>
+  <fill-color>#ff8000</fill-color>
+  <frame-brightness>0</frame-brightness>
+  <fill-brightness>0</fill-brightness>
+  <dither-pattern>I2</dither-pattern>
+  <line-style/>
+  <valid>true</valid>
+  <visible>true</visible>
+  <transparent>false</transparent>
+  <width>1</width>
+  <marked>false</marked>
+  <xfill>false</xfill>
+  <animation>0</animation>
+  <name>TOPVIA2</name>
+  <source>506/0@1</source>
+ </properties>
+ <properties>
+  <expanded>false</expanded>
+  <frame-color>#ffe6bf</frame-color>
+  <fill-color>#ffe6bf</fill-color>
+  <frame-brightness>0</frame-brightness>
+  <fill-brightness>0</fill-brightness>
+  <dither-pattern>I2</dither-pattern>
+  <line-style/>
+  <valid>true</valid>
+  <visible>true</visible>
+  <transparent>false</transparent>
+  <width>1</width>
+  <marked>false</marked>
+  <xfill>false</xfill>
+  <animation>0</animation>
+  <name>VMIM</name>
+  <source>507/0@1</source>
+ </properties>
+ <name/>
+</layer-properties>
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/xsect/sg13g2_for_EM.xs b/ihp-sg13g2/libs.tech/klayout/tech/xsect/sg13g2_for_EM.xs
new file mode 100644
index 00000000..3f611c0a
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/xsect/sg13g2_for_EM.xs
@@ -0,0 +1,183 @@
+# Copyright 2024 IHP PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Cross section file for KLayout xsection tool
+# Version 7-August-2024: updated to support MIM
+#
+# Limitations:
+# - No support for active devices (layers below ACTIV)
+
+
+# Prepare input layers
+mask_ACTIV = layer("1/0")
+mask_METAL1    = layer("8/0")
+mask_METAL2    = layer("10/0")
+mask_METAL3    = layer("30/0")
+mask_METAL4    = layer("50/0")
+mask_METAL5    = layer("67/0")
+mask_MIM   = layer("36/0")
+mask_TM1   = layer("126/0")
+mask_TM2   = layer("134/0")
+
+mask_CONT  = layer("6/0")
+mask_VIA1  = layer("19/0")
+mask_VIA2  = layer("29/0")
+mask_VIA3  = layer("49/0")
+mask_VIA4  = layer("66/0")
+mask_VMIM  = layer("129/0")
+mask_TOPVIA1  = layer("125/0")
+mask_TOPVIA2  = layer("133/0")
+
+# height of processing windows above substrate
+height(20)
+
+# Process steps:
+# Now we move to cross section view: from the layout geometry we create
+# a material stack by simulating the process step by step.
+# The basic idea is that all activity happens at the surface. We can
+# deposit material (over existing or at a mask), etch material and
+# planarize.
+
+# Start with the bulk material and assign that to material "substrate"
+# "bulk" delivers the wafer's cross section.
+
+substrate = bulk
+z = 0
+
+# TO DO: add EPI
+# t_epi = 3.75
+# epi = deposit(t_epi)
+# z = z + t_epi
+
+
+# ACTIV and CONT
+t_activ = 0.4
+t_cont  = 0.64
+activ  = mask(mask_ACTIV).grow(t_activ)
+cont  = mask(mask_CONT).grow(t_cont)
+imd0 = deposit(t_activ+t_cont)
+z = z + t_activ + t_cont
+planarize(:to => z, :into => imd0)
+
+# METAL1 and VIA1
+t_metal1 = 0.42
+t_via1   = 0.54
+metal1   = mask(mask_METAL1).grow(t_metal1)
+via1     = mask(mask_VIA1).grow(t_via1)
+imd1 = deposit(t_metal1+t_via1)
+z = z + t_metal1 + t_via1
+planarize(:to => z, :into => imd1)
+
+# METAL2 and VIA2
+t_metal2 = 0.49
+t_via2   = 0.54
+metal2   = mask(mask_METAL2).grow(t_metal2)
+via2     = mask(mask_VIA2).grow(t_via2)
+imd2 = deposit(t_metal2+t_via2)
+z = z + t_metal2 + t_via2
+planarize(:to => z, :into => imd2)
+
+# METAL3 and VIA3
+t_metal3 = 0.49
+t_via3   = 0.54
+metal3   = mask(mask_METAL3).grow(t_metal3)
+via3     = mask(mask_VIA3).grow(t_via3)
+imd3 = deposit(t_metal3+t_via3)
+z = z + t_metal3 + t_via3
+planarize(:to => z, :into => imd3)
+
+# METAL4 and VIA4
+t_metal4 = 0.49
+t_via4   = 0.54
+metal4   = mask(mask_METAL4).grow(t_metal4)
+via4     = mask(mask_VIA4).grow(t_via4)
+imd4 = deposit(t_metal4+t_via4)
+z = z + t_metal4 + t_via4
+planarize(:to => z, :into => imd4)
+
+# Metal5 and TopVia1
+t_metal5  = 0.49
+t_topvia1 = 0.85
+metal5    = mask(mask_METAL5).grow(t_metal5)
+topvia1   = mask(mask_TOPVIA1).grow(t_topvia1)
+
+t_mimdiel = 0.04
+mimdiel   = mask(mask_MIM).grow(t_mimdiel)
+t_mim     = 0.15
+mim       = mask(mask_MIM).grow(t_mim)
+
+t_vmim    = t_topvia1-t_mim-t_mimdiel
+vmim 	  = mask(mask_VMIM).grow(t_vmim)
+
+imd5     = deposit(t_metal5+t_topvia1)
+z = z + t_metal5 + t_topvia1
+planarize(:to => z, :into => imd5)
+
+# TopMetal1 and TopVia2
+t_tm1     = 2.0
+t_topvia2 = 2.8
+tm1       = mask(mask_TM1).grow(t_tm1)
+topvia2   = mask(mask_TOPVIA2).grow(t_topvia2)
+imd6 = deposit(t_tm1+t_topvia2)
+z = z + t_tm1 + t_topvia2
+planarize(:to => z, :into => imd6)
+
+
+# TopMetal2
+t_tm2 = 3
+tm2   = mask(mask_TM2).grow(t_tm2)
+
+# Passivation
+t_passi1 = 1.5
+t_passi2 = 0.4
+passi1 = deposit(t_passi1, 0.6)
+passi2 = deposit(t_passi2, 0.4)
+
+
+
+output("300/0", substrate)
+# output("301/0", epi)
+output("302/0", imd0)
+output("303/0", imd1)
+output("304/0", imd2)
+output("305/0", imd3)
+output("306/0", imd4)
+output("307/0", imd5)
+output("308/0", imd6)
+output("309/0", passi1)
+output("310/0", passi2)
+output("311/0", mimdiel)
+
+
+output("400/0", activ)
+output("401/0", metal1)
+output("402/0", metal2)
+output("403/0", metal3)
+output("404/0", metal4)
+output("405/0", metal5)
+output("406/0", tm1)
+output("407/0", tm2)
+output("408/0", mim)
+
+output("500/0", cont)
+output("501/0", via1)
+output("502/0", via2)
+output("503/0", via3)
+output("504/0", via4)
+output("505/0", topvia1)
+output("506/0", topvia2)
+output("507/0", vmim)
+
+
+
diff --git a/ihp-sg13g2/libs.tech/ngspice/.spiceinit b/ihp-sg13g2/libs.tech/ngspice/.spiceinit
new file mode 100644
index 00000000..089f9020
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/ngspice/.spiceinit
@@ -0,0 +1,29 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+
+* this option produces error in the AC/SP simulation
+*option savecurrents
+
+set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/openvaf/psp103_nqs.osdi'
+
diff --git a/ihp-sg13g2/libs.tech/ngspice/models/cornerCAP.lib b/ihp-sg13g2/libs.tech/ngspice/models/cornerCAP.lib
index 540fc62a..bfe682a0 100644
--- a/ihp-sg13g2/libs.tech/ngspice/models/cornerCAP.lib
+++ b/ihp-sg13g2/libs.tech/ngspice/models/cornerCAP.lib
@@ -19,16 +19,16 @@
 **************** CORNERS OF CAPACITORS ****************  
 * Typical without statistical modeling          
 .LIB cap_typ  
-.parameters cap_carea = 1.5E-15
-.parameters cap_cpara  = 1.0
+.param cap_carea = 1.5E-15
+.param cap_cpara  = 1.0
            
 .include capacitors_mod.lib
 .ENDL cap_typ
   
 * Typical with statistical modeling
 .LIB cap_typ_stat  
-.parameters cap_carea_norm = 1.5E-15
-.parameters cap_cpara_norm  = 1.0
+.param cap_carea_norm = 1.5E-15
+.param cap_cpara_norm  = 1.0
            
 .include capacitors_stat.lib
 .include capacitors_mod.lib
@@ -36,16 +36,16 @@
 
 * Best Case without statistical modeling
 .LIB cap_bcs  
-.parameters cap_carea = 0.9*1.5E-15
-.parameters cap_cpara  = 0.9
+.param cap_carea = 0.9*1.5E-15
+.param cap_cpara  = 0.9
            
 .include capacitors_mod.lib
 .ENDL cap_bcs
       
 * Best Case with statistical modeling
 .LIB cap_bcs_stat  
-.parameters cap_carea_norm = 0.9*1.5E-15
-.parameters cap_cpara_norm  = 0.9
+.param cap_carea_norm = 0.9*1.5E-15
+.param cap_cpara_norm  = 0.9
 
            
 .include capacitors_stat.lib
@@ -54,16 +54,16 @@
       
 * Worst Case without statistical modeling
 .LIB cap_wcs 
-.parameters cap_carea = 1.1*1.5E-15
-.parameters cap_cpara  = 1.1
+.param cap_carea = 1.1*1.5E-15
+.param cap_cpara  = 1.1
            
 .include capacitors_mod.lib
 .ENDL cap_wcs
       
 * Worst Case with statistical modeling
 .LIB cap_wcs_stat  
-.parameters cap_carea_norm = 1.1*1.5E-15
-.parameters cap_cpara_norm  = 1.1
+.param cap_carea_norm = 1.1*1.5E-15
+.param cap_cpara_norm  = 1.1
            
 .include capacitors_stat.lib
 .include capacitors_mod.lib
diff --git a/ihp-sg13g2/libs.tech/ngspice/models/cornerHBT.lib b/ihp-sg13g2/libs.tech/ngspice/models/cornerHBT.lib
index 5b6d3dd7..1ccb187d 100644
--- a/ihp-sg13g2/libs.tech/ngspice/models/cornerHBT.lib
+++ b/ihp-sg13g2/libs.tech/ngspice/models/cornerHBT.lib
@@ -17,135 +17,135 @@
 *#######################################################################
        
 .LIB hbt_typ
-.parameters vbic_cje = 1.0
-.parameters vbic_cjc = 1.0
-.parameters vbic_cjcp = 1.0
-.parameters vbic_is = 1.0
-.parameters vbic_ibei = 1.0
-.parameters vbic_re = 1.0
-.parameters vbic_rcx = 1.0
-.parameters vbic_rbx = 1.0
-.parameters vbic_tf = 1.0
+.param vbic_cje = 1.0
+.param vbic_cjc = 1.0
+.param vbic_cjcp = 1.0
+.param vbic_is = 1.0
+.param vbic_ibei = 1.0
+.param vbic_re = 1.0
+.param vbic_rcx = 1.0
+.param vbic_rbx = 1.0
+.param vbic_tf = 1.0
 
-.parameters sgp_mpa_cje = 1.0
-.parameters sgp_mpa_cjc = 1.0
-.parameters sgp_mpa_is = 1.0
-.parameters sgp_mpa_bf = 1.0
-.parameters sgp_mpa_re = 1.0
-.parameters sgp_mpa_rb = 1.0
-.parameters sgp_mpa_rc = 1.0
+.param sgp_mpa_cje = 1.0
+.param sgp_mpa_cjc = 1.0
+.param sgp_mpa_is = 1.0
+.param sgp_mpa_bf = 1.0
+.param sgp_mpa_re = 1.0
+.param sgp_mpa_rb = 1.0
+.param sgp_mpa_rc = 1.0
 
 .include sg13g2_hbt_mod.lib
 .ENDL hbt_typ
        
 .LIB hbt_typ_stat
-.parameters vbic_cje_norm = 1.0 
-.parameters vbic_cjc_norm = 1.0
-.parameters vbic_cjcp_norm = 1.0
-.parameters vbic_is_norm = 1.0
-.parameters vbic_ibei_norm = 1.0
-.parameters vbic_re_norm = 1.0
-.parameters vbic_rcx_norm = 1.0
-.parameters vbic_rbx_norm = 1.0
-.parameters vbic_tf = 1.0
+.param vbic_cje_norm = 1.0 
+.param vbic_cjc_norm = 1.0
+.param vbic_cjcp_norm = 1.0
+.param vbic_is_norm = 1.0
+.param vbic_ibei_norm = 1.0
+.param vbic_re_norm = 1.0
+.param vbic_rcx_norm = 1.0
+.param vbic_rbx_norm = 1.0
+.param vbic_tf = 1.0
 
-.parameters sgp_mpa_cje_norm = 1.0
-.parameters sgp_mpa_cjc_norm = 1.0
-.parameters sgp_mpa_is_norm = 1.0
-.parameters sgp_mpa_bf_norm = 1.0
-.parameters sgp_mpa_re_norm = 1.0
-.parameters sgp_mpa_rb_norm = 1.0
-.parameters sgp_mpa_rc_norm = 1.0
+.param sgp_mpa_cje_norm = 1.0
+.param sgp_mpa_cjc_norm = 1.0
+.param sgp_mpa_is_norm = 1.0
+.param sgp_mpa_bf_norm = 1.0
+.param sgp_mpa_re_norm = 1.0
+.param sgp_mpa_rb_norm = 1.0
+.param sgp_mpa_rc_norm = 1.0
 
 .include sg13g2_hbt_stat.lib
 .include sg13g2_hbt_mod.lib
 .ENDL hbt_typ_stat
            
 .LIB hbt_bcs
-.parameters vbic_cje = 0.83
-.parameters vbic_cjc = 0.87
-.parameters vbic_cjcp = 0.89
-.parameters vbic_is = 1.26
-.parameters vbic_ibei = 0.67
-.parameters vbic_re = 0.73
-.parameters vbic_rcx = 0.79
-.parameters vbic_rbx = 0.88
-.parameters vbic_tf = 0.89
+.param vbic_cje = 0.83
+.param vbic_cjc = 0.87
+.param vbic_cjcp = 0.89
+.param vbic_is = 1.26
+.param vbic_ibei = 0.67
+.param vbic_re = 0.73
+.param vbic_rcx = 0.79
+.param vbic_rbx = 0.88
+.param vbic_tf = 0.89
 
-.parameters sgp_mpa_cje = 0.955
-.parameters sgp_mpa_cjc = 0.98
-.parameters sgp_mpa_is = 1.13
-.parameters sgp_mpa_bf = 1.24
-.parameters sgp_mpa_re = 0.952
-.parameters sgp_mpa_rb = 0.975
-.parameters sgp_mpa_rc = 0.95
+.param sgp_mpa_cje = 0.955
+.param sgp_mpa_cjc = 0.98
+.param sgp_mpa_is = 1.13
+.param sgp_mpa_bf = 1.24
+.param sgp_mpa_re = 0.952
+.param sgp_mpa_rb = 0.975
+.param sgp_mpa_rc = 0.95
 
 .include sg13g2_hbt_mod.lib
 .ENDL hbt_bcs
        
 .LIB hbt_bcs_stat
-.parameters vbic_cje_norm = 0.83 
-.parameters vbic_cjc_norm = 0.87
-.parameters vbic_cjcp_norm = 0.89
-.parameters vbic_is_norm = 1.26
-.parameters vbic_ibei_norm = 0.67
-.parameters vbic_re_norm = 0.73
-.parameters vbic_rcx_norm = 0.79
-.parameters vbic_rbx_norm = 0.88
-.parameters vbic_tf = 0.89
+.param vbic_cje_norm = 0.83 
+.param vbic_cjc_norm = 0.87
+.param vbic_cjcp_norm = 0.89
+.param vbic_is_norm = 1.26
+.param vbic_ibei_norm = 0.67
+.param vbic_re_norm = 0.73
+.param vbic_rcx_norm = 0.79
+.param vbic_rbx_norm = 0.88
+.param vbic_tf = 0.89
 
-.parameters sgp_mpa_cje_norm = 0.955
-.parameters sgp_mpa_cjc_norm = 0.98
-.parameters sgp_mpa_is_norm = 1.13
-.parameters sgp_mpa_bf_norm = 1.24
-.parameters sgp_mpa_re_norm = 0.952
-.parameters sgp_mpa_rb_norm = 0.975
-.parameters sgp_mpa_rc_norm = 0.95
+.param sgp_mpa_cje_norm = 0.955
+.param sgp_mpa_cjc_norm = 0.98
+.param sgp_mpa_is_norm = 1.13
+.param sgp_mpa_bf_norm = 1.24
+.param sgp_mpa_re_norm = 0.952
+.param sgp_mpa_rb_norm = 0.975
+.param sgp_mpa_rc_norm = 0.95
 
 .include sg13g2_hbt_stat.lib
 .include sg13g2_hbt_mod.lib
 .ENDL hbt_bcs_stat
            
 .LIB hbt_wcs
-.parameters vbic_cje = 1.17
-.parameters vbic_cjc = 1.13
-.parameters vbic_cjcp = 1.11
-.parameters vbic_is = 0.74
-.parameters vbic_ibei = 1.33
-.parameters vbic_re = 1.27
-.parameters vbic_rcx = 1.21
-.parameters vbic_rbx = 1.12
-.parameters vbic_tf = 1.11
+.param vbic_cje = 1.17
+.param vbic_cjc = 1.13
+.param vbic_cjcp = 1.11
+.param vbic_is = 0.74
+.param vbic_ibei = 1.33
+.param vbic_re = 1.27
+.param vbic_rcx = 1.21
+.param vbic_rbx = 1.12
+.param vbic_tf = 1.11
 
-.parameters sgp_mpa_cje = 1.045
-.parameters sgp_mpa_cjc = 1.02
-.parameters sgp_mpa_is = 0.87
-.parameters sgp_mpa_bf = 0.76
-.parameters sgp_mpa_re = 1.048
-.parameters sgp_mpa_rb = 1.025
-.parameters sgp_mpa_rc = 1.05
+.param sgp_mpa_cje = 1.045
+.param sgp_mpa_cjc = 1.02
+.param sgp_mpa_is = 0.87
+.param sgp_mpa_bf = 0.76
+.param sgp_mpa_re = 1.048
+.param sgp_mpa_rb = 1.025
+.param sgp_mpa_rc = 1.05
 
 .include sg13g2_hbt_mod.lib
 .ENDL hbt_wcs
        
 .LIB hbt_wcs_stat
-.parameters vbic_cje_norm = 1.17 
-.parameters vbic_cjc_norm = 1.13
-.parameters vbic_cjcp_norm = 1.11
-.parameters vbic_is_norm = 0.74
-.parameters vbic_ibei_norm = 1.33
-.parameters vbic_re_norm = 1.27
-.parameters vbic_rcx_norm = 1.21
-.parameters vbic_rbx_norm = 1.12
-.parameters vbic_tf = 1.11
+.param vbic_cje_norm = 1.17 
+.param vbic_cjc_norm = 1.13
+.param vbic_cjcp_norm = 1.11
+.param vbic_is_norm = 0.74
+.param vbic_ibei_norm = 1.33
+.param vbic_re_norm = 1.27
+.param vbic_rcx_norm = 1.21
+.param vbic_rbx_norm = 1.12
+.param vbic_tf = 1.11
 
-.parameters sgp_mpa_cje_norm = 1.045
-.parameters sgp_mpa_cjc_norm = 1.02
-.parameters sgp_mpa_is_norm = 0.87
-.parameters sgp_mpa_bf_norm = 0.76
-.parameters sgp_mpa_re_norm = 1.048
-.parameters sgp_mpa_rb_norm = 1.025
-.parameters sgp_mpa_rc_norm = 1.05
+.param sgp_mpa_cje_norm = 1.045
+.param sgp_mpa_cjc_norm = 1.02
+.param sgp_mpa_is_norm = 0.87
+.param sgp_mpa_bf_norm = 0.76
+.param sgp_mpa_re_norm = 1.048
+.param sgp_mpa_rb_norm = 1.025
+.param sgp_mpa_rc_norm = 1.05
 
 .include sg13g2_hbt_stat.lib
 .include sg13g2_hbt_mod.lib
diff --git a/ihp-sg13g2/libs.tech/ngspice/models/cornerMOShv.lib b/ihp-sg13g2/libs.tech/ngspice/models/cornerMOShv.lib
index 0a3c546d..e70718a3 100644
--- a/ihp-sg13g2/libs.tech/ngspice/models/cornerMOShv.lib
+++ b/ihp-sg13g2/libs.tech/ngspice/models/cornerMOShv.lib
@@ -44,7 +44,7 @@
 
 * Monte-Carlo begin ---------------------------------------------
 *
-* NOTE: default of all   parameters should be 1.0
+* NOTE: default of all  .param should be 1.0
 * NOTE: deviations from 1.0 are used to fit statistical results
 * 
 *
@@ -73,94 +73,94 @@
 **************** CORNER_LIB OF sg13g2_hv TT MODEL ****************  
 * Typical without statistical     
 .LIB mos_tt
-  .parameters sg13g2_hv_nmos_vfbo_mm= 1.0
-  .parameters sg13g2_hv_nmos_rsgo   = 1.0000
-  .parameters sg13g2_hv_nmos_rsw1   = 0.7886
-  .parameters sg13g2_hv_nmos_mueo   = 1.0780
-  .parameters sg13g2_hv_nmos_dphibo = 1.4388
-  .parameters sg13g2_hv_nmos_dphibl = 1.5299
-  .parameters sg13g2_hv_nmos_dphibw = 1.0000
-  .parameters sg13g2_hv_nmos_dphiblw= 0.8712
-  .parameters sg13g2_hv_nmos_ctl    = 1.0000
-  .parameters sg13g2_hv_nmos_thesato= 1.0000
-  .parameters sg13g2_hv_nmos_thesatl= 1.0350
-  .parameters sg13g2_hv_nmos_thesatw= 1.0000
-  .parameters sg13g2_hv_nmos_thesatlw= 1.6050
-  .parameters sg13g2_hv_nmos_toxo   = 1.0000
-  .parameters sg13g2_hv_nmos_toxovo = 1.0000
-  .parameters sg13g2_hv_nmos_cjorbot= 1.0000
-  .parameters sg13g2_hv_nmos_cjorsti= 1.0000
-  .parameters sg13g2_hv_nmos_cjorgat= 1.0000
+  .param sg13g2_hv_nmos_vfbo_mm= 1.0
+  .param sg13g2_hv_nmos_rsgo   = 1.0000
+  .param sg13g2_hv_nmos_rsw1   = 0.7886
+  .param sg13g2_hv_nmos_mueo   = 1.0780
+  .param sg13g2_hv_nmos_dphibo = 1.4388
+  .param sg13g2_hv_nmos_dphibl = 1.5299
+  .param sg13g2_hv_nmos_dphibw = 1.0000
+  .param sg13g2_hv_nmos_dphiblw= 0.8712
+  .param sg13g2_hv_nmos_ctl    = 1.0000
+  .param sg13g2_hv_nmos_thesato= 1.0000
+  .param sg13g2_hv_nmos_thesatl= 1.0350
+  .param sg13g2_hv_nmos_thesatw= 1.0000
+  .param sg13g2_hv_nmos_thesatlw= 1.6050
+  .param sg13g2_hv_nmos_toxo   = 1.0000
+  .param sg13g2_hv_nmos_toxovo = 1.0000
+  .param sg13g2_hv_nmos_cjorbot= 1.0000
+  .param sg13g2_hv_nmos_cjorsti= 1.0000
+  .param sg13g2_hv_nmos_cjorgat= 1.0000
 
-  .parameters sg13g2_hv_pmos_vfbo_mm= 1.0
-  .parameters sg13g2_hv_pmos_rsgo   = 1.1110
-  .parameters sg13g2_hv_pmos_rsw1   = 1.0000
-  .parameters sg13g2_hv_pmos_mueo   = 0.9605
-  .parameters sg13g2_hv_pmos_dphibo = 1.0010
-  .parameters sg13g2_hv_pmos_dphibl = 0.9504
-  .parameters sg13g2_hv_pmos_dphibw = 1.4080
-  .parameters sg13g2_hv_pmos_dphiblw= -0.1693
-  .parameters sg13g2_hv_pmos_bgidlo = 0.8409
-  .parameters sg13g2_hv_pmos_thesato= 1.0000
-  .parameters sg13g2_hv_pmos_thesatl= 0.4814
-  .parameters sg13g2_hv_pmos_thesatw= 5.7745
-  .parameters sg13g2_hv_pmos_thesatlw= 1.0000
-  .parameters sg13g2_hv_pmos_csl    = 1.0000
-  .parameters sg13g2_hv_pmos_toxo   = 1.0000
-  .parameters sg13g2_hv_pmos_toxovo = 1.0000
-  .parameters sg13g2_hv_pmos_cjorbot= 1.0000
-  .parameters sg13g2_hv_pmos_cjorsti= 1.0000
-  .parameters sg13g2_hv_pmos_cjorgat= 1.0000
+  .param sg13g2_hv_pmos_vfbo_mm= 1.0
+  .param sg13g2_hv_pmos_rsgo   = 1.1110
+  .param sg13g2_hv_pmos_rsw1   = 1.0000
+  .param sg13g2_hv_pmos_mueo   = 0.9605
+  .param sg13g2_hv_pmos_dphibo = 1.0010
+  .param sg13g2_hv_pmos_dphibl = 0.9504
+  .param sg13g2_hv_pmos_dphibw = 1.4080
+  .param sg13g2_hv_pmos_dphiblw= -0.1693
+  .param sg13g2_hv_pmos_bgidlo = 0.8409
+  .param sg13g2_hv_pmos_thesato= 1.0000
+  .param sg13g2_hv_pmos_thesatl= 0.4814
+  .param sg13g2_hv_pmos_thesatw= 5.7745
+  .param sg13g2_hv_pmos_thesatlw= 1.0000
+  .param sg13g2_hv_pmos_csl    = 1.0000
+  .param sg13g2_hv_pmos_toxo   = 1.0000
+  .param sg13g2_hv_pmos_toxovo = 1.0000
+  .param sg13g2_hv_pmos_cjorbot= 1.0000
+  .param sg13g2_hv_pmos_cjorsti= 1.0000
+  .param sg13g2_hv_pmos_cjorgat= 1.0000
 
-  .parameters sg13g2_hv_svaricap_lap   = 0.8     
-  .parameters sg13g2_hv_svaricap_toxo  = 1     
+  .param sg13g2_hv_svaricap_lap   = 0.8     
+  .param sg13g2_hv_svaricap_toxo  = 1     
   
   .include sg13g2_moshv_mod.lib
 .ENDL mos_tt  
   
 * Typical with statistical     
 .LIB mos_tt_stat 
-  .parameters sg13g2_hv_nmos_vfbo_mm_norm= 1.0
-  .parameters sg13g2_hv_nmos_rsgo_norm   = 1.0000
-  .parameters sg13g2_hv_nmos_rsw1_norm   = 0.7886
-  .parameters sg13g2_hv_nmos_mueo_norm   = 1.0780
-  .parameters sg13g2_hv_nmos_dphibo_norm = 1.4388
-  .parameters sg13g2_hv_nmos_dphibl_norm = 1.5299
-  .parameters sg13g2_hv_nmos_dphibw_norm = 1.0000
-  .parameters sg13g2_hv_nmos_dphiblw_norm= 0.8712
-  .parameters sg13g2_hv_nmos_ctl_norm    = 1.0000
-  .parameters sg13g2_hv_nmos_thesato_norm= 1.0000
-  .parameters sg13g2_hv_nmos_thesatl_norm= 1.0350
-  .parameters sg13g2_hv_nmos_thesatw_norm= 1.0000
-  .parameters sg13g2_hv_nmos_thesatlw_norm= 1.6050
-  .parameters sg13g2_hv_nmos_toxo_norm   = 1.0000
-  .parameters sg13g2_hv_nmos_toxovo_norm = 1.0000
-  .parameters sg13g2_hv_nmos_cjorbot_norm= 1.0000
-  .parameters sg13g2_hv_nmos_cjorsti_norm= 1.0000
-  .parameters sg13g2_hv_nmos_cjorgat_norm= 1.0000
+  .param sg13g2_hv_nmos_vfbo_mm_norm= 1.0
+  .param sg13g2_hv_nmos_rsgo_norm   = 1.0000
+  .param sg13g2_hv_nmos_rsw1_norm   = 0.7886
+  .param sg13g2_hv_nmos_mueo_norm   = 1.0780
+  .param sg13g2_hv_nmos_dphibo_norm = 1.4388
+  .param sg13g2_hv_nmos_dphibl_norm = 1.5299
+  .param sg13g2_hv_nmos_dphibw_norm = 1.0000
+  .param sg13g2_hv_nmos_dphiblw_norm= 0.8712
+  .param sg13g2_hv_nmos_ctl_norm    = 1.0000
+  .param sg13g2_hv_nmos_thesato_norm= 1.0000
+  .param sg13g2_hv_nmos_thesatl_norm= 1.0350
+  .param sg13g2_hv_nmos_thesatw_norm= 1.0000
+  .param sg13g2_hv_nmos_thesatlw_norm= 1.6050
+  .param sg13g2_hv_nmos_toxo_norm   = 1.0000
+  .param sg13g2_hv_nmos_toxovo_norm = 1.0000
+  .param sg13g2_hv_nmos_cjorbot_norm= 1.0000
+  .param sg13g2_hv_nmos_cjorsti_norm= 1.0000
+  .param sg13g2_hv_nmos_cjorgat_norm= 1.0000
 
-  .parameters sg13g2_hv_pmos_vfbo_mm_norm= 1.0
-  .parameters sg13g2_hv_pmos_rsgo_norm   = 1.1110
-  .parameters sg13g2_hv_pmos_rsw1_norm   = 1.0000
-  .parameters sg13g2_hv_pmos_mueo_norm   = 0.9605
-  .parameters sg13g2_hv_pmos_dphibo_norm = 1.0010
-  .parameters sg13g2_hv_pmos_dphibl_norm = 0.9504
-  .parameters sg13g2_hv_pmos_dphibw_norm = 1.4080
-  .parameters sg13g2_hv_pmos_dphiblw_norm= -0.1693
-  .parameters sg13g2_hv_pmos_bgidlo_norm = 0.8409
-  .parameters sg13g2_hv_pmos_thesato_norm= 1.0000
-  .parameters sg13g2_hv_pmos_thesatl_norm= 0.4814
-  .parameters sg13g2_hv_pmos_thesatw_norm= 5.7745
-  .parameters sg13g2_hv_pmos_thesatlw_norm= 1.0000
-  .parameters sg13g2_hv_pmos_csl_norm    = 1.0000
-  .parameters sg13g2_hv_pmos_toxo_norm   = 1.0000
-  .parameters sg13g2_hv_pmos_toxovo_norm = 1.0000
-  .parameters sg13g2_hv_pmos_cjorbot_norm= 1.0000
-  .parameters sg13g2_hv_pmos_cjorsti_norm= 1.0000
-  .parameters sg13g2_hv_pmos_cjorgat_norm= 1.0000
+  .param sg13g2_hv_pmos_vfbo_mm_norm= 1.0
+  .param sg13g2_hv_pmos_rsgo_norm   = 1.1110
+  .param sg13g2_hv_pmos_rsw1_norm   = 1.0000
+  .param sg13g2_hv_pmos_mueo_norm   = 0.9605
+  .param sg13g2_hv_pmos_dphibo_norm = 1.0010
+  .param sg13g2_hv_pmos_dphibl_norm = 0.9504
+  .param sg13g2_hv_pmos_dphibw_norm = 1.4080
+  .param sg13g2_hv_pmos_dphiblw_norm= -0.1693
+  .param sg13g2_hv_pmos_bgidlo_norm = 0.8409
+  .param sg13g2_hv_pmos_thesato_norm= 1.0000
+  .param sg13g2_hv_pmos_thesatl_norm= 0.4814
+  .param sg13g2_hv_pmos_thesatw_norm= 5.7745
+  .param sg13g2_hv_pmos_thesatlw_norm= 1.0000
+  .param sg13g2_hv_pmos_csl_norm    = 1.0000
+  .param sg13g2_hv_pmos_toxo_norm   = 1.0000
+  .param sg13g2_hv_pmos_toxovo_norm = 1.0000
+  .param sg13g2_hv_pmos_cjorbot_norm= 1.0000
+  .param sg13g2_hv_pmos_cjorsti_norm= 1.0000
+  .param sg13g2_hv_pmos_cjorgat_norm= 1.0000
 
-  .parameters sg13g2_hv_svaricap_lap   = 0.8     
-  .parameters sg13g2_hv_svaricap_toxo  = 1     
+  .param sg13g2_hv_svaricap_lap   = 0.8     
+  .param sg13g2_hv_svaricap_toxo  = 1     
   
   .include sg13g2_moshv_stat.lib
   .include sg13g2_moshv_mod.lib
@@ -169,94 +169,94 @@
 **************** CORNER_LIB OF sg13g2_hv SS MODEL **************** 
 * Slow n, Slow p without statistical
 .LIB mos_ss
-  .parameters sg13g2_hv_nmos_vfbo_mm= 1.0
-  .parameters sg13g2_hv_nmos_rsgo   = 1.0000
-  .parameters sg13g2_hv_nmos_rsw1   = 0.7880
-  .parameters sg13g2_hv_nmos_mueo   = 1.1670
-  .parameters sg13g2_hv_nmos_dphibo = 1.0117
-  .parameters sg13g2_hv_nmos_dphibl = 0.9004
-  .parameters sg13g2_hv_nmos_dphibw = 1.0000
-  .parameters sg13g2_hv_nmos_dphiblw= 0.8247
-  .parameters sg13g2_hv_nmos_ctl    = 1.0000
-  .parameters sg13g2_hv_nmos_thesato= 1.0000
-  .parameters sg13g2_hv_nmos_thesatl= 1.1610
-  .parameters sg13g2_hv_nmos_thesatw= 1.0000
-  .parameters sg13g2_hv_nmos_thesatlw= 1.4830
-  .parameters sg13g2_hv_nmos_toxo   = 1.0400
-  .parameters sg13g2_hv_nmos_toxovo = 1.0400
-  .parameters sg13g2_hv_nmos_cjorbot= 1.0800
-  .parameters sg13g2_hv_nmos_cjorsti= 1.0800
-  .parameters sg13g2_hv_nmos_cjorgat= 1.0800
-  
-  .parameters sg13g2_hv_pmos_vfbo_mm= 1.0
-  .parameters sg13g2_hv_pmos_rsgo   = -0.0510
-  .parameters sg13g2_hv_pmos_rsw1   = 1.0000
-  .parameters sg13g2_hv_pmos_mueo   = 0.9619
-  .parameters sg13g2_hv_pmos_dphibo = 0.8319
-  .parameters sg13g2_hv_pmos_dphibl = 1.1490
-  .parameters sg13g2_hv_pmos_dphibw = 1.4480
-  .parameters sg13g2_hv_pmos_dphiblw= 2.7230
-  .parameters sg13g2_hv_pmos_bgidlo = 1.4000
-  .parameters sg13g2_hv_pmos_thesato= 1.0000
-  .parameters sg13g2_hv_pmos_thesatl= 0.6000
-  .parameters sg13g2_hv_pmos_thesatw= 3.7378
-  .parameters sg13g2_hv_pmos_thesatlw= 1.0000
-  .parameters sg13g2_hv_pmos_csl    = 1.0000
-  .parameters sg13g2_hv_pmos_toxo   = 1.0400
-  .parameters sg13g2_hv_pmos_toxovo = 1.0400
-  .parameters sg13g2_hv_pmos_cjorbot= 1.0800
-  .parameters sg13g2_hv_pmos_cjorsti= 1.0800
-  .parameters sg13g2_hv_pmos_cjorgat= 1.0800
-  
-  .parameters sg13g2_hv_svaricap_lap   = 0.6     
-  .parameters sg13g2_hv_svaricap_toxo  = 1.04   
+  .param sg13g2_hv_nmos_vfbo_mm= 1.0
+  .param sg13g2_hv_nmos_rsgo   = 1.0000
+  .param sg13g2_hv_nmos_rsw1   = 0.7880
+  .param sg13g2_hv_nmos_mueo   = 1.1670
+  .param sg13g2_hv_nmos_dphibo = 1.0117
+  .param sg13g2_hv_nmos_dphibl = 0.9004
+  .param sg13g2_hv_nmos_dphibw = 1.0000
+  .param sg13g2_hv_nmos_dphiblw= 0.8247
+  .param sg13g2_hv_nmos_ctl    = 1.0000
+  .param sg13g2_hv_nmos_thesato= 1.0000
+  .param sg13g2_hv_nmos_thesatl= 1.1610
+  .param sg13g2_hv_nmos_thesatw= 1.0000
+  .param sg13g2_hv_nmos_thesatlw= 1.4830
+  .param sg13g2_hv_nmos_toxo   = 1.0400
+  .param sg13g2_hv_nmos_toxovo = 1.0400
+  .param sg13g2_hv_nmos_cjorbot= 1.0800
+  .param sg13g2_hv_nmos_cjorsti= 1.0800
+  .param sg13g2_hv_nmos_cjorgat= 1.0800
+  
+  .param sg13g2_hv_pmos_vfbo_mm= 1.0
+  .param sg13g2_hv_pmos_rsgo   = -0.0510
+  .param sg13g2_hv_pmos_rsw1   = 1.0000
+  .param sg13g2_hv_pmos_mueo   = 0.9619
+  .param sg13g2_hv_pmos_dphibo = 0.8319
+  .param sg13g2_hv_pmos_dphibl = 1.1490
+  .param sg13g2_hv_pmos_dphibw = 1.4480
+  .param sg13g2_hv_pmos_dphiblw= 2.7230
+  .param sg13g2_hv_pmos_bgidlo = 1.4000
+  .param sg13g2_hv_pmos_thesato= 1.0000
+  .param sg13g2_hv_pmos_thesatl= 0.6000
+  .param sg13g2_hv_pmos_thesatw= 3.7378
+  .param sg13g2_hv_pmos_thesatlw= 1.0000
+  .param sg13g2_hv_pmos_csl    = 1.0000
+  .param sg13g2_hv_pmos_toxo   = 1.0400
+  .param sg13g2_hv_pmos_toxovo = 1.0400
+  .param sg13g2_hv_pmos_cjorbot= 1.0800
+  .param sg13g2_hv_pmos_cjorsti= 1.0800
+  .param sg13g2_hv_pmos_cjorgat= 1.0800
+  
+  .param sg13g2_hv_svaricap_lap   = 0.6     
+  .param sg13g2_hv_svaricap_toxo  = 1.04   
   
   .include sg13g2_moshv_mod.lib
 .ENDL mos_ss  
   
 * Slow n, Slow p with statistical
 .LIB mos_ss_stat
-  .parameters sg13g2_hv_nmos_vfbo_mm_norm= 1.0
-  .parameters sg13g2_hv_nmos_rsgo_norm   = 1.0000
-  .parameters sg13g2_hv_nmos_rsw1_norm   = 0.7880
-  .parameters sg13g2_hv_nmos_mueo_norm   = 1.1670
-  .parameters sg13g2_hv_nmos_dphibo_norm = 1.0117
-  .parameters sg13g2_hv_nmos_dphibl_norm = 0.9004
-  .parameters sg13g2_hv_nmos_dphibw_norm = 1.0000
-  .parameters sg13g2_hv_nmos_dphiblw_norm= 0.8247
-  .parameters sg13g2_hv_nmos_ctl_norm    = 1.0000
-  .parameters sg13g2_hv_nmos_thesato_norm= 1.0000
-  .parameters sg13g2_hv_nmos_thesatl_norm= 1.1610
-  .parameters sg13g2_hv_nmos_thesatw_norm= 1.0000
-  .parameters sg13g2_hv_nmos_thesatlw_norm= 1.4830
-  .parameters sg13g2_hv_nmos_toxo_norm   = 1.0400
-  .parameters sg13g2_hv_nmos_toxovo_norm = 1.0400
-  .parameters sg13g2_hv_nmos_cjorbot_norm= 1.0800
-  .parameters sg13g2_hv_nmos_cjorsti_norm= 1.0800
-  .parameters sg13g2_hv_nmos_cjorgat_norm= 1.0800
-  
-  .parameters sg13g2_hv_pmos_vfbo_mm_norm= 1.0
-  .parameters sg13g2_hv_pmos_rsgo_norm   = -0.0510
-  .parameters sg13g2_hv_pmos_rsw1_norm   = 1.0000
-  .parameters sg13g2_hv_pmos_mueo_norm   = 0.9619
-  .parameters sg13g2_hv_pmos_dphibo_norm = 0.8319
-  .parameters sg13g2_hv_pmos_dphibl_norm = 1.1490
-  .parameters sg13g2_hv_pmos_dphibw_norm = 1.4480
-  .parameters sg13g2_hv_pmos_dphiblw_norm= 2.7230
-  .parameters sg13g2_hv_pmos_bgidlo_norm = 1.4000
-  .parameters sg13g2_hv_pmos_thesato_norm= 1.0000
-  .parameters sg13g2_hv_pmos_thesatl_norm= 0.6000
-  .parameters sg13g2_hv_pmos_thesatw_norm= 3.7378
-  .parameters sg13g2_hv_pmos_thesatlw_norm= 1.0000
-  .parameters sg13g2_hv_pmos_csl_norm    = 1.0000
-  .parameters sg13g2_hv_pmos_toxo_norm   = 1.0400
-  .parameters sg13g2_hv_pmos_toxovo_norm = 1.0400
-  .parameters sg13g2_hv_pmos_cjorbot_norm= 1.0800
-  .parameters sg13g2_hv_pmos_cjorsti_norm= 1.0800
-  .parameters sg13g2_hv_pmos_cjorgat_norm= 1.0800
-  
-  .parameters sg13g2_hv_svaricap_lap   = 0.6     
-  .parameters sg13g2_hv_svaricap_toxo  = 1.04   
+  .param sg13g2_hv_nmos_vfbo_mm_norm= 1.0
+  .param sg13g2_hv_nmos_rsgo_norm   = 1.0000
+  .param sg13g2_hv_nmos_rsw1_norm   = 0.7880
+  .param sg13g2_hv_nmos_mueo_norm   = 1.1670
+  .param sg13g2_hv_nmos_dphibo_norm = 1.0117
+  .param sg13g2_hv_nmos_dphibl_norm = 0.9004
+  .param sg13g2_hv_nmos_dphibw_norm = 1.0000
+  .param sg13g2_hv_nmos_dphiblw_norm= 0.8247
+  .param sg13g2_hv_nmos_ctl_norm    = 1.0000
+  .param sg13g2_hv_nmos_thesato_norm= 1.0000
+  .param sg13g2_hv_nmos_thesatl_norm= 1.1610
+  .param sg13g2_hv_nmos_thesatw_norm= 1.0000
+  .param sg13g2_hv_nmos_thesatlw_norm= 1.4830
+  .param sg13g2_hv_nmos_toxo_norm   = 1.0400
+  .param sg13g2_hv_nmos_toxovo_norm = 1.0400
+  .param sg13g2_hv_nmos_cjorbot_norm= 1.0800
+  .param sg13g2_hv_nmos_cjorsti_norm= 1.0800
+  .param sg13g2_hv_nmos_cjorgat_norm= 1.0800
+  
+  .param sg13g2_hv_pmos_vfbo_mm_norm= 1.0
+  .param sg13g2_hv_pmos_rsgo_norm   = -0.0510
+  .param sg13g2_hv_pmos_rsw1_norm   = 1.0000
+  .param sg13g2_hv_pmos_mueo_norm   = 0.9619
+  .param sg13g2_hv_pmos_dphibo_norm = 0.8319
+  .param sg13g2_hv_pmos_dphibl_norm = 1.1490
+  .param sg13g2_hv_pmos_dphibw_norm = 1.4480
+  .param sg13g2_hv_pmos_dphiblw_norm= 2.7230
+  .param sg13g2_hv_pmos_bgidlo_norm = 1.4000
+  .param sg13g2_hv_pmos_thesato_norm= 1.0000
+  .param sg13g2_hv_pmos_thesatl_norm= 0.6000
+  .param sg13g2_hv_pmos_thesatw_norm= 3.7378
+  .param sg13g2_hv_pmos_thesatlw_norm= 1.0000
+  .param sg13g2_hv_pmos_csl_norm    = 1.0000
+  .param sg13g2_hv_pmos_toxo_norm   = 1.0400
+  .param sg13g2_hv_pmos_toxovo_norm = 1.0400
+  .param sg13g2_hv_pmos_cjorbot_norm= 1.0800
+  .param sg13g2_hv_pmos_cjorsti_norm= 1.0800
+  .param sg13g2_hv_pmos_cjorgat_norm= 1.0800
+  
+  .param sg13g2_hv_svaricap_lap   = 0.6     
+  .param sg13g2_hv_svaricap_toxo  = 1.04   
   
   .include sg13g2_moshv_stat.lib
   .include sg13g2_moshv_mod.lib
@@ -265,47 +265,47 @@
 * Fast n, Fast p without statistical
 .LIB mos_ff  
   
-  .parameters sg13g2_hv_nmos_vfbo_mm= 1.0
-  .parameters sg13g2_hv_nmos_rsgo   = 1.0000
-  .parameters sg13g2_hv_nmos_rsw1   = 0.7880
-  .parameters sg13g2_hv_nmos_mueo   = 0.9662
-  .parameters sg13g2_hv_nmos_dphibo = 1.9136
-  .parameters sg13g2_hv_nmos_dphibl = 2.1315
-  .parameters sg13g2_hv_nmos_dphibw = 1.0000
-  .parameters sg13g2_hv_nmos_dphiblw= 0.9151
-  .parameters sg13g2_hv_nmos_ctl    = 1.0000
-  .parameters sg13g2_hv_nmos_thesato= 1.0000
-  .parameters sg13g2_hv_nmos_thesatl= 0.9463
-  .parameters sg13g2_hv_nmos_thesatw= 1.0000
-  .parameters sg13g2_hv_nmos_thesatlw= 1.6950
-  .parameters sg13g2_hv_nmos_toxo   = 0.9600
-  .parameters sg13g2_hv_nmos_toxovo = 0.9600
-  .parameters sg13g2_hv_nmos_cjorbot= 0.9200
-  .parameters sg13g2_hv_nmos_cjorsti= 0.9200
-  .parameters sg13g2_hv_nmos_cjorgat= 0.9200
-  
-  .parameters sg13g2_hv_pmos_vfbo_mm= 1.0
-  .parameters sg13g2_hv_pmos_rsgo   = 2.5010
-  .parameters sg13g2_hv_pmos_rsw1   = 1.0000
-  .parameters sg13g2_hv_pmos_mueo   = 0.9687
-  .parameters sg13g2_hv_pmos_dphibo = 1.1750
-  .parameters sg13g2_hv_pmos_dphibl = 0.7456
-  .parameters sg13g2_hv_pmos_dphibw = 1.3380
-  .parameters sg13g2_hv_pmos_dphiblw= -3.3600
-  .parameters sg13g2_hv_pmos_bgidlo = 0.4770
-  .parameters sg13g2_hv_pmos_thesato= 1.0000
-  .parameters sg13g2_hv_pmos_thesatl= 0.5000
-  .parameters sg13g2_hv_pmos_thesatw= 6.3581
-  .parameters sg13g2_hv_pmos_thesatlw= 1.0000
-  .parameters sg13g2_hv_pmos_csl    = 1.0000
-  .parameters sg13g2_hv_pmos_toxo   = 0.9600
-  .parameters sg13g2_hv_pmos_toxovo = 0.9600
-  .parameters sg13g2_hv_pmos_cjorbot= 0.9200
-  .parameters sg13g2_hv_pmos_cjorsti= 0.9200
-  .parameters sg13g2_hv_pmos_cjorgat= 0.9200
-  
-  .parameters sg13g2_hv_svaricap_lap   = 1     
-  .parameters sg13g2_hv_svaricap_toxo  = 0.96  
+  .param sg13g2_hv_nmos_vfbo_mm= 1.0
+  .param sg13g2_hv_nmos_rsgo   = 1.0000
+  .param sg13g2_hv_nmos_rsw1   = 0.7880
+  .param sg13g2_hv_nmos_mueo   = 0.9662
+  .param sg13g2_hv_nmos_dphibo = 1.9136
+  .param sg13g2_hv_nmos_dphibl = 2.1315
+  .param sg13g2_hv_nmos_dphibw = 1.0000
+  .param sg13g2_hv_nmos_dphiblw= 0.9151
+  .param sg13g2_hv_nmos_ctl    = 1.0000
+  .param sg13g2_hv_nmos_thesato= 1.0000
+  .param sg13g2_hv_nmos_thesatl= 0.9463
+  .param sg13g2_hv_nmos_thesatw= 1.0000
+  .param sg13g2_hv_nmos_thesatlw= 1.6950
+  .param sg13g2_hv_nmos_toxo   = 0.9600
+  .param sg13g2_hv_nmos_toxovo = 0.9600
+  .param sg13g2_hv_nmos_cjorbot= 0.9200
+  .param sg13g2_hv_nmos_cjorsti= 0.9200
+  .param sg13g2_hv_nmos_cjorgat= 0.9200
+  
+  .param sg13g2_hv_pmos_vfbo_mm= 1.0
+  .param sg13g2_hv_pmos_rsgo   = 2.5010
+  .param sg13g2_hv_pmos_rsw1   = 1.0000
+  .param sg13g2_hv_pmos_mueo   = 0.9687
+  .param sg13g2_hv_pmos_dphibo = 1.1750
+  .param sg13g2_hv_pmos_dphibl = 0.7456
+  .param sg13g2_hv_pmos_dphibw = 1.3380
+  .param sg13g2_hv_pmos_dphiblw= -3.3600
+  .param sg13g2_hv_pmos_bgidlo = 0.4770
+  .param sg13g2_hv_pmos_thesato= 1.0000
+  .param sg13g2_hv_pmos_thesatl= 0.5000
+  .param sg13g2_hv_pmos_thesatw= 6.3581
+  .param sg13g2_hv_pmos_thesatlw= 1.0000
+  .param sg13g2_hv_pmos_csl    = 1.0000
+  .param sg13g2_hv_pmos_toxo   = 0.9600
+  .param sg13g2_hv_pmos_toxovo = 0.9600
+  .param sg13g2_hv_pmos_cjorbot= 0.9200
+  .param sg13g2_hv_pmos_cjorsti= 0.9200
+  .param sg13g2_hv_pmos_cjorgat= 0.9200
+  
+  .param sg13g2_hv_svaricap_lap   = 1     
+  .param sg13g2_hv_svaricap_toxo  = 0.96  
   
   .include sg13g2_moshv_mod.lib
 .ENDL mos_ff  
@@ -313,47 +313,47 @@
 * Fast n, Fast p with statistical
 .LIB mos_ff_stat  
   
-  .parameters sg13g2_hv_nmos_vfbo_mm_norm= 1.0
-  .parameters sg13g2_hv_nmos_rsgo_norm   = 1.0000
-  .parameters sg13g2_hv_nmos_rsw1_norm   = 0.7880
-  .parameters sg13g2_hv_nmos_mueo_norm   = 0.9662
-  .parameters sg13g2_hv_nmos_dphibo_norm = 1.9136
-  .parameters sg13g2_hv_nmos_dphibl_norm = 2.1315
-  .parameters sg13g2_hv_nmos_dphibw_norm = 1.0000
-  .parameters sg13g2_hv_nmos_dphiblw_norm= 0.9151
-  .parameters sg13g2_hv_nmos_ctl_norm    = 1.0000
-  .parameters sg13g2_hv_nmos_thesato_norm= 1.0000
-  .parameters sg13g2_hv_nmos_thesatl_norm= 0.9463
-  .parameters sg13g2_hv_nmos_thesatw_norm= 1.0000
-  .parameters sg13g2_hv_nmos_thesatlw_norm= 1.6950
-  .parameters sg13g2_hv_nmos_toxo_norm   = 0.9600
-  .parameters sg13g2_hv_nmos_toxovo_norm = 0.9600
-  .parameters sg13g2_hv_nmos_cjorbot_norm= 0.9200
-  .parameters sg13g2_hv_nmos_cjorsti_norm= 0.9200
-  .parameters sg13g2_hv_nmos_cjorgat_norm= 0.9200
-  
-  .parameters sg13g2_hv_pmos_vfbo_mm_norm= 1.0
-  .parameters sg13g2_hv_pmos_rsgo_norm   = 2.5010
-  .parameters sg13g2_hv_pmos_rsw1_norm   = 1.0000
-  .parameters sg13g2_hv_pmos_mueo_norm   = 0.9687
-  .parameters sg13g2_hv_pmos_dphibo_norm = 1.1750
-  .parameters sg13g2_hv_pmos_dphibl_norm = 0.7456
-  .parameters sg13g2_hv_pmos_dphibw_norm = 1.3380
-  .parameters sg13g2_hv_pmos_dphiblw_norm= -3.3600
-  .parameters sg13g2_hv_pmos_bgidlo_norm = 0.4770
-  .parameters sg13g2_hv_pmos_thesato_norm= 1.0000
-  .parameters sg13g2_hv_pmos_thesatl_norm= 0.5000
-  .parameters sg13g2_hv_pmos_thesatw_norm= 6.3581
-  .parameters sg13g2_hv_pmos_thesatlw_norm= 1.0000
-  .parameters sg13g2_hv_pmos_csl_norm    = 1.0000
-  .parameters sg13g2_hv_pmos_toxo_norm   = 0.9600
-  .parameters sg13g2_hv_pmos_toxovo_norm = 0.9600
-  .parameters sg13g2_hv_pmos_cjorbot_norm= 0.9200
-  .parameters sg13g2_hv_pmos_cjorsti_norm= 0.9200
-  .parameters sg13g2_hv_pmos_cjorgat_norm= 0.9200
-  
-  .parameters sg13g2_hv_svaricap_lap   = 1     
-  .parameters sg13g2_hv_svaricap_toxo  = 0.96  
+  .param sg13g2_hv_nmos_vfbo_mm_norm= 1.0
+  .param sg13g2_hv_nmos_rsgo_norm   = 1.0000
+  .param sg13g2_hv_nmos_rsw1_norm   = 0.7880
+  .param sg13g2_hv_nmos_mueo_norm   = 0.9662
+  .param sg13g2_hv_nmos_dphibo_norm = 1.9136
+  .param sg13g2_hv_nmos_dphibl_norm = 2.1315
+  .param sg13g2_hv_nmos_dphibw_norm = 1.0000
+  .param sg13g2_hv_nmos_dphiblw_norm= 0.9151
+  .param sg13g2_hv_nmos_ctl_norm    = 1.0000
+  .param sg13g2_hv_nmos_thesato_norm= 1.0000
+  .param sg13g2_hv_nmos_thesatl_norm= 0.9463
+  .param sg13g2_hv_nmos_thesatw_norm= 1.0000
+  .param sg13g2_hv_nmos_thesatlw_norm= 1.6950
+  .param sg13g2_hv_nmos_toxo_norm   = 0.9600
+  .param sg13g2_hv_nmos_toxovo_norm = 0.9600
+  .param sg13g2_hv_nmos_cjorbot_norm= 0.9200
+  .param sg13g2_hv_nmos_cjorsti_norm= 0.9200
+  .param sg13g2_hv_nmos_cjorgat_norm= 0.9200
+  
+  .param sg13g2_hv_pmos_vfbo_mm_norm= 1.0
+  .param sg13g2_hv_pmos_rsgo_norm   = 2.5010
+  .param sg13g2_hv_pmos_rsw1_norm   = 1.0000
+  .param sg13g2_hv_pmos_mueo_norm   = 0.9687
+  .param sg13g2_hv_pmos_dphibo_norm = 1.1750
+  .param sg13g2_hv_pmos_dphibl_norm = 0.7456
+  .param sg13g2_hv_pmos_dphibw_norm = 1.3380
+  .param sg13g2_hv_pmos_dphiblw_norm= -3.3600
+  .param sg13g2_hv_pmos_bgidlo_norm = 0.4770
+  .param sg13g2_hv_pmos_thesato_norm= 1.0000
+  .param sg13g2_hv_pmos_thesatl_norm= 0.5000
+  .param sg13g2_hv_pmos_thesatw_norm= 6.3581
+  .param sg13g2_hv_pmos_thesatlw_norm= 1.0000
+  .param sg13g2_hv_pmos_csl_norm    = 1.0000
+  .param sg13g2_hv_pmos_toxo_norm   = 0.9600
+  .param sg13g2_hv_pmos_toxovo_norm = 0.9600
+  .param sg13g2_hv_pmos_cjorbot_norm= 0.9200
+  .param sg13g2_hv_pmos_cjorsti_norm= 0.9200
+  .param sg13g2_hv_pmos_cjorgat_norm= 0.9200
+  
+  .param sg13g2_hv_svaricap_lap   = 1     
+  .param sg13g2_hv_svaricap_toxo  = 0.96  
   
   .include sg13g2_moshv_stat.lib
   .include sg13g2_moshv_mod.lib
@@ -362,47 +362,47 @@
 * Slow n, Fast p without statistical
 .LIB mos_sf  
   
-  .parameters sg13g2_hv_nmos_vfbo_mm= 1.0
-  .parameters sg13g2_hv_nmos_rsgo   = 1.0000
-  .parameters sg13g2_hv_nmos_rsw1   = 0.7883
-  .parameters sg13g2_hv_nmos_mueo   = 1.1225
-  .parameters sg13g2_hv_nmos_dphibo = 1.2252
-  .parameters sg13g2_hv_nmos_dphibl = 1.2151
-  .parameters sg13g2_hv_nmos_dphibw = 1.0000
-  .parameters sg13g2_hv_nmos_dphiblw= 0.8479
-  .parameters sg13g2_hv_nmos_ctl    = 1.0000
-  .parameters sg13g2_hv_nmos_thesato= 1.0000
-  .parameters sg13g2_hv_nmos_thesatl= 1.0980
-  .parameters sg13g2_hv_nmos_thesatw= 1.0000
-  .parameters sg13g2_hv_nmos_thesatlw= 1.5440
-  .parameters sg13g2_hv_nmos_toxo   = 1.0200
-  .parameters sg13g2_hv_nmos_toxovo = 1.0200
-  .parameters sg13g2_hv_nmos_cjorbot= 1.0400
-  .parameters sg13g2_hv_nmos_cjorsti= 1.0400
-  .parameters sg13g2_hv_nmos_cjorgat= 1.0400
-  
-  .parameters sg13g2_hv_pmos_vfbo_mm= 1.0
-  .parameters sg13g2_hv_pmos_rsgo   = 1.8060
-  .parameters sg13g2_hv_pmos_rsw1   = 1.0000
-  .parameters sg13g2_hv_pmos_mueo   = 0.9646
-  .parameters sg13g2_hv_pmos_dphibo = 1.0880
-  .parameters sg13g2_hv_pmos_dphibl = 0.8480
-  .parameters sg13g2_hv_pmos_dphibw = 1.3730
-  .parameters sg13g2_hv_pmos_dphiblw= -1.7647
-  .parameters sg13g2_hv_pmos_bgidlo = 0.6589
-  .parameters sg13g2_hv_pmos_thesato= 1.0000
-  .parameters sg13g2_hv_pmos_thesatl= 0.4907
-  .parameters sg13g2_hv_pmos_thesatw= 6.0663
-  .parameters sg13g2_hv_pmos_thesatlw= 1.0000
-  .parameters sg13g2_hv_pmos_csl    = 1.0000
-  .parameters sg13g2_hv_pmos_toxo   = 0.9800
-  .parameters sg13g2_hv_pmos_toxovo = 0.9800
-  .parameters sg13g2_hv_pmos_cjorbot= 0.9600
-  .parameters sg13g2_hv_pmos_cjorsti= 0.9600
-  .parameters sg13g2_hv_pmos_cjorgat= 0.9600
-  
-  .parameters sg13g2_hv_svaricap_lap   = 0.9     
-  .parameters sg13g2_hv_svaricap_toxo  = 0.98   
+  .param sg13g2_hv_nmos_vfbo_mm= 1.0
+  .param sg13g2_hv_nmos_rsgo   = 1.0000
+  .param sg13g2_hv_nmos_rsw1   = 0.7883
+  .param sg13g2_hv_nmos_mueo   = 1.1225
+  .param sg13g2_hv_nmos_dphibo = 1.2252
+  .param sg13g2_hv_nmos_dphibl = 1.2151
+  .param sg13g2_hv_nmos_dphibw = 1.0000
+  .param sg13g2_hv_nmos_dphiblw= 0.8479
+  .param sg13g2_hv_nmos_ctl    = 1.0000
+  .param sg13g2_hv_nmos_thesato= 1.0000
+  .param sg13g2_hv_nmos_thesatl= 1.0980
+  .param sg13g2_hv_nmos_thesatw= 1.0000
+  .param sg13g2_hv_nmos_thesatlw= 1.5440
+  .param sg13g2_hv_nmos_toxo   = 1.0200
+  .param sg13g2_hv_nmos_toxovo = 1.0200
+  .param sg13g2_hv_nmos_cjorbot= 1.0400
+  .param sg13g2_hv_nmos_cjorsti= 1.0400
+  .param sg13g2_hv_nmos_cjorgat= 1.0400
+  
+  .param sg13g2_hv_pmos_vfbo_mm= 1.0
+  .param sg13g2_hv_pmos_rsgo   = 1.8060
+  .param sg13g2_hv_pmos_rsw1   = 1.0000
+  .param sg13g2_hv_pmos_mueo   = 0.9646
+  .param sg13g2_hv_pmos_dphibo = 1.0880
+  .param sg13g2_hv_pmos_dphibl = 0.8480
+  .param sg13g2_hv_pmos_dphibw = 1.3730
+  .param sg13g2_hv_pmos_dphiblw= -1.7647
+  .param sg13g2_hv_pmos_bgidlo = 0.6589
+  .param sg13g2_hv_pmos_thesato= 1.0000
+  .param sg13g2_hv_pmos_thesatl= 0.4907
+  .param sg13g2_hv_pmos_thesatw= 6.0663
+  .param sg13g2_hv_pmos_thesatlw= 1.0000
+  .param sg13g2_hv_pmos_csl    = 1.0000
+  .param sg13g2_hv_pmos_toxo   = 0.9800
+  .param sg13g2_hv_pmos_toxovo = 0.9800
+  .param sg13g2_hv_pmos_cjorbot= 0.9600
+  .param sg13g2_hv_pmos_cjorsti= 0.9600
+  .param sg13g2_hv_pmos_cjorgat= 0.9600
+  
+  .param sg13g2_hv_svaricap_lap   = 0.9     
+  .param sg13g2_hv_svaricap_toxo  = 0.98   
   
   * .include sg13g2_moshv_stat.lib
   .include sg13g2_moshv_mod.lib
@@ -411,47 +411,47 @@
 * Slow n, Fast p with statistical
 .LIB mos_sf_stat  
   
-  .parameters sg13g2_hv_nmos_vfbo_mm_norm= 1.0
-  .parameters sg13g2_hv_nmos_rsgo_norm   = 1.0000
-  .parameters sg13g2_hv_nmos_rsw1_norm   = 0.7883
-  .parameters sg13g2_hv_nmos_mueo_norm   = 1.1225
-  .parameters sg13g2_hv_nmos_dphibo_norm = 1.2252
-  .parameters sg13g2_hv_nmos_dphibl_norm = 1.2151
-  .parameters sg13g2_hv_nmos_dphibw_norm = 1.0000
-  .parameters sg13g2_hv_nmos_dphiblw_norm= 0.8479
-  .parameters sg13g2_hv_nmos_ctl_norm    = 1.0000
-  .parameters sg13g2_hv_nmos_thesato_norm= 1.0000
-  .parameters sg13g2_hv_nmos_thesatl_norm= 1.0980
-  .parameters sg13g2_hv_nmos_thesatw_norm= 1.0000
-  .parameters sg13g2_hv_nmos_thesatlw_norm= 1.5440
-  .parameters sg13g2_hv_nmos_toxo_norm   = 1.0200
-  .parameters sg13g2_hv_nmos_toxovo_norm = 1.0200
-  .parameters sg13g2_hv_nmos_cjorbot_norm= 1.0400
-  .parameters sg13g2_hv_nmos_cjorsti_norm= 1.0400
-  .parameters sg13g2_hv_nmos_cjorgat_norm= 1.0400
-  
-  .parameters sg13g2_hv_pmos_vfbo_mm_norm= 1.0
-  .parameters sg13g2_hv_pmos_rsgo_norm   = 1.8060
-  .parameters sg13g2_hv_pmos_rsw1_norm   = 1.0000
-  .parameters sg13g2_hv_pmos_mueo_norm   = 0.9646
-  .parameters sg13g2_hv_pmos_dphibo_norm = 1.0880
-  .parameters sg13g2_hv_pmos_dphibl_norm = 0.8480
-  .parameters sg13g2_hv_pmos_dphibw_norm = 1.3730
-  .parameters sg13g2_hv_pmos_dphiblw_norm= -1.7647
-  .parameters sg13g2_hv_pmos_bgidlo_norm = 0.6589
-  .parameters sg13g2_hv_pmos_thesato_norm= 1.0000
-  .parameters sg13g2_hv_pmos_thesatl_norm= 0.4907
-  .parameters sg13g2_hv_pmos_thesatw_norm= 6.0663
-  .parameters sg13g2_hv_pmos_thesatlw_norm= 1.0000
-  .parameters sg13g2_hv_pmos_csl_norm    = 1.0000
-  .parameters sg13g2_hv_pmos_toxo_norm   = 0.9800
-  .parameters sg13g2_hv_pmos_toxovo_norm = 0.9800
-  .parameters sg13g2_hv_pmos_cjorbot_norm= 0.9600
-  .parameters sg13g2_hv_pmos_cjorsti_norm= 0.9600
-  .parameters sg13g2_hv_pmos_cjorgat_norm= 0.9600
-  
-  .parameters sg13g2_hv_svaricap_lap   = 0.9     
-  .parameters sg13g2_hv_svaricap_toxo  = 0.98   
+  .param sg13g2_hv_nmos_vfbo_mm_norm= 1.0
+  .param sg13g2_hv_nmos_rsgo_norm   = 1.0000
+  .param sg13g2_hv_nmos_rsw1_norm   = 0.7883
+  .param sg13g2_hv_nmos_mueo_norm   = 1.1225
+  .param sg13g2_hv_nmos_dphibo_norm = 1.2252
+  .param sg13g2_hv_nmos_dphibl_norm = 1.2151
+  .param sg13g2_hv_nmos_dphibw_norm = 1.0000
+  .param sg13g2_hv_nmos_dphiblw_norm= 0.8479
+  .param sg13g2_hv_nmos_ctl_norm    = 1.0000
+  .param sg13g2_hv_nmos_thesato_norm= 1.0000
+  .param sg13g2_hv_nmos_thesatl_norm= 1.0980
+  .param sg13g2_hv_nmos_thesatw_norm= 1.0000
+  .param sg13g2_hv_nmos_thesatlw_norm= 1.5440
+  .param sg13g2_hv_nmos_toxo_norm   = 1.0200
+  .param sg13g2_hv_nmos_toxovo_norm = 1.0200
+  .param sg13g2_hv_nmos_cjorbot_norm= 1.0400
+  .param sg13g2_hv_nmos_cjorsti_norm= 1.0400
+  .param sg13g2_hv_nmos_cjorgat_norm= 1.0400
+  
+  .param sg13g2_hv_pmos_vfbo_mm_norm= 1.0
+  .param sg13g2_hv_pmos_rsgo_norm   = 1.8060
+  .param sg13g2_hv_pmos_rsw1_norm   = 1.0000
+  .param sg13g2_hv_pmos_mueo_norm   = 0.9646
+  .param sg13g2_hv_pmos_dphibo_norm = 1.0880
+  .param sg13g2_hv_pmos_dphibl_norm = 0.8480
+  .param sg13g2_hv_pmos_dphibw_norm = 1.3730
+  .param sg13g2_hv_pmos_dphiblw_norm= -1.7647
+  .param sg13g2_hv_pmos_bgidlo_norm = 0.6589
+  .param sg13g2_hv_pmos_thesato_norm= 1.0000
+  .param sg13g2_hv_pmos_thesatl_norm= 0.4907
+  .param sg13g2_hv_pmos_thesatw_norm= 6.0663
+  .param sg13g2_hv_pmos_thesatlw_norm= 1.0000
+  .param sg13g2_hv_pmos_csl_norm    = 1.0000
+  .param sg13g2_hv_pmos_toxo_norm   = 0.9800
+  .param sg13g2_hv_pmos_toxovo_norm = 0.9800
+  .param sg13g2_hv_pmos_cjorbot_norm= 0.9600
+  .param sg13g2_hv_pmos_cjorsti_norm= 0.9600
+  .param sg13g2_hv_pmos_cjorgat_norm= 0.9600
+  
+  .param sg13g2_hv_svaricap_lap   = 0.9     
+  .param sg13g2_hv_svaricap_toxo  = 0.98   
   
   .include sg13g2_moshv_stat.lib
   .include sg13g2_moshv_mod.lib
@@ -461,47 +461,47 @@
 * Fast n, Slow p without statistical
 .LIB mos_fs  
   
-  .parameters sg13g2_hv_nmos_vfbo_mm= 1.0
-  .parameters sg13g2_hv_nmos_rsgo   = 1.0000
-  .parameters sg13g2_hv_nmos_rsw1   = 0.7883
-  .parameters sg13g2_hv_nmos_mueo   = 1.0221
-  .parameters sg13g2_hv_nmos_dphibo = 1.6762
-  .parameters sg13g2_hv_nmos_dphibl = 1.8307
-  .parameters sg13g2_hv_nmos_dphibw = 1.0000
-  .parameters sg13g2_hv_nmos_dphiblw= 0.8932
-  .parameters sg13g2_hv_nmos_ctl    = 1.0000
-  .parameters sg13g2_hv_nmos_thesato= 1.0000
-  .parameters sg13g2_hv_nmos_thesatl= 0.9907
-  .parameters sg13g2_hv_nmos_thesatw= 1.0000
-  .parameters sg13g2_hv_nmos_thesatlw= 1.6500
-  .parameters sg13g2_hv_nmos_toxo   = 0.9800
-  .parameters sg13g2_hv_nmos_toxovo = 0.9800
-  .parameters sg13g2_hv_nmos_cjorbot= 0.9600
-  .parameters sg13g2_hv_nmos_cjorsti= 0.9600
-  .parameters sg13g2_hv_nmos_cjorgat= 0.9600
-  
-  .parameters sg13g2_hv_pmos_vfbo_mm= 1.0
-  .parameters sg13g2_hv_pmos_rsgo   = 0.5300
-  .parameters sg13g2_hv_pmos_rsw1   = 1.0000
-  .parameters sg13g2_hv_pmos_mueo   = 0.9612
-  .parameters sg13g2_hv_pmos_dphibo = 0.9164
-  .parameters sg13g2_hv_pmos_dphibl = 1.0497
-  .parameters sg13g2_hv_pmos_dphibw = 1.4280
-  .parameters sg13g2_hv_pmos_dphiblw= 1.2769
-  .parameters sg13g2_hv_pmos_bgidlo = 1.1204
-  .parameters sg13g2_hv_pmos_thesato= 1.0000
-  .parameters sg13g2_hv_pmos_thesatl= 0.5407
-  .parameters sg13g2_hv_pmos_thesatw= 4.7562
-  .parameters sg13g2_hv_pmos_thesatlw= 1.0000
-  .parameters sg13g2_hv_pmos_csl    = 1.0000
-  .parameters sg13g2_hv_pmos_toxo   = 1.0200
-  .parameters sg13g2_hv_pmos_toxovo = 1.0200
-  .parameters sg13g2_hv_pmos_cjorbot= 1.0400
-  .parameters sg13g2_hv_pmos_cjorsti= 1.0400
-  .parameters sg13g2_hv_pmos_cjorgat= 1.0400
-  
-  .parameters sg13g2_hv_svaricap_lap   = 0.7     
-  .parameters sg13g2_hv_svaricap_toxo  = 1.02   
+  .param sg13g2_hv_nmos_vfbo_mm= 1.0
+  .param sg13g2_hv_nmos_rsgo   = 1.0000
+  .param sg13g2_hv_nmos_rsw1   = 0.7883
+  .param sg13g2_hv_nmos_mueo   = 1.0221
+  .param sg13g2_hv_nmos_dphibo = 1.6762
+  .param sg13g2_hv_nmos_dphibl = 1.8307
+  .param sg13g2_hv_nmos_dphibw = 1.0000
+  .param sg13g2_hv_nmos_dphiblw= 0.8932
+  .param sg13g2_hv_nmos_ctl    = 1.0000
+  .param sg13g2_hv_nmos_thesato= 1.0000
+  .param sg13g2_hv_nmos_thesatl= 0.9907
+  .param sg13g2_hv_nmos_thesatw= 1.0000
+  .param sg13g2_hv_nmos_thesatlw= 1.6500
+  .param sg13g2_hv_nmos_toxo   = 0.9800
+  .param sg13g2_hv_nmos_toxovo = 0.9800
+  .param sg13g2_hv_nmos_cjorbot= 0.9600
+  .param sg13g2_hv_nmos_cjorsti= 0.9600
+  .param sg13g2_hv_nmos_cjorgat= 0.9600
+  
+  .param sg13g2_hv_pmos_vfbo_mm= 1.0
+  .param sg13g2_hv_pmos_rsgo   = 0.5300
+  .param sg13g2_hv_pmos_rsw1   = 1.0000
+  .param sg13g2_hv_pmos_mueo   = 0.9612
+  .param sg13g2_hv_pmos_dphibo = 0.9164
+  .param sg13g2_hv_pmos_dphibl = 1.0497
+  .param sg13g2_hv_pmos_dphibw = 1.4280
+  .param sg13g2_hv_pmos_dphiblw= 1.2769
+  .param sg13g2_hv_pmos_bgidlo = 1.1204
+  .param sg13g2_hv_pmos_thesato= 1.0000
+  .param sg13g2_hv_pmos_thesatl= 0.5407
+  .param sg13g2_hv_pmos_thesatw= 4.7562
+  .param sg13g2_hv_pmos_thesatlw= 1.0000
+  .param sg13g2_hv_pmos_csl    = 1.0000
+  .param sg13g2_hv_pmos_toxo   = 1.0200
+  .param sg13g2_hv_pmos_toxovo = 1.0200
+  .param sg13g2_hv_pmos_cjorbot= 1.0400
+  .param sg13g2_hv_pmos_cjorsti= 1.0400
+  .param sg13g2_hv_pmos_cjorgat= 1.0400
+  
+  .param sg13g2_hv_svaricap_lap   = 0.7     
+  .param sg13g2_hv_svaricap_toxo  = 1.02   
   
   * .include sg13g2_moshv_stat.lib
   .include sg13g2_moshv_mod.lib
@@ -510,47 +510,47 @@
 * Fast n, Slow p with statistical
 .LIB mos_fs_stat
   
-  .parameters sg13g2_hv_nmos_vfbo_mm_norm= 1.0
-  .parameters sg13g2_hv_nmos_rsgo_norm   = 1.0000
-  .parameters sg13g2_hv_nmos_rsw1_norm   = 0.7883
-  .parameters sg13g2_hv_nmos_mueo_norm   = 1.0221
-  .parameters sg13g2_hv_nmos_dphibo_norm = 1.6762
-  .parameters sg13g2_hv_nmos_dphibl_norm = 1.8307
-  .parameters sg13g2_hv_nmos_dphibw_norm = 1.0000
-  .parameters sg13g2_hv_nmos_dphiblw_norm= 0.8932
-  .parameters sg13g2_hv_nmos_ctl_norm    = 1.0000
-  .parameters sg13g2_hv_nmos_thesato_norm= 1.0000
-  .parameters sg13g2_hv_nmos_thesatl_norm= 0.9907
-  .parameters sg13g2_hv_nmos_thesatw_norm= 1.0000
-  .parameters sg13g2_hv_nmos_thesatlw_norm= 1.6500
-  .parameters sg13g2_hv_nmos_toxo_norm   = 0.9800
-  .parameters sg13g2_hv_nmos_toxovo_norm = 0.9800
-  .parameters sg13g2_hv_nmos_cjorbot_norm= 0.9600
-  .parameters sg13g2_hv_nmos_cjorsti_norm= 0.9600
-  .parameters sg13g2_hv_nmos_cjorgat_norm= 0.9600
-  
-  .parameters sg13g2_hv_pmos_vfbo_mm_norm= 1.0
-  .parameters sg13g2_hv_pmos_rsgo_norm   = 0.5300
-  .parameters sg13g2_hv_pmos_rsw1_norm   = 1.0000
-  .parameters sg13g2_hv_pmos_mueo_norm   = 0.9612
-  .parameters sg13g2_hv_pmos_dphibo_norm = 0.9164
-  .parameters sg13g2_hv_pmos_dphibl_norm = 1.0497
-  .parameters sg13g2_hv_pmos_dphibw_norm = 1.4280
-  .parameters sg13g2_hv_pmos_dphiblw_norm= 1.2769
-  .parameters sg13g2_hv_pmos_bgidlo_norm = 1.1204
-  .parameters sg13g2_hv_pmos_thesato_norm= 1.0000
-  .parameters sg13g2_hv_pmos_thesatl_norm= 0.5407
-  .parameters sg13g2_hv_pmos_thesatw_norm= 4.7562
-  .parameters sg13g2_hv_pmos_thesatlw_norm= 1.0000
-  .parameters sg13g2_hv_pmos_csl_norm    = 1.0000
-  .parameters sg13g2_hv_pmos_toxo_norm   = 1.0200
-  .parameters sg13g2_hv_pmos_toxovo_norm = 1.0200
-  .parameters sg13g2_hv_pmos_cjorbot_norm= 1.0400
-  .parameters sg13g2_hv_pmos_cjorsti_norm= 1.0400
-  .parameters sg13g2_hv_pmos_cjorgat_norm= 1.0400
-  
-  .parameters sg13g2_hv_svaricap_lap   = 0.7     
-  .parameters sg13g2_hv_svaricap_toxo  = 1.02   
+  .param sg13g2_hv_nmos_vfbo_mm_norm= 1.0
+  .param sg13g2_hv_nmos_rsgo_norm   = 1.0000
+  .param sg13g2_hv_nmos_rsw1_norm   = 0.7883
+  .param sg13g2_hv_nmos_mueo_norm   = 1.0221
+  .param sg13g2_hv_nmos_dphibo_norm = 1.6762
+  .param sg13g2_hv_nmos_dphibl_norm = 1.8307
+  .param sg13g2_hv_nmos_dphibw_norm = 1.0000
+  .param sg13g2_hv_nmos_dphiblw_norm= 0.8932
+  .param sg13g2_hv_nmos_ctl_norm    = 1.0000
+  .param sg13g2_hv_nmos_thesato_norm= 1.0000
+  .param sg13g2_hv_nmos_thesatl_norm= 0.9907
+  .param sg13g2_hv_nmos_thesatw_norm= 1.0000
+  .param sg13g2_hv_nmos_thesatlw_norm= 1.6500
+  .param sg13g2_hv_nmos_toxo_norm   = 0.9800
+  .param sg13g2_hv_nmos_toxovo_norm = 0.9800
+  .param sg13g2_hv_nmos_cjorbot_norm= 0.9600
+  .param sg13g2_hv_nmos_cjorsti_norm= 0.9600
+  .param sg13g2_hv_nmos_cjorgat_norm= 0.9600
+  
+  .param sg13g2_hv_pmos_vfbo_mm_norm= 1.0
+  .param sg13g2_hv_pmos_rsgo_norm   = 0.5300
+  .param sg13g2_hv_pmos_rsw1_norm   = 1.0000
+  .param sg13g2_hv_pmos_mueo_norm   = 0.9612
+  .param sg13g2_hv_pmos_dphibo_norm = 0.9164
+  .param sg13g2_hv_pmos_dphibl_norm = 1.0497
+  .param sg13g2_hv_pmos_dphibw_norm = 1.4280
+  .param sg13g2_hv_pmos_dphiblw_norm= 1.2769
+  .param sg13g2_hv_pmos_bgidlo_norm = 1.1204
+  .param sg13g2_hv_pmos_thesato_norm= 1.0000
+  .param sg13g2_hv_pmos_thesatl_norm= 0.5407
+  .param sg13g2_hv_pmos_thesatw_norm= 4.7562
+  .param sg13g2_hv_pmos_thesatlw_norm= 1.0000
+  .param sg13g2_hv_pmos_csl_norm    = 1.0000
+  .param sg13g2_hv_pmos_toxo_norm   = 1.0200
+  .param sg13g2_hv_pmos_toxovo_norm = 1.0200
+  .param sg13g2_hv_pmos_cjorbot_norm= 1.0400
+  .param sg13g2_hv_pmos_cjorsti_norm= 1.0400
+  .param sg13g2_hv_pmos_cjorgat_norm= 1.0400
+  
+  .param sg13g2_hv_svaricap_lap   = 0.7     
+  .param sg13g2_hv_svaricap_toxo  = 1.02   
   
   .include sg13g2_moshv_stat.lib
   .include sg13g2_moshv_mod.lib
diff --git a/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib b/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib
index d69289a6..9bba7ec8 100644
--- a/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib
+++ b/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib
@@ -44,7 +44,7 @@
 
 * Monte-Carlo begin ---------------------------------------------
 *
-* NOTE: default of all   parameters should be 1.0
+* NOTE: default of all  .param should be 1.0
 * NOTE: deviations from 1.0 are used to fit statistical results
 * 
 *
@@ -72,88 +72,88 @@
 **************** CORNER_LIB OF sg13g2_lv TT MODEL ****************  
 * Typical           
 .LIB mos_tt  
-  .parameters sg13g2_lv_nmos_vfbo_mm= 1.0
-  .parameters sg13g2_lv_nmos_ctl    = 1.2080
-  .parameters sg13g2_lv_nmos_rsw1   = 0.7200
-  .parameters sg13g2_lv_nmos_muew   = 0.8500
-  .parameters sg13g2_lv_nmos_dphibo = 0.9915
-  .parameters sg13g2_lv_nmos_dphibl = 0.9693
-  .parameters sg13g2_lv_nmos_dphibw = 0.9749
-  .parameters sg13g2_lv_nmos_dphiblw= 0.9754
-  .parameters sg13g2_lv_nmos_themuo = 0.8757
-  .parameters sg13g2_lv_nmos_thesatl= 0.7850
-  .parameters sg13g2_lv_nmos_thesatw= 1.5000
-  .parameters sg13g2_lv_nmos_thesatlw= 0.6127
-  .parameters sg13g2_lv_nmos_toxo   = 1.0000
-  .parameters sg13g2_lv_nmos_toxovo = 1.0000
-  .parameters sg13g2_lv_nmos_cjorbot= 1.0000
-  .parameters sg13g2_lv_nmos_cjorsti= 1.0000
-  .parameters sg13g2_lv_nmos_cjorgat= 1.0000
+  .param sg13g2_lv_nmos_vfbo_mm= 1.0
+  .param sg13g2_lv_nmos_ctl    = 1.2080
+  .param sg13g2_lv_nmos_rsw1   = 0.7200
+  .param sg13g2_lv_nmos_muew   = 0.8500
+  .param sg13g2_lv_nmos_dphibo = 0.9915
+  .param sg13g2_lv_nmos_dphibl = 0.9693
+  .param sg13g2_lv_nmos_dphibw = 0.9749
+  .param sg13g2_lv_nmos_dphiblw= 0.9754
+  .param sg13g2_lv_nmos_themuo = 0.8757
+  .param sg13g2_lv_nmos_thesatl= 0.7850
+  .param sg13g2_lv_nmos_thesatw= 1.5000
+  .param sg13g2_lv_nmos_thesatlw= 0.6127
+  .param sg13g2_lv_nmos_toxo   = 1.0000
+  .param sg13g2_lv_nmos_toxovo = 1.0000
+  .param sg13g2_lv_nmos_cjorbot= 1.0000
+  .param sg13g2_lv_nmos_cjorsti= 1.0000
+  .param sg13g2_lv_nmos_cjorgat= 1.0000
 
-  .parameters sg13g2_lv_pmos_vfbo_mm= 1.0
-  .parameters sg13g2_lv_pmos_ctl    = 1.9570
-  .parameters sg13g2_lv_pmos_rsw1   = 0.7720
-  .parameters sg13g2_lv_pmos_muew   = 1.0520
-  .parameters sg13g2_lv_pmos_dphibo = 0.9050
-  .parameters sg13g2_lv_pmos_dphibl = 0.8550
-  .parameters sg13g2_lv_pmos_dphibw = -1.5800
-  .parameters sg13g2_lv_pmos_dphiblw= 1.0000
-  .parameters sg13g2_lv_pmos_themuo = 0.9580
-  .parameters sg13g2_lv_pmos_thesatl= 0.5510
-  .parameters sg13g2_lv_pmos_thesatw= 1.0800
-  .parameters sg13g2_lv_pmos_thesatlw= 1.0000
-  .parameters sg13g2_lv_pmos_toxo   = 1.0000
-  .parameters sg13g2_lv_pmos_toxovo = 1.0000
-  .parameters sg13g2_lv_pmos_cjorbot= 1.0000
-  .parameters sg13g2_lv_pmos_cjorsti= 1.0000
-  .parameters sg13g2_lv_pmos_cjorgat= 1.0000
+  .param sg13g2_lv_pmos_vfbo_mm= 1.0
+  .param sg13g2_lv_pmos_ctl    = 1.9570
+  .param sg13g2_lv_pmos_rsw1   = 0.7720
+  .param sg13g2_lv_pmos_muew   = 1.0520
+  .param sg13g2_lv_pmos_dphibo = 0.9050
+  .param sg13g2_lv_pmos_dphibl = 0.8550
+  .param sg13g2_lv_pmos_dphibw = -1.5800
+  .param sg13g2_lv_pmos_dphiblw= 1.0000
+  .param sg13g2_lv_pmos_themuo = 0.9580
+  .param sg13g2_lv_pmos_thesatl= 0.5510
+  .param sg13g2_lv_pmos_thesatw= 1.0800
+  .param sg13g2_lv_pmos_thesatlw= 1.0000
+  .param sg13g2_lv_pmos_toxo   = 1.0000
+  .param sg13g2_lv_pmos_toxovo = 1.0000
+  .param sg13g2_lv_pmos_cjorbot= 1.0000
+  .param sg13g2_lv_pmos_cjorsti= 1.0000
+  .param sg13g2_lv_pmos_cjorgat= 1.0000
  
-  .parameters sg13g2_lv_svaricap_lap   = 1.082   
-  .parameters sg13g2_lv_svaricap_toxo  = 1   
+  .param sg13g2_lv_svaricap_lap   = 1.082   
+  .param sg13g2_lv_svaricap_toxo  = 1   
 
   .include sg13g2_moslv_mod.lib
 .ENDL mos_tt
   
 * Typical with statistical modeling
 .LIB mos_tt_stat  
-  .parameters sg13g2_lv_nmos_vfbo_mm_norm= 1.0
-  .parameters sg13g2_lv_nmos_ctl_norm    = 1.2080
-  .parameters sg13g2_lv_nmos_rsw1_norm   = 0.7200
-  .parameters sg13g2_lv_nmos_muew_norm   = 0.8500
-  .parameters sg13g2_lv_nmos_dphibo_norm = 0.9915
-  .parameters sg13g2_lv_nmos_dphibl_norm = 0.9693
-  .parameters sg13g2_lv_nmos_dphibw_norm = 0.9749
-  .parameters sg13g2_lv_nmos_dphiblw_norm= 0.9754
-  .parameters sg13g2_lv_nmos_themuo_norm = 0.8757
-  .parameters sg13g2_lv_nmos_thesatl_norm= 0.7850
-  .parameters sg13g2_lv_nmos_thesatw_norm= 1.5000
-  .parameters sg13g2_lv_nmos_thesatlw_norm= 0.6127
-  .parameters sg13g2_lv_nmos_toxo_norm   = 1.0000
-  .parameters sg13g2_lv_nmos_toxovo_norm = 1.0000
-  .parameters sg13g2_lv_nmos_cjorbot_norm= 1.0000
-  .parameters sg13g2_lv_nmos_cjorsti_norm= 1.0000
-  .parameters sg13g2_lv_nmos_cjorgat_norm= 1.0000
+  .param sg13g2_lv_nmos_vfbo_mm_norm= 1.0
+  .param sg13g2_lv_nmos_ctl_norm    = 1.2080
+  .param sg13g2_lv_nmos_rsw1_norm   = 0.7200
+  .param sg13g2_lv_nmos_muew_norm   = 0.8500
+  .param sg13g2_lv_nmos_dphibo_norm = 0.9915
+  .param sg13g2_lv_nmos_dphibl_norm = 0.9693
+  .param sg13g2_lv_nmos_dphibw_norm = 0.9749
+  .param sg13g2_lv_nmos_dphiblw_norm= 0.9754
+  .param sg13g2_lv_nmos_themuo_norm = 0.8757
+  .param sg13g2_lv_nmos_thesatl_norm= 0.7850
+  .param sg13g2_lv_nmos_thesatw_norm= 1.5000
+  .param sg13g2_lv_nmos_thesatlw_norm= 0.6127
+  .param sg13g2_lv_nmos_toxo_norm   = 1.0000
+  .param sg13g2_lv_nmos_toxovo_norm = 1.0000
+  .param sg13g2_lv_nmos_cjorbot_norm= 1.0000
+  .param sg13g2_lv_nmos_cjorsti_norm= 1.0000
+  .param sg13g2_lv_nmos_cjorgat_norm= 1.0000
 
-  .parameters sg13g2_lv_pmos_vfbo_mm_norm= 1.0
-  .parameters sg13g2_lv_pmos_ctl_norm    = 1.2080
-  .parameters sg13g2_lv_pmos_rsw1_norm   = 0.7200
-  .parameters sg13g2_lv_pmos_muew_norm   = 0.8500
-  .parameters sg13g2_lv_pmos_dphibo_norm = 0.9915
-  .parameters sg13g2_lv_pmos_dphibl_norm = 0.9693
-  .parameters sg13g2_lv_pmos_dphibw_norm = 0.9749
-  .parameters sg13g2_lv_pmos_dphiblw_norm= 0.9754
-  .parameters sg13g2_lv_pmos_themuo_norm = 0.8757
-  .parameters sg13g2_lv_pmos_thesatl_norm= 0.7850
-  .parameters sg13g2_lv_pmos_thesatw_norm= 1.5000
-  .parameters sg13g2_lv_pmos_thesatlw_norm= 0.6127
-  .parameters sg13g2_lv_pmos_toxo_norm   = 1.0000
-  .parameters sg13g2_lv_pmos_toxovo_norm = 1.0000
-  .parameters sg13g2_lv_pmos_cjorbot_norm= 1.0000
-  .parameters sg13g2_lv_pmos_cjorsti_norm= 1.0000
-  .parameters sg13g2_lv_pmos_cjorgat_norm= 1.0000
+  .param sg13g2_lv_pmos_vfbo_mm_norm= 1.0
+  .param sg13g2_lv_pmos_ctl_norm    = 1.2080
+  .param sg13g2_lv_pmos_rsw1_norm   = 0.7200
+  .param sg13g2_lv_pmos_muew_norm   = 0.8500
+  .param sg13g2_lv_pmos_dphibo_norm = 0.9915
+  .param sg13g2_lv_pmos_dphibl_norm = 0.9693
+  .param sg13g2_lv_pmos_dphibw_norm = 0.9749
+  .param sg13g2_lv_pmos_dphiblw_norm= 0.9754
+  .param sg13g2_lv_pmos_themuo_norm = 0.8757
+  .param sg13g2_lv_pmos_thesatl_norm= 0.7850
+  .param sg13g2_lv_pmos_thesatw_norm= 1.5000
+  .param sg13g2_lv_pmos_thesatlw_norm= 0.6127
+  .param sg13g2_lv_pmos_toxo_norm   = 1.0000
+  .param sg13g2_lv_pmos_toxovo_norm = 1.0000
+  .param sg13g2_lv_pmos_cjorbot_norm= 1.0000
+  .param sg13g2_lv_pmos_cjorsti_norm= 1.0000
+  .param sg13g2_lv_pmos_cjorgat_norm= 1.0000
   
-  .parameters sg13g2_lv_svaricap_lap   = 1.082   
-  .parameters sg13g2_lv_svaricap_toxo  = 1   
+  .param sg13g2_lv_svaricap_lap   = 1.082   
+  .param sg13g2_lv_svaricap_toxo  = 1   
 
   .include sg13g2_moslv_stat.lib
   .include sg13g2_moslv_mod.lib
@@ -162,88 +162,88 @@
 **************** CORNER_LIB OF sg13g2_lv SS MODEL **************** 
 * Slow n, Slow p without statistical
 .LIB mos_ss  
-  .parameters sg13g2_lv_nmos_vfbo_mm= 1.0
-  .parameters sg13g2_lv_nmos_ctl    = 0.4939
-  .parameters sg13g2_lv_nmos_rsw1   = 0.6560
-  .parameters sg13g2_lv_nmos_muew   = 0.9700
-  .parameters sg13g2_lv_nmos_dphibo = 1.2070
-  .parameters sg13g2_lv_nmos_dphibl = 1.3360
-  .parameters sg13g2_lv_nmos_dphibw = 1.3290
-  .parameters sg13g2_lv_nmos_dphiblw= 1.0110
-  .parameters sg13g2_lv_nmos_themuo = 0.8866
-  .parameters sg13g2_lv_nmos_thesatl= 1.0960
-  .parameters sg13g2_lv_nmos_thesatw= 1.5930
-  .parameters sg13g2_lv_nmos_thesatlw= 0.9875
-  .parameters sg13g2_lv_nmos_toxo   = 1.0400
-  .parameters sg13g2_lv_nmos_toxovo = 1.0400
-  .parameters sg13g2_lv_nmos_cjorbot= 1.0800
-  .parameters sg13g2_lv_nmos_cjorsti= 1.0800
-  .parameters sg13g2_lv_nmos_cjorgat= 1.0800
+  .param sg13g2_lv_nmos_vfbo_mm= 1.0
+  .param sg13g2_lv_nmos_ctl    = 0.4939
+  .param sg13g2_lv_nmos_rsw1   = 0.6560
+  .param sg13g2_lv_nmos_muew   = 0.9700
+  .param sg13g2_lv_nmos_dphibo = 1.2070
+  .param sg13g2_lv_nmos_dphibl = 1.3360
+  .param sg13g2_lv_nmos_dphibw = 1.3290
+  .param sg13g2_lv_nmos_dphiblw= 1.0110
+  .param sg13g2_lv_nmos_themuo = 0.8866
+  .param sg13g2_lv_nmos_thesatl= 1.0960
+  .param sg13g2_lv_nmos_thesatw= 1.5930
+  .param sg13g2_lv_nmos_thesatlw= 0.9875
+  .param sg13g2_lv_nmos_toxo   = 1.0400
+  .param sg13g2_lv_nmos_toxovo = 1.0400
+  .param sg13g2_lv_nmos_cjorbot= 1.0800
+  .param sg13g2_lv_nmos_cjorsti= 1.0800
+  .param sg13g2_lv_nmos_cjorgat= 1.0800
  
-  .parameters sg13g2_lv_pmos_vfbo_mm= 1.0  
-  .parameters sg13g2_lv_pmos_ctl    = 1.3520
-  .parameters sg13g2_lv_pmos_rsw1   = 0.9365
-  .parameters sg13g2_lv_pmos_muew   = 1.1030
-  .parameters sg13g2_lv_pmos_dphibo = 0.5883
-  .parameters sg13g2_lv_pmos_dphibl = 1.3540
-  .parameters sg13g2_lv_pmos_dphibw = -4.9920
-  .parameters sg13g2_lv_pmos_dphiblw= 1.0000
-  .parameters sg13g2_lv_pmos_themuo = 0.8720
-  .parameters sg13g2_lv_pmos_thesatl= 1.2190
-  .parameters sg13g2_lv_pmos_thesatw= 0.9875
-  .parameters sg13g2_lv_pmos_thesatlw= 1.0000
-  .parameters sg13g2_lv_pmos_toxo   = 1.0400
-  .parameters sg13g2_lv_pmos_toxovo = 1.0400
-  .parameters sg13g2_lv_pmos_cjorbot= 1.0800
-  .parameters sg13g2_lv_pmos_cjorsti= 1.0800
-  .parameters sg13g2_lv_pmos_cjorgat= 1.0800
+  .param sg13g2_lv_pmos_vfbo_mm= 1.0  
+  .param sg13g2_lv_pmos_ctl    = 1.3520
+  .param sg13g2_lv_pmos_rsw1   = 0.9365
+  .param sg13g2_lv_pmos_muew   = 1.1030
+  .param sg13g2_lv_pmos_dphibo = 0.5883
+  .param sg13g2_lv_pmos_dphibl = 1.3540
+  .param sg13g2_lv_pmos_dphibw = -4.9920
+  .param sg13g2_lv_pmos_dphiblw= 1.0000
+  .param sg13g2_lv_pmos_themuo = 0.8720
+  .param sg13g2_lv_pmos_thesatl= 1.2190
+  .param sg13g2_lv_pmos_thesatw= 0.9875
+  .param sg13g2_lv_pmos_thesatlw= 1.0000
+  .param sg13g2_lv_pmos_toxo   = 1.0400
+  .param sg13g2_lv_pmos_toxovo = 1.0400
+  .param sg13g2_lv_pmos_cjorbot= 1.0800
+  .param sg13g2_lv_pmos_cjorsti= 1.0800
+  .param sg13g2_lv_pmos_cjorgat= 1.0800
   
-  .parameters sg13g2_lv_svaricap_lap   = 1   
-  .parameters sg13g2_lv_svaricap_toxo  = 1.04   
+  .param sg13g2_lv_svaricap_lap   = 1   
+  .param sg13g2_lv_svaricap_toxo  = 1.04   
   
   .include sg13g2_moslv_mod.lib
 .ENDL mos_ss
   
 * Slow n, Slow p with statistical
 .LIB mos_ss_stat
-  .parameters sg13g2_lv_nmos_vfbo_mm_norm= 1.0
-  .parameters sg13g2_lv_nmos_ctl_norm    = 0.4939
-  .parameters sg13g2_lv_nmos_rsw1_norm   = 0.6560
-  .parameters sg13g2_lv_nmos_muew_norm   = 0.9700
-  .parameters sg13g2_lv_nmos_dphibo_norm = 1.2070
-  .parameters sg13g2_lv_nmos_dphibl_norm = 1.3360
-  .parameters sg13g2_lv_nmos_dphibw_norm = 1.3290
-  .parameters sg13g2_lv_nmos_dphiblw_norm= 1.0110
-  .parameters sg13g2_lv_nmos_themuo_norm = 0.8866
-  .parameters sg13g2_lv_nmos_thesatl_norm= 1.0960
-  .parameters sg13g2_lv_nmos_thesatw_norm= 1.5930
-  .parameters sg13g2_lv_nmos_thesatlw_norm= 0.9875
-  .parameters sg13g2_lv_nmos_toxo_norm   = 1.0400
-  .parameters sg13g2_lv_nmos_toxovo_norm = 1.0400
-  .parameters sg13g2_lv_nmos_cjorbot_norm= 1.0800
-  .parameters sg13g2_lv_nmos_cjorsti_norm= 1.0800
-  .parameters sg13g2_lv_nmos_cjorgat_norm= 1.0800
+  .param sg13g2_lv_nmos_vfbo_mm_norm= 1.0
+  .param sg13g2_lv_nmos_ctl_norm    = 0.4939
+  .param sg13g2_lv_nmos_rsw1_norm   = 0.6560
+  .param sg13g2_lv_nmos_muew_norm   = 0.9700
+  .param sg13g2_lv_nmos_dphibo_norm = 1.2070
+  .param sg13g2_lv_nmos_dphibl_norm = 1.3360
+  .param sg13g2_lv_nmos_dphibw_norm = 1.3290
+  .param sg13g2_lv_nmos_dphiblw_norm= 1.0110
+  .param sg13g2_lv_nmos_themuo_norm = 0.8866
+  .param sg13g2_lv_nmos_thesatl_norm= 1.0960
+  .param sg13g2_lv_nmos_thesatw_norm= 1.5930
+  .param sg13g2_lv_nmos_thesatlw_norm= 0.9875
+  .param sg13g2_lv_nmos_toxo_norm   = 1.0400
+  .param sg13g2_lv_nmos_toxovo_norm = 1.0400
+  .param sg13g2_lv_nmos_cjorbot_norm= 1.0800
+  .param sg13g2_lv_nmos_cjorsti_norm= 1.0800
+  .param sg13g2_lv_nmos_cjorgat_norm= 1.0800
  
-  .parameters sg13g2_lv_pmos_vfbo_mm_norm= 1.0  
-  .parameters sg13g2_lv_pmos_ctl_norm    = 1.3520
-  .parameters sg13g2_lv_pmos_rsw1_norm   = 0.9365
-  .parameters sg13g2_lv_pmos_muew_norm   = 1.1030
-  .parameters sg13g2_lv_pmos_dphibo_norm = 0.5883
-  .parameters sg13g2_lv_pmos_dphibl_norm = 1.3540
-  .parameters sg13g2_lv_pmos_dphibw_norm = -4.9920
-  .parameters sg13g2_lv_pmos_dphiblw_norm= 1.0000
-  .parameters sg13g2_lv_pmos_themuo_norm = 0.8720
-  .parameters sg13g2_lv_pmos_thesatl_norm= 1.2190
-  .parameters sg13g2_lv_pmos_thesatw_norm= 0.9875
-  .parameters sg13g2_lv_pmos_thesatlw_norm= 1.0000
-  .parameters sg13g2_lv_pmos_toxo_norm   = 1.0400
-  .parameters sg13g2_lv_pmos_toxovo_norm = 1.0400
-  .parameters sg13g2_lv_pmos_cjorbot_norm= 1.0800
-  .parameters sg13g2_lv_pmos_cjorsti_norm= 1.0800
-  .parameters sg13g2_lv_pmos_cjorgat_norm= 1.0800
+  .param sg13g2_lv_pmos_vfbo_mm_norm= 1.0  
+  .param sg13g2_lv_pmos_ctl_norm    = 1.3520
+  .param sg13g2_lv_pmos_rsw1_norm   = 0.9365
+  .param sg13g2_lv_pmos_muew_norm   = 1.1030
+  .param sg13g2_lv_pmos_dphibo_norm = 0.5883
+  .param sg13g2_lv_pmos_dphibl_norm = 1.3540
+  .param sg13g2_lv_pmos_dphibw_norm = -4.9920
+  .param sg13g2_lv_pmos_dphiblw_norm= 1.0000
+  .param sg13g2_lv_pmos_themuo_norm = 0.8720
+  .param sg13g2_lv_pmos_thesatl_norm= 1.2190
+  .param sg13g2_lv_pmos_thesatw_norm= 0.9875
+  .param sg13g2_lv_pmos_thesatlw_norm= 1.0000
+  .param sg13g2_lv_pmos_toxo_norm   = 1.0400
+  .param sg13g2_lv_pmos_toxovo_norm = 1.0400
+  .param sg13g2_lv_pmos_cjorbot_norm= 1.0800
+  .param sg13g2_lv_pmos_cjorsti_norm= 1.0800
+  .param sg13g2_lv_pmos_cjorgat_norm= 1.0800
   
-  .parameters sg13g2_lv_svaricap_lap   = 1   
-  .parameters sg13g2_lv_svaricap_toxo  = 1.04   
+  .param sg13g2_lv_svaricap_lap   = 1   
+  .param sg13g2_lv_svaricap_toxo  = 1.04   
   
   .include sg13g2_moslv_stat.lib
   .include sg13g2_moslv_mod.lib
@@ -252,88 +252,88 @@
 **************** CORNER_LIB OF sg13g2_lv FF MODEL **************** 
 * Fast n, Fast p    
 .LIB mos_ff
-  .parameters sg13g2_lv_nmos_vfbo_mm= 1.0
-  .parameters sg13g2_lv_nmos_ctl    = 1.4310
-  .parameters sg13g2_lv_nmos_rsw1   = 0.9000
-  .parameters sg13g2_lv_nmos_muew   = 0.7780
-  .parameters sg13g2_lv_nmos_dphibo = 0.8137
-  .parameters sg13g2_lv_nmos_dphibl = 0.6550
-  .parameters sg13g2_lv_nmos_dphibw = 0.6105
-  .parameters sg13g2_lv_nmos_dphiblw= 0.9300
-  .parameters sg13g2_lv_nmos_themuo = 0.8708
-  .parameters sg13g2_lv_nmos_thesatl= 0.5510
-  .parameters sg13g2_lv_nmos_thesatw= 1.4300
-  .parameters sg13g2_lv_nmos_thesatlw= 0.0860
-  .parameters sg13g2_lv_nmos_toxo   = 0.9600
-  .parameters sg13g2_lv_nmos_toxovo = 0.9600
-  .parameters sg13g2_lv_nmos_cjorbot= 0.9200
-  .parameters sg13g2_lv_nmos_cjorsti= 0.9200
-  .parameters sg13g2_lv_nmos_cjorgat= 0.9200
+  .param sg13g2_lv_nmos_vfbo_mm= 1.0
+  .param sg13g2_lv_nmos_ctl    = 1.4310
+  .param sg13g2_lv_nmos_rsw1   = 0.9000
+  .param sg13g2_lv_nmos_muew   = 0.7780
+  .param sg13g2_lv_nmos_dphibo = 0.8137
+  .param sg13g2_lv_nmos_dphibl = 0.6550
+  .param sg13g2_lv_nmos_dphibw = 0.6105
+  .param sg13g2_lv_nmos_dphiblw= 0.9300
+  .param sg13g2_lv_nmos_themuo = 0.8708
+  .param sg13g2_lv_nmos_thesatl= 0.5510
+  .param sg13g2_lv_nmos_thesatw= 1.4300
+  .param sg13g2_lv_nmos_thesatlw= 0.0860
+  .param sg13g2_lv_nmos_toxo   = 0.9600
+  .param sg13g2_lv_nmos_toxovo = 0.9600
+  .param sg13g2_lv_nmos_cjorbot= 0.9200
+  .param sg13g2_lv_nmos_cjorsti= 0.9200
+  .param sg13g2_lv_nmos_cjorgat= 0.9200
   
-  .parameters sg13g2_lv_pmos_vfbo_mm= 1.0
-  .parameters sg13g2_lv_pmos_ctl    = 2.4800
-  .parameters sg13g2_lv_pmos_rsw1   = 0.5000
-  .parameters sg13g2_lv_pmos_muew   = 0.9620
-  .parameters sg13g2_lv_pmos_dphibo = 1.2350
-  .parameters sg13g2_lv_pmos_dphibl = 0.5066
-  .parameters sg13g2_lv_pmos_dphibw = 3.9230
-  .parameters sg13g2_lv_pmos_dphiblw= 1.0000
-  .parameters sg13g2_lv_pmos_themuo = 1.0200
-  .parameters sg13g2_lv_pmos_thesatl= 0.1880
-  .parameters sg13g2_lv_pmos_thesatw= 1.2440
-  .parameters sg13g2_lv_pmos_thesatlw= 2.0000
-  .parameters sg13g2_lv_pmos_toxo   = 0.9600
-  .parameters sg13g2_lv_pmos_toxovo = 0.9600
-  .parameters sg13g2_lv_pmos_cjorbot= 0.9200
-  .parameters sg13g2_lv_pmos_cjorsti= 0.9200
-  .parameters sg13g2_lv_pmos_cjorgat= 0.9200
+  .param sg13g2_lv_pmos_vfbo_mm= 1.0
+  .param sg13g2_lv_pmos_ctl    = 2.4800
+  .param sg13g2_lv_pmos_rsw1   = 0.5000
+  .param sg13g2_lv_pmos_muew   = 0.9620
+  .param sg13g2_lv_pmos_dphibo = 1.2350
+  .param sg13g2_lv_pmos_dphibl = 0.5066
+  .param sg13g2_lv_pmos_dphibw = 3.9230
+  .param sg13g2_lv_pmos_dphiblw= 1.0000
+  .param sg13g2_lv_pmos_themuo = 1.0200
+  .param sg13g2_lv_pmos_thesatl= 0.1880
+  .param sg13g2_lv_pmos_thesatw= 1.2440
+  .param sg13g2_lv_pmos_thesatlw= 2.0000
+  .param sg13g2_lv_pmos_toxo   = 0.9600
+  .param sg13g2_lv_pmos_toxovo = 0.9600
+  .param sg13g2_lv_pmos_cjorbot= 0.9200
+  .param sg13g2_lv_pmos_cjorsti= 0.9200
+  .param sg13g2_lv_pmos_cjorgat= 0.9200
   
-  .parameters sg13g2_lv_svaricap_lap   = 1.24   
-  .parameters sg13g2_lv_svaricap_toxo  = 0.96   
+  .param sg13g2_lv_svaricap_lap   = 1.24   
+  .param sg13g2_lv_svaricap_toxo  = 0.96   
   
   .include sg13g2_moslv_mod.lib
 .ENDL mos_ff
   
 * Fast n, Fast p    
 .LIB mos_ff_stat
-  .parameters sg13g2_lv_nmos_vfbo_mm_norm= 1.0
-  .parameters sg13g2_lv_nmos_ctl_norm    = 1.4310
-  .parameters sg13g2_lv_nmos_rsw1_norm   = 0.9000
-  .parameters sg13g2_lv_nmos_muew_norm   = 0.7780
-  .parameters sg13g2_lv_nmos_dphibo_norm = 0.8137
-  .parameters sg13g2_lv_nmos_dphibl_norm = 0.6550
-  .parameters sg13g2_lv_nmos_dphibw_norm = 0.6105
-  .parameters sg13g2_lv_nmos_dphiblw_norm= 0.9300
-  .parameters sg13g2_lv_nmos_themuo_norm = 0.8708
-  .parameters sg13g2_lv_nmos_thesatl_norm= 0.5510
-  .parameters sg13g2_lv_nmos_thesatw_norm= 1.4300
-  .parameters sg13g2_lv_nmos_thesatlw_norm= 0.0860
-  .parameters sg13g2_lv_nmos_toxo_norm   = 0.9600
-  .parameters sg13g2_lv_nmos_toxovo_norm = 0.9600
-  .parameters sg13g2_lv_nmos_cjorbot_norm= 0.9200
-  .parameters sg13g2_lv_nmos_cjorsti_norm= 0.9200
-  .parameters sg13g2_lv_nmos_cjorgat_norm= 0.9200
+  .param sg13g2_lv_nmos_vfbo_mm_norm= 1.0
+  .param sg13g2_lv_nmos_ctl_norm    = 1.4310
+  .param sg13g2_lv_nmos_rsw1_norm   = 0.9000
+  .param sg13g2_lv_nmos_muew_norm   = 0.7780
+  .param sg13g2_lv_nmos_dphibo_norm = 0.8137
+  .param sg13g2_lv_nmos_dphibl_norm = 0.6550
+  .param sg13g2_lv_nmos_dphibw_norm = 0.6105
+  .param sg13g2_lv_nmos_dphiblw_norm= 0.9300
+  .param sg13g2_lv_nmos_themuo_norm = 0.8708
+  .param sg13g2_lv_nmos_thesatl_norm= 0.5510
+  .param sg13g2_lv_nmos_thesatw_norm= 1.4300
+  .param sg13g2_lv_nmos_thesatlw_norm= 0.0860
+  .param sg13g2_lv_nmos_toxo_norm   = 0.9600
+  .param sg13g2_lv_nmos_toxovo_norm = 0.9600
+  .param sg13g2_lv_nmos_cjorbot_norm= 0.9200
+  .param sg13g2_lv_nmos_cjorsti_norm= 0.9200
+  .param sg13g2_lv_nmos_cjorgat_norm= 0.9200
   
-  .parameters sg13g2_lv_pmos_vfbo_mm_norm= 1.0
-  .parameters sg13g2_lv_pmos_ctl_norm    = 2.4800
-  .parameters sg13g2_lv_pmos_rsw1_norm   = 0.5000
-  .parameters sg13g2_lv_pmos_muew_norm   = 0.9620
-  .parameters sg13g2_lv_pmos_dphibo_norm = 1.2350
-  .parameters sg13g2_lv_pmos_dphibl_norm = 0.5066
-  .parameters sg13g2_lv_pmos_dphibw_norm = 3.9230
-  .parameters sg13g2_lv_pmos_dphiblw_norm= 1.0000
-  .parameters sg13g2_lv_pmos_themuo_norm = 1.0200
-  .parameters sg13g2_lv_pmos_thesatl_norm= 0.1880
-  .parameters sg13g2_lv_pmos_thesatw_norm= 1.2440
-  .parameters sg13g2_lv_pmos_thesatlw_norm= 2.0000
-  .parameters sg13g2_lv_pmos_toxo_norm   = 0.9600
-  .parameters sg13g2_lv_pmos_toxovo_norm = 0.9600
-  .parameters sg13g2_lv_pmos_cjorbot_norm= 0.9200
-  .parameters sg13g2_lv_pmos_cjorsti_norm= 0.9200
-  .parameters sg13g2_lv_pmos_cjorgat_norm= 0.9200
+  .param sg13g2_lv_pmos_vfbo_mm_norm= 1.0
+  .param sg13g2_lv_pmos_ctl_norm    = 2.4800
+  .param sg13g2_lv_pmos_rsw1_norm   = 0.5000
+  .param sg13g2_lv_pmos_muew_norm   = 0.9620
+  .param sg13g2_lv_pmos_dphibo_norm = 1.2350
+  .param sg13g2_lv_pmos_dphibl_norm = 0.5066
+  .param sg13g2_lv_pmos_dphibw_norm = 3.9230
+  .param sg13g2_lv_pmos_dphiblw_norm= 1.0000
+  .param sg13g2_lv_pmos_themuo_norm = 1.0200
+  .param sg13g2_lv_pmos_thesatl_norm= 0.1880
+  .param sg13g2_lv_pmos_thesatw_norm= 1.2440
+  .param sg13g2_lv_pmos_thesatlw_norm= 2.0000
+  .param sg13g2_lv_pmos_toxo_norm   = 0.9600
+  .param sg13g2_lv_pmos_toxovo_norm = 0.9600
+  .param sg13g2_lv_pmos_cjorbot_norm= 0.9200
+  .param sg13g2_lv_pmos_cjorsti_norm= 0.9200
+  .param sg13g2_lv_pmos_cjorgat_norm= 0.9200
   
-  .parameters sg13g2_lv_svaricap_lap   = 1.24   
-  .parameters sg13g2_lv_svaricap_toxo  = 0.96   
+  .param sg13g2_lv_svaricap_lap   = 1.24   
+  .param sg13g2_lv_svaricap_toxo  = 0.96   
   
   .include sg13g2_moslv_stat.lib   
   .include sg13g2_moslv_mod.lib
@@ -342,88 +342,88 @@
 **************** CORNER_LIB OF sg13g2_lv SF MODEL **************** 
 * Slow n, Fast p    
 .LIB mos_sf  
-  .parameters sg13g2_lv_nmos_vfbo_mm= 1.0
-  .parameters sg13g2_lv_nmos_ctl    = 0.8509
-  .parameters sg13g2_lv_nmos_rsw1   = 0.6880
-  .parameters sg13g2_lv_nmos_muew   = 0.9100
-  .parameters sg13g2_lv_nmos_dphibo = 1.0993
-  .parameters sg13g2_lv_nmos_dphibl = 1.1526
-  .parameters sg13g2_lv_nmos_dphibw = 1.1520
-  .parameters sg13g2_lv_nmos_dphiblw= 0.9932
-  .parameters sg13g2_lv_nmos_themuo = 0.8812
-  .parameters sg13g2_lv_nmos_thesatl= 0.9405
-  .parameters sg13g2_lv_nmos_thesatw= 1.5465
-  .parameters sg13g2_lv_nmos_thesatlw= 0.8001
-  .parameters sg13g2_lv_nmos_toxo   = 1.0200
-  .parameters sg13g2_lv_nmos_toxovo = 1.0200
-  .parameters sg13g2_lv_nmos_cjorbot= 1.0400
-  .parameters sg13g2_lv_nmos_cjorsti= 1.0400
-  .parameters sg13g2_lv_nmos_cjorgat= 1.0400
+  .param sg13g2_lv_nmos_vfbo_mm= 1.0
+  .param sg13g2_lv_nmos_ctl    = 0.8509
+  .param sg13g2_lv_nmos_rsw1   = 0.6880
+  .param sg13g2_lv_nmos_muew   = 0.9100
+  .param sg13g2_lv_nmos_dphibo = 1.0993
+  .param sg13g2_lv_nmos_dphibl = 1.1526
+  .param sg13g2_lv_nmos_dphibw = 1.1520
+  .param sg13g2_lv_nmos_dphiblw= 0.9932
+  .param sg13g2_lv_nmos_themuo = 0.8812
+  .param sg13g2_lv_nmos_thesatl= 0.9405
+  .param sg13g2_lv_nmos_thesatw= 1.5465
+  .param sg13g2_lv_nmos_thesatlw= 0.8001
+  .param sg13g2_lv_nmos_toxo   = 1.0200
+  .param sg13g2_lv_nmos_toxovo = 1.0200
+  .param sg13g2_lv_nmos_cjorbot= 1.0400
+  .param sg13g2_lv_nmos_cjorsti= 1.0400
+  .param sg13g2_lv_nmos_cjorgat= 1.0400
   
-  .parameters sg13g2_lv_pmos_vfbo_mm= 1.0  
-  .parameters sg13g2_lv_pmos_ctl    = 2.2185
-  .parameters sg13g2_lv_pmos_rsw1   = 0.6360
-  .parameters sg13g2_lv_pmos_muew   = 1.0070
-  .parameters sg13g2_lv_pmos_dphibo = 1.0700
-  .parameters sg13g2_lv_pmos_dphibl = 0.6808
-  .parameters sg13g2_lv_pmos_dphibw = 1.1715
-  .parameters sg13g2_lv_pmos_dphiblw= 1.0000
-  .parameters sg13g2_lv_pmos_themuo = 0.9890
-  .parameters sg13g2_lv_pmos_thesatl= 0.3695
-  .parameters sg13g2_lv_pmos_thesatw= 1.1620
-  .parameters sg13g2_lv_pmos_thesatlw= 1.5000
-  .parameters sg13g2_lv_pmos_toxo   = 0.9800
-  .parameters sg13g2_lv_pmos_toxovo = 0.9800
-  .parameters sg13g2_lv_pmos_cjorbot= 0.9600
-  .parameters sg13g2_lv_pmos_cjorsti= 0.9600
-  .parameters sg13g2_lv_pmos_cjorgat= 0.9600
+  .param sg13g2_lv_pmos_vfbo_mm= 1.0  
+  .param sg13g2_lv_pmos_ctl    = 2.2185
+  .param sg13g2_lv_pmos_rsw1   = 0.6360
+  .param sg13g2_lv_pmos_muew   = 1.0070
+  .param sg13g2_lv_pmos_dphibo = 1.0700
+  .param sg13g2_lv_pmos_dphibl = 0.6808
+  .param sg13g2_lv_pmos_dphibw = 1.1715
+  .param sg13g2_lv_pmos_dphiblw= 1.0000
+  .param sg13g2_lv_pmos_themuo = 0.9890
+  .param sg13g2_lv_pmos_thesatl= 0.3695
+  .param sg13g2_lv_pmos_thesatw= 1.1620
+  .param sg13g2_lv_pmos_thesatlw= 1.5000
+  .param sg13g2_lv_pmos_toxo   = 0.9800
+  .param sg13g2_lv_pmos_toxovo = 0.9800
+  .param sg13g2_lv_pmos_cjorbot= 0.9600
+  .param sg13g2_lv_pmos_cjorsti= 0.9600
+  .param sg13g2_lv_pmos_cjorgat= 0.9600
   
-  .parameters sg13g2_lv_svaricap_lap   = 1.161   
-  .parameters sg13g2_lv_svaricap_toxo  = 0.98   
+  .param sg13g2_lv_svaricap_lap   = 1.161   
+  .param sg13g2_lv_svaricap_toxo  = 0.98   
   
   .include sg13g2_moslv_mod.lib   
 .ENDL mos_sf
   
 * Slow n, Fast p with statistical modeling 
 .LIB mos_sf_stat
-  .parameters sg13g2_lv_nmos_vfbo_mm_norm= 1.0
-  .parameters sg13g2_lv_nmos_ctl_norm    = 0.8509
-  .parameters sg13g2_lv_nmos_rsw1_norm   = 0.6880
-  .parameters sg13g2_lv_nmos_muew_norm   = 0.9100
-  .parameters sg13g2_lv_nmos_dphibo_norm = 1.0993
-  .parameters sg13g2_lv_nmos_dphibl_norm = 1.1526
-  .parameters sg13g2_lv_nmos_dphibw_norm = 1.1520
-  .parameters sg13g2_lv_nmos_dphiblw_norm= 0.9932
-  .parameters sg13g2_lv_nmos_themuo_norm = 0.8812
-  .parameters sg13g2_lv_nmos_thesatl_norm= 0.9405
-  .parameters sg13g2_lv_nmos_thesatw_norm= 1.5465
-  .parameters sg13g2_lv_nmos_thesatlw_norm= 0.8001
-  .parameters sg13g2_lv_nmos_toxo_norm   = 1.0200
-  .parameters sg13g2_lv_nmos_toxovo_norm = 1.0200
-  .parameters sg13g2_lv_nmos_cjorbot_norm= 1.0400
-  .parameters sg13g2_lv_nmos_cjorsti_norm= 1.0400
-  .parameters sg13g2_lv_nmos_cjorgat_norm= 1.0400
+  .param sg13g2_lv_nmos_vfbo_mm_norm= 1.0
+  .param sg13g2_lv_nmos_ctl_norm    = 0.8509
+  .param sg13g2_lv_nmos_rsw1_norm   = 0.6880
+  .param sg13g2_lv_nmos_muew_norm   = 0.9100
+  .param sg13g2_lv_nmos_dphibo_norm = 1.0993
+  .param sg13g2_lv_nmos_dphibl_norm = 1.1526
+  .param sg13g2_lv_nmos_dphibw_norm = 1.1520
+  .param sg13g2_lv_nmos_dphiblw_norm= 0.9932
+  .param sg13g2_lv_nmos_themuo_norm = 0.8812
+  .param sg13g2_lv_nmos_thesatl_norm= 0.9405
+  .param sg13g2_lv_nmos_thesatw_norm= 1.5465
+  .param sg13g2_lv_nmos_thesatlw_norm= 0.8001
+  .param sg13g2_lv_nmos_toxo_norm   = 1.0200
+  .param sg13g2_lv_nmos_toxovo_norm = 1.0200
+  .param sg13g2_lv_nmos_cjorbot_norm= 1.0400
+  .param sg13g2_lv_nmos_cjorsti_norm= 1.0400
+  .param sg13g2_lv_nmos_cjorgat_norm= 1.0400
   
-  .parameters sg13g2_lv_pmos_vfbo_mm_norm= 1.0  
-  .parameters sg13g2_lv_pmos_ctl_norm    = 2.2185
-  .parameters sg13g2_lv_pmos_rsw1_norm   = 0.6360
-  .parameters sg13g2_lv_pmos_muew_norm   = 1.0070
-  .parameters sg13g2_lv_pmos_dphibo_norm = 1.0700
-  .parameters sg13g2_lv_pmos_dphibl_norm = 0.6808
-  .parameters sg13g2_lv_pmos_dphibw_norm = 1.1715
-  .parameters sg13g2_lv_pmos_dphiblw_norm= 1.0000
-  .parameters sg13g2_lv_pmos_themuo_norm = 0.9890
-  .parameters sg13g2_lv_pmos_thesatl_norm= 0.3695
-  .parameters sg13g2_lv_pmos_thesatw_norm= 1.1620
-  .parameters sg13g2_lv_pmos_thesatlw_norm= 1.5000
-  .parameters sg13g2_lv_pmos_toxo_norm   = 0.9800
-  .parameters sg13g2_lv_pmos_toxovo_norm = 0.9800
-  .parameters sg13g2_lv_pmos_cjorbot_norm= 0.9600
-  .parameters sg13g2_lv_pmos_cjorsti_norm= 0.9600
-  .parameters sg13g2_lv_pmos_cjorgat_norm= 0.9600
+  .param sg13g2_lv_pmos_vfbo_mm_norm= 1.0  
+  .param sg13g2_lv_pmos_ctl_norm    = 2.2185
+  .param sg13g2_lv_pmos_rsw1_norm   = 0.6360
+  .param sg13g2_lv_pmos_muew_norm   = 1.0070
+  .param sg13g2_lv_pmos_dphibo_norm = 1.0700
+  .param sg13g2_lv_pmos_dphibl_norm = 0.6808
+  .param sg13g2_lv_pmos_dphibw_norm = 1.1715
+  .param sg13g2_lv_pmos_dphiblw_norm= 1.0000
+  .param sg13g2_lv_pmos_themuo_norm = 0.9890
+  .param sg13g2_lv_pmos_thesatl_norm= 0.3695
+  .param sg13g2_lv_pmos_thesatw_norm= 1.1620
+  .param sg13g2_lv_pmos_thesatlw_norm= 1.5000
+  .param sg13g2_lv_pmos_toxo_norm   = 0.9800
+  .param sg13g2_lv_pmos_toxovo_norm = 0.9800
+  .param sg13g2_lv_pmos_cjorbot_norm= 0.9600
+  .param sg13g2_lv_pmos_cjorsti_norm= 0.9600
+  .param sg13g2_lv_pmos_cjorgat_norm= 0.9600
   
-  .parameters sg13g2_lv_svaricap_lap   = 1.161   
-  .parameters sg13g2_lv_svaricap_toxo  = 0.98   
+  .param sg13g2_lv_svaricap_lap   = 1.161   
+  .param sg13g2_lv_svaricap_toxo  = 0.98   
   
   .include sg13g2_moslv_stat.lib   
   .include sg13g2_moslv_mod.lib   
@@ -431,88 +431,88 @@
 **************** CORNER_LIB OF sg13g2_lv FS MODEL **************** 
 * Fast n, Slow p without statistical
 .LIB mos_fs
-  .parameters sg13g2_lv_nmos_vfbo_mm= 1.0
-  .parameters sg13g2_lv_nmos_ctl    = 1.3195
-  .parameters sg13g2_lv_nmos_rsw1   = 0.8100
-  .parameters sg13g2_lv_nmos_muew   = 0.8140
-  .parameters sg13g2_lv_nmos_dphibo = 0.9026
-  .parameters sg13g2_lv_nmos_dphibl = 0.8122
-  .parameters sg13g2_lv_nmos_dphibw = 0.7927
-  .parameters sg13g2_lv_nmos_dphiblw= 0.9527
-  .parameters sg13g2_lv_nmos_themuo = 0.8733
-  .parameters sg13g2_lv_nmos_thesatl= 0.6680
-  .parameters sg13g2_lv_nmos_thesatw= 1.4650
-  .parameters sg13g2_lv_nmos_thesatlw= 0.3493
-  .parameters sg13g2_lv_nmos_toxo   = 0.9800
-  .parameters sg13g2_lv_nmos_toxovo = 0.9800
-  .parameters sg13g2_lv_nmos_cjorbot= 0.9600
-  .parameters sg13g2_lv_nmos_cjorsti= 0.9600
-  .parameters sg13g2_lv_nmos_cjorgat= 0.9600
+  .param sg13g2_lv_nmos_vfbo_mm= 1.0
+  .param sg13g2_lv_nmos_ctl    = 1.3195
+  .param sg13g2_lv_nmos_rsw1   = 0.8100
+  .param sg13g2_lv_nmos_muew   = 0.8140
+  .param sg13g2_lv_nmos_dphibo = 0.9026
+  .param sg13g2_lv_nmos_dphibl = 0.8122
+  .param sg13g2_lv_nmos_dphibw = 0.7927
+  .param sg13g2_lv_nmos_dphiblw= 0.9527
+  .param sg13g2_lv_nmos_themuo = 0.8733
+  .param sg13g2_lv_nmos_thesatl= 0.6680
+  .param sg13g2_lv_nmos_thesatw= 1.4650
+  .param sg13g2_lv_nmos_thesatlw= 0.3493
+  .param sg13g2_lv_nmos_toxo   = 0.9800
+  .param sg13g2_lv_nmos_toxovo = 0.9800
+  .param sg13g2_lv_nmos_cjorbot= 0.9600
+  .param sg13g2_lv_nmos_cjorsti= 0.9600
+  .param sg13g2_lv_nmos_cjorgat= 0.9600
   
-  .parameters sg13g2_lv_pmos_vfbo_mm= 1.0  
-  .parameters sg13g2_lv_pmos_ctl    = 1.6545
-  .parameters sg13g2_lv_pmos_rsw1   = 0.8542
-  .parameters sg13g2_lv_pmos_muew   = 1.0775
-  .parameters sg13g2_lv_pmos_dphibo = 0.7467
-  .parameters sg13g2_lv_pmos_dphibl = 1.1045
-  .parameters sg13g2_lv_pmos_dphibw = -3.2860
-  .parameters sg13g2_lv_pmos_dphiblw= 1.0000
-  .parameters sg13g2_lv_pmos_themuo = 0.9150
-  .parameters sg13g2_lv_pmos_thesatl= 0.8850
-  .parameters sg13g2_lv_pmos_thesatw= 1.0337
-  .parameters sg13g2_lv_pmos_thesatlw= 1.0000
-  .parameters sg13g2_lv_pmos_toxo   = 1.0200
-  .parameters sg13g2_lv_pmos_toxovo = 1.0200
-  .parameters sg13g2_lv_pmos_cjorbot= 1.0400
-  .parameters sg13g2_lv_pmos_cjorsti= 1.0400
-  .parameters sg13g2_lv_pmos_cjorgat= 1.0400
+  .param sg13g2_lv_pmos_vfbo_mm= 1.0  
+  .param sg13g2_lv_pmos_ctl    = 1.6545
+  .param sg13g2_lv_pmos_rsw1   = 0.8542
+  .param sg13g2_lv_pmos_muew   = 1.0775
+  .param sg13g2_lv_pmos_dphibo = 0.7467
+  .param sg13g2_lv_pmos_dphibl = 1.1045
+  .param sg13g2_lv_pmos_dphibw = -3.2860
+  .param sg13g2_lv_pmos_dphiblw= 1.0000
+  .param sg13g2_lv_pmos_themuo = 0.9150
+  .param sg13g2_lv_pmos_thesatl= 0.8850
+  .param sg13g2_lv_pmos_thesatw= 1.0337
+  .param sg13g2_lv_pmos_thesatlw= 1.0000
+  .param sg13g2_lv_pmos_toxo   = 1.0200
+  .param sg13g2_lv_pmos_toxovo = 1.0200
+  .param sg13g2_lv_pmos_cjorbot= 1.0400
+  .param sg13g2_lv_pmos_cjorsti= 1.0400
+  .param sg13g2_lv_pmos_cjorgat= 1.0400
   
-  .parameters sg13g2_lv_svaricap_lap   = 1.041   
-  .parameters sg13g2_lv_svaricap_toxo  = 1.02   
+  .param sg13g2_lv_svaricap_lap   = 1.041   
+  .param sg13g2_lv_svaricap_toxo  = 1.02   
   
   .include sg13g2_moslv_mod.lib   
 .ENDL mos_fs
   
 * Fast n, Slow p with statistical
 .LIB mos_fs_stat
-  .parameters sg13g2_lv_nmos_vfbo_mm_norm= 1.0
-  .parameters sg13g2_lv_nmos_ctl_norm    = 1.3195
-  .parameters sg13g2_lv_nmos_rsw1_norm   = 0.8100
-  .parameters sg13g2_lv_nmos_muew_norm   = 0.8140
-  .parameters sg13g2_lv_nmos_dphibo_norm = 0.9026
-  .parameters sg13g2_lv_nmos_dphibl_norm = 0.8122
-  .parameters sg13g2_lv_nmos_dphibw_norm = 0.7927
-  .parameters sg13g2_lv_nmos_dphiblw_norm= 0.9527
-  .parameters sg13g2_lv_nmos_themuo_norm = 0.8733
-  .parameters sg13g2_lv_nmos_thesatl_norm= 0.6680
-  .parameters sg13g2_lv_nmos_thesatw_norm= 1.4650
-  .parameters sg13g2_lv_nmos_thesatlw_norm= 0.3493
-  .parameters sg13g2_lv_nmos_toxo_norm   = 0.9800
-  .parameters sg13g2_lv_nmos_toxovo_norm = 0.9800
-  .parameters sg13g2_lv_nmos_cjorbot_norm= 0.9600
-  .parameters sg13g2_lv_nmos_cjorsti_norm= 0.9600
-  .parameters sg13g2_lv_nmos_cjorgat_norm= 0.9600
+  .param sg13g2_lv_nmos_vfbo_mm_norm= 1.0
+  .param sg13g2_lv_nmos_ctl_norm    = 1.3195
+  .param sg13g2_lv_nmos_rsw1_norm   = 0.8100
+  .param sg13g2_lv_nmos_muew_norm   = 0.8140
+  .param sg13g2_lv_nmos_dphibo_norm = 0.9026
+  .param sg13g2_lv_nmos_dphibl_norm = 0.8122
+  .param sg13g2_lv_nmos_dphibw_norm = 0.7927
+  .param sg13g2_lv_nmos_dphiblw_norm= 0.9527
+  .param sg13g2_lv_nmos_themuo_norm = 0.8733
+  .param sg13g2_lv_nmos_thesatl_norm= 0.6680
+  .param sg13g2_lv_nmos_thesatw_norm= 1.4650
+  .param sg13g2_lv_nmos_thesatlw_norm= 0.3493
+  .param sg13g2_lv_nmos_toxo_norm   = 0.9800
+  .param sg13g2_lv_nmos_toxovo_norm = 0.9800
+  .param sg13g2_lv_nmos_cjorbot_norm= 0.9600
+  .param sg13g2_lv_nmos_cjorsti_norm= 0.9600
+  .param sg13g2_lv_nmos_cjorgat_norm= 0.9600
   
-  .parameters sg13g2_lv_pmos_vfbo_mm_norm= 1.0  
-  .parameters sg13g2_lv_pmos_ctl_norm    = 1.6545
-  .parameters sg13g2_lv_pmos_rsw1_norm   = 0.8542
-  .parameters sg13g2_lv_pmos_muew_norm   = 1.0775
-  .parameters sg13g2_lv_pmos_dphibo_norm = 0.7467
-  .parameters sg13g2_lv_pmos_dphibl_norm = 1.1045
-  .parameters sg13g2_lv_pmos_dphibw_norm = -3.2860
-  .parameters sg13g2_lv_pmos_dphiblw_norm= 1.0000
-  .parameters sg13g2_lv_pmos_themuo_norm = 0.9150
-  .parameters sg13g2_lv_pmos_thesatl_norm= 0.8850
-  .parameters sg13g2_lv_pmos_thesatw_norm= 1.0337
-  .parameters sg13g2_lv_pmos_thesatlw_norm= 1.0000
-  .parameters sg13g2_lv_pmos_toxo_norm   = 1.0200
-  .parameters sg13g2_lv_pmos_toxovo_norm = 1.0200
-  .parameters sg13g2_lv_pmos_cjorbot_norm= 1.0400
-  .parameters sg13g2_lv_pmos_cjorsti_norm= 1.0400
-  .parameters sg13g2_lv_pmos_cjorgat_norm= 1.0400
+  .param sg13g2_lv_pmos_vfbo_mm_norm= 1.0  
+  .param sg13g2_lv_pmos_ctl_norm    = 1.6545
+  .param sg13g2_lv_pmos_rsw1_norm   = 0.8542
+  .param sg13g2_lv_pmos_muew_norm   = 1.0775
+  .param sg13g2_lv_pmos_dphibo_norm = 0.7467
+  .param sg13g2_lv_pmos_dphibl_norm = 1.1045
+  .param sg13g2_lv_pmos_dphibw_norm = -3.2860
+  .param sg13g2_lv_pmos_dphiblw_norm= 1.0000
+  .param sg13g2_lv_pmos_themuo_norm = 0.9150
+  .param sg13g2_lv_pmos_thesatl_norm= 0.8850
+  .param sg13g2_lv_pmos_thesatw_norm= 1.0337
+  .param sg13g2_lv_pmos_thesatlw_norm= 1.0000
+  .param sg13g2_lv_pmos_toxo_norm   = 1.0200
+  .param sg13g2_lv_pmos_toxovo_norm = 1.0200
+  .param sg13g2_lv_pmos_cjorbot_norm= 1.0400
+  .param sg13g2_lv_pmos_cjorsti_norm= 1.0400
+  .param sg13g2_lv_pmos_cjorgat_norm= 1.0400
   
-  .parameters sg13g2_lv_svaricap_lap   = 1.041   
-  .parameters sg13g2_lv_svaricap_toxo  = 1.02   
+  .param sg13g2_lv_svaricap_lap   = 1.041   
+  .param sg13g2_lv_svaricap_toxo  = 1.02   
   
   .include sg13g2_moslv_stat.lib
   .include sg13g2_moslv_mod.lib
diff --git a/ihp-sg13g2/libs.tech/ngspice/models/cornerRES.lib b/ihp-sg13g2/libs.tech/ngspice/models/cornerRES.lib
index 746d722b..5d94cffa 100644
--- a/ihp-sg13g2/libs.tech/ngspice/models/cornerRES.lib
+++ b/ihp-sg13g2/libs.tech/ngspice/models/cornerRES.lib
@@ -17,22 +17,22 @@
 *#######################################################################
 * Typical without statistical modeling          
 .LIB res_typ  
-  .parameters rsh_rhigh = 1360
-  .parameters rsh_rppd  = 260.0
-  .parameters rsh_rsil  = 7.0
-  .parameters res_area  = 1.0
-  .parameters res_rpara = 1.0
+  .param rsh_rhigh = 1360
+  .param rsh_rppd  = 260.0
+  .param rsh_rsil  = 7.0
+  .param res_area  = 1.0
+  .param res_rpara = 1.0
            
 .include resistors_mod.lib
 .ENDL res_typ
   
 * Typical with statistical modeling
 .LIB res_typ_stat  
-  .parameters rsh_rhigh_norm= 1360
-  .parameters rsh_rppd_norm= 260.0
-  .parameters rsh_rsil_norm= 7.0
-  .parameters res_area_norm= 1.0
-  .parameters res_rpara_norm= 1.0
+  .param rsh_rhigh_norm= 1360
+  .param rsh_rppd_norm= 260.0
+  .param rsh_rsil_norm= 7.0
+  .param res_area_norm= 1.0
+  .param res_rpara_norm= 1.0
 
 .include resistors_stat.lib
 .include resistors_mod.lib
@@ -40,22 +40,22 @@
 
 * Best Case without statistical modeling
 .LIB res_bcs  
-  .parameters rsh_rhigh = 1020
-  .parameters rsh_rppd  = 234.0
-  .parameters rsh_rsil  = 6.02
-  .parameters res_area  = 1.0
-  .parameters res_rpara = 1.0
+  .param rsh_rhigh = 1020
+  .param rsh_rppd  = 234.0
+  .param rsh_rsil  = 6.02
+  .param res_area  = 1.0
+  .param res_rpara = 1.0
            
 .include resistors_mod.lib
 .ENDL res_bcs
   
 * Best Case with statistical modeling
 .LIB res_bcs_stat  
-  .parameters rsh_rhigh_norm= 1020
-  .parameters rsh_rppd_norm= 234.0
-  .parameters rsh_rsil_norm= 6.02
-  .parameters res_area_norm= 1.0
-  .parameters res_rpara_norm= 1.0
+  .param rsh_rhigh_norm= 1020
+  .param rsh_rppd_norm= 234.0
+  .param rsh_rsil_norm= 6.02
+  .param res_area_norm= 1.0
+  .param res_rpara_norm= 1.0
 
 .include resistors_stat.lib
 .include resistors_mod.lib
@@ -63,22 +63,22 @@
            
 * Worst Case without statistical modeling
 .LIB res_wcs  
-  .parameters rsh_rhigh = 1700
-  .parameters rsh_rppd  = 286.0
-  .parameters rsh_rsil  = 7.98
-  .parameters res_area  = 1.0
-  .parameters res_rpara = 1.0
+  .param rsh_rhigh = 1700
+  .param rsh_rppd  = 286.0
+  .param rsh_rsil  = 7.98
+  .param res_area  = 1.0
+  .param res_rpara = 1.0
            
 .include resistors_mod.lib
 .ENDL res_wcs
   
 * Worst Case with statistical modeling
 .LIB res_wcs_stat  
-  .parameters rsh_rhigh_norm= 1700
-  .parameters rsh_rppd_norm= 286.0
-  .parameters rsh_rsil_norm= 7.98
-  .parameters res_area_norm= 1.0
-  .parameters res_rpara_norm= 1.0
+  .param rsh_rhigh_norm= 1700
+  .param rsh_rppd_norm= 286.0
+  .param rsh_rsil_norm= 7.98
+  .param res_area_norm= 1.0
+  .param res_rpara_norm= 1.0
 
 .include resistors_stat.lib
 .include resistors_mod.lib
diff --git a/ihp-sg13g2/libs.tech/ngspice/models/sg13g2_hbt_mod.lib b/ihp-sg13g2/libs.tech/ngspice/models/sg13g2_hbt_mod.lib
index 2fa43fa6..5e6ce9af 100644
--- a/ihp-sg13g2/libs.tech/ngspice/models/sg13g2_hbt_mod.lib
+++ b/ihp-sg13g2/libs.tech/ngspice/models/sg13g2_hbt_mod.lib
@@ -410,11 +410,11 @@ Rt t 0 R = 1e9
 *
 .param ccb0 = 970e-018  isc0 = 2e-023  ikr0 = 4e-007  rc0 = 1e+003  rb0 = 700
 *
-.subckt pnpMPA e b c
+.subckt pnpMPA c b e
 .param a=2p p=6u ac=13.33p pc=14.64u
 + dev_a=a*1e12 dev_p=p*1e6 sub_a=ac*1e12 sub_p=pc*1e6
 
-QpnpMPA e b c pnpMPA_mod area=dev_a
+QpnpMPA c b e pnpMPA_mod area=dev_a
 
 .model pnpMPA_mod pnp
 + level = 1
diff --git a/ihp-sg13g2/libs.tech/openroad/export.yml b/ihp-sg13g2/libs.tech/openroad/export.yml
new file mode 100644
index 00000000..49ab733b
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/openroad/export.yml
@@ -0,0 +1,269 @@
+api_version: 1
+files:
+- destination: gds
+  file: libs.ref/sg13g2_io/gds/sg13g2_io.gds
+  md5_checksum: d3f637705a11f8867dd8efd33cffc75a
+- destination: lef
+  file: libs.ref/sg13g2_io/lef/sg13g2_io.lef
+  md5_checksum: ed10c467851cfafa782083ac2995c2b2
+- destination: lib
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diff --git a/ihp-sg13g2/libs.tech/openroad/generate.py b/ihp-sg13g2/libs.tech/openroad/generate.py
new file mode 100644
index 00000000..98c1920c
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/openroad/generate.py
@@ -0,0 +1,170 @@
+"""Generates the export.yml file which can be used OpenROAD-flow-scripts to update
+IHP PDK files there."""
+import pathlib
+import hashlib
+import yaml
+
+API_VERSION = 1
+PDK_ROOT = pathlib.Path(__file__).parent.parent.parent.resolve()
+
+SG13G2_IO = [
+    {
+        "destination": "gds",
+        "files": [
+            "gds/sg13g2_io.gds",
+        ]
+    },
+    {
+        "destination": "lef",
+        "files": [
+            "lef/sg13g2_io.lef",
+        ]
+    },
+    {
+        "destination": "lib",
+        "files": [
+            "lib/sg13g2_io_fast_1p32V_3p6V_m40C.lib",
+            "lib/sg13g2_io_fast_1p65V_3p6V_m40C.lib",
+            "lib/sg13g2_io_slow_1p08V_3p0V_125C.lib",
+            "lib/sg13g2_io_slow_1p35V_3p0V_125C.lib",
+            "lib/sg13g2_io_typ_1p2V_3p3V_25C.lib",
+            "lib/sg13g2_io_typ_1p5V_3p3V_25C.lib",
+        ]
+    },
+]
+
+SG13G2_SRAMS = [
+    "1P_1024x16_c2",
+    "1P_1024x64_c2",
+    "1P_1024x8_c2",
+    "1P_2048x64_c2",
+    "1P_256x48_c2",
+    "1P_256x64_c2",
+    "1P_4096x16_c3",
+    "1P_4096x8_c3",
+    "1P_512x64_c2",
+    "1P_64x64_c2",
+]
+
+SG13G2_SRAM = [
+    {
+        "destination": "cdl",
+        "file_formats": [
+            "cdl/RM_IHPSG13_{}_bm_bist.cdl",
+        ]
+    },
+    {
+        "destination": "gds",
+        "file_formats": [
+            "gds/RM_IHPSG13_{}_bm_bist.gds",
+        ]
+    },
+    {
+        "destination": "lef",
+        "file_formats": [
+            "lef/RM_IHPSG13_{}_bm_bist.lef",
+        ]
+    },
+    {
+        "destination": "lib",
+        "file_formats": [
+            "lib/RM_IHPSG13_{}_bm_bist_fast_1p32V_m55C.lib",
+            "lib/RM_IHPSG13_{}_bm_bist_slow_1p08V_125C.lib",
+            "lib/RM_IHPSG13_{}_bm_bist_typ_1p20V_25C.lib",
+        ]
+    },
+    {
+        "destination": "verilog",
+        "file_formats": [
+            "verilog/RM_IHPSG13_{}_bm_bist.v",
+        ]
+    },
+]
+
+SG13G2_STDCELL = [
+    {
+        "destination": "cdl",
+        "files": [
+            "cdl/sg13g2_stdcell.cdl",
+        ]
+    },
+    {
+        "destination": "gds",
+        "files": [
+            "gds/sg13g2_stdcell.gds",
+        ]
+    },
+    {
+        "destination": "lef",
+        "files": [
+            "lef/sg13g2_stdcell.lef",
+            "lef/sg13g2_tech.lef",
+        ]
+    },
+    {
+        "destination": "lib",
+        "files": [
+            "lib/sg13g2_stdcell_fast_1p32V_m40C.lib",
+            "lib/sg13g2_stdcell_fast_1p65V_m40C.lib",
+            "lib/sg13g2_stdcell_slow_1p08V_125C.lib",
+            "lib/sg13g2_stdcell_slow_1p35V_125C.lib",
+            "lib/sg13g2_stdcell_typ_1p20V_25C.lib",
+            "lib/sg13g2_stdcell_typ_1p50V_25C.lib",
+        ]
+    },
+    {
+        "destination": "verilog",
+        "files": [
+            "verilog/sg13g2_stdcell.v",
+        ]
+    },
+]
+
+
+def write_file(content):
+    """Saves the list of exportable files to the 'export.yml' file."""
+    filename = PDK_ROOT / "libs.tech" / "openroad" / "export.yml"
+    with open(filename, 'w', encoding="utf-8") as outfile:
+        yaml.dump(content, outfile, default_flow_style=False)
+
+
+def calc_file_md5(file):
+    """Calculates a MD5 checksum of a file."""
+    with open(file, 'rb') as file_content:
+        return hashlib.md5(file_content.read()).hexdigest()
+
+
+def get_entry(file, destination, cell_lib):
+    """Creates an entry for a specific file."""
+    entry = {
+        "file": str(pathlib.Path("libs.ref") / cell_lib / file),
+        "md5_checksum": calc_file_md5(PDK_ROOT / "libs.ref" / cell_lib / file),
+        "destination": destination,
+    }
+    return entry
+
+
+def main(): # pylint: disable=missing-function-docstring
+    content = {
+        "api_version": API_VERSION,
+        "files": [],
+    }
+    for entry in SG13G2_IO:
+        for file in entry.get('files', []):
+            content['files'].append(get_entry(file, entry['destination'], "sg13g2_io"))
+    for entry in SG13G2_SRAM:
+        for file in entry.get('files', []):
+            content['files'].append(get_entry(file, entry['destination'], "sg13g2_sram"))
+        for file_format in entry.get('file_formats', []):
+            for sram in SG13G2_SRAMS:
+                file = file_format.format(sram)
+                content['files'].append(get_entry(file, entry['destination'], "sg13g2_sram"))
+    for entry in SG13G2_STDCELL:
+        for file in entry.get('files', []):
+            content['files'].append(get_entry(file, entry['destination'], "sg13g2_stdcell"))
+
+    write_file(content)
+
+
+if __name__ == "__main__":
+    main()
diff --git a/ihp-sg13g2/libs.tech/pycell/cmim_code.py b/ihp-sg13g2/libs.tech/pycell/cmim_code.py
deleted file mode 100644
index fad3af8e..00000000
--- a/ihp-sg13g2/libs.tech/pycell/cmim_code.py
+++ /dev/null
@@ -1,112 +0,0 @@
-########################################################################
-#
-# Copyright 2023 IHP PDK Authors
-# 
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-# 
-#    https://www.apache.org/licenses/LICENSE-2.0
-# 
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-########################################################################
-__version__ = '$Revision: #3 $'
-
-from cni.dlo import *
-from utility_functions import *
-from geometry import *
-
-class cmim(DloGen):
-
-    @classmethod
-    def defineParamSpecs(self, specs):
-        # define parameters and default values
-        techparams = specs.tech.getTechParams()
-        
-        CDFVersion = techparams['CDFVersion']
-        minLW      = techparams['cmim_minLW']
-        defLW      = techparams['cmim_defLW']
-        caspec     = techparams['cmim_caspec']
-        cmax       = techparams['cmim_maxC']
-        model      = techparams['cmim_model']
-        
-        specs('cdf_version', CDFVersion, 'CDF Version')
-        specs('Display', 'Selected', 'Display', ChoiceConstraint(['All', 'Selected']))
-        specs('Calculate', 'w&l', 'Calculate', ChoiceConstraint(['C', 'w', 'l', 'w&l']))
-        specs('model', model, 'Model name')
-
-        C = CbCapCalc('C', 0, Numeric(defLW), Numeric(defLW), 'cmim')
-        specs('C', eng_string(C), 'C')
-        
-        specs('w', defLW, 'Width')
-        specs('l', defLW, 'Length')
-        
-        specs('Cspec', caspec, 'Cspec [F/sqm]')
-        specs('Wmin', minLW, 'Wmin')
-        specs('Lmin', minLW, 'Lmin')
-        specs('Cmax', cmax, 'Cmax')
-        
-        specs('ic', '', 'Initial condition')
-        specs('m', '1', 'Multiplier')
-        specs('trise', '', 'Temp rise from ambient')
-     
-    def setupParams(self, params):
-        # process parameter values entered by user
-        self.w = eng_string_to_float(params['w'])*1e6
-        self.l = eng_string_to_float(params['l'])*1e6
-    
-    def genLayout(self):
-        self.grid = self.tech.getGridResolution()
-        self.techparams = self.tech.getTechParams()
-        self.epsilon = self.techparams['epsilon1']
-
-        self.generateVias()
-
-        # generate rectangle layout
-        x1 = self.techparams['Mim_d']-self.techparams['TV1_d']+self.xoffset
-        x2 = self.xcont_cnt
-        y1 = self.techparams['Mim_d']-self.techparams['TV1_d']+self.yoffset
-        y2 = self.ycont_cnt
-        caplayerBBox = Box(0, 0, self.w, self.l)
-        topMetalBBox = Box(x1, y1, x2, y2)
-        bottomMetalBBox = Box(-self.techparams['Mim_c'], -self.techparams['Mim_c'], self.w + self.techparams['Mim_c'], self.l + self.techparams['Mim_c'])
-        
-        Rect(Layer('MIM'), caplayerBBox)  
-        self.bottomMetal = Rect(Layer('Metal5'), bottomMetalBBox)
-        self.topMetal= Rect(Layer('TopMetal1'), topMetalBBox)     
-
-        self.createPins() 
-
-    def createPins(self):
-        self.addPin('PLUS', 'PLUS', self.topMetal.getBBox(), Layer('TopMetal1','pin'))
-        self.addPin('MINUS', 'MINUS', self.bottomMetal.getBBox(), Layer('Metal5','pin'))
-
-    def generateVias(self):
-        cont_over = self.techparams['Mim_d']
-        cont_dist = 0.84
-        cont_size = self.techparams['TV1_a']
-
-        xanz=((self.w-cont_over-cont_over+cont_dist)//(cont_size+cont_dist)+self.epsilon)
-        w1 = xanz*(cont_size+cont_dist)-cont_dist+cont_over+cont_over
-        self.xoffset=GridFix((self.w-w1)/2)
-
-        yanz = ((self.l-cont_over-cont_over+cont_dist)//(cont_size+cont_dist)+self.epsilon)
-        l1=yanz*(cont_size+cont_dist)-cont_dist+cont_over+cont_over
-        self.yoffset=GridFix((self.l-l1)/2)
-
-        ycont_cnt=cont_over+self.yoffset
-        while ycont_cnt+cont_size+cont_over <= self.l+self.epsilon:
-            xcont_cnt=cont_over+self.xoffset
-            while xcont_cnt+cont_size+cont_over <= self.w+self.epsilon:
-                via = Box(xcont_cnt, ycont_cnt, xcont_cnt+cont_size, ycont_cnt+cont_size)
-                Rect(Layer('Vmim'), via)
-                xcont_cnt=xcont_cnt+cont_size+cont_dist
-            
-            ycont_cnt=ycont_cnt+cont_size+cont_dist
-        self.xcont_cnt=xcont_cnt+self.techparams['TV1_d']-cont_dist
-        self.ycont_cnt=ycont_cnt+self.techparams['TV1_d']-cont_dist
diff --git a/ihp-sg13g2/libs.tech/pycell/geometry.py b/ihp-sg13g2/libs.tech/pycell/geometry.py
deleted file mode 100644
index e5217e12..00000000
--- a/ihp-sg13g2/libs.tech/pycell/geometry.py
+++ /dev/null
@@ -1,1691 +0,0 @@
-########################################################################
-#
-# Copyright 2023 IHP PDK Authors
-# 
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-# 
-#    https://www.apache.org/licenses/LICENSE-2.0
-# 
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-########################################################################
-
-
-__version__ = "$Revision: #3 $"
-
-from cni.dlo import *
-from cni.geo import fgOr
-from cni.geo import fgAnd
-from cni.geo import fgXor
-from cni.geo import fgNot
-from cni.geo import fgMerge
-from utility_functions import *
-from math import *
-
-#***********************************************************************************************************************
-# nth
-#***********************************************************************************************************************        
-def nth(index, mlist):
-    if type(mlist) is Box:
-        if index == 0 :
-            lw = mlist.lowerLeft()
-            x1 = lw.getX();
-            return x1
-        elif index == 1:
-            lw = mlist.lowerLeft()
-            y1 = lw.getY();
-            return y1
-        elif index == 2:
-            ur = mlist.upperRight()
-            x2 = ur.getX();
-            return x2
-        elif index == 3:
-            ur = mlist.upperRight()
-            y2 = ur.getY();
-            return y2
-            
-    return mlist[index]
-
-#***********************************************************************************************************************
-# dbDeleteObject
-#***********************************************************************************************************************
-def dbDeleteObject(obj):
-    obj.destroy()
-
-#***********************************************************************************************************************
-# dbLayerOr
-#***********************************************************************************************************************
-def dbLayerOr(layerId, id1, id2 = None):
-    if type(layerId) == str :
-        layerId = Layer(layerId)
-        
-    if id2 == None :
-        id2 = id1
-
-    idOr = id1.fgOr(id2, layerId)
-        
-    return idOr
-    
-#***********************************************************************************************************************
-# dbLayerOrList
-#***********************************************************************************************************************
-def dbLayerOrList(layerId, shapes):
-    if type(layerId) == str :
-        layerId = Layer(layerId)
-    
-    id1 = shapes[0]
-    for index in range(1, listlen(shapes)) :
-        id2 = nth(index, shapes)
-        idOr = dbLayerOr(layerId, id1, id2)
-        if index > 0 :
-            dbDeleteObject(id1)
-        id1 = idOr
-    
-    return idOr
-
-#***********************************************************************************************************************
-# dbLayerAnd
-#***********************************************************************************************************************
-def dbLayerAnd(layerId, id1, id2):
-    if type(layerId) == str :
-        layerId = Layer(layerId)
-
-    idAnd = id1.fgAnd(id2, layerId)
-        
-    return idAnd
-    
-#***********************************************************************************************************************
-# dbLayerAndList
-#***********************************************************************************************************************
-def dbLayerAndList(layerId, shapes):
-    if type(layerId) == str :
-        layerId = Layer(layerId)
-
-    idAnd = shapes[0]
-    for id in shapes[1:] :
-        idAnd = fgAnd(idAnd, id, layerId)
-        
-    return idAnd
-
-#***********************************************************************************************************************
-# dbLayerXor
-#***********************************************************************************************************************
-def dbLayerXor(layerId, id1, id2):
-    if type(layerId) == str :
-        layerId = Layer(layerId)
-
-    xorId = id1.fgXor(id2, layerId)
-        
-    return xorId
-    
-#***********************************************************************************************************************
-# dbLayerXorList
-#***********************************************************************************************************************
-def dbLayerXorList(layerId, shapes):
-    if type(layerId) == str :
-        layerId = Layer(layerId)
-
-    xorId = shapes[0]
-    for id in shapes[1:] :
-        xorId = fgXor(xorId, id, layerId)
-        
-    return xorId
-
-#***********************************************************************************************************************
-# dbLayerNot
-#***********************************************************************************************************************
-def dbLayerNot(layerId, id1, id2):
-    if type(layerId) == str :
-        layerId = Layer(layerId)
-
-    notId = id1.fgNot(id2, layerId)
-        
-    return notId
-    
-#***********************************************************************************************************************
-# dbLayerNotList
-#***********************************************************************************************************************
-def dbLayerNotList(layerId, shapes):
-    if type(layerId) == str :
-        layerId = Layer(layerId)
-
-    notId = shapes[0]
-    for id in shapes[1:] :
-        notId = fgNot(notId, id, layerId)
-        
-    return notId
-
-#***********************************************************************************************************************
-# dbLayerMerge
-#***********************************************************************************************************************
-def dbLayerMerge(self, layerId):
-    if type(layerId) == str :
-        layerId = Layer(layerId)
- 
-    shapes = self.getLeafComps()
-    mergeId = shapes[0].fgMerge(layerId)
-        
-    return mergeId
-
-#***********************************************************************************************************************
-# dbCopyShape
-#***********************************************************************************************************************    
-def dbLayerSize(self, layerId, shapes, size, numPoints, grid = 0) :
-    for id in shapes :
-        id.fgSize(ShapeFilter(), size, layerId, grid)
-    
-#***********************************************************************************************************************
-# dbCopyShape
-#***********************************************************************************************************************
-def dbCopyShape(fig, pnt, rot):
-    copyId = fig.clone()
-    
-    dbMoveFig(copyId, pnt, rot)
-    
-    return copyId
-  
-#***********************************************************************************************************************
-# dbMoveFig
-#***********************************************************************************************************************  
-def dbMoveFig(fig, pnt, rot) :
-    if rot :
-        fig.transform(Transform(0, 0, strToOrient(rot)))
-        
-    if pnt :
-        fig.moveBy(pnt.x, pnt.y) 
-
-#***********************************************************************************************************************
-# dbLayerInside
-#   layer - new layer for cloned shape
-#***********************************************************************************************************************
-def dbLayerInside(self, layer, idlist, id):
-
-    if type(layer) == str :
-        layer = Layer(layer)
-    
-    pnts = id.getPoints()
-    
-    mlist = list()    
-    for item in idlist : 
-        if type(item) == Rect :
-            if pnts.containsPoint(Point(item.left, item.bottom)) and pnts.containsPoint(Point(item.left, item.top)) and pnts.containsPoint(Point(item.right, item.bottom)) and pnts.containsPoint(Point(item.right, item.top)) :
-                it = item.clone()
-                it.layer = layer
-                mlist.append(it)
-        else :
-            pnts1 = item.getPoints()
-            yes = False
-            for pnt in pnts1 :
-                if pnts.containsPoint(pnt) :
-                    yes = True
-                else :
-                    yes = False
-                    break
-                
-            if yes :
-                it = item.clone()
-                it.layer = layer
-                mlist.append(it)
-                    
-        #idOr = id.fgOr(item, layer)
-        #if len(idOr.getComps()) == 1 :
-        #    shape = idOr.getComp(0)
-        #    if shape.getNumPoints() == 3 :
-        #        mlist.append(item.clone())
-        #    
-        #idOr.destroy()    
-            
-    return mlist
-    
-#***********************************************************************************************************************
-# dbLayerOutside
-#***********************************************************************************************************************
-def dbLayerOutside(self, layer, idlist, id):
-    if type(layer) == str :
-        layer = Layer(layer)
-    
-    if type(id) == Rect :
-        pnts = PointList([Point(id.left, id.bottom), Point(id.left, id.top), Point(id.right, id.bottom), Point(id.right, id.top)])
-    else :
-        pnts = id.getPoints()
-    
-    mlist = list()    
-    for item in idlist :
-        if type(item) == Rect :
-            if pnts.containsPoint(Point(item.left, item.bottom)) and pnts.containsPoint(Point(item.left, item.top)) and pnts.containsPoint(Point(item.right, item.bottom)) and pnts.containsPoint(Point(item.right, item.top)) :
-                pass
-            else :
-                mlist.append(item.clone())
-        else :
-            pnts1 = item.getPoints()
-            yes = False
-            for pnt in pnts1 :
-                if pnts.containsPoint(pnt) :
-                    yes = False
-                    break
-                else :
-                    yes = True
-                
-            if yes :
-                it = item.clone()
-                it.layer = layer
-                mlist.append(it)  
-            
-    return mlist
-
-#***********************************************************************************************************************
-# dbCreateRect
-#***********************************************************************************************************************    
-def dbCreateRect(self, layerId, bBox):
-    if type(layerId) == str :
-        layerId = Layer(layerId)
-        
-    rectId = Rect(layerId, bBox)
-    return rectId
-
-#***********************************************************************************************************************
-# dbCreatePolygon
-#***********************************************************************************************************************   
-def dbCreatePolygon(self, layerId, pointList):
-    if type(layerId) is str :
-        layerId = Layer(layerId)
-        
-    if type(pointList) is list :
-        points = PointList()
-        
-        pointIndex = 0
-        pointValue = 0
-        for p in pointList :
-            if pointIndex == 0 :
-                pointValue = p
-            elif pointIndex == 1 :                 
-                point = Point(pointValue, p)
-                points.append(point)                            
-                pointIndex = -1
-            
-            pointIndex = pointIndex + 1 
-            
-        pointList = points.compress()
-    else :
-        pointList = pointList.compress()
-        
-    polyId = Polygon(layerId, pointList)
-    return polyId
-    
-#***********************************************************************************************************************
-# dbCreatePath
-#***********************************************************************************************************************   
-def dbCreatePath(self, layerId, pointList, width, style=PathStyle.TRUNCATE):
-    if type(layerId) == str :
-        layerId = Layer(layerId)
-        
-    pointList = pointList.compress()
-        
-    pathId = Path(layerId, width, pointList, style)
-    return pathId
-
-#***********************************************************************************************************************
-# dbCreateDonut
-#***********************************************************************************************************************
-def dbCreateDonut(self, layerId, pnt, outRad, inRad):
-    if type(layerId) == str :
-        layerId = Layer(layerId)
-        
-    donutId = Donut(layerId, pnt, outRad, inRad)
-    return donutId
-    
-#***********************************************************************************************************************
-# dbCreateEllipse
-#***********************************************************************************************************************
-def dbCreateEllipse(self, layerId, bbox):
-    if type(layerId) == str :
-        layerId = Layer(layerId)
-        
-    ellipseId = Ellipse(layerId, bbox)
-    
-    return ellipseId
- 
-#***********************************************************************************************************************
-# dbConvertEllipseToPolygon
-#***********************************************************************************************************************   
-def dbConvertEllipseToPolygon(self, ellipse, numPoints, grid):
-    points = Ellipse.genPolygonPoints(ellipse.getBBox(), numPoints, grid)
-    polyId = dbCreatePolygon(self, ellipse.layer, points)
-    
-    return polyId
-
-#***********************************************************************************************************************
-# dbCreateLabel
-#***********************************************************************************************************************    
-def dbCreateLabel(self, layerId, point, text, align, rotation, font, size):
-    text = Text(layerId, text, point, size)
-     
-    text.setAlignment(strToAlignt(align))
-    text.setOrientation(strToOrient(rotation)) 
-    
-    """
-    rect = text.getBBox()
-    lw = rect.lowerLeft()
-    ur = rect.upperRight()
-    
-    x1 = lw.getX()
-    x2 = ur.getX()       
-    y1 = lw.getY()
-    y2 = ur.getY()
-    
-    if y1 > y2:
-        temp = y1
-        y1 = y2
-        y2 = temp
-    
-    if x1 > x2:
-        temp = x1
-        x1 = x2
-        x2 = temp      
-
-    shiftX = (x2-x1)/2
-    shiftY = (y2-y1)/2        
-    text.setFont(font)
-    text.setAlignment(align)
-    
-    if rotation is "R0":        
-        text.setOrientation(Orientation.R0)        
-        text.setOrigin(Point(x1-shiftX, y2+shiftY))
-    elif rotation is "R90": 
-        text.setOrigin(Point(x1-shiftY, y2-shiftX))
-        text.setOrientation(Orientation.R90)      
-    """    
-    return text
-
-#***********************************************************************************************************************
-# dbCreateNet
-#*********************************************************************************************************************** 
-def dbCreateNet(name, typ=SignalType.SIGNAL):
-    net = Net.find(name)
-    if not net :
-        net = Net(name, typ)
-        
-    return net
-    
-#***********************************************************************************************************************
-# dbCreateTerm
-#*********************************************************************************************************************** 
-def dbCreateTerm(self, name, typ=TermType.INPUT_OUTPUT):
-    term = Term.find(name)
-    if not term :
-        term = self.addTerm(name, typ)
-        
-    return term
-
-#***********************************************************************************************************************
-# dbCreatePin
-#***********************************************************************************************************************  
-def dbCreatePin(self, name, shape):
-    pin = self.addPin(name, name, shape.getBBox(shape.layer), shape.layer)
-    if not (shape.getNet() or shape.getPin()) :
-        pin.addShape(shape)
-    
-    return pin
-
-#***********************************************************************************************************************
-# MkPin
-#***********************************************************************************************************************            
-def MkPin(self, termName, termIndex, bBox, layerId, label=False, labelHight = -1):
-    if type(layerId) == str :
-        layerId = Layer(layerId, 'pin')
-        
-    bBox = bBox.fix()
-    
-    self.addPin(termName, termName, bBox, layerId)
-    
-    pcInst = dbCreateRect(self, layerId, bBox) # 17.6.11 GG
-        
-    # pin label
-    if label and termName :
-        if labelHight == -1 :
-            pcLabelHeight = 0.5*min(bBox.getWidth(), abs(bBox.getHeight()))
-        else :
-            pcLabelHeight = labelHight
-        dbCreateLabel(self, layerId, bBox.getCenter(), termName, 'centerCenter', 'R0', Font.EURO_STYLE, pcLabelHeight)
-    
-#***********************************************************************************************************************
-# dbCreateVia
-#*********************************************************************************************************************** 
-def dbCreateVia(self, ViaDef, pnt, rot, params):
-    via = StdVia(ViaDef.getName())
-    
-    via.setOrientation(strToOrient(rot))
-    via.setOrigin(pnt)
-    
-    vp = via.getParams()
-    if 'cutLayer' in params : 
-        cutLayer = params['cutLayer']
-    else :
-        cutLayer = vp.cutLayer
-    if 'cutSize' in params :
-        cutSize = params['cutSize']
-    else :
-        cutSize = vp.cutSize
-    if 'cutSpace' in params :
-        cutSpace = params['cutSpace']
-    else :
-        cutSpace = vp.cutSpace
-    if 'implant1Ext' in params :
-        implant1Ext = params['implant1Ext']
-    else :
-        implant1Ext = vp.implant1Ext
-    if 'implant2Ext' in params :
-        implant2Ext = params['implant2Ext']
-    else :
-        implant2Ext = vp.implant2Ext
-    if 'layer1Ext' in params :
-        layer1Ext = params['layer1Ext']
-    else :
-        layer1Ext = vp.layer1Ext
-    if 'layer1Offset' in params :
-        layer1Offset = params['layer1Offset']
-    else :
-        layer1Offset = vp.layer1Offset
-    if 'layer2Ext' in params :
-        layer2Ext = params['layer2Ext']
-    else :
-        layer2Ext = vp.layer2Ext
-    if 'layer2Offset' in params :
-        layer2Offset = params['layer2Offset']
-    else :
-        layer2Offset = vp.layer2Offset
-    if 'numHVCuts' in params :
-        numHVCuts = params['numHVCuts']
-    else :
-        numHVCuts = vp.numHVCuts
-    if 'originOffset' in params :
-        originOffset = params['originOffset']
-    else :
-        originOffset = vp.originOffset
-    
-    vp = ViaParam(vp,
-                  layer1Ext,
-                  layer2Ext,
-                  implant1Ext,
-                  implant2Ext,
-                  layer1Offset,
-                  layer2Offset,
-                  originOffset,
-                  cutSpace,
-                  cutSize,
-                  cutLayer,
-                  numHVCuts)
-    
-    via.setParams(vp)
-    
-    return via
-   
-#***********************************************************************************************************************
-# DrawRing
-#***********************************************************************************************************************  
-def DrawRing(self, layer, rl, rr, rb, rt, rw, rh) :
-    dbCreatePolygon(self, layer, PointList([Point(rl,rb), Point(rr,rb), 
-                                            Point(rr,rt), Point(rl,rt), 
-                                            Point(rl,rb+rh), Point(rl+rw,rb+rh), 
-                                            Point(rl+rw,rt-rh), Point(rr-rw,rt-rh), 
-                                            Point(rr-rw,rb+rh), Point(rl,rb+rh)]))
-         
-#***********************************************************************************************************************
-# ihpBuildCont
-#***********************************************************************************************************************
-def ihpBuildCont(self, layer1, layer2, layer3, width1, width3, length3, pathpnts, terminal, pinlabel, 
-                       layer2_enc, offset, chop, layer3_space) :
-            
-    # pinlabel is a boolean that determines whether a label will be created
-    # terminal is the pin name string
-        
-    bBox = Box(pathpnts.left-(width1/2), pathpnts.bottom, pathpnts.right+(width1/2), pathpnts.top)
-    
-    if terminal :
-        do_pins = True
-    else :
-        do_pins = False
-        
-        
-    # paths in layers 1&2 with subrectanges in layer3 and label in layer2
-    if (layer3 and layer2 and layer1 and (layer1 != layer2)) :
-        fig = dbCreateRect(self, layer2, bBox)
-        pin_fig = dbCreateRect(self, layer2, Box(bBox.left+layer2_enc, bBox.bottom+layer2_enc, bBox.right-layer2_enc, bBox.top-layer2_enc))
-        
-        contactArray(self, layer2, layer3, 
-                     bBox.left, bBox.bottom, bBox.right, bBox.top, 
-                     layer2_enc, offset, width3, layer3_space)
-                     
-    else : # paths in layers 1&2 with no subrectanges and label in layer2
-        if ( (not layer3) and layer2 and layer1 and (layer1 != layer2) ) :
-            fig = dbCreateRect(self, layer1, bBox)
-            pin_fig = dbCreateRect(self, layer2, Box(bBox.left+layer2_enc, bBox.bottom+layer2_enc, bBox.right-layer2_enc, bBox.top-layer2_enc))
-            
-        else : # path in layer2 and rectangles in layer3 (one layer path and subrectangles)
-            if( (not layer1) and (layer3 != layer2) ) :
-                fig = dbCreateRect(self, layer2, bBox)
-                pin_fig = fig
-                contactArray(self, layer2, layer3, 
-                             bBox.left, bBox.bottom, bBox.right, bBox.top, 
-                             layer2_enc, offset, width3, layer3_space)
-                             
-            else : # paths in layer 1 (one layer path)
-                if layer1 != layer2 :
-                    fig = dbCreateRect(self, layer1, bBox)
-                    pin_fig = fig
-    
-    return [pin_fig, fig]
-
-#***********************************************************************************************************************
-# buildCont
-#***********************************************************************************************************************
-def buildCont(self, layer1, layer2, layer3, width1, width3, length3, pathpnts, terminal, pinlabel, layer2_enc, offset, chop, layer3_space) :
-    # pinlabel is a boolean that determines whether a label will be created
-    # terminal is the pin name string
-    
-    if terminal :
-        do_pins = True
-    else :
-        do_pins = False
-        
-    if pathpnts[0].x > pathpnts[1].x :
-        x = pathpnts[0].x
-        pathpnts[0].x = pathpnts[1].x
-        pathpnts[1].x = x
-    if pathpnts[0].y > pathpnts[1].y :
-        y = pathpnts[0].y
-        pathpnts[0].y = pathpnts[1].y
-        pathpnts[1].y = y
-        
-    if pathpnts[0].x == pathpnts[1].x :
-        pathl = abs(pathpnts[0].y - pathpnts[1].y)
-        hor = False
-    elif pathpnts[0].y == pathpnts[1].y :
-        pathl = abs(pathpnts[0].x - pathpnts[1].x)
-        hor = True
-    else :
-        print 'Warning: Incline path is not allowed for buildCont procedure'
-        return
-        
-    count = pathl/(length3+layer3_space+offset)
-    if  count - int(count) > 0.5 :
-        count = int(count) + 1
-    start = 0
-    if pinlabel :
-        start = 1
-    
-    # paths in layers 1&2 with subrectanges in layer3 and label in layer2
-    if layer3 and layer2 and layer1 and (layer1 != layer2) :
-        # rodCreatePath
-        fig = dbCreatePath(self, layer1, pathpnts, width1)
-        if pinlabel :
-            if hor :
-                MkPin(self, terminal, 0, Box((pathpnts[0].x+offset), pathpnts[0].y-width3/2, (pathpnts[0].x+offset)+width3, pathpnts[0].y+width3/2), layer2, pinlabel, layer2, length3)
-            else :
-                MkPin(self, terminal, 0, Box(pathpnts[0].x-width3/2, (pathpnts[0].y+offset), pathpnts[0].x+width3/2, (pathpnts[0].y+offset)+length3), layer2, pinlabel, layer2, length3)
-                
-        # subRect
-        box = fig.getBBox()
-        if hor :
-            box.expandDir(Direction.WEST, -offset)
-            box.expandDir(Direction.EAST, -offset)
-        else :
-            box.expandDir(Direction.NORTH, -offset)
-            box.expandDir(Direction.SOUTH, -offset)
-        Rect.fillBBoxWithRects(layer3, box, width3, length3, layer3_space, layer3_space, GapStyle.DISTRIBUTE)
-        
-        # rodCreateRect
-        pin_fig = list()
-        if do_pins :
-            pin = MkPin(self, terminal, 0, fig.bbox.expand(-layer2_enc), layer1)
-        else :
-            pin = dbCreateRect(self, layer1, fig.bbox.expand(-layer2_enc))
-        pin_fig.append(pin)
-
-        #rodAlign(?alignObj, pin_fig, ?alignHandle, "centerCenter", ?refObj, fig, ?refHandle, "centerCenter")
-    else :   # paths in layers 1&2 with no subrectanges and label in layer2
-        if not layer3 and layer2 and layer1 and (layer1 != layer2) :
-            # rodCreatePath
-            fig = dbCreatePath(self, layer1, pathpnts, width1)
-            if pinlabel :
-                if hor :
-                    MkPin(self, terminal, 0, Box((pathpnts[0].x+offset), pathpnts[0].y-width3/2, (pathpnts[0].x+offset)+width3, pathpnts[0].y+width3/2), layer2, pinlabel, layer2, length3, 'R0', 'centerLeft', Font.ROMAN)
-                else :
-                    MkPin(self, terminal, 0, Box(pathpnts[0].x-width3/2, (pathpnts[0].y+offset), pathpnts[0].x+width3/2, (pathpnts[0].y+offset)+length3), layer2, pinlabel, layer2, length3, 'R0', 'centerLeft', Font.ROMAN)
-            
-            # encSubPath
-            dbCreatePath(self, layer2, pathpnts, width1-(2*layer2_enc))  
-            
-            # rodCreateRect
-            pin_fig = list()
-            if do_pins :
-                pin = MkPin(self, terminal, 0, fig.bbox, layer1)
-            else :
-                pin = dbCreateRect(self, layer1, fig.bbox)
-            pin_fig.append(pin)      
-            
-            #rodAlign(?alignObj, pin_fig, ?alignHandle, "centerCenter", ?refObj, fig, ?refHandle, "centerCenter")
-        else :   # path in layer2 and rectangles in layer3 (one layer path and subrectangles)
-            if not layer1 and layer3 != layer2 :
-                # rodCreatePath
-                fig = dbCreatePath(self, layer2, pathpnts, width1)
-                if pinlabel :
-                    if hor :
-                        MkPin(self, terminal, 0, Box((pathpnts[0].x+offset), pathpnts[0].y-width3/2, (pathpnts[0].x+offset)+width3, pathpnts[0].y+width3/2), layer2)
-                    else :
-                        MkPin(self, terminal, 0, Box(pathpnts[0].x-width3/2, (pathpnts[0].y+offset), pathpnts[0].x+width3/2, (pathpnts[0].y+offset)+length3), layer2)
-                    
-                # subRect
-                box = fig.getBBox()
-                if hor :
-                    box.expandDir(Direction.WEST, -offset)
-                    box.expandDir(Direction.EAST, -offset)
-                else :
-                    box.expandDir(Direction.NORTH, -offset)
-                    box.expandDir(Direction.SOUTH, -offset)
-                Rect.fillBBoxWithRects(layer3, box, width3, length3, layer3_space, layer3_space, GapStyle.DISTRIBUTE)
-                    
-                # rodCreateRect
-                pin_fig = list()
-                if do_pins :
-                    pin = MkPin(self, terminal, 0, fig.bbox, layer2)
-                else :
-                    pin = dbCreateRect(self, layer2, fig.bbox)
-                pin_fig.append(pin)
-                        
-                #rodAlign(?alignObj, pin_fig, ?alignHandle, "centerCenter", ?refObj, fig, ?refHandle, "centerCenter")
-            else :   # paths in layer 1 (one layer path)
-                if layer1 != layer2 :
-                    # rodCreatePath
-                    fig = dbCreatePath(self, layer1, pathpnts, width1)
-                    if pinlabel :
-                        if hor :
-                            MkPin(self, terminal, 0, Box((pathpnts[0].x+offset), pathpnts[0].y-width3/2, (pathpnts[0].x+offset)+width3, pathpnts[0].y+width3/2), layer1)
-                        else :
-                            MkPin(self, terminal, 0, Box(pathpnts[0].x-width3/2, (pathpnts[0].y+offset), pathpnts[0].x+width3/2, (pathpnts[0].y+offset)+length3), layer1)
-                    
-                    # rodCreateRect
-                    pin_fig = list()
-                    if do_pins :
-                        pin = MkPin(self, terminal, 0, fig.bbox, layer1)
-                    else :
-                        pin = dbCreateRect(self, layer1, fig.bbox)
-                    pin_fig.append(pin)
-
-                    #rodAlign(?alignObj, pin_fig, ?alignHandle, "centerCenter", ?refObj, fig, ?refHandle, "centerCenter")
-                    
-    return [pin_fig, fig]
-                    
-#***********************************************************************************************************************
-# MetalCont
-#***********************************************************************************************************************   
-def MetalCont(self, p1_x, p1_y, p2_x, p2_y, _layer2, _layer3, _width1, _width3, _length3, _offset, _layer3_space) :
-    pathLayer = _layer2
-    width = _width1
-    subRectLayer = _layer3
-    srect_w = _width3
-    srect_l = _length3
-    srect_o = _offset
-    srect_space = _layer3_space
-    boxRectLayer = _layer2
-    boxRectDelta = 0.0
-    
-    mlist = ulist[Rect]()
-    __w2 = width/2
-    if p1_x == p2_x :
-        x_left  = p1_x-__w2
-        x_right = p1_x+__w2
-        if p1_y < p2_y :
-            y_bot = p1_y
-            y_top = p2_y
-        else :
-            y_bot = p2_y
-            y_top = p1_y
-
-        _sw2 = srect_w/2
-        _yl = p1_x-_sw2
-        _xr = p1_x+_sw2
-        _yges = y_top-y_bot-2*srect_o
-        _nrect = floor((_yges+srect_space)/(srect_l+srect_space))
-        
-        if _nrect > 1 :    # calculate new space and do a loop
-            _rsp = (_yges-_nrect*srect_l)/(_nrect-1)
-            _yy = y_bot+srect_o
-            while _yy+srect_l <= y_top-srect_o+0.0001 :
-                id = dbCreateRect(self, subRectLayer, Box(tog(_yl), tog(_yy), tog(_xr), tog(_yy+srect_l)))
-                mlist.append(id )
-                _yy = _yy+srect_l+_rsp
-                
-        else :
-                if _nrect == 1 :  # center a single rect
-                    _ymb = (y_top+y_bot-srect_l)/2
-                    id = dbCreateRect(self, subRectLayer, Box(tog(_yl), tog(_ymb), tog(_xr), tog(_ymb+srect_l)))
-                    mlist.append(id)
-
-    else :
-        if p1_y == p2_y :
-            y_bot = p1_y-__w2
-            y_top = p1_y+__w2
-            if p1_x < p2_x :
-                x_left = p1_x
-                x_right = p2_x
-            else :
-                x_left = p2_x
-                x_right = p1_x
-                
-            _sw2 = srect_w/2
-            _yb = p1_y-_sw2 
-            _yt = p1_y+_sw2
-            _xges = x_right-x_left-2*srect_o
-            _nrect = floor((_xges+srect_space)/(srect_l+srect_space))
-
-            if _nrect > 1  :   # calculate new space and do a loop
-                _rsp = (_xges-_nrect*srect_l)/(_nrect-1)
-                _xx = x_left+srect_o
-                while _xx+srect_l <= x_right-srect_o+0.0001 :
-                    id = dbCreateRect(self, subRectLayer, Box(tog(_xx), tog(_yb), tog(_xx+srect_l), tog(_yt)))
-                    mlist.append(id)
-                    _xx = _xx+srect_l+_rsp
-                    
-            else :
-                if _nrect == 1  :  # center a single rect
-                    _xml = (x_left+x_right-srect_l)/2
-                    id = dbCreateRect(self, subRectLayer, Box(tog(_xml), tog(_yb), tog(_xml+srect_l), tog(_yt)))
-                    mlist.append(id)
-
-        else :
-            return mlist
-
-    if pathLayer != ""  :
-        id = dbCreateRect(self, pathLayer, Box(tog(x_left), tog(y_bot), tog(x_right), tog(y_top)))
-        mlist.append(id)        
-    
-    return mlist
-
-#***********************************************************************************************************************
-# DrawContArray
-#***********************************************************************************************************************   
-def DrawContArray(self, layer, bbox, size, space, over):
-    epsilon = self.techparams['epsilon1']
-    
-    bbox = bbox.fix()
-    
-    x1 = bbox.left
-    x2 = bbox.right      
-    y1 = bbox.bottom
-    y2 = bbox.top
-        
-    xanz = fix((x2-x1-2*over+space+epsilon)/(size+space))
-    yanz = fix((y2-y1-2*over+space+epsilon)/(size+space))     
-    
-    name = self.tech.name().split()[0]
-    if name == 'SG13_dev' :
-        cont_layer = 'Cont'
-        cont_dist_big = self.techparams['Cnt_b1']
-        cont_dist_big_nr = self.techparams['Cnt_b1_nr']
-                
-        # now check, if it is cont and more than 4 rows/lines
-        if layer.name==cont_layer and xanz>=cont_dist_big_nr and yanz>=cont_dist_big_nr :
-            # it has to be bigger space between contacts
-            space = cont_dist_big
-            # it has to be bigger space between contacts
-            xanz = fix((x2-x1-2*over+space+epsilon)/(size+space))
-            yanz = fix((y2-y1-2*over+space+epsilon)/(size+space))
-    
-    xmin = xanz*(size+space)-space+2*over
-    ymin = yanz*(size+space)-space+2*over
-    xoff = (x2-x1-xmin)/2
-    xoff = GridFix(xoff)
-    yoff = (y2-y1-ymin)/2
-    yoff = GridFix(yoff)
-    
-    for j in range(int(yanz)):
-        for i in range(int(xanz)):
-            dbCreateRect(self, layer, Box(x1+xoff+over+(size+space)*i, y1+yoff+over+(size+space)*j,
-                                          x1+xoff+over+(size+space)*i+size, y1+yoff+over+(size+space)*j+size))
-                    
-    return Box(x1+xoff+over, y1+yoff+over,
-               x1+xoff+over+xanz*size+(xanz-1)*space, 
-               y1+yoff+over+yanz*size+(yanz-1)*space)
-
-#***********************************************************************************************************************
-# contactArray
-#***********************************************************************************************************************
-def contactArray(self, pathLayer, contLayer, xl, yl, xh, yh, ox, oy, ws, ds):
-    eps = self.tech.getTechParams()['epsilon1']
-
-    w = xh-xl
-    h = yh-yl
-    
-    mlist = list()
-   
-    nx = floor((w-ox*2+ds)/(ws+ds)+eps)
-    if (nx <= 0) :
-        return mlist   
-    
-    dsx = 0
-    if (nx == 1) :
-        dsx = 0
-    else :
-        dsx = (w-ox*2-ws*nx)/(nx-1)
-        
-    ny = floor((h-oy*2+ds)/(ws+ds)+eps)    
-    if (ny <= 0) :
-        return mlist
-        
-    dsy = 0
-    if (ny == 1) :
-        dsy = 0    
-    else :
-        dsy = (h-oy*2-ws*ny)/(ny-1)
-    
-    x = 0
-    if (nx == 1) :
-        x = (w-ws)/2
-    else :
-        x = ox
-    
-    if pathLayer :
-        mlist.append(dbCreateRect(self, pathLayer, Box(xl, yl, xh, yh)))
-    
-    for i in range(int(nx)) :
-    #for(i=1; i<=nx; i++) {
-        y = 0
-        if ny == 1 :
-            y = (h-ws)/2        
-        else :
-            y = oy
-        
-        for j in range(int(ny)) :
-        #for(j=1; j<=ny; j++) {
-            mlist.append(dbCreateRect(self, contLayer, Box(xl+tog(x), yl+tog(y), xl+tog(x+ws), yl+tog(y+ws))))
-            y = y+ws+dsy
-            
-        x = x+ws+dsx
-    
-    if pathLayer :
-        mlist.append(dbCreateRect(self, pathLayer, Box(xl, yl, xh, yh)))
-        
-    return mlist
-
-
-#***********************************************************************************************************************
-# DrawContRowMid
-#***********************************************************************************************************************
-def DrawContRowMid(self, layer, x0, y0, x1, y1, size, space, drawMid, GRID, EPSILON):
-    IGRID = 1/GRID
-    
-    dx = 0.0
-    dy = 0.0
-    xShift = 0.0
-    yShift = 0.0
-    
-    x0 = int(x0*IGRID+EPSILON)*GRID
-    x1 = int(x1*IGRID+EPSILON)*GRID
-    y0 = int(y0*IGRID+EPSILON)*GRID
-    y1 = int(y1*IGRID+EPSILON)*GRID
-    
-    if (x1-x0 > 0.0):
-      dx = size+space
-    
-    if (x1-x0 < 0.0):
-      dx = -(size+space)
-    
-    if (y1-y0 > 0.0):
-      dy = size+space
-    
-    if (y1-y0 < 0.0):
-      dy = -(size+space)
-    
-    if (nonzero(dx) and nonzero(dy)):
-      delta = int(space*(1.0-1.0/math.sqrt(2.0)-0.01)*IGRID-EPSILON)*GRID
-      if (dx > 0.0):
-        dx = dx-delta
-      else:
-        dx = dx+delta
-
-      if (dy > 0.0):
-        dy = dy-delta
-      else:
-        dy = dy+delta
-    
-    xofs = 0.0
-    yofs = 0.0
-    
-    if ((dy > 0.0) and iszero(dx)):
-      xofs = int(-size/2.0*IGRID+EPSILON)*GRID
-      yofs = 0.0
-      xShift = 0.0
-      yShift = 1
-    
-    if ((dx > 0.0) and (dy>0.0)):
-      xofs = 0.0
-      yofs = 0.0
-      xShift = 1.0
-      yShift = 1.0
-    
-    if ((dx > 0.0) and iszero(dy)):
-      xofs = 0.0
-      yofs = int(-size/2.0*IGRID+EPSILON)*GRID
-      xShift = 1.0
-      yShift = 0.0
-    
-    if ((dx > 0.0) and (dy < 0.0)):
-      xofs = 0.0
-      yofs = int(-size*IGRID+EPSILON)*GRID
-      xShift = 1.0
-      yShift = -1.0
-    
-    if ((dy < 0.0) and iszero(dx)):
-      xofs = int(-size/2.0*IGRID+EPSILON)*GRID
-      yofs = -size
-      xShift = 0.0
-      yShift = -1.0
-    
-    if ((dy < 0.0) and (dx < 0.0)):
-      xofs = -size
-      yofs = -size
-      xShift = -1.0
-      yShift = -1.0
-      
-    if ((dx < 0.0) and iszero (dy)):
-      xofs = -size # -fix(size/3.0*IGRID)*GRID
-      yofs = int(-size/2.0*IGRID+EPSILON)*GRID
-      xShift = -1.0
-      yShift = 0.0
-      
-    if ((dx < 0.0) and (dy > 0.0)):
-      xofs = -size
-      yofs = 0.0
-      xShift = -1.0
-      yShift = 1.0
-    
-    len = max (abs(x1-x0), abs(y1-y0))
-    orglen = len
-    len = len-space
-    sstep = max(abs(dx), abs(dy))
-    anz = int((len+(sstep-size)+EPSILON)/sstep)
-    ovhd = orglen - (anz-1)*sstep - size
-        
-    if drawMid:
-      x0 = Snap(x0+(xShift*ovhd/2))
-      y0 = Snap(y0+(yShift*ovhd/2))
-    
-    for i in range (anz):
-      dbCreateRect(self, layer, Box(xofs+x0+dx*i, yofs+y0+dy*i, xofs+x0+dx*i+size, yofs+y0+dy*i+size))
-
-#***********************************************************************************************************************
-# myBox: safe version of Box that works with x2,y2 smaller also
-#***********************************************************************************************************************
-def myBox(x1,y1,x2,y2):
-    if x1<x2:
-        xmin=x1
-        xmax=x2
-    else:
-        xmin=x2
-        xmax=x1
-  
-    if y1<y2:
-        ymin=y1
-        ymax=y2
-    else:
-        ymin=y2
-        ymax=y1
-  
-    return Box(xmin,ymin,xmax,ymax)
- 
-#***********************************************************************************************************************
-# ResizeBBox
-#*********************************************************************************************************************** 
-def ResizeBBox(bBox, value):
-    return bBox.expand(value) 
-
-#***********************************************************************************************************************
-# dbReplaceProp
-#***********************************************************************************************************************
-def dbReplaceProp(self, name, value):
-    self.props[name] = value
-
-#***********************************************************************************************************************
-# dbDeleteObject
-#*********************************************************************************************************************** 
-def dbDeleteObject(self):
-    self.destroy()
-    
-#***********************************************************************************************************************
-# DrawFillers
-#
-# procedure filler in given area
-## arguments:
-## - xl,yl,xh,yh   (rectangle to be filled)
-## - ws,hs (filler width, height)
-## - dx,dy (space between fillers)
-#*********************************************************************************************************************** 
-def DrawFillers(self, layer, xl, yl, xh, yh, ws, hs, dx, dy, dir, offset, retlist):
-    #Rect.fillBBoxWithRects(layer, Box(xl, yl, xh, yh), ws, hs, dx, dy)
-    #return 
-    
-    if type(layer) == str :
-        layer = Layer(layer)
-    
-    idlist = list()
-    W = xh-xl
-    H = yh-yl
-    nry = floor((H+dy)/(hs+dy))
-    
-    if nry > 1 : # vertical space between fillers
-        hns = (H-nry*hs)/(nry-1)
-    else :
-        hns = 0.
-        
-    nrx = floor((W+dx)/(ws+dx))
-    if nrx > 1 :    # horizontal space between fillers
-        wns = (W-nrx*ws)/(nrx-1)
-    else :
-        wns = 0.
-    
-    if dir == 'u' :
-        if nrx >= nry :
-            dir = 'h'
-        else :
-            dir = 'v'
-            
-    if dir == 'h'  :  # row-wise
-        if offset > 0 :
-            off = (ws+dx)*0.5
-        else :
-            off = 0.
-            
-        y = yl
-        for i in range(1, int(nry)+1) :
-            togy = tog(y)
-            x = xl
-            nr = nrx
-            if offset != 0 and evenp(i+offset-1) and nr > 1 :
-                nr = nr-1
-                x = x+off
-                
-            for j in range(1, int(nr)+1) :
-                togx = tog(x)
-                id = dbCreateRect(self, layer, Box(togx, togy, togx+ws, togy+hs))
-                if retlist :
-                    cons(idlist, id)
-                x = x+wns+ws
-            
-            y = y+hns+hs
-        
-    else : # column-wise
-        if offset > 0 :
-            off = (hs+dy)*0.5
-        else :
-            0
-        x = xl
-        for i in range(1, int(nrx)+1) :
-            togx = tog(x)
-            y = yl
-            nr = nry
-            if offset != 0 and evenp(i+offset-1) :
-                nr = nr-1
-                y = y+off
-                
-            for j in range(1, int(nr)+1) :
-                togy = tog(y)
-                id = dbCreateRect(self, layer, Box(togx, togy, togx+ws, togy+hs))
-                if retlist :
-                    cons(idlist, id)
-                y = y+hns+hs
-
-            x = x+wns+ws
-
-    # if
-    
-    return idlist
-    
-#***********************************************************************************************************************
-# generateCorner
-#*********************************************************************************************************************** 
-def generateCorner(self, corner_startx, corner_starty, corner_width, corner_length, corner_steps, corner_end, offset, layer):
-    item_list = list()
-    for cnt in range(corner_steps) :
-        rect = dbCreateRect(self, Layer(layer, 'drawing'), Box(corner_startx - corner_width * (cnt + 1), corner_starty + offset + (corner_length - corner_width) * cnt,
-                                                                   corner_startx - corner_width * cnt, corner_starty+corner_length + offset  + (corner_length-corner_width) * cnt))
-        cons(item_list, rect)
-    
-    rect = dbCreateRect(self, Layer(layer, 'drawing'), Box(corner_startx - corner_width * (corner_steps + 1), corner_starty + offset  + (corner_length - corner_width) * corner_steps,
-                                                               corner_startx - corner_width * corner_steps, corner_end))
-    cons(item_list, rect)
-    
-    return item_list
-    
-#***********************************************************************************************************************
-# combineLayerAndDelete
-#*********************************************************************************************************************** 
-def combineLayerAndDelete(self, item_list, groupId, layer):   
-    
-    shapes = dbLayerOrList(Layer(layer, 'drawing'), item_list)
-    
-    size = len(shapes.getComps())
-    for i in range(size) :
-        cons(groupId, shapes.getComp(i))
-    
-    for item in item_list :
-        item.destroy()
-
-    return groupId
-
-#***********************************************************************************************************************
-# ihpCopyFig
-#*********************************************************************************************************************** 
-def ihpCopyFig(groupId, pnt, rot):
-    newList = list()
-    for item in groupId :
-        cons(newList, dbCopyShape(item, pnt, rot))
-
-    return newList
-
-#**************************************************************************************************************
-# bondpadOctagonPoints
-#**************************************************************************************************************
-def bondpadOctagonPoints(rx, ry, off):
-    return PointList([Point(-rx    , -ry+off), Point(-rx    , ry-off ),
-                      Point(-rx+off, ry     ), Point(rx-off , ry     ), 
-                      Point(rx     , ry-off ), Point(rx     , -ry+off), 
-                      Point(rx-off , -ry    ), Point(-rx+off, -ry    )])
-               
-#**************************************************************************************************************
-# bondpadOctagonRingPoints
-#**************************************************************************************************************
-def bondpadOctagonRingPoints(rx, ry, off, rxi, ryi, offi):
-    return PointList([Point(-rx      , 0        ), Point(-rx      , ry-off   ), 
-                      Point(-rx+off  , ry       ), Point(rx-off   , ry       ), 
-                      Point(rx       , ry-off   ), Point(rx       , -ry+off  ), 
-                      Point(rx-off   , -ry      ), Point(-rx+off  , -ry      ), 
-                      Point(-rx      , -ry+off  ), Point(-rx      , 0        ), 
-                      Point(-rxi     , 0        ), Point(-rxi     , -ryi+offi), 
-                      Point(-rxi+offi, -ryi     ), Point(rxi-offi , -ryi     ), 
-                      Point(rxi      , -ryi+offi), Point(rxi      , ryi-offi ), 
-                      Point(rxi-offi , ryi      ), Point(-rxi+offi, ryi      ), 
-                      Point(-rxi     , ryi-offi ), Point(-rxi     , 0        )])
-               
-#**************************************************************************************************************
-# bondpadStretchedCircle
-#**************************************************************************************************************
-def bondpadStretchedCircle(self, layer, rx, ry, grid):
-    if type(layer) == str :
-        layer = Layer(layer)
-        
-    if rx == ry :
-        id1 = dbCreateEllipse(self, layer, Box(-rx, -rx, rx, rx))
-        id  = dbConvertEllipseToPolygon(self, id1, 64, grid)
-        return id
-        
-    if rx > ry :
-        id1 = dbCreateEllipse(self, layer, Box(-rx, -ry -rx+ry*2, ry))
-        id2 = dbCreateEllipse(self, layer, Box(rx-ry*2, -ry, rx, ry))
-        id3 = dbCreateRect(self, layer, Box(ry-rx, -ry, rx-ry, ry))
-        id = dbLayerOrList(layer, [id1, id2, id3])
-        dbDeleteObject(id1)
-        dbDeleteObject(id2)
-        dbDeleteObject(id3)
-        return id[0]
-        
-    id1 = dbCreateEllipse(self, layer, Box(-rx, -ry, rx, -ry+rx*2))
-    id2 = dbCreateEllipse(self, layer, Box(-rx, ry-rx*2, rx, ry))
-    id3 = dbCreateRect(self, layer, Box(-rx, rx-ry, rx, ry-rx))
-    id = dbLayerOr(layer, [id1, id2, id3])
-    dbDeleteObject(id1)
-    dbDeleteObject(id2)
-    dbDeleteObject(id3)
-    
-    return id[0]
-
-#***********************************************************************************************************************
-# geoMerge
-#*********************************************************************************************************************** 
-def geoMerge(self, layer) :
-    if type(layer) == str :
-        layer = Layer(layer)
-        
-    idlst = list()
-    shapes = self.getLeafComps()
-    for id in shapes :
-        if id.layer == layer :
-            idlst.append(id)
-      
-    if idlst :
-        dbLayerOrList(layer, idlst)
-        for id in idlst :
-            id.destroy()
-
-#***********************************************************************************************************************
-# geoRing
-#*********************************************************************************************************************** 
-def geoRing(self, layer, rl, rr, rb, rt, rw, rh):
-    if type(layer) == str :
-        layer = Layer(layer)
-        
-    dbCreatePolygon(self, layer, PointList([Point(rl-rw, rb-rw), Point(rr+rw, rb-rw), Point(rr+rw, rt+rh), Point(rl-rw, rt+rh), Point(rl-rw, rb),
-                                            Point(rl, rb), Point(rl, rt), Point(rr, rt), Point(rr, rb), Point(rl-rw, rb), Point(rl-rw, rb-rw)]))
-                                            
-#**************************************************************************************************************
-# ihpGetRectHash
-#**************************************************************************************************************
-def ihpGetRectHash(g_value) :
-    mlist = list()
-    mlist.append(g_value)
-    mlist.append(10001)
-    return mlist
-    
-#**************************************************************************************************************
-# ihpGetAskewHash
-#**************************************************************************************************************
-def ihpGetAskewHash(g_value) :
-    mlist = list()
-    mlist.append(g_value)
-    mlist.append(10002)
-    return mlist
-    
-#**************************************************************************************************************
-# ihpGetOptionPair
-#**************************************************************************************************************
-def ihpGetOptionPair(g_index, g_options) :
-    pair = list()
-    iterIndex = 0
-    
-    for i in range(fix(listlen(g_options))) :
-        if iterIndex == g_index :
-            if (i+1) < listlen(g_options) :
-                pair = pylist(nth(i, g_options), nth(i+1, g_options))
-                return pair
-        
-        if isOdd(i) :
-            iterIndex = iterIndex + 1
- 
-    return pair
-
-#**************************************************************************************************************
-# ihpIsRectOpt
-#**************************************************************************************************************
-def ihpIsRectOpt(g_index, g_options) :
-    rValue = 0
-    if (g_options != 0) and (g_index < listlen(g_options)) :
-        testOpt = ihpGetOptionPair(g_index, g_options)
-        if listlen(testOpt) == 2 :
-            testHash = nth(1, testOpt);
-            hashValue = nth(1, ihpGetRectHash(0));
-            
-            if testHash == hashValue :
-                rValue = 1;
-        
-    
-    
-    return rValue; 
-    
-#**************************************************************************************************************
-# ihpIsAskewOpt
-#**************************************************************************************************************
-def ihpIsAskewOpt(g_index, g_options) :
-    rValue = 0
-    if (g_options != 0) and (g_index < listlen(g_options)) :
-        testOpt = ihpGetOptionPair(g_index, g_options)
-        if listlen(testOpt) == 2 :
-            testHash = nth(1, testOpt);
-            hashValue = nth(1, ihpGetAskewHash(0));
-            
-            if testHash == hashValue :
-                rValue = 1;
-        
-    
-    
-    return rValue;    
-
-#**************************************************************************************************************
-# ihpGetDrawOptValue
-#**************************************************************************************************************
-def ihpGetDrawOptValue(g_index, g_drwOptions) :
-    rValue = 0
-    
-    if g_index < listlen(g_drwOptions) :
-        testOpt = ihpGetOptionPair(g_index, g_drwOptions);
-        if listlen(testOpt) == 2 :
-            rValue = nth(0, testOpt);
-    
-    return(rValue);
-
-#**************************************************************************************************************
-# ihpGetSideSkewDrawingOptions
-#**************************************************************************************************************
-def ihpGetSideSkewDrawingOptions(g_value) :
-    return pylist(ihpGetAskewHash(g_value), 
-                  ihpGetRectHash(0), ihpGetRectHash(0), 
-                  ihpGetAskewHash(g_value)); 
-
-#**************************************************************************************************************
-# ihpGetLeftSkewDrawingOptions
-#**************************************************************************************************************
-def ihpGetLeftSkewDrawingOptions(g_value) :
-    return pylist(ihpGetRectHash(0),
-                  ihpGetRectHash(0), ihpGetRectHash(0), 
-                  ihpGetAskewHash(g_value)); 
-
-#**************************************************************************************************************
-# ihpGetInnerSkewDrawingOptions
-#**************************************************************************************************************
-def ihpGetInnerSkewDrawingOptions(g_value) :
-    return pylist(ihpGetRectHash(0), 
-                  ihpGetAskewHash(g_value), ihpGetAskewHash(g_value), 
-                  ihpGetRectHash(0));
-                
-#**************************************************************************************************************
-# ihpGetNormalizedList
-#**************************************************************************************************************
-def ihpGetNormalizedList(theList) :
-    if type(theList) is PointList :
-        return theList
-    
-    normalized = list()
-    
-    if is_list(theList) :
-        for i in range(fix(listlen(theList))) :
-            item = nth(i, theList)
-            
-            itemList = ihpGetNormalizedList(item)
-            for j in range(fix(listlen(itemList))) :
-                elem = nth(j, itemList)
-                if listlen(normalized) :
-                    normalized = cons(normalized, pylist(elem))
-                else :
-                    normalized = list()
-                    normalized.append(elem)
-            
-        
-    else :
-        if listlen(normalized) :
-            normalized = append(normalized, list(theList))
-        else :
-            normalized = list()
-            normalized.append(theList)
-        
-    return normalized
-
-#**************************************************************************************************************
-# ihpGetShapeBBox
-#**************************************************************************************************************
-def ihpGetShapeBBox(shapeId) :
-    shapeList = ihpGetNormalizedList(shapeId)
-    
-    bbox = Box(0, 0, 0, 0)
-    
-    if is_list(shapeList) == 0 :
-        return bbox
-        
-    if listlen(shapeList) == 0 :
-        return bbox
-    
-    #initialize componetnts first
-    currentId = nth(0, shapeList);
-    rect = currentId.getBBox()
-    
-    x1 = rect.getLeft()
-    x2 = rect.getRight()       
-    y1 = rect.getBottom()
-    y2 = rect.getTop()
-    
-    # compute min and max Point1(X1, Y1) and Point2(X2, Y2)
-    for i in range(fix(listlen(shapeList))) :
-        currentId = nth(i, shapeList)
-        
-        crect = currentId.getBBox()
-        cx1 = crect.getLeft()
-        cx2 = crect.getRight()       
-        cy1 = crect.getBottom()
-        cy2 = crect.getTop()
-        
-        x1 = min2(x1, cx1)
-        y1 = min2(y1, cy1)
-        x2 = max2(x2, cx2)
-        y2 = max2(y2, cy2)
-    
-    return Box(x1, y1, x2, y2)
-
-#***********************************************************************************************************************
-# ihpCreatedExtendedShape
-#*********************************************************************************************************************** 
-def ihpCreatedExtendedShape(g_cvId, g_layerId, g_shapeId, g_extend = None, g_options = None) :
-    options = g_options
-    if g_options == None :
-        options = list(ihpGetRectHash(0))
-    
-    shapeList = ihpGetNormalizedList(g_shapeId)
-    
-    theShapes = list();
-    for i in range(fix(listlen(shapeList))) :
-        shapeId = nth(i, shapeList);        
-        theShapes = cons(theShapes, pylist(ihpCreateExtendedShapeByPoints(g_cvId, g_layerId, shapeId, g_extend, g_options)));
-    
-    return theShapes
-
-#**************************************************************************************************************
-# ihpCreateExtendedShapeByPoints
-#**************************************************************************************************************
-def ihpCreateExtendedShapeByPoints(g_cvId, g_layerId, g_shapeId, g_extend, g_drawOptions) :
-    points = PointList()
-    
-    bbox = ihpGetShapeBBox(g_shapeId)
-    
-    x1 = nth(0, bbox)
-    y1 = nth(1, bbox)
-    x2 = nth(2, bbox)
-    y2 = nth(3, bbox)
-    
-    if type(g_extend) is list :
-        left = nth(2, g_extend)
-        bottom = nth(1, g_extend)
-        right = nth(3, g_extend)
-        top = nth(0, g_extend)
-    if type(g_extend) is Box :
-        left = g_extend.getRight()
-        bottom = g_extend.getBottom()
-        right = g_extend.getTop()
-        top = g_extend.getLeft()
-    else :
-        left = g_extend
-        bottom = g_extend
-        right = g_extend
-        top = g_extend
-    
-    # extend the requested shape
-    x1 = x1 - left;
-    y1 = y1 - bottom;
-    x2 = x2 + right;
-    y2 = y2 + top;
-    
-    optionList = ihpGetNormalizedList(g_drawOptions)
-    
-    if ihpIsRectOpt(0, optionList) == 1 and ihpIsRectOpt(1, optionList) == 1 and ihpIsRectOpt(2, optionList) == 1 and ihpIsRectOpt(3, optionList) == 1 :
-        points.append(Point(x1, y1))
-        points.append(Point(x2, y2))
-    else :
-        if ihpIsAskewOpt(0, optionList) == 1 :
-            points.append(Point(x1 + ihpGetDrawOptValue(0, optionList), y1))
-            points.append(Point(x1, y1 + ihpGetDrawOptValue(0, optionList)))
-        else :
-            points.append(Point(x1, y1))
-            
-        if ihpIsAskewOpt(1, optionList) == 1 :
-            points.append(Point(x1, y2 - ihpGetDrawOptValue(1, optionList)))
-            points.append(Point(x1 + ihpGetDrawOptValue(1, optionList), y2))
-        else :
-            points.append(Point(x1, y2))
-            
-        if ihpIsAskewOpt(2, optionList) == 1 :
-            points.append(Point(x2 - ihpGetDrawOptValue(2, optionList), y2))
-            points.append(Point(x2, y2 - ihpGetDrawOptValue(2, optionList)))
-        else :
-            points.append(Point(x2, y2))
-        
-        if ihpIsAskewOpt(3, optionList) == 1 :
-            points.append(Point(x2, y1 + ihpGetDrawOptValue(3, optionList)))
-            points.append(Point(x2 - ihpGetDrawOptValue(3, optionList), y1))
-        else :
-            points.append(Point(x2, y1));
-                
-    return dbCreatePolygon(g_cvId, g_layerId, ihpGetNormalizedList(points))
-
-#**************************************************************************************************************
-# ihpSurroundShapeWithRing
-#**************************************************************************************************************
-def ihpSurroundShapeWithRing(g_cvId, g_layerId, g_shapeId, g_extend, g_ringWidth) :
-    left = g_extend
-    bottom = g_extend
-    right = g_extend
-    top = g_extend
-    
-    if type(g_extend) is list :
-        left = nth(2, g_extend)
-        bottom = nth(1, g_extend)
-        right = nth(3, g_extend)
-        top = nth(0, g_extend)
-    if type(g_extend) is Box :
-        left = g_extend.getRight()
-        bottom = g_extend.getBottom()
-        right = g_extend.getTop()
-        top = g_extend.getLeft()
-    else :
-        left = g_extend
-        bottom = g_extend
-        right = g_extend
-        top = g_extend
-    
-    shape1 = ihpCreatedExtendedShape(g_cvId, g_layerId, g_shapeId, Box(top, bottom, left, right))
-    shape2 = ihpCreatedExtendedShape(g_cvId, g_layerId, g_shapeId, Box(top + g_ringWidth, bottom + g_ringWidth, 
-                                                                       left + g_ringWidth, right + g_ringWidth))
-    hallo = dbLayerXor(g_layerId, car(shape1), car(shape2))
-    
-    dbDeleteObject(car(shape1));
-    dbDeleteObject(car(shape2));
-    
-    return(hallo.getComp(0));
-
-#**************************************************************************************************************
-# ihpCreateContactArrayInShape
-#**************************************************************************************************************
-def ihpCreateContactArrayInShape(g_cvId, g_layer, g_shapeId, g_baseShape, g_size, g_rect, g_drcMinOverlap = None, g_drcMinSpace = None) :
-        
-    if g_drcMinOverlap == None :
-        g_drcMinOverlap = 0.07
-    
-    if g_drcMinSpace == None :
-        g_drcMinSpace = 0.18
-    
-    if g_baseShape != None :
-        bbox = ihpGetShapeBBox(g_baseShape)      
-        width = abs(nth(0, bbox) - nth(2, bbox))
-        height = abs(nth(1, bbox) - nth(3, bbox))
-    
-    if type(g_size) is list :
-        width = nth(0, g_size)
-        height = nth(1, g_size)
-
-    top = g_drcMinOverlap;
-    bottom = g_drcMinOverlap;
-    left = g_drcMinOverlap;
-    right = g_drcMinOverlap;    
-    xspace = g_drcMinSpace;
-    yspace = g_drcMinSpace;
-    
-    if type(g_drcMinSpace) is list :
-        xspace = car(g_drcMinSpace)
-        yspace = cadr(g_drcMinSpace)
-    
-    if type(g_drcMinOverlap) is list :
-        top = car(g_drcMinOverlap)
-        bottom = cadr(g_drcMinOverlap)
-        left = caddr(g_drcMinOverlap)
-        right = cadddr(g_drcMinOverlap)
-    
-    if type(g_shapeId) != list :
-        g_shapeId = list(g_shapeId)
-    
-    snapGrid = g_cvId.tech.getGridResolution()
-    
-    contactList = list()
-    for i in range(fix(listlen(g_shapeId))) :
-        shape = nth(i, g_shapeId)
-        
-        if type(shape) == Polygon :
-            continue
-                
-        bbox = ihpGetShapeBBox(shape)         
-        rectWidth = abs(nth(2, bbox) - nth(0, bbox) - left - right)
-        rectHeight = abs(nth(3, bbox) - nth(1, bbox) - top - bottom)
-        
-        center = pylist((nth(0, bbox) + left + nth(2, bbox) - right)*0.5, (nth(0, bbox) + bottom + nth(3, bbox) - top)*0.5)
-    
-        columns = fix((rectWidth+xspace)/(1.0*(width + xspace)))
-        rows = fix((rectHeight+yspace)/(1.0*(height + yspace)))
-    
-        if columns > 0 and rows > 0 :            
-            contacts = ihpPerformContactPlacementInShape(g_cvId, g_layer, shape, pylist(columns, rows), 
-                                                         pylist(width, height, xspace, yspace, left, bottom, center, snapGrid));
-            contactList = append(contactList, contacts);
-    
-    return contactList
-
-#**************************************************************************************************************
-# ihpPerformContactPlacementInShape
-#**************************************************************************************************************
-def ihpPerformContactPlacementInShape(g_cvId, g_layer, g_shapeId, g_table, g_dimentions) :
-    
-    contactList = list()
-    
-    if type(g_table) != list or listlen(g_table) != 2 :
-        return contactList
-    
-    if type(g_dimentions) != list or listlen(g_dimentions) != 7 :
-        return contactList
-    
-    columns = nth(0, g_table)
-    rows = nth(1, g_table)
-    
-    width = nth(0, g_dimentions)
-    height = nth(1, g_dimentions)
-    xspace = nth(2, g_dimentions)
-    yspace = nth(3, g_dimentions)      
-    left = nth(4, g_dimentions)
-    bottom = nth(5, g_dimentions)
-    center = nth(6, g_dimentions)
-    snapGrid = nth(7, g_dimentions)
-    
-    bbox = ihpGetShapeBBox(shape);
-    
-    xLoc = car(center)-((columns*(width+xspace)-xspace)*0.5);
-    xLoc = fix(xLoc/snapGrid)*snapGrid;
-    if xLoc < (nth(0, bbox) + left) :
-        xLoc = xLoc+snapGrid
-        xLoc = fix(xLoc/snapGrid)*snapGrid
-    
-    yLoc = cadr(center)-((rows*(height+yspace)-yspace)*0.5)
-    yLoc = fix(yLoc/snapGrid)*snapGrid
-    
-    if yLoc < (nth(1, bbox) + bottom) :
-        yLoc = yLoc+snapGrid
-        yLoc = fix(yLoc/snapGrid)*snapGrid
-    
-    for i in range(fix(listlen(rows-1))) :
-        for j in range(fix(listlen(columns-1))) :
-            xOrig = xLoc + (j * (width + xspace))
-            xOrig = fix(xOrig / snapGrid)* snapGrid
-            yOrig = yLoc + (i * (height + yspace))
-            yOrig = fix(yOrig / snapGrid)* snapGrid
-            
-            contactId = dbCreateRect(cvid, layer, Box(xOrig, yOrig, (xOrig + width), (yOrig + height)))
-            contactList = append(newrects, list(contactId))
-    
-    return(contactList)
diff --git a/ihp-sg13g2/libs.tech/pycell/nmos_code.py b/ihp-sg13g2/libs.tech/pycell/nmos_code.py
deleted file mode 100644
index 0c3c798d..00000000
--- a/ihp-sg13g2/libs.tech/pycell/nmos_code.py
+++ /dev/null
@@ -1,259 +0,0 @@
-########################################################################
-#
-# Copyright 2023 IHP PDK Authors
-# 
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-# 
-#    https://www.apache.org/licenses/LICENSE-2.0
-# 
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-########################################################################
-__version__ = "$Revision: #3 $"
-
-from cni.dlo import *
-from thermal import *
-from geometry import *
-from utility_functions import *
-
-import math
-
-class nmos(DloGen):
-
-    @classmethod
-    def defineParamSpecs(cls, specs):
-        techparams = specs.tech.getTechParams()
-        
-        CDFVersion = techparams['CDFVersion']
-        model      = 'sg13_lv_nmos'
-        defL       = techparams['nmos_defL']
-        defW       = techparams['nmos_defW']
-        defNG      = techparams['nmos_defNG']
-        minL       = techparams['nmos_minL']
-        minW       = techparams['nmos_minW']
-        
-        specs('cdf_version', CDFVersion, 'CDF Version')
-        specs('Display', 'Selected', 'Display', ChoiceConstraint(['All', 'Selected']))
-        specs('model', model, 'Model name')
-        
-        specs('w' ,   defW, 'Width')
-        specs('ws',   eng_string(Numeric(defW)/Numeric(defNG)), 'SingleWidth')
-        specs('l' ,   defL, 'Length')
-        specs('Wmin', minW, 'Wmin')
-        specs('Lmin', minL, 'Lmin')
-        specs('ng',   defNG, 'Number of Gates')
-        
-        specs('m', '1', 'Multiplier')
-        specs('trise', '', 'Temp rise from ambient')
-
-    def setupParams(self, params):
-        # process parameter values entered by user
-        self.w = Numeric(params['w'])*1e6
-        self.ng = Numeric(params['ng'])
-        self.l = Numeric(params['l'])*1e6
-
-    def genLayout(self):
-        w = self.w
-        ng = self.ng
-        l = self.l
-
-        techparams = self.tech.getTechParams()
-        self.techparams = techparams
-        self.epsilon = techparams['epsilon1']
-        
-        Cell = self.__class__.__name__
-        typ = 'N'
-        hv = False
-        
-        epsilon = techparams['epsilon1']
-        #grid = techGetMfgGridResolution(tfId)
-        grid = techparams['grid']
-        metall_layer = Layer('Metal1')
-        metall_layer_pin = Layer('Metal1', 'pin')
-        ndiff_layer = Layer('Activ')
-        pdiff_layer = Layer('Activ')
-        pdiffx_layer = Layer('pSD')
-        poly_layer = Layer('GatPoly')
-        poly_layer_pin = Layer('GatPoly', 'pin')
-        well_layer = Layer('NWell')
-        well2_layer = Layer('nBuLay')
-        textlayer = Layer('TEXT')
-        locint_layer = Layer('Cont')
-        tgo_layer = Layer('ThickGateOx')
-        endcap = techparams['M1_c1']
-        cont_size = techparams['Cnt_a']
-        cont_dist = techparams['Cnt_b']
-        cont_Activ_overRec = techparams['Cnt_c']
-        cont_metall_over = techparams['M1_c']
-        psd_pActiv_over = techparams['pSD_c']
-        nwell_pActiv_over = techparams['NW_c']
-        #minNwellForNBuLay = techparams['NW_g']
-        well2_over = techparams['NW_NBL']
-        gatpoly_Activ_over = techparams['Gat_c']
-        gatpoly_cont_dist = techparams['Cnt_f']
-        smallw_gatpoly_cont_dist = techparams['Cnt_c']
-        psd_PFET_over = techparams['pSD_i']
-        pdiffx_poly_over_orth = 0.48
-        
-        wmin = Numeric(techparams['nmos_minW'])
-        lmin = Numeric(techparams['nmos_minL'])
-        
-        contActMin = 2*techparams['Cnt_c']+techparams['Cnt_a']
-        thGateOxGat = techparams['TGO_c']
-        thGateOxAct = techparams['TGO_a']
-        
-        dbReplaceProp(self, "pin#", 5)
-        
-        ng = math.floor(Numeric(ng)+epsilon)
-        
-        w = w/ng
-        w = GridFix(w)
-        l = GridFix(l)
-        
-        if endcap < cont_metall_over :
-            endcap = cont_metall_over
-            
-        if hv :
-            labelhv = 'HV'
-        else :
-            labelhv = ''
-            
-        smallMetAdd = cont_size + (2*cont_metall_over)
-        if (w < contActMin-epsilon) :
-            gatpoly_cont_dist = smallw_gatpoly_cont_dist
-            
-        xdiff_beg = 0
-        ydiff_beg = 0
-        ydiff_end = w
-        if w < wmin-epsilon :
-            hiGetAttention()
-            print('Width < '+str(wmin))
-            w = wmin
-            
-        if l < lmin-epsilon :
-            hiGetAttention()
-            print('Length < '+str(lmin))
-            l = lmin
-            
-        if ng < 1 :
-            hiGetAttention()
-            print('Minimum one finger')
-            ng = 1
-            
-        xanz = fix((w-2*cont_Activ_overRec+cont_dist)/(cont_size+cont_dist)+epsilon)
-        w1 = xanz*(cont_size+cont_dist)-cont_dist+cont_Activ_overRec+cont_Activ_overRec
-        xoffset = (w-w1)/2
-        xoffset = GridFix(xoffset)
-        diffoffset = 0
-        if w < contActMin :
-            xoffset = 0
-            diffoffset = (contActMin-w)/2
-            diffoffset = Snap(diffoffset)
-            
-        # get the number of contacts
-        lcon = w-2*cont_Activ_overRec
-        distc = cont_size+cont_dist
-        ncont = fix((w-2*cont_Activ_overRec+cont_dist)/(cont_size+cont_dist)+epsilon)
-        if zerop(ncont) :
-            ncont = 1
-            
-        diff_cont_offset = GridFix((w-2*cont_Activ_overRec-ncont*cont_size-(ncont-1)*cont_dist)/2)
-        
-        # draw the cont row
-        xcont_beg = xdiff_beg+cont_Activ_overRec
-        ycont_beg = ydiff_beg+cont_Activ_overRec
-        ycont_cnt = ycont_beg+diffoffset+diff_cont_offset
-        xcont_end = xcont_beg+cont_size
-        
-        # draw Metal rect
-        # calculate bot and top cont position
-        yMet1 = ycont_cnt-endcap
-        yMet2 = ycont_cnt+cont_size+( ncont-1)*distc +endcap
-        # is metal1 overlapping Activ?
-        yMet1 = min(yMet1, ydiff_beg+diffoffset)
-        yMet2 = max(yMet2, ydiff_end+diffoffset)
-        dbCreateRect(self, metall_layer, Box(xcont_beg-cont_metall_over, yMet1, xcont_end+cont_metall_over, yMet2))
-        
-        # draw contacts
-        # LI and Metall
-        contactArray(self, 0, locint_layer, xcont_beg, ydiff_beg, xcont_end, ydiff_end+diffoffset*2, 0, cont_Activ_overRec, cont_size, cont_dist)
-        
-        if w > contActMin : # smallW
-            MkPin(self, 'S', 3, Box(xcont_beg-cont_metall_over, yMet1, xcont_end+cont_metall_over, yMet2), metall_layer_pin)
-        else :
-            MkPin(self, 'S', 3, Box(xcont_beg-cont_metall_over, yMet1, xcont_end+cont_metall_over, yMet2), metall_layer_pin)
-            
-        if typ == 'N' :
-            dbCreateRect(self, ndiff_layer, Box(xcont_beg-cont_Activ_overRec, ycont_beg-cont_Activ_overRec, xcont_end+cont_Activ_overRec, ycont_beg+cont_size+cont_Activ_overRec))
-        else :
-            dbCreateRect(self, pdiff_layer, Box(xcont_beg-cont_Activ_overRec, ycont_beg-cont_Activ_overRec, xcont_end+cont_Activ_overRec, ycont_beg+cont_size+cont_Activ_overRec))
-            
-        for i in range(int(ng)) :
-            # draw the poly line
-            xpoly_beg = xcont_end+gatpoly_cont_dist
-            ypoly_beg = ydiff_beg-gatpoly_Activ_over
-            xpoly_end = xpoly_beg+l
-            ypoly_end = ydiff_end+gatpoly_Activ_over
-            dbCreateRect(self, poly_layer, Box(xpoly_beg, ypoly_beg+diffoffset, xpoly_end, ypoly_end+diffoffset))
-            
-            ihpAddThermalMosLayer(self, Box(xpoly_beg, ypoly_beg+diffoffset, xpoly_end, ypoly_end+diffoffset), True, Cell)
-            
-            if i ==  0 :
-                dbCreateLabel(self, Layer('TEXT', 'drawing'), Point((xpoly_beg+xpoly_end)/2, (ypoly_beg+ypoly_end)/2+diffoffset), 'nmos'+labelhv, 'centerCenter', 'R90', Font.EURO_STYLE, 0.09)
-                
-            if zerop(i) :
-                MkPin(self, 'G', 2, Box(xpoly_beg, ypoly_beg+diffoffset, xpoly_end, ypoly_end+diffoffset), poly_layer_pin)
-            
-            # for every gate    
-            if typ == 'P' :
-                dbCreateRect(self, pdiffx_layer, Box(xpoly_beg-pdiffx_poly_over_orth, ypoly_beg-psd_PFET_over+gatpoly_Activ_over+diffoffset, xpoly_end+pdiffx_poly_over_orth, ypoly_end+psd_PFET_over-gatpoly_Activ_over+diffoffset))
-                
-            # draw the second cont row
-            xcont_beg = xpoly_end+gatpoly_cont_dist
-            ycont_beg = ydiff_beg+cont_Activ_overRec
-            ycont_cnt = ycont_beg+diffoffset+diff_cont_offset
-            xcont_end = xcont_beg+cont_size
-            
-            dbCreateRect(self, metall_layer, Box(xcont_beg-cont_metall_over, yMet1, xcont_end+cont_metall_over, yMet2))
-            
-            # draw contacts
-            # LI and Metall
-            contactArray(self, 0, locint_layer, xcont_beg, ydiff_beg, xcont_end, ydiff_end+diffoffset*2, 0, cont_Activ_overRec, cont_size, cont_dist)
-            
-            if zerop(i) :
-                if (w > contActMin) :
-                    MkPin(self, 'D', 1, Box(xcont_beg-cont_metall_over, yMet1, xcont_end+cont_metall_over, yMet2), metall_layer)
-                else :
-                    MkPin(self, 'D', 1, Box(xcont_beg-cont_metall_over, yMet1, xcont_end+cont_metall_over, yMet2), metall_layer)
-                    
-                
-            if typ == 'N' :
-                dbCreateRect(self, ndiff_layer, Box(xcont_beg-cont_Activ_overRec, ycont_beg-cont_Activ_overRec, xcont_end+cont_Activ_overRec, ycont_beg+cont_size+cont_Activ_overRec))
-            else :
-                dbCreateRect(self, pdiff_layer, Box(xcont_beg-cont_Activ_overRec, ycont_beg-cont_Activ_overRec, xcont_end+cont_Activ_overRec, ycont_beg+cont_size+cont_Activ_overRec))
-                
-            
-        # now finish drawing the diffusion
-        xdiff_end = xcont_end+cont_Activ_overRec
-        if typ == 'N' :
-            dbCreateRect(self, ndiff_layer, Box(xdiff_beg, ydiff_beg+diffoffset, xdiff_end, ydiff_end+diffoffset))
-        else :
-            dbCreateRect(self, pdiff_layer, Box(xdiff_beg, ydiff_beg+diffoffset, xdiff_end, ydiff_end+diffoffset))
-            dbCreateRect(self, pdiffx_layer, Box(xdiff_beg-psd_pActiv_over, ydiff_beg-psd_pActiv_over+diffoffset, xdiff_end+psd_pActiv_over, ydiff_end+psd_pActiv_over+diffoffset))
-            # draw minimum nWell
-            nwell_offset = max(0, GridFix((contActMin-w)/2+0.5*grid))
-            dbCreateRect(self, well_layer, Box(xdiff_beg-nwell_pActiv_over, ydiff_beg-nwell_pActiv_over+diffoffset-nwell_offset, xdiff_end+nwell_pActiv_over, ydiff_end+nwell_pActiv_over+diffoffset+nwell_offset))
-            # draw nBuLay if nWell is large enough
-            # wmin=2.88 -> only width musdt be checked
-            if (ydiff_end+nwell_pActiv_over+diffoffset+nwell_offset)-(ydiff_beg-nwell_pActiv_over+diffoffset-nwell_offset) > minNwellForNBuLay :
-                dbCreateRect(self, well2_layer, Box(xdiff_beg-nwell_pActiv_over+well2_over, ydiff_beg-nwell_pActiv_over+diffoffset-nwell_offset+well2_over, xdiff_end+nwell_pActiv_over-well2_over, ydiff_end+nwell_pActiv_over+diffoffset+nwell_offset-well2_over))
-            
-        if hv :
-            dbCreateRect(self, Layer('ThickGateOx', 'drawing'), Box(xdiff_beg-thGateOxAct, ydiff_beg-gatpoly_Activ_over-thGateOxGat, xdiff_end+thGateOxAct, ydiff_end+gatpoly_Activ_over+thGateOxGat))
-            
diff --git a/ihp-sg13g2/libs.tech/pycell/npn13G2_base_code.py b/ihp-sg13g2/libs.tech/pycell/npn13G2_base_code.py
deleted file mode 100644
index 880deb32..00000000
--- a/ihp-sg13g2/libs.tech/pycell/npn13G2_base_code.py
+++ /dev/null
@@ -1,151 +0,0 @@
-########################################################################
-#
-# Copyright 2023 IHP PDK Authors
-# 
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-# 
-#    https://www.apache.org/licenses/LICENSE-2.0
-# 
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-########################################################################
-__version__ = "$Revision: #3 $"
-
-from cni.dlo import *
-from thermal import *
-from geometry import *
-from utility_functions import *
-
-import math
-
-class npn13G2_base(DloGen):
-
-    @classmethod
-    def defineParamSpecs(cls, specs):        
-        specs('STI', '0.44u')
-        specs('baspolyx', '0.3u')
-        specs('bipwinx', '0.07u')
-        specs('bipwiny', '0.1u')
-        specs('empolyx', '0.15u')
-        specs('empolyy', '0.18u')
-        specs('le', '0.9u')
-        specs('we', '0.07u')
-        specs('Nx', 1)
-        specs('Text', 'npn13G2')
-        specs('CMetY1', '0.0')
-        specs('CMetY2', '0.0')
-
-    def setupParams(self, params):
-        # process parameter values entered by user
-        self.STI = Numeric(params['STI'])
-        self.baspolyx = Numeric(params['baspolyx'])
-        self.bipwinx = Numeric(params['bipwinx'])
-        self.bipwiny = Numeric(params['bipwiny'])
-        self.empolyx = Numeric(params['empolyx'])
-        self.empolyy = Numeric(params['empolyy'])
-        self.le = Numeric(params['le'])
-        self.we = Numeric(params['we'])
-        self.Nx = Numeric(params['Nx'])
-        self.Text = params['Text']
-        self.CMetY1 = Numeric(params['CMetY1'])
-        self.CMetY2 = Numeric(params['CMetY2'])
-
-    def genLayout(self):        
-        STI = self.STI
-        baspolyx = self.baspolyx
-        bipwinx = self.bipwinx
-        bipwiny = self.bipwiny
-        empolyx = self.empolyx
-        empolyy = self.empolyy
-        le = self.le
-        we = self.we
-        Nx = self.Nx
-        Text = self.Text
-        CMetY1 = self.CMetY1
-        CMetY2 = self.CMetY2
-        
-        STI = Numeric(STI)*1e6
-        baspolyx = Numeric(baspolyx)*1e6
-        bipwinx = Numeric(bipwinx)*1e6
-        bipwiny = Numeric(bipwiny)*1e6
-        empolyx = Numeric(empolyx)*1e6
-        empolyy = Numeric(empolyy)*1e6
-        le = Numeric(le)*1e6
-        we = Numeric(we)*1e6;
-        
-        Cell = 'npn13G2_base'
-
-        stepX = 1.85
-        stretchX = stepX*(Nx-1)
-        bipwinxoffset = ((2 * (bipwinx - 0.04)) / 2)
-        empolyxoffset = ((2 * (empolyx - 0.15)) / 2)
-        baspolyxoffset = ((2 * (baspolyx - 0.3)) / 2)
-        STIoffset = ((2 * (STI - 0.44)) / 2)
-        bipwinyoffset = ((2 * (bipwiny - 0.1)) / 2)
-        empolyyoffset = ((2 * (empolyy - 0.18)) / 2)
-        nSDBlockShift = 0.43 - le
-        leoffset = 0
-        if le <  0.5 :
-            pcStepY = 0.41
-            yOffset = 0.20
-        else :
-            pcStepY = 0.41
-            yOffset = 0.20
-            
-        if we <=  0.9 :
-            pcRepeatY = 3
-        else :
-            pcRepeatY = 4
-            
-        pcRepeatY = 4
-        if Nx >  1 :
-            CMetY1 = -1.01 - we/2 - leoffset - bipwinyoffset - empolyyoffset
-            CMetY2 = -0.57 - we/2 - leoffset - bipwinyoffset - empolyyoffset
-        else :
-            CMetY1 = -0.8 - we/2 - leoffset - bipwinyoffset - empolyyoffset
-            CMetY2 = -0.56 - we/2 - leoffset - bipwinyoffset - empolyyoffset
-            
-        pcPurpose = 'drawing'
-        for pcIndexX in range(int(math.floor(Nx))) :
-            pcLayer = Layer('Via1')
-            for pcIndexY in range(int((math.floor(pcRepeatY)))) :
-                pcInst = dbCreateRect(self, Layer('Via1', 'drawing'), Box((stepX*pcIndexX)-0.3, ((-0.30-yOffset-leoffset-bipwinyoffset-empolyyoffset)+(pcIndexY*pcStepY))-0.2, (stepX*pcIndexX)-0.11, ((-0.11-yOffset-leoffset-bipwinyoffset-empolyyoffset)+(pcIndexY*pcStepY))-0.2))
-                pcInst = dbCreateRect(self, Layer('Via1', 'drawing'), Box((stepX*pcIndexX)+0.11, ((-0.3-yOffset-leoffset-bipwinyoffset-empolyyoffset)+(pcIndexY*pcStepY))-0.2, (stepX*pcIndexX)+0.3, ((-0.11-yOffset-leoffset-bipwinyoffset-empolyyoffset)+(pcIndexY*pcStepY))-0.2))
-                
-            pcLayer = Layer('Metal1')
-            pcInst = dbCreateRect(self, Layer('Metal1', 'drawing'), Box(stepX*pcIndexX-0.35, (-0.32-we/2-leoffset-bipwinyoffset-empolyyoffset), stepX*pcIndexX+0.35, (0.335+we/2+leoffset+bipwinyoffset+empolyyoffset)))
-            pcLayer = Layer('Cont')
-            pcInst = dbCreateRect(self, Layer('Cont', 'drawing'), Box(stepX*pcIndexX-0.79-le/2, (-0.76-we/2-leoffset-bipwinyoffset-empolyyoffset), stepX*pcIndexX+0.79+le/2, (-0.6-we/2-leoffset-bipwinyoffset-empolyyoffset)))
-            pcInst = dbCreateRect(self, Layer('Cont', 'drawing'), Box(stepX*pcIndexX-0.76, (0.77+we/2-leoffset-bipwinyoffset-empolyyoffset), stepX*pcIndexX+0.76, (0.61+we/2-leoffset-bipwinyoffset-empolyyoffset)))
-            pcLayer = Layer('EmWind')
-            pcInst = dbCreateRect(self, Layer('EmWind', 'drawing'), Box(stepX*pcIndexX-le/2, (-we/2-leoffset), stepX*pcIndexX+le/2, (we/2+leoffset)))
-            
-            #ihpAddThermalBjtLayer(pcCellView, Box((stepX*pcIndexX-le/2)-0.05, , -we/2 - leoffset, -0.05, (stepX*pcIndexX+le/2)+0.05, , we/2 + leoffset, +0.05), t, Cell)
-            pcInst = dbCreateRect(self, Layer('EmWind', 'drawing'), Box(stepX*pcIndexX-le/2, (-we/2-leoffset), stepX*pcIndexX+le/2, (we/2+leoffset)))
-            pcLayer = Layer('Activ')
-            xl = stepX*pcIndexX-0.06
-            xh = xl+0.12
-            yl = -0.24-leoffset
-            yh = -yl
-            pcInst = dbCreatePolygon(self, Layer('Activ', 'mask'), PointList([Point(xh+0.865, yl-0.74), Point(xl-0.865, yl-0.74), Point(xl-0.865, yh+0.38), Point(xl-0.385, yh+0.38), Point(xl-0.175, yh+0.59), Point(xh+0.175, yh+0.59), Point(xh+0.385, yh+0.38), Point(xh+0.865, yh+0.38)]))
-            pcLayer = Layer('Activ')
-            pcInst = dbCreateRect(self, Layer('Activ', 'drawing'), Box((stepX*pcIndexX-0.89-le/2-empolyxoffset-baspolyxoffset-STIoffset), (-0.83-we/2-leoffset-bipwinyoffset-empolyyoffset), (stepX*pcIndexX+0.89+le/2+empolyxoffset+baspolyxoffset+STIoffset), (-0.89-we/2+0.36-leoffset-bipwinyoffset-empolyyoffset)))
-            pcLayer = Layer('nSD')
-            pcInst = dbCreatePolygon(self, Layer('nSD', 'block'), PointList([Point((stepX * pcIndexX + 0.94 + le/2 + empolyxoffset + baspolyxoffset + STIoffset), (1.98 + we/2 + leoffset + bipwinyoffset + empolyyoffset)), Point((stepX * pcIndexX + 0.94 + le/2 + empolyxoffset + baspolyxoffset + STIoffset), (0.45 + we/2 + leoffset + bipwinyoffset + empolyyoffset)), Point((stepX * pcIndexX + 0.52 + le/2 + empolyxoffset + baspolyxoffset + STIoffset), (0.03 + we/2 + leoffset + bipwinyoffset + empolyyoffset)), Point((stepX * pcIndexX + 0.52 + le/2 + empolyxoffset + baspolyxoffset + STIoffset), ( - 0.6 - we/2 + leoffset + bipwinyoffset + empolyyoffset + nSDBlockShift)), Point((stepX * pcIndexX + 0.27 + le/2 + empolyxoffset + baspolyxoffset + STIoffset), (- 0.85 - we/2 + leoffset + bipwinyoffset + empolyyoffset + nSDBlockShift)), Point((stepX * pcIndexX - 0.27 - le/2 - empolyxoffset - baspolyxoffset - STIoffset), (- 0.85 - we/2 + leoffset + bipwinyoffset + empolyyoffset + nSDBlockShift)), Point((stepX * pcIndexX - 0.52 - le/2 - empolyxoffset - baspolyxoffset - STIoffset), (- 0.6 - we/2 + leoffset + bipwinyoffset + empolyyoffset + nSDBlockShift)), Point((stepX * pcIndexX - 0.52 - le/2 - empolyxoffset - baspolyxoffset - STIoffset), (0.03 + we/2 + leoffset + bipwinyoffset + empolyyoffset) ), Point((stepX * pcIndexX - 0.94 - le/2 - empolyxoffset - baspolyxoffset - STIoffset), (0.45 + we/2 + leoffset + bipwinyoffset + empolyyoffset)), Point((stepX * pcIndexX - 0.94 - le/2 - empolyxoffset - baspolyxoffset - STIoffset), (1.98 + we/2 + leoffset + bipwinyoffset + empolyyoffset))]))
-            
-        pcLayer = Layer('Metal1')
-        pcInst = dbCreateRect(self, Layer('Metal1', 'drawing'), Box(-0.89-le/2, CMetY1, stretchX+0.89+le/2, CMetY2))
-        pcInst = dbCreateRect(self, Layer('Metal1', 'drawing'), Box(-0.94-le/2, (0.57+we/2+leoffset+bipwinyoffset+empolyyoffset), stretchX+0.94+le/2, (0.81+we/2+leoffset+bipwinyoffset+empolyyoffset)))
-        pcLayer = Layer('Metal2')
-        pcInst = dbCreateRect(self, Layer('Metal2', 'drawing'), Box(-0.89-le/2, (-0.32-we/2-leoffset-bipwinyoffset-empolyyoffset), stretchX+0.89+le/2, (0.335+we/2+leoffset+bipwinyoffset+empolyyoffset)))
-        pcLayer = Layer('TEXT')
-        pcLabelText = self.Text
-        pcLabelHeight = 0.35
-        pcInst = dbCreateLabel(self, Layer('TEXT', 'drawing'), Point(0.015, (-1.86 - we/2 - leoffset - bipwinyoffset - empolyyoffset)), pcLabelText, 'centerCenter', 'R0', Font.EURO_STYLE, pcLabelHeight)
-        pcInst.setDrafting(True)
diff --git a/ihp-sg13g2/libs.tech/pycell/npn13G2_code.py b/ihp-sg13g2/libs.tech/pycell/npn13G2_code.py
deleted file mode 100644
index e200a964..00000000
--- a/ihp-sg13g2/libs.tech/pycell/npn13G2_code.py
+++ /dev/null
@@ -1,169 +0,0 @@
-########################################################################
-#
-# Copyright 2023 IHP PDK Authors
-# 
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-# 
-#    https://www.apache.org/licenses/LICENSE-2.0
-# 
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-########################################################################
-__version__ = "$Revision: #3 $"
-
-from cni.dlo import *
-from thermal import *
-from geometry import *
-from utility_functions import *
-
-import math
-
-class npn13G2(DloGen):
-
-    @classmethod
-    def defineParamSpecs(cls, specs):  
-        techparams = specs.tech.getTechParams()
-        
-        CDFVersion = techparams['CDFVersion']
-        model      = techparams['npn13G2_model']
-        
-        specs('cdf_version', CDFVersion, 'CDF Version')
-        specs('Display', 'Selected', 'Display', ChoiceConstraint(['All', 'Selected']))
-        specs('model', model, 'Model name')
-        
-        specs('Nx', 1, 'x-Multiplier', RangeConstraint(1, 10))
-        specs('Ny', 1, 'y-Multiplier', ChoiceConstraint([1]))
-        specs('le', '0.9u', "Emitter Length")
-        specs('we', '0.07u', "Emitter Width")
-        specs('STI', '0.44u', 'STI')
-        specs('baspolyx', '0.30u', 'baspolyx')
-        specs('bipwinx', '0.07u', 'bipwinx')
-        specs('bipwiny', '0.1u', 'bipwiny')
-        specs('empolyx', '0.15u', 'empolyx')
-        specs('empolyy', '0.18u', 'empolyy')
-        
-        specs('Icmax', '3m', 'Ic,max@Uce=2V (50%@0.5V)')
-        specs('Iarea', '3m', 'Ic,max/squm@Uce=2V')
-        specs('area', '1', 'Area Factor')
-        specs('bn', 'sub!', 'Bulk node connection')
-        specs('Vbe', '', 'Base-emitter voltag')
-        specs('Vce', '', 'Collector-emitter voltage')
-        specs('m', '1', 'Multiplier')
-        specs('trise', '', 'Temp rise from ambient')
-
-    def setupParams(self, params):
-        # process parameter values entered by user
-        self.params = params
-        self.STI = Numeric(params['STI'])
-        self.baspolyx = Numeric(params['baspolyx'])
-        self.bipwinx = Numeric(params['bipwinx'])
-        self.bipwiny = Numeric(params['bipwiny'])
-        self.empolyx = Numeric(params['empolyx'])
-        self.empolyy = Numeric(params['empolyy'])
-        self.le = params['le']
-        self.we = params['we']
-        self.Nx = params['Nx']
-        self.Ny = params['Ny']
-        self.masterCell   = 'npn13G2_base'
-        self.masterView   = 'layout'
-        self.masterOrient = 'MX'
-        self.masterLib    = 'SG13_dev'
-
-    def genLayout(self):
-        STI = self.STI
-        baspolyx = self.baspolyx
-        bipwinx = self.bipwinx
-        bipwiny = self.bipwiny
-        empolyx = self.empolyx
-        empolyy = self.empolyy
-        le = Numeric(self.le)
-        Nx = Numeric(self.Nx)
-        we = Numeric(self.we)
-        Ny = Numeric(self.Ny)
-        
-        STI = Numeric(STI)*1e6
-        baspolyx = Numeric(baspolyx)*1e6
-        bipwinx = Numeric(bipwinx)*1e6
-        bipwiny = Numeric(bipwiny)*1e6
-        empolyx = Numeric(empolyx)*1e6
-        empolyy = Numeric(empolyy)*1e6
-        le = Numeric(le)*1e6
-        we = Numeric(we)*1e6
-        
-        a = le
-        le = we
-        we = a
-        ActivShift = 0.01
-        ActivShift = 0.0
-        PWellBlockShift = -0.01
-        stepX = 1.85
-        stretchX = stepX*(Nx-1)
-        bipwinyoffset = (2 * (bipwiny - 0.1) - 0) / 2
-        empolyyoffset = (2 * (empolyy - 0.18)) / 2
-        
-        if le <  0.5 :
-            leoffset = 0
-        else :
-            leoffset = 0
-            
-        name = self.masterLib + '/' + self.masterCell +'/' + self.masterView
-        if Dlo.exists(name) :
-            pcMaster = Instance(name)   
-            params = pcMaster.getParams()
-            params['le'] = self.le
-            params['Nx'] = self.Nx
-            params['we'] = self.we
-            pcMaster.setParams(params)
-            pcMaster.setOrientation(strToOrient(self.masterOrient))
-            pcMaster.setOrigin(Point(0, 0))
-        else :
-            print('(OA) Design "' + name + '" was not found')
-            
-        pcLayer = 'TRANS'
-        pcPurpose = 'drawing'
-        dbCreatePolygon(self, Layer(pcLayer, pcPurpose), PointList([Point(stretchX+2.45, (2.43 + we/2 + leoffset + bipwinyoffset + empolyyoffset)), 
-                                                                    Point(-2.45, (2.43 + we/2 + leoffset + bipwinyoffset + empolyyoffset)), 
-                                                                    Point(-2.45, (-1.98 - we/2 - leoffset - bipwinyoffset - empolyyoffset)), 
-                                                                    Point(stretchX+2.45, (-1.98 - we/2 - leoffset - bipwinyoffset - empolyyoffset))]))
-        pcLayer = 'pSD'
-        dbCreatePolygon(self, Layer(pcLayer, pcPurpose), PointList([Point(stretchX+3.35, (3.33 + we/2 + leoffset + bipwinyoffset + empolyyoffset)), 
-                                                                    Point(stretchX+2.45, (3.33 + we/2 + leoffset + bipwinyoffset + empolyyoffset)), 
-                                                                    Point(stretchX+2.45, (-1.98 - we/2 - leoffset - bipwinyoffset - empolyyoffset)), 
-                                                                    Point(-2.45, (-1.98 - we/2 - leoffset - bipwinyoffset - empolyyoffset)), 
-                                                                    Point(-2.45, (2.43 + we/2 + leoffset + bipwinyoffset + empolyyoffset)), 
-                                                                    Point(stretchX+2.45, (2.43 + we/2 + leoffset + bipwinyoffset + empolyyoffset)), 
-                                                                    Point(stretchX+2.45, (3.33 + we/2 + leoffset + bipwinyoffset + empolyyoffset)), 
-                                                                    Point(-3.35, (3.33 + we/2 + leoffset + bipwinyoffset + empolyyoffset)), 
-                                                                    Point(-3.35, (-2.88 - we/2 - leoffset - bipwinyoffset - empolyyoffset)), 
-                                                                    Point(stretchX+3.35, (-2.88 - we/2 - leoffset - bipwinyoffset - empolyyoffset))]))
-        pcLayer = 'Activ'
-        dbCreatePolygon(self, Layer(pcLayer, pcPurpose), PointList([Point(stretchX+3.15+ActivShift, (3.13 + we/2 + leoffset + bipwinyoffset + empolyyoffset+ActivShift)), 
-                                                                    Point(stretchX+2.65+ActivShift, (3.13 + we/2 + leoffset + bipwinyoffset + empolyyoffset+ActivShift)), 
-                                                                    Point(stretchX+2.65+ActivShift, (-2.18 - we/2 - leoffset - bipwinyoffset - empolyyoffset-ActivShift)), 
-                                                                    Point(-2.65-ActivShift, (-2.18 - we/2 - leoffset - bipwinyoffset - empolyyoffset-ActivShift)), 
-                                                                    Point(-2.65-ActivShift, (2.63 + we/2 + leoffset + bipwinyoffset + empolyyoffset+ActivShift)), 
-                                                                    Point(stretchX+2.65+ActivShift, (2.63 + we/2 + leoffset + bipwinyoffset + empolyyoffset+ActivShift)), 
-                                                                    Point(stretchX+2.65+ActivShift, (3.13 + we/2 + leoffset + bipwinyoffset + empolyyoffset+ActivShift)), 
-                                                                    Point(-3.15-ActivShift, (3.13 + we/2 + leoffset + bipwinyoffset + empolyyoffset+ActivShift)), 
-                                                                    Point(-3.15-ActivShift, (-2.68 - we/2 - leoffset - bipwinyoffset - empolyyoffset-ActivShift)), 
-                                                                    Point(stretchX+3.15+ActivShift, (-2.68 - we/2 - leoffset - bipwinyoffset - empolyyoffset-ActivShift))]))
-        if Nx >  1 :
-            MkPin(self, 'C', 1, Box(-0.89-le/2, (0.57+we/2-leoffset-bipwinyoffset-empolyyoffset), (stretchX+0.89+le/2), (1.01+we/2-leoffset-bipwinyoffset-empolyyoffset)), Layer('Metal1', 'pin'))
-        else :
-            MkPin(self, 'C', 1, Box(-0.89-le/2, (0.56+we/2+leoffset+bipwinyoffset+empolyyoffset), (stretchX+0.89+le/2), (0.8+we/2+leoffset+bipwinyoffset+empolyyoffset)), Layer('Metal1', 'pin'))
-            
-        MkPin(self, 'B', 2, Box(-0.94-le/2, (-0.81-we/2-leoffset-bipwinyoffset-empolyyoffset), (stretchX+0.94+le/2), (-0.57-we/2-leoffset-bipwinyoffset-empolyyoffset)), Layer('Metal1', 'pin'))
-        MkPin(self, 'E', 3, Box(-0.71-le/2, (0.32+we/2+leoffset+bipwinyoffset+empolyyoffset), stretchX+0.71+le/2, (-0.335-we/2-leoffset-bipwinyoffset-empolyyoffset)), Layer('Metal2', 'pin'))
-        
-        pcLayer = 'TEXT'
-        pcLabelText = 'Ae={Ae}um2'.format(Ae=Nx*Ny*le*we)
-        pcLabelHeight = 0.35
-        pcInst = dbCreateLabel(self, Layer(pcLayer, pcPurpose), Point(-1.977, -2.546), pcLabelText, 'lowerLeft', 'R90', Font.EURO_STYLE, pcLabelHeight)
-        #setSGq(pcInst, "normalLabel", labelType)
-        
diff --git a/ihp-sg13g2/libs.tech/pycell/rhigh_code.py b/ihp-sg13g2/libs.tech/pycell/rhigh_code.py
deleted file mode 100644
index 905f5669..00000000
--- a/ihp-sg13g2/libs.tech/pycell/rhigh_code.py
+++ /dev/null
@@ -1,491 +0,0 @@
-########################################################################
-#
-# Copyright 2023 IHP PDK Authors
-# 
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-# 
-#    https://www.apache.org/licenses/LICENSE-2.0
-# 
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-########################################################################
-__version__ = '$Revision: #3 $'
-
-from cni.dlo import *
-from geometry import *
-from thermal import *
-from utility_functions import *
-
-import math
-
-class rhigh(DloGen):
-
-    @classmethod
-    def defineParamSpecs(cls, specs):
-        # define parameters and default values 
-        techparams = specs.tech.getTechParams()
-
-        SG13_TECHNOLOGY = techparams["techName"]
-        suffix = ""
-        if 'SG13G2' in SG13_TECHNOLOGY :
-            suffix = 'G2' 
-        if 'SG13G3' in SG13_TECHNOLOGY :
-            suffix = 'G3'
-        
-        CDFVersion = techparams['CDFVersion']
-        model      = techparams['rhigh_model']
-        rspec      = techparams['rhigh_rspec']
-        rkspec     = techparams['rhigh_rkspec']
-        rzspec     = techparams['rhigh_rzspec']
-        defL       = techparams['rhigh_defL']
-        defW       = techparams['rhigh_defW']
-        defB       = techparams['rhigh_defB']
-        defPS      = techparams['rhigh_defPS']
-        minL       = techparams['rhigh_minL']
-        minW       = techparams['rhigh_minW']
-        minPS      = techparams['rhigh_minPS']
-        eps        = techparams['epsilon2']
-        
-        specs('cdf_version', CDFVersion, 'CDF Version')
-        specs('Display', 'Selected', 'Display', ChoiceConstraint(['All', 'Selected']))
-        specs('Calculate', 'l', 'Calculate', ChoiceConstraint(['R', 'w', 'l']))
-        specs('Recommendation', 'No', 'Recommendation', ChoiceConstraint(['Yes', 'No']))
-        specs('model', model, 'Model name')
-        
-        resistance = CbResCalc('R', 0, defL, defW, defB, defPS, 'rhigh')
-        specs('R', eng_string(resistance), 'R')
-        
-        specs('w',  defW, 'Width')
-        specs('l',  defL, 'Length')
-        specs('b',  defB, 'Bends')
-        specs('ps', defPS, 'Poly Space')
-        
-        imax = CbResCurrent(Numeric(defW), eps, 'rhigh'+suffix)
-        specs('Imax', imax, 'Imax')
-        specs('bn', 'sub!', 'Bulk node connection')
-        specs('Wmin', minW, 'Wmin')
-        specs('Lmin', minL, 'Lmin')
-        specs('PSmin', minPS, 'PSmin')
-        specs('Rspec', rspec, 'Rspec [Ohm/sq]')
-        specs('Rkspec', rkspec, 'Rkspec [Ohm/cont]')
-        specs('Rzspec', rzspec, 'Rzspec [Ohm*m]')
-        specs('tc1', '-2300e-6', 'Temperature coefficient 1')
-        specs('tc2', '2.1e-6', 'Temperature coefficient 2')
-        specs('PWB', 'No', 'PWell Blockage', ChoiceConstraint(['Yes', 'No']))
-        specs('m', '1', 'Multiplier')
-        specs('trise', '0.0', 'Temp rise from ambient')
-        
-    def setupParams(self, params):
-        # process parameter values entered by user
-        self.l = Numeric(params['l'])
-        self.w = Numeric(params['w'])
-        self.b = int(params['b'])
-        self.ps = Numeric(params['ps'])
-        #self.resistance = Numeric(params['R'])
-        
-        self.grid = self.tech.getGridResolution()
-        self.techparams = self.tech.getTechParams()
-        self.epsilon = self.techparams['epsilon1']  
-
-    def genLayout(self):  
-        #*************************************************************************
-        #*
-        #* Cell Properties
-        #*
-        #*************************************************************************     
-        dbReplaceProp(self, 'ivCellType', 'graphic')
-        dbReplaceProp(self, 'viewSubType', 'maskLayoutParamCell')
-        dbReplaceProp(self, 'instNamePrefix', 'R')
-        dbReplaceProp(self, 'function', 'resistor')
-        dbReplaceProp(self, 'pcellVersion', '$Revision: 1.0 $')
-        dbReplaceProp(self, 'pin#', 3)
-        
-        #*************************************************************************
-        #*
-        #* Layer Definitions
-        #*
-        #*************************************************************************
-        contpolylayer = Layer('GatPoly')
-        bodypolylayer = Layer('PolyRes')
-        sallayer = Layer('SalBlock')
-        locintlayer = Layer('Cont')
-        extBlocklayer = Layer('EXTBlock')
-        metlayer = Layer('Metal1')
-        textlayer = Layer('TEXT', 'drawing')
-        nsdlayer = Layer('nSD')
-        psdlayer = Layer('pSD')
-        
-        #*************************************************************************
-        #*
-        #* Generic Design Rule Definitions
-        #*
-        #*************************************************************************
-        metover = self.techparams['M1_c']
-        salover = self.techparams['Sal_c']
-        salover1 = self.techparams['Sal_c']
-        salspace = self.techparams['Sal_d']
-        psdover1 = self.techparams['Rppd_b']
-        consize = self.techparams['Cnt_a']
-        conspace = self.techparams['Cnt_b']
-        endcap = self.techparams['M1_c1']
-        endcap2 = self.techparams['M1_c1']
-        polyover = self.techparams['Cnt_d']
-        grid = self.techparams['grid']
-        contbar_min_len = self.techparams['CntB_a1']
-        contbar_poly_over = self.techparams['CntB_d']
-        
-        #*************************************************************************
-        #*
-        #* Device Specific Design Rule Definitions
-        #*
-        #*************************************************************************
-        psdover = self.techparams['Rhi_c']
-        nsdover = self.techparams['Rhi_c']
-        li_salblock = self.techparams['Rhi_d']
-        poly_cont_len = consize+polyover # self.techparams['rhigh_poly_cont_len']   # 0.57
-        
-        # **************** Internal / External *********************************
-        # use internalCode True for internal PCell
-        internalCode = True
-        # **************** Internal / External *********************************
-        salblock_nsd_enc = 0.0
-        li_poly_over = 0.0
-        contactpush = 0.0
-        resshort = 0.0
-        gridnumber = 0.0
-        contoverlay = 0.0
-        lcor = 0.0
-        psmin = Numeric(self.techparams['rhigh_minPS'])*1e6 
-        
-        #*************************************************************************
-        #*
-        #* Instances For Mosaic Fills
-        #*
-        #*************************************************************************
-        Cell = self.__class__.__name__
-        #*************************************************************************
-        #*
-        #* Main body of code
-        #*
-        #*************************************************************************
-       
-        l = Numeric(self.l)*1e6;
-        w = Numeric(self.w)*1e6;
-        b = fix(self.b + self.epsilon)
-        ps = Numeric(self.ps)*1e6;
-        
-        # GGa Attention: Poly must be 2*Cnt_a + Cnt_b + 2*Cnt_d Min Size of Cont + 2* GatPolyEnclosure. Might be dogbone
-        wcontact = w
-        
-        # 10.12.07 GGa added block for internal code
-        drawbar = False
-        
-        if internalCode :
-            if wcontact-2*contbar_poly_over + self.epsilon >= contbar_min_len :
-                drawbar = True
-                
-        if psdover1 > psdover :
-            psdover = psdover1
-            
-        if salover1 > salover :
-            salover = salover1
-            
-        nsdover = psdover
-        # GGa dogbone has to be on grid, so make difference in gridsteps
-        contoverlay = wcontact - w
-        if contoverlay > 0 :
-            # is dogbone: keep on checking for lay on grid
-            # Distance per side
-            contoverlay = contoverlay/2
-            # gridpoints per side?
-            gridnumber = contoverlay/grid
-            # make to fixnumber
-            gridnumber = round(gridnumber + self.epsilon)
-            # need more gridpoints to lay on grip?
-            if (gridnumber*grid*100) < contoverlay :
-                gridnumber += 1
-                
-            contoverlay = gridnumber*grid
-            wcontact = w+2*contoverlay
-        # if
-        
-        # Insertionpoint for contact is at (0-contoverlay:0)    
-        xpos1 = 0-contoverlay
-        ypos1 = 0
-        xpos2 = xpos1+wcontact
-        ypos2 = 0
-        dir = -1
-        stripes = b+1
-        endcap = max(endcap, endcap2)
-        metover = max(endcap2, metover)
-        
-        # set contacts out of resistor-square?
-        # GridFix because 0.40000 < (0.20000+0.2000). Works with GridFix
-        lsumold = 0.0
-        lsumnew = 0.0
-        lcor = 0.0
-        if GridFix(ps) < GridFix((salover+salspace)) and stripes > 2 :
-            contactpush = contactpush+w+salover
-            resshort = GridFix((2*contactpush)/stripes)+grid
-            lsumold = l*stripes
-            l = l-resshort
-            lsumnew = l*stripes+contactpush*2
-            # need to push out contact2?
-            lcor = lsumold-lsumnew
-        
-        # 05.05.06 GGa Check, if contacts have to be asymmetric
-        # Some cases need to have asym contacts:
-        # 2 stripes and low ps and are not pushed out of resistor    
-        if zerop(contactpush) and (ps-2*contoverlay <= psmin) and onep(b) :
-            asymcont = True
-        else :
-            asymcont = False
-        
-        # set all parts up to get 0:0 at beginning of resistorbody:    
-        ypos1 = ypos1-contactpush*dir
-        ypos2 = ypos2-contactpush*dir
-        
-        # *********************************************************
-        # draw res contact #1 -> realise Overlap by dogbone to keep burdens, when needed
-        # BOT Contact area
-        # *********************************************************
-        # set xpos1/xpos2 to left for contacts when Stripes>1 and ps<
-        if asymcont :
-            xpos1 = xpos1-contoverlay
-            xpos2 = xpos2-contoverlay
-        
-        # *********************************************************
-        # gatpolyarea between salBlock and contact    
-        dbCreateRect(self, contpolylayer, Box(xpos1, ypos1+contactpush*dir, xpos2, ypos2+(contactpush+poly_cont_len+li_salblock)*dir))
-        
-        # *********************************************************
-        # nSD/pSD EXTBlock
-        dbCreateRect(self, psdlayer,      Box(xpos1-psdover, ypos1+(contactpush-psdover)*dir, xpos2+psdover, ypos2+(contactpush+poly_cont_len+li_salblock+psdover)*dir))
-        dbCreateRect(self, nsdlayer,      Box(xpos1-psdover, ypos1+(contactpush-psdover)*dir, xpos2+psdover, ypos2+(contactpush+poly_cont_len+li_salblock+psdover)*dir))
-        dbCreateRect(self, extBlocklayer, Box(xpos1-psdover, ypos1+(contactpush-psdover)*dir, xpos2+psdover, ypos2+(contactpush+poly_cont_len+li_salblock+psdover)*dir))
-        
-        # contact area
-        # number parallel contacts ncont, distance distc:
-        wcon = wcontact-2.0*polyover
-        distc = consize+conspace
-        ncont = floor((wcon+conspace)/distc + self.epsilon)
-        if ncont < 1 :
-            ncont = 1
-        distr = GridFix((wcon-ncont*distc+conspace)*0.5)
-        
-        # *********************************************************
-        # draw contact
-        if drawbar :
-            # can only be in internal version
-            dbCreateRect(self, locintlayer, Box(xpos1+contbar_poly_over, ypos2+(contactpush+li_salblock+li_poly_over)*dir, xpos2-contbar_poly_over, ypos2+(contactpush+consize+li_salblock+li_poly_over)*dir))
-        else :
-            for i in range(ncont) :
-                dbCreateRect(self, locintlayer, Box(xpos1+polyover+distr+i*distc, ypos2+(contactpush+li_salblock+li_poly_over)*dir, xpos1+polyover+distr+i*distc+consize, ypos2+(contactpush+consize+li_salblock+li_poly_over)*dir))
-                
-        # 26.6.08 GG: new metal block   
-        dbCreateRect(self, metlayer, Box(xpos1+contbar_poly_over-endcap, ypos2+(contactpush+li_salblock+li_poly_over-metover)*dir, xpos2-contbar_poly_over+endcap, ypos2+(contactpush+consize+li_salblock+li_poly_over+metover)*dir))
-        MkPin(self, 'PLUS', 1, Box(xpos1+contbar_poly_over-endcap, ypos2+(contactpush+li_salblock+li_poly_over-metover)*dir, xpos2-contbar_poly_over+endcap, ypos2+(contactpush+consize+li_salblock+li_poly_over+metover)*dir), metlayer)
-        
-        # set xpos1/xpos2 back to right for resistorbody
-        if asymcont :
-            xpos1 = xpos1+contoverlay
-            xpos2 = xpos2+contoverlay
-        
-        # *********************************************************
-        # resistorbody:
-        # *********************************************************    
-        dir = 1
-        xpos1 = xpos1+contoverlay
-        xpos2 = xpos1+w-contoverlay
-        ypos2 = ypos1+(l-resshort)*dir
-        
-        # *********************************************************
-        # normal contatcs or outlying contacts?
-        if contactpush >  0 :
-            # *********************************************************
-            # draw salblock and pSD over resistor and bends
-            # Sal Block over stripes and bends
-            dbCreateRect(self, sallayer, Box(xpos1-salover, ypos1-contactpush*dir, xpos1+stripes*(w+ps)-ps+salover, ypos1+l+w+salover))
-            # 09.02.07 GGa added EXTBlock
-            dbCreateRect(self, extBlocklayer, Box(xpos1-salover, ypos1-contactpush*dir, xpos1+stripes*(w+ps)-ps+salover, ypos1+l+w+salover))
-            # pSD over Stripes and bend
-            dbCreateRect(self, psdlayer, Box(xpos1-psdover, ypos1-(contactpush-salblock_nsd_enc)*dir, xpos1+stripes*(w+ps)-ps+psdover, ypos1+(l+w+psdover)*dir))
-            # nsdBlock over Stripes and Bends
-            dbCreateRect(self, nsdlayer, Box(xpos1-nsdover, ypos1-(contactpush-salblock_nsd_enc)*dir, xpos1+stripes*(w+ps)-ps+nsdover, ypos1+(l+w+nsdover)*dir))
-            
-            # *********************************************************
-            # maybe draw extra salblock for longer last stripe
-            if lcor > 0 :
-                if oddp(stripes) :
-                    # draw new rect topright
-                    # SalBlock
-                    dbCreateRect(self, sallayer, Box(xpos1+stripes*(w+ps)-ps-w-salover, ypos1+l+w+salover, xpos1+stripes*(w+ps)-ps+salover, ypos1+l+w+salover+lcor))
-                    # 09.02.07 GGa added EXTBlock
-                    dbCreateRect(self, extBlocklayer, Box(xpos1+stripes*(w+ps)-ps-w-salover, ypos1+l+w+salover, xpos1+stripes*(w+ps)-ps+salover, ypos1+l+w+salover+lcor))
-                    # pSD
-                    dbCreateRect(self, psdlayer, Box(xpos1+stripes*(w+ps)-ps-w-psdover, ypos1+l+w+salover-salblock_nsd_enc, xpos1+stripes*(w+ps)-ps+psdover, ypos1+l+w+salover+lcor-salblock_nsd_enc))
-                    # nSD
-                    dbCreateRect(self, nsdlayer, Box(xpos1+stripes*(w+ps)-ps-w-nsdover, ypos1+l+w+salover-salblock_nsd_enc, xpos1+stripes*(w+ps)-ps+nsdover, ypos1+l+w+salover+lcor-salblock_nsd_enc))
-                else :   # draw new rect bottom right
-                    dbCreateRect(self, sallayer, Box(xpos1+stripes*(w+ps)-ps-w-salover, ypos1-contactpush-lcor, xpos1+stripes*(w+ps)-ps+salover, ypos1-contactpush))
-                    # 09.02.07 GGa added EXTBlock
-                    dbCreateRect(self, extBlocklayer, Box(xpos1+stripes*(w+ps)-ps-w-salover, ypos1-contactpush-lcor, xpos1+stripes*(w+ps)-ps+salover, ypos1-contactpush))
-                    dbCreateRect(self, psdlayer, Box(xpos1+stripes*(w+ps)-ps-w-psdover, ypos1-contactpush-lcor+salblock_nsd_enc, xpos1+stripes*(w+ps)-ps+psdover, ypos1-contactpush+salblock_nsd_enc))
-                    dbCreateRect(self, nsdlayer, Box(xpos1+stripes*(w+ps)-ps-w-nsdover, ypos1-contactpush-lcor+salblock_nsd_enc, xpos1+stripes*(w+ps)-ps+nsdover, ypos1-contactpush+salblock_nsd_enc))
-                # if oddp(stripes)  
-            # if lcor>0  
-        # *********************************************************               
-        else :   # normal SalBlock
-        # *********************************************************
-            if onep(stripes) :   # only one Stripe->other nSD/pSD
-        # *********************************************************
-                # one Stripe, only one SalBlock and shorter nSD/pSD
-                # draw salblock and pSD over resistor
-                dbCreateRect(self, sallayer, Box(xpos1-salover, ypos1, xpos1+stripes*(w+ps)-ps+salover, ypos2))
-                # 09.02.07 GGa added EXTBlock
-                dbCreateRect(self, extBlocklayer, Box(xpos1-salover, ypos1, xpos1+stripes*(w+ps)-ps+salover, ypos2))
-                dbCreateRect(self, psdlayer, Box(xpos1-psdover, ypos1+salblock_nsd_enc*dir, xpos1+stripes*(w+ps)-ps+psdover, ypos2-salblock_nsd_enc))
-                dbCreateRect(self, nsdlayer, Box(xpos1-nsdover, ypos1+dir*salblock_nsd_enc, xpos1+stripes*(w+ps)-ps+nsdover, ypos2-salblock_nsd_enc))
-            else :   # other nSD/pSD Blockcover Bends
-                # draw salblock and pSD over resistor
-                dbCreateRect(self, sallayer, Box(xpos1-salover, ypos1, xpos1+stripes*(w+ps)-ps+salover, ypos2))
-                # 09.02.07 GGa added EXTBlock
-                dbCreateRect(self, extBlocklayer, Box(xpos1-salover, ypos1, xpos1+stripes*(w+ps)-ps+salover, ypos2))
-                dbCreateRect(self, psdlayer, Box(xpos1-psdover, ypos1+salblock_nsd_enc*dir, xpos1+stripes*(w+ps)-ps+psdover, ypos2))
-                dbCreateRect(self, nsdlayer, Box(xpos1-nsdover, ypos1+dir*salblock_nsd_enc, xpos1+stripes*(w+ps)-ps+nsdover, ypos2))
-                if oddp(stripes) :    # draw salblock and pSD over resistor
-                    # odd stripesnumber
-                    dbCreateRect(self, sallayer, Box(xpos1+w+ps-salover, ypos1, xpos1+stripes*(w+ps)-ps+salover, ypos1-w-salover))
-                    # 09.02.07 GGa added EXTBlock
-                    dbCreateRect(self, extBlocklayer, Box(xpos1-salover, ypos2, xpos1+(stripes-1)*(w+ps)-ps+salover, ypos2+w+salover))
-                    dbCreateRect(self, sallayer, Box(xpos1+w+ps-salover, ypos1, xpos1+stripes*(w+ps)-ps+salover, ypos1-w-salover))
-                    # 09.02.07 GGa added EXTBlock
-                    dbCreateRect(self, extBlocklayer, Box(xpos1+w+ps-salover, ypos1, xpos1+stripes*(w+ps)-ps+salover, ypos1-w-salover))
-                    dbCreateRect(self, psdlayer, Box(xpos1-psdover, ypos2, xpos1+(stripes-1)*(w+ps)-ps+psdover, ypos2+w+psdover))
-                    dbCreateRect(self, psdlayer, Box(xpos1+w+ps-psdover, ypos1+salblock_nsd_enc, xpos1+stripes*(w+ps)-ps+psdover, ypos1-w-psdover))
-                    dbCreateRect(self, nsdlayer, Box(xpos1-nsdover, ypos2, xpos1+(stripes-1)*(w+ps)-ps+nsdover, ypos2+w+nsdover))
-                    dbCreateRect(self, nsdlayer, Box(xpos1+w+ps-nsdover, ypos1+salblock_nsd_enc, xpos1+stripes*(w+ps)-ps+nsdover, ypos1-w-nsdover))
-                else :   # unodd stripesnumber
-                    dbCreateRect(self, sallayer, Box(xpos1-salover, ypos2, xpos1+stripes*(w+ps)-ps+salover, ypos2+w+salover))
-                    # 09.02.07 GGa added EXTBlock
-                    dbCreateRect(self, extBlocklayer, Box(xpos1-salover, ypos2, xpos1+stripes*(w+ps)-ps+salover, ypos2+w+salover))
-                    dbCreateRect(self, psdlayer, Box(xpos1-psdover, ypos2, xpos1+stripes*(w+ps)-ps+psdover, ypos2+w+psdover))
-                    dbCreateRect(self, nsdlayer, Box(xpos1-nsdover, ypos2, xpos1+stripes*(w+ps)-ps+nsdover, ypos2+w+nsdover))
-                    if stripes > 2 :
-                        dbCreateRect(self, sallayer, Box(xpos1+w+ps-salover, ypos1, xpos1+(stripes-1)*(w+ps)-ps+salover, ypos1-w-salover))
-                        # 09.02.07 GGa added EXTBlock
-                        dbCreateRect(self, extBlocklayer, Box(xpos1+w+ps-salover, ypos1, xpos1+(stripes-1)*(w+ps)-ps+salover, ypos1-w-salover))
-                        dbCreateRect(self, psdlayer, Box(xpos1+w+ps-psdover, ypos1+salblock_nsd_enc, xpos1+(stripes-1)*(w+ps)-ps+psdover, ypos1-w-psdover))
-                        dbCreateRect(self, nsdlayer, Box(xpos1+w+ps-nsdover, ypos1+salblock_nsd_enc, xpos1+(stripes-1)*(w+ps)-ps+nsdover, ypos1-w-nsdover))
-                    # if stripes > 2
-                # if odd(stripes)
-            # if onep(stripes)
-        # if contactspush > 0
-                        
-        # *********************************************************
-        # GatPoly parts
-    
-        for i in range(1, int(stripes)+1) :
-            xpos2 = xpos1+w
-            ypos2 = ypos1+l*dir
-            # -----------------
-            # draw long res line
-            if i ==  1 :
-                dbCreateRect(self, bodypolylayer, Box(xpos1, ypos1-contactpush*dir, xpos2, ypos2))
-                ihpAddThermalResLayer(self, Box(xpos1, ypos1-contactpush*dir, xpos2, ypos2), True, Cell)
-                dbCreateRect(self, psdlayer, Box(xpos1-psdover, ypos1-contactpush*dir, xpos2+psdover, ypos2))
-                dbCreateRect(self, nsdlayer, Box(xpos1-psdover, ypos1-contactpush*dir, xpos2+psdover, ypos2))
-            else :
-                # Last Stripe has to be longer
-                if i == stripes :
-                    dbCreateRect(self, bodypolylayer, Box(xpos1, ypos1, xpos2, ypos2+(contactpush+lcor)*dir))
-                    ihpAddThermalResLayer(self, Box(xpos1, ypos1, xpos2, ypos2+(contactpush+lcor)*dir), True, Cell)
-                    dbCreateRect(self, psdlayer, Box(xpos1-psdover, ypos1, xpos2+psdover, ypos2+(contactpush+lcor)*dir))
-                    dbCreateRect(self, nsdlayer, Box(xpos1-psdover, ypos1, xpos2+psdover, ypos2+(contactpush+lcor)*dir))
-                else : 
-                    # all other stripes
-                    dbCreateRect(self, bodypolylayer, Box(xpos1, ypos1, xpos2, ypos2))
-                    ihpAddThermalResLayer(self, Box(xpos1, ypos1, xpos2, ypos2), True, Cell)
-                    
-                
-            if i < stripes : # connectionparts
-                ypos1 = ypos2+w*dir
-                xpos2 = xpos1+2*w+ps
-                ypos2 = ypos1-w*dir
-                dir *= -1
-                dbCreateRect(self, bodypolylayer, Box(xpos1, ypos1, xpos2, ypos2))
-                ihpAddThermalResLayer(self, Box(xpos1, ypos1, xpos2, ypos2), True, Cell)
-                xpos1 = xpos1+w+ps
-                ypos1 = ypos2
-        # for
-                
-        # x1,y1,x2,y2,dir are updated, so the code of first contact can be used
-        # (Except Pin Informations)
-
-        # *********************************************************
-        # TOP Contact Area
-        #draw res contact -> realise Overlap with dogbone, to keep burdens
-        # set x1 x2 to dogbone,:
-        #contact has to be out of symetric
-           
-        if asymcont :
-            xpos1 = xpos1
-            xpos2 = xpos2+contoverlay+contoverlay
-        else :   # leave, where ist is
-            xpos1 = xpos1-contoverlay
-            xpos2 = xpos2+contoverlay
-        
-        # *********************************************************
-        # pSD and SalBlock
-        # between res and cont    
-        dbCreateRect(self, contpolylayer, Box(xpos1, ypos2+(lcor+contactpush)*dir, xpos2, ypos2+(lcor+contactpush+poly_cont_len+li_salblock)*dir))
-        # *********************************************************
-        # 26.6.08 GG: nSD/pSD added
-        dbCreateRect(self, psdlayer, Box(xpos1-psdover, ypos2+(lcor+contactpush-psdover)*dir, xpos2+psdover, ypos2+(lcor+contactpush+poly_cont_len+li_salblock+psdover)*dir))
-        dbCreateRect(self, nsdlayer, Box(xpos1-psdover, ypos2+(lcor+contactpush-psdover)*dir, xpos2+psdover, ypos2+(lcor+contactpush+poly_cont_len+li_salblock+psdover)*dir))
-        # 11.02.09 GGa added EXTBlockLayer
-        dbCreateRect(self, extBlocklayer, Box(xpos1-psdover, ypos2+(lcor+contactpush-psdover)*dir, xpos2+psdover, ypos2+(lcor+contactpush+poly_cont_len+li_salblock+psdover)*dir))
-        
-        # *********************************************************
-        # contacts
-        # 10.12.07 GGa added internal code block
-        if drawbar :
-            # can only be in internal version
-            lastCont = dbCreateRect(self, locintlayer, Box(xpos1+contbar_poly_over, ypos2+(lcor+contactpush+li_salblock+li_poly_over)*dir, xpos2-contbar_poly_over, ypos2+(lcor+contactpush+consize+li_salblock+li_poly_over)*dir))
-        else :
-            for i in range(ncont) :
-                lastCont = dbCreateRect(self, locintlayer, Box(xpos1+polyover+distr+i*distc, ypos2+(lcor+contactpush+li_salblock+li_poly_over)*dir, xpos1+polyover+distr+i*distc+consize, ypos2+(lcor+contactpush+consize+li_salblock+li_poly_over)*dir))
-                
-        # 26.6.08 GG: new metal block
-        # *********************************************************
-        # Metal and pin
-        bBox = lastCont.getBBox()
-        dbCreateRect(self, metlayer, Box(bBox.left-endcap, bBox.bottom-endcap, bBox.right+endcap, bBox.top+endcap))
-    
-        MkPin(self, 'MINUS', 2, Box(bBox.left-endcap, bBox.bottom-endcap, bBox.right+endcap, bBox.top+endcap), metlayer)
-        
-        # *********************************************************
-        # draw the label
-        # GGa 08.05.06 added lcalc
-        # create virtuel l for CbResCalc
-        lcalc = (l*stripes+contactpush*2+lcor)/stripes
-        resistance = CbResCalc('R', 0, lcalc*1e-6, w*1e-6, b, ps*1e-6, Cell)
-        labeltext = 'rpnd r={0:.3f}'.format(resistance)
-        labelpos = Point(w/2, l/2)
-        labelheight = 0.1
-        if w > l :
-            rot = 'R0'
-        else :
-            rot = 'R90'
-            
-        lbl = dbCreateLabel(self, textlayer, labelpos, labeltext, 'centerCenter', rot, Font.EURO_STYLE, labelheight)
-        lsizex = lbl.bbox.getWidth()
-        lsizey = lbl.bbox.getHeight()
-        scale = min(w/lsizex, (l+2*poly_cont_len)/lsizey)
-        #SetSGq(lbl scale height)
diff --git a/ihp-sg13g2/libs.tech/pycell/rppd_code.py b/ihp-sg13g2/libs.tech/pycell/rppd_code.py
deleted file mode 100644
index 9898ed64..00000000
--- a/ihp-sg13g2/libs.tech/pycell/rppd_code.py
+++ /dev/null
@@ -1,476 +0,0 @@
-########################################################################
-#
-# Copyright 2023 IHP PDK Authors
-# 
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-# 
-#    https://www.apache.org/licenses/LICENSE-2.0
-# 
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-########################################################################
-__version__ = '$Revision: #3 $'
-
-from cni.dlo import *
-from thermal import *
-from geometry import *
-from utility_functions import *
-
-import math
-
-class rppd(DloGen):
-
-    @classmethod
-    def defineParamSpecs(cls, specs):
-        # define parameters and default values
-        techparams = specs.tech.getTechParams()
-        
-        SG13_TECHNOLOGY = techparams["techName"]
-        suffix = ""
-        if 'SG13G2' in SG13_TECHNOLOGY :
-            suffix = 'G2' 
-        if 'SG13G3' in SG13_TECHNOLOGY :
-            suffix = 'G3'
-        
-        CDFVersion = techparams['CDFVersion']
-        model      = techparams['rppd_model']
-        rspec      = techparams['rppd'+suffix+'_rspec']
-        rkspec     = techparams['rppd_rkspec']
-        rzspec     = techparams['rppd_rzspec']
-        defL       = techparams['rppd_defL']
-        defW       = techparams['rppd_defW']
-        defB       = techparams['rppd_defB']
-        defPS      = techparams['rppd_defPS']
-        minL       = techparams['rppd_minL']
-        minW       = techparams['rppd_minW']
-        minPS      = techparams['rppd_minPS']
-        eps        = techparams['epsilon2']
-        
-        specs('cdf_version', CDFVersion, 'CDF Version')
-        specs('Display', 'Selected', 'Display', ChoiceConstraint(['All', 'Selected']))
-        specs('Calculate', 'l', 'Calculate', ChoiceConstraint(['R', 'w', 'l']))
-        specs('Recommendation', 'No', 'Recommendation', ChoiceConstraint(['Yes', 'No']))
-        specs('model', model, 'Model name')
-        
-        resistance = CbResCalc('R', 0, defL, defW, defB, defPS, 'rppd')
-        specs('R', eng_string(resistance), 'R')
-        
-        specs('w',  defW, 'Width')
-        specs('l',  defL, 'Length')
-        specs('b',  defB, 'Bends')
-        specs('ps', defPS, 'Poly Space')
-        
-        imax = CbResCurrent(Numeric(defW), eps, 'rppd'+suffix)
-        specs('Imax', imax, 'Imax')
-        specs('bn', 'sub!', 'Bulk node connection')
-        specs('Wmin', minW, 'Wmin')
-        specs('Lmin', minL, 'Lmin')
-        specs('PSmin', minPS, 'PSmin')
-        specs('Rspec', rspec, 'Rspec [Ohm/sq]')
-        specs('Rkspec', rkspec, 'Rkspec [Ohm/cont]')
-        specs('Rzspec', rzspec, 'Rzspec [Ohm*m]')
-        specs('tc1', '170e-6', 'Temperature coefficient 1')
-        specs('tc2', '0.4e-6', 'Temperature coefficient 2')
-        specs('PWB', 'No', 'PWell Blockage', ChoiceConstraint(['Yes', 'No']))
-        specs('m', '1', 'Multiplier')
-        specs('trise', '0.0', 'Temp rise from ambient')
-     
-    def setupParams(self, params):
-        self.grid = self.tech.getGridResolution()
-        self.techparams = self.tech.getTechParams()
-        self.epsilon = self.techparams['epsilon1']      
-        
-        self.b = fix(int(params['b']) + self.epsilon)
-        self.w = Numeric(params['w'])*1e6
-        self.l = Numeric(params['l'])*1e6
-        self.ps = Numeric(params['ps'])*1e6
-        #self.resistance = Numeric(params['R'])
-                
-    def genLayout(self):
-        psdlayer = Layer('pSD')
-        textlayer = Layer('TEXT')
-        metlayer = Layer('Metal1')
-        locintlayer = Layer('Cont')
-        sallayer = Layer('SalBlock')
-        contpolylayer = Layer('GatPoly')
-        bodypolylayer = Layer('PolyRes')
-        extBlocklayer = Layer('EXTBlock')  
-        metlayer_pin = Layer('Metal1', 'pin')
-        
-        lcor = 0.0        
-        resshort = 0.0
-        gridnumber = 0.0
-        contoverlay = 0.0
-        contactpush = 0.0
-        li_poly_over = 0.0        
-        
-        internalCode = True
-        Cell = self.__class__.__name__
-        
-        grid = self.techparams['grid']
-        endcap = self.techparams['M1_c1']
-        consize = self.techparams['Cnt_a']
-        conspace = self.techparams['Cnt_b']
-        polyover = self.techparams['Cnt_d']        
-        psdover1 = self.techparams['pSD_n']
-        psdNotch = self.techparams['pSD_b']
-        psdover1 = self.techparams['Rppd_b']        
-        li_salblock = self.techparams['Sal_e']        
-        salover = self.techparams['Sal_c']
-        salspace = self.techparams['Sal_d']
-        psdover = self.techparams['Rppd_b']
-        contbar_min_len = self.techparams['CntB_a1']
-        contbar_poly_over = self.techparams['CntB_d']
-        metover = self.techparams[Cell + '_met_over_cont']        
-        poly_cont_len = consize + polyover # techParam('Cnt_a')+techParam('Cnt_d')            
-        wmin = eng_string_to_float(self.techparams[Cell + '_minW'])*1e6
-        lmin = eng_string_to_float(self.techparams[Cell + '_minL'])*1e6
-        psmin = eng_string_to_float(self.techparams[Cell + '_minPS'])*1e6
-        
-        wcontact = self.w        
-        drawbar = False
-        
-        # Resistor gets 2 Pins, procedure needs '3' to understand '2'
-        dbReplaceProp(self, 'pin#', 3)
-        
-        if internalCode :
-            if wcontact-2*contbar_poly_over + self.epsilon >= contbar_min_len:
-                drawbar = True
-  
-        if psdover1 > psdover: 
-            psdover = psdover1
-
-        # dogbone has to be on grid, so make difference in gridsteps
-        contoverlay = wcontact - self.w
-        if contoverlay > 0:
-            # is dogbone: keep on checking for lay on grid
-            # Distance per side
-            contoverlay = contoverlay/2
-            # gridpoints per side?
-            gridnumber = contoverlay/self.grid
-            gridnumber = round(gridnumber + self.epsilon)
-            # need more gridpoints to lay on grip?
-            if (gridnumber*grid*100) < contoverlay:
-                gridnumber += 1            
-            
-            # set contoverlay to new length
-            contoverlay = gridnumber*grid
-            wcontact = w+2*contoverlay
-        
-        # Insertionpoint for contact is at (0-contoverlay:0)
-        xpos1 = 0-contoverlay
-        ypos1 = 0
-        xpos2 = xpos1+wcontact
-        ypos2 = 0
-        dir = -1
-        stripes = self.b+1
-
-        if self.w < wmin-self.epsilon:
-            self.w = wmin
-            hiGetAttention()
-            print('Width < '+str(wmin))
-    
-        if self.l < lmin-self.epsilon:
-            self.l = lmin
-            hiGetAttention()
-            print('Length < '+str(lmin))
-        
-        if self.ps < psmin-self.epsilon:
-            ps = psmin
-            hiGetAttention()
-            print('poly space < '+str(psmin))
-        
-        # set contacts out of resitor-square?
-        lcor = 0.0
-        lsumnew = 0.0
-        lsumold = 0.0
-        
-        if GridFix(self.ps) < GridFix((salover+salspace)) and stripes>2:
-            contactpush = contactpush+self.w+salover
-            resshort = GridFix((2*contactpush)/stripes)+grid
-            lsumold = self.l*stripes
-            self.l = self.l-resshort
-            lsumnew = self.l*stripes+contactpush*2            
-            lcor = lsumold-lsumnew
-        
-        # Check, if contacts have to be asymmetric
-        # Some cases need to have asym contacts:
-        # 2 stripes and low ps and are not pushed out of resistor
-        if zerop(contactpush) is 1 and self.ps-2*contoverlay <= psmin and onep(self.b) is 1:
-            asymcont = True
-        else :
-            asymcont = False
-
-        # set all parts up to get 0:0 at beginning of resistorbody:
-        ypos1 = ypos1-contactpush*dir
-        ypos2 = ypos2-contactpush*dir
-        
-        # **************************************************************
-        # draw res contact  #1 (bottom)
-        # **************************************************************
-        # draw res contact #1 -> realise Overlap by dogbone to keep burdens, when needed
-        # set xpos1/xpos2 to left for contacts when Stripes>1 and ps<
-
-        if asymcont :
-            xpos1 = xpos1-contoverlay
-            xpos2 = xpos2-contoverlay
-        
-        # **************************************************************
-        # Gat PolyPart of bottom ContactArea
-        # gatpolyarea between salBlock and contact
-        dbCreateRect(self, contpolylayer, Box(xpos1, ypos1+contactpush*dir, xpos2, 
-                                              ypos2+(contactpush+li_salblock)*dir))
-        # gatpolyarea right, left and under contact
-        dbCreateRect(self, contpolylayer, Box(xpos1, ypos1+(contactpush+li_salblock)*dir,
-                                              xpos2, ypos2+(contactpush+poly_cont_len+li_salblock)*dir))
-        # **************************************************************
-        # pSD Part of bottom ContactArea
-        if contactpush == 0.0:
-            dbCreateRect(self, psdlayer, Box(xpos1-psdover, ypos2+contactpush*dir,
-                                             xpos2+psdover, ypos2+(li_salblock+psdover+poly_cont_len+contactpush)*dir))
-        else :
-            dbCreateRect(self,  psdlayer, Box(xpos1-psdover, ypos2+(contactpush-salover+psdover)*dir,
-                                             xpos2+psdover, ypos2+(li_salblock+psdover+poly_cont_len+contactpush)*dir))
-        
-        # **************************************************************
-        # EXTBlock
-        # draw ExtBlock for bottom Cont Area
-        dbCreateRect(self, extBlocklayer, Box(xpos1-psdover, ypos2+contactpush*dir,
-                                              xpos2+psdover, ypos2+(li_salblock+psdover+poly_cont_len+contactpush)*dir))
-
-        # **************************************************************
-        # contact area
-        # number parallel contacts ncont, distance distc:
-        wcon = wcontact-2.0*polyover
-        distc = consize+conspace;        
-        ncont = math.floor((wcon+conspace)/distc + self.epsilon)
-        if ncont < 1: 
-            ncont = 1
-            
-        distr = GridFix((wcon-ncont*distc+conspace)*0.5);
-        
-        # draw contact
-        # block for internal PCell
-        if drawbar :    
-            dbCreateRect(self, locintlayer, Box(xpos1+contbar_poly_over, ypos2+(contactpush+li_salblock+li_poly_over)*dir,
-                                                xpos2-contbar_poly_over, ypos2+(contactpush+consize+li_salblock+li_poly_over)*dir))
-        else :
-            for i in range(int(ncont)):
-                dbCreateRect(self, locintlayer, Box(xpos1+polyover+distr+i*distc, ypos2+(contactpush+li_salblock+li_poly_over)*dir,
-                                                    xpos1+polyover+distr+i*distc+consize, ypos2+(contactpush+consize+li_salblock+li_poly_over)*dir))
-
-        # **************************************************************
-        # Metal and pin
-        ypos1 = ypos2+(contactpush+li_salblock+li_poly_over-metover)*dir
-        ypos2 = ypos2+(contactpush+consize+li_salblock+li_poly_over+metover)*dir
-        # new metal block
-        dbCreateRect(self, metlayer, Box(xpos1+contbar_poly_over-endcap, ypos1, xpos2-contbar_poly_over+endcap, ypos2))
-        
-        MkPin(self, 'PLUS', 1, Box(xpos1+contbar_poly_over-endcap, ypos1, 
-                                   xpos2-contbar_poly_over+endcap, ypos2), metlayer_pin)
-        
-        # set xpos1/xpos2 back to right for resistorbody
-        if asymcont :
-            xpos1=xpos1+contoverlay
-            xpos2=xpos2+contoverlay        
-
-        ypos1 = 0.0 - contactpush*dir
-
-        # **************************************************************
-        # resistorbody:
-        # **************************************************************
-        dir = 1;
-        xpos1 = xpos1+contoverlay
-        xpos2 = xpos1+self.w-contoverlay;
-        ypos2 = ypos1+(self.l-resshort)*dir;
-        # **************************************************************
-        # normal contatcs or outlying contacts?
-        if contactpush > 0 :   # Contacts are out of Resitorsquare->draw rectangle
-            # **************************************************************
-            # draw one salblock and pSD over resistor and bends
-            # Sal Block over stripes and bends
-            dbCreateRect(self, sallayer, Box(xpos1-salover, ypos1-contactpush,
-                                             xpos1+stripes*(self.w+self.ps)-self.ps+salover, ypos1+self.l+self.w+salover))
-        
-            dbCreateRect(self, extBlocklayer, Box(xpos1-salover, ypos1-contactpush,
-                                                  xpos1+stripes*(self.w+self.ps)-self.ps+salover, ypos1+self.l+self.w+salover))
-            # pSD over Stripes and bends
-            # lower bends are salover obove 0.0, need to have psdover, so this psd has to be psdover-salover under 0.0
-            dbCreateRect(self, psdlayer, Box(xpos1-psdover, ypos1-contactpush+salover-psdover,
-                                             xpos1+stripes*(self.w+self.ps)-self.ps+psdover, ypos1+self.l+self.w+psdover))
-            
-            yyy = ypos1-contactpush+salover-psdover
-            # maybe draw extra salblock for longer last stripe
-            if lcor > 0:
-                if oddp(stripes) :   
-                    # draw new rect topright          
-                    dbCreateRect(self, sallayer, Box(xpos1+stripes*(self.w+self.ps)-self.ps-self.w-salover, ypos1+self.l+self.w+salover,
-                                                     xpos1+stripes*(self.w+self.ps)-self.ps+salover, ypos1+self.l+self.w+salover+lcor))
-                    dbCreateRect(self, extBlocklayer, Box(xpos1+stripes*(self.w+self.ps)-self.ps-self.w-salover, ypos1+self.l+self.w+salover,
-                                                          xpos1+stripes*(self.w+self.ps)-self.ps+salover, ypos1+self.l+self.w+salover+lcor))
-                    dbCreateRect(self, psdlayer, Box(xpos1+stripes*(self.w+self.ps)-self.ps-self.w-psdover, ypos1+self.l+self.w+psdover,
-                                                     xpos1+stripes*(self.w+self.ps)-self.ps+psdover, ypos1+self.l+self.w+salover+lcor))
-
-                else :    # draw new rect bottom right
-                    dbCreateRect(self, sallayer, Box(xpos1+stripes*(self.w+self.ps)-self.ps-self.w-salover, ypos1-contactpush-lcor,
-                                                     xpos1+stripes*(self.w+self.ps)-self.ps+salover, ypos1-contactpush))
-                    dbCreateRect(self, extBlocklayer, Box(xpos1+stripes*(self.w+self.ps)-self.ps-self.w-salover, ypos1-contactpush-lcor,
-                                                          xpos1+stripes*(self.w+self.ps)-self.ps+salover, ypos1-contactpush))
-                    dbCreateRect(self, psdlayer, Box(xpos1+stripes*(self.w+self.ps)-self.ps-self.w-psdover, ypos1-contactpush-lcor,
-                                                     xpos1+stripes*(self.w+self.ps)-self.ps+psdover, yyy))
-        else :    #  normal SalBlock, Conts in Resistorsquare
-            # draw salblock and pSD over resistor
-            dbCreateRect(self, sallayer, Box(xpos1-salover, ypos1, xpos1+stripes*(self.w+self.ps)-self.ps+salover, ypos2))      
-            dbCreateRect(self, extBlocklayer, Box(xpos1-salover, ypos1, xpos1+stripes*(self.w+self.ps)-self.ps+salover, ypos2))
-            dbCreateRect(self, psdlayer, Box(xpos1-psdover, ypos1, xpos1+stripes*(self.w+self.ps)-self.ps+psdover, ypos2))
-            
-            if stripes > 1 :  # cover Bends
-                if oddp(stripes) :   # odd stripesnumber
-                    dbCreateRect(self, sallayer, Box(xpos1-salover, ypos2,
-                                                     xpos1+(stripes-1)*(self.w+self.ps)-ps+salover, ypos2+self.w+salover))
-                    dbCreateRect(self, extBlocklayer, Box(xpos1-salover, ypos2,
-                                                          xpos1+(stripes-1)*(self.w+self.ps)-self.ps+salover, ypos2+self.w+salover))
-                    dbCreateRect(self, sallayer, Box(xpos1+self.w+self.ps-salover, ypos1,
-                                                     xpos1+stripes*(self.w+self.ps)-self.ps+salover, ypos1-self.w-salover))
-                    dbCreateRect(self, extBlocklayer, Box(xpos1+self.w+self.ps-salover, ypos1,
-                                                          xpos1+stripes*(self.w+self.ps)-self.ps+salover, ypos1-self.w-salover))
-                    dbCreateRect(self, psdlayer, Box(xpos1-psdover, ypos2-psdover,
-                                                     xpos1+(stripes-1)*(self.w+self.ps)-self.ps+psdover, ypos2+self.w+psdover))
-                    dbCreateRect(self, psdlayer, Box(xpos1+self.w+self.ps-psdover, ypos1,
-                                                     xpos1+stripes*(self.w+self.ps)-self.ps+psdover, ypos1-self.w-psdover))
-                else :  # unodd stripesnumber
-                    dbCreateRect(self, sallayer, Box(xpos1-salover, ypos2, 
-                                                     xpos1+stripes*(self.w+self.ps)-self.ps+salover, ypos2+self.w+salover))
-                    dbCreateRect(self, extBlocklayer, Box(xpos1-salover, ypos2,
-                                                          xpos1+stripes*(self.w+self.ps)-self.ps+salover, ypos2+self.w+salover))
-                    dbCreateRect(self, psdlayer, Box(xpos1-psdover, ypos2, 
-                                                     xpos1+stripes*(self.w+self.ps)-self.ps+psdover, ypos2+self.w+psdover))
-                    
-                    if stripes > 2:
-                        dbCreateRect(self, sallayer, Box(xpos1+self.w+self.ps-salover, ypos1, 
-                                                         xpos1+(stripes-1)*(self.w+self.ps)-self.ps+salover, ypos1-self.w-salover))
-                        dbCreateRect(self, extBlocklayer, Box(xpos1+self.w+self.ps-salover, ypos1, 
-                                                              xpos1+(stripes-1)*(self.w+self.ps)-self.ps+salover, ypos1-self.w-salover))
-                        dbCreateRect(self, psdlayer, Box(xpos1+self.w+self.ps-psdover, ypos1, 
-                                                             xpos1+(stripes-1)*(self.w+self.ps)-self.ps+psdover, ypos1-self.w-psdover))
-                                                             
-        # **************************************************************
-        # Resistorbody GatPoly part
-        for j in range(int(stripes)):
-            i = j + 1
-            xpos2=xpos1+self.w;
-            ypos2=ypos1+self.l*dir;
-            #-----------------
-            # draw long res line
-            if i == 1 :  # first part has to be longer
-                dbCreateRect(self, bodypolylayer, Box(xpos1, ypos1-contactpush*dir, xpos2, ypos2))
-                ihpAddThermalResLayer(self, Box(xpos1, ypos1-contactpush*dir, xpos2, ypos2), True, Cell);
-            else :
-                if i == stripes :   # Last Stripe has to be longer
-                    dbCreateRect(self, bodypolylayer, Box(xpos1, ypos1, xpos2, ypos2+(contactpush+lcor)*dir))              
-                    ihpAddThermalResLayer(self, Box(xpos1, ypos1, xpos2, ypos2+(contactpush+lcor)*dir), True, Cell);
-                else :  # all other stripes
-                    dbCreateRect(self, bodypolylayer, Box(xpos1, ypos1, xpos2, ypos2))        
-                    ihpAddThermalResLayer(self, Box(xpos1, ypos1, xpos2, ypos2), True, Cell);
-      
-            if i < stripes :  # connectionparts
-                ypos1 = ypos2+self.w*dir
-                xpos2 = xpos1+2*self.w+self.ps
-                ypos2 = ypos1-self.w*dir
-                dir = dir*-1;
-                
-                # draw res bend
-                dbCreateRect(self, bodypolylayer, Box(xpos1, ypos1, xpos2, ypos2))      
-                ihpAddThermalResLayer(self, Box(xpos1, ypos1, xpos2, ypos2), True, Cell);
-                
-                xpos1 = xpos1+self.w+self.ps
-                ypos1 = ypos2
-    
-        # **************************************************************
-        # contact area (Top)
-        # **************************************************************
-        if asymcont :  # contact has to be out of symetric
-            xpos1 = xpos1
-            xpos2 = xpos2+contoverlay+contoverlay
-        else :
-            xpos1 = xpos1-contoverlay
-            xpos2 = xpos2+contoverlay
-        # **************************************************************
-        # pSD and SalBlock
-        # between res and cont
-        dbCreateRect(self, contpolylayer, Box(xpos1, ypos2+(lcor+contactpush)*dir,
-                                              xpos2, ypos2+(lcor+contactpush+li_salblock)*dir))
-        # cont
-        dbCreateRect(self, contpolylayer, Box(xpos1, ypos2+(lcor+contactpush+li_salblock)*dir,
-                                              xpos2, ypos2+(lcor+contactpush+poly_cont_len+li_salblock)*dir))
-        # psd
-        dbCreateRect(self, psdlayer, Box(xpos1-psdover, ypos2+(lcor+contactpush)*dir,
-                                         xpos2+psdover, ypos2+(lcor+contactpush+li_salblock+psdover+poly_cont_len)*dir))
-
-        # **************************************************************
-        # EXTBlock
-        # draw ExtBlock for bottom Cont Area
-        dbCreateRect(self, extBlocklayer, Box(xpos1-psdover, ypos2+(lcor+contactpush)*dir,
-                                              xpos2+psdover, ypos2+(lcor+contactpush+li_salblock+psdover+poly_cont_len)*dir))
-
-        # **************************************************************
-        # contacts
-        # codeblock for internal PCel
-        if drawbar :  # can only be in internal code
-            dbCreateRect(self, locintlayer, Box(xpos1+contbar_poly_over, ypos2+(contactpush+li_salblock+li_poly_over+lcor)*dir,
-                                                xpos2-contbar_poly_over, ypos2+(contactpush+consize+li_salblock+li_poly_over+lcor)*dir))
-        else :
-            for i in range(ncont):
-                dbCreateRect(self, locintlayer, Box(xpos1+polyover+distr+i*distc,
-                                                    ypos2+(lcor+contactpush+li_salblock+li_poly_over)*dir,
-                                                    xpos1+polyover+distr+i*distc+consize,
-                                                    ypos2+(lcor+contactpush+consize+li_salblock+li_poly_over)*dir))
-        # **************************************************************
-        # Metal and Pin
-
-        # metal block
-        dbCreateRect(self, metlayer, Box(xpos1+contbar_poly_over-endcap, 
-                                         ypos2+(contactpush+li_salblock+li_poly_over-metover+lcor)*dir,
-                                         xpos2-contbar_poly_over+endcap, 
-                                         ypos2+(contactpush+consize+li_salblock+li_poly_over+metover+lcor)*dir))
-        
-        MkPin(self, 'MINUS', 2, Box(xpos1+contbar_poly_over-endcap, ypos2+(contactpush+li_salblock+li_poly_over-metover+lcor)*dir, 
-                                    xpos2-contbar_poly_over+endcap, ypos2+(contactpush+consize+li_salblock+li_poly_over+metover+lcor)*dir), metlayer_pin)
-
-        # fill notches in pas layer
-        if (self.ps-2.0*psdover < psdNotch) and (self.ps-2.0*psdover > 0.0):
-            if stripes > 1:
-                dbCreateRect(self, psdlayer, Box(self.w+psdover, 0, self.w+self.ps-psdover, -li_salblock-poly_cont_len-psdover))
-    
-            if stripes > 2:
-                xpos1 = xpos1 - self.w - self.ps
-                dbCreateRect(self, psdlayer, Box(xpos1+w+psdover, ypos2, xpos1+self.w+self.ps-psdover, ypos2+dir*(li_salblock+poly_cont_len+psdover)))
-                
-        # **************************************************************
-        # now draw the label
-        # lcalc
-        # create virtuel l for CbResCalc
-        lcalc = (self.l*stripes+contactpush*2+lcor)/stripes
-        resistance = CbResCalc('R', 0, lcalc*1e-6, self.w*1e-6, self.b, self.ps*1e-6, Cell)
-        labeltext = 'rpnd r={0:.3f}'.format(resistance)
-
-        labelpos = Point(self.w/2, self.l/2)
-            
-        # label scaling. Should always fit into bBox of device
-        labelheight = 0.1
-        if self.w > self.l:
-            rot = 'R0'
-        else :
-            rot = 'R90'
-            
-        lbl = dbCreateLabel(self, textlayer, labelpos, labeltext, 'centerCenter', rot, Font.EURO_STYLE, labelheight)
-        lsizex = lbl.bbox.getWidth()
-        lsizey = lbl.bbox.getHeight()
-        scale = min(self.w/lsizex, (self.l+2*poly_cont_len)/lsizey)  
-        #SetSGq(lbl scale height) 
diff --git a/ihp-sg13g2/libs.tech/pycell/rsil_code.py b/ihp-sg13g2/libs.tech/pycell/rsil_code.py
deleted file mode 100644
index 2797a253..00000000
--- a/ihp-sg13g2/libs.tech/pycell/rsil_code.py
+++ /dev/null
@@ -1,339 +0,0 @@
-########################################################################
-#
-# Copyright 2023 IHP PDK Authors
-# 
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-# 
-#    https://www.apache.org/licenses/LICENSE-2.0
-# 
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-########################################################################
-__version__ = '$Revision: #3 $'
-
-from cni.dlo import *
-from geometry import *
-from thermal import *
-from utility_functions import *
-
-import math
-
-class rsil(DloGen):
-
-    @classmethod
-    def defineParamSpecs(self, specs):
-        # define parameters and default values
-        techparams = specs.tech.getTechParams()
-        
-        SG13_TECHNOLOGY = techparams["techName"]
-        suffix = ""
-        if 'SG13G2' in SG13_TECHNOLOGY :
-            suffix = 'G2' 
-        if 'SG13G3' in SG13_TECHNOLOGY :
-            suffix = 'G3'
-        
-        CDFVersion = techparams['CDFVersion']
-        model      = techparams['rsil_model']
-        rspec      = techparams['rsil'+suffix+'_rspec']
-        rkspec     = techparams['rsil_rkspec']
-        rzspec     = techparams['rsil_rzspec']
-        defL       = techparams['rsil_defL']
-        defW       = techparams['rsil_defW']
-        defB       = techparams['rsil_defB']
-        defPS      = techparams['rsil_defPS']
-        minL       = techparams['rsil_minL']
-        minW       = techparams['rsil_minW']
-        minPS      = techparams['rsil_minPS']
-        eps        = techparams['epsilon2']
-        if 'SG13G2' in SG13_TECHNOLOGY :
-            defR   = '17.248' 
-        else :
-            defR   = '16.923'
-        
-        specs('cdf_version', CDFVersion, 'CDF Version')
-        specs('Display', 'Selected', 'Display', ChoiceConstraint(['All', 'Selected']))
-        specs('Calculate', 'l', 'Calculate', ChoiceConstraint(['R', 'w', 'l']))
-        specs('Recommendation', 'No', 'Recommendation', ChoiceConstraint(['Yes', 'No']))
-        specs('model', model, 'Model name')
-        
-        resistance = CbResCalc('R', 0, defL, defW, defB, defPS, 'rsil')
-        specs('R', eng_string(resistance), 'R')
-        
-        specs('w',  defW, 'Width')
-        specs('l',  defL, 'Length')
-        specs('b',  defB, 'Bends')
-        specs('ps', defPS, 'Poly Space')
-        
-        imax = CbResCurrent(Numeric(defW), eps, 'rsil'+suffix)
-        specs('Imax', imax, 'Imax')
-        specs('bn', 'sub!', 'Bulk node connection')
-        specs('Wmin', minW, 'Wmin')
-        specs('Lmin', minL, 'Lmin')
-        specs('PSmin', minPS, 'PSmin')
-        specs('Rspec', rspec, 'Rspec [Ohm/sq]')
-        specs('Rkspec', rkspec, 'Rkspec [Ohm/cont]')
-        specs('Rzspec', rzspec, 'Rzspec [Ohm*m]')
-        specs('tc1', '3100e-6', 'Temperature coefficient 1')
-        specs('tc2', '0.30e-6', 'Temperature coefficient 2')
-        specs('PWB', 'No', 'PWell Blockage', ChoiceConstraint(['Yes', 'No']))
-        specs('m', '1', 'Multiplier')
-        specs('trise', '0.0', 'Temp rise from ambient')
-
-    def setupParams(self, params):
-        # process parameter values entered by user
-        self.params = params
-        self.l = Numeric(params['l'])
-        self.w = Numeric(params['w'])
-        self.b = int(params['b'])
-        self.ps = Numeric(params['ps'])
-        self.resistance = Numeric(params['R'])
-
-    def genLayout(self):
-        l = self.l
-        w = self.w
-        b = self.b
-        ps = self.ps
-        
-        self.techparams = self.tech.getTechParams()
-        self.epsilon = self.techparams['epsilon1']
-        self.grid = self.tech.getGridResolution()         # needed for Dogbone
-
-        contpolylayer = 'GatPoly'
-        bodypolylayer = 'PolyRes'
-        reslayer = 'RES'
-        extBlocklayer = 'EXTBlock'
-        locintlayer = 'Cont'
-        metlayer = 'Metal1'
-        textlayer = 'TEXT'
-        
-        internalCode = True
-        Cell = self.__class__.__name__
-        
-        metover = self.techparams[Cell+'_met_over_cont']
-        consize = self.techparams['Cnt_a']          # min and max size of Cont
-        conspace = self.techparams['Cnt_b']         # min ContSpace
-        polyover = self.techparams['Cnt_d']         # min GatPoly enclosure of Cont
-        li_poly_over = self.techparams['Rsil_b']    # min RES Spacing to Cont
-        ext_over = self.techparams['Rsil_e']        # min EXTBlock enclosure of RES
-        endcap = self.techparams['M1_c1']
-        poly_cont_len = li_poly_over+consize+polyover   # end of RES to end of poly
-        contbar_poly_over = self.techparams['CntB_d']   # min length of LI-Bar
-        contbar_min_len = self.techparams['CntB_a1']    # min length of LI-Bar
-        
-        wmin = eng_string_to_float(self.techparams[Cell+'_minW'])*1e6       # min Width
-        lmin = eng_string_to_float(self.techparams[Cell+'_minL'])*1e6       # Min Length
-        psmin = eng_string_to_float(self.techparams[Cell+'_minPS'])*1e6     # min PolySpace
-     
-        gridnumber = 0.0
-        contoverlay = 0.0
-
-        #dbReplaceProp(pcCV, 'pin#', 'int', 3)
-        l = Numeric(l)*1e6
-        w = Numeric(w)*1e6
-        b = fix(b + self.epsilon)
-        ps = Numeric(ps)*1e6
-        wcontact = w
-        drawbar = False
-        
-        if internalCode == True :
-            if wcontact-2*contbar_poly_over + self.epsilon >= contbar_min_len :
-                drawbar = True
-                
-        if metover < endcap :
-            metover = endcap
-            
-        contoverlay = wcontact - w
-        if contoverlay > 0 :
-            contoverlay = contoverlay/2
-            gridnumber = contoverlay/grid
-            gridnumber = round(gridnumber + self.epsilon)
-            if (gridnumber*grid*100) < contoverlay :
-                gridnumber += 1
-                
-            contoverlay = gridnumber*grid
-            wcontact = w+2*contoverlay
-            
-        # insertion point is at (0,0) - contoverlay
-        xpos1 = 0-contoverlay
-        ypos1 = 0
-        xpos2 = xpos1+wcontact
-        ypos2 = 0
-        Dir = -1
-        stripes = b+1
-        if w < wmin-self.epsilon :
-            w = wmin
-            hiGetAttention()
-            print('Width < '+str(wmin))
-            
-        if l < lmin-self.epsilon :
-            l = lmin
-            hiGetAttention()
-            print('Length < '+str(lmin))
-            
-        if ps < psmin-self.epsilon :
-            ps = psmin
-            hiGetAttention()
-            print('poly space < '+str(psmin))
-            
-        # **************************************************************
-        # draw res contact  #1 (bottom)
-        # **************************************************************
-
-        # set xpos1/xpos2 to left for contacts
-        xpos1 = xpos1-contoverlay
-        xpos2 = xpos2-contoverlay
-        # Gat PolyPart of bottom ContactArea
-        dbCreateRect(self, contpolylayer, Box(xpos1, ypos1, xpos2, ypos2+poly_cont_len*Dir))
-        
-        # number parallel conts: ncont, distance: distc:
-        wcon = wcontact-2.0*polyover
-        distc = consize+conspace
-        ncont = fix((wcon+conspace)/distc + self.epsilon)
-        if ncont < 1 :
-            ncont = 1
-            
-        distr = GridFix((wcon-ncont*distc+conspace)*0.5)
-        
-        # **************************************************************
-        # draw Cont squares or bars of bottom ContactArea
-        # LI and Metal
-        # always dot contacts, autogenerated LI
-        if drawbar == True :
-            dbCreateRect(self, locintlayer, Box(xpos1+contbar_poly_over, ypos2+li_poly_over*Dir, xpos2-contbar_poly_over, ypos2+(consize+li_poly_over)*Dir))
-        else :
-            for i in range(ncont) :
-                dbCreateRect(self, locintlayer, Box(xpos1+polyover+distr+i*distc, ypos2+li_poly_over*Dir, xpos1+polyover+distr+i*distc+consize, ypos2+(consize+li_poly_over)*Dir))
-                
-            
-        # **************************************************************
-        # draw MetalRect and Pin of bottom Contact Area
-        ypos1 = ypos2+(li_poly_over-metover)*Dir
-        ypos2 = ypos2+(consize+li_poly_over+metover)*Dir
-        dbCreateRect(self, metlayer, Box(xpos1+contbar_poly_over-endcap, ypos1, xpos2-contbar_poly_over+endcap, ypos2))
-        MkPin(self, 'PLUS', 1, Box(xpos1+contbar_poly_over-endcap, ypos1, xpos2-contbar_poly_over+endcap, ypos2), metlayer)
-        
-        # **************************************************************
-        # Resistorbody
-        # **************************************************************
-        Dir = 1
-        # set xpos1 & xpos2 correct with contoverlay
-        xpos1 = xpos1+contoverlay
-        ypos1 = 0
-        xpos2 = xpos1+w-contoverlay
-        ypos2 = ypos1+l*Dir
-        
-        # **************************************************************
-        # GatPoly and PolyRes
-        # major structures ahead -> here: not applicable
-        for i in range(1, int(stripes)+1) :
-            xpos2 = xpos1+w
-            ypos2 = ypos1+l*Dir
-            # draw long res line
-            # when dogbone and bends>0 shift long res line to inner contactline
-            if stripes > 1 :
-                if i == 1 :
-                    # fist stripe move to right
-                    xpos1 = xpos1+contoverlay
-                    xpos2 = xpos2+contoverlay
-                    
-            # all vertical ResPoly and GatPoly Parts   
-            dbCreateRect(self, bodypolylayer, Box(xpos1, ypos1, xpos2, ypos2))
-            dbCreateRect(self, reslayer, Box(xpos1, ypos1, xpos2, ypos2))
-            
-            ihpAddThermalResLayer(self, Box(xpos1, ypos1, xpos2, ypos2), True, Cell)
-            
-            # **************************************************************
-            # EXTBlock
-            if i ==  1 :
-                dbCreateRect(self, extBlocklayer, Box(xpos1-ext_over, ypos1, xpos2+ext_over, ypos2))
-            else :
-                dbCreateRect(self, extBlocklayer, Box(xpos1-ext_over, ypos1, xpos2+ext_over, ypos2))
-                 
-            # **************************************************************
-            # hor connection parts
-            if i < stripes : # Connections parts
-                ypos1 = ypos2+w*Dir
-                xpos2 = xpos1+2*w+ps
-                ypos2 = ypos1-w*Dir
-                Dir *= -1
-                # draw res bend
-                dbCreateRect(self, bodypolylayer, Box(xpos1, ypos1, xpos2, ypos2))
-                dbCreateRect(self, reslayer, Box(xpos1, ypos1, xpos2, ypos2))
-                # decide in which direction the part is drawn
-                if oddp(i) :
-                    dbCreateRect(self, extBlocklayer, Box(xpos1-ext_over, ypos1+ext_over, xpos2+ext_over, ypos2-ext_over))
-                else :
-                    dbCreateRect(self, extBlocklayer, Box(xpos1-ext_over, ypos1-ext_over, xpos2+ext_over, ypos2+ext_over))
-                    
-                xpos1 = xpos1+w+ps
-                ypos1 = ypos2
-                
-        
-        # x1,y1,x2,y2,dir are updated, use code from first contact, only pin is different
-        # **************************************************************
-        # draw res contact (Top)
-        # **************************************************************
-        # set x1 x2 to dogbone,:    
-        if stripes >  1 :
-            xpos1 = xpos1
-            xpos2 = xpos2+contoverlay+contoverlay
-        else :
-            xpos1 = xpos1-contoverlay
-            xpos2 = xpos2+contoverlay
-        
-        # **************************************************************
-        #  GatPoly Part    
-        dbCreateRect(self, contpolylayer, Box(xpos1, ypos2, xpos2, ypos2+poly_cont_len*Dir))
-        
-        # draw contacts
-        # LI and Metal
-        # always dot contacts with auto-generated LI
-
-        # **************************************************************
-        # EXTBlock
-        # draw ExtBlock for bottom Cont Area
-        dbCreateRect(self, extBlocklayer, Box(xpos1-ext_over, ypos1, xpos2+ext_over, ypos2+ext_over*Dir+poly_cont_len*Dir))
-        
-        # **************************************************************
-        #  ExtBlock Part
-        # added internal code
-        if drawbar == True :
-            # can only be in internal PCell
-            dbCreateRect(self, locintlayer, Box(xpos1+contbar_poly_over, ypos2+li_poly_over*Dir, xpos2-contbar_poly_over, ypos2+(consize+li_poly_over)*Dir))
-        else :
-            for i in range(ncont) :
-                dbCreateRect(self, locintlayer, Box(xpos1+polyover+distr+i*distc, ypos2+li_poly_over*Dir, xpos1+polyover+distr+i*distc+consize, ypos2+(consize+li_poly_over)*Dir))
-                
-        # **************************************************************
-        #  Metal ans Pin Part
-        # new metal block
-        ypos1 = ypos2+(li_poly_over-metover)*Dir
-        ypos2 = ypos2+(consize+li_poly_over+metover)*Dir
-        dbCreateRect(self, metlayer, Box(xpos1+contbar_poly_over-endcap, ypos1, xpos2-contbar_poly_over+endcap, ypos2))
-        MkPin(self, 'MINUS', 2, Box(xpos1+contbar_poly_over-endcap, ypos1, xpos2-contbar_poly_over+endcap, ypos2), metlayer)
-        
-        # **************************************************************
-        # now draw the label
-        resistance = CbResCalc('R', 0, l*1e-6, w*1e-6, b, ps*1e-6, Cell)
-        labeltext = '{0} r={1:.3f}'.format(Cell, resistance)
-        labelpos = Point(w/2, l/2)
-        
-        # label scaling. Should always fit into bBox of device
-        labelheight = 0.1    # use 1.0 to avoid later multiplication
-        if w > l :
-            rot = 'R0'
-        else :
-            rot = 'R90'
-            
-        # lbl
-        lbl = dbCreateLabel(self, Layer(textlayer, 'drawing'), labelpos, labeltext, 'centerCenter', rot, Font.EURO_STYLE, labelheight) 
-        lsizex = lbl.bbox.getWidth()
-        lsizey = lbl.bbox.getHeight()
-        scale = min(w/lsizex, (l+2*poly_cont_len)/lsizey)
-        #SetSGq(lbl scale height)
diff --git a/ihp-sg13g2/libs.tech/pycell/sealring_code.py b/ihp-sg13g2/libs.tech/pycell/sealring_code.py
deleted file mode 100644
index f9b25191..00000000
--- a/ihp-sg13g2/libs.tech/pycell/sealring_code.py
+++ /dev/null
@@ -1,238 +0,0 @@
-########################################################################
-#
-# Copyright 2024 IHP PDK Authors
-# 
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-# 
-#    https://www.apache.org/licenses/LICENSE-2.0
-# 
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-########################################################################
-__version__ = '$Revision: #3 $'
-
-from cni.dlo import *
-from geometry import *
-from utility_functions import *
-
-import math
-
-class sealring(DloGen):
-
-    @classmethod
-    def defineParamSpecs(cls, specs):   
-        techparams = specs.tech.getTechParams()
-        
-        CDFVersion = techparams['CDFVersion']
-        
-        specs('cdf_version', CDFVersion, 'CDF Version')
-        specs('Display', 'Selected', 'Display', ChoiceConstraint(['All', 'Selected']))
-             
-        specs('l', '150u', 'Length(X-Axis)')
-        specs('w', '150u', 'Width(Y-Axis)')
-        specs('wfill', '30u', 'Filler ring width')
-        specs('addLabel', 'nil', 'Add sub! label', ChoiceConstraint(['nil', 't']))
-        specs('addSlit', 'nil' , 'Add Slit', ChoiceConstraint(['nil', 't']))
-        
-        specs('Lmin', '150u', 'Lmin')
-        specs('Wmin', '150u', 'Wmin')
-
-    def setupParams(self, params):
-        # process parameter values entered by user
-        self.params = params
-        self.l = params['l']
-        self.w = params['w']
-        self.wfill = params['wfill']
-        self.addLabel = params['addLabel']
-        self.addSlit = params['addSlit']
-
-    def genLayout(self):
-        techparams = self.tech.getTechParams()
-        self.techparams = techparams
-        self.epsilon = techparams['epsilon1']
-        
-        l = self.l
-        w = self.w
-        wfill = self.wfill
-        addLabel = self.addLabel
-        addSlit = self.addSlit
-
-        corneroffset = self.techparams['Seal_k']
-        cont_size = self.techparams['Cnt_a']
-        vian_size = self.techparams['Vn_a']
-        TV1_size = self.techparams['TV1_a']
-        TV2_size = self.techparams['TV2_a']
-        
-        # PCell Code
-        
-        w = Numeric(w)*1e6;
-        l = Numeric(l)*1e6;
-        wfill = Numeric(wfill)*1e6;
-        
-        maxMetalWidth = 4.2
-        maxMetalLength = maxMetalWidth * 2
-        corner_width = 4.2
-        metalOffset = 3 + corner_width
-        viaOffset = 5.1 + corner_width
-        corner_length = corner_width * 2
-        corner_starty = 0   # start at the bottom right
-        corner_steps = 4
-        corner_end = 28.2   # end of the bottom right and top left
-        corner_startx = corner_end - (corner_end - corner_width * (corner_steps + 1))
-        metal_startx = corner_end - (corner_end - maxMetalWidth * (corner_steps + 1)) + metalOffset
-        
-        # Sealring Corner
-        layers = ['Activ', 'pSD', 'EdgeSeal', 'Metal1', 'Metal2', 'Metal3', 'Metal4', 'Metal5', 'TopMetal1', 'TopMetal2']
-        vias = ['Cont', 'Via1', 'Via2', 'Via3', 'Via4', 'TopVia1', 'TopVia2']
-        
-        item_list = list()
-        groupId   = list()
-        
-        # Passiv
-        layerobj = dbCreateRect(self, Layer('Passiv', 'drawing'), Box(corner_startx, corner_starty, corner_end, corner_width))
-        item_list.append(layerobj)
-        layerobj = generateCorner(self, corner_startx, corner_starty, corner_width, corner_length, corner_steps, corner_end, 0, 'Passiv')
-        item_list += layerobj
-        groupId = combineLayerAndDelete(self, item_list, groupId, 'Passiv')
-        
-        item_list = []
-        
-        # Metals
-        for layer in layers :
-            layerobj = generateCorner(self, metal_startx, corner_starty, maxMetalWidth, maxMetalLength, corner_steps, corner_end, metalOffset, layer)
-            groupId = combineLayerAndDelete(self, layerobj, groupId, layer)
-           
-        # Vias
-        for layer in vias :
-            if layer == 'TopVia1' :
-                viaWidth = TV1_size
-                viaLength = 4.2
-            elif layer == 'TopVia2' :
-                viaWidth = TV2_size
-                viaLength = 4.2
-            elif layer == 'Cont' :
-                viaWidth = cont_size
-                viaLength = 4.2
-            else :
-                viaWidth = vian_size
-                viaLength = 4.2
-
-            via_startx = corner_end - (corner_end - maxMetalWidth * (corner_steps + 1)) + metalOffset - maxMetalWidth/2-0.1
-            layerobj = dbCreateRect(self, layer, Box(via_startx, viaOffset, via_startx+viaWidth, viaOffset+viaLength))
-            cons(item_list, layerobj)
-            
-            viaGroupId = layerobj
-            
-            for cnt in range(1, corner_steps+1) :
-                layerobj = dbCopyShape(viaGroupId, Point(2 * viaOffset + viaLength * cnt + viaWidth-0.1, -viaLength*(cnt-1)), 'R90')
-                cons(item_list, layerobj)
-                layerobj = dbCopyShape(viaGroupId, Point(-maxMetalWidth*(cnt-1), maxMetalWidth*(cnt-1)-0.1), 'R0')
-                cons(item_list, layerobj)
-
-            layerobj = dbCreateRect(self, layer, Box(via_startx, viaOffset-0.1, corner_end, viaOffset-0.1+viaWidth))
-            cons(item_list, layerobj)
-            layerobj = dbCreateRect(self, layer, Box(viaOffset-0.1, corner_end -  maxMetalWidth/2-0.1, viaOffset-0.1+viaWidth, corner_end))
-            cons(item_list, layerobj)
-            groupId = combineLayerAndDelete(self, item_list, groupId, layer)
-            
-            item_list = []
-
-        # Copy Corners
-        ihpCopyFig(groupId, Point(l, w), 'R180')
-        ihpCopyFig(groupId, Point(l, 0), 'R90')
-        ihpCopyFig(groupId, Point(0, w), 'R270')
-        
-        # end PCell Code
-
-        # Straight Lines
-        dbCreateRect(self, Layer('Passiv', 'drawing'), Box(0.0, corner_end, corner_width, w - corner_end))
-        dbCreateRect(self, Layer('Passiv', 'drawing'), Box(corner_end, 0.0, l - corner_end, corner_width))
-        dbCreateRect(self, Layer('Passiv', 'drawing'), Box(l, corner_end, l - corner_width, w - corner_end))
-        dbCreateRect(self, Layer('Passiv', 'drawing'), Box(corner_end, w, l - corner_end, w - corner_width))
-       
-        for layer in layers :
-            dbCreateRect(self, Layer(layer, 'drawing'), Box(metalOffset, corner_end, metalOffset + corner_width, w - corner_end))
-            dbCreateRect(self, Layer(layer, 'drawing'), Box(corner_end, metalOffset, l - corner_end, metalOffset + corner_width))
-            dbCreateRect(self, Layer(layer, 'drawing'), Box(l - metalOffset, corner_end, l - corner_width - metalOffset, w - corner_end))
-            dbCreateRect(self, Layer(layer, 'drawing'), Box(corner_end, w - metalOffset, l - corner_end, w - corner_width - metalOffset))
-            
-        for layer in vias :
-            if layer == 'TopVia1' :
-                viaWidth = TV1_size
-                viaLength = 4.2
-            elif layer == 'TopVia2' :
-                viaWidth = TV2_size
-                viaLength = 4.2
-            elif layer == 'Cont' :
-                viaWidth = cont_size
-                viaLength = 4.2
-            else :
-                viaWidth = vian_size
-                viaLength = 4.2
-                        
-            dbCreateRect(self, Layer(layer, 'drawing'), Box(viaOffset-0.1, corner_end, viaOffset + viaWidth - 0.1, w - corner_end))
-            dbCreateRect(self, Layer(layer, 'drawing'), Box(corner_end, viaOffset-0.1, l - corner_end, viaOffset + viaWidth - 0.1))
-            dbCreateRect(self, Layer(layer, 'drawing'), Box(l - viaOffset+0.1, corner_end, l - viaWidth - viaOffset + 0.1, w - corner_end))
-            dbCreateRect(self, Layer(layer, 'drawing'), Box(corner_end, w - viaOffset+0.1, l - corner_end, w - viaWidth - viaOffset + 0.1))
-
-
-        if wfill > 0. :    # draw fillers
-            distance_edgeseal = self.techparams['MFil_c']
-            id = dbCreatePolygon(self, 'Metal1', PointList([Point(metalOffset, metalOffset), Point(metalOffset, metalOffset+16.8), Point(metalOffset+16.8, metalOffset)]))
-            # ActFiller and GatFiller
-            distance_edgeseal = self.techparams['GFil_d']   
-            fillerList = DrawFillers(self, Layer('Activ', 'filler'),   metalOffset-wfill, -wfill+0.8+metalOffset,  l-metalOffset, metalOffset-distance_edgeseal-0.8,  3.4, 3.4,  1.6, 1.6, 'h', 1, True)
-            item_list  = DrawFillers(self, Layer('GatPoly', 'filler'), metalOffset-wfill+1, -wfill+metalOffset,  l-metalOffset-1, metalOffset-distance_edgeseal,  1.4, 5,  3.6, 0,  'h', 1, True)
-            fillerList += item_list
-            item_list = DrawFillers(self, Layer('Activ', 'filler'), metalOffset-wfill+1, metalOffset-0.9,  metalOffset-1.8, w+wfill-metalOffset,  3.4, 3.4,  1.6, 1.6,   'v', 1, True)
-            fillerList += item_list
-            item_list = DrawFillers(self, Layer('GatPoly', 'filler'), metalOffset-wfill+0.2, metalOffset+0.1,  metalOffset-1.0, w+wfill-metalOffset-1.0, 5, 1.4, 0, 3.6, 'v', 1, True)
-            fillerList += item_list
-            
-            # M1Filler - M5Filler
-            layers = ['Metal1', 'Metal2', 'Metal3', 'Metal4', 'Metal5']
-            filler_height = self.techparams['MFil_a1']
-            filler_width = self.techparams['MFil_a2']
-            filler_space = 1.2
-            distance_edgeseal = self.techparams['MFil_c']
-            distance_edgeseal = self.techparams['MFil_b']
-            for layer in layers :
-                item_list = DrawFillers(self, Layer(layer, 'filler'), metalOffset-wfill, -wfill+metalOffset, l-metalOffset, metalOffset-distance_edgeseal , filler_width, filler_height, filler_space, filler_space, 'h', 1, True)
-                fillerList += item_list
-                item_list = DrawFillers(self, Layer(layer, 'filler'), metalOffset-wfill, metalOffset+0.8, metalOffset-filler_space, w+wfill-metalOffset, filler_height, filler_width, filler_space, filler_space, 'v', 1, True)
-                fillerList += item_list
-                idlist = DrawFillers(self, Layer(layer, 'filler'), metalOffset, metalOffset, metalOffset+16.8, metalOffset+16.8, filler_height, filler_height, filler_space, filler_space, 'h', 0, True)
-                item_list = dbLayerInside(self, Layer(layer, 'filler'), idlist, id)
-                fillerList += item_list
-                for i in idlist :
-                    dbDeleteObject(i)
-                    
-            # TopMet1Filler   
-            filler_height = self.techparams['TM1Fil_a']
-            filler_width = self.techparams['TM1Fil_a1']
-            filler_space = 3.
-            distance_edgeseal = self.techparams['TM1Fil_c']
-            
-            item_list = DrawFillers(self, Layer('TopMetal1', 'filler'), metalOffset-wfill, -wfill+metalOffset,  l-metalOffset, metalOffset-distance_edgeseal,  filler_width, filler_height, filler_space, filler_space, 'h', 1, True)
-            fillerList += item_list
-            item_list = DrawFillers(self, Layer('TopMetal1', 'filler'), metalOffset-wfill, metalOffset+0.8, metalOffset-filler_space, w+wfill-metalOffset, filler_height, filler_width, filler_space, filler_space, 'v', 1, True)
-            fillerList += item_list
-            item_list = dbCreateRect(self, Layer('TopMetal1', 'filler'), Box(metalOffset, metalOffset, metalOffset+5, metalOffset+5))
-            fillerList.append(item_list)
-            # TopMet2Filler
-            item_list = DrawFillers(self, Layer('TopMetal2', 'filler'), metalOffset-wfill, -wfill+metalOffset,  l-metalOffset, metalOffset-distance_edgeseal,  filler_width, filler_height, filler_space, filler_space,  'h', 1, True)
-            fillerList += item_list
-            item_list = DrawFillers(self, Layer('TopMetal2', 'filler'), metalOffset-wfill, metalOffset+0.8, metalOffset-filler_space, w+wfill-metalOffset, filler_height, filler_width, filler_space, filler_space, 'v', 1, True)
-            fillerList += item_list
-            item_list = dbCreateRect(self, Layer('TopMetal2', 'filler'), Box(metalOffset, metalOffset, metalOffset+5, metalOffset+5))
-            fillerList.append(item_list)
-
-            dbDeleteObject(id)
-            
-            ihpCopyFig(fillerList, Point(l, w), 'R180')
diff --git a/ihp-sg13g2/libs.tech/pycell/utility_functions.py b/ihp-sg13g2/libs.tech/pycell/utility_functions.py
deleted file mode 100644
index 4d93b983..00000000
--- a/ihp-sg13g2/libs.tech/pycell/utility_functions.py
+++ /dev/null
@@ -1,663 +0,0 @@
-########################################################################
-#
-# Copyright 2023 IHP PDK Authors
-# 
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-# 
-#    https://www.apache.org/licenses/LICENSE-2.0
-# 
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-########################################################################
-import math
-import StringIO 
-
-from cni.dlo import Tech, Numeric
-from cni.dlo import Orientation, Location, Layer
-
-nil = 0
-
-tech         = Tech.get('SG13_dev')
-techparams   = tech.getTechParams()
-
-SG13_TECHNOLOGY = tech.name()
-
-SG13_EPSILON = techparams['epsilon1']   # for rounding purposes
-SG13_GRID    = tech.getGridResolution()
-if  SG13_GRID == 0.0 :
-    SG13_GRID = techparams['grid']
-SG13_IGRID   = 1.0/SG13_GRID            # inverse grid
-
-#***********************************************************************************************************************
-# LeQp2
-#***********************************************************************************************************************
-def LeQp2(a, b, eps):
-    
-    if type(a) == str :
-        a = eng_string_to_float(a)
-    if type(b) == str :
-        b = eng_string_to_float(b)
-        
-    return a <= b*(1-eps)
-    
-#***********************************************************************************************************************
-# LeQp23
-#***********************************************************************************************************************
-def LeQp3(a, b, c, eps):
-    
-    if type(a) == str :
-        a = eng_string_to_float(a)
-    if type(b) == str :
-        b = eng_string_to_float(b)
-    if type(c) == str :
-        c = eng_string_to_float(c)
-        
-    return a >= b-c*eps
-
-#***********************************************************************************************************************
-# fix
-#***********************************************************************************************************************    
-def fix(value):
-    if type(value) == float:
-        return int(math.floor(value))
-    else :
-        return value
-        
-#***********************************************************************************************************************
-# floor
-#*********************************************************************************************************************** 
-def floor(value):
-    return int(math.floor(value))
-
-#***********************************************************************************************************************
-# car
-#***********************************************************************************************************************    
-def car(value):
-    return value[0]
-    
-#***********************************************************************************************************************
-# cdr
-#***********************************************************************************************************************    
-def cdr(value):
-    return value[1:]
-
-#***********************************************************************************************************************
-# caar
-#***********************************************************************************************************************
-def caar(value):
-    lw = value.lowerLeft()
-    x1 = lw.getX();
-    return x1
-
-#***********************************************************************************************************************
-# cadar
-#***********************************************************************************************************************    
-def cadar(value):
-    lw = value.lowerLeft()
-    y1 = lw.getY();
-    return y1
-
-#***********************************************************************************************************************
-# caadr
-#***********************************************************************************************************************    
-def caadr(value):
-    ur = value.upperRight()
-    x2 = ur.getX()
-    return x2
-
-#***********************************************************************************************************************
-# cadadr
-#***********************************************************************************************************************    
-def cadadr(value):
-    ur = value.upperRight()
-    y2 = ur.getY()
-    return y2
-
-#***********************************************************************************************************************
-# cons
-#***********************************************************************************************************************  
-def cons(mlist, value):
-    if type(mlist) != list and type(value) is list :
-        value.append(mlist)
-        return value
-        
-    if type(value) is list :
-        mlist = value + mlist
-    else :
-        mlist.insert(0, value)
-        
-    return mlist
-
-#***********************************************************************************************************************
-# oddp
-#***********************************************************************************************************************
-def oddp(value):
-    return bool(value & 1)
-    
-#***********************************************************************************************************************
-# evenp
-#***********************************************************************************************************************
-def evenp(value):
-    return not (bool(value & 1))
-        
-#***********************************************************************************************************************
-# onep
-#***********************************************************************************************************************
-def onep(value):
-    if value == 1:
-        return 1
-    else :
-        return 0
-
-#***********************************************************************************************************************
-# zerop
-#***********************************************************************************************************************
-def zerop(value):
-    if value == 0:
-        return 1
-    else :
-        return 0
-
-#***********************************************************************************************************************
-# sprintf
-#***********************************************************************************************************************
-def sprintf(fmt, *args):
-    buf = StringIO.StringIO()
-    buf.write(fmt % args)
-    return buf.getvalue()
-   
-#***********************************************************************************************************************
-# strcat
-#***********************************************************************************************************************
-def strcat(*args):
-    lst=[]
-    for arg in args:
-        lst.append(arg)
-    return ' '.join(lst)
-
-#***********************************************************************************************************************
-# eng_string
-#***********************************************************************************************************************
-def eng_string( x, sig_figs=3, si=True):
-    """
-    Returns float/int value <x> formatted in a simplified engineering format -
-    using an exponent that is a multiple of 3.
-
-    sig_figs: number of significant figures
-
-    si: if true, use SI suffix for exponent, e.g. k instead of e3, n instead of
-    e-9 etc.
-    """
-    x = float(x)
-    sign = ''
-    if x < 0:
-        x = -x
-        sign = '-'
-    if x == 0:
-        exp = 0
-        exp3 = 0
-        x3 = 0
-    else:
-        exp = int(math.floor(math.log10( x )))
-        exp3 = exp - ( exp % 3)
-        x3 = x / ( 10 ** exp3)
-        x3 = round( x3, -int( math.floor(math.log10( x3 )) - (sig_figs-1)) )
-        if x3 == int(x3): # prevent from displaying .0
-            x3 = int(x3)
-
-    if si and exp3 >= -24 and exp3 <= 24 and exp3 != 0:
-        exp3_text = 'yzafpnum kMGTPEZY'[ exp3 // 3 + 8]
-    elif exp3 == 0:
-        exp3_text = ''
-    else:
-        exp3_text = 'e%s' % exp3
-
-    return ( '%s%s%s') % ( sign, x3, exp3_text)
-
-#***********************************************************************************************************************
-# eng_string_to_float
-#***********************************************************************************************************************
-def eng_string_to_float(x):
-    """
-    Returns float/int value from formatted simplified engineering format
-    <x>
-
-    si: if true, use SI suffix for exponent, e.g. k instead of e3, n instead of
-    e-9 etc.
-    """
-    
-    eng = x[-1:]
-    exp = -1
-
-    for i in 'yzafpnum kMGTPEZY':
-        exp += 1
-        if i is eng:
-            break
-
-    exp = (exp - 8) * 3
-
-    try:
-        int(eng)
-        return eval(x)
-    except:
-        pass
-    
-    number_string = x[:-1]
-    number = 0
-
-    try:
-        number = float(number_string)
-    except:
-        raise ValueError
-
-    return number * (10**exp)
-
-#***********************************************************************************************************************
-# GridFix
-#***********************************************************************************************************************  
-def GridFix(x):
-    return fix(x*SG13_IGRID+SG13_EPSILON)*SG13_GRID         # always use "nice" numbers, as 1/grid may be irrational
-
-#***********************************************************************************************************************
-# LayerGridFix
-#***********************************************************************************************************************  
-def LayerGridFix(layerId, value):
-    if type(layerId) == str :
-        layerId = Layer(layerId)
-        
-    # take grid for used layer from tf
-    grid = layerId.getGridResolution()
-    # to avoid error if grid for used layer was not found
-    if  grid == 0 :
-        grid = SG13_GRID
-        
-    igrid = 1.0/grid    # inverse grid
-    fix(value*igrid+SG13_EPSILON)*grid # always use "nice" numbers, as 1/grid may be irrational
-    
-    return value
-    
-def tog(x):
-    return GridFix(x);
-
-def Snap(x):
-    return GridFix(x);
-
-def nonzero (x):
-    return (abs(x)>=1e-10)
-
-def iszero (x):
-    return (abs(x)<1e-10)
-    
-#***********************************************************************************************************************
-# hiGetAttention - rings the bell in the keyboard or terminal
-#***********************************************************************************************************************
-def hiGetAttention():
-    print('\a')
-    
-#***********************************************************************************************************************
-# strToOrient 
-#***********************************************************************************************************************
-def strToOrient(value):
-    if value == 'R0' :
-        return Orientation.R0
-        
-    if value == 'R90' :
-        return Orientation.R90
-        
-    if value == 'R180' :
-        return Orientation.R180
-        
-    if value == 'R270' :
-        return Orientation.R270
-        
-    if value == 'MY' :
-        return Orientation.MY
-        
-    if value == 'MYR90' :
-        return Orientation.MYR90
-        
-    if value == 'MX' :
-        return Orientation.MX
-        
-    if value == 'MXR90' :
-        return Orientation.MXR90
-
-#***********************************************************************************************************************
-# strToAlignt 
-#***********************************************************************************************************************
-def strToAlignt(value):
-    if value == 'lowerLeft' :
-        return Location.LOWER_LEFT
-        
-    if value == 'centerLeft' :
-        return Location.CENTER_LEFT
-        
-    if value == 'uperLeft' :
-        return Location.UPPER_LEFT
-        
-    if value == 'lowerCenter' :
-        return Location.LOWER_CENTER
-        
-    if value == 'centerCenter' :
-        return Location.CENTER_CENTER
-        
-    if value == 'upperCenter' :
-        return Location.UPPER_CENTER
-        
-    if value == 'lowerCenter' :
-        return Location.LOWER_CENTER
-        
-    if value == 'centerRight' :
-        return Location.CENTER_RIGHT
-        
-    if value == 'upperRight' :
-        return Location.UPPER_RIGHT
-        
-#***********************************************************************************************************************
-# strToBool
-#***********************************************************************************************************************
-def strToBool(val):
-    if val == 'nil' :
-        return False
-    elif val.upper() == 'FALSE' :
-        return False
-    elif val.upper() == 'NO' :
-        return False
-    elif val == '0' :
-        return False
-    elif val == '' :
-        return False
-        
-    return True
-
-#***********************************************************************************************************************
-# checkForYes 
-#***********************************************************************************************************************      
-def checkForYes(value):
-    if type(value) == str :
-        val = value.lower()    
-        if val == 't' or val == '1' or val == 'yes' or val == 'y' :
-            return True
-        else :
-            return False
-    else :
-        if type(value) == bool :
-            return value
-        else :
-            return value != 0
-
-#****************************************************************************************************
-# inductor_minD
-#****************************************************************************************************
-def inductor_minD(w, s, nr, grid):
-    sqrt2 = math.sqrt(2)
-    dmin = 0
-    
-    if nr == 1 :
-         dmin = GridFix((s+w+w)*(1+sqrt2)/2+grid*2)*2
-    elif nr == 2 :
-         dmin = GridFix((GridFix(w/sqrt2+s/2)+GridFix(s*0.4143)+0.02+w)*2*(1+sqrt2)+0.01)
-    elif  nr > 2 :
-        dmin = GridFix(((GridFix(w/sqrt2+s/2)+GridFix(s*0.4143))*2+2*s+4*w)*(1+sqrt2))
-
-    return dmin
-
-#***********************************************************************************************************************
-# resCalc - used for rsil, rhigh, rpnd, rppd
-#***********************************************************************************************************************
-def resCalc(self, cell):
-    
-    global techparams
-    
-    lwd    = Numeric(techparams[cell+'_lwd'])
-    rspec  = Numeric(techparams[cell+'_rspec'])
-    rzspec = Numeric(techparams[cell+'_rzspec'])
-    kappa  = Numeric(techparams[cell+'_kappa'])
-
-    weff = self.w+lwd
-    r = self.l/weff*(self.b+1)*rspec + (2.0/kappa*weff+self.ps)*self.b/weff*rspec + 2.0/self.w*rzspec
-    
-    return round(r*1e03)/1e03
-    
-#****************************************************************************************************
-# CbResCalc
-#****************************************************************************************************
-def CbResCalc(calc, r, l, w, b, ps, cell):
-    
-    global techparams
-    global SG13_TECHNOLOGY
-    
-    suffix = ''
-    if 'SG13G2' in SG13_TECHNOLOGY :
-        suffix = 'G2'
-    if 'SG13G3' in SG13_TECHNOLOGY :
-        suffix = 'G3'
-        
-    rspec  = Numeric(techparams[cell+suffix+'_rspec']) # specific body res. per sq. (float)
-    rkspec = Numeric(techparams[cell+'_rkspec']) # res. per single contact (float)
-    rzspec = Numeric(techparams[cell+'_rzspec']) * 1e6 # transition res. per um width between contact area and body (float)
-    lwd    = Numeric(techparams[cell+suffix+'_lwd']) * 1e6  # line width delta [um] (both edges, positiv value adds to w)
-    kappa  = 1.85 
-    if cell+'_kappa' in techparams :
-        kappa = Numeric(techparams[cell+'_kappa'])
-    poly_over_cont = techparams['Cnt_d'] # strcat(cell '_poly_over_cont'))
-    cont_size = techparams['Cnt_a'] # techGetSpacingRule(tfId 'minWidth' 'Cont')     # size of contact array [um]
-    cont_space = techparams['Cnt_b'] # techGetSpacingRule(tfId 'minSpacing' 'Cont')
-    cont_dist = cont_space+cont_size
-    minW = Numeric(techparams[cell+'_minW'])
-
-    # must check for string arguments and convert to float
-    if type(r) == str :
-         r=Numeric(r)
-    if type(l) == str :
-        l=Numeric(l)
-    if type(w) == str :
-        w=Numeric(w)
-    if type(b) == str :
-        b=Numeric(b)
-    if type(ps) == str :
-        ps=Numeric(ps)
-    
-    if LeQp3(w, minW, '1u', techparams['epsilon1']) :  # 6.8.03 GG: wmin -> minW,HS: Function'LeQp' 28.9.2004
-        w = minW    # avoid divide by zero errors in case of problems ; 21.7.03 GG: eps -> minW
-    
-    w = w * 1e6 # um (needed for contact calculation);HS 4.10.2004
-    l = l * 1e6
-    ps = ps * 1e6
-    
-    # here: all dimensions given in [um]!
-    result = 0
-  
-    if calc == 'R' :
-        weff = w+lwd
-        #result = l/weff*(b+1)*rspec+(2.0/kappa*weff+ps)*b/weff*rspec+2.0/weff*rzspec+2.0*(rkspec/ncont)
-        result = l/weff*(b+1)*rspec+(2.0/kappa*weff+ps)*b/weff*rspec+2.0/w*rzspec
-    elif calc == 'l' :
-        weff = w+lwd
-        #result = (weff*(r-2.0*rkspec/ncont)-b*(2.0/kappa*weff+ps)*rspec-2.0*rzspec)/(rspec*(b+1))*1.0e-6 ; in [m]
-        result = (weff*r-b*(2.0/kappa*weff+ps)*rspec-2.0*weff/w*rzspec)/(rspec*(b+1))*1.0e-6 # in [m]
-    elif calc == 'w' :
-        tmp = r-2*b*rspec/kappa
-        p = (r*lwd-l*(b+1)*rspec-(2*lwd/kappa+ps)*b*rspec-2*rzspec)/tmp
-        q = -2*lwd*rzspec/tmp
-        w = -p/2+sqrt(p*p/4-q)
-        result = Snap(w)*1e-6 #  -> [m]
-
-    return result 
-    
-#***********************************************************************************************************************
-# CbResCurrent
-#***********************************************************************************************************************
-def CbResCurrent(w, eps, cell) : # w must be float in [m], i is given as a string
-    
-    global techparams
-
-    ikspec = Numeric(techparams[cell+'_ikspec'])
-    ipspec = Numeric(techparams[cell+'_ipspec'])
-    poly_over_cont = techparams['Cnt_d'] 
-    cont_size  = techparams['Cnt_a'] 
-    cont_space = techparams['Cnt_b'] 
-    cont_dist = cont_space+cont_size
-
-    ncont = fix( (w*1.0e6-2.0*poly_over_cont+cont_space+eps)/cont_dist ) # max. nr. of contacts across resistor width
-    if ncont < 1 :
-        ncont = 1
-
-    ilim_cont = ikspec*ncont
-    ilim_poly = w*ipspec
-
-    ilim = ilim_poly
-    return str(ilim*1000)+'m'
-    
-#***********************************************************************************************************************
-# CbCapCalc
-#***********************************************************************************************************************
-def CbCapCalc(calc, c, l, w, cell) :
-    
-    global techparams
-    
-    caspec = Numeric(techparams[cell+'_caspec'])*1e-12 # specific cap per sq. [um] (float)
-    cpspec = Numeric(techparams[cell+'_cpspec'])*1e-6  # specific cap. per [um] perimeter (float)
-    lwd    = Numeric(techparams[cell+'_lwd'])          # line width delta [m] ; 30.7.05 GG: fixed
-    
-    if type(c) == str :
-        c = Numeric(c)  
-    if type(l) == str :
-        l = Numeric(l)  
-    if type(w) == str :
-        w = Numeric(w)  
-
-    w = w * 1e6 # um (needed for contact calculation)
-    l = l * 1e6
-    lwd = lwd * 1e6
-    
-    result = 0
-    if calc == 'C' :
-        leff = l+lwd
-        weff = w+lwd
-        result = leff*weff*caspec + 2.0*(leff+weff)*cpspec   
-    elif calc == 'l' :
-        weff = w+lwd
-        result = ((c-2.0*weff*cpspec)/(caspec*weff+2.0*cpspec) - lwd) * 1.0e-6 
-    elif calc == 'w' :
-        leff = l+lwd
-        result = ((c-2.0*leff*cpspec)/(caspec*leff+2.0*cpspec) - lwd) * 1.0e-6 
-    elif calc == 'lw' :
-        result = ( -2.0*cpspec/caspec + sqrt(4.0*cpspec*cpspec/(caspec*caspec) + c/caspec) - lwd) * 1.0e-6 
-    
-    return result
-    
-#***********************************************************************************************************************
-# CbTapCalc
-#***********************************************************************************************************************
-def CbTapCalc(calc, r, l, w, cell) :
-    
-    global techparams
-    
-    raspec = Numeric(techparams[cell+'_raspec'])*1.0e12 ;# specific res per sq. [um] (float)
-    rpspec = Numeric(techparams[cell+'_rpspec'])*1.0e6  ;# specific res. per [um] perimeter (float)
-
-    w = w*1.0e6 ;# um (needed for contact calculation)
-    l = l*1.0e6
-    a = l*w
-    p = 2.0*(l+w)
-    
-    result = 0
-    if calc == 'R' :
-        result = 1.0/(1.0/(raspec/a) + 1.0/(rpspec/p))
-    elif calc == 'l' :
-        result = (raspec*rpspec- r*raspec*2.0*w)/(r*raspec*2.0+r*rpspec*w)*1.0e-6
-    elif calc == 'w' :
-        result = (raspec*rpspec- r*raspec*2.0*l)/(r*raspec*2.0+r*rpspec*l)*1.0e-6
-    elif calc == 'wl' :
-        result = ((-4.0*r*raspec + sqrt(16.0*r*r*raspec*raspec + 4.0*r*rpspec*rpspec*raspec))/(2.0*r*rpspec))*1.0e-6
-    
-    return result
-    
-#***********************************************************************************************************************
-# CbDiodeCalc
-#***********************************************************************************************************************
-def CbDiodeCalc(calc, a, l, w, cell) :
-    
-    global techparams
-    
-    minL = Numeric(techparams[cell+'_minL'])
-    minW = Numeric(techparams[cell+'_minW'])
-    
-    if calc != 'w' and calc != 'wl' :
-        if w < minW :
-            print("w {0} too small\n".format(w))
-    if calc != 'l' and calc != 'wl' :
-        if l < minL :
-            print("l {0} too small\n".format(l))
-    
-    if type(a) == str :
-        a = Numeric(a)  
-    if type(l) == str :
-        l = Numeric(l)  
-    if type(w) == str :
-        w = Numeric(w) 
-    
-    w = w*1.0e6 # um (needed for contact calculation)
-    l = l*1.0e6
-    
-    result = 0
-    if calc == 'a' :
-        result = w*l*1.0e-12
-    elif calc == 'p' :
-        result = (w+l)*2.0e-6
-    elif calc == 'l' :
-        result = (a/w)*1.0e6
-    elif calc == 'w' :
-        result = (a/l)*1.0e6
-    elif calc == 'wl' :
-        result = sqrt(a)
-        
-    return result
-    
-def listlen(mlist) :
-    return len(mlist)
-
-def isOdd(x) :
-    if x == 0 :
-        return 0
-        
-    if (x % 2) != 0 :
-        return 1
-        
-    return 0
-        
-def isEven(x) :
-    if x == 0 :
-        return 1
-    
-    if (x % 2) == 0 :
-        return 1
-        
-    return 0
-
-def is_list(x) :
-    if type (x) is list :
-        return 1
-        
-    return 0
-
-def min2(a, b) :
-    return min(a, b)
-
-def max2(a, b) :
-    return max(a, b)
-
-def pylist(*args) :
-    mlist = list()
-    
-    for key in args :
-        mlist.append(key)
-        
-    return mlist
diff --git a/ihp-sg13g2/libs.tech/qucs/README.md b/ihp-sg13g2/libs.tech/qucs/README.md
index 83438728..7cc5b70a 100644
--- a/ihp-sg13g2/libs.tech/qucs/README.md
+++ b/ihp-sg13g2/libs.tech/qucs/README.md
@@ -1,10 +1,11 @@
-# Using Qucs-s with IHP-Open-PDK
+# Using Qucs-S with IHP-Open-PDK
 
-In order to work with Qucs-s run the following script:
+> make sure that you have set up the `PDK_ROOT` env variable
 
-````
-python3 install.py
-````
+In order to work with Qucs-S run the following script:
+```
+./install.py
+```
 
-Then run Qucs-s and try out the examples. 
+Then run Qucs-S and try out the examples. 
 
diff --git a/ihp-sg13g2/libs.tech/qucs/examples/README.md b/ihp-sg13g2/libs.tech/qucs/examples/README.md
new file mode 100644
index 00000000..15bdccf0
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/qucs/examples/README.md
@@ -0,0 +1,9 @@
+####################################################
+				IMPORTANT
+####################################################
+
+In order to use the SG13G2 PDK sample schematics, you must add the SG13G2 PDK library to the Qucs-S subcircuit search path:
+
+1) Go to File ->Application Settings ...
+2) Click on the "Locations" tab
+3) On the bottom, click on the "Add Path With Subfolders" button and select the SG13G2 PDK library folder ($HOME/[.qucs|QucsWorkspace]/user_lib)
diff --git a/ihp-sg13g2/libs.tech/qucs/examples/ac_mim_cap.sch b/ihp-sg13g2/libs.tech/qucs/examples/ac_mim_cap.sch
index ba7eb5bc..4d6ac9d3 100644
--- a/ihp-sg13g2/libs.tech/qucs/examples/ac_mim_cap.sch
+++ b/ihp-sg13g2/libs.tech/qucs/examples/ac_mim_cap.sch
@@ -1,6 +1,6 @@
 <Qucs Schematic 24.2.0>
 <Properties>
-  <View=-603,-96,2362,1375,0.827406,84,45>
+  <View=52,-2,1670,973,1.22451,269,33>
   <Grid=10,10,1>
   <DataSet=ac_mim_cap.dat>
   <DataDisplay=ac_mim_cap.dpl>
@@ -16,18 +16,17 @@
 <Symbol>
 </Symbol>
 <Components>
-  <INCLSCR INCLSCR1 1 120 50 -60 16 0 0 ".LIB ../../.qucs/IHP-Open-PDK-main/ihp-sg13g2/libs.tech/ngspice/models/cornerRES.lib res_typ\n.LIB ../../.qucs/IHP-Open-PDK-main/ihp-sg13g2/libs.tech/ngspice/models/cornerCAP.lib cap_typ\n.control\n\n.endc" 1 "" 0 "" 0>
+  <INCLSCR INCLSCR1 1 120 50 -60 16 0 0 "\n.LIB cornerRES.lib res_typ\n.LIB cornerCAP.lib cap_typ\n" 1 "" 0 "" 0>
   <.AC AC1 1 70 190 0 40 0 0 "log" 1 "100k" 1 "300 GHz" 1 "101" 1 "no" 0>
   <GND * 1 360 650 0 0 0 0>
   <Vac V1 1 70 570 18 -26 0 1 "1 V" 1 "1 kHz" 0 "0" 0 "0" 0 "0" 0 "0" 0>
   <GND * 1 70 650 0 0 0 0>
-  <Lib cap_cmim1 1 360 590 -120 -49 0 0 "/home/herman/.qucs/user_lib/IHP_PDK_basic_components" 0 "cap_cmim" 0 "70u" 1 "70u" 1>
   <GND * 1 360 930 0 0 0 0>
   <GND * 1 330 930 0 0 0 0>
-  <Lib cap_rfcmim1 1 370 860 50 -16 0 0 "/home/herman/.qucs/user_lib/IHP_PDK_basic_components" 0 "cap_rfcmim" 0 "70u" 1 "70u" 1>
-  <Lib rhigh1 1 240 500 -26 -122 0 1 "/home/herman/.qucs/user_lib/IHP_PDK_basic_components" 0 "rhigh" 0 "1.0u" 1 "10u" 1 "1" 1>
-  <Lib rhigh2 1 240 780 -26 -122 0 1 "/home/herman/.qucs/user_lib/IHP_PDK_basic_components" 0 "rhigh" 0 "1.0u" 1 "10u" 1 "1" 1>
-  <Lib rhigh3 1 -360 600 50 -26 0 0 "/home/herman/.qucs/user_lib/IHP_PDK_basic_components" 0 "rhigh" 0 "1.0u" 1 "0.5u" 1 "1" 1>
+  <Lib cap_rfcmim1 1 370 860 50 -16 0 0 "<userhome>/<qucs_workspace>/user_lib/IHP_PDK_basic_components" 0 "cap_rfcmim" 0 "70u" 1 "70u" 1>
+  <Lib rhigh1 1 240 500 -26 -122 0 1 "<userhome>/<qucs_workspace>/user_lib/IHP_PDK_basic_components" 0 "rhigh" 0 "1.0u" 1 "10u" 1 "1" 1>
+  <Lib rhigh2 1 240 780 -26 -122 0 1 "<userhome>/<qucs_workspace>/user_lib/IHP_PDK_basic_components" 0 "rhigh" 0 "1.0u" 1 "10u" 1 "1" 1>
+  <Lib cap_cmim1 1 360 590 -120 -49 0 0 "<userhome>/<qucs_workspace>/user_lib/IHP_PDK_basic_components" 0 "cap_cmim" 0 "70u" 1 "70u" 1>
 </Components>
 <Wires>
   <360 610 360 650 "" 0 0 0 "">
diff --git a/ihp-sg13g2/libs.tech/qucs/examples/dc_diode_op.sch b/ihp-sg13g2/libs.tech/qucs/examples/dc_diode_op.sch
index d642d5b5..f6097240 100644
--- a/ihp-sg13g2/libs.tech/qucs/examples/dc_diode_op.sch
+++ b/ihp-sg13g2/libs.tech/qucs/examples/dc_diode_op.sch
@@ -1,6 +1,6 @@
 <Qucs Schematic 24.2.0>
 <Properties>
-  <View=-86,-4,1624,1075,1.25348,0,181>
+  <View=-39,-4,1577,932,0.971123,0,1>
   <Grid=10,10,1>
   <DataSet=dc_diode_op.dat>
   <DataDisplay=dc_diode_op.dpl>
@@ -19,14 +19,13 @@
   <.SW SW1 1 90 280 0 68 0 0 "DC1" 1 "lin" 1 "V2" 1 "0" 1 "1" 1 "301" 1 "false" 0>
   <GND * 1 270 840 0 0 0 0>
   <IProbe Pr1 1 270 640 -37 -26 0 3>
-  <INCLSCR INCLSCR1 1 130 50 -60 16 0 0 ".INCLUDE ../../.qucs/IHP-Open-PDK-main/ihp-sg13g2/libs.tech/ngspice/models/diodes.lib\n.control\npre_osdi ../../.qucs/psp103_nqs.osdi\n.endc" 1 "" 0 "" 0>
-  <.DC DC1 1 90 180 0 41 0 0 "26.85" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "no" 0 "150" 0 "no" 0 "none" 0 "CroutLU" 0>
+  <INCLSCR INCLSCR1 1 130 50 -60 16 0 0 "\n.INCLUDE diodes.lib\n" 1 "" 0 "" 0>
   <GND * 1 120 840 0 0 0 0>
   <Vdc V2 1 120 750 18 -26 0 1 "1 V" 1>
-  <Lib dantenna1 1 270 750 40 -16 0 0 "/home/herman/.qucs/user_lib/IHP_PDK_nonlinear_components" 0 "dantenna" 0 "8u" 1 "8u" 1>
   <GND * 1 470 840 0 0 0 0>
   <IProbe Pr2 1 470 640 -37 -26 0 3>
-  <Lib dpantenna1 1 470 750 40 -16 0 0 "/home/herman/.qucs/user_lib/IHP_PDK_nonlinear_components" 0 "dpantenna" 0 "16u" 1 "16u" 1>
+  <Lib dpantenna1 1 470 750 40 -16 0 0 "<userhome>/<qucs_workspace>/user_lib/IHP_PDK_nonlinear_components" 0 "dpantenna" 0 "16u" 1 "16u" 1>
+  <Lib dantenna1 1 270 750 40 -16 0 0 "<userhome>/<qucs_workspace>/user_lib/IHP_PDK_nonlinear_components" 0 "dantenna" 0 "8u" 1 "8u" 1>
 </Components>
 <Wires>
   <270 590 270 610 "" 0 0 0 "">
diff --git a/ihp-sg13g2/libs.tech/qucs/examples/dc_hbt_13g2.sch b/ihp-sg13g2/libs.tech/qucs/examples/dc_hbt_13g2.sch
index 3c75968c..da2089e0 100644
--- a/ihp-sg13g2/libs.tech/qucs/examples/dc_hbt_13g2.sch
+++ b/ihp-sg13g2/libs.tech/qucs/examples/dc_hbt_13g2.sch
@@ -1,6 +1,6 @@
 <Qucs Schematic 24.2.0>
 <Properties>
-  <View=-201,-94,2082,1128,0.651338,0,0>
+  <View=-108,16,1637,1026,0.89901,0,0>
   <Grid=10,10,1>
   <DataSet=dc_hbt_13g2.dat>
   <DataDisplay=dc_hbt_13g2.dpl>
@@ -16,8 +16,6 @@
 <Symbol>
 </Symbol>
 <Components>
-  <INCLSCR INCLSCR1 1 160 70 -60 16 0 0 ".LIB ../../.qucs/IHP-Open-PDK-main/ihp-sg13g2/libs.tech/ngspice/models/cornerHBT.lib hbt_typ\n" 1 "" 0 "" 0>
-  <.DC DC1 1 40 160 0 46 0 0 "26.85" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "no" 0 "150" 0 "no" 0 "none" 0 "CroutLU" 0>
   <.SW SW1 1 50 250 0 77 0 0 "DC1" 1 "lin" 1 "V2" 1 "0" 1 "1.5" 1 "301" 1 "false" 0>
   <.SW SW2 1 50 470 0 77 0 0 "SW1" 1 "lin" 1 "I1" 1 "0" 1 "5u" 1 "10" 1 "false" 0>
   <IProbe Pr1 1 170 740 -37 -26 0 3>
@@ -27,7 +25,8 @@
   <GND * 1 290 960 0 0 0 0>
   <GND * 1 70 960 0 0 0 0>
   <Idc I1 1 70 910 18 -26 0 1 "0" 1>
-  <Lib npn13G1 1 170 850 10 64 0 0 "/home/herman/.qucs/user_lib/IHP_PDK_nonlinear_components" 0 "npn13G2" 0 "1" 1>
+  <Lib npn13G1 1 170 850 10 64 0 0 "<userhome>/<qucs_workspace>/user_lib/IHP_PDK_nonlinear_components" 0 "npn13G2" 0 "1" 1>
+  <INCLSCR INCLSCR1 1 100 100 -60 16 0 0 ".LIB cornerHBT.lib hbt_typ\n" 1 "" 0 "" 0>
 </Components>
 <Wires>
   <170 770 170 800 "" 0 0 0 "">
diff --git a/ihp-sg13g2/libs.tech/qucs/examples/dc_hv_nmos.sch b/ihp-sg13g2/libs.tech/qucs/examples/dc_hv_nmos.sch
index 812f3d1e..7f6cf50d 100644
--- a/ihp-sg13g2/libs.tech/qucs/examples/dc_hv_nmos.sch
+++ b/ihp-sg13g2/libs.tech/qucs/examples/dc_hv_nmos.sch
@@ -1,6 +1,6 @@
 <Qucs Schematic 24.2.0>
 <Properties>
-  <View=-27,-4,1565,985,0.944385,0,0>
+  <View=-39,-4,1577,932,0.971123,0,1>
   <Grid=10,10,1>
   <DataSet=dc_hv_nmos.dat>
   <DataDisplay=dc_hv_nmos.dpl>
@@ -24,10 +24,10 @@
   <GND * 1 450 840 0 0 0 0>
   <Vdc V1 1 160 800 18 -26 0 1 "1 V" 1>
   <GND * 1 160 840 0 0 0 0>
-  <INCLSCR INCLSCR1 1 130 50 -60 16 0 0 ".LIB ../../.qucs/IHP-Open-PDK-main/ihp-sg13g2/libs.tech/ngspice/models/cornerMOShv.lib mos_tt\n.control\npre_osdi ../../.qucs/psp103_nqs.osdi\n.endc" 1 "" 0 "" 0>
+  <INCLSCR INCLSCR1 1 130 50 -60 16 0 0 "\n.LIB cornerMOShv.lib mos_tt\n" 1 "" 0 "" 0>
   <.DC DC1 1 90 180 0 41 0 0 "26.85" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "no" 0 "150" 0 "no" 0 "none" 0 "CroutLU" 0>
   <.SW SW2 1 260 280 0 68 0 0 "SW1" 1 "lin" 1 "V1" 1 "0" 1 "0.9" 1 "10" 1 "false" 0>
-  <Lib sg13_hv_nmos1 1 270 750 55 -121 0 0 "/home/herman/.qucs/user_lib/IHP_PDK_nonlinear_components" 0 "sg13_hv_nmos" 0 "1.0u" 1 "0.45u" 1 "1" 1 "1" 1 "0" 0 "0" 0 "0" 0 "0" 0 "0" 0 "0.346e-6" 0 "0.38e-6" 0 "0.15e-6" 0 "0" 0 "1" 0>
+  <Lib sg13_hv_nmos1 1 270 750 55 -121 0 0 "<userhome>/<qucs_workspace>/user_lib/IHP_PDK_nonlinear_components" 0 "sg13_hv_nmos" 0 "1.0u" 1 "0.45u" 1 "1" 1 "1" 1 "0" 0 "0" 0 "0" 0 "0" 0 "0" 0 "0.346e-6" 0 "0.38e-6" 0 "0.15e-6" 0 "0" 0 "1" 0>
 </Components>
 <Wires>
   <270 810 270 840 "" 0 0 0 "">
diff --git a/ihp-sg13g2/libs.tech/qucs/examples/dc_hv_pmos.sch b/ihp-sg13g2/libs.tech/qucs/examples/dc_hv_pmos.sch
index 3b89f616..125a7fac 100644
--- a/ihp-sg13g2/libs.tech/qucs/examples/dc_hv_pmos.sch
+++ b/ihp-sg13g2/libs.tech/qucs/examples/dc_hv_pmos.sch
@@ -1,6 +1,6 @@
 <Qucs Schematic 24.2.0>
 <Properties>
-  <View=-85,-4,1583,976,0.90102,0,0>
+  <View=-98,-4,1595,976,0.926531,0,0>
   <Grid=10,10,1>
   <DataSet=dc_hv_pmos.dat>
   <DataDisplay=dc_hv_pmos.dpl>
@@ -26,8 +26,8 @@
   <Vdc V2 1 370 820 -61 -26 0 3 "1 V" 1>
   <Vdc V1 1 80 870 -61 -26 0 3 "1 V" 1>
   <IProbe Pr1 1 190 710 16 -26 0 1>
-  <INCLSCR INCLSCR1 1 130 50 -60 16 0 0 ".LIB ../../.qucs/IHP-Open-PDK-main/ihp-sg13g2/libs.tech/ngspice/models/cornerMOShv.lib mos_tt\n.control\npre_osdi ../../.qucs/psp103_nqs.osdi\n.endc" 1 "" 0 "" 0>
-  <Lib sg13_hv_pmos1 1 190 820 45 -101 0 0 "/home/herman/.qucs/user_lib/IHP_PDK_nonlinear_components" 0 "sg13_hv_pmos" 0 "1.0u" 1 "0.45u" 1 "1" 0 "1" 1 "0" 0 "0" 0 "0" 0 "0" 0 "0" 0 "0.346e-6" 0 "0.38e-6" 0 "0.15e-6" 0 "0" 0 "1" 0>
+  <INCLSCR INCLSCR1 1 130 50 -60 16 0 0 "\n.LIB cornerMOShv.lib mos_tt\n" 1 "" 0 "" 0>
+  <Lib sg13_hv_pmos1 1 190 820 45 -101 0 0 "<userhome>/<qucs_workspace>/user_lib/IHP_PDK_nonlinear_components" 0 "sg13_hv_pmos" 0 "1.0u" 1 "0.45u" 1 "1" 0 "1" 1 "0" 0 "0" 0 "0" 0 "0" 0 "0" 0 "0.346e-6" 0 "0.38e-6" 0 "0.15e-6" 0 "0" 0 "1" 0>
 </Components>
 <Wires>
   <190 880 190 910 "" 0 0 0 "">
diff --git a/ihp-sg13g2/libs.tech/qucs/examples/dc_lv_nmos.sch b/ihp-sg13g2/libs.tech/qucs/examples/dc_lv_nmos.sch
index a94d3767..3bae31ad 100644
--- a/ihp-sg13g2/libs.tech/qucs/examples/dc_lv_nmos.sch
+++ b/ihp-sg13g2/libs.tech/qucs/examples/dc_lv_nmos.sch
@@ -1,6 +1,6 @@
 <Qucs Schematic 24.2.0>
 <Properties>
-  <View=-6,-4,1543,906,0.97033,0,0>
+  <View=12,36,1515,906,1.04368,0,0>
   <Grid=10,10,1>
   <DataSet=dc_lv_nmos.dat>
   <DataDisplay=dc_lv_nmos.dpl>
@@ -24,10 +24,9 @@
   <GND * 1 450 840 0 0 0 0>
   <Vdc V1 1 160 800 18 -26 0 1 "1 V" 1>
   <GND * 1 160 840 0 0 0 0>
-  <INCLSCR INCLSCR1 1 130 50 -60 16 0 0 ".LIB ../../.qucs/IHP-Open-PDK-main/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt\n.control\npre_osdi ../../.qucs/psp103_nqs.osdi\n.endc" 1 "" 0 "" 0>
-  <.DC DC1 1 90 180 0 41 0 0 "26.85" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "no" 0 "150" 0 "no" 0 "none" 0 "CroutLU" 0>
   <.SW SW2 1 260 280 0 68 0 0 "SW1" 1 "lin" 1 "V1" 1 "0" 1 "0.9" 1 "10" 1 "false" 0>
-  <Lib sg13_lv_nmos1 1 270 750 55 -121 0 0 "/home/herman/.qucs/user_lib/IHP_PDK_nonlinear_components" 0 "sg13_lv_nmos" 0 "0.35u" 1 "0.34u" 1 "1" 1 "1" 1 "0" 0 "0" 0 "0" 0 "0" 0 "0" 0 "0.346e-6" 0 "0.38e-6" 0 "0.15e-6" 0 "0" 0 "1" 0>
+  <Lib sg13_lv_nmos1 1 270 750 55 -121 0 0 "<userhome>/<qucs_workspace>/user_lib/IHP_PDK_nonlinear_components" 0 "sg13_lv_nmos" 0 "0.35u" 1 "0.34u" 1 "1" 1 "1" 1 "0" 0 "0" 0 "0" 0 "0" 0 "0" 0 "0.346e-6" 0 "0.38e-6" 0 "0.15e-6" 0 "0" 0 "1" 0>
+  <INCLSCR INCLSCR1 1 120 90 -60 16 0 0 ".LIB cornerMOSlv.lib mos_tt\n" 1 "" 0 "" 0>
 </Components>
 <Wires>
   <270 810 270 840 "" 0 0 0 "">
@@ -43,8 +42,8 @@
   <160 830 160 840 "" 0 0 0 "">
 </Wires>
 <Diagrams>
-  <Rect 602 852 868 643 3 #c0c0c0 1 00 1 0 0.1 2 1 0 5e-05 0.000381884 1 -1 0.2 1 315 0 225 1 0 0 "" "" "">
-	<"ngspice/sw1.i(pr1)" #0000ff 0 3 0 0 0>
+  <Rect 602 852 868 643 3 #c0c0c0 1 00 1 0 0.5 10 1 -0.1 0.1 1 1 -1 0.2 1 315 0 225 1 0 0 "" "" "">
+	<"ngspice/i(pr1)" #ff00ff 0 3 0 0 0>
   </Rect>
 </Diagrams>
 <Paintings>
diff --git a/ihp-sg13g2/libs.tech/qucs/examples/dc_lv_pmos.sch b/ihp-sg13g2/libs.tech/qucs/examples/dc_lv_pmos.sch
index 5ce30f40..614d5af0 100644
--- a/ihp-sg13g2/libs.tech/qucs/examples/dc_lv_pmos.sch
+++ b/ihp-sg13g2/libs.tech/qucs/examples/dc_lv_pmos.sch
@@ -1,6 +1,6 @@
 <Qucs Schematic 24.2.0>
 <Properties>
-  <View=-85,-4,1583,976,0.90102,0,0>
+  <View=-98,-4,1595,976,0.926531,0,0>
   <Grid=10,10,1>
   <DataSet=dc_lv_pmos.dat>
   <DataDisplay=dc_lv_pmos.dpl>
@@ -26,8 +26,8 @@
   <Vdc V2 1 370 820 -61 -26 0 3 "1 V" 1>
   <Vdc V1 1 80 870 -61 -26 0 3 "1 V" 1>
   <IProbe Pr1 1 190 710 16 -26 0 1>
-  <INCLSCR INCLSCR1 1 130 50 -60 16 0 0 ".LIB ../../.qucs/IHP-Open-PDK-main/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt\n.control\npre_osdi ../../.qucs/psp103_nqs.osdi\n.endc" 1 "" 0 "" 0>
-  <Lib sg13_lv_pmos1 1 190 820 45 -101 0 0 "/home/herman/.qucs/user_lib/IHP_PDK_nonlinear_components" 0 "sg13_lv_pmos" 0 "0.35u" 1 "0.34u" 1 "1" 0 "1" 1 "0" 0 "0" 0 "0" 0 "0" 0 "0" 0 "0.346e-6" 0 "0.38e-6" 0 "0.15e-6" 0 "0" 0 "1" 0>
+  <INCLSCR INCLSCR1 1 130 50 -60 16 0 0 "\n.LIB cornerMOSlv.lib mos_tt\n" 1 "" 0 "" 0>
+  <Lib sg13_lv_pmos1 1 190 820 45 -101 0 0 "<userhome>/<qucs_workspace>/user_lib/IHP_PDK_nonlinear_components" 0 "sg13_lv_pmos" 0 "0.35u" 1 "0.34u" 1 "1" 0 "1" 1 "0" 0 "0" 0 "0" 0 "0" 0 "0" 0 "0.346e-6" 0 "0.38e-6" 0 "0.15e-6" 0 "0" 0 "1" 0>
 </Components>
 <Wires>
   <190 880 190 910 "" 0 0 0 "">
diff --git a/ihp-sg13g2/libs.tech/qucs/examples/resistors.sch b/ihp-sg13g2/libs.tech/qucs/examples/resistors.sch
index 136db237..5bfcdd88 100644
--- a/ihp-sg13g2/libs.tech/qucs/examples/resistors.sch
+++ b/ihp-sg13g2/libs.tech/qucs/examples/resistors.sch
@@ -1,6 +1,6 @@
 <Qucs Schematic 24.2.0>
 <Properties>
-  <View=-288,-4,1765,1119,1.04363,0,0>
+  <View=-143,-4,1620,1016,0.890196,0,0>
   <Grid=10,10,1>
   <DataSet=resistors.dat>
   <DataDisplay=resistors.dpl>
@@ -22,28 +22,27 @@
 </Symbol>
 <Components>
   <.SW SW1 1 90 280 0 68 0 0 "DC1" 1 "lin" 1 "V2" 1 "0" 1 "10" 1 "301" 1 "false" 0>
-  <INCLSCR INCLSCR1 1 130 50 -60 16 0 0 ".LIB ../../.qucs/IHP-Open-PDK-main/ihp-sg13g2/libs.tech/ngspice/models/cornerRES.lib res_wcs\n.control\nop\n.endc" 1 "" 0 "" 0>
+  <INCLSCR INCLSCR1 1 130 50 -60 16 0 0 "\n.LIB cornerRES.lib res_wcs\n" 1 "" 0 "" 0>
   <Vdc V2 1 110 800 18 -26 0 1 "1 V" 1>
   <GND * 1 250 950 0 0 0 0>
   <GND * 1 110 950 0 0 0 0>
   <IProbe Pr1 1 180 690 -26 16 0 0>
   <GND * 1 420 950 0 0 0 0>
-  <Lib rppd2 1 580 1060 -110 -196 0 0 "/home/herman/.qucs/user_lib/IHP_PDK_basic_components" 0 "rppd" 0 "10u" 1 "25u" 1 "2" 1>
-  <Lib rsil3 1 250 750 50 -26 0 0 "/home/herman/.qucs/user_lib/IHP_PDK_basic_components" 0 "rsil" 0 "10u" 1 "40u" 1 "1" 1>
-  <Lib rppd1 1 580 920 -110 -196 0 0 "/home/herman/.qucs/user_lib/IHP_PDK_basic_components" 0 "rppd" 0 "10u" 1 "25u" 1 "1" 1>
-  <Lib rsil2 1 250 890 50 -26 0 0 "/home/herman/.qucs/user_lib/IHP_PDK_basic_components" 0 "rsil" 0 "10u" 1 "40u" 1 "1" 1>
+  <Lib rppd2 1 580 1060 -110 -196 0 0 "<userhome>/<qucs_workspace>/user_lib/IHP_PDK_basic_components" 0 "rppd" 0 "10u" 1 "25u" 1 "2" 1>
+  <Lib rsil3 1 250 750 50 -26 0 0 "<userhome>/<qucs_workspace>/user_lib/IHP_PDK_basic_components" 0 "rsil" 0 "10u" 1 "40u" 1 "1" 1>
+  <Lib rppd1 1 580 920 -110 -196 0 0 "<userhome>/<qucs_workspace>/user_lib/IHP_PDK_basic_components" 0 "rppd" 0 "10u" 1 "25u" 1 "1" 1>
+  <Lib rsil2 1 250 890 50 -26 0 0 "<userhome>/<qucs_workspace>/user_lib/IHP_PDK_basic_components" 0 "rsil" 0 "10u" 1 "40u" 1 "1" 1>
   <GND * 1 610 950 0 0 0 0>
-  <Lib rhigh1 1 610 760 50 -26 0 0 "/home/herman/.qucs/user_lib/IHP_PDK_basic_components" 0 "rhigh" 0 "10u" 1 "30u" 1 "1" 1>
-  <Lib rhigh2 1 610 890 50 -26 0 0 "/home/herman/.qucs/user_lib/IHP_PDK_basic_components" 0 "rhigh" 0 "10u" 1 "50u" 1 "1" 1>
-  <Lib ntap1 1 890 880 50 -26 0 0 "/home/herman/.qucs/user_lib/IHP_PDK_basic_components" 0 "ntap1" 0>
+  <Lib rhigh1 1 610 760 50 -26 0 0 "<userhome>/<qucs_workspace>/user_lib/IHP_PDK_basic_components" 0 "rhigh" 0 "10u" 1 "30u" 1 "1" 1>
+  <Lib rhigh2 1 610 890 50 -26 0 0 "<userhome>/<qucs_workspace>/user_lib/IHP_PDK_basic_components" 0 "rhigh" 0 "10u" 1 "50u" 1 "1" 1>
+  <Lib ntap1 1 890 880 50 -26 0 0 "<userhome>/<qucs_workspace>/user_lib/IHP_PDK_basic_components" 0 "ntap1" 0>
   <GND * 1 890 920 0 0 0 0>
   <GND * 1 790 920 0 0 0 0>
-  <Lib ptap1 1 1120 880 50 -26 0 0 "/home/herman/.qucs/user_lib/IHP_PDK_basic_components" 0 "ptap1" 0>
+  <Lib ptap1 1 1120 880 50 -26 0 0 "<userhome>/<qucs_workspace>/user_lib/IHP_PDK_basic_components" 0 "ptap1" 0>
   <GND * 1 1120 920 0 0 0 0>
   <GND * 1 1040 920 0 0 0 0>
   <Idc I1 1 790 890 18 -26 0 1 "1 mA" 1>
   <Idc I2 1 1040 890 18 -26 0 1 "1 mA" 1>
-  <.DC DC1 1 90 180 0 41 0 0 "26.85" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "yes" 1 "150" 0 "no" 0 "none" 0 "CroutLU" 0>
 </Components>
 <Wires>
   <110 830 110 950 "" 0 0 0 "">
@@ -71,7 +70,7 @@
 <Diagrams>
   <Rect 553 615 857 473 3 #c0c0c0 1 00 1 0 0.5 10 1 -0.622632 1 7 1 0 0.1 0.525694 315 0 225 1 0 0 "" "" "">
 	<"ngspice/v(div2)" #ff0000 2 3 0 0 0>
-	  <Mkr 5.01661 503 -225 3 0 0>
+	  <Mkr 5 503 -225 3 0 0>
 	<"ngspice/i(pr1)" #ff0000 2 3 0 0 0>
 	<"ngspice/v(div1)" #ff00ff 2 3 0 0 0>
 	<"ngspice/v(div3)" #00ff00 2 3 0 0 0>
diff --git a/ihp-sg13g2/libs.tech/qucs/examples/symbols.sch b/ihp-sg13g2/libs.tech/qucs/examples/symbols.sch
index 4bf0b2d5..855edc6f 100644
--- a/ihp-sg13g2/libs.tech/qucs/examples/symbols.sch
+++ b/ihp-sg13g2/libs.tech/qucs/examples/symbols.sch
@@ -1,6 +1,6 @@
 <Qucs Schematic 24.2.0>
 <Properties>
-  <View=56,105,1360,872,1.15274,0,0>
+  <View=46,106,1370,872,1.18538,0,0>
   <Grid=10,10,1>
   <DataSet=symbols.dat>
   <DataDisplay=symbols.dpl>
@@ -16,22 +16,22 @@
 <Symbol>
 </Symbol>
 <Components>
-  <Lib ntap1 1 170 190 50 -26 0 0 "/home/herman/.qucs/user_lib/IHP_PDK_basic_components" 0 "ntap1" 0>
-  <Lib ptap1 1 300 190 50 -26 0 0 "/home/herman/.qucs/user_lib/IHP_PDK_basic_components" 0 "ptap1" 0>
-  <Lib rhigh1 1 430 190 50 -26 0 0 "/home/herman/.qucs/user_lib/IHP_PDK_basic_components" 0 "rhigh" 0 "1.0u" 1 "0.5u" 1 "1" 1>
-  <Lib rppd1 1 730 360 -110 -196 0 0 "/home/herman/.qucs/user_lib/IHP_PDK_basic_components" 0 "rppd" 0 "1.0u" 1 "0.5u" 1 "1" 1>
-  <Lib rsil1 1 710 190 50 -26 0 0 "/home/herman/.qucs/user_lib/IHP_PDK_basic_components" 0 "rsil" 0 "1.0u" 1 "0.5u" 1 "1" 1>
-  <Lib dpantenna1 1 360 310 40 -16 0 0 "/home/herman/.qucs/user_lib/IHP_PDK_nonlinear_components" 0 "dpantenna" 0 "0.78u" 1 "0.78u" 1>
-  <Lib npn13G1 1 170 710 10 64 0 0 "/home/herman/.qucs/user_lib/IHP_PDK_nonlinear_components" 0 "npn13G2" 0 "1" 1>
-  <Lib npn13G2l1 1 330 710 10 64 0 0 "/home/herman/.qucs/user_lib/IHP_PDK_nonlinear_components" 0 "npn13G2l" 0 "1" 1 "1" 1>
-  <Lib npn13G2v1 1 500 710 10 64 0 0 "/home/herman/.qucs/user_lib/IHP_PDK_nonlinear_components" 0 "npn13G2v" 0 "1" 1>
-  <Lib cap_rfcmim1 1 1160 190 50 -16 0 0 "/home/herman/.qucs/user_lib/IHP_PDK_basic_components" 0 "cap_rfcmim" 0 "7.0u" 1 "7.0u" 1>
-  <Lib cap_cmim1 1 980 190 30 -26 0 0 "/home/herman/.qucs/user_lib/IHP_PDK_basic_components" 0 "cap_cmim" 0 "7.0u" 1 "7u" 1>
-  <Lib dantenna1 1 180 310 40 -16 0 0 "/home/herman/.qucs/user_lib/IHP_PDK_nonlinear_components" 0 "dantenna" 0 "0.78u" 1 "0.78u" 1>
-  <Lib sg13_lv_nmos1 1 170 510 55 -121 0 0 "/home/herman/.qucs/user_lib/IHP_PDK_nonlinear_components" 0 "sg13_lv_nmos" 0 "0.35u" 1 "0.34u" 1 "1" 1 "1" 1 "0" 0 "0" 0 "0" 0 "0" 0 "0" 0 "0.346e-6" 0 "0.38e-6" 0 "0.15e-6" 0 "0" 0 "1" 0>
-  <Lib sg13_hv_nmos1 1 410 510 55 -121 0 0 "/home/herman/.qucs/user_lib/IHP_PDK_nonlinear_components" 0 "sg13_hv_nmos" 0 "1.0u" 1 "0.45u" 1 "1" 1 "1" 1 "0" 0 "0" 0 "0" 0 "0" 0 "0" 0 "0.346e-6" 0 "0.38e-6" 0 "0.15e-6" 0 "0" 0 "1" 0>
-  <Lib sg13_lv_pmos1 1 650 510 45 -101 0 0 "/home/herman/.qucs/user_lib/IHP_PDK_nonlinear_components" 0 "sg13_lv_pmos" 0 "0.35u" 1 "0.34u" 1 "1" 0 "1" 1 "0" 0 "0" 0 "0" 0 "0" 0 "0" 0 "0.346e-6" 0 "0.38e-6" 0 "0.15e-6" 0 "0" 0 "1" 0>
-  <Lib sg13_hv_pmos1 1 860 510 45 -101 0 0 "/home/herman/.qucs/user_lib/IHP_PDK_nonlinear_components" 0 "sg13_hv_pmos" 0 "1.0u" 1 "0.45u" 1 "1" 0 "1" 1 "0" 0 "0" 0 "0" 0 "0" 0 "0" 0 "0.346e-6" 0 "0.38e-6" 0 "0.15e-6" 0 "0" 0 "1" 0>
+  <Lib ntap1 1 170 190 50 -26 0 0 "<userhome>/<qucs_workspace>/user_lib/IHP_PDK_basic_components" 0 "ntap1" 0>
+  <Lib ptap1 1 300 190 50 -26 0 0 "<userhome>/<qucs_workspace>/user_lib/IHP_PDK_basic_components" 0 "ptap1" 0>
+  <Lib rhigh1 1 430 190 50 -26 0 0 "<userhome>/<qucs_workspace>/user_lib/IHP_PDK_basic_components" 0 "rhigh" 0 "1.0u" 1 "0.5u" 1 "1" 1>
+  <Lib rppd1 1 730 360 -110 -196 0 0 "<userhome>/<qucs_workspace>/user_lib/IHP_PDK_basic_components" 0 "rppd" 0 "1.0u" 1 "0.5u" 1 "1" 1>
+  <Lib rsil1 1 710 190 50 -26 0 0 "<userhome>/<qucs_workspace>/user_lib/IHP_PDK_basic_components" 0 "rsil" 0 "1.0u" 1 "0.5u" 1 "1" 1>
+  <Lib dpantenna1 1 360 310 40 -16 0 0 "<userhome>/<qucs_workspace>/user_lib/IHP_PDK_nonlinear_components" 0 "dpantenna" 0 "0.78u" 1 "0.78u" 1>
+  <Lib npn13G1 1 170 710 10 64 0 0 "<userhome>/<qucs_workspace>/user_lib/IHP_PDK_nonlinear_components" 0 "npn13G2" 0 "1" 1>
+  <Lib npn13G2l1 1 330 710 10 64 0 0 "<userhome>/<qucs_workspace>/user_lib/IHP_PDK_nonlinear_components" 0 "npn13G2l" 0 "1" 1 "1" 1>
+  <Lib npn13G2v1 1 500 710 10 64 0 0 "<userhome>/<qucs_workspace>/user_lib/IHP_PDK_nonlinear_components" 0 "npn13G2v" 0 "1" 1>
+  <Lib cap_rfcmim1 1 1160 190 50 -16 0 0 "<userhome>/<qucs_workspace>/user_lib/IHP_PDK_basic_components" 0 "cap_rfcmim" 0 "7.0u" 1 "7.0u" 1>
+  <Lib cap_cmim1 1 980 190 30 -26 0 0 "<userhome>/<qucs_workspace>/user_lib/IHP_PDK_basic_components" 0 "cap_cmim" 0 "7.0u" 1 "7u" 1>
+  <Lib dantenna1 1 180 310 40 -16 0 0 "<userhome>/<qucs_workspace>/user_lib/IHP_PDK_nonlinear_components" 0 "dantenna" 0 "0.78u" 1 "0.78u" 1>
+  <Lib sg13_lv_nmos1 1 170 510 55 -121 0 0 "<userhome>/<qucs_workspace>/user_lib/IHP_PDK_nonlinear_components" 0 "sg13_lv_nmos" 0 "0.35u" 1 "0.34u" 1 "1" 1 "1" 1 "0" 0 "0" 0 "0" 0 "0" 0 "0" 0 "0.346e-6" 0 "0.38e-6" 0 "0.15e-6" 0 "0" 0 "1" 0>
+  <Lib sg13_hv_nmos1 1 410 510 55 -121 0 0 "<userhome>/<qucs_workspace>/user_lib/IHP_PDK_nonlinear_components" 0 "sg13_hv_nmos" 0 "1.0u" 1 "0.45u" 1 "1" 1 "1" 1 "0" 0 "0" 0 "0" 0 "0" 0 "0" 0 "0.346e-6" 0 "0.38e-6" 0 "0.15e-6" 0 "0" 0 "1" 0>
+  <Lib sg13_lv_pmos1 1 650 510 45 -101 0 0 "<userhome>/<qucs_workspace>/user_lib/IHP_PDK_nonlinear_components" 0 "sg13_lv_pmos" 0 "0.35u" 1 "0.34u" 1 "1" 0 "1" 1 "0" 0 "0" 0 "0" 0 "0" 0 "0" 0 "0.346e-6" 0 "0.38e-6" 0 "0.15e-6" 0 "0" 0 "1" 0>
+  <Lib sg13_hv_pmos1 1 860 510 45 -101 0 0 "<userhome>/<qucs_workspace>/user_lib/IHP_PDK_nonlinear_components" 0 "sg13_hv_pmos" 0 "1.0u" 1 "0.45u" 1 "1" 0 "1" 1 "0" 0 "0" 0 "0" 0 "0" 0 "0" 0 "0.346e-6" 0 "0.38e-6" 0 "0.15e-6" 0 "0" 0 "1" 0>
 </Components>
 <Wires>
 </Wires>
diff --git a/ihp-sg13g2/libs.tech/qucs/install.py b/ihp-sg13g2/libs.tech/qucs/install.py
old mode 100644
new mode 100755
index 23035aac..5704b5ad
--- a/ihp-sg13g2/libs.tech/qucs/install.py
+++ b/ihp-sg13g2/libs.tech/qucs/install.py
@@ -1,3 +1,5 @@
+#!/usr/bin/env python3
+
 ########################################################################
 #
 # Copyright 2024 IHP PDK Authors
@@ -20,6 +22,7 @@
 import shutil
 import os
 import subprocess
+import logging
 
 
 def exec_app_in_directory(command, directory):
@@ -49,12 +52,11 @@ def copy_files(source_dir, destination_dir):
 
 def info():
     msg = """
-    This script copies the Qucs-S user library files into 
-    /home/$USER/.qucs/user_lib directory. 
-    It also creates a symbolic link there and compiles and places 
-    PSP103 model in ~/.qucs/ location. 
+    This script:
+    - copies the Qucs-S user library files into $HOME/[.qucs|QucsWorkspace]/user_lib directory. 
+    - compiles and copies PSP103 model in ../ngspice/openvaf location
     Please make sure that you have set up the PDK_ROOT env variable
-    export PDK_ROOT=your_location/IHP-Open-PDK 
+    export PDK_ROOT=<path_to_IHP-Open-PDK>
     """
     print(msg)
 
@@ -62,48 +64,105 @@ def info():
 if __name__ == "__main__":
     # Example usage:
     info()
+    
+    # Check if 'Qucs-S' tool is available
+    program_name = "qucs-s"
+    if not is_program_installed(program_name):
+        logging.error(f"{program_name} is not installed.")
+        exit(1)
+    
+    # Check if PDK_ROOT env variable exists
     pdk_root = os.environ.get("PDK_ROOT")
-    if not pdk_root:
-        print("setup PDK_ROOT environmental variable to IHP-Open-PDK location")
+    if pdk_root == None:
+        logging.error("Setup PDK_ROOT environment variable to IHP-Open-PDK location")
+        exit(1)
     else:
-        source_directory=pdk_root + "/ihp-sg13g2/libs.tech/qucs/user_lib"
+        source_directory = pdk_root + "/ihp-sg13g2/libs.tech/qucs/user_lib"
 
-    username = os.environ.get("USER")
-    destination_directory = "/home/" + username + "/.qucs/user_lib"
+    userhome = os.environ.get("HOME")
     
     # Check if the source directory exists
     if not os.path.exists(source_directory):
-        print(f"Source directory '{source_directory}' does not exist.")
+        logging.error(f"Source directory '{source_directory}' does not exist.")
+        exit(1)    
     
-    # Check if the destination directory exists, if not, create it
-    if not os.path.exists(destination_directory):
-        os.makedirs(destination_directory)
-        print(f"Destination directory '{destination_directory}' created.")
+    # Supporting two variants of Qucs-S default workspace
+    for qucs_workspace in ['/.qucs/', '/QucsWorkspace/']:
     
-    copy_files(source_directory, destination_directory)
-
-    original_file = pdk_root
-    symbolic_link = "/home/" + username + "/.qucs/IHP-Open-PDK-main"
-    # Create the symbolic link
-    if not os.path.exists(symbolic_link):
-        try:
-            os.symlink(original_file, symbolic_link)
-            print(f"Symbolic link '{symbolic_link}' created successfully.")
-        except OSError as e:
-            print(f"Failed to create symbolic link: {e}")
-
+        print(f"Preparing $HOME{qucs_workspace} directory ...")
+        print("#############################################\n")
+        
+        destination_directory = userhome + qucs_workspace + "user_lib"
+        
+        # Check if the destination directory exists, if not, create it
+        if not os.path.exists(destination_directory):
+            os.makedirs(destination_directory)
+            print(f"Destination directory '{destination_directory}' created.")
+        
+        copy_files(source_directory, destination_directory)
+
+        # Copy examples to "Qucs Home" (<userhome>/[.qucs|QucsWorkspace]/)
+        print("Copying examples into Qucs-S Home...")
+        source_directory = pdk_root + "/ihp-sg13g2/libs.tech/qucs/examples"
+        destination_directory = userhome + qucs_workspace + "IHP-Open-PDK-SG13G2-Examples_prj"
+
+        if not os.path.exists(destination_directory):
+            os.makedirs(destination_directory)
+
+        copy_files(source_directory, destination_directory)
+        print("Examples copied")
+        print("\n\n#############################################")
+        print("              IMPORTANT NOTE")
+        print("#############################################\n")
+        print("Before using the PDK example schematics, you must add the PDK library path to the Qucs-S search path list.\n")
+        print("Please read the instructions provided in " + destination_directory + "/README.md\n")
+        print("#############################################\n")
+       
+        original_file = pdk_root + "/ihp-sg13g2/libs.tech/ngspice/.spiceinit"
+        symbolic_link = userhome + "/.spiceinit"
+        # Create the symbolic link to ngspice global settings file
+        if not os.path.exists(symbolic_link):
+            try:
+                os.symlink(original_file, symbolic_link)
+                print(f"Symbolic link '{symbolic_link}' created successfully.")
+            except OSError as e:
+                print(f"Failed to create symbolic link: {e}")
+
+        original_file = pdk_root
+        symbolic_link = userhome + qucs_workspace + "IHP-Open-PDK"
+        # Create the symbolic link to IHP OpenPDK directory
+        if not os.path.exists(symbolic_link):
+            try:
+                os.symlink(original_file, symbolic_link)
+                print(f"Symbolic link '{symbolic_link}' created successfully.")
+            except OSError as e:
+                print(f"Failed to create symbolic link: {e}")
+        
+        # Post-processing example schematics
+        program_name = "sed"
+        if is_program_installed(program_name):
+            userhome_escaped = userhome.replace('/', '\\/')
+            command = f"sed -i 's/<userhome>/{userhome_escaped}/;s/<qucs_workspace>{qucs_workspace}' *.sch"
+            exec_app_in_directory(command, destination_directory)
+        else:
+            logging.error(f"{program_name} is not installed.")
+            exit(1)
+                
+    # Compiling MOSFET PSP Verilog-A models
+    print("\nCompiling MOSFET PSP Verilog-A models ...")
+    source_directory = pdk_root + "/ihp-sg13g2/libs.tech/ngspice/openvaf"
+    destination_directory = pdk_root + "/ihp-sg13g2/libs.tech/ngspice/openvaf"
     program_name = "openvaf"
     if is_program_installed(program_name):
-        command = "openvaf psp103_nqs.va --output " + "/home/" + username + "/.qucs/psp103_nqs.osdi"    
-        directory = pdk_root + "/ihp-sg13g2/libs.tech/ngspice/openvaf"
-        print(f"{program_name} is installed and about to run the command '{command}' in a location: {directory} ")	
-        exec_app_in_directory(command, directory)
+        command = "openvaf psp103_nqs.va --output " + destination_directory + "/psp103_nqs.osdi"    
+        print(f"{program_name} is available and about to run the command '{command}' in a location: {source_directory} ")	
+        exec_app_in_directory(command, source_directory)
     else:
-        print(f"{program_name} is not installed.")
-    	
-
-
-
- 	
-
-
+        logging.error(f"{program_name} is not installed.")
+        exit(1)
+                
+                
+                
+                
+                
+                
diff --git a/ihp-sg13g2/libs.tech/qucs/user_lib/IHP_PDK_basic_components.lib b/ihp-sg13g2/libs.tech/qucs/user_lib/IHP_PDK_basic_components.lib
index 9ba488ea..92846542 100644
--- a/ihp-sg13g2/libs.tech/qucs/user_lib/IHP_PDK_basic_components.lib
+++ b/ihp-sg13g2/libs.tech/qucs/user_lib/IHP_PDK_basic_components.lib
@@ -64,7 +64,6 @@ mbrin72043@yahoo.co.uk, or brinsonm@staff.londonmet.ac.uk.
   </Model>
   <Spice>*
 .SUBCKT IHP_PDK_basic_components_rhigh  gnd P1 P2 w=1.0e-6 l=0.5e-6 m=1
-.INCLUDE ../../.qucs/IHP-Open-PDK-main/ihp-sg13g2/libs.tech/ngspice/models/resistors_parm.lib          
 X1 P1 P2 rhigh w={w} l={l} m={m}
 .ENDS
   </Spice>
@@ -91,7 +90,6 @@ mbrin72043@yahoo.co.uk, or brinsonm@staff.londonmet.ac.uk.
   </Model>
   <Spice>*
 .SUBCKT IHP_PDK_basic_components_rppd  gnd P1 P2 w=1.0e-6 l=0.5e-6 m=1
-.INCLUDE ../../.qucs/IHP-Open-PDK-main/ihp-sg13g2/libs.tech/ngspice/models/resistors_parm.lib          
 X1 P1 P2 rppd w={w} l={l} m={m}
 .ENDS
   </Spice>
@@ -118,7 +116,6 @@ mbrin72043@yahoo.co.uk, or brinsonm@staff.londonmet.ac.uk.
   </Model>
   <Spice>*
 .SUBCKT IHP_PDK_basic_components_rsil  gnd P1 P2 w=1.0e-6 l=0.5e-6 m=1
-.INCLUDE ../../.qucs/IHP-Open-PDK-main/ihp-sg13g2/libs.tech/ngspice/models/resistors_parm.lib          
 X1 P1 P2 rsil w={w} l={l} m={m}
 .ENDS
   </Spice>
diff --git a/ihp-sg13g2/libs.tech/qucs/user_lib/IHP_PDK_nonlinear_components.lib b/ihp-sg13g2/libs.tech/qucs/user_lib/IHP_PDK_nonlinear_components.lib
index 9a9f918d..a082ba25 100644
--- a/ihp-sg13g2/libs.tech/qucs/user_lib/IHP_PDK_nonlinear_components.lib
+++ b/ihp-sg13g2/libs.tech/qucs/user_lib/IHP_PDK_nonlinear_components.lib
@@ -54,7 +54,7 @@ XD2 Pcathode Panode dpantenna w={w} l={l}
     <Line -20 20 40 0 #ff0000 3 1>
     <.PortSym 0 -20 1 0>
     <.PortSym 0 40 2 0>
-           <.ID 40 -16 dpantenna "1=w=0.78u==" "1=l=0.78u==">
+    <.ID 40 -16 dpantenna "1=w=0.78u==" "1=l=0.78u==">
   </Symbol>
 </Component>
 
@@ -69,7 +69,6 @@ mbrin72043@yahoo.co.uk, or m.brinson@londonmet.ac.uk.
   </Model>
   <Spice>*
 .SUBCKT IHP_PDK_nonlinear_components_sg13_lv_nmos  gnd d g s b w=0.35u l=0.34u ng=1 m=1 as=0 ad=0 pd=0 ps=0 trise=0 z1=0.346e-6 z2=0.38e-6 wmin=0.15e-6 rfmode=0 pre_layout=1 mlist=1
-.INCLUDE   ../../.qucs/IHP-Open-PDK-main/ihp-sg13g2/libs.tech/ngspice/models/sg13g2_moslv_parm.lib
 X1 d g s b  sg13_lv_nmos w={w} l={l} ng={ng} m={m} as={as} ad={ad} pd={pd} 
 + ps={ps} trise={trise} z1={z1} z2={z2} wmin={wmin} rfmode={rfmode} pre_layout={pre_layout} 
 .ENDS
@@ -108,7 +107,6 @@ mbrin72043@yahoo.co.uk, or m.brinson@londonmet.ac.uk.
   </Model>
   <Spice>*
 .SUBCKT IHP_PDK_nonlinear_components_sg13_hv_nmos  gnd d g s b w=0.35u l=0.34u ng=1 m=1 as=0 ad=0 pd=0 ps=0 trise=0 z1=0.346e-6 z2=0.38e-6 wmin=0.15e-6 rfmode=0 pre_layout=1 mlist=1
-.INCLUDE   ../../.qucs/IHP-Open-PDK-main/ihp-sg13g2/libs.tech/ngspice/models/sg13g2_moshv_parm.lib
 X1 d g s b  sg13_hv_nmos w={w} l={l} ng={ng} m={m} as={as} ad={ad} pd={pd} 
 + ps={ps} trise={trise} z1={z1} z2={z2} wmin={wmin} rfmode={rfmode} pre_layout={pre_layout} 
 .ENDS
@@ -147,7 +145,6 @@ mbrin72043@yahoo.co.uk, or m.brinson@londonmet.ac.uk.
   </Model>
   <Spice>*
 .SUBCKT IHP_PDK_nonlinear_components_sg13_lv_pmos  gnd d g s b w=0.35u l=0.34u ng=1 m=1 as=0 ad=0 pd=0 ps=0 trise=0 z1=0.346e-6 z2=0.38e-6 wmin=0.15e-6 rfmode=0 pre_layout=1 
-.INCLUDE   ../../.qucs/IHP-Open-PDK-main/ihp-sg13g2/libs.tech/ngspice/models/sg13g2_moslv_parm.lib
 X1 d g s b  sg13_lv_pmos w={w} l={l} ng={ng} m={1} as={as} ad={ad} pd={pd} 
 + ps={ps} trise={trise} z1={z1} z2={z2} wmin={wmin} rfmode={rfmode} pre_layout={pre_layout}
 .ENDS
@@ -185,7 +182,6 @@ mbrin72043@yahoo.co.uk, or m.brinson@londonmet.ac.uk.
   </Model>
   <Spice>*
 .SUBCKT IHP_PDK_nonlinear_components_sg13_hv_pmos  gnd d g s b w=0.35u l=0.34u ng=1 m=1 as=0 ad=0 pd=0 ps=0 trise=0 z1=0.346e-6 z2=0.38e-6 wmin=0.15e-6 rfmode=0 pre_layout=1 
-.INCLUDE   ../../.qucs/IHP-Open-PDK-main/ihp-sg13g2/libs.tech/ngspice/models/sg13g2_moshv_parm.lib
 X1 d g s b  sg13_hv_pmos w={w} l={l} ng={ng} m={m} as={as} ad={ad} pd={pd} 
 + ps={ps} trise={trise} z1={z1} z2={z2} wmin={wmin} rfmode={rfmode} pre_layout={pre_layout}
 .ENDS
@@ -218,13 +214,12 @@ Author: Mike Brinson, Feb 2024
 mbrin72043@yahoo.co.uk, or m.brinson@londonmet.ac.uk.
   </Description>
   <Model>
-.Def:IHP_PDK_nonlinear_components_npn13G2 c b e bn t Nx="1" 
+.Def:IHP_PDK_nonlinear_components_npn13G2 c b e bn Nx="1" 
 .Def:End
   </Model>
   <Spice>*
-.SUBCKT IHP_PDK_nonlinear_components_npn13G2  gnd c b e bn t Nx=1  
-.INCLUDE   ../../.qucs/IHP-Open-PDK-main/ihp-sg13g2/libs.tech/ngspice/models/sg13g2_hbt_mod.lib
-X1 c b e bn t  npn13G2 Nx={Nx} 
+.SUBCKT IHP_PDK_nonlinear_components_npn13G2  gnd c b e bn Nx=1  
+X1 c b e bn npn13G2 Nx={Nx} 
 .ENDS
   </Spice>
   <VerilogModel>  </VerilogModel>
@@ -252,13 +247,12 @@ Author: Mike Brinson, Feb 2024
 mbrin72043@yahoo.co.uk, or m.brinson@londonmet.ac.uk.
   </Description>
   <Model>
-.Def:IHP_PDK_nonlinear_components_npn13G2l c b e bn t Nx="1" El="1" 
+.Def:IHP_PDK_nonlinear_components_npn13G2l c b e bn Nx="1" El="1" 
 .Def:End
   </Model>
   <Spice>*
-.SUBCKT IHP_PDK_nonlinear_components_npn13G2l  gnd c b e bn t Nx=1 El=1 
-.INCLUDE   ../../.qucs/IHP-Open-PDK-main/ihp-sg13g2/libs.tech/ngspice/models/sg13g2_hbt_mod.lib
-X1 c b e bn t  npn13G2l Nx={Nx} El={El} 
+.SUBCKT IHP_PDK_nonlinear_components_npn13G2l  gnd c b e bn Nx=1 El=1 
+X1 c b e bn npn13G2l Nx={Nx} El={El} 
 .ENDS
   </Spice>
   <VerilogModel>  </VerilogModel>
@@ -287,13 +281,12 @@ Author: Mike Brinson, Feb 2024
 mbrin72043@yahoo.co.uk, or m.brinson@londonmet.ac.uk.
   </Description>
   <Model>
-.Def:IHP_PDK_nonlinear_components_npn13G2v c b e bn t Nx="1" 
+.Def:IHP_PDK_nonlinear_components_npn13G2v c b e bn Nx="1" 
 .Def:End
   </Model>
   <Spice>*
-.SUBCKT IHP_PDK_nonlinear_components_npn13G2v  gnd c b e bn t Nx=1  
-.INCLUDE   ../../.qucs/IHP-Open-PDK-main/ihp-sg13g2/libs.tech/ngspice/models/sg13g2_hbt_mod.lib
-X1 c b e bn t  npn13G2v Nx={Nx} 
+.SUBCKT IHP_PDK_nonlinear_components_npn13G2v  gnd c b e bn Nx=1  
+X1 c b e bn npn13G2v Nx={Nx} 
 .ENDS
   </Spice>
   <VerilogModel>  </VerilogModel>
diff --git a/ihp-sg13g2/libs.tech/xschem/README.md b/ihp-sg13g2/libs.tech/xschem/README.md
index a0bf5121..ff812f29 100755
--- a/ihp-sg13g2/libs.tech/xschem/README.md
+++ b/ihp-sg13g2/libs.tech/xschem/README.md
@@ -8,7 +8,7 @@ the xschem editor to in order to include PDK root directory, library directories
 Do it only once:
 ```bash
 export PDK_ROOT=<your_path>/IHP-Open-PDK
-python3 install.py
+./install.py
 ```
 Now you can run xschem and enjoy the examples:
 
diff --git a/ihp-sg13g2/libs.tech/xschem/install.py b/ihp-sg13g2/libs.tech/xschem/install.py
index 33e561ba..b55215c9 100644
--- a/ihp-sg13g2/libs.tech/xschem/install.py
+++ b/ihp-sg13g2/libs.tech/xschem/install.py
@@ -1,3 +1,5 @@
+#!/usr/bin/env python3
+
 ########################################################################
 #
 # Copyright 2024 IHP PDK Authors
@@ -39,10 +41,10 @@ def is_program_installed(program_name):
 
 def info():
     msg = """
-    This script compiles and places 
-    PSP103 model in ./simulations/ location. 
-    Please make sure that you have set up the PDK_ROOT env variable
-    export PDK_ROOT=your_location/IHP-Open-PDK 
+    This script:
+    - compiles and places PSP103 model in ../ngspice/openvaf/ location. 
+    - creates a symlink to the ../ngspice/.spiceinit file in your $HOME directory
+    Please make sure that you have set up the PDK_ROOT env variable export PDK_ROOT=your_location/IHP-Open-PDK 
     """
     print(msg)
 
@@ -57,16 +59,12 @@ def info():
         source_directory=pdk_root + "/ihp-sg13g2/libs.tech/ngspice/openvaf"
 
     username = os.environ.get("USER")
-    destination_directory = pdk_root + "/ihp-sg13g2/libs.tech/xschem/simulations"
+    destination_directory = pdk_root + "/ihp-sg13g2/libs.tech/ngspice/openvaf"
     
     # Check if the source directory exists
     if not os.path.exists(source_directory):
         print(f"Source directory '{source_directory}' does not exist.")
     
-    # Check if the destination directory exists, if not, create it
-    if not os.path.exists(destination_directory):
-        os.makedirs(destination_directory)
-        print(f"Destination directory '{destination_directory}' created.")
     
     program_name = "openvaf"
     if is_program_installed(program_name):
@@ -77,6 +75,15 @@ def info():
         print(f"{program_name} is not installed.")
     	
 
+    original_file =  pdk_root + "/ihp-sg13g2/libs.tech/ngspice/.spiceinit"
+    symbolic_link = "/home/" + username + "/.spiceinit"
+    # Create the symbolic link
+    if not os.path.exists(symbolic_link):
+        try:
+            os.symlink(original_file, symbolic_link)
+            print(f"Symbolic link '{symbolic_link}' created successfully.")
+        except OSError as e:
+            print(f"Failed to create symbolic link: {e}")
 
 
  	
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/cap_cmim.sym b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/cap_cmim.sym
index aca15232..a73cbfce 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/cap_cmim.sym
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/cap_cmim.sym
@@ -1,5 +1,5 @@
 v {xschem version=3.1.0 file_version=1.2
-* Copyright 2023 IHP PDK Authors
+* Copyright 2024 IHP PDK Authors
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
@@ -15,8 +15,14 @@ v {xschem version=3.1.0 file_version=1.2
 }
 G {}
 K {type=capacitor
-format="@spiceprefix@name @pinlist @model W=@W L=@L MF=@MF"
-template="name=C1 model=cap_cmim W=7.0e-6 L=7.0e-6 MF=1 spiceprefix=X"
+format="@spiceprefix@name @pinlist @model w=@w l=@l m=@m"
+template="name=C1
+model=cap_cmim
+w=7.0e-6
+l=7.0e-6
+m=1
+spiceprefix=X"
+drc="mim_drc @name @symname @model @w @l"
 }
 V {}
 S {}
@@ -30,8 +36,8 @@ A 4 -0 23.75 21.25 61.92751306414704 56.14497387170592 {}
 T {c0} 5 -27.5 0 0 0.15 0.15 {layer=7}
 T {c1} 5 18.75 0 0 0.15 0.15 {layer=7}
 T {@name} 15 -28.75 0 0 0.2 0.2 {}
-T {@W / @L} 15 6.25 0 0 0.2 0.2 {layer=13}
+T {@w / @l} 15 6.25 0 0 0.2 0.2 {layer=13}
 T {@model} 15 -11.25 0 0 0.2 0.2 {}
-T {tcleval(C=[ev \{@MF * (@W * @L * 1.5e-3 + 2*( @W + @L ) * 40e-12)\}])} -7.5 8.75 0 1 0.2 0.2 {layer=13}
-T {MF=@MF} 15 16.25 0 0 0.2 0.2 {layer=13}
+T {tcleval(C=[ev \{@m * (@w * @l * 1.5e-3 + 2*( @w + @l ) * 40e-12)\}])} -7.5 8.75 0 1 0.2 0.2 {layer=13}
+T {m=@m} 15 16.25 0 0 0.2 0.2 {layer=13}
 
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/cap_rfcmim.sym b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/cap_rfcmim.sym
index b952c1bc..372ae325 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/cap_rfcmim.sym
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/cap_rfcmim.sym
@@ -16,8 +16,14 @@ v {xschem version=3.1.0 file_version=1.2
 
 G {}
 K {type=capacitor
-format="@spiceprefix@name @pinlist @model W=@W L=@L wfeed=@wfeed"
-template="name=C1 model=cap_rfcmim W=10.0e-6 L=10.0e-6 wfeed=5.0e-6 spiceprefix=X"
+format="@spiceprefix@name @pinlist @model w=@w l=@l wfeed=@wfeed"
+template="name=C1 
+model=cap_rfcmim
+w=10.0e-6
+l=10.0e-6
+wfeed=5.0e-6
+spiceprefix=X"
+drc="mim_drc @name @symname @model @w @l"
 }
 V {}
 S {}
@@ -32,8 +38,8 @@ A 4 -0 23.75 21.25 61.92751306414704 56.14497387170592 {}
 T {c0} 5 -27.5 0 0 0.15 0.15 {layer=7}
 T {c1} 5 18.75 0 0 0.15 0.15 {layer=7}
 T {@name} 15 -28.75 0 0 0.2 0.2 {}
-T {@W / @L} 15 6.25 0 0 0.2 0.2 {layer=13}
+T {@w / @l} 15 6.25 0 0 0.2 0.2 {layer=13}
 T {@model} 15 -11.25 0 0 0.2 0.2 {}
-T {tcleval(C=[ev \{(@W * @L * 1.5e-3 + 2*( @W + @L ) * 40e-12)\}])} -7.5 8.75 0 1 0.2 0.2 {layer=13}
+T {tcleval(C=[ev \{(@w * @l * 1.5e-3 + 2*( @w + @l ) * 40e-12)\}])} -7.5 8.75 0 1 0.2 0.2 {layer=13}
 T {bn} -25 -7.5 0 0 0.15 0.15 {layer=7}
 
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/dantenna.sym b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/dantenna.sym
index b149a4bc..2e4ff306 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/dantenna.sym
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/dantenna.sym
@@ -16,12 +16,15 @@ v {xschem version=3.1.0 file_version=1.2
 }
 G {}
 K {type=diode
-format="@name @pinlist @model  l=@l w=@w"
-template="name=XD1
+lvs_format="@spiceprefix@name @pinlist @model l=@l w=@w"
+format="@spiceprefix@name @pinlist @model  l=@l w=@w"
+template="name=D1
 model=dantenna
-l=780n
-w=780n
+l=0.78u
+w=0.78u
+spiceprefix=X
 "
+drc="diode_drc @name @symname @model @w @l"
 }
 V {}
 S {}
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/dpantenna.sym b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/dpantenna.sym
index 87e91483..f9c481fc 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/dpantenna.sym
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/dpantenna.sym
@@ -16,12 +16,15 @@ v {xschem version=3.1.0 file_version=1.2
 }
 G {}
 K {type=diode
-format="@name @pinlist @model l=@l w=@w"
-template="name=XD1
+lvs_format="@spiceprefix@name @pinlist @model l=@l w=@w"
+format="@spiceprefix@name @pinlist @model l=@l w=@w"
+template="name=D1
 model=dpantenna
-l=780n
-w=780n
+l=0.78u
+w=0.78u
+spiceprefix=X
 "
+drc="diode_drc @name @symname @model @w @l"
 }
 V {}
 S {}
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/npn13G2.sym b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/npn13G2.sym
index 70b1b54c..6916065c 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/npn13G2.sym
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/npn13G2.sym
@@ -16,11 +16,14 @@ v {xschem version=3.1.0 file_version=1.2
 }
 G {}
 K {type=vertical_npn
+lvs_format="@spiceprefix@name @pinlist @model le=@le we=70.0n m=@Nx"
 format="@spiceprefix@name @pinlist @model Nx=@Nx"
 template="name=Q1
 model=npn13G2
 spiceprefix=X
-Nx=1"
+Nx=1
+le=900e-9"
+drc="hbt_drc @name @symname @model @Nx @le"
 }
 V {}
 S {}
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/npn13G2l.sym b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/npn13G2l.sym
index fe1a432d..c296c145 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/npn13G2l.sym
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/npn13G2l.sym
@@ -1,4 +1,4 @@
-v {xschem version=3.1.0 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 * Copyright 2023 IHP PDK Authors
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -16,12 +16,14 @@ v {xschem version=3.1.0 file_version=1.2
 }
 G {}
 K {type=vertical_npn
-format="@spiceprefix@name @pinlist @model Nx=@Nx El=@El"
+lvs_format="@spiceprefix@name @pinlist @model le=@le we=70.0n m=@Nx"
+format="@spiceprefix@name @pinlist @model Nx=@Nx le=@le"
 template="name=Q1
 model=npn13G2l
 spiceprefix=X
 Nx=1
-El=1"
+le=1.0e-6"
+drc="hbt_drc @name @symname @model @Nx @le"
 }
 V {}
 S {}
@@ -39,4 +41,4 @@ T {Nx=@Nx} 32.5 1.25 0 0 0.2 0.2 {layer=13}
 T {@model} 22.5 -15 0 0 0.2 0.2 {}
 T {S} 10 -5 0 0 0.2 0.2 {}
 T {@spiceprefix@name} 22.5 -27.5 0 0 0.2 0.2 {}
-T {El=@El} 32.5 11.25 0 0 0.2 0.2 {layer=13}
+T {le=@le} 32.5 11.25 0 0 0.2 0.2 {layer=13}
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/npn13G2v.sym b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/npn13G2v.sym
index ecd72060..c08f5336 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/npn13G2v.sym
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/npn13G2v.sym
@@ -1,4 +1,4 @@
-v {xschem version=3.1.0 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 * Copyright 2023 IHP PDK Authors
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -16,11 +16,15 @@ v {xschem version=3.1.0 file_version=1.2
 }
 G {}
 K {type=vertical_npn
-format="@spiceprefix@name @pinlist @model Nx=@Nx"
+lvs_format="@spiceprefix@name @pinlist @model le=@le we=70.0n m=@Nx"
+format="@spiceprefix@name @pinlist @model Nx=@Nx le=@le"
 template="name=Q1
 model=npn13G2v
 spiceprefix=X
-Nx=1"
+Nx=1
+le=1.0e-6
+"
+drc="hbt_drc @name @symname @model @Nx @le"
 }
 V {}
 S {}
@@ -34,7 +38,8 @@ B 5 -22.5 -2.5 -17.5 2.5 {name=B dir=in pinnumber=1}
 B 5 17.5 27.5 22.5 32.5 {name=E dir=inout pinnumber=2}
 B 5 17.5 -2.5 22.5 2.5 {name=S dir=in pinnumber=1}
 P 4 4 20 30 13.75 13.75 3.75 23.75 20 30 {fill=true}
-T {Nx=@Nx} 22.5 11.25 0 0 0.2 0.2 {layer=13}
+T {Nx=@Nx} 22.5 1.25 0 0 0.2 0.2 {layer=13}
 T {@model} 22.5 -15 0 0 0.2 0.2 {}
 T {S} 10 -5 0 0 0.2 0.2 {}
 T {@spiceprefix@name} 22.5 -27.5 0 0 0.2 0.2 {}
+T {le=@le} 22.5 11.25 0 0 0.2 0.2 {layer=13}
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/pnpMPA.sym b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/pnpMPA.sym
index a7f846a1..83283e8a 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/pnpMPA.sym
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/pnpMPA.sym
@@ -30,9 +30,9 @@ L 4 0 -30 0 30 {}
 L 4 -20 0 0 0 {}
 L 4 10 -20 20 -30 {}
 L 4 0 10 20 30 {}
-B 5 17.5 -32.5 22.5 -27.5 {name=emitter dir=inout pinnumber=1}
+B 5 17.5 27.5 22.5 32.5 {name=collector dir=inout pinnumber=1}
 B 5 -22.5 -2.5 -17.5 2.5 {name=base dir=in pinnumber=2}
-B 5 17.5 27.5 22.5 32.5 {name=collector dir=inout pinnumber=3}
+B 5 17.5 -32.5 22.5 -27.5 {name=emitter dir=inout pinnumber=3}
 P 4 4 0 -10 15 -15 5 -25 0 -10 {fill=true}
 T {@model} 22.5 15 0 0 0.2 0.2 {}
 T {@spiceprefix@name} 22.5 -26.25 0 0 0.2 0.2 {}
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/rhigh.sym b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/rhigh.sym
index aa0716bf..e9acd419 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/rhigh.sym
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/rhigh.sym
@@ -16,15 +16,16 @@ v {xschem version=3.4.5 file_version=1.2
 }
 G {}
 K {type=res
-format="@spiceprefix@name @pinlist @model w=@W l=@L m=@m b=@b"
+format="@spiceprefix@name @pinlist @model w=@w l=@l m=@m b=@b"
 template="name=R1
-W=0.5e-6
-L=0.5e-6
+w=0.5e-6
+l=0.5e-6
 model=rhigh
 spiceprefix=X
 b=0
 m=1
 "
+drc="res_drc @name @symname @model @w @l"
 }
 V {}
 S {}
@@ -42,10 +43,10 @@ L 4 -7.5 -17.5 0 -20 {}
 L 4 0 -30 0 -20 {}
 B 5 -2.5 27.5 2.5 32.5 {name=M dir=inout propag=1 pinnumber=2}
 B 5 -2.5 -32.5 2.5 -27.5 {name=P dir=inout propag=0 pinnumber=1}
-T {W/L = @W / @L} 15 -3.75 0 0 0.2 0.2 {layer=13}
+T {w/l = @w / @l} 15 -3.75 0 0 0.2 0.2 {layer=13}
 T {@model} 15 -16.25 0 0 0.2 0.2 {}
 T {@spiceprefix@name} 15 -28.75 0 0 0.2 0.2 {}
-T {tcleval(R=[ ev \{ ( 1.6e-4 / @W + 1360.0 * ( (@b + 1)*@L + ( 1.081*( @W - 0.04e-6 ) + 0.18e-6 )*@b ) / ( @W - 0.04e-6 ) ) / @m \} ] )} 15 30 0 0 0.2 0.2 {layer=13}
+T {tcleval(R=[ ev \{ ( 1.6e-4 / @w + 1360.0 * ( (@b + 1)*@l + ( 1.081*( @w - 0.04e-6 ) + 0.18e-6 )*@b ) / ( @w - 0.04e-6 ) ) / @m \} ] )} 15 30 0 0 0.2 0.2 {layer=13}
 T {} 15 20 0 0 0.2 0.2 {}
 T {b=@b} 15 6.25 0 0 0.2 0.2 {layer=13}
 T {m=@m} 15 16.25 0 0 0.2 0.2 {layer=13}
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/rppd.sym b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/rppd.sym
index f56ce94e..4e001026 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/rppd.sym
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/rppd.sym
@@ -16,15 +16,16 @@ v {xschem version=3.4.5 file_version=1.2
 }
 G {}
 K {type=res
-format="@spiceprefix@name @pinlist @model w=@W l=@L m=@m b=@b"
+format="@spiceprefix@name @pinlist @model w=@w l=@l m=@m b=@b"
 template="name=R1
-W=0.5e-6
-L=0.5e-6
+w=0.5e-6
+l=0.5e-6
 model=rppd
 spiceprefix=X
 b=0
 m=1
 "
+drc="res_drc @name @symname @model @w @l"
 }
 V {}
 S {}
@@ -42,10 +43,10 @@ L 4 -7.5 -17.5 0 -20 {}
 L 4 0 -30 0 -20 {}
 B 5 -2.5 27.5 2.5 32.5 {name=M dir=inout propag=1 pinnumber=2}
 B 5 -2.5 -32.5 2.5 -27.5 {name=P dir=inout propag=0 pinnumber=1}
-T {W/L = @W / @L} 15 -3.75 0 0 0.2 0.2 {layer=13}
+T {w/l = @w / @l} 15 -3.75 0 0 0.2 0.2 {layer=13}
 T {@model} 15 -16.25 0 0 0.2 0.2 {}
 T {@spiceprefix@name} 15 -28.75 0 0 0.2 0.2 {}
-T {tcleval(R=[ ev \{ ( 70.0e-6 / @W + 260.0 * ( (@b + 1)*@L + ( 1.081*( @W + 6.0e-9 ) + 0.18e-6 )*@b ) / ( @W + 6.0e-9 ) ) / @m \} ] )} 15 30 0 0 0.2 0.2 {layer=13}
+T {tcleval(R=[ ev \{ ( 70.0e-6 / @w + 260.0 * ( (@b + 1)*@l + ( 1.081*( @w + 6.0e-9 ) + 0.18e-6 )*@b ) / ( @w + 6.0e-9 ) ) / @m \} ] )} 15 30 0 0 0.2 0.2 {layer=13}
 T {} 15 20 0 0 0.2 0.2 {}
 T {b=@b} 15 6.25 0 0 0.2 0.2 {layer=13}
 T {m=@m} 15 16.25 0 0 0.2 0.2 {layer=13}
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/rsil.sym b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/rsil.sym
index efb51454..4877fcf7 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/rsil.sym
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/rsil.sym
@@ -16,15 +16,16 @@ v {xschem version=3.4.5 file_version=1.2
 }
 G {}
 K {type=res
-format="@spiceprefix@name @pinlist @model w=@W l=@L m=@m b=@b"
+format="@spiceprefix@name @pinlist @model w=@w l=@l m=@m b=@b"
 template="name=R1
-W=0.5e-6
-L=0.5e-6
+w=0.5e-6
+l=0.5e-6
 model=rsil
 spiceprefix=X
 b=0
 m=1
 "
+drc="res_drc @name @symname @model @w @l"
 }
 V {}
 S {}
@@ -42,10 +43,10 @@ L 4 -7.5 -17.5 0 -20 {}
 L 4 0 -30 0 -20 {}
 B 5 -2.5 27.5 2.5 32.5 {name=M dir=inout propag=1 pinnumber=2}
 B 5 -2.5 -32.5 2.5 -27.5 {name=P dir=inout propag=0 pinnumber=1}
-T {W/L = @W / @L} 15 -3.75 0 0 0.2 0.2 {layer=13}
+T {w/l = @w / @l} 15 -3.75 0 0 0.2 0.2 {layer=13}
 T {@model} 15 -16.25 0 0 0.2 0.2 {}
 T {@spiceprefix@name} 15 -28.75 0 0 0.2 0.2 {}
-T {tcleval(R=[ ev \{ ( 9.0e-6 / @W + 7.0 * ( (@b + 1)*@L + ( 1.081*( @W + 1.0e-8 ) + 0.18e-6 )*@b ) / ( @W + 1.0e-8 ) ) / @m \} ] )} 15 30 0 0 0.2 0.2 {layer=13}
+T {tcleval(R=[ ev \{ ( 9.0e-6 / @w + 7.0 * ( (@b + 1)*@l + ( 1.081*( @w + 1.0e-8 ) + 0.18e-6 )*@b ) / ( @w + 1.0e-8 ) ) / @m \} ] )} 15 30 0 0 0.2 0.2 {layer=13}
 T {} 15 20 0 0 0.2 0.2 {}
 T {b=@b} 15 6.25 0 0 0.2 0.2 {layer=13}
 T {m=@m} 15 16.25 0 0 0.2 0.2 {layer=13}
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/sg13_hv_nmos.sym b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/sg13_hv_nmos.sym
index a7904a85..8786f64f 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/sg13_hv_nmos.sym
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/sg13_hv_nmos.sym
@@ -16,16 +16,18 @@ v {xschem version=3.4.4 file_version=1.2
 }
 G {}
 K {type=nmos
-lvs_format="@name @pinlist @model L=@L W=@W ng=@ng m=@m"
-format="@spiceprefix@name @pinlist @model W=@W  L=@L ng=@ng m=@m"
+lvs_format="@spiceprefix@name @pinlist @model l=@l w=@w ng=@ng m=@m"
+format="@spiceprefix@name @pinlist @model w=@w  l=@l ng=@ng m=@m"
 template="name=M1
-L=0.45u
-W=1.0u
+l=0.45u
+w=1.0u
 ng=1
 m=1
 model=sg13_hv_nmos
 spiceprefix=X
-"}
+"
+drc="fet_drc @name @symname @model @w @l @ng"
+}
 V {}
 S {}
 E {}
@@ -35,7 +37,7 @@ L 4 20 17.5 20 30 {}
 L 4 7.5 17.5 20 17.5 {}
 L 4 7.5 -17.5 20 -17.5 {}
 L 4 -20 -0 2 -0 {}
-B 4 2 -14 3 16 {}
+B 4 2 -16 3 16 {}
 B 5 17.5 27.5 22.5 32.5 {name=D dir=inout}
 B 5 -22.5 -2.5 -17.5 2.5 {name=G dir=in}
 B 5 17.5 -32.5 22.5 -27.5 {name=S dir=inout}
@@ -50,5 +52,5 @@ T {G} -10 -10 0 1 0.15 0.15 {layer=7}
 T {@model} 30 31.25 2 1 0.2 0.2 {}
 T {m=@m} 31.25 -26.25 0 0 0.2 0.2 { layer=13}
 T {ng=@ng} 31.25 -18.75 0 0 0.2 0.2 {layer=13}
-T {L=@L} 31.25 -8.75 0 0 0.2 0.2 {layer=13}
-T {W=@W} 31.25 1.25 0 0 0.2 0.2 { layer=13}
+T {l=@l} 31.25 -8.75 0 0 0.2 0.2 {layer=13}
+T {w=@w} 31.25 1.25 0 0 0.2 0.2 { layer=13}
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/sg13_hv_pmos.sym b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/sg13_hv_pmos.sym
index 958300ca..f560ff73 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/sg13_hv_pmos.sym
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/sg13_hv_pmos.sym
@@ -16,16 +16,18 @@ v {xschem version=3.4.4 file_version=1.2
 }
 G {}
 K {type=pmos
-lvs_format="@name @pinlist @model L=@L W=@W ng=@ng m=@m"
-format="@spiceprefix@name @pinlist @model W=@W  L=@L ng=@ng m=@m"
+lvs_format="@spiceprefix@name @pinlist @model l=@l w=@w ng=@ng m=@m"
+format="@spiceprefix@name @pinlist @model w=@w  l=@l ng=@ng m=@m"
 template="name=M1
-L=0.45u
-W=1.0u
+l=0.45u
+w=1.0u
 ng=1
 m=1
 model=sg13_hv_pmos
 spiceprefix=X
-"}
+"
+drc="fet_drc @name @symname @model @w @l @ng"
+}
 V {}
 S {}
 E {}
@@ -50,5 +52,5 @@ T {G} -10 -10 0 1 0.15 0.15 {layer=7}
 T {@model} 30 31.25 2 1 0.2 0.2 {}
 T {m=@m} 31.25 -26.25 0 0 0.2 0.2 { layer=13}
 T {ng=@ng} 31.25 -18.75 0 0 0.2 0.2 {layer=13}
-T {L=@L} 31.25 -8.75 0 0 0.2 0.2 {layer=13}
-T {W=@W} 31.25 1.25 0 0 0.2 0.2 { layer=13}
+T {l=@l} 31.25 -8.75 0 0 0.2 0.2 {layer=13}
+T {w=@w} 31.25 1.25 0 0 0.2 0.2 { layer=13}
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/sg13_hv_rf_nmos.sym b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/sg13_hv_rf_nmos.sym
new file mode 100644
index 00000000..71d30f19
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/sg13_hv_rf_nmos.sym
@@ -0,0 +1,58 @@
+v {xschem version=3.1.0 file_version=1.2
+* Copyright 2023  IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+
+}
+G {}
+K {type=nmos
+lvs_format="@spiceprefix@name @pinlist @model l=@l w=@w ng=@ng m=@m"
+format="@spiceprefix@name @pinlist @model w=@w l=@l ng=@ng m=@m rfmode=@rfmode"
+template="name=M1
+l=0.35u
+w=1.0u
+ng=1
+m=1
+rfmode=1
+model=sg13_hv_nmos
+spiceprefix=X
+"
+drc="fet_drc @name @symname @model @w @l @ng"
+}
+V {}
+S {}
+E {}
+L 4 7.5 -22.5 7.5 22.5 {}
+L 4 20 -30 20 -17.5 {}
+L 4 20 17.5 20 30 {}
+L 4 7.5 17.5 20 17.5 {}
+L 4 7.5 -17.5 20 -17.5 {}
+L 4 -20 -0 2 -0 {}
+B 4 2 -16 3 16 {}
+B 5 17.5 27.5 22.5 32.5 {name=D dir=inout}
+B 5 -22.5 -2.5 -17.5 2.5 {name=G dir=in}
+B 5 17.5 -32.5 22.5 -27.5 {name=S dir=inout}
+B 5 19.921875 -0.078125 20.078125 0.078125 {name=B dir=in}
+P 4 4 12.5 -15 17.5 -17.5 12.5 -20 12.5 -15 {fill=true}
+P 5 4 15 -2.5 20 0 15 2.5 15 -2.5 {fill=true}
+T {@name} 5 -30 0 1 0.2 0.2 {}
+T {D} 22.5 17.5 0 0 0.15 0.15 {layer=7}
+T {S} 22.5 -17.5 2 1 0.15 0.15 {layer=7}
+T {B} 20 -10 0 0 0.15 0.15 {layer=7}
+T {G} -10 -10 0 1 0.15 0.15 {layer=7}
+T {@model} 30 31.25 2 1 0.2 0.2 {}
+T {m=@m} 31.25 -26.25 0 0 0.2 0.2 { layer=13}
+T {ng=@ng} 31.25 -18.75 0 0 0.2 0.2 { layer=13}
+T {l=@l} 31.25 -8.75 0 0 0.2 0.2 {layer=13}
+T {w=@w} 31.25 1.25 0 0 0.2 0.2 { layer=13}
+T {rfmode=@rfmode} 31.25 -36.25 0 0 0.2 0.2 { layer=13}
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/sg13_hv_rf_pmos.sym b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/sg13_hv_rf_pmos.sym
new file mode 100644
index 00000000..65e0f396
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/sg13_hv_rf_pmos.sym
@@ -0,0 +1,58 @@
+v {xschem version=3.4.4 file_version=1.2
+* Copyright 2023  IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+
+}
+G {}
+K {type=pmos
+lvs_format="@spiceprefix@name @pinlist @model L=@L W=@W ng=@ng m=@m rfmode=@rfmode"
+format="@spiceprefix@name @pinlist @model W=@W L=@L ng=@ng m=@m rfmode=@rfmode"
+template="name=M1
+L=0.45u
+W=1.0u
+ng=1
+m=1
+rfmode=1
+model=sg13_hv_pmos
+spiceprefix=X
+"
+drc="fet_drc @name @symname @model @w @l @ng"
+}
+V {}
+S {}
+E {}
+L 4 7.5 -22.5 7.5 22.5 {}
+L 4 20 -30 20 -17.5 {}
+L 4 20 17.5 20 30 {}
+L 4 7.5 17.5 20 17.5 {}
+L 4 7.5 -17.5 20 -17.5 {}
+L 4 -20 -0 2 -0 {}
+B 4 2 -16 3 16 {}
+B 5 17.5 27.5 22.5 32.5 {name=D dir=inout}
+B 5 -22.5 -2.5 -17.5 2.5 {name=G dir=in}
+B 5 17.5 -32.5 22.5 -27.5 {name=S dir=inout}
+B 5 19.921875 -0.078125 20.078125 0.078125 {name=B dir=in}
+P 4 4 12.5 -20 7.5 -17.5 12.5 -15 12.5 -20 {fill=true}
+P 5 4 15 -2.5 20 0 15 2.5 15 -2.5 {fill=true}
+T {@name} 5 -30 0 1 0.2 0.2 {}
+T {D} 22.5 17.5 0 0 0.15 0.15 {layer=7}
+T {S} 22.5 -17.5 2 1 0.15 0.15 {layer=7}
+T {B} 20 -10 0 0 0.15 0.15 {layer=7}
+T {G} -10 -10 0 1 0.15 0.15 {layer=7}
+T {@model} 30 31.25 2 1 0.2 0.2 {}
+T {m=@m} 31.25 -26.25 0 0 0.2 0.2 { layer=13}
+T {ng=@ng} 31.25 -18.75 0 0 0.2 0.2 { layer=13}
+T {L=@L} 31.25 -8.75 0 0 0.2 0.2 {layer=13}
+T {W=@W} 31.25 1.25 0 0 0.2 0.2 { layer=13}
+T {rfmode=@rfmode} 31.25 -36.25 0 0 0.2 0.2 { layer=13}
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/sg13_lv_nmos.sym b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/sg13_lv_nmos.sym
index ada14bb6..040a123e 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/sg13_lv_nmos.sym
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/sg13_lv_nmos.sym
@@ -1,5 +1,5 @@
 v {xschem version=3.4.4 file_version=1.2
-* Copyright 2023  IHP PDK Authors
+* Copyright 2024  IHP PDK Authors
 * 
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
@@ -16,16 +16,19 @@ v {xschem version=3.4.4 file_version=1.2
 }
 G {}
 K {type=nmos
-lvs_format="@name @pinlist @model L=@L W=@W ng=@ng m=@m"
-format="@spiceprefix@name @pinlist @model W=@W L=@L ng=@ng m=@m"
+lvs_format="@spiceprefix@name @pinlist @model l=@l w=@w ng=@ng m=@m"
+format="@spiceprefix@name @pinlist @model w=@w l=@l ng=@ng m=@m"
 template="name=M1
-L=0.45u
-W=1.0u
+l=0.45u
+w=1.0u
 ng=1
 m=1
 model=sg13_lv_nmos
 spiceprefix=X
-"}
+"
+drc="fet_drc @name @symname @model @w @l @ng"
+}
+
 V {}
 S {}
 E {}
@@ -50,5 +53,5 @@ T {G} -10 -10 0 1 0.15 0.15 {layer=7}
 T {@model} 30 31.25 2 1 0.2 0.2 {}
 T {m=@m} 31.25 -26.25 0 0 0.2 0.2 { layer=13}
 T {ng=@ng} 31.25 -18.75 0 0 0.2 0.2 { layer=13}
-T {L=@L} 31.25 -8.75 0 0 0.2 0.2 {layer=13}
-T {W=@W} 31.25 1.25 0 0 0.2 0.2 { layer=13}
+T {l=@l} 31.25 -8.75 0 0 0.2 0.2 {layer=13}
+T {w=@w} 31.25 1.25 0 0 0.2 0.2 { layer=13}
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/sg13_lv_pmos.sym b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/sg13_lv_pmos.sym
index 44ada49a..b1f6b3f4 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/sg13_lv_pmos.sym
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/sg13_lv_pmos.sym
@@ -16,16 +16,18 @@ v {xschem version=3.4.4 file_version=1.2
 }
 G {}
 K {type=pmos
-lvs_format="@name @pinlist @model L=@L W=@W ng=@ng m=@m"
-format="@spiceprefix@name @pinlist @model W=@W L=@L ng=@ng m=@m"
+lvs_format="@name @pinlist @model l=@l w=@w ng=@ng m=@m"
+format="@spiceprefix@name @pinlist @model w=@w l=@l ng=@ng m=@m"
 template="name=M1
-L=0.45u
-W=1.0u
+l=0.45u
+w=1.0u
 ng=1
 m=1
 model=sg13_lv_pmos
 spiceprefix=X
-"}
+"
+drc="fet_drc @name @symname @model @w @l @ng"
+}
 V {}
 S {}
 E {}
@@ -50,5 +52,5 @@ T {G} -10 -10 0 1 0.15 0.15 {layer=7}
 T {@model} 30 31.25 2 1 0.2 0.2 {}
 T {m=@m} 31.25 -26.25 0 0 0.2 0.2 { layer=13}
 T {ng=@ng} 31.25 -18.75 0 0 0.2 0.2 { layer=13}
-T {L=@L} 31.25 -8.75 0 0 0.2 0.2 {layer=13}
-T {W=@W} 31.25 1.25 0 0 0.2 0.2 { layer=13}
+T {l=@l} 31.25 -8.75 0 0 0.2 0.2 {layer=13}
+T {w=@w} 31.25 1.25 0 0 0.2 0.2 { layer=13}
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/sg13_lv_rf_nmos.sym b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/sg13_lv_rf_nmos.sym
index 46cf93b0..251da73b 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/sg13_lv_rf_nmos.sym
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/sg13_lv_rf_nmos.sym
@@ -16,17 +16,19 @@ v {xschem version=3.1.0 file_version=1.2
 }
 G {}
 K {type=nmos
-lvs_format="@name @pinlist @model L=@L W=@W ng=@ng m=@m"
-format="@spiceprefix@name @pinlist @model W=@W L=@L ng=@ng m=@m rfmode=@rfmode"
+lvs_format="@spiceprefix@name @pinlist @model l=@l w=@w ng=@ng m=@m"
+format="@spiceprefix@name @pinlist @model w=@w l=@l ng=@ng m=@m rfmode=@rfmode"
 template="name=M1
-L=0.35u
-W=1.0u
+l=0.35u
+w=1.0u
 ng=1
 m=1
 rfmode=1
 model=sg13_lv_nmos
 spiceprefix=X
-"}
+"
+drc="fet_drc @name @symname @model @w @l @ng"
+}
 V {}
 S {}
 E {}
@@ -51,6 +53,6 @@ T {G} -10 -10 0 1 0.15 0.15 {layer=7}
 T {@model} 30 31.25 2 1 0.2 0.2 {}
 T {m=@m} 31.25 -26.25 0 0 0.2 0.2 { layer=13}
 T {ng=@ng} 31.25 -18.75 0 0 0.2 0.2 { layer=13}
-T {L=@L} 31.25 -8.75 0 0 0.2 0.2 {layer=13}
-T {W=@W} 31.25 1.25 0 0 0.2 0.2 { layer=13}
+T {l=@l} 31.25 -8.75 0 0 0.2 0.2 {layer=13}
+T {w=@w} 31.25 1.25 0 0 0.2 0.2 { layer=13}
 T {rfmode=@rfmode} 31.25 -36.25 0 0 0.2 0.2 { layer=13}
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/sg13_lv_rf_pmos.sym b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/sg13_lv_rf_pmos.sym
index bf67aa12..a8b2b510 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/sg13_lv_rf_pmos.sym
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_pr/sg13_lv_rf_pmos.sym
@@ -16,7 +16,7 @@ v {xschem version=3.4.4 file_version=1.2
 }
 G {}
 K {type=pmos
-lvs_format="@name @pinlist @model L=@L W=@W ng=@ng m=@m rfmode=@rfmode"
+lvs_format="@spiceprefix@name @pinlist @model L=@L W=@W ng=@ng m=@m rfmode=@rfmode"
 format="@spiceprefix@name @pinlist @model W=@W L=@L ng=@ng m=@m rfmode=@rfmode"
 template="name=M1
 L=0.45u
@@ -26,7 +26,9 @@ m=1
 rfmode=1
 model=sg13_lv_pmos
 spiceprefix=X
-"}
+"
+drc="fet_drc @name @symname @model @w @l @ng"
+}
 V {}
 S {}
 E {}
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/IHP_testcases.sch b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/IHP_testcases.sch
index b3f691c0..2a0d9794 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/IHP_testcases.sch
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/IHP_testcases.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 * Copyright 2023 IHP PDK Authors
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/ac_lv_nmosrf.sch b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/ac_lv_nmosrf.sch
index d16951b6..2bc35d0c 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/ac_lv_nmosrf.sch
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/ac_lv_nmosrf.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 }
 G {}
 K {}
@@ -7,8 +7,8 @@ S {}
 E {}
 L 4 -240 -300 -220 -300 {}
 B 2 360 -410 1160 -10 {flags=graph
-y1=0.0088
-y2=0.022
+y1=0.0014
+y2=0.0015
 ypos1=0
 ypos2=2
 divy=10
@@ -98,14 +98,13 @@ lab=Vout2}
 C {devices/code_shown.sym} -200 160 0 0 {name=MODEL only_toplevel=true
 format="tcleval( @value )"
 value="
-.lib $::SG13G2_MODELS/cornerMOSlv.lib mos_tt
-.lib $::SG13G2_MODELS/cornerRES.lib res_typ 
+.lib cornerMOSlv.lib mos_tt
+.lib cornerRES.lib res_typ 
 "}
 C {devices/code_shown.sym} 1190 -310 0 0 {name=NGSPICE only_toplevel=true 
 value="
 .param temp=27
 .control
-pre_osdi ./psp103_nqs.osdi
 save all 
 ac dec 1001 10meg 10000meg 
 let vd1 = abs(Vout1)
@@ -117,73 +116,69 @@ write ac_lv_nmosrf.raw
 "}
 C {devices/gnd.sym} 160 50 0 0 {name=l1 lab=GND}
 C {devices/gnd.sym} 30 50 0 0 {name=l2 lab=GND}
-C {devices/vsource.sym} 30 0 0 0 {name=Vgs value="dc 0.75 ac 0.01 "}
-C {devices/vsource.sym} 290 -40 0 0 {name=Vds value=1.5}
+C {devices/vsource.sym} 30 0 0 0 {name=Vgs value="dc 0.45 ac 0.01 "}
+C {devices/vsource.sym} 290 -40 0 0 {name=Vds value=1.2}
 C {devices/gnd.sym} 290 50 0 0 {name=l3 lab=GND}
 C {devices/gnd.sym} 210 50 0 0 {name=l4 lab=GND}
 C {devices/title.sym} -130 260 0 0 {name=l5 author="Copyright 2023 IHP PDK Authors"}
 C {devices/launcher.sym} -210 -300 0 0 {name=h5
 descr="load waves Ctrl + left click" 
 tclcommand="xschem raw_read $netlist_dir/ac_lv_nmosrf.raw ac"}
-C {sg13g2_pr/sg13_lv_rf_nmos.sym} 140 -40 2 1 {name=M1
-L=0.35u
-W=1.0u
-ng=1
+C {devices/lab_pin.sym} 150 -110 1 0 {name=p1 sig_type=std_logic lab=Vout1}
+C {devices/gnd.sym} -170 60 0 0 {name=l6 lab=GND}
+C {devices/gnd.sym} -300 60 0 0 {name=l7 lab=GND}
+C {devices/vsource.sym} -300 10 0 0 {name=Vgs1 value="dc 0.45 ac 0.01 "}
+C {devices/vsource.sym} -40 -30 0 0 {name=Vds2 value=1.2}
+C {devices/gnd.sym} -40 60 0 0 {name=l8 lab=GND}
+C {devices/gnd.sym} -120 60 0 0 {name=l9 lab=GND}
+C {devices/lab_pin.sym} -180 -100 1 0 {name=p2 sig_type=std_logic lab=Vout2}
+C {sg13g2_pr/rppd.sym} -250 -30 3 0 {name=R1
+w=0.5e-6
+l=0.5e-6
+model=rppd
+spiceprefix=X
+b=0
 m=1
-rfmode=1
-model=sg13_lv_nmos
+}
+C {sg13g2_pr/rppd.sym} -110 -100 3 0 {name=R2
+w=0.5e-6
+l=0.5e-6
+model=rppd
 spiceprefix=X
+b=0
+m=1
 }
-C {sg13g2_pr/rppd.sym} 220 -110 3 0 {name=R1
-W=0.2e-6
-L=0.5e-5
+C {sg13g2_pr/rppd.sym} 80 -40 3 0 {name=R3
+w=0.5e-6
+l=0.5e-6
 model=rppd
 spiceprefix=X
+b=0
 m=1
-R=7.0
-Imax=0.3e-6
 }
-C {devices/lab_pin.sym} 150 -110 1 0 {name=p1 sig_type=std_logic lab=Vout1}
-C {sg13g2_pr/rppd.sym} 80 -40 3 0 {name=R2
-W=0.2e-6
-L=0.5e-5
+C {sg13g2_pr/rppd.sym} 220 -110 3 0 {name=R4
+w=0.5e-6
+l=0.5e-6
 model=rppd
 spiceprefix=X
+b=0
 m=1
-R=7.0
-Imax=0.3e-6
 }
-C {devices/gnd.sym} -170 60 0 0 {name=l6 lab=GND}
-C {devices/gnd.sym} -300 60 0 0 {name=l7 lab=GND}
-C {devices/vsource.sym} -300 10 0 0 {name=Vgs1 value="dc 0.75 ac 0.01 "}
-C {devices/vsource.sym} -40 -30 0 0 {name=Vds2 value=1.5}
-C {devices/gnd.sym} -40 60 0 0 {name=l8 lab=GND}
-C {devices/gnd.sym} -120 60 0 0 {name=l9 lab=GND}
-C {sg13g2_pr/sg13_lv_rf_nmos.sym} -190 -30 2 1 {name=M2
-L=0.35u
-W=1.0u
+C {sg13g2_pr/sg13_lv_rf_nmos.sym} -190 -30 2 1 {name=M1
+l=0.35u
+w=1.0u
 ng=1
 m=1
 rfmode=0
 model=sg13_lv_nmos
 spiceprefix=X
 }
-C {sg13g2_pr/rppd.sym} -110 -100 3 0 {name=R3
-W=0.2e-6
-L=0.5e-5
-model=rppd
-spiceprefix=X
+C {sg13g2_pr/sg13_lv_rf_nmos.sym} 140 -40 2 1 {name=M2
+l=0.35u
+w=1.0u
+ng=1
 m=1
-R=7.0
-Imax=0.3e-6
-}
-C {devices/lab_pin.sym} -180 -100 1 0 {name=p2 sig_type=std_logic lab=Vout2}
-C {sg13g2_pr/rppd.sym} -250 -30 3 0 {name=R4
-W=0.2e-6
-L=0.5e-5
-model=rppd
+rfmode=1
+model=sg13_lv_nmos
 spiceprefix=X
-m=1
-R=7.0
-Imax=0.3e-6
 }
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/ac_mim_cap.sch b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/ac_mim_cap.sch
index 0a1ea33a..74b17ccd 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/ac_mim_cap.sch
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/ac_mim_cap.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 * Copyright 2021 Stefan Frederik Schippers
 * 
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -39,8 +39,8 @@ dataset=-1
 unitx=1
 logx=1
 logy=1
-y1=-1.4
-y2=-2.5e-07
+y1=-0.26
+y2=-7.3e-07
 color=4
 node=mag
 rainbow=1}
@@ -92,8 +92,8 @@ m=1}
 C {devices/gnd.sym} 690 -230 0 0 {name=l5 lab=GND}
 C {devices/lab_pin.sym} 370 -400 1 0 {name=p1 sig_type=std_logic lab=in}
 C {devices/lab_pin.sym} 690 -390 1 0 {name=p2 sig_type=std_logic lab=out}
-C {sg13g2_pr/cap_cmim.sym} 530 -380 1 0 {name=C1 model=cap_cmim W=7.0e-6 L=7.0e-6 MF=1 spiceprefix=X}
 C {devices/launcher.sym} 200 -740 0 0 {name=h5
 descr="load waves" 
 tclcommand="xschem raw_read $netlist_dir/ac_mim_cap.raw ac"
 }
+C {sg13g2_pr/cap_cmim.sym} 530 -380 1 0 {name=C1 model=cap_cmim w=10.0e-6 l=70.0e-6 m=1 spiceprefix=X}
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_diode_op.sch b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_diode_op.sch
index 0ddc79fd..82541c69 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_diode_op.sch
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_diode_op.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 }
 G {}
 K {}
@@ -67,23 +67,25 @@ write dc_diode_op.raw
 wrdata dc_diode.csv I(Vmda) I(Vmdp)
 .endc
 "}
-C {sg13g2_pr/dantenna.sym} -350 10 2 0 {name=XD1
-model=dantenna
-l=780n
-w=780n
-}
 C {devices/title.sym} -360 130 0 0 {name=l5 author="Copyright 2023 IHP PDK Authors"}
 C {devices/launcher.sym} -470 -260 0 0 {name=h5
 descr="Load IV curve" 
 tclcommand="xschem raw_read $netlist_dir/dc_diode_op.raw dc"
 }
 C {devices/gnd.sym} -170 50 0 0 {name=l3 lab=GND}
-C {sg13g2_pr/dpantenna.sym} -170 10 2 0 {name=XD2
-model=dpantenna
-l=780n
-w=780n
-}
 C {devices/gnd.sym} -350 50 0 0 {name=l1 lab=GND}
 C {devices/vsource.sym} -500 -10 0 0 {name=V1 value=0.7}
 C {devices/ammeter.sym} -350 -60 0 0 {name=Vmda}
 C {devices/ammeter.sym} -170 -60 0 0 {name=Vmdp}
+C {sg13g2_pr/dpantenna.sym} -350 10 2 0 {name=D2
+model=dpantenna
+l=0.78u
+w=0.78u
+spiceprefix=X
+}
+C {sg13g2_pr/dantenna.sym} -170 10 2 0 {name=D1
+model=dantenna
+l=0.78u
+w=0.78u
+spiceprefix=X
+}
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_hbt_13g2.sch b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_hbt_13g2.sch
index e9a10a10..7cd3a725 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_hbt_13g2.sch
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_hbt_13g2.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 }
 G {}
 K {}
@@ -7,7 +7,7 @@ S {}
 E {}
 B 2 -280 -540 520 -140 {flags=graph
 
-y2=0.0026
+y2=0.0027
 ypos1=0
 ypos2=2
 divy=5
@@ -24,7 +24,7 @@ logx=0
 logy=0
 color=4
 node=i(Vc)
-y1=-5.5e-05
+y1=-1.9e-05
 rainbow=0}
 T {Nx - number of emitters} -210 110 0 0 0.2 0.2 {}
 N -300 60 -300 80 {
@@ -62,7 +62,7 @@ save all
 op
 print I(Vc)
 reset 
-dc Vce 0 2 0.01 I0 0 5u 0.1u
+dc Vce 0 1.5 0.01 I0 0 5u 0.1u
 write test_npn_13G2.raw
 .endc
 "}
@@ -76,9 +76,10 @@ C {devices/launcher.sym} 70 -70 0 0 {name=h5
 descr="load waves" 
 tclcommand="xschem raw_read $netlist_dir/test_npn_13G2.raw dc"
 }
+C {devices/isource.sym} -300 30 2 0 {name=I0 value=1u}
+C {devices/ammeter.sym} -110 -80 1 0 {name=Vc}
 C {sg13g2_pr/npn13G2.sym} -190 -10 0 0 {name=Q1
 model=npn13G2
 spiceprefix=X
-Nx=1}
-C {devices/isource.sym} -300 30 2 0 {name=I0 value=1u}
-C {devices/ammeter.sym} -110 -80 1 0 {name=Vc}
+Nx=1
+le=0.9e-6}
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_hv_nmos.sch b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_hv_nmos.sch
index 47fb68d5..895967b7 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_hv_nmos.sch
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_hv_nmos.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 }
 G {}
 K {}
@@ -6,8 +6,8 @@ V {}
 S {}
 E {}
 B 2 150 -490 950 -90 {flags=graph
-y1=0
-y2=2e-05
+y1=-0
+y2=0.00012
 ypos1=0
 ypos2=2
 divy=5
@@ -49,18 +49,13 @@ lab=#net1}
 C {devices/code_shown.sym} -200 160 0 0 {name=MODEL only_toplevel=true
 format="tcleval( @value )"
 value="
-.lib $::SG13G2_MODELS/cornerMOShv.lib mos_tt
+.lib cornerMOShv.lib mos_tt
 "}
 C {devices/code_shown.sym} 310 -30 0 0 {name=NGSPICE only_toplevel=true 
 value="
 .param temp=27
-.control
-pre_osdi ./psp103_nqs.osdi
-save all 
-op
-print all
-reset 
-dc Vds 0 3 0.01 Vgs 0. 0.9 0.1
+.control 
+dc Vds 0 3.0 0.01 Vgs 0.3 1.5 0.05
 write dc_hv_nmos.raw
 .endc
 "}
@@ -75,12 +70,12 @@ C {devices/launcher.sym} -200 -160 0 0 {name=h5
 descr="load waves Ctrl + left click" 
 tclcommand="xschem raw_read $netlist_dir/dc_hv_nmos.raw dc"
 }
+C {devices/ammeter.sym} 80 -70 1 0 {name=Vd}
 C {sg13g2_pr/sg13_hv_nmos.sym} 0 0 2 1 {name=M1
-L=0.45u
-W=1.0u
+l=0.45u
+w=1.0u
 ng=1
 m=1
 model=sg13_hv_nmos
 spiceprefix=X
 }
-C {devices/ammeter.sym} 80 -70 1 0 {name=Vd}
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_hv_pmos.sch b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_hv_pmos.sch
index 8be1d68b..81588337 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_hv_pmos.sch
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_hv_pmos.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 }
 G {}
 K {}
@@ -6,24 +6,25 @@ V {}
 S {}
 E {}
 B 2 150 -510 950 -110 {flags=graph
-y1=0
-y2=1.1e-05
+y1=-1.1e-05
+y2=-0
 ypos1=0
 ypos2=2
 divy=5
 subdivy=1
 unity=1
-x1=0
-x2=-2
+x1=-2
+x2=0
 divx=5
 subdivx=1
-node=i(vds)
-color=4
+
+
 dataset=-1
 unitx=1
 logx=0
 logy=0
-}
+color=4
+node=i(vd)}
 N -110 70 -110 90 {
 lab=GND}
 N -110 -0 -110 10 {
@@ -49,20 +50,17 @@ lab=#net3}
 C {devices/code_shown.sym} -200 160 0 0 {name=MODEL only_toplevel=true
 format="tcleval( @value )"
 value="
-.lib $::SG13G2_MODELS/cornerMOShv.lib mos_tt
+.lib cornerMOShv.lib mos_tt
 "}
 C {devices/code_shown.sym} 290 -10 0 0 {name=NGSPICE only_toplevel=true 
 value="
 .param temp=27
 .control
-pre_osdi ./psp103_nqs.osdi
-save all 
-op
+save all
+op 
 print I(Vd)
-reset 
 dc Vds 0 -2 -0.01 Vgs -0.45 -1.1 -0.05
 write dc_hv_pmos.raw
-*plot all
 .endc
 "}
 C {devices/gnd.sym} 20 90 0 0 {name=l1 lab=GND}
@@ -77,8 +75,8 @@ descr="load waves"
 tclcommand="xschem raw_read $netlist_dir/dc_hv_pmos.raw dc"
 }
 C {sg13g2_pr/sg13_hv_pmos.sym} 0 0 2 1 {name=M1
-L=0.45u
-W=1.0u
+l=0.45u
+w=1.0u
 ng=1
 m=1
 model=sg13_hv_pmos
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_logic_not.sch b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_logic_not.sch
index e67ff877..03903297 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_logic_not.sch
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_logic_not.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 }
 G {}
 K {}
@@ -72,14 +72,12 @@ lab=in}
 C {devices/code_shown.sym} -300 170 0 0 {name=MODEL only_toplevel=true
 format="tcleval( @value )"
 value="
-.lib $::SG13G2_MODELS/cornerMOSlv.lib mos_tt
-.lib $::SG13G2_MODELS/cornerRES.lib res_typ
+.lib cornerMOSlv.lib mos_tt
 "}
 C {devices/code_shown.sym} -360 -260 0 0 {name=NGSPICE only_toplevel=true 
 value="
 .param temp=27
 .control
-pre_osdi ./psp103_nqs.osdi
 save all 
 dc Vin 0 1.8 1m
 let gain = -deriv(V(out))/10
@@ -98,16 +96,16 @@ descr="load waves Ctrl + left click"
 tclcommand="xschem raw_read $netlist_dir/dc_logic_not.raw dc"
 }
 C {sg13g2_pr/sg13_lv_nmos.sym} 0 30 2 1 {name=M1
-L=0.45u
-W=1.0u
+l=0.45u
+w=1.0u
 ng=1
 m=1
 model=sg13_lv_nmos
 spiceprefix=X
 }
 C {sg13g2_pr/sg13_lv_pmos.sym} 0 -70 0 0 {name=M2
-L=0.45u
-W=1.0u
+l=0.45u
+w=1.0u
 ng=1
 m=1
 model=sg13_lv_pmos
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_lv_nmos.sch b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_lv_nmos.sch
index 23a0c16d..d89e0242 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_lv_nmos.sch
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_lv_nmos.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 }
 G {}
 K {}
@@ -6,15 +6,15 @@ V {}
 S {}
 E {}
 B 2 240 -350 1040 50 {flags=graph
-y1=-2.4e-11
-y2=0.00015
+y1=-6.4e-14
+y2=7.9e-06
 ypos1=0
 ypos2=2
 divy=5
 subdivy=1
 unity=1
 x1=0
-x2=3
+x2=1.2
 divx=5
 subdivx=1
 node=i(vd)
@@ -48,17 +48,15 @@ N -110 0 -20 0 {
 lab=#net1}
 C {devices/code_shown.sym} -290 190 0 0 {name=MODEL only_toplevel=true
 format="tcleval( @value )"
-value=".lib $::SG13G2_MODELS/cornerMOSlv.lib mos_tt
+value=".lib cornerMOSlv.lib mos_tt
 "}
 C {devices/code_shown.sym} -300 -320 0 0 {name=NGSPICE only_toplevel=true 
 value="
 .param temp=27
 .control
-pre_osdi ./psp103_nqs.osdi
 save all 
 op
-*reset 
-dc Vds 0 3 0.01 Vgs 0. 0.9 0.1
+dc Vds 0 1.2 0.01 Vgs 0.3 0.5 0.05
 write dc_lv_nmos.raw
 .endc
 "}
@@ -73,12 +71,12 @@ C {devices/launcher.sym} 310 90 0 0 {name=h5
 descr="load waves Ctrl + left click" 
 tclcommand="xschem raw_read $netlist_dir/dc_lv_nmos.raw dc"
 }
+C {devices/ammeter.sym} 80 -70 1 0 {name=Vd}
 C {sg13g2_pr/sg13_lv_nmos.sym} 0 0 2 1 {name=M1
-L=0.45u
-W=1.0u
+l=0.13u
+w=1.0u
 ng=1
 m=1
 model=sg13_lv_nmos
 spiceprefix=X
 }
-C {devices/ammeter.sym} 80 -70 1 0 {name=Vd}
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_lv_pmos.sch b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_lv_pmos.sch
index 33f44c63..4ea3638d 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_lv_pmos.sch
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_lv_pmos.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 }
 G {}
 K {}
@@ -6,18 +6,18 @@ V {}
 S {}
 E {}
 B 2 150 -510 950 -110 {flags=graph
-y1=-1.4e-11
-y2=5.2e-05
+y1=-5e-05
+y2=1.4e-11
 ypos1=0
 ypos2=2
 divy=5
 subdivy=1
 unity=1
-x1=0
-x2=-2
+x1=-1.2
+x2=0
 divx=5
 subdivx=1
-node=i(vds)
+node=i(vd)
 color=4
 dataset=-1
 unitx=1
@@ -53,20 +53,14 @@ lab=#net3}
 C {devices/code_shown.sym} -200 160 0 0 {name=MODEL only_toplevel=true
 format="tcleval( @value )"
 value="
-.lib $::SG13G2_MODELS/cornerMOSlv.lib mos_tt
+.lib cornerMOSlv.lib mos_tt
 "}
 C {devices/code_shown.sym} 290 -10 0 0 {name=NGSPICE only_toplevel=true 
 value="
 .param temp=27
 .control
-pre_osdi ./psp103_nqs.osdi
-save all 
-op
-print I(Vd)
-*reset 
-dc Vds 0 -2 -0.01 Vgs -0.45 -1.1 -0.05
+dc Vds 0 -1.2 -0.01 Vgs -0.35 -1.1 -0.05
 write dc_lv_pmos.raw
-*plot all
 .endc
 "}
 C {devices/gnd.sym} 20 90 0 0 {name=l1 lab=GND}
@@ -81,8 +75,8 @@ descr="load waves"
 tclcommand="xschem raw_read $netlist_dir/dc_lv_pmos.raw dc"
 }
 C {sg13g2_pr/sg13_lv_pmos.sym} 0 0 2 1 {name=M1
-L=0.45u
-W=1.0u
+l=0.45u
+w=1.0u
 ng=1
 m=1
 model=sg13_lv_pmos
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_mos_cs_temp.sch b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_mos_cs_temp.sch
index 56040879..2a0970b1 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_mos_cs_temp.sch
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_mos_cs_temp.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 }
 G {}
 K {}
@@ -6,8 +6,8 @@ V {}
 S {}
 E {}
 B 2 250 -620 1050 -220 {flags=graph
-y1=-1.5
-y2=1
+y1=-1.3
+y2=0.92
 ypos1=0
 ypos2=2
 
@@ -36,11 +36,7 @@ N -20 80 -20 140 {
 lab=GND}
 N -20 50 30 50 {
 lab=GND}
-N 80 50 80 140 {
-lab=GND}
-N -70 50 -60 50 {
-lab=Vgs1}
-N -130 50 -70 50 {
+N -90 50 -60 50 {
 lab=Vgs1}
 N -20 0 -20 20 {
 lab=Vgs1}
@@ -50,11 +46,7 @@ N 240 50 290 50 {
 lab=GND}
 N 290 50 290 140 {
 lab=GND}
-N 190 50 200 50 {
-lab=Vgs2}
-N 130 50 190 50 {
-lab=Vgs2}
-N 240 0 240 20 {
+N 170 50 200 50 {
 lab=Vgs2}
 N 640 80 640 140 {
 lab=GND}
@@ -62,9 +54,7 @@ N 640 50 690 50 {
 lab=GND}
 N 690 50 690 140 {
 lab=GND}
-N 590 50 600 50 {
-lab=Vgs3}
-N 530 50 590 50 {
+N 560 50 600 50 {
 lab=Vgs3}
 N 640 0 640 20 {
 lab=Vgs3}
@@ -74,11 +64,7 @@ N 870 50 920 50 {
 lab=GND}
 N 920 50 920 140 {
 lab=GND}
-N 820 50 830 50 {
-lab=Vgs4}
-N 760 50 820 50 {
-lab=Vgs4}
-N 870 0 870 20 {
+N 790 50 830 50 {
 lab=Vgs4}
 N -90 0 -20 0 {
 lab=Vgs1}
@@ -90,7 +76,7 @@ N -20 -40 -20 0 {
 lab=Vgs1}
 N 240 -120 240 -100 {
 lab=GND}
-N 240 -40 240 0 {
+N 240 -10 240 20 {
 lab=Vgs2}
 N 640 -30 640 0 {
 lab=Vgs3}
@@ -98,7 +84,7 @@ N 640 -110 640 -90 {
 lab=GND}
 N 870 -110 870 -90 {
 lab=GND}
-N 870 -30 870 0 {
+N 870 -10 870 20 {
 lab=Vgs4}
 N 560 0 560 50 {
 lab=Vgs3}
@@ -114,18 +100,28 @@ N 170 -10 240 -10 {
 lab=Vgs2}
 N 30 50 30 140 {
 lab=GND}
+N -130 50 -90 50 {
+lab=Vgs1}
+N 530 50 560 50 {
+lab=Vgs3}
+N 760 50 790 50 {
+lab=Vgs4}
+N 870 -30 870 -10 {
+lab=Vgs4}
+N 130 50 170 50 {
+lab=Vgs2}
+N 240 -40 240 -10 {
+lab=Vgs2}
 C {devices/code_shown.sym} -320 -630 0 0 {name=MODEL only_toplevel=true
 format="tcleval( @value )"
 value="
-.lib $::SG13G2_MODELS/cornerMOSlv.lib mos_tt
-.lib $::SG13G2_MODELS/cornerMOShv.lib mos_tt
+.lib cornerMOSlv.lib mos_tt
+.lib cornerMOShv.lib mos_tt
 "}
 C {devices/code_shown.sym} -310 -510 0 0 {name=NGSPICE only_toplevel=true 
 value="
-.savecurrents
 .param temp=27
 .control
-* pre_osdi ./psp103_nqs.osdi
 save all 
 dc temp -40 125 1
 write mos_temp.raw
@@ -133,15 +129,14 @@ wrdata mos_temp.csv Vgs1 Vgs2 Vgs3 Vgs4
 .endc
 "}
 C {devices/gnd.sym} -20 140 0 0 {name=l1 lab=GND}
-C {devices/gnd.sym} 80 140 0 0 {name=l4 lab=GND}
 C {devices/title.sym} -130 260 0 0 {name=l5 author="Copyright 2023 IHP PDK Authors"}
 C {devices/launcher.sym} -210 -250 0 0 {name=h5
 descr="load waves Ctrl + left click" 
 tclcommand="xschem raw_read $netlist_dir/mos_temp.raw dc"
 }
 C {sg13g2_pr/sg13_lv_nmos.sym} -40 50 2 1 {name=M1
-L=1.0u
-W=2.0u
+l=1.0u
+w=2.0u
 ng=1
 m=1
 model=sg13_lv_nmos
@@ -152,8 +147,8 @@ C {devices/gnd.sym} 240 140 0 0 {name=l6 lab=GND}
 C {devices/gnd.sym} 290 140 0 0 {name=l7 lab=GND}
 C {devices/lab_pin.sym} 130 50 0 0 {name=p5 sig_type=std_logic lab=Vgs2}
 C {sg13g2_pr/sg13_hv_nmos.sym} 220 50 2 1 {name=M2
-L=1.0u
-W=2.0u
+l=1.0u
+w=2.0u
 ng=1
 m=1
 model=sg13_hv_nmos
@@ -166,16 +161,16 @@ C {devices/gnd.sym} 870 140 0 0 {name=l10 lab=GND}
 C {devices/gnd.sym} 920 140 0 0 {name=l11 lab=GND}
 C {devices/lab_pin.sym} 760 50 0 0 {name=p9 sig_type=std_logic lab=Vgs4}
 C {sg13g2_pr/sg13_lv_pmos.sym} 620 50 2 1 {name=M3
-L=1.0u
-W=2.0u
+l=1.0u
+w=2.0u
 ng=1
 m=1
 model=sg13_lv_pmos
 spiceprefix=X
 }
 C {sg13g2_pr/sg13_hv_pmos.sym} 850 50 2 1 {name=M4
-L=1.0u
-W=2.0u
+l=1.0u
+w=2.0u
 ng=1
 m=1
 model=sg13_hv_pmos
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_mos_temp.sch b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_mos_temp.sch
index f0e8119d..cba02e35 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_mos_temp.sch
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_mos_temp.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 }
 G {}
 K {}
@@ -105,16 +105,14 @@ lab=Vdsp}
 C {devices/code_shown.sym} -330 -530 0 0 {name=MODEL only_toplevel=true
 format="tcleval( @value )"
 value="
-.lib $::SG13G2_MODELS/cornerMOSlv.lib mos_tt
-.lib $::SG13G2_MODELS/cornerMOShv.lib mos_tt
+.lib cornerMOSlv.lib mos_tt
+.lib cornerMOShv.lib mos_tt
 "}
 C {devices/code_shown.sym} -320 -410 0 0 {name=NGSPICE only_toplevel=true 
 value="
-.savecurrents
 .param temp=27
 .control
-pre_osdi ./psp103_nqs.osdi
-save all 
+save all
 dc temp -40 125 1
 write mos_temp.raw
 wrdata mos_temp.csv I(Vm1) I(Vm2) I(Vm3) I(Vm4)
@@ -123,7 +121,7 @@ wrdata mos_temp.csv I(Vm1) I(Vm2) I(Vm3) I(Vm4)
 C {devices/gnd.sym} -20 200 0 0 {name=l1 lab=GND}
 C {devices/gnd.sym} -280 200 0 0 {name=l2 lab=GND}
 C {devices/vsource.sym} -280 150 0 0 {name=Vgs value=0.75}
-C {devices/vsource.sym} -280 -30 0 0 {name=Vds value=1.5}
+C {devices/vsource.sym} -280 -30 0 0 {name=Vds value=1.2}
 C {devices/gnd.sym} -280 60 0 0 {name=l3 lab=GND}
 C {devices/gnd.sym} 30 200 0 0 {name=l4 lab=GND}
 C {devices/title.sym} -130 260 0 0 {name=l5 author="Copyright 2023 IHP PDK Authors"}
@@ -132,8 +130,8 @@ descr="load waves Ctrl + left click"
 tclcommand="xschem raw_read $netlist_dir/mos_temp.raw dc"
 }
 C {sg13g2_pr/sg13_lv_nmos.sym} -40 110 2 1 {name=M1
-L=0.35u
-W=1.0u
+l=0.35u
+w=1.0u
 ng=1
 m=1
 model=sg13_lv_nmos
@@ -150,8 +148,8 @@ C {devices/lab_pin.sym} 80 110 0 0 {name=p5 sig_type=std_logic lab=Vgs}
 C {devices/ammeter.sym} 190 30 0 0 {name=Vm2}
 C {devices/lab_pin.sym} 190 -20 2 0 {name=p6 sig_type=std_logic lab=Vds}
 C {sg13g2_pr/sg13_hv_nmos.sym} 170 110 2 1 {name=M2
-L=0.35u
-W=1.0u
+l=0.35u
+w=1.0u
 ng=1
 m=1
 model=sg13_hv_nmos
@@ -168,16 +166,16 @@ C {devices/lab_pin.sym} 760 110 0 0 {name=p9 sig_type=std_logic lab=Vgsp}
 C {devices/ammeter.sym} 870 30 0 0 {name=Vm4}
 C {devices/lab_pin.sym} 870 -20 2 0 {name=p10 sig_type=std_logic lab=Vdsp}
 C {sg13g2_pr/sg13_lv_pmos.sym} 640 110 2 1 {name=M3
-L=0.35u
-W=1.0u
+l=0.35u
+w=1.0u
 ng=1
 m=1
 model=sg13_lv_pmos
 spiceprefix=X
 }
 C {sg13g2_pr/sg13_hv_pmos.sym} 850 110 2 1 {name=M4
-L=0.35u
-W=1.0u
+l=0.35u
+w=1.0u
 ng=1
 m=1
 model=sg13_hv_pmos
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_pnpMPA.sch b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_pnpMPA.sch
index 5a7257d3..22b3bd56 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_pnpMPA.sch
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_pnpMPA.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 }
 G {}
 K {}
@@ -6,8 +6,8 @@ V {}
 S {}
 E {}
 B 2 -280 -540 520 -140 {flags=graph
-y1=0.4
-y2=0.7
+y1=0.65
+y2=0.9
 ypos1=0
 ypos2=2
 divy=5
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_res_temp.sch b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_res_temp.sch
index 751bc475..a46ed3dd 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_res_temp.sch
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/dc_res_temp.sch
@@ -95,30 +95,27 @@ C {devices/gnd.sym} 240 90 0 0 {name=l2 lab=GND}
 C {devices/ammeter.sym} 240 -40 0 0 {name=Vppd}
 C {devices/gnd.sym} 420 90 0 0 {name=l4 lab=GND}
 C {devices/ammeter.sym} 420 -40 0 0 {name=Vrh}
+C {sg13g2_pr/rsil.sym} 90 40 0 0 {name=R1
+w=0.5e-6
+l=1.5e-6
+model=rsil
+spiceprefix=X
+b=0
+m=1
+}
 C {sg13g2_pr/rppd.sym} 240 40 0 0 {name=R2
-W=0.5e-6
-L=2.5e-6
+w=0.5e-6
+l=0.5e-6
 model=rppd
 spiceprefix=X
+b=0
 m=1
-R=7.0
-Imax=0.3e-6
 }
 C {sg13g2_pr/rhigh.sym} 420 40 0 0 {name=R3
-W=0.5e-6
-L=2.0e-6
+w=0.5e-6
+l=0.5e-6
 model=rhigh
 spiceprefix=X
-m=1
-R=1360.0
-Imax=0.3e-6
-}
-C {sg13g2_pr/rsil.sym} 90 40 0 0 {name=R1
-W=0.5e-5
-L=0.5e-5
-model=rsil
-spiceprefix=X
 b=0
 m=1
-
 }
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/mc_hv_nmos_cs_loop.sch b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/mc_hv_nmos_cs_loop.sch
index cbc4de0e..096b90d4 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/mc_hv_nmos_cs_loop.sch
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/mc_hv_nmos_cs_loop.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 }
 G {}
 K {}
@@ -28,8 +28,7 @@ lab=Vgs}
 C {devices/code_shown.sym} 260 110 0 0 {name=MODEL only_toplevel=true
 format="tcleval( @value )"
 value="
-.lib $::SG13G2_MODELS/cornerMOSlv.lib mos_tt_stat
-.lib $::SG13G2_MODELS/cornerMOShv.lib mos_tt_stat
+.lib cornerMOShv.lib mos_tt_stat
 
 "}
 C {devices/code_shown.sym} -300 -440 0 0 {name=NGSPICE only_toplevel=true 
@@ -39,7 +38,6 @@ value="
 .param temp=27
 
 .control
-pre_osdi ./psp103_nqs.osdi
 
 let mc_runs = 1000
 let run = 0
@@ -78,8 +76,8 @@ C {devices/isource.sym} 480 -150 0 0 {name=I0 value=10u}
 C {devices/gnd.sym} 480 -200 2 0 {name=l2 lab=GND}
 C {devices/lab_pin.sym} 380 -100 0 0 {name=p1 sig_type=std_logic lab=Vgs}
 C {sg13g2_pr/sg13_hv_nmos.sym} 460 -50 2 1 {name=M1
-L=1.0u
-W=2.0u
+l=1.0u
+w=2.0u
 ng=1
 m=1
 model=sg13_hv_nmos
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/mc_hv_pmos_cs_loop.sch b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/mc_hv_pmos_cs_loop.sch
index bce4ec87..eb763111 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/mc_hv_pmos_cs_loop.sch
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/mc_hv_pmos_cs_loop.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 }
 G {}
 K {}
@@ -28,8 +28,7 @@ lab=Vgs}
 C {devices/code_shown.sym} 260 110 0 0 {name=MODEL only_toplevel=true
 format="tcleval( @value )"
 value="
-.lib $::SG13G2_MODELS/cornerMOSlv.lib mos_tt_stat
-.lib $::SG13G2_MODELS/cornerMOShv.lib mos_tt_stat
+.lib cornerMOShv.lib mos_tt_stat
 "}
 C {devices/code_shown.sym} -300 -440 0 0 {name=NGSPICE only_toplevel=true 
 value="
@@ -38,8 +37,6 @@ value="
 .param temp=27
 
 .control
-pre_osdi ./psp103_nqs.osdi
-
 let mc_runs = 1000
 let run = 0
 set curplot=new
@@ -77,8 +74,8 @@ C {devices/isource.sym} 480 -150 2 0 {name=I0 value=10u}
 C {devices/gnd.sym} 480 -200 2 0 {name=l2 lab=GND}
 C {devices/lab_pin.sym} 380 -100 0 0 {name=p1 sig_type=std_logic lab=Vgs}
 C {sg13g2_pr/sg13_hv_pmos.sym} 460 -50 2 1 {name=M1
-L=1.0u
-W=2.0u
+l=1.0u
+w=2.0u
 ng=1
 m=1
 model=sg13_hv_pmos
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/mc_lv_nmos_cs_loop.sch b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/mc_lv_nmos_cs_loop.sch
index d18094d0..68c2d93a 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/mc_lv_nmos_cs_loop.sch
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/mc_lv_nmos_cs_loop.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 }
 G {}
 K {}
@@ -28,7 +28,7 @@ lab=Vgs}
 C {devices/code_shown.sym} 260 110 0 0 {name=MODEL only_toplevel=true
 format="tcleval( @value )"
 value="
-.lib $::SG13G2_MODELS/cornerMOSlv.lib mos_tt_stat
+.lib cornerMOSlv.lib mos_tt_stat
 "}
 C {devices/code_shown.sym} -300 -440 0 0 {name=NGSPICE only_toplevel=true 
 value="
@@ -37,7 +37,6 @@ value="
 .param temp=27
 
 .control
-pre_osdi ./psp103_nqs.osdi
 
 let mc_runs = 1000
 let run = 0
@@ -76,8 +75,8 @@ C {devices/isource.sym} 480 -150 0 0 {name=I0 value=10u}
 C {devices/gnd.sym} 480 -200 2 0 {name=l2 lab=GND}
 C {devices/lab_pin.sym} 380 -100 0 0 {name=p1 sig_type=std_logic lab=Vgs}
 C {sg13g2_pr/sg13_lv_nmos.sym} 460 -50 2 1 {name=M1
-L=1.0u
-W=2.0u
+l=1.0u
+w=2.0u
 ng=1
 m=1
 model=sg13_lv_nmos
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/mc_lv_pmos_cs_loop.sch b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/mc_lv_pmos_cs_loop.sch
index 7a0cfc63..6e3dee51 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/mc_lv_pmos_cs_loop.sch
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/mc_lv_pmos_cs_loop.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 }
 G {}
 K {}
@@ -28,8 +28,7 @@ lab=Vgs}
 C {devices/code_shown.sym} 260 110 0 0 {name=MODEL only_toplevel=true
 format="tcleval( @value )"
 value="
-.lib $::SG13G2_MODELS/cornerMOSlv.lib mos_tt_stat
-.lib $::SG13G2_MODELS/cornerMOShv.lib mos_tt_stat
+.lib cornerMOSlv.lib mos_tt_stat
 "}
 C {devices/code_shown.sym} -300 -440 0 0 {name=NGSPICE only_toplevel=true 
 value="
@@ -38,8 +37,6 @@ value="
 .param temp=27
 
 .control
-pre_osdi ./psp103_nqs.osdi
-
 let mc_runs = 1000
 let run = 0
 set curplot=new
@@ -77,8 +74,8 @@ C {devices/isource.sym} 480 -150 2 0 {name=I0 value=10u}
 C {devices/gnd.sym} 480 -200 2 0 {name=l2 lab=GND}
 C {devices/lab_pin.sym} 380 -100 0 0 {name=p1 sig_type=std_logic lab=Vgs}
 C {sg13g2_pr/sg13_lv_pmos.sym} 460 -50 2 1 {name=M1
-L=1.0u
-W=2.0u
+l=1.0u
+w=2.0u
 ng=1
 m=1
 model=sg13_lv_pmos
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/mc_mim_cap_ac.sch b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/mc_mim_cap_ac.sch
index 371a8066..f734c33a 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/mc_mim_cap_ac.sch
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/mc_mim_cap_ac.sch
@@ -76,4 +76,4 @@ m=1}
 C {devices/gnd.sym} 420 -270 0 0 {name=l5 lab=GND}
 C {devices/lab_pin.sym} 100 -440 1 0 {name=p1 sig_type=std_logic lab=in}
 C {devices/lab_pin.sym} 420 -430 1 0 {name=p2 sig_type=std_logic lab=out}
-C {sg13g2_pr/cap_cmim.sym} 260 -420 1 0 {name=C1 model=cap_cmim W=7.0e-6 L=7.0e-6 MF=1 spiceprefix=X}
+C {sg13g2_pr/cap_cmim.sym} 260 -420 1 0 {name=C1 model=cap_cmim w=7.0e-6 l=7.0e-6 MF=1 spiceprefix=X}
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/mc_res_op.sch b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/mc_res_op.sch
index a46e119d..72ccb551 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/mc_res_op.sch
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/mc_res_op.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 }
 G {}
 K {}
@@ -91,8 +91,8 @@ C {devices/gnd.sym} 760 100 0 0 {name=l2 lab=GND}
 C {devices/ammeter.sym} 760 -30 0 0 {name=Vppd}
 C {devices/gnd.sym} 940 100 0 0 {name=l4 lab=GND}
 C {sg13g2_pr/rhigh.sym} 940 50 0 0 {name=R3
-W=1.0e-6
-L=1.0e-6
+w=1.0e-6
+l=1.0e-6
 model=rhigh
 spiceprefix=X
 m=1
@@ -101,8 +101,8 @@ Imax=0.11e-4
 }
 C {devices/ammeter.sym} 940 -30 0 0 {name=Vrh}
 C {sg13g2_pr/rsil.sym} 610 50 0 0 {name=R1
-W=0.5e-6
-L=0.5e-5
+w=0.5e-6
+l=0.5e-5
 model=rsil
 spiceprefix=X
 m=1
@@ -110,8 +110,8 @@ R=7.0
 Imax=0.3e-6
 }
 C {sg13g2_pr/rppd.sym} 760 50 0 0 {name=R2
-W=0.5e-6
-L=0.5e-6
+w=0.5e-6
+l=0.5e-6
 model=rppd
 spiceprefix=X
 m=1
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/sp_mim_cap.sch b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/sp_mim_cap.sch
index aa7ec63b..8d9c44c5 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/sp_mim_cap.sch
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/sp_mim_cap.sch
@@ -141,4 +141,4 @@ C {devices/launcher.sym} 900 -650 0 0 {name=h5
 descr="load waves" 
 tclcommand="xschem raw_read $netlist_dir/sp_mim_cap.raw ac"
 }
-C {sg13g2_pr/cap_cmim.sym} 530 -380 1 0 {name=C1 model=cap_cmim W=7.0e-6 L=7.0e-6 MF=1 spiceprefix=X}
+C {sg13g2_pr/cap_cmim.sym} 530 -380 1 0 {name=C1 model=cap_cmim w=7.0e-6 l=7.0e-6 MF=1 spiceprefix=X}
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/sp_rfmim_cap.sch b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/sp_rfmim_cap.sch
index 559101ee..b7ef5731 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/sp_rfmim_cap.sch
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/sp_rfmim_cap.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 * Copyright 2021 Stefan Frederik Schippers
 * 
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -167,4 +167,9 @@ descr="load waves"
 tclcommand="xschem raw_read $netlist_dir/sp_rfmim_cap.raw ac"
 }
 C {devices/gnd.sym} 530 -230 0 0 {name=l2 lab=GND}
-C {sg13g2_pr/cap_rfcmim.sym} 530 -380 3 0 {name=C1 model=cap_rfcmim W=7.0e-6 L=7.0e-6 wfeed=5.0e-6 spiceprefix=X}
+C {sg13g2_pr/cap_rfcmim.sym} 530 -380 3 0 {name=C1 
+model=cap_rfcmim
+w=2.0e-6
+l=2.0e-6
+wfeed=5.0e-6
+spiceprefix=X}
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/tran_logic_nand.sch b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/tran_logic_nand.sch
index bb45bd76..4e672c67 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/tran_logic_nand.sch
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/tran_logic_nand.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 }
 G {}
 K {}
@@ -144,23 +144,22 @@ lab=out}
 C {devices/code_shown.sym} -290 190 0 0 {name=MODEL only_toplevel=true
 format="tcleval( @value )"
 value="
-.lib $::SG13G2_MODELS/cornerMOSlv.lib mos_ff
+.lib cornerMOSlv.lib mos_ff
 "}
 C {devices/code_shown.sym} -330 -530 0 0 {name=NGSPICE only_toplevel=true 
 value="
 .param temp=127
 .control
-pre_osdi ./psp103_nqs.osdi
 save all 
 tran 50p 20n
-meas tran tdelay TRIG v(b) VAL=0.9 FALL=1 TARG v(out) VAL=0.9 RISE=1
+meas tran tdelay TRIG v(b) VAl=0.9 FALl=1 TARG v(out) VAl=0.9 RISE=1
 write tran_logic_nand.raw
 .endc
 "}
 C {devices/gnd.sym} 100 130 0 0 {name=l1 lab=GND}
 C {devices/gnd.sym} -170 130 0 0 {name=l2 lab=GND}
-C {devices/vsource.sym} -170 90 0 0 {name=VinA value="dc 0 ac 0 pulse(0, 1.8, 2n, 100p, 100p, 4n, 6n ) "}
-C {devices/vsource.sym} 410 -80 0 0 {name=Vdd value=1.8}
+C {devices/vsource.sym} -170 90 0 0 {name=VinA value="dc 0 ac 0 pulse(0, 1.2, 2n, 100p, 100p, 4n, 6n ) "}
+C {devices/vsource.sym} 410 -80 0 0 {name=Vdd value=1.2}
 C {devices/gnd.sym} 410 130 0 0 {name=l3 lab=GND}
 C {devices/gnd.sym} 150 130 0 0 {name=l4 lab=GND}
 C {devices/title.sym} -130 260 0 0 {name=l5 author="Copyright 2023 IHP PDK Authors"}
@@ -169,16 +168,16 @@ descr="load waves Ctrl + left click"
 tclcommand="xschem raw_read $netlist_dir/tran_logic_nand.raw tran"
 }
 C {sg13g2_pr/sg13_lv_nmos.sym} 80 40 2 1 {name=M1
-L=0.45u
-W=1.0u
+l=0.45u
+w=1.0u
 ng=1
 m=1
 model=sg13_lv_nmos
 spiceprefix=X
 }
 C {sg13g2_pr/sg13_lv_pmos.sym} -70 -190 0 0 {name=M2
-L=0.45u
-W=1.0u
+l=0.45u
+w=1.0u
 ng=1
 m=1
 model=sg13_lv_pmos
@@ -187,16 +186,16 @@ spiceprefix=X
 C {devices/lab_pin.sym} -190 40 0 0 {name=p1 sig_type=std_logic lab=A}
 C {devices/lab_pin.sym} 240 -90 2 0 {name=p2 sig_type=std_logic lab=out}
 C {sg13g2_pr/sg13_lv_pmos.sym} 160 -190 0 0 {name=M3
-L=0.45u
-W=1.0u
+l=0.45u
+w=1.0u
 ng=1
 m=1
 model=sg13_lv_pmos
 spiceprefix=X
 }
 C {sg13g2_pr/sg13_lv_nmos.sym} 80 -40 2 1 {name=M4
-L=0.45u
-W=1.0u
+l=0.45u
+w=1.0u
 ng=1
 m=1
 model=sg13_lv_nmos
@@ -204,5 +203,5 @@ spiceprefix=X
 }
 C {devices/gnd.sym} 200 40 0 0 {name=l6 lab=GND}
 C {devices/gnd.sym} -270 50 0 0 {name=l7 lab=GND}
-C {devices/vsource.sym} -270 10 0 0 {name=VinB value="dc 0 ac 0 pulse(0, 1.8, 0, 100p, 100p, 2n, 4n ) "}
+C {devices/vsource.sym} -270 10 0 0 {name=VinB value="dc 0 ac 0 pulse(0, 1.2, 0, 100p, 100p, 2n, 4n ) "}
 C {devices/lab_pin.sym} -290 -40 0 0 {name=p3 sig_type=std_logic lab=B}
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/tran_logic_not.sch b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/tran_logic_not.sch
index 47f012d9..1bc4bc68 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/tran_logic_not.sch
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/tran_logic_not.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 }
 G {}
 K {}
@@ -68,27 +68,25 @@ N -230 -80 -230 -30 {
 lab=in}
 N -160 -50 -160 -30 {
 lab=out}
-C {devices/code_shown.sym} -290 190 0 0 {name=MODEL only_toplevel=true
+C {devices/code_shown.sym} -300 170 0 0 {name=MODEL only_toplevel=true
 format="tcleval( @value )"
 value="
-.lib $::SG13G2_MODELS/cornerMOSlv.lib mos_tt
-.lib $::SG13G2_MODELS/cornerRES.lib res_typ
+.lib cornerMOSlv.lib mos_tt
 "}
 C {devices/code_shown.sym} 160 -70 0 0 {name=NGSPICE only_toplevel=true 
 value="
 .param temp=27
 .control
-pre_osdi ./psp103_nqs.osdi
 save all 
 tran 50p 20n
-meas tran tdelay TRIG v(in) VAL=0.9 FALL=1 TARG v(out) VAL=0.9 RISE=1
+meas tran tdelay TRIG v(in) VAl=0.9 FALl=1 TARG v(out) VAl=0.9 RISE=1
 write tran_logic_not.raw
 .endc
 "}
 C {devices/gnd.sym} -160 110 0 0 {name=l1 lab=GND}
 C {devices/gnd.sym} -440 110 0 0 {name=l2 lab=GND}
-C {devices/vsource.sym} -440 60 0 0 {name=Vin value="dc 0 ac 0 pulse(0, 1.8, 0, 100p, 100p, 2n, 4n ) "}
-C {devices/vsource.sym} 100 20 0 0 {name=Vdd value=1.8}
+C {devices/vsource.sym} -440 60 0 0 {name=Vin value="dc 0 ac 0 pulse(0, 1.2, 0, 100p, 100p, 2n, 4n ) "}
+C {devices/vsource.sym} 100 20 0 0 {name=Vdd value=1.2}
 C {devices/gnd.sym} 100 110 0 0 {name=l3 lab=GND}
 C {devices/gnd.sym} -110 110 0 0 {name=l4 lab=GND}
 C {devices/title.sym} -130 260 0 0 {name=l5 author="Copyright 2023 IHP PDK Authors"}
@@ -97,16 +95,16 @@ descr="load waves Ctrl + left click"
 tclcommand="xschem raw_read $netlist_dir/tran_logic_not.raw tran"
 }
 C {sg13g2_pr/sg13_lv_nmos.sym} -180 20 2 1 {name=M1
-L=0.45u
-W=1.0u
+l=0.45u
+w=1.0u
 ng=1
 m=1
 model=sg13_lv_nmos
 spiceprefix=X
 }
 C {sg13g2_pr/sg13_lv_pmos.sym} -180 -80 0 0 {name=M2
-L=0.45u
-W=1.0u
+l=0.45u
+w=1.0u
 ng=1
 m=1
 model=sg13_lv_pmos
diff --git a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/tran_mim_cap.sch b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/tran_mim_cap.sch
index eff379d3..0ef32e27 100644
--- a/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/tran_mim_cap.sch
+++ b/ihp-sg13g2/libs.tech/xschem/sg13g2_tests/tran_mim_cap.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 * Copyright 2021 Stefan Frederik Schippers
 * 
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -101,4 +101,9 @@ C {devices/launcher.sym} 780 -450 0 0 {name=h5
 descr="load waves" 
 tclcommand="xschem raw_read $netlist_dir/test_mim_cap.raw tran"
 }
-C {sg13g2_pr/cap_cmim.sym} 40 -220 0 0 {name=C2 model=cap_cmim W=7.0e-6 L=7.0e-6 MF=1 spiceprefix=X}
+C {sg13g2_pr/cap_cmim.sym} 40 -220 0 0 {name=C2
+model=cap_cmim
+w=7.0e-6
+l=7.0e-6
+m=1
+spiceprefix=X}
diff --git a/ihp-sg13g2/libs.tech/xschem/xschemrc b/ihp-sg13g2/libs.tech/xschem/xschemrc
index b8e09394..01c734d6 100755
--- a/ihp-sg13g2/libs.tech/xschem/xschemrc
+++ b/ihp-sg13g2/libs.tech/xschem/xschemrc
@@ -28,7 +28,8 @@
 #### Flush any previous definition
 set XSCHEM_LIBRARY_PATH {}
 #### include devices/*.sym
-append XSCHEM_LIBRARY_PATH ${XSCHEM_SHAREDIR}/xschem_library
+append XSCHEM_LIBRARY_PATH :${XSCHEM_SHAREDIR}/xschem_library/devices
+append XSCHEM_LIBRARY_PATH :${XSCHEM_SHAREDIR}/xschem_library
 #### include skywater libraries. Here i use [pwd]. This works if i start xschem from here.
 append XSCHEM_LIBRARY_PATH :[file dirname [info script]]
 #### add ~/.xschem/xschem_library (USER_CONF_DIR is normally ~/.xschem)
@@ -430,3 +431,180 @@ append XSCHEM_LIBRARY_PATH :${PDK_ROOT}/${PDK}/libs.tech/xschem
 if { [info exists ::env(XSCHEM_USER_LIBRARY_PATH) ] } {
     append XSCHEM_LIBRARY_PATH :$env(XSCHEM_USER_LIBRARY_PATH)
 }
+
+############################################################### DRC checks #######################################
+# IHP SG13G2 mosfets dimension checks
+proc fet_drc {instance symbol model w l ng } {
+  set res {}
+  # strip off the "u" suffix
+  regsub {u$} $w {} w
+  regsub {u$} $l {} l
+  # puts "$instance $model $symbol w=$w l=$l nf=$nf"
+  if { [string is double $w] && [string is double $l] && [string is integer $ng]} {
+    
+  # calculate finger width 
+    set w [expr { double($w) / double($ng)}]
+    
+    switch -regexp $model {
+      {sg13_lv_nmos$} {
+        if { $w < 0.13 } {
+          append res "${instance} ($model): finger width is too small, w/ng = $w, min. w/ng > 0.13u" \n
+        }
+        if { $w > 10.0 } {
+          append res "${instance} ($model): finger width is too big, w/ng = $w, max. w/ng < 10.0u" \n
+        }
+        if { $l < 0.13 } {
+          append res "${instance} ($model): length is too small, l = $l, min l > 0.13u" \n
+        }
+      }
+      {sg13_lv_pmos$} {
+        if { $w < 0.13 } {
+          append res "${instance} ($model): finger width is too small, w/ng = $w, min. w/ng > 0.13u" \n
+        }
+        if { $w > 10.0 } {
+          append res "${instance} ($model): finger width is too big, w/ng = $w, max. w/ng < 10.0u" \n
+        }
+        if { $l < 0.13 } {
+          append res "${instance} ($model): length is too small, l = $l, min. l > 0.13u" \n
+        }
+      }
+      {sg13_hv_nmos$} {
+        if { $w < 0.45 } {
+          append res "${instance} ($model): finger width is too small, w/ng = $w, min w/ng > 0.45u" \n
+        }
+        if { $w > 10.0 } {
+          append res "${instance} ($model): finger width is too big, w/ng = $w, max. w/ng < 10.0u" \n
+        }
+        if { $l < 0.13 } {
+         append res "${instance} ($model): length is too small, l = $l, min. l > 0.13u" \n
+        }
+      }
+      {sg13_hv_pmos$} {
+        if { $w < 0.4 } {
+          append res "${instance} ($model): finger width is too small, w/ng = $w, min. w/ng > 0.4u" \n
+        }
+        if { $w > 10.0 } {
+          append res "${instance} ($model): finger width is too big, w/ng = $w, max. w/ng < 10.0u" \n
+        }
+        if { $l < 0.13 } {
+          append res "${instance} ($model): length is too small, l = $l, min. l > 0.13u" \n
+        }
+      }
+    } ;# switch
+  }
+  return $res
+}
+# IHP SG13G2 resistors dimension checks
+proc res_drc {instance symbol model w l } {
+  set res {}
+  # puts "$instance $model $symbol w=$w l=$l nf=$nf"
+  if { [string is double $w] && [string is double $l] } {
+    
+    if { $w < 0.5e-6 } {
+      append res "${instance} ($model): resistor width is too small, w = $w, min. w > 0.5u" \n
+    }
+
+    if { $l < 0.5e-6 } {
+       append res "${instance} ($model): resistor length is too small, l = $l, min. l > 0.5u" \n
+    }
+  }
+  return $res
+}
+# IHP SG13G2 MiM capacitor dimension checks
+proc mim_drc {instance symbol model w l } {
+  set res {}
+  
+  if { [string is double $w] && [string is double $l] } {
+    set area [expr { double($w) * double($l) * 1.0e+12}]
+ 
+    if { $w < 1.14e-6 } {
+      append res "${instance} ($model): MiM capacitor width is too small, w = $w, min. w > 1.14 um" \n
+    }
+    
+    if { $area < 1.3 } {
+       append res "${instance} ($model): MiM capacitor area is too small, area = $area, min. area > 1.3 um2" \n
+    }
+    
+    if { $area > 5625.0 } {
+       append res "${instance} ($model): MiM capacitor area is too big, area = $area, max. area < 5625.0 um2" \n
+    }
+  }
+  return $res
+}
+# IHP SG13G2 HBT dimension checks
+proc hbt_drc {instance symbol model Nx le } {
+  set res {}
+  # puts "$instance $model $symbol w=$w l=$l nf=$nf"
+  if { [string is integer $Nx] && [string is double $le]} {
+    
+    
+    switch -regexp $model {
+      {npn13G2$} {
+        if { $Nx < 1 } {
+          append res "${instance} ($model):  Number of emmiters Nx = $Nx must be in range 1-10" \n
+        }
+        if { $Nx > 10 } {
+          append res "${instance} ($model): Number of emitters Nx = $Nx must be in range 1-10" \n
+        }
+      }
+      {npn13G2l$} {
+        if { $Nx < 1 } {
+          append res "${instance} ($model):  Number of emmiters Nx = $Nx must be in range 1-4" \n
+        }
+        if { $Nx > 4 } {
+          append res "${instance} ($model): Number of emitters Nx = $Nx must be in range 1-4" \n
+        }
+        if { $le < 1.0e-6 } {
+          append res "${instance} ($model): Emitter length le = $le too small, min. le > 1.0 um" \n
+        }
+        if { $le > 2.5e-6 } {
+          append res "${instance} ($model): Emitter length le = $le too big, max. le < 2.5 um" \n
+        }
+      }
+      {npn13G2v$} {
+        if { $Nx < 1 } {
+          append res "${instance} ($model):  Number of emmiters Nx = $Nx must be in range 1-8" \n
+        }
+        if { $Nx > 8 } {
+          append res "${instance} ($model): Number of emitters Nx = $Nx must be in range 1-8" \n
+        }
+        if { $le < 1.0e-6 } {
+          append res "${instance} ($model): Emitter length le = $le too small, min. le > 1.0 um" \n
+        }
+        if { $le > 5.0e-6 } {
+          append res "${instance} ($model): Emitter length le = $le too big, max. le < 5.0 um" \n
+        }
+    } ;# switch
+  }
+  }
+  return $res
+}
+# IHP SG13G2 HBT diodes checks
+proc diode_drc {instance symbol model w l } {
+  set res {}
+  regsub {u$} $w {} w
+  regsub {u$} $l {} l
+  # puts "$instance $model $symbol w=$w l=$l nf=$nf"
+  if { [string is double $w] && [string is double $l]} {
+    
+    switch -regexp $model {
+      {dantenna} {
+        if { $w < 0.78 } {
+          append res "${instance} ($model): Diode width w = $w too small, min w > 0.78 um" \n
+        }
+        if { $l < 0.78 } {
+          append res "${instance} ($model): Diode length l = $l too small, min l > 0.78 um" \n
+        }
+      }
+      {dpantenna} {
+        if { $w < 0.78 } {
+          append res "${instance} ($model): Diode width w = $w too small, min w > 0.78 um" \n
+        }
+        if { $l < 0.78 } {
+          append res "${instance} ($model): Diode length l = $l too small, min l > 0.78 um" \n
+        }
+      }
+    } ;# switch
+  }
+  return $res
+}
diff --git a/ihp-sg13g2/libs.tech/xyce/adms/Changelog b/ihp-sg13g2/libs.tech/xyce/adms/Changelog
new file mode 100644
index 00000000..ac683a43
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/adms/Changelog
@@ -0,0 +1,9 @@
+Use IHP specific code for AD, AS, PD, PS calculation.
+
+Use DTA and TRISE as instance parameter and model parameter. Instance parameter will overwrite model parameter.
+For ADMS/Xyce temperature initialization code must be shifted and pseudo event blocks needed.
+
+PSP103_module.include, line 2364: Unexpected bitwise operator '&'
+Changed to && operator
+
+Code version 103.6.0 downloaded from http://www.cea.fr/cea-tech/leti/pspsupport.
diff --git a/ihp-sg13g2/libs.tech/xyce/adms/Common103_macrodefs.include b/ihp-sg13g2/libs.tech/xyce/adms/Common103_macrodefs.include
new file mode 100644
index 00000000..4b3fc871
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/adms/Common103_macrodefs.include
@@ -0,0 +1,210 @@
+//======================================================================================
+//======================================================================================
+// Filename: Common103_macrodefs.include
+//======================================================================================
+//======================================================================================
+//
+//  (c) Copyright notice
+//
+//  Copyright 2004-2017 NXP Semiconductors, 2015-2017 Commissariat a l’energie atomique
+//  et aux energies alternatives (CEA), 2012-2015 Delft University of Technology and
+//  2004-2011 Arizona State University Licensed under the Educational Community License,
+//  Version 2.0 (the "License"); you may not use this file except in compliance with the
+//  License. You may obtain a copy of the License at
+//  http://opensource.org/licenses/ECL-2.0
+//  Unless required by applicable law or agreed to in writing, software distributed under
+//  the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF
+//  ANY KIND, either express or implied. See the License for the specific language
+//  governing permissions and limitations under the License.
+//
+//
+//  Version: 103.6.0 (PSP), 200.5.0 (JUNCAP), December 2017
+//
+//======================================================================================
+//======================================================================================
+//
+// Further information can be found in the file releasenotesPSP103.txt
+//
+
+`ifdef insideADMS
+    `define INITIAL_MODEL @(initial_model)
+    `define INITIAL_INSTANCE @(initial_instance)
+`else
+    `define INITIAL_MODEL
+    `define INITIAL_INSTANCE
+`endif
+
+//////////////////////////////////////////////////////////////
+//
+//  General macros and constants for compact va-models
+//
+//////////////////////////////////////////////////////////////
+
+// Clipping functions
+`define CLIP_LOW(val,min)      ((val)>(min)?(val):(min))
+`define CLIP_HIGH(val,max)     ((val)<(max)?(val):(max))
+`define CLIP_BOTH(val,min,max) ((val)>(min)?((val)<(max)?(val):(max)):(min))
+
+// Min/Max functions
+`define MAX(x,y)              ((x)>(y)?(x):(y))
+`define MIN(x,y)              ((x)<(y)?(x):(y))
+
+// Mathematical constants
+`define PI                    3.1415926535897931
+`define SQRTPI                1.77245385090551603
+
+// Physical constants
+`define KELVINCONVERSION      273.15
+`define KBOL                  1.3806505E-23
+`define QELE                  1.6021918E-19
+`define HBAR                  1.05457168E-34
+`define MELE                  9.1093826E-31
+`define EPSO                  8.8541878176E-12
+`define EPSRSI                11.8
+
+// Other constants
+`define oneThird              3.3333333333333333e-01
+`define twoThirds             6.6666666666666667e-01
+
+// Constants needed in safe exponential function (called "expl")
+`define se                    4.6051701859880916e+02
+`define se05                  2.3025850929940458e+02
+`define ke                    1.0e-200
+`define ke05                  1.0e-100
+`define keinv                 1.0e200
+`define ke05inv               1.0e100
+
+//  P3       3rd order polynomial expansion of exp()
+`define P3(u) (1.0 + (u) * (1.0 + 0.5 * ((u) * (1.0 + (u) * `oneThird))))
+
+//  expl     exp() with 3rd order polynomial extrapolation for very low values (exp_low),
+//           very high values (exp_high), or both (expl)
+`define expl(x, res) \
+    if (abs(x) < `se05) begin \
+        res       = exp(x); \
+    end else begin \
+        if ((x) < 0.0) begin \
+            res       = `ke05 / `P3(-`se05 - (x)); \
+        end else begin \
+            res       =  `ke05inv * `P3((x) - `se05); \
+        end \
+    end
+
+`define expl_low(x, res) \
+    if ((x) > -`se05) begin \
+        res       =  exp(x); \
+    end else begin \
+        res       = `ke05 / `P3(-`se05 - (x)); \
+    end
+
+`define expl_high(x, res) \
+    if ((x) < `se05) begin \
+        res       = exp(x); \
+    end else begin \
+        res       =  `ke05inv * `P3((x) - `se05); \
+    end
+
+//  Exchange function
+`define swap(a, b) \
+    temp = a; \
+    a    = b; \
+    b    = temp;
+
+//  Parameter definition macros: "des" description argument is intended to
+//  be a short description, the "inf" information argument is intended to be
+//  a detailed description (e.g. for display as part of on-line help).
+//
+//  MPR      model    parameter real
+//  MPI      model    parameter integer
+//  IPR      instance parameter real
+//  IPI      instance parameter integer
+//  OPP      operating point parameter, includes units and description for printing
+//  OPM      operating point parameter, scales with $mfactor
+//  OPD      operating point parameter, scales with 1/$mfactor
+//
+//  Instance parameters have the attribute *type="instance"* and note that
+//  compilers treat these as both instance and model parameters, with a
+//  specified instance value taking precedence over a specified model card value.
+//
+//  There are some issues with passing range directives with some compilers,
+//  so for each parameter declaration there are multiple versions:
+//  cc       closed lower bound, closed upper bound
+//  co       closed lower bound, open   upper bound
+//  cz       closed lower bound of zero (no upper bound)
+//  oc       open   lower bound, closed upper bound
+//  oo       open   lower bound, open   upper bound
+//  oz       open   lower bound of zero (no upper bound)
+//  nb       no bounds
+//  sw       switch (integer only, values  0=false  and >0=true)
+//  ty       switch (integer only, values -1=n-type and +1=p-type)
+//
+
+`define ALIAS(alias,paramName) aliasparam alias = paramName;
+`define OPP(nam,uni,des)               (*units=uni,                             desc=des*)           real    nam;
+`define OPM(nam,uni,des)               (*units=uni, multiplicity="multiply",    desc=des*)           real    nam;
+`define OPD(nam,uni,des)               (*units=uni, multiplicity="divide",      desc=des*)           real    nam;
+`define MPRcc(nam,def,uni,lwr,upr,des) (*units=uni                            , desc=des*) parameter real    nam=def from[lwr:upr];
+`define MPRco(nam,def,uni,lwr,upr,des) (*units=uni                            , desc=des*) parameter real    nam=def from[lwr:upr);
+`define MPRcz(nam,def,uni,        des) (*units=uni                            , desc=des*) parameter real    nam=def from[  0:inf);
+`define MPRoc(nam,def,uni,lwr,upr,des) (*units=uni                            , desc=des*) parameter real    nam=def from(lwr:upr];
+`define MPRoo(nam,def,uni,lwr,upr,des) (*units=uni                            , desc=des*) parameter real    nam=def from(lwr:upr);
+`define MPRoz(nam,def,uni,        des) (*units=uni                            , desc=des*) parameter real    nam=def from(  0:inf);
+`define MPRnb(nam,def,uni,        des) (*units=uni                            , desc=des*) parameter real    nam=def;
+`define MPIcc(nam,def,uni,lwr,upr,des) (*units=uni                            , desc=des*) parameter integer nam=def from[lwr:upr];
+`define MPIco(nam,def,uni,lwr,upr,des) (*units=uni                            , desc=des*) parameter integer nam=def from[lwr:upr);
+`define MPIcz(nam,def,uni,        des) (*units=uni                            , desc=des*) parameter integer nam=def from[  0:inf);
+`define MPIoc(nam,def,uni,lwr,upr,des) (*units=uni                            , desc=des*) parameter integer nam=def from(lwr:upr];
+`define MPIoo(nam,def,uni,lwr,upr,des) (*units=uni                            , desc=des*) parameter integer nam=def from(lwr:upr);
+`define MPIoz(nam,def,uni,        des) (*units=uni                            , desc=des*) parameter integer nam=def from(  0:inf);
+`define MPInb(nam,def,uni,        des) (*units=uni                            , desc=des*) parameter integer nam=def;
+`define MPIsw(nam,def,uni,        des) (*units=uni                            , desc=des*) parameter integer nam=def from[  0:inf);
+`define MPIty(nam,def,uni,        des) (*units=uni                            , desc=des*) parameter integer nam=def from[ -1:  1] exclude 0;
+`define IPRcc(nam,def,uni,lwr,upr,des) (*units=uni, type="instance",            desc=des*) parameter real    nam=def from[lwr:upr];
+`define IPRco(nam,def,uni,lwr,upr,des) (*units=uni, type="instance",            desc=des*) parameter real    nam=def from[lwr:upr);
+`define IPRcz(nam,def,uni,        des) (*units=uni, type="instance",            desc=des*) parameter real    nam=def from[  0:inf);
+`define IPRoc(nam,def,uni,lwr,upr,des) (*units=uni, type="instance",            desc=des*) parameter real    nam=def from(lwr:upr];
+`define IPRoo(nam,def,uni,lwr,upr,des) (*units=uni, type="instance",            desc=des*) parameter real    nam=def from(lwr:upr);
+`define IPRoz(nam,def,uni,        des) (*units=uni, type="instance",            desc=des*) parameter real    nam=def from(  0:inf);
+`define IPRnb(nam,def,uni,        des) (*units=uni, type="instance",            desc=des*) parameter real    nam=def;
+`define IPIcc(nam,def,uni,lwr,upr,des) (*units=uni, type="instance",            desc=des*) parameter integer nam=def from[lwr:upr];
+`define IPIco(nam,def,uni,lwr,upr,des) (*units=uni, type="instance",            desc=des*) parameter integer nam=def from[lwr:upr);
+`define IPIcz(nam,def,uni,        des) (*units=uni, type="instance",            desc=des*) parameter integer nam=def from[  0:inf);
+`define IPIoc(nam,def,uni,lwr,upr,des) (*units=uni, type="instance",            desc=des*) parameter integer nam=def from(lwr:upr];
+`define IPIoo(nam,def,uni,lwr,upr,des) (*units=uni, type="instance",            desc=des*) parameter integer nam=def from(lwr:upr);
+`define IPIoz(nam,def,uni,        des) (*units=uni, type="instance",            desc=des*) parameter integer nam=def from(  0:inf);
+`define IPInb(nam,def,uni,        des) (*units=uni, type="instance",            desc=des*) parameter integer nam=def;
+`define IPIsw(nam,def,uni,        des) (*units=uni, type="instance",            desc=des*) parameter integer nam=def from[  0:inf);
+
+`ifdef __XYCE__
+
+    `define MPRnb_BOTH(nam,def,uni, des) (*units=uni, desc=des, type="instance", xyceAlsoModel="yes" *) parameter real nam=def;
+
+    //
+    // These macro represent the subroutine to process the geometry dependent
+    // parasitics for PSP103, which calculates PS, PD, AS and AD
+    //
+    `define PSP103geoUpdate(AS, AD, PS, PD, NF, AS_i, AD_i, PS_i, PD_i) \
+    z1=0.34e-6; \
+    z2=0.38e-6; \
+    wmin=0.15e-6; \
+    NF_r=NF; \
+    if (AS <= 1e-50) begin \
+        if (NF % 2 != 0) begin \
+            AS_i = max(W/NF_r, wmin) * (z1 + ((NF_r-1)/2.0) * z2) / NF_r; \
+            AD_i = max(W/NF_r, wmin) * (z1 + ((NF_r-1)/2.0) * z2) / NF_r; \
+            PS_i = 2 * (max(W/NF_r, wmin) * ((NF_r-1)/2.0 + 1) + z1 + ((NF_r-1)/2.0) * z2) / NF_r; \
+            PD_i = 2 * (max(W/NF_r, wmin) * ((NF_r-1)/2.0 + 1) + z1 + ((NF_r-1)/2.0) * z2) / NF_r; \
+        end else begin \
+            AS_i = max(W/NF_r, wmin) * (2*z1 + max(0.0, (NF_r-2.0)/2.0) * z2) / NF_r; \
+            AD_i = max(W/NF_r, wmin) * z2 / 2.0; \
+            PS_i = 2 * (max(W/NF_r, wmin) * (2 + max(NF_r-2.0,0.0)/2.0) + 2*z1 + max(NF_r-2.0,0.0)/2.0 * z2) / NF_r; \
+            PD_i = max(W/NF_r, wmin) + z2; \
+        end \
+    end else begin \
+        AS_i = AS/NF_r; \
+        AD_i = AD/NF_r; \
+        PS_i = PS/NF_r; \
+        PD_i = PD/NF_r; \
+    end
+
+`endif
diff --git a/ihp-sg13g2/libs.tech/xyce/adms/JUNCAP200_InitModel.include b/ihp-sg13g2/libs.tech/xyce/adms/JUNCAP200_InitModel.include
new file mode 100644
index 00000000..0385cbfd
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/adms/JUNCAP200_InitModel.include
@@ -0,0 +1,406 @@
+//======================================================================================
+//======================================================================================
+// Filename: JUNCAP200_InitModel.include
+//======================================================================================
+//======================================================================================
+//
+//  (c) Copyright notice
+//
+//  Copyright 2004-2017 NXP Semiconductors, 2015-2017 Commissariat a l’energie atomique
+//  et aux energies alternatives (CEA) and 2012-2015 Delft University of Technology
+//  Licensed under the Educational Community License, Version 2.0 (the "License"); you
+//  may not use this file except in compliance with the License. You may obtain a copy
+//  of the License at
+//  http://opensource.org/licenses/ECL-2.0
+//  Unless required by applicable law or agreed to in writing, software distributed under
+//  the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF
+//  ANY KIND, either express or implied. See the License for the specific language
+//  governing permissions and limitations under the License.
+//
+//
+//  Version: 200.5.0, August 2016
+//
+//======================================================================================
+//======================================================================================
+//
+// Further information can be found in the file releasenotesPSP103.txt
+//
+
+                //  --------------------------------------------------------------------------------------------------------------
+                //  Calculation of internal parameters which are independent on instance parameters
+                //  --------------------------------------------------------------------------------------------------------------
+
+                TRJ_i        = `CLIP_LOW( TRJ        ,`TRJ_cliplow);
+                IMAX_i       = `CLIP_LOW( IMAX       ,`IMAX_cliplow);
+                FREV_i       = `CLIP_BOTH(FREV       ,`FREV_cliplow,`FREV_cliphigh);
+
+                CJORBOT_i    = `CLIP_LOW( CJORBOT    ,`CJORBOT_cliplow);
+                CJORSTI_i    = `CLIP_LOW( CJORSTI    ,`CJORSTI_cliplow);
+                CJORGAT_i    = `CLIP_LOW( CJORGAT    ,`CJORGAT_cliplow);
+                VBIRBOT_i    = `CLIP_LOW( VBIRBOT    ,`VBIR_cliplow);
+                VBIRSTI_i    = `CLIP_LOW( VBIRSTI    ,`VBIR_cliplow);
+                VBIRGAT_i    = `CLIP_LOW( VBIRGAT    ,`VBIR_cliplow);
+                PBOT_i       = `CLIP_BOTH(PBOT       ,`P_cliplow,`P_cliphigh);
+                PSTI_i       = `CLIP_BOTH(PSTI       ,`P_cliplow,`P_cliphigh);
+                PGAT_i       = `CLIP_BOTH(PGAT       ,`P_cliplow,`P_cliphigh);
+                PHIGBOT_i    =  PHIGBOT;
+                PHIGSTI_i    =  PHIGSTI;
+                PHIGGAT_i    =  PHIGGAT;
+                IDSATRBOT_i  = `CLIP_LOW( IDSATRBOT  ,`IDSATR_cliplow);
+                IDSATRSTI_i  = `CLIP_LOW( IDSATRSTI  ,`IDSATR_cliplow);
+                IDSATRGAT_i  = `CLIP_LOW( IDSATRGAT  ,`IDSATR_cliplow);
+                CSRHBOT_i    = `CLIP_LOW( CSRHBOT    ,`CSRH_cliplow);
+                CSRHSTI_i    = `CLIP_LOW( CSRHSTI    ,`CSRH_cliplow);
+                CSRHGAT_i    = `CLIP_LOW( CSRHGAT    ,`CSRH_cliplow);
+                XJUNSTI_i    = `CLIP_LOW( XJUNSTI    ,`XJUN_cliplow);
+                XJUNGAT_i    = `CLIP_LOW( XJUNGAT    ,`XJUN_cliplow);
+                CTATBOT_i    = `CLIP_LOW( CTATBOT    ,`CTAT_cliplow);
+                CTATSTI_i    = `CLIP_LOW( CTATSTI    ,`CTAT_cliplow);
+                CTATGAT_i    = `CLIP_LOW( CTATGAT    ,`CTAT_cliplow);
+                MEFFTATBOT_i = `CLIP_LOW( MEFFTATBOT ,`MEFFTAT_cliplow);
+                MEFFTATSTI_i = `CLIP_LOW( MEFFTATSTI ,`MEFFTAT_cliplow);
+                MEFFTATGAT_i = `CLIP_LOW( MEFFTATGAT ,`MEFFTAT_cliplow);
+                CBBTBOT_i    = `CLIP_LOW( CBBTBOT    ,`CBBT_cliplow);
+                CBBTSTI_i    = `CLIP_LOW( CBBTSTI    ,`CBBT_cliplow);
+                CBBTGAT_i    = `CLIP_LOW( CBBTGAT    ,`CBBT_cliplow);
+                FBBTRBOT_i   =  FBBTRBOT;
+                FBBTRSTI_i   =  FBBTRSTI;
+                FBBTRGAT_i   =  FBBTRGAT;
+                STFBBTBOT_i  =  STFBBTBOT;
+                STFBBTSTI_i  =  STFBBTSTI;
+                STFBBTGAT_i  =  STFBBTGAT;
+                VBRBOT_i     = `CLIP_LOW( VBRBOT     ,`VBR_cliplow);
+                VBRSTI_i     = `CLIP_LOW( VBRSTI     ,`VBR_cliplow);
+                VBRGAT_i     = `CLIP_LOW( VBRGAT     ,`VBR_cliplow);
+                PBRBOT_i     = `CLIP_LOW( PBRBOT     ,`PBR_cliplow);
+                PBRSTI_i     = `CLIP_LOW( PBRSTI     ,`PBR_cliplow);
+                PBRGAT_i     = `CLIP_LOW( PBRGAT     ,`PBR_cliplow);
+
+                SWJUNEXP_i   =  0.0;
+                if (SWJUNEXP > 0.5) begin
+                        SWJUNEXP_i   =  1.0;
+                end else begin
+                        SWJUNEXP_i   =  0.0;
+                end
+
+                VJUNREF_i    = `CLIP_LOW( VJUNREF   ,`VJUNREF_cliplow);
+                FJUNQ_i      = `CLIP_LOW( FJUNQ     ,`FJUNQ_cliplow);
+
+                `ifdef JUNCAP_StandAlone
+                // do nothing
+                `else // JUNCAP_StandAlone
+                if (SWJUNASYM == 0.0) begin
+                CJORBOTD_i   = CJORBOT_i;
+                CJORSTID_i   = CJORSTI_i;
+                CJORGATD_i   = CJORGAT_i;
+                VBIRBOTD_i   = VBIRBOT_i;
+                VBIRSTID_i   = VBIRSTI_i;
+                VBIRGATD_i   = VBIRGAT_i;
+                PBOTD_i      = PBOT_i;
+                PSTID_i      = PSTI_i;
+                PGATD_i      = PGAT_i;
+                PHIGBOTD_i   = PHIGBOT_i;
+                PHIGSTID_i   = PHIGSTI_i;
+                PHIGGATD_i   = PHIGGAT_i;
+                IDSATRBOTD_i = IDSATRBOT_i;
+                IDSATRSTID_i = IDSATRSTI_i;
+                IDSATRGATD_i = IDSATRGAT_i;
+                CSRHBOTD_i   = CSRHBOT_i;
+                CSRHSTID_i   = CSRHSTI_i;
+                CSRHGATD_i   = CSRHGAT_i;
+                XJUNSTID_i   = XJUNSTI_i;
+                XJUNGATD_i   = XJUNGAT_i;
+                CTATBOTD_i   = CTATBOT_i;
+                CTATSTID_i   = CTATSTI_i;
+                CTATGATD_i   = CTATGAT_i;
+                MEFFTATBOTD_i = MEFFTATBOT_i;
+                MEFFTATSTID_i = MEFFTATSTI_i;
+                MEFFTATGATD_i = MEFFTATGAT_i;
+                CBBTBOTD_i   = CBBTBOT_i;
+                CBBTSTID_i   = CBBTSTI_i;
+                CBBTGATD_i   = CBBTGAT_i;
+                FBBTRBOTD_i  = FBBTRBOT_i;
+                FBBTRSTID_i  = FBBTRSTI_i;
+                FBBTRGATD_i  = FBBTRGAT_i;
+                STFBBTBOTD_i = STFBBTBOT_i;
+                STFBBTSTID_i = STFBBTSTI_i;
+                STFBBTGATD_i = STFBBTGAT_i;
+                VBRBOTD_i    = VBRBOT_i;
+                VBRSTID_i    = VBRSTI_i;
+                VBRGATD_i    = VBRGAT_i;
+                PBRBOTD_i    = PBRBOT_i;
+                PBRSTID_i    = PBRSTI_i;
+                PBRGATD_i    = PBRGAT_i;
+                VJUNREFD_i   = VJUNREF_i;
+                FJUNQD_i     = FJUNQ_i;
+                end else begin
+                CJORBOTD_i   = `CLIP_LOW( CJORBOTD   ,`CJORBOT_cliplow);
+                CJORSTID_i   = `CLIP_LOW( CJORSTID   ,`CJORSTI_cliplow);
+                CJORGATD_i   = `CLIP_LOW( CJORGATD   ,`CJORGAT_cliplow);
+                VBIRBOTD_i   = `CLIP_LOW( VBIRBOTD   ,`VBIR_cliplow);
+                VBIRSTID_i   = `CLIP_LOW( VBIRSTID   ,`VBIR_cliplow);
+                VBIRGATD_i   = `CLIP_LOW( VBIRGATD   ,`VBIR_cliplow);
+                PBOTD_i      = `CLIP_BOTH(PBOTD      ,`P_cliplow,`P_cliphigh);
+                PSTID_i      = `CLIP_BOTH(PSTID      ,`P_cliplow,`P_cliphigh);
+                PGATD_i      = `CLIP_BOTH(PGATD      ,`P_cliplow,`P_cliphigh);
+                PHIGBOTD_i   =  PHIGBOTD;
+                PHIGSTID_i   =  PHIGSTID;
+                PHIGGATD_i   =  PHIGGATD;
+                IDSATRBOTD_i = `CLIP_LOW( IDSATRBOTD ,`IDSATR_cliplow);
+                IDSATRSTID_i = `CLIP_LOW( IDSATRSTID ,`IDSATR_cliplow);
+                IDSATRGATD_i = `CLIP_LOW( IDSATRGATD ,`IDSATR_cliplow);
+                CSRHBOTD_i   = `CLIP_LOW( CSRHBOTD   ,`CSRH_cliplow);
+                CSRHSTID_i   = `CLIP_LOW( CSRHSTID   ,`CSRH_cliplow);
+                CSRHGATD_i   = `CLIP_LOW( CSRHGATD   ,`CSRH_cliplow);
+                XJUNSTID_i   = `CLIP_LOW( XJUNSTID   ,`XJUN_cliplow);
+                XJUNGATD_i   = `CLIP_LOW( XJUNGATD   ,`XJUN_cliplow);
+                CTATBOTD_i   = `CLIP_LOW( CTATBOTD   ,`CTAT_cliplow);
+                CTATSTID_i   = `CLIP_LOW( CTATSTID   ,`CTAT_cliplow);
+                CTATGATD_i   = `CLIP_LOW( CTATGATD   ,`CTAT_cliplow);
+                MEFFTATBOTD_i = `CLIP_LOW( MEFFTATBOTD,`MEFFTAT_cliplow);
+                MEFFTATSTID_i = `CLIP_LOW( MEFFTATSTID,`MEFFTAT_cliplow);
+                MEFFTATGATD_i = `CLIP_LOW( MEFFTATGATD,`MEFFTAT_cliplow);
+                CBBTBOTD_i   = `CLIP_LOW( CBBTBOTD   ,`CBBT_cliplow);
+                CBBTSTID_i   = `CLIP_LOW( CBBTSTID   ,`CBBT_cliplow);
+                CBBTGATD_i   = `CLIP_LOW( CBBTGATD   ,`CBBT_cliplow);
+                FBBTRBOTD_i  =  FBBTRBOTD;
+                FBBTRSTID_i  =  FBBTRSTID;
+                FBBTRGATD_i  =  FBBTRGATD;
+                STFBBTBOTD_i =  STFBBTBOTD;
+                STFBBTSTID_i =  STFBBTSTID;
+                STFBBTGATD_i =  STFBBTGATD;
+                VBRBOTD_i    = `CLIP_LOW( VBRBOTD    ,`VBR_cliplow);
+                VBRSTID_i    = `CLIP_LOW( VBRSTID    ,`VBR_cliplow);
+                VBRGATD_i    = `CLIP_LOW( VBRGATD    ,`VBR_cliplow);
+                PBRBOTD_i    = `CLIP_LOW( PBRBOTD    ,`PBR_cliplow);
+                PBRSTID_i    = `CLIP_LOW( PBRSTID    ,`PBR_cliplow);
+                PBRGATD_i    = `CLIP_LOW( PBRGATD    ,`PBR_cliplow);
+                VJUNREFD_i   = `CLIP_LOW( VJUNREFD   ,`VJUNREF_cliplow);
+                FJUNQD_i     = `CLIP_LOW( FJUNQD     ,`FJUNQ_cliplow);
+                end
+                `endif // JUNCAP_StandAlone
+
+                tkr          = `KELVINCONVERSION + TRJ_i;
+                tkd          =  max($temperature + DTA, `KELVINCONVERSION + `MINTEMP);
+                auxt         =  tkd / tkr;
+                KBOL_over_QELE = `KBOL / `QELE;
+                phitr        =  KBOL_over_QELE * tkr;
+                phitrinv     =  1.0 / phitr;
+                phitd        =  KBOL_over_QELE * tkd;
+                phitdinv     =  1.0 / phitd;
+
+                // bandgap voltages at reference temperature
+                deltaphigr   = -(7.02e-4 * tkr * tkr) / (1108.0 + tkr);
+                phigrbot     =  PHIGBOT_i + deltaphigr;
+                phigrsti     =  PHIGSTI_i + deltaphigr;
+                phigrgat     =  PHIGGAT_i + deltaphigr;
+
+                // bandgap voltages at device temperature
+                deltaphigd   = -(7.02e-4 * tkd * tkd) / (1108.0 + tkd);
+                phigdbot     =  PHIGBOT_i + deltaphigd;
+                phigdsti     =  PHIGSTI_i + deltaphigd;
+                phigdgat     =  PHIGGAT_i + deltaphigd;
+
+                 // factors ftd for ideal-current model
+                 ftdbot      =  (pow(auxt, 1.5)) * exp(0.5 * ((phigrbot * phitrinv) - (phigdbot * phitdinv)));
+                 ftdsti      =  (pow(auxt, 1.5)) * exp(0.5 * ((phigrsti * phitrinv) - (phigdsti * phitdinv)));
+                 ftdgat      =  (pow(auxt, 1.5)) * exp(0.5 * ((phigrgat * phitrinv) - (phigdgat * phitdinv)));
+
+                // temperature-scaled saturation current for ideal-current model
+                idsatbot     =  IDSATRBOT_i * ftdbot * ftdbot;
+                idsatsti     =  IDSATRSTI_i * ftdsti * ftdsti;
+                idsatgat     =  IDSATRGAT_i * ftdgat * ftdgat;
+
+                 // built-in voltages before limiting
+                 ubibot      =  VBIRBOT_i * auxt - 2.0 * phitd * ln(ftdbot);
+                 ubisti      =  VBIRSTI_i * auxt - 2.0 * phitd * ln(ftdsti);
+                 ubigat      =  VBIRGAT_i * auxt - 2.0 * phitd * ln(ftdgat);
+
+                // built-in voltages limited to phitd
+                vbibot       =  ubibot + phitd * ln(1 + exp((`vbilow - ubibot) * phitdinv));
+                vbisti       =  ubisti + phitd * ln(1 + exp((`vbilow - ubisti) * phitdinv));
+                vbigat       =  ubigat + phitd * ln(1 + exp((`vbilow - ubigat) * phitdinv));
+
+                // inverse values of built-in voltages
+                vbiinvbot    =  1.0 / vbibot;
+                vbiinvsti    =  1.0 / vbisti;
+                vbiinvgat    =  1.0 / vbigat;
+
+                // one minus the grading coefficient
+                one_minus_PBOT =  1.0 - PBOT_i;
+                one_minus_PSTI =  1.0 - PSTI_i;
+                one_minus_PGAT =  1.0 - PGAT_i;
+
+                // one over "one minus the grading coefficient"
+                one_over_one_minus_PBOT = 1.0 / one_minus_PBOT;
+                one_over_one_minus_PSTI = 1.0 / one_minus_PSTI;
+                one_over_one_minus_PGAT = 1.0 / one_minus_PGAT;
+
+         // temperature-scaled zero-bias capacitance
+                cjobot       =  CJORBOT_i * pow((VBIRBOT_i * vbiinvbot), PBOT_i);
+                cjosti       =  CJORSTI_i * pow((VBIRSTI_i * vbiinvsti), PSTI_i);
+                cjogat       =  CJORGAT_i * pow((VBIRGAT_i * vbiinvgat), PGAT_i);
+
+                // prefactor in physical part of charge model
+                qprefbot     =  cjobot * vbibot * one_over_one_minus_PBOT;
+                qprefsti     =  cjosti * vbisti * one_over_one_minus_PSTI;
+                qprefgat     =  cjogat * vbigat * one_over_one_minus_PGAT;
+
+                // prefactor in mathematical extension of charge model
+                qpref2bot    = `a * cjobot;
+                qpref2sti    = `a * cjosti;
+                qpref2gat    = `a * cjogat;
+
+                // zero-bias depletion widths at reference temperature, needed in SRH and TAT model
+                wdepnulrbot  =  EPSSI / CJORBOT_i;
+                wdepnulrsti  =  XJUNSTI_i * EPSSI / CJORSTI_i;
+                wdepnulrgat  =  XJUNGAT_i * EPSSI / CJORGAT_i;
+
+                // inverse values of "wdepnulr", used in BBT model
+                wdepnulrinvbot = 1.0 / wdepnulrbot;
+                wdepnulrinvsti = 1.0 / wdepnulrsti;
+                wdepnulrinvgat = 1.0 / wdepnulrgat;
+
+                // inverse values of built-in voltages at reference temperature, needed in SRH and BBT model
+                VBIRBOTinv   =  1.0 / VBIRBOT_i;
+                VBIRSTIinv   =  1.0 / VBIRSTI_i;
+                VBIRGATinv   =  1.0 / VBIRGAT_i;
+
+                // some constants needed in erfc-approximation, needed in TAT model
+                perfc        =  (`SQRTPI * `aerfc);
+                berfc        =  ((-5.0 * (`aerfc) + 6.0 - pow((perfc), -2.0)) / 3.0);
+                cerfc        =  (1.0 - (`aerfc) - (berfc));
+
+                // half the bandgap energy, limited to values > phitd, needed in TAT model
+                deltaEbot    =  max(0.5 * phigdbot, phitd);
+                deltaEsti    =  max(0.5 * phigdsti, phitd);
+                 deltaEgat   =  max(0.5 * phigdgat, phitd);
+
+                // values of atat, needed in TAT model
+                atatbot      =  deltaEbot * phitdinv;
+                atatsti      =  deltaEsti * phitdinv;
+                atatgat      =  deltaEgat * phitdinv;
+
+                // values of btatpart, needed in TAT model
+                btatpartbot  =  sqrt(32.0 * MEFFTATBOT_i * `MELE * `QELE * (deltaEbot * deltaEbot * deltaEbot)) / (3.0 * `HBAR);
+                btatpartsti  =  sqrt(32.0 * MEFFTATSTI_i * `MELE * `QELE * (deltaEsti * deltaEsti * deltaEsti)) / (3.0 * `HBAR);
+                btatpartgat  =  sqrt(32.0 * MEFFTATGAT_i * `MELE * `QELE * (deltaEgat * deltaEgat * deltaEgat)) / (3.0 * `HBAR);
+
+                // temperature-scaled values of FBBT, needed in BBT model
+                fbbtbot      =  FBBTRBOT_i * (1.0 + STFBBTBOT_i * (tkd - tkr));
+                fbbtsti      =  FBBTRSTI_i * (1.0 + STFBBTSTI_i * (tkd - tkr));
+                fbbtgat      =  FBBTRGAT_i * (1.0 + STFBBTGAT_i * (tkd - tkr));
+                fbbtbot      = `CLIP_LOW(fbbtbot, 0.0);
+                fbbtsti      = `CLIP_LOW(fbbtsti, 0.0);
+                fbbtgat      = `CLIP_LOW(fbbtgat, 0.0);
+
+                // values of fstop, needed in avalanche/breakdown model
+                alphaav      =  1.0 - 1.0 / FREV_i;
+                fstopbot     =  1.0 / (1.0 - pow(alphaav, PBRBOT_i));
+                fstopsti     =  1.0 / (1.0 - pow(alphaav, PBRSTI_i));
+                fstopgat     =  1.0 / (1.0 - pow(alphaav, PBRGAT_i));
+
+                // inverse values of breakdown voltages, needed in avalanche/breakdown model
+                VBRinvbot    =  1.0 / VBRBOT_i;
+                VBRinvsti    =  1.0 / VBRSTI_i;
+                VBRinvgat    =  1.0 / VBRGAT_i;
+
+                // slopes for linear extrapolation close to and beyond breakdown, needed in avalanche/breakdown model
+                slopebot     = -(fstopbot * fstopbot * pow(alphaav, (PBRBOT_i - 1.0))) * PBRBOT_i * VBRinvbot;
+                slopesti     = -(fstopsti * fstopsti * pow(alphaav, (PBRSTI_i - 1.0))) * PBRSTI_i * VBRinvsti;
+                slopegat     = -(fstopgat * fstopgat * pow(alphaav, (PBRGAT_i - 1.0))) * PBRGAT_i * VBRinvgat;
+
+                `ifdef JUNCAP_StandAlone
+                // do nothing
+                `else // JUNCAP_StandAlone
+                phigrbot_d   =  PHIGBOTD_i + deltaphigr;
+                phigrsti_d   =  PHIGSTID_i + deltaphigr;
+                phigrgat_d   =  PHIGGATD_i + deltaphigr;
+
+                phigdbot_d   =  PHIGBOTD_i + deltaphigd;
+                phigdsti_d   =  PHIGSTID_i + deltaphigd;
+                phigdgat_d   =  PHIGGATD_i + deltaphigd;
+
+                ftdbot_d     =  (pow(auxt, 1.5)) * exp(0.5 * ((phigrbot_d * phitrinv) - (phigdbot_d * phitdinv)));
+                ftdsti_d     =  (pow(auxt, 1.5)) * exp(0.5 * ((phigrsti_d * phitrinv) - (phigdsti_d * phitdinv)));
+                ftdgat_d     =  (pow(auxt, 1.5)) * exp(0.5 * ((phigrgat_d * phitrinv) - (phigdgat_d * phitdinv)));
+
+                idsatbot_d   =  IDSATRBOTD_i * ftdbot_d * ftdbot_d;
+                idsatsti_d   =  IDSATRSTID_i * ftdsti_d * ftdsti_d;
+                idsatgat_d   =  IDSATRGATD_i * ftdgat_d * ftdgat_d;
+
+                ubibot_d     =  VBIRBOTD_i * auxt - 2.0 * phitd * ln(ftdbot_d);
+                ubisti_d     =  VBIRSTID_i * auxt - 2.0 * phitd * ln(ftdsti_d);
+                ubigat_d     =  VBIRGATD_i * auxt - 2.0 * phitd * ln(ftdgat_d);
+
+                vbibot_d     =  ubibot_d + phitd * ln(1.0 + exp((`vbilow - ubibot_d) * phitdinv));
+                vbisti_d     =  ubisti_d + phitd * ln(1.0 + exp((`vbilow - ubisti_d) * phitdinv));
+                vbigat_d     =  ubigat_d + phitd * ln(1.0 + exp((`vbilow - ubigat_d) * phitdinv));
+
+                vbiinvbot_d  =  1.0 / vbibot_d;
+                vbiinvsti_d  =  1.0 / vbisti_d;
+                vbiinvgat_d  =  1.0 / vbigat_d;
+
+                one_minus_PBOT_d = 1.0 - PBOTD_i;
+                one_minus_PSTI_d = 1.0 - PSTID_i;
+                one_minus_PGAT_d = 1.0 - PGATD_i;
+
+                one_over_one_minus_PBOT_d = 1.0 / one_minus_PBOT_d;
+                one_over_one_minus_PSTI_d = 1.0 / one_minus_PSTI_d;
+                one_over_one_minus_PGAT_d = 1.0 / one_minus_PGAT_d;
+
+                cjobot_d     =  CJORBOTD_i * pow((VBIRBOTD_i * vbiinvbot_d), PBOTD_i);
+                cjosti_d     =  CJORSTID_i * pow((VBIRSTID_i * vbiinvsti_d), PSTID_i);
+                cjogat_d     =  CJORGATD_i * pow((VBIRGATD_i * vbiinvgat_d), PGATD_i);
+
+                qprefbot_d   =  cjobot_d * vbibot_d * one_over_one_minus_PBOT_d;
+                qprefsti_d   =  cjosti_d * vbisti_d * one_over_one_minus_PSTI_d;
+                qprefgat_d   =  cjogat_d * vbigat_d * one_over_one_minus_PGAT_d;
+
+                qpref2bot_d  = `a * cjobot_d;
+                qpref2sti_d  = `a * cjosti_d;
+                qpref2gat_d  = `a * cjogat_d;
+
+                wdepnulrbot_d =  EPSSI / CJORBOTD_i;
+                wdepnulrsti_d =  XJUNSTID_i * EPSSI / CJORSTID_i;
+                wdepnulrgat_d =  XJUNGATD_i * EPSSI / CJORGATD_i;
+
+                wdepnulrinvbot_d = 1.0 / wdepnulrbot_d;
+                wdepnulrinvsti_d = 1.0 / wdepnulrsti_d;
+                wdepnulrinvgat_d = 1.0 / wdepnulrgat_d;
+
+                VBIRBOTinv_d =  1.0 / VBIRBOTD_i;
+                VBIRSTIinv_d =  1.0 / VBIRSTID_i;
+                VBIRGATinv_d =  1.0 / VBIRGATD_i;
+
+                deltaEbot_d  =  max(0.5 * phigdbot_d, phitd);
+                deltaEsti_d  =  max(0.5 * phigdsti_d, phitd);
+                deltaEgat_d  =  max(0.5 * phigdgat_d, phitd);
+
+                atatbot_d    =  deltaEbot_d * phitdinv;
+                atatsti_d    =  deltaEsti_d * phitdinv;
+                atatgat_d    =  deltaEgat_d * phitdinv;
+
+                btatpartbot_d =  sqrt(32.0 * MEFFTATBOTD_i * `MELE * `QELE * (deltaEbot_d * deltaEbot_d * deltaEbot_d)) / (3.0 * `HBAR);
+                btatpartsti_d =  sqrt(32.0 * MEFFTATSTID_i * `MELE * `QELE * (deltaEsti_d * deltaEsti_d * deltaEsti_d)) / (3.0 * `HBAR);
+                btatpartgat_d =  sqrt(32.0 * MEFFTATGATD_i * `MELE * `QELE * (deltaEgat_d * deltaEgat_d * deltaEgat_d)) / (3.0 * `HBAR);
+
+                fbbtbot_d    =  FBBTRBOTD_i * (1.0 + STFBBTBOTD_i * (tkd - tkr));
+                fbbtsti_d    =  FBBTRSTID_i * (1.0 + STFBBTSTID_i * (tkd - tkr));
+                fbbtgat_d    =  FBBTRGATD_i * (1.0 + STFBBTGATD_i * (tkd - tkr));
+                fbbtbot_d    = `CLIP_LOW(fbbtbot_d, 0.0);
+                fbbtsti_d    = `CLIP_LOW(fbbtsti_d, 0.0);
+                fbbtgat_d    = `CLIP_LOW(fbbtgat_d, 0.0);
+
+                fstopbot_d   =  1.0 / (1.0 - pow(alphaav, PBRBOTD_i));
+                fstopsti_d   =  1.0 / (1.0 - pow(alphaav, PBRSTID_i));
+                fstopgat_d   =  1.0 / (1.0 - pow(alphaav, PBRGATD_i));
+
+                VBRinvbot_d  =  1.0 / VBRBOTD_i;
+                VBRinvsti_d  =  1.0 / VBRSTID_i;
+                VBRinvgat_d  =  1.0 / VBRGATD_i;
+
+                slopebot_d   = -(fstopbot_d * fstopbot_d * pow(alphaav, (PBRBOTD_i - 1.0))) * PBRBOTD_i * VBRinvbot_d;
+                slopesti_d   = -(fstopsti_d * fstopsti_d * pow(alphaav, (PBRSTID_i - 1.0))) * PBRSTID_i * VBRinvsti_d;
+                slopegat_d   = -(fstopgat_d * fstopgat_d * pow(alphaav, (PBRGATD_i - 1.0))) * PBRGATD_i * VBRinvgat_d;
+                `endif // JUNCAP_StandAlone
diff --git a/ihp-sg13g2/libs.tech/xyce/adms/JUNCAP200_macrodefs.include b/ihp-sg13g2/libs.tech/xyce/adms/JUNCAP200_macrodefs.include
new file mode 100644
index 00000000..bad70298
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/adms/JUNCAP200_macrodefs.include
@@ -0,0 +1,471 @@
+//======================================================================================
+//======================================================================================
+// Filename: JUNCAP200_macrodefs.include
+//======================================================================================
+//======================================================================================
+//
+//  (c) Copyright notice
+//
+//  Copyright 2004-2017 NXP Semiconductors, 2015-2017 Commissariat a l’energie atomique
+//  et aux energies alternatives (CEA) and 2012-2015 Delft University of Technology
+//  Licensed under the Educational Community License, Version 2.0 (the "License"); you
+//  may not use this file except in compliance with the License. You may obtain a copy
+//  of the License at
+//  http://opensource.org/licenses/ECL-2.0
+//  Unless required by applicable law or agreed to in writing, software distributed under
+//  the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF
+//  ANY KIND, either express or implied. See the License for the specific language
+//  governing permissions and limitations under the License.
+//
+//
+//  Version: 200.5.0, August 2016
+//
+//======================================================================================
+//======================================================================================
+//
+// Further information can be found in the file releasenotesPSP103.txt
+//
+
+///////////////////////////////////////////
+//
+// Macros and constants used in JUNCAP2
+//
+///////////////////////////////////////////
+
+// Other constants
+`define MINTEMP          -2.5e2
+`define vbilow            5.0e-2
+`define a                 2.0
+`define epsch             0.1
+`define dvbi              5.0e-2
+`define epsav             1.0e-6
+`define vbrmax            1.0e3
+`define vmaxlarge         1.0e8
+`define aerfc             0.29214664
+`define twothirds         0.666666666666667
+
+// Clipping values
+`define levelnumber        2.0e2
+`define AB_cliplow         0.0
+`define LS_cliplow         0.0
+`define LG_cliplow         0.0
+`define MULT_cliplow       0.0
+`define TRJ_cliplow        `MINTEMP
+`define IMAX_cliplow       1.0e-12
+`define FREV_cliplow       1.0e1
+`define FREV_cliphigh      1.0e10
+`define CJORBOT_cliplow    1.0e-12
+`define CJORSTI_cliplow    1.0e-18
+`define CJORGAT_cliplow    1.0e-18
+`define VBIR_cliplow       `vbilow
+`define P_cliplow          5.0e-2
+`define P_cliphigh         0.95
+`define IDSATR_cliplow     0.0
+`define CSRH_cliplow       0.0
+`define XJUN_cliplow       1.0e-9
+`define CTAT_cliplow       0.0
+`define MEFFTAT_cliplow    1.0e-2
+`define CBBT_cliplow       0.0
+`define VBR_cliplow        0.1
+`define PBR_cliplow        0.1
+`define VJUNREF_cliplow    0.5
+`define FJUNQ_cliplow      0.0
+
+
+/////////////////////////////////////////////////////////////////////////////
+//
+//  Macro definitions.
+//
+//  Note that because at present locally scoped variables
+//  can only be in named blocks, the intermediate variables
+//  used in the macros below must be explicitly declared
+//  as variables.
+//
+/////////////////////////////////////////////////////////////////////////////
+
+// Variable declarations of variables that need to be *local* in juncap-express initialization
+
+`define LocalGlobalVars \
+/* declaration of variables needed in macro "calcerfcexpmtat" */ \
+real ysq, terfc, erfcpos; \
+ \
+/* declaration of variables needed in hypfunction 5 */ \
+real h1, h2, h2d, h3, h4, h5; \
+ \
+/* declaration of variables calculated outside macro "juncapfunction", voltage-dependent part */ \
+real idmult, vj, z, zinv, two_psistar, vjlim, vjsrh, vbbt, vav; \
+ \
+/* declaration of variables used within macro "juncapfunction" */ \
+real tmp, id; \
+real isrh, vbi_minus_vjsrh, wsrhstep, dwsrh, wsrh, wdep, asrh; \
+real itat, btat, twoatatoverthreebtat, umaxbeforelimiting, umax, sqrtumax, umaxpoweronepointfive; \
+real wgamma, wtat, ktat, ltat, mtat, xerfc, erfctimesexpmtat, gammamax; \
+real ibbt, Fmaxr; \
+real fbreakdown;
+
+// Instance parameter dependent initialization
+`define JuncapInitInstance(AB_i, LS_i, LG_i, idsatbot, idsatsti, idsatgat, vbibot, vbisti, vbigat, PBOT_i, PSTI_i, PGAT_i, VBIRBOT_i, VBIRSTI_i, VBIRGAT_i, VMAX, exp_VMAX_over_phitd, vbimin, vch, vfmin, vbbtlim) \
+if (idsatbot * AB_i > 0.0) begin \
+        vmaxbot      =  phitd * ln(IMAX_i / (idsatbot * AB_i) + 1.0); \
+end else begin \
+        vmaxbot      = `vmaxlarge; \
+end \
+if (idsatsti * LS_i > 0.0) begin \
+        vmaxsti      =  phitd * ln(IMAX_i / (idsatsti * LS_i) + 1.0); \
+end else begin \
+        vmaxsti      = `vmaxlarge; \
+end \
+if (idsatgat * LG_i > 0.0) begin \
+        vmaxgat      =  phitd * ln(IMAX_i / (idsatgat * LG_i) + 1.0); \
+end else begin \
+        vmaxgat      = `vmaxlarge; \
+end \
+VMAX         =  min(min(vmaxbot, vmaxsti), vmaxgat); \
+`expl(VMAX * phitdinv, exp_VMAX_over_phitd) \
+ \
+/* determination of minimum value of the relevant built-in voltages */ \
+/* and determination of limiting value of conditioned voltage for BBT calculation */ \
+vbibot2      =  vbibot; \
+vbisti2      =  vbisti; \
+vbigat2      =  vbigat; \
+pbot2        =  PBOT_i; \
+psti2        =  PSTI_i; \
+pgat2        =  PGAT_i; \
+vbibot2r     =  VBIRBOT_i; \
+vbisti2r     =  VBIRSTI_i; \
+vbigat2r     =  VBIRGAT_i; \
+if (AB_i == 0.0) begin \
+        vbibot2      =  vbisti + vbigat; \
+        pbot2        =  0.9 * min(PSTI_i, PGAT_i); \
+        vbibot2r     =  VBIRSTI_i + VBIRGAT_i; \
+end \
+if (LS_i == 0.0) begin \
+        vbisti2      =  vbibot + vbigat; \
+        psti2        =  0.9 * min(PBOT_i, PGAT_i); \
+        vbisti2r     =  VBIRBOT_i + VBIRGAT_i; \
+end \
+if (LG_i == 0.0) begin \
+        vbigat2      =  vbibot + vbisti; \
+        pgat2        =  0.9 * min(PBOT_i, PSTI_i); \
+        vbigat2r     =  VBIRBOT_i + VBIRSTI_i; \
+end \
+vbimin       =  min(min(vbibot2, vbisti2), vbigat2); \
+vch          =  vbimin * `epsch; \
+pmax         =  max(max(pbot2, psti2), pgat2); \
+vfmin        =  vbimin * (1.0 - (pow(`a, (-1.0 / (pmax))))); \
+vbbtlim      =  min(min(vbibot2r, vbisti2r), vbigat2r) - `dvbi;
+
+
+// Special power-functions
+
+`define mypower(x,power,result) \
+if (power == 0.5) begin \
+        result       =  sqrt(x); \
+end else begin \
+        result       =  pow(x, power); \
+end
+
+`define mypower2(x,power,result) \
+if (power == -1.0) begin \
+        result       =  1.0 / (x); \
+end else begin \
+        result       =  pow(x, power); \
+end
+
+`define mypower3(x,power,result) \
+if (power == 4.0) begin \
+        result       =  (x) * (x) * (x) * (x); \
+end else begin \
+        result       =  pow(abs(x), power); \
+end
+
+// Smoothing functions
+`define hypfunction2(x,x0,eps,hyp2) \
+hyp2         =  0.5 * ((x) + (x0) - sqrt(((x) - (x0)) * ((x) - (x0)) + 4.0 * (eps) * (eps)));
+
+`define hypfunction5(x,x0,eps,hyp5) \
+h1           =  4.0 * (eps) * (eps); \
+h2           =  (eps) / (x0); \
+h2d          =  (x) + (eps) * h2; \
+h3           =  (x0) + h2d; \
+h4           =  (x0) - h2d; \
+h5           =  sqrt(h4 * h4 + h1); \
+hyp5         =  2.0 * ((x) * (x0) / (h3 + h5));
+
+
+// A special function used to calculate TAT-currents,
+// including an approximation of the erfc-function
+
+`define calcerfcexpmtat(y,m,result) \
+ysq          =  y * y; \
+if (y > 0.0) begin \
+        terfc        =  1.0 / (1.0 + perfc * y); \
+end else begin \
+        terfc        =  1.0 / (1.0 - perfc * y); \
+end \
+`expl_low(-ysq + m, tmp) \
+erfcpos = (`aerfc * terfc + berfc * (terfc * terfc) + cerfc * (terfc * terfc * terfc)) * tmp; \
+if (y > 0.0) begin \
+        result       =  erfcpos; \
+end else begin \
+        `expl_low(m, tmp) \
+        result       =  2.0 * tmp - erfcpos; \
+end
+
+// This is the main function of the JUNCAP2-model. It returns the current and charge
+// for a single diode
+`define juncapfunction(VAK,qpref,qpref2,vbiinv,one_minus_P,idsat,CSRH,CTAT,vbi,wdepnulr,VBIRinv,P,ftd,btatpart,atat,one_over_one_minus_P,CBBT,VBIR,wdepnulrinv,fbbt,VBR,VBRinv,PBR,fstop,slope,Ijprime,Qjprime) \
+`mypower((1.0 - vj * vbiinv), one_minus_P, tmp) \
+Qjprime      =  qpref * (1.0 - tmp) + qpref2 * (VAK - vj); \
+id           =  idsat * idmult; \
+if ((CSRH == 0.0) && (CTAT == 0.0)) begin \
+        isrh         =  0.0; \
+end else begin \
+        vbi_minus_vjsrh =  vbi-vjsrh; \
+        wsrhstep     =  1.0 - sqrt(1.0 - two_psistar / vbi_minus_vjsrh); \
+        if (P == 0.5) begin \
+                dwsrh        =  0.0; \
+        end else begin \
+                dwsrh        =  ((wsrhstep * wsrhstep * ln(wsrhstep) / (1.0 - wsrhstep)) + wsrhstep) * (1.0 - 2.0 * P); \
+        end \
+        wsrh         =  wsrhstep + dwsrh; \
+        `mypower(vbi_minus_vjsrh * VBIRinv, P, tmp) \
+        wdep         =  wdepnulr * tmp; \
+        asrh         =  ftd * ((zinv - 1.0) * wdep); \
+        isrh         =  CSRH * (asrh * wsrh); \
+end \
+if (CTAT == 0.0) begin \
+        itat         =  0.0; \
+end else begin \
+        btat         =  btatpart * ((wdep * one_minus_P) / vbi_minus_vjsrh); \
+        twoatatoverthreebtat = (`twothirds * atat) / btat; \
+        umaxbeforelimiting = twoatatoverthreebtat * twoatatoverthreebtat; \
+        umax         =  sqrt(umaxbeforelimiting * umaxbeforelimiting / (umaxbeforelimiting * umaxbeforelimiting + 1.0)); \
+        sqrtumax     =  sqrt(abs(umax)); \
+        umaxpoweronepointfive = umax * sqrtumax; \
+        `mypower2((1.0 + btat * umaxpoweronepointfive), (-P * one_over_one_minus_P), wgamma) \
+        wtat         =  wsrh * wgamma / (wsrh + wgamma); \
+        ktat         =  sqrt(0.375 * (btat / sqrtumax)); \
+        ltat         =  2.0 * (twoatatoverthreebtat * sqrtumax) - umax; \
+        mtat         =  atat * twoatatoverthreebtat * sqrtumax - atat * umax + 0.5 * (btat * umaxpoweronepointfive); \
+        xerfc        =  (ltat - 1.0) * ktat; \
+        `calcerfcexpmtat(xerfc, mtat, erfctimesexpmtat) \
+        gammamax     = `SQRTPI * 0.5 * (atat * erfctimesexpmtat  / ktat); \
+        itat         =  CTAT * (asrh * gammamax * wtat); \
+end \
+if (CBBT == 0.0) begin \
+        ibbt         =  0.0; \
+end else begin \
+        `mypower(((VBIR - vbbt) * VBIRinv), P, tmp) \
+        Fmaxr        =  one_over_one_minus_P * ((VBIR - vbbt) * wdepnulrinv / tmp); \
+        `expl(-fbbt / Fmaxr, tmp) \
+        ibbt         =  CBBT * (VAK * Fmaxr * Fmaxr * tmp); \
+end \
+if (VBR > `vbrmax) begin \
+        fbreakdown   =  1.0; \
+end else begin \
+        if (vav > -alphaav * VBR) begin \
+                `mypower3(vav * VBRinv, PBR, tmp) \
+                fbreakdown    =  1.0 / (1.0 - tmp); \
+        end else begin \
+                fbreakdown    =  fstop + (vav + alphaav * VBR) * slope; \
+        end \
+end \
+Ijprime      =  (id + isrh + itat + ibbt) * fbreakdown;
+
+
+// The following code is written as a macro because the naming of the instance parameters is
+// different for JUNCAP2 stand-alone and JUNCAP2-in-PSP: AB, LS, LG for JUNCAP2 stand-alone,
+// ABSOURCE, LSSOURCE, LGSOURCE for source junction in PSP and ABDRAIN, LSDRAIN, LGDRAIN for
+// drain junction in PSP
+`define juncapcommon(V, AB_i, LS_i, LG_i, qprefbot, qpref2bot, vbiinvbot, one_minus_PBOT, idsatbot, CSRHBOT_i, CTATBOT_i, vbibot, wdepnulrbot, VBIRBOTinv, PBOT_i, ftdbot, btatpartbot, atatbot, one_over_one_minus_PBOT, CBBTBOT_i, VBIRBOT_i, wdepnulrinvbot, fbbtbot, VBRBOT_i, VBRinvbot, PBRBOT_i, fstopbot, slopebot, qprefsti, qpref2sti, vbiinvsti, one_minus_PSTI, idsatsti, CSRHSTI_i, CTATSTI_i, vbisti, wdepnulrsti, VBIRSTIinv, PSTI_i, ftdsti, btatpartsti, atatsti, one_over_one_minus_PSTI, CBBTSTI_i, VBIRSTI_i, wdepnulrinvsti, fbbtsti, VBRSTI_i, VBRinvsti, PBRSTI_i, fstopsti, slopesti, qprefgat, qpref2gat, vbiinvgat, one_minus_PGAT, idsatgat, CSRHGAT_i, CTATGAT_i, vbigat, wdepnulrgat, VBIRGATinv, PGAT_i, ftdgat, btatpartgat, atatgat, one_over_one_minus_PGAT, CBBTGAT_i, VBIRGAT_i, wdepnulrinvgat, fbbtgat, VBRGAT_i, VBRinvgat, PBRGAT_i, fstopgat, slopegat, VMAX, exp_VMAX_over_phitd, vbimin, vch, vfmin, vbbtlim, ijunbot, qjunbot, ijunsti, qjunsti, ijungat, qjungat) \
+vbbt         =  0.0; \
+two_psistar  =  0.0; \
+if ( !( ((AB_i) == 0.0) && ((LS_i) == 0.0) && ((LG_i) == 0.0) ) ) begin \
+        `hypfunction5(V, vfmin, vch, vj) \
+        if (V < VMAX) begin \
+                `expl(0.5 * (V * phitdinv), zinv) \
+                idmult       =  zinv * zinv; \
+        end else begin \
+                idmult       =  (1.0 + (V - VMAX) * phitdinv) * exp_VMAX_over_phitd; \
+                zinv         =  sqrt(idmult); \
+        end \
+        idmult       =  idmult - 1.0; \
+        z            =  1.0 / zinv; \
+        if (V > 0.0) begin \
+                two_psistar    =  2.0 * (phitd * ln(2.0 + z + sqrt((z + 1.0) * (z + 3.0)))); \
+        end else begin \
+                two_psistar    = -V + 2.0 * (phitd * ln(2.0 * zinv + 1.0 + sqrt((1.0 + zinv) * (1.0 + 3.0 * zinv)))); \
+        end \
+        vjlim        =  vbimin - two_psistar; \
+        `hypfunction2(V, vjlim, phitd, vjsrh) \
+        `hypfunction2(V, vbbtlim, phitr, vbbt) \
+        `hypfunction2(V, 0.0, `epsav, vav) \
+end \
+if ((AB_i) == 0.0) begin \
+        ijunbot      =  0.0; \
+        qjunbot      =  0.0; \
+end else begin \
+        `juncapfunction(V, qprefbot, qpref2bot, vbiinvbot, one_minus_PBOT, idsatbot, CSRHBOT_i, CTATBOT_i, vbibot, wdepnulrbot, VBIRBOTinv, PBOT_i, ftdbot, btatpartbot, atatbot, one_over_one_minus_PBOT, CBBTBOT_i, VBIRBOT_i, wdepnulrinvbot, fbbtbot, VBRBOT_i, VBRinvbot, PBRBOT_i, fstopbot, slopebot, ijunbot, qjunbot) \
+end \
+if ((LS_i) == 0.0) begin \
+        ijunsti      =  0.0; \
+        qjunsti      =  0.0; \
+end else begin \
+        `juncapfunction(V, qprefsti, qpref2sti, vbiinvsti, one_minus_PSTI, idsatsti, CSRHSTI_i, CTATSTI_i, vbisti, wdepnulrsti, VBIRSTIinv, PSTI_i, ftdsti, btatpartsti, atatsti, one_over_one_minus_PSTI, CBBTSTI_i, VBIRSTI_i, wdepnulrinvsti, fbbtsti, VBRSTI_i, VBRinvsti, PBRSTI_i, fstopsti, slopesti, ijunsti, qjunsti) \
+end \
+if ((LG_i) == 0.0) begin \
+        ijungat      =  0.0; \
+        qjungat      =  0.0; \
+end else begin \
+        `juncapfunction(V, qprefgat, qpref2gat, vbiinvgat, one_minus_PGAT, idsatgat, CSRHGAT_i, CTATGAT_i, vbigat, wdepnulrgat, VBIRGATinv, PGAT_i, ftdgat, btatpartgat, atatgat, one_over_one_minus_PGAT, CBBTGAT_i, VBIRGAT_i, wdepnulrinvgat, fbbtgat, VBRGAT_i, VBRinvgat, PBRGAT_i, fstopgat, slopegat, ijungat, qjungat) \
+end
+
+//============================================================================================================
+//  JUNCAP-express
+//
+//  The macros below are used in the express-version of JUNCAP2
+//============================================================================================================
+
+`define relerr      1.0e-3
+`define P1(x)       ((x) + 1.0)
+
+`define expll(x, xlow, expxlow, xhigh, expxhigh) \
+((x) < (xlow)) ? (expxlow) / `P1((xlow) - (x)) : (((x) > (xhigh)) ? (expxhigh) * `P1((x) - (xhigh)) : exp(x))
+
+
+// The "JuncapExpressInit"-macro below is split into three parts, as some verilog-A compilers cannot handle
+// macros beyond a certain size. Moreover, it is useful to limit the list of input and output variables.
+
+// Part 1
+`define JuncapExpressInit1(AB_i, LS_i, LG_i, VJUNREF_i, qprefbot, qpref2bot, vbiinvbot, one_minus_PBOT, idsatbot, CSRHBOT_i, CTATBOT_i, vbibot, wdepnulrbot, VBIRBOTinv, PBOT_i, ftdbot, btatpartbot, atatbot, one_over_one_minus_PBOT, CBBTBOT_i, VBIRBOT_i, wdepnulrinvbot, fbbtbot, VBRBOT_i, VBRinvbot, PBRBOT_i, fstopbot, slopebot, qprefsti, qpref2sti, vbiinvsti, one_minus_PSTI, idsatsti, CSRHSTI_i, CTATSTI_i, vbisti, wdepnulrsti, VBIRSTIinv, PSTI_i, ftdsti, btatpartsti, atatsti, one_over_one_minus_PSTI, CBBTSTI_i, VBIRSTI_i, wdepnulrinvsti, fbbtsti, VBRSTI_i, VBRinvsti, PBRSTI_i, fstopsti, slopesti, qprefgat, qpref2gat, vbiinvgat, one_minus_PGAT, idsatgat, CSRHGAT_i, CTATGAT_i, vbigat, wdepnulrgat, VBIRGATinv, PGAT_i, ftdgat, btatpartgat, atatgat, one_over_one_minus_PGAT, CBBTGAT_i, VBIRGAT_i, wdepnulrinvgat, fbbtgat, VBRGAT_i, VBRinvgat, PBRGAT_i, fstopgat, slopegat, VMAX, exp_VMAX_over_phitd, vbimin, vch, vfmin, vbbtlim) \
+FRACNA       =  0.4; \
+FRACNB       =  0.65; \
+FRACI        =  0.8; \
+/* Sample voltages */ \
+V1           = -FRACNA * VJUNREF_i; \
+V2           = -FRACNB * VJUNREF_i; \
+V3           = -FRACI * VJUNREF_i; \
+V4           =  0.1; \
+V5           =  0.2; \
+/* evaluate full JUNCAP-model at five voltages */ \
+`juncapcommon(V1, AB_i, LS_i, LG_i, qprefbot, qpref2bot, vbiinvbot, one_minus_PBOT, idsatbot, CSRHBOT_i, CTATBOT_i, vbibot, wdepnulrbot, VBIRBOTinv, PBOT_i, ftdbot, btatpartbot, atatbot, one_over_one_minus_PBOT, CBBTBOT_i, VBIRBOT_i, wdepnulrinvbot, fbbtbot, VBRBOT_i, VBRinvbot, PBRBOT_i, fstopbot, slopebot, qprefsti, qpref2sti, vbiinvsti, one_minus_PSTI, idsatsti, CSRHSTI_i, CTATSTI_i, vbisti, wdepnulrsti, VBIRSTIinv, PSTI_i, ftdsti, btatpartsti, atatsti, one_over_one_minus_PSTI, CBBTSTI_i, VBIRSTI_i, wdepnulrinvsti, fbbtsti, VBRSTI_i, VBRinvsti, PBRSTI_i, fstopsti, slopesti, qprefgat, qpref2gat, vbiinvgat, one_minus_PGAT, idsatgat, CSRHGAT_i, CTATGAT_i, vbigat, wdepnulrgat, VBIRGATinv, PGAT_i, ftdgat, btatpartgat, atatgat, one_over_one_minus_PGAT, CBBTGAT_i, VBIRGAT_i, wdepnulrinvgat, fbbtgat, VBRGAT_i, VBRinvgat, PBRGAT_i, fstopgat, slopegat, VMAX, exp_VMAX_over_phitd, vbimin, vch, vfmin, vbbtlim, ijunbot, qjunbot, ijunsti, qjunsti, ijungat, qjungat) \
+I1           =  AB_i * ijunbot + LS_i * ijunsti + LG_i * ijungat; \
+`juncapcommon(V2, AB_i, LS_i, LG_i, qprefbot, qpref2bot, vbiinvbot, one_minus_PBOT, idsatbot, CSRHBOT_i, CTATBOT_i, vbibot, wdepnulrbot, VBIRBOTinv, PBOT_i, ftdbot, btatpartbot, atatbot, one_over_one_minus_PBOT, CBBTBOT_i, VBIRBOT_i, wdepnulrinvbot, fbbtbot, VBRBOT_i, VBRinvbot, PBRBOT_i, fstopbot, slopebot, qprefsti, qpref2sti, vbiinvsti, one_minus_PSTI, idsatsti, CSRHSTI_i, CTATSTI_i, vbisti, wdepnulrsti, VBIRSTIinv, PSTI_i, ftdsti, btatpartsti, atatsti, one_over_one_minus_PSTI, CBBTSTI_i, VBIRSTI_i, wdepnulrinvsti, fbbtsti, VBRSTI_i, VBRinvsti, PBRSTI_i, fstopsti, slopesti, qprefgat, qpref2gat, vbiinvgat, one_minus_PGAT, idsatgat, CSRHGAT_i, CTATGAT_i, vbigat, wdepnulrgat, VBIRGATinv, PGAT_i, ftdgat, btatpartgat, atatgat, one_over_one_minus_PGAT, CBBTGAT_i, VBIRGAT_i, wdepnulrinvgat, fbbtgat, VBRGAT_i, VBRinvgat, PBRGAT_i, fstopgat, slopegat, VMAX, exp_VMAX_over_phitd, vbimin, vch, vfmin, vbbtlim, ijunbot, qjunbot, ijunsti, qjunsti, ijungat, qjungat) \
+I2           =  AB_i * ijunbot + LS_i * ijunsti + LG_i * ijungat; \
+`juncapcommon(V3, AB_i, LS_i, LG_i, qprefbot, qpref2bot, vbiinvbot, one_minus_PBOT, idsatbot, CSRHBOT_i, CTATBOT_i, vbibot, wdepnulrbot, VBIRBOTinv, PBOT_i, ftdbot, btatpartbot, atatbot, one_over_one_minus_PBOT, CBBTBOT_i, VBIRBOT_i, wdepnulrinvbot, fbbtbot, VBRBOT_i, VBRinvbot, PBRBOT_i, fstopbot, slopebot, qprefsti, qpref2sti, vbiinvsti, one_minus_PSTI, idsatsti, CSRHSTI_i, CTATSTI_i, vbisti, wdepnulrsti, VBIRSTIinv, PSTI_i, ftdsti, btatpartsti, atatsti, one_over_one_minus_PSTI, CBBTSTI_i, VBIRSTI_i, wdepnulrinvsti, fbbtsti, VBRSTI_i, VBRinvsti, PBRSTI_i, fstopsti, slopesti, qprefgat, qpref2gat, vbiinvgat, one_minus_PGAT, idsatgat, CSRHGAT_i, CTATGAT_i, vbigat, wdepnulrgat, VBIRGATinv, PGAT_i, ftdgat, btatpartgat, atatgat, one_over_one_minus_PGAT, CBBTGAT_i, VBIRGAT_i, wdepnulrinvgat, fbbtgat, VBRGAT_i, VBRinvgat, PBRGAT_i, fstopgat, slopegat, VMAX, exp_VMAX_over_phitd, vbimin, vch, vfmin, vbbtlim, ijunbot, qjunbot, ijunsti, qjunsti, ijungat, qjungat) \
+I3           =  AB_i * ijunbot + LS_i * ijunsti + LG_i * ijungat;
+
+// Part 2
+`define JuncapExpressInit2(AB_i, LS_i, LG_i, qprefbot, qpref2bot, vbiinvbot, one_minus_PBOT, idsatbot, CSRHBOT_i, CTATBOT_i, vbibot, wdepnulrbot, VBIRBOTinv, PBOT_i, ftdbot, btatpartbot, atatbot, one_over_one_minus_PBOT, CBBTBOT_i, VBIRBOT_i, wdepnulrinvbot, fbbtbot, VBRBOT_i, VBRinvbot, PBRBOT_i, fstopbot, slopebot, qprefsti, qpref2sti, vbiinvsti, one_minus_PSTI, idsatsti, CSRHSTI_i, CTATSTI_i, vbisti, wdepnulrsti, VBIRSTIinv, PSTI_i, ftdsti, btatpartsti, atatsti, one_over_one_minus_PSTI, CBBTSTI_i, VBIRSTI_i, wdepnulrinvsti, fbbtsti, VBRSTI_i, VBRinvsti, PBRSTI_i, fstopsti, slopesti, qprefgat, qpref2gat, vbiinvgat, one_minus_PGAT, idsatgat, CSRHGAT_i, CTATGAT_i, vbigat, wdepnulrgat, VBIRGATinv, PGAT_i, ftdgat, btatpartgat, atatgat, one_over_one_minus_PGAT, CBBTGAT_i, VBIRGAT_i, wdepnulrinvgat, fbbtgat, VBRGAT_i, VBRinvgat, PBRGAT_i, fstopgat, slopegat, VMAX, exp_VMAX_over_phitd, vbimin, vch, vfmin, vbbtlim) \
+/* forward currents */ \
+`juncapcommon(V4, AB_i, LS_i, LG_i, qprefbot, qpref2bot, vbiinvbot, one_minus_PBOT, idsatbot, CSRHBOT_i, CTATBOT_i, vbibot, wdepnulrbot, VBIRBOTinv, PBOT_i, ftdbot, btatpartbot, atatbot, one_over_one_minus_PBOT, CBBTBOT_i, VBIRBOT_i, wdepnulrinvbot, fbbtbot, VBRBOT_i, VBRinvbot, PBRBOT_i, fstopbot, slopebot, qprefsti, qpref2sti, vbiinvsti, one_minus_PSTI, idsatsti, CSRHSTI_i, CTATSTI_i, vbisti, wdepnulrsti, VBIRSTIinv, PSTI_i, ftdsti, btatpartsti, atatsti, one_over_one_minus_PSTI, CBBTSTI_i, VBIRSTI_i, wdepnulrinvsti, fbbtsti, VBRSTI_i, VBRinvsti, PBRSTI_i, fstopsti, slopesti, qprefgat, qpref2gat, vbiinvgat, one_minus_PGAT, idsatgat, CSRHGAT_i, CTATGAT_i, vbigat, wdepnulrgat, VBIRGATinv, PGAT_i, ftdgat, btatpartgat, atatgat, one_over_one_minus_PGAT, CBBTGAT_i, VBIRGAT_i, wdepnulrinvgat, fbbtgat, VBRGAT_i, VBRinvgat, PBRGAT_i, fstopgat, slopegat, VMAX, exp_VMAX_over_phitd, vbimin, vch, vfmin, vbbtlim, ijunbot, qjunbot, ijunsti, qjunsti, ijungat, qjungat) \
+I4           =  AB_i * ijunbot + LS_i * ijunsti + LG_i * ijungat; \
+`juncapcommon(V5, AB_i, LS_i, LG_i, qprefbot, qpref2bot, vbiinvbot, one_minus_PBOT, idsatbot, CSRHBOT_i, CTATBOT_i, vbibot, wdepnulrbot, VBIRBOTinv, PBOT_i, ftdbot, btatpartbot, atatbot, one_over_one_minus_PBOT, CBBTBOT_i, VBIRBOT_i, wdepnulrinvbot, fbbtbot, VBRBOT_i, VBRinvbot, PBRBOT_i, fstopbot, slopebot, qprefsti, qpref2sti, vbiinvsti, one_minus_PSTI, idsatsti, CSRHSTI_i, CTATSTI_i, vbisti, wdepnulrsti, VBIRSTIinv, PSTI_i, ftdsti, btatpartsti, atatsti, one_over_one_minus_PSTI, CBBTSTI_i, VBIRSTI_i, wdepnulrinvsti, fbbtsti, VBRSTI_i, VBRinvsti, PBRSTI_i, fstopsti, slopesti, qprefgat, qpref2gat, vbiinvgat, one_minus_PGAT, idsatgat, CSRHGAT_i, CTATGAT_i, vbigat, wdepnulrgat, VBIRGATinv, PGAT_i, ftdgat, btatpartgat, atatgat, one_over_one_minus_PGAT, CBBTGAT_i, VBIRGAT_i, wdepnulrinvgat, fbbtgat, VBRGAT_i, VBRinvgat, PBRGAT_i, fstopgat, slopegat, VMAX, exp_VMAX_over_phitd, vbimin, vch, vfmin, vbbtlim, ijunbot, qjunbot, ijunsti, qjunsti, ijungat, qjungat) \
+I5           =  AB_i * ijunbot + LS_i * ijunsti + LG_i * ijungat;
+
+// Part 3
+`define JuncapExpressInit3(AB_i, LS_i, LG_i, idsatbot, idsatsti, idsatgat, ISATFOR1, MFOR1, ISATFOR2, MFOR2, ISATREV, MREV, m0flag) \
+/* compute internal parameters from these five (I,V)-values */ \
+ISATFOR1     =  AB_i * idsatbot + LS_i * idsatsti + LG_i * idsatgat; \
+I4_cor       =  I4 - ISATFOR1 * (exp(V4 * phitdinv * MFOR1) - 1.0); \
+I5_cor       =  I5 - ISATFOR1 * (exp(V5 * phitdinv * MFOR1) - 1.0); \
+if ( !( ((AB_i) == 0.0) && ((LS_i) == 0.0) && ((LG_i) == 0.0) ) ) begin \
+        if ((I4 > 0.0) && (I5 > 0.0)) begin \
+                if ((((I4_cor / I4) > `relerr) || ((I5_cor / I5) > `relerr)) && (I4_cor > 0.0) && (I5_cor > 0.0)) begin \
+                        alphaje      =  I4_cor / I5_cor; \
+                        MFOR2        =  phitd * ln(alphaje) / (V4 - V5); \
+                        ISATFOR2     =  I4_cor / (exp(V4 * phitdinv * MFOR2) - 1.0); \
+                end \
+        end \
+        I1_cor       =  I1 - ISATFOR1 * (exp(V1 * phitdinv * MFOR1) - 1.0) - ISATFOR2 * (exp(V1 * phitdinv * MFOR2) - 1.0); \
+        I2_cor       =  I2 - ISATFOR1 * (exp(V2 * phitdinv * MFOR1) - 1.0) - ISATFOR2 * (exp(V2 * phitdinv * MFOR2) - 1.0); \
+        I3_cor       =  I3 - ISATFOR1 * (exp(V3 * phitdinv * MFOR1) - 1.0) - ISATFOR2 * (exp(V3 * phitdinv * MFOR2) - 1.0); \
+        if ((I1 < 0.0) && (I2 < 0.0) && (I3 < 0.0)) begin \
+                if ((((I1_cor / I1) > `relerr) || ((I2_cor / I2) > `relerr) || ((I3_cor / I3) > `relerr)) \
+             && (I1_cor < 0.0) && (I2_cor < 0.0) && (I3_cor < 0.0)) begin \
+                        alphaje      =  I1_cor / I2_cor; \
+                        m0_rev       = -phitd * ln(alphaje) / (V1 - V2); /* zeroth order approximation */ \
+                        tt0          =  V2 / (V2 - V1); \
+                        tt1          =  phitd * (alphaje - 1.0) * (pow(alphaje, tt0) - 1.0); \
+                        tt0          =  V1 / (V1 - V2); \
+                        tt2          =  pow(alphaje, tt0) * (V2 - V1) + alphaje * V1 - V2; \
+                        mcor_rev     =  tt1 / tt2; /* first order Newton correction */ \
+                        MREV         =  m0_rev + mcor_rev; \
+                        if (abs(V3 * phitdinv * MREV) < 1.0e-6) begin \
+                                /* Taylor approximation needed */ \
+                                /* Note: ISATREV and MREV have different meaning in this situation!! */ \
+                                m0flag       =  1.0; \
+                                ISATREV      =  I3_cor * (1.0 / V3 + 0.5 * phitdinv * MREV); \
+                                MREV         = -0.5 * I3_cor * MREV * phitdinv / V3; \
+                        end else begin \
+                                m0flag       =  0.0; \
+                                ISATREV      = -I3_cor / (exp(-V3 * phitdinv * MREV) - 1.0); \
+                        end \
+                end \
+        end \
+end
+
+// Part 4
+`define JuncapExpressInit4(AB_i, LS_i, LG_i, FJUNQ_i, cjobot, cjosti, cjogat, zflagbot, zflagsti, zflaggat) \
+/* charge model initialization */ \
+zfrac        =  FJUNQ_i * (AB_i * cjobot + LS_i * cjosti + LG_i * cjogat); \
+if ((AB_i * cjobot) <= zfrac) begin \
+        zflagbot     =  0.0; \
+end \
+if ((LS_i * cjosti) <= zfrac) begin \
+        zflagsti     =  0.0; \
+end \
+if ((LG_i * cjogat) <= zfrac) begin \
+        zflaggat     =  0.0; \
+end
+
+// Part 5
+`define JuncapExpressInit5(AB_i, LS_i, LG_i, ISATFOR1, ISATFOR2, ISATREV, xhighf1, expxhf1, xhighf2, expxhf2, xhighr, expxhr) \
+/* calculate limits beyond which exponentials are linearly extrapolated */ \
+if ( !( ((AB_i) == 0.0) && ((LS_i) == 0.0) && ((LG_i) == 0.0) ) ) begin \
+        xhighf1      =  ln(0.5 * IMAX_i / (ISATFOR1 + 1.0e-21)); \
+        xhighf2      =  ln(0.5 * IMAX_i / (ISATFOR2 + 1.0e-21)); \
+        xhighr       =  ln(0.5 * IMAX_i / (abs(ISATREV) + 1.0e-21)); \
+end \
+xhighf1      =  min(xhighf1, `se05); \
+expxhf1      =  exp(xhighf1); \
+xhighf2      =  min(xhighf2, `se05); \
+expxhf2      =  exp(xhighf2); \
+xhighr       =  min(xhighr, `se05); \
+expxhr       =  exp(xhighr);
+
+`define JuncapExpressCurrent(V, MFOR1, ISATFOR1, MFOR2, ISATFOR2, MREV, ISATREV, m0flag, xhighf1, expxhf1, xhighf2, expxhf2, xhighr, expxhr, ijun) \
+tm0          =  V * phitdinv * MFOR1; \
+tm1          = `expll(tm0, -`se05, `ke05, xhighf1, expxhf1); \
+ijunfor1     =  ISATFOR1 * (tm1 - 1.0); \
+tm0          =  V * phitdinv * MFOR2; \
+tm1          = `expll(tm0, -`se05, `ke05, xhighf2, expxhf2); \
+ijunfor2     =  ISATFOR2 * (tm1 - 1.0); \
+ijunrev      =  0.0; \
+if (m0flag > 0.0) begin \
+        ijunrev      =  V * (ISATREV + V * MREV); \
+end else begin \
+        tm0          = -V * phitdinv * MREV; \
+        tm1          = `expll(tm0, -`se05, `ke05, xhighr, expxhr); \
+        ijunrev      = -ISATREV * (tm1 - 1.0); \
+end \
+ijun         =  ijunfor1 + ijunfor2 + ijunrev;
+
+`define JuncapExpressCharge(V, AB_i, LS_i, LG_i, qprefbot, qprefsti, qprefgat, qpref2bot, qpref2sti, qpref2gat, vbiinvbot, vbiinvsti, vbiinvgat, one_minus_PBOT, one_minus_PSTI, one_minus_PGAT, vfmin, vch, zflagbot, zflagsti, zflaggat, qjunbot, qjunsti, qjungat) \
+tmpv         =  0.0; \
+vjv          =  0.0; \
+`hypfunction5(V, vfmin, vch, vjv) \
+if (zflagbot > 0.5) begin \
+        `mypower((1.0 - vjv * vbiinvbot), one_minus_PBOT, tmpv) \
+        qjunbot      =  qprefbot * (1.0 - tmpv) + qpref2bot * (V - vjv); \
+end \
+if (zflagsti > 0.5) begin \
+        `mypower((1.0 - vjv * vbiinvsti), one_minus_PSTI, tmpv) \
+        qjunsti      =  qprefsti * (1.0 - tmpv) + qpref2sti * (V - vjv); \
+end \
+if (zflaggat > 0.5) begin \
+        `mypower((1.0 - vjv * vbiinvgat), one_minus_PGAT, tmpv) \
+        qjungat      = qprefgat * (1.0 - tmpv) + qpref2gat * (V - vjv); \
+end
+
diff --git a/ihp-sg13g2/libs.tech/xyce/adms/JUNCAP200_parlist.include b/ihp-sg13g2/libs.tech/xyce/adms/JUNCAP200_parlist.include
new file mode 100644
index 00000000..94c0fef6
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/adms/JUNCAP200_parlist.include
@@ -0,0 +1,181 @@
+//======================================================================================
+//======================================================================================
+// Filename: JUNCAP200_parlist.include
+//======================================================================================
+//======================================================================================
+//
+//  (c) Copyright notice
+//
+//  Copyright 2004-2017 NXP Semiconductors, 2015-2017 Commissariat a l’energie atomique
+//  et aux energies alternatives (CEA) and 2012-2015 Delft University of Technology
+//  Licensed under the Educational Community License, Version 2.0 (the "License"); you
+//  may not use this file except in compliance with the License. You may obtain a copy
+//  of the License at
+//  http://opensource.org/licenses/ECL-2.0
+//  Unless required by applicable law or agreed to in writing, software distributed under
+//  the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF
+//  ANY KIND, either express or implied. See the License for the specific language
+//  governing permissions and limitations under the License.
+//
+//
+//  Version: 200.5.0, August 2016
+//
+//======================================================================================
+//======================================================================================
+//
+// Further information can be found in the file releasenotesPSP103.txt
+//
+
+        //  --------------------------------------------------------------------------------------------------------------
+        //  JUNCAP2 - Reduced parameter list
+        //  --------------------------------------------------------------------------------------------------------------
+
+                `MPRco(IMAX           ,1000.0     ,"A"        ,`IMAX_cliplow     ,inf              ,"Maximum current up to which forward current behaves exponentially")
+                `MPRco(TRJ            ,21.0       ,"C"        ,`TRJ_cliplow      ,inf              ,"Reference temperature")
+                `MPRcc(FREV           ,1.0e3      ,""         ,`FREV_cliplow     ,`FREV_cliphigh   ,"Coefficient for reverse breakdown current limitation")
+
+        // Parameters for source-bulk junction
+        `ifdef JUNCAP_StandAlone
+                `MPRco(CJORBOT        ,1.0e-3     ,"Fm^-2"    ,`CJORBOT_cliplow  ,inf              ,"Zero-bias capacitance per unit-of-area of bottom component")
+                `MPRco(CJORSTI        ,1.0e-9     ,"Fm^-1"    ,`CJORSTI_cliplow  ,inf              ,"Zero-bias capacitance per unit-of-length of STI-edge component")
+                `MPRco(CJORGAT        ,1.0e-9     ,"Fm^-1"    ,`CJORGAT_cliplow  ,inf              ,"Zero-bias capacitance per unit-of-length of gate-edge component")
+                `MPRco(VBIRBOT        ,1.0        ,"V"        ,`VBIR_cliplow     ,inf              ,"Built-in voltage at the reference temperature of bottom component")
+                `MPRco(VBIRSTI        ,1.0        ,"V"        ,`VBIR_cliplow     ,inf              ,"Built-in voltage at the reference temperature of STI-edge component")
+                `MPRco(VBIRGAT        ,1.0        ,"V"        ,`VBIR_cliplow     ,inf              ,"Built-in voltage at the reference temperature of gate-edge component")
+                `MPRcc(PBOT           ,0.5        ,""         ,`P_cliplow        ,`P_cliphigh      ,"Grading coefficient of bottom component")
+                `MPRcc(PSTI           ,0.5        ,""         ,`P_cliplow        ,`P_cliphigh      ,"Grading coefficient of STI-edge component")
+                `MPRcc(PGAT           ,0.5        ,""         ,`P_cliplow        ,`P_cliphigh      ,"Grading coefficient of gate-edge component")
+                `MPRnb(PHIGBOT        ,1.16       ,"V"                                             ,"Zero-temperature bandgap voltage of bottom component")
+                `MPRnb(PHIGSTI        ,1.16       ,"V"                                             ,"Zero-temperature bandgap voltage of STI-edge component")
+                `MPRnb(PHIGGAT        ,1.16       ,"V"                                             ,"Zero-temperature bandgap voltage of gate-edge component")
+                `MPRco(IDSATRBOT      ,1.0e-12    ,"Am^-2"    ,`IDSATR_cliplow   ,inf              ,"Saturation current density at the reference temperature of bottom component")
+                `MPRco(IDSATRSTI      ,1.0e-18    ,"Am^-1"    ,`IDSATR_cliplow   ,inf              ,"Saturation current density at the reference temperature of STI-edge component")
+                `MPRco(IDSATRGAT      ,1.0e-18    ,"Am^-1"    ,`IDSATR_cliplow   ,inf              ,"Saturation current density at the reference temperature of gate-edge component")
+                `MPRco(CSRHBOT        ,1.0e2      ,"Am^-3"    ,`CSRH_cliplow     ,inf              ,"Shockley-Read-Hall prefactor of bottom component")
+                `MPRco(CSRHSTI        ,1.0e-4     ,"Am^-2"    ,`CSRH_cliplow     ,inf              ,"Shockley-Read-Hall prefactor of STI-edge component")
+                `MPRco(CSRHGAT        ,1.0e-4     ,"Am^-2"    ,`CSRH_cliplow     ,inf              ,"Shockley-Read-Hall prefactor of gate-edge component")
+                `MPRco(XJUNSTI        ,1.0e-7     ,"m"        ,`XJUN_cliplow     ,inf              ,"Junction depth of STI-edge component")
+                `MPRco(XJUNGAT        ,1.0e-7     ,"m"        ,`XJUN_cliplow     ,inf              ,"Junction depth of gate-edge component")
+                `MPRco(CTATBOT        ,1.0e2      ,"Am^-3"    ,`CTAT_cliplow     ,inf              ,"Trap-assisted tunneling prefactor of bottom component")
+                `MPRco(CTATSTI        ,1.0e-4     ,"Am^-2"    ,`CTAT_cliplow     ,inf              ,"Trap-assisted tunneling prefactor of STI-edge component")
+                `MPRco(CTATGAT        ,1.0e-4     ,"Am^-2"    ,`CTAT_cliplow     ,inf              ,"Trap-assisted tunneling prefactor of gate-edge component")
+                `MPRco(MEFFTATBOT     ,0.25       ,""         ,`MEFFTAT_cliplow  ,inf              ,"Effective mass (in units of m0) for trap-assisted tunneling of bottom component")
+                `MPRco(MEFFTATSTI     ,0.25       ,""         ,`MEFFTAT_cliplow  ,inf              ,"Effective mass (in units of m0) for trap-assisted tunneling of STI-edge component")
+                `MPRco(MEFFTATGAT     ,0.25       ,""         ,`MEFFTAT_cliplow  ,inf              ,"Effective mass (in units of m0) for trap-assisted tunneling of gate-edge component")
+                `MPRco(CBBTBOT        ,1.0e-12    ,"AV^-3"    ,`CBBT_cliplow     ,inf              ,"Band-to-band tunneling prefactor of bottom component")
+                `MPRco(CBBTSTI        ,1.0e-18    ,"AV^-3m"   ,`CBBT_cliplow     ,inf              ,"Band-to-band tunneling prefactor of STI-edge component")
+                `MPRco(CBBTGAT        ,1.0e-18    ,"AV^-3m"   ,`CBBT_cliplow     ,inf              ,"Band-to-band tunneling prefactor of gate-edge component")
+                `MPRnb(FBBTRBOT       ,1.0e9      ,"Vm^-1"                                         ,"Normalization field at the reference temperature for band-to-band tunneling of bottom component")
+                `MPRnb(FBBTRSTI       ,1.0e9      ,"Vm^-1"                                         ,"Normalization field at the reference temperature for band-to-band tunneling of STI-edge component")
+                `MPRnb(FBBTRGAT       ,1.0e9      ,"Vm^-1"                                         ,"Normalization field at the reference temperature for band-to-band tunneling of gate-edge component")
+                `MPRnb(STFBBTBOT      ,-1.0e-3    ,"K^-1"                                          ,"Temperature scaling parameter for band-to-band tunneling of bottom component")
+                `MPRnb(STFBBTSTI      ,-1.0e-3    ,"K^-1"                                          ,"Temperature scaling parameter for band-to-band tunneling of STI-edge component")
+                `MPRnb(STFBBTGAT      ,-1.0e-3    ,"K^-1"                                          ,"Temperature scaling parameter for band-to-band tunneling of gate-edge component")
+                `MPRco(VBRBOT         ,10.0       ,"V"        ,`VBR_cliplow      ,inf              ,"Breakdown voltage of bottom component")
+                `MPRco(VBRSTI         ,10.0       ,"V"        ,`VBR_cliplow      ,inf              ,"Breakdown voltage of STI-edge component")
+                `MPRco(VBRGAT         ,10.0       ,"V"        ,`VBR_cliplow      ,inf              ,"Breakdown voltage of gate-edge component")
+                `MPRco(PBRBOT         ,4.0        ,"V"        ,`PBR_cliplow      ,inf              ,"Breakdown onset tuning parameter of bottom component")
+                `MPRco(PBRSTI         ,4.0        ,"V"        ,`PBR_cliplow      ,inf              ,"Breakdown onset tuning parameter of STI-edge component")
+                `MPRco(PBRGAT         ,4.0        ,"V"        ,`PBR_cliplow      ,inf              ,"Breakdown onset tuning parameter of gate-edge component")
+        `else // JUNCAP_StandAlone
+                `MPRco(CJORBOT        ,1.0e-3     ,"Fm^-2"    ,`CJORBOT_cliplow  ,inf              ,"Zero-bias capacitance per unit-of-area of bottom component for source-bulk junction")
+                `MPRco(CJORSTI        ,1.0e-9     ,"Fm^-1"    ,`CJORSTI_cliplow  ,inf              ,"Zero-bias capacitance per unit-of-length of STI-edge component for source-bulk junction")
+                `MPRco(CJORGAT        ,1.0e-9     ,"Fm^-1"    ,`CJORGAT_cliplow  ,inf              ,"Zero-bias capacitance per unit-of-length of gate-edge component for source-bulk junction")
+                `MPRco(VBIRBOT        ,1.0        ,"V"        ,`VBIR_cliplow     ,inf              ,"Built-in voltage at the reference temperature of bottom component for source-bulk junction")
+                `MPRco(VBIRSTI        ,1.0        ,"V"        ,`VBIR_cliplow     ,inf              ,"Built-in voltage at the reference temperature of STI-edge component for source-bulk junction")
+                `MPRco(VBIRGAT        ,1.0        ,"V"        ,`VBIR_cliplow     ,inf              ,"Built-in voltage at the reference temperature of gate-edge component for source-bulk junction")
+                `MPRcc(PBOT           ,0.5        ,""         ,`P_cliplow        ,`P_cliphigh      ,"Grading coefficient of bottom component for source-bulk junction")
+                `MPRcc(PSTI           ,0.5        ,""         ,`P_cliplow        ,`P_cliphigh      ,"Grading coefficient of STI-edge component for source-bulk junction")
+                `MPRcc(PGAT           ,0.5        ,""         ,`P_cliplow        ,`P_cliphigh      ,"Grading coefficient of gate-edge component for source-bulk junction")
+                `MPRnb(PHIGBOT        ,1.16       ,"V"                                             ,"Zero-temperature bandgap voltage of bottom component for source-bulk junction")
+                `MPRnb(PHIGSTI        ,1.16       ,"V"                                             ,"Zero-temperature bandgap voltage of STI-edge component for source-bulk junction")
+                `MPRnb(PHIGGAT        ,1.16       ,"V"                                             ,"Zero-temperature bandgap voltage of gate-edge component for source-bulk junction")
+                `MPRco(IDSATRBOT      ,1.0e-12    ,"Am^-2"    ,`IDSATR_cliplow   ,inf              ,"Saturation current density at the reference temperature of bottom component for source-bulk junction")
+                `MPRco(IDSATRSTI      ,1.0e-18    ,"Am^-1"    ,`IDSATR_cliplow   ,inf              ,"Saturation current density at the reference temperature of STI-edge component for source-bulk junction")
+                `MPRco(IDSATRGAT      ,1.0e-18    ,"Am^-1"    ,`IDSATR_cliplow   ,inf              ,"Saturation current density at the reference temperature of gate-edge component for source-bulk junction")
+                `MPRco(CSRHBOT        ,1.0e2      ,"Am^-3"    ,`CSRH_cliplow     ,inf              ,"Shockley-Read-Hall prefactor of bottom component for source-bulk junction")
+                `MPRco(CSRHSTI        ,1.0e-4     ,"Am^-2"    ,`CSRH_cliplow     ,inf              ,"Shockley-Read-Hall prefactor of STI-edge component for source-bulk junction")
+                `MPRco(CSRHGAT        ,1.0e-4     ,"Am^-2"    ,`CSRH_cliplow     ,inf              ,"Shockley-Read-Hall prefactor of gate-edge component for source-bulk junction")
+                `MPRco(XJUNSTI        ,1.0e-7     ,"m"        ,`XJUN_cliplow     ,inf              ,"Junction depth of STI-edge component for source-bulk junction")
+                `MPRco(XJUNGAT        ,1.0e-7     ,"m"        ,`XJUN_cliplow     ,inf           ,"Junction depth of gate-edge component for source-bulk junction")
+                `MPRco(CTATBOT        ,1.0e2      ,"Am^-3"    ,`CTAT_cliplow     ,inf           ,"Trap-assisted tunneling prefactor of bottom component for source-bulk junction")
+                `MPRco(CTATSTI        ,1.0e-4     ,"Am^-2"    ,`CTAT_cliplow     ,inf           ,"Trap-assisted tunneling prefactor of STI-edge component for source-bulk junction")
+                `MPRco(CTATGAT        ,1.0e-4     ,"Am^-2"    ,`CTAT_cliplow     ,inf           ,"Trap-assisted tunneling prefactor of gate-edge component for source-bulk junction")
+                `MPRco(MEFFTATBOT     ,0.25       ,""         ,`MEFFTAT_cliplow  ,inf           ,"Effective mass (in units of m0) for trap-assisted tunneling of bottom component for source-bulk junction")
+                `MPRco(MEFFTATSTI     ,0.25       ,""         ,`MEFFTAT_cliplow  ,inf           ,"Effective mass (in units of m0) for trap-assisted tunneling of STI-edge component for source-bulk junction")
+                `MPRco(MEFFTATGAT     ,0.25       ,""         ,`MEFFTAT_cliplow  ,inf           ,"Effective mass (in units of m0) for trap-assisted tunneling of gate-edge component for source-bulk junction")
+                `MPRco(CBBTBOT        ,1.0e-12    ,"AV^-3"    ,`CBBT_cliplow     ,inf           ,"Band-to-band tunneling prefactor of bottom component for source-bulk junction")
+                `MPRco(CBBTSTI        ,1.0e-18    ,"AV^-3m"   ,`CBBT_cliplow     ,inf           ,"Band-to-band tunneling prefactor of STI-edge component for source-bulk junction")
+                `MPRco(CBBTGAT        ,1.0e-18    ,"AV^-3m"   ,`CBBT_cliplow     ,inf           ,"Band-to-band tunneling prefactor of gate-edge component for source-bulk junction")
+                `MPRnb(FBBTRBOT       ,1.0e9      ,"Vm^-1"                                      ,"Normalization field at the reference temperature for band-to-band tunneling of bottom component for source-bulk junction")
+                `MPRnb(FBBTRSTI       ,1.0e9      ,"Vm^-1"                                      ,"Normalization field at the reference temperature for band-to-band tunneling of STI-edge component for source-bulk junction")
+                `MPRnb(FBBTRGAT       ,1.0e9      ,"Vm^-1"                                      ,"Normalization field at the reference temperature for band-to-band tunneling of gate-edge component for source-bulk junction")
+                `MPRnb(STFBBTBOT      ,-1.0e-3    ,"K^-1"                                       ,"Temperature scaling parameter for band-to-band tunneling of bottom component for source-bulk junction")
+                `MPRnb(STFBBTSTI      ,-1.0e-3    ,"K^-1"                                       ,"Temperature scaling parameter for band-to-band tunneling of STI-edge component for source-bulk junction")
+                `MPRnb(STFBBTGAT      ,-1.0e-3    ,"K^-1"                                       ,"Temperature scaling parameter for band-to-band tunneling of gate-edge component for source-bulk junction")
+                `MPRco(VBRBOT         ,10.0       ,"V"        ,`VBR_cliplow      ,inf           ,"Breakdown voltage of bottom component for source-bulk junction")
+                `MPRco(VBRSTI         ,10.0       ,"V"        ,`VBR_cliplow      ,inf           ,"Breakdown voltage of STI-edge component for source-bulk junction")
+                `MPRco(VBRGAT         ,10.0       ,"V"        ,`VBR_cliplow      ,inf           ,"Breakdown voltage of gate-edge component for source-bulk junction")
+                `MPRco(PBRBOT         ,4.0        ,"V"        ,`PBR_cliplow      ,inf           ,"Breakdown onset tuning parameter of bottom component for source-bulk junction")
+                `MPRco(PBRSTI         ,4.0        ,"V"        ,`PBR_cliplow      ,inf           ,"Breakdown onset tuning parameter of STI-edge component for source-bulk junction")
+                `MPRco(PBRGAT         ,4.0        ,"V"        ,`PBR_cliplow      ,inf           ,"Breakdown onset tuning parameter of gate-edge component for source-bulk junction")
+        `endif // JUNCAP_StandAlone
+
+        // Parameters for drain-bulk junction
+        `ifdef JUNCAP_StandAlone
+                // do nothing
+        `else // JUNCAP_StandAlone
+                `MPRco(CJORBOTD       ,1.0e-3     ,"Fm^-2"    ,`CJORBOT_cliplow  ,inf           ,"Zero-bias capacitance per unit-of-area of bottom component for drain-bulk junction")
+                `MPRco(CJORSTID       ,1.0e-9     ,"Fm^-1"    ,`CJORSTI_cliplow  ,inf           ,"Zero-bias capacitance per unit-of-length of STI-edge component for drain-bulk junction")
+                `MPRco(CJORGATD       ,1.0e-9     ,"Fm^-1"    ,`CJORGAT_cliplow  ,inf           ,"Zero-bias capacitance per unit-of-length of gate-edge component for drain-bulk junction")
+                `MPRco(VBIRBOTD       ,1.0        ,"V"        ,`VBIR_cliplow     ,inf           ,"Built-in voltage at the reference temperature of bottom component for drain-bulk junction")
+                `MPRco(VBIRSTID       ,1.0        ,"V"        ,`VBIR_cliplow     ,inf           ,"Built-in voltage at the reference temperature of STI-edge component for drain-bulk junction")
+                `MPRco(VBIRGATD       ,1.0        ,"V"        ,`VBIR_cliplow     ,inf           ,"Built-in voltage at the reference temperature of gate-edge component for drain-bulk junction")
+                `MPRcc(PBOTD          ,0.5        ,""         ,`P_cliplow        ,`P_cliphigh   ,"Grading coefficient of bottom component for drain-bulk junction")
+                `MPRcc(PSTID          ,0.5        ,""         ,`P_cliplow        ,`P_cliphigh   ,"Grading coefficient of STI-edge component for drain-bulk junction")
+                `MPRcc(PGATD          ,0.5        ,""         ,`P_cliplow        ,`P_cliphigh   ,"Grading coefficient of gate-edge component for drain-bulk junction")
+                 `MPRnb(PHIGBOTD       ,1.16       ,"V"                                          ,"Zero-temperature bandgap voltage of bottom component for drain-bulk junction")
+                 `MPRnb(PHIGSTID       ,1.16       ,"V"                                          ,"Zero-temperature bandgap voltage of STI-edge component for drain-bulk junction")
+                `MPRnb(PHIGGATD       ,1.16       ,"V"                                          ,"Zero-temperature bandgap voltage of gate-edge component for drain-bulk junction")
+                `MPRco(IDSATRBOTD     ,1.0e-12    ,"Am^-2"    ,`IDSATR_cliplow   ,inf           ,"Saturation current density at the reference temperature of bottom component for drain-bulk junction")
+                `MPRco(IDSATRSTID     ,1.0e-18    ,"Am^-1"    ,`IDSATR_cliplow   ,inf           ,"Saturation current density at the reference temperature of STI-edge component for drain-bulk junction")
+                `MPRco(IDSATRGATD     ,1.0e-18    ,"Am^-1"    ,`IDSATR_cliplow   ,inf           ,"Saturation current density at the reference temperature of gate-edge component for drain-bulk junction")
+                `MPRco(CSRHBOTD       ,1.0e2      ,"Am^-3"    ,`CSRH_cliplow     ,inf           ,"Shockley-Read-Hall prefactor of bottom component for drain-bulk junction")
+                `MPRco(CSRHSTID       ,1.0e-4     ,"Am^-2"    ,`CSRH_cliplow     ,inf           ,"Shockley-Read-Hall prefactor of STI-edge component for drain-bulk junction")
+                `MPRco(CSRHGATD       ,1.0e-4     ,"Am^-2"    ,`CSRH_cliplow     ,inf           ,"Shockley-Read-Hall prefactor of gate-edge component for drain-bulk junction")
+                `MPRco(XJUNSTID       ,1.0e-7     ,"m"        ,`XJUN_cliplow     ,inf           ,"Junction depth of STI-edge component for drain-bulk junction")
+                `MPRco(XJUNGATD       ,1.0e-7     ,"m"        ,`XJUN_cliplow     ,inf           ,"Junction depth of gate-edge component for drain-bulk junction")
+                `MPRco(CTATBOTD       ,1.0e2      ,"Am^-3"    ,`CTAT_cliplow     ,inf           ,"Trap-assisted tunneling prefactor of bottom component for drain-bulk junction")
+                `MPRco(CTATSTID       ,1.0e-4     ,"Am^-2"    ,`CTAT_cliplow     ,inf           ,"Trap-assisted tunneling prefactor of STI-edge component for drain-bulk junction")
+                `MPRco(CTATGATD       ,1.0e-4     ,"Am^-2"    ,`CTAT_cliplow     ,inf           ,"Trap-assisted tunneling prefactor of gate-edge component for drain-bulk junction")
+                `MPRco(MEFFTATBOTD    ,0.25       ,""         ,`MEFFTAT_cliplow  ,inf           ,"Effective mass (in units of m0) for trap-assisted tunneling of bottom component for drain-bulk junction")
+                `MPRco(MEFFTATSTID    ,0.25       ,""         ,`MEFFTAT_cliplow  ,inf           ,"Effective mass (in units of m0) for trap-assisted tunneling of STI-edge component for drain-bulk junction")
+                `MPRco(MEFFTATGATD    ,0.25       ,""         ,`MEFFTAT_cliplow  ,inf           ,"Effective mass (in units of m0) for trap-assisted tunneling of gate-edge component for drain-bulk junction")
+                `MPRco(CBBTBOTD       ,1.0e-12    ,"AV^-3"    ,`CBBT_cliplow     ,inf           ,"Band-to-band tunneling prefactor of bottom component for drain-bulk junction")
+                `MPRco(CBBTSTID       ,1.0e-18    ,"AV^-3m"   ,`CBBT_cliplow     ,inf           ,"Band-to-band tunneling prefactor of STI-edge component for drain-bulk junction")
+                `MPRco(CBBTGATD       ,1.0e-18    ,"AV^-3m"   ,`CBBT_cliplow     ,inf           ,"Band-to-band tunneling prefactor of gate-edge component for drain-bulk junction")
+                `MPRnb(FBBTRBOTD      ,1.0e9      ,"Vm^-1"                                      ,"Normalization field at the reference temperature for band-to-band tunneling of bottom component for drain-bulk junction")
+                `MPRnb(FBBTRSTID      ,1.0e9      ,"Vm^-1"                                      ,"Normalization field at the reference temperature for band-to-band tunneling of STI-edge component for drain-bulk junction")
+                `MPRnb(FBBTRGATD      ,1.0e9      ,"Vm^-1"                                      ,"Normalization field at the reference temperature for band-to-band tunneling of gate-edge component for drain-bulk junction")
+                `MPRnb(STFBBTBOTD     ,-1.0e-3    ,"K^-1"                                       ,"Temperature scaling parameter for band-to-band tunneling of bottom component for drain-bulk junction")
+                `MPRnb(STFBBTSTID     ,-1.0e-3    ,"K^-1"                                       ,"Temperature scaling parameter for band-to-band tunneling of STI-edge component for drain-bulk junction")
+                `MPRnb(STFBBTGATD     ,-1.0e-3    ,"K^-1"                                       ,"Temperature scaling parameter for band-to-band tunneling of gate-edge component for drain-bulk junction")
+                `MPRco(VBRBOTD        ,10.0       ,"V"        ,`VBR_cliplow      ,inf           ,"Breakdown voltage of bottom component for drain-bulk junction")
+                `MPRco(VBRSTID        ,10.0       ,"V"        ,`VBR_cliplow      ,inf           ,"Breakdown voltage of STI-edge component for drain-bulk junction")
+                `MPRco(VBRGATD        ,10.0       ,"V"        ,`VBR_cliplow      ,inf           ,"Breakdown voltage of gate-edge component for drain-bulk junction")
+                `MPRco(PBRBOTD        ,4.0        ,"V"        ,`PBR_cliplow      ,inf           ,"Breakdown onset tuning parameter of bottom component for drain-bulk junction")
+                `MPRco(PBRSTID        ,4.0        ,"V"        ,`PBR_cliplow      ,inf           ,"Breakdown onset tuning parameter of STI-edge component for drain-bulk junction")
+                `MPRco(PBRGATD        ,4.0        ,"V"        ,`PBR_cliplow      ,inf           ,"Breakdown onset tuning parameter of gate-edge component for drain-bulk junction")
+        `endif // JUNCAP_StandAlone
+
+        // JUNCAP2-express parameters
+                `MPRcc(SWJUNEXP       ,0.0        ,""         ,0.0               ,1.0           ,"Flag for JUNCAP-express; 0=full model, 1=express model")
+        `ifdef JUNCAP_StandAlone
+                `MPRco(VJUNREF        ,2.5        ,"V"        ,`VJUNREF_cliplow  ,inf           ,"Typical maximum junction voltage; usually about 2*VSUP")
+                `MPRco(FJUNQ          ,0.03       ,""         ,`FJUNQ_cliplow    ,inf           ,"Fraction below which junction capacitance components are considered negligible")
+                `else // JUNCAP_StandAlone
+                `MPRco(VJUNREF        ,2.5        ,"V"        ,`VJUNREF_cliplow  ,inf           ,"Typical maximum source-bulk junction voltage; usually about 2*VSUP")
+                `MPRco(FJUNQ          ,0.03       ,""         ,`FJUNQ_cliplow    ,inf           ,"Fraction below which source-bulk junction capacitance components are considered negligible")
+                `MPRco(VJUNREFD       ,2.5        ,"V"        ,`VJUNREF_cliplow  ,inf           ,"Typical maximum drain-bulk junction voltage; usually about 2*VSUP")
+                `MPRco(FJUNQD         ,0.03       ,""         ,`FJUNQ_cliplow    ,inf           ,"Fraction below which drain-bulk junction capacitance components are considered negligible")
+        `endif // JUNCAP_StandAlone
diff --git a/ihp-sg13g2/libs.tech/xyce/adms/JUNCAP200_varlist1.include b/ihp-sg13g2/libs.tech/xyce/adms/JUNCAP200_varlist1.include
new file mode 100644
index 00000000..415e01a8
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/adms/JUNCAP200_varlist1.include
@@ -0,0 +1,106 @@
+//======================================================================================
+//======================================================================================
+// Filename: JUNCAP200_varlist1.include
+//======================================================================================
+//======================================================================================
+//
+//  (c) Copyright notice
+//
+//  Copyright 2004-2017 NXP Semiconductors, 2015-2017 Commissariat a l’energie atomique
+//  et aux energies alternatives (CEA) and 2012-2015 Delft University of Technology
+//  Licensed under the Educational Community License, Version 2.0 (the "License"); you
+//  may not use this file except in compliance with the License. You may obtain a copy
+//  of the License at
+//  http://opensource.org/licenses/ECL-2.0
+//  Unless required by applicable law or agreed to in writing, software distributed under
+//  the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF
+//  ANY KIND, either express or implied. See the License for the specific language
+//  governing permissions and limitations under the License.
+//
+//
+//  Version: 200.5.0, August 2016
+//
+//======================================================================================
+//======================================================================================
+//
+// Further information can be found in the file releasenotesPSP103.txt
+//
+
+        // declaration of clipped parameters
+        real TRJ_i, IMAX_i, FREV_i;
+        real CJORBOT_i, CJORSTI_i, CJORGAT_i, VBIRBOT_i, VBIRSTI_i, VBIRGAT_i;
+        real PBOT_i, PSTI_i, PGAT_i, PHIGBOT_i, PHIGSTI_i, PHIGGAT_i;
+        real IDSATRBOT_i, IDSATRSTI_i, IDSATRGAT_i, XJUNSTI_i, XJUNGAT_i;
+        real CSRHBOT_i, CSRHSTI_i, CSRHGAT_i, CTATBOT_i, CTATSTI_i, CTATGAT_i;
+        real MEFFTATBOT_i, MEFFTATSTI_i, MEFFTATGAT_i;
+        real CBBTBOT_i, CBBTSTI_i, CBBTGAT_i, FBBTRBOT_i, FBBTRSTI_i, FBBTRGAT_i;
+        real STFBBTBOT_i, STFBBTSTI_i, STFBBTGAT_i;
+        real VBRBOT_i, VBRSTI_i, VBRGAT_i, PBRBOT_i, PBRSTI_i, PBRGAT_i;
+
+        real SWJUNEXP_i, VJUNREF_i, FJUNQ_i;
+
+        // declaration of variables calculated outside macro "juncapfunction", voltage-independent part
+        real tkr, tkd, auxt, KBOL_over_QELE, phitr, phitrinv, phitd, phitdinv;
+        real perfc, berfc, cerfc;
+        real deltaphigr, deltaphigd, pmax;
+
+        real phigrbot, phigrsti, phigrgat, phigdbot, phigdsti, phigdgat;
+        real ftdbot, ftdsti, ftdgat, idsatbot, idsatsti, idsatgat;
+        real ubibot, ubisti, ubigat, vbibot, vbisti, vbigat;
+        real vbibot2, vbisti2, vbigat2, pbot2, psti2, pgat2, vbibot2r, vbisti2r, vbigat2r;
+        real vbiinvbot, vbiinvsti, vbiinvgat;
+        real one_minus_PBOT, one_minus_PSTI, one_minus_PGAT;
+        real one_over_one_minus_PBOT, one_over_one_minus_PSTI, one_over_one_minus_PGAT;
+        real cjobot, cjosti, cjogat;
+        real qprefbot, qprefsti, qprefgat, qpref2bot, qpref2sti, qpref2gat;
+        real wdepnulrbot, wdepnulrsti, wdepnulrgat, wdepnulrinvbot, wdepnulrinvsti, wdepnulrinvgat;
+        real VBIRBOTinv, VBIRSTIinv, VBIRGATinv;
+        real deltaEbot, deltaEsti, deltaEgat, atatbot, atatsti, atatgat;
+        real btatpartbot, btatpartsti, btatpartgat;
+        real fbbtbot, fbbtsti, fbbtgat;
+        real alphaav, fstopbot, fstopsti, fstopgat, VBRinvbot, VBRinvsti, VBRinvgat;
+        real slopebot, slopesti, slopegat;
+        real vmaxbot, vmaxsti, vmaxgat;
+
+        // JUNCAP-Express variables
+        real I1, I2, I3, I4, I5;
+        real I1_cor, I2_cor, I3_cor, I4_cor, I5_cor;
+        real V1, V2, V3, V4, V5;
+        real alphaje, m0_rev, mcor_rev;
+        real tt0, tt1, tt2, tm0, tm1;
+        real FRACNA, FRACNB, FRACI;
+        real zfrac;
+        real ijunfor1, ijunfor2, ijunrev;
+
+        `ifdef JUNCAP_StandAlone
+        // do nothing
+        `else // JUNCAP_StandAlone
+        real CJORBOTD_i, CJORSTID_i, CJORGATD_i, VBIRBOTD_i, VBIRSTID_i, VBIRGATD_i;
+        real PBOTD_i, PSTID_i, PGATD_i, PHIGBOTD_i, PHIGSTID_i, PHIGGATD_i;
+        real IDSATRBOTD_i, IDSATRSTID_i, IDSATRGATD_i, XJUNSTID_i, XJUNGATD_i;
+        real CSRHBOTD_i, CSRHSTID_i, CSRHGATD_i, CTATBOTD_i, CTATSTID_i, CTATGATD_i;
+        real MEFFTATBOTD_i, MEFFTATSTID_i, MEFFTATGATD_i;
+        real CBBTBOTD_i, CBBTSTID_i, CBBTGATD_i, FBBTRBOTD_i, FBBTRSTID_i, FBBTRGATD_i;
+        real STFBBTBOTD_i, STFBBTSTID_i, STFBBTGATD_i;
+        real VBRBOTD_i, VBRSTID_i, VBRGATD_i, PBRBOTD_i, PBRSTID_i, PBRGATD_i;
+
+        real VJUNREFD_i, FJUNQD_i;
+
+        real phigrbot_d, phigrsti_d, phigrgat_d, phigdbot_d, phigdsti_d, phigdgat_d;
+        real ftdbot_d, ftdsti_d, ftdgat_d, idsatbot_d, idsatsti_d, idsatgat_d;
+        real ubibot_d, ubisti_d, ubigat_d, vbibot_d, vbisti_d, vbigat_d;
+        real vbiinvbot_d, vbiinvsti_d, vbiinvgat_d;
+        real one_minus_PBOT_d, one_minus_PSTI_d, one_minus_PGAT_d;
+        real one_over_one_minus_PBOT_d, one_over_one_minus_PSTI_d, one_over_one_minus_PGAT_d;
+        real cjobot_d, cjosti_d, cjogat_d;
+        real qprefbot_d, qprefsti_d, qprefgat_d, qpref2bot_d, qpref2sti_d, qpref2gat_d;
+        real wdepnulrbot_d, wdepnulrsti_d, wdepnulrgat_d, wdepnulrinvbot_d, wdepnulrinvsti_d, wdepnulrinvgat_d;
+        real VBIRBOTinv_d, VBIRSTIinv_d, VBIRGATinv_d;
+        real deltaEbot_d, deltaEsti_d, deltaEgat_d, atatbot_d, atatsti_d, atatgat_d;
+        real btatpartbot_d, btatpartsti_d, btatpartgat_d;
+        real fbbtbot_d, fbbtsti_d, fbbtgat_d;
+        real fstopbot_d, fstopsti_d, fstopgat_d, VBRinvbot_d, VBRinvsti_d, VBRinvgat_d;
+        real slopebot_d, slopesti_d, slopegat_d;
+        `endif // JUNCAP_StandAlone
+
+        `LocalGlobalVars
diff --git a/ihp-sg13g2/libs.tech/xyce/adms/JUNCAP200_varlist2.include b/ihp-sg13g2/libs.tech/xyce/adms/JUNCAP200_varlist2.include
new file mode 100644
index 00000000..aa192739
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/adms/JUNCAP200_varlist2.include
@@ -0,0 +1,63 @@
+//======================================================================================
+//======================================================================================
+// Filename: JUNCAP200_varlist2.include
+//======================================================================================
+//======================================================================================
+//
+//  (c) Copyright notice
+//
+//  Copyright 2004-2017 NXP Semiconductors, 2015-2017 Commissariat a l’energie atomique
+//  et aux energies alternatives (CEA) and 2012-2015 Delft University of Technology
+//  Licensed under the Educational Community License, Version 2.0 (the "License"); you
+//  may not use this file except in compliance with the License. You may obtain a copy
+//  of the License at
+//  http://opensource.org/licenses/ECL-2.0
+//  Unless required by applicable law or agreed to in writing, software distributed under
+//  the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF
+//  ANY KIND, either express or implied. See the License for the specific language
+//  governing permissions and limitations under the License.
+//
+//
+//  Version: 200.5.0, August 2016
+//
+//======================================================================================
+//======================================================================================
+//
+// Further information can be found in the file releasenotesPSP103.txt
+//
+    //================================================================
+    // Variables that are different for source and drain side junction
+    // and have a scope larger than a single macro-call
+    //================================================================
+
+        `ifdef JUNCAP_StandAlone
+        real AB_i, LS_i, LG_i;
+        real zflagbot, zflagsti, zflaggat;
+        real VMAX, exp_VMAX_over_phitd, vbimin, vch, vfmin, vbbtlim;
+
+        // JUNCAP-express variables
+        real xhighf1, expxhf1, xhighf2, expxhf2, xhighr, expxhr;
+
+        // JUNCAP2-express intermediate parameters
+        real ISATFOR1, MFOR1, ISATFOR2, MFOR2, ISATREV, MREV, m0flag;
+        `else // JUNCAP_StandAlone
+        real ABSOURCE_i, LSSOURCE_i, LGSOURCE_i, AS_i, PS_i;
+        real zflagbot_s, zflagsti_s, zflaggat_s;
+        real VMAX_s, exp_VMAX_over_phitd_s, vbimin_s, vch_s, vfmin_s, vbbtlim_s;
+
+        // JUNCAP-express variables
+        real xhighf1_s, expxhf1_s, xhighf2_s, expxhf2_s, xhighr_s, expxhr_s, m0flag_s;
+
+        // JUNCAP2-express intermediate parameters
+        real ISATFOR1_s, MFOR1_s, ISATFOR2_s, MFOR2_s, ISATREV_s, MREV_s;
+
+        real ABDRAIN_i, LSDRAIN_i, LGDRAIN_i, AD_i, PD_i;
+        real zflagbot_d, zflagsti_d, zflaggat_d;
+        real VMAX_d, exp_VMAX_over_phitd_d, vbimin_d, vch_d, vfmin_d, vbbtlim_d;
+
+        // JUNCAP-express variables
+        real xhighf1_d, expxhf1_d, xhighf2_d, expxhf2_d, xhighr_d, expxhr_d, m0flag_d;
+
+        // JUNCAP2-express intermediate parameters
+        real ISATFOR1_d, MFOR1_d, ISATFOR2_d, MFOR2_d, ISATREV_d, MREV_d;
+        `endif // JUNCAP_StandAlone
diff --git a/ihp-sg13g2/libs.tech/xyce/adms/PSP103_ChargesNQS.include b/ihp-sg13g2/libs.tech/xyce/adms/PSP103_ChargesNQS.include
new file mode 100644
index 00000000..205676be
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/adms/PSP103_ChargesNQS.include
@@ -0,0 +1,316 @@
+//======================================================================================
+//======================================================================================
+// Filename: PSP103_ChargesNQS.include
+//======================================================================================
+//======================================================================================
+//
+//  (c) Copyright notice
+//
+//  Copyright 2004-2017 NXP Semiconductors, 2015-2017 Commissariat a l’energie atomique
+//  et aux energies alternatives (CEA), 2012-2015 Delft University of Technology and 
+//  2004-2011 Arizona State University Licensed under the Educational Community License,
+//  Version 2.0 (the "License"); you may not use this file except in compliance with the
+//  License. You may obtain a copy of the License at
+//  http://opensource.org/licenses/ECL-2.0
+//  Unless required by applicable law or agreed to in writing, software distributed under
+//  the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF
+//  ANY KIND, either express or implied. See the License for the specific language
+//  governing permissions and limitations under the License.
+//
+//
+//  Version: 103.6.0 (PSP), 200.5.0 (JUNCAP), December 2017
+//
+//======================================================================================
+//======================================================================================
+//
+// Further information can be found in the file releasenotesPSP103.txt
+//
+
+                //  --------------------------------------------------------------------------------------------------------------
+                //  Calculate NQS-charge contributions
+                //  --------------------------------------------------------------------------------------------------------------
+
+                        Qp1          =  vnorm * V(SPLINE1);
+                        Qp2          =  vnorm * V(SPLINE2);
+                        Qp3          =  vnorm * V(SPLINE3);
+                        Qp4          =  vnorm * V(SPLINE4);
+                        Qp5          =  vnorm * V(SPLINE5);
+                        Qp6          =  vnorm * V(SPLINE6);
+                        Qp7          =  vnorm * V(SPLINE7);
+                        Qp8          =  vnorm * V(SPLINE8);
+                        Qp9          =  vnorm * V(SPLINE9);
+
+                        Tnorm        =  0.0;
+
+                        if (SWNQS_i != 0) begin
+                                // Dimension and mobility information is included in Tnorm
+                                Tnorm        =  MUNQS_i * phit1 * BET_i / (COX_qm * Gmob_dL_ac);
+                                thesat2      =  thesat1_ac * thesat1_ac * phit1 * phit1;
+
+                                if (SWNQS_i == 1) begin
+                                        dQy          =  QpN - Qp0;
+                                        d2Qy         =  6.0 * (Qp0 + QpN) - 12.0 * Qp1;
+                                end else if (SWNQS_i == 2) begin
+                                        dQy          =  (-7.0 * Qp0 - 3.0 * Qp1 + 12.0 * Qp2 - 2.0 * QpN) / 5.0;
+                                        d2Qy         = -18.0 / 5.0 * (-4.0 * Qp0 + 9.0 * Qp1 - 6.0 * Qp2 + QpN);
+                                end else if (SWNQS_i == 3) begin
+                                        dQy          =  (-13.0 * Qp0 - 6.0 * Qp1 + 24.0 * Qp2 - 6.0 * Qp3 + QpN) / 7.0;
+                                        d2Qy         =  (180.0 * Qp0 - 408.0 * Qp1 + 288.0 * Qp2 - 72.0 * Qp3 + 12.0 * QpN) / 7.0;
+                                end else if (SWNQS_i == 5) begin
+                                        dQy          =  (-181.0 * Qp0 - 84.0 * Qp1 + 24.0 * Qp4 - 6.0 * Qp5 - 90.0 * Qp3 + QpN
+                                   + 336.0 * Qp2) / 65.0;
+                                        d2Qy         =  (432.0 * Qp4 - 108.0 * Qp5 - 1620.0 * Qp3 + 18.0 * QpN + 3762.0 * Qp0
+                                   - 8532.0 * Qp1 + 6048.0 * Qp2) / 65.0;
+                                end else if (SWNQS_i == 9) begin
+                                        dQy          =  (1680.0 * Qp6 + 23400.0 * Qp4 + 5.0 * QpN - 87330.0 * Qp3 + 120.0 * Qp8
+                                   - 450.0 * Qp7 - 81480.0 * Qp1 + 325920.0 * Qp2
+                                   -175565.0 * Qp0 - 30.0 * Qp9) / 37829.0 - 30.0 / 181.0 * Qp5;
+                                        d2Qy         =  (-13500.0 * Qp7 + 702000.0 * Qp4 - 2619900 * Qp3 - 13793100.0 * Qp1
+                                   + 9777600.0 * Qp2 + 6081750.0 * Qp0 + 150.0 * QpN + 3600.0 * Qp8
+                                   - 900.0 * Qp9 + 50400.0 * Qp6) / 37829.0 - 900.0 / 181.0 * Qp5;
+                                end else begin
+                                        dQy          =  0.0;
+                                        d2Qy         =  0.0;
+                                end
+                                `fq(Qp1, xg_ac, dQy, d2Qy, fk1)
+                        end else begin
+                            thesat2      =  0.0;
+                        end
+
+                        if (SWNQS_i >= 2) begin
+                                if (SWNQS_i == 2) begin
+                                        dQy          =  (2.0 * Qp0 - 12.0 * Qp1 + 3.0 * Qp2 + 7.0 * QpN) / 5.0;
+                                        d2Qy         =  -18.0 / 5.0 * (-4.0 * QpN + 9.0 * Qp2 - 6.0 * Qp1 + Qp0);
+                                end else if (SWNQS_i == 3) begin
+                                        dQy          =  0.5 * Qp0 - 3.0 * Qp1 + 3.0 * Qp3 - 0.5 * QpN;
+                                        d2Qy         =  (-48.0 * Qp0 + 288.0 * Qp1 - 480.0 * Qp2 + 288.0 * Qp3 - 48.0 * QpN) / 7.0;
+                                end else if (SWNQS_i == 5) begin
+                                        dQy          =  (-291.0 * Qp1 - 6.0 * Qp2 - 84.0 * Qp4 + 21.0 * Qp5) / 65.0
+                                   + (630.0 * Qp3 - 7.0 * QpN + 97.0 * Qp0) / 130.0;
+                                        d2Qy         =  (-1728.0 * Qp4 + 432.0 * Qp5 + 6480.0 * Qp3 - 72.0 * QpN - 1008.0 * Qp0
+                                   + 6048.0 * Qp1 - 10152.0 * Qp2) / 65.0;
+                                end else if (SWNQS_i == 9) begin
+                                        dQy          =  (-5880.0 * Qp6 - 81900.0 * Qp4 + 305655.0 * Qp3 - 420.0 * Qp8
+                                   + 105.0 * Qp9 - 282255.0 * Qp1 + 1575.0 * Qp7 - 5850.0 * Qp2) / 37829.0
+                                   + 105.0 / 181.0 * Qp5 + (94085.0 * Qp0 - 35.0 * QpN) / 75658.0;
+                                        d2Qy         =  (9777600.0 * Qp1 + 54000.0 * Qp7 - 2808000.0 * Qp4 + 10479600.0 * Qp3
+                                   - 16413000.0 * Qp2 - 1629600.0 * Qp0 - 600.0 * QpN - 14400.0 * Qp8
+                                   + 3600.0 * Qp9 - 201600.0 * Qp6) / 37829.0 + 3600.0 * Qp5 / 181.0;
+                                end else begin
+                                        dQy          =  0.0;
+                                        d2Qy         =  0.0;
+                                end
+                                `fq(Qp2, xg_ac, dQy, d2Qy, fk2)
+                        end
+
+                        if (SWNQS_i >= 3) begin
+                                if (SWNQS_i == 3) begin
+                                        dQy          =  (13.0 * QpN + 6.0 * Qp3 - 24.0 * Qp2 + 6.0 * Qp1 - Qp0) / 7.0;
+                                        d2Qy         =  (180.0 * QpN - 408.0 * Qp3 + 288.0 * Qp2 - 72.0 * Qp1 + 12.0 * Qp0) / 7.0;
+                                end else if (SWNQS_i == 5) begin
+                                        dQy          =  (QpN - 6.0 * Qp5 + 24.0 * Qp4 - 24.0 * Qp2 + 6.0 * Qp1 - Qp0) / 5.0;
+                                        d2Qy         =  (1296.0 * (Qp4 + Qp2) - 324.0 * (Qp5 + Qp1) - 2052.0 * Qp3
+                                   + 54.0 * (QpN + Qp0)) / 13.0;
+                                end else if (SWNQS_i == 9) begin
+                                        dQy          =  (21840.0 * Qp6 + 304200.0 * Qp4 + 65.0 * QpN - 420.0 * Qp3 + 1560.0 * Qp8
+                                   - 12605.0 * Qp0 - 390.0 * Qp9 + 75630.0 * Qp1 - 5850.0 * Qp7
+                                   - 302520.0 * Qp2) / 37829.0 - 390.0 / 181.0 * Qp5;
+                                        d2Qy         =  (-2619900.0 * Qp1 - 202500.0 * Qp7 + 10530000.0 * Qp4 - 16601100.0 * Qp3
+                                   + 10479600.0 * Qp2 + 436650.0 * Qp0 + 2250.0 * QpN + 54000.0 * Qp8
+                                   - 13500.0 * Qp9 + 756000.0 * Qp6) / 37829.0 - 13500.0 * Qp5 / 181.0;
+                                end else begin
+                                        dQy          =  0.0;
+                                        d2Qy         =  0.0;
+                                end
+                                `fq(Qp3, xg_ac, dQy, d2Qy, fk3)
+                        end
+
+                        if (SWNQS_i >= 4) begin
+                                if (SWNQS_i == 5) begin
+                                        dQy          =  (-630.0 * Qp3 + 12.0 * Qp4 + 582.0 * Qp5 - 97.0 * QpN + 7.0 * Qp0
+                                   - 42.0 * Qp1 + 168.0 * Qp2) / 130.0;
+                                        d2Qy         =  (-10152.0 * Qp4 + 6048.0 * Qp5 + 6480.0 * Qp3 - 1008.0 * QpN
+                                   - 72.0 * Qp0 + 432.0 * Qp1 - 1728.0 * Qp2) / 65.0;
+                                        end
+                                else if (SWNQS_i == 9) begin
+                                        dQy          =  (-81480.0 * Qp6 - 30.0 * Qp4 - 303975.0 * Qp3 - 5820.0 * Qp8
+                                   + 1455.0 * Qp9 - 20265.0 * Qp1 + 21825.0 * Qp7 + 81060.0 * Qp2) / 37829.0
+                                   - 485.0 / 75658.0 * QpN + 1455.0 * Qp5 / 181.0 + 6755.0 * Qp0 / 75658.0;
+                                        d2Qy         =  (702000.0 * Qp1 + 756000.0 * Qp7 - 16614600.0 * Qp4 + 10530000.0 * Qp3
+                                   - 2808000.0 * Qp2 - 117000.0 * Qp0 - 8400.0 * QpN - 201600.0 * Qp8
+                                   + 50400.0 * Qp9 - 2822400.0 * Qp6) / 37829.0 + 50400.0 * Qp5 / 181.0;
+                                end else begin
+                                        dQy          =  0.0;
+                                        d2Qy         =  0.0;
+                                end
+                                `fq(Qp4, xg_ac, dQy, d2Qy, fk4)
+                        end
+
+                        if (SWNQS_i >= 5) begin
+                                if (SWNQS_i == 5) begin
+                                        dQy          =  (-336.0 * Qp4 + 84.0 * Qp5 + 90.0 * Qp3 + 181.0 * QpN - Qp0 + 6.0 * Qp1
+                                   - 24.0 * Qp2) / 65.0;
+                                        d2Qy         =  (18.0 * Qp0 + 3762.0 * QpN + 6048.0 * Qp4 + 432.0 * Qp2 - 1620.0 * Qp3
+                                   - 108.0 * Qp1 - 8532.0 * Qp5) / 65.0;
+                                end else if (SWNQS_i == 9) begin
+                                        dQy          =  (1680.0 * (Qp6 - Qp4) + 5.0 * (QpN - Qp0) + 450.0 * (Qp3 - Qp7)
+                                   + 120.0 * (Qp8 - Qp2) - 30.0 * (Qp9 - Qp1)) / 209.0;
+                                        d2Qy         =  (-900.0 * (Qp1 + Qp9) - 13500.0 * (Qp7 + Qp3) - 79500.0 * Qp5
+                                   + 50400.0 * (Qp4 + Qp6) + 3600.0 * (Qp2 + Qp8) + 150.0 * (Qp0 + QpN)) / 181.0;
+                                end else begin
+                                        dQy          =  0.0;
+                                        d2Qy         =  0.0;
+                                end
+                                `fq(Qp5, xg_ac, dQy, d2Qy, fk5)
+                        end
+
+                        if (SWNQS_i >= 6) begin
+                                if (SWNQS_i == 9) begin
+                                        dQy          =  (30.0 * Qp6 + 81480.0 * Qp4 - 21825.0 * Qp3 - 81060.0 * Qp8 + 20265.0 * Qp9
+                                   - 1455.0 * Qp1 + 303975.0 * Qp7 + 5820.0 * Qp2) / 37829.0
+                                   -(6755.0 * QpN - 485.0 * Qp0) / 75658.0 - 1455.0 / 181.0 * Qp5;
+                                        d2Qy         =  (50400.0 * Qp1 + 10530000.0 * Qp7 - 2822400.0 * Qp4 + 756000.0 * Qp3
+                                   - 201600.0 * Qp2 - 8400.0 * Qp0 - 117000.0 * QpN - 2808000.0 * Qp8
+                                   + 702000.0 * Qp9 - 16614600.0 * Qp6) / 37829.0 + 50400.0 * Qp5 / 181.0;
+                                end else begin
+                                        dQy          =  0.0;
+                                        d2Qy         =  0.0;
+                                end
+                                `fq(Qp6, xg_ac, dQy, d2Qy, fk6)
+                        end
+
+                        if (SWNQS_i >= 7) begin
+                                if (SWNQS_i == 9) begin
+                                        dQy          =  (-304200.0 * Qp6 - 21840.0 * Qp4 + 12605.0 * QpN + 5850.0 * Qp3
+                                   + 302520.0 * Qp8 - 65.0 * Qp0 - 75630.0 * Qp9 + 390.0 * Qp1 + 420.0 * Qp7
+                                   - 1560.0 * Qp2) / 37829.0 + 390.0 / 181.0 * Qp5;
+                                        d2Qy         =  (-13500.0 * Qp1 - 16601100.0 * Qp7 + 756000.0 * Qp4 - 202500.0 * Qp3
+                                   + 54000.0 * Qp2 + 2250.0 * Qp0 + 436650.0 * QpN + 10479600.0 * Qp8
+                                   - 2619900.0 * Qp9 + 10530000.0 * Qp6) / 37829.0 - 13500.0 * Qp5 / 181.0;
+                                end else begin
+                                        dQy          =  0.0;
+                                        d2Qy         =  0.0;
+                                end
+                                `fq(Qp7, xg_ac, dQy, d2Qy, fk7)
+                        end
+
+                        if (SWNQS_i >= 8) begin
+                                if (SWNQS_i == 9) begin
+                                        dQy          =  (81900.0 * Qp6 + 5880.0 * Qp4 - 1575.0 * Qp3 + 5850.0 * Qp8 + 282255.0 * Qp9
+                                   - 105.0 * Qp1 - 305655.0 * Qp7 + 420.0 * Qp2) / 37829.0 + (35.0 * Qp0
+                                   - 94085.0 * QpN) / 75658.0 - 105.0 / 181.0 * Qp5;
+                                        d2Qy         =  (3600.0 * Qp1 + 10479600.0 * Qp7 - 201600.0 * Qp4 + 54000.0 * Qp3
+                                   - 14400.0 * Qp2 - 600.0 * Qp0 - 1629600.0 * QpN - 16413000.0 * Qp8
+                                   + 9777600.0 * Qp9 - 2808000.0 * Qp6) / 37829.0 + 3600.0 * Qp5 / 181.0;
+                                end else begin
+                                        dQy          =  0.0;
+                                        d2Qy         =  0.0;
+                                end
+                                `fq(Qp8, xg_ac, dQy, d2Qy, fk8)
+                        end
+
+                        if (SWNQS_i >= 9) begin
+                                if (SWNQS_i == 9) begin
+                                        dQy          =  (-23400.0 * Qp6 - 1680.0 * Qp4 + 175565.0 * QpN + 450.0 * Qp3
+                                   - 325920.0 * Qp8 - 5.0 * Qp0 + 81480.0 * Qp9 + 30.0 * Qp1
+                                   + 87330.0 * Qp7 - 120.0 * Qp2) / 37829.0 + 30.0 * Qp5 / 181.0;
+                                        d2Qy         =  (-900.0 * Qp1 - 2619900.0 * Qp7 + 50400.0 * Qp4 - 13500.0 * Qp3
+                                   + 3600.0 * Qp2 + 150.0 * Qp0 + 6081750.0 * QpN + 9777600.0 * Qp8
+                                   - 13793100.0 * Qp9 + 702000.0 * Qp6) / 37829.0 - 900.0 * Qp5 / 181.0;
+                        end else begin
+                                        dQy          =  0.0;
+                                        d2Qy         =  0.0;
+                                end
+                                `fq(Qp9, xg_ac, dQy, d2Qy, fk9)
+                        end
+
+                        //--------------------------------------------------------------------
+
+                        //      Terminal charges for NQS
+                        QS_NQS       =  0.0;
+                        QD_NQS       =  0.0;
+                        QG_NQS       =  0.0;
+                        if (SWNQS_i != 0) begin
+                                if (SWNQS_i == 1) begin
+                                        QS_NQS       =  (17.0 * Qp0 + 30.0 * Qp1 + QpN) / 96.0;
+                                        QD_NQS       =  (Qp0 + 30.0 * Qp1 + 17.0 * QpN) / 96.0;
+                                        `QiToPhi(Qp1,xg_ac, temp1)
+                                        QG_NQS       =  xg_ac - (x_sp + 4.0 * temp1 + x_dp) * `oneSixth;
+                                end else if (SWNQS_i == 2) begin
+                                        QS_NQS       =  (11.0 * Qp0 + 24.0 * Qp1 + 9.0 * Qp2 + QpN) / 90.0;
+                                        QD_NQS       =  (11.0 * QpN + 24.0 * Qp2 + 9.0 * Qp1 + Qp0) / 90.0;
+                                        `QiToPhi(Qp1, xg_ac, temp1)
+                                        `QiToPhi(Qp2, xg_ac, temp2)
+                                        QG_NQS       =  xg_ac - (x_sp + 3.0 * (temp1 + temp2) + x_dp) * 0.125;
+                                end else if (SWNQS_i == 3) begin
+                                        QS_NQS       =  (251.0 * Qp0 + 594.0 * Qp1 + 312.0 * Qp2 + 174.0 * Qp3 + 13.0 * QpN) / 2688.0;
+                                        QD_NQS       =  (251.0 * QpN + 594.0 * Qp3 + 312.0 * Qp2 + 174.0 * Qp1 + 13.0 * Qp0) / 2688.0;
+                                        `QiToPhi(Qp1, xg_ac, temp1)
+                                        `QiToPhi(Qp2, xg_ac, temp2)
+                                        `QiToPhi(Qp3, xg_ac, temp3)
+                                        QG_NQS       =  xg_ac - (x_sp + 4.0 * temp1 + 2.0 * temp2 + 4.0 * temp3 + x_dp) / 12.0;
+                                end else if (SWNQS_i == 5) begin
+                                        QS_NQS       =  (1187.0 * Qp0 + 43.0 * QpN) / 18720.0 + (503.0 * Qp1 + 172.0 * Qp4
+                                   + 87.0 * Qp5 + 265.0 * Qp3 + 328.0 * Qp2) / 3120.0;
+                                        QD_NQS       =  (1187.0 * QpN + 43.0 * Qp0) / 18720.0 + (503.0 * Qp5 + 172.0 * Qp2
+                                   + 87.0 * Qp1 + 265.0 * Qp3 + 328.0 * Qp4) / 3120.0;
+                                        `QiToPhi(Qp1, xg_ac, temp1)
+                                        `QiToPhi(Qp2, xg_ac, temp2)
+                                        `QiToPhi(Qp3, xg_ac, temp3)
+                                        `QiToPhi(Qp4, xg_ac, temp4)
+                                        `QiToPhi(Qp5, xg_ac, temp5)
+                                        QG_NQS       =  xg_ac - (x_sp + 4.0 * (temp1 + temp3 + temp5) + 2.0 * (temp2 + temp4) + x_dp) / 18.0;
+                                end else if (SWNQS_i == 9) begin
+                                        QS_NQS       =  (75653.0 * Qp8 + 225999.0 * Qp4) / 3782900.0 + (151321.0 * Qp9
+                                   + 454023.0 * Qp7 + 1073767.0 * Qp3 + 1564569.0 * Qp1) / 15131600.0
+                                   + 75623.0 * Qp6 / 1891450.0 + 145.0 * Qp5 / 2896.0 + 72263.0 * Qp2 / 945725.0
+                                   + (3504517.0 * Qp0 + 75653.0 * QpN) / 90789600.0;
+                                        QD_NQS       =  (75653.0 * Qp2 + 225999.0 * Qp6) / 3782900.0 + (151321.0 * Qp1
+                                   + 454023.0 * Qp3 + 1073767.0 * Qp7 + 1564569.0 * Qp9) / 15131600.0
+                                   + 75623.0 * Qp4 / 1891450.0 + 145.0 * Qp5 / 2896.0 + 72263.0 * Qp8 / 945725.0
+                                   + (3504517.0 * QpN + 75653.0 * Qp0) / 90789600.0;
+                                        `QiToPhi(Qp1, xg_ac, temp1)
+                                        `QiToPhi(Qp2, xg_ac, temp2)
+                                        `QiToPhi(Qp3, xg_ac, temp3)
+                                        `QiToPhi(Qp4, xg_ac, temp4)
+                                        `QiToPhi(Qp5, xg_ac, temp5)
+                                        `QiToPhi(Qp6, xg_ac, temp6)
+                                        `QiToPhi(Qp7, xg_ac, temp7)
+                                        `QiToPhi(Qp8, xg_ac, temp8)
+                                        `QiToPhi(Qp9, xg_ac, temp9)
+                                        QG_NQS       =  xg_ac - (x_sp + 4.0 * (temp1 + temp3 + temp5 + temp7 + temp9)
+                                  + 2.0 * (temp2 + temp4 + temp6 + temp8) + x_dp) / 30.0;
+                                end
+                                QG_NQS      =  pd * QG_NQS;
+
+                                if (sigVds > 0) begin
+                                        Qs          =  COX_qm * phit1 * QS_NQS;
+                                        Qd          =  COX_qm * phit1 * QD_NQS;
+                                end else begin
+                                        Qs          =  COX_qm * phit1 * QD_NQS;
+                                        Qd          =  COX_qm * phit1 * QS_NQS;
+                                end
+                                Qg          =  COX_qm * phit1 * QG_NQS;
+                                Qb          = -Qg - Qs - Qd;
+                        end
+
+            // Update internal nodes
+                        V(RES1)     <+  vnorm_inv * I(RES1) * r_nqs;
+                        V(SPLINE1)  <+  vnorm_inv * idt(-Tnorm * fk1, Qp1_0);
+                        V(RES2)     <+  vnorm_inv * I(RES2) * r_nqs;
+                        V(SPLINE2)  <+  vnorm_inv * idt(-Tnorm * fk2, Qp2_0);
+                        V(RES3)     <+  vnorm_inv * I(RES3) * r_nqs;
+                        V(SPLINE3)  <+  vnorm_inv * idt(-Tnorm * fk3, Qp3_0);
+                        V(RES4)     <+  vnorm_inv * I(RES4) * r_nqs;
+                        V(SPLINE4)  <+  vnorm_inv * idt(-Tnorm * fk4, Qp4_0);
+                        V(RES5)     <+  vnorm_inv * I(RES5) * r_nqs;
+                        V(SPLINE5)  <+  vnorm_inv * idt(-Tnorm * fk5, Qp5_0);
+                        V(RES6)     <+  vnorm_inv * I(RES6) * r_nqs;
+                        V(SPLINE6)  <+  vnorm_inv * idt(-Tnorm * fk6, Qp6_0);
+                        V(RES7)     <+  vnorm_inv * I(RES7) * r_nqs;
+                        V(SPLINE7)  <+  vnorm_inv * idt(-Tnorm * fk7, Qp7_0);
+                        V(RES8)     <+  vnorm_inv * I(RES8) * r_nqs;
+                        V(SPLINE8)  <+  vnorm_inv * idt(-Tnorm * fk8, Qp8_0);
+                        V(RES9)     <+  vnorm_inv * I(RES9) * r_nqs;
+                        V(SPLINE9)  <+  vnorm_inv * idt(-Tnorm * fk9, Qp9_0);
+
diff --git a/ihp-sg13g2/libs.tech/xyce/adms/PSP103_InitNQS.include b/ihp-sg13g2/libs.tech/xyce/adms/PSP103_InitNQS.include
new file mode 100644
index 00000000..27b86359
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/adms/PSP103_InitNQS.include
@@ -0,0 +1,207 @@
+//======================================================================================
+//======================================================================================
+// Filename: PSP103_InitNQS.include
+//======================================================================================
+//======================================================================================
+//
+//  (c) Copyright notice
+//
+//  Copyright 2004-2017 NXP Semiconductors, 2015-2017 Commissariat a l’energie atomique
+//  et aux energies alternatives (CEA), 2012-2015 Delft University of Technology and 
+//  2004-2011 Arizona State University Licensed under the Educational Community License,
+//  Version 2.0 (the "License"); you may not use this file except in compliance with the
+//  License. You may obtain a copy of the License at
+//  http://opensource.org/licenses/ECL-2.0
+//  Unless required by applicable law or agreed to in writing, software distributed under
+//  the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF
+//  ANY KIND, either express or implied. See the License for the specific language
+//  governing permissions and limitations under the License.
+//
+//
+//  Version: 103.6.0 (PSP), 200.5.0 (JUNCAP), December 2017
+//
+//======================================================================================
+//======================================================================================
+//
+// Further information can be found in the file releasenotesPSP103.txt
+//
+
+                /////////////////////////////////////////////////////////////////////////////
+                //
+                //  Computing initial (dc) values for internal nodes.
+                //  This code is independent of internal-node voltages
+                //
+                /////////////////////////////////////////////////////////////////////////////
+
+                        Qp1_0       =  0.0;
+                        Qp2_0       =  0.0;
+                        Qp3_0       =  0.0;
+                        Qp4_0       =  0.0;
+                        Qp5_0       =  0.0;
+                        Qp6_0       =  0.0;
+                        Qp7_0       =  0.0;
+                        Qp8_0       =  0.0;
+                        Qp9_0       =  0.0;
+                        fk1          =  0.0;
+                        fk2          =  0.0;
+                        fk3          =  0.0;
+                        fk4          =  0.0;
+                        fk5          =  0.0;
+                        fk6          =  0.0;
+                        fk7          =  0.0;
+                        fk8          =  0.0;
+                        fk9          =  0.0;
+                        if (SWNQS_i != 0) begin
+                                dQis         =  0.0;
+                                dQy          =  0.0;
+                                dfQi         =  0.0;
+                                fQi          =  0.0;
+                                d2Qy         =  0.0;
+
+                                Qp1          =  0.0;
+                                Qp2          =  0.0;
+                                Qp3          =  0.0;
+                                Qp4          =  0.0;
+                                Qp5          =  0.0;
+                                Qp6          =  0.0;
+                                Qp7          =  0.0;
+                                Qp8          =  0.0;
+                                Qp9          =  0.0;
+
+                                phi_p1       =  0.0;
+                                phi_p2       =  0.0;
+                                phi_p3       =  0.0;
+                                phi_p4       =  0.0;
+                                phi_p5       =  0.0;
+                                phi_p6       =  0.0;
+                                phi_p7       =  0.0;
+                                phi_p8       =  0.0;
+                                phi_p9       =  0.0;
+
+                                // Setting initial values for charge along the channel
+                                // from interpolated DC-solution
+                                if (xg_ac > 0) begin
+                                        if (SWNQS_i == 1) begin
+
+                                                phi_p1      = `Phiy(0.5);
+                                                `PhiToQb(phi_p1,Qb_tmp)
+                                                Qp1_0       = -pd * (xg_ac - phi_p1) - Qb_tmp;
+
+                                        end else if (SWNQS_i == 2) begin
+                                                phi_p1      = `Phiy(`oneThird);
+                                                `PhiToQb(phi_p1,Qb_tmp)
+                                                Qp1_0       = -pd * (xg_ac - phi_p1) - Qb_tmp;
+
+                                                phi_p2      = `Phiy(`twoThirds);
+                                                `PhiToQb(phi_p2,Qb_tmp)
+                                                Qp2_0       = -pd * (xg_ac - phi_p2) - Qb_tmp;
+
+                                                if (sigVds < 0) begin
+                                                        `swap(Qp1_0, Qp2_0)
+                                                end
+                                        end else if (SWNQS_i == 3) begin
+                                                phi_p1      = `Phiy(0.25);
+                                                `PhiToQb(phi_p1,Qb_tmp)
+                                                Qp1_0       = -pd * (xg_ac - phi_p1) - Qb_tmp;
+
+                                                phi_p2      = `Phiy(0.5);
+                                                `PhiToQb(phi_p2,Qb_tmp)
+                                                Qp2_0       = -pd * (xg_ac - phi_p2) - Qb_tmp;
+
+                                                phi_p3      = `Phiy(0.75);
+                                                `PhiToQb(phi_p3,Qb_tmp)
+                                                Qp3_0       = -pd * (xg_ac - phi_p3) - Qb_tmp;
+
+                                                if (sigVds < 0) begin
+                                                        `swap(Qp1_0, Qp3_0)
+                                                end
+                                        end else if (SWNQS_i == 5) begin
+                                                phi_p1      = `Phiy(`oneSixth);
+                                                `PhiToQb(phi_p1,Qb_tmp)
+                                                Qp1_0       = -pd * (xg_ac - phi_p1) - Qb_tmp;
+
+                                                phi_p2      = `Phiy(`oneThird);
+                                                `PhiToQb(phi_p2,Qb_tmp)
+                                                Qp2_0       = -pd * (xg_ac - phi_p2) - Qb_tmp;
+
+                                                phi_p3      = `Phiy(0.5);
+                                                `PhiToQb(phi_p3,Qb_tmp)
+                                                Qp3_0       = -pd * (xg_ac - phi_p3) - Qb_tmp;
+
+                                                phi_p4      = `Phiy(`twoThirds);
+                                                `PhiToQb(phi_p4,Qb_tmp)
+                                                Qp4_0       = -pd * (xg_ac - phi_p4) - Qb_tmp;
+
+                                                phi_p5      = `Phiy(0.8333333333333333);
+                                                `PhiToQb(phi_p5,Qb_tmp)
+                                                Qp5_0       = -pd * (xg_ac - phi_p5) - Qb_tmp;
+
+                                                if (sigVds < 0) begin
+                                                        `swap(Qp1_0, Qp5_0)
+                                                        `swap(Qp2_0, Qp4_0)
+                                                end
+                                        end else if (SWNQS_i == 9) begin
+                                                phi_p1      = `Phiy(0.1);
+                                                `PhiToQb(phi_p1,Qb_tmp)
+                                                Qp1_0       = -pd * (xg_ac - phi_p1) - Qb_tmp;
+
+                                                phi_p2      = `Phiy(0.2);
+                                                `PhiToQb(phi_p2,Qb_tmp)
+                                                Qp2_0       = -pd * (xg_ac - phi_p2) - Qb_tmp;
+
+                                                phi_p3      = `Phiy(0.3);
+                                                `PhiToQb(phi_p3,Qb_tmp)
+                                                Qp3_0       = -pd * (xg_ac - phi_p3) - Qb_tmp;
+
+                                                phi_p4      = `Phiy(0.4);
+                                                `PhiToQb(phi_p4,Qb_tmp)
+                                                Qp4_0       = -pd * (xg_ac - phi_p4) - Qb_tmp;
+
+                                                phi_p5      = `Phiy(0.5);
+                                                `PhiToQb(phi_p5,Qb_tmp)
+                                                Qp5_0       = -pd * (xg_ac - phi_p5) - Qb_tmp;
+
+                                                phi_p6      = `Phiy(0.6);
+                                                `PhiToQb(phi_p6,Qb_tmp)
+                                                Qp6_0       = -pd * (xg_ac - phi_p6) - Qb_tmp;
+
+                                                phi_p7      = `Phiy(0.7);
+                                                `PhiToQb(phi_p7,Qb_tmp)
+                                                Qp7_0       = -pd * (xg_ac - phi_p7) - Qb_tmp;
+
+                                                phi_p8      = `Phiy(0.8);
+                                                `PhiToQb(phi_p8,Qb_tmp)
+                                                Qp8_0       = -pd * (xg_ac - phi_p8) - Qb_tmp;
+
+                                                phi_p9      = `Phiy(0.9);
+                                                `PhiToQb(phi_p9,Qb_tmp)
+                                                Qp9_0       = -pd * (xg_ac - phi_p9) - Qb_tmp;
+
+                                                if (sigVds < 0) begin
+                                                        `swap(Qp1_0, Qp9_0)
+                                                        `swap(Qp2_0, Qp8_0)
+                                                        `swap(Qp3_0, Qp7_0)
+                                                        `swap(Qp4_0, Qp6_0)
+                                                end
+                                        end
+                                end // (x_g >0)
+                        end // (SWNQS_i != 0)
+
+                        x_sp        =  0.0;
+                        x_dp        =  0.0;
+                        Qp0         =  0.0;
+                        QpN         =  0.0;
+                        if (SWNQS_i != 0.0) begin
+                                x_sp        =  x_m_ac - sigVds * 0.5 * dps_ac * inv_phit1;
+                                x_dp        =  x_m_ac + sigVds * 0.5 * dps_ac * inv_phit1;
+                                Qp0         =  0.0;
+                                QpN         =  0.0;
+                                if (x_sp > 0) begin
+                                        `PhiToQb(x_sp, QbSIGN)
+                                        Qp0         =  -pd * (xg_ac - x_sp) - QbSIGN;
+                                end
+                                if (x_dp > 0) begin
+                                        `PhiToQb(x_dp, QbSIGN)
+                                        QpN         =  -pd * (xg_ac - x_dp) - QbSIGN;
+                                end
+                        end
diff --git a/ihp-sg13g2/libs.tech/xyce/adms/PSP103_SPCalculation.include b/ihp-sg13g2/libs.tech/xyce/adms/PSP103_SPCalculation.include
new file mode 100644
index 00000000..75bab032
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/adms/PSP103_SPCalculation.include
@@ -0,0 +1,350 @@
+//======================================================================================
+//======================================================================================
+// Filename: PSP103_SPCalculation.include
+//======================================================================================
+//======================================================================================
+//
+//  (c) Copyright notice
+//
+//  Copyright 2004-2017 NXP Semiconductors, 2015-2017 Commissariat a l’energie atomique
+//  et aux energies alternatives (CEA), 2012-2015 Delft University of Technology and
+//  2004-2011 Arizona State University Licensed under the Educational Community License,
+//  Version 2.0 (the "License"); you may not use this file except in compliance with the
+//  License. You may obtain a copy of the License at
+//  http://opensource.org/licenses/ECL-2.0
+//  Unless required by applicable law or agreed to in writing, software distributed under
+//  the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF
+//  ANY KIND, either express or implied. See the License for the specific language
+//  governing permissions and limitations under the License.
+//
+//
+//  Version: 103.6.0 (PSP), 200.5.0 (JUNCAP), December 2017
+//
+//======================================================================================
+//======================================================================================
+//
+// Further information can be found in the file releasenotesPSP103.txt
+//
+
+// Initialisation of some variables
+    alpha        =  0.0;
+    GdL          =  1.0;
+    dL           =  0.0;
+    qbm          =  0.0;
+    dps          =  0.0;
+    qim          =  0.0;
+    qim1         =  0.0;
+    H            =  1.0;
+    s1           =  0.0;
+    eta_p        =  1.0;
+    Gvsat        =  1.0;
+    Gvsatinv     =  1.0;
+    SP_S_x1      =  0.0;
+    x_s          =  0.0;
+    sqm          =  0.0;
+    xitsb        =  0.0;
+    rhob         =  0.0;
+    Gmob         =  1.0;
+    Gmob_dL      =  1.0;
+    Udse         =  0.0;
+    thesat1      =  0.0;
+    xgm          =  0.0;
+
+// Bias definition
+    Vgbstar      =  Vgs + Vsbstar;
+    Vgb1         =  Vgbstar - VFB_T;
+    Vsbx         =  Vsbstar + 0.5 * (Vds - Vdsx);
+    if (CFD_i < 1.0e-10) begin
+        Vdsp       =  Vdsx;
+    end else begin
+        Vdsp       =  2.0 * (sqrt(1.0 + CFD_i * Vdsx) - 1.0) / CFD_i;
+    end
+    delVg        =  CF_i * Vdsp * (1.0 + CFB_i * Vsbx); // DIBL
+    dphit1       =  PSCE_i * (1.0 + PSCED_i * Vdsx) * (1.0 + PSCEB_i * Vsbx); // SCE on subthreshold slope
+    Vgb1         =  Vgb1 + delVg;
+
+// Bias dependent body factor
+    if (DNSUB_i > 0.0) begin
+        Dnsub        =  DNSUB_i * `MAXA(0.0, Vgs + Vsb - VNSUB_i, NSLP_i);
+        Gf           =  G_0 * sqrt(1.0 + Dnsub);
+    end else begin
+        Gf           =  G_0;
+    end
+    Gf2          =  Gf * Gf;
+    inv_Gf2      =  1.0 / Gf2;
+
+// Bias dependence of interface states
+    dCTG         =  1.0;
+    if (CTG_i > 0.0) begin
+        xgct         =  2.0 * Vgb1 * inv_phit;
+        temp1        =  Gf2 + xgct;
+        temp2        = `MAXA((temp1 + xgct), 0.0, 5.0);
+        xsct0        =  0.5 * (temp1 - Gf * sqrt(temp2));
+        xbct         =  phib * inv_phit;
+        xsbstar      =  Vsbx * inv_phit;
+        temp1        =  xbct + xsbstar + 2.0;
+        xsct         = `MINA(xsct0, temp1, 5.0);
+        temp2        =  CTG_T * (xsct - (1.0 + CTB_i) * (0.5 * xbct + xsbstar));
+       `expl_low(temp2, dCTG)
+    end
+    ct_fact      =  1.0 + CT_T * dCTG;
+    phit1        =  phit * ct_fact * (1.0 + dphit1);
+    inv_phit1    =  1.0 / phit1;
+    xg           =  Vgb1 * inv_phit1;
+
+// Surface potential at source side
+    xi           =  1.0 + Gf * `invSqrt2;
+    inv_xi       =  1.0 /  xi;
+    Ux           =  Vsbstar * inv_phit1;
+    xn_s         =  phib * inv_phit1 + Ux;
+    if (xn_s < `se)
+        delta_ns     =  exp(-xn_s);
+    else
+        delta_ns     = `ke / `P3(xn_s - `se);
+    margin       =  1.0e-5 * xi;
+
+    `sp_s(x_s, xg, xn_s, delta_ns)
+    x_d          =  x_s;
+    x_m          =  x_s;
+    x_ds         =  0.0;
+
+// Core PSP current calculation
+    Vdsat_lim    =  3.912023005 * phit1;
+    if (xg <= 0.0) begin
+        qis          =  0.0;
+        xgm          =  xg - x_s;
+        Voxm         =  xgm * phit1;
+        qeff1        =  Voxm;
+        Vdsat        =  Vdsat_lim;
+        Vdse         =  Vds;
+    end else begin // (xg > 0)
+        delta_1s     =  0.0;
+        temp         =  1.0 / (2.0 + x_s * x_s);
+        xi0s         =  x_s * x_s * temp;
+        xi1s         =  4.0 * (x_s * temp * temp);
+        xi2s         =  (8.0 * temp - 12.0 * xi0s) * temp * temp;
+        if (x_s < `se05) begin
+            delta_1s     =  exp(x_s);
+            Es           =  exp(-x_s);
+            delta_1s     =  delta_ns * delta_1s;
+        end else if (x_s > (xn_s - `se05)) begin
+            delta_1s     =  exp(x_s - xn_s);
+            Es           =  delta_ns / delta_1s;
+        end else begin
+            delta_1s     = `ke05 / `P3(xn_s - x_s - `se05);
+            Es           = `ke05 / `P3(x_s - `se05);
+        end
+        Ds           =  delta_1s - delta_ns * (x_s + 1.0 + xi0s);
+        if (x_s < 1.0e-5) begin
+            Ps           =  0.5 * (x_s * x_s * (1.0 - `oneThird * (x_s * (1.0 - 0.25 * x_s))));
+            Ds           =  `oneSixth * (delta_ns * x_s * x_s * x_s * (1.0 + 1.75 * x_s));
+            temp         =  sqrt(1.0 - `oneThird * (x_s * (1.0 - 0.25 * x_s)));
+            sqm          =  `invSqrt2 * (x_s * temp);
+            alpha        =  1.0 + Gf * `invSqrt2 * (1.0 - 0.5 * x_s + `oneSixth * (x_s * x_s)) / temp;
+        end else begin
+            Ps           =  x_s - 1.0 + Es;
+            sqm          =  sqrt(Ps);
+            alpha        =  1.0 + 0.5 * (Gf * (1.0 - Es) / sqm);
+        end
+        Em           =  Es;
+        Ed           =  Em;
+        Dm           =  Ds;
+        Dd           =  Dm;
+
+        // Drain saturation voltage
+        Rxcor        =  (1.0 + 0.2 * XCOR_T * Vsbx) / (1.0 + XCOR_T * Vsbx);
+        if (Ds > `ke05) begin
+            xgs          =  Gf * sqrt(Ps + Ds);
+            qis          =  Gf2 * Ds * phit1 / (xgs + Gf * sqm);
+            qbs          =  sqm * Gf * phit1;
+            if (RSB_i < 0.0) begin
+                rhob         =  1.0 / (1.0 - RSB_i * Vsbx);
+            end else begin
+                rhob         =  1.0 + RSB_i * Vsbx;
+            end
+            if (RSG_i < 0.0) begin
+                temp         =  1.0 - RSG_i * qis;
+            end else begin
+                temp         =  1.0 / (1.0 + RSG_i * qis);
+            end
+            GR           =  THER_i * (rhob * temp * qis);
+            Eeffm        =  E_eff0 * (qbs + eta_mu * qis);
+            temp1        =  ln(Ps / (Ps + Ds + 1.0e-14));
+            Mutmp        =  pow(Eeffm * MUE_T, THEMU_T) + CS_T * exp(0.5 * THECS_T * temp1);
+            Gmob         =  (1.0 + Mutmp + GR) * Rxcor;
+            if (THESATB_i < 0.0) begin
+                xitsb        =  1.0 / (1.0 - THESATB_i * Vsbx);
+            end else begin
+                xitsb        =  1.0 + THESATB_i * Vsbx;
+            end
+            temp2        =  qis * xitsb;
+            wsat         =  100.0 * (temp2 / (100.0 + temp2));
+            if (THESATG_i < 0.0) begin
+                temp         =  1.0 / (1.0 - THESATG_i * wsat);
+            end else begin
+                temp         =  1.0 + THESATG_i * wsat;
+            end
+            thesat1      =  THESAT_T * (temp / Gmob);
+            phi_inf      =  qis / alpha + phit1;
+            ysat         =  thesat1 * phi_inf * `invSqrt2;
+            if (CHNL_TYPE==`PMOS) begin
+                ysat         =  ysat / sqrt(1.0 + ysat);
+            end
+            za           =  2.0 / (1.0 + sqrt(1.0 + 4.0 * ysat));
+            temp1        =  za * ysat;
+            Phi_0        =  phi_inf * za * (1.0 + 0.86 * (temp1 * (1.0 - temp1 * za) / (1.0 + 4.0 * (temp1 * temp1 * za))));
+            asat         =  xgs + 0.5 * Gf2;
+            Phi_2        =  0.98 * (Gf2 * Ds * phit1 / (asat + sqrt(asat * asat - Gf2 * Ds * 0.98)));
+            Phi_0_2      =  Phi_0 + Phi_2;
+            Phi0_Phi2    =  2.0 * (Phi_0 * Phi_2);
+            Phi_sat      =  Phi0_Phi2 / (Phi_0_2 + sqrt(Phi_0_2 * Phi_0_2 - 1.98 * Phi0_Phi2));
+            Vdsat        =  Phi_sat - phit1 * ln(1.0 + Phi_sat * (Phi_sat - 2.0 * asat * phit1) * inv_Gf2 / (phit1 * phit1 * Ds));
+        end else begin
+            Vdsat        =  Vdsat_lim;
+        end
+        temp         =  pow(Vds / Vdsat, AX_i);
+        Vdse         =  Vds * pow(1.0 + temp, -inv_AX);
+
+        // Surface potential at drain side
+        Udse         =  Vdse * inv_phit1;
+        xn_d         =  xn_s + Udse;
+        if (Udse < `se) begin
+            k_ds         =  exp(-Udse);
+        end else begin
+            k_ds         = `ke / `P3(Udse - `se);
+        end
+        delta_nd     =  delta_ns * k_ds;
+
+        `sp_s_d(x_d, xg, xn_d, delta_nd)
+        x_ds         =  x_d - x_s;
+
+        // Approximations for extremely small x_ds: capacitance calculation
+        if (x_ds < 1.0e-10) begin
+            pC           =  2.0 * (xg - x_s) + Gf2 * (1.0 - Es + delta_1s * k_ds - delta_nd * (1.0 + xi1s));
+            qC           =  Gf2 * (1.0 - k_ds) * Ds;
+            temp         =  2.0 - Gf2 * (Es + delta_1s * k_ds - delta_nd * xi2s);
+            temp         =  pC * pC - 2.0 * (temp * qC);
+            x_ds         =  2.0 * (qC / (pC + sqrt(temp)));
+            x_d          =  x_s + x_ds;
+        end
+        dps          =  x_ds * phit1;
+
+        xi0d         =  x_d * x_d / (2.0 + x_d * x_d);
+        if (x_d < `se05) begin
+            Ed            =  exp(-x_d);
+            if (x_d < 1.0e-5) begin
+                Dd            = `oneSixth * delta_nd * x_d * x_d * x_d * (1.0 + 1.75 * x_d);
+            end else begin
+                Dd            =  delta_nd * (1.0 / Ed - x_d - 1.0 - xi0d);
+            end
+        end else begin
+            if (x_d > (xn_d - `se05)) begin
+                temp          =  exp(x_d - xn_d);
+                Ed            =  delta_nd / temp;
+                Dd            =  temp - delta_nd * (x_d + 1.0 + xi0d);
+            end else begin
+                Ed            = `ke05 / `P3(x_d - `se05);
+                temp          = `ke05 / `P3(xn_d - x_d - `se05);
+                Dd            =  temp - delta_nd * (x_d + 1.0 + xi0d);
+            end
+        end
+
+        // Mid-point surface potential
+        x_m          =  0.5 * (x_s + x_d);
+        Em           =  0.0;
+        temp         =  Ed * Es;
+        if (temp > 0.0) begin
+            Em           =  sqrt(temp);
+        end
+        D_bar        =  0.5 * (Ds + Dd);
+        Dm           =  D_bar + 0.125 * (x_ds * x_ds * (Em - 2.0 * inv_Gf2));
+
+        if (x_m < 1.0e-5) begin
+            Pm           =  0.5 * (x_m * x_m * (1.0 - `oneThird * (x_m * (1.0 - 0.25 * x_m))));
+            xgm          =  Gf * sqrt(Dm + Pm);
+
+            // Polysilicon depletion
+            if (kp > 0.0) begin
+                eta_p        =  1.0 / sqrt(1.0 + kp * xgm);
+            end // (kp > 0.0)
+            temp         =  sqrt(1.0 - `oneThird * (x_m * (1.0 - 0.25 * x_m)));
+            sqm          = `invSqrt2 * (x_m * temp);
+            alpha        =  eta_p + `invSqrt2 * (Gf * (1.0 - 0.5 * x_m + `oneSixth * (x_m * x_m)) / temp);
+        end else begin
+            Pm           =  x_m - 1.0 + Em;
+            xgm          =  Gf * sqrt(Dm + Pm);
+
+            // Polysilicon depletion
+            if (kp > 0.0) begin
+                d0           =  1.0 - Em + 2.0 * (xgm * inv_Gf2);
+                eta_p        =  1.0 / sqrt(1.0 + kp * xgm);
+                temp         =  eta_p / (eta_p + 1.0);
+                x_pm         =  kp * (temp * temp * Gf2 * Dm);
+                p_pd         =  2.0 * (xgm - x_pm) + Gf2 * (1.0 - Em + Dm);
+                q_pd         =  x_pm * (x_pm - 2.0 * xgm);
+                xi_pd        =  1.0 - 0.5 * (Gf2 * (Em + Dm));
+                u_pd         =  q_pd * p_pd / (p_pd * p_pd - xi_pd * q_pd);
+                x_m          =  x_m + u_pd;
+                km           =  exp(u_pd);
+                Em           =  Em / km;
+                Dm           =  Dm * km;
+                Pm           =  x_m - 1.0 + Em;
+                xgm          =  Gf * sqrt(Dm + Pm);
+                km0          =  1.0 - Em + 2.0 * (xgm * eta_p * inv_Gf2);
+                x_ds         =  x_ds * km * (d0 + D_bar) / (km0 + km * D_bar);
+                dps          =  x_ds * phit1;
+            end // (kp > 0.0)
+            sqm          =  sqrt(Pm);
+            alpha        =  eta_p + 0.5 * (Gf * (1.0 - Em) / sqm);
+        end
+
+        // Potential midpoint inversion charge
+        qim          =  phit1 * (Gf2 * Dm / (xgm + Gf * sqm));
+        qim1         =  qim + phit1 * alpha;
+        qbm          =  sqm * Gf * phit1;
+
+        // Series resistance
+        if (RSG_i < 0.0) begin
+            temp         = 1.0 - RSG_i * qim;
+        end else begin
+            temp         = 1.0 / (1.0 + RSG_i * qim);
+        end
+        GR           =  THER_i * (rhob * temp * qim);
+
+        // Mobility reduction
+        qeff         =  qbm + eta_mu * qim;
+        qeff1        =  qbm + eta_mu1 * qim;
+        Eeffm        =  E_eff0 * qeff;
+        temp1        =  ln(Pm / (Pm + Dm + 1.0e-14));
+        Mutmp        =  pow(Eeffm * MUE_T, THEMU_T) + CS_T * exp(0.5 * THECS_T * temp1);
+        Gmob         =  (1.0 + Mutmp + GR) * Rxcor;
+
+        // Channel length modulation
+        s1           =  ln((1.0 + (Vds - dps) * inv_VP) / (1.0 + (Vdse - dps) * inv_VP));
+        dL           =  ALP_i * s1;
+        GdL          =  1.0 / (1.0 + dL + dL * dL);
+
+        // Velocity saturation
+        temp2        =  qim * xitsb;
+        wsat         =  100.0 * (temp2 / (100.0 + temp2));
+        Gmob_dL      =  Gmob * GdL;
+        if (THESATG_i < 0.0) begin
+            temp         =  1.0 / (1.0 - THESATG_i * wsat);
+        end else begin
+            temp         =  1.0 + THESATG_i * wsat;
+        end
+        thesat1      =  THESAT_T * (temp / Gmob_dL);
+        zsat         =  thesat1 * thesat1 * dps * dps;
+        if (CHNL_TYPE == `PMOS) begin
+            zsat         =  zsat / (1.0 + thesat1 * dps);
+        end
+        Gvsat        =  0.5 * (Gmob_dL * (1.0 + sqrt(1.0 + 2.0 * zsat)));
+        Gvsatinv     =  1.0 / Gvsat;
+
+        // Variables for calculation of intrinsic charges and gate current
+        Voxm         =  xgm * phit1;
+        temp         =  Gmob_dL * Gvsatinv;
+        alpha1       =  alpha * (1.0 + 0.5 * (zsat * temp * temp));
+        H            =  temp * qim1 / alpha1;
+
+    end // (xg > 0)
diff --git a/ihp-sg13g2/libs.tech/xyce/adms/PSP103_binning.include b/ihp-sg13g2/libs.tech/xyce/adms/PSP103_binning.include
new file mode 100644
index 00000000..b8a24020
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/adms/PSP103_binning.include
@@ -0,0 +1,192 @@
+//======================================================================================
+//======================================================================================
+// Filename: PSP103_binning.include
+//======================================================================================
+//======================================================================================
+//
+//  (c) Copyright notice
+//
+//  Copyright 2004-2017 NXP Semiconductors, 2015-2017 Commissariat a l’energie atomique
+//  et aux energies alternatives (CEA), 2012-2015 Delft University of Technology and
+//  2004-2011 Arizona State University Licensed under the Educational Community License,
+//  Version 2.0 (the "License"); you may not use this file except in compliance with the
+//  License. You may obtain a copy of the License at
+//  http://opensource.org/licenses/ECL-2.0
+//  Unless required by applicable law or agreed to in writing, software distributed under
+//  the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF
+//  ANY KIND, either express or implied. See the License for the specific language
+//  governing permissions and limitations under the License.
+//
+//
+//  Version: 103.6.0 (PSP), 200.5.0 (JUNCAP), December 2017
+//
+//======================================================================================
+//======================================================================================
+//
+// Further information can be found in the file releasenotesPSP103.txt
+//
+                        // auxiliary variables
+                        iLEWE        =  iLE * iWE;
+                        iiLE         =  LE / `LEN;
+                        iiWE         =  WE / `WEN;
+                        iiLEWE       =  iiLE * iiWE;
+                        iiiLEWE      =  iiWE / iiLE;
+
+                        // auxiliary variables for COX only
+                        iiLEcv       =  LEcv / `LEN;
+                        iiWEcv       =  WEcv / `WEN;
+                        iiLEWEcv     =  iiLEcv * iiWEcv;
+
+                        // auxiliary variables for CGOV only
+                        iLEcv        = `LEN / LEcv;
+                        iiiLEWEcv    =  iiWEcv / iiLEcv;
+
+                        // auxiliary variables for CGBOV only
+                        iiLcv        =  Lcv / `LEN;
+                        iiWcv        =  Wcv / `WEN;
+                        iiLWcv       =  iiLcv * iiWcv;
+
+                        // auxiliary variables for CFR only
+                        iLcv         =  `LEN / Lcv;
+                        iiiLWcv      =   iiWcv / iiLcv;
+
+                        // Process parameters
+                        VFB_p        =  POVFB + iLE * PLVFB + iWE * PWVFB + iLEWE * PLWVFB;
+                        STVFB_p      =  POSTVFB + iLE * PLSTVFB + iWE * PWSTVFB + iLEWE * PLWSTVFB;
+                        ST2VFB_p     =  POST2VFB;
+                        TOX_p        =  POTOX;
+                        EPSROX_p     =  POEPSROX;
+                        NEFF_p       =  PONEFF + iLE * PLNEFF + iWE * PWNEFF + iLEWE * PLWNEFF;
+                        FACNEFFAC_p  =  POFACNEFFAC + iLE * PLFACNEFFAC + iWE * PWFACNEFFAC + iLEWE * PLWFACNEFFAC;
+                        GFACNUD_p    =  POGFACNUD + PLGFACNUD * iLE + PWGFACNUD * iWE + PLWGFACNUD * iLE * iWE;
+                        VSBNUD_p     =  POVSBNUD;
+                        DVSBNUD_p    =  PODVSBNUD;
+                        VNSUB_p      =  POVNSUB;
+                        NSLP_p       =  PONSLP;
+                        DNSUB_p      =  PODNSUB;
+                        DPHIB_p      =  PODPHIB + iLE * PLDPHIB + iWE * PWDPHIB + iLEWE * PLWDPHIB;
+                        DELVTAC_p    =  PODELVTAC + iLE * PLDELVTAC + iWE * PWDELVTAC + iLEWE * PLWDELVTAC;
+                        NP_p         =  PONP + iLE * PLNP + iWE * PWNP + iLEWE * PLWNP;
+                        TOXOV_p      =  POTOXOV;
+                        TOXOVD_p     =  POTOXOVD;
+                        NOV_p        =  PONOV + iLE * PLNOV + iWE * PWNOV + iLEWE * PLWNOV;
+                        NOVD_p       =  PONOVD + iLE * PLNOVD + iWE * PWNOVD + iLEWE * PLWNOVD;
+
+                        // Interface states parameters
+                        CT_p         =  POCT + iLE * PLCT + iWE * PWCT + iLEWE * PLWCT;
+                        CTG_p        =  POCTG;
+                        CTB_p        =  POCTB;
+                        STCT_p       =  POSTCT;
+
+                        // DIBL parameters
+                        CF_p         =  POCF + iLE * PLCF + iWE * PWCF + iLEWE * PLWCF;
+                        CFD_p        =  POCFD;
+                        CFB_p        =  POCFB;
+
+                        // Subthreshold slope parameters of short channel transistor
+                        PSCE_p       =  POPSCE + iLE * PLPSCE + iWE * PWPSCE + iLEWE * PLWPSCE;
+                        PSCEB_p      =  POPSCEB;
+                        PSCED_p      =  POPSCED;
+
+                        // Mobility parameters
+                        BETN_p       =  iiWE * iLE * (POBETN + iLE * PLBETN + iWE * PWBETN + iLEWE * PLWBETN);
+                        STBET_p      =  POSTBET + iLE * PLSTBET + iWE * PWSTBET + iLEWE * PLWSTBET;
+                        MUE_p        =  POMUE + iLE * PLMUE + iWE * PWMUE + iLEWE * PLWMUE;
+                        STMUE_p      =  POSTMUE;
+                        THEMU_p      =  POTHEMU;
+                        STTHEMU_p    =  POSTTHEMU;
+                        CS_p         =  POCS + iLE * PLCS + iWE * PWCS + iLEWE * PLWCS;
+                        STCS_p       =  POSTCS;
+                        THECS_p      =  POTHECS;
+                        STTHECS_p    =  POSTTHECS;
+                        XCOR_p       =  POXCOR + iLE * PLXCOR + iWE * PWXCOR + iLEWE * PLWXCOR;
+                        STXCOR_p     =  POSTXCOR;
+                        FETA_p       =  POFETA;
+
+                        // Series resistance parameters
+                        RS_p         =  PORS + iLE * PLRS + iWE * PWRS + iLEWE * PLWRS;
+                        STRS_p       =  POSTRS;
+                        RSB_p        =  PORSB;
+                        RSG_p        =  PORSG;
+
+                        // Velocity saturation parameters
+                        THESAT_p     =  POTHESAT + iLE * PLTHESAT + iWE * PWTHESAT + iLEWE * PLWTHESAT;
+                        STTHESAT_p   =  POSTTHESAT + iLE * PLSTTHESAT + iWE * PWSTTHESAT + iLEWE * PLWSTTHESAT;
+                        THESATB_p    =  POTHESATB + iLE * PLTHESATB + iWE * PWTHESATB + iLEWE * PLWTHESATB;
+                        THESATG_p    =  POTHESATG + iLE * PLTHESATG + iWE * PWTHESATG + iLEWE * PLWTHESATG;
+
+                        // Saturation voltage parameters
+                        AX_p         =  POAX + iLE * PLAX + iWE * PWAX + iLEWE * PLWAX;
+
+                        // Channel length modulation (CLM) parameters
+                        ALP_p        =  POALP + iLE * PLALP + iWE * PWALP + iLEWE * PLWALP;
+                        ALP1_p       =  POALP1 + iLE * PLALP1 + iWE * PWALP1 + iLEWE * PLWALP1;
+                        ALP2_p       =  POALP2 + iLE * PLALP2 + iWE * PWALP2 + iLEWE * PLWALP2;
+                        VP_p         =  POVP;
+
+                        // Impact ionization parameters
+                        A1_p         =  POA1 + iLE * PLA1 + iWE * PWA1 + iLEWE * PLWA1;
+                        A2_p         =  POA2;
+                        STA2_p       =  POSTA2;
+                        A3_p         =  POA3 + iLE * PLA3 + iWE * PWA3 + iLEWE * PLWA3;
+                        A4_p         =  POA4 + iLE * PLA4 + iWE * PWA4 + iLEWE * PLWA4;
+                        GCO_p        =  POGCO;
+
+                        // Gate current parameters
+                        IGINV_p      =  POIGINV + iiLE * PLIGINV + iiWE * PWIGINV + iiLEWE * PLWIGINV;
+                        IGOV_p       =  POIGOV + iLE * PLIGOV + iiWE * PWIGOV + iiiLEWE * PLWIGOV;
+                        IGOVD_p      =  POIGOVD + iLE * PLIGOVD + iiWE * PWIGOVD + iiiLEWE * PLWIGOVD;
+                        STIG_p       =  POSTIG;
+                        GC2_p        =  POGC2;
+                        GC3_p        =  POGC3;
+                        CHIB_p       =  POCHIB;
+
+                        // Gate-induced drain leakage (GIDL) parameters
+                        AGIDL_p      =  POAGIDL + iLE * PLAGIDL + iiWE * PWAGIDL + iiiLEWE * PLWAGIDL;
+                        AGIDLD_p     =  POAGIDLD + iLE * PLAGIDLD + iiWE * PWAGIDLD + iiiLEWE * PLWAGIDLD;
+                        BGIDL_p      =  POBGIDL;
+                        BGIDLD_p     =  POBGIDLD;
+                        STBGIDL_p    =  POSTBGIDL;
+                        STBGIDLD_p   =  POSTBGIDLD;
+                        CGIDL_p      =  POCGIDL;
+                        CGIDLD_p     =  POCGIDLD;
+
+                        // Charge model parameters
+                        COX_p        =  POCOX + iiLEcv * PLCOX + iiWEcv * PWCOX + iiLEWEcv * PLWCOX;
+                        CGOV_p       =  POCGOV + iLEcv * PLCGOV + iiWEcv * PWCGOV + iiiLEWEcv * PLWCGOV;
+                        CGOVD_p      =  POCGOVD + iLEcv * PLCGOVD + iiWEcv * PWCGOVD + iiiLEWEcv * PLWCGOVD;
+                        CGBOV_p      =  POCGBOV + iiLcv * PLCGBOV + iiWcv * PWCGBOV + iiLWcv * PLWCGBOV;
+                        CFR_p        =  POCFR + iLcv * PLCFR + iiWcv * PWCFR + iiiLWcv * PLWCFR;
+                        CFRD_p       =  POCFRD + iLcv * PLCFRD + iiWcv * PWCFRD + iiiLWcv * PLWCFRD;
+
+                        // Noise model parameters
+                        FNT_p        =  POFNT;
+                        FNTEXC_p     =  iLE * iLE * (POFNTEXC + iLE * PLFNTEXC + iWE * PWFNTEXC + iLEWE * PLWFNTEXC);
+                        NFA_p        =  PONFA + iLE * PLNFA + iWE * PWNFA + iLEWE * PLWNFA;
+                        NFB_p        =  PONFB + iLE * PLNFB + iWE * PWNFB + iLEWE * PLWNFB;
+                        NFC_p        =  PONFC + iLE * PLNFC + iWE * PWNFC + iLEWE * PLWNFC;
+                        EF_p         =  POEF;
+
+                        // Edge transistor: PSP 103.4
+                        VFBEDGE_p    =  POVFBEDGE;
+                        STVFBEDGE_p  =  POSTVFBEDGE + iLE * PLSTVFBEDGE + iWE * PWSTVFBEDGE + iLEWE * PLWSTVFBEDGE;
+                        DPHIBEDGE_p  =  PODPHIBEDGE + iLE * PLDPHIBEDGE + iWE * PWDPHIBEDGE + iLEWE * PLWDPHIBEDGE;
+                        NEFFEDGE_p   =  PONEFFEDGE + iLE * PLNEFFEDGE + iWE * PWNEFFEDGE + iLEWE * PLWNEFFEDGE;
+                        CTEDGE_p     =  POCTEDGE + iLE * PLCTEDGE + iWE * PWCTEDGE + iLEWE * PLWCTEDGE;
+                        BETNEDGE_p   =  iLE * (POBETNEDGE + iLE * PLBETNEDGE + iWE * PWBETNEDGE + iLEWE * PLWBETNEDGE);
+                        STBETEDGE_p  =  POSTBETEDGE + iLE * PLSTBETEDGE + iWE * PWSTBETEDGE + iLEWE * PLWSTBETEDGE;
+                        PSCEEDGE_p   =  POPSCEEDGE + iLE * PLPSCEEDGE + iWE * PWPSCEEDGE + iLEWE * PLWPSCEEDGE;
+                        PSCEBEDGE_p  =  POPSCEBEDGE;
+                        PSCEDEDGE_p  =  POPSCEDEDGE;
+                        CFEDGE_p     =  POCFEDGE + iLE * PLCFEDGE + iWE * PWCFEDGE + iLEWE * PLWCFEDGE;
+                        CFDEDGE_p    =  POCFDEDGE;
+                        CFBEDGE_p    =  POCFBEDGE;
+                        FNTEDGE_p    =  POFNTEDGE;
+                        NFAEDGE_p    =  PONFAEDGE + iLE * PLNFAEDGE + iWE * PWNFAEDGE + iLEWE * PLWNFAEDGE;
+                        NFBEDGE_p    =  PONFBEDGE + iLE * PLNFBEDGE + iWE * PWNFBEDGE + iLEWE * PLWNFBEDGE;
+                        NFCEDGE_p    =  PONFCEDGE + iLE * PLNFCEDGE + iWE * PWNFCEDGE + iLEWE * PLWNFCEDGE;
+                        EFEDGE_p     =  POEFEDGE;
+
+                        // Well proximity effect parameters
+                        KVTHOWE      =  POKVTHOWE + iLE * PLKVTHOWE + iWE * PWKVTHOWE + iLEWE * PLWKVTHOWE;
+                        KUOWE        =  POKUOWE + iLE * PLKUOWE + iWE * PWKUOWE + iLEWE * PLWKUOWE;
diff --git a/ihp-sg13g2/libs.tech/xyce/adms/PSP103_binpars.include b/ihp-sg13g2/libs.tech/xyce/adms/PSP103_binpars.include
new file mode 100644
index 00000000..6f6545d2
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/adms/PSP103_binpars.include
@@ -0,0 +1,353 @@
+//======================================================================================
+//======================================================================================
+// Filename: PSP103_binpars.include
+//======================================================================================
+//======================================================================================
+//
+//  (c) Copyright notice
+//
+//  Copyright 2004-2017 NXP Semiconductors, 2015-2017 Commissariat a l’energie atomique
+//  et aux energies alternatives (CEA), 2012-2015 Delft University of Technology and
+//  2004-2011 Arizona State University Licensed under the Educational Community License,
+//  Version 2.0 (the "License"); you may not use this file except in compliance with the
+//  License. You may obtain a copy of the License at
+//  http://opensource.org/licenses/ECL-2.0
+//  Unless required by applicable law or agreed to in writing, software distributed under
+//  the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF
+//  ANY KIND, either express or implied. See the License for the specific language
+//  governing permissions and limitations under the License.
+//
+//
+//  Version: 103.6.0 (PSP), 200.5.0 (JUNCAP), December 2017
+//
+//======================================================================================
+//======================================================================================
+//
+// Further information can be found in the file releasenotesPSP103.txt
+//
+
+
+        //  --------------------------------------------------------------------------------------------------------------
+        //  PSP global model parameters (binning)
+        //  --------------------------------------------------------------------------------------------------------------
+
+        // Process parameters
+                `MPRnb(POVFB          ,-1.0       ,"V"                                  ,"Coefficient for the geometry independent part of VFB")
+                `MPRnb(PLVFB          ,0.0        ,"V"                                  ,"Coefficient for the length dependence of VFB")
+                `MPRnb(PWVFB          ,0.0        ,"V"                                  ,"Coefficient for the width dependence of VFB")
+                `MPRnb(PLWVFB         ,0.0        ,"V"                                  ,"Coefficient for the length times width dependence of VFB")
+                `MPRnb(POSTVFB        ,5.0e-4     ,"V/K"                                ,"Coefficient for the geometry independent part of STVFB")
+                `MPRnb(PLSTVFB        ,0.0        ,"V/K"                                ,"Coefficient for the length dependence of STVFB")
+                `MPRnb(PWSTVFB        ,0.0        ,"V/K"                                ,"Coefficient for the width dependence of STVFB")
+                `MPRnb(PLWSTVFB       ,0.0        ,"V/K"                                ,"Coefficient for the length times width dependence of STVFB")
+                `MPRnb(POST2VFB       ,0.0        ,"K^-1"                               ,"Coefficient for the geometry independent part of ST2VFB")
+                `MPRnb(POTOX          ,2.0e-9     ,"m"                                  ,"Coefficient for the geometry independent part of TOX")
+                `MPRnb(POEPSROX       ,3.9        ,""                                   ,"Coefficient for the geometry independent part of EPSOX")
+                `MPRnb(PONEFF         ,5.0e23     ,"m^-3"                               ,"Coefficient for the geometry independent part of NEFF")
+                `MPRnb(PLNEFF         ,0.0        ,"m^-3"                               ,"Coefficient for the length dependence of NEFF")
+                `MPRnb(PWNEFF         ,0.0        ,"m^-3"                               ,"Coefficient for the width dependence of NEFF")
+                `MPRnb(PLWNEFF        ,0.0        ,"m^-3"                               ,"Coefficient for the length times width dependence of NEFF")
+                `MPRnb(POFACNEFFAC    ,1.0        ,""                                   ,"Coefficient for the geometry independent part of FACNEFFAC")
+                `MPRnb(PLFACNEFFAC    ,0.0        ,""                                   ,"Coefficient for the length dependence of FACNEFFAC")
+                `MPRnb(PWFACNEFFAC    ,0.0        ,""                                   ,"Coefficient for the width dependence of FACNEFFAC")
+                `MPRnb(PLWFACNEFFAC   ,0.0        ,""                                   ,"Coefficient for the length times width dependence of FACNEFFAC")
+                `MPRnb(POGFACNUD      ,1.0        ,""                                   ,"Coefficient for the geometry independent part of GFACNUD")
+                `MPRnb(PLGFACNUD      ,0.0        ,""                                   ,"Coefficient for the length dependence of GFACNUD")
+                `MPRnb(PWGFACNUD      ,0.0        ,""                                   ,"Coefficient for the width dependence of GFACNUD")
+                `MPRnb(PLWGFACNUD     ,0.0        ,""                                   ,"Coefficient for the length times width dependence of GFACNUD")
+                `MPRnb(POVSBNUD       ,0.0        ,"V"                                  ,"Coefficient for the geometry independent part of VSBNUD")
+                `MPRnb(PODVSBNUD      ,1.0        ,"V"                                  ,"Coefficient for the geometry independent part of DVSBNUD")
+                `MPRnb(POVNSUB        ,0.0        ,"V"                                  ,"Coefficient for the geometry independent part of VNSUB")
+                `MPRnb(PONSLP         ,0.05       ,"V"                                  ,"Coefficient for the geometry independent part of NSLP")
+                `MPRnb(PODNSUB        ,0.0        ,"V^-1"                               ,"Coefficient for the geometry independent part of DNSUB")
+                `MPRnb(PODPHIB        ,0.0        ,"V"                                  ,"Coefficient for the geometry independent part of DPHIB")
+                `MPRnb(PLDPHIB        ,0.0        ,"V"                                  ,"Coefficient for the length dependence of DPHIB")
+                `MPRnb(PWDPHIB        ,0.0        ,"V"                                  ,"Coefficient for the width dependence of DPHIB")
+                `MPRnb(PLWDPHIB       ,0.0        ,"V"                                  ,"Coefficient for the length times width dependence of DPHIB")
+                `MPRnb(PODELVTAC      ,0.0        ,"V"                                  ,"Coefficient for the geometry independent part of DELVTAC")
+                `MPRnb(PLDELVTAC      ,0.0        ,"V"                                  ,"Coefficient for the length dependence of DELVTAC")
+                `MPRnb(PWDELVTAC      ,0.0        ,"V"                                  ,"Coefficient for the width dependence of DELVTAC")
+                `MPRnb(PLWDELVTAC     ,0.0        ,"V"                                  ,"Coefficient for the length times width dependence of DELVTAC")
+                `MPRnb(PONP           ,1.0e26     ,"m^-3"                               ,"Coefficient for the geometry independent part of NP")
+                `MPRnb(PLNP           ,0.0        ,"m^-3"                               ,"Coefficient for the length dependence of NP")
+                `MPRnb(PWNP           ,0.0        ,"m^-3"                               ,"Coefficient for the width dependence of NP")
+                `MPRnb(PLWNP          ,0.0        ,"m^-3"                               ,"Coefficient for the length times width dependence of NP")
+                `MPRnb(POTOXOV        ,2.0e-09    ,"m"                                  ,"Coefficient for the geometry independent part of TOXOV")
+                `MPRnb(POTOXOVD       ,2.0e-09    ,"m"                                  ,"Coefficient for the geometry independent part of TOXOV for drain side")
+                `MPRnb(PONOV          ,5.0e25     ,"m^-3"                               ,"Coefficient for the geometry independent part of NOV")
+                `MPRnb(PLNOV          ,0.0        ,"m^-3"                               ,"Coefficient for the length dependence of NOV")
+                `MPRnb(PWNOV          ,0.0        ,"m^-3"                               ,"Coefficient for the width dependence of NOV")
+                `MPRnb(PLWNOV         ,0.0        ,"m^-3"                               ,"Coefficient for the length times width dependence of NOV")
+                `MPRnb(PONOVD         ,5.0e25     ,"m^-3"                               ,"Coefficient for the geometry independent part of NOV for drain side")
+                `MPRnb(PLNOVD         ,0.0        ,"m^-3"                               ,"Coefficient for the length dependence of NOV for drain side")
+                `MPRnb(PWNOVD         ,0.0        ,"m^-3"                               ,"Coefficient for the width dependence of NOV for drain side")
+                `MPRnb(PLWNOVD        ,0.0        ,"m^-3"                               ,"Coefficient for the length times width dependence of NOV for drain side")
+
+        //  Interface states parameters
+                `MPRnb(POCT           ,0.0        ,""                                   ,"Coefficient for the geometry independent part of CT")
+                `MPRnb(PLCT           ,0.0        ,""                                   ,"Coefficient for the length dependence of CT")
+                `MPRnb(PWCT           ,0.0        ,""                                   ,"Coefficient for the width dependence of CT")
+                `MPRnb(PLWCT          ,0.0        ,""                                   ,"Coefficient for the length times width dependence of CT")
+                `MPRnb(POCTG          ,0.0        ,""                                   ,"Coefficient for the geometry independent part of CTG")
+                `MPRnb(POCTB          ,0.0        ,""                                   ,"Coefficient for the geometry independent part of CTB")
+                `MPRnb(POSTCT         ,1.0        ,""                                   ,"Coefficient for the geometry independent part of STCT")
+
+        // DIBL parameters
+                `MPRnb(POCF           ,0.0        ,""                                   ,"Coefficient for the geometry independent part of CF")
+                `MPRnb(PLCF           ,0.0        ,""                                   ,"Coefficient for the length dependence of CF")
+                `MPRnb(PWCF           ,0.0        ,""                                   ,"Coefficient for the width dependence of CF")
+                `MPRnb(PLWCF          ,0.0        ,""                                   ,"Coefficient for the length times width dependence of CF")
+                `MPRnb(POCFD          ,0.0        ,"V^-1"                               ,"Coefficient for the geometry independent part of CFD")
+                `MPRnb(POCFB          ,0.0        ,"V^-1"                               ,"Coefficient for the geometry independent part of CFB")
+
+        //  Subthreshold slope parameters of short channel transistor
+                `MPRnb(POPSCE         ,0.0        ,""                                   ,"Coefficient for the geometry independent part of PSCE")
+                `MPRnb(PLPSCE         ,0.0        ,""                                   ,"Coefficient for the length dependence of PSCE")
+                `MPRnb(PWPSCE         ,0.0        ,""                                   ,"Coefficient for the width dependence of PSCE")
+                `MPRnb(PLWPSCE        ,0.0        ,""                                   ,"Coefficient for the length times width dependence of PSCE")
+                `MPRnb(POPSCEB        ,0.0        ,"V^-1"                               ,"Coefficient for the geometry independent part of PSCEB")
+                `MPRnb(POPSCED        ,0.0        ,"V^-1"                               ,"Coefficient for the geometry independent part of PSCED")
+
+        // Mobility parameters
+                `MPRnb(POBETN         ,7.0e-2     ,"m^2/V/s"                            ,"Coefficient for the geometry independent part of BETN")
+                `MPRnb(PLBETN         ,0.0        ,"m^2/V/s"                            ,"Coefficient for the length dependence of BETN")
+                `MPRnb(PWBETN         ,0.0        ,"m^2/V/s"                            ,"Coefficient for the width dependence of BETN")
+                `MPRnb(PLWBETN        ,0.0        ,"m^2/V/s"                            ,"Coefficient for the length times width dependence of BETN")
+                `MPRnb(POSTBET        ,1.0        ,""                                   ,"Coefficient for the geometry independent part of STBET")
+                `MPRnb(PLSTBET        ,0.0        ,""                                   ,"Coefficient for the length dependence of STBET")
+                `MPRnb(PWSTBET        ,0.0        ,""                                   ,"Coefficient for the width dependence of STBET")
+                `MPRnb(PLWSTBET       ,0.0        ,""                                   ,"Coefficient for the length times width dependence of STBET")
+                `MPRnb(POMUE          ,0.5        ,"m/V"                                ,"Coefficient for the geometry independent part of MUE")
+                `MPRnb(PLMUE          ,0.0        ,"m/V"                                ,"Coefficient for the length dependence of MUE")
+                `MPRnb(PWMUE          ,0.0        ,"m/V"                                ,"Coefficient for the width dependence of MUE")
+                `MPRnb(PLWMUE         ,0.0        ,"m/V"                                ,"Coefficient for the length times width dependence of MUE")
+                `MPRnb(POSTMUE        ,0.0        ,""                                   ,"Coefficient for the geometry independent part of STMUE")
+                `MPRnb(POTHEMU        ,1.5        ,""                                   ,"Coefficient for the geometry independent part of THEMU")
+                `MPRnb(POSTTHEMU      ,1.5        ,""                                   ,"Coefficient for the geometry independent part of STTHEMU")
+                `MPRnb(POCS           ,0.0        ,""                                   ,"Coefficient for the geometry independent part of CS")
+                `MPRnb(PLCS           ,0.0        ,""                                   ,"Coefficient for the length dependence of CS")
+                `MPRnb(PWCS           ,0.0        ,""                                   ,"Coefficient for the width dependence of CS")
+                `MPRnb(PLWCS          ,0.0        ,""                                   ,"Coefficient for the length times width dependence of CS")
+                `MPRnb(POSTCS         ,0.0        ,""                                   ,"Coefficient for the geometry independent part of STCS")
+                `MPRnb(POTHECS        ,2.0        ,""                                   ,"Coefficient for the geometry independent part of THECS")
+                `MPRnb(POSTTHECS      ,0.0        ,""                                   ,"Coefficient for the geometry independent part of STHTECS")
+                `MPRnb(POXCOR         ,0.0        ,"V^-1"                               ,"Coefficient for the geometry independent part of XCOR")
+                `MPRnb(PLXCOR         ,0.0        ,"V^-1"                               ,"Coefficient for the length dependence of XCOR")
+                `MPRnb(PWXCOR         ,0.0        ,"V^-1"                               ,"Coefficient for the width dependence of XCOR")
+                `MPRnb(PLWXCOR        ,0.0        ,"V^-1"                               ,"Coefficient for the length times width dependence of XCOR")
+                `MPRnb(POSTXCOR       ,0.0        ,""                                   ,"Coefficient for the geometry independent part of STXCOR")
+                `MPRnb(POFETA         ,1.0        ,""                                   ,"Coefficient for the geometry independent part of FETA")
+
+        // Series resistance parameters
+                `MPRnb(PORS           ,30.0       ,"Ohm"                                ,"Coefficient for the geometry independent part of RS")
+                `MPRnb(PLRS           ,0.0        ,"Ohm"                                ,"Coefficient for the length dependence of RS")
+                `MPRnb(PWRS           ,0.0        ,"Ohm"                                ,"Coefficient for the width dependence of RS")
+                `MPRnb(PLWRS          ,0.0        ,"Ohm"                                ,"Coefficient for the length times width dependence of RS")
+                `MPRnb(POSTRS         ,1.0        ,""                                   ,"Coefficient for the geometry independent part of STRS")
+                `MPRnb(PORSB          ,0.0        ,"V^-1"                               ,"Coefficient for the geometry independent part of RSB")
+                `MPRnb(PORSG          ,0.0        ,"V^-1"                               ,"Coefficient for the geometry independent part of RSG")
+
+        // Velocity saturation parameters
+                `MPRnb(POTHESAT       ,1.0        ,"V^-1"                               ,"Coefficient for the geometry independent part of THESAT")
+                `MPRnb(PLTHESAT       ,0.0        ,"V^-1"                               ,"Coefficient for the length dependence of THESAT")
+                `MPRnb(PWTHESAT       ,0.0        ,"V^-1"                               ,"Coefficient for the width dependence of THESAT")
+                `MPRnb(PLWTHESAT      ,0.0        ,"V^-1"                               ,"Coefficient for the length times width dependence of THESAT")
+                `MPRnb(POSTTHESAT     ,1.0        ,""                                   ,"Coefficient for the geometry independent part of STTHESAT")
+                `MPRnb(PLSTTHESAT     ,0.0        ,""                                   ,"Coefficient for the length dependence of STTHESAT")
+                `MPRnb(PWSTTHESAT     ,0.0        ,""                                   ,"Coefficient for the width dependence of STTHESAT")
+                `MPRnb(PLWSTTHESAT    ,0.0        ,""                                   ,"Coefficient for the length times width dependence of STTHESAT")
+                `MPRnb(POTHESATB      ,0.0        ,"V^-1"                               ,"Coefficient for the geometry independent part of THESATB")
+                `MPRnb(PLTHESATB      ,0.0        ,"V^-1"                               ,"Coefficient for the length dependence of THESATB")
+                `MPRnb(PWTHESATB      ,0.0        ,"V^-1"                               ,"Coefficient for the width dependence of THESATB")
+                `MPRnb(PLWTHESATB     ,0.0        ,"V^-1"                               ,"Coefficient for the length times width dependence of THESATB")
+                `MPRnb(POTHESATG      ,0.0        ,"V^-1"                               ,"Coefficient for the geometry independent part of THESATG")
+                `MPRnb(PLTHESATG      ,0.0        ,"V^-1"                               ,"Coefficient for the length dependence of THESATG")
+                `MPRnb(PWTHESATG      ,0.0        ,"V^-1"                               ,"Coefficient for the width dependence of THESATG")
+                `MPRnb(PLWTHESATG     ,0.0        ,"V^-1"                               ,"Coefficient for the length times width dependence of THESATG")
+
+        // Saturation voltage parameters
+                `MPRnb(POAX           ,3.0        ,""                                   ,"Coefficient for the geometry independent part of AX")
+                `MPRnb(PLAX           ,0.0        ,""                                   ,"Coefficient for the length dependence of AX")
+                `MPRnb(PWAX           ,0.0        ,""                                   ,"Coefficient for the width dependence of AX")
+                `MPRnb(PLWAX          ,0.0        ,""                                   ,"Coefficient for the length times width dependence of AX")
+
+        // Channel length modulation (CLM) parameters
+                `MPRnb(POALP          ,1.0e-2     ,""                                   ,"Coefficient for the geometry independent part of ALP")
+                `MPRnb(PLALP          ,0.0        ,""                                   ,"Coefficient for the length dependence of ALP")
+                `MPRnb(PWALP          ,0.0        ,""                                   ,"Coefficient for the width dependence of ALP")
+                `MPRnb(PLWALP         ,0.0        ,""                                   ,"Coefficient for the length times width dependence of ALP")
+                `MPRnb(POALP1         ,0.0        ,"V"                                  ,"Coefficient for the geometry independent part of ALP1")
+                `MPRnb(PLALP1         ,0.0        ,"V"                                  ,"Coefficient for the length dependence of ALP1")
+                `MPRnb(PWALP1         ,0.0        ,"V"                                  ,"Coefficient for the width dependence of ALP1")
+                `MPRnb(PLWALP1        ,0.0        ,"V"                                  ,"Coefficient for the length times width dependence of ALP1")
+                `MPRnb(POALP2         ,0.0        ,"V^-1"                               ,"Coefficient for the geometry independent part of ALP2")
+                `MPRnb(PLALP2         ,0.0        ,"V^-1"                               ,"Coefficient for the length dependence of ALP2")
+                `MPRnb(PWALP2         ,0.0        ,"V^-1"                               ,"Coefficient for the width dependence of ALP2")
+                `MPRnb(PLWALP2        ,0.0        ,"V^-1"                               ,"Coefficient for the length times width dependence of ALP2")
+                `MPRnb(POVP           ,0.05       ,"V"                                  ,"Coefficient for the geometry independent part of VP")
+
+        // Impact ionization parameters
+                `MPRnb(POA1           ,1.0        ,""                                   ,"Coefficient for the geometry independent part of A1")
+                `MPRnb(PLA1           ,0.0        ,""                                   ,"Coefficient for the length dependence of A1")
+                `MPRnb(PWA1           ,0.0        ,""                                   ,"Coefficient for the width dependence of A1")
+                `MPRnb(PLWA1          ,0.0        ,""                                   ,"Coefficient for the length times width dependence of A1")
+                `MPRnb(POA2           ,10.0       ,"V"                                  ,"Coefficient for the geometry independent part of A2")
+                `MPRnb(POSTA2         ,0.0        ,"V"                                  ,"Coefficient for the geometry independent part of STA2")
+                `MPRnb(POA3           ,1.0        ,""                                   ,"Coefficient for the geometry independent part of A3")
+                `MPRnb(PLA3           ,0.0        ,""                                   ,"Coefficient for the length dependence of A3")
+                `MPRnb(PWA3           ,0.0        ,""                                   ,"Coefficient for the width dependence of A3")
+                `MPRnb(PLWA3          ,0.0        ,""                                   ,"Coefficient for the length times width dependence of A3")
+                `MPRnb(POA4           ,0.0        ,"V^-0.5"                             ,"Coefficient for the geometry independent part of A4")
+                `MPRnb(PLA4           ,0.0        ,"V^-0.5"                             ,"Coefficient for the length dependence of A4")
+                `MPRnb(PWA4           ,0.0        ,"V^-0.5"                             ,"Coefficient for the width dependence of A4")
+                `MPRnb(PLWA4          ,0.0        ,"V^-0.5"                             ,"Coefficient for the length times width dependence of A4")
+                `MPRnb(POGCO          ,0.0        ,""                                   ,"Coefficient for the geometry independent part of GCO")
+
+        // Gate current parameters
+                `MPRnb(POIGINV        ,0.0        ,"A"                                  ,"Coefficient for the geometry independent part of IGINV")
+                `MPRnb(PLIGINV        ,0.0        ,"A"                                  ,"Coefficient for the length dependence of IGINV")
+                `MPRnb(PWIGINV        ,0.0        ,"A"                                  ,"Coefficient for the width dependence of IGINV")
+                `MPRnb(PLWIGINV       ,0.0        ,"A"                                  ,"Coefficient for the length times width dependence of IGINV")
+                `MPRnb(POIGOV         ,0.0        ,"A"                                  ,"Coefficient for the geometry independent part of IGOV")
+                `MPRnb(PLIGOV         ,0.0        ,"A"                                  ,"Coefficient for the length dependence of IGOV")
+                `MPRnb(PWIGOV         ,0.0        ,"A"                                  ,"Coefficient for the width dependence of IGOV")
+                `MPRnb(PLWIGOV        ,0.0        ,"A"                                  ,"Coefficient for the length times width dependence of IGOV")
+                `MPRnb(POIGOVD        ,0.0        ,"A"                                  ,"Coefficient for the geometry independent part of IGOV for drain side")
+                `MPRnb(PLIGOVD        ,0.0        ,"A"                                  ,"Coefficient for the length dependence of IGOV for drain side")
+                `MPRnb(PWIGOVD        ,0.0        ,"A"                                  ,"Coefficient for the width dependence of IGOV for drain side")
+                `MPRnb(PLWIGOVD       ,0.0        ,"A"                                  ,"Coefficient for the length times width dependence of IGOV for drain side")
+                `MPRnb(POSTIG         ,2.0        ,""                                   ,"Coefficient for the geometry independent part of STIG")
+                `MPRnb(POGC2          ,0.375      ,""                                   ,"Coefficient for the geometry independent part of GC2")
+                `MPRnb(POGC3          ,0.063      ,""                                   ,"Coefficient for the geometry independent part of GC3")
+                `MPRnb(POCHIB         ,3.1        ,"V"                                  ,"Coefficient for the geometry independent part of CHIB")
+
+        // Gate-induced drain leakage (GIDL) parameters
+                `MPRnb(POAGIDL        ,0.0        ,"A/V^3"                              ,"Coefficient for the geometry independent part of AGIDL")
+                `MPRnb(PLAGIDL        ,0.0        ,"A/V^3"                              ,"Coefficient for the length dependence of AGIDL")
+                `MPRnb(PWAGIDL        ,0.0        ,"A/V^3"                              ,"Coefficient for the width dependence of AGIDL")
+                `MPRnb(PLWAGIDL       ,0.0        ,"A/V^3"                              ,"Coefficient for the length times width dependence of AGIDL")
+                `MPRnb(POAGIDLD       ,0.0        ,"A/V^3"                              ,"Coefficient for the geometry independent part of AGIDL for drain side")
+                `MPRnb(PLAGIDLD       ,0.0        ,"A/V^3"                              ,"Coefficient for the length dependence of AGIDL for drain side")
+                `MPRnb(PWAGIDLD       ,0.0        ,"A/V^3"                              ,"Coefficient for the width dependence of AGIDL for drain side")
+                `MPRnb(PLWAGIDLD      ,0.0        ,"A/V^3"                              ,"Coefficient for the length times width dependence of AGIDL for drain side")
+                `MPRnb(POBGIDL        ,41.0       ,"V"                                  ,"Coefficient for the geometry independent part of BGIDL")
+                `MPRnb(POBGIDLD       ,41.0       ,"V"                                  ,"Coefficient for the geometry independent part of BGIDL for drain side")
+                `MPRnb(POSTBGIDL      ,0.0        ,"V/K"                                ,"Coefficient for the geometry independent part of STBGIDL")
+                `MPRnb(POSTBGIDLD     ,0.0        ,"V/K"                                ,"Coefficient for the geometry independent part of STBGIDL for drain side")
+                `MPRnb(POCGIDL        ,0.0        ,""                                   ,"Coefficient for the geometry independent part of CGIDL")
+                `MPRnb(POCGIDLD       ,0.0        ,""                                   ,"Coefficient for the geometry independent part of CGIDL for drain side")
+
+        // Charge model parameters
+                `MPRnb(POCOX          ,1.0e-14    ,"F"                                  ,"Coefficient for the geometry independent part of COX")
+                `MPRnb(PLCOX          ,0.0        ,"F"                                  ,"Coefficient for the length dependence of COX")
+                `MPRnb(PWCOX          ,0.0        ,"F"                                  ,"Coefficient for the width dependence of COX")
+                `MPRnb(PLWCOX         ,0.0        ,"F"                                  ,"Coefficient for the length times width dependence of COX")
+                `MPRnb(POCGOV         ,1.0e-15    ,"F"                                  ,"Coefficient for the geometry independent part of CGOV")
+                `MPRnb(PLCGOV         ,0.0        ,"F"                                  ,"Coefficient for the length dependence of CGOV")
+                `MPRnb(PWCGOV         ,0.0        ,"F"                                  ,"Coefficient for the width dependence of CGOV")
+                `MPRnb(PLWCGOV        ,0.0        ,"F"                                  ,"Coefficient for the length times width dependence of CGOV")
+                `MPRnb(POCGOVD        ,1.0e-15    ,"F"                                  ,"Coefficient for the geometry independent part of CGOV for drain side")
+                `MPRnb(PLCGOVD        ,0.0        ,"F"                                  ,"Coefficient for the length dependence of CGOV for drain side")
+                `MPRnb(PWCGOVD        ,0.0        ,"F"                                  ,"Coefficient for the width dependence of CGOV for drain side")
+                `MPRnb(PLWCGOVD       ,0.0        ,"F"                                  ,"Coefficient for the length times width dependence of CGOV for drain side")
+                `MPRnb(POCGBOV        ,0.0        ,"F"                                  ,"Coefficient for the geometry independent part of CGBOV")
+                `MPRnb(PLCGBOV        ,0.0        ,"F"                                  ,"Coefficient for the length dependence of CGBOV")
+                `MPRnb(PWCGBOV        ,0.0        ,"F"                                  ,"Coefficient for the width dependence of CGBOV")
+                `MPRnb(PLWCGBOV       ,0.0        ,"F"                                  ,"Coefficient for the length times width dependence of CGBOV")
+                `MPRnb(POCFR          ,0.0        ,"F"                                  ,"Coefficient for the geometry independent part of CFR")
+                `MPRnb(PLCFR          ,0.0        ,"F"                                  ,"Coefficient for the length dependence of CFR")
+                `MPRnb(PWCFR          ,0.0        ,"F"                                  ,"Coefficient for the width dependence of CFR")
+                `MPRnb(PLWCFR         ,0.0        ,"F"                                  ,"Coefficient for the length times width dependence of CFR")
+                `MPRnb(POCFRD         ,0.0        ,"F"                                  ,"Coefficient for the geometry independent part of CFR for drain side")
+                `MPRnb(PLCFRD         ,0.0        ,"F"                                  ,"Coefficient for the length dependence of CFR for drain side")
+                `MPRnb(PWCFRD         ,0.0        ,"F"                                  ,"Coefficient for the width dependence of CFR for drain side")
+                `MPRnb(PLWCFRD        ,0.0        ,"F"                                  ,"Coefficient for the length times width dependence of CFR for drain side")
+
+        // Noise model parameters
+                `MPRnb(POFNT          ,1.0        ,""                                   ,"Coefficient for the geometry independent part of FNT")
+                `MPRnb(POFNTEXC       ,0.0        ,""                                   ,"Coefficient for the geometry independent part of FNTEXC")
+                `MPRnb(PLFNTEXC       ,0.0        ,""                                   ,"Coefficient for the length dependence of FNTEXC")
+                `MPRnb(PWFNTEXC       ,0.0        ,""                                   ,"Coefficient for the width dependence of FNTEXC")
+                `MPRnb(PLWFNTEXC      ,0.0        ,""                                   ,"Coefficient for the length times width dependence of FNTEXC")
+                `MPRnb(PONFA          ,8.0e22     ,"V^-1/m^4"                           ,"Coefficient for the geometry independent part of NFA")
+                `MPRnb(PLNFA          ,0.0        ,"V^-1/m^4"                           ,"Coefficient for the length dependence of NFA")
+                `MPRnb(PWNFA          ,0.0        ,"V^-1/m^4"                           ,"Coefficient for the width dependence of NFA")
+                `MPRnb(PLWNFA         ,0.0        ,"V^-1/m^4"                           ,"Coefficient for the length times width dependence of NFA")
+                `MPRnb(PONFB          ,3.0e7      ,"V^-1/m^2"                           ,"Coefficient for the geometry independent part of NFB")
+                `MPRnb(PLNFB          ,0.0        ,"V^-1/m^2"                           ,"Coefficient for the length dependence of NFB")
+                `MPRnb(PWNFB          ,0.0        ,"V^-1/m^2"                           ,"Coefficient for the width dependence of NFB")
+                `MPRnb(PLWNFB         ,0.0        ,"V^-1/m^2"                           ,"Coefficient for the length times width dependence of NFB")
+                `MPRnb(PONFC          ,0.0        ,"V^-1"                               ,"Coefficient for the geometry independent part of NFC")
+                `MPRnb(PLNFC          ,0.0        ,"V^-1"                               ,"Coefficient for the length dependence of NFC")
+                `MPRnb(PWNFC          ,0.0        ,"V^-1"                               ,"Coefficient for the width dependence of NFC")
+                `MPRnb(PLWNFC         ,0.0        ,"V^-1"                               ,"Coefficient for the length times width dependence of NFC")
+                `MPRnb(POEF           ,1.0        ,""                                   ,"Coefficient for the flicker noise frequency exponent")
+
+        // Edge transistor parameters: PSP 103.4
+                `MPRnb(POVFBEDGE      ,-1.0       ,"V"                                  ,"Coefficient for the geometry independent part of VFBEDGE")
+                `MPRnb(POSTVFBEDGE    ,0.0        ,"V/K"                                ,"Coefficient for the geometry independent part of STVFBEDGE")
+                `MPRnb(PLSTVFBEDGE    ,0.0        ,"V/K"                                ,"Coefficient for the length dependence of STVFBEDGE")
+                `MPRnb(PWSTVFBEDGE    ,0.0        ,"V/K"                                ,"Coefficient for the width dependence of STVFBEDGE")
+                `MPRnb(PLWSTVFBEDGE   ,0.0        ,"V/K"                                ,"Coefficient for the length times width dependence of STVFBEDGE")
+                `MPRnb(PODPHIBEDGE    ,0.0        ,"V"                                  ,"Coefficient for the geometry independent part of DPHIBEDGE")
+                `MPRnb(PLDPHIBEDGE    ,0.0        ,"V"                                  ,"Coefficient for the length dependence of DPHIBEDGE")
+                `MPRnb(PWDPHIBEDGE    ,0.0        ,"V"                                  ,"Coefficient for the width dependence of DPHIBEDGE")
+                `MPRnb(PLWDPHIBEDGE   ,0.0        ,"V"                                  ,"Coefficient for the length times width dependence of DPHIBEDGE")
+                `MPRnb(PONEFFEDGE     ,5.0e23     ,"m^-3"                               ,"Coefficient for the geometry independent part of NEFFEDGE")
+                `MPRnb(PLNEFFEDGE     ,0.0        ,"m^-3"                               ,"Coefficient for the length dependence of NEFFEDGE")
+                `MPRnb(PWNEFFEDGE     ,0.0        ,"m^-3"                               ,"Coefficient for the width dependence of NEFFEDGE")
+                `MPRnb(PLWNEFFEDGE    ,0.0        ,"m^-3"                               ,"Coefficient for the length times width dependence of NEFFEDGE")
+                `MPRnb(POCTEDGE       ,0.0        ,""                                   ,"Coefficient for the geometry independent part of CTEDGE")
+                `MPRnb(PLCTEDGE       ,0.0        ,""                                   ,"Coefficient for the length dependence of CTEDGE")
+                `MPRnb(PWCTEDGE       ,0.0        ,""                                   ,"Coefficient for the width dependence of CTEDGE")
+                `MPRnb(PLWCTEDGE      ,0.0        ,""                                   ,"Coefficient for the length times width dependence of CTEDGE")
+                `MPRnb(POBETNEDGE     ,5.0e-4     ,"m^2/V/s"                            ,"Coefficient for the geometry independent part of BETNEDGE")
+                `MPRnb(PLBETNEDGE     ,0.0        ,"m^2/V/s"                            ,"Coefficient for the length dependence of BETNEDGE")
+                `MPRnb(PWBETNEDGE     ,0.0        ,"m^2/V/s"                            ,"Coefficient for the width dependence of BETNEDGE")
+                `MPRnb(PLWBETNEDGE    ,0.0        ,"m^2/V/s"                            ,"Coefficient for the length times width dependence of BETNEDGE")
+                `MPRnb(POSTBETEDGE    ,1.0        ,""                                   ,"Coefficient for the geometry independent part of STBETEDGE")
+                `MPRnb(PLSTBETEDGE    ,0.0        ,""                                   ,"Coefficient for the length dependence of STBETEDGE")
+                `MPRnb(PWSTBETEDGE    ,0.0        ,""                                   ,"Coefficient for the width dependence of STBETEDGE")
+                `MPRnb(PLWSTBETEDGE   ,0.0        ,""                                   ,"Coefficient for the length times width dependence of STBETEDGE")
+                `MPRnb(POPSCEEDGE     ,0.0        ,""                                   ,"Coefficient for the geometry independent part of PSCEEDGE")
+                `MPRnb(PLPSCEEDGE     ,0.0        ,""                                   ,"Coefficient for the length dependence of PSCEEDGE")
+                `MPRnb(PWPSCEEDGE     ,0.0        ,""                                   ,"Coefficient for the width dependence of PSCEEDGE")
+                `MPRnb(PLWPSCEEDGE    ,0.0        ,""                                   ,"Coefficient for the length times width dependence of PSCEEDGE")
+                `MPRnb(POPSCEBEDGE    ,0.0        ,"V^-1"                               ,"Coefficient for the geometry independent part of PSCEBEDGE")
+                `MPRnb(POPSCEDEDGE    ,0.0        ,"V^-1"                               ,"Coefficient for the geometry independent part of PSCEDEDGE")
+                `MPRnb(POCFEDGE       ,0.0        ,""                                   ,"Coefficient for the geometry independent part of CFEDGE")
+                `MPRnb(PLCFEDGE       ,0.0        ,""                                   ,"Coefficient for the length dependence of CFEDGE")
+                `MPRnb(PWCFEDGE       ,0.0        ,""                                   ,"Coefficient for the width dependence of CFEDGE")
+                `MPRnb(PLWCFEDGE      ,0.0        ,""                                   ,"Coefficient for the length times width dependence of CFEDGE")
+                `MPRnb(POCFDEDGE      ,0.0        ,"V^-1"                               ,"Coefficient for the geometry independent part of CFDEDGE")
+                `MPRnb(POCFBEDGE      ,0.0        ,"V^-1"                               ,"Coefficient for the geometry independent part of CFBEDGE")
+                `MPRnb(POFNTEDGE      ,1.0        ,""                                   ,"Coefficient for the geometry independent part of FNTEDGE")
+                `MPRnb(PONFAEDGE      ,8.0e22     ,"V^-1/m^4"                           ,"Coefficient for the geometry independent part of NFAEDGE")
+                `MPRnb(PLNFAEDGE      ,0.0        ,"V^-1/m^4"                           ,"Coefficient for the length dependence of NFAEDGE")
+                `MPRnb(PWNFAEDGE      ,0.0        ,"V^-1/m^4"                           ,"Coefficient for the width dependence of NFAEDGE")
+                `MPRnb(PLWNFAEDGE     ,0.0        ,"V^-1/m^4"                           ,"Coefficient for the length times width dependence of NFAEDGE")
+                `MPRnb(PONFBEDGE      ,3.0e7      ,"V^-1/m^2"                           ,"Coefficient for the geometry independent part of NFBEDGE")
+                `MPRnb(PLNFBEDGE      ,0.0        ,"V^-1/m^2"                           ,"Coefficient for the length dependence of NFBEDGE")
+                `MPRnb(PWNFBEDGE      ,0.0        ,"V^-1/m^2"                           ,"Coefficient for the width dependence of NFBEDGE")
+                `MPRnb(PLWNFBEDGE     ,0.0        ,"V^-1/m^2"                           ,"Coefficient for the length times width dependence of NFBEDGE")
+                `MPRnb(PONFCEDGE      ,0.0        ,"V^-1"                               ,"Coefficient for the geometry independent part of NFCEDGE")
+                `MPRnb(PLNFCEDGE      ,0.0        ,"V^-1"                               ,"Coefficient for the length dependence of NFCEDGE")
+                `MPRnb(PWNFCEDGE      ,0.0        ,"V^-1"                               ,"Coefficient for the width dependence of NFCEDGE")
+                `MPRnb(PLWNFCEDGE     ,0.0        ,"V^-1"                               ,"Coefficient for the length times width dependence of NFCEDGE")
+                `MPRnb(POEFEDGE       ,1.0        ,""                                   ,"Coefficient for the geometry independent part of EFEDGE")
+
+        // Well proximity effect parameters
+                `MPRnb(POKVTHOWE      ,0.0        ,""                                   ,"Coefficient for the geometry independent part of KVTHOWE")
+                `MPRnb(PLKVTHOWE      ,0.0        ,""                                   ,"Coefficient for the length dependence part of KVTHOWE")
+                `MPRnb(PWKVTHOWE      ,0.0        ,""                                   ,"Coefficient for the width dependence part of KVTHOWE")
+                `MPRnb(PLWKVTHOWE     ,0.0        ,""                                   ,"Coefficient for the length times width dependence part of KVTHOWE")
+                `MPRnb(POKUOWE        ,0.0        ,""                                   ,"Coefficient for the geometry independent part of KUOWE")
+                `MPRnb(PLKUOWE        ,0.0        ,""                                   ,"Coefficient for the length dependence part of KUOWE")
+                `MPRnb(PWKUOWE        ,0.0        ,""                                   ,"Coefficient for the width dependence part of KUOWE")
+                `MPRnb(PLWKUOWE       ,0.0        ,""                                   ,"Coefficient for the length times width dependence part of KUOWE")
+
+        // `Dummy' parameters for binning-set labeling
+                `MPRnb(LMIN           ,0          ,"m"                                  ,"Dummy parameter to label binning set")
+                `MPRnb(LMAX           ,1.0        ,"m"                                  ,"Dummy parameter to label binning set")
+                `MPRnb(WMIN           ,0.0        ,"m"                                  ,"Dummy parameter to label binning set")
+                `MPRnb(WMAX           ,1.0        ,"m"                                  ,"Dummy parameter to label binning set")
diff --git a/ihp-sg13g2/libs.tech/xyce/adms/PSP103_macrodefs.include b/ihp-sg13g2/libs.tech/xyce/adms/PSP103_macrodefs.include
new file mode 100644
index 00000000..46a6a632
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/adms/PSP103_macrodefs.include
@@ -0,0 +1,428 @@
+//======================================================================================
+//======================================================================================
+// Filename: PSP103_macrodefs.include
+//======================================================================================
+//======================================================================================
+//
+//  (c) Copyright notice
+//
+//  Copyright 2004-2017 NXP Semiconductors, 2015-2017 Commissariat a l’energie atomique
+//  et aux energies alternatives (CEA), 2012-2015 Delft University of Technology and
+//  2004-2011 Arizona State University Licensed under the Educational Community License,
+//  Version 2.0 (the "License"); you may not use this file except in compliance with the
+//  License. You may obtain a copy of the License at
+//  http://opensource.org/licenses/ECL-2.0
+//  Unless required by applicable law or agreed to in writing, software distributed under
+//  the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF
+//  ANY KIND, either express or implied. See the License for the specific language
+//  governing permissions and limitations under the License.
+//
+//
+//  Version: 103.6.0 (PSP), 200.5.0 (JUNCAP), December 2017
+//
+//======================================================================================
+//======================================================================================
+//
+// Further information can be found in the file releasenotesPSP103.txt
+//
+
+/////////////////////////////////////////////
+//
+// Macros and constants used in PSP
+//
+/////////////////////////////////////////////
+
+// Explicit Gmin
+`define GMIN 1E-15
+
+`define PMOS                 -1
+`define NMOS                 +1
+
+// Some functions
+`define MINA(x,y,a)           0.5*((x)+(y)-sqrt(((x)-(y))*((x)-(y))+(a)))
+`define MAXA(x,y,a)           0.5*((x)+(y)+sqrt(((x)-(y))*((x)-(y))+(a)))
+
+`define MNE(x,y,a,mne) \
+tme1    =  4.0 - (a); \
+tme2    =  (x) + (y); \
+mne     =  2.0 / tme1 * (tme2 - sqrt(tme2 * tme2 - tme1 * (x) * (y)));
+
+`define MXE(x,y,a,mxe) \
+tme1    =  4.0 - (a); \
+tme2    =  (x) + (y); \
+mxe     =  2.0 / tme1 * (tme2 + sqrt(tme2 * tme2 - tme1 * (x) * (y)));
+
+// Physical constants
+`define QMN                   5.951993
+`define QMP                   7.448711
+
+// Other constants (PSP-mos)
+`define DELTA1                0.02
+`define invSqrt2              7.0710678118654746e-01
+`define oneSixth              1.6666666666666667e-01
+`define LEN                   1.0e-6
+`define WEN                   1.0e-6
+
+
+/////////////////////////////////////////////////////////////////////////////
+//
+//  Macro definitions.
+//
+//  Note that because at present locally scoped variables
+//  can only be in named blocks, the intermediate variables
+//  used in the macros below must be explicitly declared
+//  as variables in the main code.
+//
+/////////////////////////////////////////////////////////////////////////////
+
+
+//  sigma function used in surface potential and other calculations
+//  --------------------------------------------------------------------------------------------------------------
+//  Note: one call uses expressions for arguments so parentheses around the arguments in the expressions are necessary
+`define sigma(a,c,tau,eta,y) \
+    nu           =  (a) + (c); \
+    mutau        =  nu * nu + (tau) * (0.5 * ((c) * (c)) - (a)); \
+    y            =  (eta) + (a) * nu * (tau) / (mutau + (nu / mutau) * (tau) * (tau) * (c) * ((c) * (c) * `oneThird - (a)));
+
+// modified version of sigma function, which takes 4 arguments
+//  --------------------------------------------------------------------------------------------------------------
+`define sigma2(a,b,c,tau,eta,y) \
+    nu           =  (a) + (c); \
+    mutau        =  (nu) * (nu) + (tau) * (0.5 * ((c) * (c)) - (a) * (b)); \
+    y            =  (eta) + (a) * nu * (tau) / (mutau + (nu / mutau) * (tau) * (tau) * (c) * ((c) * (c) * `oneThird - (a) * (b)));
+
+//  sp_s function: surface potential calculation
+//  --------------------------------------------------------------------------------------------------------------
+`define sp_s(sp,xg,xn,delta) \
+    if (abs(xg) <= margin) begin \
+        SP_S_temp1 =  inv_xi * inv_xi * `oneSixth * `invSqrt2; \
+        sp         =  xg * inv_xi * (1.0 + xg * (1.0 - (delta)) * Gf * SP_S_temp1); \
+    end else begin \
+        if (xg < -margin) begin \
+            SP_S_yg     = -xg; \
+            SP_S_ysub   = 1.25 * (SP_S_yg * inv_xi); \
+            SP_S_eta    = 0.5 * (SP_S_ysub + 10 - sqrt((SP_S_ysub - 6.0) * (SP_S_ysub - 6.0) + 64.0)); \
+            SP_S_temp   = SP_S_yg - SP_S_eta; \
+            SP_S_a      = SP_S_temp * SP_S_temp + Gf2*(SP_S_eta + 1.0);\
+            SP_S_c      = 2.0 * SP_S_temp - Gf2; \
+            SP_S_tau    = -SP_S_eta + ln(SP_S_a * inv_Gf2); \
+            `sigma(SP_S_a, SP_S_c, SP_S_tau, SP_S_eta, SP_S_y0) \
+            `expl_high(SP_S_y0, SP_S_delta0) \
+            SP_S_delta1 = 1.0 / SP_S_delta0; \
+            SP_S_temp   = 1.0 / (2.0 + SP_S_y0 * SP_S_y0); \
+            SP_S_xi0    = SP_S_y0 * SP_S_y0 * SP_S_temp; \
+            SP_S_xi1    = 4.0 * (SP_S_y0 * SP_S_temp * SP_S_temp); \
+            SP_S_xi2    = (8.0 * SP_S_temp - 12.0 * SP_S_xi0) * SP_S_temp * SP_S_temp; \
+            SP_S_temp   = SP_S_yg - SP_S_y0; \
+            SP_S_temp1  = (delta) * SP_S_delta1; \
+            SP_S_pC     = 2.0 * SP_S_temp + Gf2 * (SP_S_delta0 - 1.0 - SP_S_temp1 + (delta) * (1.0 - SP_S_xi1)); \
+            SP_S_qC     = SP_S_temp * SP_S_temp - Gf2 * (SP_S_delta0 - SP_S_y0 - 1.0 + SP_S_temp1 + (delta) * (SP_S_y0 - 1.0 - SP_S_xi0)); \
+            SP_S_temp   = 2.0 - Gf2 * (SP_S_delta0 + SP_S_temp1 - (delta) * SP_S_xi2); \
+            SP_S_temp   = SP_S_pC * SP_S_pC - 2.0 * (SP_S_qC * SP_S_temp); \
+            sp          = -SP_S_y0 - 2.0 * (SP_S_qC / (SP_S_pC + sqrt(SP_S_temp))); \
+        end else begin \
+            SP_xg1    = 1.0 / (1.25 + Gf * 7.324648775608221e-001); \
+            SP_S_A_fac= (xi * 1.25 * SP_xg1 - 1.0) * SP_xg1; \
+            SP_S_xbar = xg * inv_xi * (1.0 + SP_S_A_fac * xg); \
+            `expl_low(-SP_S_xbar, SP_S_temp) \
+            SP_S_w    = 1.0 - SP_S_temp; \
+            SP_S_x1   = xg + Gf2 * 0.5 - Gf * sqrt(xg + Gf2 * 0.25 - SP_S_w); \
+            SP_S_bx   = (xn) + 3.0; \
+            SP_S_eta  = `MINA(SP_S_x1, SP_S_bx, 5.0) - 0.5 * (SP_S_bx - sqrt(SP_S_bx * SP_S_bx + 5.0)); \
+            SP_S_temp = xg - SP_S_eta; \
+            SP_S_temp1= exp(-SP_S_eta); \
+            SP_S_temp2= 1.0 / (2.0 + SP_S_eta * SP_S_eta); \
+            SP_S_xi0  = SP_S_eta * SP_S_eta * SP_S_temp2; \
+            SP_S_xi1  = 4.0 * (SP_S_eta * SP_S_temp2 * SP_S_temp2); \
+            SP_S_xi2  = (8.0 * SP_S_temp2 - 12.0 * SP_S_xi0) * SP_S_temp2 * SP_S_temp2; \
+            SP_S_a    = max(1.0e-40, SP_S_temp * SP_S_temp - Gf2 * (SP_S_temp1 + SP_S_eta - 1.0 - (delta) * (SP_S_eta + 1.0 + SP_S_xi0))); \
+            SP_S_b    = 1.0 - 0.5 * (Gf2 * (SP_S_temp1 - (delta) * SP_S_xi2)); \
+            SP_S_c    = 2.0 * SP_S_temp + Gf2 * (1.0 - SP_S_temp1 - (delta) * (1.0 + SP_S_xi1)); \
+            SP_S_tau  = (xn) - SP_S_eta + ln(SP_S_a / Gf2); \
+            `sigma2(SP_S_a, SP_S_b, SP_S_c, SP_S_tau, SP_S_eta, SP_S_x0) \
+            if (SP_S_x0 < `se05) begin \
+                SP_S_delta0 = exp(SP_S_x0); \
+                SP_S_delta1 = 1.0 / SP_S_delta0; \
+                SP_S_delta0 = (delta) * SP_S_delta0; \
+            end else begin \
+                if (SP_S_x0 > (xn) - `se05) begin \
+                    SP_S_delta0 = exp(SP_S_x0 - (xn)); \
+                    SP_S_delta1 = (delta) / SP_S_delta0; \
+                end else begin \
+                    SP_S_delta0 = `ke05 / `P3((xn) - SP_S_x0 - `se05); \
+                    SP_S_delta1 = `ke05 / `P3(SP_S_x0 - `se05); \
+                end \
+            end \
+            SP_S_temp   = 1.0 / (2.0 + SP_S_x0 * SP_S_x0); \
+            SP_S_xi0    = SP_S_x0 * SP_S_x0 * SP_S_temp; \
+            SP_S_xi1    = 4.0 * (SP_S_x0 * SP_S_temp * SP_S_temp); \
+            SP_S_xi2    = (8.0 * SP_S_temp - 12.0 * SP_S_xi0) * SP_S_temp * SP_S_temp; \
+            SP_S_temp   = xg - SP_S_x0; \
+            SP_S_pC     = 2.0 * SP_S_temp + Gf2 * (1.0 - SP_S_delta1 + SP_S_delta0 - (delta) * (1.0 + SP_S_xi1)); \
+            SP_S_qC     = SP_S_temp * SP_S_temp - Gf2 * (SP_S_delta1 + SP_S_x0 - 1.0 + SP_S_delta0 - (delta) * (SP_S_x0 + 1.0 + SP_S_xi0)); \
+            SP_S_temp   = 2.0 - Gf2 * (SP_S_delta1 + SP_S_delta0 - (delta) * SP_S_xi2); \
+            SP_S_temp   = SP_S_pC * SP_S_pC - 2.0 * (SP_S_qC * SP_S_temp); \
+            sp          = SP_S_x0 + 2.0 * (SP_S_qC / (SP_S_pC + sqrt(SP_S_temp))); \
+        end \
+    end
+
+//  sp_s_d function: surface potential calculation at drain (subset of function sp_s)
+//  --------------------------------------------------------------------------------------------------------------
+`define sp_s_d(sp,xg,xn,delta) \
+    if (abs(xg) <= margin) begin \
+        SP_S_temp1 =  inv_xi * inv_xi * `oneSixth * `invSqrt2; \
+        sp         =  xg * inv_xi * (1.0 + xg * (1.0 - (delta)) * Gf * SP_S_temp1); \
+    end else begin \
+        SP_S_bx   = (xn) + 3; \
+        SP_S_eta  = `MINA(SP_S_x1, SP_S_bx, 5.0) - 0.5 * (SP_S_bx - sqrt(SP_S_bx * SP_S_bx + 5.0)); \
+        SP_S_temp = xg - SP_S_eta; \
+        SP_S_temp1= exp(-SP_S_eta); \
+        SP_S_temp2= 1.0 / (2.0 + SP_S_eta * SP_S_eta); \
+        SP_S_xi0  = SP_S_eta * SP_S_eta * SP_S_temp2; \
+        SP_S_xi1  = 4.0 * (SP_S_eta * SP_S_temp2 * SP_S_temp2); \
+        SP_S_xi2  = (8.0 * SP_S_temp2 - 12.0 * SP_S_xi0) * SP_S_temp2 * SP_S_temp2; \
+        SP_S_a    = max(1.0e-40, SP_S_temp * SP_S_temp - Gf2 * (SP_S_temp1 + SP_S_eta - 1.0 - (delta) * (SP_S_eta + 1.0 + SP_S_xi0))); \
+        SP_S_b    = 1.0 - 0.5 * (Gf2 * (SP_S_temp1 - (delta) * SP_S_xi2)); \
+        SP_S_c    = 2.0 * SP_S_temp + Gf2 * (1.0 - SP_S_temp1 - (delta) * (1.0 + SP_S_xi1)); \
+        SP_S_tau  = (xn) - SP_S_eta + ln(SP_S_a / Gf2); \
+        `sigma2(SP_S_a, SP_S_b, SP_S_c, SP_S_tau, SP_S_eta, SP_S_x0) \
+        if (SP_S_x0 < `se05) begin \
+                        SP_S_delta0 = exp(SP_S_x0); \
+                        SP_S_delta1 = 1.0 / SP_S_delta0; \
+                        SP_S_delta0 = (delta) * SP_S_delta0; \
+                end else begin \
+                        if (SP_S_x0 > (xn) - `se05) begin \
+                                SP_S_delta0 = exp(SP_S_x0 - (xn)); \
+                                SP_S_delta1 = (delta) / SP_S_delta0; \
+                        end else begin \
+                                SP_S_delta0 = `ke05 / `P3((xn) - SP_S_x0 - `se05); \
+                                SP_S_delta1 = `ke05 / `P3(SP_S_x0 - `se05); \
+                        end \
+        end \
+        SP_S_temp   = 1.0 / (2.0 + SP_S_x0 * SP_S_x0); \
+        SP_S_xi0    = SP_S_x0 * SP_S_x0 * SP_S_temp; \
+        SP_S_xi1    = 4.0 * (SP_S_x0 * SP_S_temp * SP_S_temp); \
+        SP_S_xi2    = (8.0 * SP_S_temp-12.0 * SP_S_xi0) * SP_S_temp * SP_S_temp; \
+        SP_S_temp   = xg - SP_S_x0; \
+        SP_S_pC     = 2.0 * SP_S_temp + Gf2 * (1.0 - SP_S_delta1 + SP_S_delta0 - (delta) * (1.0 + SP_S_xi1)); \
+        SP_S_qC     = SP_S_temp * SP_S_temp - Gf2 * (SP_S_delta1 + SP_S_x0 - 1.0 + SP_S_delta0 - (delta) * (SP_S_x0 + 1.0 + SP_S_xi0)); \
+        SP_S_temp   = 2.0 - Gf2*(SP_S_delta1+SP_S_delta0-(delta)*SP_S_xi2); \
+        SP_S_temp   = SP_S_pC * SP_S_pC - 2.0 * (SP_S_qC * SP_S_temp); \
+        sp          = SP_S_x0 + 2.0 * (SP_S_qC / (SP_S_pC + sqrt(SP_S_temp)));\
+        end
+
+//  sp_ovInit function: surface potential calculation for the overlap regions initialization
+//  --------------------------------------------------------------------------------------------------------------
+`define sp_ovInit(GOV, GOV2, SP_OV_eps2, SP_OV_a, SP_OV_delta1) \
+    inv_GOV     =  1.0 / GOV; \
+    SP_OV_eps   =  3.1 * GOV + 8.5; \
+    SP_OV_eps2  =  SP_OV_eps * SP_OV_eps; \
+    SP_OV_delta =  0.5 * SP_OV_eps; \
+    if (inv_GOV < 0.06) begin \
+        SP_OV_a     =  64.0 * inv_GOV; \
+    end else begin \
+        if (inv_GOV <= 0.45) begin \
+            SP_OV_a     =  22.0 * inv_GOV + 3.0; \
+        end else begin \
+            if (inv_GOV <= 1.6) begin \
+                SP_OV_a     = -7.2 * inv_GOV + 15.5; \
+            end else begin \
+                SP_OV_a     = GOV; \
+            end \
+        end \
+    end \
+    SP_OV_delta1 = SP_OV_delta + GOV2 * 0.5 - GOV * sqrt(SP_OV_delta + GOV2 * 0.25 + SP_OV_a);
+
+//  qi_edge    charge calculation for the edge transistor
+//  --------------------------------------------------------------------------------------------------------------
+`define qi_edge(qieff_edge,xg_edge,xn_edge) \
+    Q_EDGE_xsth  =  xbedge + xn_edge; \
+    Q_EDGE_xth0  =  Q_EDGE_xsth +  Gfedge * sqrt(Q_EDGE_xsth); \
+    Q_EDGE_xth   =  Q_EDGE_xth0 + dxthedge; \
+    Q_EDGE_n     =  1.0 + Gfedge / (2.0 * sqrt(Q_EDGE_xsth)); \
+    Q_EDGE_n_inv =  1.0 / Q_EDGE_n; \
+    Q_EDGE_xgt   =  xg_edge - Q_EDGE_xth; \
+    if (Q_EDGE_xgt > -12.0) begin \
+        Q_EDGE_xgt0  =  Q_EDGE_xgt + lnGfedge2 - 1.0; \
+        Q_EDGE_xgt0e =  0.5 * (Q_EDGE_xgt0 + sqrt(Q_EDGE_xgt0 * Q_EDGE_xgt0 + 10.0)); \
+        Q_EDGE_qi0si =  Q_EDGE_xgt - Q_EDGE_n * ln(Q_EDGE_xgt0e) + lnGfedge2; \
+        Q_EDGE_qi0   =  0.5 * (Q_EDGE_qi0si + sqrt(Q_EDGE_qi0si * Q_EDGE_qi0si + 2.0)); \
+        `expl_high((Q_EDGE_xgt - Q_EDGE_qi0), Q_EDGE_exp_x) \
+        Q_EDGE_d0    =  Gfedge2 * Q_EDGE_exp_x; \
+        Q_EDGE_d0p   =  pow(Q_EDGE_d0, Q_EDGE_n_inv); \
+        Q_EDGE_sqerr =  Q_EDGE_n * Q_EDGE_n + (2.0 * (Q_EDGE_qi0 + Q_EDGE_n) - Q_EDGE_d0p) * Q_EDGE_d0p; \
+        Q_EDGE_errq  =  Q_EDGE_n * ((sqrt(Q_EDGE_sqerr) - Q_EDGE_n) / Q_EDGE_d0p - 1.0); \
+        qieff_edge   =  Q_EDGE_qi0 - Q_EDGE_errq; \
+    end else begin \
+        `expl_low((Q_EDGE_n_inv * (Q_EDGE_xgt + lnGfedge2)), qieff_edge) \
+    end
+
+//  CollapsableR macro: used for parasitic resistances
+//  --------------------------------------------------------------------------------------------------------------
+//  Note: if R=0, the Verilog-A compiler should recognize that the corresponding nodes can be collapsed
+`define CollapsableR(G, R, SN, N1, N2, Rname) \
+    if ((R) > 0.0) begin \
+       I(N1, N2) <+ MULT_i * (G) * V(N1, N2); \
+       /* line below can be removed if compiler issue occurs */ \
+       I(N1, N2) <+ white_noise(MULT_i * SN, Rname); \
+    end else begin \
+       V(N1, N2) <+ 0.0; \
+    end
+
+//  Local variable declaration (used in SPcalc_dc/SPcalc_ac sections, PSP103_SPCalculation.include and SP macro)
+//  --------------------------------------------------------------------------------------------------------------
+`define SPcalcLocalVarDecl \
+    real phib, G_0, Vsbstar; \
+    real Vsbx, xg, Dnsub, Gf, Gf2, inv_Gf2, xi, inv_xi, Ux, xn_s, delta_ns, margin, x_s, delta_1s, xi0s, xi1s; \
+    real xi2s, Es, Ds, Ps, Rxcor, xgs, qis, qbs, rhob, GR, Eeffm, Mutmp, Gmob, xitsb, wsat, thesat1, phi_inf; \
+    real ysat, za, Phi_0, asat, Phi_2, Phi_0_2, Phi0_Phi2, Phi_sat, Vdse, Udse, xn_d, k_ds, delta_nd, x_d, x_ds; \
+    real pC, qC, dps, xi0d, Ed, Dd, x_m, Em, D_bar, Dm, Pm, xgm, eta_p, sqm, alpha, d0, x_pm, p_pd, q_pd, xi_pd; \
+    real u_pd, km, km0, qim, qim1, qbm, qeff, qeff1, s1, dL, GdL, Gmob_dL, zsat, Gvsat, Gvsatinv, Voxm, alpha1, H; \
+    real SP_S_temp, SP_S_temp1, SP_S_temp2; \
+    real SP_S_yg, SP_S_ysub, SP_S_eta, SP_S_a, SP_S_c, SP_S_tau, SP_S_y0, SP_S_delta0, SP_S_delta1, SP_S_xi0; \
+    real SP_S_xi1, SP_S_xi2, SP_S_pC, SP_S_qC, SP_xg1, SP_S_A_fac, SP_S_xbar, SP_S_w, SP_S_x1, SP_S_bx, SP_S_b; \
+    real SP_S_x0;
+
+//  TempInitialize macro: initialize the temperature dependent variables
+//  --------------------------------------------------------------------------------------------------------------
+`define TempInitialize \
+    TKD_sq     =  TKD * TKD; \
+    delT       =  TKD - TKR; \
+    rTn        =  TKR / TKD; \
+    ln_rTn     =  ln(rTn); \
+    phit       =  TKD * `KBOL / `QELE; \
+    inv_phit   =  1.0 / phit; \
+    Eg         =  1.179 - 9.025e-5 * TKD - 3.05e-7 * TKD_sq; \
+    phibFac    =  (1.045 + 4.5e-4 * TKD) * (0.523 + 1.4e-3 * TKD - 1.48e-6 * TKD_sq) * TKD_sq / 9.0E4; \
+    phibFac    =  `MAX(phibFac, 1.0E-3); \
+ \
+    /* parameter for white noise of parasitic resistances */ \
+    nt0        =  4.0 * `KBOL * TKD;
+
+//  TempScaling macro: calculation of temperature dependent variables
+//  --------------------------------------------------------------------------------------------------------------
+`define TempScaling \
+    phib_dc    =  Eg + DPHIB_i + 2.0 * phit * ln(NEFF_i * pow(phibFac, -0.75) * 4.0e-26); \
+    phib_dc    =  `MAX(phib_dc, 5.0E-2); \
+    G_0_dc     =  sqrt(2.0 * `QELE * NEFF_i * EPSSI * inv_phit) / CoxPrime; \
+ \
+    /* Poly-silicon depletion */ \
+    kp         =  0.0; \
+    np         =  0.0; \
+    if (NP_i > 0.0) begin \
+        arg2max    =  8.0e7 / tox_sq; \
+        np         = `MAX(NP_i, arg2max); \
+        np         = `MAX(5.0e24, np); \
+        kp         =  2.0 * CoxPrime * CoxPrime * phit / (`QELE * np * EPSSI); \
+    end \
+ \
+    /* QM corrections */ \
+    qlim2      =  100.0 * phit * phit; \
+    if (QMC_i > 0.0) begin \
+        qb0           =  sqrt(phit * G_0_dc * G_0_dc * phib_dc); \
+        dphibq        =  0.75 * qq * pow(qb0, `twoThirds); \
+        phib_dc       =  phib_dc + dphibq; \
+        G_0_dc        =  G_0_dc * (1.0 + 2.0 * `twoThirds * dphibq / qb0); \
+    end \
+    sqrt_phib_dc =  sqrt(phib_dc); \
+    phix_dc      =  0.95 * phib_dc; \
+    aphi_dc      =  0.0025 * phib_dc * phib_dc; \
+    bphi_dc      =  aphi_dc; \
+    phix2        =  0.5 * sqrt(bphi_dc); \
+    phix1_dc     =  `MINA(phix_dc - phix2, 0.0, aphi_dc); \
+    alpha_b      =  0.5 * (phib_dc + Eg); \
+    us1          =  sqrt(VSBNUD_i + phib_dc) - sqrt_phib_dc; \
+    us21         =  sqrt(VSBNUD_i + DVSBNUD_i + phib_dc) - sqrt_phib_dc - us1; \
+ \
+    /* Additional variables for separate surface potential calculation for CV */ \
+    phib_ac    =  Eg + DPHIB_i + DELVTAC_i + 2.0 * phit * ln(NEFFAC_i * pow(phibFac, -0.75) * 4.0e-26); \
+    phib_ac    =  `MAX(phib_ac, 5.0E-2); \
+    G_0_ac     =  sqrt(2.0 * `QELE * NEFFAC_i * EPSSI * inv_phit) / CoxPrime; \
+ \
+    if (QMC_i > 0.0) begin \
+        qb0        =  sqrt(phit * G_0_ac * G_0_ac * phib_ac); \
+        dphibq     =  0.75 * qq * pow(qb0, `twoThirds); \
+        phib_ac    =  phib_ac + dphibq; \
+        G_0_ac     =  G_0_ac * (1.0 + 2.0 * `twoThirds * dphibq / qb0); \
+    end \
+ \
+    phix_ac    =  0.95 * phib_ac; \
+    aphi_ac    =  0.0025 * phib_ac * phib_ac; \
+    bphi_ac    =  aphi_ac; \
+    phix2      =  0.5 * sqrt(bphi_ac); \
+    phix1_ac   =  `MINA(phix_ac - phix2, 0.0, aphi_ac); \
+ \
+    /* Temperature scaling of parameters*/ \
+    VFB_T      =  VFB_i + STVFB_i * delT * (1.0 + ST2VFB_i * delT)+ DELVTO_i; \
+ \
+     /* Interface states parameters*/ \
+    tf_ct     =  exp(STCT_i * ln_rTn); \
+    CT_T      =  CT_i * tf_ct; \
+    CTG_T     =  CTG_i / rTn; \
+ \
+    /* Mobility parameters */ \
+    tf_bet     =  exp(STBET_i * ln_rTn); \
+    BETN_T     =  BETN_i * tf_bet; \
+    BET_i      =  FACTUO_i * BETN_T * CoxPrime; \
+    THEMU_T    =  THEMU_i * exp(STTHEMU_i * ln_rTn); \
+    tf_mue     =  exp(STMUE_i * ln_rTn); \
+    MUE_T      =  MUE_i * tf_mue; \
+    THECS_T    =  THECS_i * exp(STTHECS_i * ln_rTn); \
+    tf_cs      =  exp(STCS_i * ln_rTn); \
+    CS_T       =  CS_i * tf_cs; \
+    tf_xcor    =  exp(STXCOR_i * ln_rTn); \
+    XCOR_T     =  XCOR_i * tf_xcor; \
+ \
+    /* Series resistance */ \
+    tf_ther    =  exp(STRS_i * ln_rTn); \
+    RS_T       =  RS_i * tf_ther; \
+    THER_i     =  2.0 * BET_i * RS_T; \
+ \
+    /* Velocity saturation */ \
+    tf_thesat  =  exp(STTHESAT_i * ln_rTn); \
+    THESAT_T   =  THESAT_i * tf_thesat; \
+ \
+    /* Impact ionization */ \
+    A2_T       =  A2_i * exp(-STA2_i * ln_rTn); \
+ \
+    /* Noise */ \
+    nt         =  FNT_i * 4.0 * `KBOL * TKD; \
+    Sfl_prefac =  phit * phit * BET_i / Cox_over_q; \
+ \
+    /* Edge transistor */ \
+    if ((SWEDGE_i != 0.0) && (BETNEDGE_i > 0.0)) begin \
+        VFBEDGE_T  =  VFBEDGE_i + STVFBEDGE_i * delT + DELVTOEDGE_i; \
+        tf_betedge =  exp(STBETEDGE_i * ln_rTn); \
+        BETNEDGE_T =  BETNEDGE_i * tf_betedge; \
+        BETEDGE_i  =  FACTUOEDGE_i * BETNEDGE_T * CoxPrime; \
+        phit0edge  =  phit * (1.0 + CTEDGE_i * rTn); \
+        phibedge   =  Eg + DPHIBEDGE_i + 2.0 * phit0edge * ln(NEFFEDGE_i * pow(phibFac, -0.75) * 4.0e-26); \
+        phibedge   = `MAX(phibedge, 5.0E-2); \
+        Gfedge     =  sqrt(2.0 * `QELE * NEFFEDGE_i * EPSSI * inv_phit) / CoxPrime; \
+        Gfedge2    =  Gfedge * Gfedge; \
+        lnGfedge2  =  ln(Gfedge2); \
+        phixedge   =  0.95 * phibedge; \
+        aphiedge   =  0.0025 * phibedge * phibedge; \
+        bphiedge   =  aphiedge; \
+        phix2edge  =  0.5 * sqrt(bphiedge); \
+        phix1edge  = `MINA(phixedge - phix2edge, 0.0, aphiedge); \
+        Sfl_prefac_edge =  phit * phit * BETEDGE_i / Cox_over_q; \
+        ntedge     =  FNTEDGE_i * 4.0 * `KBOL * TKD; \
+    end else begin \
+        VFBEDGE_T  =  0.0; \
+        tf_betedge =  1.0; \
+        BETNEDGE_T =  0.0; \
+        BETEDGE_i  =  0.0; \
+        phit0edge  =  phit; \
+        phibedge   =  0.0; \
+        Gfedge     =  1.0; \
+        Gfedge2    =  1.0; \
+        lnGfedge2  =  0.0; \
+        phixedge   =  0.0; \
+        aphiedge   =  0.0; \
+        bphiedge   =  0.0; \
+        phix2edge  =  0.0; \
+        phix1edge  =  0.0; \
+        Sfl_prefac_edge =  0.0; \
+        ntedge     = 1.0; \
+    end
diff --git a/ihp-sg13g2/libs.tech/xyce/adms/PSP103_module.include b/ihp-sg13g2/libs.tech/xyce/adms/PSP103_module.include
new file mode 100644
index 00000000..e2f9b462
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/adms/PSP103_module.include
@@ -0,0 +1,3273 @@
+//======================================================================================
+//======================================================================================
+// Filename: PSP103_module.include
+//======================================================================================
+//======================================================================================
+//
+//  (c) Copyright notice
+//
+//  Copyright 2004-2017 NXP Semiconductors, 2015-2017 Commissariat a l’energie atomique
+//  et aux energies alternatives (CEA), 2012-2015 Delft University of Technology and
+//  2004-2011 Arizona State University Licensed under the Educational Community License,
+//  Version 2.0 (the "License"); you may not use this file except in compliance with the
+//  License. You may obtain a copy of the License at
+//  http://opensource.org/licenses/ECL-2.0
+//  Unless required by applicable law or agreed to in writing, software distributed under
+//  the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF
+//  ANY KIND, either express or implied. See the License for the specific language
+//  governing permissions and limitations under the License.
+//
+//
+//  Version: 103.6.0 (PSP), 200.5.0 (JUNCAP), December 2017
+//
+//======================================================================================
+//======================================================================================
+//
+// Further information can be found in the file releasenotesPSP103.txt
+//
+//  --------------------------------------------------------------------------------------------------------------
+//  Node definitions
+//  --------------------------------------------------------------------------------------------------------------
+
+`ifdef SelfHeating
+    inout      D, G, S, B, DT;
+`else // SelfHeating
+    inout      D, G, S, B;
+`endif // SelfHeating
+electrical D;
+electrical G;
+electrical S;
+electrical B;
+`ifdef SelfHeating
+    thermal DT;
+    branch     (DT) br_rth, br_ith;
+`endif // SelfHeating
+
+// Internal nodes and branches for correlated drain and gate noise
+electrical NOI;
+branch (NOI) NOII;
+branch (NOI) NOIR;
+branch (NOI) NOIC;
+
+// Internal nodes for gate and bulk resistors
+electrical GP;
+electrical SI;
+electrical DI;
+electrical BP;
+electrical BI;
+electrical BS;
+electrical BD;
+
+// Internal nodes and branches for spline collocation (NQS)
+`ifdef NQSmodel
+    electrical INT1;
+    electrical INT2;
+    electrical INT3;
+    electrical INT4;
+    electrical INT5;
+    electrical INT6;
+    electrical INT7;
+    electrical INT8;
+    electrical INT9;
+    branch(INT1) SPLINE1;
+    branch(INT2) SPLINE2;
+    branch(INT3) SPLINE3;
+    branch(INT4) SPLINE4;
+    branch(INT5) SPLINE5;
+    branch(INT6) SPLINE6;
+    branch(INT7) SPLINE7;
+    branch(INT8) SPLINE8;
+    branch(INT9) SPLINE9;
+    branch(INT1) RES1;
+    branch(INT2) RES2;
+    branch(INT3) RES3;
+    branch(INT4) RES4;
+    branch(INT5) RES5;
+    branch(INT6) RES6;
+    branch(INT7) RES7;
+    branch(INT8) RES8;
+    branch(INT9) RES9;
+`endif // NQSmodel
+
+//  --------------------------------------------------------------------------------------------------------------
+//  Special model parameters and switch parameters
+//  --------------------------------------------------------------------------------------------------------------
+
+//  Special model parameters, some are also simulator global variables
+`MPInb(LEVEL          ,103        ,""                                   ,"Model level")
+`MPIty(TYPE           ,1          ,""                                   ,"Channel type parameter, +1=NMOS -1=PMOS")
+`MPRco(TR             ,21.0       ,"C"        ,-273.0      ,inf         ,"nominal (reference) temperature")
+
+//  Switch parameters that turn models or effects on or off
+`MPIcc(SWGEO          ,1          ,""         ,0           ,2           ,"Flag for geometrical model, 0=local, 1=global, 2=binning")
+`MPIcc(SWIGATE        ,0          ,""         ,0           ,1           ,"Flag for gate current, 0=turn off IG")
+`MPIcc(SWIMPACT       ,0          ,""         ,0           ,1           ,"Flag for impact ionization current, 0=turn off II")
+`MPIcc(SWGIDL         ,0          ,""         ,0           ,1           ,"Flag for GIDL current, 0=turn off IGIDL")
+`MPIcc(SWJUNCAP       ,0          ,""         ,0           ,3           ,"Flag for juncap, 0=turn off juncap")
+`MPIcc(SWJUNASYM      ,0          ,""         ,0           ,1           ,"Flag for asymmetric junctions; 0=symmetric, 1=asymmetric")
+`MPIcc(SWNUD          ,0          ,""         ,0           ,2           ,"Flag for NUD-effect; 0=off, 1=on, 2=on+CV-correction")
+`MPIcc(SWEDGE         ,0          ,""         ,0           ,1           ,"Flag for drain current of edge transistors; 0=off, 1=on")
+`MPIcc(SWDELVTAC      ,0          ,""         ,0           ,1           ,"Flag for separate capacitance calculation; 0=off, 1=on")
+`MPIcc(SWIGN          ,1          ,""         ,0           ,1           ,"Flag for induced gate noise; 0=off, 1=on")
+`ifdef NQSmodel
+    `MPIcc(SWNQS          ,0          ,""         ,0           ,9           ,"Flag for NQS, 0=off, 1, 2, 3, 5, or 9=number of collocation points")
+`endif // NQSmodel
+`MPRcz(QMC            ,1.0        ,""                                   ,"Quantum-mechanical correction factor")
+
+//  --------------------------------------------------------------------------------------------------------------
+//  Instance parameters
+//  --------------------------------------------------------------------------------------------------------------
+
+// Instance parameters for global and binning models only
+`IPRco(L              ,1.0e-5     ,"m"        ,1.0e-9      ,inf         ,"Design length")
+`IPRco(W              ,1.0e-5     ,"m"        ,1.0e-9      ,inf         ,"Design width")
+`IPRnb(SA             ,0.0        ,"m"                                  ,"Distance between OD-edge and poly from one side")
+`IPRnb(SB             ,0.0        ,"m"                                  ,"Distance between OD-edge and poly from other side")
+`IPRnb(SD             ,0.0        ,"m"                                  ,"Distance between neighbouring fingers")
+`IPRcz(SCA            ,0.0        ,""                                   ,"Integral of the first distribution function for scattered well dopants")
+`IPRcz(SCB            ,0.0        ,""                                   ,"Integral of the second distribution function for scattered well dopants")
+`IPRcz(SCC            ,0.0        ,""                                   ,"Integral of the third distribution function for scattered well dopants")
+`IPRnb(SC             ,0.0        ,"m"                                  ,"Distance between OD-edge and nearest well edge")
+`IPIco(NF             ,1          ,""         ,1           ,inf         ,"Number of fingers")
+`IPRcc(NGCON          ,1.0        ,""         ,1.0         ,2.0         ,"Number of gate contacts")
+`IPRnb(XGW            ,1.0e-7     ,"m"                                  ,"Distance from the gate contact to the channel edge")
+`IPRnb(NRS            ,0.0        ,""                                   ,"Number of squares of source diffusion")
+`IPRnb(NRD            ,0.0        ,""                                   ,"Number of squares of drain diffusion")
+
+// Instance parameters for local model only
+`IPRco(JW             ,1.0e-6     ,"m"        ,`LG_cliplow ,inf         ,"Gate-edge length of source/drain junction")
+
+// Instance parameters for global, binning, and local models
+`IPRnb(DELVTO         ,0.0        ,"V"                                  ,"Threshold voltage shift parameter")
+`IPRcz(FACTUO         ,1.0        ,""                                   ,"Zero-field mobility pre-factor")
+`IPRnb(DELVTOEDGE     ,0.0        ,"V"                                  ,"Threshold voltage shift parameter of edge transistor")
+`IPRcz(FACTUOEDGE     ,1.0        ,""                                   ,"Zero-field mobility pre-factor of edge transistor")
+`IPRco(ABSOURCE       ,1.0e-12    ,"m^2"      ,`AB_cliplow ,inf         ,"Bottom area of source junction")
+`IPRco(LSSOURCE       ,1.0e-6     ,"m"        ,`LS_cliplow ,inf         ,"STI-edge length of source junction")
+`IPRco(LGSOURCE       ,1.0e-6     ,"m"        ,`LG_cliplow ,inf         ,"Gate-edge length of source junction")
+`IPRco(ABDRAIN        ,1.0e-12    ,"m^2"      ,`AB_cliplow ,inf         ,"Bottom area of drain junction")
+`IPRco(LSDRAIN        ,1.0e-6     ,"m"        ,`LS_cliplow ,inf         ,"STI-edge length of drain junction")
+`IPRco(LGDRAIN        ,1.0e-6     ,"m"        ,`LG_cliplow ,inf         ,"Gate-edge length of drain junction")
+`IPRco(AS             ,1.0e-12    ,"m^2"      ,`AB_cliplow ,inf         ,"Bottom area of source junction")
+`IPRco(PS             ,1.0e-6     ,"m"        ,`LS_cliplow ,inf         ,"Perimeter of source junction")
+`IPRco(AD             ,1.0e-12    ,"m^2"      ,`AB_cliplow ,inf         ,"Bottom area of drain junction")
+`IPRco(PD             ,1.0e-6     ,"m"        ,`LS_cliplow ,inf         ,"Perimeter of drain junction")
+`IPRco(MULT           ,1.0        ,""         ,0.0         ,inf         ,"Number of devices in parallel")
+
+//  --------------------------------------------------------------------------------------------------------------
+//  PSP local model parameters
+//  --------------------------------------------------------------------------------------------------------------
+
+//  Process parameters
+`MPRnb(VFB            ,-1.0       ,"V"                                  ,"Flat band voltage at TR")
+`MPRnb(STVFB          ,5.0e-4     ,"V/K"                                ,"Temperature dependence of VFB")
+`MPRnb(ST2VFB         ,0.0        ,"K^-1"                               ,"Quadratic temperature dependence of VFB")
+`MPRco(TOX            ,2.0e-09    ,"m"        ,1.0e-10     ,inf         ,"Gate oxide thickness")
+`MPRco(EPSROX         ,3.9        ,""         ,1.0         ,inf         ,"Relative permittivity of gate dielectric")
+`MPRcc(NEFF           ,5.0e23     ,"m^-3"     ,1.0e20      ,1.0e26      ,"Effective substrate doping")
+`MPRcz(FACNEFFAC      ,1.0        ,""                                   ,"Pre-factor for effective substrate doping in separate charge calculation")
+`MPRco(GFACNUD        ,1.0        ,""         ,0.01        ,inf         ,"Body-factor change due to NUD-effect")
+`MPRcz(VSBNUD         ,0.0        ,"V"                                  ,"Lower Vsb value for NUD-effect")
+`MPRco(DVSBNUD        ,1.0        ,"V"        ,0.1         ,inf         ,"Vsb-range for NUD-effect")
+`MPRnb(VNSUB          ,0.0        ,"V"                                  ,"Effective doping bias-dependence parameter")
+`MPRco(NSLP           ,0.05       ,"V"        ,1.0e-3      ,inf         ,"Effective doping bias-dependence parameter")
+`MPRcc(DNSUB          ,0.0        ,"V^-1"     ,0.0         ,1.0         ,"Effective doping bias-dependence parameter")
+`MPRnb(DPHIB          ,0.0        ,"V"                                  ,"Offset parameter for PHIB")
+`MPRnb(DELVTAC        ,0.0        ,"V"                                  ,"Offset parameter for PHIB in separate charge calculation")
+`MPRcz(NP             ,1.0e26     ,"m^-3"                               ,"Gate poly-silicon doping")
+`MPRco(TOXOV          ,2.0e-09    ,"m"        ,1.0e-10     ,inf         ,"Overlap oxide thickness")
+`MPRco(TOXOVD         ,2.0e-09    ,"m"        ,1.0e-10     ,inf         ,"Overlap oxide thickness for drain side")
+`MPRcc(NOV            ,5.0e25     ,"m^-3"     ,1.0e23      ,1.0e27      ,"Effective doping of overlap region")
+`MPRcc(NOVD           ,5.0e25     ,"m^-3"     ,1.0e23      ,1.0e27      ,"Effective doping of overlap region for drain side")
+
+//  Interface states parameters: PSP 103.6
+`MPRcz(CT             ,0.0        ,""                                   ,"Interface states factor")
+`MPRcz(CTG            ,0.0        ,""                                   ,"Gate voltage dependence of interface states factor")
+`MPRnb(CTB            ,0.0        ,""                                   ,"Bulk voltage dependence of interface states factor")
+`MPRnb(STCT           ,1.0        ,""                                   ,"Geometry-independent temperature dependence of CT")
+
+//  DIBL parameters
+`MPRcz(CF             ,0.0        ,""                                   ,"DIBL-parameter")
+`MPRcz(CFD            ,0.0        ,"V^-1"                               ,"Drain voltage dependence of CF")
+`MPRcc(CFB            ,0.0        ,"V^-1"     ,0.0         ,1.0         ,"Back bias dependence of CF")
+
+//  Subthreshold slope parameters of short channel transistor
+`MPRcz(PSCE           ,0.0        ,""                                   ,"Subthreshold slope coefficient for short channel transistor")
+`MPRcc(PSCEB          ,0.0        ,"V^-1"     ,0.0         ,1.0         ,"Bulk voltage dependence parameter of subthreshold slope coefficient for short channel transistor")
+`MPRcz(PSCED          ,0.0        ,"V^-1"                               ,"Drain voltage dependence parameter of subthreshold slope coefficient for short channel transistor")
+
+//  Mobility parameters
+`MPRcz(BETN           ,7.0e-2     ,"m^2/V/s"                            ,"Channel aspect ratio times zero-field mobility")
+`MPRnb(STBET          ,1.0        ,""                                   ,"Temperature dependence of BETN")
+`MPRcz(MUE            ,0.5        ,"m/V"                                ,"Mobility reduction coefficient at TR")
+`MPRnb(STMUE          ,0.0        ,""                                   ,"Temperature dependence of MUE")
+`MPRcz(THEMU          ,1.5        ,""                                   ,"Mobility reduction exponent at TR")
+`MPRnb(STTHEMU        ,1.5        ,""                                   ,"Temperature dependence of THEMU")
+`MPRcz(CS             ,0.0        ,""                                   ,"Coulomb scattering parameter at TR")
+`MPRnb(STCS           ,0.0        ,""                                   ,"Temperature dependence of CS")
+`MPRcz(THECS          ,2.0        ,""                                   ,"Coulomb scattering exponent at TR")
+`MPRnb(STTHECS        ,0.0        ,""                                   ,"Temperature dependence of THECS")
+`MPRcz(XCOR           ,0.0        ,"V^-1"                               ,"Non-universality factor")
+`MPRnb(STXCOR         ,0.0        ,""                                   ,"Temperature dependence of XCOR")
+`MPRcz(FETA           ,1.0        ,""                                   ,"Effective field parameter")
+
+//  Series-resistance parameters (for resistance modeling as part of intrinsic mobility reduction)
+`MPRcz(RS             ,30.0       ,"Ohm"                                ,"Series resistance at TR")
+`MPRnb(STRS           ,1.0        ,""                                   ,"Temperature dependence of RS")
+`MPRcc(RSB            ,0.0        ,"V^-1"     ,-0.5        ,1.0         ,"Back-bias dependence of series resistance")
+`MPRco(RSG            ,0.0        ,"V^-1"     ,-0.5        ,inf         ,"Gate-bias dependence of series resistance")
+
+//  Velocity saturation parameters
+`MPRcz(THESAT         ,1.0        ,"V^-1"                               ,"Velocity saturation parameter at TR")
+`MPRnb(STTHESAT       ,1.0        ,""                                   ,"Temperature dependence of THESAT")
+`MPRcc(THESATB        ,0.0        ,"V^-1"     ,-0.5        ,1.0         ,"Back-bias dependence of velocity saturation")
+`MPRco(THESATG        ,0.0        ,"V^-1"     ,-0.5        ,inf         ,"Gate-bias dependence of velocity saturation")
+
+//  Saturation voltage parameters
+`MPRco(AX             ,3.0        ,""         ,2.0         ,inf         ,"Linear/saturation transition factor")
+
+//  Channel length modulation (CLM) parameters
+`MPRcz(ALP            ,0.01       ,""                                   ,"CLM pre-factor")
+`MPRcz(ALP1           ,0.0        ,"V"                                  ,"CLM enhancement factor above threshold")
+`MPRcz(ALP2           ,0.0        ,"V^-1"                               ,"CLM enhancement factor below threshold")
+`MPRco(VP             ,0.05       ,"V"        ,1.0e-10     ,inf         ,"CLM logarithm dependence factor")
+
+//  Impact ionization (II) parameters
+`MPRcz(A1             ,1.0        ,""                                   ,"Impact-ionization pre-factor")
+`MPRcz(A2             ,10.0       ,"V"                                  ,"Impact-ionization exponent at TR")
+`MPRnb(STA2           ,0.0        ,"V"                                  ,"Temperature dependence of A2")
+`MPRcz(A3             ,1.0        ,""                                   ,"Saturation-voltage dependence of impact-ionization")
+`MPRcz(A4             ,0.0        ,"V^-0.5"                             ,"Back-bias dependence of impact-ionization")
+
+//  Gate current parameters
+`MPRcc(GCO            ,0.0        ,""         ,-10.0       ,10.0        ,"Gate tunnelling energy adjustment")
+`MPRcz(IGINV          ,0.0        ,"A"                                  ,"Gate channel current pre-factor")
+`MPRcz(IGOV           ,0.0        ,"A"                                  ,"Gate overlap current pre-factor")
+`MPRcz(IGOVD          ,0.0        ,"A"                                  ,"Gate overlap current pre-factor for drain side")
+`MPRnb(STIG           ,2.0        ,""                                   ,"Temperature dependence of IGINV and IGOV")
+`MPRcc(GC2            ,0.375      ,""         ,0.0         ,10.0        ,"Gate current slope factor")
+`MPRcc(GC3            ,0.063      ,""         ,-2.0        ,2.0         ,"Gate current curvature factor")
+`MPRco(CHIB           ,3.1        ,"V"        ,1.0         ,inf         ,"Tunnelling barrier height")
+
+//  Gate Induced Drain/Source Leakage (GIDL) parameters
+`MPRcz(AGIDL          ,0.0        ,"A/V^3"                              ,"GIDL pre-factor")
+`MPRcz(AGIDLD         ,0.0        ,"A/V^3"                              ,"GIDL pre-factor for drain side")
+`MPRcz(BGIDL          ,41.0       ,"V"                                  ,"GIDL probability factor at TR")
+`MPRcz(BGIDLD         ,41.0       ,"V"                                  ,"GIDL probability factor at TR for drain side")
+`MPRnb(STBGIDL        ,0.0        ,"V/K"                                ,"Temperature dependence of BGIDL")
+`MPRnb(STBGIDLD       ,0.0        ,"V/K"                                ,"Temperature dependence of BGIDL for drain side")
+`MPRnb(CGIDL          ,0.0        ,""                                   ,"Back-bias dependence of GIDL")
+`MPRnb(CGIDLD         ,0.0        ,""                                   ,"Back-bias dependence of GIDL for drain side")
+
+//  Charge model parameters
+`MPRcz(COX            ,1.0e-14    ,"F"                                  ,"Oxide capacitance for intrinsic channel")
+`MPRcz(CGOV           ,1.0e-15    ,"F"                                  ,"Oxide capacitance for gate-drain/source overlap")
+`MPRcz(CGOVD          ,1.0e-15    ,"F"                                  ,"Oxide capacitance for gate-drain overlap")
+`MPRcz(CGBOV          ,0.0        ,"F"                                  ,"Oxide capacitance for gate-bulk overlap")
+`MPRcz(CFR            ,0.0        ,"F"                                  ,"Outer fringe capacitance")
+`MPRcz(CFRD           ,0.0        ,"F"                                  ,"Outer fringe capacitance for drain side")
+
+//  Noise parameters
+`MPRcz(FNT            ,1.0        ,""                                   ,"Thermal noise coefficient")
+`MPRcz(FNTEXC         ,0.0        ,""                                   ,"Excess noise coefficient")
+`MPRcz(NFA            ,8.0e22     ,"V^-1/m^4"                           ,"First coefficient of flicker noise")
+`MPRcz(NFB            ,3.0e07     ,"V^-1/m^2"                           ,"Second coefficient of flicker noise")
+`MPRcz(NFC            ,0.0        ,"V^-1"                               ,"Third coefficient of flicker noise")
+`MPRcz(EF             ,1.0        ,""                                   ,"Flicker noise frequency exponent")
+
+// Edge transistor parameters: PSP 103.4
+`MPRnb(VFBEDGE        ,-1.0       ,"V"                                  ,"Flat band voltage of edge transistors at TR")
+`MPRnb(STVFBEDGE      ,5.0e-4     ,"V/K"                                ,"Temperature dependence of VFBEDGE")
+`MPRnb(DPHIBEDGE      ,0.0        ,"V"                                  ,"Offset parameter for PHIB of edge transistors")
+`MPRcc(NEFFEDGE       ,5.0e23     ,"m^-3"     ,1.0e20      ,1.0e26      ,"Effective substrate doping of edge transistors")
+`MPRcz(CTEDGE         ,0.0        ,""                                   ,"Interface states factor of edge transistors")
+`MPRcz(BETNEDGE       ,5.0e-4     ,"m^2/V/s"                            ,"Channel aspect ratio times zero-field mobility of edge transistor")
+`MPRnb(STBETEDGE      ,1.0        ,""                                   ,"Temperature dependence of BETNEDGE")
+`MPRcz(PSCEEDGE       ,0.0        ,""                                   ,"Subthreshold slope coefficient for short channel edge transistors")
+`MPRcc(PSCEBEDGE      ,0.0        ,"V^-1"     ,0.0         ,1.0         ,"Bulk voltage dependence parameter of subthreshold slope coefficient for short channel edge transistors")
+`MPRcz(PSCEDEDGE      ,0.0        ,"V^-1"                               ,"Drain voltage dependence parameter of subthreshold slope coefficient for short channel edge transistors")
+`MPRcz(CFEDGE         ,0.0        ,""                                   ,"DIBL parameter of edge transistors")
+`MPRcz(CFDEDGE        ,0.0        ,"V^-1"                               ,"Drain voltage dependence parameter of DIBL-parameter of edge transistors")
+`MPRcc(CFBEDGE        ,0.0        ,"V^-1"     ,0.0         ,1.0         ,"Bulk voltage dependence parameter of DIBL-parameter of edge transistors")
+`MPRcz(FNTEDGE        ,1.0        ,""                                   ,"Thermal noise coefficient of edge transistors")
+`MPRcz(NFAEDGE        ,8.0e22     ,"V^-1/m^4"                           ,"First coefficient of flicker noise of edge transistors")
+`MPRcz(NFBEDGE        ,3.0e07     ,"V^-1/m^2"                           ,"Second coefficient of flicker noise of edge transistors")
+`MPRcz(NFCEDGE        ,0.0        ,"V^-1"                               ,"Third coefficient of flicker noise of edge transistors")
+`MPRcz(EFEDGE         ,1.0        ,""                                   ,"Flicker noise frequency exponent of edge transistors")
+
+//  NQS parameters
+`ifdef NQSmodel
+    `MPRcz(MUNQS          ,1.0        ,""                                   ,"Relative mobility for NQS modelling")
+`endif // NQSmodel
+
+// Parasitic resistance parameters
+`MPRcz(RG             ,0.0        ,"Ohm"                                ,"Gate resistance")
+`MPRcz(RSE            ,0.0        ,"Ohm"                                ,"External source resistance")
+`MPRcz(RDE            ,0.0        ,"Ohm"                                ,"External drain resistance")
+`MPRcz(RBULK          ,0.0        ,"Ohm"                                ,"Bulk resistance between node BP and BI")
+`MPRcz(RWELL          ,0.0        ,"Ohm"                                ,"Well resistance between node BI and B")
+`MPRcz(RJUNS          ,0.0        ,"Ohm"                                ,"Source-side bulk resistance between node BI and BS")
+`MPRcz(RJUND          ,0.0        ,"Ohm"                                ,"Drain-side bulk resistance between node BI and BD")
+
+// Self heating effect parameters
+`ifdef SelfHeating
+    `MPRcz(RTH            ,0.0        ,"K/W"                                ,"Thermal resistance")
+    `MPRcz(CTH            ,0.0        ,"J/K"                                ,"Thermal capacitance")
+    `MPRnb(STRTH          ,0.0        ,""                                   ,"Temperature sensitivity of RTH")
+`endif // SelfHeating
+
+//  --------------------------------------------------------------------------------------------------------------
+//  PSP global model parameters (binning)
+//  --------------------------------------------------------------------------------------------------------------
+
+`include "PSP103_binpars.include"
+
+//  --------------------------------------------------------------------------------------------------------------
+//  PSP global model parameters
+//  --------------------------------------------------------------------------------------------------------------
+
+// Process Parameters
+`MPRnb(LVARO          ,0.0        ,"m"                                  ,"Geom. independent difference between actual and programmed gate length")
+`MPRnb(LVARL          ,0.0        ,""                                   ,"Length dependence of LVAR")
+`MPRnb(LVARW          ,0.0        ,""                                   ,"Width dependence of LVAR")
+`MPRnb(LAP            ,0.0        ,"m"                                  ,"Effective channel length reduction per side")
+`MPRnb(WVARO          ,0.0        ,"m"                                  ,"Geom. independent difference between actual and programmed field-oxide opening")
+`MPRnb(WVARL          ,0.0        ,""                                   ,"Length dependence of WVAR")
+`MPRnb(WVARW          ,0.0        ,""                                   ,"Width dependence of WVAR")
+`MPRnb(WOT            ,0.0        ,"m"                                  ,"Effective channel width reduction per side")
+`MPRnb(DLQ            ,0.0        ,"m"                                  ,"Effective channel length reduction for CV")
+`MPRnb(DWQ            ,0.0        ,"m"                                  ,"Effective channel width reduction for CV")
+`MPRnb(VFBO           ,-1.0       ,"V"                                  ,"Geometry-independent flat-band voltage at TR")
+`MPRnb(VFBL           ,0.0        ,"V"                                  ,"Length dependence of flat-band voltage")
+`MPRnb(VFBW           ,0.0        ,"V"                                  ,"Width dependence of flat-band voltage")
+`MPRnb(VFBLW          ,0.0        ,"V"                                  ,"Area dependence of flat-band voltage")
+`MPRnb(STVFBO         ,5.0e-4     ,"V/K"                                ,"Geometry-independent temperature dependence of VFB")
+`MPRnb(STVFBL         ,0.0        ,"V/K"                                ,"Length dependence of temperature dependence of VFB")
+`MPRnb(STVFBW         ,0.0        ,"V/K"                                ,"Width dependence of temperature dependence of VFB")
+`MPRnb(STVFBLW        ,0.0        ,"V/K"                                ,"Area dependence of temperature dependence of VFB")
+`MPRnb(ST2VFBO        ,0.0        ,"K^-1"                               ,"Quadratic temperature dependence of VFB")
+`MPRco(TOXO           ,2.0e-9     ,"m"        ,1.0e-10     ,inf         ,"Gate oxide thickness")
+`MPRco(EPSROXO        ,3.9        ,""         ,1.0         ,inf         ,"Relative permittivity of gate dielectric")
+`MPRco(NSUBO          ,3.0e23     ,"m^-3"     ,1.0e20      ,inf         ,"Geometry independent substrate doping")
+`MPRnb(NSUBW          ,0.0        ,""                                   ,"Width dependence of background doping NSUBO due to segregation")
+`MPRco(WSEG           ,1.0e-8     ,"m"        ,1.0e-10     ,inf         ,"Char. length of segregation of background doping NSUBO")
+`MPRcz(NPCK           ,1.0e24     ,"m^-3"                               ,"Pocket doping level")
+`MPRnb(NPCKW          ,0.0        ,""                                   ,"Width dependence of pocket doping NPCK due to segregation")
+`MPRco(WSEGP          ,1.0e-8     ,"m"        ,1.0e-10     ,inf         ,"Char. length of segregation of pocket doping NPCK")
+`MPRco(LPCK           ,1.0e-8     ,"m"        ,1.0e-10     ,inf         ,"Char. length of lateral doping profile")
+`MPRnb(LPCKW          ,0.0        ,""                                   ,"Width dependence of char. length of lateral doping profile")
+`MPRnb(FOL1           ,0.0        ,""                                   ,"First length dependence coefficient for short channel body effect")
+`MPRnb(FOL2           ,0.0        ,""                                   ,"Second length dependence coefficient for short channel body effect")
+`MPRnb(FACNEFFACO     ,1.0        ,""                                   ,"Geom. independent pre-factor for effective substrate doping in separate charge calculation")
+`MPRnb(FACNEFFACL     ,0.0        ,""                                   ,"Length dependence of FACNEFFAC")
+`MPRnb(FACNEFFACW     ,0.0        ,""                                   ,"Width dependence of FACNEFFAC")
+`MPRnb(FACNEFFACLW    ,0.0        ,""                                   ,"Area dependence of FACNEFFAC")
+`MPRnb(GFACNUDO       ,1.0        ,""                                   ,"Geom. independent body-factor change due to NUD-effect")
+`MPRnb(GFACNUDL       ,0.0        ,""                                   ,"Length dependence of GFACNUD")
+`MPRnb(GFACNUDLEXP    ,1.0        ,""                                   ,"Exponent for length dependence of GFACNUD")
+`MPRnb(GFACNUDW       ,0.0        ,""                                   ,"Width dependence of GFACNUD")
+`MPRnb(GFACNUDLW      ,0.0        ,""                                   ,"Area dependence of GFACNUD")
+`MPRnb(VSBNUDO        ,0.0        ,"V"                                  ,"Lower Vsb value for NUD-effect")
+`MPRnb(DVSBNUDO       ,1.0        ,"V"                                  ,"Vsb range for NUD-effect")
+`MPRnb(VNSUBO         ,0.0        ,"V"                                  ,"Effective doping bias-dependence parameter")
+`MPRnb(NSLPO          ,0.05       ,"V"                                  ,"Effective doping bias-dependence parameter")
+`MPRnb(DNSUBO         ,0.0        ,"V^-1"                               ,"Effective doping bias-dependence parameter")
+`MPRnb(DPHIBO         ,0.0        ,"V"                                  ,"Geometry independent offset of PHIB")
+`MPRnb(DPHIBL         ,0.0        ,"V"                                  ,"Length dependence offset of PHIB")
+`MPRnb(DPHIBLEXP      ,1.0        ,""                                   ,"Exponent for length dependence of offset of PHIB")
+`MPRnb(DPHIBW         ,0.0        ,"V"                                  ,"Width dependence of offset of PHIB")
+`MPRnb(DPHIBLW        ,0.0        ,"V"                                  ,"Area dependence of offset of PHIB")
+`MPRnb(DELVTACO       ,0.0        ,"V"                                  ,"Geom. independent offset parameter for PHIB in separate charge calculation")
+`MPRnb(DELVTACL       ,0.0        ,"V"                                  ,"Length dependence of DELVTAC")
+`MPRnb(DELVTACLEXP    ,1.0        ,""                                   ,"Exponent for length dependence of offset of DELVTAC")
+`MPRnb(DELVTACW       ,0.0        ,"V"                                  ,"Width dependence of DELVTAC")
+`MPRnb(DELVTACLW      ,0.0        ,"V"                                  ,"Area dependence of DELVTAC")
+`MPRnb(NPO            ,1.0e26     ,"m^-3"                               ,"Geometry-independent gate poly-silicon doping")
+`MPRnb(NPL            ,0.0        ,""                                   ,"Length dependence of gate poly-silicon doping")
+`MPRco(TOXOVO         ,2.0e-9     ,"m"        ,1.0e-10     ,inf         ,"Overlap oxide thickness")
+`MPRco(TOXOVDO        ,2.0e-9     ,"m"        ,1.0e-10     ,inf         ,"Overlap oxide thickness for drain side")
+`MPRcz(LOV            ,0.0        ,"m"                                  ,"Overlap length for gate/drain and gate/source overlap capacitance")
+`MPRcz(LOVD           ,0.0        ,"m"                                  ,"Overlap length for gate/drain overlap capacitance")
+`MPRnb(NOVO           ,5e25       ,"m^-3"                               ,"Effective doping of overlap region")
+`MPRnb(NOVDO          ,5e25       ,"m^-3"                               ,"Effective doping of overlap region for drain side")
+
+//  Interface states parameters: PSP 103.6
+`MPRnb(CTO            ,0.0        ,""                                   ,"Geometry-independent interface states factor")
+`MPRnb(CTL            ,0.0        ,""                                   ,"Length dependence of interface states factor")
+`MPRnb(CTLEXP         ,1.0        ,""                                   ,"Exponent for length dependence of interface states factor")
+`MPRnb(CTW            ,0.0        ,""                                   ,"Width dependence of interface states factor")
+`MPRnb(CTLW           ,0.0        ,""                                   ,"Area dependence of interface states factor")
+`MPRcz(CTGO           ,0.0        ,""                                   ,"Gate voltage dependence of interface states factor")
+`MPRnb(CTBO           ,0.0        ,""                                   ,"Bulk voltage dependence of interface states factor")
+`MPRnb(STCTO          ,1.0        ,""                                   ,"Geometry-independent temperature dependence of CT")
+
+// DIBL Parameters
+`MPRnb(CFL            ,0.0        ,""                                   ,"Length dependence of DIBL-parameter")
+`MPRnb(CFLEXP         ,2.0        ,""                                   ,"Exponent for length dependence of CF")
+`MPRnb(CFW            ,0.0        ,""                                   ,"Width dependence of CF")
+`MPRcz(CFDO           ,0.0        ,"V^-1"                               ,"Drain voltage dependence of CF")
+`MPRnb(CFBO           ,0.0        ,"V^-1"                               ,"Back-bias dependence of CF")
+
+//  Subthreshold slope parameters of short channel transistor
+`MPRnb(PSCEL          ,0.0        ,""                                   ,"Length dependence of subthreshold slope coefficient for short channel transistor")
+`MPRnb(PSCELEXP       ,2.0        ,""                                   ,"Exponent for length dependence of subthreshold slope coefficient for short channel transistor")
+`MPRnb(PSCEW          ,0.0        ,""                                   ,"Exponent for length dependence of subthreshold slope coefficient for short channel transistor")
+`MPRcc(PSCEBO         ,0.0        ,"V^-1"     ,0.0         ,1.0         ,"Bulk voltage dependence parameter of subthreshold slope coefficient for short channel transistor")
+`MPRcz(PSCEDO         ,0.0        ,"V^-1"                               ,"Drain voltage dependence parameter of subthreshold slope coefficient for short channel transistor")
+
+// Mobility Parameters
+`MPRcz(UO             ,5.0e-2     ,"m^2/V/s"                            ,"Zero-field mobility at TR")
+`MPRnb(FBET1          ,0.0        ,""                                   ,"Relative mobility decrease due to first lateral profile")
+`MPRnb(FBET1W         ,0.0        ,""                                   ,"Width dependence of relative mobility decrease due to first lateral profile")
+`MPRco(LP1            ,1.0e-8     ,"m"        ,1.0e-10     ,inf         ,"Mobility-related characteristic length of first lateral profile")
+`MPRnb(LP1W           ,0.0        ,""                                   ,"Width dependence of mobility-related characteristic length of first lateral profile")
+`MPRnb(FBET2          ,0.0        ,""                                   ,"Relative mobility decrease due to second lateral profile")
+`MPRco(LP2            ,1.0e-8     ,"m"        ,1.0e-10     ,inf         ,"Mobility-related characteristic length of second lateral profile")
+`MPRnb(BETW1          ,0.0        ,""                                   ,"First higher-order width scaling coefficient of BETN")
+`MPRnb(BETW2          ,0.0        ,""                                   ,"Second higher-order width scaling coefficient of BETN")
+`MPRco(WBET           ,1.0e-9     ,"m"        ,1.0e-10     ,inf         ,"Characteristic width for width scaling of BETN")
+`MPRnb(STBETO         ,1.0        ,""                                   ,"Geometry independent temperature dependence of BETN")
+`MPRnb(STBETL         ,0.0        ,""                                   ,"Length dependence of temperature dependence of BETN")
+`MPRnb(STBETW         ,0.0        ,""                                   ,"Width dependence of temperature dependence of BETN")
+`MPRnb(STBETLW        ,0.0        ,""                                   ,"Area dependence of temperature dependence of BETN")
+`MPRnb(MUEO           ,0.5        ,"m/V"                                ,"Geometry independent mobility reduction coefficient at TR")
+`MPRnb(MUEW           ,0.0        ,""                                   ,"Width dependence of mobility reduction coefficient at TR")
+`MPRnb(STMUEO         ,0.0        ,""                                   ,"Temperature dependence of MUE")
+`MPRnb(THEMUO         ,1.5        ,""                                   ,"Mobility reduction exponent at TR")
+`MPRnb(STTHEMUO       ,1.5        ,""                                   ,"Temperature dependence of THEMU")
+`MPRnb(CSO            ,0.0        ,""                                   ,"Geometry independent coulomb scattering parameter at TR")
+`MPRnb(CSL            ,0.0        ,""                                   ,"Length dependence of CS")
+`MPRnb(CSLEXP         ,1.0        ,""                                   ,"Exponent for length dependence of CS")
+`MPRnb(CSW            ,0.0        ,""                                   ,"Width dependence of CS")
+`MPRnb(CSLW           ,0.0        ,""                                   ,"Area dependence of CS")
+`MPRnb(STCSO          ,0.0        ,""                                   ,"Temperature dependence of CS")
+`MPRcz(THECSO         ,2.0        ,""                                   ,"Coulomb scattering exponent at TR")
+`MPRnb(STTHECSO       ,0.0        ,""                                   ,"Temperature dependence of THECS")
+`MPRnb(XCORO          ,0.0        ,"V^-1"                               ,"Geometry independent non-universality parameter")
+`MPRnb(XCORL          ,0.0        ,""                                   ,"Length dependence of non-universality parameter")
+`MPRnb(XCORW          ,0.0        ,""                                   ,"Width dependence of non-universality parameter")
+`MPRnb(XCORLW         ,0.0        ,""                                   ,"Area dependence of non-universality parameter")
+`MPRnb(STXCORO        ,0.0        ,""                                   ,"Temperature dependence of XCOR")
+`MPRnb(FETAO          ,1.0        ,""                                   ,"Effective field parameter")
+
+// Series Resistance
+`MPRnb(RSW1           ,50.0       ,"Ohm"                                ,"Source/drain series resistance for 1 um wide channel at TR")
+`MPRnb(RSW2           ,0.0        ,""                                   ,"Higher-order width scaling of RS")
+`MPRnb(STRSO          ,1.0        ,""                                   ,"Temperature dependence of RS")
+`MPRnb(RSBO           ,0.0        ,"V^-1"                               ,"Back-bias dependence of series resistance")
+`MPRnb(RSGO           ,0.0        ,"V^-1"                               ,"Gate-bias dependence of series resistance")
+
+// Velocity Saturation
+`MPRnb(THESATO        ,0.0        ,"V^-1"                               ,"Geometry independent velocity saturation parameter at TR")
+`MPRnb(THESATL        ,0.05       ,"V^-1"                               ,"Length dependence of THESAT")
+`MPRnb(THESATLEXP     ,1.0        ,""                                   ,"Exponent for length dependence of THESAT")
+`MPRnb(THESATW        ,0.0        ,""                                   ,"Width dependence of velocity saturation parameter")
+`MPRnb(THESATLW       ,0.0        ,""                                   ,"Area dependence of velocity saturation parameter")
+`MPRnb(STTHESATO      ,1.0        ,""                                   ,"Geometry independent temperature dependence of THESAT")
+`MPRnb(STTHESATL      ,0.0        ,""                                   ,"Length dependence of temperature dependence of THESAT")
+`MPRnb(STTHESATW      ,0.0        ,""                                   ,"Width dependence of temperature dependence of THESAT")
+`MPRnb(STTHESATLW     ,0.0        ,""                                   ,"Area dependence of temperature dependence of THESAT")
+`MPRnb(THESATBO       ,0.0        ,"V^-1"                               ,"Back-bias dependence of velocity saturation")
+`MPRnb(THESATGO       ,0.0        ,"V^-1"                               ,"Gate-bias dependence of velocity saturation")
+
+// Saturation Voltage
+`MPRnb(AXO            ,18.0       ,""                                   ,"Geometry independent linear/saturation transition factor")
+`MPRcz(AXL            ,0.4        ,""                                   ,"Length dependence of AX")
+
+// Channel Length Modulation
+`MPRnb(ALPL           ,5.0e-4     ,""                                   ,"Length dependence of ALP")
+`MPRnb(ALPLEXP        ,1.0        ,""                                   ,"Exponent for length dependence of ALP")
+`MPRnb(ALPW           ,0.0        ,""                                   ,"Width dependence of ALP")
+`MPRnb(ALP1L1         ,0.0        ,"V"                                  ,"Length dependence of CLM enhancement factor above threshold")
+`MPRnb(ALP1LEXP       ,0.5        ,""                                   ,"Exponent for length dependence of ALP1")
+`MPRcz(ALP1L2         ,0.0        ,""                                   ,"Second_order length dependence of ALP1")
+`MPRnb(ALP1W          ,0.0        ,""                                   ,"Width dependence of ALP1")
+`MPRnb(ALP2L1         ,0.0        ,"V^-1"                               ,"Length dependence of CLM enhancement factor below threshold")
+`MPRnb(ALP2LEXP       ,0.5        ,""                                   ,"Exponent for length dependence of ALP2")
+`MPRcz(ALP2L2         ,0.0        ,""                                   ,"Second_order length dependence of ALP2")
+`MPRnb(ALP2W          ,0.0        ,""                                   ,"Width dependence of ALP2")
+`MPRnb(VPO            ,0.05       ,"V"                                  ,"CLM logarithmic dependence parameter")
+
+// Weak-avalanche parameters
+`MPRnb(A1O            ,1.0        ,""                                   ,"Geometry independent impact-ionization pre-factor")
+`MPRnb(A1L            ,0.0        ,""                                   ,"Length dependence of A1")
+`MPRnb(A1W            ,0.0        ,""                                   ,"Width dependence of A1")
+`MPRnb(A2O            ,10.0       ,"V"                                  ,"Impact-ionization exponent at TR")
+`MPRnb(STA2O          ,0.0        ,"V"                                  ,"Temperature dependence of A2")
+`MPRnb(A3O            ,1.0        ,""                                   ,"Geometry independent saturation-voltage dependence of II")
+`MPRnb(A3L            ,0.0        ,""                                   ,"Length dependence of A3")
+`MPRnb(A3W            ,0.0        ,""                                   ,"Width dependence of A3")
+`MPRnb(A4O            ,0.0        ,"V^-0.5"                             ,"Geometry independent back-bias dependence of II")
+`MPRnb(A4L            ,0.0        ,""                                   ,"Length dependence of A4")
+`MPRnb(A4W            ,0.0        ,""                                   ,"Width dependence of A4")
+
+// Gate current parameters
+`MPRnb(GCOO           ,0.0        ,""                                   ,"Gate tunnelling energy adjustment")
+`MPRnb(IGINVLW        ,0.0        ,"A"                                  ,"Gate channel current pre-factor for 1 um^2 channel area")
+`MPRnb(IGOVW          ,0.0        ,"A"                                  ,"Gate overlap current pre-factor for 1 um wide channel")
+`MPRnb(IGOVDW         ,0.0        ,"A"                                  ,"Gate overlap current pre-factor for 1 um wide channel for drain side")
+`MPRnb(STIGO          ,2.0        ,""                                   ,"Temperature dependence of IGINV and IGOV")
+`MPRnb(GC2O           ,0.375      ,""                                   ,"Gate current slope factor")
+`MPRnb(GC3O           ,0.063      ,""                                   ,"Gate current curvature factor")
+`MPRnb(CHIBO          ,3.1        ,"V"                                  ,"Tunnelling barrier height")
+
+// Gate-induced drain leakage parameters
+`MPRnb(AGIDLW         ,0.0        ,"A/V^3"                              ,"Width dependence of GIDL pre-factor")
+`MPRnb(AGIDLDW        ,0.0        ,"A/V^3"                              ,"Width dependence of GIDL pre-factor for drain side")
+`MPRnb(BGIDLO         ,41.0       ,"V"                                  ,"GIDL probability factor at TR")
+`MPRnb(BGIDLDO        ,41.0       ,"V"                                  ,"GIDL probability factor at TR for drain side")
+`MPRnb(STBGIDLO       ,0.0        ,"V/K"                                ,"Temperature dependence of BGIDL")
+`MPRnb(STBGIDLDO      ,0.0        ,"V/K"                                ,"Temperature dependence of BGIDL for drain side")
+`MPRnb(CGIDLO         ,0.0        ,""                                   ,"Back-bias dependence of GIDL")
+`MPRnb(CGIDLDO        ,0.0        ,""                                   ,"Back-bias dependence of GIDL for drain side")
+
+// Charge Model Parameters
+`MPRnb(CGBOVL         ,0.0        ,"F"                                  ,"Oxide capacitance for gate-bulk overlap for 1 um long channel")
+`MPRnb(CFRW           ,0.0        ,"F"                                  ,"Outer fringe capacitance for 1 um wide channel")
+`MPRnb(CFRDW          ,0.0        ,"F"                                  ,"Outer fringe capacitance for 1 um wide channel for drain side")
+
+// Noise Model Parameters
+`MPRnb(FNTO           ,1.0        ,""                                   ,"Thermal noise coefficient")
+`MPRcz(FNTEXCL        ,0.0        ,""                                   ,"Length dependence coefficient of excess noise")
+`MPRnb(NFALW          ,8.0e22     ,"V^-1/m^4"                           ,"First coefficient of flicker noise for 1 um^2 channel area")
+`MPRnb(NFBLW          ,3.0e7      ,"V^-1/m^2"                           ,"Second coefficient of flicker noise for 1 um^2 channel area")
+`MPRnb(NFCLW          ,0.0        ,"V^-1"                               ,"Third coefficient of flicker noise for 1 um^2 channel area")
+`MPRnb(EFO            ,1.0        ,""                                   ,"Flicker noise frequency exponent")
+`MPRnb(LINTNOI        ,0.0        ,"m"                                  ,"Length offset for flicker noise")
+`MPRnb(ALPNOI         ,2.0        ,""                                   ,"Exponent for length offset for flicker noise")
+
+// Edge transistor parameters: PSP 103.4
+`MPRcz(WEDGE          ,1.0e-8     ,"m"                                  ,"Electrical width of edge transistor per side")
+`MPRcz(WEDGEW         ,0.0        ,""                                   ,"Width dependence of edge WEDGE")
+`MPRnb(VFBEDGEO       ,-1.0       ,"V"                                  ,"Geometry-independent flat-band voltage of edge transistors at TR")
+`MPRnb(STVFBEDGEO     ,5.0e-4     ,"V/K"                                ,"Geometry-independent temperature dependence of VFBEDGE")
+`MPRnb(STVFBEDGEL     ,0.0        ,"V/K"                                ,"Length dependence of temperature dependence of VFBEDGE")
+`MPRnb(STVFBEDGEW     ,0.0        ,"V/K"                                ,"Width dependence of temperature dependence of VFBEDGE")
+`MPRnb(STVFBEDGELW    ,0.0        ,"V/K"                                ,"Area dependence of temperature dependence of VFBEDGE")
+`MPRnb(DPHIBEDGEO     ,0.0        ,"V"                                  ,"Geometry independent of edge transistor PHIB offset")
+`MPRnb(DPHIBEDGEL     ,0.0        ,"V"                                  ,"Length dependence of edge transistor PHIB offset")
+`MPRnb(DPHIBEDGELEXP  ,1.0        ,""                                   ,"Exponent for length dependence of edge transistor PHIB offset")
+`MPRnb(DPHIBEDGEW     ,0.0        ,"V"                                  ,"Width dependence of edge transistor PHIB offset")
+`MPRnb(DPHIBEDGELW    ,0.0        ,"V"                                  ,"Area dependence of edge transistor PHIB offset")
+`MPRco(NSUBEDGEO      ,5.0e23     ,"m^-3"     ,1.0e20      ,inf         ,"Geometry independent substrate doping of edge transistors")
+`MPRnb(NSUBEDGEL      ,0.0        ,""                                   ,"Length dependence of edge transistor substrate doping")
+`MPRnb(NSUBEDGELEXP   ,1.0        ,""                                   ,"Exponent for length dependence of edge transistor substrate doping")
+`MPRnb(NSUBEDGEW      ,0.0        ,""                                   ,"Width dependence of edge transistor substrate doping")
+`MPRnb(NSUBEDGELW     ,0.0        ,""                                   ,"Area dependence of edge transistor substrate doping")
+`MPRnb(CTEDGEO        ,0.0        ,""                                   ,"Geometry-independent interface states factor of edge transistors")
+`MPRnb(CTEDGEL        ,0.0        ,""                                   ,"Length dependence of interface states factor of edge transistors")
+`MPRnb(CTEDGELEXP     ,1.0        ,""                                   ,"Exponent for length dependence of interface states factor of edge transistors")
+`MPRnb(FBETEDGE       ,0.0        ,""                                   ,"Length dependence of edge transistor mobility")
+`MPRco(LPEDGE         ,1.0e-8     ,"m"        ,1.0e-10     ,inf         ,"Exponent for length dependence of edge transistor mobility")
+`MPRnb(BETEDGEW       ,0.0        ,""                                   ,"Width scaling coefficient of edge transistor mobility")
+`MPRnb(STBETEDGEO     ,1.0        ,""                                   ,"Geometry independent temperature dependence of BETNEDGE")
+`MPRnb(STBETEDGEL     ,0.0        ,""                                   ,"Length dependence of temperature dependence of BETNEDGE")
+`MPRnb(STBETEDGEW     ,0.0        ,""                                   ,"Width dependence of temperature dependence of BETNEDGE")
+`MPRnb(STBETEDGELW    ,0.0        ,""                                   ,"Area dependence of temperature dependence of BETNEDGE")
+`MPRnb(PSCEEDGEL      ,0.0        ,""                                   ,"Length dependence of subthreshold slope coefficient for short channel edge transistors")
+`MPRnb(PSCEEDGELEXP   ,2.0        ,""                                   ,"Exponent for length dependence of subthreshold slope coefficient for short channel edge transistors")
+`MPRnb(PSCEEDGEW      ,0.0        ,""                                   ,"Exponent for length dependence of subthreshold slope coefficient for short channel edge transistor")
+`MPRcc(PSCEBEDGEO     ,0.0        ,"V^-1"     ,0.0         ,1.0         ,"Bulk voltage dependence parameter of subthreshold slope coefficient for short channel edge transistors")
+`MPRcz(PSCEDEDGEO     ,0.0        ,"V^-1"                               ,"Drain voltage dependence parameter of subthreshold slope coefficient for short channel edge transistors")
+`MPRnb(CFEDGEL        ,0.0        ,""                                   ,"Length dependence of DIBL-parameter of edge transistors")
+`MPRnb(CFEDGELEXP     ,2.0        ,""                                   ,"Exponent for length dependence of DIBL-parameter of edge transistors")
+`MPRnb(CFEDGEW        ,0.0        ,""                                   ,"Width dependence of DIBL-parameter of edge transistors")
+`MPRcz(CFDEDGEO       ,0.0        ,"V^-1"                               ,"Drain voltage dependence parameter of DIBL-parameter of edge transistors")
+`MPRcc(CFBEDGEO       ,0.0        ,"V^-1"     ,0.0         ,1.0         ,"Bulk voltage dependence parameter of DIBL-parameter of edge transistors")
+`MPRnb(FNTEDGEO       ,1.0        ,""                                   ,"Thermal noise coefficient")
+`MPRnb(NFAEDGELW      ,8.0e22     ,"V^-1/m^4"                           ,"First coefficient of flicker noise for 1 um^2 channel area")
+`MPRnb(NFBEDGELW      ,3.0e7      ,"V^-1/m^2"                           ,"Second coefficient of flicker noise for 1 um^2 channel area")
+`MPRnb(NFCEDGELW      ,0.0        ,"V^-1"                               ,"Third coefficient of flicker noise for 1 um^2 channel area")
+`MPRnb(EFEDGEO        ,1.0        ,""                                   ,"Flicker noise frequency exponent")
+
+// Well proximity effect Parameters
+`MPRnb(KVTHOWEO       ,0.0        ,""                                   ,"Geometrical independent threshold shift parameter")
+`MPRnb(KVTHOWEL       ,0.0        ,""                                   ,"Length dependent threshold shift parameter")
+`MPRnb(KVTHOWEW       ,0.0        ,""                                   ,"Width dependent threshold shift parameter")
+`MPRnb(KVTHOWELW      ,0.0        ,""                                   ,"Area dependent threshold shift parameter")
+`MPRnb(KUOWEO         ,0.0        ,""                                   ,"Geometrical independent mobility degradation factor")
+`MPRnb(KUOWEL         ,0.0        ,""                                   ,"Length dependent mobility degradation factor")
+`MPRnb(KUOWEW         ,0.0        ,""                                   ,"Width dependent mobility degradation factor")
+`MPRnb(KUOWELW        ,0.0        ,""                                   ,"Area dependent mobility degradation factor")
+
+//  --------------------------------------------------------------------------------------------------------------
+//  Parameters that occur in both global and binning model
+//  --------------------------------------------------------------------------------------------------------------
+
+// NQS parameters
+`ifdef NQSmodel
+    `MPRnb(MUNQSO         ,1.0        ,""                                   ,"Relative mobility for NQS modelling")
+`endif // NQSmodel
+
+// Parasitic resistance parameters
+`MPRnb(RGO            ,0.0        ,"Ohm"                                ,"Gate resistance")
+`MPRcz(RINT           ,0.0        ,"Ohm m^2"                            ,"Contact resistance between silicide and ploy")
+`MPRcz(RVPOLY         ,0.0        ,"Ohm m^2"                            ,"Vertical poly resistance")
+`MPRcz(RSHG           ,0.0        ,"Ohm/sq"                             ,"Gate electrode diffusion sheet resistance")
+`MPRnb(DLSIL          ,0.0        ,"m"                                  ,"Silicide extension over the physical gate length")
+`MPRnb(RSH            ,0.0        ,"Ohm/sq"                             ,"Sheet resistance of source diffusion")
+`MPRnb(RSHD           ,0.0        ,"Ohm/sq"                             ,"Sheet resistance of drain diffusion")
+`MPRnb(RBULKO         ,0.0        ,"Ohm"                                ,"Bulk resistance between node BP and BI")
+`MPRnb(RWELLO         ,0.0        ,"Ohm"                                ,"Well resistance between node BI and B")
+`MPRnb(RJUNSO         ,0.0        ,"Ohm"                                ,"Source-side bulk resistance between node BI and BS")
+`MPRnb(RJUNDO         ,0.0        ,"Ohm"                                ,"Drain-side bulk resistance between node BI and BD")
+
+// Self heating effect parameters
+`ifdef SelfHeating
+    `MPRnb(RTHO           ,0.0        ,"K/W"                                ,"Geometry independent part of thermal resistance")
+    `MPRnb(RTHW1          ,0.0        ,"K/W"                                ,"Width dependence of thermal resistance")
+    `MPRnb(RTHW2          ,0.0        ,""                                   ,"Offset in width dependence of thermal resistance")
+    `MPRnb(RTHLW          ,0.0        ,""                                   ,"Length-correction to width dependence of thermal resistance")
+    `MPRnb(CTHO           ,0.0        ,"J/K"                                ,"Geometry independent part of thermal capacitance")
+    `MPRnb(CTHW1          ,0.0        ,"J/K"                                ,"Width dependence of thermal capacitance")
+    `MPRnb(CTHW2          ,0.0        ,""                                   ,"Offset in width dependence of thermal capacitance")
+    `MPRnb(CTHLW          ,0.0        ,""                                   ,"Length-correction to width dependence of thermal capacitance")
+    `MPRnb(STRTHO         ,0.0        ,""                                   ,"Temperature sensitivity of RTH")
+`endif // SelfHeating
+
+// Stress Model Parameters
+`MPRco(SAREF          ,1.0e-6     ,"m"        ,1.0e-9      ,inf         ,"Reference distance between OD-edge and poly from one side")
+`MPRco(SBREF          ,1.0e-6     ,"m"        ,1.0e-9      ,inf         ,"Reference distance between OD-edge and poly from other side")
+`MPRnb(WLOD           ,0.0        ,"m"                                  ,"Width parameter")
+`MPRnb(KUO            ,0.0        ,"m"                                  ,"Mobility degradation/enhancement coefficient")
+`MPRcc(KVSAT          ,0.0        ,"m"        ,-1.0        ,1.0         ,"Saturation velocity degradation/enhancement coefficient")
+`MPRnb(TKUO           ,0.0        ,""                                   ,"Temperature dependence of KUO")
+`MPRnb(LKUO           ,0.0        ,"m^LLODKUO"                          ,"Length dependence of KUO")
+`MPRnb(WKUO           ,0.0        ,"m^WLODKUO"                          ,"Width dependence of KUO")
+`MPRnb(PKUO           ,0.0        ,"m^(LLODKUO+WLODKUO)"                ,"Cross-term dependence of KUO")
+`MPRcz(LLODKUO        ,0.0        ,""                                   ,"Length parameter for UO stress effect")
+`MPRcz(WLODKUO        ,0.0        ,""                                   ,"Width parameter for UO stress effect")
+`MPRnb(KVTHO          ,0.0        ,"Vm"                                 ,"Threshold shift parameter")
+`MPRnb(LKVTHO         ,0.0        ,"m^LLODVTH"                          ,"Length dependence of KVTHO")
+`MPRnb(WKVTHO         ,0.0        ,"m^WLODVTH"                          ,"Width dependence of KVTHO")
+`MPRnb(PKVTHO         ,0.0        ,"m^(LLODVTH+WLODVTH)"                ,"Cross-term dependence of KVTHO")
+`MPRcz(LLODVTH        ,0.0        ,""                                   ,"Length parameter for VTH-stress effect")
+`MPRcz(WLODVTH        ,0.0        ,""                                   ,"Width parameter for VTH-stress effect")
+`MPRnb(STETAO         ,0.0        ,"m"                                  ,"Eta0 shift factor related to VTHO change")
+`MPRcz(LODETAO        ,1.0        ,""                                   ,"Eta0 shift modification factor for stress effect")
+
+// Well proximity effect Parameters
+`MPRcz(SCREF          ,1.0e-6     ,"m"                                  ,"Distance between OD-edge and well edge of a reference device")
+`MPRnb(WEB            ,0.0        ,""                                   ,"Coefficient for SCB")
+`MPRnb(WEC            ,0.0        ,""                                   ,"Coefficient for SCC")
+
+//  --------------------------------------------------------------------------------------------------------------
+//  JUNCAP Parameters
+//  --------------------------------------------------------------------------------------------------------------
+`include "JUNCAP200_parlist.include"
+
+//  --------------------------------------------------------------------------------------------------------------
+//  Other Parameters
+//  --------------------------------------------------------------------------------------------------------------
+`ifdef __XYCE__
+`MPRnb_BOTH(DTA       ,0.0        ,"K"                                  ,"Temperature offset w.r.t. ambient temperature")
+`else
+`IPRnb(DTA            ,0.0        ,"K"                                  ,"Temperature offset w.r.t. ambient temperature")
+`endif
+`ALIAS(TRISE, DTA)
+
+//  --------------------------------------------------------------------------------------------------------------
+//  Variables
+//  --------------------------------------------------------------------------------------------------------------
+
+// Variables for switch (initial_model parts)
+integer CHNL_TYPE, SWGEO_i, SWIGATE_i, SWIMPACT_i, SWGIDL_i, SWJUNCAP_i, SWJUNASYM_i, SWNUD_i, SWEDGE_i, SWDELVTAC_i, SWIGN_i;
+
+// Instance local variables
+real NF_i, invNF, L_i, W_i, SA_i, SB_i, SD_i, SC_i, XGW_i, JW_i, SCA_i, SCB_i, SCC_i, NGCON_i, MULT_i, FACTUO_i, DELVTO_i;
+real FACTUOEDGE_i, DELVTOEDGE_i;
+
+// Instance local variables for juncap
+real ABS_i, LSS_i, LGS_i, ABD_i, LSD_i, LGD_i, jwcorr, jww;
+
+// Variables of clipped global model parameters
+real TOXO_i, EPSROXO_i, NSUBO_i, WSEG_i, NPCK_i, WSEGP_i, LPCK_i, TOXOVO_i, TOXOVDO_i, LOV_i, LOVD_i, LP1_i, LP2_i, WBET_i;
+real AXL_i, ALP1L2_i, ALP2L2_i, SAREF_i, SBREF_i, KVSAT_i, LLODKUO_i, WLODKUO_i, LLODVTH_i, WLODVTH_i, LODETAO_i, SCREF_i;
+real WEB_i, WEC_i, RSHG_i, RSH_i, RSHD_i, RINT_i, RVPOLY_i, NSUBEDGEO_i, LPEDGE_i;
+
+// Variables of local model parameters
+real VFB_p, STVFB_p, ST2VFB_p, TOX_p, EPSROX_p, NEFF_p, FACNEFFAC_p, GFACNUD_p, VSBNUD_p, DVSBNUD_p, VNSUB_p, NSLP_p, DNSUB_p;
+real DPHIB_p, DELVTAC_p, NP_p, CT_p, CTG_p, CTB_p, STCT_p, TOXOV_p, TOXOVD_p, NOV_p, NOVD_p, PSCE_p, PSCED_p, PSCEB_p, CF_p;
+real CFD_p, CFB_p, BETN_p, STBET_p, MUE_p, STMUE_p, THEMU_p, STTHEMU_p, CS_p, STCS_p, THECS_p, STTHECS_p, XCOR_p, STXCOR_p;
+real FETA_p, RS_p, STRS_p, RSB_p, RSG_p, THESAT_p, STTHESAT_p, THESATB_p, THESATG_p, AX_p, ALP_p, ALP1_p, ALP2_p, VP_p, A1_p;
+real A2_p, STA2_p, A3_p, A4_p, GCO_p, IGINV_p, IGOV_p, IGOVD_p, STIG_p, GC2_p, GC3_p, CHIB_p, AGIDL_p, AGIDLD_p, BGIDL_p, BGIDLD_p;
+real STBGIDL_p, STBGIDLD_p, CGIDL_p, CGIDLD_p, COX_p, CGOV_p, CGOVD_p, CGBOV_p, CFR_p, CFRD_p, FNT_p, FNTEXC_p, NFA_p, NFB_p, NFC_p;
+real EF_p, VFBEDGE_p, STVFBEDGE_p, DPHIBEDGE_p, NEFFEDGE_p, CTEDGE_p, BETNEDGE_p, STBETEDGE_p, PSCEEDGE_p, PSCEBEDGE_p, PSCEDEDGE_p;
+real CFEDGE_p, CFDEDGE_p, CFBEDGE_p, FNTEDGE_p, NFAEDGE_p, NFBEDGE_p, NFCEDGE_p, EFEDGE_p, RG_p, RSE_p, RDE_p, RWELL_p, RBULK_p;
+real RJUNS_p, RJUND_p;
+`ifdef SelfHeating
+    real RTH_p, CTH_p, STRTH_p;
+`endif // SelfHeating
+`ifdef NQSmodel
+    real MUNQS_p;
+`endif // NQSmodel
+
+// Variables of clipped local model parameters
+real TR_i, QMC_i, VFB_i, STVFB_i, ST2VFB_i, STCT_i, TOX_i, EPSROX_i, NEFF_i, FACNEFFAC_i, GFACNUD_i, VSBNUD_i, DVSBNUD_i, VNSUB_i, NSLP_i;
+real DNSUB_i, DPHIB_i, DELVTAC_i, NP_i, CT_i, CTG_i, CTB_i, TOXOV_i, TOXOVD_i, NOV_i, NOVD_i, CF_i, CFD_i, CFB_i, PSCE_i, PSCEB_i, PSCED_i;
+real BETN_i, STBET_i, MUE_i, STMUE_i, THEMU_i, STTHEMU_i, CS_i, STCS_i, THECS_i, STTHECS_i, XCOR_i, STXCOR_i, FETA_i, RS_i, STRS_i;
+real RSB_i, RSG_i, THESAT_i, STTHESAT_i, THESATB_i, THESATG_i, AX_i, ALP_i, ALP1_i, ALP2_i, VP_i, A1_i, A2_i, STA2_i, A3_i, A4_i;
+real GCO_i, IGINV_i, IGOV_i, IGOVD_i, STIG_i, GC2_i, GC3_i, CHIB_i, AGIDL_i, AGIDLD_i, BGIDL_i, BGIDLD_i, STBGIDL_i, STBGIDLD_i;
+real CGIDL_i, CGIDLD_i, COX_i, CGOV_i, CGOVD_i, CGBOV_i, CFR_i, CFRD_i, FNT_i, FNTEXC_i, NFA_i, NFB_i, NFC_i, EF_i, VFBEDGE_i;
+real STVFBEDGE_i, DPHIBEDGE_i, NEFFEDGE_i, CTEDGE_i, BETNEDGE_i, STBETEDGE_i, PSCEEDGE_i, PSCEBEDGE_i, PSCEDEDGE_i, CFEDGE_i;
+real CFDEDGE_i, CFBEDGE_i, FNTEDGE_i, NFAEDGE_i, NFBEDGE_i, NFCEDGE_i, EFEDGE_i, RG_i, RSE_i, RDE_i, RBULK_i, RJUNS_i, RJUND_i;
+real RWELL_i;
+`ifdef SelfHeating
+    real RTH_i, CTH_i, STRTH_i;
+`endif // SelfHeating
+`ifdef NQSmodel
+    real MUNQS_i;
+`endif // NQSmodel
+
+// Variables for scaling rules
+real iL, iW, delLPS, delWOD, LE, WE, LEcv, WEcv, Lcv, Wcv, iLE, iWE, L_f, L_slif, W_f, XGWE, NSUB0e, NPCKe, LPCKe, AA, BB, NSUB;
+real FBET1e, LP1e, GPE, GWE, tmpx, Lnoi, Lred, WE_edge, iWE_edge, GPE_edge, KVTHOWE, KUOWE;
+`ifdef SelfHeating
+    real deltaRth;
+`endif // SelfHeating
+
+// Variables for binning-rules
+real iLEWE, iiLE, iiWE, iiLEWE, iiiLEWE, iLEcv, iiLEcv, iiWEcv, iiLEWEcv, iiiLEWEcv, iLcv, iiLcv, iiWcv, iiLWcv, iiiLWcv;
+
+// Variables for general temperature scaling
+real TKR, TKA, rTa, delTa, phita, inv_phita, TKD, TKD_sq, delT, rTn, ln_rTn, inv_phit, Eg, phibFac;
+
+// JUNCAP2 variables
+`include "JUNCAP200_varlist1.include"
+`include "JUNCAP200_varlist2.include"
+
+// Local parameters after temperature scaling and variables used in self heating effect
+real VFB_T, CT_T, CTG_T, BETN_T, MUE_T, THEMU_T, CS_T, THECS_T, XCOR_T, RS_T, BGIDL_T, BGIDLD_T, A2_T, VFBEDGE_T, BETNEDGE_T;
+`ifdef SelfHeating
+    real RTH_T;
+`else // SelfHeating
+    // in the self heating model, these variables are declared locally in the evaluate block
+    real phit, BET_i, BETEDGE_i, nt0, nt, THESAT_T, Sfl_prefac, phit0edge, Gfedge2, lnGfedge2, Sfl_prefac_edge;
+    real ntedge;
+`endif // SelfHeating
+
+// Variables for channel temperature scaling (including self heating effect)
+real phib_dc, G_0_dc, kp, np, arg2max, qlim2, qb0, dphibq, sqrt_phib_dc, phix_dc, aphi_dc, bphi_dc, phix2, phix1_dc, alpha_b;
+real us1, us21, phib_ac, G_0_ac, phix_ac, aphi_ac, bphi_ac, phix1_ac, tf_ct, tf_bet, tf_mue, tf_cs, tf_xcor, tf_ther, THER_i, tf_thesat;
+real tf_betedge, phibedge, Gfedge, phixedge, aphiedge, bphiedge, phix2edge, phix1edge;
+
+// Variables used in instance initializing
+real EPSSI, EPSOX, CoxPrime, tox_sq, Cox_over_q, NEFFAC_i, qq, E_eff0, eta_mu, eta_mu1, inv_AX, inv_VP, CoxovPrime, CoxovPrime_d, GOV_s;
+real GOV_d, GOV2_s, GOV2_d, SP_OV_eps2_s, SP_OV_a_s, SP_OV_delta1_s, SP_OV_eps2_d, SP_OV_a_d, SP_OV_delta1_d, inv_CHIB, B_fact, BCH;
+real BOV, BOV_d, GCQ, tf_ig, AGIDLs, AGIDLDs, BGIDLs, BGIDLDs, fac_exc, ggate, gsource, gdrain, gbulk, gjuns, gjund, gwell;
+
+// Variables for bias affectation
+real Vgs, Vds, Vsb, Vdb, Vgb, Vjun_s, Vjun_d, VgsPrime, VsbPrime, VdbPrime, VgdPrime;
+real Vdsx;
+
+// Global variables used in PSP103_SPCalculation.include
+real Vgbstar, Vgb1, Vdsp, delVg, Vdsat_lim, Vdsat;
+
+// Global variables used in current and charge calculations
+real xgs_ov, xgd_ov, Vsbstar_dc, Vsbstar_dc_tmp, Vmb, us, usnew, Vmbnew, qeff1_dc, Voxm_dc, GdL_dc, eta_p_dc, Gvsat_dc, Gmob_dL_dc, x_ds_dc;
+real x_m_dc, Gf_dc, Vdsat_dc, Udse_dc, SP_OV_xg, xs_ov, xd_ov, Vovs, Vovd, zg, TP, Fs1, Fs2, Fs3, Fs, Vm, Dch, arg2mina, psi_t, arg1;
+real Dsi, Dgate, Igc0, igc, igcd_h, u0, x, u0_div_H, Bg, Ag, xsq, inv_x, ex, inv_ex, Sg, Igc, Igb, Vtovd, Igidl, Vtovs, Igisl;
+real delVsat, Vsbstar_ac, xg_ac, qeff1_ac, Voxm_ac, alpha_ac, dps_ac, qim_ac, GdL_ac, H_ac, QG, QI, QD, QB, Fj, Fj2;
+real QCLM, Qg, Qd, Qb, Qs, Qgs_ov, Qgd_ov, Qgb_ov, Qfgs, Qfgd, rgatenoise, rsourcenoise, rdrainnoise, rbulknoise, rwellnoise, rjundnoise;
+real rjunsnoise;
+
+// Global variables used in macros
+real tme1, tme2;
+real inv_GOV, SP_OV_eps, SP_OV_delta, mutau, nu;
+real Q_EDGE_xsth, Q_EDGE_xth0, Q_EDGE_xth, Q_EDGE_n, Q_EDGE_n_inv, Q_EDGE_xgt, Q_EDGE_xgt0, Q_EDGE_xgt0e, Q_EDGE_qi0si, Q_EDGE_qi0;
+real Q_EDGE_exp_x, Q_EDGE_d0, Q_EDGE_d0p, Q_EDGE_sqerr, Q_EDGE_errq;
+
+// Global variables used in noise section
+real N1, Nm1, Delta_N1, Sfl, t1, sqt2, t2, r, lc, lcinv2, g_ideal, mid, temp2_exc, wsat_exc, temp_exc, thesat1_exc, zsat_exc, Gvsat_exc;
+real gfac, Sidexc, sqid, mig, migid0, migid, CGeff, sqig, c_igid, shot_igcsx, shot_igcdx, shot_igsov, shot_igdov, shot_iavl, jnoisex_s, jnoisex_d;
+real shot_igs, shot_igd, anoisedge, N1edge, Nm1edge, Delta_N1edge, H0edge, t1edge, sqt2edge, t2edge, redge, lcedge, lcinv2edge;
+real g_idealedge;
+
+// Variables used in NQS-calculations
+`ifdef NQSmodel
+    integer SWNQS_i;
+    real Gf_ac, xgm_dc, thesat1_dc, xgm_ac, x_m_ac, thesat1_ac, margin_dc, margin_ac;
+    real Qp1_0, Qp2_0, Qp3_0, Qp4_0, Qp5_0, Qp6_0, Qp7_0, Qp8_0, Qp9_0, fk1, fk2, fk3, fk4, fk5, fk6, fk7, fk8, fk9, phi_p1, phi_p2, phi_p3;
+    real phi_p4, phi_p5, phi_p6, phi_p7, phi_p8, phi_p9, Qp1, Qp2, Qp3, Qp4, Qp5, Qp6, Qp7, Qp8, Qp9, Qp0, QpN, QG_NQS, QS_NQS, QD_NQS, pd;
+    real Gp, Gp2, a_factrp, marginp, x_sp, x_dp, zsat_nqs, dfQi, fQi, dQis, dQis_1, d2Qis, dQbs, dQy, d2Qy, dpsy2, ym, inorm, Tnorm, Qb_tmp;
+    real QbSIGN, r_nqs, vnorm, vnorm_inv, NQS_xg1, NQS_yg, NQS_z, NQS_eta, NQS_a, NQS_c, NQS_tau, NQS_D0, NQS_xi, NQS_p, NQS_q, NQS_temp;
+    real NQS_A_fac, NQS_xbar, NQS_w, NQS_x0, NQS_u, NQS_y0, xphi, fk0, thesat2, Fvsat, temp3, temp4, temp5, temp6, temp7, temp8, temp9;
+`endif // NQSmodel
+
+//  --------------------------------------------------------------------------------------------------------------
+//  Variables for operating point info
+//  --------------------------------------------------------------------------------------------------------------
+real id_op, is, ig, ib, P_D, facvsb, facvsb0, sig1k, vth_i, vts_i, ids_i;
+`OPP(ctype             ,""             ,"Flag for channel type")
+`OPP(sdint             ,""             ,"Flag for source-drain interchange")
+`OPP(ise               ,"A"            ,"Total source current")
+`OPP(ige               ,"A"            ,"Total gate current")
+`OPP(ide               ,"A"            ,"Total drain current")
+`OPP(ibe               ,"A"            ,"Total bulk current")
+`OPP(ids               ,"A"            ,"Drain current, excl. edge transistor currents, avalanche, tunnel, GISL, GIDL, and junction currents")
+`OPP(idb               ,"A"            ,"Drain to bulk current")
+`OPP(isb               ,"A"            ,"Source to bulk current")
+`OPP(igs               ,"A"            ,"Gate-source tunneling current")
+`OPP(igd               ,"A"            ,"Gate-drain tunneling current")
+`OPP(igb               ,"A"            ,"Gate-bulk tunneling current")
+`OPP(idedge            ,"A"            ,"Drain current of edge transistors")
+`OPP(igcs              ,"A"            ,"Gate-channel tunneling current (source component)")
+`OPP(igcd              ,"A"            ,"Gate-channel tunneling current (drain component)")
+`OPP(iavl              ,"A"            ,"Substrate current due to weak avelanche")
+`OPP(igisl             ,"A"            ,"Gate-induced source leakage current")
+`OPP(igidl             ,"A"            ,"Gate-induced drain leakage current")
+`OPP(ijs               ,"A"            ,"Total source junction current")
+`OPP(ijsbot            ,"A"            ,"Source junction current (bottom component)")
+`OPP(ijsgat            ,"A"            ,"Source junction current (gate-edge component)")
+`OPP(ijssti            ,"A"            ,"Source junction current (STI-edge component)")
+`OPP(ijd               ,"A"            ,"Total drain junction current")
+`OPP(ijdbot            ,"A"            ,"Drain junction current (bottom component)")
+`OPP(ijdgat            ,"A"            ,"Drain junction current (gate-edge component)")
+`OPP(ijdsti            ,"A"            ,"Drain junction current (STI-edge component)")
+`OPP(vds               ,"V"            ,"Drain-source voltage")
+`OPP(vgs               ,"V"            ,"Gate-source voltage")
+`OPP(vsb               ,"V"            ,"Source-bulk voltage")
+`OPP(vto               ,"V"            ,"Zero-bias threshold voltage")
+`OPP(vts               ,"V"            ,"Threshold voltage including back bias effects")
+`OPP(vth               ,"V"            ,"Threshold voltage including back bias and drain bias effects")
+`OPP(vgt               ,"V"            ,"Effective gate drive voltage including back bias and drain bias effects")
+`OPP(vdss              ,"V"            ,"Drain saturation voltage at actual bias")
+`OPP(vsat              ,""             ,"Saturation limit")
+`ifdef OPderiv
+    `OPP(gm                ,"1/Ohm"        ,"Transconductance")
+    `OPP(gmb               ,"1/Ohm"        ,"Substrate transconductance")
+    `OPP(gds               ,"1/Ohm"        ,"Output conductance")
+    `OPP(gjs               ,"1/Ohm"        ,"Source junction conductance")
+    `OPP(gjd               ,"1/Ohm"        ,"Drain junction conductance")
+    `OPP(cdd               ,"F"            ,"Drain capacitance")
+    `OPP(cdg               ,"F"            ,"Drain-gate capacitance")
+    `OPP(cds               ,"F"            ,"Drain-source capacitance")
+    `OPP(cdb               ,"F"            ,"Drain-bulk capacitance")
+    `OPP(cgd               ,"F"            ,"Gate-drain capacitance")
+    `OPP(cgg               ,"F"            ,"Gate capacitance")
+    `OPP(cgs               ,"F"            ,"Gate-source capacitance")
+    `OPP(cgb               ,"F"            ,"Gate-bulk capacitance")
+    `OPP(csd               ,"F"            ,"Source-drain capacitance")
+    `OPP(csg               ,"F"            ,"Source-gate capacitance")
+    `OPP(css               ,"F"            ,"Source capacitance")
+    `OPP(csb               ,"F"            ,"Source-bulk capacitance")
+    `OPP(cbd               ,"F"            ,"Bulk-drain capacitance")
+    `OPP(cbg               ,"F"            ,"Bulk-gate capacitance")
+    `OPP(cbs               ,"F"            ,"Bulk-source capacitance")
+    `OPP(cbb               ,"F"            ,"Bulk capacitance")
+    `OPP(cgsol             ,"F"            ,"Total gate-source overlap capacitance")
+    `OPP(cgdol             ,"F"            ,"Total gate-drain overlap capacitance")
+    `OPP(cjs               ,"F"            ,"Total source junction capacitance")
+    `OPP(cjsbot            ,"F"            ,"Source junction capacitance (bottom component)")
+    `OPP(cjsgat            ,"F"            ,"Source junction capacitance (gate-edge component)")
+    `OPP(cjssti            ,"F"            ,"Source junction capacitance (STI-edge component)")
+    `OPP(cjd               ,"F"            ,"Total drain junction capacitance")
+    `OPP(cjdbot            ,"F"            ,"Drain junction capacitance (bottom component)")
+    `OPP(cjdgat            ,"F"            ,"Drain junction capacitance (gate-edge component)")
+    `OPP(cjdsti            ,"F"            ,"Drain junction capacitance (STI-edge component)")
+`endif // OPderiv
+`OPP(weff              ,"m"            ,"Effective channel width for geometrical models")
+`OPP(leff              ,"m"            ,"Effective channel length for geometrical models")
+`ifdef OPderiv
+    `OPP(u                 ,""             ,"Transistor gain")
+    `OPP(rout              ,"Ohm"          ,"Small-signal output resistance")
+    `OPP(vearly            ,"V"            ,"Equivalent Early voltage")
+    `OPP(beff              ,"A/V^2"        ,"Gain factor")
+    `OPP(fug               ,"Hz"           ,"Unity gain frequency at actual bias")
+    `OPP(rg                ,"Ohm"          ,"Gate resistance")
+    `OPP(sfl               ,"A^2/Hz"       ,"Flicker noise current spectral density at 1 Hz")
+    `OPP(sqrtsff           ,"V/sqrt(Hz)"   ,"Input-referred RMS white noise voltage spectral density at 1 kHz")
+    `OPP(sqrtsfw           ,"V/sqrt(Hz)"   ,"Input-referred RMS white noise voltage spectral density")
+    `OPP(sid               ,"A^2/Hz"       ,"White noise current spectral density")
+    `OPP(sig               ,"A^2/Hz"       ,"Induced gate noise current spectral density at 1 Hz")
+    `OPP(cigid             ,""             ,"Imaginary part of correlation coefficient between Sig and Sid")
+    `OPP(fknee             ,"Hz"           ,"Cross-over frequency above which white noise is dominant")
+    `OPP(sigs              ,"A^2/Hz"       ,"Gate-source current noise spectral density")
+    `OPP(sigd              ,"A^2/Hz"       ,"Gate-drain current noise spectral density")
+    `OPP(siavl             ,"A^2/Hz"       ,"Impact ionization current noise spectral density")
+    `OPP(ssi               ,"A^2/Hz"       ,"Total source junction current noise spectral density")
+    `OPP(sdi               ,"A^2/Hz"       ,"Total drain junction current noise spectral density")
+    `OPP(sfledge           ,"A^2/Hz"       ,"Flicker noise current spectral density at 1 Hz of edge transistors")
+    `OPP(sidedge           ,"A^2/Hz"       ,"White noise current spectral density of edge transistors")
+`endif // OPderiv
+// local parameters after scaling, T-scaling, and clipping
+`OPP(lp_vfb            ,"V"            ,"Local parameter VFB after T-scaling and clipping")
+`OPP(lp_stvfb          ,"V/K"          ,"Local parameter STVFB after clipping")
+`OPP(lp_st2vfb         ,"K^-1"         ,"Local parameter ST2VFB after clipping")
+`OPP(lp_tox            ,"m"            ,"Local parameter TOX after clipping")
+`OPP(lp_epsrox         ,""             ,"Local parameter EPSROX after clipping")
+`OPP(lp_neff           ,"m^-3"         ,"Local parameter NEFF after clipping")
+`OPP(lp_facneffac      ,""             ,"Local parameter FACNEFFAC after clipping")
+`OPP(lp_gfacnud        ,""             ,"Local parameter GFACNUD after clipping")
+`OPP(lp_vsbnud         ,"V"            ,"Local parameter VSBNUD after clipping")
+`OPP(lp_dvsbnud        ,"V"            ,"Local parameter DVSBNUD after clipping")
+`OPP(lp_vnsub          ,"V"            ,"Local parameter VNSUB after clipping")
+`OPP(lp_nslp           ,"V"            ,"Local parameter NSLP after clipping")
+`OPP(lp_dnsub          ,"V^-1"         ,"Local parameter DNSUB after clipping")
+`OPP(lp_dphib          ,"V"            ,"Local parameter DPHIB after clipping")
+`OPP(lp_delvtac        ,"V"            ,"Local parameter DELVTAC after clipping")
+`OPP(lp_np             ,"m^-3"         ,"Local parameter NP after clipping")
+`OPP(lp_toxov          ,"m"            ,"Local parameter TOXOV after clipping")
+`OPP(lp_toxovd         ,"m"            ,"Local parameter TOXOVD after clipping")
+`OPP(lp_nov            ,"m^-3"         ,"Local parameter NOV after clipping")
+`OPP(lp_novd           ,"m^-3"         ,"Local parameter NOVD after clipping")
+`OPP(lp_ct             ,""             ,"Local parameter CT after clipping")
+`OPP(lp_ctg            ,""             ,"Local parameter CTG after clipping")
+`OPP(lp_ctb            ,""             ,"Local parameter CTB after clipping")
+`OPP(lp_stct           ,""             ,"Local parameter STCT after clipping")
+`OPP(lp_cf             ,""             ,"Local parameter CF after clipping")
+`OPP(lp_cfd            ,"V^-1"         ,"Local parameter CFD after clipping")
+`OPP(lp_cfb            ,"V^-1"         ,"Local parameter CFB after clipping")
+`OPP(lp_psce           ,""             ,"Local parameter PSCE after clipping")
+`OPP(lp_psceb          ,"V^-1"         ,"Local parameter PSCEB after clipping")
+`OPP(lp_psced          ,"V^-1"         ,"Local parameter PSCED after clipping")
+`OPP(lp_betn           ,"m^2/(V s)"    ,"Local parameter BETN after T-scaling and clipping")
+`OPP(lp_stbet          ,""             ,"Local parameter STBET after clipping")
+`OPP(lp_mue            ,"m/V"          ,"Local parameter MUE after T-scaling and clipping")
+`OPP(lp_stmue          ,""             ,"Local parameter STMUE after clipping")
+`OPP(lp_themu          ,""             ,"Local parameter THEMU after T-scaling and clipping")
+`OPP(lp_stthemu        ,""             ,"Local parameter STTHEMU after clipping")
+`OPP(lp_cs             ,""             ,"Local parameter CS after T-scaling and clipping")
+`OPP(lp_stcs           ,""             ,"Local parameter STCS after clipping")
+`OPP(lp_thecs          ,""             ,"Local parameter THECS after T-scaling and clipping")
+`OPP(lp_stthecs        ,""             ,"Local parameter STTHECS after clipping")
+`OPP(lp_xcor           ,"V^-1"         ,"Local parameter XCOR after T-scaling and clipping")
+`OPP(lp_stxcor         ,""             ,"Local parameter STXCOR after clipping")
+`OPP(lp_feta           ,""             ,"Local parameter FETA after clipping")
+`OPP(lp_rs             ,"Ohm"          ,"Local parameter RS after T-scaling and clipping")
+`OPP(lp_strs           ,""             ,"Local parameter STRS after clipping")
+`OPP(lp_rsb            ,"V^-1"         ,"Local parameter RSB after clipping")
+`OPP(lp_rsg            ,"V^-1"         ,"Local parameter RSG after clipping")
+`OPP(lp_thesat         ,"V^-1"         ,"Local parameter THESAT after T-scaling and clipping")
+`OPP(lp_stthesat       ,""             ,"Local parameter STTHESAT after clipping")
+`OPP(lp_thesatb        ,"V^-1"         ,"Local parameter THESATB after clipping")
+`OPP(lp_thesatg        ,"V^-1"         ,"Local parameter THESATG after clipping")
+`OPP(lp_ax             ,""             ,"Local parameter AX after clipping")
+`OPP(lp_alp            ,""             ,"Local parameter ALP after clipping")
+`OPP(lp_alp1           ,"V"            ,"Local parameter ALP1 after clipping")
+`OPP(lp_alp2           ,"V^-1"         ,"Local parameter ALP2 after clipping")
+`OPP(lp_vp             ,"V"            ,"Local parameter VP after clipping")
+`OPP(lp_a1             ,""             ,"Local parameter A1 after clipping")
+`OPP(lp_a2             ,"V"            ,"Local parameter A2 after T-scaling and clipping")
+`OPP(lp_sta2           ,""             ,"Local parameter STA2 after clipping")
+`OPP(lp_a3             ,""             ,"Local parameter A3 after clipping")
+`OPP(lp_a4             ,"1/sqrt(V)"    ,"Local parameter A4 after clipping")
+`OPP(lp_gco            ,""             ,"Local parameter GCO after clipping")
+`OPP(lp_iginv          ,"A"            ,"Local parameter IGINV after T-scaling and clipping")
+`OPP(lp_igov           ,"A"            ,"Local parameter IGOV after T-scaling and clipping")
+`OPP(lp_igovd          ,"A"            ,"Local parameter IGOVD after T-scaling and clipping")
+`OPP(lp_stig           ,""             ,"Local parameter STIG after clipping")
+`OPP(lp_gc2            ,""             ,"Local parameter GC2 after clipping")
+`OPP(lp_gc3            ,""             ,"Local parameter GC3 after clipping")
+`OPP(lp_chib           ,"V"            ,"Local parameter CHIB after clipping")
+`OPP(lp_agidl          ,"A/V^3"        ,"Local parameter AGIDL after clipping")
+`OPP(lp_agidld         ,"A/V^3"        ,"Local parameter AGIDLD after clipping")
+`OPP(lp_bgidl          ,"V"            ,"Local parameter BGIDL after T-scaling and clipping")
+`OPP(lp_bgidld         ,"V"            ,"Local parameter BGIDLD after T-scaling and clipping")
+`OPP(lp_stbgidl        ,"V/K"          ,"Local parameter STBGIDL after clipping")
+`OPP(lp_stbgidld       ,"V/K"          ,"Local parameter STBGIDLD after clipping")
+`OPP(lp_cgidl          ,""             ,"Local parameter CGIDL after clipping")
+`OPP(lp_cgidld         ,""             ,"Local parameter CGIDLD after clipping")
+`OPP(lp_cox            ,"F"            ,"Local parameter COX after clipping")
+`OPP(lp_cgov           ,"F"            ,"Local parameter CGOV after clipping")
+`OPP(lp_cgovd          ,"F"            ,"Local parameter CGOVD after clipping")
+`OPP(lp_cgbov          ,"F"            ,"Local parameter CGBOV after clipping")
+`OPP(lp_cfr            ,"F"            ,"Local parameter CFR after clipping")
+`OPP(lp_cfrd           ,"F"            ,"Local parameter CFRD after clipping")
+`OPP(lp_fnt            ,""             ,"Local parameter FNT after clipping")
+`OPP(lp_fntexc         ,""             ,"Local parameter FNTEXC after clipping")
+`OPP(lp_nfa            ,"1/(V m^4)"    ,"Local parameter NFA after clipping")
+`OPP(lp_nfb            ,"1/(V m^4)"    ,"Local parameter NFB after clipping")
+`OPP(lp_nfc            ,"V^-1"         ,"Local parameter NFC after clipping")
+`OPP(lp_ef             ,""             ,"Local parameter EF after clipping")
+`OPP(lp_vfbedge        ,"V"            ,"Local parameter VFBEDGE after T-scaling and clipping")
+`OPP(lp_stvfbedge      ,"V/K"          ,"Local parameter STVFBEDGE after clipping")
+`OPP(lp_dphibedge      ,"V"            ,"Local parameter DPHIBEDGE after clipping")
+`OPP(lp_neffedge       ,"m^-3"         ,"Local parameter NEFFEDGE after clipping")
+`OPP(lp_ctedge         ,""             ,"Local parameter CTEDGE after clipping")
+`OPP(lp_betnedge       ,"m^2/V/s"      ,"Local parameter BETNEDGE after T-scaling and clipping")
+`OPP(lp_stbetedge      ,""             ,"Local parameter STBETEDGE after clipping")
+`OPP(lp_psceedge       ,""             ,"Local parameter PSCEEDGE after clipping")
+`OPP(lp_pscebedge      ,"V^-1"         ,"Local parameter PSCEBEDGE after clipping")
+`OPP(lp_pscededge      ,"V^-1"         ,"Local parameter PSCEDEDGE after clipping")
+`OPP(lp_cfedge         ,"V"            ,"Local parameter CFEDGE after clipping")
+`OPP(lp_cfdedge        ,"V^-1"         ,"Local parameter CFDEDGE after clipping")
+`OPP(lp_cfbedge        ,"V^-1"         ,"Local parameter CFBEDGE after clipping")
+`OPP(lp_fntedge        ,""             ,"Local parameter FNTEDGE after clipping")
+`OPP(lp_nfaedge        ,"1/(V m^4)"    ,"Local parameter NFAEDGE after clipping")
+`OPP(lp_nfbedge        ,"1/(V m^4)"    ,"Local parameter NFBEDGE after clipping")
+`OPP(lp_nfcedge        ,"V^-1"         ,"Local parameter NFCEDGE after clipping")
+`OPP(lp_efedge         ,""             ,"Local parameter EFEDGE after clipping")
+`OPP(lp_rg             ,"Ohm"          ,"Local parameter RG after clipping")
+`OPP(lp_rse            ,"Ohm"          ,"Local parameter RSE after clipping")
+`OPP(lp_rde            ,"Ohm"          ,"Local parameter RDE after clipping")
+`OPP(lp_rbulk          ,"Ohm"          ,"Local parameter RBULK after clipping")
+`OPP(lp_rwell          ,"Ohm"          ,"Local parameter RWELL after clipping")
+`OPP(lp_rjuns          ,"Ohm"          ,"Local parameter RJUNS after clipping")
+`OPP(lp_rjund          ,"Ohm"          ,"Local parameter RJUND after clipping")
+`ifdef SelfHeating
+    `OPP(lp_rth            ,"K/W"          ,"Local parameter RTH after T-scaling and clipping")
+    `OPP(lp_cth            ,"J/K"          ,"Local parameter CTH after clipping")
+    `OPP(lp_strth          ,""             ,"Local parameter STRTH after clipping")
+    `OPP(pdiss             ,"W"            ,"Power dissipation")
+    `OPP(dtsh              ,"K"            ,"Temperature rise due to self heating")
+`endif // SelfHeating
+`OPP(tk                ,"K"            ,"Device Temperature")
+`OPP(cjosbot           ,"F"            ,"Bottom component of total zero-bias source junction capacitance at device temperature")
+`OPP(cjossti           ,"F"            ,"STI-edge component of total zero-bias source junction capacitance at device temperature")
+`OPP(cjosgat           ,"F"            ,"Gate-edge component of total zero-bias source junction capacitance at device temperature")
+`OPP(vbisbot           ,"V"            ,"Built-in voltage of source-side bottom junction at device temperature")
+`OPP(vbissti           ,"V"            ,"Built-in voltage of source-side STI-edge junction at device temperature")
+`OPP(vbisgat           ,"V"            ,"Built-in voltage of source-side gate-edge junction at device temperature")
+`OPP(idsatsbot         ,"A"            ,"Total source-side bottom junction saturation current")
+`OPP(idsatssti         ,"A"            ,"Total source-side STI-edge junction saturation current")
+`OPP(idsatsgat         ,"A"            ,"Total source-side gate-edge junction saturation current")
+`OPP(cjosbotd          ,"F"            ,"Bottom component of total zero-bias drain junction capacitance at device temperature")
+`OPP(cjosstid          ,"F"            ,"STI-edge component of total zero-bias drain junction capacitance at device temperature")
+`OPP(cjosgatd          ,"F"            ,"Gate-edge component of total zero-bias drain junction capacitance at device temperature")
+`OPP(vbisbotd          ,"V"            ,"Built-in voltage of drain-side bottom junction at device temperature")
+`OPP(vbisstid          ,"V"            ,"Built-in voltage of drain-side STI-edge junction at device temperature")
+`OPP(vbisgatd          ,"V"            ,"Built-in voltage of drain-side gate-edge junction at device temperature")
+`OPP(idsatsbotd        ,"A"            ,"Total drain-side bottom junction saturation current")
+`OPP(idsatsstid        ,"A"            ,"Total drain-side STI-edge junction saturation current")
+`OPP(idsatsgatd        ,"A"            ,"Total drain-side gate-edge junction saturation current")
+`ifdef NQSmodel
+    `OPP(lp_munqs          ,""             ,"Local parameter MUNQS after clipping")
+`endif // NQSmodel
+
+//  --------------------------------------------------------------------------------------------------------------
+//  Analog block with all calculations and contribs
+//  --------------------------------------------------------------------------------------------------------------
+analog begin
+
+    //  --------------------------------------------------------------------------------------------------------------
+    //  Definition of bias/instance independent model variables
+    //  --------------------------------------------------------------------------------------------------------------
+    `INITIAL_MODEL
+    begin : initial_model
+
+        // Clipping and rounding of switch parameters
+        if (TYPE >= 0) begin
+            CHNL_TYPE   = `NMOS;
+        end else begin
+            CHNL_TYPE   = `PMOS;
+        end
+        EPSSI       = `EPSO * `EPSRSI;
+        SWGEO_i     =  floor(`CLIP_BOTH(SWGEO,     0.0, 2.0) + 0.5);
+        SWIGATE_i   =  floor(`CLIP_BOTH(SWIGATE,   0.0, 1.0) + 0.5);
+        SWIMPACT_i  =  floor(`CLIP_BOTH(SWIMPACT,  0.0, 1.0) + 0.5);
+        SWGIDL_i    =  floor(`CLIP_BOTH(SWGIDL,    0.0, 1.0) + 0.5);
+        SWJUNCAP_i  =  floor(`CLIP_BOTH(SWJUNCAP,  0.0, 3.0) + 0.5);
+        SWJUNASYM_i =  floor(`CLIP_BOTH(SWJUNASYM, 0.0, 1.0) + 0.5);
+        SWNUD_i     =  floor(`CLIP_BOTH(SWNUD,     0.0, 2.0) + 0.5);
+        SWEDGE_i    =  floor(`CLIP_BOTH(SWEDGE,    0.0, 1.0) + 0.5);
+        SWDELVTAC_i =  floor(`CLIP_BOTH(SWDELVTAC, 0.0, 1.0) + 0.5);
+        SWIGN_i     =  floor(`CLIP_BOTH(SWIGN, 0.0, 1.0) + 0.5);
+        QMC_i       = `CLIP_LOW(QMC, 0.0);
+        `ifdef NQSmodel
+            if (SWNQS < 0.5) begin
+                SWNQS_i     =  0;
+            end else begin
+                if (SWNQS < 1.5) begin
+                    SWNQS_i     =  1;
+                end else begin
+                    if (SWNQS < 2.5) begin
+                        SWNQS_i     =  2;
+                    end else begin
+                        if (SWNQS < 4.0) begin
+                            SWNQS_i     =  3;
+                        end else begin
+                            if (SWNQS < 7.0) begin
+                                SWNQS_i     =  5;
+                            end else begin
+                                SWNQS_i     =  9;
+                            end
+                        end
+                    end
+                end
+            end
+            inorm       =  1.0e-12;
+            r_nqs       =  1.0e3;
+            vnorm       =  10.0;
+            vnorm_inv   =  1.0 / vnorm;
+        `endif // NQSmodel
+
+        // Clipping of global model parameters
+        TOXO_i      = `CLIP_LOW(TOXO, 1.0e-10);
+        EPSROXO_i   = `CLIP_LOW(EPSROXO, 1.0);
+        NSUBO_i     = `CLIP_LOW(NSUBO, 1.0e20);
+        WSEG_i      = `CLIP_LOW(WSEG, 1.0e-10);
+        NPCK_i      = `CLIP_LOW(NPCK, 0.0);
+        WSEGP_i     = `CLIP_LOW(WSEGP, 1.0e-10);
+        LPCK_i      = `CLIP_LOW(LPCK, 1.0e-10);
+        TOXOVO_i    = `CLIP_LOW(TOXOVO, 1.0e-10);
+        TOXOVDO_i   = `CLIP_LOW(TOXOVDO, 1.0e-10);
+        LOV_i       = `CLIP_LOW(LOV, 0.0);
+        LOVD_i      = `CLIP_LOW(LOVD, 0.0);
+        LP1_i       = `CLIP_LOW(LP1, 1.0e-10);
+        LP2_i       = `CLIP_LOW(LP2, 1.0e-10);
+        WBET_i      = `CLIP_LOW(WBET, 1.0e-10);
+        AXL_i       = `CLIP_LOW(AXL, 0.0);
+        ALP1L2_i    = `CLIP_LOW(ALP1L2, 0.0);
+        ALP2L2_i    = `CLIP_LOW(ALP2L2, 0.0);
+        SAREF_i     = `CLIP_LOW(SAREF, 1.0e-9);
+        SBREF_i     = `CLIP_LOW(SBREF, 1.0e-9);
+        KVSAT_i     = `CLIP_BOTH(KVSAT, -1.0, 1.0);
+        LLODKUO_i   = `CLIP_LOW(LLODKUO, 0.0);
+        WLODKUO_i   = `CLIP_LOW(WLODKUO, 0.0);
+        LLODVTH_i   = `CLIP_LOW(LLODVTH, 0.0);
+        WLODVTH_i   = `CLIP_LOW(WLODVTH, 0.0);
+        LODETAO_i   = `CLIP_LOW(LODETAO, 0.0);
+        SCREF_i     = `CLIP_LOW(SCREF, 0.0);
+        WEB_i       =  WEB;
+        WEC_i       =  WEC;
+        RSHG_i      = `CLIP_LOW(RSHG, 0.0);
+        RSH_i       = `CLIP_LOW(RSH, 0.0);
+        RSHD_i      = `CLIP_LOW(RSHD, 0.0);
+        RINT_i      = `CLIP_LOW(RINT, 0.0);
+        RVPOLY_i    = `CLIP_LOW(RVPOLY, 0.0);
+        NSUBEDGEO_i = `CLIP_LOW(NSUBEDGEO, 1.0e20);
+        LPEDGE_i    = `CLIP_LOW(LPEDGE, 1.0e-10);
+`ifndef __XYCE__
+        // Transistor temperature
+        TR_i        = `CLIP_LOW(TR, -273.0);
+        TKR         = `KELVINCONVERSION + TR_i;
+        TKA         =  $temperature + DTA;
+        rTa         =  TKA / TKR;
+        delTa       =  TKA - TKR;
+        phita       =  TKA * `KBOL / `QELE;
+        inv_phita   =  1.0 / phita;
+        `ifdef SelfHeating
+            // do nothing
+        `else // SelfHeating
+            TKD         =  TKA;
+            `TempInitialize
+        `endif // SelfHeating
+
+        // JUNCAP2
+        `include "JUNCAP200_InitModel.include"
+`endif
+
+    end // initial_model
+
+    //  --------------------------------------------------------------------------------------------------------------
+    //  Definition of instance dependent and bias independent variables
+    //  --------------------------------------------------------------------------------------------------------------
+    `INITIAL_INSTANCE
+    begin : initial_instance
+
+        // Declaration of local variables
+        real Invsa, Invsb, Invsaref, Invsbref, Kstressu0, rhobeta, rhobetaref, Kstressvth0;
+        real temp0, temp00, templ, tempw, Lx, Wx, loop, tmpa, tmpb;
+        real z1, z2, wmin, NF_r;
+
+        // Instance variables
+        NF_i        =  1.0;
+        invNF       =  1.0;
+        LE          =  0.0;
+        WE          =  0.0;
+        L_i         =  L;
+        W_i         =  W;
+        SA_i        =  SA;
+        SB_i        =  SB;
+        SD_i        =  SD;
+        SC_i        =  SC;
+        XGW_i       =  XGW;
+        ABSOURCE_i  =  ABSOURCE;
+        LSSOURCE_i  =  LSSOURCE;
+        LGSOURCE_i  =  LGSOURCE;
+        ABDRAIN_i   =  ABDRAIN;
+        LSDRAIN_i   =  LSDRAIN;
+        LGDRAIN_i   =  LGDRAIN;
+`ifdef __XYCE__
+        `PSP103geoUpdate(AS, AD, PS, PD, NF, AS_i, AD_i, PS_i, PD_i)
+`else
+        AS_i        =  AS;
+        PS_i        =  PS;
+        AD_i        =  AD;
+        PD_i        =  PD;
+`endif
+        JW_i        =  JW;
+
+        // Clipping of the instance parameters
+        if ((SWGEO_i == 1) || (SWGEO_i == 2)) begin
+            NF_i        = `CLIP_LOW(NF, 1);
+            NF_i        =  floor(NF_i + 0.5); // round to nearest integer
+            invNF       =  1.0 / NF_i;
+        end
+        L_i          = `CLIP_LOW(L_i, 1.0e-9);
+        W_i          = `CLIP_LOW(W_i * invNF, 1.0e-9);
+        SCA_i        = `CLIP_LOW(SCA, 0.0);
+        SCB_i        = `CLIP_LOW(SCB, 0.0);
+        SCC_i        = `CLIP_LOW(SCC, 0.0);
+        NGCON_i      =  (NGCON < 1.5) ? 1.0 : 2.0;
+
+`ifdef __XYCE__
+        // Transistor temperature
+        TR_i        = `CLIP_LOW(TR, -273.0);
+        TKR         = `KELVINCONVERSION + TR_i;
+        TKA         =  $temperature + DTA;
+        rTa         =  TKA / TKR;
+        delTa       =  TKA - TKR;
+        phita       =  TKA * `KBOL / `QELE;
+        inv_phita   =  1.0 / phita;
+        `ifdef SelfHeating
+            // do nothing
+        `else // SelfHeating
+            TKD         =  TKA;
+            `TempInitialize
+        `endif // SelfHeating
+
+        // JUNCAP2
+        `include "JUNCAP200_InitModel.include"
+`endif
+
+        // Geometrical device variables
+        // Transistor geometry
+
+        iL           = `LEN / L_i;
+        iW           = `WEN / W_i;
+        delLPS       =  LVARO * (1.0 + LVARL * iL) * (1.0 + LVARW * iW);
+        delWOD       =  WVARO * (1.0 + WVARL * iL) * (1.0 + WVARW * iW);
+        if (SWGEO_i == 2) begin
+            delLPS       =  LVARO * (1.0 + LVARL * iL);
+            delWOD       =  WVARO * (1.0 + WVARW * iW);
+        end
+        LE           = `CLIP_LOW(L_i + delLPS - 2.0 * LAP, 1.0e-9);
+        WE           = `CLIP_LOW(W_i + delWOD - 2.0 * WOT, 1.0e-9);
+        LEcv         = `CLIP_LOW(L_i + delLPS - 2.0 * LAP + DLQ, 1.0e-9);
+        WEcv         = `CLIP_LOW(W_i + delWOD - 2.0 * WOT + DWQ, 1.0e-9);
+        Lcv          = `CLIP_LOW(L_i + delLPS + DLQ, 1.0e-9);
+        Wcv          = `CLIP_LOW(W_i + delWOD + DWQ, 1.0e-9);
+        iLE          = `LEN / LE;
+        iWE          = `WEN / WE;
+
+        // Geometry for multi-finger devices
+        L_f          = `CLIP_LOW(L_i + delLPS, 1.0e-9);
+        L_slif       = `CLIP_LOW(L_f + DLSIL, 1.0e-9);
+        W_f          = `CLIP_LOW(W_i + delWOD, 1.0e-9);
+        XGWE         = `CLIP_LOW(XGW_i - 0.5 * delWOD, 1.0e-9);
+
+        // Local model parameters
+        VFB_p        =  VFB;
+        STVFB_p      =  STVFB;
+        ST2VFB_p     =  ST2VFB;
+        TOX_p        =  TOX;
+        EPSROX_p     =  EPSROX;
+        NEFF_p       =  NEFF;
+        FACNEFFAC_p  =  FACNEFFAC;
+        GFACNUD_p    =  GFACNUD;
+        VSBNUD_p     =  VSBNUD;
+        DVSBNUD_p    =  DVSBNUD;
+        VNSUB_p      =  VNSUB;
+        NSLP_p       =  NSLP;
+        DNSUB_p      =  DNSUB;
+        DPHIB_p      =  DPHIB;
+        DELVTAC_p    =  DELVTAC;
+        NP_p         =  NP;
+        TOXOV_p      =  TOXOV;
+        TOXOVD_p     =  TOXOVD;
+        NOV_p        =  NOV;
+        NOVD_p       =  NOVD;
+        CT_p         =  CT;
+        CTG_p        =  CTG;
+        CTB_p        =  CTB;
+        STCT_p       =  STCT;
+        PSCE_p       =  PSCE;
+        PSCED_p      =  PSCED;
+        PSCEB_p      =  PSCEB;
+        CF_p         =  CF;
+        CFD_p        =  CFD;
+        CFB_p        =  CFB;
+        BETN_p       =  BETN;
+        STBET_p      =  STBET;
+        MUE_p        =  MUE;
+        STMUE_p      =  STMUE;
+        THEMU_p      =  THEMU;
+        STTHEMU_p    =  STTHEMU;
+        CS_p         =  CS;
+        STCS_p       =  STCS;
+        THECS_p      =  THECS;
+        STTHECS_p    =  STTHECS;
+        XCOR_p       =  XCOR;
+        STXCOR_p     =  STXCOR;
+        FETA_p       =  FETA;
+        RS_p         =  RS;
+        STRS_p       =  STRS;
+        RSB_p        =  RSB;
+        RSG_p        =  RSG;
+        THESAT_p     =  THESAT;
+        STTHESAT_p   =  STTHESAT;
+        THESATB_p    =  THESATB;
+        THESATG_p    =  THESATG;
+        AX_p         =  AX;
+        ALP_p        =  ALP;
+        ALP1_p       =  ALP1;
+        ALP2_p       =  ALP2;
+        VP_p         =  VP;
+        A1_p         =  A1;
+        A2_p         =  A2;
+        STA2_p       =  STA2;
+        A3_p         =  A3;
+        A4_p         =  A4;
+        GCO_p        =  GCO;
+        IGINV_p      =  IGINV;
+        IGOV_p       =  IGOV;
+        IGOVD_p      =  IGOVD;
+        STIG_p       =  STIG;
+        GC2_p        =  GC2;
+        GC3_p        =  GC3;
+        CHIB_p       =  CHIB;
+        AGIDL_p      =  AGIDL;
+        AGIDLD_p     =  AGIDLD;
+        BGIDL_p      =  BGIDL;
+        BGIDLD_p     =  BGIDLD;
+        STBGIDL_p    =  STBGIDL;
+        STBGIDLD_p   =  STBGIDLD;
+        CGIDL_p      =  CGIDL;
+        CGIDLD_p     =  CGIDLD;
+        COX_p        =  COX;
+        CGOV_p       =  CGOV;
+        CGOVD_p      =  CGOVD;
+        CGBOV_p      =  CGBOV;
+        CFR_p        =  CFR;
+        CFRD_p       =  CFRD;
+        FNT_p        =  FNT;
+        FNTEXC_p     =  FNTEXC;
+        NFA_p        =  NFA;
+        NFB_p        =  NFB;
+        NFC_p        =  NFC;
+        EF_p         =  EF;
+        VFBEDGE_p    =  VFBEDGE;
+        STVFBEDGE_p  =  STVFBEDGE;
+        DPHIBEDGE_p  =  DPHIBEDGE;
+        NEFFEDGE_p   =  NEFFEDGE;
+        CTEDGE_p     =  CTEDGE;
+        BETNEDGE_p   =  BETNEDGE;
+        STBETEDGE_p  =  STBETEDGE;
+        PSCEEDGE_p   =  PSCEEDGE;
+        PSCEBEDGE_p  =  PSCEBEDGE;
+        PSCEDEDGE_p  =  PSCEDEDGE;
+        CFEDGE_p     =  CFEDGE;
+        CFDEDGE_p    =  CFDEDGE;
+        CFBEDGE_p    =  CFBEDGE;
+        FNTEDGE_p    =  FNTEDGE;
+        NFAEDGE_p    =  NFAEDGE;
+        NFBEDGE_p    =  NFBEDGE;
+        NFCEDGE_p    =  NFCEDGE;
+        EFEDGE_p     =  EFEDGE;
+        RG_p         =  RG;
+        RSE_p        =  RSE;
+        RDE_p        =  RDE;
+        RWELL_p      =  RWELL;
+        RBULK_p      =  RBULK;
+        RJUNS_p      =  RJUNS;
+        RJUND_p      =  RJUND;
+        `ifdef SelfHeating
+            RTH_p        =  RTH;
+            CTH_p        =  CTH;
+            STRTH_p      =  STRTH;
+        `endif // SelfHeating
+        `ifdef NQSmodel
+            MUNQS_p      =  MUNQS;
+        `endif // NQSmodel
+
+        // Geometry scaling with physical scaling rules
+        if (SWGEO_i == 1) begin
+            // Process parameters
+            VFB_p        =  VFBO + VFBL * iLE + VFBW * iWE + VFBLW * iLE * iWE;
+            STVFB_p      =  STVFBO + STVFBL * iLE + STVFBW * iWE + STVFBLW * iLE * iWE;
+            ST2VFB_p     =  ST2VFBO;
+            TOX_p        =  TOXO;
+            EPSROX_p     =  EPSROXO;
+            NSUB0e       =  NSUBO_i * `MAX(( 1.0 + NSUBW * iWE * ln( 1.0 + WE / WSEG_i )), 1.0e-03);
+            NPCKe        =  NPCK_i * `MAX(( 1.0 + NPCKW * iWE * ln( 1.0 + WE / WSEGP_i )), 1.0e-03);
+            LPCKe        =  LPCK_i * `MAX(( 1.0 + LPCKW * iWE * ln( 1.0 + WE / WSEGP_i )), 1.0e-03);
+            if (LE > (2.0 * LPCKe)) begin
+                AA           =  7.5e10;
+                BB           =  sqrt(NSUB0e + 0.5 * NPCKe) - sqrt(NSUB0e);
+                NSUB         =  sqrt(NSUB0e) + AA * ln(1.0 + 2.0 * LPCKe / LE * (exp(BB / AA) - 1.0));
+                NSUB         =  NSUB * NSUB;
+            end else begin
+                if (LE >= LPCKe) begin
+                    NSUB          =  NSUB0e + NPCKe * LPCKe / LE;
+                end else begin // LE < LPCK
+                    NSUB          =  NSUB0e + NPCKe * (2.0 - LE / LPCKe);
+                end
+            end
+            NEFF_p       =  NSUB * (1.0 - FOL1 * iLE - FOL2 * iLE * iLE);
+            FACNEFFAC_p  =  FACNEFFACO + FACNEFFACL * iLE + FACNEFFACW * iWE + FACNEFFACLW * iLE * iWE;
+            GFACNUD_p    =  GFACNUDO + GFACNUDL * pow(iLE, GFACNUDLEXP) + GFACNUDW * iWE + GFACNUDLW * iLE * iWE;
+            VSBNUD_p     =  VSBNUDO;
+            DVSBNUD_p    =  DVSBNUDO;
+            VNSUB_p      =  VNSUBO;
+            NSLP_p       =  NSLPO;
+            DNSUB_p      =  DNSUBO;
+            DPHIB_p      =  DPHIBO + DPHIBL * pow(iLE, DPHIBLEXP) + DPHIBW * iWE + DPHIBLW * iLE * iWE;
+            DELVTAC_p    =  DELVTACO + DELVTACL * pow(iLE, DELVTACLEXP) + DELVTACW * iWE + DELVTACLW * iLE * iWE;
+            NP_p         =  NPO * `MAX(1.0e-6, (1.0 + NPL * iLE));
+            TOXOV_p      =  TOXOVO;
+            TOXOVD_p     =  TOXOVDO;
+            NOV_p        =  NOVO;
+            NOVD_p       =  NOVDO;
+
+            // Interface states parameters
+            CT_p         =  (CTO + CTL * pow(iLE, CTLEXP)) * (1.0 + CTW * iWE) * (1.0 + CTLW * iLE * iWE);
+            CTG_p        =  CTGO;
+            CTB_p        =  CTBO;
+            STCT_p       =  STCTO;
+
+            // DIBL parameters
+            CF_p         =  CFL * pow(iLE, CFLEXP) * (1.0 + CFW * iWE);
+            CFD_p        =  CFDO;
+            CFB_p        =  CFBO;
+
+            // Subthreshold slope parameters of short channel transistor
+            PSCE_p       =  PSCEL * pow(iLE, PSCELEXP) * (1.0 + PSCEW * iWE);
+            PSCED_p      =  PSCEDO;
+            PSCEB_p      =  PSCEBO;
+
+            // Mobility parameters
+            FBET1e       =  FBET1 * (1.0 + FBET1W * iWE);
+            LP1e         =  LP1_i * `MAX(1.0 + LP1W * iWE, 1.0e-03);
+            GPE          =  1.0 + FBET1e * LP1e / LE * (1.0 - exp(-LE / LP1e)) + FBET2 * LP2_i / LE * (1.0 - exp(-LE / LP2_i));
+            GPE          = `MAX(GPE, 1.0e-15);
+            GWE          =  1.0 + BETW1 * iWE + BETW2 * iWE * ln(1.0 + WE / WBET_i);
+            BETN_p       =  UO * WE / (GPE * LE) * GWE;
+            STBET_p      =  STBETO + STBETL * iLE + STBETW * iWE + STBETLW * iLE * iWE;
+            MUE_p        =  MUEO * (1.0 + MUEW * iWE);
+            STMUE_p      =  STMUEO;
+            THEMU_p      =  THEMUO;
+            STTHEMU_p    =  STTHEMUO;
+            CS_p         =  (CSO + CSL * pow(iLE, CSLEXP)) * (1.0 + CSW * iWE) * (1.0 + CSLW * iLE * iWE);
+            STCS_p       =  STCSO;
+            THECS_p      =  THECSO;
+            STTHECS_p    =  STTHECSO;
+            XCOR_p       =  XCORO * (1.0 + XCORL * iLE) * (1.0 + XCORW * iWE) * (1.0 + XCORLW * iLE * iWE);
+            STXCOR_p     =  STXCORO;
+            FETA_p       =  FETAO;
+
+            // Series resistance
+            RS_p         =  RSW1 * iWE * (1.0 + RSW2 * iWE);
+            STRS_p       =  STRSO;
+            RSB_p        =  RSBO;
+            RSG_p        =  RSGO;
+
+            // Velocity saturation
+            THESAT_p     =  (THESATO + THESATL* GWE / GPE * pow(iLE, THESATLEXP)) * (1.0 + THESATW * iWE) * (1.0 + THESATLW * iLE * iWE);
+            STTHESAT_p   =  STTHESATO + STTHESATL * iLE + STTHESATW * iWE + STTHESATLW * iLE * iWE;
+            THESATB_p    =  THESATBO;
+            THESATG_p    =  THESATGO;
+
+            // Saturation voltage
+            AX_p         =  AXO / (1.0 + AXL_i * iLE);
+
+            // Channel length modulation
+            ALP_p        =  ALPL * pow(iLE, ALPLEXP) * (1.0 + ALPW * iWE);
+            tmpx         =  pow(iLE, ALP1LEXP);
+            ALP1_p       =  ALP1L1 * tmpx * (1.0 + ALP1W * iWE) / (1.0 + ALP1L2_i * iLE * tmpx);
+            tmpx         =  pow(iLE, ALP2LEXP);
+            ALP2_p       =  ALP2L1 * tmpx * (1.0 + ALP2W * iWE) / (1.0 + ALP2L2_i * iLE * tmpx);
+            VP_p         =  VPO;
+
+            // Impact ionization
+            A1_p         =  A1O * (1.0 + A1L * iLE) * (1.0 + A1W * iWE);
+            A2_p         =  A2O;
+            STA2_p       =  STA2O;
+            A3_p         =  A3O * (1.0 + A3L * iLE) * (1.0 + A3W * iWE);
+            A4_p         =  A4O * (1.0 + A4L * iLE) * (1.0 + A4W * iWE);
+
+            // Gate current
+            GCO_p        =  GCOO;
+            IGINV_p      =  IGINVLW / (iWE * iLE);
+            IGOV_p       =  IGOVW * LOV_i / (`LEN * iWE);
+            IGOVD_p      =  IGOVDW * LOVD_i / (`LEN * iWE);
+            STIG_p       =  STIGO;
+            GC2_p        =  GC2O;
+            GC3_p        =  GC3O;
+            CHIB_p       =  CHIBO;
+
+            // GIDL
+            AGIDL_p      =  AGIDLW * LOV_i / (`LEN * iWE);
+            AGIDLD_p     =  AGIDLDW * LOVD_i / (`LEN * iWE);
+            BGIDL_p      =  BGIDLO;
+            BGIDLD_p     =  BGIDLDO;
+            STBGIDL_p    =  STBGIDLO;
+            STBGIDLD_p   =  STBGIDLDO;
+            CGIDL_p      =  CGIDLO;
+            CGIDLD_p     =  CGIDLDO;
+
+            // Charge model parameters
+            COX_p        = `EPSO * EPSROXO_i * WEcv * LEcv / TOXO_i;
+            CGOV_p       = `EPSO * EPSROXO_i * WEcv * LOV_i / TOXOVO_i;
+            CGOVD_p      = `EPSO * EPSROXO_i * WEcv * LOVD_i / TOXOVDO_i;
+            CGBOV_p      =  CGBOVL * Lcv / `LEN;
+            CFR_p        =  CFRW * Wcv / `WEN;
+            CFRD_p       =  CFRDW * Wcv / `WEN;
+
+            // Noise model parameters
+            temp0        =  1.0 - 2.0 * LINTNOI * iLE / `LEN;
+            Lnoi         = `MAX(temp0, 1.0e-3);
+            Lred         =  1.0 / pow(Lnoi, ALPNOI);
+            FNT_p        =  FNTO;
+            FNTEXC_p     =  FNTEXCL * BETN_p * BETN_p * iWE * iWE;
+            NFA_p        =  Lred * iWE * iLE * NFALW;
+            NFB_p        =  Lred * iWE * iLE * NFBLW;
+            NFC_p        =  Lred * iWE * iLE * NFCLW;
+            EF_p         =  EFO;
+
+            // Edge transistors: PSP 103.4
+            WE_edge      =  2.0 * WEDGE + WEDGEW * WE;
+            iWE_edge     = `WEN / WE_edge;
+            VFBEDGE_p    =  VFBEDGEO;
+            STVFBEDGE_p  =  STVFBEDGEO + STVFBEDGEL * iLE + STVFBEDGEW * iWE + STVFBEDGELW * iLE * iWE;
+            DPHIBEDGE_p  =  DPHIBEDGEO + DPHIBEDGEL * pow(iLE, DPHIBEDGELEXP) + DPHIBEDGEW * iWE + DPHIBEDGELW * iLE * iWE;
+            NEFFEDGE_p   =  NSUBEDGEO_i * (1.0 + NSUBEDGEL * pow(iLE, NSUBEDGELEXP)) * ( 1.0 + NSUBEDGEW * iWE) * ( 1.0 + NSUBEDGELW * iLE * iWE);
+            CTEDGE_p     =  CTEDGEO + CTEDGEL * pow(iLE, CTEDGELEXP);
+            GPE_edge     =  1.0 + FBETEDGE * LPEDGE_i / LE * (1.0 - exp(-LE / LPEDGE_i));
+            GPE_edge     = `MAX(GPE_edge, 1.0e-15);
+            BETNEDGE_p   =  UO * WE_edge / (GPE_edge * LE) * (1.0 + BETEDGEW * iWE);
+            STBETEDGE_p  =  STBETEDGEO + STBETEDGEL * iLE + STBETEDGEW * iWE + STBETEDGELW * iLE * iWE;
+            PSCEEDGE_p   =  PSCEEDGEL * pow(iLE, PSCEEDGELEXP) * (1.0 + PSCEEDGEW * iWE);
+            PSCEBEDGE_p  =  PSCEBEDGEO;
+            PSCEDEDGE_p  =  PSCEDEDGEO;
+            CFEDGE_p     =  CFEDGEL * pow(iLE, CFEDGELEXP) * (1.0 + CFEDGEW * iWE);
+            CFDEDGE_p    =  CFDEDGEO;
+            CFBEDGE_p    =  CFBEDGEO;
+            FNTEDGE_p    =  FNTEDGEO;
+            NFAEDGE_p    =  iWE_edge * iLE * NFAEDGELW;
+            NFBEDGE_p    =  iWE_edge * iLE * NFBEDGELW;
+            NFCEDGE_p    =  iWE_edge * iLE * NFCEDGELW;
+            EFEDGE_p     =  EFEDGEO;
+        end
+
+        // Well proximity effect parameters
+        KVTHOWE      =  KVTHOWEO + KVTHOWEL * iLE + KVTHOWEW * iWE + KVTHOWELW * iLE * iWE;
+        KUOWE        =  KUOWEO + KUOWEL * iLE + KUOWEW * iWE + KUOWELW * iLE * iWE;
+
+        // Geometry scaling with binning scaling rules
+        if (SWGEO_i == 2) begin
+            `include "PSP103_binning.include"
+        end
+
+        // Parasitic resistance parameters
+        if ((SWGEO_i == 1) || (SWGEO_i == 2)) begin
+            RG_p         =  RSHG_i * (`oneThird * W_f / NGCON_i + XGWE) / (NGCON_i * L_slif) + (RINT_i + RVPOLY_i) / (W_f * L_f) + NF_i * RGO;
+            if (SWJUNASYM == 0) begin
+                RSHD_i       =  RSH_i;
+            end
+            RSE_p        =  NRS * RSH_i;
+            RDE_p        =  NRD * RSHD_i;
+            RWELL_p      =  NF_i * RWELLO;
+            RBULK_p      =  NF_i * RBULKO;
+            RJUNS_p      =  NF_i * RJUNSO;
+            RJUND_p      =  NF_i * RJUNDO;
+
+            // Self heating effect parameters
+            `ifdef SelfHeating
+                deltaRth     =  RTHW2 + WE / `WEN * (1.0 + RTHLW * LE / `LEN);
+                deltaRth     = `MAX(deltaRth, 1.0e-6);
+                RTH_p        =  RTHO + RTHW1 / deltaRth;
+                CTH_p        =  CTHO + CTHW1 * (CTHW2 + WE / `WEN * (1.0 + CTHLW * LE / `LEN));
+                STRTH_p      =  STRTHO;
+            `endif // SelfHeating
+
+            // NQS parameters
+            `ifdef NQSmodel
+                MUNQS_p      =  MUNQSO;
+            `endif // NQSmodel
+
+            // Mechanical stress model
+            tmpa         =  0.0;
+            tmpb         =  0.0;
+            loop         =  0.0;
+            if ((SA_i > 0.0) && (SB_i > 0.0) && ((NF_i == 1.0) || ((NF_i > 1.0) && (SD_i > 0.0)))) begin
+                while (loop < (NF_i - 0.5)) begin
+                    tmpa         =  tmpa + 1.0 / (SA_i + 0.5 * L_i + loop * (SD_i + L_i));
+                    tmpb         =  tmpb + 1.0 / (SB_i + 0.5 * L_i + loop * (SD_i + L_i));
+                    loop         =  loop + 1.0;
+                end
+                Invsa        =  tmpa * invNF;
+                Invsb        =  tmpb * invNF;
+                Invsaref     =  1.0 / (SAREF_i + 0.5 * L_i);
+                Invsbref     =  1.0 / (SBREF_i + 0.5 * L_i);
+                Lx           = `MAX(L_i + delLPS, 1.0e-9);
+                Wx           = `MAX(W_i + delWOD + WLOD, 1.0e-9);
+                templ        =  1.0 / pow(Lx, LLODKUO_i);
+                tempw        =  1.0 / pow(Wx, WLODKUO_i);
+                Kstressu0    =  (1.0 + LKUO * templ + WKUO * tempw + PKUO * templ * tempw) * (1.0 + TKUO * (rTa - 1.0));
+                rhobeta      =  KUO * (Invsa + Invsb) / Kstressu0;
+                rhobetaref   =  KUO * (Invsaref + Invsbref) / Kstressu0;
+                templ        =  1.0 / pow(Lx, LLODVTH_i);
+                tempw        =  1.0 / pow(Wx, WLODVTH_i);
+                Kstressvth0  =  1.0 + LKVTHO * templ + WKVTHO * tempw + PKVTHO * templ * tempw;
+                temp0        =  Invsa + Invsb - Invsaref - Invsbref;
+                //  Parameter adaptations
+                BETN_p       =  BETN_p * (1.0 + rhobeta) / (1.0 + rhobetaref);
+                THESAT_p     =  THESAT_p * (1.0 + rhobeta) * (1.0 + KVSAT_i * rhobetaref) / ((1.0 + rhobetaref) * (1.0  + KVSAT_i * rhobeta));
+                VFB_p        =  VFB_p + KVTHO * temp0 / Kstressvth0;
+                CF_p         =  CF_p + STETAO * temp0 / pow(Kstressvth0, LODETAO_i);
+                BETNEDGE_p   =  BETNEDGE_p * (1.0 + rhobeta) / (1.0 + rhobetaref);
+                VFBEDGE_p    =  VFBEDGE_p + KVTHO * temp0 / Kstressvth0;
+                CFEDGE_p     =  CFEDGE_p + STETAO * temp0 / pow(Kstressvth0, LODETAO_i);
+            end
+
+            // Well proximity effect equations
+            if ((SCA_i > 0.0) || (SCB_i > 0.0) || (SCC_i > 0.0) || (SC_i > 0.0)) begin
+                if ((SCA_i == 0.0) && (SCB_i == 0.0) && (SCC_i == 0.0)) begin
+                    temp0        =  SC_i + W_i;
+                    temp00       =  1.0 / SCREF_i;
+                    SCA_i        =  SCREF_i * SCREF_i / (SC_i * temp0);
+                    SCB_i        =  ((0.1 * SC_i + 0.01 * SCREF_i) * exp(-10.0 * SC_i * temp00) - (0.1 * temp0 + 0.01 * SCREF_i) * exp(-10.0 * temp0 * temp00)) / W_i;
+                    SCC_i        =  ((0.05 * SC_i + 0.0025 * SCREF_i) * exp(-20.0 * SC_i * temp00) - (0.05 * temp0 + 0.0025 * SCREF_i) * exp(-20.0 * temp0 * temp00)) / W_i;
+                end
+                // Parameter adaptations
+                temp0        =  SCA_i + WEB_i * SCB_i + WEC_i * SCC_i;
+                VFB_p        =  VFB_p + KVTHOWE * temp0;
+                BETN_p       =  BETN_p * (1.0 + KUOWE * temp0);
+                VFBEDGE_p    =  VFBEDGE_p + KVTHOWE * temp0;
+                BETNEDGE_p   =  BETNEDGE_p * (1.0 + KUOWE * temp0);
+            end
+        end
+
+        // Internal parameters (including temperature scaling)
+        // Clipping of the local model parameters
+        VFB_i        =  VFB_p;
+        STVFB_i      =  STVFB_p;
+        ST2VFB_i     =  ST2VFB_p;
+        TOX_i        = `CLIP_LOW(TOX_p, 1.0e-10);
+        EPSROX_i     = `CLIP_LOW(EPSROX_p, 1.0);
+        NEFF_i       = `CLIP_BOTH(NEFF_p, 1.0e20, 1.0e26);
+        FACNEFFAC_i  = `CLIP_LOW(FACNEFFAC_p, 0.0);
+        GFACNUD_i    = `CLIP_LOW(GFACNUD_p, 0.01);
+        VSBNUD_i     = `CLIP_LOW(VSBNUD_p, 0.0);
+        DVSBNUD_i    = `CLIP_LOW(DVSBNUD_p, 0.1);
+        VNSUB_i      =  VNSUB_p;
+        NSLP_i       = `CLIP_LOW(NSLP_p, 1.0e-3);
+        DNSUB_i      = `CLIP_BOTH(DNSUB_p, 0.0, 1.0);
+        DPHIB_i      =  DPHIB_p;
+        DELVTAC_i    =  DELVTAC_p;
+        NP_i         = `CLIP_LOW(NP_p, 0.0);
+        TOXOV_i      = `CLIP_LOW(TOXOV_p, 1.0e-10);
+        TOXOVD_i     = `CLIP_LOW(TOXOVD_p, 1.0e-10);
+        NOV_i        = `CLIP_BOTH(NOV_p, 1.0e23, 1.0e27);
+        NOVD_i       = `CLIP_BOTH(NOVD_p, 1.0e23, 1.0e27);
+        CT_i         = `CLIP_LOW(CT_p, 0.0);
+        CTG_i        = `CLIP_LOW(CTG_p, 0.0);
+        CTB_i        =  CTB_p;
+        STCT_i       =  STCT_p;
+        CF_i         = `CLIP_LOW(CF_p, 0.0);
+        CFD_i        = `CLIP_LOW(CFD_p, 0.0);
+        CFB_i        = `CLIP_BOTH(CFB_p, 0.0, 1.0);
+        PSCE_i       = `CLIP_LOW(PSCE_p, 0.0);
+        PSCEB_i      = `CLIP_BOTH(PSCEB_p, 0.0, 1.0);
+        PSCED_i      = `CLIP_LOW(PSCED_p, 0.0);
+        BETN_i       = `CLIP_LOW(BETN_p, 0.0);
+        STBET_i      =  STBET_p;
+        MUE_i        = `CLIP_LOW(MUE_p, 0.0);
+        STMUE_i      =  STMUE_p;
+        THEMU_i      = `CLIP_LOW(THEMU_p, 0.0);
+        STTHEMU_i    =  STTHEMU_p;
+        CS_i         = `CLIP_LOW(CS_p,  0.0);
+        STCS_i       =  STCS_p;
+        THECS_i      = `CLIP_LOW(THECS_p, 0.0);
+        STTHECS_i    =  STTHECS_p;
+        XCOR_i       = `CLIP_LOW(XCOR_p, 0.0);
+        STXCOR_i     =  STXCOR_p;
+        FETA_i       = `CLIP_LOW(FETA_p, 0.0);
+        RS_i         = `CLIP_LOW(RS_p, 0.0);
+        STRS_i       =  STRS_p;
+        RSB_i        = `CLIP_BOTH(RSB_p, -0.5, 1.0);
+        RSG_i        = `CLIP_LOW(RSG_p, -0.5);
+        THESAT_i     = `CLIP_LOW(THESAT_p, 0.0);
+        STTHESAT_i   =  STTHESAT_p;
+        THESATB_i    = `CLIP_BOTH(THESATB_p, -0.5, 1.0);
+        THESATG_i    = `CLIP_LOW(THESATG_p, -0.5);
+        AX_i         = `CLIP_LOW(AX_p, 2.0);
+        ALP_i        = `CLIP_LOW(ALP_p, 0.0);
+        ALP1_i       = `CLIP_LOW(ALP1_p, 0.0);
+        ALP2_i       = `CLIP_LOW(ALP2_p, 0.0);
+        VP_i         = `CLIP_LOW(VP_p, 1.0e-10);
+        A1_i         = `CLIP_LOW(A1_p, 0.0);
+        A2_i         = `CLIP_LOW(A2_p, 0.0);
+        STA2_i       =  STA2_p;
+        A3_i         = `CLIP_LOW(A3_p, 0.0);
+        A4_i         = `CLIP_LOW(A4_p, 0.0);
+        GCO_i        = `CLIP_BOTH(GCO_p, -10.0, 10.0);
+        IGINV_i      = `CLIP_LOW(IGINV_p, 0.0);
+        IGOV_i       = `CLIP_LOW(IGOV_p, 0.0);
+        IGOVD_i      = `CLIP_LOW(IGOVD_p, 0.0);
+        STIG_i       =  STIG_p;
+        GC2_i        = `CLIP_BOTH(GC2_p, 0.0, 10.0);
+        GC3_i        = `CLIP_BOTH(GC3_p, -10.0, 10.0);
+        CHIB_i       = `CLIP_LOW(CHIB_p, 1.0);
+        AGIDL_i      = `CLIP_LOW(AGIDL_p, 0.0);
+        AGIDLD_i     = `CLIP_LOW(AGIDLD_p, 0.0);
+        BGIDL_i      = `CLIP_LOW(BGIDL_p, 0.0);
+        BGIDLD_i     = `CLIP_LOW(BGIDLD_p, 0.0);
+        STBGIDL_i    =  STBGIDL_p;
+        STBGIDLD_i   =  STBGIDLD_p;
+        CGIDL_i      =  CGIDL_p;
+        CGIDLD_i     =  CGIDLD_p;
+        COX_i        = `CLIP_LOW(COX_p, 0.0);
+        CGOV_i       = `CLIP_LOW(CGOV_p, 0.0);
+        CGOVD_i      = `CLIP_LOW(CGOVD_p, 0.0);
+        CGBOV_i      = `CLIP_LOW(CGBOV_p, 0.0);
+        CFR_i        = `CLIP_LOW(CFR_p, 0.0);
+        CFRD_i       = `CLIP_LOW(CFRD_p, 0.0);
+        FNT_i        = `CLIP_LOW(FNT_p, 0.0);
+        FNTEXC_i     = `CLIP_LOW(FNTEXC_p, 0.0);
+        NFA_i        = `CLIP_LOW(NFA_p, 0.0);
+        NFB_i        = `CLIP_LOW(NFB_p, 0.0);
+        NFC_i        = `CLIP_LOW(NFC_p, 0.0);
+        EF_i         = `CLIP_LOW(EF_p,  0.0);
+        VFBEDGE_i    =  VFBEDGE_p;
+        STVFBEDGE_i  =  STVFBEDGE_p;
+        DPHIBEDGE_i  =  DPHIBEDGE_p;
+        NEFFEDGE_i   = `CLIP_BOTH(NEFFEDGE_p, 1.0e20, 1.0e26);
+        CTEDGE_i     = `CLIP_LOW(CTEDGE_p, 0.0);
+        BETNEDGE_i   = `CLIP_LOW(BETNEDGE_p, 0.0);
+        STBETEDGE_i  =  STBETEDGE_p;
+        PSCEEDGE_i   = `CLIP_LOW(PSCEEDGE_p, 0.0);
+        PSCEBEDGE_i  = `CLIP_BOTH(PSCEBEDGE_p, 0.0, 1.0);
+        PSCEDEDGE_i  = `CLIP_LOW(PSCEDEDGE_p, 0.0);
+        CFEDGE_i     = `CLIP_LOW(CFEDGE_p, 0.0);
+        CFDEDGE_i    = `CLIP_LOW(CFDEDGE_p, 0.0);
+        CFBEDGE_i    = `CLIP_BOTH(CFBEDGE_p, 0.0, 1.0);
+        FNTEDGE_i    = `CLIP_LOW(FNTEDGE_p, 0.0);
+        NFAEDGE_i    = `CLIP_LOW(NFAEDGE_p, 0.0);
+        NFBEDGE_i    = `CLIP_LOW(NFBEDGE_p, 0.0);
+        NFCEDGE_i    = `CLIP_LOW(NFCEDGE_p, 0.0);
+        EFEDGE_i     = `CLIP_LOW(EFEDGE_p,  0.0);
+        RG_i         = `CLIP_LOW(RG_p, 0.0);
+        RSE_i        = `CLIP_LOW(RSE_p, 0.0);
+        RDE_i        = `CLIP_LOW(RDE_p, 0.0);
+        RBULK_i      = `CLIP_LOW(RBULK_p, 0.0);
+        RJUNS_i      = `CLIP_LOW(RJUNS_p, 0.0);
+        RJUND_i      = `CLIP_LOW(RJUND_p, 0.0);
+        RWELL_i      = `CLIP_LOW(RWELL_p, 0.0);
+        `ifdef SelfHeating
+            RTH_i        = `CLIP_LOW(RTH_p, 1.0e-4);
+            CTH_i        = `CLIP_LOW(CTH_p, 0.0);
+            STRTH_i      =  STRTH_p;
+        `endif // SelfHeating
+        MULT_i       = `CLIP_LOW(MULT * NF_i, 0.0); // Note: NF_i is set to 1 for local model
+        FACTUO_i     = `CLIP_LOW(FACTUO, 0.0);
+        DELVTO_i     =  DELVTO;
+        FACTUOEDGE_i = `CLIP_LOW(FACTUOEDGE, 0.0);
+        DELVTOEDGE_i =  DELVTOEDGE;
+        `ifdef NQSmodel
+            MUNQS_i      = `CLIP_LOW(MUNQS_p, 0.0);
+        `endif // NQSmodel
+
+        // Ignore drain-side values in case of symmetric junctions
+        if (SWJUNASYM_i == 0) begin
+            TOXOVD_i      =  TOXOV_i;
+            NOVD_i        =  NOV_i;
+            AGIDLD_i      =  AGIDL_i;
+            BGIDLD_i      =  BGIDL_i;
+            STBGIDLD_i    =  STBGIDL_i;
+            CGIDLD_i      =  CGIDL_i;
+            IGOVD_i       =  IGOV_i;
+            CGOVD_i       =  CGOV_i;
+            CFRD_i        =  CFR_i;
+        end
+
+        // Local process parameters
+        EPSOX        = `EPSO * EPSROX_i;
+        CoxPrime     =  EPSOX / TOX_i;
+        tox_sq       =  TOX_i * TOX_i;
+        Cox_over_q   =  CoxPrime / `QELE;
+        NEFFAC_i     =  FACNEFFAC_i * NEFF_i;
+        NEFFAC_i     = `CLIP_BOTH(NEFFAC_i, 1.0e20, 1.0e26);
+
+        // QM corrections: initially calculated in PSP103_macrodefs.include (PSP103.3)
+        qq           =  0.0;
+        if (QMC_i > 0.0) begin
+            qq           =  0.4 * `QMN * QMC_i * pow(CoxPrime, `twoThirds);
+            if (CHNL_TYPE==`PMOS) begin
+                qq           = `QMP / `QMN * qq;
+            end
+        end
+
+        // Electrical field parameters
+        E_eff0       =  1.0e-8 * CoxPrime / EPSSI;
+        eta_mu       =  0.5 * FETA_i;
+        eta_mu1      =  0.5;
+        if (CHNL_TYPE == `PMOS) begin
+            eta_mu       =  `oneThird * FETA_i;
+            eta_mu1      =  `oneThird;
+        end
+
+        // Linear-saturation transition parameter
+        inv_AX       =  1.0 / AX_i;
+
+        // CLM parameter
+        inv_VP       =  1.0 / VP_i;
+
+        // Gate overlap
+        CoxovPrime   =  EPSOX / TOXOV_i;
+        CoxovPrime_d =  EPSOX / TOXOVD_i;
+        GOV_s        =  sqrt(2.0 * `QELE * NOV_i * EPSSI * inv_phita) / CoxovPrime;
+        GOV_d        =  sqrt(2.0 * `QELE * NOVD_i * EPSSI * inv_phita) / CoxovPrime_d;
+        GOV2_s       =  GOV_s * GOV_s;
+        GOV2_d       =  GOV_d * GOV_d;
+        `sp_ovInit(GOV_s, GOV2_s, SP_OV_eps2_s, SP_OV_a_s, SP_OV_delta1_s)
+        `sp_ovInit(GOV_d, GOV2_d, SP_OV_eps2_d, SP_OV_a_d, SP_OV_delta1_d)
+
+        // Temperature scaling variables
+        `ifdef SelfHeating
+            // do nothing
+        `else // SelfHeating
+            // Initialize variables of edge transistor
+            `TempScaling
+        `endif // SelfHeating
+
+        // Gate to channel leakage parameters
+        inv_CHIB     =  1.0 / CHIB_i;
+        B_fact       =  4.0 * `oneThird * sqrt(2.0 * `QELE * `MELE * CHIB_i) / `HBAR;
+        BCH          =  B_fact * TOX_i;
+        BOV          =  B_fact * TOXOV_i;
+        BOV_d        =  B_fact * TOXOVD_i;
+        GCQ          =  0.0;
+        if (GC3_i < 0) begin
+            GCQ          =  -0.495 * GC2_i / GC3_i;
+        end
+        tf_ig        =  pow(rTa, STIG_i);
+        IGINV_i      =  IGINV_i * tf_ig;
+        IGOV_i       =  IGOV_i * tf_ig;
+        IGOVD_i      =  IGOVD_i * tf_ig;
+
+        // GIDL parameters
+        AGIDLs       =  AGIDL_i * 4.0e-18 / (TOXOV_i * TOXOV_i);
+        AGIDLDs      =  AGIDLD_i * 4.0e-18 / (TOXOVD_i * TOXOVD_i);
+        B_fact       = `MAX(1.0 + STBGIDL_i * delTa, 0.0);
+        BGIDL_T      =  BGIDL_i * B_fact;
+        BGIDLs       =  BGIDL_T * TOXOV_i * 5.0e8;
+        B_fact       = `MAX(1.0 + STBGIDLD_i * delTa, 0.0);
+        BGIDLD_T     =  BGIDLD_i * B_fact;
+        BGIDLDs      =  BGIDLD_T * TOXOVD_i * 5.0e8;
+
+        // Self Heating parameters
+        `ifdef SelfHeating
+            RTH_T        =  RTH_i * pow(rTa, STRTH_i);
+        `endif // SelfHeating
+
+        // Noise model parameters
+        fac_exc      = `MELE * 1.0e9 * FNTEXC_i;
+
+        // Conductance of parasitic resistance
+        if (RG_i > 0.0) begin
+            ggate        =  1.0 / RG_i;
+        end else begin
+            ggate        =  0.0;
+        end
+        if (RSE_i > 0.0) begin
+            gsource      =  1.0 / RSE_i;
+        end else begin
+            gsource      =  0.0;
+        end
+        if (RDE_i > 0.0) begin
+            gdrain       =  1.0 / RDE_i;
+        end else begin
+            gdrain       =  0.0;
+        end
+        if (RBULK_i > 0.0) begin
+            gbulk        =  1.0 / RBULK_i;
+        end else begin
+            gbulk        =  0.0;
+        end
+        if (RJUNS_i > 0.0) begin
+            gjuns        =  1.0 / RJUNS_i;
+        end else begin
+            gjuns        =  0.0;
+        end
+        if (RJUND_i > 0.0) begin
+            gjund        =  1.0 / RJUND_i;
+        end else begin
+            gjund        =  0.0;
+        end
+        if (RWELL_i > 0.0) begin
+            gwell        =  1.0 / RWELL_i;
+        end else begin
+            gwell        =  0.0;
+        end
+
+        // JUNCAP instance parameters
+        ABS_i        =  0.0;
+        LSS_i        =  0.0;
+        LGS_i        =  0.0;
+        ABD_i        =  0.0;
+        LSD_i        =  0.0;
+        LGD_i        =  0.0;
+        jwcorr       =  0.0;
+        jww          =  WE;
+        if (SWGEO_i == 0) begin
+            jww          = `CLIP_LOW(JW_i, `LG_cliplow);
+        end
+        if (SWJUNCAP_i == 3) begin
+            jwcorr       =  1.0;
+        end
+        ABS_i        =  ABSOURCE_i * invNF;
+        LSS_i        =  LSSOURCE_i * invNF;
+        LGS_i        =  LGSOURCE_i * invNF;
+        ABD_i        =  ABDRAIN_i * invNF;
+        LSD_i        =  LSDRAIN_i * invNF;
+        LGD_i        =  LGDRAIN_i * invNF;
+        if ((SWJUNCAP_i == 2) || (SWJUNCAP_i == 3)) begin
+            ABS_i        =  AS_i * invNF;
+            LSS_i        =  PS_i * invNF - jwcorr * jww;
+            LGS_i        =  jww;
+            ABD_i        =  AD_i * invNF;
+            LSD_i        =  PD_i * invNF - jwcorr * jww;
+            LGD_i        =  jww;
+        end
+        if ((SWJUNCAP_i == 1) || (SWJUNCAP_i == 2) || (SWJUNCAP_i == 3)) begin
+            ABSOURCE_i   = `CLIP_LOW(ABS_i, `AB_cliplow);
+            LSSOURCE_i   = `CLIP_LOW(LSS_i, `LS_cliplow);
+            LGSOURCE_i   = `CLIP_LOW(LGS_i, `LG_cliplow);
+            ABDRAIN_i    = `CLIP_LOW(ABD_i, `AB_cliplow);
+            LSDRAIN_i    = `CLIP_LOW(LSD_i, `LS_cliplow);
+            LGDRAIN_i    = `CLIP_LOW(LGD_i, `LG_cliplow);
+        end else begin
+            ABSOURCE_i   =  0.0;
+            LSSOURCE_i   =  0.0;
+            LGSOURCE_i   =  0.0;
+            ABDRAIN_i    =  0.0;
+            LSDRAIN_i    =  0.0;
+            LGDRAIN_i    =  0.0;
+        end
+
+        // Initialization of JUNCAP (global) variables; required for some verilog-A compilers
+        vbimin_s     =  0.0;
+        vbimin_d     =  0.0;
+        vfmin_s      =  0.0;
+        vfmin_d      =  0.0;
+        vch_s        =  0.0;
+        vch_d        =  0.0;
+        vbbtlim_s    =  0.0;
+        vbbtlim_d    =  0.0;
+        VMAX_s       =  0.0;
+        VMAX_d       =  0.0;
+        exp_VMAX_over_phitd_s =  0.0;
+        exp_VMAX_over_phitd_d =  0.0;
+        ISATFOR1_s   =  0.0;
+        ISATFOR1_d   =  0.0;
+        MFOR1_s      =  1.0;
+        MFOR1_d      =  1.0;
+        ISATFOR2_s   =  0.0;
+        ISATFOR2_d   =  0.0;
+        MFOR2_s      =  1.0;
+        MFOR2_d      =  1.0;
+        ISATREV_s    =  0.0;
+        ISATREV_d    =  0.0;
+        MREV_s       =  1.0;
+        MREV_d       =  1.0;
+        m0flag_s     =  0.0;
+        m0flag_d     =  0.0;
+        xhighf1_s    =  0.0;
+        xhighf1_d    =  0.0;
+        expxhf1_s    =  0.0;
+        expxhf1_d    =  0.0;
+        xhighf2_s    =  0.0;
+        xhighf2_d    =  0.0;
+        expxhf2_s    =  0.0;
+        expxhf2_d    =  0.0;
+        xhighr_s     =  0.0;
+        xhighr_d     =  0.0;
+        expxhr_s     =  0.0;
+        expxhr_d     =  0.0;
+        zflagbot_s   =  1.0;
+        zflagbot_d   =  1.0;
+        zflagsti_s   =  1.0;
+        zflagsti_d   =  1.0;
+        zflaggat_s   =  1.0;
+        zflaggat_d   =  1.0;
+        m0_rev       =  0.0;
+        mcor_rev     =  0.0;
+        I1_cor       =  0.0;
+        I2_cor       =  0.0;
+        I3_cor       =  0.0;
+        I4_cor       =  0.0;
+        I5_cor       =  0.0;
+        tt0          =  0.0;
+        tt1          =  0.0;
+        tt2          =  0.0;
+        zfrac        =  0.0;
+        alphaje      =  0.0;
+
+        if (SWJUNCAP_i > 0) begin
+            `JuncapInitInstance(ABSOURCE_i, LSSOURCE_i, LGSOURCE_i, idsatbot,   idsatsti,   idsatgat,   vbibot,   vbisti,   vbigat,   PBOT_i,  PSTI_i,  PGAT_i,  VBIRBOT_i,  VBIRSTI_i,  VBIRGAT_i,  VMAX_s, exp_VMAX_over_phitd_s, vbimin_s, vch_s, vfmin_s, vbbtlim_s)
+            `JuncapInitInstance(ABDRAIN_i,  LSDRAIN_i,  LGDRAIN_i,  idsatbot_d, idsatsti_d, idsatgat_d, vbibot_d, vbisti_d, vbigat_d, PBOTD_i, PSTID_i, PGATD_i, VBIRBOTD_i, VBIRSTID_i, VBIRGATD_i, VMAX_d, exp_VMAX_over_phitd_d, vbimin_d, vch_d, vfmin_d, vbbtlim_d)
+
+            if (SWJUNEXP_i == 1) begin : JUNCAPexpressInit
+                // Local variable declaration
+                `LocalGlobalVars
+
+                // results computed here are not used elsewhere
+                real ijunbot, ijunsti, ijungat, qjunbot, qjunsti, qjungat;
+
+                // Initialization of (local) variables; required for some verilog-A compilers
+                ysq          =  0.0;
+                terfc        =  0.0;
+                erfcpos      =  0.0;
+                h1           =  0.0;
+                h2           =  0.0;
+                h2d          =  0.0;
+                h3           =  0.0;
+                h4           =  0.0;
+                h5           =  0.0;
+                idmult       =  0.0;
+                vj           =  0.0;
+                z            =  0.0;
+                zinv         =  0.0;
+                two_psistar  =  0.0;
+                vjlim        =  0.0;
+                vjsrh        =  0.0;
+                vbbt         =  0.0;
+                vav          =  0.0;
+                tmp          =  0.0;
+                id           =  0.0;
+                isrh         =  0.0;
+                vbi_minus_vjsrh =  0.0;
+                wsrhstep     =  0.0;
+                dwsrh        =  0.0;
+                wsrh         =  0.0;
+                wdep         =  0.0;
+                asrh         =  0.0;
+                itat         =  0.0;
+                btat         =  0.0;
+                twoatatoverthreebtat =  0.0;
+                umaxbeforelimiting =  0.0;
+                umax         =  0.0;
+                sqrtumax     =  0.0;
+                umaxpoweronepointfive = 0.0;
+                wgamma       =  0.0;
+                wtat         =  0.0;
+                ktat         =  0.0;
+                ltat         =  0.0;
+                mtat         =  0.0;
+                xerfc        =  0.0;
+                erfctimesexpmtat =  0.0;
+                gammamax     =  0.0;
+                ibbt         =  0.0;
+                Fmaxr        =  0.0;
+                fbreakdown   =  0.0;
+                qjunbot      =  0.0;
+                qjunsti      =  0.0;
+                qjungat      =  0.0;
+
+                // Computation of JUNCAP-express internal parameters
+                `JuncapExpressInit1(ABSOURCE_i, LSSOURCE_i, LGSOURCE_i, VJUNREF_i, qprefbot, qpref2bot, vbiinvbot, one_minus_PBOT, idsatbot, CSRHBOT_i, CTATBOT_i, vbibot, wdepnulrbot, VBIRBOTinv, PBOT_i, ftdbot, btatpartbot, atatbot, one_over_one_minus_PBOT, CBBTBOT_i, VBIRBOT_i, wdepnulrinvbot, fbbtbot, VBRBOT_i, VBRinvbot, PBRBOT_i, fstopbot, slopebot, qprefsti, qpref2sti, vbiinvsti, one_minus_PSTI, idsatsti, CSRHSTI_i, CTATSTI_i, vbisti, wdepnulrsti, VBIRSTIinv, PSTI_i, ftdsti, btatpartsti, atatsti, one_over_one_minus_PSTI, CBBTSTI_i, VBIRSTI_i, wdepnulrinvsti, fbbtsti, VBRSTI_i, VBRinvsti, PBRSTI_i, fstopsti, slopesti, qprefgat, qpref2gat, vbiinvgat, one_minus_PGAT, idsatgat, CSRHGAT_i, CTATGAT_i, vbigat, wdepnulrgat, VBIRGATinv, PGAT_i, ftdgat, btatpartgat, atatgat, one_over_one_minus_PGAT, CBBTGAT_i, VBIRGAT_i, wdepnulrinvgat, fbbtgat, VBRGAT_i, VBRinvgat, PBRGAT_i, fstopgat, slopegat, VMAX_s, exp_VMAX_over_phitd_s, vbimin_s, vch_s, vfmin_s, vbbtlim_s)
+                `JuncapExpressInit2(ABSOURCE_i, LSSOURCE_i, LGSOURCE_i, qprefbot, qpref2bot, vbiinvbot, one_minus_PBOT, idsatbot, CSRHBOT_i, CTATBOT_i, vbibot, wdepnulrbot, VBIRBOTinv, PBOT_i, ftdbot, btatpartbot, atatbot, one_over_one_minus_PBOT, CBBTBOT_i, VBIRBOT_i, wdepnulrinvbot, fbbtbot, VBRBOT_i, VBRinvbot, PBRBOT_i, fstopbot, slopebot, qprefsti, qpref2sti, vbiinvsti, one_minus_PSTI, idsatsti, CSRHSTI_i, CTATSTI_i, vbisti, wdepnulrsti, VBIRSTIinv, PSTI_i, ftdsti, btatpartsti, atatsti, one_over_one_minus_PSTI, CBBTSTI_i, VBIRSTI_i, wdepnulrinvsti, fbbtsti, VBRSTI_i, VBRinvsti, PBRSTI_i, fstopsti, slopesti, qprefgat, qpref2gat, vbiinvgat, one_minus_PGAT, idsatgat, CSRHGAT_i, CTATGAT_i, vbigat, wdepnulrgat, VBIRGATinv, PGAT_i, ftdgat, btatpartgat, atatgat, one_over_one_minus_PGAT, CBBTGAT_i, VBIRGAT_i, wdepnulrinvgat, fbbtgat, VBRGAT_i, VBRinvgat, PBRGAT_i, fstopgat, slopegat, VMAX_s, exp_VMAX_over_phitd_s, vbimin_s, vch_s, vfmin_s, vbbtlim_s)
+                `JuncapExpressInit3(ABSOURCE_i, LSSOURCE_i, LGSOURCE_i, idsatbot, idsatsti, idsatgat, ISATFOR1_s, MFOR1_s, ISATFOR2_s, MFOR2_s, ISATREV_s, MREV_s, m0flag_s)
+                `JuncapExpressInit4(ABSOURCE_i, LSSOURCE_i, LGSOURCE_i, FJUNQ_i, cjobot, cjosti, cjogat, zflagbot_s, zflagsti_s, zflaggat_s)
+                `JuncapExpressInit5(ABSOURCE_i, LSSOURCE_i, LGSOURCE_i, ISATFOR1_s, ISATFOR2_s, ISATREV_s, xhighf1_s, expxhf1_s, xhighf2_s, expxhf2_s, xhighr_s, expxhr_s)
+
+                `JuncapExpressInit1(ABDRAIN_i, LSDRAIN_i, LGDRAIN_i, VJUNREFD_i, qprefbot_d, qpref2bot_d, vbiinvbot_d, one_minus_PBOT_d, idsatbot_d, CSRHBOTD_i, CTATBOTD_i, vbibot_d, wdepnulrbot_d, VBIRBOTinv_d, PBOTD_i, ftdbot_d, btatpartbot_d, atatbot_d, one_over_one_minus_PBOT_d, CBBTBOTD_i, VBIRBOTD_i, wdepnulrinvbot_d, fbbtbot_d, VBRBOTD_i, VBRinvbot_d, PBRBOTD_i, fstopbot_d, slopebot_d, qprefsti_d, qpref2sti_d, vbiinvsti_d, one_minus_PSTI_d, idsatsti_d, CSRHSTID_i, CTATSTID_i, vbisti_d, wdepnulrsti_d, VBIRSTIinv_d, PSTID_i, ftdsti_d, btatpartsti_d, atatsti_d, one_over_one_minus_PSTI_d, CBBTSTID_i, VBIRSTID_i, wdepnulrinvsti_d, fbbtsti_d, VBRSTID_i, VBRinvsti_d, PBRSTID_i, fstopsti_d, slopesti_d, qprefgat_d, qpref2gat_d, vbiinvgat_d, one_minus_PGAT_d, idsatgat_d, CSRHGATD_i, CTATGATD_i, vbigat_d, wdepnulrgat_d, VBIRGATinv_d, PGATD_i, ftdgat_d, btatpartgat_d, atatgat_d, one_over_one_minus_PGAT_d, CBBTGATD_i, VBIRGATD_i, wdepnulrinvgat_d, fbbtgat_d, VBRGATD_i, VBRinvgat_d, PBRGATD_i, fstopgat_d, slopegat_d, VMAX_d, exp_VMAX_over_phitd_d, vbimin_d, vch_d, vfmin_d, vbbtlim_d)
+                `JuncapExpressInit2(ABDRAIN_i, LSDRAIN_i, LGDRAIN_i, qprefbot_d, qpref2bot_d, vbiinvbot_d, one_minus_PBOT_d, idsatbot_d, CSRHBOTD_i, CTATBOTD_i, vbibot_d, wdepnulrbot_d, VBIRBOTinv_d, PBOTD_i, ftdbot_d, btatpartbot_d, atatbot_d, one_over_one_minus_PBOT_d, CBBTBOTD_i, VBIRBOTD_i, wdepnulrinvbot_d, fbbtbot_d, VBRBOTD_i, VBRinvbot_d, PBRBOTD_i, fstopbot_d, slopebot_d, qprefsti_d, qpref2sti_d, vbiinvsti_d, one_minus_PSTI_d, idsatsti_d, CSRHSTID_i, CTATSTID_i, vbisti_d, wdepnulrsti_d, VBIRSTIinv_d, PSTID_i, ftdsti_d, btatpartsti_d, atatsti_d, one_over_one_minus_PSTI_d, CBBTSTID_i, VBIRSTID_i, wdepnulrinvsti_d, fbbtsti_d, VBRSTID_i, VBRinvsti_d, PBRSTID_i, fstopsti_d, slopesti_d, qprefgat_d, qpref2gat_d, vbiinvgat_d, one_minus_PGAT_d, idsatgat_d, CSRHGATD_i, CTATGATD_i, vbigat_d, wdepnulrgat_d, VBIRGATinv_d, PGATD_i, ftdgat_d, btatpartgat_d, atatgat_d, one_over_one_minus_PGAT_d, CBBTGATD_i, VBIRGATD_i, wdepnulrinvgat_d, fbbtgat_d, VBRGATD_i, VBRinvgat_d, PBRGATD_i, fstopgat_d, slopegat_d, VMAX_d, exp_VMAX_over_phitd_d, vbimin_d, vch_d, vfmin_d, vbbtlim_d)
+                `JuncapExpressInit3(ABDRAIN_i, LSDRAIN_i, LGDRAIN_i, idsatbot_d, idsatsti_d, idsatgat_d, ISATFOR1_d, MFOR1_d, ISATFOR2_d, MFOR2_d, ISATREV_d, MREV_d, m0flag_d)
+                `JuncapExpressInit4(ABDRAIN_i, LSDRAIN_i, LGDRAIN_i, FJUNQD_i, cjobot_d, cjosti_d, cjogat_d, zflagbot_d, zflagsti_d, zflaggat_d)
+                `JuncapExpressInit5(ABDRAIN_i, LSDRAIN_i, LGDRAIN_i, ISATFOR1_d, ISATFOR2_d, ISATREV_d, xhighf1_d, expxhf1_d, xhighf2_d, expxhf2_d, xhighr_d, expxhr_d)
+            end // JUNCAPexpressInit
+
+        end
+
+    end // initial_instance
+
+    begin : evaluateblock
+
+        real sigVds, dphit1, xgct, xsct0, xbct, xsbstar, xsct, dCTG, ct_fact, phit1, inv_phit1, xg_dc, alpha_dc, dps_dc, qim_dc;
+        real qim1_dc, H_dc, FdL_dc, Gvsatinv_dc, Ids, Iimpact, mavl, Igdov, Igsov, Igcd, Igcs, eta_p_ac, Gvsat_ac, Gmob_dL_ac, H0;
+        real COX_qm, ijun_s, ijunbot_s, ijunsti_s, ijungat_s, ijun_d, ijunbot_d, ijunsti_d, ijungat_d, qjun_s, qjunbot_s, qjunsti_s;
+        real qjungat_s, qjun_d, qjunbot_d, qjunsti_d, qjungat_d, jnoise_s, jnoise_d, Gmob_dc, xitsb_dc, Vdse_dc, Vsbstaredge, Vsbxedge;
+        real dphit1edge, phit1edge, inv_phit1edge, Vdspedge, delVgedge, xgedge, xbedge, dxthedge, xnedge_s, qseffedge, xnedge_d;
+        real qdseffedge, qdeffedge, qmeffedge, dsqredge, alphabmedge, Idsedge, Sfledge, midedge, sqidedge;
+        `ifdef SelfHeating
+            real Pdiss, phit, BET_i, BETEDGE_i, nt0, nt, THESAT_T, Sfl_prefac, phit0edge, Gfedge2, lnGfedge2, Sfl_prefac_edge;
+            real ntedge;
+        `endif // SelfHeating
+        real temp, temp1, temp2;
+
+        //  --------------------------------------------------------------------------------------------------------------
+        //  DC bias dependent quantities (calculations for current contribs)
+        //  --------------------------------------------------------------------------------------------------------------
+        begin : evaluateStatic
+
+            // Initialize temporary variables
+            temp        =  0.0;
+            temp1       =  0.0;
+            temp2       =  0.0;
+
+            // Initialization of variables for SHE effect
+            `ifdef SelfHeating
+                TKD          =  TKA + Temp(br_rth);
+                `TempInitialize
+                `TempScaling
+            `endif // SelfHeating
+            QCLM         =  0.0;
+            xs_ov        =  0.0;
+            xd_ov        =  0.0;
+            Vovs         =  0.0;
+            Vovd         =  0.0;
+            Iimpact      =  0.0;
+            mavl         =  0.0;
+
+            // Initialization of variables for NQS model
+            `ifdef NQSmodel
+                pd           =  1.0;
+                ym           =  0.0;
+            `endif // NQSmodel
+
+            // Voltage affectations
+            if (CHNL_TYPE == `NMOS) begin
+                Vgs          =  V(GP, SI);
+                Vds          =  V(DI, SI);
+                Vsb          =  V(SI, BP);
+                Vjun_s       = -V(SI, BS);
+                Vjun_d       = -V(DI, BD);
+            end else begin
+                Vgs          = -V(GP, SI);
+                Vds          = -V(DI, SI);
+                Vsb          = -V(SI, BP);
+                Vjun_s       =  V(SI, BS);
+                Vjun_d       =  V(DI, BD);
+            end
+
+            // Voltages NOT subject to S/D-interchange
+            VgsPrime     =  Vgs;
+            VsbPrime     =  Vsb;
+            VdbPrime     =  Vds + Vsb;
+            VgdPrime     =  Vgs - Vds;
+            xgs_ov       = -VgsPrime * inv_phita;
+            xgd_ov       = -VgdPrime * inv_phita;
+
+            // Source-drain interchange
+            sigVds       =  1.0;
+            if (Vds < 0.0) begin
+                sigVds       = -1.0;
+                Vgs          =  Vgs - Vds;
+                Vsb          =  Vsb + Vds;
+                Vds          = -Vds;
+            end
+            Vdb          =  Vds + Vsb;
+            Vdsx         =  Vds * Vds / (sqrt(Vds * Vds + 0.01) + 0.1);
+
+            // Core's model calculation for DC
+            begin : SPcalc_dc
+
+                // Local variable declaration
+                `SPcalcLocalVarDecl
+                real FdL, qim1_1, r1, r2, s2, dL1;
+
+                // Conditioning of terminal voltages
+                temp         = `MINA(Vdb, Vsb, bphi_dc) + phix_dc;
+                Vsbstar_dc   =  Vsb - `MINA(temp, 0, aphi_dc) + phix1_dc;
+                Vsbstar_dc_tmp = Vsbstar_dc;
+
+                // Adapt Vsb for NUD-effect
+                if ((SWNUD_i != 0) && (GFACNUD_i != 1.0)) begin
+                    Vmb          =  Vsbstar_dc + 0.5 * (Vds - Vdsx);
+                    us           =  sqrt(Vmb + phib_dc) - sqrt_phib_dc;
+                    temp         =  2.0 * (us - us1) / us21 - 1.0;
+                    usnew        =  us - 0.25 * (1.0 - GFACNUD_i) * us21 * (temp + sqrt(temp * temp + 0.4804530139182));
+                    Vmbnew       =  usnew * usnew + (2.0 * sqrt_phib_dc) * usnew;
+                    Vsbstar_dc   =  Vmbnew - 0.5 * (Vds - Vdsx);
+                end
+
+                // Set variables needed in PSP103_SPCalculation.include
+                phib         =  phib_dc;
+                G_0          =  G_0_dc;
+                Vsbstar      =  Vsbstar_dc;
+                FdL          =  1.0;
+
+                `include "PSP103_SPCalculation.include"
+
+                if (xg > 0.0) begin
+                    qim1_1       =  1.0 / qim1;
+                    r1           =  qim * qim1_1;
+                    r2           =  phit1 * (alpha * qim1_1);
+                    s2           =  ln(1.0 + Vdsx * inv_VP);
+                    dL1          =  dL + ALP1_i * (qim1_1 * r1 * s1) + ALP2_i * (qbm * r2 * r2 * s2);
+                    FdL          =  (1.0 + dL1 + dL1 * dL1) * GdL;
+                end
+
+                xg_dc        =  xg;
+                qeff1_dc     =  qeff1;
+                Voxm_dc      =  Voxm;
+                alpha_dc     =  alpha;
+                dps_dc       =  dps;
+                qim_dc       =  qim;
+                qim1_dc      =  qim1;
+                GdL_dc       =  GdL;
+                FdL_dc       =  FdL;
+                H_dc         =  H;
+                eta_p_dc     =  eta_p;
+                Gvsat_dc     =  Gvsat;
+                Gvsatinv_dc  =  Gvsatinv;
+                Gmob_dL_dc   =  Gmob_dL;
+                x_ds_dc      =  x_ds;
+                x_m_dc       =  x_m;
+                Gf_dc        =  Gf;
+                Vdsat_dc     =  Vdsat;
+                Udse_dc      =  Udse;
+                Gmob_dc      =  Gmob;
+                xitsb_dc     =  xitsb;
+                Vdse_dc      =  Vdse;
+                `ifdef NQSmodel
+                    xgm_dc       =  xgm;
+                    thesat1_dc   =  thesat1;
+                    margin_dc    =  margin;
+                `endif // NQSmodel
+            end // SPcalc_dc
+
+            if (xg_dc <= 0) begin
+                Ids          =  0.0;
+            end else begin
+                // Drain-source current
+                Ids          =  BET_i * (FdL_dc * qim1_dc * dps_dc * Gvsatinv_dc);
+            end
+
+            // Surface potential in gate overlap regions
+            if (((SWIGATE_i != 0) && ((IGOV_i > 0.0) || (IGOVD_i > 0.0))) || ((SWGIDL_i != 0) && ((AGIDL_i > 0.0) || (AGIDLD_i > 0.0))) || (CGOV_i > 0.0) || (CGOVD_i > 0.0)) begin
+                SP_OV_xg     = 0.5 * (xgs_ov + sqrt(xgs_ov * xgs_ov + SP_OV_eps2_s));
+                xs_ov        = -SP_OV_xg - GOV2_s * 0.5 + GOV_s * sqrt(SP_OV_xg + GOV2_s * 0.25 + SP_OV_a_s) + SP_OV_delta1_s;
+                SP_OV_xg     = 0.5 * (xgd_ov + sqrt(xgd_ov * xgd_ov + SP_OV_eps2_d));
+                xd_ov        = -SP_OV_xg - GOV2_d * 0.5 + GOV_d * sqrt(SP_OV_xg + GOV2_d * 0.25 + SP_OV_a_d) + SP_OV_delta1_d;
+                Vovs         = -phita * (xgs_ov + xs_ov);
+                Vovd         = -phita * (xgd_ov + xd_ov);
+            end
+
+            // Gate current
+            Igsov        =  0.0;
+            Igdov        =  0.0;
+            Igc          =  0.0;
+            Igb          =  0.0;
+            Igcs         =  0.0;
+            Igcd         =  0.0;
+            if (SWIGATE_i != 0) begin
+                if (IGOV_i > 0.0) begin
+                    // Gate-source overlap component of gate current
+                    zg           =  sqrt(Vovs * Vovs + 1.0e-6) * inv_CHIB;
+                    if (GC3_i < 0.0) begin
+                        zg           = `MINA(zg, GCQ, 1.0e-6);
+                    end
+                    temp         =  BOV * (-1.5 + zg * (GC2_i + GC3_i * zg));
+                    if (temp > 0.0) begin
+                        TP           = `P3(temp);
+                    end else begin
+                        `expl_low(temp, TP)
+                    end
+                    Fs1          =  3.0 + xs_ov;
+                    Fs2          = -3.0 - GCO_i;
+                    Fs3          =  30.0 * VgsPrime;
+                    `MNE(Fs1, Fs3, 0.9, temp)
+                    `MXE(Fs2, temp, 0.3, Fs)
+                    Igsov        =  IGOV_i * (TP * Fs);
+                end
+
+                if (IGOVD_i > 0.0) begin
+                    // Gate-drain overlap component of gate current
+                    zg           =  sqrt(Vovd * Vovd + 1.0e-6) * inv_CHIB;
+                    if (GC3_i < 0.0) begin
+                        zg           = `MINA(zg, GCQ, 1.0e-6);
+                    end
+                    temp         =  BOV_d * (-1.5 + zg * (GC2_i + GC3_i * zg));
+                    if (temp > 0.0) begin
+                        TP           = `P3(temp);
+                    end else begin
+                        `expl_low(temp, TP)
+                    end
+                    Fs1          =  3.0 + xd_ov;
+                    Fs2          = -3.0 - GCO_i;
+                    Fs3          =  30.0 * VgdPrime;
+                    `MNE(Fs1, Fs3, 0.9, temp)
+                    `MXE(Fs2, temp, 0.3, Fs)
+                    Igdov        =  IGOVD_i * (TP * Fs);
+                end
+
+                // Gate-channel component of gate current
+                if (IGINV_i > 0.0) begin
+                    if (xg_dc <= 0.0) begin
+                        temp         =  pow(Vds / Vdsat_lim, AX_i);
+                        Udse_dc      =  Vds * pow(1.0 + temp, -inv_AX) * inv_phit1;
+                    end
+                    `expl_low(x_ds_dc-Udse_dc, temp)
+                    Vm           =  Vsbstar_dc + phit1 * (0.5 * x_ds_dc - ln(0.5 * (1.0 + temp)));
+                    Dch          =  GCO_i * phit1;
+                    arg2mina     =  Voxm_dc + Dch;
+                    psi_t        = `MINA(0.0, arg2mina, 0.01);
+                    zg           =  sqrt(Voxm_dc * Voxm_dc + 1.0e-6) * inv_CHIB;
+                    if (GC3_i < 0.0) begin
+                        zg           = `MINA(zg, GCQ, 1.0e-06);
+                    end
+                    arg1         =  (x_m_dc + (psi_t - alpha_b - Vm) * inv_phit1);
+                    `expl(arg1,Dsi)
+                    arg1         = -(Vgs + Vsbstar_dc - Vm) * inv_phit1;
+                    `expl(arg1,temp)
+                    Dgate        =  Dsi * temp;
+                    temp         =  BCH * (-1.5 + zg * (GC2_i + GC3_i * zg));
+                    if (temp > 0) begin
+                        TP           = `P3(temp);
+                    end else begin
+                        `expl_low(temp, TP)
+                    end
+                    Igc0         =  IGINV_i * (TP * ln((1.0 + Dsi) / (1.0 + Dgate)));
+
+                    // Source/drain partitioning of gate-channel current
+                    if ((xg_dc <= 0.0) || ((GC2_i == 0.0) && (GC3_i == 0.0))) begin
+                        igc          =  1.0;
+                        igcd_h       =  0.5;
+                    end else begin
+                        temp         =  GC2_i + 2.0 * GC3_i * zg;
+                        u0           =  CHIB_i / (temp * BCH);
+                        x            =  0.5 * (dps_dc / u0);
+                        u0_div_H     =  u0 / H_dc;
+                        Bg           =  u0_div_H * (1.0 - u0_div_H) * 0.5;
+                        Ag           =  0.5 - 3.0 * Bg;
+                        if (x < 1.0e-3) begin
+                            xsq          =  x * x;
+                            igc          =  1.0 + xsq * (`oneSixth + u0_div_H * `oneThird + `oneSixth * (xsq * (0.05 + 0.2 * u0_div_H)));
+                            igcd_h       =  0.5 * igc - `oneSixth * (x * (1.0 + xsq * (0.4 * (Bg + 0.25) + 0.0285714285714 * (xsq * (0.125 + Bg)))));
+                        end else begin
+                            inv_x        =  1.0 / x;
+                            `expl(x, ex)
+                            inv_ex       =  1.0 / ex;
+                            temp         =  ex - inv_ex;
+                            temp2        =  ex + inv_ex;
+                            igc          =  0.5 * ((1.0 - u0_div_H) * temp * inv_x + u0_div_H * temp2);
+                            igcd_h       =  0.5 * (igc - temp * (Bg - Ag * inv_x * inv_x) - Ag * temp2 * inv_x);
+                        end
+                    end
+                    Sg           =  0.5 * (1.0 + xg_dc / sqrt(xg_dc * xg_dc + 1.0e-6));
+                    Igc          =  Igc0 * igc * Sg;
+                    Igcd         =  Igc0 * igcd_h * Sg;
+                    Igcs         =  Igc - Igcd;
+                    Igb          =  Igc0 * igc * (1.0 - Sg);
+                end // (IGINV >0)
+            end // (SWIGATE != 0)
+
+            // GIDL/GISL current
+            Igidl        =  0.0;
+            Igisl        =  0.0;
+            if (SWGIDL_i != 0) begin
+                // GIDL current computation
+                if ((AGIDLD_i > 0) && (Vovd < 0)) begin
+                    Vtovd        =  sqrt(Vovd * Vovd + CGIDLD_i * CGIDLD_i * (VdbPrime * VdbPrime) + 1.0e-6);
+                    temp         = -BGIDLDs / Vtovd;
+                    `expl_low(temp, temp2)
+                    Igidl        = -AGIDLDs * (VdbPrime * Vovd * Vtovd * temp2);
+                end
+
+                // GISL current computation
+                if ((AGIDL_i > 0) && (Vovs < 0)) begin
+                    Vtovs        =  sqrt(Vovs * Vovs + CGIDL_i * CGIDL_i * (VsbPrime * VsbPrime) + 1.0e-6);
+                    temp         = -BGIDLs / Vtovs;
+                    `expl_low(temp, temp2)
+                    Igisl        = -AGIDLs * (VsbPrime * Vovs * Vtovs * temp2);
+                end
+            end // (SWGIDL != 0)
+
+            // Drain current of edge transistors: PSP 103.4
+            xgedge       =  0.0;
+            qdseffedge   =  0.0;
+            qmeffedge    =  0.0;
+            dsqredge     =  1.0e-40;
+            alphabmedge  =  1.0;
+            Idsedge      =  0.0;
+            if ((SWEDGE_i != 0.0) && (BETNEDGE_i > 0)) begin
+                temp         = `MINA(Vdb, Vsb, bphiedge) + phixedge;
+                Vsbstaredge  =  Vsb - `MINA(temp, 0, aphiedge) + phix1edge;
+                Vsbxedge     =  Vsbstaredge + 0.5 * (Vds - Vdsx);
+                dphit1edge   =  PSCEEDGE_i * (1 + PSCEDEDGE_i * Vdsx)* (1.0 + PSCEBEDGE_i * Vsbxedge); // SCE on subthreshold slope
+                phit1edge    =  phit0edge * (1.0 + dphit1edge);
+                inv_phit1edge =  1.0 / phit1edge;
+                if (CFDEDGE_i < 0.05) begin
+                    Vdspedge     =  Vdsx;
+                end else begin
+                    Vdspedge     =  2.0 * (sqrt(1.0 + CFDEDGE_i * Vdsx) - 1.0) / CFDEDGE_i;
+                end
+                delVgedge    =  CFEDGE_i * Vdspedge * (1 + CFBEDGE_i * Vsbxedge); // DIBL effect
+                xgedge       =  inv_phit1edge * (Vgs + Vsbstaredge + delVgedge - VFBEDGE_T);
+                xbedge       =  inv_phit1edge * phibedge;
+                dxthedge     =  2.0 * ln(xbedge / Gfedge + sqrt(xbedge));
+                xnedge_s     =  inv_phit1edge * Vsbstaredge;
+                `qi_edge(qseffedge,xgedge,xnedge_s)
+                xnedge_d     =  inv_phit1edge * (Vdse_dc + Vsbstaredge);
+                if ((qseffedge < 1.0e-3) && (Vdse_dc < 1.0e-6)) begin
+                    `expl_low((-xnedge_d + xnedge_s), temp)
+                    qdseffedge   =  qseffedge * (temp - 1.0);
+                    qdeffedge    =  qdseffedge + qseffedge;
+                end else begin
+                    `qi_edge(qdeffedge,xgedge,xnedge_d)
+                    qdseffedge   =  qdeffedge - qseffedge;
+                end
+                qmeffedge    =  0.5 * (qdeffedge + qseffedge);
+                dsqredge     =  max(xgedge - qmeffedge, 1.0e-40);
+                alphabmedge  =  1.0 - 0.5 * Gfedge / sqrt(dsqredge + 0.25 * Gfedge2);
+                Idsedge      = -BETEDGE_i * phit1edge * phit1edge * (alphabmedge * qmeffedge  + 1.0) * qdseffedge / Gmob_dc;
+            end
+
+            // Impact-Ionization
+            if ((xg_dc > 0) && (SWIMPACT_i != 0)) begin
+                delVsat      =  Vds - A3_i * dps_dc;
+                if (delVsat > 0) begin
+                    temp2        =  A2_T * ((1.0 + A4_i * (sqrt(phib_dc + Vsbstar_dc) - sqrt_phib_dc)) / (delVsat + 1.0e-30));
+                    `expl(-temp2, temp)
+                    mavl         =  A1_i * (delVsat * temp);
+                    Iimpact      =  mavl * (Ids + Idsedge);
+                end
+            end
+
+            // Threshold voltage calculation for .OP
+            P_D          =  1.0 + 0.25 * (Gf_dc * kp);
+            facvsb0      =  phib_dc + 2.0 * phit1;
+            facvsb       =  Vsbstar_dc + facvsb0;
+            vts_i        =  VFB_T + P_D * facvsb - Vsbstar_dc + Gf_dc * sqrt(phit1 * facvsb );
+            vth_i        =  vts_i - delVg;
+
+        end // evaluateStatic
+
+        //  --------------------------------------------------------------------------------------------------------------
+        //  AC bias dependent quantities (calculations for charge contribs)
+        //  --------------------------------------------------------------------------------------------------------------
+        begin : evaluateDynamic
+
+            // Core's model calculation for AC
+            begin : SPcalc_ac
+
+                // Local variable declaration
+                `SPcalcLocalVarDecl
+
+                // SP calculations
+                if ((SWNUD_i == 1) || (SWDELVTAC_i != 0)) begin
+                    if (SWDELVTAC_i != 0) begin
+                        // Conditioning of terminal voltages
+                        temp         = `MINA(Vdb, Vsb, bphi_ac) + phix_ac;
+                        Vsbstar_ac   =  Vsb - `MINA(temp, 0.0, aphi_ac) + phix1_ac;
+                        Vsbstar      =  Vsbstar_ac;
+                        phib         =  phib_ac;
+                        G_0          =  G_0_ac;
+                    end else begin
+                        Vsbstar      =  Vsbstar_dc_tmp;
+                        phib         =  phib_dc;
+                        G_0          =  G_0_dc;
+                    end
+
+                    `include "PSP103_SPCalculation.include"
+
+                    xg_ac        =  xg;
+                    qeff1_ac     =  qeff1;
+                    Voxm_ac      =  Voxm;
+                    alpha_ac     =  alpha;
+                    dps_ac       =  dps;
+                    qim_ac       =  qim;
+                    GdL_ac       =  GdL;
+                    H_ac         =  H;
+                    eta_p_ac     =  eta_p;
+                    Gvsat_ac     =  Gvsat;
+                    Gmob_dL_ac   =  Gmob_dL;
+                    `ifdef NQSmodel
+                        Gf_ac        =  Gf;
+                        x_m_ac       =  x_m;
+                        xgm_ac       =  xgm;
+                        thesat1_ac   =  thesat1;
+                        margin_ac    =  margin;
+                    `endif // NQSmodel
+                end else begin
+                    xg_ac        =  xg_dc;
+                    qeff1_ac     =  qeff1_dc;
+                    Voxm_ac      =  Voxm_dc;
+                    alpha_ac     =  alpha_dc;
+                    dps_ac       =  dps_dc;
+                    qim_ac       =  qim_dc;
+                    GdL_ac       =  GdL_dc;
+                    H_ac         =  H_dc;
+                    eta_p_ac     =  eta_p_dc;
+                    Gvsat_ac     =  Gvsat_dc;
+                    Gmob_dL_ac   =  Gmob_dL_dc;
+                    `ifdef NQSmodel
+                        Gf_ac        =  Gf_dc;
+                        x_m_ac       =  x_m_dc;
+                        xgm_ac       =  xgm_dc;
+                        thesat1_ac   =  thesat1_dc;
+                        margin_ac    =  margin_dc;
+                    `endif // NQSmodel
+                end
+            end // SPcalc_ac
+
+            // Quantum mechanical corrections
+            Vgb          =  Vgs + Vsb;
+            COX_qm       =  COX_i;
+            if (qq > 0.0) begin
+                COX_qm       =  COX_i / (1.0 + qq * pow(qeff1_ac * qeff1_ac + qlim2, -1.0 * `oneSixth));
+            end
+
+            // Intrinsic charge model
+            if (xg_ac <= 0.0) begin
+                QG           =  Voxm_ac;
+                QI           =  0.0;
+                QD           =  0.0;
+                QB           =  QG;
+            end else begin
+                Fj           =  0.5 * (dps_ac / H_ac);
+                Fj2          =  Fj * Fj;
+                QCLM         =  (1.0 - GdL_ac) * (qim_ac - 0.5 * (alpha_ac * dps_ac));
+                QG           =  Voxm_ac + 0.5 * (eta_p_ac * dps_ac * (Fj * GdL_ac * `oneThird - 1.0 + GdL_ac));
+                temp         =  alpha_ac * dps_ac * `oneSixth;
+                QI           =  GdL_ac * (qim_ac + temp * Fj) + QCLM;
+                QD           =  0.5 * (GdL_ac * GdL_ac * (qim_ac - temp * (1.0 - Fj - 0.2 * Fj2)) + QCLM * (1.0 + GdL_ac));
+                QB           =  QG - QI;
+            end
+            Qg           =  QG * COX_qm;
+            Qd           = -QD * COX_qm;
+            Qb           = -QB * COX_qm;
+
+            // Extrinsic charge model
+            Qgs_ov       =  CGOV_i * Vovs;
+            Qgd_ov       =  CGOVD_i * Vovd;
+            Qgb_ov       =  CGBOV_i * Vgb;
+
+            // Outer fringe charge
+            Qfgs         =  CFR_i * VgsPrime;
+            Qfgd         =  CFRD_i * VgdPrime;
+
+            // Variables for NQS model
+            `ifdef NQSmodel
+                Gp           =  0.0;
+                Gp2          =  0.0;
+                a_factrp     =  0.0;
+                marginp      =  0.0;
+                if (SWNQS_i != 0) begin
+                    if (xg_ac <= 0.0) begin
+                        ym           =  0.5;
+                        pd           =  1.0;
+                        Gp           =  Gf_ac;
+                    end else begin
+                        ym           =  0.5 * ( 1.0 + 0.25 * (dps_ac / H_ac));
+                        pd           =  xgm_ac / (xg_ac - x_m_ac);
+                        Gp           =  Gf_ac / pd;
+                    end
+                    Gp2          =  Gp * Gp;
+                    a_factrp     =  1.0 + Gp * `invSqrt2;
+                    marginp      =  1.0e-5 * a_factrp;
+                end
+            `endif // NQSmodel
+
+        end // evaluateDynamic
+
+        //  --------------------------------------------------------------------------------------------------------------
+        //  JUNCAP2 contribs
+        //  --------------------------------------------------------------------------------------------------------------
+        begin : evaluateStaticDynamic
+            ijun_s       =  0.0;
+            ijunbot_s    =  0.0;
+            ijunsti_s    =  0.0;
+            ijungat_s    =  0.0;
+            ijun_d       =  0.0;
+            ijunbot_d    =  0.0;
+            ijunsti_d    =  0.0;
+            ijungat_d    =  0.0;
+            qjun_s       =  0.0;
+            qjunbot_s    =  0.0;
+            qjunsti_s    =  0.0;
+            qjungat_s    =  0.0;
+            qjun_d       =  0.0;
+            qjunbot_d    =  0.0;
+            qjunsti_d    =  0.0;
+            qjungat_d    =  0.0;
+            if (SWJUNCAP_i > 0) begin
+                if (SWJUNEXP_i == 1) begin
+                    `JuncapExpressCurrent(Vjun_s, MFOR1_s, ISATFOR1_s, MFOR2_s, ISATFOR2_s, MREV_s, ISATREV_s, m0flag_s, xhighf1_s, expxhf1_s, xhighf2_s, expxhf2_s, xhighr_s, expxhr_s, ijun_s)
+                    `JuncapExpressCurrent(Vjun_d, MFOR1_d, ISATFOR1_d, MFOR2_d, ISATFOR2_d, MREV_d, ISATREV_d, m0flag_d, xhighf1_d, expxhf1_d, xhighf2_d, expxhf2_d, xhighr_d, expxhr_d, ijun_d)
+                    begin : evaluateDynamic
+                        real tmpv, vjv;
+                        `JuncapExpressCharge(Vjun_s, ABSOURCE_i, LSSOURCE_i, LGSOURCE_i, qprefbot,   qprefsti,   qprefgat,   qpref2bot,   qpref2sti,   qpref2gat,   vbiinvbot,   vbiinvsti,   vbiinvgat,   one_minus_PBOT,   one_minus_PSTI,   one_minus_PGAT,   vfmin_s, vch_s, zflagbot_s, zflagsti_s, zflaggat_s, qjunbot_s, qjunsti_s, qjungat_s)
+                        `JuncapExpressCharge(Vjun_d, ABDRAIN_i,  LSDRAIN_i,  LGDRAIN_i,  qprefbot_d, qprefsti_d, qprefgat_d, qpref2bot_d, qpref2sti_d, qpref2gat_d, vbiinvbot_d, vbiinvsti_d, vbiinvgat_d, one_minus_PBOT_d, one_minus_PSTI_d, one_minus_PGAT_d, vfmin_d, vch_d, zflagbot_d, zflagsti_d, zflaggat_d, qjunbot_d, qjunsti_d, qjungat_d)
+                    end
+                end else begin
+                    `juncapcommon(Vjun_s, ABSOURCE_i, LSSOURCE_i, LGSOURCE_i, qprefbot, qpref2bot, vbiinvbot, one_minus_PBOT, idsatbot, CSRHBOT_i, CTATBOT_i, vbibot, wdepnulrbot, VBIRBOTinv, PBOT_i, ftdbot, btatpartbot, atatbot, one_over_one_minus_PBOT, CBBTBOT_i, VBIRBOT_i, wdepnulrinvbot, fbbtbot, VBRBOT_i, VBRinvbot, PBRBOT_i, fstopbot, slopebot, qprefsti, qpref2sti, vbiinvsti, one_minus_PSTI, idsatsti, CSRHSTI_i, CTATSTI_i, vbisti, wdepnulrsti, VBIRSTIinv, PSTI_i, ftdsti, btatpartsti, atatsti, one_over_one_minus_PSTI, CBBTSTI_i, VBIRSTI_i, wdepnulrinvsti, fbbtsti, VBRSTI_i, VBRinvsti, PBRSTI_i, fstopsti, slopesti, qprefgat, qpref2gat, vbiinvgat, one_minus_PGAT, idsatgat, CSRHGAT_i, CTATGAT_i, vbigat, wdepnulrgat, VBIRGATinv, PGAT_i, ftdgat, btatpartgat, atatgat, one_over_one_minus_PGAT, CBBTGAT_i, VBIRGAT_i, wdepnulrinvgat, fbbtgat, VBRGAT_i, VBRinvgat, PBRGAT_i, fstopgat, slopegat, VMAX_s, exp_VMAX_over_phitd_s, vbimin_s, vch_s, vfmin_s, vbbtlim_s, ijunbot_s, qjunbot_s, ijunsti_s, qjunsti_s, ijungat_s, qjungat_s)
+                    ijun_s = ABSOURCE_i * ijunbot_s + LSSOURCE_i * ijunsti_s + LGSOURCE_i * ijungat_s;
+                    `juncapcommon(Vjun_d, ABDRAIN_i,  LSDRAIN_i,  LGDRAIN_i,  qprefbot_d, qpref2bot_d, vbiinvbot_d, one_minus_PBOT_d, idsatbot_d, CSRHBOTD_i, CTATBOTD_i, vbibot_d, wdepnulrbot_d, VBIRBOTinv_d, PBOTD_i, ftdbot_d, btatpartbot_d, atatbot_d, one_over_one_minus_PBOT_d, CBBTBOTD_i, VBIRBOTD_i, wdepnulrinvbot_d, fbbtbot_d, VBRBOTD_i, VBRinvbot_d, PBRBOTD_i, fstopbot_d, slopebot_d, qprefsti_d, qpref2sti_d, vbiinvsti_d, one_minus_PSTI_d, idsatsti_d, CSRHSTID_i, CTATSTID_i, vbisti_d, wdepnulrsti_d, VBIRSTIinv_d, PSTID_i, ftdsti_d, btatpartsti_d, atatsti_d, one_over_one_minus_PSTI_d, CBBTSTID_i, VBIRSTID_i, wdepnulrinvsti_d, fbbtsti_d, VBRSTID_i, VBRinvsti_d, PBRSTID_i, fstopsti_d, slopesti_d, qprefgat_d, qpref2gat_d, vbiinvgat_d, one_minus_PGAT_d, idsatgat_d, CSRHGATD_i, CTATGATD_i, vbigat_d, wdepnulrgat_d, VBIRGATinv_d, PGATD_i, ftdgat_d, btatpartgat_d, atatgat_d, one_over_one_minus_PGAT_d, CBBTGATD_i, VBIRGATD_i, wdepnulrinvgat_d, fbbtgat_d, VBRGATD_i, VBRinvgat_d, PBRGATD_i, fstopgat_d, slopegat_d, VMAX_d, exp_VMAX_over_phitd_d, vbimin_d, vch_d, vfmin_d, vbbtlim_d, ijunbot_d, qjunbot_d, ijunsti_d, qjunsti_d, ijungat_d, qjungat_d)
+                    ijun_d = ABDRAIN_i * ijunbot_d + LSDRAIN_i * ijunsti_d + LGDRAIN_i * ijungat_d;
+                end
+            end
+
+            //  --------------------------------------------------------------------------------------------------------------
+            //  NQS and parasitic resistance contribs
+            //  --------------------------------------------------------------------------------------------------------------
+
+            // Set initial conditions for NQS model
+            `ifdef NQSmodel
+                `include "PSP103_InitNQS.include"
+            `endif // NQSmodel
+
+            // Parasitic resistances (including noise)
+            rgatenoise   =  nt0 * ggate;
+            rsourcenoise =  nt0 * gsource;
+            rdrainnoise  =  nt0 * gdrain;
+            rbulknoise   =  nt0 * gbulk;
+            rjunsnoise   =  nt0 * gjuns;
+            rjundnoise   =  nt0 * gjund;
+            rwellnoise   =  nt0 * gwell;
+
+        end // evaluateStaticDynamic
+
+        //  --------------------------------------------------------------------------------------------------------------
+        //  Current contribs
+        //  --------------------------------------------------------------------------------------------------------------
+        begin : loadStatic
+
+            // Convert back for NMOS-PMOS and Source-Drain interchange
+            if (sigVds > 0.0) begin
+                I(DI, BP)    <+  CHNL_TYPE * MULT_i * Iimpact;
+                I(DI, SI)    <+  CHNL_TYPE * MULT_i * (Ids + Idsedge);
+                I(GP, SI)    <+  CHNL_TYPE * MULT_i * Igcs;
+                I(GP, DI)    <+  CHNL_TYPE * MULT_i * Igcd;
+            end else begin
+                I(SI, BP)    <+  CHNL_TYPE * MULT_i * Iimpact;
+                I(SI, DI)    <+  CHNL_TYPE * MULT_i * (Ids + Idsedge);
+                I(GP, DI)    <+  CHNL_TYPE * MULT_i * Igcs;
+                I(GP, SI)    <+  CHNL_TYPE * MULT_i * Igcd;
+            end
+            I(GP, BP)    <+  CHNL_TYPE * MULT_i * Igb;
+            I(GP, SI)    <+  CHNL_TYPE * MULT_i * Igsov;
+            I(GP, DI)    <+  CHNL_TYPE * MULT_i * Igdov;
+            I(SI, BP)    <+  CHNL_TYPE * MULT_i * Igisl;
+            I(DI, BP)    <+  CHNL_TYPE * MULT_i * Igidl;
+            I(BS, SI)    <+  CHNL_TYPE * MULT_i * ijun_s;
+            I(BD, DI)    <+  CHNL_TYPE * MULT_i * ijun_d;
+
+            `CollapsableR(ggate,   RG_i,    rgatenoise,   G,  GP, "rgate")
+            `CollapsableR(gsource, RSE_i,   rsourcenoise, S,  SI, "rsource")
+            `CollapsableR(gdrain,  RDE_i,   rdrainnoise,  D,  DI, "rdrain")
+            `CollapsableR(gbulk,   RBULK_i, rbulknoise,   BP, BI, "rbulk")
+            `CollapsableR(gjuns,   RJUNS_i, rjunsnoise,   BS, BI, "rjuns")
+            `CollapsableR(gjund,   RJUND_i, rjundnoise,   BD, BI, "rjund")
+            `CollapsableR(gwell,   RWELL_i, rwellnoise,   B,  BI, "rwell")
+
+            I(DI, SI)  <+  `GMIN * V(DI, SI);
+
+        end // loadStatic
+
+        //  --------------------------------------------------------------------------------------------------------------
+        //  ddt() contribs from charges (Note: MULT is handled explicitly)
+        //  --------------------------------------------------------------------------------------------------------------
+        begin : loadStaticDynamic
+
+            // Implementation of NQS charges
+            `ifdef NQSmodel
+                `include "PSP103_ChargesNQS.include"
+            `endif // NQSmodel
+
+            // Implementation of Self heating effect
+            `ifdef SelfHeating
+                begin : self_heating
+                    real Pdiss_s, Pdiss_d;
+                    Pdiss        =  0.0;
+                    Pdiss_s      =  0.0;
+                    Pdiss_d      =  0.0;
+                    if (RSE_i > 0.0) begin
+                        Pdiss_s      =  gsource * V(S, SI) * V(S, SI);
+                    end
+                    if (RDE_i > 0.0) begin
+                        Pdiss_d      =  gdrain * V(D, DI) * V(D, DI);
+                    end
+                    if (RTH_p > 1.0e-3) begin
+                        Pdiss        =  ((Ids + Idsedge) * Vds + Iimpact * (Vds + Vsb) + Pdiss_s + Pdiss_d);
+                    end
+                    Pwr(br_ith)  <+ -MULT_i * Pdiss;
+                    Pwr(br_rth)  <+  ddt(MULT_i * CTH_i * Temp(br_rth));
+                    Pwr(br_rth)  <+  MULT_i * Temp(br_rth) / RTH_T;
+                end // self_heating
+            `endif // SelfHeating
+
+        end // loadStaticDynamic
+
+        begin : loadDynamic
+
+            // Local variable
+            real temp;
+
+            // Intrinsic MOSFET charges
+            Qs           =  -(Qg + Qb + Qd);
+
+            // Total outerFringe + overlap for gate-source and gate-drain.
+            Qfgs         =  Qfgs + Qgs_ov;
+            Qfgd         =  Qfgd + Qgd_ov;
+
+            // JUNCAP2
+            qjun_s       =  ABSOURCE_i * qjunbot_s + LSSOURCE_i * qjunsti_s + LGSOURCE_i * qjungat_s;
+            qjun_d       =  ABDRAIN_i * qjunbot_d + LSDRAIN_i * qjunsti_d + LGDRAIN_i * qjungat_d;
+
+            // Convert back (undo S-D interchange)
+            if (sigVds < 0.0) begin
+                temp         =  Qd;    // Qd <--> Qs
+                Qd           =  Qs;
+                Qs           =  temp;
+            end
+
+            I(GP, SI)    <+  ddt(CHNL_TYPE * MULT_i * Qg);
+            I(BP, SI)    <+  ddt(CHNL_TYPE * MULT_i * Qb);
+            I(DI, SI)    <+  ddt(CHNL_TYPE * MULT_i * Qd);
+            I(GP, SI)    <+  ddt(CHNL_TYPE * MULT_i * Qfgs);
+            I(GP, DI)    <+  ddt(CHNL_TYPE * MULT_i * Qfgd);
+            I(GP, BP)    <+  ddt(CHNL_TYPE * MULT_i * Qgb_ov);
+            I(BS, SI)    <+  ddt(CHNL_TYPE * MULT_i * qjun_s);
+            I(BD, DI)    <+  ddt(CHNL_TYPE * MULT_i * qjun_d);
+
+        end // loadDynamic
+
+        //  --------------------------------------------------------------------------------------------------------------
+        //  Noise
+        //  --------------------------------------------------------------------------------------------------------------
+        begin : noise
+
+            // Noise variable calculation
+            Sfl          =  0.0;
+            Sidexc       =  0.0;
+            mid          =  0.0;
+            mig          =  1.0e-40;
+            migid        =  0.0;
+            c_igid       =  0.0;
+            CGeff        =  COX_qm * eta_p_ac;
+            sqid         =  0.0;
+            sqig         =  0.0;
+            Sfledge      =  0.0;
+            midedge      =  0.0;
+            sqidedge     =  0.0;
+
+            // Channel noise contributions
+            if ((xg_dc > 0.0) && (MULT_i > 0.0) && (BET_i > 0.0)) begin
+                // Flicker noise
+                N1           =  Cox_over_q * alpha_dc * phit;
+                Nm1          =  Cox_over_q * qim1_dc;
+                Delta_N1     =  Cox_over_q * alpha_dc * dps_dc;
+                Sfl          =  (NFA_i - NFB_i * N1 + NFC_i * (N1 * N1)) * ln((Nm1 + 0.5 * Delta_N1) / (Nm1 - 0.5 * Delta_N1));
+                Sfl          =  Sfl + (NFB_i + NFC_i * (Nm1 - 2.0 * N1)) * Delta_N1;
+                Sfl          =  Sfl_prefac * Ids * Gvsatinv_dc * Sfl / N1;
+                Sfl          = `CLIP_LOW(Sfl, 0.0);
+
+                // Thermal channel noise
+                H0           =  qim1_dc / alpha_dc;
+                t1           =  qim_dc / qim1_dc;
+                sqt2         =  0.5 * `oneSixth * (dps_dc / H0);
+                t2           =  sqt2 * sqt2;
+                r            =  H0 / H_dc - 1.0;
+                lc           = `CLIP_LOW(1.0 - 12.0 * (r * t2), 1.0e-20);
+                lcinv2       =  1.0 / (lc * lc);
+                g_ideal      =  BET_i * (FdL_dc * qim1_dc * Gvsatinv_dc);
+                mid          =  t1 + 12.0 * t2 - 24.0 * ((1.0 + t1) * t2 * r);
+                mid          = `CLIP_LOW(mid, 1.0e-40);
+                mid          =  g_ideal * lcinv2 * mid;
+                if (FNTEXC_i > 0.0) begin
+                    // recalculate Gvsat, excluding Gmob-effect
+                    temp2_exc    =  qim_dc * xitsb_dc;
+                    wsat_exc     =  100.0 * (temp2_exc / (100.0 + temp2_exc));
+                    if (THESATG_i < 0) begin
+                        temp_exc     = 1.0 / (1.0 - THESATG_i * wsat_exc);
+                    end else begin
+                        temp_exc     = 1.0 + THESATG_i * wsat_exc;
+                    end
+                    thesat1_exc  =  THESAT_T * (temp_exc / Gmob_dc);
+                    zsat_exc     =  thesat1_exc * thesat1_exc * dps_dc * dps_dc;
+                    if (CHNL_TYPE == `PMOS) begin
+                        zsat_exc     =  zsat_exc / (1.0 + thesat1_exc * dps_dc);
+                    end
+                    Gvsat_exc    =  0.5 * (Gmob_dc * (1.0 + sqrt(1.0 + 2.0 * zsat_exc)));
+                    gfac         =  Gmob_dc / (Gvsat_exc * lc);
+                    Sidexc       =  fac_exc * Ids * Vdse_dc * gfac * gfac;
+                    mid          =  mid + Sidexc / nt0;
+                end
+                sqid         =  sqrt(nt * mid);
+
+                // Induced gate noise
+                if ((SWIGN_i == 1) && (nt > 0.0)) begin
+                    mig          =  t1 / 12.0 - t2 * (t1 + 0.2 - 12.0 * t2) - 1.6 * (t2 * (t1 + 1.0 - 12.0 * t2) * r);
+                    mig          = `CLIP_LOW(mig, 1.0e-40);
+                    mig          =  lcinv2 / g_ideal * mig;
+                    migid0       =  lcinv2 * sqt2 * (1.0 - 12.0 * t2 - (t1 + 19.2 * t2 - 12.0 * (t1 * t2)) * r);
+                    CGeff        =  Gvsat_ac * Gvsat_ac * COX_qm * eta_p_ac / (Gmob_dL_ac * Gmob_dL_ac);
+                    if (FNTEXC_i > 0.0) begin
+                        mig          =  mig + Sidexc * (1.0 + 12.0 * t2) / (12.0 * g_ideal * g_ideal * nt0);
+                        migid0       =  migid0 - Sidexc * sqt2 * (1.0 + r) / (g_ideal * nt0);
+                    end
+                    sqig         =  sqrt(nt / mig);
+                    if (sqid == 0) begin
+                        c_igid       =  0.0;
+                    end else begin
+                        c_igid       =  migid0 * sqig / sqid; // = migid0 / sqrt(mig * mid);
+                    end
+                    c_igid       = `CLIP_BOTH(c_igid, 0.0, 1.0);
+                    migid        =  c_igid * sqid / sqig;
+                end
+            end
+
+            // Noise of gate leakage currents
+            shot_igcsx   =  2.0 * `QELE * abs(Igcs);
+            shot_igcdx   =  2.0 * `QELE * abs(Igcd);
+            shot_igsov   =  2.0 * `QELE * abs(Igsov);
+            shot_igdov   =  2.0 * `QELE * abs(Igdov);
+
+            // Noise of impact ionization currents
+            shot_iavl    =  2.0 * `QELE * ((mavl + 1) * abs(Iimpact));
+
+            // Noise of junctions (JUNCAP2)
+            jnoisex_s    =  2.0 * `QELE * abs(ijun_s);
+            jnoisex_d    =  2.0 * `QELE * abs(ijun_d);
+            if (sigVds > 0.0) begin
+                shot_igs     =  shot_igcsx + shot_igsov;
+                shot_igd     =  shot_igcdx + shot_igdov;
+                jnoise_s     =  jnoisex_s;
+                jnoise_d     =  jnoisex_d + shot_iavl;
+            end else begin
+                shot_igs     =  shot_igcdx + shot_igsov;
+                shot_igd     =  shot_igcsx + shot_igdov;
+                jnoise_s     =  jnoisex_s + shot_iavl;
+                jnoise_d     =  jnoisex_d;
+            end
+
+            // Noise of edge transistors: PSP 103.4
+            if ((SWEDGE_i != 0.0) && (BETNEDGE_i > 0) && (xgedge > 0)) begin
+                // Flicker noise of edge transistor
+                temp1        =  4.0 * dsqredge / Gfedge2;
+                anoisedge    =  sqrt(temp1 + 1.0) / (sqrt(temp1 + 1.1) - 1.0);
+                temp1        =  Cox_over_q * phit;
+                N1edge       =  temp1 * anoisedge;
+                Nm1edge      =  temp1 * (qmeffedge + anoisedge);
+                Delta_N1edge = -temp1 * anoisedge * alphabmedge * qdseffedge;
+                Sfledge      =  (NFAEDGE_i - (NFBEDGE_i - NFCEDGE_i * N1edge) * N1edge) * ln((Nm1edge + 0.5 * Delta_N1edge) / (Nm1edge - 0.5 * Delta_N1edge));
+                Sfledge      =  Sfledge + (NFBEDGE_i + NFCEDGE_i * (Nm1edge - 2.0 * N1edge)) * Delta_N1edge;
+                Sfledge      =  Sfl_prefac_edge * Idsedge * Gvsatinv_dc * Sfledge / N1edge;
+                Sfledge      = `CLIP_LOW(Sfledge, 0.0);
+
+                // Thermal channel noise of edge transistor
+                H0edge       =  phit * (qmeffedge + anoisedge) / anoisedge;
+                t1edge       =  phit1 / phit * qmeffedge / (qmeffedge + anoisedge);
+                sqt2edge     = -0.5 * `oneSixth * phit * alphabmedge * qdseffedge / H0edge;
+                t2edge       =  sqt2edge * sqt2edge;
+                redge        =  0.0;
+                temp1        =  alpha_dc * H_dc;
+                if (temp1 > 1.0e-10) begin
+                    redge        =  anoisedge * H0edge / temp1 - 1.0;
+                end
+                lcedge       = `CLIP_LOW(1.0 - 12.0 * (redge * t2edge), 1.0e-20);
+                lcinv2edge   =  1.0 / (lcedge * lcedge);
+                g_idealedge  =  BETEDGE_i * phit * (qmeffedge + anoisedge) * FdL_dc * Gvsatinv_dc;
+                midedge      =  t1edge + 12.0 * t2edge - 24.0 * ((1.0 + t1edge) * t2edge * redge);
+                midedge      = `CLIP_LOW(midedge, 1.0e-40);
+                midedge      =  g_idealedge * lcinv2edge * midedge;
+                sqidedge     =  sqrt(ntedge * midedge);
+            end
+
+            // Noise contributions
+            I(NOII)      <+  white_noise((nt / mig), "igig");
+            I(NOIR)      <+  V(NOIR) / mig;
+            I(NOIC)      <+  ddt(CGeff * V(NOIC));
+            I(GP,SI)     <+ -ddt(sqrt(MULT_i) * 0.5 * CGeff * V(NOIC));
+            I(GP,DI)     <+ -ddt(sqrt(MULT_i) * 0.5 * CGeff * V(NOIC));
+            I(DI,SI)     <+  sigVds * sqrt(MULT_i) * migid * I(NOII);
+            I(DI,SI)     <+  white_noise(MULT_i * sqid * sqid * (1.0 - c_igid * c_igid), "idid");
+            I(DI,SI)     <+  flicker_noise(MULT_i * Sfl, EF_i, "flicker");
+            I(GP,SI)     <+  white_noise(MULT_i * shot_igs, "igs");
+            I(GP,DI)     <+  white_noise(MULT_i * shot_igd, "igd");
+            I(BS,SI)     <+  white_noise(MULT_i * jnoise_s, "ibs");
+            I(BD,DI)     <+  white_noise(MULT_i * jnoise_d, "ibd");
+            I(DI,SI)     <+  flicker_noise(MULT_i * Sfledge, EFEDGE_i, "flicker");
+            I(DI,SI)     <+  white_noise(MULT_i * sqidedge * sqidedge, "ididedge");
+
+        end // noise
+
+        //  --------------------------------------------------------------------------------------------------------------
+        //  Operating point info
+        //  --------------------------------------------------------------------------------------------------------------
+        begin : OPinfo
+
+            // Auxiliary variables
+            id_op        =  Ids + Idsedge + Iimpact - Igcd;
+            is           = -Ids - Idsedge - Igcs;
+            ig           =  Igcs + Igcd + Igsov + Igdov + Igb;
+            ib           = -Iimpact - Igb - Igidl - Igisl;
+            sig1k        =  2.0e3 * `PI * CGeff;
+            sig1k        =  sig1k * sig1k * mig;
+
+            //  Actual operation point output variables
+            sdint        =  sigVds;
+            ctype        =  CHNL_TYPE;
+            if (sigVds < 0.0) begin
+                ise          =  MULT_i * (is - Igdov + Igidl - ijun_d);
+                ige          =  MULT_i * ig;
+                ide          =  MULT_i * (id_op - Igsov + Igisl - ijun_s);
+                ibe          =  MULT_i * (ib + ijun_s + ijun_d);
+                ids          =  MULT_i * Ids;
+                idb          =  MULT_i * (Iimpact + Igisl - ijun_s);
+                isb          =  MULT_i * (Igidl - ijun_d);
+                igs          =  MULT_i * (Igcs + Igdov);
+                igd          =  MULT_i * (Igcd + Igsov);
+                igb          =  MULT_i * Igb;
+                idedge       =  MULT_i * Idsedge;
+                igcs         =  MULT_i * Igcs;
+                igcd         =  MULT_i * Igcd;
+                iavl         =  MULT_i * Iimpact;
+                igisl        =  MULT_i * Igidl;
+                igidl        =  MULT_i * Igisl;
+                if (SWJUNEXP_i == 1) begin
+                    ijsbot       =  0.0;
+                    ijsgat       =  0.0;
+                    ijssti       =  0.0;
+                    ijdbot       =  0.0;
+                    ijdgat       =  0.0;
+                    ijdsti       =  0.0;
+                    idsatsbot    =  0.0;
+                    idsatssti    =  0.0;
+                    idsatsgat    =  0.0;
+                    idsatsbotd   =  0.0;
+                    idsatsstid   =  0.0;
+                    idsatsgatd   =  0.0;
+                end else begin
+                    ijsbot       =  MULT_i * ABDRAIN_i * ijunbot_d;
+                    ijsgat       =  MULT_i * LGDRAIN_i * ijungat_d;
+                    ijssti       =  MULT_i * LSDRAIN_i * ijunsti_d;
+                    ijdbot       =  MULT_i * ABSOURCE_i * ijunbot_s;
+                    ijdgat       =  MULT_i * LGSOURCE_i * ijungat_s;
+                    ijdsti       =  MULT_i * LSSOURCE_i * ijunsti_s;
+                    idsatsbot    =  MULT_i * ABSOURCE_i * idsatbot;
+                    idsatssti    =  MULT_i * LSSOURCE_i * idsatsti;
+                    idsatsgat    =  MULT_i * LGSOURCE_i * idsatgat;
+                    idsatsbotd   =  MULT_i * ABDRAIN_i * idsatbot_d;
+                    idsatsstid   =  MULT_i * LSDRAIN_i * idsatsti_d;
+                    idsatsgatd   =  MULT_i * LGDRAIN_i * idsatgat_d;
+                end
+                ijs          =  MULT_i * ijun_d;
+                ijd          =  MULT_i * ijun_s;
+                vds          =  Vds;
+                vgs          =  Vgs;
+                vsb          =  Vsb;
+                vto          =  VFB_T + P_D * facvsb0 + Gf_dc * sqrt(phit1 * facvsb0);
+                vts          =  vts_i;
+                vth          =  vth_i;
+                vgt          =  vgs - vth;
+                vdss         =  Vdsat_dc;
+                vsat         =  Vds - vdss;
+                ids_i        =  Ids + Idsedge + Iimpact + Igisl - Igcd - Igsov - ijun_s; // Total drain-current
+                `ifdef OPderiv
+                    gm           =  CHNL_TYPE * MULT_i * ddx(ids_i, V(GP));
+                    gmb          =  CHNL_TYPE * MULT_i * ddx(ids_i, V(BP));
+                    gds          =  CHNL_TYPE * MULT_i * ddx(ids_i, V(SI));
+                    gjs          =  MULT_i * ddx(ijun_d, V(BD));
+                    gjd          =  MULT_i * ddx(ijun_s, V(BS));
+                    css          =  CHNL_TYPE * MULT_i * ddx(Qd, V(DI));
+                    csg          = -CHNL_TYPE * MULT_i * ddx(Qd, V(GP));
+                    csb          = -CHNL_TYPE * MULT_i * ddx(Qd, V(BP));
+                    csd          =  css - csg - csb;
+                    cgs          = -CHNL_TYPE * MULT_i * ddx(Qg, V(DI));
+                    cgg          =  CHNL_TYPE * MULT_i * ddx(Qg, V(GP));
+                    cgb          = -CHNL_TYPE * MULT_i * ddx(Qg, V(BP));
+                    cgd          =  cgg - cgs - cgb;
+                    cds          = -CHNL_TYPE * MULT_i * ddx(Qs, V(DI));
+                    cdg          = -CHNL_TYPE * MULT_i * ddx(Qs, V(GP));
+                    cdb          = -CHNL_TYPE * MULT_i * ddx(Qs, V(BP));
+                    cdd          =  cdg + cds + cdb;
+                    cbs          = -CHNL_TYPE * MULT_i * ddx(Qb, V(DI));
+                    cbg          = -CHNL_TYPE * MULT_i * ddx(Qb, V(GP));
+                    cbb          =  CHNL_TYPE * MULT_i * ddx(Qb, V(BP));
+                    cbd          =  cbb - cbs - cbg;
+                    cgsol        =  CHNL_TYPE * MULT_i * ddx(Qfgd, V(GP));
+                    cgdol        =  CHNL_TYPE * MULT_i * ddx(Qfgs, V(GP));
+                    cjsbot       = -MULT_i * CHNL_TYPE * ABDRAIN_i * ddx(qjunbot_d, V(DI));
+                    cjsgat       = -MULT_i * CHNL_TYPE * LGDRAIN_i * ddx(qjungat_d, V(DI));
+                    cjssti       = -MULT_i * CHNL_TYPE * LSDRAIN_i * ddx(qjunsti_d, V(DI));
+                    cjs          =  cjsbot + cjsgat + cjssti;
+                    cjdbot       = -MULT_i * CHNL_TYPE * ABSOURCE_i * ddx(qjunbot_s, V(SI));
+                    cjdgat       = -MULT_i * CHNL_TYPE * LGSOURCE_i * ddx(qjungat_s, V(SI));
+                    cjdsti       = -MULT_i * CHNL_TYPE * LSSOURCE_i * ddx(qjunsti_s, V(SI));
+                    cjd          =  cjdbot + cjdgat + cjdsti;
+                `endif // OPderiv
+            end else begin
+                ise          =  MULT_i * (is - Igsov + Igisl - ijun_s);
+                ige          =  MULT_i * ig;
+                ide          =  MULT_i * (id_op - Igdov + Igidl - ijun_d);
+                ibe          =  MULT_i * (ib + ijun_s + ijun_d);
+                ids          =  MULT_i * Ids;
+                idb          =  MULT_i * (Iimpact + Igidl - ijun_d);
+                isb          =  MULT_i * (Igisl - ijun_s);
+                igs          =  MULT_i * (Igcs + Igsov);
+                igd          =  MULT_i * (Igcd + Igdov);
+                igb          =  MULT_i * Igb;
+                idedge       =  MULT_i * Idsedge;
+                igcs         =  MULT_i * Igcs;
+                igcd         =  MULT_i * Igcd;
+                iavl         =  MULT_i * Iimpact;
+                igisl        =  MULT_i * Igisl;
+                igidl        =  MULT_i * Igidl;
+                if (SWJUNEXP_i == 1) begin
+                    ijsbot       =  0.0;
+                    ijsgat       =  0.0;
+                    ijssti       =  0.0;
+                    ijdbot       =  0.0;
+                    ijdgat       =  0.0;
+                    ijdsti       =  0.0;
+                    idsatsbot    =  0.0;
+                    idsatssti    =  0.0;
+                    idsatsgat    =  0.0;
+                    idsatsbotd   =  0.0;
+                    idsatsstid   =  0.0;
+                    idsatsgatd   =  0.0;
+                end else begin
+                    ijsbot       =  MULT_i * ABSOURCE_i * ijunbot_s;
+                    ijsgat       =  MULT_i * LGSOURCE_i * ijungat_s;
+                    ijssti       =  MULT_i * LSSOURCE_i * ijunsti_s;
+                    ijdbot       =  MULT_i * ABDRAIN_i * ijunbot_d;
+                    ijdgat       =  MULT_i * LGDRAIN_i * ijungat_d;
+                    ijdsti       =  MULT_i * LSDRAIN_i * ijunsti_d;
+                    idsatsbot    =  MULT_i * ABSOURCE_i * idsatbot;
+                    idsatssti    =  MULT_i * LSSOURCE_i * idsatsti;
+                    idsatsgat    =  MULT_i * LGSOURCE_i * idsatgat;
+                    idsatsbotd   =  MULT_i * ABDRAIN_i * idsatbot_d;
+                    idsatsstid   =  MULT_i * LSDRAIN_i * idsatsti_d;
+                    idsatsgatd   =  MULT_i * LGDRAIN_i * idsatgat_d;
+                end
+                ijs          =  MULT_i * ijun_s;
+                ijd          =  MULT_i * ijun_d;
+                vds          =  Vds;
+                vgs          =  Vgs;
+                vsb          =  Vsb;
+                vto          =  VFB_T + P_D * facvsb0 + Gf_dc * sqrt(phit1 * facvsb0);
+                vts          =  vts_i;
+                vth          =  vth_i;
+                vgt          =  vgs - vth;
+                vdss         =  Vdsat_dc;
+                vsat         =  Vds - vdss;
+                ids_i        =  Ids + Idsedge + Iimpact + Igidl - Igcd - Igdov - ijun_d; // Total drain-current
+                `ifdef OPderiv
+                    gm           =  CHNL_TYPE * MULT_i * ddx(ids_i, V(GP));
+                    gmb          =  CHNL_TYPE * MULT_i * ddx(ids_i, V(BP));
+                    gds          =  CHNL_TYPE * MULT_i * ddx(ids_i, V(DI));
+                    gjs          = -MULT_i * ddx(ijun_s, V(SI));
+                    gjd          = -MULT_i * ddx(ijun_d, V(DI));
+                    cdd          =  CHNL_TYPE * MULT_i * ddx(Qd, V(DI));
+                    cdg          = -CHNL_TYPE * MULT_i * ddx(Qd, V(GP));
+                    cdb          = -CHNL_TYPE * MULT_i * ddx(Qd, V(BP));
+                    cds          =  cdd - cdg - cdb;
+                    cgd          = -CHNL_TYPE * MULT_i * ddx(Qg, V(DI));
+                    cgg          =  CHNL_TYPE * MULT_i * ddx(Qg, V(GP));
+                    cgb          = -CHNL_TYPE * MULT_i * ddx(Qg, V(BP));
+                    cgs          =  cgg - cgd - cgb;
+                    csd          = -CHNL_TYPE * MULT_i * ddx(Qs, V(DI));
+                    csg          = -CHNL_TYPE * MULT_i * ddx(Qs, V(GP));
+                    csb          = -CHNL_TYPE * MULT_i * ddx(Qs, V(BP));
+                    css          =  csg + csd + csb;
+                    cbd          = -CHNL_TYPE * MULT_i * ddx(Qb, V(DI));
+                    cbg          = -CHNL_TYPE * MULT_i * ddx(Qb, V(GP));
+                    cbb          =  CHNL_TYPE * MULT_i * ddx(Qb, V(BP));
+                    cbs          =  cbb - cbd - cbg;
+                    cgsol        =  CHNL_TYPE * MULT_i * ddx(Qfgs, V(GP));
+                    cgdol        =  CHNL_TYPE * MULT_i * ddx(Qfgd, V(GP));
+                    cjsbot       = -MULT_i * CHNL_TYPE * ABSOURCE_i * ddx(qjunbot_s, V(SI));
+                    cjsgat       = -MULT_i * CHNL_TYPE * LGSOURCE_i * ddx(qjungat_s, V(SI));
+                    cjssti       = -MULT_i * CHNL_TYPE * LSSOURCE_i * ddx(qjunsti_s, V(SI));
+                    cjs          =  cjsbot + cjsgat + cjssti;
+                    cjdbot       = -MULT_i * CHNL_TYPE * ABDRAIN_i * ddx(qjunbot_d, V(DI));
+                    cjdgat       = -MULT_i * CHNL_TYPE * LGDRAIN_i * ddx(qjungat_d, V(DI));
+                    cjdsti       = -MULT_i * CHNL_TYPE * LSDRAIN_i * ddx(qjunsti_d, V(DI));
+                    cjd          =  cjdbot + cjdgat + cjdsti;
+                `endif // OPderiv
+            end
+            weff         =  WE;
+            leff         =  LE;
+            `ifdef OPderiv
+                if (abs(gds) < 1.0e-18) begin
+                    u            =  0.0;
+                    rout         =  0.0;
+                    vearly       =  0.0;
+                end else begin
+                    u            =  gm / gds;
+                    rout         =  1.0 / gds;
+                    vearly       =  ide / gds;
+                end
+                if (abs(vgt) < 1.0e-12) begin
+                    beff         =  0.0;
+                end else begin
+                    beff         =  2.0 * abs(ide) / (vgt * vgt);
+                end
+                if (abs(cgg + cgsol + cgdol) < 1.0e-30) begin
+                    fug          =  0.0;
+                end else begin
+                    fug          =  gm / (2.0 * `PI * (cgg + cgsol + cgdol));
+                end
+                rg           =  RG_i / MULT_i;
+                sfl          =  MULT_i * Sfl;
+                if (abs(gm) < 1.0e-18) begin
+                    sqrtsff      =  0.0;
+                    sqrtsfw      =  0.0;
+                end else begin
+                    sqrtsff      =  sqrt(MULT_i * Sfl / 1000.0) / gm;
+                    sqrtsfw      =  sqrt(MULT_i) * sqid / gm;
+                end
+                sid          =  MULT_i * sqid * sqid;
+                sig          =  MULT_i * nt * sig1k / (1.0 + sig1k * mig);
+                cigid        =  c_igid;
+                if (sid == 0.0) begin
+                    fknee        =  0.0;
+                end else begin
+                    fknee        =  sfl / sid;
+                end
+                siavl        =  MULT_i * shot_iavl;
+                if (sigVds < 0.0) begin
+                    sigs         =  MULT_i * (shot_igcsx + shot_igdov);
+                    sigd         =  MULT_i * (shot_igcdx + shot_igsov);
+                    ssi          =  MULT_i * jnoisex_d;
+                    sdi          =  MULT_i * jnoisex_s;
+                end else begin
+                    sigs         =  MULT_i * (shot_igcsx + shot_igsov);
+                    sigd         =  MULT_i * (shot_igcdx + shot_igdov);
+                    ssi          =  MULT_i * jnoisex_s;
+                    sdi          =  MULT_i * jnoisex_d;
+                end
+                sfledge      =  MULT_i * Sfledge;
+                sidedge      =  MULT_i * sqidedge;
+            `endif // OPderiv
+
+            lp_vfb       =  VFB_T;
+            lp_stvfb     =  STVFB_i;
+            lp_st2vfb    =  ST2VFB_i;
+            lp_tox       =  TOX_i;
+            lp_epsrox    =  EPSROX_i;
+            lp_neff      =  NEFF_i;
+            lp_facneffac =  FACNEFFAC_i;
+            lp_gfacnud   =  GFACNUD_i;
+            lp_vsbnud    =  VSBNUD_i;
+            lp_dvsbnud   =  DVSBNUD_i;
+            lp_vnsub     =  VNSUB_i;
+            lp_nslp      =  NSLP_i;
+            lp_dnsub     =  DNSUB_i;
+            lp_dphib     =  DPHIB_i;
+            lp_delvtac   =  DELVTAC_i;
+            lp_np        =  NP_i;
+            lp_toxov     =  TOXOV_i;
+            lp_toxovd    =  TOXOVD_i;
+            lp_nov       =  NOV_i;
+            lp_novd      =  NOVD_i;
+            lp_ct        =  CT_T;
+            lp_ctg       =  CTG_T;
+            lp_ctb       =  CTB_i;
+            lp_stct      =  STCT_i;
+            lp_cf        =  CF_i;
+            lp_cfd       =  CFD_i;
+            lp_cfb       =  CFB_i;
+            lp_psce      =  PSCE_i;
+            lp_psceb     =  PSCEB_i;
+            lp_psced     =  PSCED_i;
+            lp_betn      =  BETN_T;
+            lp_stbet     =  STBET_i;
+            lp_mue       =  MUE_T;
+            lp_stmue     =  STMUE_i;
+            lp_themu     =  THEMU_T;
+            lp_stthemu   =  STTHEMU_i;
+            lp_cs        =  CS_T;
+            lp_stcs      =  STCS_i;
+            lp_thecs     =  THECS_T;
+            lp_stthecs   =  STTHECS_i;
+            lp_xcor      =  XCOR_T;
+            lp_stxcor    =  STXCOR_i;
+            lp_feta      =  FETA_i;
+            lp_rs        =  RS_T;
+            lp_strs      =  STRS_i;
+            lp_rsb       =  RSB_i;
+            lp_rsg       =  RSG_i;
+            lp_thesat    =  THESAT_T;
+            lp_stthesat  =  STTHESAT_i;
+            lp_thesatb   =  THESATB_i;
+            lp_thesatg   =  THESATG_i;
+            lp_ax        =  AX_i;
+            lp_alp       =  ALP_i;
+            lp_alp1      =  ALP1_i;
+            lp_alp2      =  ALP2_i;
+            lp_vp        =  VP_i;
+            lp_a1        =  A1_i;
+            lp_a2        =  A2_T;
+            lp_sta2      =  STA2_i;
+            lp_a3        =  A3_i;
+            lp_a4        =  A4_i;
+            lp_gco       =  GCO_i;
+            lp_iginv     =  IGINV_i;
+            lp_igov      =  IGOV_i;
+            lp_igovd     =  IGOVD_i;
+            lp_stig      =  STIG_i;
+            lp_gc2       =  GC2_i;
+            lp_gc3       =  GC3_i;
+            lp_chib      =  CHIB_i;
+            lp_agidl     =  AGIDL_i;
+            lp_agidld    =  AGIDLD_i;
+            lp_bgidl     =  BGIDL_T;
+            lp_bgidld    =  BGIDLD_T;
+            lp_stbgidl   =  STBGIDL_i;
+            lp_stbgidld  =  STBGIDLD_i;
+            lp_cgidl     =  CGIDL_i;
+            lp_cgidld    =  CGIDLD_i;
+            lp_cox       =  COX_i;
+            lp_cgov      =  CGOV_i;
+            lp_cgovd     =  CGOVD_i;
+            lp_cgbov     =  CGBOV_i;
+            lp_cfr       =  CFR_i;
+            lp_cfrd      =  CFRD_i;
+            lp_fnt       =  FNT_i;
+            lp_fntexc    =  FNTEXC_i;
+            lp_nfa       =  NFA_i;
+            lp_nfb       =  NFB_i;
+            lp_nfc       =  NFC_i;
+            lp_ef        =  EF_i;
+            lp_vfbedge   =  VFBEDGE_T;
+            lp_stvfbedge =  STVFBEDGE_i;
+            lp_dphibedge =  DPHIBEDGE_i;
+            lp_neffedge  =  NEFFEDGE_i;
+            lp_ctedge    =  CTEDGE_i;
+            lp_betnedge  =  BETNEDGE_T;
+            lp_stbetedge =  STBETEDGE_i;
+            lp_psceedge  =  PSCEEDGE_i;
+            lp_pscebedge =  PSCEBEDGE_i;
+            lp_pscededge =  PSCEDEDGE_i;
+            lp_cfedge    =  CFEDGE_i;
+            lp_cfdedge   =  CFDEDGE_i;
+            lp_cfbedge   =  CFBEDGE_i;
+            lp_fntedge   =  FNTEDGE_i;
+            lp_nfaedge   =  NFAEDGE_i;
+            lp_nfbedge   =  NFBEDGE_i;
+            lp_nfcedge   =  NFCEDGE_i;
+            lp_efedge    =  EFEDGE_i;
+            lp_rg        =  RG_i;
+            lp_rse       =  RSE_i;
+            lp_rde       =  RDE_i;
+            lp_rbulk     =  RBULK_i;
+            lp_rwell     =  RWELL_i;
+            lp_rjuns     =  RJUNS_i;
+            lp_rjund     =  RJUND_i;
+            `ifdef SelfHeating
+                lp_rth       =  RTH_i;
+                lp_cth       =  CTH_i;
+                lp_strth     =  STRTH_i;
+                pdiss        =  MULT_i * Pdiss;
+                dtsh         =  TKD - TKA;
+            `endif // SelfHeating
+            tk           =  TKD;
+            cjosbot      =  MULT_i * ABSOURCE_i * cjobot;
+            cjossti      =  MULT_i * LSSOURCE_i * cjosti;
+            cjosgat      =  MULT_i * LGSOURCE_i * cjogat;
+            vbisbot      =  vbibot;
+            vbissti      =  vbisti;
+            vbisgat      =  vbigat;
+            cjosbotd     =  MULT_i * ABDRAIN_i * cjobot_d;
+            cjosstid     =  MULT_i * LSDRAIN_i * cjosti_d;
+            cjosgatd     =  MULT_i * LGDRAIN_i * cjogat_d;
+            vbisbotd     =  vbibot_d;
+            vbisstid     =  vbisti_d;
+            vbisgatd     =  vbigat_d;
+            `ifdef NQSmodel
+                lp_munqs     =  MUNQS_i;
+            `endif // NQSmodel
+
+        end // OPinfo
+
+    end // evaluateblock
+
+end // analogBlock
diff --git a/ihp-sg13g2/libs.tech/xyce/adms/PSP103_nqs_macrodefs.include b/ihp-sg13g2/libs.tech/xyce/adms/PSP103_nqs_macrodefs.include
new file mode 100644
index 00000000..7bd812e7
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/adms/PSP103_nqs_macrodefs.include
@@ -0,0 +1,125 @@
+//======================================================================================
+//======================================================================================
+// Filename: PSP103_nqs_macrodefs.include
+//======================================================================================
+//======================================================================================
+//
+//  (c) Copyright notice
+//
+//  Copyright 2004-2017 NXP Semiconductors, 2015-2017 Commissariat a l’energie atomique
+//  et aux energies alternatives (CEA), 2012-2015 Delft University of Technology and 
+//  2004-2011 Arizona State University Licensed under the Educational Community License,
+//  Version 2.0 (the "License"); you may not use this file except in compliance with the
+//  License. You may obtain a copy of the License at
+//  http://opensource.org/licenses/ECL-2.0
+//  Unless required by applicable law or agreed to in writing, software distributed under
+//  the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF
+//  ANY KIND, either express or implied. See the License for the specific language
+//  governing permissions and limitations under the License.
+//
+//
+//  Version: 103.6.0 (PSP), 200.5.0 (JUNCAP), December 2017
+//
+//======================================================================================
+//======================================================================================
+//
+// Further information can be found in the file releasenotesPSP103.txt
+//
+
+//////////////////////////////////////////
+//
+// Macros used in PSP-NQS
+//
+//////////////////////////////////////////
+
+// Function to calculate bulk charge from surface potential
+`define PhiToQb(phi,Qb_tmp) \
+if (abs(phi) <= margin_ac) \
+        Qb_tmp     = -0.70710678 * phi * Gf_ac * (1.0 - `oneSixth * phi * (1.0 - `oneSixth * phi)); \
+else begin \
+        `expl((-phi), temp) \
+        Qb_tmp     =  Gf_ac * sqrt(temp + phi - 1.0); \
+        if (phi > margin_ac) \
+                Qb_tmp     = -Qb_tmp; \
+end
+
+// Function used in fq-macro
+`define PhiTod2Qis(xphi,d2Qis) \
+if (abs(xphi) <= margin_ac) begin \
+        Qb_tmp     = -0.70710678 * xphi * Gf_ac * (1.0 - `oneSixth * xphi * (1.0 - `oneSixth * xphi)); \
+        dQbs       = -0.70710678 * Gf_ac * (1.0 - `oneThird * xphi * (1.0 - 0.25 * xphi)); \
+        d2Qis      = -0.235702 * Gf_ac * (1.0 - 0.5 * xphi); \
+end else begin \
+        `expl((-xphi),temp) \
+        Qb_tmp     =  Gf_ac * sqrt(temp + xphi - 1.0); \
+        if (xphi > margin_ac) \
+                Qb_tmp     = -Qb_tmp; \
+        dQbs       =  0.5 * Gf_ac * Gf_ac * (1.0 - temp) / Qb_tmp; \
+        d2Qis      = (dQbs * dQbs - 0.5 * Gf_ac * Gf_ac) / Qb_tmp + dQbs; \
+end
+
+
+// Function used in QiToPhi
+`define sps(sp, xg) \
+if (abs(xg) <= marginp) begin \
+        sp         = xg / a_factrp; \
+end else begin \
+        if (xg < -marginp) begin \
+                NQS_yg     =  -xg; \
+                NQS_z      =  1.25 * NQS_yg / a_factrp; \
+                NQS_eta    =  (NQS_z + 10.0 - sqrt((NQS_z - 6.0) * (NQS_z - 6.0) + 64.0)) * 0.5; \
+                NQS_a      =  (NQS_yg - NQS_eta) * (NQS_yg - NQS_eta) + Gp2 * (NQS_eta + 1.0); \
+                NQS_c      =  2.0 * (NQS_yg - NQS_eta) - Gp2; \
+                NQS_tau    =  ln(NQS_a / Gp2) - NQS_eta; \
+                `sigma(NQS_a, NQS_c, NQS_tau, NQS_eta, NQS_y0) \
+                `expl(NQS_y0, NQS_D0) \
+                NQS_xi     =  1.0 - Gp2 * NQS_D0 * 0.5;  \
+                NQS_p      =  2.0 * (NQS_yg - NQS_y0) + Gp2 * (NQS_D0 - 1.0); \
+                NQS_q      =  (NQS_yg - NQS_y0) * (NQS_yg - NQS_y0) + Gp2 * (NQS_y0 + 1.0 - NQS_D0); \
+                NQS_temp   =  NQS_p * NQS_p - 4.0 * NQS_xi * NQS_q; \
+                NQS_w      =  2.0 * NQS_q / (NQS_p + sqrt(NQS_temp)); \
+                sp         =  -(NQS_y0 + NQS_w); \
+        end else begin \
+                NQS_xg1    =  1.0 / ( 1.25 + 7.32464877560822e-01 * Gp); \
+                NQS_A_fac  =  (1.25 * a_factrp * NQS_xg1 - 1.0) * NQS_xg1; \
+                NQS_xbar   =  xg / a_factrp * (1.0 + NQS_A_fac * xg); \
+                `expl(-NQS_xbar, NQS_temp)   \
+                NQS_w      =  1.0 - NQS_temp; \
+                NQS_x0     =  xg + Gp2 * 0.5 - Gp * sqrt(xg + Gp2 * 0.25 - NQS_w); \
+                `expl((-NQS_x0), NQS_D0) \
+                NQS_xi     =  1.0 - Gp2 * 0.5 * NQS_D0; \
+                NQS_p      =  2.0 * (xg - NQS_x0) + Gp2 * (1.0 - NQS_D0); \
+                NQS_q      =  (xg - NQS_x0) * (xg - NQS_x0) - Gp2 * (NQS_x0 - 1.0 + NQS_D0); \
+                NQS_temp   =  NQS_p * NQS_p - 4.0 * NQS_xi * NQS_q; \
+                NQS_u      =  2.0 * NQS_q / (NQS_p + sqrt(NQS_temp)); \
+                sp         =  NQS_x0 + NQS_u; \
+        end \
+end
+
+
+// Function to calculate surface potential from inversion charge
+`define QiToPhi(Qi,xg,xphi) \
+        temp       =  Qi / pd + xg; \
+        `sps(xphi,temp)
+
+// Calculation of fk
+`define fq(Qi,xg,dQy,d2Qy,fk) \
+        `QiToPhi(Qi, xg, xphi) \
+        `PhiTod2Qis(xphi, d2Qis) \
+        dQis       =  pd - dQbs; \
+        dQis_1     =  1.0 / dQis; \
+        fQi        =  Qi * dQis_1 - 1.0; \
+        dfQi       =  (1.0 - Qi * d2Qis * dQis_1 * dQis_1) * dQis_1; \
+        fk0        =  dfQi * dQy * dQy + fQi * d2Qy; \
+        dpsy2      =  dQy * dQy * dQis_1 * dQis_1; \
+        zsat_nqs   =  thesat2 * dpsy2; \
+        if (CHNL_TYPE == `PMOS) \
+                zsat_nqs   =  zsat_nqs / (1.0 + thesat1_ac * dps_ac); \
+        temp       =  sqrt(1.0 + 2.0 * zsat_nqs); \
+        Fvsat      =  2.0 / (1.0 + temp); \
+        temp1      =  d2Qy - dpsy2 * d2Qis; \
+        fk         =  Fvsat * (fk0 - zsat_nqs * fQi * temp1 * Fvsat / temp);
+
+// Interpolation of surface potential along channel
+`define Phiy(y) \
+        x_m_ac + H_ac * (1.0 - sqrt(1.0 - 2.0 * dps_ac / H_ac * ((y) - ym))) * inv_phit1
diff --git a/ihp-sg13g2/libs.tech/xyce/adms/README.md b/ihp-sg13g2/libs.tech/xyce/adms/README.md
new file mode 100644
index 00000000..1fc48f77
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/adms/README.md
@@ -0,0 +1,8 @@
+# Compilation and installation of the psp_103 model for XYCE
+
+
+```
+buildxyceplugin psp103.va .
+cp Xyce_Plugin_PSP103_VA.so ../xschem/simulations/
+mv Xyce_Plugin_PSP103_VA.so ../xschem/examples/
+```
diff --git a/ihp-sg13g2/libs.tech/xyce/adms/juncap200.va b/ihp-sg13g2/libs.tech/xyce/adms/juncap200.va
new file mode 100644
index 00000000..ab97cb62
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/adms/juncap200.va
@@ -0,0 +1,343 @@
+//======================================================================================
+//======================================================================================
+// Filename: juncap200.va
+//======================================================================================
+//======================================================================================
+//
+//  (c) Copyright notice
+//
+//  Copyright 2004-2017 NXP Semiconductors, 2015-2017 Commissariat a l’energie atomique
+//  et aux energies alternatives (CEA) and 2012-2015 Delft University of Technology
+//  Licensed under the Educational Community License, Version 2.0 (the "License"); you
+//  may not use this file except in compliance with the License. You may obtain a copy
+//  of the License at
+//  http://opensource.org/licenses/ECL-2.0
+//  Unless required by applicable law or agreed to in writing, software distributed under
+//  the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF
+//  ANY KIND, either express or implied. See the License for the specific language
+//  governing permissions and limitations under the License.
+//
+//
+//  Version: 200.5.0, August 2016
+//
+//======================================================================================
+//======================================================================================
+//
+// Further information can be found in the file releasenotesPSP103.txt
+//
+
+`include "discipline.h"
+
+`include "Common103_macrodefs.include"
+
+`include "JUNCAP200_macrodefs.include"
+
+`define JUNCAP_StandAlone
+
+// Note: some verilog-A compilers have problems handling the ddx-operator,
+// which occurs in definition of OP-output variables. If the line below is
+// commented out, all OP-output variables using the ddx-operator are skipped.
+`define OPderiv
+
+/////////////////////////////////////////////////////////////////////////////
+//
+//  Start of JUNCAP2 model code
+//
+/////////////////////////////////////////////////////////////////////////////
+
+module JUNCAP200(A,K);
+
+    //  --------------------------------------------------------------------------------------------------------------
+    //  Node definitions
+    //  --------------------------------------------------------------------------------------------------------------
+    inout       A,K;
+    electrical  A,K;
+
+    //  --------------------------------------------------------------------------------------------------------------
+    //  Special model parameters and switch parameters
+    //  --------------------------------------------------------------------------------------------------------------
+    `MPInb(LEVEL          ,200        ,""                                     ,"Model level must be 200")
+    `MPIty(TYPE           ,1.0        ,""                                     ,"Type parameter, in output value 1 reflects n-type, -1 reflects p-type")
+`ifdef __XYCE__
+    `MPRnb_BOTH(DTA            ,0.0        ,"K"                                    ,"Temperature offset with respect to ambient temperature")
+`else
+    `IPRnb(DTA            ,0.0        ,"K"                                    ,"Temperature offset with respect to ambient temperature")
+`endif
+
+    //  --------------------------------------------------------------------------------------------------------------
+    //  Instance parameters
+    //  --------------------------------------------------------------------------------------------------------------
+    `IPRco(AB             ,1.0e-12    ,"m^2"      ,`AB_cliplow   ,inf         ,"Junction area")
+    `IPRco(LS             ,1.0e-6     ,"m^2"      ,`LS_cliplow   ,inf         ,"STI-edge part of junction perimeter")
+    `IPRco(LG             ,1.0e-6     ,"m^2"      ,`LG_cliplow   ,inf         ,"Gate-edge part of junction perimeter")
+    `IPRco(MULT           ,1.0        ,""         ,`MULT_cliplow ,inf         ,"Number of devices in parallel")
+
+    //  --------------------------------------------------------------------------------------------------------------
+    //  JUNCAP2 model parameters
+    //  --------------------------------------------------------------------------------------------------------------
+    `include "JUNCAP200_parlist.include"
+
+    //  --------------------------------------------------------------------------------------------------------------
+    //  Variables
+    //  --------------------------------------------------------------------------------------------------------------
+    real MULT_i;
+    real EPSSI;
+    `include "JUNCAP200_varlist1.include"
+    `include "JUNCAP200_varlist2.include"
+
+    //  --------------------------------------------------------------------------------------------------------------
+    //  Variables for operating point info
+    //  --------------------------------------------------------------------------------------------------------------
+
+    `OPP(vak               ,"V"            ,"Voltage between anode and cathode")
+    `ifdef OPderiv
+        `OPP(cj                ,"F"            ,"Total source junction capacitance")
+        `OPP(cjbot             ,"F"            ,"Junction capacitance (bottom component)")
+        `OPP(cjgat             ,"F"            ,"Junction capacitance (gate-edge component)")
+        `OPP(cjsti             ,"F"            ,"Junction capacitance (STI-edge component)")
+    `endif // OPderiv
+    `OPP(ij                ,"A"            ,"Total source junction current")
+    `OPP(ijbot             ,"A"            ,"Junction current (bottom component)")
+    `OPP(ijgat             ,"A"            ,"Junction current (gate-edge component)")
+    `OPP(ijsti             ,"A"            ,"Junction current (STI-edge component)")
+    `OPP(si                ,"A^2/Hz"       ,"Total junction current noise spectral density")
+
+    // local parameters after scaling, T-scaling, and clipping
+    `OPP(idsatsbot         ,"A"            ,"Total bottom saturation current")
+    `OPP(idsatssti         ,"A"            ,"Total STI-edge saturation current")
+    `OPP(idsatsgat         ,"A"            ,"Total gate-edge saturation current")
+    `OPP(cjosbot           ,"F"            ,"Total bottom capacity")
+    `OPP(cjossti           ,"F"            ,"Total STI-edge capacity")
+    `OPP(cjosgat           ,"F"            ,"Total gate-edge capacity")
+    `OPP(vbisbot           ,"V"            ,"built-in voltage of the bottom junction")
+    `OPP(vbissti           ,"V"            ,"built-in voltage of the STI-edge junction")
+    `OPP(vbisgat           ,"V"            ,"built-in voltage of the gate-edge junction")
+
+    //  --------------------------------------------------------------------------------------------------------------
+    //  Analog block with all calculations and contribs
+    //  --------------------------------------------------------------------------------------------------------------
+
+    analog begin
+
+        //  --------------------------------------------------------------------------------------------------------------
+        //  Definition of bias/instance independent model variables
+        //  --------------------------------------------------------------------------------------------------------------
+        begin : initial_model
+
+            EPSSI        = `EPSO * `EPSRSI;
+            `include "JUNCAP200_InitModel.include"
+
+        end // initial_model
+
+        //  --------------------------------------------------------------------------------------------------------------
+        //  Definition of instance dependent and bias independent variables
+        //  --------------------------------------------------------------------------------------------------------------
+        begin : initial_instance
+
+            // Clipping of the local model parameters
+
+            AB_i         = `CLIP_LOW(AB, `AB_cliplow);
+            LS_i         = `CLIP_LOW(LS, `LS_cliplow);
+            LG_i         = `CLIP_LOW(LG, `LG_cliplow);
+            MULT_i       = `CLIP_LOW(MULT, `MULT_cliplow);
+
+            exp_VMAX_over_phitd = 0.0;
+            `JuncapInitInstance(AB_i, LS_i, LG_i, idsatbot, idsatsti, idsatgat, vbibot, vbisti, vbigat, PBOT_i, PSTI_i, PGAT_i, VBIRBOT_i, VBIRSTI_i, VBIRGAT_i, VMAX, exp_VMAX_over_phitd, vbimin, vch, vfmin, vbbtlim)
+
+            // Initialization of (global) variables; required for some verilog-A compilers
+            ISATFOR1     =  0.0;
+            MFOR1        =  1.0;
+            MFOR2        =  1.0;
+            ISATFOR2     =  0.0;
+            MREV         =  1.0;
+            ISATREV      =  0.0;
+            m0flag       =  0.0;
+            xhighf1      =  0.0;
+            expxhf1      =  0.0;
+            xhighf2      =  0.0;
+            expxhf2      =  0.0;
+            xhighr       =  0.0;
+            expxhr       =  0.0;
+
+            m0_rev       =  0.0;
+            mcor_rev     =  0.0;
+            I1_cor       =  0.0;
+            I2_cor       =  0.0;
+            I3_cor       =  0.0;
+            I4_cor       =  0.0;
+            I5_cor       =  0.0;
+            tt0          =  0.0;
+            tt1          =  0.0;
+            tt2          =  0.0;
+            zfrac        =  0.0;
+            zflagbot     =  1.0;
+            zflagsti     =  1.0;
+            zflaggat     =  1.0;
+            alphaje      =  0.0;
+
+            if (SWJUNEXP_i == 1.0) begin : JUNCAPexpressInit
+                // Note: the variables in the macro below are (re-)declared locally, to keep them separated from their globally declared counterparts.
+                // This trick allows one to use the "juncapcommon" macro both in the JUNCAP-express initialization and in the full-JUNCAP evalutation,
+                // while in the former the verilog-A compiler will still consider the variables as voltage-INdependent. This is essential to avoid
+                // recomputation of the JUNCAP-express initialization at each bias-step.
+
+                `LocalGlobalVars
+                // results computed here are not used elsewhere
+                real ijunbot, ijunsti, ijungat, qjunbot, qjunsti, qjungat;
+
+                // Initialization of (local) variables; required for some verilog-A compilers
+                ysq         =  0.0;
+                terfc       =  0.0;
+                erfcpos     =  0.0;
+                h1          =  0.0;
+                h2          =  0.0;
+                h2d         =  0.0;
+                h3          =  0.0;
+                h4          =  0.0;
+                h5          =  0.0;
+                idmult      =  0.0;
+                vj          =  0.0;
+                z           =  0.0;
+                zinv        =  0.0;
+                two_psistar =  0.0;
+                vjlim       =  0.0;
+                vjsrh       =  0.0;
+                vbbt        =  0.0;
+                vav         =  0.0;
+                tmp         =  0.0;
+                id          =  0.0;
+                isrh        =  0.0;
+                vbi_minus_vjsrh = 0.0;
+                wsrhstep    =  0.0;
+                dwsrh       =  0.0;
+                wsrh        =  0.0;
+                wdep        =  0.0;
+                asrh        =  0.0;
+                itat        =  0.0;
+                btat        =  0.0;
+                twoatatoverthreebtat =  0.0;
+                umaxbeforelimiting =  0.0;
+                umax        =  0.0;
+                sqrtumax    =  0.0;
+                umaxpoweronepointfive =  0.0;
+                wgamma      =  0.0;
+                wtat        =  0.0;
+                ktat        =  0.0;
+                ltat        =  0.0;
+                mtat        =  0.0;
+                xerfc       =  0.0;
+                erfctimesexpmtat =  0.0;
+                gammamax    =  0.0;
+                ibbt        =  0.0;
+                Fmaxr       =  0.0;
+                fbreakdown  =  0.0;
+                qjunbot     =  0.0;
+                qjunsti     =  0.0;
+                qjungat     =  0.0;
+
+                // Computation of JUNCAP-express internal parameters
+                `JuncapExpressInit1(AB_i, LS_i, LG_i, VJUNREF_i, qprefbot, qpref2bot, vbiinvbot, one_minus_PBOT, idsatbot, CSRHBOT_i, CTATBOT_i, vbibot, wdepnulrbot, VBIRBOTinv, PBOT_i, ftdbot, btatpartbot, atatbot, one_over_one_minus_PBOT, CBBTBOT_i, VBIRBOT_i, wdepnulrinvbot, fbbtbot, VBRBOT_i, VBRinvbot, PBRBOT_i, fstopbot, slopebot, qprefsti, qpref2sti, vbiinvsti, one_minus_PSTI, idsatsti, CSRHSTI_i, CTATSTI_i, vbisti, wdepnulrsti, VBIRSTIinv, PSTI_i, ftdsti, btatpartsti, atatsti, one_over_one_minus_PSTI, CBBTSTI_i, VBIRSTI_i, wdepnulrinvsti, fbbtsti, VBRSTI_i, VBRinvsti, PBRSTI_i, fstopsti, slopesti, qprefgat, qpref2gat, vbiinvgat, one_minus_PGAT, idsatgat, CSRHGAT_i, CTATGAT_i, vbigat, wdepnulrgat, VBIRGATinv, PGAT_i, ftdgat, btatpartgat, atatgat, one_over_one_minus_PGAT, CBBTGAT_i, VBIRGAT_i, wdepnulrinvgat, fbbtgat, VBRGAT_i, VBRinvgat, PBRGAT_i, fstopgat, slopegat, VMAX, exp_VMAX_over_phitd, vbimin, vch, vfmin, vbbtlim)
+                `JuncapExpressInit2(AB_i, LS_i, LG_i, qprefbot, qpref2bot, vbiinvbot, one_minus_PBOT, idsatbot, CSRHBOT_i, CTATBOT_i, vbibot, wdepnulrbot, VBIRBOTinv, PBOT_i, ftdbot, btatpartbot, atatbot, one_over_one_minus_PBOT, CBBTBOT_i, VBIRBOT_i, wdepnulrinvbot, fbbtbot, VBRBOT_i, VBRinvbot, PBRBOT_i, fstopbot, slopebot, qprefsti, qpref2sti, vbiinvsti, one_minus_PSTI, idsatsti, CSRHSTI_i, CTATSTI_i, vbisti, wdepnulrsti, VBIRSTIinv, PSTI_i, ftdsti, btatpartsti, atatsti, one_over_one_minus_PSTI, CBBTSTI_i, VBIRSTI_i, wdepnulrinvsti, fbbtsti, VBRSTI_i, VBRinvsti, PBRSTI_i, fstopsti, slopesti, qprefgat, qpref2gat, vbiinvgat, one_minus_PGAT, idsatgat, CSRHGAT_i, CTATGAT_i, vbigat, wdepnulrgat, VBIRGATinv, PGAT_i, ftdgat, btatpartgat, atatgat, one_over_one_minus_PGAT, CBBTGAT_i, VBIRGAT_i, wdepnulrinvgat, fbbtgat, VBRGAT_i, VBRinvgat, PBRGAT_i, fstopgat, slopegat, VMAX, exp_VMAX_over_phitd, vbimin, vch, vfmin, vbbtlim)
+                `JuncapExpressInit3(AB_i, LS_i, LG_i, idsatbot, idsatsti, idsatgat, ISATFOR1, MFOR1, ISATFOR2, MFOR2, ISATREV, MREV, m0flag)
+                `JuncapExpressInit4(AB_i, LS_i, LG_i, FJUNQ_i, cjobot, cjosti, cjogat, zflagbot, zflagsti, zflaggat)
+                `JuncapExpressInit5(AB_i, LS_i, LG_i, ISATFOR1, ISATFOR2, ISATREV, xhighf1, expxhf1, xhighf2, expxhf2, xhighr, expxhr)
+
+            end // JUNCAPexpressInit
+
+        end // initial_instance
+
+        begin : evaluateblock
+
+            // Local variables
+            real ijunbot, qjunbot, ijunsti, qjunsti, ijungat, qjungat, ijun, qjun, jnoise, VAK;
+
+            // Variable initializing
+            ijun        =  0.0;
+            ijunbot     =  0.0;
+            ijunsti     =  0.0;
+            ijungat     =  0.0;
+
+            //  --------------------------------------------------------------------------------------------------------------
+            //  DC and AC bias dependent quantities (calculations for current and charge contributions)
+            //  --------------------------------------------------------------------------------------------------------------
+            begin : evaluateStaticDynamic
+
+                VAK         =  TYPE * V(A, K);
+                if (SWJUNEXP_i == 1.0) begin
+                    `JuncapExpressCurrent(VAK, MFOR1, ISATFOR1, MFOR2, ISATFOR2, MREV, ISATREV, m0flag, xhighf1, expxhf1, xhighf2, expxhf2, xhighr, expxhr, ijun)
+                    begin : evaluateDynamic
+                        real tmpv, vjv;
+                        `JuncapExpressCharge(VAK, AB_i, LS_i, LG_i, qprefbot, qprefsti, qprefgat, qpref2bot, qpref2sti, qpref2gat, vbiinvbot, vbiinvsti, vbiinvgat, one_minus_PBOT, one_minus_PSTI, one_minus_PGAT, vfmin, vch, zflagbot, zflagsti, zflaggat, qjunbot, qjunsti, qjungat)
+                    end
+                end else begin
+                    `juncapcommon(VAK, AB_i, LS_i, LG_i, qprefbot, qpref2bot, vbiinvbot, one_minus_PBOT, idsatbot, CSRHBOT_i, CTATBOT_i, vbibot, wdepnulrbot, VBIRBOTinv, PBOT_i, ftdbot, btatpartbot, atatbot, one_over_one_minus_PBOT, CBBTBOT_i, VBIRBOT_i, wdepnulrinvbot, fbbtbot, VBRBOT_i, VBRinvbot, PBRBOT_i, fstopbot, slopebot, qprefsti, qpref2sti, vbiinvsti, one_minus_PSTI, idsatsti, CSRHSTI_i, CTATSTI_i, vbisti, wdepnulrsti, VBIRSTIinv, PSTI_i, ftdsti, btatpartsti, atatsti, one_over_one_minus_PSTI, CBBTSTI_i, VBIRSTI_i, wdepnulrinvsti, fbbtsti, VBRSTI_i, VBRinvsti, PBRSTI_i, fstopsti, slopesti, qprefgat, qpref2gat, vbiinvgat, one_minus_PGAT, idsatgat, CSRHGAT_i, CTATGAT_i, vbigat, wdepnulrgat, VBIRGATinv, PGAT_i, ftdgat, btatpartgat, atatgat, one_over_one_minus_PGAT, CBBTGAT_i, VBIRGAT_i, wdepnulrinvgat, fbbtgat, VBRGAT_i, VBRinvgat, PBRGAT_i, fstopgat, slopegat, VMAX, exp_VMAX_over_phitd, vbimin, vch, vfmin, vbbtlim, ijunbot, qjunbot, ijunsti, qjunsti, ijungat, qjungat)
+                    ijun        =  AB_i * ijunbot + LS_i * ijunsti + LG_i * ijungat;
+                end
+                qjun        =  AB_i * qjunbot + LS_i * qjunsti + LG_i * qjungat;
+
+            end // evaluateStaticDynamic
+
+            //  --------------------------------------------------------------------------------------------------------------
+            //  Current contributions
+            //  --------------------------------------------------------------------------------------------------------------
+
+            begin : loadStatic
+                I(A, K)      <+  (TYPE * MULT_i) * ijun;
+            end // loadStatic
+
+            //  --------------------------------------------------------------------------------------------------------------
+            //  ddt() contribs from charges
+            //  --------------------------------------------------------------------------------------------------------------
+
+            begin : loadDynamic
+                I(A, K)      <+  ddt((TYPE * MULT_i) * qjun);
+            end // loadDynamic
+
+            //  --------------------------------------------------------------------------------------------------------------
+            //  Noise
+            //  --------------------------------------------------------------------------------------------------------------
+
+            begin : noise
+                jnoise      = (2 * `QELE) * abs(ijun);
+                I(A, K)      <+  white_noise(MULT_i * jnoise, "shot");
+            end // noise
+
+            //  --------------------------------------------------------------------------------------------------------------
+            //  Operating point info
+            //  --------------------------------------------------------------------------------------------------------------
+
+            begin : OPinfo
+                vak         =  VAK;
+                `ifdef OPderiv
+                    cjbot       =  TYPE * MULT_i * AB_i * ddx(qjunbot, V(A));
+                    cjgat       =  TYPE * MULT_i * LG_i * ddx(qjungat, V(A));
+                    cjsti       =  TYPE * MULT_i * LS_i * ddx(qjunsti, V(A));
+                    cj          =  cjbot + cjgat + cjsti;
+                `endif // OPderiv
+                if (SWJUNEXP_i == 1.0) begin
+                    ijbot       =  0.0;
+                    ijgat       =  0.0;
+                    ijsti       =  0.0;
+                    idsatsbot   =  0.0;
+                    idsatssti   =  0.0;
+                    idsatsgat   =  0.0;
+                end else begin
+                    ijbot       =  MULT_i * AB_i * ijunbot;
+                    ijgat       =  MULT_i * LG_i * ijungat;
+                    ijsti       =  MULT_i * LS_i * ijunsti;
+                    idsatsbot   =  MULT_i * AB_i * idsatbot;
+                    idsatssti   =  MULT_i * LS_i * idsatsti;
+                    idsatsgat   =  MULT_i * LG_i * idsatgat;
+                end
+                ij        = MULT_i * ijun;
+                si        = MULT_i * jnoise;
+                cjosbot   = MULT_i * AB_i * cjobot;
+                cjossti   = MULT_i * LS_i * cjosti;
+                cjosgat   = MULT_i * LG_i * cjogat;
+                vbisbot   = vbibot;
+                vbissti   = vbisti;
+                vbisgat   = vbigat;
+            end // OPinfo
+        end // evaluateblock
+    end // analogBlock
+endmodule
diff --git a/ihp-sg13g2/libs.tech/xyce/adms/psp103.va b/ihp-sg13g2/libs.tech/xyce/adms/psp103.va
new file mode 100644
index 00000000..ec72951a
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/adms/psp103.va
@@ -0,0 +1,52 @@
+//======================================================================================
+//======================================================================================
+// Filename: psp103.va
+//======================================================================================
+//======================================================================================
+//
+//  (c) Copyright notice
+//
+//  Copyright 2004-2017 NXP Semiconductors, 2015-2017 Commissariat a l’energie atomique
+//  et aux energies alternatives (CEA), 2012-2015 Delft University of Technology and
+//  2004-2011 Arizona State University Licensed under the Educational Community License,
+//  Version 2.0 (the "License"); you may not use this file except in compliance with the
+//  License. You may obtain a copy of the License at
+//  http://opensource.org/licenses/ECL-2.0
+//  Unless required by applicable law or agreed to in writing, software distributed under
+//  the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF
+//  ANY KIND, either express or implied. See the License for the specific language
+//  governing permissions and limitations under the License.
+//
+//
+//  Version: 103.6.0 (PSP), 200.5.0 (JUNCAP), December 2017
+//
+//======================================================================================
+//======================================================================================
+//
+// Further information can be found in the file releasenotesPSP103.txt
+//
+
+`include "discipline.h"
+
+`include "Common103_macrodefs.include"
+
+`include "JUNCAP200_macrodefs.include"
+
+`include "PSP103_macrodefs.include"
+
+// Note: some verilog-A compilers have problems handling the ddx-operator,
+// which occurs in definition of OP-output variables. If the line below is
+// commented out, all OP-output variables using the ddx-operator are skipped.
+`define OPderiv
+
+/////////////////////////////////////////////////////////////////////////////
+//
+//  PSP global model code
+//
+/////////////////////////////////////////////////////////////////////////////
+
+module PSP103_VA(D, G, S, B);
+
+`include "PSP103_module.include"
+
+endmodule
diff --git a/ihp-sg13g2/libs.tech/xyce/adms/psp103_nqs.va b/ihp-sg13g2/libs.tech/xyce/adms/psp103_nqs.va
new file mode 100644
index 00000000..ec7dd8d0
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/adms/psp103_nqs.va
@@ -0,0 +1,56 @@
+//======================================================================================
+//======================================================================================
+// Filename: psp103_nqs.va
+//======================================================================================
+//======================================================================================
+//
+//  (c) Copyright notice
+//
+//  Copyright 2004-2017 NXP Semiconductors, 2015-2017 Commissariat a l’energie atomique
+//  et aux energies alternatives (CEA), 2012-2015 Delft University of Technology and 
+//  2004-2011 Arizona State University Licensed under the Educational Community License,
+//  Version 2.0 (the "License"); you may not use this file except in compliance with the
+//  License. You may obtain a copy of the License at
+//  http://opensource.org/licenses/ECL-2.0
+//  Unless required by applicable law or agreed to in writing, software distributed under
+//  the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF
+//  ANY KIND, either express or implied. See the License for the specific language
+//  governing permissions and limitations under the License.
+//
+//
+//  Version: 103.6.0 (PSP), 200.5.0 (JUNCAP), December 2017
+//
+//======================================================================================
+//======================================================================================
+//
+// Further information can be found in the file releasenotesPSP103.txt
+//
+
+`include "discipline.h"
+
+`define NQSmodel true
+
+`include "Common103_macrodefs.include"
+
+`include "JUNCAP200_macrodefs.include"
+
+`include "PSP103_macrodefs.include"
+
+// Note: some verilog-A compilers have problems handling the ddx-operator,
+// which occurs in definition of OP-output variables. If the line below is
+// commented out, all OP-output variables using the ddx-operator are skipped.
+`define OPderiv
+
+/////////////////////////////////////////////////////////////////////////////
+//
+//  PSP global model code
+//
+/////////////////////////////////////////////////////////////////////////////
+
+`include "PSP103_nqs_macrodefs.include"
+
+module PSPNQS103VA(D, G, S, B);
+
+`include "PSP103_module.include"
+
+endmodule
diff --git a/ihp-sg13g2/libs.tech/xyce/adms/psp103t.va b/ihp-sg13g2/libs.tech/xyce/adms/psp103t.va
new file mode 100644
index 00000000..4526d86e
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/adms/psp103t.va
@@ -0,0 +1,54 @@
+//======================================================================================
+//======================================================================================
+// Filename: psp103t.va
+//======================================================================================
+//======================================================================================
+//
+//  (c) Copyright notice
+//
+//  Copyright 2004-2017 NXP Semiconductors, 2015-2017 Commissariat a l’energie atomique
+//  et aux energies alternatives (CEA), 2012-2015 Delft University of Technology and 
+//  2004-2011 Arizona State University Licensed under the Educational Community License,
+//  Version 2.0 (the "License"); you may not use this file except in compliance with the
+//  License. You may obtain a copy of the License at
+//  http://opensource.org/licenses/ECL-2.0
+//  Unless required by applicable law or agreed to in writing, software distributed under
+//  the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF
+//  ANY KIND, either express or implied. See the License for the specific language
+//  governing permissions and limitations under the License.
+//
+//
+//  Version: 103.6.0 (PSP), 200.5.0 (JUNCAP), December 2017
+//
+//======================================================================================
+//======================================================================================
+//
+// Further information can be found in the file releasenotesPSP103.txt
+//
+
+`include "discipline.h"
+
+`define SelfHeating true
+
+`include "Common103_macrodefs.include"
+
+`include "JUNCAP200_macrodefs.include"
+
+`include "PSP103_macrodefs.include"
+
+// Note: some verilog-A compilers have problems handling the ddx-operator,
+// which occurs in definition of OP-output variables. If the line below is
+// commented out, all OP-output variables using the ddx-operator are skipped.
+`define OPderiv
+
+/////////////////////////////////////////////////////////////////////////////
+//
+//  PSP global model code
+//
+/////////////////////////////////////////////////////////////////////////////
+
+module PSP103TVA(D, G, S, B, DT);
+
+`include "PSP103_module.include"
+
+endmodule
diff --git a/ihp-sg13g2/libs.tech/xyce/adms/releasenotesPSP103p6.txt b/ihp-sg13g2/libs.tech/xyce/adms/releasenotesPSP103p6.txt
new file mode 100644
index 00000000..7eb88a77
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/adms/releasenotesPSP103p6.txt
@@ -0,0 +1,151 @@
+
+======================================================================================
+======================================================================================
+                      Silicon Integration Initiative (Si2)
+                    Compact Model Coalition In-Code Statement
+
+  Copyright 2004-2017 NXP Semiconductors, 2015-2017 Commissariat a l’energie atomique
+  et aux energies alternatives (CEA), 2012-2015 Delft University of Technology and 
+  2004-2011 Arizona State University Licensed under the Educational Community License,
+  Version 2.0 (the "License"); you may not use this file except in compliance with the
+  License. You may obtain a copy of the License at
+  http://opensource.org/licenses/ECL-2.0
+  Unless required by applicable law or agreed to in writing, software distributed under
+  the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF
+  ANY KIND, either express or implied. See the License for the specific language
+  governing permissions and limitations under the License.
+  This work is licensed under the Creative Commons Attribution 4.0 International License.
+  To view a copy of this license, visit http://creativecommons.org/licenses/by/4.0/ or
+  send a letter to Creative Commons, PO Box 1866, Mountain View, CA 94042, USA.
+
+  CMC In-Code Statement Revision: 103.6.0 (PSP), 12/14/2017
+                                  200.5.0 (JUNCAP),09/09/2016
+
+======================================================================================
+======================================================================================
+
+  Authors: G.D.J. Smit, A.J. Scholten, and D.B.M. Klaassen (NXP Semiconductors)
+           O. Rozeau, S. Martinie, T. Poiroux, J.C. Barbé (CEA-Leti)
+
+  Former contributers:
+           G. Gildenblat, W. Yao, Z. Zhu, X. Li and W. Wu (Arizona State University)
+           R. van Langevelde (Philips Research)
+           R. van der Toorn (Delft University of Technology)
+
+  The most recent version of the model code, the documentation, and contact
+  information can be found on:
+
+       http://www.cea.fr/cea-tech/leti/pspsupport
+       
+======================================================================================
+======================================================================================
+
+This package consists of the following files:
+
+     - releasenotesPSP103.txt         This file
+
+     - psp103.va                      Main file for PSP model
+     - psp103t.va                     Main file for PSP model with self heating
+     - psp103_nqs.va                  Main file for PSP model with NQS-effects
+     - juncap200.va                   Main file for JUNCAP2 stand-alone model
+
+     - Common103_macrodefs.include    Common macro definitions
+     - PSP103_macrodefs.include       Macro definitions for PSP
+     - PSP103_module.include          Actual model code for intrinsic MOS model
+     - PSP103_SPCalculation.include   Surface potential and related calculations
+     - PSP103_binning.include         Geometry scaling equation for binning
+     - PSP103_binpars.include         Parameterlist for global PSP binning model
+     - PSP103_nqs_macrodefs.include   Macro definitions for PSP-NQS
+     - PSP103_InitNQS.include         PSP-NQS initialization code
+     - PSP103_ChargesNQS.include      Calculation of NQS-charge contributions
+     - JUNCAP200_macrodefs.include    Macro definitions for JUNCAP2 model
+     - JUNCAP200_parlist.include      JUNCAP2 parameter list
+     - JUNCAP200_varlist1.include     JUNCAP2 variable declarations
+     - JUNCAP200_varlist2.include     JUNCAP2 variable declarations
+     - JUNCAP200_InitModel.include    JUNCAP2 model initialization code
+
+======================================================================================
+======================================================================================
+
+Usage
+-----
+
+Depending which model one wants to use, one should compile one of the four .va-files
+(psp103.va, psp103t.va, psp103_nqs.va, and juncap200.va). The module names are
+"PSP103VA", "PSP103TVA", and "PSPNQS103VA" (for QS, self heating, and NQS,
+respectively), and "JUNCAP200" for the JUNCAP2-model.
+
+
+======================================================================================
+======================================================================================
+
+Release notes vA-code of PSP 103.6.0 (December 2017)
+---------------------------------------------------------
+
+Changes include 2 bug fixes, new modeling of interface states, new parameter for edge
+scaling rules and new clipping values of local parameters:
+    - Induced gate noise: clipped value of migid in line with c_igid
+    - Thermal noise of edge transistor: bug fix to avoid possible division by zero
+      during the calculation of redge.
+    - Improvement of gm/Id in weak inversion: new model of interface states.
+    - Addition of new parameter NSUBEDGELEXP: exponent for channel length dependence
+      of edge transistor substrate doping.
+    - Minimum values of calculated local parameters NOV and NOVD in global mode: now in
+      lines with minimum values of local model parameters.
+
+- PSP103_macrodefs.include:
+    - Calculation of phit0 is cancelled, temperature dependence of interface states is
+      now calculated using the variable CT_T: lines 356 to 359
+
+- PSP103_module.include:
+    - Addition of new local parameters related to the new model of interface states 
+      CTG, CTB and STCT: lines 181 to 185
+    - Addition of new global parameters related to the new model of interface states 
+      CTGO, CTBO and STCTO: lines 392 to 400
+    - Addition of new global parameter related to edge transistor doping NSUBEDGELEXP:
+      line 552
+    - Addition of new variable declarations CTG_p, CTB_p, STCT_p, CT_i, CTG_i, CTB_i,
+      STCT_i, CT_T, tf_ct, migid0: lines 732 to 777
+    - Cancelling of the variable declaration phit0. This variable is not used.
+    - New variable declarations for OP info related to interface states model: lines
+      908 to 910
+    - Calculation of CTG_p, CTB_p, STCT_p: lines 1238 to 1240 and lines 1379 to 1383
+    - Addition of an exponent parameter NSUBEDGELEXP in calculation of NEFFEDGE_p: 
+      line 1490
+    - Calculation of CTG_i, CTB_i and STCT_i: lines 1621 to 1623
+    - modification of min clipping values of NOV_i and NOVD_i, now in line with local
+      parameters: lines 1618 and 1619
+    - Addition of new variable declarations xgct, xsct0, xbct, xsbstar, xsct, dCTG,
+      and ct_fact in section evaluateblock: line 2045
+
+    - Modification of a condition: line 2750
+        "if (SWIGN_i == 1) begin" is replaced by
+        "if ((SWIGN_i == 1) && (nt > 0.0)) begin"
+    - Changing of variable: migid is replaced by migid0, lines 2754, 2758 and 2764
+    - New calculation of migid: "migid = c_igid * sqid / sqig;", line 2767
+    - New calculation of redge to avoid division by zero: lines 2814 to 2818
+    - Affectation of variables for OP info related to the new model of interface states
+      lp_ctg, lp_ctb, lp_stct: lines 3117 to 3119
+
+- PSP103_SPCalculation.include:
+    - Modification of calculation of phit1 and inv_phit1 including new model of
+      interface states: lines 74 to 91
+
+- PSP103_binpars.include:
+    - Addition of new binning parameters related to the new model of interface states
+      POCTG, POCTB and POSTCT: lines 84 to 91
+
+- PSP103_binning.include:
+    - Addition of local parameter calculation related to the new model of interface
+      states CTG_p, CTB_p, STCT_p: lines 73 to 77
+
+PSP 103.6.0 is backwards compatible with the previous version, PSP 103.5.0
+
+
+======================================================================================
+======================================================================================
+
+The authors want to thank Laurent Lemaitre and Colin McAndrew (Freescale)
+for their help with ADMS and the implementation of the model code. Geoffrey
+Coram (Analog Devices) is acknowledged for input concerning the Verilog-A
+implementation of the model.
diff --git a/ihp-sg13g2/libs.tech/xyce/examples/c7552_ann_psp.cir b/ihp-sg13g2/libs.tech/xyce/examples/c7552_ann_psp.cir
new file mode 100644
index 00000000..a8c1d70a
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/examples/c7552_ann_psp.cir
@@ -0,0 +1,89227 @@
+* ISCAS85 benchmark circuit SPICE netlist
+* generated by spicegen.pl 1.0
+* by Jingye Xu @ VLSI group, Dept of ECE, UIC
+
+* Path to the models
+.lib ../models/cornerMOSlv.lib mos_tt
+
+*.OPTIONS GMIN=1e-015 ABSTOL=1e-13 ACCT noopiter
+*.options vntol=10u
+
+**** the input ports: g110_0 g21_0 g18_1 g189_1 g172_2 g70_1 g103_0 g114_0 g92_1 g150_1 g198_1 g125_0 g30_0 g69_1 g45_0 g83_1 g157_0 g182_1 g82_0 g63_1 g42_1 g51_2 g99_1 g62_0 g169_2 g39_0 g128_1 g130_0 g78_1 g195_2 g38_1 g134_1 g191_2 g5_1 g176_1 g117_1 g35_1 g194_1 g41_0 g97_0 g147_1 g14_2 g137_0 g66_2 g26_1 g140_1 g154_1 g185_0 g48_0 g87_0 g106_1 g151_0 g158_0 g15_0 g7_1 g74_1 g122_0 g86_1 g56_1 g165_0 g34_0 g206_6 g57_1 g138_1 g168_0 g17_0 g27_1 g93_0 g199_0 g180_0 g202_0 g173_0 g22_1 g131_0 g192_1 g135_1 g4_1 g77_1 g111_1 g126_1 g52_2 g79_1 g81_1 g156_1 g64_1 g43_0 g183_1 g23_1 g13_2 g53_1 g90_0 g143_0 g153_1 g177_2 g98_0 g19_1 g118_1 g146_1 g102_1 g186_2 g6_4 g1_2 g28_0 g164_1 g33_0 g49_1 g123_0 g205_1 g105_0 g73_1 g170_1 g85_1 g44_0 g67_1 g204_1 g163_1 g159_0 g76_0 g94_0 g139_1 g193_2 g58_1 g100_0 g32_2 g50_0 g132_1 g174_0 g149_1 g12_2 g112_1 g101_0 g119_1 g24_1 g127_1 g201_2 g37_0 g9_2 g207_1 g120_1 g60_1 g108_1 g171_2 g72_2 g46_1 g3_1 g80_1 g59_1 g54_0 g10_1 g152_1 g115_0 g166_2 g95_0 g167_1 g178_2 g187_1 g142_1 g196_0 g113_1 g31_1 g124_1 g190_0 g175_2 g84_0 g133_0 g68_1 g203_2 g75_0 g162_0 g11_1 g144_1 g136_0 g129_1 g91_1 g161_1 g29_1 g155_0 g200_0 g89_1 g141_0 g20_1 g188_2 g104_1 g148_0 g61_1 g65_2 g2_0 g184_3 g109_0 g71_2 g40_0 g47_1 g107_0 g36_1 g121_1 g8_0 g88_0 g16_1 g160_0 g179_0 g96_0 g55_1 g181_3 g25_0 g197_2 g116_0 g145_1 ****
+**** the output ports: g7529_1 g7509_0 g7484_1 g7477_1 g7460_0 g7503_1 g7522_0 g7485_1 g7453_0 g7474_0 g7500_0 g7514_0 g7546_1 g7549_0 g7467_0 g7491_0 g7456_0 g7495_1 g7545_0 g7473_0 g7541_0 g7448_1 g7525_1 g7550_1 g165_1 g7510_1 g7535_1 g7534_1 g7469_1 g7476_0 g7517_1 g7537_0 g7489_1 g7521_1 g7486_0 g7533_1 g7449_0 g7447_0 g7528_0 g7513_1 g7548_0 g7544_1 g7552_0 g7540_1 g7507_0 g7481_0 g7455_0 g7502_1 g7446_1 g7478_1 g7470_0 g7526_0 g7494_1 g7452_1 g7463_0 g7532_1 g7512_0 g7527_0 g7451_0 g7472_0 g7498_1 g7475_0 g7536_0 g7488_1 g7493_1 g7551_1 g7482_0 g7487_1 g7501_1 g7520_1 g7516_1 g7450_1 g7508_0 g7458_1 g7479_1 g7506_1 g7499_0 g7471_0 g7465_1 g7464_1 g7543_1 g7524_0 g7539_1 g7468_1 g7459_0 g7504_1 g7515_1 g7492_1 g7511_0 g7462_1 g7530_0 g7497_1 g7454_1 g7519_1 g7531_0 g7547_0 g7483_1 g7466_1 g7480_1 g7523_1 g7496_0 g7538_0 g7490_1 g7518_1 g7461_0 g7542_0 g7457_0 g7505_1 ****
+
+* the voltage sources:
+Vdd vdd 0 DC 1.8
+
+* the input ports:
+V1 g110_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V2 g21_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V3 g18_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V4 g189_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V5 g172_2 0 pulse(0 1 0p 200p 100p 1n 2n)
+V6 g70_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V7 g103_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V8 g114_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V9 g92_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V10 g150_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V11 g198_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V12 g125_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V13 g30_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V14 g69_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V15 g45_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V16 g83_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V17 g157_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V18 g182_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V19 g82_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V20 g63_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V21 g42_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V22 g51_2 0 pulse(0 1 0p 200p 100p 1n 2n)
+V23 g99_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V24 g62_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V25 g169_2 0 pulse(0 1 0p 200p 100p 1n 2n)
+V26 g39_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V27 g128_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V28 g130_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V29 g78_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V30 g195_2 0 pulse(0 1 0p 200p 100p 1n 2n)
+V31 g38_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V32 g134_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V33 g191_2 0 pulse(0 1 0p 200p 100p 1n 2n)
+V34 g5_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V35 g176_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V36 g117_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V37 g35_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V38 g194_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V39 g41_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V40 g97_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V41 g147_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V42 g14_2 0 pulse(0 1 0p 200p 100p 1n 2n)
+V43 g137_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V44 g66_2 0 pulse(0 1 0p 200p 100p 1n 2n)
+V45 g26_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V46 g140_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V47 g154_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V48 g185_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V49 g48_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V50 g87_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V51 g106_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V52 g151_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V53 g158_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V54 g15_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V55 g7_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V56 g74_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V57 g122_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V58 g86_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V59 g56_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V60 g165_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V61 g34_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V62 g206_6 0 pulse(0 1 0p 200p 100p 1n 2n)
+V63 g57_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V64 g138_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V65 g168_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V66 g17_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V67 g27_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V68 g93_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V69 g199_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V70 g180_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V71 g202_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V72 g173_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V73 g22_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V74 g131_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V75 g192_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V76 g135_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V77 g4_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V78 g77_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V79 g111_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V80 g126_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V81 g52_2 0 pulse(0 1 0p 200p 100p 1n 2n)
+V82 g79_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V83 g81_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V84 g156_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V85 g64_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V86 g43_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V87 g183_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V88 g23_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V89 g13_2 0 pulse(0 1 0p 200p 100p 1n 2n)
+V90 g53_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V91 g90_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V92 g143_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V93 g153_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V94 g177_2 0 pulse(0 1 0p 200p 100p 1n 2n)
+V95 g98_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V96 g19_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V97 g118_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V98 g146_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V99 g102_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V100 g186_2 0 pulse(0 1 0p 200p 100p 1n 2n)
+V101 g6_4 0 pulse(0 1 0p 200p 100p 1n 2n)
+V102 g1_2 0 pulse(0 1 0p 200p 100p 1n 2n)
+V103 g28_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V104 g164_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V105 g33_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V106 g49_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V107 g123_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V108 g205_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V109 g105_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V110 g73_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V111 g170_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V112 g85_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V113 g44_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V114 g67_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V115 g204_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V116 g163_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V117 g159_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V118 g76_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V119 g94_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V120 g139_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V121 g193_2 0 pulse(0 1 0p 200p 100p 1n 2n)
+V122 g58_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V123 g100_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V124 g32_2 0 pulse(0 1 0p 200p 100p 1n 2n)
+V125 g50_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V126 g132_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V127 g174_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V128 g149_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V129 g12_2 0 pulse(0 1 0p 200p 100p 1n 2n)
+V130 g112_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V131 g101_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V132 g119_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V133 g24_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V134 g127_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V135 g201_2 0 pulse(0 1 0p 200p 100p 1n 2n)
+V136 g37_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V137 g9_2 0 pulse(0 1 0p 200p 100p 1n 2n)
+V138 g207_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V139 g120_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V140 g60_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V141 g108_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V142 g171_2 0 pulse(0 1 0p 200p 100p 1n 2n)
+V143 g72_2 0 pulse(0 1 0p 200p 100p 1n 2n)
+V144 g46_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V145 g3_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V146 g80_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V147 g59_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V148 g54_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V149 g10_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V150 g152_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V151 g115_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V152 g166_2 0 pulse(0 1 0p 200p 100p 1n 2n)
+V153 g95_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V154 g167_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V155 g178_2 0 pulse(0 1 0p 200p 100p 1n 2n)
+V156 g187_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V157 g142_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V158 g196_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V159 g113_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V160 g31_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V161 g124_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V162 g190_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V163 g175_2 0 pulse(0 1 0p 200p 100p 1n 2n)
+V164 g84_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V165 g133_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V166 g68_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V167 g203_2 0 pulse(0 1 0p 200p 100p 1n 2n)
+V168 g75_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V169 g162_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V170 g11_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V171 g144_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V172 g136_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V173 g129_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V174 g91_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V175 g161_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V176 g29_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V177 g155_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V178 g200_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V179 g89_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V180 g141_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V181 g20_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V182 g188_2 0 pulse(0 1 0p 200p 100p 1n 2n)
+V183 g104_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V184 g148_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V185 g61_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V186 g65_2 0 pulse(0 1 0p 200p 100p 1n 2n)
+V187 g2_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V188 g184_3 0 pulse(0 1 0p 200p 100p 1n 2n)
+V189 g109_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V190 g71_2 0 pulse(0 1 0p 200p 100p 1n 2n)
+V191 g40_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V192 g47_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V193 g107_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V194 g36_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V195 g121_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V196 g8_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V197 g88_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V198 g16_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V199 g160_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V200 g179_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V201 g96_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V202 g55_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+V203 g181_3 0 pulse(0 1 0p 200p 100p 1n 2n)
+V204 g25_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V205 g197_2 0 pulse(0 1 0p 200p 100p 1n 2n)
+V206 g116_0 0 pulse(0 1 0p 200p 100p 1n 2n)
+V207 g145_1 0 pulse(0 1 0p 200p 100p 1n 2n)
+
+* the net sub circuits:
+
+.subckt netx81 x81_1 x81_0 gnd
+C1  x81_1 gnd 2.080806f
+C2  x81_0 gnd 2.080806f
+R1 x81_1 x81_0 2.224404
+.ends
+
+.subckt netg4055 g4055_1 g4055_0 gnd
+C1  g4055_1 gnd 2.080806f
+C2  g4055_0 gnd 2.080806f
+R1 g4055_1 g4055_0 2.224404
+.ends
+
+.subckt netg6531 g6531_1 g6531_0 gnd
+C1  g6531_1 gnd 2.080806f
+C2  g6531_0 gnd 2.080806f
+R1 g6531_0 g6531_1 2.224404
+.ends
+
+.subckt netg1255 g1255_0 g1255_1 gnd
+C1  g1255_0 gnd 2.080806f
+C2  g1255_1 gnd 2.080806f
+R1 g1255_1 g1255_0 2.224404
+.ends
+
+.subckt netg5391 g5391_0 g5391_1 gnd
+C1  g5391_0 gnd 2.080806f
+C2  g5391_1 gnd 2.080806f
+R1 g5391_1 g5391_0 2.224404
+.ends
+
+.subckt netg4749 g4749_0 g4749_1 gnd
+C1  g4749_0 gnd 2.080806f
+C2  g4749_1 gnd 2.080806f
+R1 g4749_0 g4749_1 2.224404
+.ends
+
+.subckt netg7003 g7003_0 g7003_1 gnd
+C1  g7003_0 gnd 2.080806f
+C2  g7003_1 gnd 2.080806f
+R1 g7003_0 g7003_1 2.224404
+.ends
+
+.subckt netx242 x242_1 x242_0 gnd
+C1  x242_1 gnd 2.080806f
+C2  x242_0 gnd 2.080806f
+R1 x242_0 x242_1 2.224404
+.ends
+
+.subckt netg6733 g6733_0 g6733_1 gnd
+C1  g6733_0 gnd 2.080806f
+C2  g6733_1 gnd 2.080806f
+R1 g6733_1 g6733_0 2.224404
+.ends
+
+.subckt netg404 g404_2 g404_0 gnd
+C1  g404_2 gnd 2.080806f
+C2  g404_0 gnd 2.080806f
+R1 g404_2 g404_0 2.224404
+.ends
+
+.subckt netg2934 g2934_1 g2934_0 gnd
+C1  g2934_1 gnd 2.080806f
+C2  g2934_0 gnd 2.080806f
+R1 g2934_0 g2934_1 2.224404
+.ends
+
+.subckt netg6397 g6397_0 g6397_1 gnd
+C1  g6397_0 gnd 2.080806f
+C2  g6397_1 gnd 2.080806f
+R1 g6397_1 g6397_0 2.224404
+.ends
+
+.subckt netg7266 g7266_1 g7266_0 gnd
+C1  g7266_1 gnd 2.080806f
+C2  g7266_0 gnd 2.080806f
+R1 g7266_0 g7266_1 2.224404
+.ends
+
+.subckt netg5784 g5784_0 g5784_1 gnd
+C1  g5784_0 gnd 2.080806f
+C2  g5784_1 gnd 2.080806f
+R1 g5784_1 g5784_0 2.224404
+.ends
+
+.subckt netg6546 g6546_1 g6546_2 gnd
+C1  g6546_1 gnd 2.080806f
+C2  g6546_2 gnd 2.080806f
+R1 g6546_2 g6546_1 2.224404
+.ends
+
+.subckt netg6937 g6937_1 g6937_0 gnd
+C1  g6937_1 gnd 2.080806f
+C2  g6937_0 gnd 2.080806f
+R1 g6937_0 g6937_1 2.224404
+.ends
+
+.subckt netg2929 g2929_1 g2929_0 gnd
+C1  g2929_1 gnd 2.080806f
+C2  g2929_0 gnd 2.080806f
+R1 g2929_0 g2929_1 2.224404
+.ends
+
+.subckt netg4099 g4099_1 g4099_0 gnd
+C1  g4099_1 gnd 2.080806f
+C2  g4099_0 gnd 2.080806f
+R1 g4099_1 g4099_0 2.224404
+.ends
+
+.subckt netg3537 g3537_0 g3537_1 gnd
+C1  g3537_0 gnd 2.080806f
+C2  g3537_1 gnd 2.080806f
+R1 g3537_1 g3537_0 2.224404
+.ends
+
+.subckt netg4245 g4245_0 g4245_1 gnd
+C1  g4245_0 gnd 2.080806f
+C2  g4245_1 gnd 2.080806f
+R1 g4245_0 g4245_1 2.224404
+.ends
+
+.subckt netg5584 g5584_1 g5584_0 gnd
+C1  g5584_1 gnd 2.080806f
+C2  g5584_0 gnd 2.080806f
+R1 g5584_0 g5584_1 2.224404
+.ends
+
+.subckt netg4531 g4531_1 g4531_0 gnd
+C1  g4531_1 gnd 2.080806f
+C2  g4531_0 gnd 2.080806f
+R1 g4531_1 g4531_0 2.224404
+.ends
+
+.subckt netg3903 g3903_1 g3903_0 gnd
+C1  g3903_1 gnd 2.080806f
+C2  g3903_0 gnd 2.080806f
+R1 g3903_1 g3903_0 2.224404
+.ends
+
+.subckt netg7164 g7164_1 g7164_0 gnd
+C1  g7164_1 gnd 2.080806f
+C2  g7164_0 gnd 2.080806f
+R1 g7164_0 g7164_1 2.224404
+.ends
+
+.subckt netg1998 g1998_0 g1998_1 gnd
+C1  g1998_0 gnd 2.080806f
+C2  g1998_1 gnd 2.080806f
+R1 g1998_1 g1998_0 2.224404
+.ends
+
+.subckt netx461 x461_0 x461_1 gnd
+C1  x461_0 gnd 2.080806f
+C2  x461_1 gnd 2.080806f
+R1 x461_0 x461_1 2.224404
+.ends
+
+.subckt netg4257 g4257_0 g4257_1 gnd
+C1  g4257_0 gnd 2.080806f
+C2  g4257_1 gnd 2.080806f
+R1 g4257_1 g4257_0 2.224404
+.ends
+
+.subckt netg961 g961_2 g961_1 gnd
+C1  g961_2 gnd 2.080806f
+C2  g961_1 gnd 2.080806f
+R1 g961_2 g961_1 2.224404
+.ends
+
+.subckt netg2816 g2816_0 g2816_1 gnd
+C1  g2816_0 gnd 2.080806f
+C2  g2816_1 gnd 2.080806f
+R1 g2816_0 g2816_1 2.224404
+.ends
+
+.subckt netg6439 g6439_1 g6439_0 gnd
+C1  g6439_1 gnd 2.080806f
+C2  g6439_0 gnd 2.080806f
+R1 g6439_1 g6439_0 2.224404
+.ends
+
+.subckt netg6979 g6979_1 g6979_0 gnd
+C1  g6979_1 gnd 2.080806f
+C2  g6979_0 gnd 2.080806f
+R1 g6979_0 g6979_1 2.224404
+.ends
+
+.subckt netg6213 g6213_0 g6213_1 gnd
+C1  g6213_0 gnd 2.080806f
+C2  g6213_1 gnd 2.080806f
+R1 g6213_0 g6213_1 2.224404
+.ends
+
+.subckt netg7268 g7268_1 g7268_0 gnd
+C1  g7268_1 gnd 2.080806f
+C2  g7268_0 gnd 2.080806f
+R1 g7268_0 g7268_1 2.224404
+.ends
+
+.subckt netg1933 g1933_1 g1933_0 gnd
+C1  g1933_1 gnd 2.080806f
+C2  g1933_0 gnd 2.080806f
+R1 g1933_1 g1933_0 2.224404
+.ends
+
+.subckt netg3986 g3986_0 g3986_1 gnd
+C1  g3986_0 gnd 2.080806f
+C2  g3986_1 gnd 2.080806f
+R1 g3986_1 g3986_0 2.224404
+.ends
+
+.subckt netg2916 g2916_1 g2916_0 gnd
+C1  g2916_1 gnd 2.080806f
+C2  g2916_0 gnd 2.080806f
+R1 g2916_1 g2916_0 2.224404
+.ends
+
+.subckt netg6553 g6553_0 g6553_1 gnd
+C1  g6553_0 gnd 2.080806f
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+.ends
+
+.subckt netg2788 g2788_0 g2788_1 gnd
+C1  g2788_0 gnd 2.080806f
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+.ends
+
+.subckt netg5960 g5960_0 g5960_1 gnd
+C1  g5960_0 gnd 2.080806f
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+.ends
+
+.subckt netg3549 g3549_0 g3549_1 gnd
+C1  g3549_0 gnd 2.080806f
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+.ends
+
+.subckt netg6206 g6206_0 g6206_1 gnd
+C1  g6206_0 gnd 2.080806f
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+.ends
+
+.subckt netg1874 g1874_2 g1874_1 gnd
+C1  g1874_2 gnd 2.080806f
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+.ends
+
+.subckt netg6916 g6916_1 g6916_0 gnd
+C1  g6916_1 gnd 2.080806f
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+.ends
+
+.subckt netg5365 g5365_0 g5365_1 gnd
+C1  g5365_0 gnd 2.080806f
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+R1 g5365_1 g5365_0 2.224404
+.ends
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+.subckt netg1131 g1131_1 g1131_0 gnd
+C1  g1131_1 gnd 2.080806f
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+.ends
+
+.subckt netg7189 g7189_1 g7189_0 gnd
+C1  g7189_1 gnd 2.080806f
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+.ends
+
+.subckt netg4313 g4313_1 g4313_0 gnd
+C1  g4313_1 gnd 2.080806f
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+.ends
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+.subckt netg2426 g2426_0 g2426_2 gnd
+C1  g2426_0 gnd 2.080806f
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+.ends
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+.subckt netg7001 g7001_1 g7001_0 gnd
+C1  g7001_1 gnd 2.080806f
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+.ends
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+.subckt netg2952 g2952_1 g2952_0 gnd
+C1  g2952_1 gnd 2.080806f
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+.ends
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+.subckt netg5880 g5880_1 g5880_0 gnd
+C1  g5880_1 gnd 2.080806f
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+.ends
+
+.subckt netg3513 g3513_1 g3513_0 gnd
+C1  g3513_1 gnd 2.080806f
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+.ends
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+.subckt netg2939 g2939_0 g2939_1 gnd
+C1  g2939_0 gnd 2.080806f
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+R1 g2939_1 g2939_0 2.224404
+.ends
+
+.subckt netg3524 g3524_0 g3524_1 gnd
+C1  g3524_0 gnd 2.080806f
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+.ends
+
+.subckt netg6729 g6729_1 g6729_0 gnd
+C1  g6729_1 gnd 2.080806f
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+.ends
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+.subckt netg7354 g7354_1 g7354_0 gnd
+C1  g7354_1 gnd 2.080806f
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+.ends
+
+.subckt netg2818 g2818_0 g2818_1 gnd
+C1  g2818_0 gnd 2.080806f
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+R1 g2818_1 g2818_0 2.224404
+.ends
+
+.subckt netg6447 g6447_1 g6447_0 gnd
+C1  g6447_1 gnd 2.080806f
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+.ends
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+.subckt netg6132 g6132_0 g6132_1 gnd
+C1  g6132_0 gnd 2.080806f
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+.ends
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+.subckt netg3510 g3510_0 g3510_1 gnd
+C1  g3510_0 gnd 2.080806f
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+.ends
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+.subckt netg3486 g3486_1 g3486_0 gnd
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+.ends
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+.subckt netg6042 g6042_0 g6042_1 gnd
+C1  g6042_0 gnd 2.080806f
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+.ends
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+.subckt netg1591 g1591_1 g1591_0 gnd
+C1  g1591_1 gnd 2.080806f
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+.ends
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+.subckt netg4096 g4096_1 g4096_0 gnd
+C1  g4096_1 gnd 2.080806f
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+R1 g4096_1 g4096_0 2.224404
+.ends
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+.subckt netg4048 g4048_1 g4048_0 gnd
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+R1 g4048_1 g4048_0 2.224404
+.ends
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+.subckt netg2813 g2813_1 g2813_0 gnd
+C1  g2813_1 gnd 2.080806f
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+.ends
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+.subckt netg1928 g1928_0 g1928_1 gnd
+C1  g1928_0 gnd 2.080806f
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+R1 g1928_1 g1928_0 2.224404
+.ends
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+.subckt netg5233 g5233_0 g5233_1 gnd
+C1  g5233_0 gnd 2.080806f
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+R1 g5233_1 g5233_0 2.224404
+.ends
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+.subckt netg5369 g5369_1 g5369_0 gnd
+C1  g5369_1 gnd 2.080806f
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+.ends
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+.subckt netg4451 g4451_1 g4451_0 gnd
+C1  g4451_1 gnd 2.080806f
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+R1 g4451_1 g4451_0 2.224404
+.ends
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+.subckt netg3480 g3480_1 g3480_0 gnd
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+.ends
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+.subckt netg7359 g7359_0 g7359_1 gnd
+C1  g7359_0 gnd 2.080806f
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+.ends
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+.subckt netg4302 g4302_0 g4302_1 gnd
+C1  g4302_0 gnd 2.080806f
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+.ends
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+.subckt netg6047 g6047_1 g6047_0 gnd
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+R1 g6047_1 g6047_0 2.224404
+.ends
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+.subckt netg7358 g7358_0 g7358_1 gnd
+C1  g7358_0 gnd 2.080806f
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+R1 g7358_1 g7358_0 2.224404
+.ends
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+.subckt netg4280 g4280_1 g4280_0 gnd
+C1  g4280_1 gnd 2.080806f
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+R1 g4280_0 g4280_1 2.224404
+.ends
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+.subckt netg5411 g5411_1 g5411_0 gnd
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+.ends
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+.subckt netx22 x22_0 x22_1 gnd
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+.ends
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+.subckt netg1128 g1128_0 g1128_1 gnd
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+.ends
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+.subckt netg3691 g3691_2 g3691_0 gnd
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+.ends
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+.subckt netg7213 g7213_1 g7213_0 gnd
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+.ends
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+.subckt netg2764 g2764_0 g2764_1 gnd
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+.ends
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+.subckt netg6382 g6382_1 g6382_0 gnd
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+.ends
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+.subckt netg3894 g3894_1 g3894_0 gnd
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+.ends
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+.subckt netg6815 g6815_1 g6815_0 gnd
+C1  g6815_1 gnd 2.080806f
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+.ends
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+.subckt netg2773 g2773_0 g2773_1 gnd
+C1  g2773_0 gnd 2.080806f
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+.ends
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+.subckt netg2228 g2228_1 g2228_0 gnd
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+.ends
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+.subckt netg5246 g5246_1 g5246_0 gnd
+C1  g5246_1 gnd 2.080806f
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+.ends
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+.subckt netg2821 g2821_0 g2821_1 gnd
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+.ends
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+.subckt netx312 x312_0 x312_1 gnd
+C1  x312_0 gnd 2.080806f
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+.ends
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+.subckt netg3983 g3983_1 g3983_0 gnd
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+R1 g3983_1 g3983_0 2.224404
+.ends
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+.subckt netg4329 g4329_1 g4329_0 gnd
+C1  g4329_1 gnd 2.080806f
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+.ends
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+.subckt netg7374 g7374_0 g7374_1 gnd
+C1  g7374_0 gnd 2.080806f
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+.ends
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+.subckt netg2501 g2501_2 g2501_0 gnd
+C1  g2501_2 gnd 2.080806f
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+.ends
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+.subckt netg4100 g4100_1 g4100_0 gnd
+C1  g4100_1 gnd 2.080806f
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+R1 g4100_1 g4100_0 2.224404
+.ends
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+.subckt netg6013 g6013_0 g6013_1 gnd
+C1  g6013_0 gnd 2.080806f
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+.ends
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+.subckt netg2760 g2760_1 g2760_0 gnd
+C1  g2760_1 gnd 2.080806f
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+R1 g2760_1 g2760_0 2.224404
+.ends
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+.subckt netg7212 g7212_0 g7212_1 gnd
+C1  g7212_0 gnd 2.080806f
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+R1 g7212_1 g7212_0 2.224404
+.ends
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+.subckt netg3923 g3923_1 g3923_0 gnd
+C1  g3923_1 gnd 2.080806f
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+R1 g3923_1 g3923_0 2.224404
+.ends
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+.subckt netg3414 g3414_2 g3414_1 gnd
+C1  g3414_2 gnd 2.080806f
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+R1 g3414_1 g3414_2 2.224404
+.ends
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+.subckt netg5597 g5597_0 g5597_1 gnd
+C1  g5597_0 gnd 2.080806f
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+R1 g5597_0 g5597_1 2.224404
+.ends
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+.subckt netg4298 g4298_0 g4298_1 gnd
+C1  g4298_0 gnd 2.080806f
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+R1 g4298_1 g4298_0 2.224404
+.ends
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+.subckt netg7046 g7046_0 g7046_1 gnd
+C1  g7046_0 gnd 2.080806f
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+R1 g7046_0 g7046_1 2.224404
+.ends
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+.subckt netg6452 g6452_1 g6452_0 gnd
+C1  g6452_1 gnd 2.080806f
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+R1 g6452_1 g6452_0 2.224404
+.ends
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+.subckt netg6081 g6081_1 g6081_0 gnd
+C1  g6081_1 gnd 2.080806f
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+R1 g6081_0 g6081_1 2.224404
+.ends
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+.subckt netg5448 g5448_2 g5448_1 gnd
+C1  g5448_2 gnd 2.080806f
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+R1 g5448_1 g5448_2 2.224404
+.ends
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+.subckt netg3367 g3367_1 g3367_0 gnd
+C1  g3367_1 gnd 2.080806f
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+R1 g3367_0 g3367_1 2.224404
+.ends
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+.subckt netg5353 g5353_0 g5353_1 gnd
+C1  g5353_0 gnd 2.080806f
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+R1 g5353_1 g5353_0 2.224404
+.ends
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+.subckt netg7191 g7191_0 g7191_1 gnd
+C1  g7191_0 gnd 2.080806f
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+R1 g7191_1 g7191_0 2.224404
+.ends
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+.subckt netg4013 g4013_0 g4013_1 gnd
+C1  g4013_0 gnd 2.080806f
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+R1 g4013_0 g4013_1 2.224404
+.ends
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+.subckt netg6580 g6580_0 g6580_1 gnd
+C1  g6580_0 gnd 2.080806f
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+R1 g6580_1 g6580_0 2.224404
+.ends
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+.subckt netg2350 g2350_2 g2350_0 gnd
+C1  g2350_2 gnd 2.080806f
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+R1 g2350_2 g2350_0 2.224404
+.ends
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+.subckt netg3519 g3519_1 g3519_0 gnd
+C1  g3519_1 gnd 2.080806f
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+R1 g3519_1 g3519_0 2.224404
+.ends
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+.subckt netg387 g387_0 g387_1 gnd
+C1  g387_0 gnd 2.080806f
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+R1 g387_0 g387_1 2.224404
+.ends
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+.subckt netg6199 g6199_2 g6199_0 gnd
+C1  g6199_2 gnd 2.080806f
+C2  g6199_0 gnd 2.080806f
+R1 g6199_2 g6199_0 2.224404
+.ends
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+.subckt netg7293 g7293_1 g7293_0 gnd
+C1  g7293_1 gnd 2.080806f
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+R1 g7293_1 g7293_0 2.224404
+.ends
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+.subckt netg1432 g1432_0 g1432_1 gnd
+C1  g1432_0 gnd 2.080806f
+C2  g1432_1 gnd 2.080806f
+R1 g1432_0 g1432_1 2.224404
+.ends
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+.subckt netg1378 g1378_1 g1378_0 gnd
+C1  g1378_1 gnd 2.080806f
+C2  g1378_0 gnd 2.080806f
+R1 g1378_1 g1378_0 2.224404
+.ends
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+.subckt netx332 x332_0 x332_1 gnd
+C1  x332_0 gnd 2.080806f
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+R1 x332_0 x332_1 2.224404
+.ends
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+.subckt netg6611 g6611_1 g6611_0 gnd
+C1  g6611_1 gnd 2.080806f
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+R1 g6611_0 g6611_1 2.224404
+.ends
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+.subckt netg3564 g3564_0 g3564_1 gnd
+C1  g3564_0 gnd 2.080806f
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+R1 g3564_0 g3564_1 2.224404
+.ends
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+.subckt netg2774 g2774_1 g2774_0 gnd
+C1  g2774_1 gnd 2.080806f
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+R1 g2774_0 g2774_1 2.224404
+.ends
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+.subckt netg1313 g1313_0 g1313_1 gnd
+C1  g1313_0 gnd 2.080806f
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+R1 g1313_1 g1313_0 2.224404
+.ends
+
+.subckt netg6741 g6741_1 g6741_0 gnd
+C1  g6741_1 gnd 2.080806f
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+R1 g6741_0 g6741_1 2.224404
+.ends
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+.subckt netg4290 g4290_0 g4290_1 gnd
+C1  g4290_0 gnd 2.080806f
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+R1 g4290_1 g4290_0 2.224404
+.ends
+
+.subckt netg6931 g6931_1 g6931_0 gnd
+C1  g6931_1 gnd 2.080806f
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+R1 g6931_0 g6931_1 2.224404
+.ends
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+.subckt netg5859 g5859_1 g5859_0 gnd
+C1  g5859_1 gnd 2.080806f
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+R1 g5859_0 g5859_1 2.224404
+.ends
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+.subckt netg5827 g5827_0 g5827_1 gnd
+C1  g5827_0 gnd 2.080806f
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+R1 g5827_1 g5827_0 2.224404
+.ends
+
+.subckt netg4428 g4428_0 g4428_1 gnd
+C1  g4428_0 gnd 2.080806f
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+R1 g4428_1 g4428_0 2.224404
+.ends
+
+.subckt netg4220 g4220_0 g4220_1 gnd
+C1  g4220_0 gnd 2.080806f
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+R1 g4220_0 g4220_1 2.224404
+.ends
+
+.subckt netg1174 g1174_0 g1174_1 gnd
+C1  g1174_0 gnd 2.080806f
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+R1 g1174_0 g1174_1 2.224404
+.ends
+
+.subckt netg5857 g5857_0 g5857_1 gnd
+C1  g5857_0 gnd 2.080806f
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+R1 g5857_0 g5857_1 2.224404
+.ends
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+.subckt netg4103 g4103_1 g4103_0 gnd
+C1  g4103_1 gnd 2.080806f
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+R1 g4103_0 g4103_1 2.224404
+.ends
+
+.subckt netg6102 g6102_0 g6102_1 gnd
+C1  g6102_0 gnd 2.080806f
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+R1 g6102_1 g6102_0 2.224404
+.ends
+
+.subckt netg3070 g3070_0 g3070_1 gnd
+C1  g3070_0 gnd 2.080806f
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+R1 g3070_1 g3070_0 2.224404
+.ends
+
+.subckt netg6474 g6474_1 g6474_0 gnd
+C1  g6474_1 gnd 2.080806f
+C2  g6474_0 gnd 2.080806f
+R1 g6474_1 g6474_0 2.224404
+.ends
+
+.subckt netg2781 g2781_1 g2781_0 gnd
+C1  g2781_1 gnd 2.080806f
+C2  g2781_0 gnd 2.080806f
+R1 g2781_0 g2781_1 2.224404
+.ends
+
+.subckt netg7397 g7397_1 g7397_0 gnd
+C1  g7397_1 gnd 2.080806f
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+R1 g7397_0 g7397_1 2.224404
+.ends
+
+.subckt netg1284 g1284_0 g1284_1 gnd
+C1  g1284_0 gnd 2.080806f
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+R1 g1284_1 g1284_0 2.224404
+.ends
+
+.subckt netg410 g410_2 g410_0 gnd
+C1  g410_2 gnd 2.080806f
+C2  g410_0 gnd 2.080806f
+R1 g410_2 g410_0 2.224404
+.ends
+
+.subckt netg2778 g2778_0 g2778_1 gnd
+C1  g2778_0 gnd 2.080806f
+C2  g2778_1 gnd 2.080806f
+R1 g2778_0 g2778_1 2.224404
+.ends
+
+.subckt netg4283 g4283_0 g4283_1 gnd
+C1  g4283_0 gnd 2.080806f
+C2  g4283_1 gnd 2.080806f
+R1 g4283_0 g4283_1 2.224404
+.ends
+
+.subckt netg6345 g6345_0 g6345_1 gnd
+C1  g6345_0 gnd 2.080806f
+C2  g6345_1 gnd 2.080806f
+R1 g6345_0 g6345_1 2.224404
+.ends
+
+.subckt netg5766 g5766_0 g5766_1 gnd
+C1  g5766_0 gnd 2.080806f
+C2  g5766_1 gnd 2.080806f
+R1 g5766_1 g5766_0 2.224404
+.ends
+
+.subckt netg6254 g6254_0 g6254_1 gnd
+C1  g6254_0 gnd 2.080806f
+C2  g6254_1 gnd 2.080806f
+R1 g6254_0 g6254_1 2.224404
+.ends
+
+.subckt netg3069 g3069_1 g3069_0 gnd
+C1  g3069_1 gnd 2.080806f
+C2  g3069_0 gnd 2.080806f
+R1 g3069_1 g3069_0 2.224404
+.ends
+
+.subckt netg6640 g6640_1 g6640_0 gnd
+C1  g6640_1 gnd 2.080806f
+C2  g6640_0 gnd 2.080806f
+R1 g6640_1 g6640_0 2.224404
+.ends
+
+.subckt netg6014 g6014_1 g6014_0 gnd
+C1  g6014_1 gnd 2.080806f
+C2  g6014_0 gnd 2.080806f
+R1 g6014_1 g6014_0 2.224404
+.ends
+
+.subckt netg4216 g4216_1 g4216_0 gnd
+C1  g4216_1 gnd 2.080806f
+C2  g4216_0 gnd 2.080806f
+R1 g4216_0 g4216_1 2.224404
+.ends
+
+.subckt netg1945 g1945_2 g1945_1 gnd
+C1  g1945_2 gnd 2.080806f
+C2  g1945_1 gnd 2.080806f
+R1 g1945_1 g1945_2 2.224404
+.ends
+
+.subckt netg5527 g5527_0 g5527_1 gnd
+C1  g5527_0 gnd 2.080806f
+C2  g5527_1 gnd 2.080806f
+R1 g5527_1 g5527_0 2.224404
+.ends
+
+.subckt netg2371 g2371_1 g2371_2 gnd
+C1  g2371_1 gnd 2.080806f
+C2  g2371_2 gnd 2.080806f
+R1 g2371_1 g2371_2 2.224404
+.ends
+
+.subckt netx82 x82_1 x82_0 gnd
+C1  x82_1 gnd 2.080806f
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+R1 x82_1 x82_0 2.224404
+.ends
+
+.subckt netg2751 g2751_0 g2751_1 gnd
+C1  g2751_0 gnd 2.080806f
+C2  g2751_1 gnd 2.080806f
+R1 g2751_0 g2751_1 2.224404
+.ends
+
+.subckt netg4219 g4219_1 g4219_0 gnd
+C1  g4219_1 gnd 2.080806f
+C2  g4219_0 gnd 2.080806f
+R1 g4219_1 g4219_0 2.224404
+.ends
+
+.subckt netg5998 g5998_0 g5998_1 gnd
+C1  g5998_0 gnd 2.080806f
+C2  g5998_1 gnd 2.080806f
+R1 g5998_0 g5998_1 2.224404
+.ends
+
+.subckt netg5065 g5065_2 g5065_1 gnd
+C1  g5065_2 gnd 2.080806f
+C2  g5065_1 gnd 2.080806f
+R1 g5065_2 g5065_1 2.224404
+.ends
+
+.subckt netg6103 g6103_0 g6103_1 gnd
+C1  g6103_0 gnd 2.080806f
+C2  g6103_1 gnd 2.080806f
+R1 g6103_0 g6103_1 2.224404
+.ends
+
+.subckt netg7047 g7047_0 g7047_1 gnd
+C1  g7047_0 gnd 2.080806f
+C2  g7047_1 gnd 2.080806f
+R1 g7047_0 g7047_1 2.224404
+.ends
+
+.subckt netg5316 g5316_0 g5316_1 gnd
+C1  g5316_0 gnd 2.080806f
+C2  g5316_1 gnd 2.080806f
+R1 g5316_1 g5316_0 2.224404
+.ends
+
+.subckt netg7405 g7405_1 g7405_0 gnd
+C1  g7405_1 gnd 2.080806f
+C2  g7405_0 gnd 2.080806f
+R1 g7405_1 g7405_0 2.224404
+.ends
+
+.subckt netg1518 g1518_1 g1518_0 gnd
+C1  g1518_1 gnd 2.080806f
+C2  g1518_0 gnd 2.080806f
+R1 g1518_1 g1518_0 2.224404
+.ends
+
+.subckt netg5191 g5191_0 g5191_2 gnd
+C1  g5191_0 gnd 2.080806f
+C2  g5191_2 gnd 2.080806f
+R1 g5191_0 g5191_2 2.224404
+.ends
+
+.subckt netg5996 g5996_0 g5996_1 gnd
+C1  g5996_0 gnd 2.080806f
+C2  g5996_1 gnd 2.080806f
+R1 g5996_0 g5996_1 2.224404
+.ends
+
+.subckt netg1125 g1125_1 g1125_0 gnd
+C1  g1125_1 gnd 2.080806f
+C2  g1125_0 gnd 2.080806f
+R1 g1125_1 g1125_0 2.224404
+.ends
+
+.subckt netg5792 g5792_1 g5792_0 gnd
+C1  g5792_1 gnd 2.080806f
+C2  g5792_0 gnd 2.080806f
+R1 g5792_1 g5792_0 2.224404
+.ends
+
+.subckt netg2380 g2380_2 g2380_1 gnd
+C1  g2380_2 gnd 2.080806f
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+R1 g2380_1 g2380_2 2.224404
+.ends
+
+.subckt netg6084 g6084_0 g6084_1 gnd
+C1  g6084_0 gnd 2.080806f
+C2  g6084_1 gnd 2.080806f
+R1 g6084_1 g6084_0 2.224404
+.ends
+
+.subckt netg6052 g6052_0 g6052_1 gnd
+C1  g6052_0 gnd 2.080806f
+C2  g6052_1 gnd 2.080806f
+R1 g6052_1 g6052_0 2.224404
+.ends
+
+.subckt netg5297 g5297_1 g5297_0 gnd
+C1  g5297_1 gnd 2.080806f
+C2  g5297_0 gnd 2.080806f
+R1 g5297_0 g5297_1 2.224404
+.ends
+
+.subckt netg4323 g4323_1 g4323_0 gnd
+C1  g4323_1 gnd 2.080806f
+C2  g4323_0 gnd 2.080806f
+R1 g4323_0 g4323_1 2.224404
+.ends
+
+.subckt netg4628 g4628_0 g4628_1 gnd
+C1  g4628_0 gnd 2.080806f
+C2  g4628_1 gnd 2.080806f
+R1 g4628_0 g4628_1 2.224404
+.ends
+
+.subckt netg3540 g3540_1 g3540_0 gnd
+C1  g3540_1 gnd 2.080806f
+C2  g3540_0 gnd 2.080806f
+R1 g3540_1 g3540_0 2.224404
+.ends
+
+.subckt netg4065 g4065_1 g4065_0 gnd
+C1  g4065_1 gnd 2.080806f
+C2  g4065_0 gnd 2.080806f
+R1 g4065_1 g4065_0 2.224404
+.ends
+
+.subckt netg4239 g4239_1 g4239_0 gnd
+C1  g4239_1 gnd 2.080806f
+C2  g4239_0 gnd 2.080806f
+R1 g4239_1 g4239_0 2.224404
+.ends
+
+.subckt netg5350 g5350_0 g5350_1 gnd
+C1  g5350_0 gnd 2.080806f
+C2  g5350_1 gnd 2.080806f
+R1 g5350_0 g5350_1 2.224404
+.ends
+
+.subckt netg1234 g1234_0 g1234_1 gnd
+C1  g1234_0 gnd 2.080806f
+C2  g1234_1 gnd 2.080806f
+R1 g1234_0 g1234_1 2.224404
+.ends
+
+.subckt netg4318 g4318_1 g4318_0 gnd
+C1  g4318_1 gnd 2.080806f
+C2  g4318_0 gnd 2.080806f
+R1 g4318_1 g4318_0 2.224404
+.ends
+
+.subckt netg6667 g6667_1 g6667_0 gnd
+C1  g6667_1 gnd 2.080806f
+C2  g6667_0 gnd 2.080806f
+R1 g6667_0 g6667_1 2.224404
+.ends
+
+.subckt netg5737 g5737_2 g5737_1 gnd
+C1  g5737_2 gnd 2.080806f
+C2  g5737_1 gnd 2.080806f
+R1 g5737_1 g5737_2 2.224404
+.ends
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+.subckt netg7004 g7004_1 g7004_2 gnd
+C1  g7004_1 gnd 2.080806f
+C2  g7004_2 gnd 2.080806f
+R1 g7004_2 g7004_1 2.224404
+.ends
+
+.subckt netg5244 g5244_1 g5244_0 gnd
+C1  g5244_1 gnd 2.080806f
+C2  g5244_0 gnd 2.080806f
+R1 g5244_1 g5244_0 2.224404
+.ends
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+.subckt netg6184 g6184_1 g6184_0 gnd
+C1  g6184_1 gnd 2.080806f
+C2  g6184_0 gnd 2.080806f
+R1 g6184_0 g6184_1 2.224404
+.ends
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+.subckt netg6862 g6862_0 g6862_1 gnd
+C1  g6862_0 gnd 2.080806f
+C2  g6862_1 gnd 2.080806f
+R1 g6862_0 g6862_1 2.224404
+.ends
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+.subckt netg1264 g1264_0 g1264_1 gnd
+C1  g1264_0 gnd 2.080806f
+C2  g1264_1 gnd 2.080806f
+R1 g1264_0 g1264_1 2.224404
+.ends
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+.subckt netg2879 g2879_1 g2879_0 gnd
+C1  g2879_1 gnd 2.080806f
+C2  g2879_0 gnd 2.080806f
+R1 g2879_0 g2879_1 2.224404
+.ends
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+.subckt netg3509 g3509_0 g3509_1 gnd
+C1  g3509_0 gnd 2.080806f
+C2  g3509_1 gnd 2.080806f
+R1 g3509_0 g3509_1 2.224404
+.ends
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+.subckt netg3411 g3411_0 g3411_1 gnd
+C1  g3411_0 gnd 2.080806f
+C2  g3411_1 gnd 2.080806f
+R1 g3411_0 g3411_1 2.224404
+.ends
+
+.subckt netg2719 g2719_1 g2719_2 gnd
+C1  g2719_1 gnd 2.080806f
+C2  g2719_2 gnd 2.080806f
+R1 g2719_2 g2719_1 2.224404
+.ends
+
+.subckt netg6642 g6642_1 g6642_2 gnd
+C1  g6642_1 gnd 2.080806f
+C2  g6642_2 gnd 2.080806f
+R1 g6642_1 g6642_2 2.224404
+.ends
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+.subckt netg5601 g5601_1 g5601_0 gnd
+C1  g5601_1 gnd 2.080806f
+C2  g5601_0 gnd 2.080806f
+R1 g5601_1 g5601_0 2.224404
+.ends
+
+.subckt netg6287 g6287_0 g6287_1 gnd
+C1  g6287_0 gnd 2.080806f
+C2  g6287_1 gnd 2.080806f
+R1 g6287_1 g6287_0 2.224404
+.ends
+
+.subckt netg5182 g5182_0 g5182_1 gnd
+C1  g5182_0 gnd 2.080806f
+C2  g5182_1 gnd 2.080806f
+R1 g5182_0 g5182_1 2.224404
+.ends
+
+.subckt netg4344 g4344_1 g4344_0 gnd
+C1  g4344_1 gnd 2.080806f
+C2  g4344_0 gnd 2.080806f
+R1 g4344_1 g4344_0 2.224404
+.ends
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+.subckt netg7399 g7399_1 g7399_0 gnd
+C1  g7399_1 gnd 2.080806f
+C2  g7399_0 gnd 2.080806f
+R1 g7399_0 g7399_1 2.224404
+.ends
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+.subckt netg1461 g1461_1 g1461_0 gnd
+C1  g1461_1 gnd 2.080806f
+C2  g1461_0 gnd 2.080806f
+R1 g1461_0 g1461_1 2.224404
+.ends
+
+.subckt netg1123 g1123_1 g1123_0 gnd
+C1  g1123_1 gnd 2.080806f
+C2  g1123_0 gnd 2.080806f
+R1 g1123_0 g1123_1 2.224404
+.ends
+
+.subckt netg5322 g5322_1 g5322_0 gnd
+C1  g5322_1 gnd 2.080806f
+C2  g5322_0 gnd 2.080806f
+R1 g5322_0 g5322_1 2.224404
+.ends
+
+.subckt netg4010 g4010_1 g4010_0 gnd
+C1  g4010_1 gnd 2.080806f
+C2  g4010_0 gnd 2.080806f
+R1 g4010_0 g4010_1 2.224404
+.ends
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+.subckt netx21 x21_0 x21_1 gnd
+C1  x21_0 gnd 2.080806f
+C2  x21_1 gnd 2.080806f
+R1 x21_1 x21_0 2.224404
+.ends
+
+.subckt netg2847 g2847_1 g2847_0 gnd
+C1  g2847_1 gnd 2.080806f
+C2  g2847_0 gnd 2.080806f
+R1 g2847_0 g2847_1 2.224404
+.ends
+
+.subckt netg1222 g1222_0 g1222_1 gnd
+C1  g1222_0 gnd 2.080806f
+C2  g1222_1 gnd 2.080806f
+R1 g1222_1 g1222_0 2.224404
+.ends
+
+.subckt netg1916 g1916_1 g1916_0 gnd
+C1  g1916_1 gnd 2.080806f
+C2  g1916_0 gnd 2.080806f
+R1 g1916_1 g1916_0 2.224404
+.ends
+
+.subckt netg5425 g5425_1 g5425_0 gnd
+C1  g5425_1 gnd 2.080806f
+C2  g5425_0 gnd 2.080806f
+R1 g5425_1 g5425_0 2.224404
+.ends
+
+.subckt netg6385 g6385_0 g6385_1 gnd
+C1  g6385_0 gnd 2.080806f
+C2  g6385_1 gnd 2.080806f
+R1 g6385_1 g6385_0 2.224404
+.ends
+
+.subckt netg2240 g2240_1 g2240_0 gnd
+C1  g2240_1 gnd 2.080806f
+C2  g2240_0 gnd 2.080806f
+R1 g2240_0 g2240_1 2.224404
+.ends
+
+.subckt netg5603 g5603_1 g5603_0 gnd
+C1  g5603_1 gnd 2.080806f
+C2  g5603_0 gnd 2.080806f
+R1 g5603_0 g5603_1 2.224404
+.ends
+
+.subckt netg4043 g4043_0 g4043_1 gnd
+C1  g4043_0 gnd 2.080806f
+C2  g4043_1 gnd 2.080806f
+R1 g4043_1 g4043_0 2.224404
+.ends
+
+.subckt netg4404 g4404_1 g4404_0 gnd
+C1  g4404_1 gnd 2.080806f
+C2  g4404_0 gnd 2.080806f
+R1 g4404_0 g4404_1 2.224404
+.ends
+
+.subckt netg1491 g1491_0 g1491_1 gnd
+C1  g1491_0 gnd 2.080806f
+C2  g1491_1 gnd 2.080806f
+R1 g1491_1 g1491_0 2.224404
+.ends
+
+.subckt netg5965 g5965_0 g5965_1 gnd
+C1  g5965_0 gnd 2.080806f
+C2  g5965_1 gnd 2.080806f
+R1 g5965_1 g5965_0 2.224404
+.ends
+
+.subckt netg6137 g6137_0 g6137_1 gnd
+C1  g6137_0 gnd 2.080806f
+C2  g6137_1 gnd 2.080806f
+R1 g6137_1 g6137_0 2.224404
+.ends
+
+.subckt netg2945 g2945_1 g2945_0 gnd
+C1  g2945_1 gnd 2.080806f
+C2  g2945_0 gnd 2.080806f
+R1 g2945_1 g2945_0 2.224404
+.ends
+
+.subckt netx61 x61_0 x61_1 gnd
+C1  x61_0 gnd 2.080806f
+C2  x61_1 gnd 2.080806f
+R1 x61_1 x61_0 2.224404
+.ends
+
+.subckt netg7093 g7093_1 g7093_2 gnd
+C1  g7093_1 gnd 2.080806f
+C2  g7093_2 gnd 2.080806f
+R1 g7093_1 g7093_2 2.224404
+.ends
+
+.subckt netg6420 g6420_0 g6420_1 gnd
+C1  g6420_0 gnd 2.080806f
+C2  g6420_1 gnd 2.080806f
+R1 g6420_0 g6420_1 2.224404
+.ends
+
+.subckt netg874 g874_0 g874_2 gnd
+C1  g874_0 gnd 2.080806f
+C2  g874_2 gnd 2.080806f
+R1 g874_2 g874_0 2.224404
+.ends
+
+.subckt netg7344 g7344_1 g7344_0 gnd
+C1  g7344_1 gnd 2.080806f
+C2  g7344_0 gnd 2.080806f
+R1 g7344_0 g7344_1 2.224404
+.ends
+
+.subckt netg6243 g6243_1 g6243_0 gnd
+C1  g6243_1 gnd 2.080806f
+C2  g6243_0 gnd 2.080806f
+R1 g6243_1 g6243_0 2.224404
+.ends
+
+.subckt netg1069 g1069_0 g1069_1 gnd
+C1  g1069_0 gnd 2.080806f
+C2  g1069_1 gnd 2.080806f
+R1 g1069_1 g1069_0 2.224404
+.ends
+
+.subckt netg6846 g6846_1 g6846_0 gnd
+C1  g6846_1 gnd 2.080806f
+C2  g6846_0 gnd 2.080806f
+R1 g6846_0 g6846_1 2.224404
+.ends
+
+.subckt netg4353 g4353_1 g4353_0 gnd
+C1  g4353_1 gnd 2.080806f
+C2  g4353_0 gnd 2.080806f
+R1 g4353_1 g4353_0 2.224404
+.ends
+
+.subckt netg1250 g1250_1 g1250_0 gnd
+C1  g1250_1 gnd 2.080806f
+C2  g1250_0 gnd 2.080806f
+R1 g1250_0 g1250_1 2.224404
+.ends
+
+.subckt netg5270 g5270_0 g5270_1 gnd
+C1  g5270_0 gnd 2.080806f
+C2  g5270_1 gnd 2.080806f
+R1 g5270_0 g5270_1 2.224404
+.ends
+
+.subckt netg2918 g2918_0 g2918_1 gnd
+C1  g2918_0 gnd 2.080806f
+C2  g2918_1 gnd 2.080806f
+R1 g2918_0 g2918_1 2.224404
+.ends
+
+.subckt netg5980 g5980_0 g5980_1 gnd
+C1  g5980_0 gnd 2.080806f
+C2  g5980_1 gnd 2.080806f
+R1 g5980_0 g5980_1 2.224404
+.ends
+
+.subckt netg1307 g1307_1 g1307_0 gnd
+C1  g1307_1 gnd 2.080806f
+C2  g1307_0 gnd 2.080806f
+R1 g1307_1 g1307_0 2.224404
+.ends
+
+.subckt netg7273 g7273_1 g7273_0 gnd
+C1  g7273_1 gnd 2.080806f
+C2  g7273_0 gnd 2.080806f
+R1 g7273_1 g7273_0 2.224404
+.ends
+
+.subckt netg2743 g2743_2 g2743_1 gnd
+C1  g2743_2 gnd 2.080806f
+C2  g2743_1 gnd 2.080806f
+R1 g2743_2 g2743_1 2.224404
+.ends
+
+.subckt netg3207 g3207_1 g3207_2 gnd
+C1  g3207_1 gnd 2.080806f
+C2  g3207_2 gnd 2.080806f
+R1 g3207_1 g3207_2 2.224404
+.ends
+
+.subckt netx471 x471_0 x471_1 gnd
+C1  x471_0 gnd 2.080806f
+C2  x471_1 gnd 2.080806f
+R1 x471_1 x471_0 2.224404
+.ends
+
+.subckt netg7275 g7275_0 g7275_1 gnd
+C1  g7275_0 gnd 2.080806f
+C2  g7275_1 gnd 2.080806f
+R1 g7275_0 g7275_1 2.224404
+.ends
+
+.subckt netg5266 g5266_1 g5266_0 gnd
+C1  g5266_1 gnd 2.080806f
+C2  g5266_0 gnd 2.080806f
+R1 g5266_0 g5266_1 2.224404
+.ends
+
+.subckt netg4265 g4265_0 g4265_1 gnd
+C1  g4265_0 gnd 2.080806f
+C2  g4265_1 gnd 2.080806f
+R1 g4265_0 g4265_1 2.224404
+.ends
+
+.subckt netg4022 g4022_1 g4022_0 gnd
+C1  g4022_1 gnd 2.080806f
+C2  g4022_0 gnd 2.080806f
+R1 g4022_1 g4022_0 2.224404
+.ends
+
+.subckt netg1360 g1360_0 g1360_1 gnd
+C1  g1360_0 gnd 2.080806f
+C2  g1360_1 gnd 2.080806f
+R1 g1360_0 g1360_1 2.224404
+.ends
+
+.subckt netg6399 g6399_0 g6399_1 gnd
+C1  g6399_0 gnd 2.080806f
+C2  g6399_1 gnd 2.080806f
+R1 g6399_0 g6399_1 2.224404
+.ends
+
+.subckt netg6182 g6182_0 g6182_1 gnd
+C1  g6182_0 gnd 2.080806f
+C2  g6182_1 gnd 2.080806f
+R1 g6182_0 g6182_1 2.224404
+.ends
+
+.subckt netg6673 g6673_0 g6673_1 gnd
+C1  g6673_0 gnd 2.080806f
+C2  g6673_1 gnd 2.080806f
+R1 g6673_0 g6673_1 2.224404
+.ends
+
+.subckt netg3082 g3082_1 g3082_0 gnd
+C1  g3082_1 gnd 2.080806f
+C2  g3082_0 gnd 2.080806f
+R1 g3082_0 g3082_1 2.224404
+.ends
+
+.subckt netg2930 g2930_1 g2930_0 gnd
+C1  g2930_1 gnd 2.080806f
+C2  g2930_0 gnd 2.080806f
+R1 g2930_1 g2930_0 2.224404
+.ends
+
+.subckt netg1494 g1494_0 g1494_1 gnd
+C1  g1494_0 gnd 2.080806f
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+R1 g1494_1 g1494_0 2.224404
+.ends
+
+.subckt netg5368 g5368_0 g5368_1 gnd
+C1  g5368_0 gnd 2.080806f
+C2  g5368_1 gnd 2.080806f
+R1 g5368_1 g5368_0 2.224404
+.ends
+
+.subckt netg1422 g1422_0 g1422_1 gnd
+C1  g1422_0 gnd 2.080806f
+C2  g1422_1 gnd 2.080806f
+R1 g1422_0 g1422_1 2.224404
+.ends
+
+.subckt netg2937 g2937_1 g2937_0 gnd
+C1  g2937_1 gnd 2.080806f
+C2  g2937_0 gnd 2.080806f
+R1 g2937_0 g2937_1 2.224404
+.ends
+
+.subckt netg2555 g2555_1 g2555_2 gnd
+C1  g2555_1 gnd 2.080806f
+C2  g2555_2 gnd 2.080806f
+R1 g2555_1 g2555_2 2.224404
+.ends
+
+.subckt netg3061 g3061_0 g3061_1 gnd
+C1  g3061_0 gnd 2.080806f
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+R1 g3061_0 g3061_1 2.224404
+.ends
+
+.subckt netg5394 g5394_0 g5394_1 gnd
+C1  g5394_0 gnd 2.080806f
+C2  g5394_1 gnd 2.080806f
+R1 g5394_1 g5394_0 2.224404
+.ends
+
+.subckt netg2845 g2845_1 g2845_0 gnd
+C1  g2845_1 gnd 2.080806f
+C2  g2845_0 gnd 2.080806f
+R1 g2845_0 g2845_1 2.224404
+.ends
+
+.subckt netg1534 g1534_1 g1534_0 gnd
+C1  g1534_1 gnd 2.080806f
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+R1 g1534_1 g1534_0 2.224404
+.ends
+
+.subckt netg3045 g3045_1 g3045_0 gnd
+C1  g3045_1 gnd 2.080806f
+C2  g3045_0 gnd 2.080806f
+R1 g3045_0 g3045_1 2.224404
+.ends
+
+.subckt netg6887 g6887_1 g6887_0 gnd
+C1  g6887_1 gnd 2.080806f
+C2  g6887_0 gnd 2.080806f
+R1 g6887_1 g6887_0 2.224404
+.ends
+
+.subckt netg6278 g6278_0 g6278_2 gnd
+C1  g6278_0 gnd 2.080806f
+C2  g6278_2 gnd 2.080806f
+R1 g6278_0 g6278_2 2.224404
+.ends
+
+.subckt netg6977 g6977_0 g6977_1 gnd
+C1  g6977_0 gnd 2.080806f
+C2  g6977_1 gnd 2.080806f
+R1 g6977_0 g6977_1 2.224404
+.ends
+
+.subckt netg3551 g3551_1 g3551_0 gnd
+C1  g3551_1 gnd 2.080806f
+C2  g3551_0 gnd 2.080806f
+R1 g3551_0 g3551_1 2.224404
+.ends
+
+.subckt netg6751 g6751_2 g6751_0 gnd
+C1  g6751_2 gnd 2.080806f
+C2  g6751_0 gnd 2.080806f
+R1 g6751_0 g6751_2 2.224404
+.ends
+
+.subckt netx72 x72_1 x72_0 gnd
+C1  x72_1 gnd 2.080806f
+C2  x72_0 gnd 2.080806f
+R1 x72_1 x72_0 2.224404
+.ends
+
+.subckt netg5421 g5421_1 g5421_0 gnd
+C1  g5421_1 gnd 2.080806f
+C2  g5421_0 gnd 2.080806f
+R1 g5421_0 g5421_1 2.224404
+.ends
+
+.subckt netx122 x122_1 x122_0 gnd
+C1  x122_1 gnd 2.080806f
+C2  x122_0 gnd 2.080806f
+R1 x122_0 x122_1 2.224404
+.ends
+
+.subckt netg5251 g5251_1 g5251_0 gnd
+C1  g5251_1 gnd 2.080806f
+C2  g5251_0 gnd 2.080806f
+R1 g5251_0 g5251_1 2.224404
+.ends
+
+.subckt netg2784 g2784_1 g2784_0 gnd
+C1  g2784_1 gnd 2.080806f
+C2  g2784_0 gnd 2.080806f
+R1 g2784_1 g2784_0 2.224404
+.ends
+
+.subckt netx131 x131_1 x131_0 gnd
+C1  x131_1 gnd 2.080806f
+C2  x131_0 gnd 2.080806f
+R1 x131_0 x131_1 2.224404
+.ends
+
+.subckt netg6814 g6814_1 g6814_0 gnd
+C1  g6814_1 gnd 2.080806f
+C2  g6814_0 gnd 2.080806f
+R1 g6814_0 g6814_1 2.224404
+.ends
+
+.subckt netg6205 g6205_1 g6205_0 gnd
+C1  g6205_1 gnd 2.080806f
+C2  g6205_0 gnd 2.080806f
+R1 g6205_0 g6205_1 2.224404
+.ends
+
+.subckt netg6693 g6693_1 g6693_0 gnd
+C1  g6693_1 gnd 2.080806f
+C2  g6693_0 gnd 2.080806f
+R1 g6693_0 g6693_1 2.224404
+.ends
+
+.subckt netg6465 g6465_0 g6465_1 gnd
+C1  g6465_0 gnd 2.080806f
+C2  g6465_1 gnd 2.080806f
+R1 g6465_0 g6465_1 2.224404
+.ends
+
+.subckt netg2995 g2995_1 g2995_0 gnd
+C1  g2995_1 gnd 2.080806f
+C2  g2995_0 gnd 2.080806f
+R1 g2995_0 g2995_1 2.224404
+.ends
+
+.subckt netg3261 g3261_2 g3261_0 gnd
+C1  g3261_2 gnd 2.080806f
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+R1 g3261_0 g3261_2 2.224404
+.ends
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+.subckt netg1236 g1236_0 g1236_1 gnd
+C1  g1236_0 gnd 2.080806f
+C2  g1236_1 gnd 2.080806f
+R1 g1236_0 g1236_1 2.224404
+.ends
+
+.subckt netg5333 g5333_0 g5333_1 gnd
+C1  g5333_0 gnd 2.080806f
+C2  g5333_1 gnd 2.080806f
+R1 g5333_1 g5333_0 2.224404
+.ends
+
+.subckt netg4098 g4098_1 g4098_0 gnd
+C1  g4098_1 gnd 2.080806f
+C2  g4098_0 gnd 2.080806f
+R1 g4098_0 g4098_1 2.224404
+.ends
+
+.subckt netg5144 g5144_1 g5144_2 gnd
+C1  g5144_1 gnd 2.080806f
+C2  g5144_2 gnd 2.080806f
+R1 g5144_2 g5144_1 2.224404
+.ends
+
+.subckt netg1375 g1375_0 g1375_1 gnd
+C1  g1375_0 gnd 2.080806f
+C2  g1375_1 gnd 2.080806f
+R1 g1375_1 g1375_0 2.224404
+.ends
+
+.subckt netg5366 g5366_0 g5366_1 gnd
+C1  g5366_0 gnd 2.080806f
+C2  g5366_1 gnd 2.080806f
+R1 g5366_0 g5366_1 2.224404
+.ends
+
+.subckt netg4131 g4131_0 g4131_1 gnd
+C1  g4131_0 gnd 2.080806f
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+R1 g4131_1 g4131_0 2.224404
+.ends
+
+.subckt netg4240 g4240_1 g4240_0 gnd
+C1  g4240_1 gnd 2.080806f
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+R1 g4240_0 g4240_1 2.224404
+.ends
+
+.subckt netg3563 g3563_0 g3563_1 gnd
+C1  g3563_0 gnd 2.080806f
+C2  g3563_1 gnd 2.080806f
+R1 g3563_0 g3563_1 2.224404
+.ends
+
+.subckt netg1158 g1158_0 g1158_1 gnd
+C1  g1158_0 gnd 2.080806f
+C2  g1158_1 gnd 2.080806f
+R1 g1158_1 g1158_0 2.224404
+.ends
+
+.subckt netg7002 g7002_0 g7002_1 gnd
+C1  g7002_0 gnd 2.080806f
+C2  g7002_1 gnd 2.080806f
+R1 g7002_0 g7002_1 2.224404
+.ends
+
+.subckt netg5870 g5870_1 g5870_0 gnd
+C1  g5870_1 gnd 2.080806f
+C2  g5870_0 gnd 2.080806f
+R1 g5870_0 g5870_1 2.224404
+.ends
+
+.subckt netg4106 g4106_0 g4106_1 gnd
+C1  g4106_0 gnd 2.080806f
+C2  g4106_1 gnd 2.080806f
+R1 g4106_0 g4106_1 2.224404
+.ends
+
+.subckt netg4352 g4352_1 g4352_0 gnd
+C1  g4352_1 gnd 2.080806f
+C2  g4352_0 gnd 2.080806f
+R1 g4352_1 g4352_0 2.224404
+.ends
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+.subckt netx91 x91_1 x91_0 gnd
+C1  x91_1 gnd 2.080806f
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+R1 x91_0 x91_1 2.224404
+.ends
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+.subckt netg5932 g5932_1 g5932_0 gnd
+C1  g5932_1 gnd 2.080806f
+C2  g5932_0 gnd 2.080806f
+R1 g5932_1 g5932_0 2.224404
+.ends
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+.subckt netg7306 g7306_2 g7306_1 gnd
+C1  g7306_2 gnd 2.080806f
+C2  g7306_1 gnd 2.080806f
+R1 g7306_2 g7306_1 2.224404
+.ends
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+.subckt netg2579 g2579_1 g2579_2 gnd
+C1  g2579_1 gnd 2.080806f
+C2  g2579_2 gnd 2.080806f
+R1 g2579_1 g2579_2 2.224404
+.ends
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+.subckt netg2919 g2919_0 g2919_1 gnd
+C1  g2919_0 gnd 2.080806f
+C2  g2919_1 gnd 2.080806f
+R1 g2919_0 g2919_1 2.224404
+.ends
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+.subckt netg3429 g3429_2 g3429_0 gnd
+C1  g3429_2 gnd 2.080806f
+C2  g3429_0 gnd 2.080806f
+R1 g3429_0 g3429_2 2.224404
+.ends
+
+.subckt netg4082 g4082_1 g4082_0 gnd
+C1  g4082_1 gnd 2.080806f
+C2  g4082_0 gnd 2.080806f
+R1 g4082_1 g4082_0 2.224404
+.ends
+
+.subckt netg3901 g3901_0 g3901_1 gnd
+C1  g3901_0 gnd 2.080806f
+C2  g3901_1 gnd 2.080806f
+R1 g3901_1 g3901_0 2.224404
+.ends
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+.subckt netg5999 g5999_1 g5999_0 gnd
+C1  g5999_1 gnd 2.080806f
+C2  g5999_0 gnd 2.080806f
+R1 g5999_0 g5999_1 2.224404
+.ends
+
+.subckt netg4309 g4309_0 g4309_1 gnd
+C1  g4309_0 gnd 2.080806f
+C2  g4309_1 gnd 2.080806f
+R1 g4309_1 g4309_0 2.224404
+.ends
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+.subckt netg5705 g5705_1 g5705_0 gnd
+C1  g5705_1 gnd 2.080806f
+C2  g5705_0 gnd 2.080806f
+R1 g5705_1 g5705_0 2.224404
+.ends
+
+.subckt netg6450 g6450_1 g6450_0 gnd
+C1  g6450_1 gnd 2.080806f
+C2  g6450_0 gnd 2.080806f
+R1 g6450_1 g6450_0 2.224404
+.ends
+
+.subckt netg7240 g7240_1 g7240_0 gnd
+C1  g7240_1 gnd 2.080806f
+C2  g7240_0 gnd 2.080806f
+R1 g7240_0 g7240_1 2.224404
+.ends
+
+.subckt netg6392 g6392_0 g6392_1 gnd
+C1  g6392_0 gnd 2.080806f
+C2  g6392_1 gnd 2.080806f
+R1 g6392_0 g6392_1 2.224404
+.ends
+
+.subckt netg1169 g1169_1 g1169_0 gnd
+C1  g1169_1 gnd 2.080806f
+C2  g1169_0 gnd 2.080806f
+R1 g1169_0 g1169_1 2.224404
+.ends
+
+.subckt netg6871 g6871_1 g6871_0 gnd
+C1  g6871_1 gnd 2.080806f
+C2  g6871_0 gnd 2.080806f
+R1 g6871_0 g6871_1 2.224404
+.ends
+
+.subckt netg4138 g4138_0 g4138_1 gnd
+C1  g4138_0 gnd 2.080806f
+C2  g4138_1 gnd 2.080806f
+R1 g4138_0 g4138_1 2.224404
+.ends
+
+.subckt netg6363 g6363_1 g6363_0 gnd
+C1  g6363_1 gnd 2.080806f
+C2  g6363_0 gnd 2.080806f
+R1 g6363_1 g6363_0 2.224404
+.ends
+
+.subckt netg5278 g5278_0 g5278_1 gnd
+C1  g5278_0 gnd 2.080806f
+C2  g5278_1 gnd 2.080806f
+R1 g5278_0 g5278_1 2.224404
+.ends
+
+.subckt netg1479 g1479_1 g1479_0 gnd
+C1  g1479_1 gnd 2.080806f
+C2  g1479_0 gnd 2.080806f
+R1 g1479_0 g1479_1 2.224404
+.ends
+
+.subckt netg6167 g6167_0 g6167_1 gnd
+C1  g6167_0 gnd 2.080806f
+C2  g6167_1 gnd 2.080806f
+R1 g6167_0 g6167_1 2.224404
+.ends
+
+.subckt netg6131 g6131_0 g6131_1 gnd
+C1  g6131_0 gnd 2.080806f
+C2  g6131_1 gnd 2.080806f
+R1 g6131_1 g6131_0 2.224404
+.ends
+
+.subckt netg2933 g2933_0 g2933_1 gnd
+C1  g2933_0 gnd 2.080806f
+C2  g2933_1 gnd 2.080806f
+R1 g2933_0 g2933_1 2.224404
+.ends
+
+.subckt netg6744 g6744_1 g6744_0 gnd
+C1  g6744_1 gnd 2.080806f
+C2  g6744_0 gnd 2.080806f
+R1 g6744_0 g6744_1 2.224404
+.ends
+
+.subckt netg7400 g7400_1 g7400_0 gnd
+C1  g7400_1 gnd 2.080806f
+C2  g7400_0 gnd 2.080806f
+R1 g7400_1 g7400_0 2.224404
+.ends
+
+.subckt netg1852 g1852_1 g1852_0 gnd
+C1  g1852_1 gnd 2.080806f
+C2  g1852_0 gnd 2.080806f
+R1 g1852_0 g1852_1 2.224404
+.ends
+
+.subckt netg2731 g2731_1 g2731_2 gnd
+C1  g2731_1 gnd 2.080806f
+C2  g2731_2 gnd 2.080806f
+R1 g2731_1 g2731_2 2.224404
+.ends
+
+.subckt netg3453 g3453_2 g3453_0 gnd
+C1  g3453_2 gnd 2.080806f
+C2  g3453_0 gnd 2.080806f
+R1 g3453_0 g3453_2 2.224404
+.ends
+
+.subckt netg1151 g1151_0 g1151_1 gnd
+C1  g1151_0 gnd 2.080806f
+C2  g1151_1 gnd 2.080806f
+R1 g1151_0 g1151_1 2.224404
+.ends
+
+.subckt netg1421 g1421_1 g1421_0 gnd
+C1  g1421_1 gnd 2.080806f
+C2  g1421_0 gnd 2.080806f
+R1 g1421_0 g1421_1 2.224404
+.ends
+
+.subckt netg3113 g3113_1 g3113_0 gnd
+C1  g3113_1 gnd 2.080806f
+C2  g3113_0 gnd 2.080806f
+R1 g3113_1 g3113_0 2.224404
+.ends
+
+.subckt netg3089 g3089_1 g3089_0 gnd
+C1  g3089_1 gnd 2.080806f
+C2  g3089_0 gnd 2.080806f
+R1 g3089_0 g3089_1 2.224404
+.ends
+
+.subckt netx192 x192_0 x192_1 gnd
+C1  x192_0 gnd 2.080806f
+C2  x192_1 gnd 2.080806f
+R1 x192_1 x192_0 2.224404
+.ends
+
+.subckt netg6000 g6000_1 g6000_0 gnd
+C1  g6000_1 gnd 2.080806f
+C2  g6000_0 gnd 2.080806f
+R1 g6000_0 g6000_1 2.224404
+.ends
+
+.subckt netg1573 g1573_0 g1573_1 gnd
+C1  g1573_0 gnd 2.080806f
+C2  g1573_1 gnd 2.080806f
+R1 g1573_0 g1573_1 2.224404
+.ends
+
+.subckt netg6373 g6373_1 g6373_0 gnd
+C1  g6373_1 gnd 2.080806f
+C2  g6373_0 gnd 2.080806f
+R1 g6373_0 g6373_1 2.224404
+.ends
+
+.subckt netg456 g456_0 g456_1 gnd
+C1  g456_0 gnd 2.080806f
+C2  g456_1 gnd 2.080806f
+R1 g456_1 g456_0 2.224404
+.ends
+
+.subckt netg3180 g3180_2 g3180_1 gnd
+C1  g3180_2 gnd 2.080806f
+C2  g3180_1 gnd 2.080806f
+R1 g3180_1 g3180_2 2.224404
+.ends
+
+.subckt netg5313 g5313_1 g5313_0 gnd
+C1  g5313_1 gnd 2.080806f
+C2  g5313_0 gnd 2.080806f
+R1 g5313_1 g5313_0 2.224404
+.ends
+
+.subckt netg6413 g6413_1 g6413_0 gnd
+C1  g6413_1 gnd 2.080806f
+C2  g6413_0 gnd 2.080806f
+R1 g6413_0 g6413_1 2.224404
+.ends
+
+.subckt netg4149 g4149_0 g4149_1 gnd
+C1  g4149_0 gnd 2.080806f
+C2  g4149_1 gnd 2.080806f
+R1 g4149_0 g4149_1 2.224404
+.ends
+
+.subckt netg6105 g6105_1 g6105_0 gnd
+C1  g6105_1 gnd 2.080806f
+C2  g6105_0 gnd 2.080806f
+R1 g6105_1 g6105_0 2.224404
+.ends
+
+.subckt netg6448 g6448_0 g6448_1 gnd
+C1  g6448_0 gnd 2.080806f
+C2  g6448_1 gnd 2.080806f
+R1 g6448_1 g6448_0 2.224404
+.ends
+
+.subckt netg4247 g4247_1 g4247_0 gnd
+C1  g4247_1 gnd 2.080806f
+C2  g4247_0 gnd 2.080806f
+R1 g4247_1 g4247_0 2.224404
+.ends
+
+.subckt netg7269 g7269_0 g7269_1 gnd
+C1  g7269_0 gnd 2.080806f
+C2  g7269_1 gnd 2.080806f
+R1 g7269_1 g7269_0 2.224404
+.ends
+
+.subckt netg4436 g4436_0 g4436_1 gnd
+C1  g4436_0 gnd 2.080806f
+C2  g4436_1 gnd 2.080806f
+R1 g4436_1 g4436_0 2.224404
+.ends
+
+.subckt netg7346 g7346_1 g7346_0 gnd
+C1  g7346_1 gnd 2.080806f
+C2  g7346_0 gnd 2.080806f
+R1 g7346_0 g7346_1 2.224404
+.ends
+
+.subckt netg5134 g5134_0 g5134_1 gnd
+C1  g5134_0 gnd 2.080806f
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+R1 g5134_1 g5134_0 2.224404
+.ends
+
+.subckt netg2822 g2822_1 g2822_0 gnd
+C1  g2822_1 gnd 2.080806f
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+.ends
+
+.subckt netg4403 g4403_0 g4403_1 gnd
+C1  g4403_0 gnd 2.080806f
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+R1 g4403_1 g4403_0 2.224404
+.ends
+
+.subckt netg3968 g3968_0 g3968_1 gnd
+C1  g3968_0 gnd 2.080806f
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+R1 g3968_1 g3968_0 2.224404
+.ends
+
+.subckt netg1308 g1308_0 g1308_1 gnd
+C1  g1308_0 gnd 2.080806f
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+R1 g1308_0 g1308_1 2.224404
+.ends
+
+.subckt netg1165 g1165_1 g1165_0 gnd
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+R1 g1165_1 g1165_0 2.224404
+.ends
+
+.subckt netg6976 g6976_0 g6976_1 gnd
+C1  g6976_0 gnd 2.080806f
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+R1 g6976_0 g6976_1 2.224404
+.ends
+
+.subckt netg3315 g3315_0 g3315_2 gnd
+C1  g3315_0 gnd 2.080806f
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+R1 g3315_0 g3315_2 2.224404
+.ends
+
+.subckt netg2749 g2749_0 g2749_1 gnd
+C1  g2749_0 gnd 2.080806f
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+.ends
+
+.subckt netg6732 g6732_1 g6732_0 gnd
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+.ends
+
+.subckt netg5634 g5634_2 g5634_1 gnd
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+.ends
+
+.subckt netg1380 g1380_1 g1380_0 gnd
+C1  g1380_1 gnd 2.080806f
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+R1 g1380_0 g1380_1 2.224404
+.ends
+
+.subckt netg6326 g6326_0 g6326_1 gnd
+C1  g6326_0 gnd 2.080806f
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+R1 g6326_0 g6326_1 2.224404
+.ends
+
+.subckt netg3225 g3225_0 g3225_2 gnd
+C1  g3225_0 gnd 2.080806f
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+R1 g3225_2 g3225_0 2.224404
+.ends
+
+.subckt netg7437 g7437_1 g7437_0 gnd
+C1  g7437_1 gnd 2.080806f
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+R1 g7437_0 g7437_1 2.224404
+.ends
+
+.subckt netx162 x162_0 x162_1 gnd
+C1  x162_0 gnd 2.080806f
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+R1 x162_1 x162_0 2.224404
+.ends
+
+.subckt netg6139 g6139_1 g6139_0 gnd
+C1  g6139_1 gnd 2.080806f
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+R1 g6139_1 g6139_0 2.224404
+.ends
+
+.subckt netg6106 g6106_1 g6106_0 gnd
+C1  g6106_1 gnd 2.080806f
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+R1 g6106_0 g6106_1 2.224404
+.ends
+
+.subckt netg1510 g1510_1 g1510_0 gnd
+C1  g1510_1 gnd 2.080806f
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+.ends
+
+.subckt netg1585 g1585_0 g1585_1 gnd
+C1  g1585_0 gnd 2.080806f
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+R1 g1585_0 g1585_1 2.224404
+.ends
+
+.subckt netg4047 g4047_0 g4047_1 gnd
+C1  g4047_0 gnd 2.080806f
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+R1 g4047_1 g4047_0 2.224404
+.ends
+
+.subckt netg5415 g5415_1 g5415_0 gnd
+C1  g5415_1 gnd 2.080806f
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+R1 g5415_1 g5415_0 2.224404
+.ends
+
+.subckt netg3897 g3897_1 g3897_0 gnd
+C1  g3897_1 gnd 2.080806f
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+R1 g3897_1 g3897_0 2.224404
+.ends
+
+.subckt netg6584 g6584_1 g6584_0 gnd
+C1  g6584_1 gnd 2.080806f
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+R1 g6584_1 g6584_0 2.224404
+.ends
+
+.subckt netg1815 g1815_1 g1815_0 gnd
+C1  g1815_1 gnd 2.080806f
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+R1 g1815_1 g1815_0 2.224404
+.ends
+
+.subckt netg6962 g6962_1 g6962_0 gnd
+C1  g6962_1 gnd 2.080806f
+C2  g6962_0 gnd 2.080806f
+R1 g6962_1 g6962_0 2.224404
+.ends
+
+.subckt netg5879 g5879_0 g5879_1 gnd
+C1  g5879_0 gnd 2.080806f
+C2  g5879_1 gnd 2.080806f
+R1 g5879_0 g5879_1 2.224404
+.ends
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+.subckt netg2486 g2486_1 g2486_2 gnd
+C1  g2486_1 gnd 2.080806f
+C2  g2486_2 gnd 2.080806f
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+.ends
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+.subckt netg4206 g4206_0 g4206_1 gnd
+C1  g4206_0 gnd 2.080806f
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+.ends
+
+.subckt netg4070 g4070_1 g4070_0 gnd
+C1  g4070_1 gnd 2.080806f
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+R1 g4070_0 g4070_1 2.224404
+.ends
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+.subckt netg7156 g7156_1 g7156_0 gnd
+C1  g7156_1 gnd 2.080806f
+C2  g7156_0 gnd 2.080806f
+R1 g7156_1 g7156_0 2.224404
+.ends
+
+.subckt netg1519 g1519_0 g1519_1 gnd
+C1  g1519_0 gnd 2.080806f
+C2  g1519_1 gnd 2.080806f
+R1 g1519_1 g1519_0 2.224404
+.ends
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+.subckt netg6669 g6669_0 g6669_1 gnd
+C1  g6669_0 gnd 2.080806f
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+R1 g6669_1 g6669_0 2.224404
+.ends
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+.subckt netg1492 g1492_1 g1492_0 gnd
+C1  g1492_1 gnd 2.080806f
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+R1 g1492_0 g1492_1 2.224404
+.ends
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+.subckt netg6272 g6272_0 g6272_1 gnd
+C1  g6272_0 gnd 2.080806f
+C2  g6272_1 gnd 2.080806f
+R1 g6272_1 g6272_0 2.224404
+.ends
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+.subckt netg1122 g1122_0 g1122_1 gnd
+C1  g1122_0 gnd 2.080806f
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+R1 g1122_1 g1122_0 2.224404
+.ends
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+.subckt netg5526 g5526_1 g5526_0 gnd
+C1  g5526_1 gnd 2.080806f
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+R1 g5526_0 g5526_1 2.224404
+.ends
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+.subckt netg3557 g3557_1 g3557_0 gnd
+C1  g3557_1 gnd 2.080806f
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+R1 g3557_1 g3557_0 2.224404
+.ends
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+.subckt netg3568 g3568_1 g3568_0 gnd
+C1  g3568_1 gnd 2.080806f
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+R1 g3568_0 g3568_1 2.224404
+.ends
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+.subckt netg6464 g6464_0 g6464_1 gnd
+C1  g6464_0 gnd 2.080806f
+C2  g6464_1 gnd 2.080806f
+R1 g6464_1 g6464_0 2.224404
+.ends
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+.subckt netg7129 g7129_0 g7129_1 gnd
+C1  g7129_0 gnd 2.080806f
+C2  g7129_1 gnd 2.080806f
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+.ends
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+.subckt netg4982 g4982_1 g4982_2 gnd
+C1  g4982_1 gnd 2.080806f
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+.ends
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+.subckt netg1134 g1134_1 g1134_0 gnd
+C1  g1134_1 gnd 2.080806f
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+R1 g1134_1 g1134_0 2.224404
+.ends
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+.subckt netg7099 g7099_0 g7099_1 gnd
+C1  g7099_0 gnd 2.080806f
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+.ends
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+.subckt netg6920 g6920_1 g6920_0 gnd
+C1  g6920_1 gnd 2.080806f
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+.ends
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+.subckt netg6011 g6011_1 g6011_0 gnd
+C1  g6011_1 gnd 2.080806f
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+.ends
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+.subckt netg1252 g1252_0 g1252_1 gnd
+C1  g1252_0 gnd 2.080806f
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+R1 g1252_1 g1252_0 2.224404
+.ends
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+.subckt netg6894 g6894_0 g6894_1 gnd
+C1  g6894_0 gnd 2.080806f
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+.ends
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+.subckt netg4067 g4067_1 g4067_0 gnd
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+.ends
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+.subckt netg1265 g1265_0 g1265_1 gnd
+C1  g1265_0 gnd 2.080806f
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+R1 g1265_0 g1265_1 2.224404
+.ends
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+.subckt netg5249 g5249_1 g5249_0 gnd
+C1  g5249_1 gnd 2.080806f
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+R1 g5249_0 g5249_1 2.224404
+.ends
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+.subckt netg4230 g4230_0 g4230_1 gnd
+C1  g4230_0 gnd 2.080806f
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+R1 g4230_0 g4230_1 2.224404
+.ends
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+.subckt netg4414 g4414_0 g4414_1 gnd
+C1  g4414_0 gnd 2.080806f
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+R1 g4414_0 g4414_1 2.224404
+.ends
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+.subckt netx221 x221_0 x221_1 gnd
+C1  x221_0 gnd 2.080806f
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+R1 x221_0 x221_1 2.224404
+.ends
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+.subckt netg3487 g3487_1 g3487_0 gnd
+C1  g3487_1 gnd 2.080806f
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+R1 g3487_1 g3487_0 2.224404
+.ends
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+.subckt netg6720 g6720_0 g6720_1 gnd
+C1  g6720_0 gnd 2.080806f
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+R1 g6720_0 g6720_1 2.224404
+.ends
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+.subckt netg1452 g1452_0 g1452_1 gnd
+C1  g1452_0 gnd 2.080806f
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+R1 g1452_1 g1452_0 2.224404
+.ends
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+.subckt netg6134 g6134_0 g6134_1 gnd
+C1  g6134_0 gnd 2.080806f
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+R1 g6134_1 g6134_0 2.224404
+.ends
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+.subckt netg3500 g3500_1 g3500_0 gnd
+C1  g3500_1 gnd 2.080806f
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+R1 g3500_1 g3500_0 2.224404
+.ends
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+.subckt netg4237 g4237_1 g4237_0 gnd
+C1  g4237_1 gnd 2.080806f
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+R1 g4237_0 g4237_1 2.224404
+.ends
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+.subckt netg4530 g4530_1 g4530_0 gnd
+C1  g4530_1 gnd 2.080806f
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+R1 g4530_1 g4530_0 2.224404
+.ends
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+.subckt netg6554 g6554_1 g6554_0 gnd
+C1  g6554_1 gnd 2.080806f
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+R1 g6554_1 g6554_0 2.224404
+.ends
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+.subckt netg7131 g7131_2 g7131_1 gnd
+C1  g7131_2 gnd 2.080806f
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+R1 g7131_1 g7131_2 2.224404
+.ends
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+.subckt netg6207 g6207_1 g6207_0 gnd
+C1  g6207_1 gnd 2.080806f
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+R1 g6207_1 g6207_0 2.224404
+.ends
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+.subckt netg4997 g4997_1 g4997_2 gnd
+C1  g4997_1 gnd 2.080806f
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+R1 g4997_2 g4997_1 2.224404
+.ends
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+.subckt netg5458 g5458_0 g5458_1 gnd
+C1  g5458_0 gnd 2.080806f
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+R1 g5458_1 g5458_0 2.224404
+.ends
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+.subckt netg7381 g7381_1 g7381_0 gnd
+C1  g7381_1 gnd 2.080806f
+C2  g7381_0 gnd 2.080806f
+R1 g7381_0 g7381_1 2.224404
+.ends
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+.subckt netg2404 g2404_1 g2404_0 gnd
+C1  g2404_1 gnd 2.080806f
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+R1 g2404_0 g2404_1 2.224404
+.ends
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+.subckt netg3468 g3468_1 g3468_0 gnd
+C1  g3468_1 gnd 2.080806f
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+R1 g3468_0 g3468_1 2.224404
+.ends
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+.subckt netg4256 g4256_1 g4256_0 gnd
+C1  g4256_1 gnd 2.080806f
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+R1 g4256_0 g4256_1 2.224404
+.ends
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+.subckt netg5298 g5298_1 g5298_0 gnd
+C1  g5298_1 gnd 2.080806f
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+R1 g5298_0 g5298_1 2.224404
+.ends
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+.subckt netg6141 g6141_1 g6141_0 gnd
+C1  g6141_1 gnd 2.080806f
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+R1 g6141_1 g6141_0 2.224404
+.ends
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+.subckt netg6175 g6175_0 g6175_1 gnd
+C1  g6175_0 gnd 2.080806f
+C2  g6175_1 gnd 2.080806f
+R1 g6175_0 g6175_1 2.224404
+.ends
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+.subckt netg1948 g1948_2 g1948_0 gnd
+C1  g1948_2 gnd 2.080806f
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+R1 g1948_0 g1948_2 2.224404
+.ends
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+.subckt netg5330 g5330_1 g5330_0 gnd
+C1  g5330_1 gnd 2.080806f
+C2  g5330_0 gnd 2.080806f
+R1 g5330_0 g5330_1 2.224404
+.ends
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+.subckt netg2786 g2786_0 g2786_1 gnd
+C1  g2786_0 gnd 2.080806f
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+R1 g2786_1 g2786_0 2.224404
+.ends
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+.subckt netg4226 g4226_0 g4226_1 gnd
+C1  g4226_0 gnd 2.080806f
+C2  g4226_1 gnd 2.080806f
+R1 g4226_1 g4226_0 2.224404
+.ends
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+.subckt netg5143 g5143_0 g5143_1 gnd
+C1  g5143_0 gnd 2.080806f
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+R1 g5143_0 g5143_1 2.224404
+.ends
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+.subckt netg2792 g2792_0 g2792_1 gnd
+C1  g2792_0 gnd 2.080806f
+C2  g2792_1 gnd 2.080806f
+R1 g2792_0 g2792_1 2.224404
+.ends
+
+.subckt netg6507 g6507_0 g6507_1 gnd
+C1  g6507_0 gnd 2.080806f
+C2  g6507_1 gnd 2.080806f
+R1 g6507_1 g6507_0 2.224404
+.ends
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+.subckt netg3570 g3570_1 g3570_0 gnd
+C1  g3570_1 gnd 2.080806f
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+R1 g3570_0 g3570_1 2.224404
+.ends
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+.subckt netg6259 g6259_2 g6259_1 gnd
+C1  g6259_2 gnd 2.080806f
+C2  g6259_1 gnd 2.080806f
+R1 g6259_2 g6259_1 2.224404
+.ends
+
+.subckt netg5606 g5606_1 g5606_0 gnd
+C1  g5606_1 gnd 2.080806f
+C2  g5606_0 gnd 2.080806f
+R1 g5606_0 g5606_1 2.224404
+.ends
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+.subckt netg2835 g2835_0 g2835_1 gnd
+C1  g2835_0 gnd 2.080806f
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+R1 g2835_0 g2835_1 2.224404
+.ends
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+.subckt netg1533 g1533_1 g1533_0 gnd
+C1  g1533_1 gnd 2.080806f
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+R1 g1533_1 g1533_0 2.224404
+.ends
+
+.subckt netg6820 g6820_1 g6820_0 gnd
+C1  g6820_1 gnd 2.080806f
+C2  g6820_0 gnd 2.080806f
+R1 g6820_1 g6820_0 2.224404
+.ends
+
+.subckt netg3547 g3547_0 g3547_1 gnd
+C1  g3547_0 gnd 2.080806f
+C2  g3547_1 gnd 2.080806f
+R1 g3547_1 g3547_0 2.224404
+.ends
+
+.subckt netg7347 g7347_0 g7347_1 gnd
+C1  g7347_0 gnd 2.080806f
+C2  g7347_1 gnd 2.080806f
+R1 g7347_1 g7347_0 2.224404
+.ends
+
+.subckt netg3717 g3717_1 g3717_0 gnd
+C1  g3717_1 gnd 2.080806f
+C2  g3717_0 gnd 2.080806f
+R1 g3717_0 g3717_1 2.224404
+.ends
+
+.subckt netg5592 g5592_1 g5592_0 gnd
+C1  g5592_1 gnd 2.080806f
+C2  g5592_0 gnd 2.080806f
+R1 g5592_1 g5592_0 2.224404
+.ends
+
+.subckt netg6073 g6073_0 g6073_1 gnd
+C1  g6073_0 gnd 2.080806f
+C2  g6073_1 gnd 2.080806f
+R1 g6073_0 g6073_1 2.224404
+.ends
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+.subckt netg4424 g4424_0 g4424_1 gnd
+C1  g4424_0 gnd 2.080806f
+C2  g4424_1 gnd 2.080806f
+R1 g4424_1 g4424_0 2.224404
+.ends
+
+.subckt netg1582 g1582_0 g1582_1 gnd
+C1  g1582_0 gnd 2.080806f
+C2  g1582_1 gnd 2.080806f
+R1 g1582_1 g1582_0 2.224404
+.ends
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+.subckt netg6902 g6902_0 g6902_1 gnd
+C1  g6902_0 gnd 2.080806f
+C2  g6902_1 gnd 2.080806f
+R1 g6902_0 g6902_1 2.224404
+.ends
+
+.subckt netg5706 g5706_1 g5706_0 gnd
+C1  g5706_1 gnd 2.080806f
+C2  g5706_0 gnd 2.080806f
+R1 g5706_0 g5706_1 2.224404
+.ends
+
+.subckt netg1227 g1227_1 g1227_0 gnd
+C1  g1227_1 gnd 2.080806f
+C2  g1227_0 gnd 2.080806f
+R1 g1227_1 g1227_0 2.224404
+.ends
+
+.subckt netg2846 g2846_0 g2846_1 gnd
+C1  g2846_0 gnd 2.080806f
+C2  g2846_1 gnd 2.080806f
+R1 g2846_1 g2846_0 2.224404
+.ends
+
+.subckt netg1173 g1173_0 g1173_1 gnd
+C1  g1173_0 gnd 2.080806f
+C2  g1173_1 gnd 2.080806f
+R1 g1173_1 g1173_0 2.224404
+.ends
+
+.subckt netg5769 g5769_1 g5769_0 gnd
+C1  g5769_1 gnd 2.080806f
+C2  g5769_0 gnd 2.080806f
+R1 g5769_0 g5769_1 2.224404
+.ends
+
+.subckt netg2785 g2785_0 g2785_1 gnd
+C1  g2785_0 gnd 2.080806f
+C2  g2785_1 gnd 2.080806f
+R1 g2785_0 g2785_1 2.224404
+.ends
+
+.subckt netg7332 g7332_1 g7332_0 gnd
+C1  g7332_1 gnd 2.080806f
+C2  g7332_0 gnd 2.080806f
+R1 g7332_0 g7332_1 2.224404
+.ends
+
+.subckt netg1481 g1481_1 g1481_0 gnd
+C1  g1481_1 gnd 2.080806f
+C2  g1481_0 gnd 2.080806f
+R1 g1481_1 g1481_0 2.224404
+.ends
+
+.subckt netg3541 g3541_1 g3541_0 gnd
+C1  g3541_1 gnd 2.080806f
+C2  g3541_0 gnd 2.080806f
+R1 g3541_0 g3541_1 2.224404
+.ends
+
+.subckt netg3096 g3096_2 g3096_1 gnd
+C1  g3096_2 gnd 2.080806f
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+R1 g3096_2 g3096_1 2.224404
+.ends
+
+.subckt netg4452 g4452_1 g4452_0 gnd
+C1  g4452_1 gnd 2.080806f
+C2  g4452_0 gnd 2.080806f
+R1 g4452_1 g4452_0 2.224404
+.ends
+
+.subckt netg7183 g7183_0 g7183_1 gnd
+C1  g7183_0 gnd 2.080806f
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+R1 g7183_1 g7183_0 2.224404
+.ends
+
+.subckt netg1457 g1457_1 g1457_0 gnd
+C1  g1457_1 gnd 2.080806f
+C2  g1457_0 gnd 2.080806f
+R1 g1457_1 g1457_0 2.224404
+.ends
+
+.subckt netg6737 g6737_1 g6737_0 gnd
+C1  g6737_1 gnd 2.080806f
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+R1 g6737_1 g6737_0 2.224404
+.ends
+
+.subckt netg7013 g7013_1 g7013_0 gnd
+C1  g7013_1 gnd 2.080806f
+C2  g7013_0 gnd 2.080806f
+R1 g7013_0 g7013_1 2.224404
+.ends
+
+.subckt netg6697 g6697_0 g6697_1 gnd
+C1  g6697_0 gnd 2.080806f
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+R1 g6697_1 g6697_0 2.224404
+.ends
+
+.subckt netg3915 g3915_1 g3915_0 gnd
+C1  g3915_1 gnd 2.080806f
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+R1 g3915_1 g3915_0 2.224404
+.ends
+
+.subckt netg6460 g6460_1 g6460_0 gnd
+C1  g6460_1 gnd 2.080806f
+C2  g6460_0 gnd 2.080806f
+R1 g6460_1 g6460_0 2.224404
+.ends
+
+.subckt netg5476 g5476_1 g5476_0 gnd
+C1  g5476_1 gnd 2.080806f
+C2  g5476_0 gnd 2.080806f
+R1 g5476_0 g5476_1 2.224404
+.ends
+
+.subckt netg5114 g5114_1 g5114_0 gnd
+C1  g5114_1 gnd 2.080806f
+C2  g5114_0 gnd 2.080806f
+R1 g5114_1 g5114_0 2.224404
+.ends
+
+.subckt netg7092 g7092_1 g7092_0 gnd
+C1  g7092_1 gnd 2.080806f
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+R1 g7092_1 g7092_0 2.224404
+.ends
+
+.subckt netg7249 g7249_0 g7249_1 gnd
+C1  g7249_0 gnd 2.080806f
+C2  g7249_1 gnd 2.080806f
+R1 g7249_0 g7249_1 2.224404
+.ends
+
+.subckt netg6244 g6244_0 g6244_1 gnd
+C1  g6244_0 gnd 2.080806f
+C2  g6244_1 gnd 2.080806f
+R1 g6244_0 g6244_1 2.224404
+.ends
+
+.subckt netg3578 g3578_1 g3578_0 gnd
+C1  g3578_1 gnd 2.080806f
+C2  g3578_0 gnd 2.080806f
+R1 g3578_0 g3578_1 2.224404
+.ends
+
+.subckt netx231 x231_0 x231_1 gnd
+C1  x231_0 gnd 2.080806f
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+R1 x231_0 x231_1 2.224404
+.ends
+
+.subckt netg7279 g7279_0 g7279_1 gnd
+C1  g7279_0 gnd 2.080806f
+C2  g7279_1 gnd 2.080806f
+R1 g7279_1 g7279_0 2.224404
+.ends
+
+.subckt netg6088 g6088_1 g6088_0 gnd
+C1  g6088_1 gnd 2.080806f
+C2  g6088_0 gnd 2.080806f
+R1 g6088_1 g6088_0 2.224404
+.ends
+
+.subckt netg5546 g5546_0 g5546_2 gnd
+C1  g5546_0 gnd 2.080806f
+C2  g5546_2 gnd 2.080806f
+R1 g5546_0 g5546_2 2.224404
+.ends
+
+.subckt netg6696 g6696_0 g6696_1 gnd
+C1  g6696_0 gnd 2.080806f
+C2  g6696_1 gnd 2.080806f
+R1 g6696_1 g6696_0 2.224404
+.ends
+
+.subckt netg4340 g4340_1 g4340_0 gnd
+C1  g4340_1 gnd 2.080806f
+C2  g4340_0 gnd 2.080806f
+R1 g4340_0 g4340_1 2.224404
+.ends
+
+.subckt netg6008 g6008_0 g6008_1 gnd
+C1  g6008_0 gnd 2.080806f
+C2  g6008_1 gnd 2.080806f
+R1 g6008_0 g6008_1 2.224404
+.ends
+
+.subckt netg7076 g7076_1 g7076_0 gnd
+C1  g7076_1 gnd 2.080806f
+C2  g7076_0 gnd 2.080806f
+R1 g7076_1 g7076_0 2.224404
+.ends
+
+.subckt netg5776 g5776_0 g5776_1 gnd
+C1  g5776_0 gnd 2.080806f
+C2  g5776_1 gnd 2.080806f
+R1 g5776_1 g5776_0 2.224404
+.ends
+
+.subckt netg6229 g6229_1 g6229_0 gnd
+C1  g6229_1 gnd 2.080806f
+C2  g6229_0 gnd 2.080806f
+R1 g6229_0 g6229_1 2.224404
+.ends
+
+.subckt netg1051 g1051_2 g1051_0 gnd
+C1  g1051_2 gnd 2.080806f
+C2  g1051_0 gnd 2.080806f
+R1 g1051_2 g1051_0 2.224404
+.ends
+
+.subckt netg2435 g2435_0 g2435_2 gnd
+C1  g2435_0 gnd 2.080806f
+C2  g2435_2 gnd 2.080806f
+R1 g2435_0 g2435_2 2.224404
+.ends
+
+.subckt netg3900 g3900_1 g3900_0 gnd
+C1  g3900_1 gnd 2.080806f
+C2  g3900_0 gnd 2.080806f
+R1 g3900_1 g3900_0 2.224404
+.ends
+
+.subckt netg455 g455_0 g455_1 gnd
+C1  g455_0 gnd 2.080806f
+C2  g455_1 gnd 2.080806f
+R1 g455_1 g455_0 2.224404
+.ends
+
+.subckt netg6684 g6684_0 g6684_1 gnd
+C1  g6684_0 gnd 2.080806f
+C2  g6684_1 gnd 2.080806f
+R1 g6684_1 g6684_0 2.224404
+.ends
+
+.subckt netg6006 g6006_1 g6006_0 gnd
+C1  g6006_1 gnd 2.080806f
+C2  g6006_0 gnd 2.080806f
+R1 g6006_1 g6006_0 2.224404
+.ends
+
+.subckt netg1314 g1314_1 g1314_0 gnd
+C1  g1314_1 gnd 2.080806f
+C2  g1314_0 gnd 2.080806f
+R1 g1314_1 g1314_0 2.224404
+.ends
+
+.subckt netg5238 g5238_1 g5238_0 gnd
+C1  g5238_1 gnd 2.080806f
+C2  g5238_0 gnd 2.080806f
+R1 g5238_1 g5238_0 2.224404
+.ends
+
+.subckt netg5538 g5538_1 g5538_0 gnd
+C1  g5538_1 gnd 2.080806f
+C2  g5538_0 gnd 2.080806f
+R1 g5538_0 g5538_1 2.224404
+.ends
+
+.subckt netg3573 g3573_1 g3573_0 gnd
+C1  g3573_1 gnd 2.080806f
+C2  g3573_0 gnd 2.080806f
+R1 g3573_0 g3573_1 2.224404
+.ends
+
+.subckt netg5362 g5362_1 g5362_0 gnd
+C1  g5362_1 gnd 2.080806f
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+R1 g5362_1 g5362_0 2.224404
+.ends
+
+.subckt netg5252 g5252_1 g5252_0 gnd
+C1  g5252_1 gnd 2.080806f
+C2  g5252_0 gnd 2.080806f
+R1 g5252_0 g5252_1 2.224404
+.ends
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+.subckt netg6135 g6135_0 g6135_1 gnd
+C1  g6135_0 gnd 2.080806f
+C2  g6135_1 gnd 2.080806f
+R1 g6135_1 g6135_0 2.224404
+.ends
+
+.subckt netg4023 g4023_0 g4023_1 gnd
+C1  g4023_0 gnd 2.080806f
+C2  g4023_1 gnd 2.080806f
+R1 g4023_1 g4023_0 2.224404
+.ends
+
+.subckt netg7442 g7442_1 g7442_0 gnd
+C1  g7442_1 gnd 2.080806f
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+R1 g7442_1 g7442_0 2.224404
+.ends
+
+.subckt netg910 g910_1 g910_2 gnd
+C1  g910_1 gnd 2.080806f
+C2  g910_2 gnd 2.080806f
+R1 g910_2 g910_1 2.224404
+.ends
+
+.subckt netg5671 g5671_1 g5671_2 gnd
+C1  g5671_1 gnd 2.080806f
+C2  g5671_2 gnd 2.080806f
+R1 g5671_2 g5671_1 2.224404
+.ends
+
+.subckt netg1929 g1929_0 g1929_1 gnd
+C1  g1929_0 gnd 2.080806f
+C2  g1929_1 gnd 2.080806f
+R1 g1929_1 g1929_0 2.224404
+.ends
+
+.subckt netg4137 g4137_0 g4137_1 gnd
+C1  g4137_0 gnd 2.080806f
+C2  g4137_1 gnd 2.080806f
+R1 g4137_0 g4137_1 2.224404
+.ends
+
+.subckt netg1359 g1359_0 g1359_1 gnd
+C1  g1359_0 gnd 2.080806f
+C2  g1359_1 gnd 2.080806f
+R1 g1359_0 g1359_1 2.224404
+.ends
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+.subckt netg6648 g6648_1 g6648_0 gnd
+C1  g6648_1 gnd 2.080806f
+C2  g6648_0 gnd 2.080806f
+R1 g6648_1 g6648_0 2.224404
+.ends
+
+.subckt netg6940 g6940_0 g6940_1 gnd
+C1  g6940_0 gnd 2.080806f
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+R1 g6940_0 g6940_1 2.224404
+.ends
+
+.subckt netg6099 g6099_0 g6099_1 gnd
+C1  g6099_0 gnd 2.080806f
+C2  g6099_1 gnd 2.080806f
+R1 g6099_0 g6099_1 2.224404
+.ends
+
+.subckt netg6362 g6362_1 g6362_0 gnd
+C1  g6362_1 gnd 2.080806f
+C2  g6362_0 gnd 2.080806f
+R1 g6362_0 g6362_1 2.224404
+.ends
+
+.subckt netg4321 g4321_0 g4321_1 gnd
+C1  g4321_0 gnd 2.080806f
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+R1 g4321_0 g4321_1 2.224404
+.ends
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+.subckt netg3920 g3920_1 g3920_0 gnd
+C1  g3920_1 gnd 2.080806f
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+R1 g3920_1 g3920_0 2.224404
+.ends
+
+.subckt netg5540 g5540_1 g5540_2 gnd
+C1  g5540_1 gnd 2.080806f
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+R1 g5540_1 g5540_2 2.224404
+.ends
+
+.subckt netg4160 g4160_0 g4160_1 gnd
+C1  g4160_0 gnd 2.080806f
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+R1 g4160_1 g4160_0 2.224404
+.ends
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+.subckt netg6936 g6936_1 g6936_0 gnd
+C1  g6936_1 gnd 2.080806f
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+R1 g6936_1 g6936_0 2.224404
+.ends
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+.subckt netg7185 g7185_1 g7185_0 gnd
+C1  g7185_1 gnd 2.080806f
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+R1 g7185_1 g7185_0 2.224404
+.ends
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+.subckt netg6665 g6665_0 g6665_1 gnd
+C1  g6665_0 gnd 2.080806f
+C2  g6665_1 gnd 2.080806f
+R1 g6665_1 g6665_0 2.224404
+.ends
+
+.subckt netg1939 g1939_0 g1939_1 gnd
+C1  g1939_0 gnd 2.080806f
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+R1 g1939_0 g1939_1 2.224404
+.ends
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+.subckt netg6996 g6996_1 g6996_0 gnd
+C1  g6996_1 gnd 2.080806f
+C2  g6996_0 gnd 2.080806f
+R1 g6996_1 g6996_0 2.224404
+.ends
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+.subckt netg6529 g6529_1 g6529_0 gnd
+C1  g6529_1 gnd 2.080806f
+C2  g6529_0 gnd 2.080806f
+R1 g6529_0 g6529_1 2.224404
+.ends
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+.subckt netg1232 g1232_0 g1232_1 gnd
+C1  g1232_0 gnd 2.080806f
+C2  g1232_1 gnd 2.080806f
+R1 g1232_0 g1232_1 2.224404
+.ends
+
+.subckt netg3529 g3529_1 g3529_0 gnd
+C1  g3529_1 gnd 2.080806f
+C2  g3529_0 gnd 2.080806f
+R1 g3529_0 g3529_1 2.224404
+.ends
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+.subckt netg6191 g6191_1 g6191_0 gnd
+C1  g6191_1 gnd 2.080806f
+C2  g6191_0 gnd 2.080806f
+R1 g6191_1 g6191_0 2.224404
+.ends
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+.subckt netg3198 g3198_1 g3198_2 gnd
+C1  g3198_1 gnd 2.080806f
+C2  g3198_2 gnd 2.080806f
+R1 g3198_2 g3198_1 2.224404
+.ends
+
+.subckt netg4328 g4328_0 g4328_1 gnd
+C1  g4328_0 gnd 2.080806f
+C2  g4328_1 gnd 2.080806f
+R1 g4328_0 g4328_1 2.224404
+.ends
+
+.subckt netg3514 g3514_1 g3514_0 gnd
+C1  g3514_1 gnd 2.080806f
+C2  g3514_0 gnd 2.080806f
+R1 g3514_0 g3514_1 2.224404
+.ends
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+.subckt netg7022 g7022_1 g7022_0 gnd
+C1  g7022_1 gnd 2.080806f
+C2  g7022_0 gnd 2.080806f
+R1 g7022_0 g7022_1 2.224404
+.ends
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+.subckt netg7198 g7198_0 g7198_1 gnd
+C1  g7198_0 gnd 2.080806f
+C2  g7198_1 gnd 2.080806f
+R1 g7198_0 g7198_1 2.224404
+.ends
+
+.subckt netg1431 g1431_0 g1431_1 gnd
+C1  g1431_0 gnd 2.080806f
+C2  g1431_1 gnd 2.080806f
+R1 g1431_0 g1431_1 2.224404
+.ends
+
+.subckt netg2701 g2701_1 g2701_2 gnd
+C1  g2701_1 gnd 2.080806f
+C2  g2701_2 gnd 2.080806f
+R1 g2701_1 g2701_2 2.224404
+.ends
+
+.subckt netg7353 g7353_1 g7353_0 gnd
+C1  g7353_1 gnd 2.080806f
+C2  g7353_0 gnd 2.080806f
+R1 g7353_0 g7353_1 2.224404
+.ends
+
+.subckt netg4053 g4053_0 g4053_1 gnd
+C1  g4053_0 gnd 2.080806f
+C2  g4053_1 gnd 2.080806f
+R1 g4053_1 g4053_0 2.224404
+.ends
+
+.subckt netg5410 g5410_0 g5410_1 gnd
+C1  g5410_0 gnd 2.080806f
+C2  g5410_1 gnd 2.080806f
+R1 g5410_0 g5410_1 2.224404
+.ends
+
+.subckt netg6525 g6525_1 g6525_0 gnd
+C1  g6525_1 gnd 2.080806f
+C2  g6525_0 gnd 2.080806f
+R1 g6525_1 g6525_0 2.224404
+.ends
+
+.subckt netx281 x281_1 x281_0 gnd
+C1  x281_1 gnd 2.080806f
+C2  x281_0 gnd 2.080806f
+R1 x281_1 x281_0 2.224404
+.ends
+
+.subckt netg4332 g4332_1 g4332_0 gnd
+C1  g4332_1 gnd 2.080806f
+C2  g4332_0 gnd 2.080806f
+R1 g4332_1 g4332_0 2.224404
+.ends
+
+.subckt netg2558 g2558_2 g2558_1 gnd
+C1  g2558_2 gnd 2.080806f
+C2  g2558_1 gnd 2.080806f
+R1 g2558_1 g2558_2 2.224404
+.ends
+
+.subckt netg2914 g2914_1 g2914_0 gnd
+C1  g2914_1 gnd 2.080806f
+C2  g2914_0 gnd 2.080806f
+R1 g2914_0 g2914_1 2.224404
+.ends
+
+.subckt netg7107 g7107_0 g7107_1 gnd
+C1  g7107_0 gnd 2.080806f
+C2  g7107_1 gnd 2.080806f
+R1 g7107_1 g7107_0 2.224404
+.ends
+
+.subckt netg6186 g6186_1 g6186_0 gnd
+C1  g6186_1 gnd 2.080806f
+C2  g6186_0 gnd 2.080806f
+R1 g6186_1 g6186_0 2.224404
+.ends
+
+.subckt netg7228 g7228_1 g7228_2 gnd
+C1  g7228_1 gnd 2.080806f
+C2  g7228_2 gnd 2.080806f
+R1 g7228_2 g7228_1 2.224404
+.ends
+
+.subckt netg4173 g4173_1 g4173_0 gnd
+C1  g4173_1 gnd 2.080806f
+C2  g4173_0 gnd 2.080806f
+R1 g4173_0 g4173_1 2.224404
+.ends
+
+.subckt netg6356 g6356_1 g6356_0 gnd
+C1  g6356_1 gnd 2.080806f
+C2  g6356_0 gnd 2.080806f
+R1 g6356_0 g6356_1 2.224404
+.ends
+
+.subckt netg6317 g6317_0 g6317_1 gnd
+C1  g6317_0 gnd 2.080806f
+C2  g6317_1 gnd 2.080806f
+R1 g6317_1 g6317_0 2.224404
+.ends
+
+.subckt netg5443 g5443_1 g5443_0 gnd
+C1  g5443_1 gnd 2.080806f
+C2  g5443_0 gnd 2.080806f
+R1 g5443_1 g5443_0 2.224404
+.ends
+
+.subckt netg1999 g1999_0 g1999_1 gnd
+C1  g1999_0 gnd 2.080806f
+C2  g1999_1 gnd 2.080806f
+R1 g1999_0 g1999_1 2.224404
+.ends
+
+.subckt netg6163 g6163_1 g6163_0 gnd
+C1  g6163_1 gnd 2.080806f
+C2  g6163_0 gnd 2.080806f
+R1 g6163_1 g6163_0 2.224404
+.ends
+
+.subckt netg6731 g6731_0 g6731_1 gnd
+C1  g6731_0 gnd 2.080806f
+C2  g6731_1 gnd 2.080806f
+R1 g6731_0 g6731_1 2.224404
+.ends
+
+.subckt netg4134 g4134_1 g4134_0 gnd
+C1  g4134_1 gnd 2.080806f
+C2  g4134_0 gnd 2.080806f
+R1 g4134_0 g4134_1 2.224404
+.ends
+
+.subckt netg1162 g1162_1 g1162_0 gnd
+C1  g1162_1 gnd 2.080806f
+C2  g1162_0 gnd 2.080806f
+R1 g1162_0 g1162_1 2.224404
+.ends
+
+.subckt netg6298 g6298_0 g6298_1 gnd
+C1  g6298_0 gnd 2.080806f
+C2  g6298_1 gnd 2.080806f
+R1 g6298_0 g6298_1 2.224404
+.ends
+
+.subckt netg4286 g4286_0 g4286_1 gnd
+C1  g4286_0 gnd 2.080806f
+C2  g4286_1 gnd 2.080806f
+R1 g4286_1 g4286_0 2.224404
+.ends
+
+.subckt netg6694 g6694_1 g6694_0 gnd
+C1  g6694_1 gnd 2.080806f
+C2  g6694_0 gnd 2.080806f
+R1 g6694_1 g6694_0 2.224404
+.ends
+
+.subckt netg1408 g1408_0 g1408_1 gnd
+C1  g1408_0 gnd 2.080806f
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+R1 g1408_0 g1408_1 2.224404
+.ends
+
+.subckt netg6087 g6087_0 g6087_1 gnd
+C1  g6087_0 gnd 2.080806f
+C2  g6087_1 gnd 2.080806f
+R1 g6087_1 g6087_0 2.224404
+.ends
+
+.subckt netg1231 g1231_0 g1231_1 gnd
+C1  g1231_0 gnd 2.080806f
+C2  g1231_1 gnd 2.080806f
+R1 g1231_0 g1231_1 2.224404
+.ends
+
+.subckt netx402 x402_1 x402_0 gnd
+C1  x402_1 gnd 2.080806f
+C2  x402_0 gnd 2.080806f
+R1 x402_1 x402_0 2.224404
+.ends
+
+.subckt netg5423 g5423_0 g5423_1 gnd
+C1  g5423_0 gnd 2.080806f
+C2  g5423_1 gnd 2.080806f
+R1 g5423_0 g5423_1 2.224404
+.ends
+
+.subckt netg5992 g5992_0 g5992_1 gnd
+C1  g5992_0 gnd 2.080806f
+C2  g5992_1 gnd 2.080806f
+R1 g5992_0 g5992_1 2.224404
+.ends
+
+.subckt netg3508 g3508_1 g3508_0 gnd
+C1  g3508_1 gnd 2.080806f
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+R1 g3508_0 g3508_1 2.224404
+.ends
+
+.subckt netg2823 g2823_0 g2823_1 gnd
+C1  g2823_0 gnd 2.080806f
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+R1 g2823_0 g2823_1 2.224404
+.ends
+
+.subckt netg6169 g6169_0 g6169_1 gnd
+C1  g6169_0 gnd 2.080806f
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+R1 g6169_0 g6169_1 2.224404
+.ends
+
+.subckt netg4062 g4062_1 g4062_0 gnd
+C1  g4062_1 gnd 2.080806f
+C2  g4062_0 gnd 2.080806f
+R1 g4062_1 g4062_0 2.224404
+.ends
+
+.subckt netg4129 g4129_0 g4129_1 gnd
+C1  g4129_0 gnd 2.080806f
+C2  g4129_1 gnd 2.080806f
+R1 g4129_1 g4129_0 2.224404
+.ends
+
+.subckt netg2795 g2795_0 g2795_1 gnd
+C1  g2795_0 gnd 2.080806f
+C2  g2795_1 gnd 2.080806f
+R1 g2795_1 g2795_0 2.224404
+.ends
+
+.subckt netg2923 g2923_1 g2923_0 gnd
+C1  g2923_1 gnd 2.080806f
+C2  g2923_0 gnd 2.080806f
+R1 g2923_0 g2923_1 2.224404
+.ends
+
+.subckt netg4203 g4203_0 g4203_1 gnd
+C1  g4203_0 gnd 2.080806f
+C2  g4203_1 gnd 2.080806f
+R1 g4203_1 g4203_0 2.224404
+.ends
+
+.subckt netg4057 g4057_1 g4057_0 gnd
+C1  g4057_1 gnd 2.080806f
+C2  g4057_0 gnd 2.080806f
+R1 g4057_0 g4057_1 2.224404
+.ends
+
+.subckt netg1886 g1886_1 g1886_0 gnd
+C1  g1886_1 gnd 2.080806f
+C2  g1886_0 gnd 2.080806f
+R1 g1886_1 g1886_0 2.224404
+.ends
+
+.subckt netx121 x121_1 x121_0 gnd
+C1  x121_1 gnd 2.080806f
+C2  x121_0 gnd 2.080806f
+R1 x121_1 x121_0 2.224404
+.ends
+
+.subckt netg5994 g5994_1 g5994_0 gnd
+C1  g5994_1 gnd 2.080806f
+C2  g5994_0 gnd 2.080806f
+R1 g5994_0 g5994_1 2.224404
+.ends
+
+.subckt netg6395 g6395_0 g6395_1 gnd
+C1  g6395_0 gnd 2.080806f
+C2  g6395_1 gnd 2.080806f
+R1 g6395_1 g6395_0 2.224404
+.ends
+
+.subckt netg6166 g6166_1 g6166_0 gnd
+C1  g6166_1 gnd 2.080806f
+C2  g6166_0 gnd 2.080806f
+R1 g6166_1 g6166_0 2.224404
+.ends
+
+.subckt netg1921 g1921_1 g1921_0 gnd
+C1  g1921_1 gnd 2.080806f
+C2  g1921_0 gnd 2.080806f
+R1 g1921_0 g1921_1 2.224404
+.ends
+
+.subckt netx291 x291_1 x291_0 gnd
+C1  x291_1 gnd 2.080806f
+C2  x291_0 gnd 2.080806f
+R1 x291_1 x291_0 2.224404
+.ends
+
+.subckt netg5982 g5982_1 g5982_0 gnd
+C1  g5982_1 gnd 2.080806f
+C2  g5982_0 gnd 2.080806f
+R1 g5982_0 g5982_1 2.224404
+.ends
+
+.subckt netg5408 g5408_0 g5408_1 gnd
+C1  g5408_0 gnd 2.080806f
+C2  g5408_1 gnd 2.080806f
+R1 g5408_0 g5408_1 2.224404
+.ends
+
+.subckt netg6333 g6333_1 g6333_0 gnd
+C1  g6333_1 gnd 2.080806f
+C2  g6333_0 gnd 2.080806f
+R1 g6333_0 g6333_1 2.224404
+.ends
+
+.subckt netg1168 g1168_1 g1168_0 gnd
+C1  g1168_1 gnd 2.080806f
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+R1 g1168_1 g1168_0 2.224404
+.ends
+
+.subckt netg1394 g1394_1 g1394_0 gnd
+C1  g1394_1 gnd 2.080806f
+C2  g1394_0 gnd 2.080806f
+R1 g1394_1 g1394_0 2.224404
+.ends
+
+.subckt netg6440 g6440_0 g6440_1 gnd
+C1  g6440_0 gnd 2.080806f
+C2  g6440_1 gnd 2.080806f
+R1 g6440_1 g6440_0 2.224404
+.ends
+
+.subckt netg5354 g5354_1 g5354_0 gnd
+C1  g5354_1 gnd 2.080806f
+C2  g5354_0 gnd 2.080806f
+R1 g5354_0 g5354_1 2.224404
+.ends
+
+.subckt netg6437 g6437_0 g6437_1 gnd
+C1  g6437_0 gnd 2.080806f
+C2  g6437_1 gnd 2.080806f
+R1 g6437_0 g6437_1 2.224404
+.ends
+
+.subckt netg865 g865_1 g865_2 gnd
+C1  g865_1 gnd 2.080806f
+C2  g865_2 gnd 2.080806f
+R1 g865_2 g865_1 2.224404
+.ends
+
+.subckt netg2931 g2931_0 g2931_1 gnd
+C1  g2931_0 gnd 2.080806f
+C2  g2931_1 gnd 2.080806f
+R1 g2931_0 g2931_1 2.224404
+.ends
+
+.subckt netg5135 g5135_0 g5135_1 gnd
+C1  g5135_0 gnd 2.080806f
+C2  g5135_1 gnd 2.080806f
+R1 g5135_1 g5135_0 2.224404
+.ends
+
+.subckt netg6994 g6994_1 g6994_0 gnd
+C1  g6994_1 gnd 2.080806f
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+R1 g6994_1 g6994_0 2.224404
+.ends
+
+.subckt netg6194 g6194_1 g6194_0 gnd
+C1  g6194_1 gnd 2.080806f
+C2  g6194_0 gnd 2.080806f
+R1 g6194_0 g6194_1 2.224404
+.ends
+
+.subckt netg752 g752_1 g752_0 gnd
+C1  g752_1 gnd 2.080806f
+C2  g752_0 gnd 2.080806f
+R1 g752_1 g752_0 2.224404
+.ends
+
+.subckt netg7270 g7270_1 g7270_0 gnd
+C1  g7270_1 gnd 2.080806f
+C2  g7270_0 gnd 2.080806f
+R1 g7270_1 g7270_0 2.224404
+.ends
+
+.subckt netx11 x11_1 x11_0 gnd
+C1  x11_1 gnd 2.080806f
+C2  x11_0 gnd 2.080806f
+R1 x11_1 x11_0 2.224404
+.ends
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+.subckt netg4108 g4108_0 g4108_1 gnd
+C1  g4108_0 gnd 2.080806f
+C2  g4108_1 gnd 2.080806f
+R1 g4108_0 g4108_1 2.224404
+.ends
+
+.subckt netg6502 g6502_2 g6502_0 gnd
+C1  g6502_2 gnd 2.080806f
+C2  g6502_0 gnd 2.080806f
+R1 g6502_0 g6502_2 2.224404
+.ends
+
+.subckt netg3904 g3904_1 g3904_0 gnd
+C1  g3904_1 gnd 2.080806f
+C2  g3904_0 gnd 2.080806f
+R1 g3904_1 g3904_0 2.224404
+.ends
+
+.subckt netg1382 g1382_1 g1382_0 gnd
+C1  g1382_1 gnd 2.080806f
+C2  g1382_0 gnd 2.080806f
+R1 g1382_1 g1382_0 2.224404
+.ends
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+.subckt netg3497 g3497_1 g3497_0 gnd
+C1  g3497_1 gnd 2.080806f
+C2  g3497_0 gnd 2.080806f
+R1 g3497_1 g3497_0 2.224404
+.ends
+
+.subckt netg6587 g6587_1 g6587_0 gnd
+C1  g6587_1 gnd 2.080806f
+C2  g6587_0 gnd 2.080806f
+R1 g6587_1 g6587_0 2.224404
+.ends
+
+.subckt netg4242 g4242_1 g4242_0 gnd
+C1  g4242_1 gnd 2.080806f
+C2  g4242_0 gnd 2.080806f
+R1 g4242_1 g4242_0 2.224404
+.ends
+
+.subckt netg4121 g4121_0 g4121_2 gnd
+C1  g4121_0 gnd 2.080806f
+C2  g4121_2 gnd 2.080806f
+R1 g4121_2 g4121_0 2.224404
+.ends
+
+.subckt netg3081 g3081_0 g3081_1 gnd
+C1  g3081_0 gnd 2.080806f
+C2  g3081_1 gnd 2.080806f
+R1 g3081_1 g3081_0 2.224404
+.ends
+
+.subckt netg6549 g6549_1 g6549_0 gnd
+C1  g6549_1 gnd 2.080806f
+C2  g6549_0 gnd 2.080806f
+R1 g6549_1 g6549_0 2.224404
+.ends
+
+.subckt netg3129 g3129_2 g3129_1 gnd
+C1  g3129_2 gnd 2.080806f
+C2  g3129_1 gnd 2.080806f
+R1 g3129_1 g3129_2 2.224404
+.ends
+
+.subckt netg1934 g1934_0 g1934_1 gnd
+C1  g1934_0 gnd 2.080806f
+C2  g1934_1 gnd 2.080806f
+R1 g1934_1 g1934_0 2.224404
+.ends
+
+.subckt netg3577 g3577_1 g3577_0 gnd
+C1  g3577_1 gnd 2.080806f
+C2  g3577_0 gnd 2.080806f
+R1 g3577_0 g3577_1 2.224404
+.ends
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+.subckt netg2793 g2793_1 g2793_0 gnd
+C1  g2793_1 gnd 2.080806f
+C2  g2793_0 gnd 2.080806f
+R1 g2793_0 g2793_1 2.224404
+.ends
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+.subckt netg5604 g5604_1 g5604_0 gnd
+C1  g5604_1 gnd 2.080806f
+C2  g5604_0 gnd 2.080806f
+R1 g5604_0 g5604_1 2.224404
+.ends
+
+.subckt netg1925 g1925_0 g1925_1 gnd
+C1  g1925_0 gnd 2.080806f
+C2  g1925_1 gnd 2.080806f
+R1 g1925_1 g1925_0 2.224404
+.ends
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+.subckt netg4264 g4264_0 g4264_1 gnd
+C1  g4264_0 gnd 2.080806f
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+R1 g4264_0 g4264_1 2.224404
+.ends
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+.subckt netg6586 g6586_0 g6586_1 gnd
+C1  g6586_0 gnd 2.080806f
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+R1 g6586_1 g6586_0 2.224404
+.ends
+
+.subckt netg4223 g4223_0 g4223_1 gnd
+C1  g4223_0 gnd 2.080806f
+C2  g4223_1 gnd 2.080806f
+R1 g4223_1 g4223_0 2.224404
+.ends
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+.subckt netg3565 g3565_0 g3565_1 gnd
+C1  g3565_0 gnd 2.080806f
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+R1 g3565_0 g3565_1 2.224404
+.ends
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+.subckt netg6390 g6390_0 g6390_1 gnd
+C1  g6390_0 gnd 2.080806f
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+R1 g6390_0 g6390_1 2.224404
+.ends
+
+.subckt netg7025 g7025_1 g7025_0 gnd
+C1  g7025_1 gnd 2.080806f
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+R1 g7025_0 g7025_1 2.224404
+.ends
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+.subckt netg3049 g3049_1 g3049_0 gnd
+C1  g3049_1 gnd 2.080806f
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+R1 g3049_0 g3049_1 2.224404
+.ends
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+.subckt netg6743 g6743_1 g6743_0 gnd
+C1  g6743_1 gnd 2.080806f
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+R1 g6743_1 g6743_0 2.224404
+.ends
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+.subckt netg6101 g6101_1 g6101_0 gnd
+C1  g6101_1 gnd 2.080806f
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+R1 g6101_0 g6101_1 2.224404
+.ends
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+.subckt netg1228 g1228_1 g1228_0 gnd
+C1  g1228_1 gnd 2.080806f
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+R1 g1228_0 g1228_1 2.224404
+.ends
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+.subckt netg6451 g6451_1 g6451_0 gnd
+C1  g6451_1 gnd 2.080806f
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+R1 g6451_0 g6451_1 2.224404
+.ends
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+.subckt netg2790 g2790_1 g2790_0 gnd
+C1  g2790_1 gnd 2.080806f
+C2  g2790_0 gnd 2.080806f
+R1 g2790_0 g2790_1 2.224404
+.ends
+
+.subckt netg3067 g3067_0 g3067_1 gnd
+C1  g3067_0 gnd 2.080806f
+C2  g3067_1 gnd 2.080806f
+R1 g3067_1 g3067_0 2.224404
+.ends
+
+.subckt netg6138 g6138_0 g6138_1 gnd
+C1  g6138_0 gnd 2.080806f
+C2  g6138_1 gnd 2.080806f
+R1 g6138_1 g6138_0 2.224404
+.ends
+
+.subckt netx371 x371_1 x371_0 gnd
+C1  x371_1 gnd 2.080806f
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+R1 x371_1 x371_0 2.224404
+.ends
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+.subckt netg1172 g1172_0 g1172_1 gnd
+C1  g1172_0 gnd 2.080806f
+C2  g1172_1 gnd 2.080806f
+R1 g1172_1 g1172_0 2.224404
+.ends
+
+.subckt netg2762 g2762_1 g2762_0 gnd
+C1  g2762_1 gnd 2.080806f
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+R1 g2762_1 g2762_0 2.224404
+.ends
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+.subckt netg5599 g5599_1 g5599_0 gnd
+C1  g5599_1 gnd 2.080806f
+C2  g5599_0 gnd 2.080806f
+R1 g5599_0 g5599_1 2.224404
+.ends
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+.subckt netg5364 g5364_0 g5364_1 gnd
+C1  g5364_0 gnd 2.080806f
+C2  g5364_1 gnd 2.080806f
+R1 g5364_0 g5364_1 2.224404
+.ends
+
+.subckt netg5318 g5318_0 g5318_1 gnd
+C1  g5318_0 gnd 2.080806f
+C2  g5318_1 gnd 2.080806f
+R1 g5318_1 g5318_0 2.224404
+.ends
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+.subckt netg6539 g6539_0 g6539_1 gnd
+C1  g6539_0 gnd 2.080806f
+C2  g6539_1 gnd 2.080806f
+R1 g6539_1 g6539_0 2.224404
+.ends
+
+.subckt netg6742 g6742_0 g6742_1 gnd
+C1  g6742_0 gnd 2.080806f
+C2  g6742_1 gnd 2.080806f
+R1 g6742_1 g6742_0 2.224404
+.ends
+
+.subckt netg7082 g7082_0 g7082_1 gnd
+C1  g7082_0 gnd 2.080806f
+C2  g7082_1 gnd 2.080806f
+R1 g7082_0 g7082_1 2.224404
+.ends
+
+.subckt netg1930 g1930_0 g1930_1 gnd
+C1  g1930_0 gnd 2.080806f
+C2  g1930_1 gnd 2.080806f
+R1 g1930_1 g1930_0 2.224404
+.ends
+
+.subckt netg4336 g4336_1 g4336_0 gnd
+C1  g4336_1 gnd 2.080806f
+C2  g4336_0 gnd 2.080806f
+R1 g4336_0 g4336_1 2.224404
+.ends
+
+.subckt netg4529 g4529_1 g4529_0 gnd
+C1  g4529_1 gnd 2.080806f
+C2  g4529_0 gnd 2.080806f
+R1 g4529_1 g4529_0 2.224404
+.ends
+
+.subckt netg5596 g5596_1 g5596_0 gnd
+C1  g5596_1 gnd 2.080806f
+C2  g5596_0 gnd 2.080806f
+R1 g5596_0 g5596_1 2.224404
+.ends
+
+.subckt netg1369 g1369_2 g1369_0 gnd
+C1  g1369_2 gnd 2.080806f
+C2  g1369_0 gnd 2.080806f
+R1 g1369_2 g1369_0 2.224404
+.ends
+
+.subckt netx512 x512_1 x512_0 gnd
+C1  x512_1 gnd 2.080806f
+C2  x512_0 gnd 2.080806f
+R1 x512_1 x512_0 2.224404
+.ends
+
+.subckt netg4058 g4058_0 g4058_1 gnd
+C1  g4058_0 gnd 2.080806f
+C2  g4058_1 gnd 2.080806f
+R1 g4058_0 g4058_1 2.224404
+.ends
+
+.subckt netg1906 g1906_1 g1906_0 gnd
+C1  g1906_1 gnd 2.080806f
+C2  g1906_0 gnd 2.080806f
+R1 g1906_1 g1906_0 2.224404
+.ends
+
+.subckt netg4402 g4402_0 g4402_1 gnd
+C1  g4402_0 gnd 2.080806f
+C2  g4402_1 gnd 2.080806f
+R1 g4402_0 g4402_1 2.224404
+.ends
+
+.subckt netg2833 g2833_1 g2833_0 gnd
+C1  g2833_1 gnd 2.080806f
+C2  g2833_0 gnd 2.080806f
+R1 g2833_0 g2833_1 2.224404
+.ends
+
+.subckt netg5775 g5775_1 g5775_0 gnd
+C1  g5775_1 gnd 2.080806f
+C2  g5775_0 gnd 2.080806f
+R1 g5775_1 g5775_0 2.224404
+.ends
+
+.subckt netg2998 g2998_1 g2998_0 gnd
+C1  g2998_1 gnd 2.080806f
+C2  g2998_0 gnd 2.080806f
+R1 g2998_1 g2998_0 2.224404
+.ends
+
+.subckt netg3556 g3556_0 g3556_1 gnd
+C1  g3556_0 gnd 2.080806f
+C2  g3556_1 gnd 2.080806f
+R1 g3556_0 g3556_1 2.224404
+.ends
+
+.subckt netg3365 g3365_0 g3365_1 gnd
+C1  g3365_0 gnd 2.080806f
+C2  g3365_1 gnd 2.080806f
+R1 g3365_0 g3365_1 2.224404
+.ends
+
+.subckt netg5511 g5511_0 g5511_1 gnd
+C1  g5511_0 gnd 2.080806f
+C2  g5511_1 gnd 2.080806f
+R1 g5511_0 g5511_1 2.224404
+.ends
+
+.subckt netg1251 g1251_0 g1251_1 gnd
+C1  g1251_0 gnd 2.080806f
+C2  g1251_1 gnd 2.080806f
+R1 g1251_1 g1251_0 2.224404
+.ends
+
+.subckt netg4110 g4110_1 g4110_0 gnd
+C1  g4110_1 gnd 2.080806f
+C2  g4110_0 gnd 2.080806f
+R1 g4110_1 g4110_0 2.224404
+.ends
+
+.subckt netg6649 g6649_1 g6649_0 gnd
+C1  g6649_1 gnd 2.080806f
+C2  g6649_0 gnd 2.080806f
+R1 g6649_0 g6649_1 2.224404
+.ends
+
+.subckt netg5674 g5674_0 g5674_2 gnd
+C1  g5674_0 gnd 2.080806f
+C2  g5674_2 gnd 2.080806f
+R1 g5674_0 g5674_2 2.224404
+.ends
+
+.subckt netg6150 g6150_1 g6150_0 gnd
+C1  g6150_1 gnd 2.080806f
+C2  g6150_0 gnd 2.080806f
+R1 g6150_0 g6150_1 2.224404
+.ends
+
+.subckt netg7340 g7340_0 g7340_1 gnd
+C1  g7340_0 gnd 2.080806f
+C2  g7340_1 gnd 2.080806f
+R1 g7340_0 g7340_1 2.224404
+.ends
+
+.subckt netg1033 g1033_2 g1033_1 gnd
+C1  g1033_2 gnd 2.080806f
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+R1 g1033_2 g1033_1 2.224404
+.ends
+
+.subckt netg6208 g6208_1 g6208_0 gnd
+C1  g6208_1 gnd 2.080806f
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+R1 g6208_0 g6208_1 2.224404
+.ends
+
+.subckt netg5969 g5969_1 g5969_0 gnd
+C1  g5969_1 gnd 2.080806f
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+R1 g5969_0 g5969_1 2.224404
+.ends
+
+.subckt netg6662 g6662_0 g6662_1 gnd
+C1  g6662_0 gnd 2.080806f
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+R1 g6662_1 g6662_0 2.224404
+.ends
+
+.subckt netg4132 g4132_1 g4132_0 gnd
+C1  g4132_1 gnd 2.080806f
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+R1 g4132_1 g4132_0 2.224404
+.ends
+
+.subckt netg5417 g5417_1 g5417_0 gnd
+C1  g5417_1 gnd 2.080806f
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+R1 g5417_1 g5417_0 2.224404
+.ends
+
+.subckt netg3109 g3109_0 g3109_1 gnd
+C1  g3109_0 gnd 2.080806f
+C2  g3109_1 gnd 2.080806f
+R1 g3109_0 g3109_1 2.224404
+.ends
+
+.subckt netg2815 g2815_0 g2815_1 gnd
+C1  g2815_0 gnd 2.080806f
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+R1 g2815_0 g2815_1 2.224404
+.ends
+
+.subckt netg7045 g7045_0 g7045_1 gnd
+C1  g7045_0 gnd 2.080806f
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+R1 g7045_1 g7045_0 2.224404
+.ends
+
+.subckt netg3974 g3974_0 g3974_1 gnd
+C1  g3974_0 gnd 2.080806f
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+R1 g3974_1 g3974_0 2.224404
+.ends
+
+.subckt netx481 x481_0 x481_1 gnd
+C1  x481_0 gnd 2.080806f
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+R1 x481_1 x481_0 2.224404
+.ends
+
+.subckt netx412 x412_1 x412_0 gnd
+C1  x412_1 gnd 2.080806f
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+R1 x412_1 x412_0 2.224404
+.ends
+
+.subckt netg6624 g6624_1 g6624_0 gnd
+C1  g6624_1 gnd 2.080806f
+C2  g6624_0 gnd 2.080806f
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+.ends
+
+.subckt netg5392 g5392_1 g5392_0 gnd
+C1  g5392_1 gnd 2.080806f
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+.ends
+
+.subckt netg3477 g3477_1 g3477_0 gnd
+C1  g3477_1 gnd 2.080806f
+C2  g3477_0 gnd 2.080806f
+R1 g3477_1 g3477_0 2.224404
+.ends
+
+.subckt netg1230 g1230_1 g1230_0 gnd
+C1  g1230_1 gnd 2.080806f
+C2  g1230_0 gnd 2.080806f
+R1 g1230_0 g1230_1 2.224404
+.ends
+
+.subckt netg2944 g2944_0 g2944_1 gnd
+C1  g2944_0 gnd 2.080806f
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+R1 g2944_0 g2944_1 2.224404
+.ends
+
+.subckt netg4334 g4334_1 g4334_0 gnd
+C1  g4334_1 gnd 2.080806f
+C2  g4334_0 gnd 2.080806f
+R1 g4334_0 g4334_1 2.224404
+.ends
+
+.subckt netg3682 g3682_0 g3682_1 gnd
+C1  g3682_0 gnd 2.080806f
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+R1 g3682_0 g3682_1 2.224404
+.ends
+
+.subckt netg7396 g7396_1 g7396_0 gnd
+C1  g7396_1 gnd 2.080806f
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+R1 g7396_1 g7396_0 2.224404
+.ends
+
+.subckt netg1480 g1480_0 g1480_1 gnd
+C1  g1480_0 gnd 2.080806f
+C2  g1480_1 gnd 2.080806f
+R1 g1480_0 g1480_1 2.224404
+.ends
+
+.subckt netg2780 g2780_1 g2780_0 gnd
+C1  g2780_1 gnd 2.080806f
+C2  g2780_0 gnd 2.080806f
+R1 g2780_0 g2780_1 2.224404
+.ends
+
+.subckt netg4299 g4299_1 g4299_0 gnd
+C1  g4299_1 gnd 2.080806f
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+R1 g4299_1 g4299_0 2.224404
+.ends
+
+.subckt netg7186 g7186_1 g7186_0 gnd
+C1  g7186_1 gnd 2.080806f
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+R1 g7186_0 g7186_1 2.224404
+.ends
+
+.subckt netg4308 g4308_1 g4308_0 gnd
+C1  g4308_1 gnd 2.080806f
+C2  g4308_0 gnd 2.080806f
+R1 g4308_0 g4308_1 2.224404
+.ends
+
+.subckt netg2707 g2707_0 g2707_2 gnd
+C1  g2707_0 gnd 2.080806f
+C2  g2707_2 gnd 2.080806f
+R1 g2707_2 g2707_0 2.224404
+.ends
+
+.subckt netg7272 g7272_0 g7272_1 gnd
+C1  g7272_0 gnd 2.080806f
+C2  g7272_1 gnd 2.080806f
+R1 g7272_1 g7272_0 2.224404
+.ends
+
+.subckt netg6873 g6873_1 g6873_0 gnd
+C1  g6873_1 gnd 2.080806f
+C2  g6873_0 gnd 2.080806f
+R1 g6873_0 g6873_1 2.224404
+.ends
+
+.subckt netg5247 g5247_1 g5247_0 gnd
+C1  g5247_1 gnd 2.080806f
+C2  g5247_0 gnd 2.080806f
+R1 g5247_1 g5247_0 2.224404
+.ends
+
+.subckt netg5856 g5856_0 g5856_1 gnd
+C1  g5856_0 gnd 2.080806f
+C2  g5856_1 gnd 2.080806f
+R1 g5856_1 g5856_0 2.224404
+.ends
+
+.subckt netg2941 g2941_0 g2941_1 gnd
+C1  g2941_0 gnd 2.080806f
+C2  g2941_1 gnd 2.080806f
+R1 g2941_1 g2941_0 2.224404
+.ends
+
+.subckt netg5997 g5997_1 g5997_0 gnd
+C1  g5997_1 gnd 2.080806f
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+R1 g5997_0 g5997_1 2.224404
+.ends
+
+.subckt netg6040 g6040_0 g6040_1 gnd
+C1  g6040_0 gnd 2.080806f
+C2  g6040_1 gnd 2.080806f
+R1 g6040_1 g6040_0 2.224404
+.ends
+
+.subckt netg1261 g1261_1 g1261_0 gnd
+C1  g1261_1 gnd 2.080806f
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+R1 g1261_0 g1261_1 2.224404
+.ends
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+.subckt netg3555 g3555_1 g3555_0 gnd
+C1  g3555_1 gnd 2.080806f
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+R1 g3555_1 g3555_0 2.224404
+.ends
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+.subckt netg6292 g6292_1 g6292_0 gnd
+C1  g6292_1 gnd 2.080806f
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+R1 g6292_1 g6292_0 2.224404
+.ends
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+.subckt netg5684 g5684_1 g5684_0 gnd
+C1  g5684_1 gnd 2.080806f
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+R1 g5684_0 g5684_1 2.224404
+.ends
+
+.subckt netg4288 g4288_0 g4288_1 gnd
+C1  g4288_0 gnd 2.080806f
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+R1 g4288_0 g4288_1 2.224404
+.ends
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+.subckt netg7175 g7175_1 g7175_0 gnd
+C1  g7175_1 gnd 2.080806f
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+R1 g7175_0 g7175_1 2.224404
+.ends
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+.subckt netg4618 g4618_0 g4618_1 gnd
+C1  g4618_0 gnd 2.080806f
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+R1 g4618_0 g4618_1 2.224404
+.ends
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+.subckt netg7403 g7403_1 g7403_0 gnd
+C1  g7403_1 gnd 2.080806f
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+R1 g7403_1 g7403_0 2.224404
+.ends
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+.subckt netg4208 g4208_1 g4208_0 gnd
+C1  g4208_1 gnd 2.080806f
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+R1 g4208_0 g4208_1 2.224404
+.ends
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+.subckt netg2644 g2644_2 g2644_1 gnd
+C1  g2644_2 gnd 2.080806f
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+R1 g2644_2 g2644_1 2.224404
+.ends
+
+.subckt netg4261 g4261_0 g4261_1 gnd
+C1  g4261_0 gnd 2.080806f
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+R1 g4261_0 g4261_1 2.224404
+.ends
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+.subckt netg3438 g3438_2 g3438_1 gnd
+C1  g3438_2 gnd 2.080806f
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+R1 g3438_2 g3438_1 2.224404
+.ends
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+.subckt netg7409 g7409_1 g7409_0 gnd
+C1  g7409_1 gnd 2.080806f
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+R1 g7409_0 g7409_1 2.224404
+.ends
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+.subckt netg4234 g4234_0 g4234_1 gnd
+C1  g4234_0 gnd 2.080806f
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+R1 g4234_1 g4234_0 2.224404
+.ends
+
+.subckt netg1922 g1922_0 g1922_1 gnd
+C1  g1922_0 gnd 2.080806f
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+R1 g1922_1 g1922_0 2.224404
+.ends
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+.subckt netg1254 g1254_0 g1254_1 gnd
+C1  g1254_0 gnd 2.080806f
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+.ends
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+.subckt netg4311 g4311_1 g4311_0 gnd
+C1  g4311_1 gnd 2.080806f
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+R1 g4311_1 g4311_0 2.224404
+.ends
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+.subckt netg6082 g6082_1 g6082_0 gnd
+C1  g6082_1 gnd 2.080806f
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+.ends
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+.subckt netg3349 g3349_2 g3349_1 gnd
+C1  g3349_2 gnd 2.080806f
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+R1 g3349_1 g3349_2 2.224404
+.ends
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+.subckt netg1893 g1893_1 g1893_0 gnd
+C1  g1893_1 gnd 2.080806f
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+R1 g1893_0 g1893_1 2.224404
+.ends
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+.subckt netg6845 g6845_0 g6845_1 gnd
+C1  g6845_0 gnd 2.080806f
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+R1 g6845_1 g6845_0 2.224404
+.ends
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+.subckt netg5788 g5788_1 g5788_0 gnd
+C1  g5788_1 gnd 2.080806f
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+R1 g5788_0 g5788_1 2.224404
+.ends
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+.subckt netg6929 g6929_1 g6929_0 gnd
+C1  g6929_1 gnd 2.080806f
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+R1 g6929_1 g6929_0 2.224404
+.ends
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+.subckt netg694 g694_1 g694_0 gnd
+C1  g694_1 gnd 2.080806f
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+R1 g694_0 g694_1 2.224404
+.ends
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+.subckt netg5071 g5071_2 g5071_0 gnd
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+R1 g5071_0 g5071_2 2.224404
+.ends
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+.subckt netg4018 g4018_1 g4018_0 gnd
+C1  g4018_1 gnd 2.080806f
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+R1 g4018_0 g4018_1 2.224404
+.ends
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+.subckt netg4398 g4398_1 g4398_0 gnd
+C1  g4398_1 gnd 2.080806f
+C2  g4398_0 gnd 2.080806f
+R1 g4398_0 g4398_1 2.224404
+.ends
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+.subckt netg6079 g6079_0 g6079_1 gnd
+C1  g6079_0 gnd 2.080806f
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+R1 g6079_1 g6079_0 2.224404
+.ends
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+.subckt netg7277 g7277_0 g7277_1 gnd
+C1  g7277_0 gnd 2.080806f
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+R1 g7277_0 g7277_1 2.224404
+.ends
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+.subckt netx52 x52_0 x52_1 gnd
+C1  x52_0 gnd 2.080806f
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+R1 x52_0 x52_1 2.224404
+.ends
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+.subckt netg1406 g1406_1 g1406_0 gnd
+C1  g1406_1 gnd 2.080806f
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+R1 g1406_0 g1406_1 2.224404
+.ends
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+.subckt netg7439 g7439_1 g7439_0 gnd
+C1  g7439_1 gnd 2.080806f
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+R1 g7439_0 g7439_1 2.224404
+.ends
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+.subckt netg6695 g6695_1 g6695_0 gnd
+C1  g6695_1 gnd 2.080806f
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+R1 g6695_0 g6695_1 2.224404
+.ends
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+.subckt netg6490 g6490_1 g6490_0 gnd
+C1  g6490_1 gnd 2.080806f
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+R1 g6490_0 g6490_1 2.224404
+.ends
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+.subckt netg690 g690_1 g690_0 gnd
+C1  g690_1 gnd 2.080806f
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+R1 g690_1 g690_0 2.224404
+.ends
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+.subckt netg6825 g6825_1 g6825_0 gnd
+C1  g6825_1 gnd 2.080806f
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+R1 g6825_0 g6825_1 2.224404
+.ends
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+.subckt netg5119 g5119_1 g5119_0 gnd
+C1  g5119_1 gnd 2.080806f
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+R1 g5119_1 g5119_0 2.224404
+.ends
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+.subckt netg7196 g7196_1 g7196_0 gnd
+C1  g7196_1 gnd 2.080806f
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+R1 g7196_1 g7196_0 2.224404
+.ends
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+.subckt netg6404 g6404_1 g6404_0 gnd
+C1  g6404_1 gnd 2.080806f
+C2  g6404_0 gnd 2.080806f
+R1 g6404_1 g6404_0 2.224404
+.ends
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+.subckt netg5607 g5607_0 g5607_1 gnd
+C1  g5607_0 gnd 2.080806f
+C2  g5607_1 gnd 2.080806f
+R1 g5607_0 g5607_1 2.224404
+.ends
+
+.subckt netg1377 g1377_1 g1377_0 gnd
+C1  g1377_1 gnd 2.080806f
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+R1 g1377_0 g1377_1 2.224404
+.ends
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+.subckt netg4097 g4097_1 g4097_0 gnd
+C1  g4097_1 gnd 2.080806f
+C2  g4097_0 gnd 2.080806f
+R1 g4097_1 g4097_0 2.224404
+.ends
+
+.subckt netg5321 g5321_1 g5321_0 gnd
+C1  g5321_1 gnd 2.080806f
+C2  g5321_0 gnd 2.080806f
+R1 g5321_0 g5321_1 2.224404
+.ends
+
+.subckt netg3417 g3417_2 g3417_0 gnd
+C1  g3417_2 gnd 2.080806f
+C2  g3417_0 gnd 2.080806f
+R1 g3417_0 g3417_2 2.224404
+.ends
+
+.subckt netg913 g913_1 g913_2 gnd
+C1  g913_1 gnd 2.080806f
+C2  g913_2 gnd 2.080806f
+R1 g913_1 g913_2 2.224404
+.ends
+
+.subckt netg6461 g6461_0 g6461_1 gnd
+C1  g6461_0 gnd 2.080806f
+C2  g6461_1 gnd 2.080806f
+R1 g6461_0 g6461_1 2.224404
+.ends
+
+.subckt netg2779 g2779_1 g2779_0 gnd
+C1  g2779_1 gnd 2.080806f
+C2  g2779_0 gnd 2.080806f
+R1 g2779_0 g2779_1 2.224404
+.ends
+
+.subckt netg97 g97_0 g97_1 gnd
+C1  g97_0 gnd 2.080806f
+C2  g97_1 gnd 2.080806f
+R1 g97_1 g97_0 2.224404
+.ends
+
+.subckt netg985 g985_0 g985_2 gnd
+C1  g985_0 gnd 2.080806f
+C2  g985_2 gnd 2.080806f
+R1 g985_0 g985_2 2.224404
+.ends
+
+.subckt netg1259 g1259_0 g1259_1 gnd
+C1  g1259_0 gnd 2.080806f
+C2  g1259_1 gnd 2.080806f
+R1 g1259_0 g1259_1 2.224404
+.ends
+
+.subckt netg3046 g3046_1 g3046_0 gnd
+C1  g3046_1 gnd 2.080806f
+C2  g3046_0 gnd 2.080806f
+R1 g3046_1 g3046_0 2.224404
+.ends
+
+.subckt netg7389 g7389_0 g7389_1 gnd
+C1  g7389_0 gnd 2.080806f
+C2  g7389_1 gnd 2.080806f
+R1 g7389_0 g7389_1 2.224404
+.ends
+
+.subckt netg1516 g1516_0 g1516_1 gnd
+C1  g1516_0 gnd 2.080806f
+C2  g1516_1 gnd 2.080806f
+R1 g1516_1 g1516_0 2.224404
+.ends
+
+.subckt netg5367 g5367_0 g5367_1 gnd
+C1  g5367_0 gnd 2.080806f
+C2  g5367_1 gnd 2.080806f
+R1 g5367_1 g5367_0 2.224404
+.ends
+
+.subckt netg7026 g7026_1 g7026_0 gnd
+C1  g7026_1 gnd 2.080806f
+C2  g7026_0 gnd 2.080806f
+R1 g7026_1 g7026_0 2.224404
+.ends
+
+.subckt netg6579 g6579_1 g6579_0 gnd
+C1  g6579_1 gnd 2.080806f
+C2  g6579_0 gnd 2.080806f
+R1 g6579_0 g6579_1 2.224404
+.ends
+
+.subckt netg5360 g5360_0 g5360_1 gnd
+C1  g5360_0 gnd 2.080806f
+C2  g5360_1 gnd 2.080806f
+R1 g5360_0 g5360_1 2.224404
+.ends
+
+.subckt netg2477 g2477_2 g2477_1 gnd
+C1  g2477_2 gnd 2.080806f
+C2  g2477_1 gnd 2.080806f
+R1 g2477_2 g2477_1 2.224404
+.ends
+
+.subckt netg7168 g7168_0 g7168_1 gnd
+C1  g7168_0 gnd 2.080806f
+C2  g7168_1 gnd 2.080806f
+R1 g7168_1 g7168_0 2.224404
+.ends
+
+.subckt netg3892 g3892_1 g3892_0 gnd
+C1  g3892_1 gnd 2.080806f
+C2  g3892_0 gnd 2.080806f
+R1 g3892_0 g3892_1 2.224404
+.ends
+
+.subckt netg4295 g4295_1 g4295_0 gnd
+C1  g4295_1 gnd 2.080806f
+C2  g4295_0 gnd 2.080806f
+R1 g4295_0 g4295_1 2.224404
+.ends
+
+.subckt netg6365 g6365_1 g6365_0 gnd
+C1  g6365_1 gnd 2.080806f
+C2  g6365_0 gnd 2.080806f
+R1 g6365_0 g6365_1 2.224404
+.ends
+
+.subckt netg6819 g6819_1 g6819_0 gnd
+C1  g6819_1 gnd 2.080806f
+C2  g6819_0 gnd 2.080806f
+R1 g6819_0 g6819_1 2.224404
+.ends
+
+.subckt netg560 g560_1 g560_0 gnd
+C1  g560_1 gnd 2.080806f
+C2  g560_0 gnd 2.080806f
+R1 g560_1 g560_0 2.224404
+.ends
+
+.subckt netg2783 g2783_0 g2783_1 gnd
+C1  g2783_0 gnd 2.080806f
+C2  g2783_1 gnd 2.080806f
+R1 g2783_1 g2783_0 2.224404
+.ends
+
+.subckt netg5605 g5605_0 g5605_1 gnd
+C1  g5605_0 gnd 2.080806f
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+R1 g5605_1 g5605_0 2.224404
+.ends
+
+.subckt netg3412 g3412_0 g3412_1 gnd
+C1  g3412_0 gnd 2.080806f
+C2  g3412_1 gnd 2.080806f
+R1 g3412_1 g3412_0 2.224404
+.ends
+
+.subckt netg3085 g3085_1 g3085_0 gnd
+C1  g3085_1 gnd 2.080806f
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+R1 g3085_1 g3085_0 2.224404
+.ends
+
+.subckt netg5961 g5961_0 g5961_1 gnd
+C1  g5961_0 gnd 2.080806f
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+R1 g5961_0 g5961_1 2.224404
+.ends
+
+.subckt netg1535 g1535_1 g1535_0 gnd
+C1  g1535_1 gnd 2.080806f
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+R1 g1535_1 g1535_0 2.224404
+.ends
+
+.subckt netg6967 g6967_2 g6967_1 gnd
+C1  g6967_2 gnd 2.080806f
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+R1 g6967_2 g6967_1 2.224404
+.ends
+
+.subckt netx401 x401_1 x401_0 gnd
+C1  x401_1 gnd 2.080806f
+C2  x401_0 gnd 2.080806f
+R1 x401_0 x401_1 2.224404
+.ends
+
+.subckt netg4182 g4182_1 g4182_0 gnd
+C1  g4182_1 gnd 2.080806f
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+R1 g4182_1 g4182_0 2.224404
+.ends
+
+.subckt netg6888 g6888_1 g6888_0 gnd
+C1  g6888_1 gnd 2.080806f
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+R1 g6888_0 g6888_1 2.224404
+.ends
+
+.subckt netg3982 g3982_0 g3982_1 gnd
+C1  g3982_0 gnd 2.080806f
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+R1 g3982_1 g3982_0 2.224404
+.ends
+
+.subckt netg6672 g6672_1 g6672_0 gnd
+C1  g6672_1 gnd 2.080806f
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+R1 g6672_0 g6672_1 2.224404
+.ends
+
+.subckt netg4112 g4112_0 g4112_1 gnd
+C1  g4112_0 gnd 2.080806f
+C2  g4112_1 gnd 2.080806f
+R1 g4112_0 g4112_1 2.224404
+.ends
+
+.subckt netg5874 g5874_1 g5874_0 gnd
+C1  g5874_1 gnd 2.080806f
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+R1 g5874_1 g5874_0 2.224404
+.ends
+
+.subckt netg5317 g5317_0 g5317_1 gnd
+C1  g5317_0 gnd 2.080806f
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+R1 g5317_1 g5317_0 2.224404
+.ends
+
+.subckt netg5181 g5181_1 g5181_0 gnd
+C1  g5181_1 gnd 2.080806f
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+R1 g5181_1 g5181_0 2.224404
+.ends
+
+.subckt netg5890 g5890_1 g5890_0 gnd
+C1  g5890_1 gnd 2.080806f
+C2  g5890_0 gnd 2.080806f
+R1 g5890_1 g5890_0 2.224404
+.ends
+
+.subckt netg2221 g2221_0 g2221_1 gnd
+C1  g2221_0 gnd 2.080806f
+C2  g2221_1 gnd 2.080806f
+R1 g2221_1 g2221_0 2.224404
+.ends
+
+.subckt netg2810 g2810_1 g2810_0 gnd
+C1  g2810_1 gnd 2.080806f
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+R1 g2810_1 g2810_0 2.224404
+.ends
+
+.subckt netg7214 g7214_0 g7214_1 gnd
+C1  g7214_0 gnd 2.080806f
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+R1 g7214_0 g7214_1 2.224404
+.ends
+
+.subckt netg5200 g5200_0 g5200_1 gnd
+C1  g5200_0 gnd 2.080806f
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+R1 g5200_0 g5200_1 2.224404
+.ends
+
+.subckt netg4202 g4202_0 g4202_1 gnd
+C1  g4202_0 gnd 2.080806f
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+R1 g4202_1 g4202_0 2.224404
+.ends
+
+.subckt netg6516 g6516_1 g6516_0 gnd
+C1  g6516_1 gnd 2.080806f
+C2  g6516_0 gnd 2.080806f
+R1 g6516_1 g6516_0 2.224404
+.ends
+
+.subckt netg7395 g7395_1 g7395_0 gnd
+C1  g7395_1 gnd 2.080806f
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+R1 g7395_0 g7395_1 2.224404
+.ends
+
+.subckt netg3410 g3410_0 g3410_1 gnd
+C1  g3410_0 gnd 2.080806f
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+R1 g3410_0 g3410_1 2.224404
+.ends
+
+.subckt netg6469 g6469_0 g6469_1 gnd
+C1  g6469_0 gnd 2.080806f
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+R1 g6469_0 g6469_1 2.224404
+.ends
+
+.subckt netg4278 g4278_0 g4278_1 gnd
+C1  g4278_0 gnd 2.080806f
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+R1 g4278_0 g4278_1 2.224404
+.ends
+
+.subckt netg3895 g3895_0 g3895_1 gnd
+C1  g3895_0 gnd 2.080806f
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+R1 g3895_0 g3895_1 2.224404
+.ends
+
+.subckt netg6405 g6405_1 g6405_0 gnd
+C1  g6405_1 gnd 2.080806f
+C2  g6405_0 gnd 2.080806f
+R1 g6405_0 g6405_1 2.224404
+.ends
+
+.subckt netg7299 g7299_1 g7299_0 gnd
+C1  g7299_1 gnd 2.080806f
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+R1 g7299_0 g7299_1 2.224404
+.ends
+
+.subckt netg6606 g6606_0 g6606_1 gnd
+C1  g6606_0 gnd 2.080806f
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+R1 g6606_0 g6606_1 2.224404
+.ends
+
+.subckt netg6609 g6609_0 g6609_1 gnd
+C1  g6609_0 gnd 2.080806f
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+R1 g6609_0 g6609_1 2.224404
+.ends
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+.subckt netg6015 g6015_1 g6015_0 gnd
+C1  g6015_1 gnd 2.080806f
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+R1 g6015_1 g6015_0 2.224404
+.ends
+
+.subckt netg6999 g6999_0 g6999_1 gnd
+C1  g6999_0 gnd 2.080806f
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+R1 g6999_1 g6999_0 2.224404
+.ends
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+.subckt netg1009 g1009_1 g1009_2 gnd
+C1  g1009_1 gnd 2.080806f
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+.ends
+
+.subckt netg7192 g7192_0 g7192_1 gnd
+C1  g7192_0 gnd 2.080806f
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+R1 g7192_0 g7192_1 2.224404
+.ends
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+.subckt netg2921 g2921_0 g2921_1 gnd
+C1  g2921_0 gnd 2.080806f
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+R1 g2921_1 g2921_0 2.224404
+.ends
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+.subckt netg1003 g1003_1 g1003_2 gnd
+C1  g1003_1 gnd 2.080806f
+C2  g1003_2 gnd 2.080806f
+R1 g1003_1 g1003_2 2.224404
+.ends
+
+.subckt netg4229 g4229_0 g4229_1 gnd
+C1  g4229_0 gnd 2.080806f
+C2  g4229_1 gnd 2.080806f
+R1 g4229_0 g4229_1 2.224404
+.ends
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+.subckt netg4150 g4150_0 g4150_1 gnd
+C1  g4150_0 gnd 2.080806f
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+R1 g4150_0 g4150_1 2.224404
+.ends
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+.subckt netg4042 g4042_1 g4042_0 gnd
+C1  g4042_1 gnd 2.080806f
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+R1 g4042_0 g4042_1 2.224404
+.ends
+
+.subckt netg7064 g7064_1 g7064_0 gnd
+C1  g7064_1 gnd 2.080806f
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+R1 g7064_1 g7064_0 2.224404
+.ends
+
+.subckt netg6170 g6170_0 g6170_1 gnd
+C1  g6170_0 gnd 2.080806f
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+R1 g6170_1 g6170_0 2.224404
+.ends
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+.subckt netx292 x292_1 x292_0 gnd
+C1  x292_1 gnd 2.080806f
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+R1 x292_1 x292_0 2.224404
+.ends
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+.subckt netg6656 g6656_1 g6656_0 gnd
+C1  g6656_1 gnd 2.080806f
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+R1 g6656_1 g6656_0 2.224404
+.ends
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+.subckt netg7407 g7407_1 g7407_0 gnd
+C1  g7407_1 gnd 2.080806f
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+R1 g7407_0 g7407_1 2.224404
+.ends
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+.subckt netg4432 g4432_0 g4432_1 gnd
+C1  g4432_0 gnd 2.080806f
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+R1 g4432_1 g4432_0 2.224404
+.ends
+
+.subckt netg4072 g4072_1 g4072_0 gnd
+C1  g4072_1 gnd 2.080806f
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+R1 g4072_1 g4072_0 2.224404
+.ends
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+.subckt netg2951 g2951_0 g2951_1 gnd
+C1  g2951_0 gnd 2.080806f
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+R1 g2951_0 g2951_1 2.224404
+.ends
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+.subckt netg4136 g4136_1 g4136_0 gnd
+C1  g4136_1 gnd 2.080806f
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+R1 g4136_0 g4136_1 2.224404
+.ends
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+.subckt netg4049 g4049_1 g4049_0 gnd
+C1  g4049_1 gnd 2.080806f
+C2  g4049_0 gnd 2.080806f
+R1 g4049_0 g4049_1 2.224404
+.ends
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+.subckt netg3423 g3423_1 g3423_2 gnd
+C1  g3423_1 gnd 2.080806f
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+R1 g3423_1 g3423_2 2.224404
+.ends
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+.subckt netg4276 g4276_1 g4276_0 gnd
+C1  g4276_1 gnd 2.080806f
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+R1 g4276_1 g4276_0 2.224404
+.ends
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+.subckt netg3471 g3471_1 g3471_0 gnd
+C1  g3471_1 gnd 2.080806f
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+R1 g3471_1 g3471_0 2.224404
+.ends
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+.subckt netg5470 g5470_0 g5470_1 gnd
+C1  g5470_0 gnd 2.080806f
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+R1 g5470_1 g5470_0 2.224404
+.ends
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+.subckt netg3469 g3469_0 g3469_1 gnd
+C1  g3469_0 gnd 2.080806f
+C2  g3469_1 gnd 2.080806f
+R1 g3469_1 g3469_0 2.224404
+.ends
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+.subckt netg4316 g4316_0 g4316_1 gnd
+C1  g4316_0 gnd 2.080806f
+C2  g4316_1 gnd 2.080806f
+R1 g4316_0 g4316_1 2.224404
+.ends
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+.subckt netg6532 g6532_0 g6532_1 gnd
+C1  g6532_0 gnd 2.080806f
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+R1 g6532_1 g6532_0 2.224404
+.ends
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+.subckt netg2704 g2704_1 g2704_2 gnd
+C1  g2704_1 gnd 2.080806f
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+R1 g2704_2 g2704_1 2.224404
+.ends
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+.subckt netg6522 g6522_0 g6522_1 gnd
+C1  g6522_0 gnd 2.080806f
+C2  g6522_1 gnd 2.080806f
+R1 g6522_0 g6522_1 2.224404
+.ends
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+.subckt netg7102 g7102_0 g7102_1 gnd
+C1  g7102_0 gnd 2.080806f
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+.ends
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+.subckt netg6358 g6358_1 g6358_0 gnd
+C1  g6358_1 gnd 2.080806f
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+R1 g6358_0 g6358_1 2.224404
+.ends
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+.subckt netg6072 g6072_1 g6072_0 gnd
+C1  g6072_1 gnd 2.080806f
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+R1 g6072_1 g6072_0 2.224404
+.ends
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+.subckt netg6651 g6651_1 g6651_0 gnd
+C1  g6651_1 gnd 2.080806f
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+R1 g6651_1 g6651_0 2.224404
+.ends
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+.subckt netg3345 g3345_0 g3345_1 gnd
+C1  g3345_0 gnd 2.080806f
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+R1 g3345_0 g3345_1 2.224404
+.ends
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+.subckt netg6083 g6083_0 g6083_1 gnd
+C1  g6083_0 gnd 2.080806f
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+R1 g6083_0 g6083_1 2.224404
+.ends
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+.subckt netg4304 g4304_1 g4304_0 gnd
+C1  g4304_1 gnd 2.080806f
+C2  g4304_0 gnd 2.080806f
+R1 g4304_1 g4304_0 2.224404
+.ends
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+.subckt netg4236 g4236_0 g4236_1 gnd
+C1  g4236_0 gnd 2.080806f
+C2  g4236_1 gnd 2.080806f
+R1 g4236_1 g4236_0 2.224404
+.ends
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+.subckt netg3534 g3534_0 g3534_1 gnd
+C1  g3534_0 gnd 2.080806f
+C2  g3534_1 gnd 2.080806f
+R1 g3534_1 g3534_0 2.224404
+.ends
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+.subckt netg4051 g4051_1 g4051_0 gnd
+C1  g4051_1 gnd 2.080806f
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+R1 g4051_1 g4051_0 2.224404
+.ends
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+.subckt netg4104 g4104_0 g4104_1 gnd
+C1  g4104_0 gnd 2.080806f
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+R1 g4104_0 g4104_1 2.224404
+.ends
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+.subckt netg7074 g7074_0 g7074_1 gnd
+C1  g7074_0 gnd 2.080806f
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+R1 g7074_1 g7074_0 2.224404
+.ends
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+.subckt netg6415 g6415_0 g6415_1 gnd
+C1  g6415_0 gnd 2.080806f
+C2  g6415_1 gnd 2.080806f
+R1 g6415_0 g6415_1 2.224404
+.ends
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+.subckt netg3575 g3575_1 g3575_0 gnd
+C1  g3575_1 gnd 2.080806f
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+R1 g3575_1 g3575_0 2.224404
+.ends
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+.subckt netg5765 g5765_1 g5765_0 gnd
+C1  g5765_1 gnd 2.080806f
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+R1 g5765_1 g5765_0 2.224404
+.ends
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+.subckt netg7210 g7210_1 g7210_0 gnd
+C1  g7210_1 gnd 2.080806f
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+R1 g7210_1 g7210_0 2.224404
+.ends
+
+.subckt netg6582 g6582_1 g6582_0 gnd
+C1  g6582_1 gnd 2.080806f
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+R1 g6582_1 g6582_0 2.224404
+.ends
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+.subckt netg4133 g4133_1 g4133_0 gnd
+C1  g4133_1 gnd 2.080806f
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+R1 g4133_0 g4133_1 2.224404
+.ends
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+.subckt netg7219 g7219_2 g7219_0 gnd
+C1  g7219_2 gnd 2.080806f
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+R1 g7219_0 g7219_2 2.224404
+.ends
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+.subckt netg6409 g6409_0 g6409_1 gnd
+C1  g6409_0 gnd 2.080806f
+C2  g6409_1 gnd 2.080806f
+R1 g6409_0 g6409_1 2.224404
+.ends
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+.subckt netg7081 g7081_1 g7081_0 gnd
+C1  g7081_1 gnd 2.080806f
+C2  g7081_0 gnd 2.080806f
+R1 g7081_1 g7081_0 2.224404
+.ends
+
+.subckt netg5018 g5018_1 g5018_2 gnd
+C1  g5018_1 gnd 2.080806f
+C2  g5018_2 gnd 2.080806f
+R1 g5018_2 g5018_1 2.224404
+.ends
+
+.subckt netx482 x482_0 x482_1 gnd
+C1  x482_0 gnd 2.080806f
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+R1 x482_1 x482_0 2.224404
+.ends
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+.subckt netg7123 g7123_1 g7123_0 gnd
+C1  g7123_1 gnd 2.080806f
+C2  g7123_0 gnd 2.080806f
+R1 g7123_0 g7123_1 2.224404
+.ends
+
+.subckt netg3063 g3063_1 g3063_0 gnd
+C1  g3063_1 gnd 2.080806f
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+R1 g3063_0 g3063_1 2.224404
+.ends
+
+.subckt netg5667 g5667_0 g5667_1 gnd
+C1  g5667_0 gnd 2.080806f
+C2  g5667_1 gnd 2.080806f
+R1 g5667_1 g5667_0 2.224404
+.ends
+
+.subckt netg2820 g2820_0 g2820_1 gnd
+C1  g2820_0 gnd 2.080806f
+C2  g2820_1 gnd 2.080806f
+R1 g2820_0 g2820_1 2.224404
+.ends
+
+.subckt netg5466 g5466_0 g5466_1 gnd
+C1  g5466_0 gnd 2.080806f
+C2  g5466_1 gnd 2.080806f
+R1 g5466_1 g5466_0 2.224404
+.ends
+
+.subckt netg2634 g2634_1 g2634_0 gnd
+C1  g2634_1 gnd 2.080806f
+C2  g2634_0 gnd 2.080806f
+R1 g2634_1 g2634_0 2.224404
+.ends
+
+.subckt netg7127 g7127_0 g7127_1 gnd
+C1  g7127_0 gnd 2.080806f
+C2  g7127_1 gnd 2.080806f
+R1 g7127_0 g7127_1 2.224404
+.ends
+
+.subckt netg4209 g4209_1 g4209_0 gnd
+C1  g4209_1 gnd 2.080806f
+C2  g4209_0 gnd 2.080806f
+R1 g4209_0 g4209_1 2.224404
+.ends
+
+.subckt netg3898 g3898_1 g3898_0 gnd
+C1  g3898_1 gnd 2.080806f
+C2  g3898_0 gnd 2.080806f
+R1 g3898_0 g3898_1 2.224404
+.ends
+
+.subckt netg5991 g5991_1 g5991_0 gnd
+C1  g5991_1 gnd 2.080806f
+C2  g5991_0 gnd 2.080806f
+R1 g5991_0 g5991_1 2.224404
+.ends
+
+.subckt netg4277 g4277_1 g4277_0 gnd
+C1  g4277_1 gnd 2.080806f
+C2  g4277_0 gnd 2.080806f
+R1 g4277_0 g4277_1 2.224404
+.ends
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+.subckt netg4019 g4019_0 g4019_1 gnd
+C1  g4019_0 gnd 2.080806f
+C2  g4019_1 gnd 2.080806f
+R1 g4019_1 g4019_0 2.224404
+.ends
+
+.subckt netg5525 g5525_1 g5525_0 gnd
+C1  g5525_1 gnd 2.080806f
+C2  g5525_0 gnd 2.080806f
+R1 g5525_0 g5525_1 2.224404
+.ends
+
+.subckt netg4059 g4059_0 g4059_1 gnd
+C1  g4059_0 gnd 2.080806f
+C2  g4059_1 gnd 2.080806f
+R1 g4059_0 g4059_1 2.224404
+.ends
+
+.subckt netg2765 g2765_0 g2765_1 gnd
+C1  g2765_0 gnd 2.080806f
+C2  g2765_1 gnd 2.080806f
+R1 g2765_0 g2765_1 2.224404
+.ends
+
+.subckt netg6926 g6926_1 g6926_0 gnd
+C1  g6926_1 gnd 2.080806f
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+R1 g6926_0 g6926_1 2.224404
+.ends
+
+.subckt netg4038 g4038_1 g4038_0 gnd
+C1  g4038_1 gnd 2.080806f
+C2  g4038_0 gnd 2.080806f
+R1 g4038_0 g4038_1 2.224404
+.ends
+
+.subckt netg6536 g6536_0 g6536_1 gnd
+C1  g6536_0 gnd 2.080806f
+C2  g6536_1 gnd 2.080806f
+R1 g6536_0 g6536_1 2.224404
+.ends
+
+.subckt netg1509 g1509_1 g1509_0 gnd
+C1  g1509_1 gnd 2.080806f
+C2  g1509_0 gnd 2.080806f
+R1 g1509_1 g1509_0 2.224404
+.ends
+
+.subckt netg6055 g6055_0 g6055_1 gnd
+C1  g6055_0 gnd 2.080806f
+C2  g6055_1 gnd 2.080806f
+R1 g6055_1 g6055_0 2.224404
+.ends
+
+.subckt netg3492 g3492_0 g3492_1 gnd
+C1  g3492_0 gnd 2.080806f
+C2  g3492_1 gnd 2.080806f
+R1 g3492_1 g3492_0 2.224404
+.ends
+
+.subckt netg2915 g2915_1 g2915_0 gnd
+C1  g2915_1 gnd 2.080806f
+C2  g2915_0 gnd 2.080806f
+R1 g2915_0 g2915_1 2.224404
+.ends
+
+.subckt netg6115 g6115_1 g6115_0 gnd
+C1  g6115_1 gnd 2.080806f
+C2  g6115_0 gnd 2.080806f
+R1 g6115_0 g6115_1 2.224404
+.ends
+
+.subckt netg2830 g2830_1 g2830_0 gnd
+C1  g2830_1 gnd 2.080806f
+C2  g2830_0 gnd 2.080806f
+R1 g2830_1 g2830_0 2.224404
+.ends
+
+.subckt netg6211 g6211_1 g6211_0 gnd
+C1  g6211_1 gnd 2.080806f
+C2  g6211_0 gnd 2.080806f
+R1 g6211_0 g6211_1 2.224404
+.ends
+
+.subckt netg5428 g5428_1 g5428_0 gnd
+C1  g5428_1 gnd 2.080806f
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+R1 g5428_0 g5428_1 2.224404
+.ends
+
+.subckt netg6165 g6165_1 g6165_0 gnd
+C1  g6165_1 gnd 2.080806f
+C2  g6165_0 gnd 2.080806f
+R1 g6165_0 g6165_1 2.224404
+.ends
+
+.subckt netg1477 g1477_1 g1477_0 gnd
+C1  g1477_1 gnd 2.080806f
+C2  g1477_0 gnd 2.080806f
+R1 g1477_0 g1477_1 2.224404
+.ends
+
+.subckt netg7211 g7211_1 g7211_0 gnd
+C1  g7211_1 gnd 2.080806f
+C2  g7211_0 gnd 2.080806f
+R1 g7211_0 g7211_1 2.224404
+.ends
+
+.subckt netg6316 g6316_0 g6316_1 gnd
+C1  g6316_0 gnd 2.080806f
+C2  g6316_1 gnd 2.080806f
+R1 g6316_0 g6316_1 2.224404
+.ends
+
+.subckt netg4052 g4052_1 g4052_0 gnd
+C1  g4052_1 gnd 2.080806f
+C2  g4052_0 gnd 2.080806f
+R1 g4052_0 g4052_1 2.224404
+.ends
+
+.subckt netg4176 g4176_0 g4176_1 gnd
+C1  g4176_0 gnd 2.080806f
+C2  g4176_1 gnd 2.080806f
+R1 g4176_0 g4176_1 2.224404
+.ends
+
+.subckt netg2225 g2225_0 g2225_1 gnd
+C1  g2225_0 gnd 2.080806f
+C2  g2225_1 gnd 2.080806f
+R1 g2225_1 g2225_0 2.224404
+.ends
+
+.subckt netg7241 g7241_1 g7241_0 gnd
+C1  g7241_1 gnd 2.080806f
+C2  g7241_0 gnd 2.080806f
+R1 g7241_0 g7241_1 2.224404
+.ends
+
+.subckt netg6185 g6185_0 g6185_1 gnd
+C1  g6185_0 gnd 2.080806f
+C2  g6185_1 gnd 2.080806f
+R1 g6185_1 g6185_0 2.224404
+.ends
+
+.subckt netg6718 g6718_0 g6718_1 gnd
+C1  g6718_0 gnd 2.080806f
+C2  g6718_1 gnd 2.080806f
+R1 g6718_0 g6718_1 2.224404
+.ends
+
+.subckt netg2504 g2504_0 g2504_2 gnd
+C1  g2504_0 gnd 2.080806f
+C2  g2504_2 gnd 2.080806f
+R1 g2504_2 g2504_0 2.224404
+.ends
+
+.subckt netg4071 g4071_0 g4071_1 gnd
+C1  g4071_0 gnd 2.080806f
+C2  g4071_1 gnd 2.080806f
+R1 g4071_1 g4071_0 2.224404
+.ends
+
+.subckt netg7101 g7101_0 g7101_1 gnd
+C1  g7101_0 gnd 2.080806f
+C2  g7101_1 gnd 2.080806f
+R1 g7101_0 g7101_1 2.224404
+.ends
+
+.subckt netg6935 g6935_0 g6935_1 gnd
+C1  g6935_0 gnd 2.080806f
+C2  g6935_1 gnd 2.080806f
+R1 g6935_0 g6935_1 2.224404
+.ends
+
+.subckt netg6875 g6875_0 g6875_1 gnd
+C1  g6875_0 gnd 2.080806f
+C2  g6875_1 gnd 2.080806f
+R1 g6875_1 g6875_0 2.224404
+.ends
+
+.subckt netg5972 g5972_0 g5972_1 gnd
+C1  g5972_0 gnd 2.080806f
+C2  g5972_1 gnd 2.080806f
+R1 g5972_0 g5972_1 2.224404
+.ends
+
+.subckt netg5142 g5142_1 g5142_0 gnd
+C1  g5142_1 gnd 2.080806f
+C2  g5142_0 gnd 2.080806f
+R1 g5142_1 g5142_0 2.224404
+.ends
+
+.subckt netg4333 g4333_0 g4333_1 gnd
+C1  g4333_0 gnd 2.080806f
+C2  g4333_1 gnd 2.080806f
+R1 g4333_1 g4333_0 2.224404
+.ends
+
+.subckt netg4128 g4128_0 g4128_1 gnd
+C1  g4128_0 gnd 2.080806f
+C2  g4128_1 gnd 2.080806f
+R1 g4128_1 g4128_0 2.224404
+.ends
+
+.subckt netg2534 g2534_2 g2534_1 gnd
+C1  g2534_2 gnd 2.080806f
+C2  g2534_1 gnd 2.080806f
+R1 g2534_1 g2534_2 2.224404
+.ends
+
+.subckt netg6245 g6245_0 g6245_1 gnd
+C1  g6245_0 gnd 2.080806f
+C2  g6245_1 gnd 2.080806f
+R1 g6245_1 g6245_0 2.224404
+.ends
+
+.subckt netg4418 g4418_1 g4418_0 gnd
+C1  g4418_1 gnd 2.080806f
+C2  g4418_0 gnd 2.080806f
+R1 g4418_0 g4418_1 2.224404
+.ends
+
+.subckt netg5619 g5619_2 g5619_1 gnd
+C1  g5619_2 gnd 2.080806f
+C2  g5619_1 gnd 2.080806f
+R1 g5619_2 g5619_1 2.224404
+.ends
+
+.subckt netg5794 g5794_1 g5794_0 gnd
+C1  g5794_1 gnd 2.080806f
+C2  g5794_0 gnd 2.080806f
+R1 g5794_1 g5794_0 2.224404
+.ends
+
+.subckt netg1923 g1923_1 g1923_0 gnd
+C1  g1923_1 gnd 2.080806f
+C2  g1923_0 gnd 2.080806f
+R1 g1923_0 g1923_1 2.224404
+.ends
+
+.subckt netg7263 g7263_0 g7263_1 gnd
+C1  g7263_0 gnd 2.080806f
+C2  g7263_1 gnd 2.080806f
+R1 g7263_1 g7263_0 2.224404
+.ends
+
+.subckt netg5279 g5279_1 g5279_0 gnd
+C1  g5279_1 gnd 2.080806f
+C2  g5279_0 gnd 2.080806f
+R1 g5279_1 g5279_0 2.224404
+.ends
+
+.subckt netg3913 g3913_0 g3913_1 gnd
+C1  g3913_0 gnd 2.080806f
+C2  g3913_1 gnd 2.080806f
+R1 g3913_1 g3913_0 2.224404
+.ends
+
+.subckt netg5740 g5740_0 g5740_2 gnd
+C1  g5740_0 gnd 2.080806f
+C2  g5740_2 gnd 2.080806f
+R1 g5740_2 g5740_0 2.224404
+.ends
+
+.subckt netg6171 g6171_0 g6171_1 gnd
+C1  g6171_0 gnd 2.080806f
+C2  g6171_1 gnd 2.080806f
+R1 g6171_0 g6171_1 2.224404
+.ends
+
+.subckt netg5430 g5430_0 g5430_1 gnd
+C1  g5430_0 gnd 2.080806f
+C2  g5430_1 gnd 2.080806f
+R1 g5430_0 g5430_1 2.224404
+.ends
+
+.subckt netg1393 g1393_1 g1393_0 gnd
+C1  g1393_1 gnd 2.080806f
+C2  g1393_0 gnd 2.080806f
+R1 g1393_1 g1393_0 2.224404
+.ends
+
+.subckt netg2359 g2359_2 g2359_1 gnd
+C1  g2359_2 gnd 2.080806f
+C2  g2359_1 gnd 2.080806f
+R1 g2359_1 g2359_2 2.224404
+.ends
+
+.subckt netg892 g892_1 g892_2 gnd
+C1  g892_1 gnd 2.080806f
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+R1 g892_2 g892_1 2.224404
+.ends
+
+.subckt netg3003 g3003_0 g3003_1 gnd
+C1  g3003_0 gnd 2.080806f
+C2  g3003_1 gnd 2.080806f
+R1 g3003_1 g3003_0 2.224404
+.ends
+
+.subckt netg5993 g5993_1 g5993_0 gnd
+C1  g5993_1 gnd 2.080806f
+C2  g5993_0 gnd 2.080806f
+R1 g5993_0 g5993_1 2.224404
+.ends
+
+.subckt netg7218 g7218_1 g7218_0 gnd
+C1  g7218_1 gnd 2.080806f
+C2  g7218_0 gnd 2.080806f
+R1 g7218_0 g7218_1 2.224404
+.ends
+
+.subckt netg1405 g1405_0 g1405_1 gnd
+C1  g1405_0 gnd 2.080806f
+C2  g1405_1 gnd 2.080806f
+R1 g1405_0 g1405_1 2.224404
+.ends
+
+.subckt netg5916 g5916_1 g5916_0 gnd
+C1  g5916_1 gnd 2.080806f
+C2  g5916_0 gnd 2.080806f
+R1 g5916_0 g5916_1 2.224404
+.ends
+
+.subckt netg6312 g6312_1 g6312_0 gnd
+C1  g6312_1 gnd 2.080806f
+C2  g6312_0 gnd 2.080806f
+R1 g6312_0 g6312_1 2.224404
+.ends
+
+.subckt netg4665 g4665_1 g4665_0 gnd
+C1  g4665_1 gnd 2.080806f
+C2  g4665_0 gnd 2.080806f
+R1 g4665_0 g4665_1 2.224404
+.ends
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+.subckt netg3702 g3702_2 g3702_1 gnd
+C1  g3702_2 gnd 2.080806f
+C2  g3702_1 gnd 2.080806f
+R1 g3702_1 g3702_2 2.224404
+.ends
+
+.subckt netg4141 g4141_0 g4141_1 gnd
+C1  g4141_0 gnd 2.080806f
+C2  g4141_1 gnd 2.080806f
+R1 g4141_1 g4141_0 2.224404
+.ends
+
+.subckt netg6190 g6190_1 g6190_0 gnd
+C1  g6190_1 gnd 2.080806f
+C2  g6190_0 gnd 2.080806f
+R1 g6190_1 g6190_0 2.224404
+.ends
+
+.subckt netg2796 g2796_0 g2796_1 gnd
+C1  g2796_0 gnd 2.080806f
+C2  g2796_1 gnd 2.080806f
+R1 g2796_0 g2796_1 2.224404
+.ends
+
+.subckt netg1358 g1358_0 g1358_1 gnd
+C1  g1358_0 gnd 2.080806f
+C2  g1358_1 gnd 2.080806f
+R1 g1358_1 g1358_0 2.224404
+.ends
+
+.subckt netg6974 g6974_1 g6974_0 gnd
+C1  g6974_1 gnd 2.080806f
+C2  g6974_0 gnd 2.080806f
+R1 g6974_0 g6974_1 2.224404
+.ends
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+.subckt netg3051 g3051_1 g3051_0 gnd
+C1  g3051_1 gnd 2.080806f
+C2  g3051_0 gnd 2.080806f
+R1 g3051_1 g3051_0 2.224404
+.ends
+
+.subckt netg6889 g6889_1 g6889_0 gnd
+C1  g6889_1 gnd 2.080806f
+C2  g6889_0 gnd 2.080806f
+R1 g6889_0 g6889_1 2.224404
+.ends
+
+.subckt netg4253 g4253_1 g4253_0 gnd
+C1  g4253_1 gnd 2.080806f
+C2  g4253_0 gnd 2.080806f
+R1 g4253_1 g4253_0 2.224404
+.ends
+
+.subckt netg3981 g3981_0 g3981_1 gnd
+C1  g3981_0 gnd 2.080806f
+C2  g3981_1 gnd 2.080806f
+R1 g3981_1 g3981_0 2.224404
+.ends
+
+.subckt netg2710 g2710_2 g2710_0 gnd
+C1  g2710_2 gnd 2.080806f
+C2  g2710_0 gnd 2.080806f
+R1 g2710_0 g2710_2 2.224404
+.ends
+
+.subckt netg6972 g6972_1 g6972_0 gnd
+C1  g6972_1 gnd 2.080806f
+C2  g6972_0 gnd 2.080806f
+R1 g6972_1 g6972_0 2.224404
+.ends
+
+.subckt netg6158 g6158_0 g6158_2 gnd
+C1  g6158_0 gnd 2.080806f
+C2  g6158_2 gnd 2.080806f
+R1 g6158_0 g6158_2 2.224404
+.ends
+
+.subckt netg1894 g1894_1 g1894_0 gnd
+C1  g1894_1 gnd 2.080806f
+C2  g1894_0 gnd 2.080806f
+R1 g1894_0 g1894_1 2.224404
+.ends
+
+.subckt netg1960 g1960_0 g1960_1 gnd
+C1  g1960_0 gnd 2.080806f
+C2  g1960_1 gnd 2.080806f
+R1 g1960_0 g1960_1 2.224404
+.ends
+
+.subckt netg1176 g1176_1 g1176_0 gnd
+C1  g1176_1 gnd 2.080806f
+C2  g1176_0 gnd 2.080806f
+R1 g1176_0 g1176_1 2.224404
+.ends
+
+.subckt netg6065 g6065_1 g6065_0 gnd
+C1  g6065_1 gnd 2.080806f
+C2  g6065_0 gnd 2.080806f
+R1 g6065_1 g6065_0 2.224404
+.ends
+
+.subckt netg6963 g6963_1 g6963_0 gnd
+C1  g6963_1 gnd 2.080806f
+C2  g6963_0 gnd 2.080806f
+R1 g6963_0 g6963_1 2.224404
+.ends
+
+.subckt netg7023 g7023_0 g7023_1 gnd
+C1  g7023_0 gnd 2.080806f
+C2  g7023_1 gnd 2.080806f
+R1 g7023_1 g7023_0 2.224404
+.ends
+
+.subckt netx391 x391_0 x391_1 gnd
+C1  x391_0 gnd 2.080806f
+C2  x391_1 gnd 2.080806f
+R1 x391_1 x391_0 2.224404
+.ends
+
+.subckt netg2356 g2356_2 g2356_1 gnd
+C1  g2356_2 gnd 2.080806f
+C2  g2356_1 gnd 2.080806f
+R1 g2356_2 g2356_1 2.224404
+.ends
+
+.subckt netg1129 g1129_1 g1129_0 gnd
+C1  g1129_1 gnd 2.080806f
+C2  g1129_0 gnd 2.080806f
+R1 g1129_0 g1129_1 2.224404
+.ends
+
+.subckt netg6383 g6383_1 g6383_0 gnd
+C1  g6383_1 gnd 2.080806f
+C2  g6383_0 gnd 2.080806f
+R1 g6383_1 g6383_0 2.224404
+.ends
+
+.subckt netg2932 g2932_0 g2932_1 gnd
+C1  g2932_0 gnd 2.080806f
+C2  g2932_1 gnd 2.080806f
+R1 g2932_0 g2932_1 2.224404
+.ends
+
+.subckt netg7334 g7334_1 g7334_0 gnd
+C1  g7334_1 gnd 2.080806f
+C2  g7334_0 gnd 2.080806f
+R1 g7334_0 g7334_1 2.224404
+.ends
+
+.subckt netg6277 g6277_1 g6277_0 gnd
+C1  g6277_1 gnd 2.080806f
+C2  g6277_0 gnd 2.080806f
+R1 g6277_0 g6277_1 2.224404
+.ends
+
+.subckt netg3533 g3533_1 g3533_0 gnd
+C1  g3533_1 gnd 2.080806f
+C2  g3533_0 gnd 2.080806f
+R1 g3533_0 g3533_1 2.224404
+.ends
+
+.subckt netg5482 g5482_1 g5482_0 gnd
+C1  g5482_1 gnd 2.080806f
+C2  g5482_0 gnd 2.080806f
+R1 g5482_0 g5482_1 2.224404
+.ends
+
+.subckt netg3973 g3973_0 g3973_1 gnd
+C1  g3973_0 gnd 2.080806f
+C2  g3973_1 gnd 2.080806f
+R1 g3973_0 g3973_1 2.224404
+.ends
+
+.subckt netg7438 g7438_0 g7438_1 gnd
+C1  g7438_0 gnd 2.080806f
+C2  g7438_1 gnd 2.080806f
+R1 g7438_0 g7438_1 2.224404
+.ends
+
+.subckt netg6418 g6418_1 g6418_0 gnd
+C1  g6418_1 gnd 2.080806f
+C2  g6418_0 gnd 2.080806f
+R1 g6418_0 g6418_1 2.224404
+.ends
+
+.subckt netg7427 g7427_1 g7427_0 gnd
+C1  g7427_1 gnd 2.080806f
+C2  g7427_0 gnd 2.080806f
+R1 g7427_0 g7427_1 2.224404
+.ends
+
+.subckt netg7410 g7410_0 g7410_1 gnd
+C1  g7410_0 gnd 2.080806f
+C2  g7410_1 gnd 2.080806f
+R1 g7410_1 g7410_0 2.224404
+.ends
+
+.subckt netg4317 g4317_0 g4317_1 gnd
+C1  g4317_0 gnd 2.080806f
+C2  g4317_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4317_0 1 2.224404
+R2 1 g4317_1 2.224404
+.ends
+
+.subckt netg3499 g3499_1 g3499_0 gnd
+C1  g3499_1 gnd 2.080806f
+C2  g3499_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3499_0 2.224404
+R2 g3499_1 1 2.224404
+.ends
+
+.subckt netg6519 g6519_0 g6519_1 gnd
+C1  g6519_0 gnd 2.080806f
+C2  g6519_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6519_0 1 2.224404
+R2 1 g6519_1 2.224404
+.ends
+
+.subckt netg2770 g2770_1 g2770_0 gnd
+C1  g2770_1 gnd 2.080806f
+C2  g2770_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2770_0 2.224404
+R2 g2770_1 1 2.224404
+.ends
+
+.subckt netg3896 g3896_1 g3896_0 gnd
+C1  g3896_1 gnd 2.080806f
+C2  g3896_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3896_0 1 2.224404
+R2 1 g3896_1 2.224404
+.ends
+
+.subckt netg1385 g1385_1 g1385_0 gnd
+C1  g1385_1 gnd 2.080806f
+C2  g1385_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1385_0 1 2.224404
+R2 g1385_1 1 2.224404
+.ends
+
+.subckt netg4175 g4175_1 g4175_0 gnd
+C1  g4175_1 gnd 2.080806f
+C2  g4175_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4175_0 2.224404
+R2 g4175_1 1 2.224404
+.ends
+
+.subckt netg7116 g7116_2 g7116_1 g7116_0 gnd
+C1  g7116_2 gnd 2.080806f
+C2  g7116_1 gnd 2.080806f
+C3  g7116_0 gnd 2.080806f
+R1 g7116_0 g7116_2 2.224404
+R2 g7116_2 g7116_1 2.224404
+.ends
+
+.subckt netg3916 g3916_1 g3916_0 gnd
+C1  g3916_1 gnd 2.080806f
+C2  g3916_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3916_0 2.224404
+R2 g3916_1 1 2.224404
+.ends
+
+.subckt netg3572 g3572_1 g3572_0 gnd
+C1  g3572_1 gnd 2.080806f
+C2  g3572_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3572_0 1 2.224404
+R2 1 g3572_1 2.224404
+.ends
+
+.subckt netg6100 g6100_1 g6100_0 gnd
+C1  g6100_1 gnd 2.080806f
+C2  g6100_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6100_0 2.224404
+R2 g6100_1 1 2.224404
+.ends
+
+.subckt netg5361 g5361_1 g5361_0 gnd
+C1  g5361_1 gnd 2.080806f
+C2  g5361_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5361_0 2.224404
+R2 g5361_1 1 2.224404
+.ends
+
+.subckt netg5347 g5347_1 g5347_0 gnd
+C1  g5347_1 gnd 2.080806f
+C2  g5347_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5347_0 1 2.224404
+R2 1 g5347_1 2.224404
+.ends
+
+.subckt netg2229 g2229_1 g2229_0 gnd
+C1  g2229_1 gnd 2.080806f
+C2  g2229_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2229_0 1 2.224404
+R2 g2229_1 1 2.224404
+.ends
+
+.subckt netx452 x452_0 x452_1 gnd
+C1  x452_0 gnd 2.080806f
+C2  x452_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 x452_0 1 2.224404
+R2 1 x452_1 2.224404
+.ends
+
+.subckt netg6330 g6330_1 g6330_0 gnd
+C1  g6330_1 gnd 2.080806f
+C2  g6330_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6330_0 2.224404
+R2 g6330_1 1 2.224404
+.ends
+
+.subckt netg5128 g5128_2 g5128_1 g5128_0 gnd
+C1  g5128_2 gnd 2.080806f
+C2  g5128_1 gnd 2.080806f
+C3  g5128_0 gnd 2.080806f
+R1 g5128_0 g5128_1 2.224404
+R2 g5128_2 g5128_1 2.224404
+.ends
+
+.subckt netg7294 g7294_1 g7294_0 gnd
+C1  g7294_1 gnd 2.080806f
+C2  g7294_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7294_0 1 2.224404
+R2 1 g7294_1 2.224404
+.ends
+
+.subckt netg5349 g5349_1 g5349_0 gnd
+C1  g5349_1 gnd 2.080806f
+C2  g5349_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5349_0 1 2.224404
+R2 g5349_1 1 2.224404
+.ends
+
+.subckt netg1436 g1436_0 g1436_1 gnd
+C1  g1436_0 gnd 2.080806f
+C2  g1436_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1436_0 1 2.224404
+R2 1 g1436_1 2.224404
+.ends
+
+.subckt netg6436 g6436_1 g6436_0 gnd
+C1  g6436_1 gnd 2.080806f
+C2  g6436_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6436_0 1 2.224404
+R2 1 g6436_1 2.224404
+.ends
+
+.subckt netg3117 g3117_0 g3117_1 g3117_2 gnd
+C1  g3117_0 gnd 2.080806f
+C2  g3117_1 gnd 2.080806f
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+R1 g3117_0 g3117_1 2.224404
+R2 g3117_2 g3117_1 2.224404
+.ends
+
+.subckt netg6513 g6513_1 g6513_0 gnd
+C1  g6513_1 gnd 2.080806f
+C2  g6513_0 gnd 2.080806f
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+R1 g6513_0 1 2.224404
+R2 1 g6513_1 2.224404
+.ends
+
+.subckt netg5483 g5483_0 g5483_1 gnd
+C1  g5483_0 gnd 2.080806f
+C2  g5483_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5483_0 1 2.224404
+R2 1 g5483_1 2.224404
+.ends
+
+.subckt netg6604 g6604_1 g6604_0 gnd
+C1  g6604_1 gnd 2.080806f
+C2  g6604_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6604_0 2.224404
+R2 1 g6604_1 2.224404
+.ends
+
+.subckt netg7217 g7217_1 g7217_0 gnd
+C1  g7217_1 gnd 2.080806f
+C2  g7217_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7217_0 1 2.224404
+R2 1 g7217_1 2.224404
+.ends
+
+.subckt netg3413 g3413_0 g3413_1 gnd
+C1  g3413_0 gnd 2.080806f
+C2  g3413_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3413_0 1 2.224404
+R2 1 g3413_1 2.224404
+.ends
+
+.subckt netg5320 g5320_1 g5320_0 gnd
+C1  g5320_1 gnd 2.080806f
+C2  g5320_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5320_0 1 2.224404
+R2 1 g5320_1 2.224404
+.ends
+
+.subckt netg6173 g6173_1 g6173_0 gnd
+C1  g6173_1 gnd 2.080806f
+C2  g6173_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6173_0 2.224404
+R2 g6173_1 1 2.224404
+.ends
+
+.subckt netg4354 g4354_0 g4354_1 gnd
+C1  g4354_0 gnd 2.080806f
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+C3 1 gnd 2.080806f
+R1 1 g4354_0 2.224404
+R2 g4354_1 1 2.224404
+.ends
+
+.subckt netg5786 g5786_1 g5786_0 gnd
+C1  g5786_1 gnd 2.080806f
+C2  g5786_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5786_0 2.224404
+R2 g5786_1 1 2.224404
+.ends
+
+.subckt netg1453 g1453_1 g1453_0 gnd
+C1  g1453_1 gnd 2.080806f
+C2  g1453_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1453_0 1 2.224404
+R2 1 g1453_1 2.224404
+.ends
+
+.subckt netg6736 g6736_0 g6736_1 gnd
+C1  g6736_0 gnd 2.080806f
+C2  g6736_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6736_0 2.224404
+R2 g6736_1 1 2.224404
+.ends
+
+.subckt netg7103 g7103_0 g7103_1 gnd
+C1  g7103_0 gnd 2.080806f
+C2  g7103_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7103_0 1 2.224404
+R2 1 g7103_1 2.224404
+.ends
+
+.subckt netg4438 g4438_0 g4438_1 gnd
+C1  g4438_0 gnd 2.080806f
+C2  g4438_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4438_0 1 2.224404
+R2 g4438_1 1 2.224404
+.ends
+
+.subckt netg3977 g3977_1 g3977_0 gnd
+C1  g3977_1 gnd 2.080806f
+C2  g3977_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3977_0 1 2.224404
+R2 1 g3977_1 2.224404
+.ends
+
+.subckt netg6329 g6329_0 g6329_1 gnd
+C1  g6329_0 gnd 2.080806f
+C2  g6329_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6329_0 1 2.224404
+R2 g6329_1 1 2.224404
+.ends
+
+.subckt netg3324 g3324_1 g3324_2 g3324_0 gnd
+C1  g3324_1 gnd 2.080806f
+C2  g3324_2 gnd 2.080806f
+C3  g3324_0 gnd 2.080806f
+R1 g3324_1 g3324_0 2.224404
+R2 g3324_2 g3324_1 2.224404
+.ends
+
+.subckt netg6805 g6805_0 g6805_1 g6805_2 gnd
+C1  g6805_0 gnd 2.080806f
+C2  g6805_1 gnd 2.080806f
+C3  g6805_2 gnd 2.080806f
+R1 g6805_2 g6805_0 2.224404
+R2 g6805_1 g6805_2 2.224404
+.ends
+
+.subckt netg6823 g6823_1 g6823_0 gnd
+C1  g6823_1 gnd 2.080806f
+C2  g6823_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6823_0 1 2.224404
+R2 1 g6823_1 2.224404
+.ends
+
+.subckt netg4244 g4244_1 g4244_0 gnd
+C1  g4244_1 gnd 2.080806f
+C2  g4244_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4244_0 1 2.224404
+R2 1 g4244_1 2.224404
+.ends
+
+.subckt netg1490 g1490_1 g1490_0 gnd
+C1  g1490_1 gnd 2.080806f
+C2  g1490_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1490_0 1 2.224404
+R2 1 g1490_1 2.224404
+.ends
+
+.subckt netg5328 g5328_0 g5328_1 gnd
+C1  g5328_0 gnd 2.080806f
+C2  g5328_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5328_0 1 2.224404
+R2 1 g5328_1 2.224404
+.ends
+
+.subckt netg2543 g2543_0 g2543_1 g2543_2 gnd
+C1  g2543_0 gnd 2.080806f
+C2  g2543_1 gnd 2.080806f
+C3  g2543_2 gnd 2.080806f
+R1 g2543_0 g2543_2 2.224404
+R2 g2543_2 g2543_1 2.224404
+.ends
+
+.subckt netg6255 g6255_1 g6255_0 g6255_2 gnd
+C1  g6255_1 gnd 2.080806f
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+C3  g6255_2 gnd 2.080806f
+R1 g6255_0 g6255_2 2.224404
+R2 g6255_1 g6255_2 2.224404
+.ends
+
+.subckt netg6195 g6195_1 g6195_0 gnd
+C1  g6195_1 gnd 2.080806f
+C2  g6195_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6195_0 2.224404
+R2 1 g6195_1 2.224404
+.ends
+
+.subckt netg3481 g3481_0 g3481_1 gnd
+C1  g3481_0 gnd 2.080806f
+C2  g3481_1 gnd 2.080806f
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+R1 g3481_0 1 2.224404
+R2 g3481_1 1 2.224404
+.ends
+
+.subckt netg5970 g5970_1 g5970_0 gnd
+C1  g5970_1 gnd 2.080806f
+C2  g5970_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5970_0 1 2.224404
+R2 1 g5970_1 2.224404
+.ends
+
+.subckt netg6033 g6033_1 g6033_0 gnd
+C1  g6033_1 gnd 2.080806f
+C2  g6033_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6033_0 1 2.224404
+R2 1 g6033_1 2.224404
+.ends
+
+.subckt netg5030 g5030_2 g5030_1 g5030_0 gnd
+C1  g5030_2 gnd 2.080806f
+C2  g5030_1 gnd 2.080806f
+C3  g5030_0 gnd 2.080806f
+R1 g5030_1 g5030_0 2.224404
+R2 g5030_0 g5030_2 2.224404
+.ends
+
+.subckt netg5167 g5167_2 g5167_0 gnd
+C1  g5167_2 gnd 2.080806f
+C2  g5167_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5167_0 2.224404
+R2 g5167_2 1 2.224404
+.ends
+
+.subckt netg6903 g6903_1 g6903_0 gnd
+C1  g6903_1 gnd 2.080806f
+C2  g6903_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6903_0 1 2.224404
+R2 1 g6903_1 2.224404
+.ends
+
+.subckt netg4273 g4273_0 g4273_1 gnd
+C1  g4273_0 gnd 2.080806f
+C2  g4273_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4273_0 1 2.224404
+R2 1 g4273_1 2.224404
+.ends
+
+.subckt netg6037 g6037_0 g6037_1 gnd
+C1  g6037_0 gnd 2.080806f
+C2  g6037_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6037_0 2.224404
+R2 g6037_1 1 2.224404
+.ends
+
+.subckt netg6659 g6659_0 g6659_1 gnd
+C1  g6659_0 gnd 2.080806f
+C2  g6659_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6659_0 1 2.224404
+R2 1 g6659_1 2.224404
+.ends
+
+.subckt netg4629 g4629_1 g4629_0 gnd
+C1  g4629_1 gnd 2.080806f
+C2  g4629_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4629_0 2.224404
+R2 1 g4629_1 2.224404
+.ends
+
+.subckt netg7342 g7342_1 g7342_0 gnd
+C1  g7342_1 gnd 2.080806f
+C2  g7342_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7342_0 1 2.224404
+R2 1 g7342_1 2.224404
+.ends
+
+.subckt netg1225 g1225_0 g1225_1 gnd
+C1  g1225_0 gnd 2.080806f
+C2  g1225_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1225_0 2.224404
+R2 g1225_1 1 2.224404
+.ends
+
+.subckt netg5583 g5583_0 g5583_1 gnd
+C1  g5583_0 gnd 2.080806f
+C2  g5583_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5583_0 2.224404
+R2 1 g5583_1 2.224404
+.ends
+
+.subckt netg1045 g1045_0 g1045_2 gnd
+C1  g1045_0 gnd 2.080806f
+C2  g1045_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1045_0 1 2.224404
+R2 1 g1045_2 2.224404
+.ends
+
+.subckt netg6725 g6725_2 g6725_0 gnd
+C1  g6725_2 gnd 2.080806f
+C2  g6725_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6725_0 1 2.224404
+R2 1 g6725_2 2.224404
+.ends
+
+.subckt netg6886 g6886_0 g6886_1 gnd
+C1  g6886_0 gnd 2.080806f
+C2  g6886_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6886_0 2.224404
+R2 g6886_1 1 2.224404
+.ends
+
+.subckt netg7020 g7020_0 g7020_1 gnd
+C1  g7020_0 gnd 2.080806f
+C2  g7020_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7020_0 2.224404
+R2 g7020_1 1 2.224404
+.ends
+
+.subckt netg6634 g6634_2 g6634_1 g6634_0 gnd
+C1  g6634_2 gnd 2.080806f
+C2  g6634_1 gnd 2.080806f
+C3  g6634_0 gnd 2.080806f
+R1 g6634_0 g6634_1 2.224404
+R2 g6634_0 g6634_2 2.224404
+.ends
+
+.subckt netg4227 g4227_1 g4227_0 gnd
+C1  g4227_1 gnd 2.080806f
+C2  g4227_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4227_0 2.224404
+R2 g4227_1 1 2.224404
+.ends
+
+.subckt netg1039 g1039_1 g1039_2 gnd
+C1  g1039_1 gnd 2.080806f
+C2  g1039_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1039_1 1 2.224404
+R2 1 g1039_2 2.224404
+.ends
+
+.subckt netg1166 g1166_0 g1166_1 gnd
+C1  g1166_0 gnd 2.080806f
+C2  g1166_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1166_0 1 2.224404
+R2 1 g1166_1 2.224404
+.ends
+
+.subckt netg2513 g2513_1 g2513_2 g2513_0 gnd
+C1  g2513_1 gnd 2.080806f
+C2  g2513_2 gnd 2.080806f
+C3  g2513_0 gnd 2.080806f
+R1 g2513_1 g2513_0 2.224404
+R2 g2513_2 g2513_1 2.224404
+.ends
+
+.subckt netg566 g566_0 g566_1 gnd
+C1  g566_0 gnd 2.080806f
+C2  g566_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g566_0 1 2.224404
+R2 1 g566_1 2.224404
+.ends
+
+.subckt netg5963 g5963_1 g5963_0 gnd
+C1  g5963_1 gnd 2.080806f
+C2  g5963_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5963_0 1 2.224404
+R2 1 g5963_1 2.224404
+.ends
+
+.subckt netg2519 g2519_1 g2519_2 gnd
+C1  g2519_1 gnd 2.080806f
+C2  g2519_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2519_2 1 2.224404
+R2 g2519_1 1 2.224404
+.ends
+
+.subckt netg6538 g6538_1 g6538_0 gnd
+C1  g6538_1 gnd 2.080806f
+C2  g6538_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6538_0 1 2.224404
+R2 1 g6538_1 2.224404
+.ends
+
+.subckt netg7350 g7350_1 g7350_0 gnd
+C1  g7350_1 gnd 2.080806f
+C2  g7350_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7350_0 1 2.224404
+R2 g7350_1 1 2.224404
+.ends
+
+.subckt netg6043 g6043_1 g6043_0 gnd
+C1  g6043_1 gnd 2.080806f
+C2  g6043_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6043_0 2.224404
+R2 1 g6043_1 2.224404
+.ends
+
+.subckt netg1305 g1305_0 g1305_1 gnd
+C1  g1305_0 gnd 2.080806f
+C2  g1305_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1305_0 2.224404
+R2 g1305_1 1 2.224404
+.ends
+
+.subckt netg7209 g7209_0 g7209_1 gnd
+C1  g7209_0 gnd 2.080806f
+C2  g7209_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7209_0 2.224404
+R2 1 g7209_1 2.224404
+.ends
+
+.subckt netg5691 g5691_0 g5691_2 gnd
+C1  g5691_0 gnd 2.080806f
+C2  g5691_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5691_0 1 2.224404
+R2 1 g5691_2 2.224404
+.ends
+
+.subckt netg7068 g7068_1 g7068_0 g7068_2 gnd
+C1  g7068_1 gnd 2.080806f
+C2  g7068_0 gnd 2.080806f
+C3  g7068_2 gnd 2.080806f
+R1 g7068_1 g7068_0 2.224404
+R2 g7068_0 g7068_2 2.224404
+.ends
+
+.subckt netg3478 g3478_1 g3478_0 gnd
+C1  g3478_1 gnd 2.080806f
+C2  g3478_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3478_0 2.224404
+R2 g3478_1 1 2.224404
+.ends
+
+.subckt netg1130 g1130_1 g1130_0 gnd
+C1  g1130_1 gnd 2.080806f
+C2  g1130_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1130_0 2.224404
+R2 g1130_1 1 2.224404
+.ends
+
+.subckt netg6053 g6053_0 g6053_1 gnd
+C1  g6053_0 gnd 2.080806f
+C2  g6053_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6053_0 1 2.224404
+R2 1 g6053_1 2.224404
+.ends
+
+.subckt netg6328 g6328_1 g6328_0 gnd
+C1  g6328_1 gnd 2.080806f
+C2  g6328_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6328_0 1 2.224404
+R2 1 g6328_1 2.224404
+.ends
+
+.subckt netg1475 g1475_0 g1475_1 gnd
+C1  g1475_0 gnd 2.080806f
+C2  g1475_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1475_0 2.224404
+R2 g1475_1 1 2.224404
+.ends
+
+.subckt netg4437 g4437_1 g4437_0 gnd
+C1  g4437_1 gnd 2.080806f
+C2  g4437_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4437_0 2.224404
+R2 g4437_1 1 2.224404
+.ends
+
+.subckt netg4241 g4241_1 g4241_0 gnd
+C1  g4241_1 gnd 2.080806f
+C2  g4241_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4241_0 1 2.224404
+R2 g4241_1 1 2.224404
+.ends
+
+.subckt netg6921 g6921_1 g6921_2 g6921_0 gnd
+C1  g6921_1 gnd 2.080806f
+C2  g6921_2 gnd 2.080806f
+C3  g6921_0 gnd 2.080806f
+R1 g6921_1 g6921_0 2.224404
+R2 g6921_2 g6921_1 2.224404
+.ends
+
+.subckt netg1384 g1384_1 g1384_0 gnd
+C1  g1384_1 gnd 2.080806f
+C2  g1384_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1384_0 1 2.224404
+R2 1 g1384_1 2.224404
+.ends
+
+.subckt netg5355 g5355_0 g5355_1 gnd
+C1  g5355_0 gnd 2.080806f
+C2  g5355_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5355_0 2.224404
+R2 g5355_1 1 2.224404
+.ends
+
+.subckt netg5488 g5488_1 g5488_0 gnd
+C1  g5488_1 gnd 2.080806f
+C2  g5488_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5488_0 2.224404
+R2 g5488_1 1 2.224404
+.ends
+
+.subckt netx422 x422_1 x422_0 gnd
+C1  x422_1 gnd 2.080806f
+C2  x422_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x422_0 2.224404
+R2 x422_1 1 2.224404
+.ends
+
+.subckt netg4938 g4938_0 g4938_1 gnd
+C1  g4938_0 gnd 2.080806f
+C2  g4938_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4938_0 1 2.224404
+R2 1 g4938_1 2.224404
+.ends
+
+.subckt netg3495 g3495_0 g3495_1 gnd
+C1  g3495_0 gnd 2.080806f
+C2  g3495_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3495_0 2.224404
+R2 g3495_1 1 2.224404
+.ends
+
+.subckt netg6001 g6001_0 g6001_1 gnd
+C1  g6001_0 gnd 2.080806f
+C2  g6001_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6001_0 1 2.224404
+R2 1 g6001_1 2.224404
+.ends
+
+.subckt netg4279 g4279_0 g4279_1 gnd
+C1  g4279_0 gnd 2.080806f
+C2  g4279_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4279_0 2.224404
+R2 g4279_1 1 2.224404
+.ends
+
+.subckt netg6622 g6622_1 g6622_0 gnd
+C1  g6622_1 gnd 2.080806f
+C2  g6622_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6622_0 2.224404
+R2 g6622_1 1 2.224404
+.ends
+
+.subckt netg922 g922_2 g922_0 gnd
+C1  g922_2 gnd 2.080806f
+C2  g922_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g922_0 1 2.224404
+R2 1 g922_2 2.224404
+.ends
+
+.subckt netx381 x381_1 x381_0 gnd
+C1  x381_1 gnd 2.080806f
+C2  x381_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 x381_0 1 2.224404
+R2 1 x381_1 2.224404
+.ends
+
+.subckt netg6948 g6948_1 g6948_2 gnd
+C1  g6948_1 gnd 2.080806f
+C2  g6948_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6948_2 2.224404
+R2 g6948_1 1 2.224404
+.ends
+
+.subckt netx361 x361_0 x361_1 gnd
+C1  x361_0 gnd 2.080806f
+C2  x361_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x361_0 2.224404
+R2 x361_1 1 2.224404
+.ends
+
+.subckt netg5424 g5424_0 g5424_1 gnd
+C1  g5424_0 gnd 2.080806f
+C2  g5424_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5424_0 1 2.224404
+R2 1 g5424_1 2.224404
+.ends
+
+.subckt netg4056 g4056_1 g4056_0 gnd
+C1  g4056_1 gnd 2.080806f
+C2  g4056_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4056_0 1 2.224404
+R2 1 g4056_1 2.224404
+.ends
+
+.subckt netg2828 g2828_0 g2828_1 gnd
+C1  g2828_0 gnd 2.080806f
+C2  g2828_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2828_0 2.224404
+R2 g2828_1 1 2.224404
+.ends
+
+.subckt netg1000 g1000_1 g1000_2 gnd
+C1  g1000_1 gnd 2.080806f
+C2  g1000_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1000_1 1 2.224404
+R2 g1000_2 1 2.224404
+.ends
+
+.subckt netg5059 g5059_2 g5059_0 g5059_1 gnd
+C1  g5059_2 gnd 2.080806f
+C2  g5059_0 gnd 2.080806f
+C3  g5059_1 gnd 2.080806f
+R1 g5059_0 g5059_1 2.224404
+R2 g5059_1 g5059_2 2.224404
+.ends
+
+.subckt netg6168 g6168_1 g6168_0 gnd
+C1  g6168_1 gnd 2.080806f
+C2  g6168_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6168_0 1 2.224404
+R2 1 g6168_1 2.224404
+.ends
+
+.subckt netg4331 g4331_0 g4331_1 gnd
+C1  g4331_0 gnd 2.080806f
+C2  g4331_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4331_0 2.224404
+R2 1 g4331_1 2.224404
+.ends
+
+.subckt netg6484 g6484_0 g6484_1 g6484_2 gnd
+C1  g6484_0 gnd 2.080806f
+C2  g6484_1 gnd 2.080806f
+C3  g6484_2 gnd 2.080806f
+R1 g6484_0 g6484_2 2.224404
+R2 g6484_2 g6484_1 2.224404
+.ends
+
+.subckt netg3488 g3488_1 g3488_0 gnd
+C1  g3488_1 gnd 2.080806f
+C2  g3488_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3488_0 2.224404
+R2 g3488_1 1 2.224404
+.ends
+
+.subckt netg1390 g1390_2 g1390_0 g1390_1 gnd
+C1  g1390_2 gnd 2.080806f
+C2  g1390_0 gnd 2.080806f
+C3  g1390_1 gnd 2.080806f
+R1 g1390_0 g1390_1 2.224404
+R2 g1390_1 g1390_2 2.224404
+.ends
+
+.subckt netg3456 g3456_1 g3456_2 g3456_0 gnd
+C1  g3456_1 gnd 2.080806f
+C2  g3456_2 gnd 2.080806f
+C3  g3456_0 gnd 2.080806f
+R1 g3456_1 g3456_0 2.224404
+R2 g3456_2 g3456_1 2.224404
+.ends
+
+.subckt netg5429 g5429_0 g5429_1 gnd
+C1  g5429_0 gnd 2.080806f
+C2  g5429_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5429_0 1 2.224404
+R2 1 g5429_1 2.224404
+.ends
+
+.subckt netg1386 g1386_0 g1386_1 gnd
+C1  g1386_0 gnd 2.080806f
+C2  g1386_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1386_0 2.224404
+R2 g1386_1 1 2.224404
+.ends
+
+.subckt netg6220 g6220_0 g6220_2 gnd
+C1  g6220_0 gnd 2.080806f
+C2  g6220_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6220_0 1 2.224404
+R2 g6220_2 1 2.224404
+.ends
+
+.subckt netg3288 g3288_2 g3288_1 gnd
+C1  g3288_2 gnd 2.080806f
+C2  g3288_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3288_2 1 2.224404
+R2 g3288_1 1 2.224404
+.ends
+
+.subckt netg6533 g6533_1 g6533_0 gnd
+C1  g6533_1 gnd 2.080806f
+C2  g6533_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6533_0 2.224404
+R2 g6533_1 1 2.224404
+.ends
+
+.subckt netg5113 g5113_1 g5113_0 gnd
+C1  g5113_1 gnd 2.080806f
+C2  g5113_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5113_0 2.224404
+R2 1 g5113_1 2.224404
+.ends
+
+.subckt netg2949 g2949_0 g2949_1 gnd
+C1  g2949_0 gnd 2.080806f
+C2  g2949_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2949_0 1 2.224404
+R2 1 g2949_1 2.224404
+.ends
+
+.subckt netg6489 g6489_0 g6489_1 gnd
+C1  g6489_0 gnd 2.080806f
+C2  g6489_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6489_0 1 2.224404
+R2 1 g6489_1 2.224404
+.ends
+
+.subckt netg6655 g6655_1 g6655_0 gnd
+C1  g6655_1 gnd 2.080806f
+C2  g6655_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6655_0 2.224404
+R2 g6655_1 1 2.224404
+.ends
+
+.subckt netg3099 g3099_1 g3099_0 gnd
+C1  g3099_1 gnd 2.080806f
+C2  g3099_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3099_0 1 2.224404
+R2 1 g3099_1 2.224404
+.ends
+
+.subckt netg7383 g7383_1 g7383_0 gnd
+C1  g7383_1 gnd 2.080806f
+C2  g7383_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7383_0 1 2.224404
+R2 1 g7383_1 2.224404
+.ends
+
+.subckt netg7208 g7208_0 g7208_1 gnd
+C1  g7208_0 gnd 2.080806f
+C2  g7208_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7208_0 1 2.224404
+R2 1 g7208_1 2.224404
+.ends
+
+.subckt netg3000 g3000_1 g3000_0 gnd
+C1  g3000_1 gnd 2.080806f
+C2  g3000_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3000_0 1 2.224404
+R2 g3000_1 1 2.224404
+.ends
+
+.subckt netg6089 g6089_0 g6089_1 gnd
+C1  g6089_0 gnd 2.080806f
+C2  g6089_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6089_0 1 2.224404
+R2 1 g6089_1 2.224404
+.ends
+
+.subckt netg4293 g4293_1 g4293_0 gnd
+C1  g4293_1 gnd 2.080806f
+C2  g4293_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4293_0 2.224404
+R2 g4293_1 1 2.224404
+.ends
+
+.subckt netg6918 g6918_0 g6918_1 gnd
+C1  g6918_0 gnd 2.080806f
+C2  g6918_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6918_0 1 2.224404
+R2 1 g6918_1 2.224404
+.ends
+
+.subckt netg7388 g7388_1 g7388_0 gnd
+C1  g7388_1 gnd 2.080806f
+C2  g7388_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7388_0 2.224404
+R2 g7388_1 1 2.224404
+.ends
+
+.subckt netg4069 g4069_0 g4069_1 gnd
+C1  g4069_0 gnd 2.080806f
+C2  g4069_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4069_0 1 2.224404
+R2 1 g4069_1 2.224404
+.ends
+
+.subckt netx101 x101_1 x101_0 gnd
+C1  x101_1 gnd 2.080806f
+C2  x101_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x101_0 2.224404
+R2 x101_1 1 2.224404
+.ends
+
+.subckt netg6119 g6119_0 g6119_1 gnd
+C1  g6119_0 gnd 2.080806f
+C2  g6119_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6119_0 1 2.224404
+R2 g6119_1 1 2.224404
+.ends
+
+.subckt netg5267 g5267_1 g5267_0 gnd
+C1  g5267_1 gnd 2.080806f
+C2  g5267_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5267_0 1 2.224404
+R2 1 g5267_1 2.224404
+.ends
+
+.subckt netg2576 g2576_2 g2576_0 g2576_1 gnd
+C1  g2576_2 gnd 2.080806f
+C2  g2576_0 gnd 2.080806f
+C3  g2576_1 gnd 2.080806f
+R1 g2576_1 g2576_0 2.224404
+R2 g2576_0 g2576_2 2.224404
+.ends
+
+.subckt netg6660 g6660_0 g6660_1 gnd
+C1  g6660_0 gnd 2.080806f
+C2  g6660_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6660_0 1 2.224404
+R2 1 g6660_1 2.224404
+.ends
+
+.subckt netg4442 g4442_1 g4442_0 gnd
+C1  g4442_1 gnd 2.080806f
+C2  g4442_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4442_0 2.224404
+R2 g4442_1 1 2.224404
+.ends
+
+.subckt netg6266 g6266_2 g6266_0 g6266_1 gnd
+C1  g6266_2 gnd 2.080806f
+C2  g6266_0 gnd 2.080806f
+C3  g6266_1 gnd 2.080806f
+R1 g6266_0 g6266_1 2.224404
+R2 g6266_1 g6266_2 2.224404
+.ends
+
+.subckt netg2740 g2740_2 g2740_0 g2740_1 gnd
+C1  g2740_2 gnd 2.080806f
+C2  g2740_0 gnd 2.080806f
+C3  g2740_1 gnd 2.080806f
+R1 g2740_0 g2740_1 2.224404
+R2 g2740_2 g2740_0 2.224404
+.ends
+
+.subckt netg7165 g7165_0 g7165_1 gnd
+C1  g7165_0 gnd 2.080806f
+C2  g7165_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7165_0 2.224404
+R2 g7165_1 1 2.224404
+.ends
+
+.subckt netg2492 g2492_2 g2492_1 gnd
+C1  g2492_2 gnd 2.080806f
+C2  g2492_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2492_2 2.224404
+R2 g2492_1 1 2.224404
+.ends
+
+.subckt netg7406 g7406_1 g7406_0 gnd
+C1  g7406_1 gnd 2.080806f
+C2  g7406_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7406_0 1 2.224404
+R2 1 g7406_1 2.224404
+.ends
+
+.subckt netg6901 g6901_0 g6901_1 gnd
+C1  g6901_0 gnd 2.080806f
+C2  g6901_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6901_0 1 2.224404
+R2 1 g6901_1 2.224404
+.ends
+
+.subckt netg5444 g5444_0 g5444_1 gnd
+C1  g5444_0 gnd 2.080806f
+C2  g5444_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5444_0 1 2.224404
+R2 1 g5444_1 2.224404
+.ends
+
+.subckt netg3544 g3544_0 g3544_1 gnd
+C1  g3544_0 gnd 2.080806f
+C2  g3544_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3544_0 2.224404
+R2 g3544_1 1 2.224404
+.ends
+
+.subckt netg5050 g5050_1 g5050_0 g5050_2 gnd
+C1  g5050_1 gnd 2.080806f
+C2  g5050_0 gnd 2.080806f
+C3  g5050_2 gnd 2.080806f
+R1 g5050_0 g5050_1 2.224404
+R2 g5050_1 g5050_2 2.224404
+.ends
+
+.subckt netg7206 g7206_1 g7206_0 gnd
+C1  g7206_1 gnd 2.080806f
+C2  g7206_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7206_0 2.224404
+R2 g7206_1 1 2.224404
+.ends
+
+.subckt netg2838 g2838_1 g2838_0 gnd
+C1  g2838_1 gnd 2.080806f
+C2  g2838_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2838_0 2.224404
+R2 g2838_1 1 2.224404
+.ends
+
+.subckt netg1223 g1223_1 g1223_0 gnd
+C1  g1223_1 gnd 2.080806f
+C2  g1223_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1223_0 2.224404
+R2 g1223_1 1 2.224404
+.ends
+
+.subckt netg1557 g1557_1 g1557_0 gnd
+C1  g1557_1 gnd 2.080806f
+C2  g1557_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1557_0 2.224404
+R2 g1557_1 1 2.224404
+.ends
+
+.subckt netg6790 g6790_2 g6790_1 g6790_0 gnd
+C1  g6790_2 gnd 2.080806f
+C2  g6790_1 gnd 2.080806f
+C3  g6790_0 gnd 2.080806f
+R1 g6790_1 g6790_0 2.224404
+R2 g6790_2 g6790_1 2.224404
+.ends
+
+.subckt netg4204 g4204_0 g4204_1 gnd
+C1  g4204_0 gnd 2.080806f
+C2  g4204_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4204_0 1 2.224404
+R2 g4204_1 1 2.224404
+.ends
+
+.subckt netg6048 g6048_1 g6048_0 gnd
+C1  g6048_1 gnd 2.080806f
+C2  g6048_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6048_0 1 2.224404
+R2 g6048_1 1 2.224404
+.ends
+
+.subckt netg6613 g6613_1 g6613_0 gnd
+C1  g6613_1 gnd 2.080806f
+C2  g6613_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6613_0 1 2.224404
+R2 1 g6613_1 2.224404
+.ends
+
+.subckt netg5357 g5357_0 g5357_1 gnd
+C1  g5357_0 gnd 2.080806f
+C2  g5357_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5357_0 2.224404
+R2 g5357_1 1 2.224404
+.ends
+
+.subckt netg2483 g2483_2 g2483_1 gnd
+C1  g2483_2 gnd 2.080806f
+C2  g2483_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2483_2 1 2.224404
+R2 1 g2483_1 2.224404
+.ends
+
+.subckt netg4275 g4275_0 g4275_1 gnd
+C1  g4275_0 gnd 2.080806f
+C2  g4275_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4275_0 1 2.224404
+R2 g4275_1 1 2.224404
+.ends
+
+.subckt netg979 g979_0 g979_1 g979_2 gnd
+C1  g979_0 gnd 2.080806f
+C2  g979_1 gnd 2.080806f
+C3  g979_2 gnd 2.080806f
+R1 g979_0 g979_1 2.224404
+R2 g979_1 g979_2 2.224404
+.ends
+
+.subckt netg4228 g4228_1 g4228_0 gnd
+C1  g4228_1 gnd 2.080806f
+C2  g4228_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4228_0 1 2.224404
+R2 1 g4228_1 2.224404
+.ends
+
+.subckt netg3531 g3531_0 g3531_1 gnd
+C1  g3531_0 gnd 2.080806f
+C2  g3531_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3531_0 2.224404
+R2 1 g3531_1 2.224404
+.ends
+
+.subckt netg5024 g5024_2 g5024_0 gnd
+C1  g5024_2 gnd 2.080806f
+C2  g5024_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5024_0 2.224404
+R2 g5024_2 1 2.224404
+.ends
+
+.subckt netg4450 g4450_0 g4450_1 gnd
+C1  g4450_0 gnd 2.080806f
+C2  g4450_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4450_0 2.224404
+R2 g4450_1 1 2.224404
+.ends
+
+.subckt netg2759 g2759_1 g2759_0 gnd
+C1  g2759_1 gnd 2.080806f
+C2  g2759_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2759_0 1 2.224404
+R2 1 g2759_1 2.224404
+.ends
+
+.subckt netg5885 g5885_0 g5885_1 gnd
+C1  g5885_0 gnd 2.080806f
+C2  g5885_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5885_0 2.224404
+R2 g5885_1 1 2.224404
+.ends
+
+.subckt netg3062 g3062_1 g3062_0 gnd
+C1  g3062_1 gnd 2.080806f
+C2  g3062_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3062_0 2.224404
+R2 g3062_1 1 2.224404
+.ends
+
+.subckt netg6381 g6381_0 g6381_1 gnd
+C1  g6381_0 gnd 2.080806f
+C2  g6381_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6381_0 2.224404
+R2 g6381_1 1 2.224404
+.ends
+
+.subckt netg7349 g7349_1 g7349_0 gnd
+C1  g7349_1 gnd 2.080806f
+C2  g7349_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7349_0 1 2.224404
+R2 1 g7349_1 2.224404
+.ends
+
+.subckt netg6511 g6511_0 g6511_1 gnd
+C1  g6511_0 gnd 2.080806f
+C2  g6511_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6511_0 1 2.224404
+R2 1 g6511_1 2.224404
+.ends
+
+.subckt netg4976 g4976_2 g4976_1 g4976_0 gnd
+C1  g4976_2 gnd 2.080806f
+C2  g4976_1 gnd 2.080806f
+C3  g4976_0 gnd 2.080806f
+R1 g4976_1 g4976_0 2.224404
+R2 g4976_2 g4976_1 2.224404
+.ends
+
+.subckt netg4007 g4007_1 g4007_0 gnd
+C1  g4007_1 gnd 2.080806f
+C2  g4007_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4007_0 1 2.224404
+R2 1 g4007_1 2.224404
+.ends
+
+.subckt netx421 x421_1 x421_0 gnd
+C1  x421_1 gnd 2.080806f
+C2  x421_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 x421_0 1 2.224404
+R2 1 x421_1 2.224404
+.ends
+
+.subckt netg5325 g5325_1 g5325_0 gnd
+C1  g5325_1 gnd 2.080806f
+C2  g5325_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5325_0 2.224404
+R2 g5325_1 1 2.224404
+.ends
+
+.subckt netg6433 g6433_2 g6433_0 g6433_1 gnd
+C1  g6433_2 gnd 2.080806f
+C2  g6433_0 gnd 2.080806f
+C3  g6433_1 gnd 2.080806f
+R1 g6433_0 g6433_1 2.224404
+R2 g6433_1 g6433_2 2.224404
+.ends
+
+.subckt netg7079 g7079_1 g7079_0 gnd
+C1  g7079_1 gnd 2.080806f
+C2  g7079_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7079_0 2.224404
+R2 g7079_1 1 2.224404
+.ends
+
+.subckt netg6692 g6692_0 g6692_1 gnd
+C1  g6692_0 gnd 2.080806f
+C2  g6692_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6692_0 1 2.224404
+R2 1 g6692_1 2.224404
+.ends
+
+.subckt netg3102 g3102_1 g3102_0 gnd
+C1  g3102_1 gnd 2.080806f
+C2  g3102_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3102_0 1 2.224404
+R2 1 g3102_1 2.224404
+.ends
+
+.subckt netg1161 g1161_0 g1161_1 gnd
+C1  g1161_0 gnd 2.080806f
+C2  g1161_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1161_0 2.224404
+R2 g1161_1 1 2.224404
+.ends
+
+.subckt netg6462 g6462_1 g6462_0 gnd
+C1  g6462_1 gnd 2.080806f
+C2  g6462_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6462_0 2.224404
+R2 g6462_1 1 2.224404
+.ends
+
+.subckt netg970 g970_0 g970_1 g970_2 gnd
+C1  g970_0 gnd 2.080806f
+C2  g970_1 gnd 2.080806f
+C3  g970_2 gnd 2.080806f
+R1 g970_2 g970_0 2.224404
+R2 g970_1 g970_2 2.224404
+.ends
+
+.subckt netg5245 g5245_0 g5245_1 gnd
+C1  g5245_0 gnd 2.080806f
+C2  g5245_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5245_0 1 2.224404
+R2 g5245_1 1 2.224404
+.ends
+
+.subckt netg3919 g3919_0 g3919_1 gnd
+C1  g3919_0 gnd 2.080806f
+C2  g3919_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3919_0 1 2.224404
+R2 1 g3919_1 2.224404
+.ends
+
+.subckt netg1154 g1154_0 g1154_1 gnd
+C1  g1154_0 gnd 2.080806f
+C2  g1154_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1154_0 1 2.224404
+R2 1 g1154_1 2.224404
+.ends
+
+.subckt netg1407 g1407_1 g1407_0 gnd
+C1  g1407_1 gnd 2.080806f
+C2  g1407_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1407_0 1 2.224404
+R2 1 g1407_1 2.224404
+.ends
+
+.subckt netg6980 g6980_0 g6980_2 g6980_1 gnd
+C1  g6980_0 gnd 2.080806f
+C2  g6980_2 gnd 2.080806f
+C3  g6980_1 gnd 2.080806f
+R1 g6980_0 g6980_2 2.224404
+R2 g6980_2 g6980_1 2.224404
+.ends
+
+.subckt netg4024 g4024_1 g4024_0 gnd
+C1  g4024_1 gnd 2.080806f
+C2  g4024_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4024_0 2.224404
+R2 g4024_1 1 2.224404
+.ends
+
+.subckt netg3466 g3466_0 g3466_1 gnd
+C1  g3466_0 gnd 2.080806f
+C2  g3466_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3466_0 1 2.224404
+R2 1 g3466_1 2.224404
+.ends
+
+.subckt netg7167 g7167_1 g7167_0 gnd
+C1  g7167_1 gnd 2.080806f
+C2  g7167_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7167_0 1 2.224404
+R2 1 g7167_1 2.224404
+.ends
+
+.subckt netg4083 g4083_1 g4083_0 gnd
+C1  g4083_1 gnd 2.080806f
+C2  g4083_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4083_0 2.224404
+R2 g4083_1 1 2.224404
+.ends
+
+.subckt netg5990 g5990_1 g5990_0 gnd
+C1  g5990_1 gnd 2.080806f
+C2  g5990_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5990_0 2.224404
+R2 g5990_1 1 2.224404
+.ends
+
+.subckt netg7254 g7254_1 g7254_0 gnd
+C1  g7254_1 gnd 2.080806f
+C2  g7254_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7254_0 2.224404
+R2 g7254_1 1 2.224404
+.ends
+
+.subckt netg7432 g7432_0 g7432_1 gnd
+C1  g7432_0 gnd 2.080806f
+C2  g7432_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7432_0 2.224404
+R2 g7432_1 1 2.224404
+.ends
+
+.subckt netg7161 g7161_2 g7161_0 g7161_1 gnd
+C1  g7161_2 gnd 2.080806f
+C2  g7161_0 gnd 2.080806f
+C3  g7161_1 gnd 2.080806f
+R1 g7161_1 g7161_0 2.224404
+R2 g7161_2 g7161_1 2.224404
+.ends
+
+.subckt netg2999 g2999_0 g2999_1 gnd
+C1  g2999_0 gnd 2.080806f
+C2  g2999_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2999_0 2.224404
+R2 g2999_1 1 2.224404
+.ends
+
+.subckt netg2447 g2447_0 g2447_1 g2447_2 gnd
+C1  g2447_0 gnd 2.080806f
+C2  g2447_1 gnd 2.080806f
+C3  g2447_2 gnd 2.080806f
+R1 g2447_0 g2447_2 2.224404
+R2 g2447_2 g2447_1 2.224404
+.ends
+
+.subckt netg7413 g7413_1 g7413_0 gnd
+C1  g7413_1 gnd 2.080806f
+C2  g7413_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7413_0 2.224404
+R2 g7413_1 1 2.224404
+.ends
+
+.subckt netg2936 g2936_0 g2936_1 gnd
+C1  g2936_0 gnd 2.080806f
+C2  g2936_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2936_0 2.224404
+R2 g2936_1 1 2.224404
+.ends
+
+.subckt netx62 x62_1 x62_0 gnd
+C1  x62_1 gnd 2.080806f
+C2  x62_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 x62_0 1 2.224404
+R2 x62_1 1 2.224404
+.ends
+
+.subckt netg4433 g4433_0 g4433_1 gnd
+C1  g4433_0 gnd 2.080806f
+C2  g4433_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4433_0 1 2.224404
+R2 1 g4433_1 2.224404
+.ends
+
+.subckt netg1082 g1082_2 g1082_1 gnd
+C1  g1082_2 gnd 2.080806f
+C2  g1082_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1082_1 1 2.224404
+R2 1 g1082_2 2.224404
+.ends
+
+.subckt netg6388 g6388_1 g6388_0 gnd
+C1  g6388_1 gnd 2.080806f
+C2  g6388_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6388_0 2.224404
+R2 g6388_1 1 2.224404
+.ends
+
+.subckt netg4335 g4335_1 g4335_0 gnd
+C1  g4335_1 gnd 2.080806f
+C2  g4335_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4335_0 2.224404
+R2 g4335_1 1 2.224404
+.ends
+
+.subckt netg3985 g3985_0 g3985_1 gnd
+C1  g3985_0 gnd 2.080806f
+C2  g3985_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3985_0 2.224404
+R2 g3985_1 1 2.224404
+.ends
+
+.subckt netg7016 g7016_0 g7016_1 gnd
+C1  g7016_0 gnd 2.080806f
+C2  g7016_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7016_0 2.224404
+R2 1 g7016_1 2.224404
+.ends
+
+.subckt netg5296 g5296_1 g5296_0 gnd
+C1  g5296_1 gnd 2.080806f
+C2  g5296_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5296_0 2.224404
+R2 g5296_1 1 2.224404
+.ends
+
+.subckt netg5348 g5348_1 g5348_0 gnd
+C1  g5348_1 gnd 2.080806f
+C2  g5348_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5348_0 1 2.224404
+R2 g5348_1 1 2.224404
+.ends
+
+.subckt netg4037 g4037_1 g4037_0 gnd
+C1  g4037_1 gnd 2.080806f
+C2  g4037_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4037_0 2.224404
+R2 g4037_1 1 2.224404
+.ends
+
+.subckt netg4330 g4330_1 g4330_0 gnd
+C1  g4330_1 gnd 2.080806f
+C2  g4330_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4330_0 2.224404
+R2 g4330_1 1 2.224404
+.ends
+
+.subckt netg2441 g2441_1 g2441_0 g2441_2 gnd
+C1  g2441_1 gnd 2.080806f
+C2  g2441_0 gnd 2.080806f
+C3  g2441_2 gnd 2.080806f
+R1 g2441_0 g2441_1 2.224404
+R2 g2441_0 g2441_2 2.224404
+.ends
+
+.subckt netx172 x172_1 x172_0 gnd
+C1  x172_1 gnd 2.080806f
+C2  x172_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x172_0 2.224404
+R2 1 x172_1 2.224404
+.ends
+
+.subckt netg5625 g5625_1 g5625_2 gnd
+C1  g5625_1 gnd 2.080806f
+C2  g5625_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5625_2 1 2.224404
+R2 1 g5625_1 2.224404
+.ends
+
+.subckt netg5104 g5104_2 g5104_0 g5104_1 gnd
+C1  g5104_2 gnd 2.080806f
+C2  g5104_0 gnd 2.080806f
+C3  g5104_1 gnd 2.080806f
+R1 g5104_2 g5104_0 2.224404
+R2 g5104_1 g5104_2 2.224404
+.ends
+
+.subckt netg5528 g5528_1 g5528_0 gnd
+C1  g5528_1 gnd 2.080806f
+C2  g5528_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5528_0 2.224404
+R2 g5528_1 1 2.224404
+.ends
+
+.subckt netg931 g931_2 g931_1 g931_0 gnd
+C1  g931_2 gnd 2.080806f
+C2  g931_1 gnd 2.080806f
+C3  g931_0 gnd 2.080806f
+R1 g931_0 g931_1 2.224404
+R2 g931_2 g931_0 2.224404
+.ends
+
+.subckt netg7345 g7345_1 g7345_0 gnd
+C1  g7345_1 gnd 2.080806f
+C2  g7345_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7345_0 1 2.224404
+R2 1 g7345_1 2.224404
+.ends
+
+.subckt netg5120 g5120_0 g5120_1 gnd
+C1  g5120_0 gnd 2.080806f
+C2  g5120_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5120_0 2.224404
+R2 g5120_1 1 2.224404
+.ends
+
+.subckt netg6971 g6971_1 g6971_0 gnd
+C1  g6971_1 gnd 2.080806f
+C2  g6971_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6971_0 1 2.224404
+R2 1 g6971_1 2.224404
+.ends
+
+.subckt netg5131 g5131_0 g5131_2 gnd
+C1  g5131_0 gnd 2.080806f
+C2  g5131_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5131_0 1 2.224404
+R2 1 g5131_2 2.224404
+.ends
+
+.subckt netg5273 g5273_0 g5273_1 gnd
+C1  g5273_0 gnd 2.080806f
+C2  g5273_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5273_0 2.224404
+R2 g5273_1 1 2.224404
+.ends
+
+.subckt netg5184 g5184_1 g5184_0 gnd
+C1  g5184_1 gnd 2.080806f
+C2  g5184_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5184_0 2.224404
+R2 g5184_1 1 2.224404
+.ends
+
+.subckt netg6526 g6526_0 g6526_1 gnd
+C1  g6526_0 gnd 2.080806f
+C2  g6526_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6526_0 2.224404
+R2 1 g6526_1 2.224404
+.ends
+
+.subckt netg6983 g6983_0 g6983_1 gnd
+C1  g6983_0 gnd 2.080806f
+C2  g6983_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6983_0 1 2.224404
+R2 1 g6983_1 2.224404
+.ends
+
+.subckt netg6735 g6735_0 g6735_1 gnd
+C1  g6735_0 gnd 2.080806f
+C2  g6735_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6735_0 2.224404
+R2 g6735_1 1 2.224404
+.ends
+
+.subckt netg1428 g1428_1 g1428_0 gnd
+C1  g1428_1 gnd 2.080806f
+C2  g1428_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1428_0 2.224404
+R2 1 g1428_1 2.224404
+.ends
+
+.subckt netg2224 g2224_1 g2224_0 gnd
+C1  g2224_1 gnd 2.080806f
+C2  g2224_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2224_0 2.224404
+R2 g2224_1 1 2.224404
+.ends
+
+.subckt netx92 x92_0 x92_1 gnd
+C1  x92_0 gnd 2.080806f
+C2  x92_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x92_0 2.224404
+R2 x92_1 1 2.224404
+.ends
+
+.subckt netg7371 g7371_0 g7371_1 gnd
+C1  g7371_0 gnd 2.080806f
+C2  g7371_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7371_0 1 2.224404
+R2 1 g7371_1 2.224404
+.ends
+
+.subckt netg7077 g7077_0 g7077_1 gnd
+C1  g7077_0 gnd 2.080806f
+C2  g7077_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7077_0 1 2.224404
+R2 1 g7077_1 2.224404
+.ends
+
+.subckt netg7296 g7296_0 g7296_1 gnd
+C1  g7296_0 gnd 2.080806f
+C2  g7296_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7296_0 2.224404
+R2 g7296_1 1 2.224404
+.ends
+
+.subckt netx501 x501_0 x501_1 gnd
+C1  x501_0 gnd 2.080806f
+C2  x501_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x501_0 2.224404
+R2 x501_1 1 2.224404
+.ends
+
+.subckt netg880 g880_2 g880_0 gnd
+C1  g880_2 gnd 2.080806f
+C2  g880_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g880_0 1 2.224404
+R2 1 g880_2 2.224404
+.ends
+
+.subckt netg6130 g6130_1 g6130_0 gnd
+C1  g6130_1 gnd 2.080806f
+C2  g6130_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6130_0 2.224404
+R2 1 g6130_1 2.224404
+.ends
+
+.subckt netg83 g83_0 g83_1 gnd
+C1  g83_0 gnd 2.080806f
+C2  g83_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g83_0 2.224404
+R2 1 g83_1 2.224404
+.ends
+
+.subckt netg7278 g7278_1 g7278_0 gnd
+C1  g7278_1 gnd 2.080806f
+C2  g7278_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7278_0 2.224404
+R2 g7278_1 1 2.224404
+.ends
+
+.subckt netg1531 g1531_1 g1531_0 gnd
+C1  g1531_1 gnd 2.080806f
+C2  g1531_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1531_0 2.224404
+R2 g1531_1 1 2.224404
+.ends
+
+.subckt netg2489 g2489_2 g2489_1 g2489_0 gnd
+C1  g2489_2 gnd 2.080806f
+C2  g2489_1 gnd 2.080806f
+C3  g2489_0 gnd 2.080806f
+R1 g2489_0 g2489_1 2.224404
+R2 g2489_2 g2489_0 2.224404
+.ends
+
+.subckt netg6307 g6307_1 g6307_0 gnd
+C1  g6307_1 gnd 2.080806f
+C2  g6307_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6307_0 1 2.224404
+R2 g6307_1 1 2.224404
+.ends
+
+.subckt netg6505 g6505_1 g6505_0 gnd
+C1  g6505_1 gnd 2.080806f
+C2  g6505_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6505_0 2.224404
+R2 g6505_1 1 2.224404
+.ends
+
+.subckt netg5767 g5767_1 g5767_0 gnd
+C1  g5767_1 gnd 2.080806f
+C2  g5767_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5767_0 1 2.224404
+R2 1 g5767_1 2.224404
+.ends
+
+.subckt netg6652 g6652_0 g6652_1 gnd
+C1  g6652_0 gnd 2.080806f
+C2  g6652_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6652_0 2.224404
+R2 g6652_1 1 2.224404
+.ends
+
+.subckt netg6291 g6291_1 g6291_0 gnd
+C1  g6291_1 gnd 2.080806f
+C2  g6291_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6291_0 1 2.224404
+R2 g6291_1 1 2.224404
+.ends
+
+.subckt netg5505 g5505_1 g5505_2 gnd
+C1  g5505_1 gnd 2.080806f
+C2  g5505_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5505_1 1 2.224404
+R2 1 g5505_2 2.224404
+.ends
+
+.subckt netx261 x261_0 x261_1 gnd
+C1  x261_0 gnd 2.080806f
+C2  x261_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 x261_0 1 2.224404
+R2 1 x261_1 2.224404
+.ends
+
+.subckt netg6172 g6172_0 g6172_1 gnd
+C1  g6172_0 gnd 2.080806f
+C2  g6172_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6172_0 2.224404
+R2 g6172_1 1 2.224404
+.ends
+
+.subckt netg5300 g5300_1 g5300_0 gnd
+C1  g5300_1 gnd 2.080806f
+C2  g5300_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5300_0 2.224404
+R2 1 g5300_1 2.224404
+.ends
+
+.subckt netg5833 g5833_1 g5833_0 gnd
+C1  g5833_1 gnd 2.080806f
+C2  g5833_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5833_0 1 2.224404
+R2 1 g5833_1 2.224404
+.ends
+
+.subckt netg6612 g6612_0 g6612_1 gnd
+C1  g6612_0 gnd 2.080806f
+C2  g6612_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6612_0 2.224404
+R2 g6612_1 1 2.224404
+.ends
+
+.subckt netg4416 g4416_1 g4416_0 gnd
+C1  g4416_1 gnd 2.080806f
+C2  g4416_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4416_0 1 2.224404
+R2 1 g4416_1 2.224404
+.ends
+
+.subckt netg4073 g4073_1 g4073_0 gnd
+C1  g4073_1 gnd 2.080806f
+C2  g4073_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4073_0 1 2.224404
+R2 1 g4073_1 2.224404
+.ends
+
+.subckt netg946 g946_2 g946_1 gnd
+C1  g946_2 gnd 2.080806f
+C2  g946_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g946_2 2.224404
+R2 g946_1 1 2.224404
+.ends
+
+.subckt netg7124 g7124_0 g7124_1 gnd
+C1  g7124_0 gnd 2.080806f
+C2  g7124_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7124_0 1 2.224404
+R2 1 g7124_1 2.224404
+.ends
+
+.subckt netg3336 g3336_0 g3336_1 g3336_2 gnd
+C1  g3336_0 gnd 2.080806f
+C2  g3336_1 gnd 2.080806f
+C3  g3336_2 gnd 2.080806f
+R1 g3336_2 g3336_0 2.224404
+R2 g3336_1 g3336_2 2.224404
+.ends
+
+.subckt netg871 g871_1 g871_2 gnd
+C1  g871_1 gnd 2.080806f
+C2  g871_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g871_2 2.224404
+R2 g871_1 1 2.224404
+.ends
+
+.subckt netg3216 g3216_0 g3216_2 g3216_1 gnd
+C1  g3216_0 gnd 2.080806f
+C2  g3216_2 gnd 2.080806f
+C3  g3216_1 gnd 2.080806f
+R1 g3216_1 g3216_0 2.224404
+R2 g3216_0 g3216_2 2.224404
+.ends
+
+.subckt netg2516 g2516_2 g2516_1 gnd
+C1  g2516_2 gnd 2.080806f
+C2  g2516_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2516_1 2.224404
+R2 g2516_2 1 2.224404
+.ends
+
+.subckt netg4011 g4011_1 g4011_0 gnd
+C1  g4011_1 gnd 2.080806f
+C2  g4011_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4011_0 2.224404
+R2 g4011_1 1 2.224404
+.ends
+
+.subckt netg3532 g3532_1 g3532_0 gnd
+C1  g3532_1 gnd 2.080806f
+C2  g3532_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3532_0 2.224404
+R2 1 g3532_1 2.224404
+.ends
+
+.subckt netg4186 g4186_1 g4186_0 gnd
+C1  g4186_1 gnd 2.080806f
+C2  g4186_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4186_0 2.224404
+R2 g4186_1 1 2.224404
+.ends
+
+.subckt netg4274 g4274_1 g4274_0 gnd
+C1  g4274_1 gnd 2.080806f
+C2  g4274_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4274_0 1 2.224404
+R2 1 g4274_1 2.224404
+.ends
+
+.subckt netg2674 g2674_1 g2674_2 g2674_0 gnd
+C1  g2674_1 gnd 2.080806f
+C2  g2674_2 gnd 2.080806f
+C3  g2674_0 gnd 2.080806f
+R1 g2674_1 g2674_0 2.224404
+R2 g2674_2 g2674_1 2.224404
+.ends
+
+.subckt netg4269 g4269_1 g4269_0 gnd
+C1  g4269_1 gnd 2.080806f
+C2  g4269_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4269_0 2.224404
+R2 1 g4269_1 2.224404
+.ends
+
+.subckt netg5229 g5229_2 g5229_1 g5229_0 gnd
+C1  g5229_2 gnd 2.080806f
+C2  g5229_1 gnd 2.080806f
+C3  g5229_0 gnd 2.080806f
+R1 g5229_2 g5229_0 2.224404
+R2 g5229_1 g5229_2 2.224404
+.ends
+
+.subckt netg7130 g7130_0 g7130_1 gnd
+C1  g7130_0 gnd 2.080806f
+C2  g7130_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7130_0 1 2.224404
+R2 1 g7130_1 2.224404
+.ends
+
+.subckt netg5223 g5223_2 g5223_1 g5223_0 gnd
+C1  g5223_2 gnd 2.080806f
+C2  g5223_1 gnd 2.080806f
+C3  g5223_0 gnd 2.080806f
+R1 g5223_0 g5223_1 2.224404
+R2 g5223_2 g5223_0 2.224404
+.ends
+
+.subckt netg3574 g3574_0 g3574_1 gnd
+C1  g3574_0 gnd 2.080806f
+C2  g3574_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3574_0 2.224404
+R2 g3574_1 1 2.224404
+.ends
+
+.subckt netg3525 g3525_0 g3525_1 gnd
+C1  g3525_0 gnd 2.080806f
+C2  g3525_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3525_0 2.224404
+R2 g3525_1 1 2.224404
+.ends
+
+.subckt netg5467 g5467_1 g5467_0 gnd
+C1  g5467_1 gnd 2.080806f
+C2  g5467_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5467_0 2.224404
+R2 1 g5467_1 2.224404
+.ends
+
+.subckt netg682 g682_1 g682_0 gnd
+C1  g682_1 gnd 2.080806f
+C2  g682_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g682_0 2.224404
+R2 g682_1 1 2.224404
+.ends
+
+.subckt netg1132 g1132_0 g1132_1 gnd
+C1  g1132_0 gnd 2.080806f
+C2  g1132_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1132_0 2.224404
+R2 g1132_1 1 2.224404
+.ends
+
+.subckt netg856 g856_2 g856_1 g856_0 gnd
+C1  g856_2 gnd 2.080806f
+C2  g856_1 gnd 2.080806f
+C3  g856_0 gnd 2.080806f
+R1 g856_0 g856_1 2.224404
+R2 g856_2 g856_0 2.224404
+.ends
+
+.subckt netg3890 g3890_0 g3890_1 gnd
+C1  g3890_0 gnd 2.080806f
+C2  g3890_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3890_0 1 2.224404
+R2 1 g3890_1 2.224404
+.ends
+
+.subckt netg1256 g1256_0 g1256_1 gnd
+C1  g1256_0 gnd 2.080806f
+C2  g1256_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1256_0 2.224404
+R2 g1256_1 1 2.224404
+.ends
+
+.subckt netg4235 g4235_1 g4235_0 gnd
+C1  g4235_1 gnd 2.080806f
+C2  g4235_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4235_0 1 2.224404
+R2 g4235_1 1 2.224404
+.ends
+
+.subckt netg3512 g3512_0 g3512_1 gnd
+C1  g3512_0 gnd 2.080806f
+C2  g3512_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3512_0 1 2.224404
+R2 g3512_1 1 2.224404
+.ends
+
+.subckt netg5077 g5077_0 g5077_2 gnd
+C1  g5077_0 gnd 2.080806f
+C2  g5077_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5077_0 2.224404
+R2 g5077_2 1 2.224404
+.ends
+
+.subckt netg868 g868_2 g868_0 g868_1 gnd
+C1  g868_2 gnd 2.080806f
+C2  g868_0 gnd 2.080806f
+C3  g868_1 gnd 2.080806f
+R1 g868_0 g868_1 2.224404
+R2 g868_1 g868_2 2.224404
+.ends
+
+.subckt netg1410 g1410_0 g1410_1 gnd
+C1  g1410_0 gnd 2.080806f
+C2  g1410_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1410_0 2.224404
+R2 g1410_1 1 2.224404
+.ends
+
+.subckt netg2633 g2633_1 g2633_0 gnd
+C1  g2633_1 gnd 2.080806f
+C2  g2633_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2633_0 2.224404
+R2 g2633_1 1 2.224404
+.ends
+
+.subckt netg5000 g5000_0 g5000_2 gnd
+C1  g5000_0 gnd 2.080806f
+C2  g5000_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5000_0 1 2.224404
+R2 1 g5000_2 2.224404
+.ends
+
+.subckt netg6621 g6621_0 g6621_1 gnd
+C1  g6621_0 gnd 2.080806f
+C2  g6621_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6621_0 1 2.224404
+R2 1 g6621_1 2.224404
+.ends
+
+.subckt netg1888 g1888_0 g1888_1 gnd
+C1  g1888_0 gnd 2.080806f
+C2  g1888_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1888_0 1 2.224404
+R2 1 g1888_1 2.224404
+.ends
+
+.subckt netg6650 g6650_0 g6650_1 gnd
+C1  g6650_0 gnd 2.080806f
+C2  g6650_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6650_0 2.224404
+R2 g6650_1 1 2.224404
+.ends
+
+.subckt netg7113 g7113_0 g7113_1 gnd
+C1  g7113_0 gnd 2.080806f
+C2  g7113_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7113_0 1 2.224404
+R2 1 g7113_1 2.224404
+.ends
+
+.subckt netg5519 g5519_1 g5519_0 gnd
+C1  g5519_1 gnd 2.080806f
+C2  g5519_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5519_0 1 2.224404
+R2 1 g5519_1 2.224404
+.ends
+
+.subckt netg5920 g5920_1 g5920_2 gnd
+C1  g5920_1 gnd 2.080806f
+C2  g5920_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5920_2 2.224404
+R2 1 g5920_1 2.224404
+.ends
+
+.subckt netg886 g886_0 g886_2 gnd
+C1  g886_0 gnd 2.080806f
+C2  g886_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g886_0 1 2.224404
+R2 1 g886_2 2.224404
+.ends
+
+.subckt netg3364 g3364_1 g3364_0 gnd
+C1  g3364_1 gnd 2.080806f
+C2  g3364_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3364_0 2.224404
+R2 g3364_1 1 2.224404
+.ends
+
+.subckt netg7271 g7271_1 g7271_0 gnd
+C1  g7271_1 gnd 2.080806f
+C2  g7271_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7271_0 1 2.224404
+R2 1 g7271_1 2.224404
+.ends
+
+.subckt netg5386 g5386_0 g5386_1 gnd
+C1  g5386_0 gnd 2.080806f
+C2  g5386_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5386_0 1 2.224404
+R2 1 g5386_1 2.224404
+.ends
+
+.subckt netg7426 g7426_0 g7426_1 gnd
+C1  g7426_0 gnd 2.080806f
+C2  g7426_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7426_0 2.224404
+R2 g7426_1 1 2.224404
+.ends
+
+.subckt netg5469 g5469_1 g5469_0 gnd
+C1  g5469_1 gnd 2.080806f
+C2  g5469_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5469_0 2.224404
+R2 g5469_1 1 2.224404
+.ends
+
+.subckt netg6878 g6878_0 g6878_1 gnd
+C1  g6878_0 gnd 2.080806f
+C2  g6878_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6878_0 1 2.224404
+R2 1 g6878_1 2.224404
+.ends
+
+.subckt netg4320 g4320_0 g4320_1 gnd
+C1  g4320_0 gnd 2.080806f
+C2  g4320_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4320_0 2.224404
+R2 g4320_1 1 2.224404
+.ends
+
+.subckt netg7140 g7140_0 g7140_1 gnd
+C1  g7140_0 gnd 2.080806f
+C2  g7140_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7140_0 2.224404
+R2 g7140_1 1 2.224404
+.ends
+
+.subckt netg1901 g1901_1 g1901_0 gnd
+C1  g1901_1 gnd 2.080806f
+C2  g1901_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1901_0 1 2.224404
+R2 1 g1901_1 2.224404
+.ends
+
+.subckt netg3065 g3065_1 g3065_0 gnd
+C1  g3065_1 gnd 2.080806f
+C2  g3065_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3065_0 2.224404
+R2 g3065_1 1 2.224404
+.ends
+
+.subckt netg5513 g5513_1 g5513_0 gnd
+C1  g5513_1 gnd 2.080806f
+C2  g5513_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5513_0 2.224404
+R2 g5513_1 1 2.224404
+.ends
+
+.subckt netg4946 g4946_2 g4946_0 g4946_1 gnd
+C1  g4946_2 gnd 2.080806f
+C2  g4946_0 gnd 2.080806f
+C3  g4946_1 gnd 2.080806f
+R1 g4946_0 g4946_2 2.224404
+R2 g4946_2 g4946_1 2.224404
+.ends
+
+.subckt netg7080 g7080_0 g7080_1 gnd
+C1  g7080_0 gnd 2.080806f
+C2  g7080_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7080_0 2.224404
+R2 1 g7080_1 2.224404
+.ends
+
+.subckt netg4439 g4439_0 g4439_1 gnd
+C1  g4439_0 gnd 2.080806f
+C2  g4439_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4439_0 1 2.224404
+R2 1 g4439_1 2.224404
+.ends
+
+.subckt netg3498 g3498_1 g3498_0 gnd
+C1  g3498_1 gnd 2.080806f
+C2  g3498_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3498_0 1 2.224404
+R2 1 g3498_1 2.224404
+.ends
+
+.subckt netg3078 g3078_0 g3078_1 gnd
+C1  g3078_0 gnd 2.080806f
+C2  g3078_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3078_0 1 2.224404
+R2 g3078_1 1 2.224404
+.ends
+
+.subckt netg5658 g5658_1 g5658_2 gnd
+C1  g5658_1 gnd 2.080806f
+C2  g5658_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5658_1 2.224404
+R2 g5658_2 1 2.224404
+.ends
+
+.subckt netg2609 g2609_2 g2609_1 gnd
+C1  g2609_2 gnd 2.080806f
+C2  g2609_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2609_1 1 2.224404
+R2 g2609_2 1 2.224404
+.ends
+
+.subckt netg3969 g3969_0 g3969_1 gnd
+C1  g3969_0 gnd 2.080806f
+C2  g3969_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3969_0 1 2.224404
+R2 g3969_1 1 2.224404
+.ends
+
+.subckt netg6699 g6699_0 g6699_1 gnd
+C1  g6699_0 gnd 2.080806f
+C2  g6699_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6699_0 2.224404
+R2 g6699_1 1 2.224404
+.ends
+
+.subckt netg1309 g1309_1 g1309_0 gnd
+C1  g1309_1 gnd 2.080806f
+C2  g1309_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1309_0 2.224404
+R2 g1309_1 1 2.224404
+.ends
+
+.subckt netg5640 g5640_0 g5640_2 gnd
+C1  g5640_0 gnd 2.080806f
+C2  g5640_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5640_0 1 2.224404
+R2 1 g5640_2 2.224404
+.ends
+
+.subckt netg5056 g5056_1 g5056_2 gnd
+C1  g5056_1 gnd 2.080806f
+C2  g5056_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5056_1 1 2.224404
+R2 g5056_2 1 2.224404
+.ends
+
+.subckt netg3339 g3339_2 g3339_1 gnd
+C1  g3339_2 gnd 2.080806f
+C2  g3339_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3339_1 1 2.224404
+R2 1 g3339_2 2.224404
+.ends
+
+.subckt netg6517 g6517_1 g6517_0 gnd
+C1  g6517_1 gnd 2.080806f
+C2  g6517_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6517_0 1 2.224404
+R2 g6517_1 1 2.224404
+.ends
+
+.subckt netg1257 g1257_1 g1257_0 gnd
+C1  g1257_1 gnd 2.080806f
+C2  g1257_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1257_0 1 2.224404
+R2 g1257_1 1 2.224404
+.ends
+
+.subckt netg5468 g5468_0 g5468_1 gnd
+C1  g5468_0 gnd 2.080806f
+C2  g5468_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5468_0 2.224404
+R2 g5468_1 1 2.224404
+.ends
+
+.subckt netg5331 g5331_1 g5331_0 gnd
+C1  g5331_1 gnd 2.080806f
+C2  g5331_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5331_0 2.224404
+R2 g5331_1 1 2.224404
+.ends
+
+.subckt netg5768 g5768_1 g5768_0 gnd
+C1  g5768_1 gnd 2.080806f
+C2  g5768_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5768_0 2.224404
+R2 g5768_1 1 2.224404
+.ends
+
+.subckt netg5543 g5543_1 g5543_0 g5543_2 gnd
+C1  g5543_1 gnd 2.080806f
+C2  g5543_0 gnd 2.080806f
+C3  g5543_2 gnd 2.080806f
+R1 g5543_0 g5543_1 2.224404
+R2 g5543_2 g5543_1 2.224404
+.ends
+
+.subckt netg3156 g3156_0 g3156_1 g3156_2 gnd
+C1  g3156_0 gnd 2.080806f
+C2  g3156_1 gnd 2.080806f
+C3  g3156_2 gnd 2.080806f
+R1 g3156_2 g3156_0 2.224404
+R2 g3156_1 g3156_2 2.224404
+.ends
+
+.subckt netg3905 g3905_0 g3905_1 gnd
+C1  g3905_0 gnd 2.080806f
+C2  g3905_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3905_0 2.224404
+R2 g3905_1 1 2.224404
+.ends
+
+.subckt netg3306 g3306_1 g3306_2 gnd
+C1  g3306_1 gnd 2.080806f
+C2  g3306_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3306_1 1 2.224404
+R2 1 g3306_2 2.224404
+.ends
+
+.subckt netg6506 g6506_0 g6506_1 gnd
+C1  g6506_0 gnd 2.080806f
+C2  g6506_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6506_0 2.224404
+R2 g6506_1 1 2.224404
+.ends
+
+.subckt netg5356 g5356_1 g5356_0 gnd
+C1  g5356_1 gnd 2.080806f
+C2  g5356_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5356_0 2.224404
+R2 1 g5356_1 2.224404
+.ends
+
+.subckt netg916 g916_2 g916_1 gnd
+C1  g916_2 gnd 2.080806f
+C2  g916_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g916_2 2.224404
+R2 1 g916_1 2.224404
+.ends
+
+.subckt netg6394 g6394_0 g6394_1 gnd
+C1  g6394_0 gnd 2.080806f
+C2  g6394_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6394_0 2.224404
+R2 g6394_1 1 2.224404
+.ends
+
+.subckt netg5015 g5015_1 g5015_2 g5015_0 gnd
+C1  g5015_1 gnd 2.080806f
+C2  g5015_2 gnd 2.080806f
+C3  g5015_0 gnd 2.080806f
+R1 g5015_1 g5015_0 2.224404
+R2 g5015_1 g5015_2 2.224404
+.ends
+
+.subckt netg6422 g6422_1 g6422_0 gnd
+C1  g6422_1 gnd 2.080806f
+C2  g6422_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6422_0 1 2.224404
+R2 1 g6422_1 2.224404
+.ends
+
+.subckt netg3059 g3059_0 g3059_1 gnd
+C1  g3059_0 gnd 2.080806f
+C2  g3059_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3059_0 2.224404
+R2 g3059_1 1 2.224404
+.ends
+
+.subckt netg2811 g2811_1 g2811_0 gnd
+C1  g2811_1 gnd 2.080806f
+C2  g2811_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2811_0 1 2.224404
+R2 1 g2811_1 2.224404
+.ends
+
+.subckt netg3926 g3926_0 g3926_1 gnd
+C1  g3926_0 gnd 2.080806f
+C2  g3926_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3926_0 2.224404
+R2 g3926_1 1 2.224404
+.ends
+
+.subckt netg3110 g3110_0 g3110_2 g3110_1 gnd
+C1  g3110_0 gnd 2.080806f
+C2  g3110_2 gnd 2.080806f
+C3  g3110_1 gnd 2.080806f
+R1 g3110_2 g3110_0 2.224404
+R2 g3110_1 g3110_2 2.224404
+.ends
+
+.subckt netg1889 g1889_0 g1889_1 gnd
+C1  g1889_0 gnd 2.080806f
+C2  g1889_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1889_0 2.224404
+R2 g1889_1 1 2.224404
+.ends
+
+.subckt netg6925 g6925_0 g6925_1 gnd
+C1  g6925_0 gnd 2.080806f
+C2  g6925_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6925_0 2.224404
+R2 g6925_1 1 2.224404
+.ends
+
+.subckt netg6313 g6313_1 g6313_0 gnd
+C1  g6313_1 gnd 2.080806f
+C2  g6313_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6313_0 2.224404
+R2 g6313_1 1 2.224404
+.ends
+
+.subckt netg3055 g3055_1 g3055_0 gnd
+C1  g3055_1 gnd 2.080806f
+C2  g3055_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3055_0 1 2.224404
+R2 1 g3055_1 2.224404
+.ends
+
+.subckt netg4016 g4016_1 g4016_0 gnd
+C1  g4016_1 gnd 2.080806f
+C2  g4016_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4016_0 2.224404
+R2 g4016_1 1 2.224404
+.ends
+
+.subckt netg2653 g2653_2 g2653_0 gnd
+C1  g2653_2 gnd 2.080806f
+C2  g2653_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2653_0 2.224404
+R2 g2653_2 1 2.224404
+.ends
+
+.subckt netg6518 g6518_0 g6518_1 gnd
+C1  g6518_0 gnd 2.080806f
+C2  g6518_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6518_0 1 2.224404
+R2 1 g6518_1 2.224404
+.ends
+
+.subckt netg6010 g6010_0 g6010_1 gnd
+C1  g6010_0 gnd 2.080806f
+C2  g6010_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6010_0 1 2.224404
+R2 1 g6010_1 2.224404
+.ends
+
+.subckt netg3494 g3494_0 g3494_1 gnd
+C1  g3494_0 gnd 2.080806f
+C2  g3494_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3494_0 1 2.224404
+R2 1 g3494_1 2.224404
+.ends
+
+.subckt netg2928 g2928_0 g2928_1 gnd
+C1  g2928_0 gnd 2.080806f
+C2  g2928_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2928_0 2.224404
+R2 g2928_1 1 2.224404
+.ends
+
+.subckt netg4389 g4389_2 g4389_0 g4389_1 gnd
+C1  g4389_2 gnd 2.080806f
+C2  g4389_0 gnd 2.080806f
+C3  g4389_1 gnd 2.080806f
+R1 g4389_2 g4389_0 2.224404
+R2 g4389_1 g4389_2 2.224404
+.ends
+
+.subckt netg5953 g5953_0 g5953_1 gnd
+C1  g5953_0 gnd 2.080806f
+C2  g5953_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5953_0 2.224404
+R2 g5953_1 1 2.224404
+.ends
+
+.subckt netg2837 g2837_1 g2837_0 gnd
+C1  g2837_1 gnd 2.080806f
+C2  g2837_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2837_0 2.224404
+R2 g2837_1 1 2.224404
+.ends
+
+.subckt netg6499 g6499_2 g6499_0 gnd
+C1  g6499_2 gnd 2.080806f
+C2  g6499_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6499_0 1 2.224404
+R2 1 g6499_2 2.224404
+.ends
+
+.subckt netg6555 g6555_0 g6555_1 gnd
+C1  g6555_0 gnd 2.080806f
+C2  g6555_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6555_0 1 2.224404
+R2 1 g6555_1 2.224404
+.ends
+
+.subckt netg4341 g4341_0 g4341_1 gnd
+C1  g4341_0 gnd 2.080806f
+C2  g4341_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4341_0 2.224404
+R2 g4341_1 1 2.224404
+.ends
+
+.subckt netg3300 g3300_1 g3300_2 g3300_0 gnd
+C1  g3300_1 gnd 2.080806f
+C2  g3300_2 gnd 2.080806f
+C3  g3300_0 gnd 2.080806f
+R1 g3300_2 g3300_0 2.224404
+R2 g3300_1 g3300_2 2.224404
+.ends
+
+.subckt netg7072 g7072_0 g7072_1 gnd
+C1  g7072_0 gnd 2.080806f
+C2  g7072_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7072_0 2.224404
+R2 g7072_1 1 2.224404
+.ends
+
+.subckt netg5646 g5646_2 g5646_1 gnd
+C1  g5646_2 gnd 2.080806f
+C2  g5646_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5646_1 1 2.224404
+R2 1 g5646_2 2.224404
+.ends
+
+.subckt netg3312 g3312_1 g3312_2 gnd
+C1  g3312_1 gnd 2.080806f
+C2  g3312_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3312_2 1 2.224404
+R2 1 g3312_1 2.224404
+.ends
+
+.subckt netg4420 g4420_0 g4420_1 gnd
+C1  g4420_0 gnd 2.080806f
+C2  g4420_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4420_0 1 2.224404
+R2 1 g4420_1 2.224404
+.ends
+
+.subckt netg7253 g7253_0 g7253_1 gnd
+C1  g7253_0 gnd 2.080806f
+C2  g7253_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7253_0 2.224404
+R2 1 g7253_1 2.224404
+.ends
+
+.subckt netg6410 g6410_1 g6410_0 gnd
+C1  g6410_1 gnd 2.080806f
+C2  g6410_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6410_0 2.224404
+R2 g6410_1 1 2.224404
+.ends
+
+.subckt netg1018 g1018_1 g1018_2 g1018_0 gnd
+C1  g1018_1 gnd 2.080806f
+C2  g1018_2 gnd 2.080806f
+C3  g1018_0 gnd 2.080806f
+R1 g1018_1 g1018_0 2.224404
+R2 g1018_2 g1018_1 2.224404
+.ends
+
+.subckt netg5813 g5813_1 g5813_0 g5813_2 gnd
+C1  g5813_1 gnd 2.080806f
+C2  g5813_0 gnd 2.080806f
+C3  g5813_2 gnd 2.080806f
+R1 g5813_2 g5813_0 2.224404
+R2 g5813_1 g5813_2 2.224404
+.ends
+
+.subckt netg4890 g4890_2 g4890_1 g4890_0 gnd
+C1  g4890_2 gnd 2.080806f
+C2  g4890_1 gnd 2.080806f
+C3  g4890_0 gnd 2.080806f
+R1 g4890_2 g4890_0 2.224404
+R2 g4890_1 g4890_2 2.224404
+.ends
+
+.subckt netg1288 g1288_1 g1288_0 gnd
+C1  g1288_1 gnd 2.080806f
+C2  g1288_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1288_0 1 2.224404
+R2 1 g1288_1 2.224404
+.ends
+
+.subckt netg4310 g4310_0 g4310_1 gnd
+C1  g4310_0 gnd 2.080806f
+C2  g4310_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4310_0 1 2.224404
+R2 1 g4310_1 2.224404
+.ends
+
+.subckt netg5774 g5774_0 g5774_1 gnd
+C1  g5774_0 gnd 2.080806f
+C2  g5774_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5774_0 2.224404
+R2 g5774_1 1 2.224404
+.ends
+
+.subckt netg3168 g3168_0 g3168_1 g3168_2 gnd
+C1  g3168_0 gnd 2.080806f
+C2  g3168_1 gnd 2.080806f
+C3  g3168_2 gnd 2.080806f
+R1 g3168_0 g3168_2 2.224404
+R2 g3168_1 g3168_2 2.224404
+.ends
+
+.subckt netg1951 g1951_2 g1951_1 g1951_0 gnd
+C1  g1951_2 gnd 2.080806f
+C2  g1951_1 gnd 2.080806f
+C3  g1951_0 gnd 2.080806f
+R1 g1951_0 g1951_2 2.224404
+R2 g1951_2 g1951_1 2.224404
+.ends
+
+.subckt netg2817 g2817_1 g2817_0 gnd
+C1  g2817_1 gnd 2.080806f
+C2  g2817_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2817_0 2.224404
+R2 g2817_1 1 2.224404
+.ends
+
+.subckt netg5790 g5790_1 g5790_0 gnd
+C1  g5790_1 gnd 2.080806f
+C2  g5790_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5790_0 2.224404
+R2 g5790_1 1 2.224404
+.ends
+
+.subckt netg3159 g3159_1 g3159_2 gnd
+C1  g3159_1 gnd 2.080806f
+C2  g3159_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3159_2 2.224404
+R2 g3159_1 1 2.224404
+.ends
+
+.subckt netg3101 g3101_0 g3101_1 gnd
+C1  g3101_0 gnd 2.080806f
+C2  g3101_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3101_0 1 2.224404
+R2 1 g3101_1 2.224404
+.ends
+
+.subckt netg4142 g4142_0 g4142_1 gnd
+C1  g4142_0 gnd 2.080806f
+C2  g4142_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4142_0 1 2.224404
+R2 1 g4142_1 2.224404
+.ends
+
+.subckt netg5359 g5359_1 g5359_0 gnd
+C1  g5359_1 gnd 2.080806f
+C2  g5359_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5359_0 2.224404
+R2 g5359_1 1 2.224404
+.ends
+
+.subckt netg4417 g4417_0 g4417_1 gnd
+C1  g4417_0 gnd 2.080806f
+C2  g4417_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4417_0 2.224404
+R2 g4417_1 1 2.224404
+.ends
+
+.subckt netg7054 g7054_0 g7054_2 g7054_1 gnd
+C1  g7054_0 gnd 2.080806f
+C2  g7054_2 gnd 2.080806f
+C3  g7054_1 gnd 2.080806f
+R1 g7054_1 g7054_0 2.224404
+R2 g7054_0 g7054_2 2.224404
+.ends
+
+.subckt netg6508 g6508_0 g6508_1 gnd
+C1  g6508_0 gnd 2.080806f
+C2  g6508_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6508_0 1 2.224404
+R2 1 g6508_1 2.224404
+.ends
+
+.subckt netg6558 g6558_0 g6558_1 gnd
+C1  g6558_0 gnd 2.080806f
+C2  g6558_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6558_0 2.224404
+R2 g6558_1 1 2.224404
+.ends
+
+.subckt netg6344 g6344_1 g6344_0 gnd
+C1  g6344_1 gnd 2.080806f
+C2  g6344_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6344_0 1 2.224404
+R2 1 g6344_1 2.224404
+.ends
+
+.subckt netg6615 g6615_1 g6615_2 gnd
+C1  g6615_1 gnd 2.080806f
+C2  g6615_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6615_1 1 2.224404
+R2 g6615_2 1 2.224404
+.ends
+
+.subckt netg7351 g7351_0 g7351_1 gnd
+C1  g7351_0 gnd 2.080806f
+C2  g7351_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7351_0 2.224404
+R2 g7351_1 1 2.224404
+.ends
+
+.subckt netg6645 g6645_0 g6645_2 g6645_1 gnd
+C1  g6645_0 gnd 2.080806f
+C2  g6645_2 gnd 2.080806f
+C3  g6645_1 gnd 2.080806f
+R1 g6645_2 g6645_0 2.224404
+R2 g6645_1 g6645_2 2.224404
+.ends
+
+.subckt netg6984 g6984_1 g6984_0 gnd
+C1  g6984_1 gnd 2.080806f
+C2  g6984_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6984_0 2.224404
+R2 g6984_1 1 2.224404
+.ends
+
+.subckt netg2591 g2591_0 g2591_1 g2591_2 gnd
+C1  g2591_0 gnd 2.080806f
+C2  g2591_1 gnd 2.080806f
+C3  g2591_2 gnd 2.080806f
+R1 g2591_2 g2591_0 2.224404
+R2 g2591_1 g2591_2 2.224404
+.ends
+
+.subckt netg1312 g1312_1 g1312_0 gnd
+C1  g1312_1 gnd 2.080806f
+C2  g1312_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1312_0 1 2.224404
+R2 1 g1312_1 2.224404
+.ends
+
+.subckt netg1070 g1070_2 g1070_0 g1070_1 gnd
+C1  g1070_2 gnd 2.080806f
+C2  g1070_0 gnd 2.080806f
+C3  g1070_1 gnd 2.080806f
+R1 g1070_0 g1070_2 2.224404
+R2 g1070_2 g1070_1 2.224404
+.ends
+
+.subckt netg5409 g5409_1 g5409_0 gnd
+C1  g5409_1 gnd 2.080806f
+C2  g5409_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5409_0 1 2.224404
+R2 1 g5409_1 2.224404
+.ends
+
+.subckt netg4258 g4258_1 g4258_0 gnd
+C1  g4258_1 gnd 2.080806f
+C2  g4258_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4258_0 1 2.224404
+R2 1 g4258_1 2.224404
+.ends
+
+.subckt netg7170 g7170_0 g7170_1 gnd
+C1  g7170_0 gnd 2.080806f
+C2  g7170_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7170_0 1 2.224404
+R2 1 g7170_1 2.224404
+.ends
+
+.subckt netg7391 g7391_1 g7391_2 gnd
+C1  g7391_1 gnd 2.080806f
+C2  g7391_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7391_2 2.224404
+R2 g7391_1 1 2.224404
+.ends
+
+.subckt netg5147 g5147_2 g5147_0 gnd
+C1  g5147_2 gnd 2.080806f
+C2  g5147_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5147_0 1 2.224404
+R2 1 g5147_2 2.224404
+.ends
+
+.subckt netg5585 g5585_0 g5585_1 gnd
+C1  g5585_0 gnd 2.080806f
+C2  g5585_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5585_0 1 2.224404
+R2 g5585_1 1 2.224404
+.ends
+
+.subckt netg7280 g7280_0 g7280_1 gnd
+C1  g7280_0 gnd 2.080806f
+C2  g7280_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7280_0 2.224404
+R2 g7280_1 1 2.224404
+.ends
+
+.subckt netg5552 g5552_1 g5552_0 gnd
+C1  g5552_1 gnd 2.080806f
+C2  g5552_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5552_0 2.224404
+R2 1 g5552_1 2.224404
+.ends
+
+.subckt netg6534 g6534_1 g6534_0 gnd
+C1  g6534_1 gnd 2.080806f
+C2  g6534_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6534_0 1 2.224404
+R2 1 g6534_1 2.224404
+.ends
+
+.subckt netg6589 g6589_0 g6589_1 gnd
+C1  g6589_0 gnd 2.080806f
+C2  g6589_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6589_0 2.224404
+R2 g6589_1 1 2.224404
+.ends
+
+.subckt netg3975 g3975_0 g3975_1 gnd
+C1  g3975_0 gnd 2.080806f
+C2  g3975_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3975_0 1 2.224404
+R2 g3975_1 1 2.224404
+.ends
+
+.subckt netg7234 g7234_2 g7234_1 g7234_0 gnd
+C1  g7234_2 gnd 2.080806f
+C2  g7234_1 gnd 2.080806f
+C3  g7234_0 gnd 2.080806f
+R1 g7234_0 g7234_1 2.224404
+R2 g7234_1 g7234_2 2.224404
+.ends
+
+.subckt netg4252 g4252_1 g4252_0 gnd
+C1  g4252_1 gnd 2.080806f
+C2  g4252_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4252_0 1 2.224404
+R2 1 g4252_1 2.224404
+.ends
+
+.subckt netg2713 g2713_1 g2713_0 g2713_2 gnd
+C1  g2713_1 gnd 2.080806f
+C2  g2713_0 gnd 2.080806f
+C3  g2713_2 gnd 2.080806f
+R1 g2713_1 g2713_0 2.224404
+R2 g2713_0 g2713_2 2.224404
+.ends
+
+.subckt netg5966 g5966_1 g5966_0 gnd
+C1  g5966_1 gnd 2.080806f
+C2  g5966_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5966_0 1 2.224404
+R2 1 g5966_1 2.224404
+.ends
+
+.subckt netg7295 g7295_1 g7295_0 gnd
+C1  g7295_1 gnd 2.080806f
+C2  g7295_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7295_0 2.224404
+R2 1 g7295_1 2.224404
+.ends
+
+.subckt netg6104 g6104_0 g6104_1 gnd
+C1  g6104_0 gnd 2.080806f
+C2  g6104_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6104_0 2.224404
+R2 1 g6104_1 2.224404
+.ends
+
+.subckt netg4371 g4371_0 g4371_2 g4371_1 gnd
+C1  g4371_0 gnd 2.080806f
+C2  g4371_2 gnd 2.080806f
+C3  g4371_1 gnd 2.080806f
+R1 g4371_0 g4371_2 2.224404
+R2 g4371_2 g4371_1 2.224404
+.ends
+
+.subckt netg6151 g6151_1 g6151_0 gnd
+C1  g6151_1 gnd 2.080806f
+C2  g6151_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6151_0 1 2.224404
+R2 g6151_1 1 2.224404
+.ends
+
+.subckt netg3562 g3562_0 g3562_1 gnd
+C1  g3562_0 gnd 2.080806f
+C2  g3562_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3562_0 2.224404
+R2 1 g3562_1 2.224404
+.ends
+
+.subckt netg1372 g1372_1 g1372_2 gnd
+C1  g1372_1 gnd 2.080806f
+C2  g1372_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1372_2 1 2.224404
+R2 1 g1372_1 2.224404
+.ends
+
+.subckt netg5276 g5276_0 g5276_1 gnd
+C1  g5276_0 gnd 2.080806f
+C2  g5276_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5276_0 1 2.224404
+R2 1 g5276_1 2.224404
+.ends
+
+.subckt netg6877 g6877_0 g6877_1 gnd
+C1  g6877_0 gnd 2.080806f
+C2  g6877_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6877_0 2.224404
+R2 1 g6877_1 2.224404
+.ends
+
+.subckt netg3001 g3001_1 g3001_0 gnd
+C1  g3001_1 gnd 2.080806f
+C2  g3001_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3001_0 2.224404
+R2 1 g3001_1 2.224404
+.ends
+
+.subckt netg6335 g6335_0 g6335_1 gnd
+C1  g6335_0 gnd 2.080806f
+C2  g6335_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6335_0 2.224404
+R2 g6335_1 1 2.224404
+.ends
+
+.subckt netg3505 g3505_1 g3505_0 gnd
+C1  g3505_1 gnd 2.080806f
+C2  g3505_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3505_0 2.224404
+R2 g3505_1 1 2.224404
+.ends
+
+.subckt netg4753 g4753_1 g4753_2 g4753_0 gnd
+C1  g4753_1 gnd 2.080806f
+C2  g4753_2 gnd 2.080806f
+C3  g4753_0 gnd 2.080806f
+R1 g4753_0 g4753_2 2.224404
+R2 g4753_2 g4753_1 2.224404
+.ends
+
+.subckt netg5188 g5188_2 g5188_1 gnd
+C1  g5188_2 gnd 2.080806f
+C2  g5188_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5188_2 2.224404
+R2 g5188_1 1 2.224404
+.ends
+
+.subckt netg2840 g2840_1 g2840_0 gnd
+C1  g2840_1 gnd 2.080806f
+C2  g2840_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2840_0 1 2.224404
+R2 1 g2840_1 2.224404
+.ends
+
+.subckt netg4187 g4187_1 g4187_0 gnd
+C1  g4187_1 gnd 2.080806f
+C2  g4187_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4187_0 1 2.224404
+R2 1 g4187_1 2.224404
+.ends
+
+.subckt netg3348 g3348_1 g3348_0 gnd
+C1  g3348_1 gnd 2.080806f
+C2  g3348_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3348_0 2.224404
+R2 1 g3348_1 2.224404
+.ends
+
+.subckt netg1556 g1556_0 g1556_1 gnd
+C1  g1556_0 gnd 2.080806f
+C2  g1556_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1556_0 1 2.224404
+R2 1 g1556_1 2.224404
+.ends
+
+.subckt netg7422 g7422_0 g7422_1 gnd
+C1  g7422_0 gnd 2.080806f
+C2  g7422_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7422_0 1 2.224404
+R2 1 g7422_1 2.224404
+.ends
+
+.subckt netg6212 g6212_1 g6212_0 gnd
+C1  g6212_1 gnd 2.080806f
+C2  g6212_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6212_0 2.224404
+R2 1 g6212_1 2.224404
+.ends
+
+.subckt netg4205 g4205_1 g4205_0 gnd
+C1  g4205_1 gnd 2.080806f
+C2  g4205_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4205_0 1 2.224404
+R2 1 g4205_1 2.224404
+.ends
+
+.subckt netg3426 g3426_2 g3426_1 gnd
+C1  g3426_2 gnd 2.080806f
+C2  g3426_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3426_1 2.224404
+R2 g3426_2 1 2.224404
+.ends
+
+.subckt netg4231 g4231_0 g4231_1 gnd
+C1  g4231_0 gnd 2.080806f
+C2  g4231_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4231_0 1 2.224404
+R2 1 g4231_1 2.224404
+.ends
+
+.subckt netg4970 g4970_0 g4970_2 g4970_1 gnd
+C1  g4970_0 gnd 2.080806f
+C2  g4970_2 gnd 2.080806f
+C3  g4970_1 gnd 2.080806f
+R1 g4970_1 g4970_0 2.224404
+R2 g4970_1 g4970_2 2.224404
+.ends
+
+.subckt netg6700 g6700_1 g6700_2 gnd
+C1  g6700_1 gnd 2.080806f
+C2  g6700_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6700_1 2.224404
+R2 g6700_2 1 2.224404
+.ends
+
+.subckt netg4337 g4337_0 g4337_1 gnd
+C1  g4337_0 gnd 2.080806f
+C2  g4337_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4337_0 2.224404
+R2 g4337_1 1 2.224404
+.ends
+
+.subckt netg2943 g2943_0 g2943_1 gnd
+C1  g2943_0 gnd 2.080806f
+C2  g2943_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2943_0 1 2.224404
+R2 1 g2943_1 2.224404
+.ends
+
+.subckt netg6230 g6230_0 g6230_1 g6230_2 gnd
+C1  g6230_0 gnd 2.080806f
+C2  g6230_1 gnd 2.080806f
+C3  g6230_2 gnd 2.080806f
+R1 g6230_2 g6230_0 2.224404
+R2 g6230_1 g6230_2 2.224404
+.ends
+
+.subckt netg4902 g4902_2 g4902_0 gnd
+C1  g4902_2 gnd 2.080806f
+C2  g4902_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4902_0 2.224404
+R2 g4902_2 1 2.224404
+.ends
+
+.subckt netx251 x251_0 x251_1 gnd
+C1  x251_0 gnd 2.080806f
+C2  x251_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 x251_0 1 2.224404
+R2 1 x251_1 2.224404
+.ends
+
+.subckt netg5301 g5301_0 g5301_1 gnd
+C1  g5301_0 gnd 2.080806f
+C2  g5301_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5301_0 2.224404
+R2 g5301_1 1 2.224404
+.ends
+
+.subckt netg7369 g7369_1 g7369_0 gnd
+C1  g7369_1 gnd 2.080806f
+C2  g7369_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7369_0 1 2.224404
+R2 1 g7369_1 2.224404
+.ends
+
+.subckt netg2976 g2976_1 g2976_0 gnd
+C1  g2976_1 gnd 2.080806f
+C2  g2976_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2976_0 2.224404
+R2 g2976_1 1 2.224404
+.ends
+
+.subckt netg2621 g2621_2 g2621_0 g2621_1 gnd
+C1  g2621_2 gnd 2.080806f
+C2  g2621_0 gnd 2.080806f
+C3  g2621_1 gnd 2.080806f
+R1 g2621_0 g2621_2 2.224404
+R2 g2621_1 g2621_2 2.224404
+.ends
+
+.subckt netg6821 g6821_1 g6821_0 gnd
+C1  g6821_1 gnd 2.080806f
+C2  g6821_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6821_0 1 2.224404
+R2 1 g6821_1 2.224404
+.ends
+
+.subckt netg6808 g6808_2 g6808_1 g6808_0 gnd
+C1  g6808_2 gnd 2.080806f
+C2  g6808_1 gnd 2.080806f
+C3  g6808_0 gnd 2.080806f
+R1 g6808_1 g6808_0 2.224404
+R2 g6808_2 g6808_1 2.224404
+.ends
+
+.subckt netg6993 g6993_0 g6993_1 gnd
+C1  g6993_0 gnd 2.080806f
+C2  g6993_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6993_0 1 2.224404
+R2 1 g6993_1 2.224404
+.ends
+
+.subckt netg5393 g5393_1 g5393_0 gnd
+C1  g5393_1 gnd 2.080806f
+C2  g5393_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5393_0 1 2.224404
+R2 1 g5393_1 2.224404
+.ends
+
+.subckt netg3566 g3566_1 g3566_0 gnd
+C1  g3566_1 gnd 2.080806f
+C2  g3566_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3566_0 2.224404
+R2 1 g3566_1 2.224404
+.ends
+
+.subckt netg4441 g4441_1 g4441_0 gnd
+C1  g4441_1 gnd 2.080806f
+C2  g4441_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4441_0 2.224404
+R2 1 g4441_1 2.224404
+.ends
+
+.subckt netg2827 g2827_0 g2827_1 gnd
+C1  g2827_0 gnd 2.080806f
+C2  g2827_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2827_0 1 2.224404
+R2 1 g2827_1 2.224404
+.ends
+
+.subckt netg5021 g5021_2 g5021_0 gnd
+C1  g5021_2 gnd 2.080806f
+C2  g5021_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5021_0 2.224404
+R2 g5021_2 1 2.224404
+.ends
+
+.subckt netg7010 g7010_0 g7010_1 gnd
+C1  g7010_0 gnd 2.080806f
+C2  g7010_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7010_0 1 2.224404
+R2 1 g7010_1 2.224404
+.ends
+
+.subckt netx42 x42_1 x42_0 gnd
+C1  x42_1 gnd 2.080806f
+C2  x42_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 x42_0 1 2.224404
+R2 1 x42_1 2.224404
+.ends
+
+.subckt netg4109 g4109_0 g4109_1 gnd
+C1  g4109_0 gnd 2.080806f
+C2  g4109_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4109_0 2.224404
+R2 1 g4109_1 2.224404
+.ends
+
+.subckt netg7387 g7387_0 g7387_1 gnd
+C1  g7387_0 gnd 2.080806f
+C2  g7387_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7387_0 1 2.224404
+R2 1 g7387_1 2.224404
+.ends
+
+.subckt netg3561 g3561_0 g3561_1 gnd
+C1  g3561_0 gnd 2.080806f
+C2  g3561_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3561_0 2.224404
+R2 g3561_1 1 2.224404
+.ends
+
+.subckt netg7355 g7355_1 g7355_0 gnd
+C1  g7355_1 gnd 2.080806f
+C2  g7355_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7355_0 2.224404
+R2 g7355_1 1 2.224404
+.ends
+
+.subckt netg1514 g1514_1 g1514_0 gnd
+C1  g1514_1 gnd 2.080806f
+C2  g1514_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1514_0 2.224404
+R2 g1514_1 1 2.224404
+.ends
+
+.subckt netg3970 g3970_0 g3970_1 gnd
+C1  g3970_0 gnd 2.080806f
+C2  g3970_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3970_0 2.224404
+R2 1 g3970_1 2.224404
+.ends
+
+.subckt netg1512 g1512_0 g1512_1 gnd
+C1  g1512_0 gnd 2.080806f
+C2  g1512_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1512_0 1 2.224404
+R2 g1512_1 1 2.224404
+.ends
+
+.subckt netg1379 g1379_1 g1379_0 gnd
+C1  g1379_1 gnd 2.080806f
+C2  g1379_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1379_0 2.224404
+R2 g1379_1 1 2.224404
+.ends
+
+.subckt netg3050 g3050_0 g3050_1 gnd
+C1  g3050_0 gnd 2.080806f
+C2  g3050_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3050_0 2.224404
+R2 g3050_1 1 2.224404
+.ends
+
+.subckt netg6661 g6661_0 g6661_1 gnd
+C1  g6661_0 gnd 2.080806f
+C2  g6661_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6661_0 2.224404
+R2 g6661_1 1 2.224404
+.ends
+
+.subckt netg5535 g5535_2 g5535_1 g5535_0 gnd
+C1  g5535_2 gnd 2.080806f
+C2  g5535_1 gnd 2.080806f
+C3  g5535_0 gnd 2.080806f
+R1 g5535_0 g5535_1 2.224404
+R2 g5535_1 g5535_2 2.224404
+.ends
+
+.subckt netg2689 g2689_0 g2689_1 g2689_2 gnd
+C1  g2689_0 gnd 2.080806f
+C2  g2689_1 gnd 2.080806f
+C3  g2689_2 gnd 2.080806f
+R1 g2689_0 g2689_1 2.224404
+R2 g2689_2 g2689_1 2.224404
+.ends
+
+.subckt netg5237 g5237_1 g5237_0 gnd
+C1  g5237_1 gnd 2.080806f
+C2  g5237_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5237_0 1 2.224404
+R2 1 g5237_1 2.224404
+.ends
+
+.subckt netg6676 g6676_1 g6676_0 gnd
+C1  g6676_1 gnd 2.080806f
+C2  g6676_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6676_0 2.224404
+R2 g6676_1 1 2.224404
+.ends
+
+.subckt netg4224 g4224_0 g4224_1 gnd
+C1  g4224_0 gnd 2.080806f
+C2  g4224_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4224_0 1 2.224404
+R2 g4224_1 1 2.224404
+.ends
+
+.subckt netg2841 g2841_1 g2841_0 gnd
+C1  g2841_1 gnd 2.080806f
+C2  g2841_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2841_0 1 2.224404
+R2 1 g2841_1 2.224404
+.ends
+
+.subckt netg5426 g5426_0 g5426_1 gnd
+C1  g5426_0 gnd 2.080806f
+C2  g5426_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5426_0 1 2.224404
+R2 g5426_1 1 2.224404
+.ends
+
+.subckt netg7292 g7292_1 g7292_0 gnd
+C1  g7292_1 gnd 2.080806f
+C2  g7292_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7292_0 2.224404
+R2 1 g7292_1 2.224404
+.ends
+
+.subckt netg2831 g2831_0 g2831_1 gnd
+C1  g2831_0 gnd 2.080806f
+C2  g2831_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2831_0 2.224404
+R2 g2831_1 1 2.224404
+.ends
+
+.subckt netg75 g75_1 g75_0 gnd
+C1  g75_1 gnd 2.080806f
+C2  g75_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g75_0 1 2.224404
+R2 1 g75_1 2.224404
+.ends
+
+.subckt netg4427 g4427_0 g4427_1 gnd
+C1  g4427_0 gnd 2.080806f
+C2  g4427_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4427_0 1 2.224404
+R2 g4427_1 1 2.224404
+.ends
+
+.subckt netg6209 g6209_0 g6209_1 gnd
+C1  g6209_0 gnd 2.080806f
+C2  g6209_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6209_0 2.224404
+R2 g6209_1 1 2.224404
+.ends
+
+.subckt netg5962 g5962_0 g5962_1 gnd
+C1  g5962_0 gnd 2.080806f
+C2  g5962_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5962_0 1 2.224404
+R2 1 g5962_1 2.224404
+.ends
+
+.subckt netx12 x12_1 x12_0 gnd
+C1  x12_1 gnd 2.080806f
+C2  x12_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x12_0 2.224404
+R2 x12_1 1 2.224404
+.ends
+
+.subckt netg6666 g6666_1 g6666_0 gnd
+C1  g6666_1 gnd 2.080806f
+C2  g6666_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6666_0 1 2.224404
+R2 1 g6666_1 2.224404
+.ends
+
+.subckt netg6133 g6133_0 g6133_1 gnd
+C1  g6133_0 gnd 2.080806f
+C2  g6133_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6133_0 2.224404
+R2 g6133_1 1 2.224404
+.ends
+
+.subckt netg7187 g7187_0 g7187_1 gnd
+C1  g7187_0 gnd 2.080806f
+C2  g7187_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7187_0 1 2.224404
+R2 1 g7187_1 2.224404
+.ends
+
+.subckt netg6892 g6892_1 g6892_0 gnd
+C1  g6892_1 gnd 2.080806f
+C2  g6892_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6892_0 2.224404
+R2 g6892_1 1 2.224404
+.ends
+
+.subckt netg7078 g7078_0 g7078_1 gnd
+C1  g7078_0 gnd 2.080806f
+C2  g7078_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7078_0 1 2.224404
+R2 1 g7078_1 2.224404
+.ends
+
+.subckt netg1549 g1549_1 g1549_0 gnd
+C1  g1549_1 gnd 2.080806f
+C2  g1549_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1549_0 1 2.224404
+R2 1 g1549_1 2.224404
+.ends
+
+.subckt netg4453 g4453_1 g4453_0 gnd
+C1  g4453_1 gnd 2.080806f
+C2  g4453_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4453_0 1 2.224404
+R2 1 g4453_1 2.224404
+.ends
+
+.subckt netg6734 g6734_1 g6734_0 gnd
+C1  g6734_1 gnd 2.080806f
+C2  g6734_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6734_0 2.224404
+R2 g6734_1 1 2.224404
+.ends
+
+.subckt netg5457 g5457_1 g5457_0 gnd
+C1  g5457_1 gnd 2.080806f
+C2  g5457_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5457_0 1 2.224404
+R2 g5457_1 1 2.224404
+.ends
+
+.subckt netg6411 g6411_1 g6411_0 gnd
+C1  g6411_1 gnd 2.080806f
+C2  g6411_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6411_0 2.224404
+R2 g6411_1 1 2.224404
+.ends
+
+.subckt netg2453 g2453_0 g2453_2 g2453_1 gnd
+C1  g2453_0 gnd 2.080806f
+C2  g2453_2 gnd 2.080806f
+C3  g2453_1 gnd 2.080806f
+R1 g2453_0 g2453_1 2.224404
+R2 g2453_2 g2453_0 2.224404
+.ends
+
+.subckt netg6468 g6468_0 g6468_1 gnd
+C1  g6468_0 gnd 2.080806f
+C2  g6468_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6468_0 1 2.224404
+R2 1 g6468_1 2.224404
+.ends
+
+.subckt netg5265 g5265_0 g5265_1 gnd
+C1  g5265_0 gnd 2.080806f
+C2  g5265_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5265_0 2.224404
+R2 g5265_1 1 2.224404
+.ends
+
+.subckt netg2803 g2803_1 g2803_0 gnd
+C1  g2803_1 gnd 2.080806f
+C2  g2803_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2803_0 2.224404
+R2 1 g2803_1 2.224404
+.ends
+
+.subckt netg4668 g4668_1 g4668_0 gnd
+C1  g4668_1 gnd 2.080806f
+C2  g4668_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4668_0 2.224404
+R2 1 g4668_1 2.224404
+.ends
+
+.subckt netg4305 g4305_1 g4305_0 gnd
+C1  g4305_1 gnd 2.080806f
+C2  g4305_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4305_0 2.224404
+R2 g4305_1 1 2.224404
+.ends
+
+.subckt netg6036 g6036_1 g6036_0 gnd
+C1  g6036_1 gnd 2.080806f
+C2  g6036_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6036_0 2.224404
+R2 g6036_1 1 2.224404
+.ends
+
+.subckt netg7402 g7402_0 g7402_1 gnd
+C1  g7402_0 gnd 2.080806f
+C2  g7402_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7402_0 2.224404
+R2 g7402_1 1 2.224404
+.ends
+
+.subckt netg4246 g4246_1 g4246_0 gnd
+C1  g4246_1 gnd 2.080806f
+C2  g4246_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4246_0 1 2.224404
+R2 1 g4246_1 2.224404
+.ends
+
+.subckt netg6273 g6273_0 g6273_1 gnd
+C1  g6273_0 gnd 2.080806f
+C2  g6273_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6273_0 1 2.224404
+R2 g6273_1 1 2.224404
+.ends
+
+.subckt netg6449 g6449_0 g6449_1 gnd
+C1  g6449_0 gnd 2.080806f
+C2  g6449_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6449_0 2.224404
+R2 g6449_1 1 2.224404
+.ends
+
+.subckt netg5602 g5602_0 g5602_1 gnd
+C1  g5602_0 gnd 2.080806f
+C2  g5602_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5602_0 1 2.224404
+R2 1 g5602_1 2.224404
+.ends
+
+.subckt netg7417 g7417_2 g7417_1 g7417_0 gnd
+C1  g7417_2 gnd 2.080806f
+C2  g7417_1 gnd 2.080806f
+C3  g7417_0 gnd 2.080806f
+R1 g7417_0 g7417_1 2.224404
+R2 g7417_1 g7417_2 2.224404
+.ends
+
+.subckt netg4362 g4362_2 g4362_1 gnd
+C1  g4362_2 gnd 2.080806f
+C2  g4362_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4362_2 1 2.224404
+R2 1 g4362_1 2.224404
+.ends
+
+.subckt netg6155 g6155_1 g6155_2 g6155_0 gnd
+C1  g6155_1 gnd 2.080806f
+C2  g6155_2 gnd 2.080806f
+C3  g6155_0 gnd 2.080806f
+R1 g6155_0 g6155_1 2.224404
+R2 g6155_2 g6155_0 2.224404
+.ends
+
+.subckt netg949 g949_0 g949_2 g949_1 gnd
+C1  g949_0 gnd 2.080806f
+C2  g949_2 gnd 2.080806f
+C3  g949_1 gnd 2.080806f
+R1 g949_1 g949_0 2.224404
+R2 g949_0 g949_2 2.224404
+.ends
+
+.subckt netg7290 g7290_1 g7290_0 gnd
+C1  g7290_1 gnd 2.080806f
+C2  g7290_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7290_0 2.224404
+R2 g7290_1 1 2.224404
+.ends
+
+.subckt netg7539 g7539_1 g7539_0 gnd
+C1  g7539_1 gnd 2.080806f
+C2  g7539_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7539_0 2.224404
+R2 g7539_1 1 2.224404
+.ends
+
+.subckt netg5324 g5324_0 g5324_1 gnd
+C1  g5324_0 gnd 2.080806f
+C2  g5324_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5324_0 1 2.224404
+R2 1 g5324_1 2.224404
+.ends
+
+.subckt netg6543 g6543_1 g6543_2 gnd
+C1  g6543_1 gnd 2.080806f
+C2  g6543_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6543_1 2.224404
+R2 g6543_2 1 2.224404
+.ends
+
+.subckt netg3716 g3716_0 g3716_1 gnd
+C1  g3716_0 gnd 2.080806f
+C2  g3716_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3716_0 2.224404
+R2 g3716_1 1 2.224404
+.ends
+
+.subckt netg6494 g6494_1 g6494_0 gnd
+C1  g6494_1 gnd 2.080806f
+C2  g6494_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6494_0 1 2.224404
+R2 1 g6494_1 2.224404
+.ends
+
+.subckt netg6837 g6837_2 g6837_1 g6837_0 gnd
+C1  g6837_2 gnd 2.080806f
+C2  g6837_1 gnd 2.080806f
+C3  g6837_0 gnd 2.080806f
+R1 g6837_1 g6837_0 2.224404
+R2 g6837_2 g6837_0 2.224404
+.ends
+
+.subckt netg6498 g6498_1 g6498_0 gnd
+C1  g6498_1 gnd 2.080806f
+C2  g6498_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6498_0 1 2.224404
+R2 1 g6498_1 2.224404
+.ends
+
+.subckt netg4040 g4040_0 g4040_1 gnd
+C1  g4040_0 gnd 2.080806f
+C2  g4040_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4040_0 1 2.224404
+R2 g4040_1 1 2.224404
+.ends
+
+.subckt netg5074 g5074_2 g5074_0 g5074_1 gnd
+C1  g5074_2 gnd 2.080806f
+C2  g5074_0 gnd 2.080806f
+C3  g5074_1 gnd 2.080806f
+R1 g5074_1 g5074_0 2.224404
+R2 g5074_2 g5074_1 2.224404
+.ends
+
+.subckt netg6605 g6605_0 g6605_1 gnd
+C1  g6605_0 gnd 2.080806f
+C2  g6605_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6605_0 1 2.224404
+R2 g6605_1 1 2.224404
+.ends
+
+.subckt netg6355 g6355_1 g6355_0 gnd
+C1  g6355_1 gnd 2.080806f
+C2  g6355_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6355_0 2.224404
+R2 g6355_1 1 2.224404
+.ends
+
+.subckt netg3048 g3048_0 g3048_1 gnd
+C1  g3048_0 gnd 2.080806f
+C2  g3048_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3048_0 2.224404
+R2 1 g3048_1 2.224404
+.ends
+
+.subckt netg6738 g6738_2 g6738_1 gnd
+C1  g6738_2 gnd 2.080806f
+C2  g6738_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6738_2 2.224404
+R2 g6738_1 1 2.224404
+.ends
+
+.subckt netg7137 g7137_1 g7137_0 gnd
+C1  g7137_1 gnd 2.080806f
+C2  g7137_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7137_0 2.224404
+R2 1 g7137_1 2.224404
+.ends
+
+.subckt netg6197 g6197_0 g6197_1 gnd
+C1  g6197_0 gnd 2.080806f
+C2  g6197_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6197_0 2.224404
+R2 g6197_1 1 2.224404
+.ends
+
+.subckt netg4291 g4291_0 g4291_1 gnd
+C1  g4291_0 gnd 2.080806f
+C2  g4291_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4291_0 1 2.224404
+R2 1 g4291_1 2.224404
+.ends
+
+.subckt netg4266 g4266_0 g4266_1 gnd
+C1  g4266_0 gnd 2.080806f
+C2  g4266_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4266_0 1 2.224404
+R2 1 g4266_1 2.224404
+.ends
+
+.subckt netg777 g777_0 g777_2 g777_1 gnd
+C1  g777_0 gnd 2.080806f
+C2  g777_2 gnd 2.080806f
+C3  g777_1 gnd 2.080806f
+R1 g777_1 g777_0 2.224404
+R2 g777_0 g777_2 2.224404
+.ends
+
+.subckt netg5427 g5427_1 g5427_0 gnd
+C1  g5427_1 gnd 2.080806f
+C2  g5427_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5427_0 1 2.224404
+R2 1 g5427_1 2.224404
+.ends
+
+.subckt netg3503 g3503_0 g3503_1 gnd
+C1  g3503_0 gnd 2.080806f
+C2  g3503_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3503_0 1 2.224404
+R2 1 g3503_1 2.224404
+.ends
+
+.subckt netg7199 g7199_1 g7199_0 gnd
+C1  g7199_1 gnd 2.080806f
+C2  g7199_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7199_0 2.224404
+R2 g7199_1 1 2.224404
+.ends
+
+.subckt netg6251 g6251_1 g6251_2 gnd
+C1  g6251_1 gnd 2.080806f
+C2  g6251_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6251_2 1 2.224404
+R2 g6251_1 1 2.224404
+.ends
+
+.subckt netg4064 g4064_0 g4064_1 gnd
+C1  g4064_0 gnd 2.080806f
+C2  g4064_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4064_0 2.224404
+R2 1 g4064_1 2.224404
+.ends
+
+.subckt netg3520 g3520_0 g3520_1 gnd
+C1  g3520_0 gnd 2.080806f
+C2  g3520_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3520_0 1 2.224404
+R2 1 g3520_1 2.224404
+.ends
+
+.subckt netg1937 g1937_0 g1937_1 gnd
+C1  g1937_0 gnd 2.080806f
+C2  g1937_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1937_0 2.224404
+R2 1 g1937_1 2.224404
+.ends
+
+.subckt netg1362 g1362_1 g1362_0 gnd
+C1  g1362_1 gnd 2.080806f
+C2  g1362_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1362_0 1 2.224404
+R2 1 g1362_1 2.224404
+.ends
+
+.subckt netg6487 g6487_1 g6487_0 gnd
+C1  g6487_1 gnd 2.080806f
+C2  g6487_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6487_0 2.224404
+R2 g6487_1 1 2.224404
+.ends
+
+.subckt netg5481 g5481_1 g5481_0 gnd
+C1  g5481_1 gnd 2.080806f
+C2  g5481_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5481_0 2.224404
+R2 g5481_1 1 2.224404
+.ends
+
+.subckt netg4218 g4218_1 g4218_0 gnd
+C1  g4218_1 gnd 2.080806f
+C2  g4218_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4218_0 2.224404
+R2 g4218_1 1 2.224404
+.ends
+
+.subckt netg6108 g6108_1 g6108_0 gnd
+C1  g6108_1 gnd 2.080806f
+C2  g6108_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6108_0 1 2.224404
+R2 1 g6108_1 2.224404
+.ends
+
+.subckt netg1429 g1429_1 g1429_0 gnd
+C1  g1429_1 gnd 2.080806f
+C2  g1429_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1429_0 1 2.224404
+R2 1 g1429_1 2.224404
+.ends
+
+.subckt netg3404 g3404_2 g3404_1 g3404_0 gnd
+C1  g3404_2 gnd 2.080806f
+C2  g3404_1 gnd 2.080806f
+C3  g3404_0 gnd 2.080806f
+R1 g3404_1 g3404_0 2.224404
+R2 g3404_0 g3404_2 2.224404
+.ends
+
+.subckt netg3906 g3906_1 g3906_0 gnd
+C1  g3906_1 gnd 2.080806f
+C2  g3906_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3906_0 1 2.224404
+R2 1 g3906_1 2.224404
+.ends
+
+.subckt netg3435 g3435_1 g3435_0 g3435_2 gnd
+C1  g3435_1 gnd 2.080806f
+C2  g3435_0 gnd 2.080806f
+C3  g3435_2 gnd 2.080806f
+R1 g3435_0 g3435_1 2.224404
+R2 g3435_2 g3435_0 2.224404
+.ends
+
+.subckt netg1258 g1258_1 g1258_0 gnd
+C1  g1258_1 gnd 2.080806f
+C2  g1258_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1258_0 2.224404
+R2 1 g1258_1 2.224404
+.ends
+
+.subckt netg7169 g7169_1 g7169_0 gnd
+C1  g7169_1 gnd 2.080806f
+C2  g7169_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7169_0 1 2.224404
+R2 g7169_1 1 2.224404
+.ends
+
+.subckt netg6308 g6308_1 g6308_0 gnd
+C1  g6308_1 gnd 2.080806f
+C2  g6308_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6308_0 2.224404
+R2 g6308_1 1 2.224404
+.ends
+
+.subckt netg3383 g3383_0 g3383_2 g3383_1 gnd
+C1  g3383_0 gnd 2.080806f
+C2  g3383_2 gnd 2.080806f
+C3  g3383_1 gnd 2.080806f
+R1 g3383_0 g3383_1 2.224404
+R2 g3383_1 g3383_2 2.224404
+.ends
+
+.subckt netg4426 g4426_0 g4426_1 gnd
+C1  g4426_0 gnd 2.080806f
+C2  g4426_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4426_0 1 2.224404
+R2 1 g4426_1 2.224404
+.ends
+
+.subckt netg6512 g6512_0 g6512_1 gnd
+C1  g6512_0 gnd 2.080806f
+C2  g6512_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6512_0 1 2.224404
+R2 1 g6512_1 2.224404
+.ends
+
+.subckt netg4207 g4207_0 g4207_1 gnd
+C1  g4207_0 gnd 2.080806f
+C2  g4207_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4207_0 1 2.224404
+R2 1 g4207_1 2.224404
+.ends
+
+.subckt netg6847 g6847_0 g6847_1 g6847_2 gnd
+C1  g6847_0 gnd 2.080806f
+C2  g6847_1 gnd 2.080806f
+C3  g6847_2 gnd 2.080806f
+R1 g6847_0 g6847_1 2.224404
+R2 g6847_1 g6847_2 2.224404
+.ends
+
+.subckt netg7390 g7390_0 g7390_1 gnd
+C1  g7390_0 gnd 2.080806f
+C2  g7390_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7390_0 2.224404
+R2 g7390_1 1 2.224404
+.ends
+
+.subckt netg4454 g4454_1 g4454_0 gnd
+C1  g4454_1 gnd 2.080806f
+C2  g4454_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4454_0 1 2.224404
+R2 1 g4454_1 2.224404
+.ends
+
+.subckt netg4221 g4221_0 g4221_1 gnd
+C1  g4221_0 gnd 2.080806f
+C2  g4221_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4221_0 1 2.224404
+R2 g4221_1 1 2.224404
+.ends
+
+.subckt netg3972 g3972_1 g3972_0 gnd
+C1  g3972_1 gnd 2.080806f
+C2  g3972_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3972_0 1 2.224404
+R2 g3972_1 1 2.224404
+.ends
+
+.subckt netg6463 g6463_0 g6463_1 gnd
+C1  g6463_0 gnd 2.080806f
+C2  g6463_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6463_0 1 2.224404
+R2 1 g6463_1 2.224404
+.ends
+
+.subckt netg1356 g1356_1 g1356_0 gnd
+C1  g1356_1 gnd 2.080806f
+C2  g1356_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1356_0 1 2.224404
+R2 1 g1356_1 2.224404
+.ends
+
+.subckt netg6675 g6675_0 g6675_1 gnd
+C1  g6675_0 gnd 2.080806f
+C2  g6675_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6675_0 2.224404
+R2 g6675_1 1 2.224404
+.ends
+
+.subckt netg7215 g7215_1 g7215_0 gnd
+C1  g7215_1 gnd 2.080806f
+C2  g7215_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7215_0 1 2.224404
+R2 g7215_1 1 2.224404
+.ends
+
+.subckt netg439 g439_2 g439_1 gnd
+C1  g439_2 gnd 2.080806f
+C2  g439_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g439_2 1 2.224404
+R2 1 g439_1 2.224404
+.ends
+
+.subckt netg2462 g2462_2 g2462_1 gnd
+C1  g2462_2 gnd 2.080806f
+C2  g2462_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2462_1 2.224404
+R2 g2462_2 1 2.224404
+.ends
+
+.subckt netg1136 g1136_1 g1136_0 gnd
+C1  g1136_1 gnd 2.080806f
+C2  g1136_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1136_0 2.224404
+R2 g1136_1 1 2.224404
+.ends
+
+.subckt netg6196 g6196_0 g6196_1 gnd
+C1  g6196_0 gnd 2.080806f
+C2  g6196_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6196_0 1 2.224404
+R2 1 g6196_1 2.224404
+.ends
+
+.subckt netg5294 g5294_0 g5294_1 gnd
+C1  g5294_0 gnd 2.080806f
+C2  g5294_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5294_0 2.224404
+R2 g5294_1 1 2.224404
+.ends
+
+.subckt netg4339 g4339_1 g4339_0 gnd
+C1  g4339_1 gnd 2.080806f
+C2  g4339_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4339_0 2.224404
+R2 g4339_1 1 2.224404
+.ends
+
+.subckt netg4425 g4425_1 g4425_0 gnd
+C1  g4425_1 gnd 2.080806f
+C2  g4425_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4425_0 1 2.224404
+R2 1 g4425_1 2.224404
+.ends
+
+.subckt netg6728 g6728_1 g6728_0 gnd
+C1  g6728_1 gnd 2.080806f
+C2  g6728_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6728_0 1 2.224404
+R2 1 g6728_1 2.224404
+.ends
+
+.subckt netg6890 g6890_0 g6890_1 gnd
+C1  g6890_0 gnd 2.080806f
+C2  g6890_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6890_0 1 2.224404
+R2 1 g6890_1 2.224404
+.ends
+
+.subckt netg1589 g1589_0 g1589_1 gnd
+C1  g1589_0 gnd 2.080806f
+C2  g1589_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1589_0 2.224404
+R2 g1589_1 1 2.224404
+.ends
+
+.subckt netg4248 g4248_1 g4248_0 gnd
+C1  g4248_1 gnd 2.080806f
+C2  g4248_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4248_0 2.224404
+R2 g4248_1 1 2.224404
+.ends
+
+.subckt netg3231 g3231_1 g3231_2 g3231_0 gnd
+C1  g3231_1 gnd 2.080806f
+C2  g3231_2 gnd 2.080806f
+C3  g3231_0 gnd 2.080806f
+R1 g3231_0 g3231_2 2.224404
+R2 g3231_2 g3231_1 2.224404
+.ends
+
+.subckt netg3228 g3228_2 g3228_1 g3228_0 gnd
+C1  g3228_2 gnd 2.080806f
+C2  g3228_1 gnd 2.080806f
+C3  g3228_0 gnd 2.080806f
+R1 g3228_0 g3228_1 2.224404
+R2 g3228_1 g3228_2 2.224404
+.ends
+
+.subckt netg6872 g6872_0 g6872_1 gnd
+C1  g6872_0 gnd 2.080806f
+C2  g6872_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6872_0 2.224404
+R2 g6872_1 1 2.224404
+.ends
+
+.subckt netg4991 g4991_0 g4991_2 g4991_1 gnd
+C1  g4991_0 gnd 2.080806f
+C2  g4991_2 gnd 2.080806f
+C3  g4991_1 gnd 2.080806f
+R1 g4991_0 g4991_1 2.224404
+R2 g4991_2 g4991_0 2.224404
+.ends
+
+.subckt netg1924 g1924_1 g1924_0 gnd
+C1  g1924_1 gnd 2.080806f
+C2  g1924_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1924_0 1 2.224404
+R2 g1924_1 1 2.224404
+.ends
+
+.subckt netg994 g994_1 g994_0 g994_2 gnd
+C1  g994_1 gnd 2.080806f
+C2  g994_0 gnd 2.080806f
+C3  g994_2 gnd 2.080806f
+R1 g994_0 g994_1 2.224404
+R2 g994_2 g994_0 2.224404
+.ends
+
+.subckt netg988 g988_1 g988_2 gnd
+C1  g988_1 gnd 2.080806f
+C2  g988_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g988_2 2.224404
+R2 1 g988_1 2.224404
+.ends
+
+.subckt netg6066 g6066_0 g6066_1 gnd
+C1  g6066_0 gnd 2.080806f
+C2  g6066_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6066_0 1 2.224404
+R2 1 g6066_1 2.224404
+.ends
+
+.subckt netg1220 g1220_0 g1220_1 gnd
+C1  g1220_0 gnd 2.080806f
+C2  g1220_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1220_0 1 2.224404
+R2 1 g1220_1 2.224404
+.ends
+
+.subckt netg5983 g5983_0 g5983_1 gnd
+C1  g5983_0 gnd 2.080806f
+C2  g5983_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5983_0 1 2.224404
+R2 g5983_1 1 2.224404
+.ends
+
+.subckt netg6334 g6334_1 g6334_0 gnd
+C1  g6334_1 gnd 2.080806f
+C2  g6334_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6334_0 2.224404
+R2 g6334_1 1 2.224404
+.ends
+
+.subckt netg7108 g7108_0 g7108_1 gnd
+C1  g7108_0 gnd 2.080806f
+C2  g7108_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7108_0 2.224404
+R2 g7108_1 1 2.224404
+.ends
+
+.subckt netg1237 g1237_1 g1237_0 gnd
+C1  g1237_1 gnd 2.080806f
+C2  g1237_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1237_0 2.224404
+R2 g1237_1 1 2.224404
+.ends
+
+.subckt netg620 g620_1 g620_0 gnd
+C1  g620_1 gnd 2.080806f
+C2  g620_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g620_0 1 2.224404
+R2 g620_1 1 2.224404
+.ends
+
+.subckt netg4994 g4994_0 g4994_2 gnd
+C1  g4994_0 gnd 2.080806f
+C2  g4994_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4994_0 1 2.224404
+R2 g4994_2 1 2.224404
+.ends
+
+.subckt netg6588 g6588_1 g6588_0 gnd
+C1  g6588_1 gnd 2.080806f
+C2  g6588_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6588_0 1 2.224404
+R2 1 g6588_1 2.224404
+.ends
+
+.subckt netg5560 g5560_2 g5560_1 gnd
+C1  g5560_2 gnd 2.080806f
+C2  g5560_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5560_2 1 2.224404
+R2 1 g5560_1 2.224404
+.ends
+
+.subckt netx411 x411_1 x411_0 gnd
+C1  x411_1 gnd 2.080806f
+C2  x411_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x411_0 2.224404
+R2 1 x411_1 2.224404
+.ends
+
+.subckt netg4107 g4107_1 g4107_0 gnd
+C1  g4107_1 gnd 2.080806f
+C2  g4107_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4107_0 2.224404
+R2 g4107_1 1 2.224404
+.ends
+
+.subckt netg5329 g5329_1 g5329_0 gnd
+C1  g5329_1 gnd 2.080806f
+C2  g5329_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5329_0 2.224404
+R2 1 g5329_1 2.224404
+.ends
+
+.subckt netg5906 g5906_0 g5906_1 g5906_2 gnd
+C1  g5906_0 gnd 2.080806f
+C2  g5906_1 gnd 2.080806f
+C3  g5906_2 gnd 2.080806f
+R1 g5906_1 g5906_0 2.224404
+R2 g5906_0 g5906_2 2.224404
+.ends
+
+.subckt netg2807 g2807_1 g2807_0 gnd
+C1  g2807_1 gnd 2.080806f
+C2  g2807_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2807_0 2.224404
+R2 g2807_1 1 2.224404
+.ends
+
+.subckt netg7083 g7083_1 g7083_0 gnd
+C1  g7083_1 gnd 2.080806f
+C2  g7083_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7083_0 2.224404
+R2 g7083_1 1 2.224404
+.ends
+
+.subckt netg3327 g3327_2 g3327_0 g3327_1 gnd
+C1  g3327_2 gnd 2.080806f
+C2  g3327_0 gnd 2.080806f
+C3  g3327_1 gnd 2.080806f
+R1 g3327_1 g3327_0 2.224404
+R2 g3327_2 g3327_1 2.224404
+.ends
+
+.subckt netg4939 g4939_1 g4939_0 gnd
+C1  g4939_1 gnd 2.080806f
+C2  g4939_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4939_0 1 2.224404
+R2 1 g4939_1 2.224404
+.ends
+
+.subckt netg997 g997_1 g997_2 g997_0 gnd
+C1  g997_1 gnd 2.080806f
+C2  g997_2 gnd 2.080806f
+C3  g997_0 gnd 2.080806f
+R1 g997_2 g997_0 2.224404
+R2 g997_2 g997_1 2.224404
+.ends
+
+.subckt netg2465 g2465_1 g2465_2 gnd
+C1  g2465_1 gnd 2.080806f
+C2  g2465_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2465_2 1 2.224404
+R2 1 g2465_1 2.224404
+.ends
+
+.subckt netg4446 g4446_0 g4446_1 gnd
+C1  g4446_0 gnd 2.080806f
+C2  g4446_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4446_0 1 2.224404
+R2 1 g4446_1 2.224404
+.ends
+
+.subckt netg1304 g1304_1 g1304_0 gnd
+C1  g1304_1 gnd 2.080806f
+C2  g1304_0 gnd 2.080806f
+.ends
+
+.subckt netx252 x252_1 x252_0 gnd
+C1  x252_1 gnd 2.080806f
+C2  x252_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 x252_0 1 2.224404
+R2 1 x252_1 2.224404
+.ends
+
+.subckt netg7231 g7231_2 g7231_0 gnd
+C1  g7231_2 gnd 2.080806f
+C2  g7231_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7231_0 2.224404
+R2 1 g7231_2 2.224404
+.ends
+
+.subckt netg6488 g6488_0 g6488_1 gnd
+C1  g6488_0 gnd 2.080806f
+C2  g6488_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6488_0 1 2.224404
+R2 1 g6488_1 2.224404
+.ends
+
+.subckt netg3392 g3392_2 g3392_0 g3392_1 gnd
+C1  g3392_2 gnd 2.080806f
+C2  g3392_0 gnd 2.080806f
+C3  g3392_1 gnd 2.080806f
+R1 g3392_0 g3392_2 2.224404
+R2 g3392_2 g3392_1 2.224404
+.ends
+
+.subckt netg485 g485_0 g485_1 gnd
+C1  g485_0 gnd 2.080806f
+C2  g485_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g485_0 2.224404
+R2 g485_1 1 2.224404
+.ends
+
+.subckt netg3530 g3530_1 g3530_0 gnd
+C1  g3530_1 gnd 2.080806f
+C2  g3530_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3530_0 2.224404
+R2 g3530_1 1 2.224404
+.ends
+
+.subckt netg4435 g4435_1 g4435_0 gnd
+C1  g4435_1 gnd 2.080806f
+C2  g4435_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4435_0 2.224404
+R2 g4435_1 1 2.224404
+.ends
+
+.subckt netg3479 g3479_1 g3479_0 gnd
+C1  g3479_1 gnd 2.080806f
+C2  g3479_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3479_0 1 2.224404
+R2 1 g3479_1 2.224404
+.ends
+
+.subckt netg5875 g5875_1 g5875_2 g5875_0 gnd
+C1  g5875_1 gnd 2.080806f
+C2  g5875_2 gnd 2.080806f
+C3  g5875_0 gnd 2.080806f
+R1 g5875_0 g5875_2 2.224404
+R2 g5875_2 g5875_1 2.224404
+.ends
+
+.subckt netg3984 g3984_1 g3984_0 gnd
+C1  g3984_1 gnd 2.080806f
+C2  g3984_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3984_0 1 2.224404
+R2 1 g3984_1 2.224404
+.ends
+
+.subckt netx532 x532_0 x532_1 gnd
+C1  x532_0 gnd 2.080806f
+C2  x532_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x532_0 2.224404
+R2 x532_1 1 2.224404
+.ends
+
+.subckt netg6039 g6039_1 g6039_0 gnd
+C1  g6039_1 gnd 2.080806f
+C2  g6039_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6039_0 1 2.224404
+R2 1 g6039_1 2.224404
+.ends
+
+.subckt netg6664 g6664_0 g6664_1 gnd
+C1  g6664_0 gnd 2.080806f
+C2  g6664_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6664_0 1 2.224404
+R2 1 g6664_1 2.224404
+.ends
+
+.subckt netg7531 g7531_1 g7531_0 gnd
+C1  g7531_1 gnd 2.080806f
+C2  g7531_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7531_0 1 2.224404
+R2 1 g7531_1 2.224404
+.ends
+
+.subckt netg7105 g7105_1 g7105_0 gnd
+C1  g7105_1 gnd 2.080806f
+C2  g7105_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7105_0 2.224404
+R2 g7105_1 1 2.224404
+.ends
+
+.subckt netg2996 g2996_1 g2996_0 gnd
+C1  g2996_1 gnd 2.080806f
+C2  g2996_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2996_0 1 2.224404
+R2 1 g2996_1 2.224404
+.ends
+
+.subckt netg1366 g1366_0 g1366_2 g1366_1 gnd
+C1  g1366_0 gnd 2.080806f
+C2  g1366_2 gnd 2.080806f
+C3  g1366_1 gnd 2.080806f
+R1 g1366_0 g1366_1 2.224404
+R2 g1366_1 g1366_2 2.224404
+.ends
+
+.subckt netg4307 g4307_0 g4307_1 gnd
+C1  g4307_0 gnd 2.080806f
+C2  g4307_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4307_0 1 2.224404
+R2 1 g4307_1 2.224404
+.ends
+
+.subckt netg3401 g3401_0 g3401_1 g3401_2 gnd
+C1  g3401_0 gnd 2.080806f
+C2  g3401_1 gnd 2.080806f
+C3  g3401_2 gnd 2.080806f
+R1 g3401_0 g3401_1 2.224404
+R2 g3401_2 g3401_0 2.224404
+.ends
+
+.subckt netg1498 g1498_1 g1498_0 gnd
+C1  g1498_1 gnd 2.080806f
+C2  g1498_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1498_0 1 2.224404
+R2 1 g1498_1 2.224404
+.ends
+
+.subckt netg7384 g7384_0 g7384_1 gnd
+C1  g7384_0 gnd 2.080806f
+C2  g7384_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7384_0 1 2.224404
+R2 1 g7384_1 2.224404
+.ends
+
+.subckt netg5959 g5959_0 g5959_1 gnd
+C1  g5959_0 gnd 2.080806f
+C2  g5959_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5959_0 1 2.224404
+R2 1 g5959_1 2.224404
+.ends
+
+.subckt netg3917 g3917_0 g3917_1 gnd
+C1  g3917_0 gnd 2.080806f
+C2  g3917_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3917_0 1 2.224404
+R2 g3917_1 1 2.224404
+.ends
+
+.subckt netg2946 g2946_1 g2946_0 gnd
+C1  g2946_1 gnd 2.080806f
+C2  g2946_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2946_0 1 2.224404
+R2 1 g2946_1 2.224404
+.ends
+
+.subckt netg2767 g2767_1 g2767_0 gnd
+C1  g2767_1 gnd 2.080806f
+C2  g2767_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2767_0 1 2.224404
+R2 1 g2767_1 2.224404
+.ends
+
+.subckt netg407 g407_0 g407_1 g407_2 gnd
+C1  g407_0 gnd 2.080806f
+C2  g407_1 gnd 2.080806f
+C3  g407_2 gnd 2.080806f
+R1 g407_0 g407_1 2.224404
+R2 g407_2 g407_0 2.224404
+.ends
+
+.subckt netg5608 g5608_0 g5608_1 gnd
+C1  g5608_0 gnd 2.080806f
+C2  g5608_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5608_0 1 2.224404
+R2 1 g5608_1 2.224404
+.ends
+
+.subckt netg6822 g6822_0 g6822_1 gnd
+C1  g6822_0 gnd 2.080806f
+C2  g6822_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6822_0 2.224404
+R2 g6822_1 1 2.224404
+.ends
+
+.subckt netg678 g678_0 g678_2 gnd
+C1  g678_0 gnd 2.080806f
+C2  g678_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g678_0 2.224404
+R2 g678_2 1 2.224404
+.ends
+
+.subckt netg6614 g6614_0 g6614_1 gnd
+C1  g6614_0 gnd 2.080806f
+C2  g6614_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6614_0 2.224404
+R2 g6614_1 1 2.224404
+.ends
+
+.subckt netx41 x41_1 x41_0 gnd
+C1  x41_1 gnd 2.080806f
+C2  x41_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 x41_0 1 2.224404
+R2 1 x41_1 2.224404
+.ends
+
+.subckt netg877 g877_1 g877_2 gnd
+C1  g877_1 gnd 2.080806f
+C2  g877_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g877_1 2.224404
+R2 g877_2 1 2.224404
+.ends
+
+.subckt netg2814 g2814_1 g2814_0 gnd
+C1  g2814_1 gnd 2.080806f
+C2  g2814_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2814_0 1 2.224404
+R2 1 g2814_1 2.224404
+.ends
+
+.subckt netg6009 g6009_0 g6009_1 gnd
+C1  g6009_0 gnd 2.080806f
+C2  g6009_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6009_0 1 2.224404
+R2 1 g6009_1 2.224404
+.ends
+
+.subckt netg7251 g7251_0 g7251_1 gnd
+C1  g7251_0 gnd 2.080806f
+C2  g7251_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7251_0 2.224404
+R2 g7251_1 1 2.224404
+.ends
+
+.subckt netg2746 g2746_1 g2746_0 gnd
+C1  g2746_1 gnd 2.080806f
+C2  g2746_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2746_0 1 2.224404
+R2 1 g2746_1 2.224404
+.ends
+
+.subckt netg5566 g5566_1 g5566_0 g5566_2 gnd
+C1  g5566_1 gnd 2.080806f
+C2  g5566_0 gnd 2.080806f
+C3  g5566_2 gnd 2.080806f
+R1 g5566_0 g5566_1 2.224404
+R2 g5566_2 g5566_0 2.224404
+.ends
+
+.subckt netg7177 g7177_1 g7177_2 gnd
+C1  g7177_1 gnd 2.080806f
+C2  g7177_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7177_2 1 2.224404
+R2 g7177_1 1 2.224404
+.ends
+
+.subckt netg6311 g6311_1 g6311_0 gnd
+C1  g6311_1 gnd 2.080806f
+C2  g6311_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6311_0 2.224404
+R2 1 g6311_1 2.224404
+.ends
+
+.subckt netg2926 g2926_0 g2926_1 gnd
+C1  g2926_0 gnd 2.080806f
+C2  g2926_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2926_0 2.224404
+R2 1 g2926_1 2.224404
+.ends
+
+.subckt netx531 x531_0 x531_1 gnd
+C1  x531_0 gnd 2.080806f
+C2  x531_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x531_0 2.224404
+R2 x531_1 1 2.224404
+.ends
+
+.subckt netg7401 g7401_1 g7401_0 gnd
+C1  g7401_1 gnd 2.080806f
+C2  g7401_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7401_0 2.224404
+R2 g7401_1 1 2.224404
+.ends
+
+.subckt netg1233 g1233_1 g1233_0 gnd
+C1  g1233_1 gnd 2.080806f
+C2  g1233_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1233_0 2.224404
+R2 g1233_1 1 2.224404
+.ends
+
+.subckt netg5777 g5777_0 g5777_1 gnd
+C1  g5777_0 gnd 2.080806f
+C2  g5777_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5777_0 1 2.224404
+R2 g5777_1 1 2.224404
+.ends
+
+.subckt netg7398 g7398_1 g7398_0 gnd
+C1  g7398_1 gnd 2.080806f
+C2  g7398_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7398_0 1 2.224404
+R2 g7398_1 1 2.224404
+.ends
+
+.subckt netg5887 g5887_1 g5887_2 gnd
+C1  g5887_1 gnd 2.080806f
+C2  g5887_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5887_2 1 2.224404
+R2 1 g5887_1 2.224404
+.ends
+
+.subckt netg3450 g3450_1 g3450_2 gnd
+C1  g3450_1 gnd 2.080806f
+C2  g3450_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3450_2 1 2.224404
+R2 1 g3450_1 2.224404
+.ends
+
+.subckt netg6364 g6364_1 g6364_0 gnd
+C1  g6364_1 gnd 2.080806f
+C2  g6364_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6364_0 2.224404
+R2 g6364_1 1 2.224404
+.ends
+
+.subckt netg2954 g2954_1 g2954_0 gnd
+C1  g2954_1 gnd 2.080806f
+C2  g2954_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2954_0 1 2.224404
+R2 1 g2954_1 2.224404
+.ends
+
+.subckt netg6691 g6691_1 g6691_0 gnd
+C1  g6691_1 gnd 2.080806f
+C2  g6691_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6691_0 2.224404
+R2 g6691_1 1 2.224404
+.ends
+
+.subckt netg1303 g1303_0 g1303_1 gnd
+C1  g1303_0 gnd 2.080806f
+C2  g1303_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1303_0 2.224404
+R2 g1303_1 1 2.224404
+.ends
+
+.subckt netg1155 g1155_1 g1155_0 gnd
+C1  g1155_1 gnd 2.080806f
+C2  g1155_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1155_0 2.224404
+R2 g1155_1 1 2.224404
+.ends
+
+.subckt netg5532 g5532_2 g5532_1 g5532_0 gnd
+C1  g5532_2 gnd 2.080806f
+C2  g5532_1 gnd 2.080806f
+C3  g5532_0 gnd 2.080806f
+R1 g5532_2 g5532_0 2.224404
+R2 g5532_1 g5532_2 2.224404
+.ends
+
+.subckt netg5006 g5006_1 g5006_2 gnd
+C1  g5006_1 gnd 2.080806f
+C2  g5006_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5006_1 2.224404
+R2 g5006_2 1 2.224404
+.ends
+
+.subckt netg1994 g1994_1 g1994_0 gnd
+C1  g1994_1 gnd 2.080806f
+C2  g1994_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1994_0 1 2.224404
+R2 g1994_1 1 2.224404
+.ends
+
+.subckt netg5363 g5363_0 g5363_1 gnd
+C1  g5363_0 gnd 2.080806f
+C2  g5363_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5363_0 1 2.224404
+R2 1 g5363_1 2.224404
+.ends
+
+.subckt netg2028 g2028_1 g2028_0 gnd
+C1  g2028_1 gnd 2.080806f
+C2  g2028_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2028_0 1 2.224404
+R2 g2028_1 1 2.224404
+.ends
+
+.subckt netg7090 g7090_0 g7090_1 gnd
+C1  g7090_0 gnd 2.080806f
+C2  g7090_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7090_0 2.224404
+R2 g7090_1 1 2.224404
+.ends
+
+.subckt netg2222 g2222_1 g2222_0 gnd
+C1  g2222_1 gnd 2.080806f
+C2  g2222_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2222_0 1 2.224404
+R2 1 g2222_1 2.224404
+.ends
+
+.subckt netg5931 g5931_1 g5931_0 gnd
+C1  g5931_1 gnd 2.080806f
+C2  g5931_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5931_0 2.224404
+R2 g5931_1 1 2.224404
+.ends
+
+.subckt netg6973 g6973_0 g6973_1 gnd
+C1  g6973_0 gnd 2.080806f
+C2  g6973_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6973_0 2.224404
+R2 g6973_1 1 2.224404
+.ends
+
+.subckt netg4179 g4179_1 g4179_2 gnd
+C1  g4179_1 gnd 2.080806f
+C2  g4179_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4179_2 1 2.224404
+R2 1 g4179_1 2.224404
+.ends
+
+.subckt netg6933 g6933_0 g6933_1 gnd
+C1  g6933_0 gnd 2.080806f
+C2  g6933_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6933_0 1 2.224404
+R2 g6933_1 1 2.224404
+.ends
+
+.subckt netg1383 g1383_0 g1383_1 gnd
+C1  g1383_0 gnd 2.080806f
+C2  g1383_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1383_0 2.224404
+R2 1 g1383_1 2.224404
+.ends
+
+.subckt netx301 x301_0 x301_1 gnd
+C1  x301_0 gnd 2.080806f
+C2  x301_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x301_0 2.224404
+R2 x301_1 1 2.224404
+.ends
+
+.subckt netg3420 g3420_1 g3420_2 gnd
+C1  g3420_1 gnd 2.080806f
+C2  g3420_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3420_1 1 2.224404
+R2 1 g3420_2 2.224404
+.ends
+
+.subckt netg2771 g2771_1 g2771_0 gnd
+C1  g2771_1 gnd 2.080806f
+C2  g2771_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2771_0 2.224404
+R2 g2771_1 1 2.224404
+.ends
+
+.subckt netg517 g517_1 g517_0 gnd
+C1  g517_1 gnd 2.080806f
+C2  g517_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g517_0 2.224404
+R2 g517_1 1 2.224404
+.ends
+
+.subckt netg2438 g2438_1 g2438_0 g2438_2 gnd
+C1  g2438_1 gnd 2.080806f
+C2  g2438_0 gnd 2.080806f
+C3  g2438_2 gnd 2.080806f
+R1 g2438_0 g2438_2 2.224404
+R2 g2438_2 g2438_1 2.224404
+.ends
+
+.subckt netg2233 g2233_1 g2233_0 gnd
+C1  g2233_1 gnd 2.080806f
+C2  g2233_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2233_0 1 2.224404
+R2 g2233_1 1 2.224404
+.ends
+
+.subckt netg5463 g5463_1 g5463_0 gnd
+C1  g5463_1 gnd 2.080806f
+C2  g5463_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5463_0 1 2.224404
+R2 1 g5463_1 2.224404
+.ends
+
+.subckt netg2925 g2925_1 g2925_0 gnd
+C1  g2925_1 gnd 2.080806f
+C2  g2925_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2925_0 2.224404
+R2 g2925_1 1 2.224404
+.ends
+
+.subckt netg7126 g7126_1 g7126_0 gnd
+C1  g7126_1 gnd 2.080806f
+C2  g7126_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7126_0 2.224404
+R2 g7126_1 1 2.224404
+.ends
+
+.subckt netg6391 g6391_1 g6391_0 gnd
+C1  g6391_1 gnd 2.080806f
+C2  g6391_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6391_0 2.224404
+R2 g6391_1 1 2.224404
+.ends
+
+.subckt netg4356 g4356_0 g4356_1 gnd
+C1  g4356_0 gnd 2.080806f
+C2  g4356_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4356_0 2.224404
+R2 g4356_1 1 2.224404
+.ends
+
+.subckt netg7537 g7537_1 g7537_0 gnd
+C1  g7537_1 gnd 2.080806f
+C2  g7537_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7537_0 1 2.224404
+R2 1 g7537_1 2.224404
+.ends
+
+.subckt netx152 x152_0 x152_1 gnd
+C1  x152_0 gnd 2.080806f
+C2  x152_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x152_0 2.224404
+R2 x152_1 1 2.224404
+.ends
+
+.subckt netg3558 g3558_1 g3558_0 gnd
+C1  g3558_1 gnd 2.080806f
+C2  g3558_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3558_0 2.224404
+R2 g3558_1 1 2.224404
+.ends
+
+.subckt netg4270 g4270_0 g4270_1 gnd
+C1  g4270_0 gnd 2.080806f
+C2  g4270_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4270_0 2.224404
+R2 g4270_1 1 2.224404
+.ends
+
+.subckt netg7011 g7011_1 g7011_0 gnd
+C1  g7011_1 gnd 2.080806f
+C2  g7011_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7011_0 1 2.224404
+R2 1 g7011_1 2.224404
+.ends
+
+.subckt netg862 g862_2 g862_0 g862_1 gnd
+C1  g862_2 gnd 2.080806f
+C2  g862_0 gnd 2.080806f
+C3  g862_1 gnd 2.080806f
+R1 g862_1 g862_0 2.224404
+R2 g862_0 g862_2 2.224404
+.ends
+
+.subckt netg7394 g7394_1 g7394_0 gnd
+C1  g7394_1 gnd 2.080806f
+C2  g7394_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7394_0 1 2.224404
+R2 1 g7394_1 2.224404
+.ends
+
+.subckt netg4440 g4440_1 g4440_0 gnd
+C1  g4440_1 gnd 2.080806f
+C2  g4440_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4440_0 2.224404
+R2 g4440_1 1 2.224404
+.ends
+
+.subckt netg6663 g6663_0 g6663_1 gnd
+C1  g6663_0 gnd 2.080806f
+C2  g6663_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6663_0 1 2.224404
+R2 1 g6663_1 2.224404
+.ends
+
+.subckt netg5346 g5346_0 g5346_1 gnd
+C1  g5346_0 gnd 2.080806f
+C2  g5346_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5346_0 1 2.224404
+R2 1 g5346_1 2.224404
+.ends
+
+.subckt netg7538 g7538_0 g7538_1 gnd
+C1  g7538_0 gnd 2.080806f
+C2  g7538_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7538_0 1 2.224404
+R2 1 g7538_1 2.224404
+.ends
+
+.subckt netg2737 g2737_1 g2737_2 g2737_0 gnd
+C1  g2737_1 gnd 2.080806f
+C2  g2737_2 gnd 2.080806f
+C3  g2737_0 gnd 2.080806f
+R1 g2737_0 g2737_1 2.224404
+R2 g2737_2 g2737_0 2.224404
+.ends
+
+.subckt netg3258 g3258_2 g3258_1 g3258_0 gnd
+C1  g3258_2 gnd 2.080806f
+C2  g3258_1 gnd 2.080806f
+C3  g3258_0 gnd 2.080806f
+R1 g3258_1 g3258_0 2.224404
+R2 g3258_0 g3258_2 2.224404
+.ends
+
+.subckt netg6187 g6187_0 g6187_1 gnd
+C1  g6187_0 gnd 2.080806f
+C2  g6187_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6187_0 1 2.224404
+R2 1 g6187_1 2.224404
+.ends
+
+.subckt netg1550 g1550_0 g1550_1 gnd
+C1  g1550_0 gnd 2.080806f
+C2  g1550_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1550_0 1 2.224404
+R2 1 g1550_1 2.224404
+.ends
+
+.subckt netg2799 g2799_0 g2799_1 gnd
+C1  g2799_0 gnd 2.080806f
+C2  g2799_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2799_0 1 2.224404
+R2 1 g2799_1 2.224404
+.ends
+
+.subckt netg5263 g5263_1 g5263_0 gnd
+C1  g5263_1 gnd 2.080806f
+C2  g5263_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5263_0 1 2.224404
+R2 1 g5263_1 2.224404
+.ends
+
+.subckt netg7324 g7324_2 g7324_1 gnd
+C1  g7324_2 gnd 2.080806f
+C2  g7324_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7324_1 2.224404
+R2 g7324_2 1 2.224404
+.ends
+
+.subckt netg4979 g4979_2 g4979_0 g4979_1 gnd
+C1  g4979_2 gnd 2.080806f
+C2  g4979_0 gnd 2.080806f
+C3  g4979_1 gnd 2.080806f
+R1 g4979_0 g4979_2 2.224404
+R2 g4979_1 g4979_2 2.224404
+.ends
+
+.subckt netg3571 g3571_0 g3571_1 gnd
+C1  g3571_0 gnd 2.080806f
+C2  g3571_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3571_0 1 2.224404
+R2 1 g3571_1 2.224404
+.ends
+
+.subckt netg4101 g4101_1 g4101_0 gnd
+C1  g4101_1 gnd 2.080806f
+C2  g4101_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4101_0 2.224404
+R2 g4101_1 1 2.224404
+.ends
+
+.subckt netg5110 g5110_0 g5110_2 g5110_1 gnd
+C1  g5110_0 gnd 2.080806f
+C2  g5110_2 gnd 2.080806f
+C3  g5110_1 gnd 2.080806f
+R1 g5110_0 g5110_1 2.224404
+R2 g5110_1 g5110_2 2.224404
+.ends
+
+.subckt netg4935 g4935_0 g4935_2 g4935_1 gnd
+C1  g4935_0 gnd 2.080806f
+C2  g4935_2 gnd 2.080806f
+C3  g4935_1 gnd 2.080806f
+R1 g4935_0 g4935_1 2.224404
+R2 g4935_2 g4935_0 2.224404
+.ends
+
+.subckt netg7352 g7352_0 g7352_1 gnd
+C1  g7352_0 gnd 2.080806f
+C2  g7352_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7352_0 1 2.224404
+R2 1 g7352_1 2.224404
+.ends
+
+.subckt netg6332 g6332_1 g6332_0 gnd
+C1  g6332_1 gnd 2.080806f
+C2  g6332_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6332_0 2.224404
+R2 g6332_1 1 2.224404
+.ends
+
+.subckt netg3476 g3476_1 g3476_0 gnd
+C1  g3476_1 gnd 2.080806f
+C2  g3476_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3476_0 1 2.224404
+R2 1 g3476_1 2.224404
+.ends
+
+.subckt netg3066 g3066_1 g3066_0 gnd
+C1  g3066_1 gnd 2.080806f
+C2  g3066_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3066_0 1 2.224404
+R2 1 g3066_1 2.224404
+.ends
+
+.subckt netg3047 g3047_0 g3047_1 gnd
+C1  g3047_0 gnd 2.080806f
+C2  g3047_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3047_0 1 2.224404
+R2 1 g3047_1 2.224404
+.ends
+
+.subckt netg4015 g4015_0 g4015_1 gnd
+C1  g4015_0 gnd 2.080806f
+C2  g4015_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4015_0 1 2.224404
+R2 1 g4015_1 2.224404
+.ends
+
+.subckt netg2772 g2772_1 g2772_0 gnd
+C1  g2772_1 gnd 2.080806f
+C2  g2772_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2772_0 2.224404
+R2 g2772_1 1 2.224404
+.ends
+
+.subckt netg2750 g2750_0 g2750_1 gnd
+C1  g2750_0 gnd 2.080806f
+C2  g2750_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2750_0 2.224404
+R2 g2750_1 1 2.224404
+.ends
+
+.subckt netg5683 g5683_1 g5683_0 gnd
+C1  g5683_1 gnd 2.080806f
+C2  g5683_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5683_0 1 2.224404
+R2 g5683_1 1 2.224404
+.ends
+
+.subckt netg2606 g2606_2 g2606_0 gnd
+C1  g2606_2 gnd 2.080806f
+C2  g2606_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2606_0 2.224404
+R2 g2606_2 1 2.224404
+.ends
+
+.subckt netg4315 g4315_1 g4315_0 gnd
+C1  g4315_1 gnd 2.080806f
+C2  g4315_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4315_0 2.224404
+R2 g4315_1 1 2.224404
+.ends
+
+.subckt netg7386 g7386_1 g7386_0 gnd
+C1  g7386_1 gnd 2.080806f
+C2  g7386_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7386_0 2.224404
+R2 g7386_1 1 2.224404
+.ends
+
+.subckt netg6817 g6817_1 g6817_0 gnd
+C1  g6817_1 gnd 2.080806f
+C2  g6817_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6817_0 1 2.224404
+R2 1 g6817_1 2.224404
+.ends
+
+.subckt netg6293 g6293_0 g6293_1 gnd
+C1  g6293_0 gnd 2.080806f
+C2  g6293_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6293_0 1 2.224404
+R2 g6293_1 1 2.224404
+.ends
+
+.subckt netg967 g967_0 g967_2 g967_1 gnd
+C1  g967_0 gnd 2.080806f
+C2  g967_2 gnd 2.080806f
+C3  g967_1 gnd 2.080806f
+R1 g967_1 g967_0 2.224404
+R2 g967_1 g967_2 2.224404
+.ends
+
+.subckt netg5985 g5985_1 g5985_0 gnd
+C1  g5985_1 gnd 2.080806f
+C2  g5985_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5985_0 2.224404
+R2 g5985_1 1 2.224404
+.ends
+
+.subckt netg1883 g1883_2 g1883_1 gnd
+C1  g1883_2 gnd 2.080806f
+C2  g1883_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1883_1 1 2.224404
+R2 g1883_2 1 2.224404
+.ends
+
+.subckt netg5445 g5445_0 g5445_2 g5445_1 gnd
+C1  g5445_0 gnd 2.080806f
+C2  g5445_2 gnd 2.080806f
+C3  g5445_1 gnd 2.080806f
+R1 g5445_0 g5445_1 2.224404
+R2 g5445_2 g5445_0 2.224404
+.ends
+
+.subckt netg6456 g6456_2 g6456_1 g6456_0 gnd
+C1  g6456_2 gnd 2.080806f
+C2  g6456_1 gnd 2.080806f
+C3  g6456_0 gnd 2.080806f
+R1 g6456_1 g6456_0 2.224404
+R2 g6456_2 g6456_1 2.224404
+.ends
+
+.subckt netg7252 g7252_1 g7252_0 gnd
+C1  g7252_1 gnd 2.080806f
+C2  g7252_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7252_0 2.224404
+R2 1 g7252_1 2.224404
+.ends
+
+.subckt netg2836 g2836_0 g2836_1 gnd
+C1  g2836_0 gnd 2.080806f
+C2  g2836_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2836_0 2.224404
+R2 g2836_1 1 2.224404
+.ends
+
+.subckt netg1226 g1226_0 g1226_1 gnd
+C1  g1226_0 gnd 2.080806f
+C2  g1226_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1226_0 1 2.224404
+R2 1 g1226_1 2.224404
+.ends
+
+.subckt netg4225 g4225_0 g4225_1 gnd
+C1  g4225_0 gnd 2.080806f
+C2  g4225_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4225_0 1 2.224404
+R2 1 g4225_1 2.224404
+.ends
+
+.subckt netg4050 g4050_1 g4050_0 gnd
+C1  g4050_1 gnd 2.080806f
+C2  g4050_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4050_0 1 2.224404
+R2 1 g4050_1 2.224404
+.ends
+
+.subckt netg1357 g1357_0 g1357_1 gnd
+C1  g1357_0 gnd 2.080806f
+C2  g1357_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1357_0 2.224404
+R2 g1357_1 1 2.224404
+.ends
+
+.subckt netg6430 g6430_2 g6430_0 gnd
+C1  g6430_2 gnd 2.080806f
+C2  g6430_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6430_0 2.224404
+R2 g6430_2 1 2.224404
+.ends
+
+.subckt netg5009 g5009_1 g5009_2 gnd
+C1  g5009_1 gnd 2.080806f
+C2  g5009_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5009_1 2.224404
+R2 g5009_2 1 2.224404
+.ends
+
+.subckt netg4289 g4289_0 g4289_1 gnd
+C1  g4289_0 gnd 2.080806f
+C2  g4289_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4289_0 2.224404
+R2 g4289_1 1 2.224404
+.ends
+
+.subckt netg696 g696_0 g696_1 g696_2 gnd
+C1  g696_0 gnd 2.080806f
+C2  g696_1 gnd 2.080806f
+C3  g696_2 gnd 2.080806f
+R1 g696_0 g696_1 2.224404
+R2 g696_0 g696_2 2.224404
+.ends
+
+.subckt netg2422 g2422_1 g2422_0 gnd
+C1  g2422_1 gnd 2.080806f
+C2  g2422_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2422_0 1 2.224404
+R2 1 g2422_1 2.224404
+.ends
+
+.subckt netg5554 g5554_1 g5554_2 g5554_0 gnd
+C1  g5554_1 gnd 2.080806f
+C2  g5554_2 gnd 2.080806f
+C3  g5554_0 gnd 2.080806f
+R1 g5554_0 g5554_2 2.224404
+R2 g5554_2 g5554_1 2.224404
+.ends
+
+.subckt netg7173 g7173_1 g7173_0 gnd
+C1  g7173_1 gnd 2.080806f
+C2  g7173_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7173_0 1 2.224404
+R2 1 g7173_1 2.224404
+.ends
+
+.subckt netg6274 g6274_2 g6274_0 g6274_1 gnd
+C1  g6274_2 gnd 2.080806f
+C2  g6274_0 gnd 2.080806f
+C3  g6274_1 gnd 2.080806f
+R1 g6274_0 g6274_1 2.224404
+R2 g6274_2 g6274_0 2.224404
+.ends
+
+.subckt netg3346 g3346_1 g3346_0 gnd
+C1  g3346_1 gnd 2.080806f
+C2  g3346_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3346_0 1 2.224404
+R2 g3346_1 1 2.224404
+.ends
+
+.subckt netg5314 g5314_0 g5314_1 gnd
+C1  g5314_0 gnd 2.080806f
+C2  g5314_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5314_0 1 2.224404
+R2 g5314_1 1 2.224404
+.ends
+
+.subckt netg5591 g5591_1 g5591_0 gnd
+C1  g5591_1 gnd 2.080806f
+C2  g5591_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5591_0 2.224404
+R2 g5591_1 1 2.224404
+.ends
+
+.subckt netg7302 g7302_0 g7302_1 gnd
+C1  g7302_0 gnd 2.080806f
+C2  g7302_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7302_0 2.224404
+R2 g7302_1 1 2.224404
+.ends
+
+.subckt netg5462 g5462_0 g5462_1 gnd
+C1  g5462_0 gnd 2.080806f
+C2  g5462_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5462_0 2.224404
+R2 g5462_1 1 2.224404
+.ends
+
+.subckt netg4411 g4411_1 g4411_0 gnd
+C1  g4411_1 gnd 2.080806f
+C2  g4411_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4411_0 1 2.224404
+R2 1 g4411_1 2.224404
+.ends
+
+.subckt netg4415 g4415_1 g4415_0 gnd
+C1  g4415_1 gnd 2.080806f
+C2  g4415_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4415_0 2.224404
+R2 g4415_1 1 2.224404
+.ends
+
+.subckt netg7024 g7024_1 g7024_0 gnd
+C1  g7024_1 gnd 2.080806f
+C2  g7024_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7024_0 1 2.224404
+R2 1 g7024_1 2.224404
+.ends
+
+.subckt netg4111 g4111_0 g4111_1 gnd
+C1  g4111_0 gnd 2.080806f
+C2  g4111_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4111_0 1 2.224404
+R2 1 g4111_1 2.224404
+.ends
+
+.subckt netg7171 g7171_0 g7171_1 gnd
+C1  g7171_0 gnd 2.080806f
+C2  g7171_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7171_0 2.224404
+R2 g7171_1 1 2.224404
+.ends
+
+.subckt netg4251 g4251_1 g4251_0 gnd
+C1  g4251_1 gnd 2.080806f
+C2  g4251_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4251_0 1 2.224404
+R2 1 g4251_1 2.224404
+.ends
+
+.subckt netg4988 g4988_2 g4988_0 gnd
+C1  g4988_2 gnd 2.080806f
+C2  g4988_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4988_0 1 2.224404
+R2 1 g4988_2 2.224404
+.ends
+
+.subckt netg883 g883_1 g883_0 g883_2 gnd
+C1  g883_1 gnd 2.080806f
+C2  g883_0 gnd 2.080806f
+C3  g883_2 gnd 2.080806f
+R1 g883_1 g883_0 2.224404
+R2 g883_0 g883_2 2.224404
+.ends
+
+.subckt netg3077 g3077_0 g3077_1 gnd
+C1  g3077_0 gnd 2.080806f
+C2  g3077_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3077_0 1 2.224404
+R2 1 g3077_1 2.224404
+.ends
+
+.subckt netg2582 g2582_0 g2582_1 g2582_2 gnd
+C1  g2582_0 gnd 2.080806f
+C2  g2582_1 gnd 2.080806f
+C3  g2582_2 gnd 2.080806f
+R1 g2582_2 g2582_0 2.224404
+R2 g2582_1 g2582_2 2.224404
+.ends
+
+.subckt netx222 x222_1 x222_0 gnd
+C1  x222_1 gnd 2.080806f
+C2  x222_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x222_0 2.224404
+R2 1 x222_1 2.224404
+.ends
+
+.subckt netg4021 g4021_0 g4021_1 gnd
+C1  g4021_0 gnd 2.080806f
+C2  g4021_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4021_0 2.224404
+R2 g4021_1 1 2.224404
+.ends
+
+.subckt netg2843 g2843_0 g2843_1 gnd
+C1  g2843_0 gnd 2.080806f
+C2  g2843_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2843_0 1 2.224404
+R2 1 g2843_1 2.224404
+.ends
+
+.subckt netg4355 g4355_1 g4355_0 gnd
+C1  g4355_1 gnd 2.080806f
+C2  g4355_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4355_0 2.224404
+R2 g4355_1 1 2.224404
+.ends
+
+.subckt netg4267 g4267_1 g4267_0 gnd
+C1  g4267_1 gnd 2.080806f
+C2  g4267_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4267_0 2.224404
+R2 1 g4267_1 2.224404
+.ends
+
+.subckt netg5299 g5299_1 g5299_0 gnd
+C1  g5299_1 gnd 2.080806f
+C2  g5299_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5299_0 1 2.224404
+R2 1 g5299_1 2.224404
+.ends
+
+.subckt netg3398 g3398_0 g3398_1 g3398_2 gnd
+C1  g3398_0 gnd 2.080806f
+C2  g3398_1 gnd 2.080806f
+C3  g3398_2 gnd 2.080806f
+R1 g3398_0 g3398_2 2.224404
+R2 g3398_2 g3398_1 2.224404
+.ends
+
+.subckt netg6954 g6954_2 g6954_0 gnd
+C1  g6954_2 gnd 2.080806f
+C2  g6954_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6954_0 2.224404
+R2 g6954_2 1 2.224404
+.ends
+
+.subckt netg2171 g2171_2 g2171_3 g2171_0 gnd
+C1  g2171_2 gnd 2.080806f
+C2  g2171_3 gnd 2.080806f
+C3  g2171_0 gnd 2.080806f
+R1 g2171_2 g2171_0 2.224404
+R2 g2171_3 g2171_2 2.224404
+.ends
+
+.subckt netg6402 g6402_1 g6402_0 gnd
+C1  g6402_1 gnd 2.080806f
+C2  g6402_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6402_0 2.224404
+R2 g6402_1 1 2.224404
+.ends
+
+.subckt netg1765 g1765_1 g1765_0 gnd
+C1  g1765_1 gnd 2.080806f
+C2  g1765_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1765_0 2.224404
+R2 g1765_1 1 2.224404
+.ends
+
+.subckt netg2444 g2444_2 g2444_1 g2444_0 gnd
+C1  g2444_2 gnd 2.080806f
+C2  g2444_1 gnd 2.080806f
+C3  g2444_0 gnd 2.080806f
+R1 g2444_0 g2444_1 2.224404
+R2 g2444_0 g2444_2 2.224404
+.ends
+
+.subckt netg6608 g6608_1 g6608_0 gnd
+C1  g6608_1 gnd 2.080806f
+C2  g6608_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6608_0 1 2.224404
+R2 1 g6608_1 2.224404
+.ends
+
+.subckt netg3543 g3543_1 g3543_0 gnd
+C1  g3543_1 gnd 2.080806f
+C2  g3543_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3543_0 2.224404
+R2 g3543_1 1 2.224404
+.ends
+
+.subckt netg2368 g2368_1 g2368_2 g2368_0 gnd
+C1  g2368_1 gnd 2.080806f
+C2  g2368_2 gnd 2.080806f
+C3  g2368_0 gnd 2.080806f
+R1 g2368_2 g2368_0 2.224404
+R2 g2368_1 g2368_2 2.224404
+.ends
+
+.subckt netg2588 g2588_2 g2588_0 gnd
+C1  g2588_2 gnd 2.080806f
+C2  g2588_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2588_0 1 2.224404
+R2 1 g2588_2 2.224404
+.ends
+
+.subckt netg3475 g3475_1 g3475_0 gnd
+C1  g3475_1 gnd 2.080806f
+C2  g3475_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3475_0 2.224404
+R2 g3475_1 1 2.224404
+.ends
+
+.subckt netg6041 g6041_0 g6041_1 gnd
+C1  g6041_0 gnd 2.080806f
+C2  g6041_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6041_0 1 2.224404
+R2 g6041_1 1 2.224404
+.ends
+
+.subckt netg2920 g2920_0 g2920_1 gnd
+C1  g2920_0 gnd 2.080806f
+C2  g2920_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2920_0 2.224404
+R2 g2920_1 1 2.224404
+.ends
+
+.subckt netg6561 g6561_1 g6561_0 gnd
+C1  g6561_1 gnd 2.080806f
+C2  g6561_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6561_0 2.224404
+R2 g6561_1 1 2.224404
+.ends
+
+.subckt netg1015 g1015_0 g1015_2 g1015_1 gnd
+C1  g1015_0 gnd 2.080806f
+C2  g1015_2 gnd 2.080806f
+C3  g1015_1 gnd 2.080806f
+R1 g1015_0 g1015_2 2.224404
+R2 g1015_2 g1015_1 2.224404
+.ends
+
+.subckt netg5520 g5520_0 g5520_1 gnd
+C1  g5520_0 gnd 2.080806f
+C2  g5520_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5520_0 1 2.224404
+R2 1 g5520_1 2.224404
+.ends
+
+.subckt netx211 x211_0 x211_1 gnd
+C1  x211_0 gnd 2.080806f
+C2  x211_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 x211_0 1 2.224404
+R2 1 x211_1 2.224404
+.ends
+
+.subckt netg2776 g2776_1 g2776_0 gnd
+C1  g2776_1 gnd 2.080806f
+C2  g2776_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2776_0 1 2.224404
+R2 1 g2776_1 2.224404
+.ends
+
+.subckt netg6683 g6683_0 g6683_1 gnd
+C1  g6683_0 gnd 2.080806f
+C2  g6683_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6683_0 1 2.224404
+R2 1 g6683_1 2.224404
+.ends
+
+.subckt netg1583 g1583_0 g1583_1 gnd
+C1  g1583_0 gnd 2.080806f
+C2  g1583_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1583_0 2.224404
+R2 g1583_1 1 2.224404
+.ends
+
+.subckt netg1219 g1219_0 g1219_1 gnd
+C1  g1219_0 gnd 2.080806f
+C2  g1219_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1219_0 2.224404
+R2 g1219_1 1 2.224404
+.ends
+
+.subckt netg6034 g6034_0 g6034_1 gnd
+C1  g6034_0 gnd 2.080806f
+C2  g6034_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6034_0 1 2.224404
+R2 1 g6034_1 2.224404
+.ends
+
+.subckt netg559 g559_1 g559_0 gnd
+C1  g559_1 gnd 2.080806f
+C2  g559_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g559_0 2.224404
+R2 1 g559_1 2.224404
+.ends
+
+.subckt netg6417 g6417_1 g6417_0 gnd
+C1  g6417_1 gnd 2.080806f
+C2  g6417_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6417_0 2.224404
+R2 g6417_1 1 2.224404
+.ends
+
+.subckt netg6412 g6412_1 g6412_0 gnd
+C1  g6412_1 gnd 2.080806f
+C2  g6412_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6412_0 1 2.224404
+R2 1 g6412_1 2.224404
+.ends
+
+.subckt netg4222 g4222_1 g4222_0 gnd
+C1  g4222_1 gnd 2.080806f
+C2  g4222_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4222_0 2.224404
+R2 g4222_1 1 2.224404
+.ends
+
+.subckt netg3377 g3377_2 g3377_1 gnd
+C1  g3377_2 gnd 2.080806f
+C2  g3377_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3377_1 2.224404
+R2 g3377_2 1 2.224404
+.ends
+
+.subckt netg6698 g6698_1 g6698_0 gnd
+C1  g6698_1 gnd 2.080806f
+C2  g6698_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6698_0 2.224404
+R2 1 g6698_1 2.224404
+.ends
+
+.subckt netg4054 g4054_1 g4054_0 gnd
+C1  g4054_1 gnd 2.080806f
+C2  g4054_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4054_0 2.224404
+R2 1 g4054_1 2.224404
+.ends
+
+.subckt netg4262 g4262_1 g4262_0 gnd
+C1  g4262_1 gnd 2.080806f
+C2  g4262_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4262_0 1 2.224404
+R2 1 g4262_1 2.224404
+.ends
+
+.subckt netg5274 g5274_1 g5274_0 gnd
+C1  g5274_1 gnd 2.080806f
+C2  g5274_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5274_0 1 2.224404
+R2 1 g5274_1 2.224404
+.ends
+
+.subckt netg5829 g5829_0 g5829_1 gnd
+C1  g5829_0 gnd 2.080806f
+C2  g5829_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5829_0 2.224404
+R2 g5829_1 1 2.224404
+.ends
+
+.subckt netg5454 g5454_1 g5454_0 g5454_2 gnd
+C1  g5454_1 gnd 2.080806f
+C2  g5454_0 gnd 2.080806f
+C3  g5454_2 gnd 2.080806f
+R1 g5454_0 g5454_1 2.224404
+R2 g5454_2 g5454_0 2.224404
+.ends
+
+.subckt netg1887 g1887_1 g1887_0 gnd
+C1  g1887_1 gnd 2.080806f
+C2  g1887_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1887_0 1 2.224404
+R2 1 g1887_1 2.224404
+.ends
+
+.subckt netg1024 g1024_2 g1024_1 g1024_0 gnd
+C1  g1024_2 gnd 2.080806f
+C2  g1024_1 gnd 2.080806f
+C3  g1024_0 gnd 2.080806f
+R1 g1024_1 g1024_0 2.224404
+R2 g1024_2 g1024_1 2.224404
+.ends
+
+.subckt netg6654 g6654_0 g6654_1 gnd
+C1  g6654_0 gnd 2.080806f
+C2  g6654_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6654_0 2.224404
+R2 g6654_1 1 2.224404
+.ends
+
+.subckt netg4285 g4285_1 g4285_0 gnd
+C1  g4285_1 gnd 2.080806f
+C2  g4285_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4285_0 2.224404
+R2 g4285_1 1 2.224404
+.ends
+
+.subckt netg7086 g7086_1 g7086_0 gnd
+C1  g7086_1 gnd 2.080806f
+C2  g7086_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7086_0 1 2.224404
+R2 1 g7086_1 2.224404
+.ends
+
+.subckt netg7372 g7372_0 g7372_1 gnd
+C1  g7372_0 gnd 2.080806f
+C2  g7372_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7372_0 2.224404
+R2 g7372_1 1 2.224404
+.ends
+
+.subckt netg1076 g1076_2 g1076_1 gnd
+C1  g1076_2 gnd 2.080806f
+C2  g1076_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1076_2 1 2.224404
+R2 g1076_1 1 2.224404
+.ends
+
+.subckt netg6530 g6530_1 g6530_0 gnd
+C1  g6530_1 gnd 2.080806f
+C2  g6530_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6530_0 1 2.224404
+R2 g6530_1 1 2.224404
+.ends
+
+.subckt netg2392 g2392_2 g2392_1 gnd
+C1  g2392_2 gnd 2.080806f
+C2  g2392_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2392_1 1 2.224404
+R2 1 g2392_2 2.224404
+.ends
+
+.subckt netg7424 g7424_1 g7424_0 gnd
+C1  g7424_1 gnd 2.080806f
+C2  g7424_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7424_0 1 2.224404
+R2 1 g7424_1 2.224404
+.ends
+
+.subckt netg6924 g6924_1 g6924_0 gnd
+C1  g6924_1 gnd 2.080806f
+C2  g6924_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6924_0 2.224404
+R2 g6924_1 1 2.224404
+.ends
+
+.subckt netg5121 g5121_0 g5121_1 gnd
+C1  g5121_0 gnd 2.080806f
+C2  g5121_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5121_0 1 2.224404
+R2 g5121_1 1 2.224404
+.ends
+
+.subckt netg5027 g5027_1 g5027_2 g5027_0 gnd
+C1  g5027_1 gnd 2.080806f
+C2  g5027_2 gnd 2.080806f
+C3  g5027_0 gnd 2.080806f
+R1 g5027_2 g5027_0 2.224404
+R2 g5027_1 g5027_2 2.224404
+.ends
+
+.subckt netg5995 g5995_1 g5995_0 gnd
+C1  g5995_1 gnd 2.080806f
+C2  g5995_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5995_0 2.224404
+R2 g5995_1 1 2.224404
+.ends
+
+.subckt netg5033 g5033_2 g5033_0 g5033_1 gnd
+C1  g5033_2 gnd 2.080806f
+C2  g5033_0 gnd 2.080806f
+C3  g5033_1 gnd 2.080806f
+R1 g5033_1 g5033_0 2.224404
+R2 g5033_2 g5033_1 2.224404
+.ends
+
+.subckt netg7180 g7180_2 g7180_1 g7180_0 gnd
+C1  g7180_2 gnd 2.080806f
+C2  g7180_1 gnd 2.080806f
+C3  g7180_0 gnd 2.080806f
+R1 g7180_2 g7180_0 2.224404
+R2 g7180_2 g7180_1 2.224404
+.ends
+
+.subckt netg1315 g1315_0 g1315_1 gnd
+C1  g1315_0 gnd 2.080806f
+C2  g1315_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1315_0 1 2.224404
+R2 g1315_1 1 2.224404
+.ends
+
+.subckt netg6174 g6174_0 g6174_1 gnd
+C1  g6174_0 gnd 2.080806f
+C2  g6174_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6174_0 2.224404
+R2 g6174_1 1 2.224404
+.ends
+
+.subckt netg2763 g2763_1 g2763_0 gnd
+C1  g2763_1 gnd 2.080806f
+C2  g2763_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2763_0 2.224404
+R2 g2763_1 1 2.224404
+.ends
+
+.subckt netg5846 g5846_1 g5846_0 gnd
+C1  g5846_1 gnd 2.080806f
+C2  g5846_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5846_0 2.224404
+R2 g5846_1 1 2.224404
+.ends
+
+.subckt netg5700 g5700_1 g5700_0 g5700_2 gnd
+C1  g5700_1 gnd 2.080806f
+C2  g5700_0 gnd 2.080806f
+C3  g5700_2 gnd 2.080806f
+R1 g5700_2 g5700_0 2.224404
+R2 g5700_1 g5700_2 2.224404
+.ends
+
+.subckt netg3459 g3459_2 g3459_0 gnd
+C1  g3459_2 gnd 2.080806f
+C2  g3459_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3459_0 2.224404
+R2 g3459_2 1 2.224404
+.ends
+
+.subckt netg3465 g3465_1 g3465_0 gnd
+C1  g3465_1 gnd 2.080806f
+C2  g3465_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3465_0 2.224404
+R2 g3465_1 1 2.224404
+.ends
+
+.subckt netg7348 g7348_0 g7348_1 gnd
+C1  g7348_0 gnd 2.080806f
+C2  g7348_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7348_0 1 2.224404
+R2 g7348_1 1 2.224404
+.ends
+
+.subckt netg5864 g5864_1 g5864_0 gnd
+C1  g5864_1 gnd 2.080806f
+C2  g5864_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5864_0 1 2.224404
+R2 1 g5864_1 2.224404
+.ends
+
+.subckt netg3891 g3891_0 g3891_1 gnd
+C1  g3891_0 gnd 2.080806f
+C2  g3891_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3891_0 1 2.224404
+R2 1 g3891_1 2.224404
+.ends
+
+.subckt netg7339 g7339_1 g7339_0 gnd
+C1  g7339_1 gnd 2.080806f
+C2  g7339_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7339_0 1 2.224404
+R2 1 g7339_1 2.224404
+.ends
+
+.subckt netg5981 g5981_1 g5981_0 gnd
+C1  g5981_1 gnd 2.080806f
+C2  g5981_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5981_0 1 2.224404
+R2 1 g5981_1 2.224404
+.ends
+
+.subckt netg7115 g7115_0 g7115_1 gnd
+C1  g7115_0 gnd 2.080806f
+C2  g7115_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7115_0 1 2.224404
+R2 g7115_1 1 2.224404
+.ends
+
+.subckt netg6670 g6670_1 g6670_0 gnd
+C1  g6670_1 gnd 2.080806f
+C2  g6670_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6670_0 2.224404
+R2 g6670_1 1 2.224404
+.ends
+
+.subckt netg2507 g2507_1 g2507_2 g2507_0 gnd
+C1  g2507_1 gnd 2.080806f
+C2  g2507_2 gnd 2.080806f
+C3  g2507_0 gnd 2.080806f
+R1 g2507_0 g2507_1 2.224404
+R2 g2507_1 g2507_2 2.224404
+.ends
+
+.subckt netg6070 g6070_0 g6070_1 gnd
+C1  g6070_0 gnd 2.080806f
+C2  g6070_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6070_0 2.224404
+R2 g6070_1 1 2.224404
+.ends
+
+.subckt netg7256 g7256_1 g7256_0 gnd
+C1  g7256_1 gnd 2.080806f
+C2  g7256_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7256_0 2.224404
+R2 1 g7256_1 2.224404
+.ends
+
+.subckt netg4041 g4041_1 g4041_0 gnd
+C1  g4041_1 gnd 2.080806f
+C2  g4041_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4041_0 1 2.224404
+R2 1 g4041_1 2.224404
+.ends
+
+.subckt netx522 x522_0 x522_1 gnd
+C1  x522_0 gnd 2.080806f
+C2  x522_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x522_0 2.224404
+R2 x522_1 1 2.224404
+.ends
+
+.subckt netg99 g99_1 g99_0 gnd
+C1  g99_1 gnd 2.080806f
+C2  g99_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g99_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g99_1 2.224404
+.ends
+
+.subckt netg5086 g5086_0 g5086_2 g5086_1 gnd
+C1  g5086_0 gnd 2.080806f
+C2  g5086_2 gnd 2.080806f
+C3  g5086_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5086_0 1 2.224404
+R2 g5086_1 1 2.224404
+R3 g5086_1 g5086_2 2.224404
+.ends
+
+.subckt netg4343 g4343_0 g4343_1 gnd
+C1  g4343_0 gnd 2.080806f
+C2  g4343_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4343_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g4343_1 2 2.224404
+.ends
+
+.subckt netg1587 g1587_0 g1587_1 gnd
+C1  g1587_0 gnd 2.080806f
+C2  g1587_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1587_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g1587_1 2.224404
+.ends
+
+.subckt netg3472 g3472_1 g3472_0 gnd
+C1  g3472_1 gnd 2.080806f
+C2  g3472_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3472_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g3472_1 2.224404
+.ends
+
+.subckt netg7014 g7014_1 g7014_0 gnd
+C1  g7014_1 gnd 2.080806f
+C2  g7014_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7014_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g7014_1 2.224404
+.ends
+
+.subckt netg3186 g3186_2 g3186_1 g3186_0 gnd
+C1  g3186_2 gnd 2.080806f
+C2  g3186_1 gnd 2.080806f
+C3  g3186_0 gnd 2.080806f
+R1 g3186_0 g3186_1 2.224404
+C4 1 gnd 2.080806f
+R2 g3186_1 1 2.224404
+R3 1 g3186_2 2.224404
+.ends
+
+.subckt netg1048 g1048_0 g1048_2 g1048_1 gnd
+C1  g1048_0 gnd 2.080806f
+C2  g1048_2 gnd 2.080806f
+C3  g1048_1 gnd 2.080806f
+R1 g1048_1 g1048_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g1048_1 2.224404
+R3 g1048_2 1 2.224404
+.ends
+
+.subckt netg6370 g6370_1 g6370_0 gnd
+C1  g6370_1 gnd 2.080806f
+C2  g6370_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6370_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g6370_1 2 2.224404
+.ends
+
+.subckt netg5214 g5214_0 g5214_1 g5214_2 gnd
+C1  g5214_0 gnd 2.080806f
+C2  g5214_1 gnd 2.080806f
+C3  g5214_2 gnd 2.080806f
+R1 g5214_2 g5214_0 2.224404
+C4 1 gnd 2.080806f
+R2 g5214_2 1 2.224404
+R3 g5214_1 1 2.224404
+.ends
+
+.subckt netg6722 g6722_0 g6722_2 gnd
+C1  g6722_0 gnd 2.080806f
+C2  g6722_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6722_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g6722_2 2.224404
+.ends
+
+.subckt netg5492 g5492_1 g5492_0 gnd
+C1  g5492_1 gnd 2.080806f
+C2  g5492_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5492_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 2 g5492_1 2.224404
+.ends
+
+.subckt netx232 x232_0 x232_1 gnd
+C1  x232_0 gnd 2.080806f
+C2  x232_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 x232_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 x232_1 2.224404
+.ends
+
+.subckt netg6687 g6687_2 g6687_1 g6687_3 g6687_0 gnd
+C1  g6687_2 gnd 2.080806f
+C2  g6687_1 gnd 2.080806f
+C3  g6687_3 gnd 2.080806f
+C4  g6687_0 gnd 2.080806f
+R1 g6687_1 g6687_0 2.224404
+R2 g6687_2 g6687_0 2.224404
+R3 g6687_2 g6687_3 2.224404
+.ends
+
+.subckt netg2880 g2880_0 g2880_1 gnd
+C1  g2880_0 gnd 2.080806f
+C2  g2880_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2880_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g2880_1 2 2.224404
+.ends
+
+.subckt netg2594 g2594_2 g2594_0 g2594_1 gnd
+C1  g2594_2 gnd 2.080806f
+C2  g2594_0 gnd 2.080806f
+C3  g2594_1 gnd 2.080806f
+R1 g2594_1 g2594_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g2594_1 2.224404
+R3 1 g2594_2 2.224404
+.ends
+
+.subckt netg6917 g6917_0 g6917_1 gnd
+C1  g6917_0 gnd 2.080806f
+C2  g6917_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6917_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g6917_1 2 2.224404
+.ends
+
+.subckt netx302 x302_1 x302_0 gnd
+C1  x302_1 gnd 2.080806f
+C2  x302_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x302_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 x302_1 2 2.224404
+.ends
+
+.subckt netg6044 g6044_1 g6044_0 gnd
+C1  g6044_1 gnd 2.080806f
+C2  g6044_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6044_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g6044_1 2 2.224404
+.ends
+
+.subckt netg1938 g1938_0 g1938_1 gnd
+C1  g1938_0 gnd 2.080806f
+C2  g1938_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1938_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g1938_1 2 2.224404
+.ends
+
+.subckt netg2624 g2624_1 g2624_2 g2624_0 gnd
+C1  g2624_1 gnd 2.080806f
+C2  g2624_2 gnd 2.080806f
+C3  g2624_0 gnd 2.080806f
+R1 g2624_0 g2624_2 2.224404
+C4 1 gnd 2.080806f
+R2 1 g2624_0 2.224404
+R3 g2624_1 1 2.224404
+.ends
+
+.subckt netg1877 g1877_0 g1877_2 g1877_1 gnd
+C1  g1877_0 gnd 2.080806f
+C2  g1877_2 gnd 2.080806f
+C3  g1877_1 gnd 2.080806f
+R1 g1877_0 g1877_2 2.224404
+C4 1 gnd 2.080806f
+R2 1 g1877_0 2.224404
+R3 g1877_1 1 2.224404
+.ends
+
+.subckt netg5598 g5598_0 g5598_1 gnd
+C1  g5598_0 gnd 2.080806f
+C2  g5598_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5598_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g5598_1 2 2.224404
+.ends
+
+.subckt netg6198 g6198_1 g6198_0 gnd
+C1  g6198_1 gnd 2.080806f
+C2  g6198_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6198_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 2 g6198_1 2.224404
+.ends
+
+.subckt netg2231 g2231_1 g2231_0 gnd
+C1  g2231_1 gnd 2.080806f
+C2  g2231_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2231_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g2231_1 2.224404
+.ends
+
+.subckt netg2665 g2665_0 g2665_1 g2665_2 gnd
+C1  g2665_0 gnd 2.080806f
+C2  g2665_1 gnd 2.080806f
+C3  g2665_2 gnd 2.080806f
+R1 g2665_0 g2665_1 2.224404
+C4 1 gnd 2.080806f
+R2 1 g2665_0 2.224404
+R3 g2665_2 1 2.224404
+.ends
+
+.subckt netg6975 g6975_1 g6975_0 gnd
+C1  g6975_1 gnd 2.080806f
+C2  g6975_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6975_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g6975_1 2 2.224404
+.ends
+
+.subckt netg544 g544_1 g544_0 gnd
+C1  g544_1 gnd 2.080806f
+C2  g544_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g544_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g544_1 2.224404
+.ends
+
+.subckt netg4893 g4893_1 g4893_0 g4893_2 gnd
+C1  g4893_1 gnd 2.080806f
+C2  g4893_0 gnd 2.080806f
+C3  g4893_2 gnd 2.080806f
+R1 g4893_1 g4893_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g4893_1 2.224404
+R3 g4893_2 1 2.224404
+.ends
+
+.subckt netg3114 g3114_0 g3114_2 g3114_1 gnd
+C1  g3114_0 gnd 2.080806f
+C2  g3114_2 gnd 2.080806f
+C3  g3114_1 gnd 2.080806f
+R1 g3114_0 g3114_1 2.224404
+C4 1 gnd 2.080806f
+R2 1 g3114_0 2.224404
+R3 g3114_2 1 2.224404
+.ends
+
+.subckt netg6927 g6927_0 g6927_1 gnd
+C1  g6927_0 gnd 2.080806f
+C2  g6927_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6927_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g6927_1 2.224404
+.ends
+
+.subckt netg3165 g3165_1 g3165_2 g3165_0 gnd
+C1  g3165_1 gnd 2.080806f
+C2  g3165_2 gnd 2.080806f
+C3  g3165_0 gnd 2.080806f
+R1 g3165_0 g3165_1 2.224404
+C4 1 gnd 2.080806f
+R2 g3165_1 1 2.224404
+R3 1 g3165_2 2.224404
+.ends
+
+.subckt netg3902 g3902_1 g3902_0 gnd
+C1  g3902_1 gnd 2.080806f
+C2  g3902_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3902_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g3902_1 2 2.224404
+.ends
+
+.subckt netg5153 g5153_2 g5153_1 g5153_0 gnd
+C1  g5153_2 gnd 2.080806f
+C2  g5153_1 gnd 2.080806f
+C3  g5153_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5153_0 2.224404
+R2 1 g5153_1 2.224404
+C5 2 gnd 2.080806f
+R3 g5153_0 2 2.224404
+R4 2 g5153_2 2.224404
+.ends
+
+.subckt netg5578 g5578_0 g5578_1 g5578_2 gnd
+C1  g5578_0 gnd 2.080806f
+C2  g5578_1 gnd 2.080806f
+C3  g5578_2 gnd 2.080806f
+R1 g5578_2 g5578_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g5578_2 2.224404
+R3 g5578_1 1 2.224404
+.ends
+
+.subckt netg4657 g4657_0 g4657_1 g4657_2 gnd
+C1  g4657_0 gnd 2.080806f
+C2  g4657_1 gnd 2.080806f
+C3  g4657_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g4657_0 1 2.224404
+R2 1 g4657_1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g4657_0 2.224404
+R4 2 g4657_2 2.224404
+.ends
+
+.subckt netg6288 g6288_0 g6288_2 g6288_1 gnd
+C1  g6288_0 gnd 2.080806f
+C2  g6288_2 gnd 2.080806f
+C3  g6288_1 gnd 2.080806f
+R1 g6288_2 g6288_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g6288_2 2.224404
+R3 g6288_1 1 2.224404
+.ends
+
+.subckt netg82 g82_0 g82_1 gnd
+C1  g82_0 gnd 2.080806f
+C2  g82_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g82_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g82_1 2 2.224404
+.ends
+
+.subckt netg1907 g1907_0 g1907_1 gnd
+C1  g1907_0 gnd 2.080806f
+C2  g1907_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1907_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g1907_1 2.224404
+.ends
+
+.subckt netg4953 g4953_0 g4953_2 gnd
+C1  g4953_0 gnd 2.080806f
+C2  g4953_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4953_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g4953_2 2 2.224404
+.ends
+
+.subckt netg6653 g6653_1 g6653_0 gnd
+C1  g6653_1 gnd 2.080806f
+C2  g6653_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6653_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g6653_1 2 2.224404
+.ends
+
+.subckt netg5047 g5047_0 g5047_2 gnd
+C1  g5047_0 gnd 2.080806f
+C2  g5047_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5047_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g5047_2 2 2.224404
+.ends
+
+.subckt netg6164 g6164_1 g6164_0 gnd
+C1  g6164_1 gnd 2.080806f
+C2  g6164_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6164_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g6164_1 2 2.224404
+.ends
+
+.subckt netg5422 g5422_1 g5422_0 gnd
+C1  g5422_1 gnd 2.080806f
+C2  g5422_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5422_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g5422_1 2 2.224404
+.ends
+
+.subckt netg1936 g1936_1 g1936_0 gnd
+C1  g1936_1 gnd 2.080806f
+C2  g1936_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1936_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g1936_1 2 2.224404
+.ends
+
+.subckt netg2498 g2498_0 g2498_1 g2498_2 gnd
+C1  g2498_0 gnd 2.080806f
+C2  g2498_1 gnd 2.080806f
+C3  g2498_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g2498_0 2.224404
+R2 g2498_1 1 2.224404
+R3 g2498_2 g2498_1 2.224404
+.ends
+
+.subckt netg2722 g2722_2 g2722_0 g2722_1 gnd
+C1  g2722_2 gnd 2.080806f
+C2  g2722_0 gnd 2.080806f
+C3  g2722_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g2722_0 2.224404
+R2 g2722_1 1 2.224404
+R3 g2722_1 g2722_2 2.224404
+.ends
+
+.subckt netg3276 g3276_0 g3276_2 g3276_1 gnd
+C1  g3276_0 gnd 2.080806f
+C2  g3276_2 gnd 2.080806f
+C3  g3276_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g3276_0 2.224404
+R2 1 g3276_2 2.224404
+R3 g3276_1 g3276_2 2.224404
+.ends
+
+.subckt netg958 g958_1 g958_2 gnd
+C1  g958_1 gnd 2.080806f
+C2  g958_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g958_2 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g958_1 2.224404
+.ends
+
+.subckt netg5539 g5539_1 g5539_0 gnd
+C1  g5539_1 gnd 2.080806f
+C2  g5539_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5539_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g5539_1 2 2.224404
+.ends
+
+.subckt netg4066 g4066_1 g4066_0 gnd
+C1  g4066_1 gnd 2.080806f
+C2  g4066_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4066_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g4066_1 2 2.224404
+.ends
+
+.subckt netg2769 g2769_0 g2769_1 gnd
+C1  g2769_0 gnd 2.080806f
+C2  g2769_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2769_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g2769_1 2 2.224404
+.ends
+
+.subckt netg6049 g6049_0 g6049_1 gnd
+C1  g6049_0 gnd 2.080806f
+C2  g6049_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6049_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g6049_1 2 2.224404
+.ends
+
+.subckt netg3380 g3380_1 g3380_0 g3380_2 gnd
+C1  g3380_1 gnd 2.080806f
+C2  g3380_0 gnd 2.080806f
+C3  g3380_2 gnd 2.080806f
+R1 g3380_2 g3380_0 2.224404
+C4 1 gnd 2.080806f
+R2 g3380_2 1 2.224404
+R3 g3380_1 1 2.224404
+.ends
+
+.subckt netg6007 g6007_0 g6007_1 gnd
+C1  g6007_0 gnd 2.080806f
+C2  g6007_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6007_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g6007_1 2 2.224404
+.ends
+
+.subckt netg4905 g4905_2 g4905_1 g4905_0 gnd
+C1  g4905_2 gnd 2.080806f
+C2  g4905_1 gnd 2.080806f
+C3  g4905_0 gnd 2.080806f
+R1 g4905_2 g4905_0 2.224404
+C4 1 gnd 2.080806f
+R2 g4905_2 1 2.224404
+R3 1 g4905_1 2.224404
+.ends
+
+.subckt netg2695 g2695_1 g2695_0 g2695_2 gnd
+C1  g2695_1 gnd 2.080806f
+C2  g2695_0 gnd 2.080806f
+C3  g2695_2 gnd 2.080806f
+R1 g2695_0 g2695_2 2.224404
+C4 1 gnd 2.080806f
+R2 g2695_2 1 2.224404
+R3 1 g2695_1 2.224404
+.ends
+
+.subckt netg6552 g6552_0 g6552_1 gnd
+C1  g6552_0 gnd 2.080806f
+C2  g6552_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6552_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g6552_1 2 2.224404
+.ends
+
+.subckt netg3368 g3368_2 g3368_1 g3368_0 gnd
+C1  g3368_2 gnd 2.080806f
+C2  g3368_1 gnd 2.080806f
+C3  g3368_0 gnd 2.080806f
+R1 g3368_2 g3368_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g3368_2 2.224404
+R3 1 g3368_1 2.224404
+.ends
+
+.subckt netg5622 g5622_0 g5622_2 gnd
+C1  g5622_0 gnd 2.080806f
+C2  g5622_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5622_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g5622_2 2.224404
+.ends
+
+.subckt netg3318 g3318_0 g3318_2 g3318_1 gnd
+C1  g3318_0 gnd 2.080806f
+C2  g3318_2 gnd 2.080806f
+C3  g3318_1 gnd 2.080806f
+R1 g3318_1 g3318_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g3318_1 2.224404
+R3 g3318_2 1 2.224404
+.ends
+
+.subckt netg2401 g2401_1 g2401_0 g2401_2 gnd
+C1  g2401_1 gnd 2.080806f
+C2  g2401_0 gnd 2.080806f
+C3  g2401_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g2401_0 2.224404
+R2 g2401_1 1 2.224404
+R3 g2401_2 g2401_1 2.224404
+.ends
+
+.subckt netg1439 g1439_1 g1439_0 gnd
+C1  g1439_1 gnd 2.080806f
+C2  g1439_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1439_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g1439_1 2 2.224404
+.ends
+
+.subckt netg2232 g2232_1 g2232_0 gnd
+C1  g2232_1 gnd 2.080806f
+C2  g2232_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2232_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g2232_1 2.224404
+.ends
+
+.subckt netg6466 g6466_0 g6466_1 gnd
+C1  g6466_0 gnd 2.080806f
+C2  g6466_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6466_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g6466_1 2 2.224404
+.ends
+
+.subckt netg5929 g5929_0 g5929_1 gnd
+C1  g5929_0 gnd 2.080806f
+C2  g5929_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5929_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g5929_1 2 2.224404
+.ends
+
+.subckt netg4319 g4319_1 g4319_0 gnd
+C1  g4319_1 gnd 2.080806f
+C2  g4319_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4319_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g4319_1 2 2.224404
+.ends
+
+.subckt netg3019 g3019_1 g3019_0 gnd
+C1  g3019_1 gnd 2.080806f
+C2  g3019_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3019_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 2 g3019_1 2.224404
+.ends
+
+.subckt netg7138 g7138_0 g7138_1 gnd
+C1  g7138_0 gnd 2.080806f
+C2  g7138_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7138_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g7138_1 2.224404
+.ends
+
+.subckt netg6262 g6262_0 g6262_1 gnd
+C1  g6262_0 gnd 2.080806f
+C2  g6262_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6262_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g6262_1 2 2.224404
+.ends
+
+.subckt netg3545 g3545_0 g3545_1 gnd
+C1  g3545_0 gnd 2.080806f
+C2  g3545_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3545_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g3545_1 2 2.224404
+.ends
+
+.subckt netg6540 g6540_0 g6540_1 gnd
+C1  g6540_0 gnd 2.080806f
+C2  g6540_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6540_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g6540_1 2.224404
+.ends
+
+.subckt netg6964 g6964_1 g6964_0 g6964_2 gnd
+C1  g6964_1 gnd 2.080806f
+C2  g6964_0 gnd 2.080806f
+C3  g6964_2 gnd 2.080806f
+R1 g6964_0 g6964_2 2.224404
+C4 1 gnd 2.080806f
+R2 1 g6964_0 2.224404
+R3 g6964_1 1 2.224404
+.ends
+
+.subckt netg1454 g1454_0 g1454_1 gnd
+C1  g1454_0 gnd 2.080806f
+C2  g1454_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1454_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g1454_1 2.224404
+.ends
+
+.subckt netg2468 g2468_1 g2468_2 g2468_0 gnd
+C1  g2468_1 gnd 2.080806f
+C2  g2468_2 gnd 2.080806f
+C3  g2468_0 gnd 2.080806f
+R1 g2468_2 g2468_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g2468_0 2.224404
+R3 g2468_1 1 2.224404
+.ends
+
+.subckt netg5915 g5915_0 g5915_1 gnd
+C1  g5915_0 gnd 2.080806f
+C2  g5915_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5915_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g5915_1 2 2.224404
+.ends
+
+.subckt netg5668 g5668_2 g5668_0 g5668_1 gnd
+C1  g5668_2 gnd 2.080806f
+C2  g5668_0 gnd 2.080806f
+C3  g5668_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5668_0 1 2.224404
+R2 1 g5668_2 2.224404
+R3 g5668_1 g5668_2 2.224404
+.ends
+
+.subckt netg6387 g6387_1 g6387_0 gnd
+C1  g6387_1 gnd 2.080806f
+C2  g6387_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6387_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 2 g6387_1 2.224404
+.ends
+
+.subckt netg5923 g5923_2 g5923_1 g5923_0 gnd
+C1  g5923_2 gnd 2.080806f
+C2  g5923_1 gnd 2.080806f
+C3  g5923_0 gnd 2.080806f
+R1 g5923_0 g5923_1 2.224404
+C4 1 gnd 2.080806f
+R2 1 g5923_0 2.224404
+R3 1 g5923_2 2.224404
+.ends
+
+.subckt netg2528 g2528_1 g2528_0 g2528_2 gnd
+C1  g2528_1 gnd 2.080806f
+C2  g2528_0 gnd 2.080806f
+C3  g2528_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g2528_0 1 2.224404
+R2 1 g2528_1 2.224404
+R3 g2528_1 g2528_2 2.224404
+.ends
+
+.subckt netg5685 g5685_2 g5685_0 g5685_1 gnd
+C1  g5685_2 gnd 2.080806f
+C2  g5685_0 gnd 2.080806f
+C3  g5685_1 gnd 2.080806f
+R1 g5685_2 g5685_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g5685_0 2.224404
+R3 g5685_1 1 2.224404
+.ends
+
+.subckt netg6934 g6934_0 g6934_1 gnd
+C1  g6934_0 gnd 2.080806f
+C2  g6934_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6934_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 2 g6934_1 2.224404
+.ends
+
+.subckt netx321 x321_0 x321_1 gnd
+C1  x321_0 gnd 2.080806f
+C2  x321_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x321_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 x321_1 2 2.224404
+.ends
+
+.subckt netg1057 g1057_2 g1057_0 g1057_1 gnd
+C1  g1057_2 gnd 2.080806f
+C2  g1057_0 gnd 2.080806f
+C3  g1057_1 gnd 2.080806f
+R1 g1057_0 g1057_2 2.224404
+C4 1 gnd 2.080806f
+R2 g1057_2 1 2.224404
+R3 g1057_1 1 2.224404
+.ends
+
+.subckt netg4292 g4292_0 g4292_1 gnd
+C1  g4292_0 gnd 2.080806f
+C2  g4292_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4292_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g4292_1 2 2.224404
+.ends
+
+.subckt netg2615 g2615_0 g2615_2 g2615_1 gnd
+C1  g2615_0 gnd 2.080806f
+C2  g2615_2 gnd 2.080806f
+C3  g2615_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g2615_0 1 2.224404
+R2 1 g2615_1 2.224404
+R3 g2615_2 1 2.224404
+.ends
+
+.subckt netg6796 g6796_2 g6796_1 g6796_0 gnd
+C1  g6796_2 gnd 2.080806f
+C2  g6796_1 gnd 2.080806f
+C3  g6796_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g6796_0 1 2.224404
+R2 1 g6796_2 2.224404
+R3 g6796_2 g6796_1 2.224404
+.ends
+
+.subckt netg3567 g3567_0 g3567_1 gnd
+C1  g3567_0 gnd 2.080806f
+C2  g3567_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3567_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g3567_1 2.224404
+.ends
+
+.subckt netg1157 g1157_0 g1157_1 gnd
+C1  g1157_0 gnd 2.080806f
+C2  g1157_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1157_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g1157_1 2.224404
+.ends
+
+.subckt netg6495 g6495_0 g6495_2 g6495_1 gnd
+C1  g6495_0 gnd 2.080806f
+C2  g6495_2 gnd 2.080806f
+C3  g6495_1 gnd 2.080806f
+R1 g6495_2 g6495_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g6495_2 2.224404
+R3 g6495_1 1 2.224404
+.ends
+
+.subckt netg2346 g2346_1 g2346_0 gnd
+C1  g2346_1 gnd 2.080806f
+C2  g2346_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2346_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g2346_1 2.224404
+.ends
+
+.subckt netg2418 g2418_0 g2418_2 g2418_1 gnd
+C1  g2418_0 gnd 2.080806f
+C2  g2418_2 gnd 2.080806f
+C3  g2418_1 gnd 2.080806f
+R1 g2418_2 g2418_0 2.224404
+C4 1 gnd 2.080806f
+R2 g2418_2 1 2.224404
+R3 1 g2418_1 2.224404
+.ends
+
+.subckt netg3539 g3539_1 g3539_0 gnd
+C1  g3539_1 gnd 2.080806f
+C2  g3539_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3539_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g3539_1 2.224404
+.ends
+
+.subckt netg4044 g4044_1 g4044_0 gnd
+C1  g4044_1 gnd 2.080806f
+C2  g4044_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4044_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g4044_1 2.224404
+.ends
+
+.subckt netg2825 g2825_0 g2825_1 gnd
+C1  g2825_0 gnd 2.080806f
+C2  g2825_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2825_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g2825_1 2 2.224404
+.ends
+
+.subckt netg4003 g4003_1 g4003_2 g4003_0 gnd
+C1  g4003_1 gnd 2.080806f
+C2  g4003_2 gnd 2.080806f
+C3  g4003_0 gnd 2.080806f
+R1 g4003_2 g4003_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g4003_2 2.224404
+R3 1 g4003_1 2.224404
+.ends
+
+.subckt netg2395 g2395_2 g2395_1 g2395_0 gnd
+C1  g2395_2 gnd 2.080806f
+C2  g2395_1 gnd 2.080806f
+C3  g2395_0 gnd 2.080806f
+R1 g2395_2 g2395_0 2.224404
+C4 1 gnd 2.080806f
+R2 g2395_0 1 2.224404
+R3 1 g2395_1 2.224404
+.ends
+
+.subckt netg3893 g3893_0 g3893_1 gnd
+C1  g3893_0 gnd 2.080806f
+C2  g3893_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3893_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g3893_1 2 2.224404
+.ends
+
+.subckt netg1513 g1513_0 g1513_1 gnd
+C1  g1513_0 gnd 2.080806f
+C2  g1513_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1513_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g1513_1 2.224404
+.ends
+
+.subckt netg5677 g5677_0 g5677_2 g5677_1 gnd
+C1  g5677_0 gnd 2.080806f
+C2  g5677_2 gnd 2.080806f
+C3  g5677_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5677_0 1 2.224404
+R2 g5677_1 1 2.224404
+R3 1 g5677_2 2.224404
+.ends
+
+.subckt netg5553 g5553_0 g5553_1 gnd
+C1  g5553_0 gnd 2.080806f
+C2  g5553_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5553_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g5553_1 2.224404
+.ends
+
+.subckt netg7433 g7433_2 g7433_0 g7433_1 gnd
+C1  g7433_2 gnd 2.080806f
+C2  g7433_0 gnd 2.080806f
+C3  g7433_1 gnd 2.080806f
+R1 g7433_0 g7433_2 2.224404
+C4 1 gnd 2.080806f
+R2 1 g7433_0 2.224404
+R3 g7433_1 1 2.224404
+.ends
+
+.subckt netg5861 g5861_0 g5861_2 g5861_1 gnd
+C1  g5861_0 gnd 2.080806f
+C2  g5861_2 gnd 2.080806f
+C3  g5861_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5861_0 2.224404
+R2 g5861_2 1 2.224404
+R3 g5861_1 g5861_2 2.224404
+.ends
+
+.subckt netg6074 g6074_1 g6074_0 gnd
+C1  g6074_1 gnd 2.080806f
+C2  g6074_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6074_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g6074_1 2 2.224404
+.ends
+
+.subckt netg5734 g5734_1 g5734_2 gnd
+C1  g5734_1 gnd 2.080806f
+C2  g5734_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5734_2 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g5734_1 2.224404
+.ends
+
+.subckt netg4190 g4190_2 g4190_0 g4190_1 gnd
+C1  g4190_2 gnd 2.080806f
+C2  g4190_0 gnd 2.080806f
+C3  g4190_1 gnd 2.080806f
+R1 g4190_0 g4190_1 2.224404
+C4 1 gnd 2.080806f
+R2 g4190_1 1 2.224404
+R3 1 g4190_2 2.224404
+.ends
+
+.subckt netg3504 g3504_1 g3504_0 gnd
+C1  g3504_1 gnd 2.080806f
+C2  g3504_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3504_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g3504_1 2 2.224404
+.ends
+
+.subckt netg5967 g5967_1 g5967_0 gnd
+C1  g5967_1 gnd 2.080806f
+C2  g5967_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5967_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g5967_1 2 2.224404
+.ends
+
+.subckt netg7000 g7000_1 g7000_0 gnd
+C1  g7000_1 gnd 2.080806f
+C2  g7000_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7000_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g7000_1 2.224404
+.ends
+
+.subckt netg5522 g5522_2 g5522_0 g5522_1 gnd
+C1  g5522_2 gnd 2.080806f
+C2  g5522_0 gnd 2.080806f
+C3  g5522_1 gnd 2.080806f
+R1 g5522_1 g5522_0 2.224404
+C4 1 gnd 2.080806f
+R2 g5522_0 1 2.224404
+R3 1 g5522_2 2.224404
+.ends
+
+.subckt netg3441 g3441_1 g3441_2 gnd
+C1  g3441_1 gnd 2.080806f
+C2  g3441_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3441_2 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g3441_1 2 2.224404
+.ends
+
+.subckt netg6535 g6535_1 g6535_0 gnd
+C1  g6535_1 gnd 2.080806f
+C2  g6535_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6535_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g6535_1 2 2.224404
+.ends
+
+.subckt netg6541 g6541_1 g6541_0 gnd
+C1  g6541_1 gnd 2.080806f
+C2  g6541_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6541_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g6541_1 2 2.224404
+.ends
+
+.subckt netg3485 g3485_1 g3485_0 gnd
+C1  g3485_1 gnd 2.080806f
+C2  g3485_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3485_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g3485_1 2 2.224404
+.ends
+
+.subckt netg4617 g4617_1 g4617_0 gnd
+C1  g4617_1 gnd 2.080806f
+C2  g4617_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4617_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g4617_1 2 2.224404
+.ends
+
+.subckt netg1579 g1579_1 g1579_0 gnd
+C1  g1579_1 gnd 2.080806f
+C2  g1579_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1579_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g1579_1 2 2.224404
+.ends
+
+.subckt netg4151 g4151_1 g4151_2 g4151_0 gnd
+C1  g4151_1 gnd 2.080806f
+C2  g4151_2 gnd 2.080806f
+C3  g4151_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g4151_0 2.224404
+R2 g4151_1 1 2.224404
+R3 1 g4151_2 2.224404
+.ends
+
+.subckt netg4213 g4213_1 g4213_2 gnd
+C1  g4213_1 gnd 2.080806f
+C2  g4213_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4213_1 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g4213_2 2.224404
+.ends
+
+.subckt netg6093 g6093_2 g6093_1 g6093_0 gnd
+C1  g6093_2 gnd 2.080806f
+C2  g6093_1 gnd 2.080806f
+C3  g6093_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g6093_0 2.224404
+R2 g6093_2 1 2.224404
+R3 g6093_1 g6093_2 2.224404
+.ends
+
+.subckt netg3569 g3569_0 g3569_1 gnd
+C1  g3569_0 gnd 2.080806f
+C2  g3569_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3569_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g3569_1 2 2.224404
+.ends
+
+.subckt netg2800 g2800_0 g2800_1 gnd
+C1  g2800_0 gnd 2.080806f
+C2  g2800_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2800_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g2800_1 2 2.224404
+.ends
+
+.subckt netg5089 g5089_0 g5089_2 g5089_1 gnd
+C1  g5089_0 gnd 2.080806f
+C2  g5089_2 gnd 2.080806f
+C3  g5089_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5089_0 2.224404
+R2 g5089_1 1 2.224404
+R3 g5089_2 1 2.224404
+.ends
+
+.subckt netg6467 g6467_1 g6467_0 gnd
+C1  g6467_1 gnd 2.080806f
+C2  g6467_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6467_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g6467_1 2 2.224404
+.ends
+
+.subckt netg6856 g6856_1 g6856_2 g6856_0 gnd
+C1  g6856_1 gnd 2.080806f
+C2  g6856_2 gnd 2.080806f
+C3  g6856_0 gnd 2.080806f
+R1 g6856_1 g6856_0 2.224404
+C4 1 gnd 2.080806f
+R2 g6856_0 1 2.224404
+R3 1 g6856_2 2.224404
+.ends
+
+.subckt netg7312 g7312_2 g7312_0 g7312_1 gnd
+C1  g7312_2 gnd 2.080806f
+C2  g7312_0 gnd 2.080806f
+C3  g7312_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g7312_0 1 2.224404
+R2 1 g7312_1 2.224404
+R3 1 g7312_2 2.224404
+.ends
+
+.subckt netg2958 g2958_0 g2958_1 gnd
+C1  g2958_0 gnd 2.080806f
+C2  g2958_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2958_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g2958_1 2.224404
+.ends
+
+.subckt netg6327 g6327_0 g6327_1 gnd
+C1  g6327_0 gnd 2.080806f
+C2  g6327_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6327_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g6327_1 2.224404
+.ends
+
+.subckt netg4178 g4178_1 g4178_0 gnd
+C1  g4178_1 gnd 2.080806f
+C2  g4178_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4178_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 2 g4178_1 2.224404
+.ends
+
+.subckt netg5886 g5886_1 g5886_0 gnd
+C1  g5886_1 gnd 2.080806f
+C2  g5886_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5886_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g5886_1 2 2.224404
+.ends
+
+.subckt netg6315 g6315_1 g6315_0 gnd
+C1  g6315_1 gnd 2.080806f
+C2  g6315_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6315_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g6315_1 2.224404
+.ends
+
+.subckt netg2561 g2561_2 g2561_1 g2561_0 gnd
+C1  g2561_2 gnd 2.080806f
+C2  g2561_1 gnd 2.080806f
+C3  g2561_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g2561_0 2.224404
+R2 g2561_1 1 2.224404
+R3 g2561_1 g2561_2 2.224404
+.ends
+
+.subckt netg1571 g1571_1 g1571_0 gnd
+C1  g1571_1 gnd 2.080806f
+C2  g1571_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1571_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g1571_1 2 2.224404
+.ends
+
+.subckt netg1435 g1435_1 g1435_0 gnd
+C1  g1435_1 gnd 2.080806f
+C2  g1435_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1435_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g1435_1 2.224404
+.ends
+
+.subckt netg991 g991_2 g991_0 gnd
+C1  g991_2 gnd 2.080806f
+C2  g991_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g991_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g991_2 2 2.224404
+.ends
+
+.subckt netg6551 g6551_0 g6551_1 gnd
+C1  g6551_0 gnd 2.080806f
+C2  g6551_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6551_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g6551_1 2.224404
+.ends
+
+.subckt netg6374 g6374_1 g6374_2 g6374_0 gnd
+C1  g6374_1 gnd 2.080806f
+C2  g6374_2 gnd 2.080806f
+C3  g6374_0 gnd 2.080806f
+R1 g6374_1 g6374_0 2.224404
+C4 1 gnd 2.080806f
+R2 g6374_0 1 2.224404
+R3 1 g6374_2 2.224404
+.ends
+
+.subckt netg2353 g2353_0 g2353_1 g2353_2 gnd
+C1  g2353_0 gnd 2.080806f
+C2  g2353_1 gnd 2.080806f
+C3  g2353_2 gnd 2.080806f
+R1 g2353_0 g2353_2 2.224404
+C4 1 gnd 2.080806f
+R2 g2353_2 1 2.224404
+R3 1 g2353_1 2.224404
+.ends
+
+.subckt netg2618 g2618_1 g2618_2 gnd
+C1  g2618_1 gnd 2.080806f
+C2  g2618_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2618_2 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g2618_1 2.224404
+.ends
+
+.subckt netg1253 g1253_1 g1253_0 gnd
+C1  g1253_1 gnd 2.080806f
+C2  g1253_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1253_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g1253_1 2.224404
+.ends
+
+.subckt netg2450 g2450_0 g2450_1 g2450_2 gnd
+C1  g2450_0 gnd 2.080806f
+C2  g2450_1 gnd 2.080806f
+C3  g2450_2 gnd 2.080806f
+R1 g2450_1 g2450_0 2.224404
+C4 1 gnd 2.080806f
+R2 g2450_0 1 2.224404
+R3 1 g2450_2 2.224404
+.ends
+
+.subckt netg5731 g5731_0 g5731_1 g5731_2 gnd
+C1  g5731_0 gnd 2.080806f
+C2  g5731_1 gnd 2.080806f
+C3  g5731_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5731_0 2.224404
+R2 g5731_2 1 2.224404
+R3 g5731_1 g5731_2 2.224404
+.ends
+
+.subckt netg2627 g2627_0 g2627_2 g2627_1 gnd
+C1  g2627_0 gnd 2.080806f
+C2  g2627_2 gnd 2.080806f
+C3  g2627_1 gnd 2.080806f
+R1 g2627_1 g2627_0 2.224404
+C4 1 gnd 2.080806f
+R2 g2627_1 1 2.224404
+R3 1 g2627_2 2.224404
+.ends
+
+.subckt netg3303 g3303_1 g3303_2 gnd
+C1  g3303_1 gnd 2.080806f
+C2  g3303_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3303_2 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 2 g3303_1 2.224404
+.ends
+
+.subckt netg6124 g6124_1 g6124_0 g6124_2 gnd
+C1  g6124_1 gnd 2.080806f
+C2  g6124_0 gnd 2.080806f
+C3  g6124_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g6124_0 1 2.224404
+R2 1 g6124_2 2.224404
+R3 g6124_1 g6124_2 2.224404
+.ends
+
+.subckt netg6893 g6893_1 g6893_0 gnd
+C1  g6893_1 gnd 2.080806f
+C2  g6893_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6893_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 2 g6893_1 2.224404
+.ends
+
+.subckt netg3058 g3058_0 g3058_1 gnd
+C1  g3058_0 gnd 2.080806f
+C2  g3058_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3058_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g3058_1 2 2.224404
+.ends
+
+.subckt netg6987 g6987_2 g6987_1 g6987_0 gnd
+C1  g6987_2 gnd 2.080806f
+C2  g6987_1 gnd 2.080806f
+C3  g6987_0 gnd 2.080806f
+R1 g6987_1 g6987_0 2.224404
+C4 1 gnd 2.080806f
+R2 g6987_0 1 2.224404
+R3 1 g6987_2 2.224404
+.ends
+
+.subckt netg5036 g5036_1 g5036_0 g5036_2 gnd
+C1  g5036_1 gnd 2.080806f
+C2  g5036_0 gnd 2.080806f
+C3  g5036_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5036_0 1 2.224404
+R2 1 g5036_1 2.224404
+R3 g5036_1 g5036_2 2.224404
+.ends
+
+.subckt netg1581 g1581_0 g1581_1 gnd
+C1  g1581_0 gnd 2.080806f
+C2  g1581_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1581_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g1581_1 2 2.224404
+.ends
+
+.subckt netg6625 g6625_2 g6625_1 g6625_0 gnd
+C1  g6625_2 gnd 2.080806f
+C2  g6625_1 gnd 2.080806f
+C3  g6625_0 gnd 2.080806f
+R1 g6625_0 g6625_1 2.224404
+C4 1 gnd 2.080806f
+R2 g6625_1 1 2.224404
+R3 1 g6625_2 2.224404
+.ends
+
+.subckt netg4448 g4448_1 g4448_0 gnd
+C1  g4448_1 gnd 2.080806f
+C2  g4448_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4448_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g4448_1 2 2.224404
+.ends
+
+.subckt netg955 g955_0 g955_2 g955_1 gnd
+C1  g955_0 gnd 2.080806f
+C2  g955_2 gnd 2.080806f
+C3  g955_1 gnd 2.080806f
+R1 g955_0 g955_1 2.224404
+C4 1 gnd 2.080806f
+R2 1 g955_0 2.224404
+R3 g955_2 1 2.224404
+.ends
+
+.subckt netg3987 g3987_0 g3987_1 gnd
+C1  g3987_0 gnd 2.080806f
+C2  g3987_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3987_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g3987_1 2 2.224404
+.ends
+
+.subckt netg4045 g4045_0 g4045_1 gnd
+C1  g4045_0 gnd 2.080806f
+C2  g4045_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4045_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g4045_1 2 2.224404
+.ends
+
+.subckt netg1932 g1932_0 g1932_1 gnd
+C1  g1932_0 gnd 2.080806f
+C2  g1932_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1932_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g1932_1 2 2.224404
+.ends
+
+.subckt netg3538 g3538_1 g3538_0 gnd
+C1  g3538_1 gnd 2.080806f
+C2  g3538_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3538_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g3538_1 2.224404
+.ends
+
+.subckt netg2659 g2659_1 g2659_0 g2659_2 gnd
+C1  g2659_1 gnd 2.080806f
+C2  g2659_0 gnd 2.080806f
+C3  g2659_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g2659_0 1 2.224404
+R2 1 g2659_2 2.224404
+R3 g2659_2 g2659_1 2.224404
+.ends
+
+.subckt netx272 x272_0 x272_1 gnd
+C1  x272_0 gnd 2.080806f
+C2  x272_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x272_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 x272_1 2 2.224404
+.ends
+
+.subckt netg2805 g2805_0 g2805_1 gnd
+C1  g2805_0 gnd 2.080806f
+C2  g2805_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2805_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g2805_1 2.224404
+.ends
+
+.subckt netg5107 g5107_0 g5107_2 g5107_1 gnd
+C1  g5107_0 gnd 2.080806f
+C2  g5107_2 gnd 2.080806f
+C3  g5107_1 gnd 2.080806f
+R1 g5107_0 g5107_1 2.224404
+C4 1 gnd 2.080806f
+R2 g5107_0 1 2.224404
+R3 g5107_2 1 2.224404
+.ends
+
+.subckt netg3918 g3918_1 g3918_0 gnd
+C1  g3918_1 gnd 2.080806f
+C2  g3918_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3918_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g3918_1 2.224404
+.ends
+
+.subckt netg6904 g6904_1 g6904_0 gnd
+C1  g6904_1 gnd 2.080806f
+C2  g6904_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6904_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g6904_1 2.224404
+.ends
+
+.subckt netg6400 g6400_0 g6400_1 gnd
+C1  g6400_0 gnd 2.080806f
+C2  g6400_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6400_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 2 g6400_1 2.224404
+.ends
+
+.subckt netg6515 g6515_1 g6515_0 gnd
+C1  g6515_1 gnd 2.080806f
+C2  g6515_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6515_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g6515_1 2.224404
+.ends
+
+.subckt netg2573 g2573_2 g2573_1 g2573_0 gnd
+C1  g2573_2 gnd 2.080806f
+C2  g2573_1 gnd 2.080806f
+C3  g2573_0 gnd 2.080806f
+R1 g2573_1 g2573_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g2573_1 2.224404
+R3 g2573_2 1 2.224404
+.ends
+
+.subckt netg6096 g6096_1 g6096_2 gnd
+C1  g6096_1 gnd 2.080806f
+C2  g6096_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6096_2 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 2 g6096_1 2.224404
+.ends
+
+.subckt netg6829 g6829_2 g6829_1 g6829_0 g6829_3 gnd
+C1  g6829_2 gnd 2.080806f
+C2  g6829_1 gnd 2.080806f
+C3  g6829_0 gnd 2.080806f
+C4  g6829_3 gnd 2.080806f
+R1 g6829_3 g6829_0 2.224404
+R2 g6829_2 g6829_3 2.224404
+R3 g6829_1 g6829_2 2.224404
+.ends
+
+.subckt netg5407 g5407_1 g5407_0 gnd
+C1  g5407_1 gnd 2.080806f
+C2  g5407_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5407_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g5407_1 2 2.224404
+.ends
+
+.subckt netg4303 g4303_0 g4303_1 gnd
+C1  g4303_0 gnd 2.080806f
+C2  g4303_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4303_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 2 g4303_1 2.224404
+.ends
+
+.subckt netg3321 g3321_0 g3321_1 g3321_2 gnd
+C1  g3321_0 gnd 2.080806f
+C2  g3321_1 gnd 2.080806f
+C3  g3321_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g3321_0 1 2.224404
+R2 1 g3321_1 2.224404
+R3 g3321_1 g3321_2 2.224404
+.ends
+
+.subckt netg895 g895_2 g895_1 g895_0 gnd
+C1  g895_2 gnd 2.080806f
+C2  g895_1 gnd 2.080806f
+C3  g895_0 gnd 2.080806f
+R1 g895_0 g895_2 2.224404
+C4 1 gnd 2.080806f
+R2 g895_2 1 2.224404
+R3 1 g895_1 2.224404
+.ends
+
+.subckt netg6715 g6715_0 g6715_1 g6715_2 gnd
+C1  g6715_0 gnd 2.080806f
+C2  g6715_1 gnd 2.080806f
+C3  g6715_2 gnd 2.080806f
+R1 g6715_0 g6715_2 2.224404
+C4 1 gnd 2.080806f
+R2 g6715_0 1 2.224404
+R3 1 g6715_1 2.224404
+.ends
+
+.subckt netx382 x382_1 x382_0 gnd
+C1  x382_1 gnd 2.080806f
+C2  x382_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x382_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 x382_1 2 2.224404
+.ends
+
+.subckt netg2600 g2600_2 g2600_0 g2600_1 gnd
+C1  g2600_2 gnd 2.080806f
+C2  g2600_0 gnd 2.080806f
+C3  g2600_1 gnd 2.080806f
+R1 g2600_0 g2600_1 2.224404
+C4 1 gnd 2.080806f
+R2 1 g2600_1 2.224404
+R3 g2600_2 1 2.224404
+.ends
+
+.subckt netg3386 g3386_1 g3386_2 g3386_0 gnd
+C1  g3386_1 gnd 2.080806f
+C2  g3386_2 gnd 2.080806f
+C3  g3386_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g3386_0 2.224404
+R2 g3386_2 1 2.224404
+R3 g3386_2 g3386_1 2.224404
+.ends
+
+.subckt netg3297 g3297_2 g3297_1 g3297_0 gnd
+C1  g3297_2 gnd 2.080806f
+C2  g3297_1 gnd 2.080806f
+C3  g3297_0 gnd 2.080806f
+R1 g3297_2 g3297_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g3297_2 2.224404
+R3 1 g3297_1 2.224404
+.ends
+
+.subckt netg3527 g3527_0 g3527_1 gnd
+C1  g3527_0 gnd 2.080806f
+C2  g3527_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3527_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g3527_1 2.224404
+.ends
+
+.subckt netg7444 g7444_1 g7444_0 gnd
+C1  g7444_1 gnd 2.080806f
+C2  g7444_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7444_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g7444_1 2.224404
+.ends
+
+.subckt netg4296 g4296_0 g4296_1 gnd
+C1  g4296_0 gnd 2.080806f
+C2  g4296_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4296_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g4296_1 2.224404
+.ends
+
+.subckt netg5593 g5593_2 g5593_1 g5593_0 gnd
+C1  g5593_2 gnd 2.080806f
+C2  g5593_1 gnd 2.080806f
+C3  g5593_0 gnd 2.080806f
+R1 g5593_0 g5593_1 2.224404
+C4 1 gnd 2.080806f
+R2 1 g5593_0 2.224404
+R3 g5593_2 1 2.224404
+.ends
+
+.subckt netg2806 g2806_1 g2806_0 gnd
+C1  g2806_1 gnd 2.080806f
+C2  g2806_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2806_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g2806_1 2.224404
+.ends
+
+.subckt netg2917 g2917_1 g2917_0 gnd
+C1  g2917_1 gnd 2.080806f
+C2  g2917_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2917_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g2917_1 2 2.224404
+.ends
+
+.subckt netg4985 g4985_2 g4985_1 g4985_0 gnd
+C1  g4985_2 gnd 2.080806f
+C2  g4985_1 gnd 2.080806f
+C3  g4985_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g4985_0 2.224404
+R2 g4985_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g4985_0 2.224404
+R4 g4985_2 2 2.224404
+.ends
+
+.subckt netg4060 g4060_0 g4060_1 gnd
+C1  g4060_0 gnd 2.080806f
+C2  g4060_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4060_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g4060_1 2.224404
+.ends
+
+.subckt netg1387 g1387_0 g1387_1 g1387_2 gnd
+C1  g1387_0 gnd 2.080806f
+C2  g1387_1 gnd 2.080806f
+C3  g1387_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g1387_0 1 2.224404
+R2 1 g1387_2 2.224404
+R3 g1387_2 g1387_1 2.224404
+.ends
+
+.subckt netg5003 g5003_1 g5003_2 g5003_0 gnd
+C1  g5003_1 gnd 2.080806f
+C2  g5003_2 gnd 2.080806f
+C3  g5003_0 gnd 2.080806f
+R1 g5003_2 g5003_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g5003_2 2.224404
+R3 g5003_1 1 2.224404
+.ends
+
+.subckt netg2044 g2044_0 g2044_1 gnd
+C1  g2044_0 gnd 2.080806f
+C2  g2044_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2044_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g2044_1 2 2.224404
+.ends
+
+.subckt netg6685 g6685_0 g6685_1 gnd
+C1  g6685_0 gnd 2.080806f
+C2  g6685_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6685_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g6685_1 2 2.224404
+.ends
+
+.subckt netg5387 g5387_0 g5387_1 gnd
+C1  g5387_0 gnd 2.080806f
+C2  g5387_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5387_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g5387_1 2.224404
+.ends
+
+.subckt netg1871 g1871_2 g1871_1 g1871_0 gnd
+C1  g1871_2 gnd 2.080806f
+C2  g1871_1 gnd 2.080806f
+C3  g1871_0 gnd 2.080806f
+R1 g1871_2 g1871_0 2.224404
+C4 1 gnd 2.080806f
+R2 g1871_0 1 2.224404
+R3 1 g1871_1 2.224404
+.ends
+
+.subckt netg4401 g4401_0 g4401_1 gnd
+C1  g4401_0 gnd 2.080806f
+C2  g4401_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4401_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g4401_1 2.224404
+.ends
+
+.subckt netg1865 g1865_1 g1865_0 g1865_2 gnd
+C1  g1865_1 gnd 2.080806f
+C2  g1865_0 gnd 2.080806f
+C3  g1865_2 gnd 2.080806f
+R1 g1865_0 g1865_1 2.224404
+C4 1 gnd 2.080806f
+R2 g1865_1 1 2.224404
+R3 1 g1865_2 2.224404
+.ends
+
+.subckt netg4887 g4887_1 g4887_2 g4887_0 gnd
+C1  g4887_1 gnd 2.080806f
+C2  g4887_2 gnd 2.080806f
+C3  g4887_0 gnd 2.080806f
+R1 g4887_2 g4887_0 2.224404
+C4 1 gnd 2.080806f
+R2 g4887_0 1 2.224404
+R3 1 g4887_1 2.224404
+.ends
+
+.subckt netg3192 g3192_1 g3192_2 g3192_0 gnd
+C1  g3192_1 gnd 2.080806f
+C2  g3192_2 gnd 2.080806f
+C3  g3192_0 gnd 2.080806f
+R1 g3192_2 g3192_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g3192_0 2.224404
+R3 1 g3192_1 2.224404
+.ends
+
+.subckt netg2471 g2471_0 g2471_2 g2471_1 gnd
+C1  g2471_0 gnd 2.080806f
+C2  g2471_2 gnd 2.080806f
+C3  g2471_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g2471_0 2.224404
+R2 1 g2471_1 2.224404
+C5 2 gnd 2.080806f
+R3 g2471_0 2 2.224404
+R4 2 g2471_2 2.224404
+.ends
+
+.subckt netg6226 g6226_1 g6226_0 g6226_2 gnd
+C1  g6226_1 gnd 2.080806f
+C2  g6226_0 gnd 2.080806f
+C3  g6226_2 gnd 2.080806f
+R1 g6226_1 g6226_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g6226_1 2.224404
+R3 g6226_2 1 2.224404
+.ends
+
+.subckt netg5909 g5909_1 g5909_0 g5909_2 gnd
+C1  g5909_1 gnd 2.080806f
+C2  g5909_0 gnd 2.080806f
+C3  g5909_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5909_0 1 2.224404
+R2 1 g5909_2 2.224404
+R3 g5909_1 g5909_2 2.224404
+.ends
+
+.subckt netg4764 g4764_1 g4764_2 g4764_0 gnd
+C1  g4764_1 gnd 2.080806f
+C2  g4764_2 gnd 2.080806f
+C3  g4764_0 gnd 2.080806f
+R1 g4764_0 g4764_1 2.224404
+C4 1 gnd 2.080806f
+R2 g4764_1 1 2.224404
+R3 1 g4764_2 2.224404
+.ends
+
+.subckt netg4157 g4157_0 g4157_2 gnd
+C1  g4157_0 gnd 2.080806f
+C2  g4157_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4157_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g4157_2 2 2.224404
+.ends
+
+.subckt netg5232 g5232_0 g5232_1 gnd
+C1  g5232_0 gnd 2.080806f
+C2  g5232_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5232_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g5232_1 2.224404
+.ends
+
+.subckt netg1137 g1137_1 g1137_0 gnd
+C1  g1137_1 gnd 2.080806f
+C2  g1137_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1137_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g1137_1 2.224404
+.ends
+
+.subckt netx282 x282_1 x282_0 gnd
+C1  x282_1 gnd 2.080806f
+C2  x282_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 x282_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 x282_1 2.224404
+.ends
+
+.subckt netg1553 g1553_0 g1553_1 gnd
+C1  g1553_0 gnd 2.080806f
+C2  g1553_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1553_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g1553_1 2.224404
+.ends
+
+.subckt netg4667 g4667_0 g4667_1 gnd
+C1  g4667_0 gnd 2.080806f
+C2  g4667_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4667_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g4667_1 2 2.224404
+.ends
+
+.subckt netg1073 g1073_1 g1073_0 g1073_2 gnd
+C1  g1073_1 gnd 2.080806f
+C2  g1073_0 gnd 2.080806f
+C3  g1073_2 gnd 2.080806f
+R1 g1073_1 g1073_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g1073_1 2.224404
+R3 g1073_2 1 2.224404
+.ends
+
+.subckt netg2829 g2829_1 g2829_0 gnd
+C1  g2829_1 gnd 2.080806f
+C2  g2829_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2829_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g2829_1 2.224404
+.ends
+
+.subckt netg1042 g1042_1 g1042_0 g1042_2 gnd
+C1  g1042_1 gnd 2.080806f
+C2  g1042_0 gnd 2.080806f
+C3  g1042_2 gnd 2.080806f
+R1 g1042_0 g1042_2 2.224404
+C4 1 gnd 2.080806f
+R2 1 g1042_0 2.224404
+R3 1 g1042_1 2.224404
+.ends
+
+.subckt netg6419 g6419_0 g6419_1 gnd
+C1  g6419_0 gnd 2.080806f
+C2  g6419_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6419_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g6419_1 2 2.224404
+.ends
+
+.subckt netg3554 g3554_1 g3554_0 gnd
+C1  g3554_1 gnd 2.080806f
+C2  g3554_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3554_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g3554_1 2.224404
+.ends
+
+.subckt netg3474 g3474_1 g3474_0 gnd
+C1  g3474_1 gnd 2.080806f
+C2  g3474_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3474_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g3474_1 2.224404
+.ends
+
+.subckt netg6824 g6824_1 g6824_0 gnd
+C1  g6824_1 gnd 2.080806f
+C2  g6824_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6824_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g6824_1 2.224404
+.ends
+
+.subckt netg5160 g5160_1 g5160_0 g5160_2 gnd
+C1  g5160_1 gnd 2.080806f
+C2  g5160_0 gnd 2.080806f
+C3  g5160_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5160_0 2.224404
+R2 g5160_1 1 2.224404
+R3 1 g5160_2 2.224404
+.ends
+
+.subckt netg4781 g4781_1 g4781_0 g4781_2 gnd
+C1  g4781_1 gnd 2.080806f
+C2  g4781_0 gnd 2.080806f
+C3  g4781_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g4781_0 1 2.224404
+R2 1 g4781_2 2.224404
+R3 g4781_2 g4781_1 2.224404
+.ends
+
+.subckt netx441 x441_0 x441_1 gnd
+C1  x441_0 gnd 2.080806f
+C2  x441_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x441_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 x441_1 2 2.224404
+.ends
+
+.subckt netg7041 g7041_1 g7041_2 g7041_0 gnd
+C1  g7041_1 gnd 2.080806f
+C2  g7041_2 gnd 2.080806f
+C3  g7041_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g7041_0 2.224404
+R2 g7041_2 1 2.224404
+R3 g7041_2 g7041_1 2.224404
+.ends
+
+.subckt netg3502 g3502_1 g3502_0 gnd
+C1  g3502_1 gnd 2.080806f
+C2  g3502_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3502_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g3502_1 2 2.224404
+.ends
+
+.subckt netg5858 g5858_0 g5858_1 gnd
+C1  g5858_0 gnd 2.080806f
+C2  g5858_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5858_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g5858_1 2 2.224404
+.ends
+
+.subckt netg5951 g5951_0 g5951_1 gnd
+C1  g5951_0 gnd 2.080806f
+C2  g5951_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5951_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 2 g5951_1 2.224404
+.ends
+
+.subckt netg1433 g1433_1 g1433_0 gnd
+C1  g1433_1 gnd 2.080806f
+C2  g1433_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1433_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g1433_1 2 2.224404
+.ends
+
+.subckt netg6116 g6116_0 g6116_2 g6116_1 gnd
+C1  g6116_0 gnd 2.080806f
+C2  g6116_2 gnd 2.080806f
+C3  g6116_1 gnd 2.080806f
+R1 g6116_1 g6116_0 2.224404
+C4 1 gnd 2.080806f
+R2 g6116_0 1 2.224404
+R3 1 g6116_2 2.224404
+.ends
+
+.subckt netg7106 g7106_0 g7106_1 gnd
+C1  g7106_0 gnd 2.080806f
+C2  g7106_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7106_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g7106_1 2.224404
+.ends
+
+.subckt netg6193 g6193_0 g6193_1 gnd
+C1  g6193_0 gnd 2.080806f
+C2  g6193_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6193_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g6193_1 2 2.224404
+.ends
+
+.subckt netg6386 g6386_1 g6386_0 gnd
+C1  g6386_1 gnd 2.080806f
+C2  g6386_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6386_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g6386_1 2 2.224404
+.ends
+
+.subckt netg4405 g4405_0 g4405_1 gnd
+C1  g4405_0 gnd 2.080806f
+C2  g4405_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4405_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g4405_1 2.224404
+.ends
+
+.subckt netg937 g937_2 g937_0 g937_1 gnd
+C1  g937_2 gnd 2.080806f
+C2  g937_0 gnd 2.080806f
+C3  g937_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g937_0 2.224404
+R2 g937_1 1 2.224404
+R3 g937_1 g937_2 2.224404
+.ends
+
+.subckt netg2347 g2347_0 g2347_2 g2347_1 gnd
+C1  g2347_0 gnd 2.080806f
+C2  g2347_2 gnd 2.080806f
+C3  g2347_1 gnd 2.080806f
+R1 g2347_1 g2347_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g2347_0 2.224404
+R3 g2347_2 1 2.224404
+.ends
+
+.subckt netg3219 g3219_1 g3219_2 g3219_0 gnd
+C1  g3219_1 gnd 2.080806f
+C2  g3219_2 gnd 2.080806f
+C3  g3219_0 gnd 2.080806f
+R1 g3219_0 g3219_2 2.224404
+C4 1 gnd 2.080806f
+R2 g3219_2 1 2.224404
+R3 1 g3219_1 2.224404
+.ends
+
+.subckt netg1311 g1311_1 g1311_0 gnd
+C1  g1311_1 gnd 2.080806f
+C2  g1311_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1311_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 2 g1311_1 2.224404
+.ends
+
+.subckt netg3054 g3054_1 g3054_0 gnd
+C1  g3054_1 gnd 2.080806f
+C2  g3054_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3054_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g3054_1 2.224404
+.ends
+
+.subckt netg964 g964_1 g964_0 g964_2 gnd
+C1  g964_1 gnd 2.080806f
+C2  g964_0 gnd 2.080806f
+C3  g964_2 gnd 2.080806f
+R1 g964_0 g964_2 2.224404
+C4 1 gnd 2.080806f
+R2 g964_2 1 2.224404
+R3 1 g964_1 2.224404
+.ends
+
+.subckt netg6941 g6941_1 g6941_0 gnd
+C1  g6941_1 gnd 2.080806f
+C2  g6941_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6941_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g6941_1 2 2.224404
+.ends
+
+.subckt netg1552 g1552_0 g1552_1 gnd
+C1  g1552_0 gnd 2.080806f
+C2  g1552_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1552_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g1552_1 2.224404
+.ends
+
+.subckt netg3222 g3222_0 g3222_2 g3222_1 gnd
+C1  g3222_0 gnd 2.080806f
+C2  g3222_2 gnd 2.080806f
+C3  g3222_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g3222_0 2.224404
+R2 1 g3222_2 2.224404
+R3 g3222_1 g3222_2 2.224404
+.ends
+
+.subckt netg6527 g6527_0 g6527_1 gnd
+C1  g6527_0 gnd 2.080806f
+C2  g6527_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6527_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g6527_1 2.224404
+.ends
+
+.subckt netg5508 g5508_2 g5508_0 g5508_1 gnd
+C1  g5508_2 gnd 2.080806f
+C2  g5508_0 gnd 2.080806f
+C3  g5508_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5508_0 1 2.224404
+R2 1 g5508_2 2.224404
+R3 g5508_2 g5508_1 2.224404
+.ends
+
+.subckt netg4095 g4095_1 g4095_0 gnd
+C1  g4095_1 gnd 2.080806f
+C2  g4095_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4095_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g4095_1 2.224404
+.ends
+
+.subckt netg898 g898_1 g898_2 g898_0 gnd
+C1  g898_1 gnd 2.080806f
+C2  g898_2 gnd 2.080806f
+C3  g898_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g898_0 2.224404
+R2 g898_1 1 2.224404
+R3 g898_2 g898_1 2.224404
+.ends
+
+.subckt netg1175 g1175_1 g1175_0 gnd
+C1  g1175_1 gnd 2.080806f
+C2  g1175_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1175_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 2 g1175_1 2.224404
+.ends
+
+.subckt netg6478 g6478_1 g6478_2 g6478_0 gnd
+C1  g6478_1 gnd 2.080806f
+C2  g6478_2 gnd 2.080806f
+C3  g6478_0 gnd 2.080806f
+R1 g6478_0 g6478_1 2.224404
+C4 1 gnd 2.080806f
+R2 1 g6478_0 2.224404
+R3 g6478_2 1 2.224404
+.ends
+
+.subckt netg7357 g7357_1 g7357_0 gnd
+C1  g7357_1 gnd 2.080806f
+C2  g7357_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7357_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 2 g7357_1 2.224404
+.ends
+
+.subckt netg7343 g7343_1 g7343_0 gnd
+C1  g7343_1 gnd 2.080806f
+C2  g7343_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7343_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 2 g7343_1 2.224404
+.ends
+
+.subckt netg919 g919_2 g919_1 g919_0 gnd
+C1  g919_2 gnd 2.080806f
+C2  g919_1 gnd 2.080806f
+C3  g919_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g919_0 1 2.224404
+R2 1 g919_2 2.224404
+R3 g919_2 g919_1 2.224404
+.ends
+
+.subckt netg2716 g2716_1 g2716_0 g2716_2 gnd
+C1  g2716_1 gnd 2.080806f
+C2  g2716_0 gnd 2.080806f
+C3  g2716_2 gnd 2.080806f
+R1 g2716_0 g2716_1 2.224404
+C4 1 gnd 2.080806f
+R2 g2716_1 1 2.224404
+R3 1 g2716_2 2.224404
+.ends
+
+.subckt netg3138 g3138_0 g3138_2 g3138_1 gnd
+C1  g3138_0 gnd 2.080806f
+C2  g3138_2 gnd 2.080806f
+C3  g3138_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g3138_0 2.224404
+R2 1 g3138_1 2.224404
+C5 2 gnd 2.080806f
+R3 g3138_0 2 2.224404
+R4 2 g3138_2 2.224404
+.ends
+
+.subckt netg1096 g1096_0 g1096_1 gnd
+C1  g1096_0 gnd 2.080806f
+C2  g1096_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1096_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g1096_1 2.224404
+.ends
+
+.subckt netg4046 g4046_0 g4046_1 gnd
+C1  g4046_0 gnd 2.080806f
+C2  g4046_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4046_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g4046_1 2 2.224404
+.ends
+
+.subckt netg7216 g7216_1 g7216_0 gnd
+C1  g7216_1 gnd 2.080806f
+C2  g7216_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7216_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g7216_1 2.224404
+.ends
+
+.subckt netg4399 g4399_1 g4399_0 gnd
+C1  g4399_1 gnd 2.080806f
+C2  g4399_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4399_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g4399_1 2.224404
+.ends
+
+.subckt netg7104 g7104_0 g7104_1 gnd
+C1  g7104_0 gnd 2.080806f
+C2  g7104_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7104_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g7104_1 2 2.224404
+.ends
+
+.subckt netx71 x71_0 x71_1 gnd
+C1  x71_0 gnd 2.080806f
+C2  x71_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 x71_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 x71_1 2 2.224404
+.ends
+
+.subckt netg3264 g3264_0 g3264_1 g3264_2 gnd
+C1  g3264_0 gnd 2.080806f
+C2  g3264_1 gnd 2.080806f
+C3  g3264_2 gnd 2.080806f
+R1 g3264_2 g3264_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g3264_2 2.224404
+R3 g3264_1 1 2.224404
+.ends
+
+.subckt netg5194 g5194_2 g5194_0 g5194_1 gnd
+C1  g5194_2 gnd 2.080806f
+C2  g5194_0 gnd 2.080806f
+C3  g5194_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5194_0 1 2.224404
+R2 g5194_1 1 2.224404
+R3 g5194_2 g5194_1 2.224404
+.ends
+
+.subckt netg4154 g4154_1 g4154_2 gnd
+C1  g4154_1 gnd 2.080806f
+C2  g4154_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4154_2 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g4154_1 2 2.224404
+.ends
+
+.subckt netg6051 g6051_1 g6051_0 gnd
+C1  g6051_1 gnd 2.080806f
+C2  g6051_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6051_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g6051_1 2 2.224404
+.ends
+
+.subckt netg5954 g5954_1 g5954_0 gnd
+C1  g5954_1 gnd 2.080806f
+C2  g5954_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5954_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g5954_1 2 2.224404
+.ends
+
+.subckt netg3542 g3542_1 g3542_0 gnd
+C1  g3542_1 gnd 2.080806f
+C2  g3542_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3542_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g3542_1 2 2.224404
+.ends
+
+.subckt netg6883 g6883_1 g6883_0 gnd
+C1  g6883_1 gnd 2.080806f
+C2  g6883_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6883_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g6883_1 2.224404
+.ends
+
+.subckt netg1844 g1844_3 g1844_1 g1844_2 gnd
+C1  g1844_3 gnd 2.080806f
+C2  g1844_1 gnd 2.080806f
+C3  g1844_2 gnd 2.080806f
+R1 g1844_2 g1844_3 2.224404
+C4 1 gnd 2.080806f
+R2 g1844_3 1 2.224404
+R3 1 g1844_1 2.224404
+.ends
+
+.subckt netg4312 g4312_1 g4312_0 gnd
+C1  g4312_1 gnd 2.080806f
+C2  g4312_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4312_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g4312_1 2 2.224404
+.ends
+
+.subckt netx351 x351_0 x351_1 gnd
+C1  x351_0 gnd 2.080806f
+C2  x351_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x351_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 x351_1 2 2.224404
+.ends
+
+.subckt netg3347 g3347_1 g3347_0 gnd
+C1  g3347_1 gnd 2.080806f
+C2  g3347_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3347_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g3347_1 2.224404
+.ends
+
+.subckt netg6932 g6932_1 g6932_0 gnd
+C1  g6932_1 gnd 2.080806f
+C2  g6932_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6932_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g6932_1 2.224404
+.ends
+
+.subckt netg681 g681_1 g681_0 gnd
+C1  g681_1 gnd 2.080806f
+C2  g681_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g681_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g681_1 2.224404
+.ends
+
+.subckt netg7441 g7441_1 g7441_0 gnd
+C1  g7441_1 gnd 2.080806f
+C2  g7441_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7441_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g7441_1 2.224404
+.ends
+
+.subckt netg1283 g1283_0 g1283_1 gnd
+C1  g1283_0 gnd 2.080806f
+C2  g1283_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1283_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g1283_1 2 2.224404
+.ends
+
+.subckt netg3309 g3309_0 g3309_2 g3309_1 gnd
+C1  g3309_0 gnd 2.080806f
+C2  g3309_2 gnd 2.080806f
+C3  g3309_1 gnd 2.080806f
+R1 g3309_0 g3309_1 2.224404
+C4 1 gnd 2.080806f
+R2 g3309_0 1 2.224404
+R3 1 g3309_2 2.224404
+.ends
+
+.subckt netg7017 g7017_0 g7017_1 gnd
+C1  g7017_0 gnd 2.080806f
+C2  g7017_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7017_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g7017_1 2 2.224404
+.ends
+
+.subckt netg6637 g6637_1 g6637_0 g6637_2 gnd
+C1  g6637_1 gnd 2.080806f
+C2  g6637_0 gnd 2.080806f
+C3  g6637_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g6637_0 1 2.224404
+R2 1 g6637_1 2.224404
+R3 g6637_1 g6637_2 2.224404
+.ends
+
+.subckt netg7291 g7291_1 g7291_0 gnd
+C1  g7291_1 gnd 2.080806f
+C2  g7291_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7291_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g7291_1 2.224404
+.ends
+
+.subckt netg2374 g2374_2 g2374_0 g2374_1 gnd
+C1  g2374_2 gnd 2.080806f
+C2  g2374_0 gnd 2.080806f
+C3  g2374_1 gnd 2.080806f
+R1 g2374_1 g2374_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g2374_1 2.224404
+R3 g2374_2 1 2.224404
+.ends
+
+.subckt netg3921 g3921_1 g3921_0 gnd
+C1  g3921_1 gnd 2.080806f
+C2  g3921_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3921_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g3921_1 2 2.224404
+.ends
+
+.subckt netg1229 g1229_0 g1229_1 gnd
+C1  g1229_0 gnd 2.080806f
+C2  g1229_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1229_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g1229_1 2.224404
+.ends
+
+.subckt netx521 x521_1 x521_0 gnd
+C1  x521_1 gnd 2.080806f
+C2  x521_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 x521_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 x521_1 2.224404
+.ends
+
+.subckt netx182 x182_0 x182_1 gnd
+C1  x182_0 gnd 2.080806f
+C2  x182_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x182_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 x182_1 2.224404
+.ends
+
+.subckt netg7134 g7134_2 g7134_0 g7134_1 gnd
+C1  g7134_2 gnd 2.080806f
+C2  g7134_0 gnd 2.080806f
+C3  g7134_1 gnd 2.080806f
+R1 g7134_1 g7134_0 2.224404
+C4 1 gnd 2.080806f
+R2 g7134_0 1 2.224404
+R3 1 g7134_2 2.224404
+.ends
+
+.subckt netg6360 g6360_0 g6360_1 gnd
+C1  g6360_0 gnd 2.080806f
+C2  g6360_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6360_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g6360_1 2 2.224404
+.ends
+
+.subckt netg2638 g2638_0 g2638_2 g2638_1 gnd
+C1  g2638_0 gnd 2.080806f
+C2  g2638_2 gnd 2.080806f
+C3  g2638_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g2638_0 1 2.224404
+R2 1 g2638_1 2.224404
+R3 g2638_2 1 2.224404
+.ends
+
+.subckt netg6712 g6712_1 g6712_0 g6712_2 gnd
+C1  g6712_1 gnd 2.080806f
+C2  g6712_0 gnd 2.080806f
+C3  g6712_2 gnd 2.080806f
+R1 g6712_2 g6712_0 2.224404
+C4 1 gnd 2.080806f
+R2 g6712_0 1 2.224404
+R3 1 g6712_1 2.224404
+.ends
+
+.subckt netg1021 g1021_0 g1021_2 g1021_1 gnd
+C1  g1021_0 gnd 2.080806f
+C2  g1021_2 gnd 2.080806f
+C3  g1021_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g1021_0 2.224404
+R2 1 g1021_1 2.224404
+C5 2 gnd 2.080806f
+R3 g1021_0 2 2.224404
+R4 2 g1021_2 2.224404
+.ends
+
+.subckt netg5485 g5485_1 g5485_0 gnd
+C1  g5485_1 gnd 2.080806f
+C2  g5485_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5485_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g5485_1 2 2.224404
+.ends
+
+.subckt netg2386 g2386_1 g2386_2 g2386_0 gnd
+C1  g2386_1 gnd 2.080806f
+C2  g2386_2 gnd 2.080806f
+C3  g2386_0 gnd 2.080806f
+R1 g2386_2 g2386_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g2386_2 2.224404
+R3 g2386_1 1 2.224404
+.ends
+
+.subckt netg5413 g5413_1 g5413_0 gnd
+C1  g5413_1 gnd 2.080806f
+C2  g5413_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5413_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g5413_1 2 2.224404
+.ends
+
+.subckt netg2997 g2997_1 g2997_0 gnd
+C1  g2997_1 gnd 2.080806f
+C2  g2997_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2997_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g2997_1 2 2.224404
+.ends
+
+.subckt netg1903 g1903_0 g1903_1 gnd
+C1  g1903_0 gnd 2.080806f
+C2  g1903_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1903_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g1903_1 2 2.224404
+.ends
+
+.subckt netg2662 g2662_2 g2662_1 g2662_0 gnd
+C1  g2662_2 gnd 2.080806f
+C2  g2662_1 gnd 2.080806f
+C3  g2662_0 gnd 2.080806f
+R1 g2662_0 g2662_1 2.224404
+C4 1 gnd 2.080806f
+R2 1 g2662_0 2.224404
+R3 g2662_2 1 2.224404
+.ends
+
+.subckt netg5465 g5465_1 g5465_0 gnd
+C1  g5465_1 gnd 2.080806f
+C2  g5465_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5465_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g5465_1 2 2.224404
+.ends
+
+.subckt netg3395 g3395_0 g3395_1 g3395_2 gnd
+C1  g3395_0 gnd 2.080806f
+C2  g3395_1 gnd 2.080806f
+C3  g3395_2 gnd 2.080806f
+R1 g3395_2 g3395_0 2.224404
+C4 1 gnd 2.080806f
+R2 g3395_0 1 2.224404
+R3 1 g3395_1 2.224404
+.ends
+
+.subckt netg6557 g6557_1 g6557_0 gnd
+C1  g6557_1 gnd 2.080806f
+C2  g6557_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6557_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g6557_1 2.224404
+.ends
+
+.subckt netg2698 g2698_2 g2698_0 g2698_1 gnd
+C1  g2698_2 gnd 2.080806f
+C2  g2698_0 gnd 2.080806f
+C3  g2698_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g2698_0 2.224404
+R2 g2698_1 1 2.224404
+R3 g2698_2 g2698_1 2.224404
+.ends
+
+.subckt netg7007 g7007_1 g7007_0 gnd
+C1  g7007_1 gnd 2.080806f
+C2  g7007_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7007_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g7007_1 2.224404
+.ends
+
+.subckt netg4255 g4255_0 g4255_1 gnd
+C1  g4255_0 gnd 2.080806f
+C2  g4255_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4255_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g4255_1 2 2.224404
+.ends
+
+.subckt netg7274 g7274_0 g7274_1 gnd
+C1  g7274_0 gnd 2.080806f
+C2  g7274_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7274_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g7274_1 2 2.224404
+.ends
+
+.subckt netg2734 g2734_2 g2734_1 gnd
+C1  g2734_2 gnd 2.080806f
+C2  g2734_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2734_1 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g2734_2 2 2.224404
+.ends
+
+.subckt netg859 g859_2 g859_1 g859_0 gnd
+C1  g859_2 gnd 2.080806f
+C2  g859_1 gnd 2.080806f
+C3  g859_0 gnd 2.080806f
+R1 g859_2 g859_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g859_2 2.224404
+R3 g859_1 1 2.224404
+.ends
+
+.subckt netg1221 g1221_1 g1221_0 gnd
+C1  g1221_1 gnd 2.080806f
+C2  g1221_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1221_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g1221_1 2 2.224404
+.ends
+
+.subckt netg4105 g4105_1 g4105_0 gnd
+C1  g4105_1 gnd 2.080806f
+C2  g4105_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4105_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g4105_1 2 2.224404
+.ends
+
+.subckt netg6421 g6421_1 g6421_0 gnd
+C1  g6421_1 gnd 2.080806f
+C2  g6421_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6421_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g6421_1 2 2.224404
+.ends
+
+.subckt netg7122 g7122_0 g7122_1 gnd
+C1  g7122_0 gnd 2.080806f
+C2  g7122_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7122_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g7122_1 2 2.224404
+.ends
+
+.subckt netg4282 g4282_1 g4282_0 gnd
+C1  g4282_1 gnd 2.080806f
+C2  g4282_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4282_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g4282_1 2 2.224404
+.ends
+
+.subckt netg3052 g3052_0 g3052_1 gnd
+C1  g3052_0 gnd 2.080806f
+C2  g3052_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3052_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g3052_1 2.224404
+.ends
+
+.subckt netg3120 g3120_0 g3120_2 g3120_1 gnd
+C1  g3120_0 gnd 2.080806f
+C2  g3120_2 gnd 2.080806f
+C3  g3120_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g3120_0 2.224404
+R2 g3120_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 g3120_0 2 2.224404
+R4 g3120_2 2 2.224404
+.ends
+
+.subckt netg2495 g2495_0 g2495_1 g2495_2 gnd
+C1  g2495_0 gnd 2.080806f
+C2  g2495_1 gnd 2.080806f
+C3  g2495_2 gnd 2.080806f
+R1 g2495_1 g2495_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g2495_1 2.224404
+R3 g2495_2 1 2.224404
+.ends
+
+.subckt netg5323 g5323_0 g5323_1 gnd
+C1  g5323_0 gnd 2.080806f
+C2  g5323_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5323_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g5323_1 2.224404
+.ends
+
+.subckt netx241 x241_0 x241_1 gnd
+C1  x241_0 gnd 2.080806f
+C2  x241_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x241_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 x241_1 2.224404
+.ends
+
+.subckt netg1114 g1114_0 g1114_1 gnd
+C1  g1114_0 gnd 2.080806f
+C2  g1114_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1114_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g1114_1 2.224404
+.ends
+
+.subckt netg2630 g2630_2 g2630_0 g2630_1 gnd
+C1  g2630_2 gnd 2.080806f
+C2  g2630_0 gnd 2.080806f
+C3  g2630_1 gnd 2.080806f
+R1 g2630_1 g2630_0 2.224404
+C4 1 gnd 2.080806f
+R2 g2630_0 1 2.224404
+R3 1 g2630_2 2.224404
+.ends
+
+.subckt netx112 x112_1 x112_0 gnd
+C1  x112_1 gnd 2.080806f
+C2  x112_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x112_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 x112_1 2 2.224404
+.ends
+
+.subckt netg5719 g5719_1 g5719_2 gnd
+C1  g5719_1 gnd 2.080806f
+C2  g5719_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5719_2 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g5719_1 2.224404
+.ends
+
+.subckt netg3234 g3234_2 g3234_1 g3234_0 gnd
+C1  g3234_2 gnd 2.080806f
+C2  g3234_1 gnd 2.080806f
+C3  g3234_0 gnd 2.080806f
+R1 g3234_0 g3234_1 2.224404
+C4 1 gnd 2.080806f
+R2 g3234_1 1 2.224404
+R3 1 g3234_2 2.224404
+.ends
+
+.subckt netg5836 g5836_2 g5836_1 g5836_0 gnd
+C1  g5836_2 gnd 2.080806f
+C2  g5836_1 gnd 2.080806f
+C3  g5836_0 gnd 2.080806f
+R1 g5836_1 g5836_0 2.224404
+C4 1 gnd 2.080806f
+R2 g5836_1 1 2.224404
+R3 1 g5836_2 2.224404
+.ends
+
+.subckt netg7360 g7360_2 g7360_0 g7360_1 gnd
+C1  g7360_2 gnd 2.080806f
+C2  g7360_0 gnd 2.080806f
+C3  g7360_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g7360_0 1 2.224404
+R2 g7360_1 1 2.224404
+R3 1 g7360_2 2.224404
+.ends
+
+.subckt netg2459 g2459_2 g2459_1 g2459_0 gnd
+C1  g2459_2 gnd 2.080806f
+C2  g2459_1 gnd 2.080806f
+C3  g2459_0 gnd 2.080806f
+R1 g2459_2 g2459_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g2459_0 2.224404
+R3 g2459_1 1 2.224404
+.ends
+
+.subckt netg3352 g3352_0 g3352_2 g3352_1 gnd
+C1  g3352_0 gnd 2.080806f
+C2  g3352_2 gnd 2.080806f
+C3  g3352_1 gnd 2.080806f
+R1 g3352_0 g3352_1 2.224404
+C4 1 gnd 2.080806f
+R2 g3352_0 1 2.224404
+R3 1 g3352_2 2.224404
+.ends
+
+.subckt netg5098 g5098_2 g5098_1 g5098_0 gnd
+C1  g5098_2 gnd 2.080806f
+C2  g5098_1 gnd 2.080806f
+C3  g5098_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5098_0 2.224404
+R2 g5098_1 1 2.224404
+R3 g5098_2 g5098_1 2.224404
+.ends
+
+.subckt netg7100 g7100_0 g7100_1 gnd
+C1  g7100_0 gnd 2.080806f
+C2  g7100_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7100_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g7100_1 2 2.224404
+.ends
+
+.subckt netg5115 g5115_1 g5115_0 g5115_2 gnd
+C1  g5115_1 gnd 2.080806f
+C2  g5115_0 gnd 2.080806f
+C3  g5115_2 gnd 2.080806f
+R1 g5115_0 g5115_2 2.224404
+C4 1 gnd 2.080806f
+R2 1 g5115_2 2.224404
+R3 1 g5115_1 2.224404
+.ends
+
+.subckt netg1263 g1263_1 g1263_0 gnd
+C1  g1263_1 gnd 2.080806f
+C2  g1263_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1263_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g1263_1 2 2.224404
+.ends
+
+.subckt netx142 x142_1 x142_0 gnd
+C1  x142_1 gnd 2.080806f
+C2  x142_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 x142_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 x142_1 2 2.224404
+.ends
+
+.subckt netg3064 g3064_1 g3064_0 gnd
+C1  g3064_1 gnd 2.080806f
+C2  g3064_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3064_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g3064_1 2 2.224404
+.ends
+
+.subckt netg5062 g5062_0 g5062_1 g5062_2 gnd
+C1  g5062_0 gnd 2.080806f
+C2  g5062_1 gnd 2.080806f
+C3  g5062_2 gnd 2.080806f
+R1 g5062_0 g5062_2 2.224404
+C4 1 gnd 2.080806f
+R2 1 g5062_2 2.224404
+R3 g5062_1 1 2.224404
+.ends
+
+.subckt netg7075 g7075_1 g7075_0 gnd
+C1  g7075_1 gnd 2.080806f
+C2  g7075_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7075_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g7075_1 2.224404
+.ends
+
+.subckt netg3095 g3095_1 g3095_0 gnd
+C1  g3095_1 gnd 2.080806f
+C2  g3095_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3095_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g3095_1 2.224404
+.ends
+
+.subckt netg4419 g4419_1 g4419_0 gnd
+C1  g4419_1 gnd 2.080806f
+C2  g4419_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4419_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g4419_1 2 2.224404
+.ends
+
+.subckt netg2777 g2777_1 g2777_0 gnd
+C1  g2777_1 gnd 2.080806f
+C2  g2777_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2777_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g2777_1 2 2.224404
+.ends
+
+.subckt netg928 g928_0 g928_1 g928_2 gnd
+C1  g928_0 gnd 2.080806f
+C2  g928_1 gnd 2.080806f
+C3  g928_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g928_0 2.224404
+R2 g928_2 1 2.224404
+R3 g928_1 g928_2 2.224404
+.ends
+
+.subckt netg6811 g6811_2 g6811_0 g6811_1 gnd
+C1  g6811_2 gnd 2.080806f
+C2  g6811_0 gnd 2.080806f
+C3  g6811_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g6811_0 2.224404
+R2 g6811_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g6811_0 2.224404
+R4 g6811_2 2 2.224404
+.ends
+
+.subckt netg934 g934_0 g934_2 g934_1 gnd
+C1  g934_0 gnd 2.080806f
+C2  g934_2 gnd 2.080806f
+C3  g934_1 gnd 2.080806f
+R1 g934_1 g934_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g934_1 2.224404
+R3 g934_2 1 2.224404
+.ends
+
+.subckt netg5118 g5118_1 g5118_0 gnd
+C1  g5118_1 gnd 2.080806f
+C2  g5118_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5118_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g5118_1 2.224404
+.ends
+
+.subckt netg4164 g4164_1 g4164_0 g4164_2 gnd
+C1  g4164_1 gnd 2.080806f
+C2  g4164_0 gnd 2.080806f
+C3  g4164_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g4164_0 1 2.224404
+R2 g4164_1 1 2.224404
+R3 g4164_1 g4164_2 2.224404
+.ends
+
+.subckt netx271 x271_1 x271_0 gnd
+C1  x271_1 gnd 2.080806f
+C2  x271_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x271_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 x271_1 2 2.224404
+.ends
+
+.subckt netg5600 g5600_0 g5600_1 gnd
+C1  g5600_0 gnd 2.080806f
+C2  g5600_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5600_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g5600_1 2.224404
+.ends
+
+.subckt netg1551 g1551_1 g1551_0 gnd
+C1  g1551_1 gnd 2.080806f
+C2  g1551_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1551_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g1551_1 2 2.224404
+.ends
+
+.subckt netg2597 g2597_1 g2597_0 g2597_2 gnd
+C1  g2597_1 gnd 2.080806f
+C2  g2597_0 gnd 2.080806f
+C3  g2597_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g2597_0 1 2.224404
+R2 1 g2597_2 2.224404
+R3 g2597_2 g2597_1 2.224404
+.ends
+
+.subckt netg3084 g3084_1 g3084_0 gnd
+C1  g3084_1 gnd 2.080806f
+C2  g3084_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3084_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g3084_1 2.224404
+.ends
+
+.subckt netg5661 g5661_1 g5661_2 g5661_0 gnd
+C1  g5661_1 gnd 2.080806f
+C2  g5661_2 gnd 2.080806f
+C3  g5661_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5661_0 2.224404
+R2 g5661_1 1 2.224404
+R3 g5661_2 g5661_1 2.224404
+.ends
+
+.subckt netg2377 g2377_0 g2377_2 g2377_1 gnd
+C1  g2377_0 gnd 2.080806f
+C2  g2377_2 gnd 2.080806f
+C3  g2377_1 gnd 2.080806f
+R1 g2377_0 g2377_2 2.224404
+C4 1 gnd 2.080806f
+R2 g2377_2 1 2.224404
+R3 1 g2377_1 2.224404
+.ends
+
+.subckt netx442 x442_1 x442_0 gnd
+C1  x442_1 gnd 2.080806f
+C2  x442_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x442_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 x442_1 2.224404
+.ends
+
+.subckt netg6607 g6607_1 g6607_0 gnd
+C1  g6607_1 gnd 2.080806f
+C2  g6607_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6607_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g6607_1 2 2.224404
+.ends
+
+.subckt netg1365 g1365_0 g1365_1 gnd
+C1  g1365_0 gnd 2.080806f
+C2  g1365_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1365_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g1365_1 2 2.224404
+.ends
+
+.subckt netg2725 g2725_0 g2725_1 g2725_2 gnd
+C1  g2725_0 gnd 2.080806f
+C2  g2725_1 gnd 2.080806f
+C3  g2725_2 gnd 2.080806f
+R1 g2725_1 g2725_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g2725_1 2.224404
+R3 g2725_2 1 2.224404
+.ends
+
+.subckt netg5728 g5728_1 g5728_2 g5728_0 gnd
+C1  g5728_1 gnd 2.080806f
+C2  g5728_2 gnd 2.080806f
+C3  g5728_0 gnd 2.080806f
+R1 g5728_0 g5728_2 2.224404
+C4 1 gnd 2.080806f
+R2 1 g5728_2 2.224404
+R3 g5728_1 1 2.224404
+.ends
+
+.subckt netg5616 g5616_1 g5616_0 g5616_2 gnd
+C1  g5616_1 gnd 2.080806f
+C2  g5616_0 gnd 2.080806f
+C3  g5616_2 gnd 2.080806f
+R1 g5616_0 g5616_1 2.224404
+C4 1 gnd 2.080806f
+R2 g5616_1 1 2.224404
+R3 1 g5616_2 2.224404
+.ends
+
+.subckt netg7018 g7018_1 g7018_0 gnd
+C1  g7018_1 gnd 2.080806f
+C2  g7018_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7018_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g7018_1 2 2.224404
+.ends
+
+.subckt netg7370 g7370_1 g7370_0 gnd
+C1  g7370_1 gnd 2.080806f
+C2  g7370_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7370_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g7370_1 2.224404
+.ends
+
+.subckt netg3279 g3279_1 g3279_2 gnd
+C1  g3279_1 gnd 2.080806f
+C2  g3279_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3279_2 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 2 g3279_1 2.224404
+.ends
+
+.subckt netg6523 g6523_1 g6523_0 gnd
+C1  g6523_1 gnd 2.080806f
+C2  g6523_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6523_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g6523_1 2.224404
+.ends
+
+.subckt netg3342 g3342_1 g3342_2 g3342_0 gnd
+C1  g3342_1 gnd 2.080806f
+C2  g3342_2 gnd 2.080806f
+C3  g3342_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g3342_0 1 2.224404
+R2 1 g3342_1 2.224404
+R3 g3342_2 g3342_1 2.224404
+.ends
+
+.subckt netg6445 g6445_0 g6445_1 gnd
+C1  g6445_0 gnd 2.080806f
+C2  g6445_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6445_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g6445_1 2 2.224404
+.ends
+
+.subckt netg7184 g7184_0 g7184_1 gnd
+C1  g7184_0 gnd 2.080806f
+C2  g7184_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7184_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g7184_1 2.224404
+.ends
+
+.subckt netg6063 g6063_1 g6063_0 gnd
+C1  g6063_1 gnd 2.080806f
+C2  g6063_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6063_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g6063_1 2.224404
+.ends
+
+.subckt netg5664 g5664_0 g5664_2 g5664_1 gnd
+C1  g5664_0 gnd 2.080806f
+C2  g5664_2 gnd 2.080806f
+C3  g5664_1 gnd 2.080806f
+R1 g5664_0 g5664_1 2.224404
+C4 1 gnd 2.080806f
+R2 1 g5664_1 2.224404
+R3 g5664_2 1 2.224404
+.ends
+
+.subckt netg3273 g3273_1 g3273_0 g3273_2 gnd
+C1  g3273_1 gnd 2.080806f
+C2  g3273_0 gnd 2.080806f
+C3  g3273_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g3273_0 2.224404
+R2 g3273_2 1 2.224404
+R3 g3273_2 g3273_1 2.224404
+.ends
+
+.subckt netg3246 g3246_0 g3246_2 g3246_1 gnd
+C1  g3246_0 gnd 2.080806f
+C2  g3246_2 gnd 2.080806f
+C3  g3246_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g3246_0 1 2.224404
+R2 g3246_1 1 2.224404
+R3 1 g3246_2 2.224404
+.ends
+
+.subckt netx111 x111_1 x111_0 gnd
+C1  x111_1 gnd 2.080806f
+C2  x111_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x111_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 x111_1 2 2.224404
+.ends
+
+.subckt netx551 x551_0 x551_1 gnd
+C1  x551_0 gnd 2.080806f
+C2  x551_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x551_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 x551_1 2 2.224404
+.ends
+
+.subckt netg5351 g5351_1 g5351_0 gnd
+C1  g5351_1 gnd 2.080806f
+C2  g5351_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5351_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g5351_1 2 2.224404
+.ends
+
+.subckt netg5588 g5588_1 g5588_0 gnd
+C1  g5588_1 gnd 2.080806f
+C2  g5588_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5588_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g5588_1 2 2.224404
+.ends
+
+.subckt netg4130 g4130_1 g4130_0 gnd
+C1  g4130_1 gnd 2.080806f
+C2  g4130_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4130_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g4130_1 2 2.224404
+.ends
+
+.subckt netg2603 g2603_1 g2603_2 g2603_0 gnd
+C1  g2603_1 gnd 2.080806f
+C2  g2603_2 gnd 2.080806f
+C3  g2603_0 gnd 2.080806f
+R1 g2603_1 g2603_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g2603_0 2.224404
+R3 g2603_2 1 2.224404
+.ends
+
+.subckt netg1517 g1517_1 g1517_0 gnd
+C1  g1517_1 gnd 2.080806f
+C2  g1517_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1517_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g1517_1 2 2.224404
+.ends
+
+.subckt netg3267 g3267_0 g3267_1 g3267_2 gnd
+C1  g3267_0 gnd 2.080806f
+C2  g3267_1 gnd 2.080806f
+C3  g3267_2 gnd 2.080806f
+R1 g3267_1 g3267_0 2.224404
+C4 1 gnd 2.080806f
+R2 g3267_0 1 2.224404
+R3 g3267_2 1 2.224404
+.ends
+
+.subckt netg4012 g4012_0 g4012_1 gnd
+C1  g4012_0 gnd 2.080806f
+C2  g4012_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4012_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g4012_1 2.224404
+.ends
+
+.subckt netg6556 g6556_0 g6556_1 gnd
+C1  g6556_0 gnd 2.080806f
+C2  g6556_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6556_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g6556_1 2.224404
+.ends
+
+.subckt netg3162 g3162_0 g3162_1 g3162_2 gnd
+C1  g3162_0 gnd 2.080806f
+C2  g3162_1 gnd 2.080806f
+C3  g3162_2 gnd 2.080806f
+R1 g3162_0 g3162_2 2.224404
+C4 1 gnd 2.080806f
+R2 g3162_2 1 2.224404
+R3 1 g3162_1 2.224404
+.ends
+
+.subckt netg4271 g4271_1 g4271_0 gnd
+C1  g4271_1 gnd 2.080806f
+C2  g4271_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4271_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g4271_1 2 2.224404
+.ends
+
+.subckt netg3709 g3709_0 g3709_3 g3709_2 g3709_1 gnd
+C1  g3709_0 gnd 2.080806f
+C2  g3709_3 gnd 2.080806f
+C3  g3709_2 gnd 2.080806f
+C4  g3709_1 gnd 2.080806f
+R1 g3709_2 g3709_0 2.224404
+R2 g3709_2 g3709_1 2.224404
+C5 1 gnd 2.080806f
+R3 g3709_0 1 2.224404
+R4 1 g3709_3 2.224404
+.ends
+
+.subckt netg6562 g6562_0 g6562_1 gnd
+C1  g6562_0 gnd 2.080806f
+C2  g6562_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6562_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g6562_1 2 2.224404
+.ends
+
+.subckt netg1927 g1927_0 g1927_1 gnd
+C1  g1927_0 gnd 2.080806f
+C2  g1927_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1927_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g1927_1 2 2.224404
+.ends
+
+.subckt netg5852 g5852_2 g5852_0 g5852_1 gnd
+C1  g5852_2 gnd 2.080806f
+C2  g5852_0 gnd 2.080806f
+C3  g5852_1 gnd 2.080806f
+R1 g5852_0 g5852_1 2.224404
+C4 1 gnd 2.080806f
+R2 g5852_1 1 2.224404
+R3 1 g5852_2 2.224404
+.ends
+
+.subckt netg6802 g6802_1 g6802_0 g6802_2 gnd
+C1  g6802_1 gnd 2.080806f
+C2  g6802_0 gnd 2.080806f
+C3  g6802_2 gnd 2.080806f
+R1 g6802_0 g6802_1 2.224404
+C4 1 gnd 2.080806f
+R2 g6802_1 1 2.224404
+R3 1 g6802_2 2.224404
+.ends
+
+.subckt netg5226 g5226_0 g5226_2 g5226_1 gnd
+C1  g5226_0 gnd 2.080806f
+C2  g5226_2 gnd 2.080806f
+C3  g5226_1 gnd 2.080806f
+R1 g5226_0 g5226_2 2.224404
+C4 1 gnd 2.080806f
+R2 g5226_2 1 2.224404
+R3 g5226_1 1 2.224404
+.ends
+
+.subckt netg6951 g6951_1 g6951_0 g6951_2 gnd
+C1  g6951_1 gnd 2.080806f
+C2  g6951_0 gnd 2.080806f
+C3  g6951_2 gnd 2.080806f
+R1 g6951_0 g6951_2 2.224404
+C4 1 gnd 2.080806f
+R2 g6951_2 1 2.224404
+R3 1 g6951_1 2.224404
+.ends
+
+.subckt netg904 g904_2 g904_1 g904_0 gnd
+C1  g904_2 gnd 2.080806f
+C2  g904_1 gnd 2.080806f
+C3  g904_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g904_0 1 2.224404
+R2 1 g904_2 2.224404
+R3 g904_2 g904_1 2.224404
+.ends
+
+.subckt netg1995 g1995_2 g1995_0 g1995_1 gnd
+C1  g1995_2 gnd 2.080806f
+C2  g1995_0 gnd 2.080806f
+C3  g1995_1 gnd 2.080806f
+R1 g1995_0 g1995_1 2.224404
+C4 1 gnd 2.080806f
+R2 1 g1995_0 2.224404
+R3 g1995_2 1 2.224404
+.ends
+
+.subckt netg5068 g5068_1 g5068_0 g5068_2 gnd
+C1  g5068_1 gnd 2.080806f
+C2  g5068_0 gnd 2.080806f
+C3  g5068_2 gnd 2.080806f
+R1 g5068_2 g5068_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g5068_0 2.224404
+R3 1 g5068_1 2.224404
+.ends
+
+.subckt netg5549 g5549_2 g5549_1 g5549_0 gnd
+C1  g5549_2 gnd 2.080806f
+C2  g5549_1 gnd 2.080806f
+C3  g5549_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5549_0 1 2.224404
+R2 1 g5549_1 2.224404
+R3 g5549_2 g5549_1 2.224404
+.ends
+
+.subckt netg5243 g5243_0 g5243_1 gnd
+C1  g5243_0 gnd 2.080806f
+C2  g5243_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5243_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g5243_1 2.224404
+.ends
+
+.subckt netg3090 g3090_2 g3090_1 g3090_0 gnd
+C1  g3090_2 gnd 2.080806f
+C2  g3090_1 gnd 2.080806f
+C3  g3090_0 gnd 2.080806f
+R1 g3090_0 g3090_1 2.224404
+C4 1 gnd 2.080806f
+R2 1 g3090_0 2.224404
+R3 g3090_2 1 2.224404
+.ends
+
+.subckt netg6745 g6745_2 g6745_0 g6745_1 gnd
+C1  g6745_2 gnd 2.080806f
+C2  g6745_0 gnd 2.080806f
+C3  g6745_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g6745_0 1 2.224404
+R2 1 g6745_2 2.224404
+R3 g6745_2 g6745_1 2.224404
+.ends
+
+.subckt netg6086 g6086_1 g6086_0 gnd
+C1  g6086_1 gnd 2.080806f
+C2  g6086_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6086_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g6086_1 2.224404
+.ends
+
+.subckt netg5474 g5474_1 g5474_0 gnd
+C1  g5474_1 gnd 2.080806f
+C2  g5474_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5474_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 2 g5474_1 2.224404
+.ends
+
+.subckt netg901 g901_2 g901_0 g901_1 gnd
+C1  g901_2 gnd 2.080806f
+C2  g901_0 gnd 2.080806f
+C3  g901_1 gnd 2.080806f
+R1 g901_1 g901_0 2.224404
+C4 1 gnd 2.080806f
+R2 g901_1 1 2.224404
+R3 1 g901_2 2.224404
+.ends
+
+.subckt netg3171 g3171_2 g3171_0 g3171_1 gnd
+C1  g3171_2 gnd 2.080806f
+C2  g3171_0 gnd 2.080806f
+C3  g3171_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g3171_0 1 2.224404
+R2 1 g3171_1 2.224404
+R3 g3171_1 g3171_2 2.224404
+.ends
+
+.subckt netg5385 g5385_0 g5385_1 gnd
+C1  g5385_0 gnd 2.080806f
+C2  g5385_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5385_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g5385_1 2.224404
+.ends
+
+.subckt netg1012 g1012_0 g1012_2 g1012_1 gnd
+C1  g1012_0 gnd 2.080806f
+C2  g1012_2 gnd 2.080806f
+C3  g1012_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g1012_0 1 2.224404
+R2 1 g1012_2 2.224404
+R3 g1012_1 g1012_2 2.224404
+.ends
+
+.subckt netg982 g982_2 g982_1 g982_0 gnd
+C1  g982_2 gnd 2.080806f
+C2  g982_1 gnd 2.080806f
+C3  g982_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g982_0 1 2.224404
+R2 g982_2 1 2.224404
+R3 g982_1 g982_2 2.224404
+.ends
+
+.subckt netg1079 g1079_0 g1079_2 g1079_1 gnd
+C1  g1079_0 gnd 2.080806f
+C2  g1079_2 gnd 2.080806f
+C3  g1079_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g1079_0 2.224404
+R2 g1079_2 1 2.224404
+R3 g1079_1 g1079_2 2.224404
+.ends
+
+.subckt netg3126 g3126_0 g3126_1 g3126_2 gnd
+C1  g3126_0 gnd 2.080806f
+C2  g3126_1 gnd 2.080806f
+C3  g3126_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g3126_0 1 2.224404
+R2 1 g3126_2 2.224404
+R3 g3126_2 g3126_1 2.224404
+.ends
+
+.subckt netg6080 g6080_0 g6080_1 gnd
+C1  g6080_0 gnd 2.080806f
+C2  g6080_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6080_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g6080_1 2 2.224404
+.ends
+
+.subckt netg5139 g5139_2 g5139_1 g5139_0 gnd
+C1  g5139_2 gnd 2.080806f
+C2  g5139_1 gnd 2.080806f
+C3  g5139_0 gnd 2.080806f
+R1 g5139_1 g5139_0 2.224404
+C4 1 gnd 2.080806f
+R2 g5139_0 1 2.224404
+R3 1 g5139_2 2.224404
+.ends
+
+.subckt netg5486 g5486_1 g5486_0 gnd
+C1  g5486_1 gnd 2.080806f
+C2  g5486_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5486_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g5486_1 2 2.224404
+.ends
+
+.subckt netg7301 g7301_1 g7301_0 gnd
+C1  g7301_1 gnd 2.080806f
+C2  g7301_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7301_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g7301_1 2 2.224404
+.ends
+
+.subckt netg4167 g4167_0 g4167_2 g4167_1 gnd
+C1  g4167_0 gnd 2.080806f
+C2  g4167_2 gnd 2.080806f
+C3  g4167_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g4167_0 1 2.224404
+R2 1 g4167_2 2.224404
+R3 g4167_2 g4167_1 2.224404
+.ends
+
+.subckt netg1310 g1310_1 g1310_0 gnd
+C1  g1310_1 gnd 2.080806f
+C2  g1310_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1310_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 2 g1310_1 2.224404
+.ends
+
+.subckt netg7174 g7174_1 g7174_0 gnd
+C1  g7174_1 gnd 2.080806f
+C2  g7174_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7174_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g7174_1 2 2.224404
+.ends
+
+.subckt netg5694 g5694_1 g5694_2 g5694_0 gnd
+C1  g5694_1 gnd 2.080806f
+C2  g5694_2 gnd 2.080806f
+C3  g5694_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5694_0 1 2.224404
+R2 1 g5694_1 2.224404
+R3 g5694_2 g5694_1 2.224404
+.ends
+
+.subckt netg3249 g3249_1 g3249_0 g3249_2 gnd
+C1  g3249_1 gnd 2.080806f
+C2  g3249_0 gnd 2.080806f
+C3  g3249_2 gnd 2.080806f
+R1 g3249_1 g3249_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g3249_1 2.224404
+R3 g3249_2 1 2.224404
+.ends
+
+.subckt netg5697 g5697_0 g5697_1 g5697_2 gnd
+C1  g5697_0 gnd 2.080806f
+C2  g5697_1 gnd 2.080806f
+C3  g5697_2 gnd 2.080806f
+R1 g5697_0 g5697_1 2.224404
+C4 1 gnd 2.080806f
+R2 1 g5697_0 2.224404
+R3 g5697_2 1 2.224404
+.ends
+
+.subckt netg943 g943_0 g943_2 g943_1 gnd
+C1  g943_0 gnd 2.080806f
+C2  g943_2 gnd 2.080806f
+C3  g943_1 gnd 2.080806f
+R1 g943_0 g943_1 2.224404
+C4 1 gnd 2.080806f
+R2 1 g943_0 2.224404
+R3 g943_2 1 2.224404
+.ends
+
+.subckt netg6898 g6898_0 g6898_1 gnd
+C1  g6898_0 gnd 2.080806f
+C2  g6898_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6898_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g6898_1 2 2.224404
+.ends
+
+.subckt netg6109 g6109_1 g6109_2 gnd
+C1  g6109_1 gnd 2.080806f
+C2  g6109_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6109_1 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g6109_2 2 2.224404
+.ends
+
+.subckt netx552 x552_0 x552_1 gnd
+C1  x552_0 gnd 2.080806f
+C2  x552_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x552_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 x552_1 2.224404
+.ends
+
+.subckt netg3507 g3507_0 g3507_1 gnd
+C1  g3507_0 gnd 2.080806f
+C2  g3507_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3507_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g3507_1 2.224404
+.ends
+
+.subckt netg6389 g6389_0 g6389_1 gnd
+C1  g6389_0 gnd 2.080806f
+C2  g6389_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6389_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 2 g6389_1 2.224404
+.ends
+
+.subckt netg1574 g1574_0 g1574_1 gnd
+C1  g1574_0 gnd 2.080806f
+C2  g1574_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1574_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g1574_1 2.224404
+.ends
+
+.subckt netg5332 g5332_1 g5332_0 gnd
+C1  g5332_1 gnd 2.080806f
+C2  g5332_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5332_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g5332_1 2 2.224404
+.ends
+
+.subckt netg3536 g3536_1 g3536_0 gnd
+C1  g3536_1 gnd 2.080806f
+C2  g3536_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3536_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g3536_1 2.224404
+.ends
+
+.subckt netg2564 g2564_2 g2564_1 gnd
+C1  g2564_2 gnd 2.080806f
+C2  g2564_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2564_1 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g2564_2 2.224404
+.ends
+
+.subckt netg4374 g4374_0 g4374_1 g4374_2 gnd
+C1  g4374_0 gnd 2.080806f
+C2  g4374_1 gnd 2.080806f
+C3  g4374_2 gnd 2.080806f
+R1 g4374_1 g4374_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g4374_0 2.224404
+R3 1 g4374_2 2.224404
+.ends
+
+.subckt netg7109 g7109_2 g7109_1 g7109_0 gnd
+C1  g7109_2 gnd 2.080806f
+C2  g7109_1 gnd 2.080806f
+C3  g7109_0 gnd 2.080806f
+R1 g7109_2 g7109_0 2.224404
+C4 1 gnd 2.080806f
+R2 g7109_0 1 2.224404
+R3 1 g7109_1 2.224404
+.ends
+
+.subckt netg4421 g4421_1 g4421_0 gnd
+C1  g4421_1 gnd 2.080806f
+C2  g4421_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4421_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 2 g4421_1 2.224404
+.ends
+
+.subckt netg2415 g2415_2 g2415_1 g2415_0 gnd
+C1  g2415_2 gnd 2.080806f
+C2  g2415_1 gnd 2.080806f
+C3  g2415_0 gnd 2.080806f
+R1 g2415_0 g2415_2 2.224404
+C4 1 gnd 2.080806f
+R2 g2415_0 1 2.224404
+R3 g2415_1 1 2.224404
+.ends
+
+.subckt netg5041 g5041_0 g5041_1 g5041_2 gnd
+C1  g5041_0 gnd 2.080806f
+C2  g5041_1 gnd 2.080806f
+C3  g5041_2 gnd 2.080806f
+R1 g5041_2 g5041_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g5041_0 2.224404
+R3 g5041_1 1 2.224404
+.ends
+
+.subckt netg2570 g2570_1 g2570_2 g2570_0 gnd
+C1  g2570_1 gnd 2.080806f
+C2  g2570_2 gnd 2.080806f
+C3  g2570_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g2570_0 1 2.224404
+R2 1 g2570_1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g2570_0 2.224404
+R4 2 g2570_2 2.224404
+.ends
+
+.subckt netg5867 g5867_2 g5867_0 g5867_1 gnd
+C1  g5867_2 gnd 2.080806f
+C2  g5867_0 gnd 2.080806f
+C3  g5867_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5867_0 1 2.224404
+R2 1 g5867_1 2.224404
+R3 g5867_1 g5867_2 2.224404
+.ends
+
+.subckt netg6879 g6879_1 g6879_0 gnd
+C1  g6879_1 gnd 2.080806f
+C2  g6879_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6879_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g6879_1 2 2.224404
+.ends
+
+.subckt netg6876 g6876_0 g6876_1 gnd
+C1  g6876_0 gnd 2.080806f
+C2  g6876_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6876_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 2 g6876_1 2.224404
+.ends
+
+.subckt netg5725 g5725_1 g5725_0 g5725_2 gnd
+C1  g5725_1 gnd 2.080806f
+C2  g5725_0 gnd 2.080806f
+C3  g5725_2 gnd 2.080806f
+R1 g5725_0 g5725_1 2.224404
+C4 1 gnd 2.080806f
+R2 1 g5725_0 2.224404
+R3 g5725_2 1 2.224404
+.ends
+
+.subckt netg1942 g1942_0 g1942_1 g1942_2 gnd
+C1  g1942_0 gnd 2.080806f
+C2  g1942_1 gnd 2.080806f
+C3  g1942_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g1942_0 2.224404
+R2 g1942_1 1 2.224404
+R3 g1942_2 1 2.224404
+.ends
+
+.subckt netg3183 g3183_0 g3183_1 g3183_2 gnd
+C1  g3183_0 gnd 2.080806f
+C2  g3183_1 gnd 2.080806f
+C3  g3183_2 gnd 2.080806f
+R1 g3183_0 g3183_2 2.224404
+C4 1 gnd 2.080806f
+R2 g3183_2 1 2.224404
+R3 1 g3183_1 2.224404
+.ends
+
+.subckt netg4263 g4263_1 g4263_0 gnd
+C1  g4263_1 gnd 2.080806f
+C2  g4263_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4263_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g4263_1 2.224404
+.ends
+
+.subckt netg7425 g7425_0 g7425_1 gnd
+C1  g7425_0 gnd 2.080806f
+C2  g7425_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7425_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g7425_1 2 2.224404
+.ends
+
+.subckt netg1508 g1508_0 g1508_1 gnd
+C1  g1508_0 gnd 2.080806f
+C2  g1508_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1508_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g1508_1 2 2.224404
+.ends
+
+.subckt netg1558 g1558_0 g1558_1 gnd
+C1  g1558_0 gnd 2.080806f
+C2  g1558_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1558_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g1558_1 2.224404
+.ends
+
+.subckt netg5434 g5434_2 g5434_0 g5434_1 gnd
+C1  g5434_2 gnd 2.080806f
+C2  g5434_0 gnd 2.080806f
+C3  g5434_1 gnd 2.080806f
+R1 g5434_0 g5434_1 2.224404
+C4 1 gnd 2.080806f
+R2 g5434_1 1 2.224404
+R3 1 g5434_2 2.224404
+.ends
+
+.subckt netg7203 g7203_2 g7203_1 g7203_0 gnd
+C1  g7203_2 gnd 2.080806f
+C2  g7203_1 gnd 2.080806f
+C3  g7203_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g7203_0 2.224404
+R2 g7203_2 1 2.224404
+R3 g7203_1 g7203_2 2.224404
+.ends
+
+.subckt netg7341 g7341_1 g7341_0 gnd
+C1  g7341_1 gnd 2.080806f
+C2  g7341_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7341_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g7341_1 2.224404
+.ends
+
+.subckt netg2804 g2804_0 g2804_1 gnd
+C1  g2804_0 gnd 2.080806f
+C2  g2804_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2804_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g2804_1 2 2.224404
+.ends
+
+.subckt netg7119 g7119_1 g7119_0 g7119_2 gnd
+C1  g7119_1 gnd 2.080806f
+C2  g7119_0 gnd 2.080806f
+C3  g7119_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g7119_0 2.224404
+R2 g7119_2 1 2.224404
+R3 g7119_2 g7119_1 2.224404
+.ends
+
+.subckt netg4349 g4349_1 g4349_0 gnd
+C1  g4349_1 gnd 2.080806f
+C2  g4349_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4349_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g4349_1 2.224404
+.ends
+
+.subckt netg4260 g4260_0 g4260_1 gnd
+C1  g4260_0 gnd 2.080806f
+C2  g4260_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4260_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g4260_1 2 2.224404
+.ends
+
+.subckt netg6528 g6528_1 g6528_0 gnd
+C1  g6528_1 gnd 2.080806f
+C2  g6528_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6528_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 2 g6528_1 2.224404
+.ends
+
+.subckt netg7264 g7264_1 g7264_0 gnd
+C1  g7264_1 gnd 2.080806f
+C2  g7264_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7264_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g7264_1 2 2.224404
+.ends
+
+.subckt netg6905 g6905_3 g6905_2 gnd
+C1  g6905_3 gnd 2.080806f
+C2  g6905_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6905_2 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g6905_3 2.224404
+.ends
+
+.subckt netg7084 g7084_1 g7084_0 gnd
+C1  g7084_1 gnd 2.080806f
+C2  g7084_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7084_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g7084_1 2 2.224404
+.ends
+
+.subckt netg4973 g4973_0 g4973_2 g4973_1 gnd
+C1  g4973_0 gnd 2.080806f
+C2  g4973_2 gnd 2.080806f
+C3  g4973_1 gnd 2.080806f
+R1 g4973_1 g4973_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g4973_0 2.224404
+R3 g4973_2 1 2.224404
+.ends
+
+.subckt netg2656 g2656_1 g2656_0 g2656_2 gnd
+C1  g2656_1 gnd 2.080806f
+C2  g2656_0 gnd 2.080806f
+C3  g2656_2 gnd 2.080806f
+R1 g2656_2 g2656_0 2.224404
+C4 1 gnd 2.080806f
+R2 g2656_2 1 2.224404
+R3 g2656_1 1 2.224404
+.ends
+
+.subckt netg6054 g6054_1 g6054_0 gnd
+C1  g6054_1 gnd 2.080806f
+C2  g6054_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6054_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g6054_1 2.224404
+.ends
+
+.subckt netg5945 g5945_2 g5945_1 g5945_0 gnd
+C1  g5945_2 gnd 2.080806f
+C2  g5945_1 gnd 2.080806f
+C3  g5945_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5945_0 1 2.224404
+R2 1 g5945_2 2.224404
+R3 g5945_2 g5945_1 2.224404
+.ends
+
+.subckt netg7207 g7207_1 g7207_0 gnd
+C1  g7207_1 gnd 2.080806f
+C2  g7207_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7207_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g7207_1 2.224404
+.ends
+
+.subckt netg3899 g3899_0 g3899_1 gnd
+C1  g3899_0 gnd 2.080806f
+C2  g3899_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3899_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g3899_1 2.224404
+.ends
+
+.subckt netg889 g889_2 g889_1 g889_0 gnd
+C1  g889_2 gnd 2.080806f
+C2  g889_1 gnd 2.080806f
+C3  g889_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g889_0 2.224404
+R2 g889_1 1 2.224404
+R3 g889_2 g889_1 2.224404
+.ends
+
+.subckt netg5989 g5989_0 g5989_1 gnd
+C1  g5989_0 gnd 2.080806f
+C2  g5989_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5989_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g5989_1 2.224404
+.ends
+
+.subckt netg2924 g2924_1 g2924_0 gnd
+C1  g2924_1 gnd 2.080806f
+C2  g2924_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2924_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g2924_1 2.224404
+.ends
+
+.subckt netg7176 g7176_1 g7176_0 gnd
+C1  g7176_1 gnd 2.080806f
+C2  g7176_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7176_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g7176_1 2 2.224404
+.ends
+
+.subckt netg7200 g7200_2 g7200_1 g7200_0 gnd
+C1  g7200_2 gnd 2.080806f
+C2  g7200_1 gnd 2.080806f
+C3  g7200_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g7200_0 1 2.224404
+R2 1 g7200_1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g7200_0 2.224404
+R4 g7200_2 2 2.224404
+.ends
+
+.subckt netg1159 g1159_0 g1159_1 gnd
+C1  g1159_0 gnd 2.080806f
+C2  g1159_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1159_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g1159_1 2.224404
+.ends
+
+.subckt netg1121 g1121_0 g1121_1 gnd
+C1  g1121_0 gnd 2.080806f
+C2  g1121_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1121_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g1121_1 3 2.224404
+.ends
+
+.subckt netg5012 g5012_0 g5012_1 g5012_2 gnd
+C1  g5012_0 gnd 2.080806f
+C2  g5012_1 gnd 2.080806f
+C3  g5012_2 gnd 2.080806f
+R1 g5012_0 g5012_2 2.224404
+C4 1 gnd 2.080806f
+R2 g5012_2 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+R4 2 g5012_1 2.224404
+.ends
+
+.subckt netg4896 g4896_2 g4896_1 g4896_0 gnd
+C1  g4896_2 gnd 2.080806f
+C2  g4896_1 gnd 2.080806f
+C3  g4896_0 gnd 2.080806f
+R1 g4896_0 g4896_2 2.224404
+C4 1 gnd 2.080806f
+R2 1 g4896_2 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+R4 g4896_1 2 2.224404
+.ends
+
+.subckt netg2832 g2832_1 g2832_0 gnd
+C1  g2832_1 gnd 2.080806f
+C2  g2832_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2832_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g2832_1 2.224404
+.ends
+
+.subckt netg976 g976_2 g976_0 g976_1 gnd
+C1  g976_2 gnd 2.080806f
+C2  g976_0 gnd 2.080806f
+C3  g976_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g976_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g976_1 2 2.224404
+R4 g976_2 g976_1 2.224404
+.ends
+
+.subckt netg2866 g2866_0 g2866_1 gnd
+C1  g2866_0 gnd 2.080806f
+C2  g2866_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2866_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 3 g2866_1 2.224404
+.ends
+
+.subckt netg2027 g2027_1 g2027_0 gnd
+C1  g2027_1 gnd 2.080806f
+C2  g2027_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2027_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g2027_1 3 2.224404
+.ends
+
+.subckt netg7197 g7197_0 g7197_1 gnd
+C1  g7197_0 gnd 2.080806f
+C2  g7197_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7197_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g7197_1 3 2.224404
+.ends
+
+.subckt netg2942 g2942_0 g2942_1 gnd
+C1  g2942_0 gnd 2.080806f
+C2  g2942_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2942_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g2942_1 2.224404
+.ends
+
+.subckt netx341 x341_1 x341_0 gnd
+C1  x341_1 gnd 2.080806f
+C2  x341_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x341_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 x341_1 3 2.224404
+.ends
+
+.subckt netg6384 g6384_0 g6384_1 gnd
+C1  g6384_0 gnd 2.080806f
+C2  g6384_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6384_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g6384_1 3 2.224404
+.ends
+
+.subckt netg7309 g7309_1 g7309_0 g7309_2 gnd
+C1  g7309_1 gnd 2.080806f
+C2  g7309_0 gnd 2.080806f
+C3  g7309_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g7309_0 2.224404
+R2 g7309_2 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g7309_2 2.224404
+R4 g7309_1 2 2.224404
+.ends
+
+.subckt netg3560 g3560_1 g3560_0 gnd
+C1  g3560_1 gnd 2.080806f
+C2  g3560_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3560_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 g3560_1 3 2.224404
+.ends
+
+.subckt netg1511 g1511_1 g1511_0 gnd
+C1  g1511_1 gnd 2.080806f
+C2  g1511_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1511_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g1511_1 3 2.224404
+.ends
+
+.subckt netg7327 g7327_2 g7327_0 g7327_1 gnd
+C1  g7327_2 gnd 2.080806f
+C2  g7327_0 gnd 2.080806f
+C3  g7327_1 gnd 2.080806f
+R1 g7327_0 g7327_2 2.224404
+C4 1 gnd 2.080806f
+R2 g7327_2 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+R4 2 g7327_1 2.224404
+.ends
+
+.subckt netg4346 g4346_0 g4346_1 g4346_2 gnd
+C1  g4346_0 gnd 2.080806f
+C2  g4346_1 gnd 2.080806f
+C3  g4346_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g4346_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g4346_2 2.224404
+R4 g4346_2 g4346_1 2.224404
+.ends
+
+.subckt netg6299 g6299_0 g6299_1 gnd
+C1  g6299_0 gnd 2.080806f
+C2  g6299_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6299_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g6299_1 2.224404
+.ends
+
+.subckt netg5529 g5529_2 g5529_0 g5529_1 gnd
+C1  g5529_2 gnd 2.080806f
+C2  g5529_0 gnd 2.080806f
+C3  g5529_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5529_0 2.224404
+R2 g5529_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 g5529_1 2 2.224404
+R4 2 g5529_2 2.224404
+.ends
+
+.subckt netg3100 g3100_0 g3100_1 gnd
+C1  g3100_0 gnd 2.080806f
+C2  g3100_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3100_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 g3100_1 3 2.224404
+.ends
+
+.subckt netg6223 g6223_0 g6223_2 g6223_1 gnd
+C1  g6223_0 gnd 2.080806f
+C2  g6223_2 gnd 2.080806f
+C3  g6223_1 gnd 2.080806f
+R1 g6223_0 g6223_1 2.224404
+C4 1 gnd 2.080806f
+R2 1 g6223_1 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+R4 g6223_2 2 2.224404
+.ends
+
+.subckt netg6247 g6247_1 g6247_2 g6247_0 gnd
+C1  g6247_1 gnd 2.080806f
+C2  g6247_2 gnd 2.080806f
+C3  g6247_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g6247_0 2.224404
+R2 g6247_2 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g6247_2 2.224404
+R4 g6247_1 2 2.224404
+.ends
+
+.subckt netg3389 g3389_2 g3389_1 g3389_0 gnd
+C1  g3389_2 gnd 2.080806f
+C2  g3389_1 gnd 2.080806f
+C3  g3389_0 gnd 2.080806f
+R1 g3389_2 g3389_0 2.224404
+C4 1 gnd 2.080806f
+R2 g3389_2 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+R4 2 g3389_1 2.224404
+.ends
+
+.subckt netg7009 g7009_1 g7009_0 gnd
+C1  g7009_1 gnd 2.080806f
+C2  g7009_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7009_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g7009_1 3 2.224404
+.ends
+
+.subckt netg4259 g4259_1 g4259_0 gnd
+C1  g4259_1 gnd 2.080806f
+C2  g4259_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4259_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 3 g4259_1 2.224404
+.ends
+
+.subckt netx451 x451_0 x451_1 gnd
+C1  x451_0 gnd 2.080806f
+C2  x451_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x451_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 x451_1 3 2.224404
+.ends
+
+.subckt netg1085 g1085_0 g1085_1 gnd
+C1  g1085_0 gnd 2.080806f
+C2  g1085_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1085_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g1085_1 2.224404
+.ends
+
+.subckt netg705 g705_4 g705_6 g705_3 g705_2 g705_0 gnd
+C1  g705_4 gnd 2.080806f
+C2  g705_6 gnd 2.080806f
+C3  g705_3 gnd 2.080806f
+C4  g705_2 gnd 2.080806f
+C5  g705_0 gnd 2.080806f
+R1 g705_0 g705_3 2.224404
+R2 g705_4 g705_0 2.224404
+R3 g705_6 g705_4 2.224404
+R4 g705_2 g705_6 2.224404
+.ends
+
+.subckt netg2013 g2013_4 g2013_5 g2013_2 g2013_1 g2013_3 gnd
+C1  g2013_4 gnd 2.080806f
+C2  g2013_5 gnd 2.080806f
+C3  g2013_2 gnd 2.080806f
+C4  g2013_1 gnd 2.080806f
+C5  g2013_3 gnd 2.080806f
+R1 g2013_4 g2013_5 2.224404
+R2 g2013_5 g2013_1 2.224404
+R3 g2013_5 g2013_2 2.224404
+R4 g2013_2 g2013_3 2.224404
+.ends
+
+.subckt netg6668 g6668_1 g6668_0 gnd
+C1  g6668_1 gnd 2.080806f
+C2  g6668_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6668_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 g6668_1 3 2.224404
+.ends
+
+.subckt netg5414 g5414_1 g5414_0 gnd
+C1  g5414_1 gnd 2.080806f
+C2  g5414_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5414_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g5414_1 2.224404
+.ends
+
+.subckt netg3177 g3177_1 g3177_2 gnd
+C1  g3177_1 gnd 2.080806f
+C2  g3177_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3177_2 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g3177_1 2.224404
+.ends
+
+.subckt netx202 x202_0 x202_1 gnd
+C1  x202_0 gnd 2.080806f
+C2  x202_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x202_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 3 x202_1 2.224404
+.ends
+
+.subckt netg7431 g7431_1 g7431_0 gnd
+C1  g7431_1 gnd 2.080806f
+C2  g7431_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7431_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g7431_1 2.224404
+.ends
+
+.subckt netg5484 g5484_0 g5484_1 gnd
+C1  g5484_0 gnd 2.080806f
+C2  g5484_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5484_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g5484_1 2.224404
+.ends
+
+.subckt netg5855 g5855_0 g5855_1 gnd
+C1  g5855_0 gnd 2.080806f
+C2  g5855_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5855_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g5855_1 2.224404
+.ends
+
+.subckt netg6884 g6884_0 g6884_1 gnd
+C1  g6884_0 gnd 2.080806f
+C2  g6884_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6884_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g6884_1 2.224404
+.ends
+
+.subckt netg6361 g6361_0 g6361_1 gnd
+C1  g6361_0 gnd 2.080806f
+C2  g6361_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6361_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g6361_1 2.224404
+.ends
+
+.subckt netg7356 g7356_0 g7356_1 gnd
+C1  g7356_0 gnd 2.080806f
+C2  g7356_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7356_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 g7356_1 3 2.224404
+.ends
+
+.subckt netg5440 g5440_0 g5440_1 g5440_2 gnd
+C1  g5440_0 gnd 2.080806f
+C2  g5440_1 gnd 2.080806f
+C3  g5440_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5440_0 1 2.224404
+R2 g5440_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+R4 2 g5440_2 2.224404
+.ends
+
+.subckt netg2677 g2677_2 g2677_1 gnd
+C1  g2677_2 gnd 2.080806f
+C2  g2677_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2677_1 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g2677_2 2.224404
+.ends
+
+.subckt netg6189 g6189_0 g6189_1 gnd
+C1  g6189_0 gnd 2.080806f
+C2  g6189_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6189_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g6189_1 2.224404
+.ends
+
+.subckt netg7375 g7375_2 g7375_1 g7375_0 gnd
+C1  g7375_2 gnd 2.080806f
+C2  g7375_1 gnd 2.080806f
+C3  g7375_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g7375_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g7375_1 2 2.224404
+R4 g7375_2 g7375_1 2.224404
+.ends
+
+.subckt netg1027 g1027_1 g1027_2 g1027_0 gnd
+C1  g1027_1 gnd 2.080806f
+C2  g1027_2 gnd 2.080806f
+C3  g1027_0 gnd 2.080806f
+R1 g1027_0 g1027_1 2.224404
+C4 1 gnd 2.080806f
+R2 1 g1027_0 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+R4 g1027_2 2 2.224404
+.ends
+
+.subckt netg812 g812_3 g812_1 g812_2 g812_0 gnd
+C1  g812_3 gnd 2.080806f
+C2  g812_1 gnd 2.080806f
+C3  g812_2 gnd 2.080806f
+C4  g812_0 gnd 2.080806f
+R1 g812_3 g812_0 2.224404
+R2 g812_3 g812_1 2.224404
+C5 1 gnd 2.080806f
+R3 g812_1 1 2.224404
+R4 1 g812_2 2.224404
+.ends
+
+.subckt netg1054 g1054_1 g1054_0 g1054_2 gnd
+C1  g1054_1 gnd 2.080806f
+C2  g1054_0 gnd 2.080806f
+C3  g1054_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g1054_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g1054_2 2 2.224404
+R4 g1054_1 g1054_2 2.224404
+.ends
+
+.subckt netg5575 g5575_1 g5575_2 g5575_0 gnd
+C1  g5575_1 gnd 2.080806f
+C2  g5575_2 gnd 2.080806f
+C3  g5575_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5575_0 1 2.224404
+R2 g5575_2 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g5575_2 2.224404
+R4 g5575_1 2 2.224404
+.ends
+
+.subckt netg7225 g7225_1 g7225_0 g7225_2 gnd
+C1  g7225_1 gnd 2.080806f
+C2  g7225_0 gnd 2.080806f
+C3  g7225_2 gnd 2.080806f
+R1 g7225_2 g7225_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g7225_2 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+R4 g7225_1 2 2.224404
+.ends
+
+.subckt netg6258 g6258_1 g6258_0 gnd
+C1  g6258_1 gnd 2.080806f
+C2  g6258_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6258_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g6258_1 3 2.224404
+.ends
+
+.subckt netg7060 g7060_2 g7060_0 g7060_1 gnd
+C1  g7060_2 gnd 2.080806f
+C2  g7060_0 gnd 2.080806f
+C3  g7060_1 gnd 2.080806f
+R1 g7060_0 g7060_1 2.224404
+C4 1 gnd 2.080806f
+R2 1 g7060_1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+R4 2 g7060_2 2.224404
+.ends
+
+.subckt netg2474 g2474_0 g2474_1 g2474_2 gnd
+C1  g2474_0 gnd 2.080806f
+C2  g2474_1 gnd 2.080806f
+C3  g2474_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g2474_0 2.224404
+R2 g2474_2 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g2474_2 2.224404
+R4 g2474_1 2 2.224404
+.ends
+
+.subckt netg6161 g6161_1 g6161_0 gnd
+C1  g6161_1 gnd 2.080806f
+C2  g6161_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6161_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g6161_1 2.224404
+.ends
+
+.subckt netg4350 g4350_1 g4350_0 gnd
+C1  g4350_1 gnd 2.080806f
+C2  g4350_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4350_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 g4350_1 3 2.224404
+.ends
+
+.subckt netg4899 g4899_2 g4899_1 g4899_0 gnd
+C1  g4899_2 gnd 2.080806f
+C2  g4899_1 gnd 2.080806f
+C3  g4899_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g4899_0 1 2.224404
+R2 1 g4899_2 2.224404
+C5 2 gnd 2.080806f
+R3 g4899_2 2 2.224404
+R4 2 g4899_1 2.224404
+.ends
+
+.subckt netx32 x32_0 x32_1 gnd
+C1  x32_0 gnd 2.080806f
+C2  x32_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 x32_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 x32_1 2.224404
+.ends
+
+.subckt netg7540 g7540_0 g7540_1 gnd
+C1  g7540_0 gnd 2.080806f
+C2  g7540_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7540_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g7540_1 3 2.224404
+.ends
+
+.subckt netg1554 g1554_0 g1554_1 gnd
+C1  g1554_0 gnd 2.080806f
+C2  g1554_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1554_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g1554_1 2.224404
+.ends
+
+.subckt netg5326 g5326_1 g5326_0 gnd
+C1  g5326_1 gnd 2.080806f
+C2  g5326_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5326_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g5326_1 2.224404
+.ends
+
+.subckt netg5150 g5150_2 g5150_0 g5150_1 gnd
+C1  g5150_2 gnd 2.080806f
+C2  g5150_0 gnd 2.080806f
+C3  g5150_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5150_0 1 2.224404
+R2 1 g5150_2 2.224404
+C5 2 gnd 2.080806f
+R3 g5150_2 2 2.224404
+R4 g5150_1 2 2.224404
+.ends
+
+.subckt netg2809 g2809_0 g2809_1 gnd
+C1  g2809_0 gnd 2.080806f
+C2  g2809_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2809_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 g2809_1 3 2.224404
+.ends
+
+.subckt netg6162 g6162_0 g6162_1 gnd
+C1  g6162_0 gnd 2.080806f
+C2  g6162_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6162_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 3 g6162_1 2.224404
+.ends
+
+.subckt netg5451 g5451_2 g5451_0 g5451_1 gnd
+C1  g5451_2 gnd 2.080806f
+C2  g5451_0 gnd 2.080806f
+C3  g5451_1 gnd 2.080806f
+R1 g5451_1 g5451_0 2.224404
+C4 1 gnd 2.080806f
+R2 g5451_0 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+R4 2 g5451_2 2.224404
+.ends
+
+.subckt netg3141 g3141_1 g3141_2 g3141_0 gnd
+C1  g3141_1 gnd 2.080806f
+C2  g3141_2 gnd 2.080806f
+C3  g3141_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g3141_0 2.224404
+R2 g3141_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 g3141_0 2 2.224404
+R4 2 g3141_2 2.224404
+.ends
+
+.subckt netg3943 g3943_1 g3943_3 g3943_0 g3943_2 gnd
+C1  g3943_1 gnd 2.080806f
+C2  g3943_3 gnd 2.080806f
+C3  g3943_0 gnd 2.080806f
+C4  g3943_2 gnd 2.080806f
+R1 g3943_0 g3943_1 2.224404
+C5 1 gnd 2.080806f
+R2 1 g3943_1 2.224404
+R3 g3943_2 1 2.224404
+R4 g3943_2 g3943_3 2.224404
+.ends
+
+.subckt netg5080 g5080_1 g5080_0 g5080_2 gnd
+C1  g5080_1 gnd 2.080806f
+C2  g5080_0 gnd 2.080806f
+C3  g5080_2 gnd 2.080806f
+R1 g5080_0 g5080_1 2.224404
+C4 1 gnd 2.080806f
+R2 1 g5080_1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+R4 g5080_2 2 2.224404
+.ends
+
+.subckt netg3965 g3965_1 g3965_0 g3965_2 gnd
+C1  g3965_1 gnd 2.080806f
+C2  g3965_0 gnd 2.080806f
+C3  g3965_2 gnd 2.080806f
+R1 g3965_1 g3965_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g3965_0 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+R4 2 g3965_2 2.224404
+.ends
+
+.subckt netg5053 g5053_1 g5053_0 g5053_2 gnd
+C1  g5053_1 gnd 2.080806f
+C2  g5053_0 gnd 2.080806f
+C3  g5053_2 gnd 2.080806f
+R1 g5053_0 g5053_2 2.224404
+C4 1 gnd 2.080806f
+R2 g5053_0 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+R4 2 g5053_1 2.224404
+.ends
+
+.subckt netg6217 g6217_2 g6217_0 g6217_1 gnd
+C1  g6217_2 gnd 2.080806f
+C2  g6217_0 gnd 2.080806f
+C3  g6217_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g6217_0 1 2.224404
+R2 1 g6217_2 2.224404
+C5 2 gnd 2.080806f
+R3 g6217_2 2 2.224404
+R4 2 g6217_1 2.224404
+.ends
+
+.subckt netg6853 g6853_0 g6853_2 g6853_1 gnd
+C1  g6853_0 gnd 2.080806f
+C2  g6853_2 gnd 2.080806f
+C3  g6853_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g6853_0 1 2.224404
+R2 1 g6853_1 2.224404
+C5 2 gnd 2.080806f
+R3 g6853_0 2 2.224404
+R4 g6853_2 2 2.224404
+.ends
+
+.subckt netg4639 g4639_0 g4639_2 g4639_1 gnd
+C1  g4639_0 gnd 2.080806f
+C2  g4639_2 gnd 2.080806f
+C3  g4639_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g4639_0 2.224404
+R2 1 g4639_1 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+R4 g4639_2 2 2.224404
+.ends
+
+.subckt netg1917 g1917_1 g1917_0 gnd
+C1  g1917_1 gnd 2.080806f
+C2  g1917_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1917_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g1917_1 2.224404
+.ends
+
+.subckt netx181 x181_1 x181_0 gnd
+C1  x181_1 gnd 2.080806f
+C2  x181_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x181_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 x181_1 3 2.224404
+.ends
+
+.subckt netg6152 g6152_1 g6152_0 gnd
+C1  g6152_1 gnd 2.080806f
+C2  g6152_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6152_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g6152_1 2.224404
+.ends
+
+.subckt netg6121 g6121_0 g6121_2 g6121_1 gnd
+C1  g6121_0 gnd 2.080806f
+C2  g6121_2 gnd 2.080806f
+C3  g6121_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g6121_0 1 2.224404
+R2 g6121_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g6121_0 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+R5 g6121_2 3 2.224404
+.ends
+
+.subckt netg5746 g5746_1 g5746_2 g5746_0 gnd
+C1  g5746_1 gnd 2.080806f
+C2  g5746_2 gnd 2.080806f
+C3  g5746_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5746_0 2.224404
+R2 g5746_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 g5746_0 2 2.224404
+R4 2 g5746_2 2.224404
+.ends
+
+.subckt netg3123 g3123_1 g3123_2 gnd
+C1  g3123_1 gnd 2.080806f
+C2  g3123_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3123_1 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g3123_2 3 2.224404
+.ends
+
+.subckt netg1468 g1468_0 g1468_1 g1468_4 g1468_3 g1468_5 gnd
+C1  g1468_0 gnd 2.080806f
+C2  g1468_1 gnd 2.080806f
+C3  g1468_4 gnd 2.080806f
+C4  g1468_3 gnd 2.080806f
+C5  g1468_5 gnd 2.080806f
+R1 g1468_5 g1468_0 2.224404
+R2 g1468_0 g1468_4 2.224404
+C6 1 gnd 2.080806f
+R3 g1468_0 1 2.224404
+R4 1 g1468_3 2.224404
+R5 g1468_1 g1468_3 2.224404
+.ends
+
+.subckt netg1774 g1774_1 g1774_2 g1774_3 g1774_0 gnd
+C1  g1774_1 gnd 2.080806f
+C2  g1774_2 gnd 2.080806f
+C3  g1774_3 gnd 2.080806f
+C4  g1774_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g1774_0 2.224404
+R2 g1774_1 1 2.224404
+C6 2 gnd 2.080806f
+R3 g1774_0 2 2.224404
+R4 2 g1774_2 2.224404
+C7 3 gnd 2.080806f
+R5 g1774_1 3 2.224404
+R6 3 g1774_3 2.224404
+.ends
+
+.subckt netg4358 g4358_0 g4358_1 gnd
+C1  g4358_0 gnd 2.080806f
+C2  g4358_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4358_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g4358_1 2.224404
+.ends
+
+.subckt netg6237 g6237_0 g6237_1 g6237_2 gnd
+C1  g6237_0 gnd 2.080806f
+C2  g6237_1 gnd 2.080806f
+C3  g6237_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g6237_0 1 2.224404
+R2 1 g6237_1 2.224404
+C5 2 gnd 2.080806f
+R3 g6237_1 2 2.224404
+R4 2 g6237_2 2.224404
+.ends
+
+.subckt netg4619 g4619_2 g4619_1 gnd
+C1  g4619_2 gnd 2.080806f
+C2  g4619_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4619_2 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g4619_1 2.224404
+.ends
+
+.subckt netg5092 g5092_0 g5092_2 g5092_1 gnd
+C1  g5092_0 gnd 2.080806f
+C2  g5092_2 gnd 2.080806f
+C3  g5092_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5092_0 2.224404
+R2 g5092_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 g5092_0 2 2.224404
+R4 2 g5092_2 2.224404
+.ends
+
+.subckt netg3240 g3240_2 g3240_1 g3240_0 gnd
+C1  g3240_2 gnd 2.080806f
+C2  g3240_1 gnd 2.080806f
+C3  g3240_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g3240_0 1 2.224404
+R2 g3240_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 g3240_1 2 2.224404
+R4 2 g3240_2 2.224404
+.ends
+
+.subckt netg2313 g2313_1 g2313_0 gnd
+C1  g2313_1 gnd 2.080806f
+C2  g2313_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2313_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g2313_1 2.224404
+.ends
+
+.subckt netg4434 g4434_1 g4434_0 gnd
+C1  g4434_1 gnd 2.080806f
+C2  g4434_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4434_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 g4434_1 3 2.224404
+.ends
+
+.subckt netg6300 g6300_2 g6300_1 g6300_0 gnd
+C1  g6300_2 gnd 2.080806f
+C2  g6300_1 gnd 2.080806f
+C3  g6300_0 gnd 2.080806f
+R1 g6300_2 g6300_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g6300_2 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+R4 2 g6300_1 2.224404
+.ends
+
+.subckt netg1908 g1908_1 g1908_0 gnd
+C1  g1908_1 gnd 2.080806f
+C2  g1908_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1908_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g1908_1 2.224404
+.ends
+
+.subckt netg1572 g1572_0 g1572_1 gnd
+C1  g1572_0 gnd 2.080806f
+C2  g1572_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1572_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g1572_1 2.224404
+.ends
+
+.subckt netg952 g952_2 g952_0 g952_1 gnd
+C1  g952_2 gnd 2.080806f
+C2  g952_0 gnd 2.080806f
+C3  g952_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g952_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 2 g952_1 2.224404
+C6 3 gnd 2.080806f
+R4 g952_1 3 2.224404
+R5 3 g952_2 2.224404
+.ends
+
+.subckt netg5477 g5477_0 g5477_1 gnd
+C1  g5477_0 gnd 2.080806f
+C2  g5477_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5477_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g5477_1 2.224404
+.ends
+
+.subckt netg2480 g2480_2 g2480_1 g2480_0 gnd
+C1  g2480_2 gnd 2.080806f
+C2  g2480_1 gnd 2.080806f
+C3  g2480_0 gnd 2.080806f
+R1 g2480_0 g2480_1 2.224404
+C4 1 gnd 2.080806f
+R2 g2480_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+R4 g2480_2 2 2.224404
+.ends
+
+.subckt netg4413 g4413_1 g4413_0 gnd
+C1  g4413_1 gnd 2.080806f
+C2  g4413_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4413_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g4413_1 3 2.224404
+.ends
+
+.subckt netg5936 g5936_1 g5936_0 g5936_2 gnd
+C1  g5936_1 gnd 2.080806f
+C2  g5936_0 gnd 2.080806f
+C3  g5936_2 gnd 2.080806f
+R1 g5936_1 g5936_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g5936_1 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+R4 g5936_2 2 2.224404
+.ends
+
+.subckt netg2510 g2510_0 g2510_2 g2510_1 gnd
+C1  g2510_0 gnd 2.080806f
+C2  g2510_2 gnd 2.080806f
+C3  g2510_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g2510_0 2.224404
+R2 g2510_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g2510_1 2.224404
+R4 2 g2510_2 2.224404
+.ends
+
+.subckt netg2867 g2867_1 g2867_2 g2867_0 gnd
+C1  g2867_1 gnd 2.080806f
+C2  g2867_2 gnd 2.080806f
+C3  g2867_0 gnd 2.080806f
+R1 g2867_0 g2867_2 2.224404
+C4 1 gnd 2.080806f
+R2 g2867_2 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+R4 2 g2867_1 2.224404
+.ends
+
+.subckt netg6140 g6140_1 g6140_0 gnd
+C1  g6140_1 gnd 2.080806f
+C2  g6140_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6140_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g6140_1 3 2.224404
+.ends
+
+.subckt netg6188 g6188_0 g6188_1 gnd
+C1  g6188_0 gnd 2.080806f
+C2  g6188_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6188_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g6188_1 3 2.224404
+.ends
+
+.subckt netg1306 g1306_0 g1306_1 gnd
+C1  g1306_0 gnd 2.080806f
+C2  g1306_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1306_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g1306_1 3 2.224404
+.ends
+
+.subckt netg6127 g6127_1 g6127_2 gnd
+C1  g6127_1 gnd 2.080806f
+C2  g6127_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6127_2 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g6127_1 2.224404
+.ends
+
+.subckt netg1434 g1434_1 g1434_0 gnd
+C1  g1434_1 gnd 2.080806f
+C2  g1434_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1434_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g1434_1 2.224404
+.ends
+
+.subckt netg5315 g5315_0 g5315_1 gnd
+C1  g5315_0 gnd 2.080806f
+C2  g5315_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5315_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g5315_1 3 2.224404
+.ends
+
+.subckt netg6314 g6314_1 g6314_0 gnd
+C1  g6314_1 gnd 2.080806f
+C2  g6314_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6314_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g6314_1 3 2.224404
+.ends
+
+.subckt netg7363 g7363_2 g7363_0 g7363_1 gnd
+C1  g7363_2 gnd 2.080806f
+C2  g7363_0 gnd 2.080806f
+C3  g7363_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g7363_0 2.224404
+R2 g7363_2 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+R4 g7363_1 2 2.224404
+.ends
+
+.subckt netg3285 g3285_2 g3285_0 g3285_1 gnd
+C1  g3285_2 gnd 2.080806f
+C2  g3285_0 gnd 2.080806f
+C3  g3285_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g3285_0 2.224404
+R2 g3285_2 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+R4 2 g3285_1 2.224404
+.ends
+
+.subckt netg3243 g3243_1 g3243_2 g3243_0 gnd
+C1  g3243_1 gnd 2.080806f
+C2  g3243_2 gnd 2.080806f
+C3  g3243_0 gnd 2.080806f
+R1 g3243_0 g3243_2 2.224404
+C4 1 gnd 2.080806f
+R2 1 g3243_0 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+R4 2 g3243_1 2.224404
+.ends
+
+.subckt netg1036 g1036_2 g1036_0 gnd
+C1  g1036_2 gnd 2.080806f
+C2  g1036_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1036_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 3 g1036_2 2.224404
+.ends
+
+.subckt netg3147 g3147_1 g3147_2 g3147_0 gnd
+C1  g3147_1 gnd 2.080806f
+C2  g3147_2 gnd 2.080806f
+C3  g3147_0 gnd 2.080806f
+R1 g3147_1 g3147_0 2.224404
+C4 1 gnd 2.080806f
+R2 g3147_0 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+R4 2 g3147_2 2.224404
+.ends
+
+.subckt netg3447 g3447_1 g3447_2 g3447_0 gnd
+C1  g3447_1 gnd 2.080806f
+C2  g3447_2 gnd 2.080806f
+C3  g3447_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g3447_0 1 2.224404
+R2 1 g3447_1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+R4 2 g3447_2 2.224404
+.ends
+
+.subckt netg7245 g7245_2 g7245_0 g7245_1 gnd
+C1  g7245_2 gnd 2.080806f
+C2  g7245_0 gnd 2.080806f
+C3  g7245_1 gnd 2.080806f
+R1 g7245_1 g7245_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g7245_1 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+R4 g7245_2 2 2.224404
+.ends
+
+.subckt netg5125 g5125_0 g5125_2 g5125_1 gnd
+C1  g5125_0 gnd 2.080806f
+C2  g5125_2 gnd 2.080806f
+C3  g5125_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5125_0 1 2.224404
+R2 1 g5125_2 2.224404
+C5 2 gnd 2.080806f
+R3 g5125_0 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g5125_1 2.224404
+.ends
+
+.subckt netx262 x262_1 x262_0 gnd
+C1  x262_1 gnd 2.080806f
+C2  x262_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x262_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 x262_1 3 2.224404
+.ends
+
+.subckt netg5271 g5271_1 g5271_0 gnd
+C1  g5271_1 gnd 2.080806f
+C2  g5271_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5271_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g5271_1 2.224404
+.ends
+
+.subckt netg7012 g7012_1 g7012_0 gnd
+C1  g7012_1 gnd 2.080806f
+C2  g7012_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7012_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g7012_1 3 2.224404
+.ends
+
+.subckt netg7242 g7242_1 g7242_2 g7242_0 gnd
+C1  g7242_1 gnd 2.080806f
+C2  g7242_2 gnd 2.080806f
+C3  g7242_0 gnd 2.080806f
+R1 g7242_0 g7242_1 2.224404
+C4 1 gnd 2.080806f
+R2 g7242_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+R4 2 g7242_2 2.224404
+.ends
+
+.subckt netg6471 g6471_2 g6471_1 g6471_0 gnd
+C1  g6471_2 gnd 2.080806f
+C2  g6471_1 gnd 2.080806f
+C3  g6471_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g6471_0 2.224404
+R2 g6471_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g6471_1 2.224404
+R4 g6471_2 2 2.224404
+.ends
+
+.subckt netg6793 g6793_1 g6793_2 g6793_0 gnd
+C1  g6793_1 gnd 2.080806f
+C2  g6793_2 gnd 2.080806f
+C3  g6793_0 gnd 2.080806f
+R1 g6793_0 g6793_2 2.224404
+C4 1 gnd 2.080806f
+R2 1 g6793_0 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+R4 g6793_1 2 2.224404
+.ends
+
+.subckt netg7051 g7051_0 g7051_2 g7051_1 gnd
+C1  g7051_0 gnd 2.080806f
+C2  g7051_2 gnd 2.080806f
+C3  g7051_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g7051_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g7051_2 2 2.224404
+R4 g7051_1 g7051_2 2.224404
+.ends
+
+.subckt netg6658 g6658_1 g6658_0 gnd
+C1  g6658_1 gnd 2.080806f
+C2  g6658_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6658_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 g6658_1 3 2.224404
+.ends
+
+.subckt netg7255 g7255_0 g7255_1 gnd
+C1  g7255_0 gnd 2.080806f
+C2  g7255_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7255_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g7255_1 2.224404
+.ends
+
+.subckt netg1361 g1361_0 g1361_1 gnd
+C1  g1361_0 gnd 2.080806f
+C2  g1361_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1361_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g1361_1 2.224404
+.ends
+
+.subckt netx311 x311_1 x311_0 gnd
+C1  x311_1 gnd 2.080806f
+C2  x311_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x311_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 x311_1 3 2.224404
+.ends
+
+.subckt netg6686 g6686_0 g6686_1 gnd
+C1  g6686_0 gnd 2.080806f
+C2  g6686_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6686_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g6686_1 3 2.224404
+.ends
+
+.subckt netg925 g925_2 g925_0 g925_1 gnd
+C1  g925_2 gnd 2.080806f
+C2  g925_0 gnd 2.080806f
+C3  g925_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g925_0 1 2.224404
+R2 1 g925_2 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+R4 2 g925_1 2.224404
+.ends
+
+.subckt netg6799 g6799_0 g6799_2 g6799_1 gnd
+C1  g6799_0 gnd 2.080806f
+C2  g6799_2 gnd 2.080806f
+C3  g6799_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g6799_0 1 2.224404
+R2 1 g6799_2 2.224404
+C5 2 gnd 2.080806f
+R3 g6799_2 2 2.224404
+R4 2 g6799_1 2.224404
+.ends
+
+.subckt netg6144 g6144_2 g6144_1 g6144_0 gnd
+C1  g6144_2 gnd 2.080806f
+C2  g6144_1 gnd 2.080806f
+C3  g6144_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g6144_0 2.224404
+R2 1 g6144_1 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+R4 g6144_2 2 2.224404
+.ends
+
+.subckt netx331 x331_0 x331_1 gnd
+C1  x331_0 gnd 2.080806f
+C2  x331_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 x331_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 x331_1 2.224404
+.ends
+
+.subckt netg3135 g3135_1 g3135_0 g3135_2 gnd
+C1  g3135_1 gnd 2.080806f
+C2  g3135_0 gnd 2.080806f
+C3  g3135_2 gnd 2.080806f
+R1 g3135_1 g3135_0 2.224404
+C4 1 gnd 2.080806f
+R2 g3135_0 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+R4 2 g3135_2 2.224404
+.ends
+
+.subckt netg7527 g7527_0 g7527_1 gnd
+C1  g7527_0 gnd 2.080806f
+C2  g7527_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7527_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g7527_1 2.224404
+.ends
+
+.subckt netg6524 g6524_1 g6524_0 gnd
+C1  g6524_1 gnd 2.080806f
+C2  g6524_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6524_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 g6524_1 3 2.224404
+.ends
+
+.subckt netg3559 g3559_0 g3559_1 gnd
+C1  g3559_0 gnd 2.080806f
+C2  g3559_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3559_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g3559_1 3 2.224404
+.ends
+
+.subckt netg1555 g1555_0 g1555_1 gnd
+C1  g1555_0 gnd 2.080806f
+C2  g1555_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1555_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g1555_1 3 2.224404
+.ends
+
+.subckt netg940 g940_2 g940_1 g940_0 gnd
+C1  g940_2 gnd 2.080806f
+C2  g940_1 gnd 2.080806f
+C3  g940_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g940_0 2.224404
+R2 g940_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 g940_0 2 2.224404
+R4 2 g940_2 2.224404
+.ends
+
+.subckt netg5487 g5487_1 g5487_0 gnd
+C1  g5487_1 gnd 2.080806f
+C2  g5487_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5487_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g5487_1 3 2.224404
+.ends
+
+.subckt netg5412 g5412_0 g5412_1 gnd
+C1  g5412_0 gnd 2.080806f
+C2  g5412_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5412_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 g5412_1 3 2.224404
+.ends
+
+.subckt netg567 g567_1 g567_0 g567_2 gnd
+C1  g567_1 gnd 2.080806f
+C2  g567_0 gnd 2.080806f
+C3  g567_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g567_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g567_1 2 2.224404
+R4 g567_2 g567_1 2.224404
+.ends
+
+.subckt netx561 x561_1 x561_0 gnd
+C1  x561_1 gnd 2.080806f
+C2  x561_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 x561_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 x561_1 2.224404
+.ends
+
+.subckt netg5716 g5716_0 g5716_2 g5716_1 gnd
+C1  g5716_0 gnd 2.080806f
+C2  g5716_2 gnd 2.080806f
+C3  g5716_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5716_0 1 2.224404
+R2 1 g5716_1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g5716_0 2.224404
+R4 g5716_2 2 2.224404
+.ends
+
+.subckt netg1302 g1302_0 g1302_1 gnd
+C1  g1302_0 gnd 2.080806f
+C2  g1302_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1302_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 g1302_1 3 2.224404
+.ends
+
+.subckt netg7404 g7404_1 g7404_0 gnd
+C1  g7404_1 gnd 2.080806f
+C2  g7404_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7404_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g7404_1 3 2.224404
+.ends
+
+.subckt netg3371 g3371_2 g3371_1 g3371_0 gnd
+C1  g3371_2 gnd 2.080806f
+C2  g3371_1 gnd 2.080806f
+C3  g3371_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g3371_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g3371_2 2.224404
+R4 g3371_2 g3371_1 2.224404
+.ends
+
+.subckt netg2241 g2241_1 g2241_0 g2241_2 gnd
+C1  g2241_1 gnd 2.080806f
+C2  g2241_0 gnd 2.080806f
+C3  g2241_2 gnd 2.080806f
+R1 g2241_1 g2241_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g2241_0 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+R4 g2241_2 2 2.224404
+.ends
+
+.subckt netg6509 g6509_0 g6509_1 gnd
+C1  g6509_0 gnd 2.080806f
+C2  g6509_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6509_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g6509_1 3 2.224404
+.ends
+
+.subckt netg4943 g4943_2 g4943_1 g4943_0 gnd
+C1  g4943_2 gnd 2.080806f
+C2  g4943_1 gnd 2.080806f
+C3  g4943_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g4943_0 1 2.224404
+R2 1 g4943_1 2.224404
+C5 2 gnd 2.080806f
+R3 g4943_1 2 2.224404
+R4 2 g4943_2 2.224404
+.ends
+
+.subckt netg6310 g6310_0 g6310_1 gnd
+C1  g6310_0 gnd 2.080806f
+C2  g6310_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6310_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 g6310_1 3 2.224404
+.ends
+
+.subckt netg6085 g6085_1 g6085_0 gnd
+C1  g6085_1 gnd 2.080806f
+C2  g6085_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6085_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g6085_1 2.224404
+.ends
+
+.subckt netg1438 g1438_0 g1438_1 gnd
+C1  g1438_0 gnd 2.080806f
+C2  g1438_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1438_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g1438_1 2.224404
+.ends
+
+.subckt netg5778 g5778_1 g5778_0 gnd
+C1  g5778_1 gnd 2.080806f
+C2  g5778_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5778_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g5778_1 2.224404
+.ends
+
+.subckt netg7414 g7414_0 g7414_2 g7414_1 gnd
+C1  g7414_0 gnd 2.080806f
+C2  g7414_2 gnd 2.080806f
+C3  g7414_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g7414_0 2.224404
+R2 g7414_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+R4 g7414_2 2 2.224404
+.ends
+
+.subckt netg7237 g7237_2 g7237_0 g7237_1 gnd
+C1  g7237_2 gnd 2.080806f
+C2  g7237_0 gnd 2.080806f
+C3  g7237_1 gnd 2.080806f
+R1 g7237_1 g7237_0 2.224404
+C4 1 gnd 2.080806f
+R2 g7237_0 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+R4 2 g7237_2 2.224404
+.ends
+
+.subckt netg3150 g3150_1 g3150_2 g3150_0 gnd
+C1  g3150_1 gnd 2.080806f
+C2  g3150_2 gnd 2.080806f
+C3  g3150_0 gnd 2.080806f
+R1 g3150_0 g3150_1 2.224404
+C4 1 gnd 2.080806f
+R2 g3150_0 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+R4 2 g3150_2 2.224404
+.ends
+
+.subckt netg7153 g7153_1 g7153_0 g7153_2 gnd
+C1  g7153_1 gnd 2.080806f
+C2  g7153_0 gnd 2.080806f
+C3  g7153_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g7153_0 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g7153_1 2.224404
+R4 g7153_2 2 2.224404
+.ends
+
+.subckt netg1520 g1520_1 g1520_0 gnd
+C1  g1520_1 gnd 2.080806f
+C2  g1520_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1520_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g1520_1 3 2.224404
+.ends
+
+.subckt netg5722 g5722_2 g5722_1 g5722_0 gnd
+C1  g5722_2 gnd 2.080806f
+C2  g5722_1 gnd 2.080806f
+C3  g5722_0 gnd 2.080806f
+R1 g5722_1 g5722_0 2.224404
+C4 1 gnd 2.080806f
+R2 g5722_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+R4 g5722_2 2 2.224404
+.ends
+
+.subckt netg1497 g1497_1 g1497_0 gnd
+C1  g1497_1 gnd 2.080806f
+C2  g1497_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1497_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g1497_1 3 2.224404
+.ends
+
+.subckt netg4447 g4447_0 g4447_1 gnd
+C1  g4447_0 gnd 2.080806f
+C2  g4447_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4447_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g4447_1 3 2.224404
+.ends
+
+.subckt netg5843 g5843_2 g5843_1 g5843_0 gnd
+C1  g5843_2 gnd 2.080806f
+C2  g5843_1 gnd 2.080806f
+C3  g5843_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5843_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g5843_1 2 2.224404
+R4 g5843_1 g5843_2 2.224404
+.ends
+
+.subckt netg98 g98_0 g98_1 gnd
+C1  g98_0 gnd 2.080806f
+C2  g98_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g98_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g98_1 3 2.224404
+.ends
+
+.subckt netg5521 g5521_0 g5521_1 gnd
+C1  g5521_0 gnd 2.080806f
+C2  g5521_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5521_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g5521_1 3 2.224404
+.ends
+
+.subckt netg2612 g2612_1 g2612_2 g2612_0 gnd
+C1  g2612_1 gnd 2.080806f
+C2  g2612_2 gnd 2.080806f
+C3  g2612_0 gnd 2.080806f
+R1 g2612_2 g2612_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g2612_0 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+R4 2 g2612_1 2.224404
+.ends
+
+.subckt netg7428 g7428_1 g7428_2 g7428_0 gnd
+C1  g7428_1 gnd 2.080806f
+C2  g7428_2 gnd 2.080806f
+C3  g7428_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g7428_0 1 2.224404
+R2 1 g7428_1 2.224404
+C5 2 gnd 2.080806f
+R3 g7428_0 2 2.224404
+R4 2 g7428_2 2.224404
+.ends
+
+.subckt netg1853 g1853_2 g1853_1 g1853_0 gnd
+C1  g1853_2 gnd 2.080806f
+C2  g1853_1 gnd 2.080806f
+C3  g1853_0 gnd 2.080806f
+R1 g1853_0 g1853_2 2.224404
+C4 1 gnd 2.080806f
+R2 g1853_0 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+R4 2 g1853_1 2.224404
+.ends
+
+.subckt netg7027 g7027_2 g7027_1 gnd
+C1  g7027_2 gnd 2.080806f
+C2  g7027_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7027_1 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 g7027_2 3 2.224404
+.ends
+
+.subckt netg2752 g2752_0 g2752_3 g2752_2 g2752_1 gnd
+C1  g2752_0 gnd 2.080806f
+C2  g2752_3 gnd 2.080806f
+C3  g2752_2 gnd 2.080806f
+C4  g2752_1 gnd 2.080806f
+R1 g2752_2 g2752_0 2.224404
+R2 g2752_3 g2752_2 2.224404
+C5 1 gnd 2.080806f
+R3 g2752_2 1 2.224404
+R4 1 g2752_1 2.224404
+.ends
+
+.subckt netg4217 g4217_1 g4217_0 gnd
+C1  g4217_1 gnd 2.080806f
+C2  g4217_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4217_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g4217_1 3 2.224404
+.ends
+
+.subckt netg5563 g5563_0 g5563_2 g5563_1 gnd
+C1  g5563_0 gnd 2.080806f
+C2  g5563_2 gnd 2.080806f
+C3  g5563_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5563_0 2.224404
+R2 g5563_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 g5563_1 2 2.224404
+R4 2 g5563_2 2.224404
+.ends
+
+.subckt netg2728 g2728_0 g2728_1 g2728_2 gnd
+C1  g2728_0 gnd 2.080806f
+C2  g2728_1 gnd 2.080806f
+C3  g2728_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g2728_0 2.224404
+R2 g2728_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 g2728_1 2 2.224404
+R4 g2728_2 2 2.224404
+.ends
+
+.subckt netg7336 g7336_0 g7336_2 g7336_1 gnd
+C1  g7336_0 gnd 2.080806f
+C2  g7336_2 gnd 2.080806f
+C3  g7336_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g7336_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g7336_2 2.224404
+R4 g7336_2 g7336_1 2.224404
+.ends
+
+.subckt netg3060 g3060_1 g3060_0 gnd
+C1  g3060_1 gnd 2.080806f
+C2  g3060_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3060_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g3060_1 3 2.224404
+.ends
+
+.subckt netg6453 g6453_1 g6453_0 g6453_2 gnd
+C1  g6453_1 gnd 2.080806f
+C2  g6453_0 gnd 2.080806f
+C3  g6453_2 gnd 2.080806f
+R1 g6453_0 g6453_2 2.224404
+C4 1 gnd 2.080806f
+R2 g6453_0 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+R4 2 g6453_1 2.224404
+.ends
+
+.subckt netg7193 g7193_1 g7193_0 g7193_2 gnd
+C1  g7193_1 gnd 2.080806f
+C2  g7193_0 gnd 2.080806f
+C3  g7193_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g7193_0 2.224404
+R2 1 g7193_1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g7193_0 2.224404
+R4 g7193_2 2 2.224404
+.ends
+
+.subckt netg5917 g5917_1 g5917_2 g5917_0 gnd
+C1  g5917_1 gnd 2.080806f
+C2  g5917_2 gnd 2.080806f
+C3  g5917_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5917_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g5917_2 2 2.224404
+R4 g5917_2 g5917_1 2.224404
+.ends
+
+.subckt netg4117 g4117_0 g4117_3 g4117_1 g4117_2 gnd
+C1  g4117_0 gnd 2.080806f
+C2  g4117_3 gnd 2.080806f
+C3  g4117_1 gnd 2.080806f
+C4  g4117_2 gnd 2.080806f
+R1 g4117_0 g4117_1 2.224404
+C5 1 gnd 2.080806f
+R2 1 g4117_0 2.224404
+R3 g4117_2 1 2.224404
+R4 g4117_3 1 2.224404
+.ends
+
+.subckt netg2686 g2686_1 g2686_0 g2686_2 gnd
+C1  g2686_1 gnd 2.080806f
+C2  g2686_0 gnd 2.080806f
+C3  g2686_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g2686_0 1 2.224404
+R2 g2686_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g2686_0 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+R5 g2686_2 3 2.224404
+.ends
+
+.subckt netg5643 g5643_2 g5643_0 g5643_1 gnd
+C1  g5643_2 gnd 2.080806f
+C2  g5643_0 gnd 2.080806f
+C3  g5643_1 gnd 2.080806f
+R1 g5643_0 g5643_1 2.224404
+C4 1 gnd 2.080806f
+R2 1 g5643_0 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+R4 g5643_2 2 2.224404
+.ends
+
+.subckt netg4357 g4357_0 g4357_1 gnd
+C1  g4357_0 gnd 2.080806f
+C2  g4357_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4357_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g4357_1 3 2.224404
+.ends
+
+.subckt netg3213 g3213_2 g3213_1 gnd
+C1  g3213_2 gnd 2.080806f
+C2  g3213_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3213_1 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 g3213_2 3 2.224404
+.ends
+
+.subckt netx51 x51_1 x51_0 gnd
+C1  x51_1 gnd 2.080806f
+C2  x51_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 x51_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 x51_1 2.224404
+.ends
+
+.subckt netx151 x151_0 x151_1 gnd
+C1  x151_0 gnd 2.080806f
+C2  x151_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x151_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 x151_1 3 2.224404
+.ends
+
+.subckt netg6995 g6995_0 g6995_1 gnd
+C1  g6995_0 gnd 2.080806f
+C2  g6995_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6995_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 g6995_1 3 2.224404
+.ends
+
+.subckt netg4423 g4423_0 g4423_1 gnd
+C1  g4423_0 gnd 2.080806f
+C2  g4423_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4423_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 3 g4423_1 2.224404
+.ends
+
+.subckt netg6537 g6537_1 g6537_0 gnd
+C1  g6537_1 gnd 2.080806f
+C2  g6537_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6537_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g6537_1 2.224404
+.ends
+
+.subckt netg6560 g6560_1 g6560_0 gnd
+C1  g6560_1 gnd 2.080806f
+C2  g6560_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6560_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g6560_1 3 2.224404
+.ends
+
+.subckt netg7015 g7015_1 g7015_0 gnd
+C1  g7015_1 gnd 2.080806f
+C2  g7015_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7015_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g7015_1 2.224404
+.ends
+
+.subckt netg3086 g3086_1 g3086_2 g3086_0 gnd
+C1  g3086_1 gnd 2.080806f
+C2  g3086_2 gnd 2.080806f
+C3  g3086_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g3086_0 2.224404
+R2 g3086_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 g3086_1 2 2.224404
+R4 g3086_2 2 2.224404
+.ends
+
+.subckt netg6396 g6396_1 g6396_0 gnd
+C1  g6396_1 gnd 2.080806f
+C2  g6396_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6396_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g6396_1 3 2.224404
+.ends
+
+.subckt netg5710 g5710_2 g5710_0 g5710_1 gnd
+C1  g5710_2 gnd 2.080806f
+C2  g5710_0 gnd 2.080806f
+C3  g5710_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5710_0 2.224404
+R2 g5710_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g5710_1 2.224404
+R4 g5710_2 2 2.224404
+.ends
+
+.subckt netg5044 g5044_1 g5044_0 g5044_2 gnd
+C1  g5044_1 gnd 2.080806f
+C2  g5044_0 gnd 2.080806f
+C3  g5044_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5044_0 1 2.224404
+R2 g5044_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 g5044_1 2 2.224404
+R4 g5044_2 2 2.224404
+.ends
+
+.subckt netg5834 g5834_1 g5834_0 gnd
+C1  g5834_1 gnd 2.080806f
+C2  g5834_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5834_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g5834_1 2.224404
+.ends
+
+.subckt netg5871 g5871_2 g5871_0 gnd
+C1  g5871_2 gnd 2.080806f
+C2  g5871_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5871_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g5871_2 2.224404
+.ends
+
+.subckt netg6850 g6850_1 g6850_0 g6850_2 gnd
+C1  g6850_1 gnd 2.080806f
+C2  g6850_0 gnd 2.080806f
+C3  g6850_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g6850_0 2.224404
+R2 g6850_2 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g6850_2 2.224404
+R4 g6850_1 2 2.224404
+.ends
+
+.subckt netg2023 g2023_2 g2023_3 g2023_1 gnd
+C1  g2023_2 gnd 2.080806f
+C2  g2023_3 gnd 2.080806f
+C3  g2023_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g2023_3 2.224404
+R2 g2023_2 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g2023_2 2.224404
+R4 g2023_1 2 2.224404
+.ends
+
+.subckt netg1940 g1940_0 g1940_1 gnd
+C1  g1940_0 gnd 2.080806f
+C2  g1940_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1940_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 g1940_1 3 2.224404
+.ends
+
+.subckt netg2549 g2549_0 g2549_1 g2549_2 gnd
+C1  g2549_0 gnd 2.080806f
+C2  g2549_1 gnd 2.080806f
+C3  g2549_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g2549_0 1 2.224404
+R2 1 g2549_1 2.224404
+C5 2 gnd 2.080806f
+R3 g2549_1 2 2.224404
+R4 2 g2549_2 2.224404
+.ends
+
+.subckt netg1030 g1030_1 g1030_2 gnd
+C1  g1030_1 gnd 2.080806f
+C2  g1030_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1030_2 1 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 g1030_1 3 2.224404
+.ends
+
+.subckt netg2070 g2070_1 g2070_0 gnd
+C1  g2070_1 gnd 2.080806f
+C2  g2070_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2070_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g2070_1 3 2.224404
+.ends
+
+.subckt netg1478 g1478_0 g1478_1 gnd
+C1  g1478_0 gnd 2.080806f
+C2  g1478_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1478_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g1478_1 2.224404
+.ends
+
+.subckt netg4666 g4666_1 g4666_0 gnd
+C1  g4666_1 gnd 2.080806f
+C2  g4666_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4666_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 3 g4666_1 2.224404
+.ends
+
+.subckt netg4625 g4625_1 g4625_0 gnd
+C1  g4625_1 gnd 2.080806f
+C2  g4625_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4625_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g4625_1 2.224404
+.ends
+
+.subckt netg3914 g3914_0 g3914_1 gnd
+C1  g3914_0 gnd 2.080806f
+C2  g3914_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3914_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 g3914_1 3 2.224404
+.ends
+
+.subckt netg7321 g7321_0 g7321_2 g7321_1 gnd
+C1  g7321_0 gnd 2.080806f
+C2  g7321_2 gnd 2.080806f
+C3  g7321_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g7321_0 1 2.224404
+R2 1 g7321_2 2.224404
+C5 2 gnd 2.080806f
+R3 g7321_2 2 2.224404
+R4 2 g7321_1 2.224404
+.ends
+
+.subckt netg5780 g5780_1 g5780_2 gnd
+C1  g5780_1 gnd 2.080806f
+C2  g5780_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5780_1 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g5780_2 3 2.224404
+.ends
+
+.subckt netg6318 g6318_2 g6318_0 g6318_1 g6318_3 gnd
+C1  g6318_2 gnd 2.080806f
+C2  g6318_0 gnd 2.080806f
+C3  g6318_1 gnd 2.080806f
+C4  g6318_3 gnd 2.080806f
+R1 g6318_0 g6318_2 2.224404
+R2 g6318_1 g6318_2 2.224404
+C5 1 gnd 2.080806f
+R3 g6318_2 1 2.224404
+R4 1 g6318_3 2.224404
+.ends
+
+.subckt netg1060 g1060_2 g1060_3 g1060_5 g1060_4 g1060_1 g1060_0 gnd
+C1  g1060_2 gnd 2.080806f
+C2  g1060_3 gnd 2.080806f
+C3  g1060_5 gnd 2.080806f
+C4  g1060_4 gnd 2.080806f
+C5  g1060_1 gnd 2.080806f
+C6  g1060_0 gnd 2.080806f
+R1 g1060_2 g1060_0 2.224404
+R2 g1060_0 g1060_4 2.224404
+R3 g1060_3 g1060_2 2.224404
+R4 g1060_5 g1060_3 2.224404
+R5 g1060_5 g1060_1 2.224404
+.ends
+
+.subckt netg3407 g3407_1 g3407_2 g3407_0 gnd
+C1  g3407_1 gnd 2.080806f
+C2  g3407_2 gnd 2.080806f
+C3  g3407_0 gnd 2.080806f
+R1 g3407_1 g3407_0 2.224404
+C4 1 gnd 2.080806f
+R2 g3407_0 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+R4 2 g3407_2 2.224404
+.ends
+
+.subckt netg5083 g5083_0 g5083_1 g5083_2 gnd
+C1  g5083_0 gnd 2.080806f
+C2  g5083_1 gnd 2.080806f
+C3  g5083_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5083_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g5083_1 2 2.224404
+C6 3 gnd 2.080806f
+R4 g5083_1 3 2.224404
+R5 g5083_2 3 2.224404
+.ends
+
+.subckt netg5489 g5489_0 g5489_1 gnd
+C1  g5489_0 gnd 2.080806f
+C2  g5489_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5489_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g5489_1 3 2.224404
+.ends
+
+.subckt netg3270 g3270_0 g3270_1 g3270_2 gnd
+C1  g3270_0 gnd 2.080806f
+C2  g3270_1 gnd 2.080806f
+C3  g3270_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g3270_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g3270_2 2.224404
+R4 g3270_2 g3270_1 2.224404
+.ends
+
+.subckt netg7421 g7421_1 g7421_0 gnd
+C1  g7421_1 gnd 2.080806f
+C2  g7421_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7421_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 g7421_1 3 2.224404
+.ends
+
+.subckt netx472 x472_1 x472_0 gnd
+C1  x472_1 gnd 2.080806f
+C2  x472_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x472_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 3 x472_1 2.224404
+.ends
+
+.subckt netg3947 g3947_0 g3947_1 g3947_2 gnd
+C1  g3947_0 gnd 2.080806f
+C2  g3947_1 gnd 2.080806f
+C3  g3947_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g3947_0 1 2.224404
+R2 1 g3947_2 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+R4 2 g3947_1 2.224404
+.ends
+
+.subckt netg1897 g1897_0 g1897_1 gnd
+C1  g1897_0 gnd 2.080806f
+C2  g1897_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1897_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g1897_1 2.224404
+.ends
+
+.subckt netg5903 g5903_1 g5903_0 g5903_2 gnd
+C1  g5903_1 gnd 2.080806f
+C2  g5903_0 gnd 2.080806f
+C3  g5903_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5903_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g5903_1 2.224404
+R4 2 g5903_2 2.224404
+.ends
+
+.subckt netg4931 g4931_0 g4931_3 g4931_1 g4931_2 gnd
+C1  g4931_0 gnd 2.080806f
+C2  g4931_3 gnd 2.080806f
+C3  g4931_1 gnd 2.080806f
+C4  g4931_2 gnd 2.080806f
+R1 g4931_3 g4931_0 2.224404
+R2 g4931_1 g4931_3 2.224404
+C5 1 gnd 2.080806f
+R3 1 g4931_1 2.224404
+R4 g4931_2 1 2.224404
+.ends
+
+.subckt netg7033 g7033_0 g7033_1 g7033_4 g7033_3 gnd
+C1  g7033_0 gnd 2.080806f
+C2  g7033_1 gnd 2.080806f
+C3  g7033_4 gnd 2.080806f
+C4  g7033_3 gnd 2.080806f
+R1 g7033_0 g7033_4 2.224404
+C5 1 gnd 2.080806f
+R2 1 g7033_4 2.224404
+R3 g7033_3 1 2.224404
+C6 2 gnd 2.080806f
+R4 2 g7033_3 2.224404
+R5 g7033_1 2 2.224404
+.ends
+
+.subckt netg6826 g6826_0 g6826_1 gnd
+C1  g6826_0 gnd 2.080806f
+C2  g6826_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6826_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g6826_1 2.224404
+.ends
+
+.subckt netg5649 g5649_0 g5649_2 g5649_1 gnd
+C1  g5649_0 gnd 2.080806f
+C2  g5649_2 gnd 2.080806f
+C3  g5649_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5649_0 2.224404
+R2 1 g5649_2 2.224404
+C5 2 gnd 2.080806f
+R3 2 g5649_2 2.224404
+R4 g5649_1 2 2.224404
+.ends
+
+.subckt netg3526 g3526_0 g3526_1 gnd
+C1  g3526_0 gnd 2.080806f
+C2  g3526_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3526_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g3526_1 2.224404
+.ends
+
+.subckt netg4967 g4967_1 g4967_2 g4967_0 gnd
+C1  g4967_1 gnd 2.080806f
+C2  g4967_2 gnd 2.080806f
+C3  g4967_0 gnd 2.080806f
+R1 g4967_2 g4967_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g4967_2 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+R4 g4967_1 2 2.224404
+.ends
+
+.subckt netg1066 g1066_0 g1066_1 g1066_2 gnd
+C1  g1066_0 gnd 2.080806f
+C2  g1066_1 gnd 2.080806f
+C3  g1066_2 gnd 2.080806f
+R1 g1066_2 g1066_0 2.224404
+C4 1 gnd 2.080806f
+R2 g1066_0 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g1066_1 2.224404
+.ends
+
+.subckt netg5707 g5707_1 g5707_0 g5707_2 gnd
+C1  g5707_1 gnd 2.080806f
+C2  g5707_0 gnd 2.080806f
+C3  g5707_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5707_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g5707_1 2 2.224404
+C6 3 gnd 2.080806f
+R4 g5707_1 3 2.224404
+R5 g5707_2 3 2.224404
+.ends
+
+.subckt netg7088 g7088_0 g7088_1 gnd
+C1  g7088_0 gnd 2.080806f
+C2  g7088_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7088_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 4 g7088_1 2.224404
+.ends
+
+.subckt netg5912 g5912_2 g5912_0 g5912_1 gnd
+C1  g5912_2 gnd 2.080806f
+C2  g5912_0 gnd 2.080806f
+C3  g5912_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5912_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g5912_1 3 2.224404
+R5 g5912_2 g5912_1 2.224404
+.ends
+
+.subckt netg5942 g5942_2 g5942_1 g5942_0 gnd
+C1  g5942_2 gnd 2.080806f
+C2  g5942_1 gnd 2.080806f
+C3  g5942_0 gnd 2.080806f
+R1 g5942_1 g5942_0 2.224404
+C4 1 gnd 2.080806f
+R2 g5942_0 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g5942_2 2.224404
+.ends
+
+.subckt netg4940 g4940_2 g4940_0 g4940_1 gnd
+C1  g4940_2 gnd 2.080806f
+C2  g4940_0 gnd 2.080806f
+C3  g4940_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g4940_0 2.224404
+R2 1 g4940_1 2.224404
+C5 2 gnd 2.080806f
+R3 g4940_0 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 4 g4940_2 2.224404
+.ends
+
+.subckt netg2756 g2756_0 g2756_2 g2756_1 gnd
+C1  g2756_0 gnd 2.080806f
+C2  g2756_2 gnd 2.080806f
+C3  g2756_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g2756_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g2756_1 2 2.224404
+C6 3 gnd 2.080806f
+R4 3 g2756_0 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+R6 g2756_2 4 2.224404
+.ends
+
+.subckt netg3444 g3444_1 g3444_0 g3444_2 gnd
+C1  g3444_1 gnd 2.080806f
+C2  g3444_0 gnd 2.080806f
+C3  g3444_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g3444_0 2.224404
+R2 g3444_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g3444_1 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+R5 g3444_2 3 2.224404
+.ends
+
+.subckt netg4183 g4183_0 g4183_1 g4183_2 gnd
+C1  g4183_0 gnd 2.080806f
+C2  g4183_1 gnd 2.080806f
+C3  g4183_2 gnd 2.080806f
+R1 g4183_1 g4183_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g4183_0 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g4183_2 2.224404
+.ends
+
+.subckt netg1536 g1536_1 g1536_0 gnd
+C1  g1536_1 gnd 2.080806f
+C2  g1536_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1536_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 g1536_1 4 2.224404
+.ends
+
+.subckt netg1006 g1006_2 g1006_0 g1006_1 gnd
+C1  g1006_2 gnd 2.080806f
+C2  g1006_0 gnd 2.080806f
+C3  g1006_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g1006_0 2.224404
+R2 g1006_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g1006_2 2.224404
+.ends
+
+.subckt netg2938 g2938_1 g2938_0 gnd
+C1  g2938_1 gnd 2.080806f
+C2  g2938_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2938_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 4 g2938_1 2.224404
+.ends
+
+.subckt netg4964 g4964_1 g4964_2 g4964_0 gnd
+C1  g4964_1 gnd 2.080806f
+C2  g4964_2 gnd 2.080806f
+C3  g4964_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g4964_0 2.224404
+R2 g4964_2 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g4964_0 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+R5 g4964_1 3 2.224404
+.ends
+
+.subckt netg2848 g2848_1 g2848_0 gnd
+C1  g2848_1 gnd 2.080806f
+C2  g2848_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2848_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 4 g2848_1 2.224404
+.ends
+
+.subckt netg1101 g1101_1 g1101_0 gnd
+C1  g1101_1 gnd 2.080806f
+C2  g1101_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1101_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 g1101_1 4 2.224404
+.ends
+
+.subckt netg1458 g1458_1 g1458_0 gnd
+C1  g1458_1 gnd 2.080806f
+C2  g1458_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1458_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 g1458_1 4 2.224404
+.ends
+
+.subckt netg5095 g5095_2 g5095_1 g5095_0 gnd
+C1  g5095_2 gnd 2.080806f
+C2  g5095_1 gnd 2.080806f
+C3  g5095_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5095_0 2.224404
+R2 g5095_2 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g5095_2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g5095_1 2.224404
+.ends
+
+.subckt netg3483 g3483_1 g3483_0 gnd
+C1  g3483_1 gnd 2.080806f
+C2  g3483_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3483_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 g3483_1 4 2.224404
+.ends
+
+.subckt netg4188 g4188_0 g4188_1 gnd
+C1  g4188_0 gnd 2.080806f
+C2  g4188_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4188_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 4 g4188_1 2.224404
+.ends
+
+.subckt netg3002 g3002_1 g3002_0 gnd
+C1  g3002_1 gnd 2.080806f
+C2  g3002_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3002_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 4 g3002_1 2.224404
+.ends
+
+.subckt netg5464 g5464_1 g5464_0 gnd
+C1  g5464_1 gnd 2.080806f
+C2  g5464_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5464_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 g5464_1 4 2.224404
+.ends
+
+.subckt netg2522 g2522_2 g2522_1 g2522_0 gnd
+C1  g2522_2 gnd 2.080806f
+C2  g2522_1 gnd 2.080806f
+C3  g2522_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g2522_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g2522_1 2 2.224404
+C6 3 gnd 2.080806f
+R4 g2522_1 3 2.224404
+R5 g2522_2 3 2.224404
+.ends
+
+.subckt netg1330 g1330_6 g1330_5 g1330_4 g1330_0 g1330_3 g1330_1 gnd
+C1  g1330_6 gnd 2.080806f
+C2  g1330_5 gnd 2.080806f
+C3  g1330_4 gnd 2.080806f
+C4  g1330_0 gnd 2.080806f
+C5  g1330_3 gnd 2.080806f
+C6  g1330_1 gnd 2.080806f
+R1 g1330_0 g1330_5 2.224404
+R2 g1330_6 g1330_0 2.224404
+R3 g1330_3 g1330_6 2.224404
+R4 g1330_3 g1330_1 2.224404
+R5 g1330_4 g1330_3 2.224404
+.ends
+
+.subckt netg5272 g5272_0 g5272_1 gnd
+C1  g5272_0 gnd 2.080806f
+C2  g5272_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5272_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 4 g5272_1 2.224404
+.ends
+
+.subckt netg5761 g5761_0 g5761_1 g5761_2 gnd
+C1  g5761_0 gnd 2.080806f
+C2  g5761_1 gnd 2.080806f
+C3  g5761_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5761_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g5761_2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g5761_1 2.224404
+.ends
+
+.subckt netg1152 g1152_0 g1152_1 gnd
+C1  g1152_0 gnd 2.080806f
+C2  g1152_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1152_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 g1152_1 4 2.224404
+.ends
+
+.subckt netg7411 g7411_0 g7411_1 gnd
+C1  g7411_0 gnd 2.080806f
+C2  g7411_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7411_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 4 g7411_1 2.224404
+.ends
+
+.subckt netg1120 g1120_1 g1120_0 gnd
+C1  g1120_1 gnd 2.080806f
+C2  g1120_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1120_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 4 g1120_1 2.224404
+.ends
+
+.subckt netg5881 g5881_2 g5881_1 g5881_0 gnd
+C1  g5881_2 gnd 2.080806f
+C2  g5881_1 gnd 2.080806f
+C3  g5881_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5881_0 2.224404
+R2 1 g5881_2 2.224404
+C5 2 gnd 2.080806f
+R3 g5881_0 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 4 g5881_1 2.224404
+.ends
+
+.subckt netx541 x541_1 x541_0 gnd
+C1  x541_1 gnd 2.080806f
+C2  x541_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x541_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 x541_1 4 2.224404
+.ends
+
+.subckt netg5894 g5894_1 g5894_2 g5894_0 gnd
+C1  g5894_1 gnd 2.080806f
+C2  g5894_2 gnd 2.080806f
+C3  g5894_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5894_0 1 2.224404
+R2 1 g5894_1 2.224404
+C5 2 gnd 2.080806f
+R3 g5894_0 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g5894_2 2.224404
+.ends
+
+.subckt netg6269 g6269_0 g6269_2 g6269_1 gnd
+C1  g6269_0 gnd 2.080806f
+C2  g6269_2 gnd 2.080806f
+C3  g6269_1 gnd 2.080806f
+R1 g6269_0 g6269_2 2.224404
+C4 1 gnd 2.080806f
+R2 g6269_2 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g6269_1 2.224404
+.ends
+
+.subckt netg6990 g6990_1 g6990_2 g6990_0 gnd
+C1  g6990_1 gnd 2.080806f
+C2  g6990_2 gnd 2.080806f
+C3  g6990_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g6990_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 g6990_1 3 2.224404
+C7 4 gnd 2.080806f
+R5 4 g6990_1 2.224404
+R6 g6990_2 4 2.224404
+.ends
+
+.subckt netg7366 g7366_0 g7366_2 g7366_1 gnd
+C1  g7366_0 gnd 2.080806f
+C2  g7366_2 gnd 2.080806f
+C3  g7366_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g7366_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g7366_1 2 2.224404
+C6 3 gnd 2.080806f
+R4 3 g7366_0 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+R6 g7366_2 4 2.224404
+.ends
+
+.subckt netg7158 g7158_1 g7158_2 g7158_0 gnd
+C1  g7158_1 gnd 2.080806f
+C2  g7158_2 gnd 2.080806f
+C3  g7158_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g7158_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g7158_1 2 2.224404
+C6 3 gnd 2.080806f
+R4 3 g7158_1 2.224404
+R5 g7158_2 3 2.224404
+.ends
+
+.subckt netg5220 g5220_0 g5220_2 g5220_1 gnd
+C1  g5220_0 gnd 2.080806f
+C2  g5220_2 gnd 2.080806f
+C3  g5220_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5220_0 1 2.224404
+R2 1 g5220_1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g5220_1 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g5220_2 2.224404
+.ends
+
+.subckt netg3255 g3255_2 g3255_1 g3255_0 gnd
+C1  g3255_2 gnd 2.080806f
+C2  g3255_1 gnd 2.080806f
+C3  g3255_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g3255_0 1 2.224404
+R2 1 g3255_2 2.224404
+C5 2 gnd 2.080806f
+R3 2 g3255_0 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+R5 g3255_1 3 2.224404
+.ends
+
+.subckt netg1344 g1344_0 g1344_1 g1344_3 g1344_2 g1344_5 g1344_4 gnd
+C1  g1344_0 gnd 2.080806f
+C2  g1344_1 gnd 2.080806f
+C3  g1344_3 gnd 2.080806f
+C4  g1344_2 gnd 2.080806f
+C5  g1344_5 gnd 2.080806f
+C6  g1344_4 gnd 2.080806f
+R1 g1344_0 g1344_3 2.224404
+C7 1 gnd 2.080806f
+R2 1 g1344_0 2.224404
+R3 g1344_1 1 2.224404
+C8 2 gnd 2.080806f
+R4 g1344_3 2 2.224404
+R5 2 g1344_2 2.224404
+C9 3 gnd 2.080806f
+R6 g1344_1 3 2.224404
+R7 3 g1344_5 2.224404
+R8 g1344_5 g1344_4 2.224404
+.ends
+
+.subckt netg5926 g5926_1 g5926_2 g5926_0 gnd
+C1  g5926_1 gnd 2.080806f
+C2  g5926_2 gnd 2.080806f
+C3  g5926_0 gnd 2.080806f
+R1 g5926_1 g5926_0 2.224404
+C4 1 gnd 2.080806f
+R2 g5926_0 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g5926_2 2.224404
+.ends
+
+.subckt netg487 g487_0 g487_1 gnd
+C1  g487_0 gnd 2.080806f
+C2  g487_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g487_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 g487_1 4 2.224404
+.ends
+
+.subckt netg5891 g5891_1 g5891_2 g5891_0 gnd
+C1  g5891_1 gnd 2.080806f
+C2  g5891_2 gnd 2.080806f
+C3  g5891_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5891_0 2.224404
+R2 g5891_2 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g5891_2 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+R5 g5891_1 3 2.224404
+.ends
+
+.subckt netg7303 g7303_2 g7303_1 g7303_0 gnd
+C1  g7303_2 gnd 2.080806f
+C2  g7303_1 gnd 2.080806f
+C3  g7303_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g7303_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g7303_1 2.224404
+C6 3 gnd 2.080806f
+R4 g7303_1 3 2.224404
+R5 3 g7303_2 2.224404
+.ends
+
+.subckt netg4756 g4756_0 g4756_3 g4756_2 g4756_1 gnd
+C1  g4756_0 gnd 2.080806f
+C2  g4756_3 gnd 2.080806f
+C3  g4756_2 gnd 2.080806f
+C4  g4756_1 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g4756_0 2.224404
+R2 g4756_3 1 2.224404
+R3 g4756_1 g4756_3 2.224404
+C6 2 gnd 2.080806f
+R4 1 2 2.224404
+R5 2 g4756_2 2.224404
+.ends
+
+.subckt netg5758 g5758_0 g5758_1 g5758_2 gnd
+C1  g5758_0 gnd 2.080806f
+C2  g5758_1 gnd 2.080806f
+C3  g5758_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5758_0 2.224404
+R2 g5758_2 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g5758_2 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+R5 g5758_1 3 2.224404
+.ends
+
+.subckt netg5478 g5478_1 g5478_0 gnd
+C1  g5478_1 gnd 2.080806f
+C2  g5478_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5478_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 g5478_1 4 2.224404
+.ends
+
+.subckt netg5613 g5613_0 g5613_1 g5613_2 gnd
+C1  g5613_0 gnd 2.080806f
+C2  g5613_1 gnd 2.080806f
+C3  g5613_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5613_0 2.224404
+R2 g5613_2 1 2.224404
+C5 2 gnd 2.080806f
+R3 g5613_0 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g5613_1 2.224404
+.ends
+
+.subckt netg4661 g4661_1 g4661_0 gnd
+C1  g4661_1 gnd 2.080806f
+C2  g4661_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4661_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 4 g4661_1 2.224404
+.ends
+
+.subckt netg2650 g2650_1 g2650_0 g2650_2 gnd
+C1  g2650_1 gnd 2.080806f
+C2  g2650_0 gnd 2.080806f
+C3  g2650_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g2650_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g2650_2 2.224404
+R5 g2650_2 g2650_1 2.224404
+.ends
+
+.subckt netg100 g100_0 g100_1 gnd
+C1  g100_0 gnd 2.080806f
+C2  g100_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g100_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 g100_1 4 2.224404
+.ends
+
+.subckt netg6631 g6631_1 g6631_2 g6631_0 gnd
+C1  g6631_1 gnd 2.080806f
+C2  g6631_2 gnd 2.080806f
+C3  g6631_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g6631_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g6631_2 3 2.224404
+R5 g6631_1 g6631_2 2.224404
+.ends
+
+.subckt netg6346 g6346_1 g6346_3 g6346_0 gnd
+C1  g6346_1 gnd 2.080806f
+C2  g6346_3 gnd 2.080806f
+C3  g6346_0 gnd 2.080806f
+R1 g6346_0 g6346_1 2.224404
+C4 1 gnd 2.080806f
+R2 g6346_0 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g6346_3 2.224404
+.ends
+
+.subckt netg5930 g5930_1 g5930_0 gnd
+C1  g5930_1 gnd 2.080806f
+C2  g5930_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5930_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 4 g5930_1 2.224404
+.ends
+
+.subckt netg5688 g5688_0 g5688_2 g5688_1 gnd
+C1  g5688_0 gnd 2.080806f
+C2  g5688_2 gnd 2.080806f
+C3  g5688_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5688_0 1 2.224404
+R2 1 g5688_1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g5688_0 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+R5 g5688_2 3 2.224404
+.ends
+
+.subckt netg6023 g6023_1 g6023_0 g6023_2 gnd
+C1  g6023_1 gnd 2.080806f
+C2  g6023_0 gnd 2.080806f
+C3  g6023_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g6023_0 1 2.224404
+R2 g6023_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g6023_0 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+R5 3 g6023_2 2.224404
+.ends
+
+.subckt netg2423 g2423_2 g2423_1 g2423_0 gnd
+C1  g2423_2 gnd 2.080806f
+C2  g2423_1 gnd 2.080806f
+C3  g2423_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g2423_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g2423_2 2 2.224404
+C6 3 gnd 2.080806f
+R4 3 g2423_2 2.224404
+R5 g2423_1 3 2.224404
+.ends
+
+.subckt netg1404 g1404_1 g1404_0 gnd
+C1  g1404_1 gnd 2.080806f
+C2  g1404_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1404_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 g1404_1 4 2.224404
+.ends
+
+.subckt netg6818 g6818_1 g6818_0 gnd
+C1  g6818_1 gnd 2.080806f
+C2  g6818_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6818_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 g6818_1 4 2.224404
+.ends
+
+.subckt netg747 g747_3 g747_1 g747_4 g747_2 g747_0 gnd
+C1  g747_3 gnd 2.080806f
+C2  g747_1 gnd 2.080806f
+C3  g747_4 gnd 2.080806f
+C4  g747_2 gnd 2.080806f
+C5  g747_0 gnd 2.080806f
+R1 g747_0 g747_2 2.224404
+R2 g747_3 g747_0 2.224404
+R3 g747_4 g747_0 2.224404
+C6 1 gnd 2.080806f
+R4 1 g747_3 2.224404
+C7 2 gnd 2.080806f
+R5 2 1 2.224404
+R6 g747_1 2 2.224404
+.ends
+
+.subckt netg6147 g6147_2 g6147_0 g6147_1 gnd
+C1  g6147_2 gnd 2.080806f
+C2  g6147_0 gnd 2.080806f
+C3  g6147_1 gnd 2.080806f
+R1 g6147_0 g6147_2 2.224404
+C4 1 gnd 2.080806f
+R2 g6147_0 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g6147_1 2.224404
+.ends
+
+.subckt netg2761 g2761_1 g2761_0 gnd
+C1  g2761_1 gnd 2.080806f
+C2  g2761_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2761_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 4 g2761_1 2.224404
+.ends
+
+.subckt netg5431 g5431_0 g5431_2 g5431_1 gnd
+C1  g5431_0 gnd 2.080806f
+C2  g5431_2 gnd 2.080806f
+C3  g5431_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5431_0 1 2.224404
+R2 1 g5431_2 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g5431_1 2.224404
+.ends
+
+.subckt netg6481 g6481_1 g6481_2 g6481_0 gnd
+C1  g6481_1 gnd 2.080806f
+C2  g6481_2 gnd 2.080806f
+C3  g6481_0 gnd 2.080806f
+R1 g6481_0 g6481_2 2.224404
+C4 1 gnd 2.080806f
+R2 1 g6481_0 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+R5 g6481_1 3 2.224404
+.ends
+
+.subckt netg7551 g7551_1 g7551_0 gnd
+C1  g7551_1 gnd 2.080806f
+C2  g7551_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7551_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 g7551_1 4 2.224404
+.ends
+
+.subckt netg4030 g4030_0 g4030_3 g4030_1 g4030_2 gnd
+C1  g4030_0 gnd 2.080806f
+C2  g4030_3 gnd 2.080806f
+C3  g4030_1 gnd 2.080806f
+C4  g4030_2 gnd 2.080806f
+R1 g4030_0 g4030_1 2.224404
+C5 1 gnd 2.080806f
+R2 g4030_1 1 2.224404
+C6 2 gnd 2.080806f
+R3 1 2 2.224404
+R4 2 g4030_3 2.224404
+R5 g4030_3 g4030_2 2.224404
+.ends
+
+.subckt netg5743 g5743_0 g5743_2 g5743_1 gnd
+C1  g5743_0 gnd 2.080806f
+C2  g5743_2 gnd 2.080806f
+C3  g5743_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5743_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g5743_1 2.224404
+C6 3 gnd 2.080806f
+R4 g5743_1 3 2.224404
+R5 3 g5743_2 2.224404
+.ends
+
+.subckt netg3482 g3482_1 g3482_0 gnd
+C1  g3482_1 gnd 2.080806f
+C2  g3482_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3482_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 4 g3482_1 2.224404
+.ends
+
+.subckt netg1286 g1286_1 g1286_0 gnd
+C1  g1286_1 gnd 2.080806f
+C2  g1286_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1286_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 g1286_1 4 2.224404
+.ends
+
+.subckt netg4422 g4422_0 g4422_1 gnd
+C1  g4422_0 gnd 2.080806f
+C2  g4422_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4422_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 g4422_1 4 2.224404
+.ends
+
+.subckt netg2668 g2668_2 g2668_0 gnd
+C1  g2668_2 gnd 2.080806f
+C2  g2668_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2668_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 4 g2668_2 2.224404
+.ends
+
+.subckt netg7065 g7065_1 g7065_0 g7065_2 gnd
+C1  g7065_1 gnd 2.080806f
+C2  g7065_0 gnd 2.080806f
+C3  g7065_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g7065_0 1 2.224404
+R2 1 g7065_1 2.224404
+C5 2 gnd 2.080806f
+R3 g7065_1 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g7065_2 2.224404
+.ends
+
+.subckt netg4368 g4368_1 g4368_0 g4368_2 gnd
+C1  g4368_1 gnd 2.080806f
+C2  g4368_0 gnd 2.080806f
+C3  g4368_2 gnd 2.080806f
+R1 g4368_0 g4368_1 2.224404
+C4 1 gnd 2.080806f
+R2 g4368_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g4368_2 2.224404
+.ends
+
+.subckt netg4913 g4913_2 g4913_1 g4913_3 gnd
+C1  g4913_2 gnd 2.080806f
+C2  g4913_1 gnd 2.080806f
+C3  g4913_3 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g4913_2 2.224404
+R2 g4913_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+R5 g4913_3 3 2.224404
+.ends
+
+.subckt netg3106 g3106_0 g3106_2 g3106_1 gnd
+C1  g3106_0 gnd 2.080806f
+C2  g3106_2 gnd 2.080806f
+C3  g3106_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g3106_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g3106_1 2.224404
+C6 3 gnd 2.080806f
+R4 1 3 2.224404
+R5 3 g3106_2 2.224404
+.ends
+
+.subckt netg3374 g3374_0 g3374_1 g3374_2 gnd
+C1  g3374_0 gnd 2.080806f
+C2  g3374_1 gnd 2.080806f
+C3  g3374_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g3374_0 2.224404
+R2 g3374_2 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g3374_2 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+R5 g3374_1 3 2.224404
+.ends
+
+.subckt netg1986 g1986_1 g1986_0 g1986_2 g1986_3 gnd
+C1  g1986_1 gnd 2.080806f
+C2  g1986_0 gnd 2.080806f
+C3  g1986_2 gnd 2.080806f
+C4  g1986_3 gnd 2.080806f
+R1 g1986_2 g1986_0 2.224404
+C5 1 gnd 2.080806f
+R2 g1986_0 1 2.224404
+R3 1 g1986_1 2.224404
+C6 2 gnd 2.080806f
+R4 2 g1986_2 2.224404
+R5 g1986_3 2 2.224404
+.ends
+
+.subckt netg1484 g1484_1 g1484_5 g1484_4 g1484_0 g1484_2 gnd
+C1  g1484_1 gnd 2.080806f
+C2  g1484_5 gnd 2.080806f
+C3  g1484_4 gnd 2.080806f
+C4  g1484_0 gnd 2.080806f
+C5  g1484_2 gnd 2.080806f
+R1 g1484_2 g1484_0 2.224404
+C6 1 gnd 2.080806f
+R2 g1484_2 1 2.224404
+R3 1 g1484_4 2.224404
+C7 2 gnd 2.080806f
+R4 g1484_4 2 2.224404
+R5 2 g1484_1 2.224404
+R6 2 g1484_5 2.224404
+.ends
+
+.subckt netg5174 g5174_2 g5174_1 g5174_0 gnd
+C1  g5174_2 gnd 2.080806f
+C2  g5174_1 gnd 2.080806f
+C3  g5174_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5174_0 2.224404
+R2 1 g5174_1 2.224404
+C5 2 gnd 2.080806f
+R3 g5174_0 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g5174_2 2.224404
+.ends
+
+.subckt netg4400 g4400_0 g4400_1 gnd
+C1  g4400_0 gnd 2.080806f
+C2  g4400_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4400_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 4 g4400_1 2.224404
+.ends
+
+.subckt netg6867 g6867_1 g6867_2 g6867_0 gnd
+C1  g6867_1 gnd 2.080806f
+C2  g6867_2 gnd 2.080806f
+C3  g6867_0 gnd 2.080806f
+R1 g6867_0 g6867_2 2.224404
+C4 1 gnd 2.080806f
+R2 g6867_0 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 g6867_1 3 2.224404
+.ends
+
+.subckt netg5352 g5352_1 g5352_0 gnd
+C1  g5352_1 gnd 2.080806f
+C2  g5352_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5352_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 g5352_1 4 2.224404
+.ends
+
+.subckt netg973 g973_2 g973_1 g973_0 gnd
+C1  g973_2 gnd 2.080806f
+C2  g973_1 gnd 2.080806f
+C3  g973_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g973_0 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g973_1 2.224404
+C6 3 gnd 2.080806f
+R4 g973_1 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 4 g973_2 2.224404
+.ends
+
+.subckt netg4017 g4017_1 g4017_0 gnd
+C1  g4017_1 gnd 2.080806f
+C2  g4017_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4017_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 4 g4017_1 2.224404
+.ends
+
+.subckt netg3068 g3068_1 g3068_0 gnd
+C1  g3068_1 gnd 2.080806f
+C2  g3068_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3068_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 4 g3068_1 2.224404
+.ends
+
+.subckt netg3189 g3189_1 g3189_2 g3189_0 gnd
+C1  g3189_1 gnd 2.080806f
+C2  g3189_2 gnd 2.080806f
+C3  g3189_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g3189_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g3189_1 2.224404
+C6 3 gnd 2.080806f
+R4 3 g3189_1 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 4 g3189_2 2.224404
+.ends
+
+.subckt netg5479 g5479_1 g5479_0 gnd
+C1  g5479_1 gnd 2.080806f
+C2  g5479_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5479_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 g5479_1 4 2.224404
+.ends
+
+.subckt netg4917 g4917_2 g4917_0 g4917_1 gnd
+C1  g4917_2 gnd 2.080806f
+C2  g4917_0 gnd 2.080806f
+C3  g4917_1 gnd 2.080806f
+R1 g4917_0 g4917_1 2.224404
+C4 1 gnd 2.080806f
+R2 g4917_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g4917_2 2.224404
+.ends
+
+.subckt netg5437 g5437_2 g5437_0 g5437_1 gnd
+C1  g5437_2 gnd 2.080806f
+C2  g5437_0 gnd 2.080806f
+C3  g5437_1 gnd 2.080806f
+R1 g5437_2 g5437_0 2.224404
+C4 1 gnd 2.080806f
+R2 g5437_0 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g5437_1 2.224404
+.ends
+
+.subckt netg1287 g1287_1 g1287_0 gnd
+C1  g1287_1 gnd 2.080806f
+C2  g1287_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1287_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 4 g1287_1 2.224404
+.ends
+
+.subckt netg4429 g4429_0 g4429_2 g4429_1 gnd
+C1  g4429_0 gnd 2.080806f
+C2  g4429_2 gnd 2.080806f
+C3  g4429_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g4429_0 1 2.224404
+R2 1 g4429_1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g4429_1 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+R5 g4429_2 3 2.224404
+.ends
+
+.subckt netg1911 g1911_1 g1911_0 gnd
+C1  g1911_1 gnd 2.080806f
+C2  g1911_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1911_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 g1911_1 4 2.224404
+.ends
+
+.subckt netg1150 g1150_1 g1150_0 gnd
+C1  g1150_1 gnd 2.080806f
+C2  g1150_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1150_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 g1150_1 4 2.224404
+.ends
+
+.subckt netg2230 g2230_1 g2230_0 gnd
+C1  g2230_1 gnd 2.080806f
+C2  g2230_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2230_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 4 g2230_1 2.224404
+.ends
+
+.subckt netg110 g110_0 g110_1 gnd
+C1  g110_0 gnd 2.080806f
+C2  g110_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g110_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 g110_1 4 2.224404
+.ends
+
+.subckt netg6864 g6864_1 g6864_0 g6864_2 gnd
+C1  g6864_1 gnd 2.080806f
+C2  g6864_0 gnd 2.080806f
+C3  g6864_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g6864_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g6864_2 2 2.224404
+C6 3 gnd 2.080806f
+R4 g6864_2 3 2.224404
+R5 3 g6864_1 2.224404
+.ends
+
+.subckt netg5900 g5900_0 g5900_1 g5900_2 gnd
+C1  g5900_0 gnd 2.080806f
+C2  g5900_1 gnd 2.080806f
+C3  g5900_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5900_0 2.224404
+R2 1 g5900_2 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+R5 g5900_1 3 2.224404
+.ends
+
+.subckt netg1912 g1912_0 g1912_1 gnd
+C1  g1912_0 gnd 2.080806f
+C2  g1912_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1912_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 g1912_1 4 2.224404
+.ends
+
+.subckt netg2567 g2567_1 g2567_2 g2567_0 gnd
+C1  g2567_1 gnd 2.080806f
+C2  g2567_2 gnd 2.080806f
+C3  g2567_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g2567_0 1 2.224404
+R2 g2567_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g2567_0 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+R5 g2567_2 3 2.224404
+.ends
+
+.subckt netg5572 g5572_2 g5572_1 gnd
+C1  g5572_2 gnd 2.080806f
+C2  g5572_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5572_1 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 4 g5572_2 2.224404
+.ends
+
+.subckt netg6350 g6350_0 g6350_1 gnd
+C1  g6350_0 gnd 2.080806f
+C2  g6350_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6350_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 g6350_1 4 2.224404
+.ends
+
+.subckt netg4193 g4193_2 g4193_1 g4193_0 gnd
+C1  g4193_2 gnd 2.080806f
+C2  g4193_1 gnd 2.080806f
+C3  g4193_0 gnd 2.080806f
+R1 g4193_0 g4193_2 2.224404
+C4 1 gnd 2.080806f
+R2 1 g4193_0 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 g4193_1 3 2.224404
+.ends
+
+.subckt netg4778 g4778_2 g4778_0 g4778_1 gnd
+C1  g4778_2 gnd 2.080806f
+C2  g4778_0 gnd 2.080806f
+C3  g4778_1 gnd 2.080806f
+R1 g4778_0 g4778_1 2.224404
+C4 1 gnd 2.080806f
+R2 g4778_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g4778_2 2.224404
+.ends
+
+.subckt netg1719 g1719_1 g1719_2 g1719_3 gnd
+C1  g1719_1 gnd 2.080806f
+C2  g1719_2 gnd 2.080806f
+C3  g1719_3 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g1719_2 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g1719_3 3 2.224404
+R5 g1719_3 g1719_1 2.224404
+.ends
+
+.subckt netg7287 g7287_1 g7287_0 g7287_2 gnd
+C1  g7287_1 gnd 2.080806f
+C2  g7287_0 gnd 2.080806f
+C3  g7287_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g7287_0 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g7287_1 2.224404
+C6 3 gnd 2.080806f
+R4 g7287_1 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 4 g7287_2 2.224404
+.ends
+
+.subckt netg6407 g6407_1 g6407_0 gnd
+C1  g6407_1 gnd 2.080806f
+C2  g6407_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6407_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 4 g6407_1 2.224404
+.ends
+
+.subckt netg3522 g3522_1 g3522_0 gnd
+C1  g3522_1 gnd 2.080806f
+C2  g3522_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3522_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 4 g3522_1 2.224404
+.ends
+
+.subckt netg5652 g5652_0 g5652_1 g5652_2 gnd
+C1  g5652_0 gnd 2.080806f
+C2  g5652_1 gnd 2.080806f
+C3  g5652_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5652_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g5652_2 2 2.224404
+C6 3 gnd 2.080806f
+R4 3 g5652_2 2.224404
+R5 g5652_1 3 2.224404
+.ends
+
+.subckt netg3490 g3490_1 g3490_0 gnd
+C1  g3490_1 gnd 2.080806f
+C2  g3490_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3490_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 4 g3490_1 2.224404
+.ends
+
+.subckt netg5749 g5749_0 g5749_2 g5749_1 gnd
+C1  g5749_0 gnd 2.080806f
+C2  g5749_2 gnd 2.080806f
+C3  g5749_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5749_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g5749_1 2 2.224404
+C6 3 gnd 2.080806f
+R4 3 g5749_1 2.224404
+R5 g5749_2 3 2.224404
+.ends
+
+.subckt netg2383 g2383_0 g2383_2 g2383_1 gnd
+C1  g2383_0 gnd 2.080806f
+C2  g2383_2 gnd 2.080806f
+C3  g2383_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g2383_0 2.224404
+R2 1 g2383_1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g2383_1 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+R5 g2383_2 3 2.224404
+.ends
+
+.subckt netg5631 g5631_1 g5631_0 g5631_2 gnd
+C1  g5631_1 gnd 2.080806f
+C2  g5631_0 gnd 2.080806f
+C3  g5631_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5631_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g5631_1 2.224404
+R5 g5631_1 g5631_2 2.224404
+.ends
+
+.subckt netg4078 g4078_0 g4078_3 g4078_2 g4078_1 gnd
+C1  g4078_0 gnd 2.080806f
+C2  g4078_3 gnd 2.080806f
+C3  g4078_2 gnd 2.080806f
+C4  g4078_1 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g4078_0 1 2.224404
+R2 1 g4078_2 2.224404
+C6 2 gnd 2.080806f
+R3 g4078_2 2 2.224404
+R4 2 g4078_3 2.224404
+R5 g4078_3 g4078_1 2.224404
+.ends
+
+.subckt netg7423 g7423_0 g7423_1 gnd
+C1  g7423_0 gnd 2.080806f
+C2  g7423_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7423_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 g7423_1 4 2.224404
+.ends
+
+.subckt netg4196 g4196_1 g4196_2 gnd
+C1  g4196_1 gnd 2.080806f
+C2  g4196_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4196_1 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 g4196_2 4 2.224404
+.ends
+
+.subckt netg3528 g3528_1 g3528_0 gnd
+C1  g3528_1 gnd 2.080806f
+C2  g3528_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3528_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 4 g3528_1 2.224404
+.ends
+
+.subckt netg5984 g5984_0 g5984_1 gnd
+C1  g5984_0 gnd 2.080806f
+C2  g5984_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5984_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 g5984_1 4 2.224404
+.ends
+
+.subckt netg3210 g3210_1 g3210_2 gnd
+C1  g3210_1 gnd 2.080806f
+C2  g3210_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3210_1 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 g3210_2 4 2.224404
+.ends
+
+.subckt netg5655 g5655_0 g5655_1 g5655_2 gnd
+C1  g5655_0 gnd 2.080806f
+C2  g5655_1 gnd 2.080806f
+C3  g5655_2 gnd 2.080806f
+R1 g5655_2 g5655_0 2.224404
+C4 1 gnd 2.080806f
+R2 g5655_0 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 g5655_1 3 2.224404
+.ends
+
+.subckt netg4074 g4074_3 g4074_1 g4074_2 g4074_0 gnd
+C1  g4074_3 gnd 2.080806f
+C2  g4074_1 gnd 2.080806f
+C3  g4074_2 gnd 2.080806f
+C4  g4074_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g4074_0 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g4074_2 2 2.224404
+C7 3 gnd 2.080806f
+R4 1 3 2.224404
+R5 3 g4074_3 2.224404
+R6 g4074_1 g4074_3 2.224404
+.ends
+
+.subckt netg5202 g5202_1 g5202_0 g5202_2 gnd
+C1  g5202_1 gnd 2.080806f
+C2  g5202_0 gnd 2.080806f
+C3  g5202_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5202_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g5202_2 3 2.224404
+R5 g5202_1 g5202_2 2.224404
+.ends
+
+.subckt netg6442 g6442_1 g6442_2 g6442_0 gnd
+C1  g6442_1 gnd 2.080806f
+C2  g6442_2 gnd 2.080806f
+C3  g6442_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g6442_0 2.224404
+R2 g6442_2 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g6442_2 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+R5 g6442_1 3 2.224404
+.ends
+
+.subckt netg3291 g3291_2 g3291_0 g3291_1 gnd
+C1  g3291_2 gnd 2.080806f
+C2  g3291_0 gnd 2.080806f
+C3  g3291_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g3291_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g3291_1 2 2.224404
+C6 3 gnd 2.080806f
+R4 g3291_1 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 g3291_2 4 2.224404
+.ends
+
+.subckt netg907 g907_2 g907_1 g907_0 gnd
+C1  g907_2 gnd 2.080806f
+C2  g907_1 gnd 2.080806f
+C3  g907_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g907_0 2.224404
+R2 g907_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g907_0 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+R5 3 g907_2 2.224404
+.ends
+
+.subckt netg5637 g5637_0 g5637_2 g5637_1 gnd
+C1  g5637_0 gnd 2.080806f
+C2  g5637_2 gnd 2.080806f
+C3  g5637_1 gnd 2.080806f
+R1 g5637_0 g5637_2 2.224404
+C4 1 gnd 2.080806f
+R2 g5637_2 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g5637_1 2.224404
+.ends
+
+.subckt netg4232 g4232_1 g4232_0 gnd
+C1  g4232_1 gnd 2.080806f
+C2  g4232_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4232_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 4 g4232_1 2.224404
+.ends
+
+.subckt netx141 x141_0 x141_1 gnd
+C1  x141_0 gnd 2.080806f
+C2  x141_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x141_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 x141_1 4 2.224404
+.ends
+
+.subckt netg4449 g4449_1 g4449_0 gnd
+C1  g4449_1 gnd 2.080806f
+C2  g4449_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4449_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 4 g4449_1 2.224404
+.ends
+
+.subckt netg2671 g2671_1 g2671_0 g2671_2 gnd
+C1  g2671_1 gnd 2.080806f
+C2  g2671_0 gnd 2.080806f
+C3  g2671_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g2671_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g2671_1 2.224404
+C6 3 gnd 2.080806f
+R4 3 g2671_1 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 4 g2671_2 2.224404
+.ends
+
+.subckt netg2365 g2365_0 g2365_2 g2365_1 gnd
+C1  g2365_0 gnd 2.080806f
+C2  g2365_2 gnd 2.080806f
+C3  g2365_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g2365_0 2.224404
+R2 1 g2365_1 2.224404
+C5 2 gnd 2.080806f
+R3 g2365_0 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 4 g2365_2 2.224404
+.ends
+
+.subckt netg5610 g5610_0 g5610_2 g5610_1 gnd
+C1  g5610_0 gnd 2.080806f
+C2  g5610_2 gnd 2.080806f
+C3  g5610_1 gnd 2.080806f
+R1 g5610_1 g5610_0 2.224404
+C4 1 gnd 2.080806f
+R2 g5610_0 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g5610_2 2.224404
+.ends
+
+.subckt netg5309 g5309_0 g5309_1 g5309_3 g5309_2 gnd
+C1  g5309_0 gnd 2.080806f
+C2  g5309_1 gnd 2.080806f
+C3  g5309_3 gnd 2.080806f
+C4  g5309_2 gnd 2.080806f
+R1 g5309_3 g5309_0 2.224404
+R2 g5309_2 g5309_3 2.224404
+C5 1 gnd 2.080806f
+R3 g5309_0 1 2.224404
+C6 2 gnd 2.080806f
+R4 2 1 2.224404
+C7 3 gnd 2.080806f
+R5 2 3 2.224404
+R6 g5309_1 3 2.224404
+.ends
+
+.subckt netg413 g413_1 g413_2 g413_0 g413_3 g413_4 gnd
+C1  g413_1 gnd 2.080806f
+C2  g413_2 gnd 2.080806f
+C3  g413_0 gnd 2.080806f
+C4  g413_3 gnd 2.080806f
+C5  g413_4 gnd 2.080806f
+R1 g413_1 g413_0 2.224404
+C6 1 gnd 2.080806f
+R2 g413_0 1 2.224404
+R3 1 g413_3 2.224404
+C7 2 gnd 2.080806f
+R4 2 g413_3 2.224404
+R5 g413_4 2 2.224404
+R6 g413_4 g413_2 2.224404
+.ends
+
+.subckt netg6880 g6880_1 g6880_0 gnd
+C1  g6880_1 gnd 2.080806f
+C2  g6880_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6880_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 4 g6880_1 2.224404
+.ends
+
+.subckt netg3432 g3432_1 g3432_0 g3432_2 gnd
+C1  g3432_1 gnd 2.080806f
+C2  g3432_0 gnd 2.080806f
+C3  g3432_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g3432_0 1 2.224404
+R2 g3432_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g3432_2 2.224404
+.ends
+
+.subckt netg4161 g4161_1 g4161_2 g4161_0 gnd
+C1  g4161_1 gnd 2.080806f
+C2  g4161_2 gnd 2.080806f
+C3  g4161_0 gnd 2.080806f
+R1 g4161_0 g4161_2 2.224404
+C4 1 gnd 2.080806f
+R2 1 g4161_0 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+R5 g4161_1 3 2.224404
+.ends
+
+.subckt netg3462 g3462_0 g3462_1 g3462_2 gnd
+C1  g3462_0 gnd 2.080806f
+C2  g3462_1 gnd 2.080806f
+C3  g3462_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g3462_0 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g3462_1 2.224404
+C6 3 gnd 2.080806f
+R4 g3462_1 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 4 g3462_2 2.224404
+.ends
+
+.subckt netg1575 g1575_1 g1575_0 gnd
+C1  g1575_1 gnd 2.080806f
+C2  g1575_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1575_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 g1575_1 4 2.224404
+.ends
+
+.subckt netg2088 g2088_0 g2088_1 gnd
+C1  g2088_0 gnd 2.080806f
+C2  g2088_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2088_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 g2088_1 4 2.224404
+.ends
+
+.subckt netg6754 g6754_0 g6754_2 g6754_1 gnd
+C1  g6754_0 gnd 2.080806f
+C2  g6754_2 gnd 2.080806f
+C3  g6754_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g6754_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 2 g6754_1 2.224404
+C6 3 gnd 2.080806f
+R4 g6754_1 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 4 g6754_2 2.224404
+.ends
+
+.subckt netg1529 g1529_1 g1529_0 gnd
+C1  g1529_1 gnd 2.080806f
+C2  g1529_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1529_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 5 g1529_1 2.224404
+.ends
+
+.subckt netx502 x502_0 x502_1 gnd
+C1  x502_0 gnd 2.080806f
+C2  x502_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x502_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 5 x502_1 2.224404
+.ends
+
+.subckt netg4026 g4026_2 g4026_3 g4026_1 g4026_0 gnd
+C1  g4026_2 gnd 2.080806f
+C2  g4026_3 gnd 2.080806f
+C3  g4026_1 gnd 2.080806f
+C4  g4026_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g4026_0 1 2.224404
+R2 1 g4026_1 2.224404
+R3 g4026_1 g4026_2 2.224404
+C6 2 gnd 2.080806f
+R4 2 g4026_2 2.224404
+C7 3 gnd 2.080806f
+R5 2 3 2.224404
+C8 4 gnd 2.080806f
+R6 3 4 2.224404
+R7 4 g4026_3 2.224404
+.ends
+
+.subckt netg1532 g1532_1 g1532_0 gnd
+C1  g1532_1 gnd 2.080806f
+C2  g1532_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1532_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+R6 g1532_1 5 2.224404
+.ends
+
+.subckt netg1868 g1868_2 g1868_0 gnd
+C1  g1868_2 gnd 2.080806f
+C2  g1868_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1868_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 5 g1868_2 2.224404
+.ends
+
+.subckt netg7150 g7150_2 g7150_0 g7150_1 gnd
+C1  g7150_2 gnd 2.080806f
+C2  g7150_0 gnd 2.080806f
+C3  g7150_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g7150_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g7150_2 2.224404
+C6 3 gnd 2.080806f
+R4 g7150_2 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 4 g7150_1 2.224404
+.ends
+
+.subckt netg4250 g4250_1 g4250_0 gnd
+C1  g4250_1 gnd 2.080806f
+C2  g4250_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4250_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 5 g4250_1 2.224404
+.ends
+
+.subckt netg1762 g1762_2 g1762_1 g1762_0 gnd
+C1  g1762_2 gnd 2.080806f
+C2  g1762_1 gnd 2.080806f
+C3  g1762_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g1762_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g1762_2 2.224404
+C7 4 gnd 2.080806f
+R5 g1762_2 4 2.224404
+R6 g1762_1 4 2.224404
+.ends
+
+.subckt netg2239 g2239_1 g2239_0 gnd
+C1  g2239_1 gnd 2.080806f
+C2  g2239_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2239_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 5 g2239_1 2.224404
+.ends
+
+.subckt netg3333 g3333_1 g3333_2 g3333_0 gnd
+C1  g3333_1 gnd 2.080806f
+C2  g3333_2 gnd 2.080806f
+C3  g3333_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g3333_0 2.224404
+R2 1 g3333_1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g3333_0 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+R6 g3333_2 4 2.224404
+.ends
+
+.subckt netg1364 g1364_1 g1364_0 gnd
+C1  g1364_1 gnd 2.080806f
+C2  g1364_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1364_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 g1364_1 5 2.224404
+.ends
+
+.subckt netg6075 g6075_2 g6075_0 g6075_3 g6075_1 gnd
+C1  g6075_2 gnd 2.080806f
+C2  g6075_0 gnd 2.080806f
+C3  g6075_3 gnd 2.080806f
+C4  g6075_1 gnd 2.080806f
+R1 g6075_1 g6075_0 2.224404
+C5 1 gnd 2.080806f
+R2 1 g6075_1 2.224404
+C6 2 gnd 2.080806f
+R3 1 2 2.224404
+R4 g6075_3 2 2.224404
+C7 3 gnd 2.080806f
+R5 3 g6075_3 2.224404
+C8 4 gnd 2.080806f
+R6 4 3 2.224404
+R7 g6075_2 4 2.224404
+.ends
+
+.subckt netg1896 g1896_1 g1896_0 gnd
+C1  g1896_1 gnd 2.080806f
+C2  g1896_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1896_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+R6 g1896_1 5 2.224404
+.ends
+
+.subckt netg6882 g6882_0 g6882_1 gnd
+C1  g6882_0 gnd 2.080806f
+C2  g6882_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6882_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 5 g6882_1 2.224404
+.ends
+
+.subckt netg500 g500_0 g500_1 gnd
+C1  g500_0 gnd 2.080806f
+C2  g500_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g500_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 5 g500_1 2.224404
+.ends
+
+.subckt netg5806 g5806_1 g5806_2 g5806_0 gnd
+C1  g5806_1 gnd 2.080806f
+C2  g5806_2 gnd 2.080806f
+C3  g5806_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5806_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g5806_1 2 2.224404
+C6 3 gnd 2.080806f
+R4 3 g5806_1 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+R6 g5806_2 4 2.224404
+.ends
+
+.subckt netg2647 g2647_2 g2647_1 g2647_0 gnd
+C1  g2647_2 gnd 2.080806f
+C2  g2647_1 gnd 2.080806f
+C3  g2647_0 gnd 2.080806f
+R1 g2647_0 g2647_2 2.224404
+C4 1 gnd 2.080806f
+R2 1 g2647_0 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+R6 g2647_1 4 2.224404
+.ends
+
+.subckt netg6618 g6618_0 g6618_1 g6618_2 gnd
+C1  g6618_0 gnd 2.080806f
+C2  g6618_1 gnd 2.080806f
+C3  g6618_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g6618_0 1 2.224404
+R2 1 g6618_1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g6618_1 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 4 g6618_2 2.224404
+.ends
+
+.subckt netg6911 g6911_4 g6911_1 g6911_3 g6911_2 g6911_0 gnd
+C1  g6911_4 gnd 2.080806f
+C2  g6911_1 gnd 2.080806f
+C3  g6911_3 gnd 2.080806f
+C4  g6911_2 gnd 2.080806f
+C5  g6911_0 gnd 2.080806f
+C6 1 gnd 2.080806f
+R1 1 g6911_0 2.224404
+R2 g6911_1 1 2.224404
+C7 2 gnd 2.080806f
+R3 2 g6911_0 2.224404
+R4 g6911_4 2 2.224404
+C8 3 gnd 2.080806f
+R5 g6911_4 3 2.224404
+C9 4 gnd 2.080806f
+R6 3 4 2.224404
+R7 4 g6911_3 2.224404
+R8 g6911_3 g6911_2 2.224404
+.ends
+
+.subckt netg2935 g2935_0 g2935_1 gnd
+C1  g2935_0 gnd 2.080806f
+C2  g2935_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2935_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+R6 g2935_1 5 2.224404
+.ends
+
+.subckt netg4365 g4365_1 g4365_0 g4365_2 gnd
+C1  g4365_1 gnd 2.080806f
+C2  g4365_0 gnd 2.080806f
+C3  g4365_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g4365_0 2.224404
+R2 g4365_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 4 g4365_2 2.224404
+.ends
+
+.subckt netg5897 g5897_2 g5897_1 g5897_0 gnd
+C1  g5897_2 gnd 2.080806f
+C2  g5897_1 gnd 2.080806f
+C3  g5897_0 gnd 2.080806f
+R1 g5897_1 g5897_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g5897_1 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+R6 g5897_2 4 2.224404
+.ends
+
+.subckt netg7222 g7222_2 g7222_1 g7222_0 gnd
+C1  g7222_2 gnd 2.080806f
+C2  g7222_1 gnd 2.080806f
+C3  g7222_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g7222_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 4 g7222_2 2.224404
+R6 g7222_1 g7222_2 2.224404
+.ends
+
+.subckt netg1496 g1496_1 g1496_0 gnd
+C1  g1496_1 gnd 2.080806f
+C2  g1496_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1496_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+R6 g1496_1 5 2.224404
+.ends
+
+.subckt netg7281 g7281_1 g7281_0 g7281_2 gnd
+C1  g7281_1 gnd 2.080806f
+C2  g7281_0 gnd 2.080806f
+C3  g7281_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g7281_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g7281_1 2.224404
+C6 3 gnd 2.080806f
+R4 g7281_1 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 4 g7281_2 2.224404
+.ends
+
+.subckt netg2989 g2989_2 g2989_3 g2989_1 g2989_5 g2989_4 g2989_0 gnd
+C1  g2989_2 gnd 2.080806f
+C2  g2989_3 gnd 2.080806f
+C3  g2989_1 gnd 2.080806f
+C4  g2989_5 gnd 2.080806f
+C5  g2989_4 gnd 2.080806f
+C6  g2989_0 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 g2989_0 1 2.224404
+C8 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g2989_2 2.224404
+C9 3 gnd 2.080806f
+R4 g2989_2 3 2.224404
+R5 3 g2989_3 2.224404
+R6 g2989_1 g2989_3 2.224404
+R7 g2989_3 g2989_4 2.224404
+C10 4 gnd 2.080806f
+R8 4 g2989_1 2.224404
+R9 4 g2989_5 2.224404
+.ends
+
+.subckt netg2081 g2081_0 g2081_3 g2081_2 g2081_1 g2081_5 g2081_6 g2081_4 gnd
+C1  g2081_0 gnd 2.080806f
+C2  g2081_3 gnd 2.080806f
+C3  g2081_2 gnd 2.080806f
+C4  g2081_1 gnd 2.080806f
+C5  g2081_5 gnd 2.080806f
+C6  g2081_6 gnd 2.080806f
+C7  g2081_4 gnd 2.080806f
+R1 g2081_5 g2081_0 2.224404
+C8 1 gnd 2.080806f
+R2 g2081_0 1 2.224404
+R3 g2081_3 1 2.224404
+R4 g2081_3 g2081_6 2.224404
+R5 g2081_6 g2081_4 2.224404
+C9 2 gnd 2.080806f
+R6 2 g2081_0 2.224404
+R7 g2081_2 2 2.224404
+C10 3 gnd 2.080806f
+R8 3 g2081_3 2.224404
+R9 g2081_1 3 2.224404
+.ends
+
+.subckt netg7318 g7318_2 g7318_1 gnd
+C1  g7318_2 gnd 2.080806f
+C2  g7318_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7318_1 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 g7318_2 5 2.224404
+.ends
+
+.subckt netg1506 g1506_0 g1506_1 gnd
+C1  g1506_0 gnd 2.080806f
+C2  g1506_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1506_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 5 g1506_1 2.224404
+.ends
+
+.subckt netg1590 g1590_1 g1590_0 gnd
+C1  g1590_1 gnd 2.080806f
+C2  g1590_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1590_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+R6 5 g1590_1 2.224404
+.ends
+
+.subckt netg4767 g4767_2 g4767_0 g4767_1 g4767_3 gnd
+C1  g4767_2 gnd 2.080806f
+C2  g4767_0 gnd 2.080806f
+C3  g4767_1 gnd 2.080806f
+C4  g4767_3 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g4767_0 2.224404
+R2 g4767_2 1 2.224404
+C6 2 gnd 2.080806f
+R3 2 g4767_2 2.224404
+R4 g4767_1 2 2.224404
+C7 3 gnd 2.080806f
+R5 g4767_1 3 2.224404
+R6 g4767_3 3 2.224404
+.ends
+
+.subckt netg4113 g4113_2 g4113_3 g4113_1 g4113_0 gnd
+C1  g4113_2 gnd 2.080806f
+C2  g4113_3 gnd 2.080806f
+C3  g4113_1 gnd 2.080806f
+C4  g4113_0 gnd 2.080806f
+R1 g4113_1 g4113_0 2.224404
+C5 1 gnd 2.080806f
+R2 g4113_0 1 2.224404
+R3 1 g4113_3 2.224404
+C6 2 gnd 2.080806f
+R4 2 g4113_3 2.224404
+C7 3 gnd 2.080806f
+R5 3 2 2.224404
+C8 4 gnd 2.080806f
+R6 3 4 2.224404
+R7 g4113_2 4 2.224404
+.ends
+
+.subckt netg4392 g4392_2 g4392_0 g4392_1 gnd
+C1  g4392_2 gnd 2.080806f
+C2  g4392_0 gnd 2.080806f
+C3  g4392_1 gnd 2.080806f
+R1 g4392_1 g4392_0 2.224404
+C4 1 gnd 2.080806f
+R2 g4392_0 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 4 g4392_2 2.224404
+.ends
+
+.subckt netg1399 g1399_0 g1399_1 gnd
+C1  g1399_0 gnd 2.080806f
+C2  g1399_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1399_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 5 g1399_1 2.224404
+.ends
+
+.subckt netg1910 g1910_0 g1910_1 gnd
+C1  g1910_0 gnd 2.080806f
+C2  g1910_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1910_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 5 g1910_1 2.224404
+.ends
+
+.subckt netx161 x161_0 x161_1 gnd
+C1  x161_0 gnd 2.080806f
+C2  x161_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 x161_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 5 x161_1 2.224404
+.ends
+
+.subckt netg5820 g5820_2 g5820_1 g5820_0 g5820_3 gnd
+C1  g5820_2 gnd 2.080806f
+C2  g5820_1 gnd 2.080806f
+C3  g5820_0 gnd 2.080806f
+C4  g5820_3 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g5820_0 1 2.224404
+R2 g5820_1 1 2.224404
+C6 2 gnd 2.080806f
+R3 2 g5820_0 2.224404
+R4 g5820_3 2 2.224404
+C7 3 gnd 2.080806f
+R5 g5820_1 3 2.224404
+R6 g5820_2 3 2.224404
+.ends
+
+.subckt netg1588 g1588_0 g1588_1 gnd
+C1  g1588_0 gnd 2.080806f
+C2  g1588_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1588_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+R6 g1588_1 5 2.224404
+.ends
+
+.subckt netg3961 g3961_3 g3961_2 g3961_0 g3961_1 gnd
+C1  g3961_3 gnd 2.080806f
+C2  g3961_2 gnd 2.080806f
+C3  g3961_0 gnd 2.080806f
+C4  g3961_1 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g3961_0 1 2.224404
+R2 1 g3961_2 2.224404
+C6 2 gnd 2.080806f
+R3 g3961_2 2 2.224404
+R4 2 g3961_3 2.224404
+C7 3 gnd 2.080806f
+R5 3 g3961_3 2.224404
+R6 g3961_1 3 2.224404
+.ends
+
+.subckt netg2019 g2019_3 g2019_1 g2019_0 gnd
+C1  g2019_3 gnd 2.080806f
+C2  g2019_1 gnd 2.080806f
+C3  g2019_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g2019_0 1 2.224404
+R2 1 g2019_3 2.224404
+C5 2 gnd 2.080806f
+R3 g2019_3 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 4 g2019_1 2.224404
+.ends
+
+.subckt netg4210 g4210_2 g4210_0 gnd
+C1  g4210_2 gnd 2.080806f
+C2  g4210_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4210_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+R6 g4210_2 5 2.224404
+.ends
+
+.subckt netg3195 g3195_2 g3195_0 g3195_1 gnd
+C1  g3195_2 gnd 2.080806f
+C2  g3195_0 gnd 2.080806f
+C3  g3195_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g3195_0 2.224404
+R2 g3195_2 1 2.224404
+C5 2 gnd 2.080806f
+R3 g3195_0 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 4 g3195_1 2.224404
+.ends
+
+.subckt netg6475 g6475_1 g6475_2 gnd
+C1  g6475_1 gnd 2.080806f
+C2  g6475_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6475_2 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 5 g6475_1 2.224404
+.ends
+
+.subckt netg6304 g6304_0 g6304_2 g6304_1 gnd
+C1  g6304_0 gnd 2.080806f
+C2  g6304_2 gnd 2.080806f
+C3  g6304_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g6304_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 g6304_1 4 2.224404
+R6 g6304_2 g6304_1 2.224404
+.ends
+
+.subckt netg3174 g3174_0 g3174_2 g3174_1 gnd
+C1  g3174_0 gnd 2.080806f
+C2  g3174_2 gnd 2.080806f
+C3  g3174_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g3174_0 2.224404
+R2 g3174_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g3174_1 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+R6 g3174_2 4 2.224404
+.ends
+
+.subckt netg109 g109_0 g109_1 gnd
+C1  g109_0 gnd 2.080806f
+C2  g109_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g109_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 g109_1 5 2.224404
+.ends
+
+.subckt netg4653 g4653_3 g4653_2 g4653_1 g4653_0 gnd
+C1  g4653_3 gnd 2.080806f
+C2  g4653_2 gnd 2.080806f
+C3  g4653_1 gnd 2.080806f
+C4  g4653_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g4653_0 1 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g4653_3 2.224404
+R4 g4653_3 g4653_2 2.224404
+C7 3 gnd 2.080806f
+R5 g4653_2 3 2.224404
+R6 3 g4653_1 2.224404
+.ends
+
+.subckt netg6438 g6438_0 g6438_1 gnd
+C1  g6438_0 gnd 2.080806f
+C2  g6438_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6438_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 5 g6438_1 2.224404
+.ends
+
+.subckt netg561 g561_4 g561_0 g561_3 g561_1 g561_2 gnd
+C1  g561_4 gnd 2.080806f
+C2  g561_0 gnd 2.080806f
+C3  g561_3 gnd 2.080806f
+C4  g561_1 gnd 2.080806f
+C5  g561_2 gnd 2.080806f
+R1 g561_3 g561_0 2.224404
+R2 g561_2 g561_3 2.224404
+C6 1 gnd 2.080806f
+R3 g561_0 1 2.224404
+C7 2 gnd 2.080806f
+R4 1 2 2.224404
+R5 2 g561_4 2.224404
+R6 g561_4 g561_1 2.224404
+.ends
+
+.subckt netg4760 g4760_1 g4760_3 g4760_2 g4760_0 gnd
+C1  g4760_1 gnd 2.080806f
+C2  g4760_3 gnd 2.080806f
+C3  g4760_2 gnd 2.080806f
+C4  g4760_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g4760_0 1 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g4760_1 2 2.224404
+R4 2 g4760_2 2.224404
+C7 3 gnd 2.080806f
+R5 3 g4760_1 2.224404
+R6 g4760_3 3 2.224404
+.ends
+
+.subckt netg1400 g1400_1 g1400_0 gnd
+C1  g1400_1 gnd 2.080806f
+C2  g1400_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1400_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 5 g1400_1 2.224404
+.ends
+
+.subckt netg1559 g1559_5 g1559_4 g1559_2 g1559_0 g1559_1 g1559_3 gnd
+C1  g1559_5 gnd 2.080806f
+C2  g1559_4 gnd 2.080806f
+C3  g1559_2 gnd 2.080806f
+C4  g1559_0 gnd 2.080806f
+C5  g1559_1 gnd 2.080806f
+C6  g1559_3 gnd 2.080806f
+R1 g1559_0 g1559_3 2.224404
+R2 g1559_5 g1559_0 2.224404
+C7 1 gnd 2.080806f
+R3 g1559_0 1 2.224404
+C8 2 gnd 2.080806f
+R4 1 2 2.224404
+R5 2 g1559_1 2.224404
+R6 g1559_1 g1559_4 2.224404
+C9 3 gnd 2.080806f
+R7 3 g1559_4 2.224404
+R8 3 g1559_2 2.224404
+.ends
+
+.subckt netx191 x191_1 x191_0 gnd
+C1  x191_1 gnd 2.080806f
+C2  x191_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x191_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 x191_1 5 2.224404
+.ends
+
+.subckt netx372 x372_0 x372_1 gnd
+C1  x372_0 gnd 2.080806f
+C2  x372_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x372_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+R6 x372_1 5 2.224404
+.ends
+
+.subckt netg4456 g4456_4 g4456_6 g4456_5 g4456_2 g4456_1 g4456_3 g4456_0 gnd
+C1  g4456_4 gnd 2.080806f
+C2  g4456_6 gnd 2.080806f
+C3  g4456_5 gnd 2.080806f
+C4  g4456_2 gnd 2.080806f
+C5  g4456_1 gnd 2.080806f
+C6  g4456_3 gnd 2.080806f
+C7  g4456_0 gnd 2.080806f
+C8 1 gnd 2.080806f
+R1 1 g4456_0 2.224404
+R2 g4456_1 1 2.224404
+R3 g4456_6 1 2.224404
+C9 2 gnd 2.080806f
+R4 2 g4456_1 2.224404
+C10 3 gnd 2.080806f
+R5 3 2 2.224404
+R6 g4456_3 3 2.224404
+R7 g4456_2 g4456_3 2.224404
+R8 g4456_2 g4456_4 2.224404
+C11 4 gnd 2.080806f
+R9 g4456_3 4 2.224404
+R10 4 g4456_5 2.224404
+.ends
+
+.subckt netx431 x431_0 x431_1 gnd
+C1  x431_0 gnd 2.080806f
+C2  x431_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x431_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+R6 x431_1 5 2.224404
+.ends
+
+.subckt netg3484 g3484_0 g3484_1 gnd
+C1  g3484_0 gnd 2.080806f
+C2  g3484_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3484_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+R6 g3484_1 5 2.224404
+.ends
+
+.subckt netg4630 g4630_0 g4630_3 g4630_1 g4630_4 g4630_2 gnd
+C1  g4630_0 gnd 2.080806f
+C2  g4630_3 gnd 2.080806f
+C3  g4630_1 gnd 2.080806f
+C4  g4630_4 gnd 2.080806f
+C5  g4630_2 gnd 2.080806f
+R1 g4630_0 g4630_3 2.224404
+R2 g4630_2 g4630_3 2.224404
+C6 1 gnd 2.080806f
+R3 g4630_2 1 2.224404
+C7 2 gnd 2.080806f
+R4 1 2 2.224404
+C8 3 gnd 2.080806f
+R5 2 3 2.224404
+R6 3 g4630_4 2.224404
+R7 g4630_4 g4630_1 2.224404
+.ends
+
+.subckt netg1503 g1503_1 g1503_0 gnd
+C1  g1503_1 gnd 2.080806f
+C2  g1503_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1503_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 g1503_1 5 2.224404
+.ends
+
+.subckt netg5939 g5939_1 g5939_2 g5939_0 gnd
+C1  g5939_1 gnd 2.080806f
+C2  g5939_2 gnd 2.080806f
+C3  g5939_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5939_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g5939_1 2.224404
+C7 4 gnd 2.080806f
+R5 4 2 2.224404
+R6 g5939_2 4 2.224404
+.ends
+
+.subckt netg785 g785_6 g785_2 g785_3 g785_0 g785_5 g785_4 gnd
+C1  g785_6 gnd 2.080806f
+C2  g785_2 gnd 2.080806f
+C3  g785_3 gnd 2.080806f
+C4  g785_0 gnd 2.080806f
+C5  g785_5 gnd 2.080806f
+C6  g785_4 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 g785_0 1 2.224404
+R2 1 g785_5 2.224404
+C8 2 gnd 2.080806f
+R3 2 g785_0 2.224404
+C9 3 gnd 2.080806f
+R4 3 2 2.224404
+R5 g785_4 3 2.224404
+R6 g785_2 g785_4 2.224404
+C10 4 gnd 2.080806f
+R7 g785_4 4 2.224404
+R8 4 g785_3 2.224404
+R9 g785_6 g785_3 2.224404
+.ends
+
+.subckt netg5971 g5971_1 g5971_0 gnd
+C1  g5971_1 gnd 2.080806f
+C2  g5971_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5971_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 5 g5971_1 2.224404
+.ends
+
+.subckt netg4146 g4146_0 g4146_1 g4146_2 gnd
+C1  g4146_0 gnd 2.080806f
+C2  g4146_1 gnd 2.080806f
+C3  g4146_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g4146_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 g4146_2 3 2.224404
+C7 4 gnd 2.080806f
+R5 4 g4146_2 2.224404
+R6 g4146_1 4 2.224404
+.ends
+
+.subckt netg3144 g3144_2 g3144_1 g3144_0 gnd
+C1  g3144_2 gnd 2.080806f
+C2  g3144_1 gnd 2.080806f
+C3  g3144_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g3144_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g3144_1 2 2.224404
+C6 3 gnd 2.080806f
+R4 g3144_0 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 4 g3144_2 2.224404
+.ends
+
+.subckt netg1543 g1543_5 g1543_0 g1543_2 g1543_4 g1543_3 g1543_1 gnd
+C1  g1543_5 gnd 2.080806f
+C2  g1543_0 gnd 2.080806f
+C3  g1543_2 gnd 2.080806f
+C4  g1543_4 gnd 2.080806f
+C5  g1543_3 gnd 2.080806f
+C6  g1543_1 gnd 2.080806f
+R1 g1543_0 g1543_5 2.224404
+C7 1 gnd 2.080806f
+R2 g1543_5 1 2.224404
+R3 1 g1543_3 2.224404
+R4 g1543_3 g1543_2 2.224404
+C8 2 gnd 2.080806f
+R5 g1543_5 2 2.224404
+R6 2 g1543_4 2.224404
+C9 3 gnd 2.080806f
+R7 3 g1543_3 2.224404
+R8 g1543_1 3 2.224404
+.ends
+
+.subckt netg1323 g1323_6 g1323_1 g1323_4 g1323_5 g1323_3 gnd
+C1  g1323_6 gnd 2.080806f
+C2  g1323_1 gnd 2.080806f
+C3  g1323_4 gnd 2.080806f
+C4  g1323_5 gnd 2.080806f
+C5  g1323_3 gnd 2.080806f
+C6 1 gnd 2.080806f
+R1 g1323_1 1 2.224404
+C7 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g1323_4 2.224404
+R4 g1323_4 g1323_6 2.224404
+R5 g1323_6 g1323_3 2.224404
+R6 g1323_5 g1323_6 2.224404
+.ends
+
+.subckt netg7549 g7549_1 g7549_0 gnd
+C1  g7549_1 gnd 2.080806f
+C2  g7549_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7549_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 5 g7549_1 2.224404
+.ends
+
+.subckt netg6840 g6840_2 g6840_0 g6840_1 gnd
+C1  g6840_2 gnd 2.080806f
+C2  g6840_0 gnd 2.080806f
+C3  g6840_1 gnd 2.080806f
+R1 g6840_0 g6840_1 2.224404
+C4 1 gnd 2.080806f
+R2 g6840_0 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 4 g6840_2 2.224404
+.ends
+
+.subckt netg6284 g6284_1 g6284_0 g6284_2 gnd
+C1  g6284_1 gnd 2.080806f
+C2  g6284_0 gnd 2.080806f
+C3  g6284_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g6284_0 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 4 g6284_1 2.224404
+R6 g6284_1 g6284_2 2.224404
+.ends
+
+.subckt netg4383 g4383_2 g4383_1 g4383_0 gnd
+C1  g4383_2 gnd 2.080806f
+C2  g4383_1 gnd 2.080806f
+C3  g4383_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g4383_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g4383_2 2.224404
+C7 4 gnd 2.080806f
+R5 4 g4383_2 2.224404
+R6 g4383_1 4 2.224404
+.ends
+
+.subckt netg5933 g5933_1 g5933_2 gnd
+C1  g5933_1 gnd 2.080806f
+C2  g5933_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5933_2 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 g5933_1 5 2.224404
+.ends
+
+.subckt netg1537 g1537_1 g1537_4 g1537_2 g1537_5 g1537_3 g1537_0 gnd
+C1  g1537_1 gnd 2.080806f
+C2  g1537_4 gnd 2.080806f
+C3  g1537_2 gnd 2.080806f
+C4  g1537_5 gnd 2.080806f
+C5  g1537_3 gnd 2.080806f
+C6  g1537_0 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 g1537_0 1 2.224404
+R2 1 g1537_3 2.224404
+R3 g1537_3 g1537_4 2.224404
+C8 2 gnd 2.080806f
+R4 2 g1537_4 2.224404
+R5 g1537_1 2 2.224404
+R6 g1537_1 g1537_2 2.224404
+C9 3 gnd 2.080806f
+R7 3 g1537_1 2.224404
+R8 g1537_5 3 2.224404
+.ends
+
+.subckt netg4750 g4750_2 g4750_0 g4750_1 gnd
+C1  g4750_2 gnd 2.080806f
+C2  g4750_0 gnd 2.080806f
+C3  g4750_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g4750_0 1 2.224404
+R2 1 g4750_2 2.224404
+C5 2 gnd 2.080806f
+R3 2 g4750_0 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+R6 g4750_1 4 2.224404
+.ends
+
+.subckt netg7141 g7141_0 g7141_2 g7141_1 gnd
+C1  g7141_0 gnd 2.080806f
+C2  g7141_2 gnd 2.080806f
+C3  g7141_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g7141_0 2.224404
+R2 g7141_2 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g7141_0 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 4 g7141_1 2.224404
+.ends
+
+.subckt netg5122 g5122_2 g5122_1 g5122_0 gnd
+C1  g5122_2 gnd 2.080806f
+C2  g5122_1 gnd 2.080806f
+C3  g5122_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5122_0 1 2.224404
+R2 1 g5122_1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g5122_0 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 g5122_2 4 2.224404
+.ends
+
+.subckt netg3201 g3201_2 g3201_0 g3201_1 gnd
+C1  g3201_2 gnd 2.080806f
+C2  g3201_0 gnd 2.080806f
+C3  g3201_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g3201_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g3201_1 3 2.224404
+C7 4 gnd 2.080806f
+R5 4 g3201_1 2.224404
+R6 g3201_2 4 2.224404
+.ends
+
+.subckt netg1493 g1493_0 g1493_1 gnd
+C1  g1493_0 gnd 2.080806f
+C2  g1493_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1493_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 5 g1493_1 2.224404
+.ends
+
+.subckt netg6322 g6322_3 g6322_1 g6322_0 g6322_2 gnd
+C1  g6322_3 gnd 2.080806f
+C2  g6322_1 gnd 2.080806f
+C3  g6322_0 gnd 2.080806f
+C4  g6322_2 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g6322_0 1 2.224404
+R2 1 g6322_1 2.224404
+R3 g6322_1 g6322_3 2.224404
+C6 2 gnd 2.080806f
+R4 g6322_1 2 2.224404
+C7 3 gnd 2.080806f
+R5 2 3 2.224404
+R6 3 g6322_2 2.224404
+.ends
+
+.subckt netg5459 g5459_2 g5459_1 g5459_0 gnd
+C1  g5459_2 gnd 2.080806f
+C2  g5459_1 gnd 2.080806f
+C3  g5459_0 gnd 2.080806f
+R1 g5459_0 g5459_1 2.224404
+C4 1 gnd 2.080806f
+R2 g5459_0 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 4 g5459_2 2.224404
+.ends
+
+.subckt netg5795 g5795_0 g5795_1 g5795_2 g5795_3 gnd
+C1  g5795_0 gnd 2.080806f
+C2  g5795_1 gnd 2.080806f
+C3  g5795_2 gnd 2.080806f
+C4  g5795_3 gnd 2.080806f
+R1 g5795_2 g5795_0 2.224404
+C5 1 gnd 2.080806f
+R2 g5795_2 1 2.224404
+C6 2 gnd 2.080806f
+R3 1 2 2.224404
+R4 2 g5795_3 2.224404
+C7 3 gnd 2.080806f
+R5 g5795_3 3 2.224404
+R6 3 g5795_1 2.224404
+.ends
+
+.subckt netg6491 g6491_1 g6491_2 gnd
+C1  g6491_1 gnd 2.080806f
+C2  g6491_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6491_1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 5 g6491_2 2.224404
+.ends
+
+.subckt netg3971 g3971_1 g3971_0 gnd
+C1  g3971_1 gnd 2.080806f
+C2  g3971_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3971_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+R6 g3971_1 5 2.224404
+.ends
+
+.subckt netg1153 g1153_1 g1153_0 gnd
+C1  g1153_1 gnd 2.080806f
+C2  g1153_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1153_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 5 g1153_1 2.224404
+.ends
+
+.subckt netg1499 g1499_0 g1499_1 gnd
+C1  g1499_0 gnd 2.080806f
+C2  g1499_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1499_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 5 g1499_1 2.224404
+.ends
+
+.subckt netg6919 g6919_0 g6919_1 gnd
+C1  g6919_0 gnd 2.080806f
+C2  g6919_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6919_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 g6919_1 5 2.224404
+.ends
+
+.subckt netg2456 g2456_1 g2456_2 gnd
+C1  g2456_1 gnd 2.080806f
+C2  g2456_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2456_2 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 5 g2456_1 2.224404
+.ends
+
+.subckt netg4949 g4949_3 g4949_0 g4949_1 g4949_2 gnd
+C1  g4949_3 gnd 2.080806f
+C2  g4949_0 gnd 2.080806f
+C3  g4949_1 gnd 2.080806f
+C4  g4949_2 gnd 2.080806f
+R1 g4949_2 g4949_0 2.224404
+C5 1 gnd 2.080806f
+R2 g4949_0 1 2.224404
+C6 2 gnd 2.080806f
+R3 1 2 2.224404
+R4 2 g4949_3 2.224404
+C7 3 gnd 2.080806f
+R5 g4949_3 3 2.224404
+R6 3 g4949_1 2.224404
+.ends
+
+.subckt netg3153 g3153_0 g3153_2 gnd
+C1  g3153_0 gnd 2.080806f
+C2  g3153_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3153_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+R6 g3153_2 5 2.224404
+.ends
+
+.subckt netg2585 g2585_1 g2585_0 g2585_2 gnd
+C1  g2585_1 gnd 2.080806f
+C2  g2585_0 gnd 2.080806f
+C3  g2585_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g2585_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g2585_1 2.224404
+C7 4 gnd 2.080806f
+R5 g2585_1 4 2.224404
+R6 4 g2585_2 2.224404
+.ends
+
+.subckt netg5177 g5177_1 g5177_0 gnd
+C1  g5177_1 gnd 2.080806f
+C2  g5177_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5177_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 5 g5177_1 2.224404
+.ends
+
+.subckt netg3938 g3938_4 g3938_0 g3938_1 g3938_3 g3938_2 gnd
+C1  g3938_4 gnd 2.080806f
+C2  g3938_0 gnd 2.080806f
+C3  g3938_1 gnd 2.080806f
+C4  g3938_3 gnd 2.080806f
+C5  g3938_2 gnd 2.080806f
+C6 1 gnd 2.080806f
+R1 g3938_0 1 2.224404
+R2 1 g3938_1 2.224404
+R3 g3938_1 g3938_2 2.224404
+C7 2 gnd 2.080806f
+R4 2 g3938_1 2.224404
+R5 g3938_4 2 2.224404
+C8 3 gnd 2.080806f
+R6 3 g3938_4 2.224404
+R7 3 g3938_3 2.224404
+.ends
+
+.subckt netg1848 g1848_0 g1848_1 g1848_3 g1848_2 gnd
+C1  g1848_0 gnd 2.080806f
+C2  g1848_1 gnd 2.080806f
+C3  g1848_3 gnd 2.080806f
+C4  g1848_2 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g1848_0 2.224404
+R2 g1848_2 1 2.224404
+C6 2 gnd 2.080806f
+R3 2 g1848_2 2.224404
+C7 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g1848_1 2.224404
+R6 g1848_3 3 2.224404
+.ends
+
+.subckt netg5217 g5217_2 g5217_0 gnd
+C1  g5217_2 gnd 2.080806f
+C2  g5217_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5217_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 5 g5217_2 2.224404
+.ends
+
+.subckt netg2223 g2223_1 g2223_0 gnd
+C1  g2223_1 gnd 2.080806f
+C2  g2223_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2223_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 5 g2223_1 2.224404
+.ends
+
+.subckt netg6628 g6628_1 g6628_2 g6628_0 gnd
+C1  g6628_1 gnd 2.080806f
+C2  g6628_2 gnd 2.080806f
+C3  g6628_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g6628_0 1 2.224404
+R2 1 g6628_2 2.224404
+C5 2 gnd 2.080806f
+R3 g6628_0 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 g6628_1 4 2.224404
+.ends
+
+.subckt netg4660 g4660_1 g4660_0 gnd
+C1  g4660_1 gnd 2.080806f
+C2  g4660_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4660_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 5 g4660_1 2.224404
+.ends
+
+.subckt netg1961 g1961_3 g1961_1 g1961_0 g1961_2 gnd
+C1  g1961_3 gnd 2.080806f
+C2  g1961_1 gnd 2.080806f
+C3  g1961_0 gnd 2.080806f
+C4  g1961_2 gnd 2.080806f
+R1 g1961_1 g1961_0 2.224404
+C5 1 gnd 2.080806f
+R2 1 g1961_1 2.224404
+C6 2 gnd 2.080806f
+R3 2 1 2.224404
+R4 g1961_3 2 2.224404
+C7 3 gnd 2.080806f
+R5 3 g1961_3 2.224404
+R6 g1961_2 3 2.224404
+.ends
+
+.subckt netg2004 g2004_1 g2004_3 g2004_0 g2004_2 gnd
+C1  g2004_1 gnd 2.080806f
+C2  g2004_3 gnd 2.080806f
+C3  g2004_0 gnd 2.080806f
+C4  g2004_2 gnd 2.080806f
+R1 g2004_1 g2004_0 2.224404
+R2 g2004_3 g2004_1 2.224404
+C5 1 gnd 2.080806f
+R3 1 g2004_3 2.224404
+C6 2 gnd 2.080806f
+R4 2 1 2.224404
+C7 3 gnd 2.080806f
+R5 3 2 2.224404
+R6 g2004_2 3 2.224404
+.ends
+
+.subckt netg1423 g1423_1 g1423_0 g1423_4 g1423_3 g1423_2 gnd
+C1  g1423_1 gnd 2.080806f
+C2  g1423_0 gnd 2.080806f
+C3  g1423_4 gnd 2.080806f
+C4  g1423_3 gnd 2.080806f
+C5  g1423_2 gnd 2.080806f
+R1 g1423_2 g1423_0 2.224404
+C6 1 gnd 2.080806f
+R2 1 g1423_0 2.224404
+R3 g1423_3 1 2.224404
+C7 2 gnd 2.080806f
+R4 2 g1423_2 2.224404
+R5 g1423_4 2 2.224404
+C8 3 gnd 2.080806f
+R6 3 g1423_4 2.224404
+C9 4 gnd 2.080806f
+R7 4 3 2.224404
+R8 g1423_1 4 2.224404
+.ends
+
+.subckt netg5388 g5388_2 g5388_1 g5388_0 gnd
+C1  g5388_2 gnd 2.080806f
+C2  g5388_1 gnd 2.080806f
+C3  g5388_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5388_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 4 g5388_2 2.224404
+R6 g5388_2 g5388_1 2.224404
+.ends
+
+.subckt netg5974 g5974_0 g5974_1 g5974_2 gnd
+C1  g5974_0 gnd 2.080806f
+C2  g5974_1 gnd 2.080806f
+C3  g5974_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5974_0 2.224404
+R2 g5974_2 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g5974_2 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+R6 g5974_1 4 2.224404
+.ends
+
+.subckt netx462 x462_0 x462_1 gnd
+C1  x462_0 gnd 2.080806f
+C2  x462_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x462_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+R6 x462_1 5 2.224404
+.ends
+
+.subckt netg780 g780_3 g780_1 g780_2 g780_0 g780_4 gnd
+C1  g780_3 gnd 2.080806f
+C2  g780_1 gnd 2.080806f
+C3  g780_2 gnd 2.080806f
+C4  g780_0 gnd 2.080806f
+C5  g780_4 gnd 2.080806f
+R1 g780_0 g780_3 2.224404
+C6 1 gnd 2.080806f
+R2 1 g780_3 2.224404
+R3 1 g780_2 2.224404
+C7 2 gnd 2.080806f
+R4 2 1 2.224404
+R5 g780_1 2 2.224404
+C8 3 gnd 2.080806f
+R6 3 g780_1 2.224404
+R7 3 g780_4 2.224404
+.ends
+
+.subckt netg7048 g7048_2 g7048_1 g7048_0 gnd
+C1  g7048_2 gnd 2.080806f
+C2  g7048_1 gnd 2.080806f
+C3  g7048_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g7048_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 g7048_1 4 2.224404
+R6 4 g7048_2 2.224404
+.ends
+
+.subckt netg7030 g7030_1 g7030_2 gnd
+C1  g7030_1 gnd 2.080806f
+C2  g7030_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7030_1 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 g7030_2 5 2.224404
+.ends
+
+.subckt netg6559 g6559_1 g6559_0 gnd
+C1  g6559_1 gnd 2.080806f
+C2  g6559_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6559_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 g6559_1 5 2.224404
+.ends
+
+.subckt netg3698 g3698_3 g3698_0 g3698_2 g3698_1 gnd
+C1  g3698_3 gnd 2.080806f
+C2  g3698_0 gnd 2.080806f
+C3  g3698_2 gnd 2.080806f
+C4  g3698_1 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g3698_0 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g3698_2 2 2.224404
+C7 3 gnd 2.080806f
+R4 g3698_2 3 2.224404
+R5 3 g3698_3 2.224404
+C8 4 gnd 2.080806f
+R6 g3698_3 4 2.224404
+C9 5 gnd 2.080806f
+R7 4 5 2.224404
+R8 5 g3698_1 2.224404
+.ends
+
+.subckt netg4960 g4960_3 g4960_0 g4960_2 g4960_1 gnd
+C1  g4960_3 gnd 2.080806f
+C2  g4960_0 gnd 2.080806f
+C3  g4960_2 gnd 2.080806f
+C4  g4960_1 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g4960_0 1 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+C7 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g4960_3 2.224404
+R5 g4960_3 g4960_1 2.224404
+R6 g4960_1 g4960_2 2.224404
+.ends
+
+.subckt netg4775 g4775_1 g4775_0 g4775_2 gnd
+C1  g4775_1 gnd 2.080806f
+C2  g4775_0 gnd 2.080806f
+C3  g4775_2 gnd 2.080806f
+R1 g4775_0 g4775_1 2.224404
+C4 1 gnd 2.080806f
+R2 1 g4775_0 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+R6 g4775_2 4 2.224404
+.ends
+
+.subckt netg7378 g7378_1 g7378_0 g7378_2 gnd
+C1  g7378_1 gnd 2.080806f
+C2  g7378_0 gnd 2.080806f
+C3  g7378_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g7378_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g7378_1 3 2.224404
+C7 4 gnd 2.080806f
+R5 4 g7378_1 2.224404
+R6 g7378_2 4 2.224404
+.ends
+
+.subckt netg4006 g4006_1 g4006_0 gnd
+C1  g4006_1 gnd 2.080806f
+C2  g4006_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4006_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 g4006_1 5 2.224404
+.ends
+
+.subckt netg1206 g1206_2 g1206_4 g1206_3 g1206_1 g1206_0 g1206_5 gnd
+C1  g1206_2 gnd 2.080806f
+C2  g1206_4 gnd 2.080806f
+C3  g1206_3 gnd 2.080806f
+C4  g1206_1 gnd 2.080806f
+C5  g1206_0 gnd 2.080806f
+C6  g1206_5 gnd 2.080806f
+R1 g1206_0 g1206_3 2.224404
+R2 g1206_3 g1206_5 2.224404
+R3 g1206_5 g1206_1 2.224404
+C7 1 gnd 2.080806f
+R4 g1206_1 1 2.224404
+R5 1 g1206_4 2.224404
+R6 g1206_4 g1206_2 2.224404
+.ends
+
+.subckt netx31 x31_1 x31_0 gnd
+C1  x31_1 gnd 2.080806f
+C2  x31_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 x31_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 5 x31_1 2.224404
+.ends
+
+.subckt netg4386 g4386_2 g4386_0 g4386_1 gnd
+C1  g4386_2 gnd 2.080806f
+C2  g4386_0 gnd 2.080806f
+C3  g4386_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g4386_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 4 g4386_1 2.224404
+C8 5 gnd 2.080806f
+R6 5 3 2.224404
+R7 g4386_2 5 2.224404
+.ends
+
+.subckt netg7420 g7420_0 g7420_1 gnd
+C1  g7420_0 gnd 2.080806f
+C2  g7420_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7420_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+R7 6 g7420_1 2.224404
+.ends
+
+.subckt netg3999 g3999_3 g3999_1 g3999_2 g3999_0 gnd
+C1  g3999_3 gnd 2.080806f
+C2  g3999_1 gnd 2.080806f
+C3  g3999_2 gnd 2.080806f
+C4  g3999_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g3999_0 1 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g3999_1 2.224404
+C7 3 gnd 2.080806f
+R4 g3999_0 3 2.224404
+C8 4 gnd 2.080806f
+R5 3 4 2.224404
+C9 5 gnd 2.080806f
+R6 4 5 2.224404
+R7 5 g3999_2 2.224404
+R8 5 g3999_3 2.224404
+.ends
+
+.subckt netg5713 g5713_1 g5713_0 g5713_2 gnd
+C1  g5713_1 gnd 2.080806f
+C2  g5713_0 gnd 2.080806f
+C3  g5713_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5713_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g5713_1 2 2.224404
+C6 3 gnd 2.080806f
+R4 g5713_0 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+C8 5 gnd 2.080806f
+R6 4 5 2.224404
+R7 5 g5713_2 2.224404
+.ends
+
+.subckt netg1289 g1289_3 g1289_2 g1289_5 g1289_1 g1289_4 gnd
+C1  g1289_3 gnd 2.080806f
+C2  g1289_2 gnd 2.080806f
+C3  g1289_5 gnd 2.080806f
+C4  g1289_1 gnd 2.080806f
+C5  g1289_4 gnd 2.080806f
+R1 g1289_3 g1289_2 2.224404
+R2 g1289_1 g1289_2 2.224404
+C6 1 gnd 2.080806f
+R3 1 g1289_3 2.224404
+C7 2 gnd 2.080806f
+R4 2 1 2.224404
+R5 g1289_5 2 2.224404
+C8 3 gnd 2.080806f
+R6 3 g1289_5 2.224404
+C9 4 gnd 2.080806f
+R7 4 3 2.224404
+R8 g1289_4 4 2.224404
+.ends
+
+.subckt netg7315 g7315_2 g7315_0 gnd
+C1  g7315_2 gnd 2.080806f
+C2  g7315_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7315_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+R7 g7315_2 6 2.224404
+.ends
+
+.subckt netg95 g95_1 g95_0 gnd
+C1  g95_1 gnd 2.080806f
+C2  g95_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g95_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+R7 g95_1 6 2.224404
+.ends
+
+.subckt netg6263 g6263_0 g6263_2 g6263_1 gnd
+C1  g6263_0 gnd 2.080806f
+C2  g6263_2 gnd 2.080806f
+C3  g6263_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g6263_0 2.224404
+R2 g6263_2 1 2.224404
+C5 2 gnd 2.080806f
+R3 g6263_0 2 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+R8 g6263_1 6 2.224404
+.ends
+
+.subckt netg5680 g5680_2 g5680_1 g5680_0 gnd
+C1  g5680_2 gnd 2.080806f
+C2  g5680_1 gnd 2.080806f
+C3  g5680_0 gnd 2.080806f
+R1 g5680_1 g5680_0 2.224404
+C4 1 gnd 2.080806f
+R2 g5680_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+C8 5 gnd 2.080806f
+R6 4 5 2.224404
+R7 5 g5680_2 2.224404
+.ends
+
+.subckt netg3330 g3330_2 g3330_0 g3330_1 gnd
+C1  g3330_2 gnd 2.080806f
+C2  g3330_0 gnd 2.080806f
+C3  g3330_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g3330_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 g3330_1 3 2.224404
+C7 4 gnd 2.080806f
+R5 4 2 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+R7 g3330_2 5 2.224404
+.ends
+
+.subckt netg1716 g1716_2 g1716_0 g1716_1 gnd
+C1  g1716_2 gnd 2.080806f
+C2  g1716_0 gnd 2.080806f
+C3  g1716_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g1716_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g1716_2 2 2.224404
+C6 3 gnd 2.080806f
+R4 3 g1716_2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+R7 g1716_1 5 2.224404
+.ends
+
+.subckt netg6881 g6881_0 g6881_1 gnd
+C1  g6881_0 gnd 2.080806f
+C2  g6881_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6881_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+R7 6 g6881_1 2.224404
+.ends
+
+.subckt netg3491 g3491_0 g3491_1 gnd
+C1  g3491_0 gnd 2.080806f
+C2  g3491_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3491_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+R7 6 g3491_1 2.224404
+.ends
+
+.subckt netg3053 g3053_1 g3053_0 gnd
+C1  g3053_1 gnd 2.080806f
+C2  g3053_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3053_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+R7 6 g3053_1 2.224404
+.ends
+
+.subckt netg3705 g3705_2 g3705_0 g3705_3 g3705_1 gnd
+C1  g3705_2 gnd 2.080806f
+C2  g3705_0 gnd 2.080806f
+C3  g3705_3 gnd 2.080806f
+C4  g3705_1 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g3705_0 1 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g3705_3 2.224404
+C7 3 gnd 2.080806f
+R4 g3705_3 3 2.224404
+R5 3 g3705_1 2.224404
+C8 4 gnd 2.080806f
+R6 g3705_1 4 2.224404
+R7 4 g3705_2 2.224404
+.ends
+
+.subckt netg4635 g4635_3 g4635_0 g4635_2 g4635_1 gnd
+C1  g4635_3 gnd 2.080806f
+C2  g4635_0 gnd 2.080806f
+C3  g4635_2 gnd 2.080806f
+C4  g4635_1 gnd 2.080806f
+R1 g4635_0 g4635_2 2.224404
+R2 g4635_1 g4635_2 2.224404
+C5 1 gnd 2.080806f
+R3 g4635_2 1 2.224404
+C6 2 gnd 2.080806f
+R4 1 2 2.224404
+C7 3 gnd 2.080806f
+R5 2 3 2.224404
+C8 4 gnd 2.080806f
+R6 3 4 2.224404
+R7 4 g4635_3 2.224404
+.ends
+
+.subckt netg2525 g2525_1 g2525_2 g2525_0 gnd
+C1  g2525_1 gnd 2.080806f
+C2  g2525_2 gnd 2.080806f
+C3  g2525_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g2525_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g2525_2 2.224404
+C7 4 gnd 2.080806f
+R5 4 1 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+R8 g2525_1 6 2.224404
+.ends
+
+.subckt netg115 g115_1 g115_0 gnd
+C1  g115_1 gnd 2.080806f
+C2  g115_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g115_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+R7 g115_1 6 2.224404
+.ends
+
+.subckt netg1246 g1246_1 g1246_3 g1246_2 g1246_0 gnd
+C1  g1246_1 gnd 2.080806f
+C2  g1246_3 gnd 2.080806f
+C3  g1246_2 gnd 2.080806f
+C4  g1246_0 gnd 2.080806f
+R1 g1246_2 g1246_0 2.224404
+R2 g1246_3 g1246_2 2.224404
+C5 1 gnd 2.080806f
+R3 1 g1246_3 2.224404
+C6 2 gnd 2.080806f
+R4 2 1 2.224404
+C7 3 gnd 2.080806f
+R5 3 2 2.224404
+C8 4 gnd 2.080806f
+R6 3 4 2.224404
+R7 g1246_1 4 2.224404
+.ends
+
+.subckt netg3637 g3637_5 g3637_1 g3637_6 g3637_4 g3637_0 g3637_3 g3637_2 gnd
+C1  g3637_5 gnd 2.080806f
+C2  g3637_1 gnd 2.080806f
+C3  g3637_6 gnd 2.080806f
+C4  g3637_4 gnd 2.080806f
+C5  g3637_0 gnd 2.080806f
+C6  g3637_3 gnd 2.080806f
+C7  g3637_2 gnd 2.080806f
+R1 g3637_0 g3637_6 2.224404
+R2 g3637_6 g3637_2 2.224404
+C8 1 gnd 2.080806f
+R3 g3637_2 1 2.224404
+R4 1 g3637_5 2.224404
+R5 g3637_1 g3637_5 2.224404
+R6 g3637_5 g3637_3 2.224404
+C9 2 gnd 2.080806f
+R7 g3637_1 2 2.224404
+R8 2 g3637_4 2.224404
+.ends
+
+.subckt netg6760 g6760_4 g6760_3 g6760_2 g6760_1 g6760_0 gnd
+C1  g6760_4 gnd 2.080806f
+C2  g6760_3 gnd 2.080806f
+C3  g6760_2 gnd 2.080806f
+C4  g6760_1 gnd 2.080806f
+C5  g6760_0 gnd 2.080806f
+R1 g6760_2 g6760_0 2.224404
+C6 1 gnd 2.080806f
+R2 g6760_0 1 2.224404
+C7 2 gnd 2.080806f
+R3 1 2 2.224404
+C8 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g6760_1 2.224404
+C9 4 gnd 2.080806f
+R6 4 g6760_1 2.224404
+R7 4 g6760_4 2.224404
+R8 g6760_4 g6760_3 2.224404
+.ends
+
+.subckt netg5404 g5404_0 g5404_1 g5404_2 gnd
+C1  g5404_0 gnd 2.080806f
+C2  g5404_1 gnd 2.080806f
+C3  g5404_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5404_0 2.224404
+R2 1 g5404_1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g5404_1 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+R7 5 g5404_2 2.224404
+.ends
+
+.subckt netg792 g792_1 g792_0 g792_3 g792_2 gnd
+C1  g792_1 gnd 2.080806f
+C2  g792_0 gnd 2.080806f
+C3  g792_3 gnd 2.080806f
+C4  g792_2 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g792_0 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g792_2 2 2.224404
+C7 3 gnd 2.080806f
+R4 3 g792_2 2.224404
+R5 g792_3 3 2.224404
+C8 4 gnd 2.080806f
+R6 4 2 2.224404
+R7 g792_1 4 2.224404
+.ends
+
+.subckt netg6176 g6176_3 g6176_2 g6176_1 g6176_0 gnd
+C1  g6176_3 gnd 2.080806f
+C2  g6176_2 gnd 2.080806f
+C3  g6176_1 gnd 2.080806f
+C4  g6176_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g6176_0 1 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+C7 3 gnd 2.080806f
+R3 2 3 2.224404
+C8 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 4 g6176_1 2.224404
+C9 5 gnd 2.080806f
+R6 g6176_1 5 2.224404
+R7 5 g6176_3 2.224404
+R8 g6176_2 g6176_3 2.224404
+.ends
+
+.subckt netg6710 g6710_1 g6710_0 gnd
+C1  g6710_1 gnd 2.080806f
+C2  g6710_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6710_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+R7 g6710_1 6 2.224404
+.ends
+
+.subckt netg4920 g4920_5 g4920_0 g4920_4 g4920_1 g4920_2 g4920_3 gnd
+C1  g4920_5 gnd 2.080806f
+C2  g4920_0 gnd 2.080806f
+C3  g4920_4 gnd 2.080806f
+C4  g4920_1 gnd 2.080806f
+C5  g4920_2 gnd 2.080806f
+C6  g4920_3 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g4920_0 2.224404
+R2 g4920_3 1 2.224404
+C8 2 gnd 2.080806f
+R3 2 g4920_0 2.224404
+R4 g4920_5 2 2.224404
+C9 3 gnd 2.080806f
+R5 3 g4920_3 2.224404
+R6 g4920_4 3 2.224404
+C10 4 gnd 2.080806f
+R7 4 g4920_5 2.224404
+R8 g4920_2 4 2.224404
+C11 5 gnd 2.080806f
+R9 5 g4920_4 2.224404
+C12 6 gnd 2.080806f
+R10 6 5 2.224404
+R11 g4920_1 6 2.224404
+.ends
+
+.subckt netg3132 g3132_2 g3132_0 g3132_1 gnd
+C1  g3132_2 gnd 2.080806f
+C2  g3132_0 gnd 2.080806f
+C3  g3132_1 gnd 2.080806f
+R1 g3132_0 g3132_1 2.224404
+C4 1 gnd 2.080806f
+R2 1 g3132_1 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+R7 5 g3132_2 2.224404
+.ends
+
+.subckt netg2870 g2870_3 g2870_0 g2870_1 gnd
+C1  g2870_3 gnd 2.080806f
+C2  g2870_0 gnd 2.080806f
+C3  g2870_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g2870_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 g2870_1 4 2.224404
+C8 5 gnd 2.080806f
+R6 5 g2870_1 2.224404
+R7 g2870_3 5 2.224404
+.ends
+
+.subckt netg691 g691_2 g691_0 g691_1 gnd
+C1  g691_2 gnd 2.080806f
+C2  g691_0 gnd 2.080806f
+C3  g691_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g691_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g691_2 2 2.224404
+C6 3 gnd 2.080806f
+R4 3 1 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+R7 g691_1 5 2.224404
+.ends
+
+.subckt netg5211 g5211_2 g5211_1 g5211_0 gnd
+C1  g5211_2 gnd 2.080806f
+C2  g5211_1 gnd 2.080806f
+C3  g5211_0 gnd 2.080806f
+R1 g5211_0 g5211_2 2.224404
+C4 1 gnd 2.080806f
+R2 g5211_0 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 4 5 2.224404
+R7 g5211_1 5 2.224404
+.ends
+
+.subckt netg6957 g6957_1 g6957_2 g6957_0 gnd
+C1  g6957_1 gnd 2.080806f
+C2  g6957_2 gnd 2.080806f
+C3  g6957_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g6957_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 3 g6957_2 2.224404
+C7 4 gnd 2.080806f
+R5 4 g6957_2 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+R7 5 g6957_1 2.224404
+.ends
+
+.subckt netg1316 g1316_3 g1316_2 g1316_6 g1316_1 g1316_5 g1316_4 gnd
+C1  g1316_3 gnd 2.080806f
+C2  g1316_2 gnd 2.080806f
+C3  g1316_6 gnd 2.080806f
+C4  g1316_1 gnd 2.080806f
+C5  g1316_5 gnd 2.080806f
+C6  g1316_4 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 g1316_2 1 2.224404
+R2 1 g1316_6 2.224404
+C8 2 gnd 2.080806f
+R3 g1316_2 2 2.224404
+R4 g1316_5 2 2.224404
+C9 3 gnd 2.080806f
+R5 g1316_6 3 2.224404
+C10 4 gnd 2.080806f
+R6 3 4 2.224404
+R7 4 g1316_4 2.224404
+R8 g1316_1 g1316_4 2.224404
+C11 5 gnd 2.080806f
+R9 g1316_5 5 2.224404
+C12 6 gnd 2.080806f
+R10 5 6 2.224404
+R11 g1316_3 6 2.224404
+.ends
+
+.subckt netg5948 g5948_0 g5948_1 g5948_2 gnd
+C1  g5948_0 gnd 2.080806f
+C2  g5948_1 gnd 2.080806f
+C3  g5948_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5948_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+R6 5 g5948_2 2.224404
+R7 g5948_2 g5948_1 2.224404
+.ends
+
+.subckt netg2062 g2062_0 g2062_3 g2062_2 g2062_7 g2062_5 g2062_4 g2062_1 gnd
+C1  g2062_0 gnd 2.080806f
+C2  g2062_3 gnd 2.080806f
+C3  g2062_2 gnd 2.080806f
+C4  g2062_7 gnd 2.080806f
+C5  g2062_5 gnd 2.080806f
+C6  g2062_4 gnd 2.080806f
+C7  g2062_1 gnd 2.080806f
+C8 1 gnd 2.080806f
+R1 g2062_0 1 2.224404
+R2 1 g2062_1 2.224404
+R3 g2062_4 g2062_1 2.224404
+R4 g2062_7 g2062_4 2.224404
+R5 g2062_3 g2062_7 2.224404
+R6 g2062_5 g2062_3 2.224404
+R7 g2062_2 g2062_5 2.224404
+.ends
+
+.subckt netg6294 g6294_1 g6294_2 g6294_0 gnd
+C1  g6294_1 gnd 2.080806f
+C2  g6294_2 gnd 2.080806f
+C3  g6294_0 gnd 2.080806f
+R1 g6294_2 g6294_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g6294_0 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 4 5 2.224404
+R7 g6294_1 5 2.224404
+.ends
+
+.subckt netg5628 g5628_1 g5628_2 g5628_0 gnd
+C1  g5628_1 gnd 2.080806f
+C2  g5628_2 gnd 2.080806f
+C3  g5628_0 gnd 2.080806f
+R1 g5628_2 g5628_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g5628_2 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+R7 g5628_1 5 2.224404
+.ends
+
+.subckt netg6372 g6372_1 g6372_0 gnd
+C1  g6372_1 gnd 2.080806f
+C2  g6372_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6372_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+R7 6 g6372_1 2.224404
+.ends
+
+.subckt netg7057 g7057_0 g7057_1 g7057_2 gnd
+C1  g7057_0 gnd 2.080806f
+C2  g7057_1 gnd 2.080806f
+C3  g7057_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g7057_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g7057_1 2.224404
+C7 4 gnd 2.080806f
+R5 4 g7057_0 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+R8 6 g7057_2 2.224404
+.ends
+
+.subckt netg3252 g3252_1 g3252_2 g3252_0 gnd
+C1  g3252_1 gnd 2.080806f
+C2  g3252_2 gnd 2.080806f
+C3  g3252_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g3252_0 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+C8 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 5 g3252_1 2.224404
+R7 g3252_2 5 2.224404
+.ends
+
+.subckt netg796 g796_2 g796_1 g796_0 gnd
+C1  g796_2 gnd 2.080806f
+C2  g796_1 gnd 2.080806f
+C3  g796_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g796_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 4 g796_2 2.224404
+C8 5 gnd 2.080806f
+R6 g796_2 5 2.224404
+R7 5 g796_1 2.224404
+.ends
+
+.subckt netg4648 g4648_1 g4648_3 g4648_0 g4648_4 g4648_2 gnd
+C1  g4648_1 gnd 2.080806f
+C2  g4648_3 gnd 2.080806f
+C3  g4648_0 gnd 2.080806f
+C4  g4648_4 gnd 2.080806f
+C5  g4648_2 gnd 2.080806f
+R1 g4648_2 g4648_0 2.224404
+R2 g4648_3 g4648_0 2.224404
+C6 1 gnd 2.080806f
+R3 g4648_0 1 2.224404
+R4 1 g4648_4 2.224404
+C7 2 gnd 2.080806f
+R5 g4648_4 2 2.224404
+C8 3 gnd 2.080806f
+R6 2 3 2.224404
+R7 3 g4648_1 2.224404
+.ends
+
+.subckt netg5752 g5752_0 g5752_2 g5752_1 gnd
+C1  g5752_0 gnd 2.080806f
+C2  g5752_2 gnd 2.080806f
+C3  g5752_1 gnd 2.080806f
+R1 g5752_2 g5752_0 2.224404
+C4 1 gnd 2.080806f
+R2 g5752_2 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+C8 5 gnd 2.080806f
+R6 4 5 2.224404
+R7 g5752_1 5 2.224404
+.ends
+
+.subckt netg4642 g4642_2 g4642_1 g4642_5 g4642_3 g4642_0 g4642_4 gnd
+C1  g4642_2 gnd 2.080806f
+C2  g4642_1 gnd 2.080806f
+C3  g4642_5 gnd 2.080806f
+C4  g4642_3 gnd 2.080806f
+C5  g4642_0 gnd 2.080806f
+C6  g4642_4 gnd 2.080806f
+R1 g4642_3 g4642_0 2.224404
+C7 1 gnd 2.080806f
+R2 g4642_0 1 2.224404
+R3 1 g4642_4 2.224404
+C8 2 gnd 2.080806f
+R4 2 g4642_3 2.224404
+R5 g4642_2 2 2.224404
+C9 3 gnd 2.080806f
+R6 g4642_4 3 2.224404
+R7 3 g4642_1 2.224404
+R8 g4642_5 3 2.224404
+.ends
+
+.subckt netg113 g113_0 g113_1 gnd
+C1  g113_0 gnd 2.080806f
+C2  g113_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g113_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+R7 6 g113_1 2.224404
+.ends
+
+.subckt netg2235 g2235_3 g2235_1 g2235_2 g2235_0 gnd
+C1  g2235_3 gnd 2.080806f
+C2  g2235_1 gnd 2.080806f
+C3  g2235_2 gnd 2.080806f
+C4  g2235_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g2235_0 2.224404
+R2 1 g2235_3 2.224404
+C6 2 gnd 2.080806f
+R3 g2235_3 2 2.224404
+C7 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g2235_1 2.224404
+C8 4 gnd 2.080806f
+R6 g2235_1 4 2.224404
+R7 4 g2235_2 2.224404
+.ends
+
+.subckt netg5783 g5783_0 g5783_1 gnd
+C1  g5783_0 gnd 2.080806f
+C2  g5783_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5783_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+R7 6 g5783_1 2.224404
+.ends
+
+.subckt netg816 g816_4 g816_0 g816_3 gnd
+C1  g816_4 gnd 2.080806f
+C2  g816_0 gnd 2.080806f
+C3  g816_3 gnd 2.080806f
+R1 g816_0 g816_3 2.224404
+C4 1 gnd 2.080806f
+R2 1 g816_0 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+R7 g816_4 5 2.224404
+.ends
+
+.subckt netg3013 g3013_1 g3013_4 g3013_2 g3013_0 g3013_5 g3013_3 gnd
+C1  g3013_1 gnd 2.080806f
+C2  g3013_4 gnd 2.080806f
+C3  g3013_2 gnd 2.080806f
+C4  g3013_0 gnd 2.080806f
+C5  g3013_5 gnd 2.080806f
+C6  g3013_3 gnd 2.080806f
+R1 g3013_4 g3013_0 2.224404
+C7 1 gnd 2.080806f
+R2 g3013_0 1 2.224404
+R3 1 g3013_3 2.224404
+C8 2 gnd 2.080806f
+R4 2 g3013_4 2.224404
+R5 g3013_1 2 2.224404
+C9 3 gnd 2.080806f
+R6 3 g3013_1 2.224404
+R7 g3013_2 3 2.224404
+C10 4 gnd 2.080806f
+R8 g3013_1 4 2.224404
+R9 4 g3013_5 2.224404
+.ends
+
+.subckt netg7284 g7284_2 g7284_1 gnd
+C1  g7284_2 gnd 2.080806f
+C2  g7284_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7284_1 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+R7 g7284_2 6 2.224404
+.ends
+
+.subckt netg6859 g6859_0 g6859_2 g6859_1 gnd
+C1  g6859_0 gnd 2.080806f
+C2  g6859_2 gnd 2.080806f
+C3  g6859_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g6859_0 2.224404
+R2 g6859_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 g6859_0 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+C8 5 gnd 2.080806f
+R6 4 5 2.224404
+R7 5 g6859_2 2.224404
+.ends
+
+.subckt netg1576 g1576_1 g1576_0 gnd
+C1  g1576_1 gnd 2.080806f
+C2  g1576_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1576_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+R7 g1576_1 6 2.224404
+.ends
+
+.subckt netg4884 g4884_2 g4884_0 gnd
+C1  g4884_2 gnd 2.080806f
+C2  g4884_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4884_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+R7 6 g4884_2 2.224404
+.ends
+
+.subckt netg3988 g3988_2 g3988_4 g3988_3 g3988_1 g3988_5 g3988_0 gnd
+C1  g3988_2 gnd 2.080806f
+C2  g3988_4 gnd 2.080806f
+C3  g3988_3 gnd 2.080806f
+C4  g3988_1 gnd 2.080806f
+C5  g3988_5 gnd 2.080806f
+C6  g3988_0 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g3988_0 2.224404
+R2 1 g3988_3 2.224404
+C8 2 gnd 2.080806f
+R3 g3988_0 2 2.224404
+R4 2 g3988_5 2.224404
+C9 3 gnd 2.080806f
+R5 3 g3988_3 2.224404
+R6 g3988_4 3 2.224404
+R7 g3988_1 g3988_4 2.224404
+C10 4 gnd 2.080806f
+R8 4 1 2.224404
+R9 g3988_2 4 2.224404
+.ends
+
+.subckt netg2896 g2896_1 g2896_0 gnd
+C1  g2896_1 gnd 2.080806f
+C2  g2896_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2896_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+R7 g2896_1 6 2.224404
+.ends
+
+.subckt netg2977 g2977_0 g2977_1 g2977_2 gnd
+C1  g2977_0 gnd 2.080806f
+C2  g2977_1 gnd 2.080806f
+C3  g2977_2 gnd 2.080806f
+R1 g2977_2 g2977_0 2.224404
+C4 1 gnd 2.080806f
+R2 g2977_2 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 4 5 2.224404
+R7 g2977_1 5 2.224404
+.ends
+
+.subckt netg3683 g3683_1 g3683_0 g3683_3 gnd
+C1  g3683_1 gnd 2.080806f
+C2  g3683_0 gnd 2.080806f
+C3  g3683_3 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g3683_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g3683_1 3 2.224404
+C7 4 gnd 2.080806f
+R5 4 g3683_1 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+R7 g3683_3 5 2.224404
+.ends
+
+.subckt netg4233 g4233_1 g4233_0 gnd
+C1  g4233_1 gnd 2.080806f
+C2  g4233_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4233_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+R7 g4233_1 6 2.224404
+.ends
+
+.subckt netg4771 g4771_3 g4771_2 g4771_1 g4771_0 gnd
+C1  g4771_3 gnd 2.080806f
+C2  g4771_2 gnd 2.080806f
+C3  g4771_1 gnd 2.080806f
+C4  g4771_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g4771_0 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+C7 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g4771_1 2.224404
+C8 4 gnd 2.080806f
+R5 g4771_1 4 2.224404
+R6 4 g4771_3 2.224404
+R7 g4771_3 g4771_2 2.224404
+.ends
+
+.subckt netg1363 g1363_0 g1363_1 gnd
+C1  g1363_0 gnd 2.080806f
+C2  g1363_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1363_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+R7 g1363_1 6 2.224404
+.ends
+
+.subckt netg116 g116_1 g116_0 gnd
+C1  g116_1 gnd 2.080806f
+C2  g116_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g116_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+R8 g116_1 7 2.224404
+.ends
+
+.subckt netg1909 g1909_1 g1909_0 gnd
+C1  g1909_1 gnd 2.080806f
+C2  g1909_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1909_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+R8 g1909_1 7 2.224404
+.ends
+
+.subckt netg1397 g1397_1 g1397_0 gnd
+C1  g1397_1 gnd 2.080806f
+C2  g1397_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1397_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+R8 7 g1397_1 2.224404
+.ends
+
+.subckt netg1914 g1914_0 g1914_1 gnd
+C1  g1914_0 gnd 2.080806f
+C2  g1914_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1914_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+R8 g1914_1 7 2.224404
+.ends
+
+.subckt netg1880 g1880_1 g1880_0 g1880_2 gnd
+C1  g1880_1 gnd 2.080806f
+C2  g1880_0 gnd 2.080806f
+C3  g1880_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g1880_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g1880_1 2.224404
+C7 4 gnd 2.080806f
+R5 g1880_1 4 2.224404
+C8 5 gnd 2.080806f
+R6 4 5 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+R8 6 g1880_2 2.224404
+.ends
+
+.subckt netg5197 g5197_2 g5197_1 gnd
+C1  g5197_2 gnd 2.080806f
+C2  g5197_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5197_1 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+R8 7 g5197_2 2.224404
+.ends
+
+.subckt netg6045 g6045_0 g6045_1 gnd
+C1  g6045_0 gnd 2.080806f
+C2  g6045_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6045_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+R8 7 g6045_1 2.224404
+.ends
+
+.subckt netg5496 g5496_2 g5496_0 g5496_1 gnd
+C1  g5496_2 gnd 2.080806f
+C2  g5496_0 gnd 2.080806f
+C3  g5496_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5496_0 2.224404
+R2 g5496_2 1 2.224404
+C5 2 gnd 2.080806f
+R3 g5496_0 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+C8 5 gnd 2.080806f
+R6 4 5 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+R8 6 g5496_1 2.224404
+.ends
+
+.subckt netg4908 g4908_2 g4908_4 g4908_1 g4908_3 g4908_0 gnd
+C1  g4908_2 gnd 2.080806f
+C2  g4908_4 gnd 2.080806f
+C3  g4908_1 gnd 2.080806f
+C4  g4908_3 gnd 2.080806f
+C5  g4908_0 gnd 2.080806f
+C6 1 gnd 2.080806f
+R1 g4908_0 1 2.224404
+C7 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g4908_4 2.224404
+C8 3 gnd 2.080806f
+R4 2 3 2.224404
+C9 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 4 g4908_2 2.224404
+C10 5 gnd 2.080806f
+R7 g4908_2 5 2.224404
+R8 5 g4908_3 2.224404
+R9 g4908_3 g4908_1 2.224404
+.ends
+
+.subckt netg1505 g1505_1 g1505_0 gnd
+C1  g1505_1 gnd 2.080806f
+C2  g1505_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1505_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+R8 7 g1505_1 2.224404
+.ends
+
+.subckt netg5234 g5234_1 g5234_0 gnd
+C1  g5234_1 gnd 2.080806f
+C2  g5234_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5234_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+R8 g5234_1 7 2.224404
+.ends
+
+.subckt netg1898 g1898_0 g1898_1 gnd
+C1  g1898_0 gnd 2.080806f
+C2  g1898_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1898_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+R8 7 g1898_1 2.224404
+.ends
+
+.subckt netg1504 g1504_0 g1504_1 gnd
+C1  g1504_0 gnd 2.080806f
+C2  g1504_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1504_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+R8 g1504_1 7 2.224404
+.ends
+
+.subckt netg7038 g7038_1 g7038_0 g7038_2 gnd
+C1  g7038_1 gnd 2.080806f
+C2  g7038_0 gnd 2.080806f
+C3  g7038_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g7038_0 2.224404
+R2 g7038_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 g7038_0 2 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+C8 5 gnd 2.080806f
+R6 4 5 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+R8 6 g7038_2 2.224404
+.ends
+
+.subckt netg4088 g4088_2 g4088_1 g4088_3 g4088_0 gnd
+C1  g4088_2 gnd 2.080806f
+C2  g4088_1 gnd 2.080806f
+C3  g4088_3 gnd 2.080806f
+C4  g4088_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g4088_0 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+C7 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 3 g4088_1 2.224404
+C8 4 gnd 2.080806f
+R5 g4088_1 4 2.224404
+C9 5 gnd 2.080806f
+R6 4 5 2.224404
+R7 5 g4088_3 2.224404
+R8 g4088_3 g4088_2 2.224404
+.ends
+
+.subckt netg5235 g5235_0 g5235_1 gnd
+C1  g5235_0 gnd 2.080806f
+C2  g5235_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5235_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+R8 g5235_1 7 2.224404
+.ends
+
+.subckt netg1144 g1144_2 g1144_5 g1144_3 g1144_1 g1144_4 g1144_0 gnd
+C1  g1144_2 gnd 2.080806f
+C2  g1144_5 gnd 2.080806f
+C3  g1144_3 gnd 2.080806f
+C4  g1144_1 gnd 2.080806f
+C5  g1144_4 gnd 2.080806f
+C6  g1144_0 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 g1144_0 1 2.224404
+R2 1 g1144_3 2.224404
+C8 2 gnd 2.080806f
+R3 2 g1144_0 2.224404
+C9 3 gnd 2.080806f
+R4 3 2 2.224404
+R5 g1144_1 3 2.224404
+R6 g1144_1 g1144_2 2.224404
+C10 4 gnd 2.080806f
+R7 1 4 2.224404
+R8 4 g1144_4 2.224404
+R9 g1144_5 g1144_4 2.224404
+.ends
+
+.subckt netg1580 g1580_1 g1580_0 gnd
+C1  g1580_1 gnd 2.080806f
+C2  g1580_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1580_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+R8 g1580_1 7 2.224404
+.ends
+
+.subckt netg4314 g4314_1 g4314_0 gnd
+C1  g4314_1 gnd 2.080806f
+C2  g4314_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4314_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+R8 g4314_1 7 2.224404
+.ends
+
+.subckt netg2890 g2890_3 g2890_1 g2890_5 g2890_0 g2890_4 g2890_2 gnd
+C1  g2890_3 gnd 2.080806f
+C2  g2890_1 gnd 2.080806f
+C3  g2890_5 gnd 2.080806f
+C4  g2890_0 gnd 2.080806f
+C5  g2890_4 gnd 2.080806f
+C6  g2890_2 gnd 2.080806f
+R1 g2890_1 g2890_0 2.224404
+R2 g2890_4 g2890_0 2.224404
+C7 1 gnd 2.080806f
+R3 1 g2890_1 2.224404
+C8 2 gnd 2.080806f
+R4 2 1 2.224404
+C9 3 gnd 2.080806f
+R5 3 2 2.224404
+R6 g2890_5 3 2.224404
+R7 g2890_2 g2890_5 2.224404
+C10 4 gnd 2.080806f
+R8 g2890_2 4 2.224404
+C11 5 gnd 2.080806f
+R9 4 5 2.224404
+R10 g2890_3 5 2.224404
+.ends
+
+.subckt netg1670 g1670_3 g1670_2 g1670_0 g1670_1 gnd
+C1  g1670_3 gnd 2.080806f
+C2  g1670_2 gnd 2.080806f
+C3  g1670_0 gnd 2.080806f
+C4  g1670_1 gnd 2.080806f
+R1 g1670_1 g1670_0 2.224404
+C5 1 gnd 2.080806f
+R2 g1670_0 1 2.224404
+C6 2 gnd 2.080806f
+R3 1 2 2.224404
+C7 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g1670_3 2.224404
+C8 4 gnd 2.080806f
+R6 2 4 2.224404
+C9 5 gnd 2.080806f
+R7 4 5 2.224404
+R8 5 g1670_2 2.224404
+.ends
+
+.subckt netg1495 g1495_0 g1495_1 gnd
+C1  g1495_0 gnd 2.080806f
+C2  g1495_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1495_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+R8 7 g1495_1 2.224404
+.ends
+
+.subckt netg6781 g6781_1 g6781_0 g6781_2 gnd
+C1  g6781_1 gnd 2.080806f
+C2  g6781_0 gnd 2.080806f
+C3  g6781_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g6781_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g6781_2 2.224404
+C7 4 gnd 2.080806f
+R5 g6781_2 4 2.224404
+C8 5 gnd 2.080806f
+R6 4 5 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+R8 6 g6781_1 2.224404
+.ends
+
+.subckt netg3204 g3204_2 g3204_1 gnd
+C1  g3204_2 gnd 2.080806f
+C2  g3204_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3204_1 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+R8 g3204_2 7 2.224404
+.ends
+
+.subckt netg6757 g6757_2 g6757_1 g6757_0 gnd
+C1  g6757_2 gnd 2.080806f
+C2  g6757_1 gnd 2.080806f
+C3  g6757_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g6757_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+C8 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 5 g6757_2 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+R8 6 g6757_1 2.224404
+.ends
+
+.subckt netg1527 g1527_1 g1527_0 gnd
+C1  g1527_1 gnd 2.080806f
+C2  g1527_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1527_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+R8 7 g1527_1 2.224404
+.ends
+
+.subckt netg2922 g2922_0 g2922_1 gnd
+C1  g2922_0 gnd 2.080806f
+C2  g2922_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2922_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+R8 g2922_1 7 2.224404
+.ends
+
+.subckt netg1920 g1920_0 g1920_1 gnd
+C1  g1920_0 gnd 2.080806f
+C2  g1920_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1920_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+R8 g1920_1 7 2.224404
+.ends
+
+.subckt netg5755 g5755_2 g5755_1 g5755_0 gnd
+C1  g5755_2 gnd 2.080806f
+C2  g5755_1 gnd 2.080806f
+C3  g5755_0 gnd 2.080806f
+R1 g5755_0 g5755_1 2.224404
+C4 1 gnd 2.080806f
+R2 g5755_0 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+C8 5 gnd 2.080806f
+R6 4 5 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+R8 g5755_2 6 2.224404
+.ends
+
+.subckt netg4611 g4611_2 g4611_5 g4611_1 g4611_4 g4611_0 g4611_3 gnd
+C1  g4611_2 gnd 2.080806f
+C2  g4611_5 gnd 2.080806f
+C3  g4611_1 gnd 2.080806f
+C4  g4611_4 gnd 2.080806f
+C5  g4611_0 gnd 2.080806f
+C6  g4611_3 gnd 2.080806f
+R1 g4611_2 g4611_0 2.224404
+C7 1 gnd 2.080806f
+R2 g4611_0 1 2.224404
+R3 1 g4611_4 2.224404
+R4 g4611_4 g4611_5 2.224404
+C8 2 gnd 2.080806f
+R5 g4611_4 2 2.224404
+C9 3 gnd 2.080806f
+R6 2 3 2.224404
+R7 3 g4611_1 2.224404
+C10 4 gnd 2.080806f
+R8 g4611_1 4 2.224404
+R9 4 g4611_3 2.224404
+.ends
+
+.subckt netg1437 g1437_0 g1437_1 gnd
+C1  g1437_0 gnd 2.080806f
+C2  g1437_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1437_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+R8 7 g1437_1 2.224404
+.ends
+
+.subckt netg1891 g1891_0 g1891_1 gnd
+C1  g1891_0 gnd 2.080806f
+C2  g1891_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1891_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+R8 g1891_1 7 2.224404
+.ends
+
+.subckt netg1915 g1915_1 g1915_0 gnd
+C1  g1915_1 gnd 2.080806f
+C2  g1915_0 gnd 2.080806f
+.ends
+
+.subckt netg2167 g2167_1 g2167_0 g2167_3 g2167_2 gnd
+C1  g2167_1 gnd 2.080806f
+C2  g2167_0 gnd 2.080806f
+C3  g2167_3 gnd 2.080806f
+C4  g2167_2 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g2167_0 2.224404
+R2 g2167_2 1 2.224404
+C6 2 gnd 2.080806f
+R3 2 g2167_0 2.224404
+C7 3 gnd 2.080806f
+R4 3 2 2.224404
+C8 4 gnd 2.080806f
+R5 4 3 2.224404
+C9 5 gnd 2.080806f
+R6 5 4 2.224404
+R7 g2167_1 5 2.224404
+C10 6 gnd 2.080806f
+R8 6 g2167_1 2.224404
+C11 7 gnd 2.080806f
+R9 7 6 2.224404
+R10 g2167_3 7 2.224404
+.ends
+
+.subckt netg3282 g3282_2 g3282_1 g3282_0 gnd
+C1  g3282_2 gnd 2.080806f
+C2  g3282_1 gnd 2.080806f
+C3  g3282_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g3282_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g3282_2 2 2.224404
+C6 3 gnd 2.080806f
+R4 3 g3282_2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 6 7 2.224404
+R9 g3282_1 7 2.224404
+.ends
+
+.subckt netg3713 g3713_1 g3713_0 g3713_2 gnd
+C1  g3713_1 gnd 2.080806f
+C2  g3713_0 gnd 2.080806f
+C3  g3713_2 gnd 2.080806f
+R1 g3713_1 g3713_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g3713_0 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 4 5 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+R8 6 g3713_2 2.224404
+.ends
+
+.subckt netg4124 g4124_2 g4124_3 g4124_1 g4124_0 gnd
+C1  g4124_2 gnd 2.080806f
+C2  g4124_3 gnd 2.080806f
+C3  g4124_1 gnd 2.080806f
+C4  g4124_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g4124_0 1 2.224404
+R2 1 g4124_1 2.224404
+C6 2 gnd 2.080806f
+R3 g4124_1 2 2.224404
+C7 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g4124_3 2.224404
+C8 4 gnd 2.080806f
+R6 g4124_3 4 2.224404
+C9 5 gnd 2.080806f
+R7 4 5 2.224404
+R8 5 g4124_2 2.224404
+.ends
+
+.subckt netg117 g117_0 g117_1 gnd
+C1  g117_0 gnd 2.080806f
+C2  g117_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g117_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+R8 7 g117_1 2.224404
+.ends
+
+.subckt netg3725 g3725_9 g3725_8 g3725_6 g3725_5 g3725_10 g3725_0 g3725_2 g3725_3 g3725_7 gnd
+C1  g3725_9 gnd 2.080806f
+C2  g3725_8 gnd 2.080806f
+C3  g3725_6 gnd 2.080806f
+C4  g3725_5 gnd 2.080806f
+C5  g3725_10 gnd 2.080806f
+C6  g3725_0 gnd 2.080806f
+C7  g3725_2 gnd 2.080806f
+C8  g3725_3 gnd 2.080806f
+C9  g3725_7 gnd 2.080806f
+R1 g3725_5 g3725_0 2.224404
+R2 g3725_8 g3725_5 2.224404
+C10 1 gnd 2.080806f
+R3 g3725_0 1 2.224404
+R4 1 g3725_7 2.224404
+C11 2 gnd 2.080806f
+R5 g3725_8 2 2.224404
+R6 2 g3725_9 2.224404
+R7 g3725_2 g3725_9 2.224404
+R8 1 g3725_3 2.224404
+C12 3 gnd 2.080806f
+R9 3 g3725_8 2.224404
+R10 g3725_10 3 2.224404
+C13 4 gnd 2.080806f
+R11 4 g3725_2 2.224404
+R12 g3725_6 4 2.224404
+.ends
+
+.subckt netg4143 g4143_1 g4143_0 g4143_2 gnd
+C1  g4143_1 gnd 2.080806f
+C2  g4143_0 gnd 2.080806f
+C3  g4143_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g4143_0 1 2.224404
+R2 1 g4143_2 2.224404
+C5 2 gnd 2.080806f
+R3 2 g4143_2 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+R8 6 g4143_1 2.224404
+.ends
+
+.subckt netg1192 g1192_1 g1192_0 g1192_5 g1192_2 g1192_6 g1192_3 gnd
+C1  g1192_1 gnd 2.080806f
+C2  g1192_0 gnd 2.080806f
+C3  g1192_5 gnd 2.080806f
+C4  g1192_2 gnd 2.080806f
+C5  g1192_6 gnd 2.080806f
+C6  g1192_3 gnd 2.080806f
+R1 g1192_0 g1192_5 2.224404
+C7 1 gnd 2.080806f
+R2 1 g1192_0 2.224404
+R3 g1192_2 1 2.224404
+C8 2 gnd 2.080806f
+R4 2 g1192_0 2.224404
+C9 3 gnd 2.080806f
+R5 3 2 2.224404
+R6 g1192_1 3 2.224404
+R7 g1192_3 g1192_1 2.224404
+C10 4 gnd 2.080806f
+R8 4 g1192_3 2.224404
+C11 5 gnd 2.080806f
+R9 5 4 2.224404
+R10 g1192_6 5 2.224404
+.ends
+
+.subckt netg6336 g6336_0 g6336_1 g6336_3 g6336_2 gnd
+C1  g6336_0 gnd 2.080806f
+C2  g6336_1 gnd 2.080806f
+C3  g6336_3 gnd 2.080806f
+C4  g6336_2 gnd 2.080806f
+R1 g6336_0 g6336_3 2.224404
+R2 g6336_3 g6336_1 2.224404
+C5 1 gnd 2.080806f
+R3 g6336_1 1 2.224404
+C6 2 gnd 2.080806f
+R4 1 2 2.224404
+C7 3 gnd 2.080806f
+R5 2 3 2.224404
+C8 4 gnd 2.080806f
+R6 3 4 2.224404
+C9 5 gnd 2.080806f
+R7 4 5 2.224404
+R8 5 g6336_2 2.224404
+.ends
+
+.subckt netg518 g518_1 g518_0 gnd
+C1  g518_1 gnd 2.080806f
+C2  g518_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g518_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+R8 g518_1 7 2.224404
+.ends
+
+.subckt netg1528 g1528_1 g1528_0 gnd
+C1  g1528_1 gnd 2.080806f
+C2  g1528_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1528_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+R8 7 g1528_1 2.224404
+.ends
+
+.subckt netg3797 g3797_2 g3797_5 g3797_0 g3797_4 g3797_3 gnd
+C1  g3797_2 gnd 2.080806f
+C2  g3797_5 gnd 2.080806f
+C3  g3797_0 gnd 2.080806f
+C4  g3797_4 gnd 2.080806f
+C5  g3797_3 gnd 2.080806f
+C6 1 gnd 2.080806f
+R1 1 g3797_0 2.224404
+C7 2 gnd 2.080806f
+R2 2 1 2.224404
+C8 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g3797_4 3 2.224404
+R5 g3797_3 g3797_4 2.224404
+C9 4 gnd 2.080806f
+R6 g3797_3 4 2.224404
+C10 5 gnd 2.080806f
+R7 4 5 2.224404
+R8 g3797_5 5 2.224404
+C11 6 gnd 2.080806f
+R9 6 g3797_5 2.224404
+C12 7 gnd 2.080806f
+R10 7 6 2.224404
+R11 g3797_2 7 2.224404
+.ends
+
+.subckt netg85 g85_0 g85_1 gnd
+C1  g85_0 gnd 2.080806f
+C2  g85_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g85_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+R8 7 g85_1 2.224404
+.ends
+
+.subckt netg1990 g1990_2 g1990_0 g1990_3 g1990_1 gnd
+C1  g1990_2 gnd 2.080806f
+C2  g1990_0 gnd 2.080806f
+C3  g1990_3 gnd 2.080806f
+C4  g1990_1 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g1990_0 2.224404
+R2 g1990_2 1 2.224404
+C6 2 gnd 2.080806f
+R3 2 1 2.224404
+R4 g1990_3 2 2.224404
+C7 3 gnd 2.080806f
+R5 3 g1990_3 2.224404
+C8 4 gnd 2.080806f
+R6 4 3 2.224404
+C9 5 gnd 2.080806f
+R7 5 4 2.224404
+C10 6 gnd 2.080806f
+R8 6 5 2.224404
+R9 g1990_1 6 2.224404
+.ends
+
+.subckt netg1515 g1515_0 g1515_1 gnd
+C1  g1515_0 gnd 2.080806f
+C2  g1515_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1515_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+R9 g1515_1 8 2.224404
+.ends
+
+.subckt netg1440 g1440_5 g1440_2 g1440_3 g1440_1 g1440_4 g1440_0 gnd
+C1  g1440_5 gnd 2.080806f
+C2  g1440_2 gnd 2.080806f
+C3  g1440_3 gnd 2.080806f
+C4  g1440_1 gnd 2.080806f
+C5  g1440_4 gnd 2.080806f
+C6  g1440_0 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 g1440_0 1 2.224404
+R2 1 g1440_2 2.224404
+R3 g1440_2 g1440_5 2.224404
+R4 g1440_5 g1440_4 2.224404
+R5 g1440_3 g1440_4 2.224404
+C8 2 gnd 2.080806f
+R6 g1440_4 2 2.224404
+C9 3 gnd 2.080806f
+R7 2 3 2.224404
+C10 4 gnd 2.080806f
+R8 3 4 2.224404
+R9 4 g1440_1 2.224404
+.ends
+
+.subckt netg3907 g3907_2 g3907_4 g3907_1 g3907_0 g3907_5 g3907_3 gnd
+C1  g3907_2 gnd 2.080806f
+C2  g3907_4 gnd 2.080806f
+C3  g3907_1 gnd 2.080806f
+C4  g3907_0 gnd 2.080806f
+C5  g3907_5 gnd 2.080806f
+C6  g3907_3 gnd 2.080806f
+R1 g3907_0 g3907_3 2.224404
+C7 1 gnd 2.080806f
+R2 g3907_3 1 2.224404
+C8 2 gnd 2.080806f
+R3 1 2 2.224404
+C9 3 gnd 2.080806f
+R4 2 3 2.224404
+C10 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 4 g3907_1 2.224404
+C11 5 gnd 2.080806f
+R7 g3907_1 5 2.224404
+R8 5 g3907_2 2.224404
+R9 g3907_2 g3907_5 2.224404
+R10 g3907_4 g3907_5 2.224404
+.ends
+
+.subckt netg6016 g6016_5 g6016_4 g6016_3 g6016_2 g6016_0 g6016_6 g6016_1 gnd
+C1  g6016_5 gnd 2.080806f
+C2  g6016_4 gnd 2.080806f
+C3  g6016_3 gnd 2.080806f
+C4  g6016_2 gnd 2.080806f
+C5  g6016_0 gnd 2.080806f
+C6  g6016_6 gnd 2.080806f
+C7  g6016_1 gnd 2.080806f
+R1 g6016_1 g6016_0 2.224404
+R2 g6016_6 g6016_0 2.224404
+R3 g6016_3 g6016_1 2.224404
+R4 g6016_5 g6016_3 2.224404
+C8 1 gnd 2.080806f
+R5 g6016_1 1 2.224404
+C9 2 gnd 2.080806f
+R6 1 2 2.224404
+R7 2 g6016_2 2.224404
+C10 3 gnd 2.080806f
+R8 g6016_2 3 2.224404
+C11 4 gnd 2.080806f
+R9 3 4 2.224404
+R10 g6016_4 4 2.224404
+.ends
+
+.subckt netg6204 g6204_0 g6204_1 gnd
+C1  g6204_0 gnd 2.080806f
+C2  g6204_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6204_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+R9 g6204_1 8 2.224404
+.ends
+
+.subckt netg7096 g7096_1 g7096_0 g7096_2 gnd
+C1  g7096_1 gnd 2.080806f
+C2  g7096_0 gnd 2.080806f
+C3  g7096_2 gnd 2.080806f
+R1 g7096_2 g7096_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g7096_2 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+R9 g7096_1 7 2.224404
+.ends
+
+.subckt netg7412 g7412_1 g7412_0 gnd
+C1  g7412_1 gnd 2.080806f
+C2  g7412_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7412_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+R9 8 g7412_1 2.224404
+.ends
+
+.subckt netg1723 g1723_0 g1723_2 g1723_3 g1723_1 gnd
+C1  g1723_0 gnd 2.080806f
+C2  g1723_2 gnd 2.080806f
+C3  g1723_3 gnd 2.080806f
+C4  g1723_1 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g1723_0 1 2.224404
+R2 1 g1723_1 2.224404
+C6 2 gnd 2.080806f
+R3 g1723_1 2 2.224404
+C7 3 gnd 2.080806f
+R4 2 3 2.224404
+C8 4 gnd 2.080806f
+R5 3 4 2.224404
+C9 5 gnd 2.080806f
+R6 4 5 2.224404
+R7 5 g1723_2 2.224404
+C10 6 gnd 2.080806f
+R8 6 g1723_2 2.224404
+C11 7 gnd 2.080806f
+R9 6 7 2.224404
+R10 7 g1723_3 2.224404
+.ends
+
+.subckt netg5824 g5824_0 g5824_1 g5824_2 gnd
+C1  g5824_0 gnd 2.080806f
+C2  g5824_1 gnd 2.080806f
+C3  g5824_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5824_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g5824_2 2.224404
+C6 3 gnd 2.080806f
+R4 3 g5824_0 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+R9 7 g5824_1 2.224404
+.ends
+
+.subckt netg3004 g3004_3 g3004_2 g3004_0 g3004_1 gnd
+C1  g3004_3 gnd 2.080806f
+C2  g3004_2 gnd 2.080806f
+C3  g3004_0 gnd 2.080806f
+C4  g3004_1 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g3004_0 1 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g3004_2 2.224404
+C7 3 gnd 2.080806f
+R4 3 g3004_0 2.224404
+C8 4 gnd 2.080806f
+R5 4 3 2.224404
+R6 g3004_3 4 2.224404
+C9 5 gnd 2.080806f
+R7 g3004_2 5 2.224404
+C10 6 gnd 2.080806f
+R8 5 6 2.224404
+R9 6 g3004_1 2.224404
+.ends
+
+.subckt netg5156 g5156_2 g5156_3 g5156_0 g5156_1 gnd
+C1  g5156_2 gnd 2.080806f
+C2  g5156_3 gnd 2.080806f
+C3  g5156_0 gnd 2.080806f
+C4  g5156_1 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g5156_0 1 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g5156_2 2.224404
+C7 3 gnd 2.080806f
+R4 g5156_2 3 2.224404
+C8 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 4 g5156_3 2.224404
+C9 5 gnd 2.080806f
+R7 g5156_3 5 2.224404
+C10 6 gnd 2.080806f
+R8 5 6 2.224404
+R9 6 g5156_1 2.224404
+.ends
+
+.subckt netg6939 g6939_1 g6939_0 gnd
+C1  g6939_1 gnd 2.080806f
+C2  g6939_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6939_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+R9 g6939_1 8 2.224404
+.ends
+
+.subckt netg7528 g7528_0 g7528_1 gnd
+C1  g7528_0 gnd 2.080806f
+C2  g7528_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7528_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+R9 8 g7528_1 2.224404
+.ends
+
+.subckt netg6377 g6377_3 g6377_1 g6377_2 g6377_0 gnd
+C1  g6377_3 gnd 2.080806f
+C2  g6377_1 gnd 2.080806f
+C3  g6377_2 gnd 2.080806f
+C4  g6377_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g6377_0 1 2.224404
+R2 g6377_3 1 2.224404
+C6 2 gnd 2.080806f
+R3 2 g6377_0 2.224404
+C7 3 gnd 2.080806f
+R4 3 2 2.224404
+C8 4 gnd 2.080806f
+R5 4 3 2.224404
+C9 5 gnd 2.080806f
+R6 5 4 2.224404
+R7 g6377_2 5 2.224404
+C10 6 gnd 2.080806f
+R8 6 g6377_2 2.224404
+C11 7 gnd 2.080806f
+R9 7 6 2.224404
+C12 8 gnd 2.080806f
+R10 7 8 2.224404
+R11 g6377_1 8 2.224404
+.ends
+
+.subckt netg2901 g2901_2 g2901_5 g2901_4 g2901_3 g2901_1 g2901_0 gnd
+C1  g2901_2 gnd 2.080806f
+C2  g2901_5 gnd 2.080806f
+C3  g2901_4 gnd 2.080806f
+C4  g2901_3 gnd 2.080806f
+C5  g2901_1 gnd 2.080806f
+C6  g2901_0 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 g2901_0 1 2.224404
+R2 g2901_3 1 2.224404
+C8 2 gnd 2.080806f
+R3 2 g2901_0 2.224404
+C9 3 gnd 2.080806f
+R4 3 2 2.224404
+C10 4 gnd 2.080806f
+R5 4 3 2.224404
+R6 g2901_1 4 2.224404
+R7 g2901_4 4 2.224404
+C11 5 gnd 2.080806f
+R8 g2901_4 5 2.224404
+C12 6 gnd 2.080806f
+R9 5 6 2.224404
+R10 6 g2901_2 2.224404
+C13 7 gnd 2.080806f
+R11 1 7 2.224404
+C14 8 gnd 2.080806f
+R12 7 8 2.224404
+R13 8 g2901_5 2.224404
+.ends
+
+.subckt netg5136 g5136_2 g5136_1 g5136_0 gnd
+C1  g5136_2 gnd 2.080806f
+C2  g5136_1 gnd 2.080806f
+C3  g5136_0 gnd 2.080806f
+R1 g5136_0 g5136_1 2.224404
+C4 1 gnd 2.080806f
+R2 g5136_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 6 7 2.224404
+R9 g5136_2 7 2.224404
+.ends
+
+.subckt netg1402 g1402_0 g1402_1 gnd
+C1  g1402_0 gnd 2.080806f
+C2  g1402_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1402_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+R9 8 g1402_1 2.224404
+.ends
+
+.subckt netg6359 g6359_1 g6359_0 gnd
+C1  g6359_1 gnd 2.080806f
+C2  g6359_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6359_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+R9 8 g6359_1 2.224404
+.ends
+
+.subckt netg4199 g4199_0 g4199_1 g4199_2 gnd
+C1  g4199_0 gnd 2.080806f
+C2  g4199_1 gnd 2.080806f
+C3  g4199_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g4199_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 g4199_2 5 2.224404
+C9 6 gnd 2.080806f
+R7 6 g4199_2 2.224404
+C10 7 gnd 2.080806f
+R8 6 7 2.224404
+R9 g4199_1 7 2.224404
+.ends
+
+.subckt netg4926 g4926_3 g4926_2 g4926_4 g4926_0 g4926_1 gnd
+C1  g4926_3 gnd 2.080806f
+C2  g4926_2 gnd 2.080806f
+C3  g4926_4 gnd 2.080806f
+C4  g4926_0 gnd 2.080806f
+C5  g4926_1 gnd 2.080806f
+C6 1 gnd 2.080806f
+R1 g4926_0 1 2.224404
+C7 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g4926_1 2.224404
+C8 3 gnd 2.080806f
+R4 g4926_0 3 2.224404
+C9 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 g4926_3 4 2.224404
+C10 5 gnd 2.080806f
+R7 5 g4926_3 2.224404
+R8 g4926_2 5 2.224404
+C11 6 gnd 2.080806f
+R9 6 g4926_3 2.224404
+C12 7 gnd 2.080806f
+R10 7 6 2.224404
+C13 8 gnd 2.080806f
+R11 8 7 2.224404
+R12 g4926_4 8 2.224404
+.ends
+
+.subckt netg2033 g2033_4 g2033_1 g2033_0 g2033_3 g2033_2 gnd
+C1  g2033_4 gnd 2.080806f
+C2  g2033_1 gnd 2.080806f
+C3  g2033_0 gnd 2.080806f
+C4  g2033_3 gnd 2.080806f
+C5  g2033_2 gnd 2.080806f
+C6 1 gnd 2.080806f
+R1 g2033_0 1 2.224404
+C7 2 gnd 2.080806f
+R2 1 2 2.224404
+C8 3 gnd 2.080806f
+R3 2 3 2.224404
+C9 4 gnd 2.080806f
+R4 3 4 2.224404
+C10 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 g2033_3 5 2.224404
+R7 g2033_3 g2033_4 2.224404
+C11 6 gnd 2.080806f
+R8 5 6 2.224404
+R9 6 g2033_2 2.224404
+R10 g2033_2 g2033_1 2.224404
+.ends
+
+.subckt netg5956 g5956_1 g5956_0 gnd
+C1  g5956_1 gnd 2.080806f
+C2  g5956_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5956_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+R9 g5956_1 8 2.224404
+.ends
+
+.subckt netg4863 g4863_4 g4863_5 g4863_2 g4863_1 g4863_3 g4863_0 gnd
+C1  g4863_4 gnd 2.080806f
+C2  g4863_5 gnd 2.080806f
+C3  g4863_2 gnd 2.080806f
+C4  g4863_1 gnd 2.080806f
+C5  g4863_3 gnd 2.080806f
+C6  g4863_0 gnd 2.080806f
+R1 g4863_0 g4863_2 2.224404
+C7 1 gnd 2.080806f
+R2 g4863_0 1 2.224404
+R3 1 g4863_3 2.224404
+C8 2 gnd 2.080806f
+R4 g4863_3 2 2.224404
+C9 3 gnd 2.080806f
+R5 2 3 2.224404
+R6 3 g4863_4 2.224404
+C10 4 gnd 2.080806f
+R7 4 g4863_3 2.224404
+C11 5 gnd 2.080806f
+R8 5 4 2.224404
+R9 g4863_5 5 2.224404
+C12 6 gnd 2.080806f
+R10 g4863_5 6 2.224404
+C13 7 gnd 2.080806f
+R11 6 7 2.224404
+R12 7 g4863_1 2.224404
+.ends
+
+.subckt netg2897 g2897_3 g2897_2 g2897_1 g2897_0 gnd
+C1  g2897_3 gnd 2.080806f
+C2  g2897_2 gnd 2.080806f
+C3  g2897_1 gnd 2.080806f
+C4  g2897_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g2897_0 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+C7 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g2897_3 3 2.224404
+C8 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 4 g2897_2 2.224404
+C9 5 gnd 2.080806f
+R7 g2897_0 5 2.224404
+C10 6 gnd 2.080806f
+R8 5 6 2.224404
+C11 7 gnd 2.080806f
+R9 6 7 2.224404
+C12 8 gnd 2.080806f
+R10 7 8 2.224404
+R11 8 g2897_1 2.224404
+.ends
+
+.subckt netg2881 g2881_3 g2881_2 g2881_0 gnd
+C1  g2881_3 gnd 2.080806f
+C2  g2881_2 gnd 2.080806f
+C3  g2881_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g2881_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 g2881_3 4 2.224404
+C8 5 gnd 2.080806f
+R6 1 5 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 6 7 2.224404
+C11 8 gnd 2.080806f
+R9 7 8 2.224404
+R10 8 g2881_2 2.224404
+.ends
+
+.subckt netg2163 g2163_2 g2163_3 g2163_1 gnd
+C1  g2163_2 gnd 2.080806f
+C2  g2163_3 gnd 2.080806f
+C3  g2163_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g2163_3 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+C8 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 5 g2163_2 2.224404
+C9 6 gnd 2.080806f
+R7 g2163_2 6 2.224404
+C10 7 gnd 2.080806f
+R8 6 7 2.224404
+R9 7 g2163_1 2.224404
+.ends
+
+.subckt netg5770 g5770_3 g5770_2 g5770_1 g5770_0 gnd
+C1  g5770_3 gnd 2.080806f
+C2  g5770_2 gnd 2.080806f
+C3  g5770_1 gnd 2.080806f
+C4  g5770_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g5770_0 1 2.224404
+R2 g5770_3 1 2.224404
+C6 2 gnd 2.080806f
+R3 2 g5770_0 2.224404
+C7 3 gnd 2.080806f
+R4 3 2 2.224404
+C8 4 gnd 2.080806f
+R5 4 3 2.224404
+C9 5 gnd 2.080806f
+R6 5 4 2.224404
+C10 6 gnd 2.080806f
+R7 6 5 2.224404
+R8 g5770_2 6 2.224404
+C11 7 gnd 2.080806f
+R9 7 g5770_2 2.224404
+R10 g5770_1 7 2.224404
+.ends
+
+.subckt netg5163 g5163_2 g5163_1 g5163_0 gnd
+C1  g5163_2 gnd 2.080806f
+C2  g5163_1 gnd 2.080806f
+C3  g5163_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5163_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g5163_2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+C8 5 gnd 2.080806f
+R6 4 5 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+C10 7 gnd 2.080806f
+R8 6 7 2.224404
+R9 7 g5163_1 2.224404
+.ends
+
+.subckt netg1401 g1401_1 g1401_0 gnd
+C1  g1401_1 gnd 2.080806f
+C2  g1401_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1401_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+R9 8 g1401_1 2.224404
+.ends
+
+.subckt netg2980 g2980_2 g2980_0 g2980_3 g2980_1 gnd
+C1  g2980_2 gnd 2.080806f
+C2  g2980_0 gnd 2.080806f
+C3  g2980_3 gnd 2.080806f
+C4  g2980_1 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g2980_0 2.224404
+R2 g2980_1 1 2.224404
+R3 g2980_2 1 2.224404
+C6 2 gnd 2.080806f
+R4 2 g2980_2 2.224404
+C7 3 gnd 2.080806f
+R5 3 2 2.224404
+C8 4 gnd 2.080806f
+R6 4 3 2.224404
+C9 5 gnd 2.080806f
+R7 5 4 2.224404
+C10 6 gnd 2.080806f
+R8 6 5 2.224404
+R9 g2980_3 6 2.224404
+.ends
+
+.subckt netg1577 g1577_0 g1577_1 gnd
+C1  g1577_0 gnd 2.080806f
+C2  g1577_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1577_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+R9 g1577_1 8 2.224404
+.ends
+
+.subckt netg835 g835_1 g835_4 g835_3 g835_2 g835_6 g835_5 g835_0 gnd
+C1  g835_1 gnd 2.080806f
+C2  g835_4 gnd 2.080806f
+C3  g835_3 gnd 2.080806f
+C4  g835_2 gnd 2.080806f
+C5  g835_6 gnd 2.080806f
+C6  g835_5 gnd 2.080806f
+C7  g835_0 gnd 2.080806f
+.ends
+
+.subckt netg3489 g3489_0 g3489_1 gnd
+C1  g3489_0 gnd 2.080806f
+C2  g3489_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3489_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+R10 9 g3489_1 2.224404
+.ends
+
+.subckt netg4532 g4532_5 g4532_4 g4532_2 g4532_6 g4532_1 g4532_3 g4532_0 gnd
+C1  g4532_5 gnd 2.080806f
+C2  g4532_4 gnd 2.080806f
+C3  g4532_2 gnd 2.080806f
+C4  g4532_6 gnd 2.080806f
+C5  g4532_1 gnd 2.080806f
+C6  g4532_3 gnd 2.080806f
+C7  g4532_0 gnd 2.080806f
+C8 1 gnd 2.080806f
+R1 1 g4532_0 2.224404
+R2 1 g4532_1 2.224404
+C9 2 gnd 2.080806f
+R3 2 1 2.224404
+R4 g4532_6 2 2.224404
+C10 3 gnd 2.080806f
+R5 g4532_0 3 2.224404
+C11 4 gnd 2.080806f
+R6 3 4 2.224404
+R7 4 g4532_5 2.224404
+R8 g4532_5 g4532_3 2.224404
+C12 5 gnd 2.080806f
+R9 4 5 2.224404
+R10 5 g4532_2 2.224404
+R11 g4532_2 g4532_4 2.224404
+.ends
+
+.subckt netg1902 g1902_1 g1902_0 gnd
+C1  g1902_1 gnd 2.080806f
+C2  g1902_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1902_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+R10 g1902_1 9 2.224404
+.ends
+
+.subckt netg6563 g6563_1 g6563_0 gnd
+C1  g6563_1 gnd 2.080806f
+C2  g6563_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6563_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+R10 g6563_1 9 2.224404
+.ends
+
+.subckt netg4622 g4622_0 g4622_1 gnd
+C1  g4622_0 gnd 2.080806f
+C2  g4622_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4622_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+R10 9 g4622_1 2.224404
+.ends
+
+.subckt netg3008 g3008_1 g3008_4 g3008_2 g3008_3 g3008_0 gnd
+C1  g3008_1 gnd 2.080806f
+C2  g3008_4 gnd 2.080806f
+C3  g3008_2 gnd 2.080806f
+C4  g3008_3 gnd 2.080806f
+C5  g3008_0 gnd 2.080806f
+C6 1 gnd 2.080806f
+R1 g3008_0 1 2.224404
+R2 1 g3008_4 2.224404
+C7 2 gnd 2.080806f
+R3 g3008_4 2 2.224404
+R4 2 g3008_2 2.224404
+C8 3 gnd 2.080806f
+R5 g3008_4 3 2.224404
+C9 4 gnd 2.080806f
+R6 3 4 2.224404
+C10 5 gnd 2.080806f
+R7 4 5 2.224404
+C11 6 gnd 2.080806f
+R8 5 6 2.224404
+R9 6 g3008_1 2.224404
+C12 7 gnd 2.080806f
+R10 g3008_1 7 2.224404
+C13 8 gnd 2.080806f
+R11 7 8 2.224404
+R12 8 g3008_3 2.224404
+.ends
+
+.subckt netg4623 g4623_0 g4623_1 gnd
+C1  g4623_0 gnd 2.080806f
+C2  g4623_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4623_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+R10 9 g4623_1 2.224404
+.ends
+
+.subckt netg6833 g6833_3 g6833_2 g6833_0 g6833_1 gnd
+C1  g6833_3 gnd 2.080806f
+C2  g6833_2 gnd 2.080806f
+C3  g6833_0 gnd 2.080806f
+C4  g6833_1 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g6833_0 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+C7 3 gnd 2.080806f
+R3 3 2 2.224404
+C8 4 gnd 2.080806f
+R4 4 3 2.224404
+C9 5 gnd 2.080806f
+R5 5 4 2.224404
+C10 6 gnd 2.080806f
+R6 6 5 2.224404
+R7 g6833_1 6 2.224404
+C11 7 gnd 2.080806f
+R8 g6833_1 7 2.224404
+C12 8 gnd 2.080806f
+R9 7 8 2.224404
+R10 8 g6833_2 2.224404
+C13 9 gnd 2.080806f
+R11 8 9 2.224404
+R12 9 g6833_3 2.224404
+.ends
+
+.subckt netg78 g78_0 g78_1 gnd
+C1  g78_0 gnd 2.080806f
+C2  g78_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g78_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+R10 g78_1 9 2.224404
+.ends
+
+.subckt netg1521 g1521_3 g1521_1 g1521_2 g1521_5 g1521_4 g1521_0 gnd
+C1  g1521_3 gnd 2.080806f
+C2  g1521_1 gnd 2.080806f
+C3  g1521_2 gnd 2.080806f
+C4  g1521_5 gnd 2.080806f
+C5  g1521_4 gnd 2.080806f
+C6  g1521_0 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 g1521_0 1 2.224404
+C8 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g1521_1 2.224404
+C9 3 gnd 2.080806f
+R4 3 g1521_0 2.224404
+C10 4 gnd 2.080806f
+R5 4 3 2.224404
+R6 g1521_4 4 2.224404
+C11 5 gnd 2.080806f
+R7 g1521_0 5 2.224404
+C12 6 gnd 2.080806f
+R8 5 6 2.224404
+R9 6 g1521_5 2.224404
+R10 g1521_5 g1521_2 2.224404
+C13 7 gnd 2.080806f
+R11 g1521_2 7 2.224404
+C14 8 gnd 2.080806f
+R12 7 8 2.224404
+R13 8 g1521_3 2.224404
+.ends
+
+.subckt netg5802 g5802_3 g5802_1 g5802_2 g5802_0 gnd
+C1  g5802_3 gnd 2.080806f
+C2  g5802_1 gnd 2.080806f
+C3  g5802_2 gnd 2.080806f
+C4  g5802_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g5802_0 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 2 g5802_3 2.224404
+C7 3 gnd 2.080806f
+R4 3 2 2.224404
+R5 g5802_2 3 2.224404
+C8 4 gnd 2.080806f
+R6 g5802_0 4 2.224404
+C9 5 gnd 2.080806f
+R7 4 5 2.224404
+C10 6 gnd 2.080806f
+R8 5 6 2.224404
+C11 7 gnd 2.080806f
+R9 6 7 2.224404
+C12 8 gnd 2.080806f
+R10 7 8 2.224404
+R11 8 g5802_1 2.224404
+.ends
+
+.subckt netx511 x511_0 x511_1 gnd
+C1  x511_0 gnd 2.080806f
+C2  x511_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 x511_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+R10 9 x511_1 2.224404
+.ends
+
+.subckt netg1892 g1892_1 g1892_0 gnd
+C1  g1892_1 gnd 2.080806f
+C2  g1892_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1892_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+R10 9 g1892_1 2.224404
+.ends
+
+.subckt netg4624 g4624_1 g4624_0 gnd
+C1  g4624_1 gnd 2.080806f
+C2  g4624_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4624_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+R10 9 g4624_1 2.224404
+.ends
+
+.subckt netg3994 g3994_1 g3994_4 g3994_0 g3994_2 g3994_3 gnd
+C1  g3994_1 gnd 2.080806f
+C2  g3994_4 gnd 2.080806f
+C3  g3994_0 gnd 2.080806f
+C4  g3994_2 gnd 2.080806f
+C5  g3994_3 gnd 2.080806f
+C6 1 gnd 2.080806f
+R1 g3994_0 1 2.224404
+R2 1 g3994_1 2.224404
+C7 2 gnd 2.080806f
+R3 2 g3994_0 2.224404
+C8 3 gnd 2.080806f
+R4 3 2 2.224404
+R5 3 g3994_4 2.224404
+R6 g3994_3 g3994_4 2.224404
+C9 4 gnd 2.080806f
+R7 g3994_4 4 2.224404
+C10 5 gnd 2.080806f
+R8 4 5 2.224404
+C11 6 gnd 2.080806f
+R9 5 6 2.224404
+R10 6 g3994_2 2.224404
+.ends
+
+.subckt netg1507 g1507_1 g1507_0 gnd
+C1  g1507_1 gnd 2.080806f
+C2  g1507_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1507_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+R10 g1507_1 9 2.224404
+.ends
+
+.subckt netg2984 g2984_1 g2984_3 g2984_0 g2984_4 g2984_2 gnd
+C1  g2984_1 gnd 2.080806f
+C2  g2984_3 gnd 2.080806f
+C3  g2984_0 gnd 2.080806f
+C4  g2984_4 gnd 2.080806f
+C5  g2984_2 gnd 2.080806f
+C6 1 gnd 2.080806f
+R1 g2984_0 1 2.224404
+C7 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g2984_1 2.224404
+C8 3 gnd 2.080806f
+R4 g2984_0 3 2.224404
+C9 4 gnd 2.080806f
+R5 3 4 2.224404
+C10 5 gnd 2.080806f
+R6 4 5 2.224404
+R7 5 g2984_3 2.224404
+C11 6 gnd 2.080806f
+R8 g2984_3 6 2.224404
+C12 7 gnd 2.080806f
+R9 6 7 2.224404
+C13 8 gnd 2.080806f
+R10 7 8 2.224404
+R11 8 g2984_2 2.224404
+C14 9 gnd 2.080806f
+R12 g2984_2 9 2.224404
+R13 9 g2984_4 2.224404
+.ends
+
+.subckt netg2071 g2071_2 g2071_0 g2071_1 g2071_3 gnd
+C1  g2071_2 gnd 2.080806f
+C2  g2071_0 gnd 2.080806f
+C3  g2071_1 gnd 2.080806f
+C4  g2071_3 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g2071_0 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+C7 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g2071_1 2.224404
+R5 g2071_3 3 2.224404
+C8 4 gnd 2.080806f
+R6 g2071_1 4 2.224404
+C9 5 gnd 2.080806f
+R7 4 5 2.224404
+C10 6 gnd 2.080806f
+R8 5 6 2.224404
+C11 7 gnd 2.080806f
+R9 6 7 2.224404
+C12 8 gnd 2.080806f
+R10 7 8 2.224404
+C13 9 gnd 2.080806f
+R11 8 9 2.224404
+R12 9 g2071_2 2.224404
+.ends
+
+.subckt netg3675 g3675_1 g3675_0 g3675_3 g3675_6 g3675_2 g3675_5 g3675_4 gnd
+C1  g3675_1 gnd 2.080806f
+C2  g3675_0 gnd 2.080806f
+C3  g3675_3 gnd 2.080806f
+C4  g3675_6 gnd 2.080806f
+C5  g3675_2 gnd 2.080806f
+C6  g3675_5 gnd 2.080806f
+C7  g3675_4 gnd 2.080806f
+C8 1 gnd 2.080806f
+R1 1 g3675_0 2.224404
+R2 g3675_5 1 2.224404
+C9 2 gnd 2.080806f
+R3 2 g3675_5 2.224404
+R4 g3675_3 2 2.224404
+R5 g3675_3 g3675_4 2.224404
+C10 3 gnd 2.080806f
+R6 g3675_4 3 2.224404
+C11 4 gnd 2.080806f
+R7 3 4 2.224404
+C12 5 gnd 2.080806f
+R8 4 5 2.224404
+R9 5 g3675_6 2.224404
+C13 6 gnd 2.080806f
+R10 g3675_6 6 2.224404
+R11 6 g3675_1 2.224404
+C14 7 gnd 2.080806f
+R12 g3675_1 7 2.224404
+C15 8 gnd 2.080806f
+R13 7 8 2.224404
+C16 9 gnd 2.080806f
+R14 8 9 2.224404
+R15 g3675_2 9 2.224404
+.ends
+
+.subckt netg1446 g1446_2 g1446_5 g1446_0 g1446_1 g1446_4 g1446_3 gnd
+C1  g1446_2 gnd 2.080806f
+C2  g1446_5 gnd 2.080806f
+C3  g1446_0 gnd 2.080806f
+C4  g1446_1 gnd 2.080806f
+C5  g1446_4 gnd 2.080806f
+C6  g1446_3 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 g1446_0 1 2.224404
+R2 1 g1446_2 2.224404
+R3 g1446_2 g1446_4 2.224404
+C8 2 gnd 2.080806f
+R4 2 g1446_2 2.224404
+R5 g1446_3 2 2.224404
+C9 3 gnd 2.080806f
+R6 3 g1446_3 2.224404
+C10 4 gnd 2.080806f
+R7 4 3 2.224404
+C11 5 gnd 2.080806f
+R8 5 4 2.224404
+C12 6 gnd 2.080806f
+R9 6 5 2.224404
+R10 g1446_5 6 2.224404
+C13 7 gnd 2.080806f
+R11 7 g1446_5 2.224404
+R12 g1446_1 7 2.224404
+.ends
+
+.subckt netg3654 g3654_8 g3654_7 g3654_10 g3654_4 g3654_9 g3654_0 g3654_2 g3654_3 g3654_1 g3654_6 g3654_5 gnd
+C1  g3654_8 gnd 2.080806f
+C2  g3654_7 gnd 2.080806f
+C3  g3654_10 gnd 2.080806f
+C4  g3654_4 gnd 2.080806f
+C5  g3654_9 gnd 2.080806f
+C6  g3654_0 gnd 2.080806f
+C7  g3654_2 gnd 2.080806f
+C8  g3654_3 gnd 2.080806f
+C9  g3654_1 gnd 2.080806f
+C10  g3654_6 gnd 2.080806f
+C11  g3654_5 gnd 2.080806f
+R1 g3654_3 g3654_0 2.224404
+C12 1 gnd 2.080806f
+R2 1 g3654_3 2.224404
+R3 g3654_4 1 2.224404
+C13 2 gnd 2.080806f
+R4 2 g3654_4 2.224404
+R5 g3654_2 2 2.224404
+R6 g3654_6 g3654_2 2.224404
+R7 g3654_5 g3654_6 2.224404
+R8 g3654_9 2 2.224404
+C14 3 gnd 2.080806f
+R9 3 g3654_9 2.224404
+R10 g3654_1 3 2.224404
+R11 g3654_1 g3654_7 2.224404
+C15 4 gnd 2.080806f
+R12 g3654_7 4 2.224404
+R13 4 g3654_10 2.224404
+C16 5 gnd 2.080806f
+R14 5 g3654_1 2.224404
+C17 6 gnd 2.080806f
+R15 6 5 2.224404
+R16 g3654_8 6 2.224404
+.ends
+
+.subckt netg92 g92_1 g92_0 gnd
+C1  g92_1 gnd 2.080806f
+C2  g92_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g92_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+R10 9 g92_1 2.224404
+.ends
+
+.subckt netg7533 g7533_0 g7533_1 gnd
+C1  g7533_0 gnd 2.080806f
+C2  g7533_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7533_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+R10 g7533_1 9 2.224404
+.ends
+
+.subckt netg2874 g2874_1 g2874_3 g2874_2 g2874_0 g2874_4 gnd
+C1  g2874_1 gnd 2.080806f
+C2  g2874_3 gnd 2.080806f
+C3  g2874_2 gnd 2.080806f
+C4  g2874_0 gnd 2.080806f
+C5  g2874_4 gnd 2.080806f
+C6 1 gnd 2.080806f
+R1 1 g2874_0 2.224404
+R2 1 g2874_4 2.224404
+C7 2 gnd 2.080806f
+R3 g2874_4 2 2.224404
+C8 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g2874_1 2.224404
+C9 4 gnd 2.080806f
+R6 4 g2874_1 2.224404
+C10 5 gnd 2.080806f
+R7 4 5 2.224404
+C11 6 gnd 2.080806f
+R8 5 6 2.224404
+R9 6 g2874_3 2.224404
+R10 g2874_2 g2874_3 2.224404
+.ends
+
+.subckt netg1199 g1199_2 g1199_0 g1199_5 g1199_3 g1199_1 g1199_6 g1199_4 gnd
+C1  g1199_2 gnd 2.080806f
+C2  g1199_0 gnd 2.080806f
+C3  g1199_5 gnd 2.080806f
+C4  g1199_3 gnd 2.080806f
+C5  g1199_1 gnd 2.080806f
+C6  g1199_6 gnd 2.080806f
+C7  g1199_4 gnd 2.080806f
+C8 1 gnd 2.080806f
+R1 g1199_0 1 2.224404
+R2 1 g1199_3 2.224404
+C9 2 gnd 2.080806f
+R3 g1199_0 2 2.224404
+R4 2 g1199_6 2.224404
+R5 2 g1199_5 2.224404
+C10 3 gnd 2.080806f
+R6 3 g1199_3 2.224404
+C11 4 gnd 2.080806f
+R7 4 3 2.224404
+R8 g1199_1 4 2.224404
+C12 5 gnd 2.080806f
+R9 g1199_6 5 2.224404
+C13 6 gnd 2.080806f
+R10 5 6 2.224404
+R11 g1199_2 6 2.224404
+C14 7 gnd 2.080806f
+R12 7 g1199_1 2.224404
+C15 8 gnd 2.080806f
+R13 8 7 2.224404
+R14 g1199_4 8 2.224404
+.ends
+
+.subckt netg1586 g1586_1 g1586_0 gnd
+C1  g1586_1 gnd 2.080806f
+C2  g1586_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1586_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+R10 g1586_1 9 2.224404
+.ends
+
+.subckt netg1403 g1403_0 g1403_1 gnd
+C1  g1403_0 gnd 2.080806f
+C2  g1403_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1403_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+R10 g1403_1 9 2.224404
+.ends
+
+.subckt netg107 g107_1 g107_0 gnd
+C1  g107_1 gnd 2.080806f
+C2  g107_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g107_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+R10 g107_1 9 2.224404
+.ends
+
+.subckt netg1097 g1097_1 g1097_0 gnd
+C1  g1097_1 gnd 2.080806f
+C2  g1097_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1097_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+R10 g1097_1 9 2.224404
+.ends
+
+.subckt netg2885 g2885_2 g2885_4 g2885_1 g2885_3 g2885_0 gnd
+C1  g2885_2 gnd 2.080806f
+C2  g2885_4 gnd 2.080806f
+C3  g2885_1 gnd 2.080806f
+C4  g2885_3 gnd 2.080806f
+C5  g2885_0 gnd 2.080806f
+C6 1 gnd 2.080806f
+R1 1 g2885_0 2.224404
+R2 1 g2885_2 2.224404
+C7 2 gnd 2.080806f
+R3 g2885_0 2 2.224404
+C8 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g2885_3 2.224404
+C9 4 gnd 2.080806f
+R6 g2885_3 4 2.224404
+C10 5 gnd 2.080806f
+R7 4 5 2.224404
+R8 5 g2885_4 2.224404
+C11 6 gnd 2.080806f
+R9 6 1 2.224404
+C12 7 gnd 2.080806f
+R10 7 6 2.224404
+R11 g2885_1 7 2.224404
+.ends
+
+.subckt netx492 x492_1 x492_0 gnd
+C1  x492_1 gnd 2.080806f
+C2  x492_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 x492_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+R10 9 x492_1 2.224404
+.ends
+
+.subckt netg6677 g6677_2 g6677_1 g6677_3 g6677_4 g6677_0 gnd
+C1  g6677_2 gnd 2.080806f
+C2  g6677_1 gnd 2.080806f
+C3  g6677_3 gnd 2.080806f
+C4  g6677_4 gnd 2.080806f
+C5  g6677_0 gnd 2.080806f
+R1 g6677_4 g6677_0 2.224404
+C6 1 gnd 2.080806f
+R2 g6677_4 1 2.224404
+C7 2 gnd 2.080806f
+R3 2 1 2.224404
+C8 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 g6677_2 3 2.224404
+C9 4 gnd 2.080806f
+R6 g6677_2 4 2.224404
+R7 g6677_3 4 2.224404
+C10 5 gnd 2.080806f
+R8 g6677_0 5 2.224404
+C11 6 gnd 2.080806f
+R9 5 6 2.224404
+C12 7 gnd 2.080806f
+R10 6 7 2.224404
+C13 8 gnd 2.080806f
+R11 7 8 2.224404
+R12 8 g6677_1 2.224404
+.ends
+
+.subckt netg5205 g5205_1 g5205_2 g5205_0 gnd
+C1  g5205_1 gnd 2.080806f
+C2  g5205_2 gnd 2.080806f
+C3  g5205_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5205_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 6 5 2.224404
+C10 7 gnd 2.080806f
+R7 7 6 2.224404
+C11 8 gnd 2.080806f
+R8 8 7 2.224404
+R9 g5205_2 8 2.224404
+R10 g5205_1 g5205_2 2.224404
+.ends
+
+.subckt netg4742 g4742_5 g4742_3 g4742_4 g4742_2 g4742_0 g4742_6 g4742_1 gnd
+C1  g4742_5 gnd 2.080806f
+C2  g4742_3 gnd 2.080806f
+C3  g4742_4 gnd 2.080806f
+C4  g4742_2 gnd 2.080806f
+C5  g4742_0 gnd 2.080806f
+C6  g4742_6 gnd 2.080806f
+C7  g4742_1 gnd 2.080806f
+R1 g4742_1 g4742_0 2.224404
+C8 1 gnd 2.080806f
+R2 g4742_0 1 2.224404
+C9 2 gnd 2.080806f
+R3 1 2 2.224404
+C10 3 gnd 2.080806f
+R4 3 2 2.224404
+C11 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 g4742_5 4 2.224404
+R7 g4742_2 g4742_5 2.224404
+R8 g4742_3 g4742_2 2.224404
+R9 g4742_6 g4742_3 2.224404
+C12 5 gnd 2.080806f
+R10 5 g4742_6 2.224404
+R11 g4742_4 5 2.224404
+.ends
+
+.subckt netg94 g94_1 g94_0 gnd
+C1  g94_1 gnd 2.080806f
+C2  g94_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g94_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+R10 g94_1 9 2.224404
+.ends
+
+.subckt netg1565 g1565_0 g1565_2 g1565_4 g1565_5 g1565_3 gnd
+C1  g1565_0 gnd 2.080806f
+C2  g1565_2 gnd 2.080806f
+C3  g1565_4 gnd 2.080806f
+C4  g1565_5 gnd 2.080806f
+C5  g1565_3 gnd 2.080806f
+C6 1 gnd 2.080806f
+R1 g1565_0 1 2.224404
+R2 1 g1565_5 2.224404
+C7 2 gnd 2.080806f
+R3 2 g1565_0 2.224404
+C8 3 gnd 2.080806f
+R4 3 2 2.224404
+C9 4 gnd 2.080806f
+R5 4 3 2.224404
+R6 g1565_2 4 2.224404
+C10 5 gnd 2.080806f
+R7 5 g1565_5 2.224404
+C11 6 gnd 2.080806f
+R8 6 5 2.224404
+C12 7 gnd 2.080806f
+R9 7 6 2.224404
+R10 g1565_4 7 2.224404
+C13 8 gnd 2.080806f
+R11 g1565_4 8 2.224404
+R12 8 g1565_3 2.224404
+.ends
+
+.subckt netg5493 g5493_0 g5493_2 g5493_1 gnd
+C1  g5493_0 gnd 2.080806f
+C2  g5493_2 gnd 2.080806f
+C3  g5493_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5493_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g5493_2 2 2.224404
+C6 3 gnd 2.080806f
+R4 3 g5493_2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+R11 g5493_1 9 2.224404
+.ends
+
+.subckt netg767 g767_4 g767_2 g767_0 g767_1 g767_3 gnd
+C1  g767_4 gnd 2.080806f
+C2  g767_2 gnd 2.080806f
+C3  g767_0 gnd 2.080806f
+C4  g767_1 gnd 2.080806f
+C5  g767_3 gnd 2.080806f
+C6 1 gnd 2.080806f
+R1 1 g767_0 2.224404
+C7 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g767_4 2 2.224404
+C8 3 gnd 2.080806f
+R4 g767_4 3 2.224404
+R5 3 g767_1 2.224404
+C9 4 gnd 2.080806f
+R6 g767_0 4 2.224404
+C10 5 gnd 2.080806f
+R7 4 5 2.224404
+C11 6 gnd 2.080806f
+R8 5 6 2.224404
+C12 7 gnd 2.080806f
+R9 6 7 2.224404
+R10 g767_3 7 2.224404
+C13 8 gnd 2.080806f
+R11 7 8 2.224404
+C14 9 gnd 2.080806f
+R12 8 9 2.224404
+R13 9 g767_2 2.224404
+.ends
+
+.subckt netg1795 g1795_2 g1795_3 g1795_1 gnd
+C1  g1795_2 gnd 2.080806f
+C2  g1795_3 gnd 2.080806f
+C3  g1795_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g1795_3 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g1795_2 2.224404
+C6 3 gnd 2.080806f
+R4 g1795_2 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+C8 5 gnd 2.080806f
+R6 4 5 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+C10 7 gnd 2.080806f
+R8 6 7 2.224404
+C11 8 gnd 2.080806f
+R9 7 8 2.224404
+C12 9 gnd 2.080806f
+R10 8 9 2.224404
+R11 9 g1795_1 2.224404
+.ends
+
+.subckt netg5178 g5178_1 g5178_0 g5178_2 gnd
+C1  g5178_1 gnd 2.080806f
+C2  g5178_0 gnd 2.080806f
+C3  g5178_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5178_0 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 5 6 2.224404
+C10 7 gnd 2.080806f
+R7 6 7 2.224404
+C11 8 gnd 2.080806f
+R8 8 7 2.224404
+C12 9 gnd 2.080806f
+R9 8 9 2.224404
+R10 g5178_1 9 2.224404
+R11 g5178_1 g5178_2 2.224404
+.ends
+
+.subckt netg2959 g2959_1 g2959_3 g2959_0 g2959_2 gnd
+C1  g2959_1 gnd 2.080806f
+C2  g2959_3 gnd 2.080806f
+C3  g2959_0 gnd 2.080806f
+C4  g2959_2 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g2959_0 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g2959_2 2 2.224404
+C7 3 gnd 2.080806f
+R4 3 g2959_2 2.224404
+C8 4 gnd 2.080806f
+R5 3 4 2.224404
+C9 5 gnd 2.080806f
+R6 4 5 2.224404
+C10 6 gnd 2.080806f
+R7 6 5 2.224404
+C11 7 gnd 2.080806f
+R8 6 7 2.224404
+R9 g2959_1 7 2.224404
+C12 8 gnd 2.080806f
+R10 7 8 2.224404
+R11 8 g2959_3 2.224404
+.ends
+
+.subckt netg1766 g1766_3 g1766_2 g1766_1 g1766_0 gnd
+C1  g1766_3 gnd 2.080806f
+C2  g1766_2 gnd 2.080806f
+C3  g1766_1 gnd 2.080806f
+C4  g1766_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g1766_0 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+C7 3 gnd 2.080806f
+R3 3 2 2.224404
+C8 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 g1766_3 4 2.224404
+C9 5 gnd 2.080806f
+R6 5 g1766_0 2.224404
+C10 6 gnd 2.080806f
+R7 6 5 2.224404
+C11 7 gnd 2.080806f
+R8 7 6 2.224404
+C12 8 gnd 2.080806f
+R9 8 7 2.224404
+C13 9 gnd 2.080806f
+R10 8 9 2.224404
+R11 9 g1766_2 2.224404
+C14 10 gnd 2.080806f
+R12 10 8 2.224404
+C15 11 gnd 2.080806f
+R13 11 10 2.224404
+R14 g1766_1 11 2.224404
+.ends
+
+.subckt netg418 g418_3 g418_4 g418_2 g418_0 gnd
+C1  g418_3 gnd 2.080806f
+C2  g418_4 gnd 2.080806f
+C3  g418_2 gnd 2.080806f
+C4  g418_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g418_0 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+C7 3 gnd 2.080806f
+R3 3 2 2.224404
+C8 4 gnd 2.080806f
+R4 4 3 2.224404
+C9 5 gnd 2.080806f
+R5 5 4 2.224404
+R6 g418_2 5 2.224404
+C10 6 gnd 2.080806f
+R7 6 g418_2 2.224404
+C11 7 gnd 2.080806f
+R8 7 6 2.224404
+R9 g418_4 7 2.224404
+C12 8 gnd 2.080806f
+R10 8 g418_4 2.224404
+R11 g418_3 8 2.224404
+.ends
+
+.subckt netg5395 g5395_0 g5395_4 g5395_2 g5395_1 g5395_5 g5395_3 g5395_6 g5395_8 g5395_7 gnd
+C1  g5395_0 gnd 2.080806f
+C2  g5395_4 gnd 2.080806f
+C3  g5395_2 gnd 2.080806f
+C4  g5395_1 gnd 2.080806f
+C5  g5395_5 gnd 2.080806f
+C6  g5395_3 gnd 2.080806f
+C7  g5395_6 gnd 2.080806f
+C8  g5395_8 gnd 2.080806f
+C9  g5395_7 gnd 2.080806f
+R1 g5395_0 g5395_2 2.224404
+R2 g5395_1 g5395_2 2.224404
+R3 g5395_2 g5395_5 2.224404
+C10 1 gnd 2.080806f
+R4 g5395_0 1 2.224404
+R5 1 g5395_8 2.224404
+R6 g5395_4 1 2.224404
+C11 2 gnd 2.080806f
+R7 2 g5395_8 2.224404
+R8 2 g5395_7 2.224404
+C12 3 gnd 2.080806f
+R9 g5395_7 3 2.224404
+C13 4 gnd 2.080806f
+R10 3 4 2.224404
+C14 5 gnd 2.080806f
+R11 4 5 2.224404
+R12 5 g5395_6 2.224404
+C15 6 gnd 2.080806f
+R13 5 6 2.224404
+R14 6 g5395_3 2.224404
+.ends
+
+.subckt netg1295 g1295_4 g1295_2 g1295_1 g1295_6 g1295_0 g1295_5 g1295_3 gnd
+C1  g1295_4 gnd 2.080806f
+C2  g1295_2 gnd 2.080806f
+C3  g1295_1 gnd 2.080806f
+C4  g1295_6 gnd 2.080806f
+C5  g1295_0 gnd 2.080806f
+C6  g1295_5 gnd 2.080806f
+C7  g1295_3 gnd 2.080806f
+.ends
+
+.subckt netx542 x542_1 x542_0 gnd
+C1  x542_1 gnd 2.080806f
+C2  x542_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 x542_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+R11 x542_1 10 2.224404
+.ends
+
+.subckt netg1778 g1778_0 g1778_3 g1778_1 g1778_2 gnd
+C1  g1778_0 gnd 2.080806f
+C2  g1778_3 gnd 2.080806f
+C3  g1778_1 gnd 2.080806f
+C4  g1778_2 gnd 2.080806f
+R1 g1778_3 g1778_0 2.224404
+C5 1 gnd 2.080806f
+R2 g1778_3 1 2.224404
+C6 2 gnd 2.080806f
+R3 1 2 2.224404
+C7 3 gnd 2.080806f
+R4 2 3 2.224404
+C8 4 gnd 2.080806f
+R5 4 3 2.224404
+C9 5 gnd 2.080806f
+R6 4 5 2.224404
+R7 g1778_1 5 2.224404
+C10 6 gnd 2.080806f
+R8 6 g1778_1 2.224404
+C11 7 gnd 2.080806f
+R9 7 6 2.224404
+C12 8 gnd 2.080806f
+R10 8 7 2.224404
+C13 9 gnd 2.080806f
+R11 9 8 2.224404
+C14 10 gnd 2.080806f
+R12 10 9 2.224404
+R13 g1778_2 10 2.224404
+.ends
+
+.subckt netg2038 g2038_0 g2038_3 g2038_5 g2038_4 g2038_2 g2038_1 gnd
+C1  g2038_0 gnd 2.080806f
+C2  g2038_3 gnd 2.080806f
+C3  g2038_5 gnd 2.080806f
+C4  g2038_4 gnd 2.080806f
+C5  g2038_2 gnd 2.080806f
+C6  g2038_1 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g2038_0 2.224404
+C8 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g2038_3 2 2.224404
+C9 3 gnd 2.080806f
+R4 g2038_0 3 2.224404
+C10 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 4 g2038_4 2.224404
+C11 5 gnd 2.080806f
+R7 1 5 2.224404
+C12 6 gnd 2.080806f
+R8 5 6 2.224404
+C13 7 gnd 2.080806f
+R9 6 7 2.224404
+R10 7 g2038_5 2.224404
+C14 8 gnd 2.080806f
+R11 g2038_5 8 2.224404
+C15 9 gnd 2.080806f
+R12 8 9 2.224404
+R13 9 g2038_1 2.224404
+C16 10 gnd 2.080806f
+R14 10 9 2.224404
+R15 g2038_2 10 2.224404
+.ends
+
+.subckt netg734 g734_1 g734_5 g734_4 g734_2 g734_0 gnd
+C1  g734_1 gnd 2.080806f
+C2  g734_5 gnd 2.080806f
+C3  g734_4 gnd 2.080806f
+C4  g734_2 gnd 2.080806f
+C5  g734_0 gnd 2.080806f
+C6 1 gnd 2.080806f
+R1 1 g734_0 2.224404
+C7 2 gnd 2.080806f
+R2 2 1 2.224404
+C8 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g734_1 3 2.224404
+R5 3 g734_2 2.224404
+C9 4 gnd 2.080806f
+R6 g734_0 4 2.224404
+C10 5 gnd 2.080806f
+R7 4 5 2.224404
+C11 6 gnd 2.080806f
+R8 5 6 2.224404
+R9 6 g734_4 2.224404
+C12 7 gnd 2.080806f
+R10 6 7 2.224404
+C13 8 gnd 2.080806f
+R11 7 8 2.224404
+R12 8 g734_5 2.224404
+.ends
+
+.subckt netg1269 g1269_2 g1269_4 g1269_5 g1269_3 g1269_0 g1269_1 gnd
+C1  g1269_2 gnd 2.080806f
+C2  g1269_4 gnd 2.080806f
+C3  g1269_5 gnd 2.080806f
+C4  g1269_3 gnd 2.080806f
+C5  g1269_0 gnd 2.080806f
+C6  g1269_1 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g1269_0 2.224404
+C8 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g1269_2 2 2.224404
+C9 3 gnd 2.080806f
+R4 2 3 2.224404
+C10 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 4 g1269_5 2.224404
+C11 5 gnd 2.080806f
+R7 g1269_5 5 2.224404
+R8 5 g1269_3 2.224404
+C12 6 gnd 2.080806f
+R9 g1269_3 6 2.224404
+C13 7 gnd 2.080806f
+R10 6 7 2.224404
+C14 8 gnd 2.080806f
+R11 7 8 2.224404
+R12 8 g1269_4 2.224404
+R13 g1269_4 g1269_1 2.224404
+.ends
+
+.subckt netg1608 g1608_3 g1608_0 g1608_1 g1608_2 gnd
+C1  g1608_3 gnd 2.080806f
+C2  g1608_0 gnd 2.080806f
+C3  g1608_1 gnd 2.080806f
+C4  g1608_2 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g1608_0 2.224404
+R2 1 g1608_3 2.224404
+C6 2 gnd 2.080806f
+R3 g1608_0 2 2.224404
+C7 3 gnd 2.080806f
+R4 2 3 2.224404
+C8 4 gnd 2.080806f
+R5 4 3 2.224404
+C9 5 gnd 2.080806f
+R6 4 5 2.224404
+C10 6 gnd 2.080806f
+R7 5 6 2.224404
+C11 7 gnd 2.080806f
+R8 7 6 2.224404
+C12 8 gnd 2.080806f
+R9 7 8 2.224404
+R10 g1608_2 8 2.224404
+R11 g1608_2 g1608_1 2.224404
+.ends
+
+.subckt netg1957 g1957_0 g1957_1 g1957_2 gnd
+C1  g1957_0 gnd 2.080806f
+C2  g1957_1 gnd 2.080806f
+C3  g1957_2 gnd 2.080806f
+R1 g1957_2 g1957_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g1957_2 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+R11 g1957_1 9 2.224404
+.ends
+
+.subckt netg1799 g1799_1 g1799_0 g1799_2 g1799_3 gnd
+C1  g1799_1 gnd 2.080806f
+C2  g1799_0 gnd 2.080806f
+C3  g1799_2 gnd 2.080806f
+C4  g1799_3 gnd 2.080806f
+R1 g1799_3 g1799_0 2.224404
+C5 1 gnd 2.080806f
+R2 1 g1799_3 2.224404
+C6 2 gnd 2.080806f
+R3 2 1 2.224404
+C7 3 gnd 2.080806f
+R4 3 2 2.224404
+C8 4 gnd 2.080806f
+R5 4 3 2.224404
+C9 5 gnd 2.080806f
+R6 5 4 2.224404
+C10 6 gnd 2.080806f
+R7 6 5 2.224404
+R8 g1799_1 6 2.224404
+C11 7 gnd 2.080806f
+R9 7 g1799_1 2.224404
+C12 8 gnd 2.080806f
+R10 8 7 2.224404
+R11 g1799_2 8 2.224404
+.ends
+
+.subckt netg7535 g7535_1 g7535_0 gnd
+C1  g7535_1 gnd 2.080806f
+C2  g7535_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7535_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+R11 g7535_1 10 2.224404
+.ends
+
+.subckt netg1624 g1624_1 g1624_2 g1624_3 g1624_0 gnd
+C1  g1624_1 gnd 2.080806f
+C2  g1624_2 gnd 2.080806f
+C3  g1624_3 gnd 2.080806f
+C4  g1624_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g1624_0 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+C7 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g1624_2 3 2.224404
+C8 4 gnd 2.080806f
+R5 g1624_0 4 2.224404
+C9 5 gnd 2.080806f
+R6 4 5 2.224404
+C10 6 gnd 2.080806f
+R7 5 6 2.224404
+C11 7 gnd 2.080806f
+R8 6 7 2.224404
+R9 7 g1624_1 2.224404
+C12 8 gnd 2.080806f
+R10 8 g1624_2 2.224404
+C13 9 gnd 2.080806f
+R11 8 9 2.224404
+C14 10 gnd 2.080806f
+R12 10 9 2.224404
+C15 11 gnd 2.080806f
+R13 10 11 2.224404
+C16 12 gnd 2.080806f
+R14 11 12 2.224404
+R15 12 g1624_3 2.224404
+.ends
+
+.subckt netg106 g106_0 g106_1 gnd
+C1  g106_0 gnd 2.080806f
+C2  g106_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g106_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+R11 10 g106_1 2.224404
+.ends
+
+.subckt netg1913 g1913_1 g1913_0 gnd
+C1  g1913_1 gnd 2.080806f
+C2  g1913_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1913_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+R11 10 g1913_1 2.224404
+.ends
+
+.subckt netg2029 g2029_3 g2029_2 g2029_1 g2029_0 gnd
+C1  g2029_3 gnd 2.080806f
+C2  g2029_2 gnd 2.080806f
+C3  g2029_1 gnd 2.080806f
+C4  g2029_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g2029_0 2.224404
+R2 g2029_2 1 2.224404
+C6 2 gnd 2.080806f
+R3 g2029_0 2 2.224404
+C7 3 gnd 2.080806f
+R4 2 3 2.224404
+C8 4 gnd 2.080806f
+R5 3 4 2.224404
+C9 5 gnd 2.080806f
+R6 4 5 2.224404
+C10 6 gnd 2.080806f
+R7 5 6 2.224404
+R8 6 g2029_1 2.224404
+C11 7 gnd 2.080806f
+R9 7 g2029_1 2.224404
+C12 8 gnd 2.080806f
+R10 7 8 2.224404
+C13 9 gnd 2.080806f
+R11 8 9 2.224404
+R12 9 g2029_3 2.224404
+.ends
+
+.subckt netg2322 g2322_2 g2322_0 g2322_1 g2322_3 gnd
+C1  g2322_2 gnd 2.080806f
+C2  g2322_0 gnd 2.080806f
+C3  g2322_1 gnd 2.080806f
+C4  g2322_3 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g2322_0 1 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+C7 3 gnd 2.080806f
+R3 2 3 2.224404
+C8 4 gnd 2.080806f
+R4 3 4 2.224404
+C9 5 gnd 2.080806f
+R5 4 5 2.224404
+C10 6 gnd 2.080806f
+R6 5 6 2.224404
+R7 6 g2322_3 2.224404
+R8 g2322_3 g2322_1 2.224404
+C11 7 gnd 2.080806f
+R9 g2322_1 7 2.224404
+C12 8 gnd 2.080806f
+R10 7 8 2.224404
+R11 8 g2322_2 2.224404
+.ends
+
+.subckt netg4508 g4508_8 g4508_0 g4508_9 g4508_5 g4508_10 g4508_7 g4508_6 g4508_3 g4508_2 g4508_1 g4508_4 gnd
+C1  g4508_8 gnd 2.080806f
+C2  g4508_0 gnd 2.080806f
+C3  g4508_9 gnd 2.080806f
+C4  g4508_5 gnd 2.080806f
+C5  g4508_10 gnd 2.080806f
+C6  g4508_7 gnd 2.080806f
+C7  g4508_6 gnd 2.080806f
+C8  g4508_3 gnd 2.080806f
+C9  g4508_2 gnd 2.080806f
+C10  g4508_1 gnd 2.080806f
+C11  g4508_4 gnd 2.080806f
+C12 1 gnd 2.080806f
+R1 1 g4508_0 2.224404
+R2 1 g4508_7 2.224404
+C13 2 gnd 2.080806f
+R3 g4508_0 2 2.224404
+R4 g4508_8 2 2.224404
+R5 g4508_10 1 2.224404
+C14 3 gnd 2.080806f
+R6 g4508_7 3 2.224404
+R7 3 g4508_2 2.224404
+C15 4 gnd 2.080806f
+R8 g4508_0 4 2.224404
+R9 4 g4508_9 2.224404
+R10 g4508_9 g4508_5 2.224404
+C16 5 gnd 2.080806f
+R11 5 g4508_0 2.224404
+C17 6 gnd 2.080806f
+R12 6 5 2.224404
+R13 g4508_6 6 2.224404
+C18 7 gnd 2.080806f
+R14 7 g4508_6 2.224404
+R15 g4508_1 7 2.224404
+R16 g4508_3 7 2.224404
+C19 8 gnd 2.080806f
+R17 8 g4508_6 2.224404
+R18 g4508_4 8 2.224404
+.ends
+
+.subckt netg4669 g4669_0 g4669_2 g4669_5 g4669_3 g4669_4 g4669_1 g4669_6 gnd
+C1  g4669_0 gnd 2.080806f
+C2  g4669_2 gnd 2.080806f
+C3  g4669_5 gnd 2.080806f
+C4  g4669_3 gnd 2.080806f
+C5  g4669_4 gnd 2.080806f
+C6  g4669_1 gnd 2.080806f
+C7  g4669_6 gnd 2.080806f
+R1 g4669_6 g4669_0 2.224404
+C8 1 gnd 2.080806f
+R2 1 g4669_6 2.224404
+R3 g4669_3 1 2.224404
+R4 g4669_4 1 2.224404
+C9 2 gnd 2.080806f
+R5 g4669_3 2 2.224404
+R6 g4669_5 2 2.224404
+C10 3 gnd 2.080806f
+R7 3 g4669_4 2.224404
+C11 4 gnd 2.080806f
+R8 4 3 2.224404
+C12 5 gnd 2.080806f
+R9 4 5 2.224404
+C13 6 gnd 2.080806f
+R10 5 6 2.224404
+R11 6 g4669_1 2.224404
+C14 7 gnd 2.080806f
+R12 g4669_1 7 2.224404
+C15 8 gnd 2.080806f
+R13 7 8 2.224404
+R14 8 g4669_2 2.224404
+.ends
+
+.subckt netg6046 g6046_1 g6046_0 gnd
+C1  g6046_1 gnd 2.080806f
+C2  g6046_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6046_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+R11 g6046_1 10 2.224404
+.ends
+
+.subckt netg3928 g3928_4 g3928_3 g3928_7 g3928_6 g3928_0 g3928_1 g3928_2 g3928_5 gnd
+C1  g3928_4 gnd 2.080806f
+C2  g3928_3 gnd 2.080806f
+C3  g3928_7 gnd 2.080806f
+C4  g3928_6 gnd 2.080806f
+C5  g3928_0 gnd 2.080806f
+C6  g3928_1 gnd 2.080806f
+C7  g3928_2 gnd 2.080806f
+C8  g3928_5 gnd 2.080806f
+R1 g3928_0 g3928_1 2.224404
+C9 1 gnd 2.080806f
+R2 g3928_0 1 2.224404
+R3 g3928_3 1 2.224404
+C10 2 gnd 2.080806f
+R4 g3928_1 2 2.224404
+R5 2 g3928_6 2.224404
+C11 3 gnd 2.080806f
+R6 3 g3928_3 2.224404
+C12 4 gnd 2.080806f
+R7 4 3 2.224404
+C13 5 gnd 2.080806f
+R8 5 4 2.224404
+R9 g3928_5 5 2.224404
+R10 g3928_2 5 2.224404
+C14 6 gnd 2.080806f
+R11 1 6 2.224404
+C15 7 gnd 2.080806f
+R12 6 7 2.224404
+R13 7 g3928_4 2.224404
+C16 8 gnd 2.080806f
+R14 8 g3928_4 2.224404
+C17 9 gnd 2.080806f
+R15 9 8 2.224404
+R16 g3928_7 9 2.224404
+.ends
+
+.subckt netg3020 g3020_3 g3020_1 g3020_0 g3020_2 gnd
+C1  g3020_3 gnd 2.080806f
+C2  g3020_1 gnd 2.080806f
+C3  g3020_0 gnd 2.080806f
+C4  g3020_2 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g3020_0 1 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+C7 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 g3020_1 3 2.224404
+C8 4 gnd 2.080806f
+R5 4 g3020_1 2.224404
+R6 g3020_3 4 2.224404
+C9 5 gnd 2.080806f
+R7 5 g3020_3 2.224404
+C10 6 gnd 2.080806f
+R8 6 5 2.224404
+C11 7 gnd 2.080806f
+R9 7 6 2.224404
+C12 8 gnd 2.080806f
+R10 8 7 2.224404
+C13 9 gnd 2.080806f
+R11 9 8 2.224404
+C14 10 gnd 2.080806f
+R12 10 9 2.224404
+R13 g3020_2 10 2.224404
+.ends
+
+.subckt netg4324 g4324_0 g4324_2 g4324_3 g4324_1 gnd
+C1  g4324_0 gnd 2.080806f
+C2  g4324_2 gnd 2.080806f
+C3  g4324_3 gnd 2.080806f
+C4  g4324_1 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g4324_0 1 2.224404
+R2 1 g4324_1 2.224404
+C6 2 gnd 2.080806f
+R3 2 g4324_0 2.224404
+C7 3 gnd 2.080806f
+R4 3 2 2.224404
+R5 g4324_3 3 2.224404
+C8 4 gnd 2.080806f
+R6 g4324_3 4 2.224404
+C9 5 gnd 2.080806f
+R7 4 5 2.224404
+C10 6 gnd 2.080806f
+R8 5 6 2.224404
+C11 7 gnd 2.080806f
+R9 6 7 2.224404
+C12 8 gnd 2.080806f
+R10 7 8 2.224404
+C13 9 gnd 2.080806f
+R11 9 8 2.224404
+C14 10 gnd 2.080806f
+R12 9 10 2.224404
+R13 g4324_2 10 2.224404
+.ends
+
+.subckt netg6704 g6704_1 g6704_0 gnd
+C1  g6704_1 gnd 2.080806f
+C2  g6704_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6704_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+R11 g6704_1 10 2.224404
+.ends
+
+.subckt netg1117 g1117_0 g1117_1 gnd
+C1  g1117_0 gnd 2.080806f
+C2  g1117_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1117_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+R11 10 g1117_1 2.224404
+.ends
+
+.subckt netg5381 g5381_0 g5381_2 g5381_3 g5381_1 gnd
+C1  g5381_0 gnd 2.080806f
+C2  g5381_2 gnd 2.080806f
+C3  g5381_3 gnd 2.080806f
+C4  g5381_1 gnd 2.080806f
+R1 g5381_0 g5381_3 2.224404
+C5 1 gnd 2.080806f
+R2 1 g5381_3 2.224404
+C6 2 gnd 2.080806f
+R3 2 1 2.224404
+C7 3 gnd 2.080806f
+R4 3 2 2.224404
+C8 4 gnd 2.080806f
+R5 3 4 2.224404
+C9 5 gnd 2.080806f
+R6 4 5 2.224404
+R7 5 g5381_1 2.224404
+C10 6 gnd 2.080806f
+R8 6 5 2.224404
+C11 7 gnd 2.080806f
+R9 7 6 2.224404
+C12 8 gnd 2.080806f
+R10 8 7 2.224404
+R11 g5381_2 8 2.224404
+.ends
+
+.subckt netg1138 g1138_2 g1138_1 g1138_5 g1138_3 g1138_4 g1138_0 gnd
+C1  g1138_2 gnd 2.080806f
+C2  g1138_1 gnd 2.080806f
+C3  g1138_5 gnd 2.080806f
+C4  g1138_3 gnd 2.080806f
+C5  g1138_4 gnd 2.080806f
+C6  g1138_0 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g1138_0 2.224404
+R2 g1138_3 1 2.224404
+C8 2 gnd 2.080806f
+R3 1 2 2.224404
+C9 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g1138_4 2.224404
+C10 4 gnd 2.080806f
+R6 4 g1138_4 2.224404
+C11 5 gnd 2.080806f
+R7 5 4 2.224404
+C12 6 gnd 2.080806f
+R8 6 5 2.224404
+R9 g1138_5 6 2.224404
+C13 7 gnd 2.080806f
+R10 g1138_5 7 2.224404
+R11 g1138_1 7 2.224404
+C14 8 gnd 2.080806f
+R12 8 g1138_3 2.224404
+C15 9 gnd 2.080806f
+R13 9 8 2.224404
+C16 10 gnd 2.080806f
+R14 10 9 2.224404
+C17 11 gnd 2.080806f
+R15 11 10 2.224404
+R16 g1138_2 11 2.224404
+.ends
+
+.subckt netg6711 g6711_0 g6711_1 gnd
+C1  g6711_0 gnd 2.080806f
+C2  g6711_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6711_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+R11 g6711_1 10 2.224404
+.ends
+
+.subckt netg6240 g6240_1 g6240_0 g6240_2 gnd
+C1  g6240_1 gnd 2.080806f
+C2  g6240_0 gnd 2.080806f
+C3  g6240_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g6240_0 1 2.224404
+R2 g6240_2 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g6240_0 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+R12 g6240_1 10 2.224404
+.ends
+
+.subckt netg2406 g2406_1 g2406_0 g2406_2 gnd
+C1  g2406_1 gnd 2.080806f
+C2  g2406_0 gnd 2.080806f
+C3  g2406_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g2406_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g2406_2 2.224404
+C6 3 gnd 2.080806f
+R4 3 g2406_2 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+C8 5 gnd 2.080806f
+R6 4 5 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+C10 7 gnd 2.080806f
+R8 6 7 2.224404
+C11 8 gnd 2.080806f
+R9 7 8 2.224404
+C12 9 gnd 2.080806f
+R10 8 9 2.224404
+C13 10 gnd 2.080806f
+R11 9 10 2.224404
+C14 11 gnd 2.080806f
+R12 10 11 2.224404
+R13 11 g2406_1 2.224404
+.ends
+
+.subckt netg3358 g3358_2 g3358_1 g3358_0 gnd
+C1  g3358_2 gnd 2.080806f
+C2  g3358_1 gnd 2.080806f
+C3  g3358_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g3358_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g3358_1 3 2.224404
+C7 4 gnd 2.080806f
+R5 4 g3358_1 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+R11 g3358_2 9 2.224404
+.ends
+
+.subckt netg5253 g5253_0 g5253_3 g5253_4 g5253_2 g5253_1 gnd
+C1  g5253_0 gnd 2.080806f
+C2  g5253_3 gnd 2.080806f
+C3  g5253_4 gnd 2.080806f
+C4  g5253_2 gnd 2.080806f
+C5  g5253_1 gnd 2.080806f
+C6 1 gnd 2.080806f
+R1 1 g5253_0 2.224404
+R2 g5253_4 1 2.224404
+R3 g5253_4 g5253_1 2.224404
+R4 g5253_3 g5253_4 2.224404
+C7 2 gnd 2.080806f
+R5 2 g5253_3 2.224404
+C8 3 gnd 2.080806f
+R6 3 2 2.224404
+C9 4 gnd 2.080806f
+R7 4 3 2.224404
+C10 5 gnd 2.080806f
+R8 5 4 2.224404
+C11 6 gnd 2.080806f
+R9 6 5 2.224404
+C12 7 gnd 2.080806f
+R10 7 6 2.224404
+R11 g5253_2 7 2.224404
+.ends
+
+.subckt netg2008 g2008_2 g2008_3 g2008_1 g2008_0 g2008_4 gnd
+C1  g2008_2 gnd 2.080806f
+C2  g2008_3 gnd 2.080806f
+C3  g2008_1 gnd 2.080806f
+C4  g2008_0 gnd 2.080806f
+C5  g2008_4 gnd 2.080806f
+R1 g2008_0 g2008_3 2.224404
+C6 1 gnd 2.080806f
+R2 1 g2008_0 2.224404
+C7 2 gnd 2.080806f
+R3 2 1 2.224404
+R4 g2008_2 2 2.224404
+C8 3 gnd 2.080806f
+R5 g2008_2 3 2.224404
+C9 4 gnd 2.080806f
+R6 3 4 2.224404
+R7 g2008_4 4 2.224404
+C10 5 gnd 2.080806f
+R8 g2008_3 5 2.224404
+C11 6 gnd 2.080806f
+R9 5 6 2.224404
+C12 7 gnd 2.080806f
+R10 6 7 2.224404
+R11 7 g2008_1 2.224404
+.ends
+
+.subckt netg1820 g1820_0 g1820_3 g1820_1 g1820_2 gnd
+C1  g1820_0 gnd 2.080806f
+C2  g1820_3 gnd 2.080806f
+C3  g1820_1 gnd 2.080806f
+C4  g1820_2 gnd 2.080806f
+R1 g1820_0 g1820_2 2.224404
+C5 1 gnd 2.080806f
+R2 g1820_0 1 2.224404
+C6 2 gnd 2.080806f
+R3 1 2 2.224404
+C7 3 gnd 2.080806f
+R4 2 3 2.224404
+C8 4 gnd 2.080806f
+R5 3 4 2.224404
+C9 5 gnd 2.080806f
+R6 4 5 2.224404
+C10 6 gnd 2.080806f
+R7 5 6 2.224404
+R8 6 g1820_1 2.224404
+C11 7 gnd 2.080806f
+R9 g1820_1 7 2.224404
+C12 8 gnd 2.080806f
+R10 7 8 2.224404
+C13 9 gnd 2.080806f
+R11 8 9 2.224404
+R12 9 g1820_3 2.224404
+.ends
+
+.subckt netg716 g716_4 g716_1 g716_0 g716_2 g716_3 gnd
+C1  g716_4 gnd 2.080806f
+C2  g716_1 gnd 2.080806f
+C3  g716_0 gnd 2.080806f
+C4  g716_2 gnd 2.080806f
+C5  g716_3 gnd 2.080806f
+R1 g716_3 g716_0 2.224404
+R2 g716_0 g716_4 2.224404
+C6 1 gnd 2.080806f
+R3 g716_4 1 2.224404
+C7 2 gnd 2.080806f
+R4 1 2 2.224404
+C8 3 gnd 2.080806f
+R5 2 3 2.224404
+R6 3 g716_1 2.224404
+C9 4 gnd 2.080806f
+R7 4 g716_1 2.224404
+C10 5 gnd 2.080806f
+R8 5 4 2.224404
+C11 6 gnd 2.080806f
+R9 6 5 2.224404
+C12 7 gnd 2.080806f
+R10 7 6 2.224404
+C13 8 gnd 2.080806f
+R11 8 7 2.224404
+R12 8 g716_2 2.224404
+.ends
+
+.subckt netg5955 g5955_0 g5955_1 gnd
+C1  g5955_0 gnd 2.080806f
+C2  g5955_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5955_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+R12 11 g5955_1 2.224404
+.ends
+
+.subckt netg4443 g4443_0 g4443_1 g4443_2 gnd
+C1  g4443_0 gnd 2.080806f
+C2  g4443_1 gnd 2.080806f
+C3  g4443_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g4443_0 1 2.224404
+R2 1 g4443_1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g4443_0 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 9 10 2.224404
+R12 10 g4443_2 2.224404
+.ends
+
+.subckt netg1396 g1396_1 g1396_0 gnd
+C1  g1396_1 gnd 2.080806f
+C2  g1396_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1396_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+R12 g1396_1 11 2.224404
+.ends
+
+.subckt netg6340 g6340_3 g6340_0 g6340_2 g6340_1 gnd
+C1  g6340_3 gnd 2.080806f
+C2  g6340_0 gnd 2.080806f
+C3  g6340_2 gnd 2.080806f
+C4  g6340_1 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g6340_0 1 2.224404
+R2 1 g6340_3 2.224404
+C6 2 gnd 2.080806f
+R3 g6340_3 2 2.224404
+R4 2 g6340_2 2.224404
+C7 3 gnd 2.080806f
+R5 g6340_2 3 2.224404
+C8 4 gnd 2.080806f
+R6 3 4 2.224404
+C9 5 gnd 2.080806f
+R7 4 5 2.224404
+C10 6 gnd 2.080806f
+R8 5 6 2.224404
+C11 7 gnd 2.080806f
+R9 6 7 2.224404
+C12 8 gnd 2.080806f
+R10 7 8 2.224404
+C13 9 gnd 2.080806f
+R11 8 9 2.224404
+R12 9 g6340_1 2.224404
+.ends
+
+.subckt netg93 g93_0 g93_1 gnd
+C1  g93_0 gnd 2.080806f
+C2  g93_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g93_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+R12 g93_1 11 2.224404
+.ends
+
+.subckt netg4380 g4380_2 g4380_1 g4380_0 gnd
+C1  g4380_2 gnd 2.080806f
+C2  g4380_1 gnd 2.080806f
+C3  g4380_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g4380_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+C8 5 gnd 2.080806f
+R5 4 5 2.224404
+C9 6 gnd 2.080806f
+R6 5 6 2.224404
+R7 6 g4380_2 2.224404
+C10 7 gnd 2.080806f
+R8 g4380_2 7 2.224404
+C11 8 gnd 2.080806f
+R9 7 8 2.224404
+C12 9 gnd 2.080806f
+R10 8 9 2.224404
+C13 10 gnd 2.080806f
+R11 9 10 2.224404
+R12 10 g4380_1 2.224404
+.ends
+
+.subckt netg5166 g5166_0 g5166_1 gnd
+C1  g5166_0 gnd 2.080806f
+C2  g5166_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5166_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+R12 g5166_1 11 2.224404
+.ends
+
+.subckt netg1675 g1675_2 g1675_3 g1675_0 g1675_1 gnd
+C1  g1675_2 gnd 2.080806f
+C2  g1675_3 gnd 2.080806f
+C3  g1675_0 gnd 2.080806f
+C4  g1675_1 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g1675_0 1 2.224404
+R2 1 g1675_1 2.224404
+C6 2 gnd 2.080806f
+R3 g1675_1 2 2.224404
+C7 3 gnd 2.080806f
+R4 2 3 2.224404
+C8 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 4 g1675_3 2.224404
+C9 5 gnd 2.080806f
+R7 g1675_3 5 2.224404
+C10 6 gnd 2.080806f
+R8 5 6 2.224404
+C11 7 gnd 2.080806f
+R9 6 7 2.224404
+C12 8 gnd 2.080806f
+R10 7 8 2.224404
+C13 9 gnd 2.080806f
+R11 8 9 2.224404
+R12 9 g1675_2 2.224404
+.ends
+
+.subckt netg1895 g1895_0 g1895_1 gnd
+C1  g1895_0 gnd 2.080806f
+C2  g1895_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1895_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+R12 g1895_1 11 2.224404
+.ends
+
+.subckt netg84 g84_1 g84_0 gnd
+C1  g84_1 gnd 2.080806f
+C2  g84_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g84_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+R12 g84_1 11 2.224404
+.ends
+
+.subckt netg91 g91_1 g91_0 gnd
+C1  g91_1 gnd 2.080806f
+C2  g91_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g91_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+R12 11 g91_1 2.224404
+.ends
+
+.subckt netg1409 g1409_0 g1409_1 gnd
+C1  g1409_0 gnd 2.080806f
+C2  g1409_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1409_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+R12 11 g1409_1 2.224404
+.ends
+
+.subckt netg2963 g2963_2 g2963_0 g2963_1 g2963_4 g2963_5 gnd
+C1  g2963_2 gnd 2.080806f
+C2  g2963_0 gnd 2.080806f
+C3  g2963_1 gnd 2.080806f
+C4  g2963_4 gnd 2.080806f
+C5  g2963_5 gnd 2.080806f
+C6 1 gnd 2.080806f
+R1 1 g2963_0 2.224404
+R2 g2963_4 1 2.224404
+C7 2 gnd 2.080806f
+R3 2 g2963_0 2.224404
+C8 3 gnd 2.080806f
+R4 3 2 2.224404
+R5 g2963_2 3 2.224404
+C9 4 gnd 2.080806f
+R6 4 g2963_2 2.224404
+C10 5 gnd 2.080806f
+R7 5 4 2.224404
+C11 6 gnd 2.080806f
+R8 5 6 2.224404
+R9 g2963_5 6 2.224404
+C12 7 gnd 2.080806f
+R10 7 g2963_5 2.224404
+C13 8 gnd 2.080806f
+R11 8 7 2.224404
+C14 9 gnd 2.080806f
+R12 9 8 2.224404
+C15 10 gnd 2.080806f
+R13 10 9 2.224404
+R14 g2963_1 10 2.224404
+.ends
+
+.subckt netg5848 g5848_1 g5848_3 g5848_2 g5848_0 gnd
+C1  g5848_1 gnd 2.080806f
+C2  g5848_3 gnd 2.080806f
+C3  g5848_2 gnd 2.080806f
+C4  g5848_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g5848_0 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g5848_2 2 2.224404
+C7 3 gnd 2.080806f
+R4 3 2 2.224404
+C8 4 gnd 2.080806f
+R5 4 3 2.224404
+R6 g5848_1 4 2.224404
+C9 5 gnd 2.080806f
+R7 5 g5848_1 2.224404
+C10 6 gnd 2.080806f
+R8 6 5 2.224404
+C11 7 gnd 2.080806f
+R9 7 6 2.224404
+C12 8 gnd 2.080806f
+R10 8 7 2.224404
+C13 9 gnd 2.080806f
+R11 9 8 2.224404
+C14 10 gnd 2.080806f
+R12 10 9 2.224404
+R13 g5848_3 10 2.224404
+.ends
+
+.subckt netg5208 g5208_2 g5208_1 g5208_0 gnd
+C1  g5208_2 gnd 2.080806f
+C2  g5208_1 gnd 2.080806f
+C3  g5208_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5208_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g5208_1 2 2.224404
+C6 3 gnd 2.080806f
+R4 3 g5208_1 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 10 11 2.224404
+R13 g5208_2 11 2.224404
+.ends
+
+.subckt netg7408 g7408_0 g7408_1 gnd
+C1  g7408_0 gnd 2.080806f
+C2  g7408_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7408_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+R12 11 g7408_1 2.224404
+.ends
+
+.subckt netg2798 g2798_0 g2798_1 gnd
+C1  g2798_0 gnd 2.080806f
+C2  g2798_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2798_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+R16 g2798_1 15 2.224404
+.ends
+
+.subckt netg2969 g2969_4 g2969_1 g2969_2 g2969_6 g2969_3 g2969_5 gnd
+C1  g2969_4 gnd 2.080806f
+C2  g2969_1 gnd 2.080806f
+C3  g2969_2 gnd 2.080806f
+C4  g2969_6 gnd 2.080806f
+C5  g2969_3 gnd 2.080806f
+C6  g2969_5 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g2969_2 2.224404
+C8 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g2969_3 2 2.224404
+C9 3 gnd 2.080806f
+R4 3 g2969_3 2.224404
+R5 g2969_5 3 2.224404
+C10 4 gnd 2.080806f
+R6 1 4 2.224404
+R7 4 g2969_6 2.224404
+C11 5 gnd 2.080806f
+R8 5 g2969_5 2.224404
+C12 6 gnd 2.080806f
+R9 6 5 2.224404
+C13 7 gnd 2.080806f
+R10 6 7 2.224404
+R11 g2969_4 7 2.224404
+C14 8 gnd 2.080806f
+R12 g2969_4 8 2.224404
+R13 g2969_1 8 2.224404
+.ends
+
+.subckt netg4485 g4485_2 g4485_5 g4485_0 g4485_4 g4485_1 g4485_3 gnd
+C1  g4485_2 gnd 2.080806f
+C2  g4485_5 gnd 2.080806f
+C3  g4485_0 gnd 2.080806f
+C4  g4485_4 gnd 2.080806f
+C5  g4485_1 gnd 2.080806f
+C6  g4485_3 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g4485_0 2.224404
+R2 g4485_4 1 2.224404
+C8 2 gnd 2.080806f
+R3 g4485_0 2 2.224404
+C9 3 gnd 2.080806f
+R4 2 3 2.224404
+C10 4 gnd 2.080806f
+R5 3 4 2.224404
+C11 5 gnd 2.080806f
+R6 4 5 2.224404
+R7 5 g4485_2 2.224404
+R8 g4485_2 g4485_3 2.224404
+C12 6 gnd 2.080806f
+R9 g4485_3 6 2.224404
+C13 7 gnd 2.080806f
+R10 6 7 2.224404
+C14 8 gnd 2.080806f
+R11 7 8 2.224404
+R12 8 g4485_5 2.224404
+C15 9 gnd 2.080806f
+R13 9 8 2.224404
+C16 10 gnd 2.080806f
+R14 10 9 2.224404
+R15 g4485_1 10 2.224404
+.ends
+
+.subckt netg5809 g5809_3 g5809_1 g5809_0 g5809_2 gnd
+C1  g5809_3 gnd 2.080806f
+C2  g5809_1 gnd 2.080806f
+C3  g5809_0 gnd 2.080806f
+C4  g5809_2 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g5809_0 1 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+C7 3 gnd 2.080806f
+R3 2 3 2.224404
+C8 4 gnd 2.080806f
+R4 3 4 2.224404
+C9 5 gnd 2.080806f
+R5 4 5 2.224404
+C10 6 gnd 2.080806f
+R6 5 6 2.224404
+R7 6 g5809_2 2.224404
+C11 7 gnd 2.080806f
+R8 g5809_2 7 2.224404
+C12 8 gnd 2.080806f
+R9 7 8 2.224404
+C13 9 gnd 2.080806f
+R10 8 9 2.224404
+R11 9 g5809_1 2.224404
+R12 g5809_1 g5809_3 2.224404
+.ends
+
+.subckt netg1919 g1919_1 g1919_0 gnd
+C1  g1919_1 gnd 2.080806f
+C2  g1919_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1919_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+R12 11 g1919_1 2.224404
+.ends
+
+.subckt netg5471 g5471_1 g5471_2 g5471_0 gnd
+C1  g5471_1 gnd 2.080806f
+C2  g5471_2 gnd 2.080806f
+C3  g5471_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5471_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g5471_2 2.224404
+C6 3 gnd 2.080806f
+R4 g5471_2 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+C8 5 gnd 2.080806f
+R6 4 5 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 7 8 2.224404
+C12 9 gnd 2.080806f
+R10 8 9 2.224404
+C13 10 gnd 2.080806f
+R11 9 10 2.224404
+R12 10 g5471_1 2.224404
+.ends
+
+.subckt netg2159 g2159_3 g2159_0 g2159_1 g2159_2 gnd
+C1  g2159_3 gnd 2.080806f
+C2  g2159_0 gnd 2.080806f
+C3  g2159_1 gnd 2.080806f
+C4  g2159_2 gnd 2.080806f
+R1 g2159_0 g2159_3 2.224404
+C5 1 gnd 2.080806f
+R2 g2159_3 1 2.224404
+C6 2 gnd 2.080806f
+R3 1 2 2.224404
+C7 3 gnd 2.080806f
+R4 2 3 2.224404
+C8 4 gnd 2.080806f
+R5 3 4 2.224404
+C9 5 gnd 2.080806f
+R6 4 5 2.224404
+C10 6 gnd 2.080806f
+R7 5 6 2.224404
+C11 7 gnd 2.080806f
+R8 6 7 2.224404
+R9 7 g2159_1 2.224404
+C12 8 gnd 2.080806f
+R10 8 g2159_1 2.224404
+C13 9 gnd 2.080806f
+R11 9 8 2.224404
+R12 9 g2159_2 2.224404
+.ends
+
+.subckt netg828 g828_6 g828_4 g828_3 g828_0 g828_2 g828_5 g828_1 gnd
+C1  g828_6 gnd 2.080806f
+C2  g828_4 gnd 2.080806f
+C3  g828_3 gnd 2.080806f
+C4  g828_0 gnd 2.080806f
+C5  g828_2 gnd 2.080806f
+C6  g828_5 gnd 2.080806f
+C7  g828_1 gnd 2.080806f
+C8 1 gnd 2.080806f
+R1 1 g828_0 2.224404
+R2 g828_3 1 2.224404
+R3 g828_2 g828_3 2.224404
+C9 2 gnd 2.080806f
+R4 2 g828_3 2.224404
+C10 3 gnd 2.080806f
+R5 3 2 2.224404
+R6 g828_6 3 2.224404
+R7 g828_4 g828_6 2.224404
+C11 4 gnd 2.080806f
+R8 4 g828_4 2.224404
+C12 5 gnd 2.080806f
+R9 5 4 2.224404
+C13 6 gnd 2.080806f
+R10 6 5 2.224404
+C14 7 gnd 2.080806f
+R11 7 6 2.224404
+R12 g828_1 7 2.224404
+C15 8 gnd 2.080806f
+R13 8 g828_2 2.224404
+C16 9 gnd 2.080806f
+R14 9 8 2.224404
+C17 10 gnd 2.080806f
+R15 10 9 2.224404
+C18 11 gnd 2.080806f
+R16 11 10 2.224404
+C19 12 gnd 2.080806f
+R17 11 12 2.224404
+R18 g828_5 12 2.224404
+.ends
+
+.subckt netg6565 g6565_0 g6565_1 g6565_2 gnd
+C1  g6565_0 gnd 2.080806f
+C2  g6565_1 gnd 2.080806f
+C3  g6565_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g6565_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g6565_1 2.224404
+C7 4 gnd 2.080806f
+R5 g6565_0 4 2.224404
+C8 5 gnd 2.080806f
+R6 4 5 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+C10 7 gnd 2.080806f
+R8 6 7 2.224404
+C11 8 gnd 2.080806f
+R9 7 8 2.224404
+C12 9 gnd 2.080806f
+R10 8 9 2.224404
+C13 10 gnd 2.080806f
+R11 9 10 2.224404
+C14 11 gnd 2.080806f
+R12 10 11 2.224404
+R13 11 g6565_2 2.224404
+.ends
+
+.subckt netg1770 g1770_0 g1770_2 g1770_1 g1770_3 gnd
+C1  g1770_0 gnd 2.080806f
+C2  g1770_2 gnd 2.080806f
+C3  g1770_1 gnd 2.080806f
+C4  g1770_3 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g1770_0 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+C7 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g1770_3 2.224404
+C8 4 gnd 2.080806f
+R5 4 3 2.224404
+R6 g1770_1 4 2.224404
+C9 5 gnd 2.080806f
+R7 5 g1770_1 2.224404
+C10 6 gnd 2.080806f
+R8 6 5 2.224404
+C11 7 gnd 2.080806f
+R9 6 7 2.224404
+C12 8 gnd 2.080806f
+R10 8 7 2.224404
+C13 9 gnd 2.080806f
+R11 8 9 2.224404
+C14 10 gnd 2.080806f
+R12 9 10 2.224404
+R13 10 g1770_2 2.224404
+.ends
+
+.subckt netg1578 g1578_1 g1578_0 gnd
+C1  g1578_1 gnd 2.080806f
+C2  g1578_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1578_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+R12 11 g1578_1 2.224404
+.ends
+
+.subckt netg114 g114_0 g114_1 gnd
+C1  g114_0 gnd 2.080806f
+C2  g114_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g114_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+R12 g114_1 11 2.224404
+.ends
+
+.subckt netg1411 g1411_6 g1411_1 g1411_5 g1411_8 g1411_4 g1411_0 g1411_9 g1411_2 g1411_7 g1411_3 gnd
+C1  g1411_6 gnd 2.080806f
+C2  g1411_1 gnd 2.080806f
+C3  g1411_5 gnd 2.080806f
+C4  g1411_8 gnd 2.080806f
+C5  g1411_4 gnd 2.080806f
+C6  g1411_0 gnd 2.080806f
+C7  g1411_9 gnd 2.080806f
+C8  g1411_2 gnd 2.080806f
+C9  g1411_7 gnd 2.080806f
+C10  g1411_3 gnd 2.080806f
+C11 1 gnd 2.080806f
+R1 1 g1411_0 2.224404
+R2 g1411_7 1 2.224404
+R3 g1411_7 g1411_1 2.224404
+R4 g1411_6 g1411_7 2.224404
+C12 2 gnd 2.080806f
+R5 2 g1411_7 2.224404
+R6 g1411_9 2 2.224404
+C13 3 gnd 2.080806f
+R7 3 g1411_9 2.224404
+R8 g1411_5 3 2.224404
+C14 4 gnd 2.080806f
+R9 g1411_1 4 2.224404
+C15 5 gnd 2.080806f
+R10 4 5 2.224404
+R11 5 g1411_2 2.224404
+C16 6 gnd 2.080806f
+R12 g1411_2 6 2.224404
+R13 6 g1411_3 2.224404
+R14 6 g1411_4 2.224404
+C17 7 gnd 2.080806f
+R15 g1411_3 7 2.224404
+R16 g1411_8 7 2.224404
+.ends
+
+.subckt netg5515 g5515_1 g5515_2 g5515_3 g5515_0 gnd
+C1  g5515_1 gnd 2.080806f
+C2  g5515_2 gnd 2.080806f
+C3  g5515_3 gnd 2.080806f
+C4  g5515_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g5515_0 2.224404
+R2 g5515_2 1 2.224404
+C6 2 gnd 2.080806f
+R3 g5515_2 2 2.224404
+C7 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g5515_3 2.224404
+C8 4 gnd 2.080806f
+R6 4 g5515_3 2.224404
+C9 5 gnd 2.080806f
+R7 5 4 2.224404
+C10 6 gnd 2.080806f
+R8 6 5 2.224404
+C11 7 gnd 2.080806f
+R9 7 6 2.224404
+C12 8 gnd 2.080806f
+R10 8 7 2.224404
+C13 9 gnd 2.080806f
+R11 9 8 2.224404
+R12 g5515_1 9 2.224404
+.ends
+
+.subckt netg3883 g3883_0 g3883_6 g3883_2 g3883_1 g3883_5 g3883_3 g3883_4 gnd
+C1  g3883_0 gnd 2.080806f
+C2  g3883_6 gnd 2.080806f
+C3  g3883_2 gnd 2.080806f
+C4  g3883_1 gnd 2.080806f
+C5  g3883_5 gnd 2.080806f
+C6  g3883_3 gnd 2.080806f
+C7  g3883_4 gnd 2.080806f
+C8 1 gnd 2.080806f
+R1 1 g3883_0 2.224404
+R2 g3883_1 1 2.224404
+C9 2 gnd 2.080806f
+R3 g3883_0 2 2.224404
+R4 2 g3883_2 2.224404
+C10 3 gnd 2.080806f
+R5 g3883_1 3 2.224404
+C11 4 gnd 2.080806f
+R6 3 4 2.224404
+C12 5 gnd 2.080806f
+R7 4 5 2.224404
+R8 5 g3883_3 2.224404
+C13 6 gnd 2.080806f
+R9 6 g3883_0 2.224404
+C14 7 gnd 2.080806f
+R10 7 6 2.224404
+C15 8 gnd 2.080806f
+R11 8 7 2.224404
+R12 g3883_4 8 2.224404
+C16 9 gnd 2.080806f
+R13 9 g3883_4 2.224404
+R14 g3883_5 9 2.224404
+C17 10 gnd 2.080806f
+R15 10 g3883_4 2.224404
+R16 g3883_6 10 2.224404
+.ends
+
+.subckt netg112 g112_1 g112_0 gnd
+C1  g112_1 gnd 2.080806f
+C2  g112_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g112_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+R12 11 g112_1 2.224404
+.ends
+
+.subckt netg1899 g1899_1 g1899_0 gnd
+C1  g1899_1 gnd 2.080806f
+C2  g1899_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1899_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+R14 g1899_1 13 2.224404
+.ends
+
+.subckt netg2405 g2405_0 g2405_1 gnd
+C1  g2405_0 gnd 2.080806f
+C2  g2405_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2405_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+R12 11 g2405_1 2.224404
+.ends
+
+.subckt netg4687 g4687_8 g4687_0 g4687_1 g4687_2 g4687_4 g4687_5 g4687_10 g4687_9 g4687_6 g4687_7 g4687_3 gnd
+C1  g4687_8 gnd 2.080806f
+C2  g4687_0 gnd 2.080806f
+C3  g4687_1 gnd 2.080806f
+C4  g4687_2 gnd 2.080806f
+C5  g4687_4 gnd 2.080806f
+C6  g4687_5 gnd 2.080806f
+C7  g4687_10 gnd 2.080806f
+C8  g4687_9 gnd 2.080806f
+C9  g4687_6 gnd 2.080806f
+C10  g4687_7 gnd 2.080806f
+C11  g4687_3 gnd 2.080806f
+R1 g4687_6 g4687_0 2.224404
+R2 g4687_6 g4687_8 2.224404
+R3 g4687_8 g4687_9 2.224404
+R4 g4687_9 g4687_10 2.224404
+C12 1 gnd 2.080806f
+R5 g4687_10 1 2.224404
+R6 1 g4687_4 2.224404
+C13 2 gnd 2.080806f
+R7 2 g4687_4 2.224404
+C14 3 gnd 2.080806f
+R8 3 2 2.224404
+R9 g4687_5 3 2.224404
+C15 4 gnd 2.080806f
+R10 3 4 2.224404
+R11 4 g4687_2 2.224404
+C16 5 gnd 2.080806f
+R12 g4687_2 5 2.224404
+C17 6 gnd 2.080806f
+R13 5 6 2.224404
+R14 6 g4687_1 2.224404
+C18 7 gnd 2.080806f
+R15 7 g4687_1 2.224404
+R16 7 g4687_3 2.224404
+R17 g4687_3 g4687_7 2.224404
+.ends
+
+.subckt netg2859 g2859_0 g2859_4 g2859_1 g2859_6 g2859_2 g2859_5 g2859_3 gnd
+C1  g2859_0 gnd 2.080806f
+C2  g2859_4 gnd 2.080806f
+C3  g2859_1 gnd 2.080806f
+C4  g2859_6 gnd 2.080806f
+C5  g2859_2 gnd 2.080806f
+C6  g2859_5 gnd 2.080806f
+C7  g2859_3 gnd 2.080806f
+C8 1 gnd 2.080806f
+R1 1 g2859_0 2.224404
+C9 2 gnd 2.080806f
+R2 2 1 2.224404
+C10 3 gnd 2.080806f
+R3 3 2 2.224404
+C11 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 g2859_6 4 2.224404
+R6 g2859_2 g2859_6 2.224404
+C12 5 gnd 2.080806f
+R7 5 g2859_2 2.224404
+C13 6 gnd 2.080806f
+R8 6 5 2.224404
+C14 7 gnd 2.080806f
+R9 7 6 2.224404
+R10 g2859_1 7 2.224404
+R11 g2859_3 7 2.224404
+C15 8 gnd 2.080806f
+R12 8 g2859_1 2.224404
+R13 g2859_4 8 2.224404
+C16 9 gnd 2.080806f
+R14 9 5 2.224404
+C17 10 gnd 2.080806f
+R15 10 9 2.224404
+R16 g2859_5 10 2.224404
+.ends
+
+.subckt netg740 g740_2 g740_5 g740_6 g740_3 g740_0 g740_1 g740_4 gnd
+C1  g740_2 gnd 2.080806f
+C2  g740_5 gnd 2.080806f
+C3  g740_6 gnd 2.080806f
+C4  g740_3 gnd 2.080806f
+C5  g740_0 gnd 2.080806f
+C6  g740_1 gnd 2.080806f
+C7  g740_4 gnd 2.080806f
+R1 g740_5 g740_0 2.224404
+R2 g740_5 g740_4 2.224404
+C8 1 gnd 2.080806f
+R3 1 g740_5 2.224404
+C9 2 gnd 2.080806f
+R4 2 1 2.224404
+C10 3 gnd 2.080806f
+R5 3 2 2.224404
+R6 g740_2 3 2.224404
+C11 4 gnd 2.080806f
+R7 4 g740_2 2.224404
+C12 5 gnd 2.080806f
+R8 5 4 2.224404
+R9 g740_1 5 2.224404
+C13 6 gnd 2.080806f
+R10 g740_4 6 2.224404
+C14 7 gnd 2.080806f
+R11 6 7 2.224404
+C15 8 gnd 2.080806f
+R12 7 8 2.224404
+C16 9 gnd 2.080806f
+R13 8 9 2.224404
+R14 9 g740_6 2.224404
+C17 10 gnd 2.080806f
+R15 10 g740_6 2.224404
+C18 11 gnd 2.080806f
+R16 11 10 2.224404
+C19 12 gnd 2.080806f
+R17 12 11 2.224404
+R18 g740_3 12 2.224404
+.ends
+
+.subckt netg6202 g6202_1 g6202_0 gnd
+C1  g6202_1 gnd 2.080806f
+C2  g6202_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6202_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+R13 g6202_1 12 2.224404
+.ends
+
+.subckt netg2398 g2398_2 g2398_0 g2398_1 gnd
+C1  g2398_2 gnd 2.080806f
+C2  g2398_0 gnd 2.080806f
+C3  g2398_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g2398_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 g2398_2 3 2.224404
+C7 4 gnd 2.080806f
+R5 4 g2398_2 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 11 10 2.224404
+C15 12 gnd 2.080806f
+R13 11 12 2.224404
+C16 13 gnd 2.080806f
+R14 13 12 2.224404
+R15 g2398_1 13 2.224404
+.ends
+
+.subckt netg1092 g1092_2 g1092_1 g1092_0 g1092_3 gnd
+C1  g1092_2 gnd 2.080806f
+C2  g1092_1 gnd 2.080806f
+C3  g1092_0 gnd 2.080806f
+C4  g1092_3 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g1092_0 1 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+C7 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g1092_3 2.224404
+C8 4 gnd 2.080806f
+R5 g1092_0 4 2.224404
+C9 5 gnd 2.080806f
+R6 4 5 2.224404
+C10 6 gnd 2.080806f
+R7 5 6 2.224404
+C11 7 gnd 2.080806f
+R8 6 7 2.224404
+C12 8 gnd 2.080806f
+R9 7 8 2.224404
+C13 9 gnd 2.080806f
+R10 8 9 2.224404
+C14 10 gnd 2.080806f
+R11 9 10 2.224404
+R12 10 g1092_1 2.224404
+C15 11 gnd 2.080806f
+R13 10 11 2.224404
+C16 12 gnd 2.080806f
+R14 11 12 2.224404
+C17 13 gnd 2.080806f
+R15 12 13 2.224404
+C18 14 gnd 2.080806f
+R16 13 14 2.224404
+C19 15 gnd 2.080806f
+R17 14 15 2.224404
+R18 15 g1092_2 2.224404
+.ends
+
+.subckt netg1212 g1212_4 g1212_0 g1212_3 g1212_2 g1212_5 g1212_6 g1212_1 gnd
+C1  g1212_4 gnd 2.080806f
+C2  g1212_0 gnd 2.080806f
+C3  g1212_3 gnd 2.080806f
+C4  g1212_2 gnd 2.080806f
+C5  g1212_5 gnd 2.080806f
+C6  g1212_6 gnd 2.080806f
+C7  g1212_1 gnd 2.080806f
+C8 1 gnd 2.080806f
+R1 1 g1212_0 2.224404
+R2 g1212_2 1 2.224404
+C9 2 gnd 2.080806f
+R3 g1212_0 2 2.224404
+R4 2 g1212_6 2.224404
+C10 3 gnd 2.080806f
+R5 3 g1212_6 2.224404
+R6 g1212_4 3 2.224404
+R7 g1212_5 g1212_4 2.224404
+C11 4 gnd 2.080806f
+R8 g1212_0 4 2.224404
+C12 5 gnd 2.080806f
+R9 4 5 2.224404
+C13 6 gnd 2.080806f
+R10 5 6 2.224404
+R11 6 g1212_3 2.224404
+C14 7 gnd 2.080806f
+R12 g1212_3 7 2.224404
+C15 8 gnd 2.080806f
+R13 7 8 2.224404
+C16 9 gnd 2.080806f
+R14 8 9 2.224404
+C17 10 gnd 2.080806f
+R15 9 10 2.224404
+R16 10 g1212_1 2.224404
+.ends
+
+.subckt netg1918 g1918_1 g1918_0 gnd
+C1  g1918_1 gnd 2.080806f
+C2  g1918_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1918_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+R13 g1918_1 12 2.224404
+.ends
+
+.subckt netg7550 g7550_0 g7550_1 gnd
+C1  g7550_0 gnd 2.080806f
+C2  g7550_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7550_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+R13 g7550_1 12 2.224404
+.ends
+
+.subckt netg6765 g6765_4 g6765_5 g6765_1 g6765_2 g6765_0 g6765_3 gnd
+C1  g6765_4 gnd 2.080806f
+C2  g6765_5 gnd 2.080806f
+C3  g6765_1 gnd 2.080806f
+C4  g6765_2 gnd 2.080806f
+C5  g6765_0 gnd 2.080806f
+C6  g6765_3 gnd 2.080806f
+R1 g6765_0 g6765_5 2.224404
+C7 1 gnd 2.080806f
+R2 1 g6765_0 2.224404
+R3 g6765_2 1 2.224404
+C8 2 gnd 2.080806f
+R4 g6765_5 2 2.224404
+C9 3 gnd 2.080806f
+R5 2 3 2.224404
+R6 3 g6765_3 2.224404
+C10 4 gnd 2.080806f
+R7 4 g6765_3 2.224404
+C11 5 gnd 2.080806f
+R8 4 5 2.224404
+C12 6 gnd 2.080806f
+R9 6 5 2.224404
+C13 7 gnd 2.080806f
+R10 6 7 2.224404
+C14 8 gnd 2.080806f
+R11 7 8 2.224404
+R12 8 g6765_1 2.224404
+C15 9 gnd 2.080806f
+R13 9 g6765_1 2.224404
+C16 10 gnd 2.080806f
+R14 10 9 2.224404
+R15 10 g6765_4 2.224404
+.ends
+
+.subckt netg4539 g4539_2 g4539_9 g4539_5 g4539_8 g4539_6 g4539_1 g4539_4 g4539_10 g4539_3 g4539_7 g4539_0 gnd
+C1  g4539_2 gnd 2.080806f
+C2  g4539_9 gnd 2.080806f
+C3  g4539_5 gnd 2.080806f
+C4  g4539_8 gnd 2.080806f
+C5  g4539_6 gnd 2.080806f
+C6  g4539_1 gnd 2.080806f
+C7  g4539_4 gnd 2.080806f
+C8  g4539_10 gnd 2.080806f
+C9  g4539_3 gnd 2.080806f
+C10  g4539_7 gnd 2.080806f
+C11  g4539_0 gnd 2.080806f
+C12 1 gnd 2.080806f
+R1 1 g4539_0 2.224404
+C13 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g4539_7 2 2.224404
+C14 3 gnd 2.080806f
+R4 1 3 2.224404
+C15 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 4 g4539_6 2.224404
+R7 g4539_6 g4539_4 2.224404
+R8 g4539_1 g4539_4 2.224404
+C16 5 gnd 2.080806f
+R9 g4539_4 5 2.224404
+R10 5 g4539_5 2.224404
+C17 6 gnd 2.080806f
+R11 g4539_5 6 2.224404
+R12 6 g4539_9 2.224404
+R13 g4539_9 g4539_10 2.224404
+R14 g4539_8 g4539_10 2.224404
+C18 7 gnd 2.080806f
+R15 5 7 2.224404
+R16 7 g4539_3 2.224404
+C19 8 gnd 2.080806f
+R17 g4539_1 8 2.224404
+C20 9 gnd 2.080806f
+R18 8 9 2.224404
+R19 g4539_2 9 2.224404
+.ends
+
+.subckt netg1115 g1115_1 g1115_0 gnd
+C1  g1115_1 gnd 2.080806f
+C2  g1115_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1115_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+R15 g1115_1 14 2.224404
+.ends
+
+.subckt netg6002 g6002_3 g6002_2 g6002_1 g6002_0 gnd
+C1  g6002_3 gnd 2.080806f
+C2  g6002_2 gnd 2.080806f
+C3  g6002_1 gnd 2.080806f
+C4  g6002_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g6002_0 1 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+C7 3 gnd 2.080806f
+R3 2 3 2.224404
+C8 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 4 g6002_2 2.224404
+C9 5 gnd 2.080806f
+R6 g6002_2 5 2.224404
+C10 6 gnd 2.080806f
+R7 5 6 2.224404
+C11 7 gnd 2.080806f
+R8 6 7 2.224404
+R9 7 g6002_3 2.224404
+C12 8 gnd 2.080806f
+R10 g6002_3 8 2.224404
+C13 9 gnd 2.080806f
+R11 8 9 2.224404
+C14 10 gnd 2.080806f
+R12 9 10 2.224404
+R13 10 g6002_1 2.224404
+.ends
+
+.subckt netg90 g90_0 g90_1 gnd
+C1  g90_0 gnd 2.080806f
+C2  g90_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g90_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+R13 g90_1 12 2.224404
+.ends
+
+.subckt netg6657 g6657_0 g6657_1 gnd
+C1  g6657_0 gnd 2.080806f
+C2  g6657_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6657_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+R13 12 g6657_1 2.224404
+.ends
+
+.subckt netg4704 g4704_6 g4704_1 g4704_0 g4704_2 g4704_5 g4704_4 g4704_3 gnd
+C1  g4704_6 gnd 2.080806f
+C2  g4704_1 gnd 2.080806f
+C3  g4704_0 gnd 2.080806f
+C4  g4704_2 gnd 2.080806f
+C5  g4704_5 gnd 2.080806f
+C6  g4704_4 gnd 2.080806f
+C7  g4704_3 gnd 2.080806f
+C8 1 gnd 2.080806f
+R1 g4704_0 1 2.224404
+C9 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g4704_1 2.224404
+C10 3 gnd 2.080806f
+R4 3 g4704_0 2.224404
+C11 4 gnd 2.080806f
+R5 4 3 2.224404
+R6 g4704_3 4 2.224404
+C12 5 gnd 2.080806f
+R7 5 1 2.224404
+R8 g4704_5 5 2.224404
+C13 6 gnd 2.080806f
+R9 6 g4704_5 2.224404
+R10 6 g4704_4 2.224404
+C14 7 gnd 2.080806f
+R11 7 g4704_3 2.224404
+C15 8 gnd 2.080806f
+R12 7 8 2.224404
+R13 g4704_2 8 2.224404
+C16 9 gnd 2.080806f
+R14 9 g4704_2 2.224404
+R15 g4704_6 9 2.224404
+.ends
+
+.subckt netg3817 g3817_9 g3817_5 g3817_4 g3817_7 g3817_10 g3817_8 g3817_1 g3817_2 g3817_6 g3817_3 gnd
+C1  g3817_9 gnd 2.080806f
+C2  g3817_5 gnd 2.080806f
+C3  g3817_4 gnd 2.080806f
+C4  g3817_7 gnd 2.080806f
+C5  g3817_10 gnd 2.080806f
+C6  g3817_8 gnd 2.080806f
+C7  g3817_1 gnd 2.080806f
+C8  g3817_2 gnd 2.080806f
+C9  g3817_6 gnd 2.080806f
+C10  g3817_3 gnd 2.080806f
+C11 1 gnd 2.080806f
+R1 1 g3817_1 2.224404
+C12 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g3817_2 2.224404
+R4 g3817_10 g3817_2 2.224404
+C13 3 gnd 2.080806f
+R5 3 g3817_10 2.224404
+C14 4 gnd 2.080806f
+R6 3 4 2.224404
+R7 4 g3817_8 2.224404
+C15 5 gnd 2.080806f
+R8 g3817_8 5 2.224404
+R9 5 g3817_9 2.224404
+C16 6 gnd 2.080806f
+R10 g3817_2 6 2.224404
+C17 7 gnd 2.080806f
+R11 6 7 2.224404
+R12 7 g3817_3 2.224404
+C18 8 gnd 2.080806f
+R13 g3817_3 8 2.224404
+R14 8 g3817_5 2.224404
+R15 8 g3817_7 2.224404
+C19 9 gnd 2.080806f
+R16 9 1 2.224404
+C20 10 gnd 2.080806f
+R17 10 9 2.224404
+C21 11 gnd 2.080806f
+R18 11 10 2.224404
+R19 g3817_6 11 2.224404
+C22 12 gnd 2.080806f
+R20 12 g3817_9 2.224404
+C23 13 gnd 2.080806f
+R21 13 12 2.224404
+C24 14 gnd 2.080806f
+R22 14 13 2.224404
+C25 15 gnd 2.080806f
+R23 15 14 2.224404
+R24 15 g3817_4 2.224404
+.ends
+
+.subckt netg4550 g4550_3 g4550_9 g4550_0 g4550_4 g4550_8 g4550_7 g4550_1 g4550_2 g4550_5 g4550_6 gnd
+C1  g4550_3 gnd 2.080806f
+C2  g4550_9 gnd 2.080806f
+C3  g4550_0 gnd 2.080806f
+C4  g4550_4 gnd 2.080806f
+C5  g4550_8 gnd 2.080806f
+C6  g4550_7 gnd 2.080806f
+C7  g4550_1 gnd 2.080806f
+C8  g4550_2 gnd 2.080806f
+C9  g4550_5 gnd 2.080806f
+C10  g4550_6 gnd 2.080806f
+C11 1 gnd 2.080806f
+R1 1 g4550_0 2.224404
+R2 g4550_3 1 2.224404
+C12 2 gnd 2.080806f
+R3 2 g4550_3 2.224404
+R4 g4550_2 2 2.224404
+C13 3 gnd 2.080806f
+R5 g4550_2 3 2.224404
+R6 3 g4550_8 2.224404
+C14 4 gnd 2.080806f
+R7 1 4 2.224404
+R8 4 g4550_5 2.224404
+C15 5 gnd 2.080806f
+R9 g4550_5 5 2.224404
+R10 5 g4550_1 2.224404
+C16 6 gnd 2.080806f
+R11 g4550_1 6 2.224404
+C17 7 gnd 2.080806f
+R12 6 7 2.224404
+R13 7 g4550_4 2.224404
+C18 8 gnd 2.080806f
+R14 8 6 2.224404
+R15 g4550_9 8 2.224404
+R16 g4550_7 g4550_9 2.224404
+C19 9 gnd 2.080806f
+R17 9 g4550_4 2.224404
+C20 10 gnd 2.080806f
+R18 9 10 2.224404
+R19 10 g4550_6 2.224404
+.ends
+
+.subckt netg3630 g3630_6 g3630_4 g3630_3 g3630_2 g3630_1 g3630_0 g3630_5 gnd
+C1  g3630_6 gnd 2.080806f
+C2  g3630_4 gnd 2.080806f
+C3  g3630_3 gnd 2.080806f
+C4  g3630_2 gnd 2.080806f
+C5  g3630_1 gnd 2.080806f
+C6  g3630_0 gnd 2.080806f
+C7  g3630_5 gnd 2.080806f
+C8 1 gnd 2.080806f
+R1 1 g3630_0 2.224404
+R2 g3630_4 1 2.224404
+R3 g3630_3 g3630_4 2.224404
+C9 2 gnd 2.080806f
+R4 g3630_0 2 2.224404
+C10 3 gnd 2.080806f
+R5 2 3 2.224404
+C11 4 gnd 2.080806f
+R6 3 4 2.224404
+R7 4 g3630_6 2.224404
+C12 5 gnd 2.080806f
+R8 5 g3630_3 2.224404
+C13 6 gnd 2.080806f
+R9 6 5 2.224404
+C14 7 gnd 2.080806f
+R10 7 6 2.224404
+C15 8 gnd 2.080806f
+R11 8 7 2.224404
+C16 9 gnd 2.080806f
+R12 9 8 2.224404
+R13 g3630_2 9 2.224404
+C17 10 gnd 2.080806f
+R14 g3630_2 10 2.224404
+C18 11 gnd 2.080806f
+R15 10 11 2.224404
+R16 11 g3630_1 2.224404
+C19 12 gnd 2.080806f
+R17 g3630_1 12 2.224404
+R18 12 g3630_5 2.224404
+.ends
+
+.subckt netg2432 g2432_0 g2432_1 g2432_2 gnd
+C1  g2432_0 gnd 2.080806f
+C2  g2432_1 gnd 2.080806f
+C3  g2432_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g2432_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 g2432_1 3 2.224404
+C7 4 gnd 2.080806f
+R5 4 g2432_1 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 7 8 2.224404
+C12 9 gnd 2.080806f
+R10 8 9 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 10 11 2.224404
+R13 g2432_2 11 2.224404
+.ends
+
+.subckt netg4407 g4407_1 g4407_2 g4407_0 gnd
+C1  g4407_1 gnd 2.080806f
+C2  g4407_2 gnd 2.080806f
+C3  g4407_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g4407_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+R6 5 g4407_2 2.224404
+C9 6 gnd 2.080806f
+R7 g4407_2 6 2.224404
+C10 7 gnd 2.080806f
+R8 6 7 2.224404
+C11 8 gnd 2.080806f
+R9 7 8 2.224404
+C12 9 gnd 2.080806f
+R10 8 9 2.224404
+C13 10 gnd 2.080806f
+R11 9 10 2.224404
+C14 11 gnd 2.080806f
+R12 10 11 2.224404
+R13 11 g4407_1 2.224404
+.ends
+
+.subckt netg1108 g1108_1 g1108_0 g1108_5 g1108_4 g1108_3 g1108_2 gnd
+C1  g1108_1 gnd 2.080806f
+C2  g1108_0 gnd 2.080806f
+C3  g1108_5 gnd 2.080806f
+C4  g1108_4 gnd 2.080806f
+C5  g1108_3 gnd 2.080806f
+C6  g1108_2 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g1108_0 2.224404
+C8 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g1108_1 2 2.224404
+R4 g1108_3 g1108_1 2.224404
+C9 3 gnd 2.080806f
+R5 3 g1108_3 2.224404
+C10 4 gnd 2.080806f
+R6 4 3 2.224404
+R7 g1108_2 4 2.224404
+C11 5 gnd 2.080806f
+R8 g1108_0 5 2.224404
+C12 6 gnd 2.080806f
+R9 5 6 2.224404
+C13 7 gnd 2.080806f
+R10 6 7 2.224404
+C14 8 gnd 2.080806f
+R11 7 8 2.224404
+C15 9 gnd 2.080806f
+R12 8 9 2.224404
+R13 9 g1108_5 2.224404
+C16 10 gnd 2.080806f
+R14 10 g1108_5 2.224404
+C17 11 gnd 2.080806f
+R15 11 10 2.224404
+C18 12 gnd 2.080806f
+R16 12 11 2.224404
+R17 g1108_4 12 2.224404
+.ends
+
+.subckt netg1285 g1285_1 g1285_0 gnd
+C1  g1285_1 gnd 2.080806f
+C2  g1285_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1285_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+R13 12 g1285_1 2.224404
+.ends
+
+.subckt netg5334 g5334_4 g5334_2 g5334_6 g5334_1 g5334_3 g5334_0 g5334_5 gnd
+C1  g5334_4 gnd 2.080806f
+C2  g5334_2 gnd 2.080806f
+C3  g5334_6 gnd 2.080806f
+C4  g5334_1 gnd 2.080806f
+C5  g5334_3 gnd 2.080806f
+C6  g5334_0 gnd 2.080806f
+C7  g5334_5 gnd 2.080806f
+C8 1 gnd 2.080806f
+R1 g5334_0 1 2.224404
+R2 1 g5334_5 2.224404
+C9 2 gnd 2.080806f
+R3 2 1 2.224404
+C10 3 gnd 2.080806f
+R4 3 2 2.224404
+R5 g5334_6 3 2.224404
+C11 4 gnd 2.080806f
+R6 4 g5334_6 2.224404
+C12 5 gnd 2.080806f
+R7 5 4 2.224404
+C13 6 gnd 2.080806f
+R8 6 5 2.224404
+R9 g5334_4 6 2.224404
+C14 7 gnd 2.080806f
+R10 7 g5334_4 2.224404
+C15 8 gnd 2.080806f
+R11 8 7 2.224404
+R12 g5334_2 8 2.224404
+R13 g5334_3 g5334_2 2.224404
+C16 9 gnd 2.080806f
+R14 g5334_2 9 2.224404
+C17 10 gnd 2.080806f
+R15 9 10 2.224404
+R16 10 g5334_1 2.224404
+.ends
+
+.subckt netg6542 g6542_0 g6542_1 gnd
+C1  g6542_0 gnd 2.080806f
+C2  g6542_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6542_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+R13 12 g6542_1 2.224404
+.ends
+
+.subckt netg3810 g3810_3 g3810_4 g3810_1 g3810_0 g3810_6 g3810_5 g3810_2 gnd
+C1  g3810_3 gnd 2.080806f
+C2  g3810_4 gnd 2.080806f
+C3  g3810_1 gnd 2.080806f
+C4  g3810_0 gnd 2.080806f
+C5  g3810_6 gnd 2.080806f
+C6  g3810_5 gnd 2.080806f
+C7  g3810_2 gnd 2.080806f
+R1 g3810_3 g3810_0 2.224404
+C8 1 gnd 2.080806f
+R2 1 g3810_3 2.224404
+C9 2 gnd 2.080806f
+R3 2 1 2.224404
+C10 3 gnd 2.080806f
+R4 3 2 2.224404
+C11 4 gnd 2.080806f
+R5 4 3 2.224404
+R6 g3810_5 4 2.224404
+R7 g3810_1 g3810_5 2.224404
+C12 5 gnd 2.080806f
+R8 5 g3810_5 2.224404
+C13 6 gnd 2.080806f
+R9 6 5 2.224404
+R10 g3810_2 6 2.224404
+C14 7 gnd 2.080806f
+R11 7 g3810_2 2.224404
+C15 8 gnd 2.080806f
+R12 8 7 2.224404
+R13 g3810_4 8 2.224404
+C16 9 gnd 2.080806f
+R14 6 9 2.224404
+R15 9 g3810_6 2.224404
+.ends
+
+.subckt netg2200 g2200_1 g2200_2 gnd
+C1  g2200_1 gnd 2.080806f
+C2  g2200_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2200_2 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+R13 g2200_1 12 2.224404
+.ends
+
+.subckt netg127 g127_1 g127_0 gnd
+C1  g127_1 gnd 2.080806f
+C2  g127_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g127_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+R14 13 g127_1 2.224404
+.ends
+
+.subckt netg849 g849_6 g849_4 g849_2 g849_3 g849_0 g849_5 g849_1 gnd
+C1  g849_6 gnd 2.080806f
+C2  g849_4 gnd 2.080806f
+C3  g849_2 gnd 2.080806f
+C4  g849_3 gnd 2.080806f
+C5  g849_0 gnd 2.080806f
+C6  g849_5 gnd 2.080806f
+C7  g849_1 gnd 2.080806f
+C8 1 gnd 2.080806f
+R1 g849_0 1 2.224404
+C9 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g849_2 2.224404
+R4 g849_2 g849_4 2.224404
+C10 3 gnd 2.080806f
+R5 g849_2 3 2.224404
+C11 4 gnd 2.080806f
+R6 3 4 2.224404
+C12 5 gnd 2.080806f
+R7 4 5 2.224404
+C13 6 gnd 2.080806f
+R8 5 6 2.224404
+C14 7 gnd 2.080806f
+R9 6 7 2.224404
+R10 7 g849_3 2.224404
+C15 8 gnd 2.080806f
+R11 g849_3 8 2.224404
+C16 9 gnd 2.080806f
+R12 8 9 2.224404
+C17 10 gnd 2.080806f
+R13 9 10 2.224404
+R14 10 g849_1 2.224404
+C18 11 gnd 2.080806f
+R15 11 g849_1 2.224404
+R16 11 g849_5 2.224404
+C19 12 gnd 2.080806f
+R17 12 11 2.224404
+C20 13 gnd 2.080806f
+R18 13 12 2.224404
+R19 g849_6 13 2.224404
+.ends
+
+.subckt netg3644 g3644_4 g3644_8 g3644_5 g3644_1 g3644_7 g3644_9 g3644_2 g3644_3 g3644_0 gnd
+C1  g3644_4 gnd 2.080806f
+C2  g3644_8 gnd 2.080806f
+C3  g3644_5 gnd 2.080806f
+C4  g3644_1 gnd 2.080806f
+C5  g3644_7 gnd 2.080806f
+C6  g3644_9 gnd 2.080806f
+C7  g3644_2 gnd 2.080806f
+C8  g3644_3 gnd 2.080806f
+C9  g3644_0 gnd 2.080806f
+C10 1 gnd 2.080806f
+R1 1 g3644_0 2.224404
+R2 g3644_1 1 2.224404
+C11 2 gnd 2.080806f
+R3 2 g3644_1 2.224404
+C12 3 gnd 2.080806f
+R4 3 2 2.224404
+C13 4 gnd 2.080806f
+R5 4 3 2.224404
+R6 g3644_2 4 2.224404
+R7 g3644_2 g3644_5 2.224404
+C14 5 gnd 2.080806f
+R8 5 g3644_5 2.224404
+R9 g3644_9 5 2.224404
+R10 g3644_8 g3644_9 2.224404
+R11 g3644_3 g3644_8 2.224404
+C15 6 gnd 2.080806f
+R12 g3644_8 6 2.224404
+R13 6 g3644_4 2.224404
+C16 7 gnd 2.080806f
+R14 7 g3644_3 2.224404
+C17 8 gnd 2.080806f
+R15 8 7 2.224404
+C18 9 gnd 2.080806f
+R16 9 8 2.224404
+R17 g3644_7 9 2.224404
+.ends
+
+.subckt netg2092 g2092_0 g2092_1 g2092_3 g2092_2 gnd
+C1  g2092_0 gnd 2.080806f
+C2  g2092_1 gnd 2.080806f
+C3  g2092_3 gnd 2.080806f
+C4  g2092_2 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g2092_0 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g2092_3 2 2.224404
+C7 3 gnd 2.080806f
+R4 3 g2092_3 2.224404
+C8 4 gnd 2.080806f
+R5 4 3 2.224404
+C9 5 gnd 2.080806f
+R6 5 4 2.224404
+C10 6 gnd 2.080806f
+R7 6 5 2.224404
+C11 7 gnd 2.080806f
+R8 7 6 2.224404
+C12 8 gnd 2.080806f
+R9 8 7 2.224404
+C13 9 gnd 2.080806f
+R10 9 8 2.224404
+C14 10 gnd 2.080806f
+R11 10 9 2.224404
+R12 g2092_1 10 2.224404
+C15 11 gnd 2.080806f
+R13 11 g2092_1 2.224404
+R14 g2092_2 11 2.224404
+.ends
+
+.subckt netg4092 g4092_2 g4092_1 g4092_0 gnd
+C1  g4092_2 gnd 2.080806f
+C2  g4092_1 gnd 2.080806f
+C3  g4092_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g4092_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 5 g4092_2 2.224404
+C9 6 gnd 2.080806f
+R7 6 g4092_0 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 11 10 2.224404
+C15 12 gnd 2.080806f
+R13 12 11 2.224404
+R14 g4092_1 12 2.224404
+.ends
+
+.subckt netg1792 g1792_2 g1792_0 g1792_1 gnd
+C1  g1792_2 gnd 2.080806f
+C2  g1792_0 gnd 2.080806f
+C3  g1792_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g1792_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+C8 5 gnd 2.080806f
+R5 4 5 2.224404
+C9 6 gnd 2.080806f
+R6 5 6 2.224404
+C10 7 gnd 2.080806f
+R7 6 7 2.224404
+C11 8 gnd 2.080806f
+R8 7 8 2.224404
+C12 9 gnd 2.080806f
+R9 8 9 2.224404
+C13 10 gnd 2.080806f
+R10 9 10 2.224404
+C14 11 gnd 2.080806f
+R11 10 11 2.224404
+R12 11 g1792_2 2.224404
+C15 12 gnd 2.080806f
+R13 g1792_2 12 2.224404
+R14 12 g1792_1 2.224404
+.ends
+
+.subckt netg2537 g2537_1 g2537_2 g2537_0 gnd
+C1  g2537_1 gnd 2.080806f
+C2  g2537_2 gnd 2.080806f
+C3  g2537_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g2537_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 6 5 2.224404
+C10 7 gnd 2.080806f
+R7 7 6 2.224404
+C11 8 gnd 2.080806f
+R8 8 7 2.224404
+C12 9 gnd 2.080806f
+R9 9 8 2.224404
+C13 10 gnd 2.080806f
+R10 10 9 2.224404
+C14 11 gnd 2.080806f
+R11 11 10 2.224404
+R12 g2537_1 11 2.224404
+C15 12 gnd 2.080806f
+R13 12 g2537_1 2.224404
+R14 g2537_2 12 2.224404
+.ends
+
+.subckt netg2226 g2226_1 g2226_0 gnd
+C1  g2226_1 gnd 2.080806f
+C2  g2226_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2226_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+R14 g2226_1 13 2.224404
+.ends
+
+.subckt netg1803 g1803_1 g1803_3 g1803_0 g1803_2 gnd
+C1  g1803_1 gnd 2.080806f
+C2  g1803_3 gnd 2.080806f
+C3  g1803_0 gnd 2.080806f
+C4  g1803_2 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g1803_0 1 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g1803_3 2.224404
+C7 3 gnd 2.080806f
+R4 g1803_3 3 2.224404
+C8 4 gnd 2.080806f
+R5 3 4 2.224404
+C9 5 gnd 2.080806f
+R6 4 5 2.224404
+C10 6 gnd 2.080806f
+R7 5 6 2.224404
+C11 7 gnd 2.080806f
+R8 6 7 2.224404
+C12 8 gnd 2.080806f
+R9 7 8 2.224404
+C13 9 gnd 2.080806f
+R10 8 9 2.224404
+C14 10 gnd 2.080806f
+R11 9 10 2.224404
+C15 11 gnd 2.080806f
+R12 10 11 2.224404
+R13 11 g1803_2 2.224404
+R14 g1803_2 g1803_1 2.224404
+.ends
+
+.subckt netg4698 g4698_2 g4698_1 g4698_4 g4698_3 g4698_0 g4698_5 gnd
+C1  g4698_2 gnd 2.080806f
+C2  g4698_1 gnd 2.080806f
+C3  g4698_4 gnd 2.080806f
+C4  g4698_3 gnd 2.080806f
+C5  g4698_0 gnd 2.080806f
+C6  g4698_5 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 g4698_0 1 2.224404
+C8 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g4698_2 2.224404
+C9 3 gnd 2.080806f
+R4 3 g4698_2 2.224404
+R5 3 g4698_4 2.224404
+C10 4 gnd 2.080806f
+R6 g4698_2 4 2.224404
+C11 5 gnd 2.080806f
+R7 4 5 2.224404
+C12 6 gnd 2.080806f
+R8 5 6 2.224404
+R9 6 g4698_1 2.224404
+C13 7 gnd 2.080806f
+R10 7 1 2.224404
+C14 8 gnd 2.080806f
+R11 8 7 2.224404
+C15 9 gnd 2.080806f
+R12 9 8 2.224404
+R13 g4698_3 9 2.224404
+C16 10 gnd 2.080806f
+R14 10 g4698_3 2.224404
+C17 11 gnd 2.080806f
+R15 11 10 2.224404
+C18 12 gnd 2.080806f
+R16 12 11 2.224404
+C19 13 gnd 2.080806f
+R17 12 13 2.224404
+R18 13 g4698_5 2.224404
+.ends
+
+.subckt netg4732 g4732_9 g4732_5 g4732_6 g4732_2 g4732_4 g4732_0 g4732_8 g4732_3 g4732_7 g4732_1 gnd
+C1  g4732_9 gnd 2.080806f
+C2  g4732_5 gnd 2.080806f
+C3  g4732_6 gnd 2.080806f
+C4  g4732_2 gnd 2.080806f
+C5  g4732_4 gnd 2.080806f
+C6  g4732_0 gnd 2.080806f
+C7  g4732_8 gnd 2.080806f
+C8  g4732_3 gnd 2.080806f
+C9  g4732_7 gnd 2.080806f
+C10  g4732_1 gnd 2.080806f
+C11 1 gnd 2.080806f
+R1 1 g4732_0 2.224404
+C12 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g4732_4 2 2.224404
+C13 3 gnd 2.080806f
+R4 3 g4732_4 2.224404
+R5 g4732_6 3 2.224404
+R6 g4732_8 g4732_6 2.224404
+C14 4 gnd 2.080806f
+R7 g4732_8 4 2.224404
+C15 5 gnd 2.080806f
+R8 4 5 2.224404
+R9 g4732_3 5 2.224404
+C16 6 gnd 2.080806f
+R10 6 3 2.224404
+R11 g4732_1 6 2.224404
+C17 7 gnd 2.080806f
+R12 7 g4732_1 2.224404
+R13 g4732_5 7 2.224404
+R14 g4732_7 g4732_5 2.224404
+C18 8 gnd 2.080806f
+R15 5 8 2.224404
+R16 8 g4732_9 2.224404
+C19 9 gnd 2.080806f
+R17 g4732_9 9 2.224404
+R18 9 g4732_2 2.224404
+.ends
+
+.subckt netg2338 g2338_2 g2338_1 g2338_3 g2338_0 gnd
+C1  g2338_2 gnd 2.080806f
+C2  g2338_1 gnd 2.080806f
+C3  g2338_3 gnd 2.080806f
+C4  g2338_0 gnd 2.080806f
+R1 g2338_1 g2338_0 2.224404
+C5 1 gnd 2.080806f
+R2 1 g2338_1 2.224404
+R3 g2338_3 1 2.224404
+C6 2 gnd 2.080806f
+R4 2 g2338_3 2.224404
+C7 3 gnd 2.080806f
+R5 3 2 2.224404
+C8 4 gnd 2.080806f
+R6 4 3 2.224404
+C9 5 gnd 2.080806f
+R7 5 4 2.224404
+C10 6 gnd 2.080806f
+R8 6 5 2.224404
+C11 7 gnd 2.080806f
+R9 7 6 2.224404
+C12 8 gnd 2.080806f
+R10 8 7 2.224404
+C13 9 gnd 2.080806f
+R11 9 8 2.224404
+C14 10 gnd 2.080806f
+R12 10 9 2.224404
+C15 11 gnd 2.080806f
+R13 11 10 2.224404
+R14 g2338_2 11 2.224404
+.ends
+
+.subckt netg2429 g2429_2 g2429_1 g2429_0 gnd
+C1  g2429_2 gnd 2.080806f
+C2  g2429_1 gnd 2.080806f
+C3  g2429_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g2429_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 5 6 2.224404
+C10 7 gnd 2.080806f
+R7 7 6 2.224404
+C11 8 gnd 2.080806f
+R8 7 8 2.224404
+C12 9 gnd 2.080806f
+R9 8 9 2.224404
+C13 10 gnd 2.080806f
+R10 10 9 2.224404
+C14 11 gnd 2.080806f
+R11 10 11 2.224404
+C15 12 gnd 2.080806f
+R12 11 12 2.224404
+R13 12 g2429_2 2.224404
+R14 g2429_2 g2429_1 2.224404
+.ends
+
+.subckt netg805 g805_4 g805_6 g805_2 g805_5 g805_3 g805_0 g805_1 gnd
+C1  g805_4 gnd 2.080806f
+C2  g805_6 gnd 2.080806f
+C3  g805_2 gnd 2.080806f
+C4  g805_5 gnd 2.080806f
+C5  g805_3 gnd 2.080806f
+C6  g805_0 gnd 2.080806f
+C7  g805_1 gnd 2.080806f
+R1 g805_0 g805_3 2.224404
+R2 g805_6 g805_0 2.224404
+C8 1 gnd 2.080806f
+R3 1 g805_3 2.224404
+R4 1 g805_2 2.224404
+C9 2 gnd 2.080806f
+R5 2 g805_6 2.224404
+R6 g805_1 2 2.224404
+C10 3 gnd 2.080806f
+R7 3 g805_1 2.224404
+C11 4 gnd 2.080806f
+R8 4 3 2.224404
+C12 5 gnd 2.080806f
+R9 5 4 2.224404
+C13 6 gnd 2.080806f
+R10 6 5 2.224404
+R11 g805_4 6 2.224404
+C14 7 gnd 2.080806f
+R12 7 g805_4 2.224404
+C15 8 gnd 2.080806f
+R13 8 7 2.224404
+C16 9 gnd 2.080806f
+R14 9 8 2.224404
+R15 g805_5 9 2.224404
+.ends
+
+.subckt netg3665 g3665_2 g3665_9 g3665_6 g3665_3 g3665_1 g3665_7 g3665_5 g3665_8 g3665_4 g3665_0 gnd
+C1  g3665_2 gnd 2.080806f
+C2  g3665_9 gnd 2.080806f
+C3  g3665_6 gnd 2.080806f
+C4  g3665_3 gnd 2.080806f
+C5  g3665_1 gnd 2.080806f
+C6  g3665_7 gnd 2.080806f
+C7  g3665_5 gnd 2.080806f
+C8  g3665_8 gnd 2.080806f
+C9  g3665_4 gnd 2.080806f
+C10  g3665_0 gnd 2.080806f
+C11 1 gnd 2.080806f
+R1 g3665_0 1 2.224404
+R2 1 g3665_1 2.224404
+C12 2 gnd 2.080806f
+R3 2 g3665_0 2.224404
+C13 3 gnd 2.080806f
+R4 3 2 2.224404
+R5 g3665_5 3 2.224404
+R6 g3665_4 g3665_5 2.224404
+C14 4 gnd 2.080806f
+R7 g3665_5 4 2.224404
+R8 4 g3665_6 2.224404
+R9 g3665_2 g3665_6 2.224404
+C15 5 gnd 2.080806f
+R10 5 g3665_4 2.224404
+R11 g3665_8 5 2.224404
+R12 g3665_7 g3665_8 2.224404
+C16 6 gnd 2.080806f
+R13 6 g3665_2 2.224404
+R14 g3665_9 6 2.224404
+C17 7 gnd 2.080806f
+R15 g3665_1 7 2.224404
+C18 8 gnd 2.080806f
+R16 7 8 2.224404
+C19 9 gnd 2.080806f
+R17 8 9 2.224404
+C20 10 gnd 2.080806f
+R18 9 10 2.224404
+R19 10 g3665_3 2.224404
+.ends
+
+.subckt netg5380 g5380_0 g5380_1 gnd
+C1  g5380_0 gnd 2.080806f
+C2  g5380_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5380_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+R14 g5380_1 13 2.224404
+.ends
+
+.subckt netg2101 g2101_2 g2101_3 g2101_0 g2101_5 g2101_4 g2101_1 gnd
+C1  g2101_2 gnd 2.080806f
+C2  g2101_3 gnd 2.080806f
+C3  g2101_0 gnd 2.080806f
+C4  g2101_5 gnd 2.080806f
+C5  g2101_4 gnd 2.080806f
+C6  g2101_1 gnd 2.080806f
+R1 g2101_0 g2101_2 2.224404
+C7 1 gnd 2.080806f
+R2 g2101_0 1 2.224404
+R3 1 g2101_4 2.224404
+C8 2 gnd 2.080806f
+R4 g2101_4 2 2.224404
+C9 3 gnd 2.080806f
+R5 2 3 2.224404
+C10 4 gnd 2.080806f
+R6 3 4 2.224404
+R7 4 g2101_1 2.224404
+C11 5 gnd 2.080806f
+R8 g2101_1 5 2.224404
+C12 6 gnd 2.080806f
+R9 5 6 2.224404
+C13 7 gnd 2.080806f
+R10 6 7 2.224404
+C14 8 gnd 2.080806f
+R11 7 8 2.224404
+C15 9 gnd 2.080806f
+R12 8 9 2.224404
+R13 9 g2101_5 2.224404
+C16 10 gnd 2.080806f
+R14 10 g2101_5 2.224404
+C17 11 gnd 2.080806f
+R15 10 11 2.224404
+R16 11 g2101_3 2.224404
+.ends
+
+.subckt netg4519 g4519_6 g4519_5 g4519_4 g4519_8 g4519_2 g4519_9 g4519_3 g4519_1 g4519_7 g4519_0 gnd
+C1  g4519_6 gnd 2.080806f
+C2  g4519_5 gnd 2.080806f
+C3  g4519_4 gnd 2.080806f
+C4  g4519_8 gnd 2.080806f
+C5  g4519_2 gnd 2.080806f
+C6  g4519_9 gnd 2.080806f
+C7  g4519_3 gnd 2.080806f
+C8  g4519_1 gnd 2.080806f
+C9  g4519_7 gnd 2.080806f
+C10  g4519_0 gnd 2.080806f
+C11 1 gnd 2.080806f
+R1 1 g4519_0 2.224404
+R2 g4519_4 1 2.224404
+C12 2 gnd 2.080806f
+R3 2 g4519_0 2.224404
+R4 g4519_6 2 2.224404
+R5 1 g4519_8 2.224404
+C13 3 gnd 2.080806f
+R6 3 g4519_6 2.224404
+R7 g4519_7 3 2.224404
+R8 g4519_9 3 2.224404
+C14 4 gnd 2.080806f
+R9 4 g4519_7 2.224404
+R10 g4519_2 4 2.224404
+C15 5 gnd 2.080806f
+R11 5 g4519_2 2.224404
+R12 g4519_5 5 2.224404
+C16 6 gnd 2.080806f
+R13 6 g4519_4 2.224404
+C17 7 gnd 2.080806f
+R14 7 6 2.224404
+R15 g4519_1 7 2.224404
+C18 8 gnd 2.080806f
+R16 g4519_0 8 2.224404
+C19 9 gnd 2.080806f
+R17 8 9 2.224404
+C20 10 gnd 2.080806f
+R18 9 10 2.224404
+R19 10 g4519_3 2.224404
+.ends
+
+.subckt netg1978 g1978_4 g1978_1 g1978_5 g1978_6 g1978_2 g1978_7 g1978_0 g1978_3 gnd
+C1  g1978_4 gnd 2.080806f
+C2  g1978_1 gnd 2.080806f
+C3  g1978_5 gnd 2.080806f
+C4  g1978_6 gnd 2.080806f
+C5  g1978_2 gnd 2.080806f
+C6  g1978_7 gnd 2.080806f
+C7  g1978_0 gnd 2.080806f
+C8  g1978_3 gnd 2.080806f
+R1 g1978_6 g1978_0 2.224404
+C9 1 gnd 2.080806f
+R2 1 g1978_6 2.224404
+R3 1 g1978_4 2.224404
+R4 g1978_4 g1978_3 2.224404
+C10 2 gnd 2.080806f
+R5 2 g1978_3 2.224404
+R6 g1978_2 2 2.224404
+C11 3 gnd 2.080806f
+R7 g1978_3 3 2.224404
+C12 4 gnd 2.080806f
+R8 3 4 2.224404
+C13 5 gnd 2.080806f
+R9 4 5 2.224404
+R10 5 g1978_1 2.224404
+C14 6 gnd 2.080806f
+R11 g1978_0 6 2.224404
+C15 7 gnd 2.080806f
+R12 6 7 2.224404
+C16 8 gnd 2.080806f
+R13 7 8 2.224404
+R14 8 g1978_5 2.224404
+C17 9 gnd 2.080806f
+R15 9 g1978_2 2.224404
+C18 10 gnd 2.080806f
+R16 10 9 2.224404
+C19 11 gnd 2.080806f
+R17 11 10 2.224404
+C20 12 gnd 2.080806f
+R18 12 11 2.224404
+R19 g1978_7 12 2.224404
+.ends
+
+.subckt netg4956 g4956_2 g4956_1 g4956_0 g4956_3 gnd
+C1  g4956_2 gnd 2.080806f
+C2  g4956_1 gnd 2.080806f
+C3  g4956_0 gnd 2.080806f
+C4  g4956_3 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g4956_0 1 2.224404
+R2 1 g4956_2 2.224404
+C6 2 gnd 2.080806f
+R3 g4956_2 2 2.224404
+R4 2 g4956_1 2.224404
+C7 3 gnd 2.080806f
+R5 3 g4956_0 2.224404
+C8 4 gnd 2.080806f
+R6 4 3 2.224404
+C9 5 gnd 2.080806f
+R7 5 4 2.224404
+C10 6 gnd 2.080806f
+R8 6 5 2.224404
+C11 7 gnd 2.080806f
+R9 7 6 2.224404
+C12 8 gnd 2.080806f
+R10 8 7 2.224404
+C13 9 gnd 2.080806f
+R11 9 8 2.224404
+C14 10 gnd 2.080806f
+R12 10 9 2.224404
+C15 11 gnd 2.080806f
+R13 11 10 2.224404
+R14 g4956_3 11 2.224404
+.ends
+
+.subckt netg1240 g1240_5 g1240_3 g1240_4 g1240_2 g1240_1 g1240_0 gnd
+C1  g1240_5 gnd 2.080806f
+C2  g1240_3 gnd 2.080806f
+C3  g1240_4 gnd 2.080806f
+C4  g1240_2 gnd 2.080806f
+C5  g1240_1 gnd 2.080806f
+C6  g1240_0 gnd 2.080806f
+R1 g1240_0 g1240_2 2.224404
+C7 1 gnd 2.080806f
+R2 1 g1240_2 2.224404
+C8 2 gnd 2.080806f
+R3 2 1 2.224404
+R4 2 g1240_4 2.224404
+R5 g1240_4 g1240_1 2.224404
+R6 g1240_1 g1240_3 2.224404
+C9 3 gnd 2.080806f
+R7 3 2 2.224404
+C10 4 gnd 2.080806f
+R8 4 3 2.224404
+C11 5 gnd 2.080806f
+R9 5 4 2.224404
+C12 6 gnd 2.080806f
+R10 6 5 2.224404
+C13 7 gnd 2.080806f
+R11 7 6 2.224404
+C14 8 gnd 2.080806f
+R12 8 7 2.224404
+C15 9 gnd 2.080806f
+R13 9 8 2.224404
+C16 10 gnd 2.080806f
+R14 10 9 2.224404
+R15 g1240_5 10 2.224404
+.ends
+
+.subckt netg1281 g1281_1 g1281_0 gnd
+C1  g1281_1 gnd 2.080806f
+C2  g1281_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1281_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+R14 g1281_1 13 2.224404
+.ends
+
+.subckt netg5264 g5264_1 g5264_0 gnd
+C1  g5264_1 gnd 2.080806f
+C2  g5264_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5264_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+R16 g5264_1 15 2.224404
+.ends
+
+.subckt netg5341 g5341_2 g5341_3 g5341_1 g5341_0 gnd
+C1  g5341_2 gnd 2.080806f
+C2  g5341_3 gnd 2.080806f
+C3  g5341_1 gnd 2.080806f
+C4  g5341_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g5341_0 1 2.224404
+R2 1 g5341_1 2.224404
+C6 2 gnd 2.080806f
+R3 g5341_1 2 2.224404
+C7 3 gnd 2.080806f
+R4 2 3 2.224404
+C8 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 4 g5341_3 2.224404
+C9 5 gnd 2.080806f
+R7 g5341_3 5 2.224404
+C10 6 gnd 2.080806f
+R8 5 6 2.224404
+C11 7 gnd 2.080806f
+R9 6 7 2.224404
+C12 8 gnd 2.080806f
+R10 7 8 2.224404
+C13 9 gnd 2.080806f
+R11 8 9 2.224404
+C14 10 gnd 2.080806f
+R12 9 10 2.224404
+C15 11 gnd 2.080806f
+R13 10 11 2.224404
+R14 11 g5341_2 2.224404
+.ends
+
+.subckt netg1099 g1099_0 g1099_1 gnd
+C1  g1099_0 gnd 2.080806f
+C2  g1099_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1099_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+R14 13 g1099_1 2.224404
+.ends
+
+.subckt netg7526 g7526_1 g7526_0 gnd
+C1  g7526_1 gnd 2.080806f
+C2  g7526_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7526_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+R14 13 g7526_1 2.224404
+.ends
+
+.subckt netg4676 g4676_6 g4676_3 g4676_1 g4676_2 g4676_4 g4676_9 g4676_7 g4676_8 g4676_10 g4676_5 gnd
+C1  g4676_6 gnd 2.080806f
+C2  g4676_3 gnd 2.080806f
+C3  g4676_1 gnd 2.080806f
+C4  g4676_2 gnd 2.080806f
+C5  g4676_4 gnd 2.080806f
+C6  g4676_9 gnd 2.080806f
+C7  g4676_7 gnd 2.080806f
+C8  g4676_8 gnd 2.080806f
+C9  g4676_10 gnd 2.080806f
+C10  g4676_5 gnd 2.080806f
+R1 g4676_9 g4676_6 2.224404
+R2 g4676_6 g4676_7 2.224404
+R3 g4676_7 g4676_8 2.224404
+C11 1 gnd 2.080806f
+R4 g4676_7 1 2.224404
+R5 1 g4676_4 2.224404
+C12 2 gnd 2.080806f
+R6 g4676_8 2 2.224404
+R7 2 g4676_3 2.224404
+C13 3 gnd 2.080806f
+R8 3 g4676_3 2.224404
+R9 3 g4676_2 2.224404
+C14 4 gnd 2.080806f
+R10 g4676_2 4 2.224404
+R11 4 g4676_10 2.224404
+R12 g4676_10 g4676_1 2.224404
+C15 5 gnd 2.080806f
+R13 g4676_4 5 2.224404
+C16 6 gnd 2.080806f
+R14 5 6 2.224404
+C17 7 gnd 2.080806f
+R15 6 7 2.224404
+C18 8 gnd 2.080806f
+R16 7 8 2.224404
+R17 g4676_5 8 2.224404
+.ends
+
+.subckt netg4491 g4491_4 g4491_5 g4491_3 g4491_2 g4491_1 g4491_6 g4491_0 gnd
+C1  g4491_4 gnd 2.080806f
+C2  g4491_5 gnd 2.080806f
+C3  g4491_3 gnd 2.080806f
+C4  g4491_2 gnd 2.080806f
+C5  g4491_1 gnd 2.080806f
+C6  g4491_6 gnd 2.080806f
+C7  g4491_0 gnd 2.080806f
+C8 1 gnd 2.080806f
+R1 1 g4491_0 2.224404
+C9 2 gnd 2.080806f
+R2 2 1 2.224404
+C10 3 gnd 2.080806f
+R3 3 2 2.224404
+C11 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 g4491_4 4 2.224404
+C12 5 gnd 2.080806f
+R6 5 g4491_4 2.224404
+C13 6 gnd 2.080806f
+R7 6 5 2.224404
+C14 7 gnd 2.080806f
+R8 7 6 2.224404
+C15 8 gnd 2.080806f
+R9 8 7 2.224404
+C16 9 gnd 2.080806f
+R10 9 8 2.224404
+R11 g4491_1 9 2.224404
+C17 10 gnd 2.080806f
+R12 10 g4491_1 2.224404
+R13 g4491_5 10 2.224404
+R14 10 g4491_6 2.224404
+R15 g4491_6 g4491_2 2.224404
+C18 11 gnd 2.080806f
+R16 11 g4491_2 2.224404
+C19 12 gnd 2.080806f
+R17 12 11 2.224404
+R18 12 g4491_3 2.224404
+.ends
+
+.subckt netg772 g772_2 g772_3 g772_0 g772_1 g772_4 gnd
+C1  g772_2 gnd 2.080806f
+C2  g772_3 gnd 2.080806f
+C3  g772_0 gnd 2.080806f
+C4  g772_1 gnd 2.080806f
+C5  g772_4 gnd 2.080806f
+C6 1 gnd 2.080806f
+R1 1 g772_0 2.224404
+C7 2 gnd 2.080806f
+R2 2 1 2.224404
+C8 3 gnd 2.080806f
+R3 3 2 2.224404
+C9 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 g772_3 4 2.224404
+C10 5 gnd 2.080806f
+R6 3 5 2.224404
+C11 6 gnd 2.080806f
+R7 6 5 2.224404
+R8 g772_4 6 2.224404
+C12 7 gnd 2.080806f
+R9 g772_4 7 2.224404
+C13 8 gnd 2.080806f
+R10 7 8 2.224404
+C14 9 gnd 2.080806f
+R11 8 9 2.224404
+C15 10 gnd 2.080806f
+R12 9 10 2.224404
+R13 10 g772_1 2.224404
+C16 11 gnd 2.080806f
+R14 g772_0 11 2.224404
+C17 12 gnd 2.080806f
+R15 11 12 2.224404
+C18 13 gnd 2.080806f
+R16 12 13 2.224404
+C19 14 gnd 2.080806f
+R17 13 14 2.224404
+C20 15 gnd 2.080806f
+R18 14 15 2.224404
+R19 15 g772_2 2.224404
+.ends
+
+.subckt netg77 g77_1 g77_0 gnd
+C1  g77_1 gnd 2.080806f
+C2  g77_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g77_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+R14 13 g77_1 2.224404
+.ends
+
+.subckt netg7529 g7529_0 g7529_1 gnd
+C1  g7529_0 gnd 2.080806f
+C2  g7529_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7529_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+R14 g7529_1 13 2.224404
+.ends
+
+.subckt netg6351 g6351_0 g6351_1 g6351_3 g6351_2 gnd
+C1  g6351_0 gnd 2.080806f
+C2  g6351_1 gnd 2.080806f
+C3  g6351_3 gnd 2.080806f
+C4  g6351_2 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g6351_0 1 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+C7 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 g6351_2 3 2.224404
+R5 g6351_2 g6351_1 2.224404
+C8 4 gnd 2.080806f
+R6 g6351_0 4 2.224404
+C9 5 gnd 2.080806f
+R7 5 4 2.224404
+C10 6 gnd 2.080806f
+R8 6 5 2.224404
+C11 7 gnd 2.080806f
+R9 7 6 2.224404
+C12 8 gnd 2.080806f
+R10 8 7 2.224404
+C13 9 gnd 2.080806f
+R11 9 8 2.224404
+C14 10 gnd 2.080806f
+R12 10 9 2.224404
+C15 11 gnd 2.080806f
+R13 10 11 2.224404
+C16 12 gnd 2.080806f
+R14 11 12 2.224404
+R15 12 g6351_3 2.224404
+.ends
+
+.subckt netg1456 g1456_0 g1456_1 gnd
+C1  g1456_0 gnd 2.080806f
+C2  g1456_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1456_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+R15 g1456_1 14 2.224404
+.ends
+
+.subckt netg2318 g2318_1 g2318_3 g2318_2 gnd
+C1  g2318_1 gnd 2.080806f
+C2  g2318_3 gnd 2.080806f
+C3  g2318_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g2318_3 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 6 5 2.224404
+C10 7 gnd 2.080806f
+R7 7 6 2.224404
+C11 8 gnd 2.080806f
+R8 8 7 2.224404
+C12 9 gnd 2.080806f
+R9 9 8 2.224404
+C13 10 gnd 2.080806f
+R10 10 9 2.224404
+R11 g2318_2 10 2.224404
+C14 11 gnd 2.080806f
+R12 11 g2318_2 2.224404
+C15 12 gnd 2.080806f
+R13 12 11 2.224404
+C16 13 gnd 2.080806f
+R14 12 13 2.224404
+R15 g2318_1 13 2.224404
+.ends
+
+.subckt netg753 g753_5 g753_6 g753_0 g753_2 g753_3 g753_1 gnd
+C1  g753_5 gnd 2.080806f
+C2  g753_6 gnd 2.080806f
+C3  g753_0 gnd 2.080806f
+C4  g753_2 gnd 2.080806f
+C5  g753_3 gnd 2.080806f
+C6  g753_1 gnd 2.080806f
+R1 g753_5 g753_0 2.224404
+C7 1 gnd 2.080806f
+R2 1 g753_5 2.224404
+C8 2 gnd 2.080806f
+R3 2 1 2.224404
+C9 3 gnd 2.080806f
+R4 3 2 2.224404
+C10 4 gnd 2.080806f
+R5 4 3 2.224404
+R6 g753_1 4 2.224404
+C11 5 gnd 2.080806f
+R7 g753_0 5 2.224404
+C12 6 gnd 2.080806f
+R8 5 6 2.224404
+C13 7 gnd 2.080806f
+R9 6 7 2.224404
+C14 8 gnd 2.080806f
+R10 7 8 2.224404
+C15 9 gnd 2.080806f
+R11 8 9 2.224404
+R12 9 g753_2 2.224404
+C16 10 gnd 2.080806f
+R13 10 g753_2 2.224404
+C17 11 gnd 2.080806f
+R14 11 10 2.224404
+C18 12 gnd 2.080806f
+R15 12 11 2.224404
+C19 13 gnd 2.080806f
+R16 12 13 2.224404
+R17 13 g753_6 2.224404
+R18 g753_6 g753_3 2.224404
+.ends
+
+.subckt netg4802 g4802_6 g4802_9 g4802_7 g4802_3 g4802_1 g4802_5 g4802_0 g4802_8 g4802_2 g4802_4 gnd
+C1  g4802_6 gnd 2.080806f
+C2  g4802_9 gnd 2.080806f
+C3  g4802_7 gnd 2.080806f
+C4  g4802_3 gnd 2.080806f
+C5  g4802_1 gnd 2.080806f
+C6  g4802_5 gnd 2.080806f
+C7  g4802_0 gnd 2.080806f
+C8  g4802_8 gnd 2.080806f
+C9  g4802_2 gnd 2.080806f
+C10  g4802_4 gnd 2.080806f
+R1 g4802_0 g4802_5 2.224404
+C11 1 gnd 2.080806f
+R2 g4802_5 1 2.224404
+R3 1 g4802_1 2.224404
+R4 g4802_1 g4802_2 2.224404
+C12 2 gnd 2.080806f
+R5 g4802_2 2 2.224404
+R6 2 g4802_8 2.224404
+C13 3 gnd 2.080806f
+R7 3 g4802_8 2.224404
+R8 g4802_6 3 2.224404
+C14 4 gnd 2.080806f
+R9 g4802_8 4 2.224404
+R10 4 g4802_9 2.224404
+C15 5 gnd 2.080806f
+R11 5 g4802_2 2.224404
+C16 6 gnd 2.080806f
+R12 6 5 2.224404
+R13 6 g4802_7 2.224404
+C17 7 gnd 2.080806f
+R14 7 g4802_0 2.224404
+C18 8 gnd 2.080806f
+R15 8 7 2.224404
+C19 9 gnd 2.080806f
+R16 9 8 2.224404
+R17 g4802_4 9 2.224404
+C20 10 gnd 2.080806f
+R18 10 g4802_6 2.224404
+C21 11 gnd 2.080806f
+R19 11 10 2.224404
+C22 12 gnd 2.080806f
+R20 12 11 2.224404
+C23 13 gnd 2.080806f
+R21 13 12 2.224404
+C24 14 gnd 2.080806f
+R22 14 13 2.224404
+C25 15 gnd 2.080806f
+R23 15 14 2.224404
+C26 16 gnd 2.080806f
+R24 15 16 2.224404
+R25 g4802_3 16 2.224404
+.ends
+
+.subckt netg1965 g1965_4 g1965_5 g1965_0 g1965_3 g1965_1 g1965_2 gnd
+C1  g1965_4 gnd 2.080806f
+C2  g1965_5 gnd 2.080806f
+C3  g1965_0 gnd 2.080806f
+C4  g1965_3 gnd 2.080806f
+C5  g1965_1 gnd 2.080806f
+C6  g1965_2 gnd 2.080806f
+R1 g1965_0 g1965_2 2.224404
+C7 1 gnd 2.080806f
+R2 g1965_2 1 2.224404
+C8 2 gnd 2.080806f
+R3 1 2 2.224404
+C9 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g1965_5 2.224404
+C10 4 gnd 2.080806f
+R6 g1965_5 4 2.224404
+R7 4 g1965_3 2.224404
+C11 5 gnd 2.080806f
+R8 g1965_3 5 2.224404
+C12 6 gnd 2.080806f
+R9 5 6 2.224404
+C13 7 gnd 2.080806f
+R10 7 6 2.224404
+C14 8 gnd 2.080806f
+R11 7 8 2.224404
+C15 9 gnd 2.080806f
+R12 8 9 2.224404
+C16 10 gnd 2.080806f
+R13 10 9 2.224404
+C17 11 gnd 2.080806f
+R14 10 11 2.224404
+R15 g1965_1 11 2.224404
+C18 12 gnd 2.080806f
+R16 12 g1965_1 2.224404
+C19 13 gnd 2.080806f
+R17 13 12 2.224404
+C20 14 gnd 2.080806f
+R18 13 14 2.224404
+R19 g1965_4 14 2.224404
+.ends
+
+.subckt netg695 g695_1 g695_0 gnd
+C1  g695_1 gnd 2.080806f
+C2  g695_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g695_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+R15 g695_1 14 2.224404
+.ends
+
+.subckt netg2001 g2001_1 g2001_0 g2001_2 gnd
+C1  g2001_1 gnd 2.080806f
+C2  g2001_0 gnd 2.080806f
+C3  g2001_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g2001_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 6 5 2.224404
+C10 7 gnd 2.080806f
+R7 7 6 2.224404
+C11 8 gnd 2.080806f
+R8 8 7 2.224404
+C12 9 gnd 2.080806f
+R9 9 8 2.224404
+C13 10 gnd 2.080806f
+R10 10 9 2.224404
+C14 11 gnd 2.080806f
+R11 11 10 2.224404
+R12 g2001_2 11 2.224404
+C15 12 gnd 2.080806f
+R13 12 g2001_2 2.224404
+C16 13 gnd 2.080806f
+R14 13 12 2.224404
+R15 g2001_1 13 2.224404
+.ends
+
+.subckt netg4177 g4177_0 g4177_1 gnd
+C1  g4177_0 gnd 2.080806f
+C2  g4177_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g4177_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+R15 g4177_1 14 2.224404
+.ends
+
+.subckt netg608 g608_2 g608_1 g608_5 g608_3 g608_0 g608_4 gnd
+C1  g608_2 gnd 2.080806f
+C2  g608_1 gnd 2.080806f
+C3  g608_5 gnd 2.080806f
+C4  g608_3 gnd 2.080806f
+C5  g608_0 gnd 2.080806f
+C6  g608_4 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 g608_0 1 2.224404
+C8 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g608_1 2.224404
+C9 3 gnd 2.080806f
+R4 g608_0 3 2.224404
+C10 4 gnd 2.080806f
+R5 3 4 2.224404
+C11 5 gnd 2.080806f
+R6 4 5 2.224404
+R7 5 g608_5 2.224404
+C12 6 gnd 2.080806f
+R8 g608_5 6 2.224404
+C13 7 gnd 2.080806f
+R9 6 7 2.224404
+R10 7 g608_4 2.224404
+C14 8 gnd 2.080806f
+R11 6 8 2.224404
+C15 9 gnd 2.080806f
+R12 8 9 2.224404
+R13 9 g608_3 2.224404
+C16 10 gnd 2.080806f
+R14 g608_3 10 2.224404
+C17 11 gnd 2.080806f
+R15 10 11 2.224404
+C18 12 gnd 2.080806f
+R16 11 12 2.224404
+C19 13 gnd 2.080806f
+R17 12 13 2.224404
+C20 14 gnd 2.080806f
+R18 13 14 2.224404
+C21 15 gnd 2.080806f
+R19 14 15 2.224404
+R20 15 g608_2 2.224404
+.ends
+
+.subckt netg68 g68_0 g68_1 gnd
+C1  g68_0 gnd 2.080806f
+C2  g68_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g68_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+R15 g68_1 14 2.224404
+.ends
+
+.subckt netg507 g507_1 g507_3 g507_4 g507_0 g507_2 gnd
+C1  g507_1 gnd 2.080806f
+C2  g507_3 gnd 2.080806f
+C3  g507_4 gnd 2.080806f
+C4  g507_0 gnd 2.080806f
+C5  g507_2 gnd 2.080806f
+C6 1 gnd 2.080806f
+R1 g507_0 1 2.224404
+R2 1 g507_3 2.224404
+C7 2 gnd 2.080806f
+R3 g507_3 2 2.224404
+R4 2 g507_2 2.224404
+C8 3 gnd 2.080806f
+R5 g507_3 3 2.224404
+R6 3 g507_4 2.224404
+C9 4 gnd 2.080806f
+R7 g507_2 4 2.224404
+C10 5 gnd 2.080806f
+R8 4 5 2.224404
+C11 6 gnd 2.080806f
+R9 5 6 2.224404
+C12 7 gnd 2.080806f
+R10 6 7 2.224404
+C13 8 gnd 2.080806f
+R11 7 8 2.224404
+C14 9 gnd 2.080806f
+R12 8 9 2.224404
+C15 10 gnd 2.080806f
+R13 9 10 2.224404
+C16 11 gnd 2.080806f
+R14 10 11 2.224404
+C17 12 gnd 2.080806f
+R15 11 12 2.224404
+C18 13 gnd 2.080806f
+R16 12 13 2.224404
+R17 13 g507_1 2.224404
+.ends
+
+.subckt netg2907 g2907_6 g2907_4 g2907_1 g2907_0 g2907_5 g2907_3 g2907_2 gnd
+C1  g2907_6 gnd 2.080806f
+C2  g2907_4 gnd 2.080806f
+C3  g2907_1 gnd 2.080806f
+C4  g2907_0 gnd 2.080806f
+C5  g2907_5 gnd 2.080806f
+C6  g2907_3 gnd 2.080806f
+C7  g2907_2 gnd 2.080806f
+C8 1 gnd 2.080806f
+R1 g2907_0 1 2.224404
+R2 g2907_4 1 2.224404
+C9 2 gnd 2.080806f
+R3 1 2 2.224404
+C10 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g2907_6 2.224404
+C11 4 gnd 2.080806f
+R6 1 4 2.224404
+C12 5 gnd 2.080806f
+R7 4 5 2.224404
+R8 5 g2907_1 2.224404
+R9 g2907_1 g2907_3 2.224404
+C13 6 gnd 2.080806f
+R10 6 g2907_1 2.224404
+C14 7 gnd 2.080806f
+R11 7 6 2.224404
+C15 8 gnd 2.080806f
+R12 8 7 2.224404
+R13 g2907_2 8 2.224404
+C16 9 gnd 2.080806f
+R14 g2907_3 9 2.224404
+C17 10 gnd 2.080806f
+R15 9 10 2.224404
+C18 11 gnd 2.080806f
+R16 10 11 2.224404
+C19 12 gnd 2.080806f
+R17 11 12 2.224404
+R18 12 g2907_5 2.224404
+.ends
+
+.subckt netg5280 g5280_5 g5280_4 g5280_6 g5280_0 g5280_1 g5280_3 g5280_2 gnd
+C1  g5280_5 gnd 2.080806f
+C2  g5280_4 gnd 2.080806f
+C3  g5280_6 gnd 2.080806f
+C4  g5280_0 gnd 2.080806f
+C5  g5280_1 gnd 2.080806f
+C6  g5280_3 gnd 2.080806f
+C7  g5280_2 gnd 2.080806f
+R1 g5280_0 g5280_4 2.224404
+C8 1 gnd 2.080806f
+R2 1 g5280_0 2.224404
+R3 g5280_3 1 2.224404
+C9 2 gnd 2.080806f
+R4 g5280_0 2 2.224404
+R5 g5280_1 2 2.224404
+C10 3 gnd 2.080806f
+R6 g5280_3 3 2.224404
+R7 3 g5280_5 2.224404
+C11 4 gnd 2.080806f
+R8 4 g5280_3 2.224404
+C12 5 gnd 2.080806f
+R9 5 4 2.224404
+R10 g5280_6 5 2.224404
+C13 6 gnd 2.080806f
+R11 6 g5280_5 2.224404
+C14 7 gnd 2.080806f
+R12 7 6 2.224404
+C15 8 gnd 2.080806f
+R13 8 7 2.224404
+C16 9 gnd 2.080806f
+R14 9 8 2.224404
+C17 10 gnd 2.080806f
+R15 10 9 2.224404
+C18 11 gnd 2.080806f
+R16 11 10 2.224404
+C19 12 gnd 2.080806f
+R17 12 11 2.224404
+C20 13 gnd 2.080806f
+R18 13 12 2.224404
+R19 g5280_2 13 2.224404
+.ends
+
+.subckt netg3718 g3718_4 g3718_6 g3718_5 g3718_1 g3718_0 g3718_2 g3718_3 gnd
+C1  g3718_4 gnd 2.080806f
+C2  g3718_6 gnd 2.080806f
+C3  g3718_5 gnd 2.080806f
+C4  g3718_1 gnd 2.080806f
+C5  g3718_0 gnd 2.080806f
+C6  g3718_2 gnd 2.080806f
+C7  g3718_3 gnd 2.080806f
+C8 1 gnd 2.080806f
+R1 g3718_0 1 2.224404
+R2 1 g3718_2 2.224404
+R3 g3718_2 g3718_4 2.224404
+C9 2 gnd 2.080806f
+R4 g3718_2 2 2.224404
+R5 2 g3718_6 2.224404
+C10 3 gnd 2.080806f
+R6 3 g3718_6 2.224404
+C11 4 gnd 2.080806f
+R7 4 3 2.224404
+C12 5 gnd 2.080806f
+R8 5 4 2.224404
+C13 6 gnd 2.080806f
+R9 5 6 2.224404
+R10 g3718_5 6 2.224404
+C14 7 gnd 2.080806f
+R11 7 g3718_5 2.224404
+C15 8 gnd 2.080806f
+R12 8 7 2.224404
+C16 9 gnd 2.080806f
+R13 9 8 2.224404
+C17 10 gnd 2.080806f
+R14 10 9 2.224404
+C18 11 gnd 2.080806f
+R15 11 10 2.224404
+C19 12 gnd 2.080806f
+R16 12 11 2.224404
+R17 g3718_1 12 2.224404
+R18 g3718_3 g3718_1 2.224404
+.ends
+
+.subckt netg1840 g1840_3 g1840_1 g1840_0 g1840_2 gnd
+C1  g1840_3 gnd 2.080806f
+C2  g1840_1 gnd 2.080806f
+C3  g1840_0 gnd 2.080806f
+C4  g1840_2 gnd 2.080806f
+R1 g1840_3 g1840_0 2.224404
+C5 1 gnd 2.080806f
+R2 1 g1840_3 2.224404
+C6 2 gnd 2.080806f
+R3 2 1 2.224404
+C7 3 gnd 2.080806f
+R4 3 2 2.224404
+C8 4 gnd 2.080806f
+R5 4 3 2.224404
+C9 5 gnd 2.080806f
+R6 5 4 2.224404
+C10 6 gnd 2.080806f
+R7 6 5 2.224404
+C11 7 gnd 2.080806f
+R8 7 6 2.224404
+C12 8 gnd 2.080806f
+R9 8 7 2.224404
+C13 9 gnd 2.080806f
+R10 9 8 2.224404
+C14 10 gnd 2.080806f
+R11 10 9 2.224404
+C15 11 gnd 2.080806f
+R12 11 10 2.224404
+R13 g1840_2 11 2.224404
+C16 12 gnd 2.080806f
+R14 12 g1840_2 2.224404
+R15 g1840_1 12 2.224404
+.ends
+
+.subckt netg4626 g4626_0 g4626_1 gnd
+C1  g4626_0 gnd 2.080806f
+C2  g4626_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g4626_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+R15 14 g4626_1 2.224404
+.ends
+
+.subckt netg6446 g6446_1 g6446_0 gnd
+C1  g6446_1 gnd 2.080806f
+C2  g6446_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6446_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+R15 14 g6446_1 2.224404
+.ends
+
+.subckt netg1275 g1275_5 g1275_4 g1275_0 g1275_3 g1275_1 g1275_2 gnd
+C1  g1275_5 gnd 2.080806f
+C2  g1275_4 gnd 2.080806f
+C3  g1275_0 gnd 2.080806f
+C4  g1275_3 gnd 2.080806f
+C5  g1275_1 gnd 2.080806f
+C6  g1275_2 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g1275_0 2.224404
+C8 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 2 g1275_5 2.224404
+C9 3 gnd 2.080806f
+R4 3 2 2.224404
+C10 4 gnd 2.080806f
+R5 4 3 2.224404
+C11 5 gnd 2.080806f
+R6 5 4 2.224404
+C12 6 gnd 2.080806f
+R7 6 5 2.224404
+R8 g1275_2 6 2.224404
+C13 7 gnd 2.080806f
+R9 7 6 2.224404
+C14 8 gnd 2.080806f
+R10 8 7 2.224404
+R11 g1275_4 8 2.224404
+C15 9 gnd 2.080806f
+R12 9 g1275_4 2.224404
+C16 10 gnd 2.080806f
+R13 10 9 2.224404
+C17 11 gnd 2.080806f
+R14 10 11 2.224404
+C18 12 gnd 2.080806f
+R15 11 12 2.224404
+C19 13 gnd 2.080806f
+R16 13 12 2.224404
+C20 14 gnd 2.080806f
+R17 13 14 2.224404
+R18 g1275_3 14 2.224404
+R19 g1275_3 g1275_1 2.224404
+.ends
+
+.subckt netg108 g108_0 g108_1 gnd
+C1  g108_0 gnd 2.080806f
+C2  g108_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g108_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+R15 14 g108_1 2.224404
+.ends
+
+.subckt netg4395 g4395_1 g4395_0 g4395_2 gnd
+C1  g4395_1 gnd 2.080806f
+C2  g4395_0 gnd 2.080806f
+C3  g4395_2 gnd 2.080806f
+R1 g4395_2 g4395_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g4395_2 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 11 10 2.224404
+C15 12 gnd 2.080806f
+R13 12 11 2.224404
+C16 13 gnd 2.080806f
+R14 13 12 2.224404
+R15 g4395_1 13 2.224404
+.ends
+
+.subckt netg3736 g3736_8 g3736_6 g3736_5 g3736_9 g3736_1 g3736_4 g3736_7 g3736_0 g3736_3 g3736_2 gnd
+C1  g3736_8 gnd 2.080806f
+C2  g3736_6 gnd 2.080806f
+C3  g3736_5 gnd 2.080806f
+C4  g3736_9 gnd 2.080806f
+C5  g3736_1 gnd 2.080806f
+C6  g3736_4 gnd 2.080806f
+C7  g3736_7 gnd 2.080806f
+C8  g3736_0 gnd 2.080806f
+C9  g3736_3 gnd 2.080806f
+C10  g3736_2 gnd 2.080806f
+R1 g3736_0 g3736_1 2.224404
+C11 1 gnd 2.080806f
+R2 1 g3736_0 2.224404
+R3 g3736_6 1 2.224404
+C12 2 gnd 2.080806f
+R4 2 g3736_1 2.224404
+C13 3 gnd 2.080806f
+R5 3 2 2.224404
+R6 g3736_3 3 2.224404
+C14 4 gnd 2.080806f
+R7 4 g3736_6 2.224404
+C15 5 gnd 2.080806f
+R8 5 4 2.224404
+R9 g3736_4 5 2.224404
+C16 6 gnd 2.080806f
+R10 6 g3736_6 2.224404
+C17 7 gnd 2.080806f
+R11 7 6 2.224404
+R12 g3736_9 7 2.224404
+C18 8 gnd 2.080806f
+R13 5 8 2.224404
+C19 9 gnd 2.080806f
+R14 9 8 2.224404
+R15 g3736_7 9 2.224404
+C20 10 gnd 2.080806f
+R16 10 g3736_9 2.224404
+C21 11 gnd 2.080806f
+R17 11 10 2.224404
+C22 12 gnd 2.080806f
+R18 12 11 2.224404
+C23 13 gnd 2.080806f
+R19 13 12 2.224404
+C24 14 gnd 2.080806f
+R20 14 13 2.224404
+R21 g3736_8 14 2.224404
+C25 15 gnd 2.080806f
+R22 g3736_8 15 2.224404
+C26 16 gnd 2.080806f
+R23 15 16 2.224404
+R24 16 g3736_2 2.224404
+C27 17 gnd 2.080806f
+R25 17 g3736_8 2.224404
+C28 18 gnd 2.080806f
+R26 18 17 2.224404
+R27 g3736_5 18 2.224404
+.ends
+
+.subckt netg1455 g1455_1 g1455_0 gnd
+C1  g1455_1 gnd 2.080806f
+C2  g1455_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1455_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+R17 16 g1455_1 2.224404
+.ends
+
+.subckt netg1100 g1100_0 g1100_1 gnd
+C1  g1100_0 gnd 2.080806f
+C2  g1100_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1100_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+R15 g1100_1 14 2.224404
+.ends
+
+.subckt netg3839 g3839_0 g3839_5 g3839_4 g3839_2 g3839_1 g3839_3 gnd
+C1  g3839_0 gnd 2.080806f
+C2  g3839_5 gnd 2.080806f
+C3  g3839_4 gnd 2.080806f
+C4  g3839_2 gnd 2.080806f
+C5  g3839_1 gnd 2.080806f
+C6  g3839_3 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 g3839_0 1 2.224404
+R2 g3839_1 1 2.224404
+C8 2 gnd 2.080806f
+R3 2 g3839_0 2.224404
+C9 3 gnd 2.080806f
+R4 3 2 2.224404
+C10 4 gnd 2.080806f
+R5 4 3 2.224404
+R6 g3839_3 4 2.224404
+C11 5 gnd 2.080806f
+R7 5 g3839_3 2.224404
+C12 6 gnd 2.080806f
+R8 6 5 2.224404
+C13 7 gnd 2.080806f
+R9 7 6 2.224404
+C14 8 gnd 2.080806f
+R10 8 7 2.224404
+C15 9 gnd 2.080806f
+R11 8 9 2.224404
+R12 g3839_4 9 2.224404
+C16 10 gnd 2.080806f
+R13 g3839_4 10 2.224404
+C17 11 gnd 2.080806f
+R14 10 11 2.224404
+C18 12 gnd 2.080806f
+R15 11 12 2.224404
+C19 13 gnd 2.080806f
+R16 12 13 2.224404
+C20 14 gnd 2.080806f
+R17 13 14 2.224404
+R18 g3839_5 14 2.224404
+C21 15 gnd 2.080806f
+R19 g3839_5 15 2.224404
+R20 15 g3839_2 2.224404
+.ends
+
+.subckt netg4084 g4084_2 g4084_1 g4084_0 g4084_3 gnd
+C1  g4084_2 gnd 2.080806f
+C2  g4084_1 gnd 2.080806f
+C3  g4084_0 gnd 2.080806f
+C4  g4084_3 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g4084_0 1 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g4084_2 2.224404
+C7 3 gnd 2.080806f
+R4 3 g4084_2 2.224404
+C8 4 gnd 2.080806f
+R5 4 3 2.224404
+C9 5 gnd 2.080806f
+R6 5 4 2.224404
+R7 5 g4084_1 2.224404
+C10 6 gnd 2.080806f
+R8 g4084_1 6 2.224404
+C11 7 gnd 2.080806f
+R9 6 7 2.224404
+C12 8 gnd 2.080806f
+R10 7 8 2.224404
+C13 9 gnd 2.080806f
+R11 8 9 2.224404
+C14 10 gnd 2.080806f
+R12 9 10 2.224404
+C15 11 gnd 2.080806f
+R13 10 11 2.224404
+C16 12 gnd 2.080806f
+R14 11 12 2.224404
+R15 12 g4084_3 2.224404
+.ends
+
+.subckt netg3746 g3746_3 g3746_0 g3746_1 g3746_6 g3746_7 g3746_4 g3746_2 g3746_5 gnd
+C1  g3746_3 gnd 2.080806f
+C2  g3746_0 gnd 2.080806f
+C3  g3746_1 gnd 2.080806f
+C4  g3746_6 gnd 2.080806f
+C5  g3746_7 gnd 2.080806f
+C6  g3746_4 gnd 2.080806f
+C7  g3746_2 gnd 2.080806f
+C8  g3746_5 gnd 2.080806f
+R1 g3746_5 g3746_0 2.224404
+C9 1 gnd 2.080806f
+R2 g3746_0 1 2.224404
+C10 2 gnd 2.080806f
+R3 1 2 2.224404
+C11 3 gnd 2.080806f
+R4 2 3 2.224404
+C12 4 gnd 2.080806f
+R5 3 4 2.224404
+C13 5 gnd 2.080806f
+R6 4 5 2.224404
+R7 5 g3746_1 2.224404
+C14 6 gnd 2.080806f
+R8 g3746_1 6 2.224404
+C15 7 gnd 2.080806f
+R9 6 7 2.224404
+R10 7 g3746_4 2.224404
+C16 8 gnd 2.080806f
+R11 g3746_4 8 2.224404
+C17 9 gnd 2.080806f
+R12 8 9 2.224404
+R13 9 g3746_3 2.224404
+R14 g3746_3 g3746_2 2.224404
+C18 10 gnd 2.080806f
+R15 g3746_3 10 2.224404
+R16 10 g3746_7 2.224404
+C19 11 gnd 2.080806f
+R17 1 11 2.224404
+C20 12 gnd 2.080806f
+R18 11 12 2.224404
+C21 13 gnd 2.080806f
+R19 12 13 2.224404
+C22 14 gnd 2.080806f
+R20 13 14 2.224404
+C23 15 gnd 2.080806f
+R21 14 15 2.224404
+R22 15 g3746_6 2.224404
+.ends
+
+.subckt netg2849 g2849_1 g2849_2 g2849_0 g2849_3 gnd
+C1  g2849_1 gnd 2.080806f
+C2  g2849_2 gnd 2.080806f
+C3  g2849_0 gnd 2.080806f
+C4  g2849_3 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g2849_0 1 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g2849_2 2.224404
+C7 3 gnd 2.080806f
+R4 2 3 2.224404
+C8 4 gnd 2.080806f
+R5 3 4 2.224404
+C9 5 gnd 2.080806f
+R6 4 5 2.224404
+C10 6 gnd 2.080806f
+R7 5 6 2.224404
+R8 6 g2849_3 2.224404
+C11 7 gnd 2.080806f
+R9 g2849_3 7 2.224404
+C12 8 gnd 2.080806f
+R10 7 8 2.224404
+C13 9 gnd 2.080806f
+R11 9 8 2.224404
+C14 10 gnd 2.080806f
+R12 9 10 2.224404
+C15 11 gnd 2.080806f
+R13 10 11 2.224404
+C16 12 gnd 2.080806f
+R14 11 12 2.224404
+C17 13 gnd 2.080806f
+R15 13 12 2.224404
+C18 14 gnd 2.080806f
+R16 13 14 2.224404
+C19 15 gnd 2.080806f
+R17 14 15 2.224404
+R18 15 g2849_1 2.224404
+.ends
+
+.subckt netg3103 g3103_0 g3103_2 g3103_1 gnd
+C1  g3103_0 gnd 2.080806f
+C2  g3103_2 gnd 2.080806f
+C3  g3103_1 gnd 2.080806f
+.ends
+
+.subckt netg2075 g2075_3 g2075_5 g2075_4 g2075_2 g2075_1 g2075_0 gnd
+C1  g2075_3 gnd 2.080806f
+C2  g2075_5 gnd 2.080806f
+C3  g2075_4 gnd 2.080806f
+C4  g2075_2 gnd 2.080806f
+C5  g2075_1 gnd 2.080806f
+C6  g2075_0 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g2075_0 2.224404
+R2 g2075_5 1 2.224404
+C8 2 gnd 2.080806f
+R3 1 2 2.224404
+R4 2 g2075_4 2.224404
+C9 3 gnd 2.080806f
+R5 3 g2075_5 2.224404
+C10 4 gnd 2.080806f
+R6 4 3 2.224404
+R7 g2075_2 4 2.224404
+C11 5 gnd 2.080806f
+R8 5 g2075_4 2.224404
+C12 6 gnd 2.080806f
+R9 6 5 2.224404
+C13 7 gnd 2.080806f
+R10 7 6 2.224404
+C14 8 gnd 2.080806f
+R11 8 7 2.224404
+C15 9 gnd 2.080806f
+R12 9 8 2.224404
+R13 9 g2075_3 2.224404
+C16 10 gnd 2.080806f
+R14 g2075_3 10 2.224404
+C17 11 gnd 2.080806f
+R15 10 11 2.224404
+C18 12 gnd 2.080806f
+R16 11 12 2.224404
+C19 13 gnd 2.080806f
+R17 12 13 2.224404
+C20 14 gnd 2.080806f
+R18 13 14 2.224404
+R19 14 g2075_1 2.224404
+.ends
+
+.subckt netg6573 g6573_4 g6573_0 g6573_2 g6573_1 g6573_5 g6573_3 gnd
+C1  g6573_4 gnd 2.080806f
+C2  g6573_0 gnd 2.080806f
+C3  g6573_2 gnd 2.080806f
+C4  g6573_1 gnd 2.080806f
+C5  g6573_5 gnd 2.080806f
+C6  g6573_3 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g6573_0 2.224404
+C8 2 gnd 2.080806f
+R2 2 1 2.224404
+C9 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g6573_5 2.224404
+C10 4 gnd 2.080806f
+R5 4 g6573_5 2.224404
+C11 5 gnd 2.080806f
+R6 5 4 2.224404
+C12 6 gnd 2.080806f
+R7 5 6 2.224404
+R8 6 g6573_3 2.224404
+C13 7 gnd 2.080806f
+R9 g6573_0 7 2.224404
+C14 8 gnd 2.080806f
+R10 7 8 2.224404
+C15 9 gnd 2.080806f
+R11 8 9 2.224404
+C16 10 gnd 2.080806f
+R12 9 10 2.224404
+R13 10 g6573_1 2.224404
+C17 11 gnd 2.080806f
+R14 11 5 2.224404
+C18 12 gnd 2.080806f
+R15 12 11 2.224404
+R16 g6573_2 12 2.224404
+C19 13 gnd 2.080806f
+R17 g6573_2 13 2.224404
+C20 14 gnd 2.080806f
+R18 14 13 2.224404
+C21 15 gnd 2.080806f
+R19 14 15 2.224404
+R20 g6573_4 15 2.224404
+.ends
+
+.subckt netg1086 g1086_3 g1086_5 g1086_1 g1086_4 gnd
+C1  g1086_3 gnd 2.080806f
+C2  g1086_5 gnd 2.080806f
+C3  g1086_1 gnd 2.080806f
+C4  g1086_4 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g1086_1 1 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+C7 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 g1086_4 3 2.224404
+C8 4 gnd 2.080806f
+R5 4 g1086_1 2.224404
+C9 5 gnd 2.080806f
+R6 5 4 2.224404
+C10 6 gnd 2.080806f
+R7 6 5 2.224404
+C11 7 gnd 2.080806f
+R8 6 7 2.224404
+C12 8 gnd 2.080806f
+R9 8 7 2.224404
+C13 9 gnd 2.080806f
+R10 9 8 2.224404
+R11 g1086_5 9 2.224404
+C14 10 gnd 2.080806f
+R12 10 g1086_5 2.224404
+C15 11 gnd 2.080806f
+R13 11 10 2.224404
+C16 12 gnd 2.080806f
+R14 12 11 2.224404
+C17 13 gnd 2.080806f
+R15 13 12 2.224404
+C18 14 gnd 2.080806f
+R16 14 13 2.224404
+C19 15 gnd 2.080806f
+R17 15 14 2.224404
+C20 16 gnd 2.080806f
+R18 16 15 2.224404
+C21 17 gnd 2.080806f
+R19 17 16 2.224404
+C22 18 gnd 2.080806f
+R20 18 17 2.224404
+C23 19 gnd 2.080806f
+R21 18 19 2.224404
+R22 g1086_3 19 2.224404
+.ends
+
+.subckt netg2540 g2540_1 g2540_2 g2540_0 gnd
+C1  g2540_1 gnd 2.080806f
+C2  g2540_2 gnd 2.080806f
+C3  g2540_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g2540_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 6 5 2.224404
+C10 7 gnd 2.080806f
+R7 7 6 2.224404
+C11 8 gnd 2.080806f
+R8 7 8 2.224404
+R9 g2540_2 8 2.224404
+C12 9 gnd 2.080806f
+R10 g2540_2 9 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 11 10 2.224404
+C15 12 gnd 2.080806f
+R13 12 11 2.224404
+C16 13 gnd 2.080806f
+R14 13 12 2.224404
+C17 14 gnd 2.080806f
+R15 13 14 2.224404
+R16 g2540_1 14 2.224404
+.ends
+
+.subckt netg2096 g2096_4 g2096_2 g2096_1 g2096_3 g2096_0 gnd
+C1  g2096_4 gnd 2.080806f
+C2  g2096_2 gnd 2.080806f
+C3  g2096_1 gnd 2.080806f
+C4  g2096_3 gnd 2.080806f
+C5  g2096_0 gnd 2.080806f
+C6 1 gnd 2.080806f
+R1 g2096_0 1 2.224404
+R2 1 g2096_1 2.224404
+C7 2 gnd 2.080806f
+R3 g2096_1 2 2.224404
+C8 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g2096_2 2.224404
+C9 4 gnd 2.080806f
+R6 g2096_1 4 2.224404
+C10 5 gnd 2.080806f
+R7 4 5 2.224404
+C11 6 gnd 2.080806f
+R8 5 6 2.224404
+C12 7 gnd 2.080806f
+R9 6 7 2.224404
+R10 7 g2096_4 2.224404
+C13 8 gnd 2.080806f
+R11 8 g2096_0 2.224404
+C14 9 gnd 2.080806f
+R12 9 8 2.224404
+C15 10 gnd 2.080806f
+R13 10 9 2.224404
+C16 11 gnd 2.080806f
+R14 11 10 2.224404
+C17 12 gnd 2.080806f
+R15 12 11 2.224404
+C18 13 gnd 2.080806f
+R16 13 12 2.224404
+R17 g2096_3 13 2.224404
+.ends
+
+.subckt netg1337 g1337_3 g1337_1 g1337_2 g1337_5 g1337_0 g1337_6 g1337_4 gnd
+C1  g1337_3 gnd 2.080806f
+C2  g1337_1 gnd 2.080806f
+C3  g1337_2 gnd 2.080806f
+C4  g1337_5 gnd 2.080806f
+C5  g1337_0 gnd 2.080806f
+C6  g1337_6 gnd 2.080806f
+C7  g1337_4 gnd 2.080806f
+C8 1 gnd 2.080806f
+R1 g1337_0 1 2.224404
+C9 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g1337_5 2 2.224404
+C10 3 gnd 2.080806f
+R4 1 3 2.224404
+C11 4 gnd 2.080806f
+R5 3 4 2.224404
+C12 5 gnd 2.080806f
+R6 4 5 2.224404
+R7 5 g1337_6 2.224404
+R8 g1337_6 g1337_3 2.224404
+C13 6 gnd 2.080806f
+R9 g1337_3 6 2.224404
+R10 6 g1337_2 2.224404
+C14 7 gnd 2.080806f
+R11 7 g1337_2 2.224404
+R12 g1337_4 7 2.224404
+C15 8 gnd 2.080806f
+R13 7 8 2.224404
+C16 9 gnd 2.080806f
+R14 8 9 2.224404
+C17 10 gnd 2.080806f
+R15 9 10 2.224404
+C18 11 gnd 2.080806f
+R16 10 11 2.224404
+C19 12 gnd 2.080806f
+R17 11 12 2.224404
+C20 13 gnd 2.080806f
+R18 12 13 2.224404
+R19 13 g1337_1 2.224404
+.ends
+
+.subckt netg6090 g6090_2 g6090_1 g6090_0 gnd
+C1  g6090_2 gnd 2.080806f
+C2  g6090_1 gnd 2.080806f
+C3  g6090_0 gnd 2.080806f
+R1 g6090_0 g6090_1 2.224404
+C4 1 gnd 2.080806f
+R2 1 g6090_1 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 11 10 2.224404
+C15 12 gnd 2.080806f
+R13 12 11 2.224404
+C16 13 gnd 2.080806f
+R14 13 12 2.224404
+C17 14 gnd 2.080806f
+R15 14 13 2.224404
+R16 g6090_2 14 2.224404
+.ends
+
+.subckt netg1592 g1592_3 g1592_1 g1592_0 g1592_2 gnd
+C1  g1592_3 gnd 2.080806f
+C2  g1592_1 gnd 2.080806f
+C3  g1592_0 gnd 2.080806f
+C4  g1592_2 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g1592_0 1 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+C7 3 gnd 2.080806f
+R3 2 3 2.224404
+C8 4 gnd 2.080806f
+R4 3 4 2.224404
+C9 5 gnd 2.080806f
+R5 4 5 2.224404
+C10 6 gnd 2.080806f
+R6 5 6 2.224404
+C11 7 gnd 2.080806f
+R7 6 7 2.224404
+C12 8 gnd 2.080806f
+R8 7 8 2.224404
+C13 9 gnd 2.080806f
+R9 8 9 2.224404
+C14 10 gnd 2.080806f
+R10 9 10 2.224404
+C15 11 gnd 2.080806f
+R11 10 11 2.224404
+R12 11 g1592_3 2.224404
+C16 12 gnd 2.080806f
+R13 12 g1592_3 2.224404
+C17 13 gnd 2.080806f
+R14 12 13 2.224404
+C18 14 gnd 2.080806f
+R15 14 13 2.224404
+C19 15 gnd 2.080806f
+R16 14 15 2.224404
+C20 16 gnd 2.080806f
+R17 15 16 2.224404
+R18 16 g1592_2 2.224404
+R19 g1592_1 g1592_2 2.224404
+.ends
+
+.subckt netg570 g570_1 g570_5 g570_0 g570_4 g570_3 g570_2 gnd
+C1  g570_1 gnd 2.080806f
+C2  g570_5 gnd 2.080806f
+C3  g570_0 gnd 2.080806f
+C4  g570_4 gnd 2.080806f
+C5  g570_3 gnd 2.080806f
+C6  g570_2 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g570_0 2.224404
+R2 g570_1 1 2.224404
+C8 2 gnd 2.080806f
+R3 g570_1 2 2.224404
+C9 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 g570_3 3 2.224404
+C10 4 gnd 2.080806f
+R6 g570_3 4 2.224404
+R7 4 g570_2 2.224404
+C11 5 gnd 2.080806f
+R8 g570_2 5 2.224404
+C12 6 gnd 2.080806f
+R9 5 6 2.224404
+C13 7 gnd 2.080806f
+R10 6 7 2.224404
+C14 8 gnd 2.080806f
+R11 7 8 2.224404
+C15 9 gnd 2.080806f
+R12 8 9 2.224404
+C16 10 gnd 2.080806f
+R13 9 10 2.224404
+C17 11 gnd 2.080806f
+R14 10 11 2.224404
+R15 11 g570_4 2.224404
+C18 12 gnd 2.080806f
+R16 g570_4 12 2.224404
+C19 13 gnd 2.080806f
+R17 12 13 2.224404
+C20 14 gnd 2.080806f
+R18 13 14 2.224404
+R19 14 g570_5 2.224404
+.ends
+
+.subckt netg7147 g7147_2 g7147_1 g7147_0 gnd
+C1  g7147_2 gnd 2.080806f
+C2  g7147_1 gnd 2.080806f
+C3  g7147_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g7147_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g7147_1 2 2.224404
+C6 3 gnd 2.080806f
+R4 g7147_0 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+C8 5 gnd 2.080806f
+R6 4 5 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+C10 7 gnd 2.080806f
+R8 6 7 2.224404
+C11 8 gnd 2.080806f
+R9 7 8 2.224404
+C12 9 gnd 2.080806f
+R10 8 9 2.224404
+C13 10 gnd 2.080806f
+R11 9 10 2.224404
+C14 11 gnd 2.080806f
+R12 10 11 2.224404
+C15 12 gnd 2.080806f
+R13 11 12 2.224404
+C16 13 gnd 2.080806f
+R14 12 13 2.224404
+C17 14 gnd 2.080806f
+R15 13 14 2.224404
+R16 14 g7147_2 2.224404
+.ends
+
+.subckt netg5514 g5514_0 g5514_1 gnd
+C1  g5514_0 gnd 2.080806f
+C2  g5514_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g5514_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+R16 15 g5514_1 2.224404
+.ends
+
+.subckt netg4598 g4598_5 g4598_3 g4598_12 g4598_8 g4598_6 g4598_0 g4598_9 g4598_4 g4598_1 g4598_2 g4598_10 g4598_7 g4598_11 gnd
+C1  g4598_5 gnd 2.080806f
+C2  g4598_3 gnd 2.080806f
+C3  g4598_12 gnd 2.080806f
+C4  g4598_8 gnd 2.080806f
+C5  g4598_6 gnd 2.080806f
+C6  g4598_0 gnd 2.080806f
+C7  g4598_9 gnd 2.080806f
+C8  g4598_4 gnd 2.080806f
+C9  g4598_1 gnd 2.080806f
+C10  g4598_2 gnd 2.080806f
+C11  g4598_10 gnd 2.080806f
+C12  g4598_7 gnd 2.080806f
+C13  g4598_11 gnd 2.080806f
+C14 1 gnd 2.080806f
+R1 1 g4598_0 2.224404
+C15 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g4598_11 2 2.224404
+R4 g4598_8 g4598_11 2.224404
+R5 g4598_2 g4598_8 2.224404
+R6 g4598_6 g4598_8 2.224404
+C16 3 gnd 2.080806f
+R7 3 g4598_11 2.224404
+R8 g4598_4 3 2.224404
+C17 4 gnd 2.080806f
+R9 g4598_11 4 2.224404
+C18 5 gnd 2.080806f
+R10 4 5 2.224404
+C19 6 gnd 2.080806f
+R11 5 6 2.224404
+R12 6 g4598_3 2.224404
+C20 7 gnd 2.080806f
+R13 7 g4598_3 2.224404
+R14 7 g4598_12 2.224404
+R15 g4598_1 g4598_12 2.224404
+R16 g4598_1 g4598_9 2.224404
+C21 8 gnd 2.080806f
+R17 8 g4598_9 2.224404
+R18 8 g4598_7 2.224404
+C22 9 gnd 2.080806f
+R19 g4598_12 9 2.224404
+C23 10 gnd 2.080806f
+R20 9 10 2.224404
+C24 11 gnd 2.080806f
+R21 10 11 2.224404
+R22 11 g4598_5 2.224404
+C25 12 gnd 2.080806f
+R23 g4598_9 12 2.224404
+C26 13 gnd 2.080806f
+R24 12 13 2.224404
+C27 14 gnd 2.080806f
+R25 13 14 2.224404
+C28 15 gnd 2.080806f
+R26 14 15 2.224404
+R27 15 g4598_10 2.224404
+.ends
+
+.subckt netg5258 g5258_0 g5258_1 g5258_4 g5258_3 g5258_2 gnd
+C1  g5258_0 gnd 2.080806f
+C2  g5258_1 gnd 2.080806f
+C3  g5258_4 gnd 2.080806f
+C4  g5258_3 gnd 2.080806f
+C5  g5258_2 gnd 2.080806f
+C6 1 gnd 2.080806f
+R1 1 g5258_0 2.224404
+R2 g5258_1 1 2.224404
+R3 g5258_2 g5258_1 2.224404
+R4 g5258_4 1 2.224404
+C7 2 gnd 2.080806f
+R5 2 g5258_2 2.224404
+C8 3 gnd 2.080806f
+R6 3 2 2.224404
+C9 4 gnd 2.080806f
+R7 4 3 2.224404
+C10 5 gnd 2.080806f
+R8 5 4 2.224404
+C11 6 gnd 2.080806f
+R9 6 5 2.224404
+C12 7 gnd 2.080806f
+R10 7 6 2.224404
+C13 8 gnd 2.080806f
+R11 8 7 2.224404
+C14 9 gnd 2.080806f
+R12 9 8 2.224404
+C15 10 gnd 2.080806f
+R13 10 9 2.224404
+C16 11 gnd 2.080806f
+R14 11 10 2.224404
+C17 12 gnd 2.080806f
+R15 12 11 2.224404
+C18 13 gnd 2.080806f
+R16 12 13 2.224404
+R17 g5258_3 13 2.224404
+.ends
+
+.subckt netg70 g70_0 g70_1 g70_2 gnd
+C1  g70_0 gnd 2.080806f
+C2  g70_1 gnd 2.080806f
+C3  g70_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g70_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 3 g70_2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 11 10 2.224404
+C15 12 gnd 2.080806f
+R13 12 11 2.224404
+C16 13 gnd 2.080806f
+R14 13 12 2.224404
+C17 14 gnd 2.080806f
+R15 14 13 2.224404
+R16 g70_1 14 2.224404
+.ends
+
+.subckt netg1971 g1971_4 g1971_0 g1971_2 g1971_6 g1971_5 g1971_3 g1971_1 gnd
+C1  g1971_4 gnd 2.080806f
+C2  g1971_0 gnd 2.080806f
+C3  g1971_2 gnd 2.080806f
+C4  g1971_6 gnd 2.080806f
+C5  g1971_5 gnd 2.080806f
+C6  g1971_3 gnd 2.080806f
+C7  g1971_1 gnd 2.080806f
+C8 1 gnd 2.080806f
+R1 1 g1971_0 2.224404
+R2 g1971_6 1 2.224404
+C9 2 gnd 2.080806f
+R3 1 2 2.224404
+R4 2 g1971_2 2.224404
+C10 3 gnd 2.080806f
+R5 3 g1971_6 2.224404
+C11 4 gnd 2.080806f
+R6 4 3 2.224404
+C12 5 gnd 2.080806f
+R7 5 4 2.224404
+R8 g1971_3 5 2.224404
+C13 6 gnd 2.080806f
+R9 g1971_3 6 2.224404
+C14 7 gnd 2.080806f
+R10 6 7 2.224404
+C15 8 gnd 2.080806f
+R11 7 8 2.224404
+C16 9 gnd 2.080806f
+R12 8 9 2.224404
+C17 10 gnd 2.080806f
+R13 9 10 2.224404
+R14 g1971_4 10 2.224404
+C18 11 gnd 2.080806f
+R15 10 11 2.224404
+C19 12 gnd 2.080806f
+R16 11 12 2.224404
+R17 12 g1971_5 2.224404
+C20 13 gnd 2.080806f
+R18 g1971_4 13 2.224404
+C21 14 gnd 2.080806f
+R19 13 14 2.224404
+C22 15 gnd 2.080806f
+R20 14 15 2.224404
+C23 16 gnd 2.080806f
+R21 15 16 2.224404
+R22 g1971_1 16 2.224404
+.ends
+
+.subckt netx491 x491_1 x491_0 gnd
+C1  x491_1 gnd 2.080806f
+C2  x491_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 x491_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+R16 15 x491_1 2.224404
+.ends
+
+.subckt netg423 g423_4 g423_1 g423_0 g423_3 g423_2 gnd
+C1  g423_4 gnd 2.080806f
+C2  g423_1 gnd 2.080806f
+C3  g423_0 gnd 2.080806f
+C4  g423_3 gnd 2.080806f
+C5  g423_2 gnd 2.080806f
+C6 1 gnd 2.080806f
+R1 g423_0 1 2.224404
+C7 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g423_1 2.224404
+C8 3 gnd 2.080806f
+R4 3 g423_1 2.224404
+C9 4 gnd 2.080806f
+R5 3 4 2.224404
+C10 5 gnd 2.080806f
+R6 4 5 2.224404
+C11 6 gnd 2.080806f
+R7 5 6 2.224404
+C12 7 gnd 2.080806f
+R8 7 6 2.224404
+C13 8 gnd 2.080806f
+R9 7 8 2.224404
+C14 9 gnd 2.080806f
+R10 8 9 2.224404
+R11 9 g423_3 2.224404
+R12 g423_3 g423_2 2.224404
+C15 10 gnd 2.080806f
+R13 g423_2 10 2.224404
+C16 11 gnd 2.080806f
+R14 10 11 2.224404
+C17 12 gnd 2.080806f
+R15 11 12 2.224404
+C18 13 gnd 2.080806f
+R16 12 13 2.224404
+C19 14 gnd 2.080806f
+R17 13 14 2.224404
+R18 14 g423_4 2.224404
+.ends
+
+.subckt netg760 g760_1 g760_4 g760_2 g760_0 g760_6 g760_3 g760_5 gnd
+C1  g760_1 gnd 2.080806f
+C2  g760_4 gnd 2.080806f
+C3  g760_2 gnd 2.080806f
+C4  g760_0 gnd 2.080806f
+C5  g760_6 gnd 2.080806f
+C6  g760_3 gnd 2.080806f
+C7  g760_5 gnd 2.080806f
+C8 1 gnd 2.080806f
+R1 1 g760_0 2.224404
+C9 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g760_6 2 2.224404
+R4 g760_6 g760_2 2.224404
+C10 3 gnd 2.080806f
+R5 3 g760_0 2.224404
+C11 4 gnd 2.080806f
+R6 4 3 2.224404
+C12 5 gnd 2.080806f
+R7 4 5 2.224404
+C13 6 gnd 2.080806f
+R8 5 6 2.224404
+R9 6 g760_4 2.224404
+C14 7 gnd 2.080806f
+R10 7 g760_4 2.224404
+C15 8 gnd 2.080806f
+R11 7 8 2.224404
+R12 8 g760_1 2.224404
+C16 9 gnd 2.080806f
+R13 9 g760_1 2.224404
+C17 10 gnd 2.080806f
+R14 10 9 2.224404
+C18 11 gnd 2.080806f
+R15 11 10 2.224404
+R16 g760_5 11 2.224404
+C19 12 gnd 2.080806f
+R17 12 g760_5 2.224404
+C20 13 gnd 2.080806f
+R18 13 12 2.224404
+C21 14 gnd 2.080806f
+R19 14 13 2.224404
+R20 g760_3 14 2.224404
+.ends
+
+.subckt netg4498 g4498_7 g4498_6 g4498_2 g4498_8 g4498_1 g4498_9 g4498_4 g4498_5 g4498_0 g4498_3 gnd
+C1  g4498_7 gnd 2.080806f
+C2  g4498_6 gnd 2.080806f
+C3  g4498_2 gnd 2.080806f
+C4  g4498_8 gnd 2.080806f
+C5  g4498_1 gnd 2.080806f
+C6  g4498_9 gnd 2.080806f
+C7  g4498_4 gnd 2.080806f
+C8  g4498_5 gnd 2.080806f
+C9  g4498_0 gnd 2.080806f
+C10  g4498_3 gnd 2.080806f
+C11 1 gnd 2.080806f
+R1 1 g4498_0 2.224404
+C12 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g4498_3 2 2.224404
+C13 3 gnd 2.080806f
+R4 g4498_0 3 2.224404
+C14 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 4 g4498_4 2.224404
+C15 5 gnd 2.080806f
+R7 3 5 2.224404
+R8 5 g4498_5 2.224404
+R9 g4498_5 g4498_7 2.224404
+R10 g4498_7 g4498_2 2.224404
+R11 g4498_2 g4498_9 2.224404
+C16 6 gnd 2.080806f
+R12 g4498_2 6 2.224404
+C17 7 gnd 2.080806f
+R13 6 7 2.224404
+R14 7 g4498_6 2.224404
+C18 8 gnd 2.080806f
+R15 g4498_6 8 2.224404
+C19 9 gnd 2.080806f
+R16 8 9 2.224404
+R17 9 g4498_1 2.224404
+C20 10 gnd 2.080806f
+R18 g4498_1 10 2.224404
+R19 10 g4498_8 2.224404
+.ends
+
+.subckt netg67 g67_1 g67_0 gnd
+C1  g67_1 gnd 2.080806f
+C2  g67_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g67_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+R16 g67_1 15 2.224404
+.ends
+
+.subckt netg6784 g6784_2 g6784_0 g6784_1 gnd
+C1  g6784_2 gnd 2.080806f
+C2  g6784_0 gnd 2.080806f
+C3  g6784_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g6784_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g6784_1 2.224404
+C6 3 gnd 2.080806f
+R4 1 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+C8 5 gnd 2.080806f
+R6 4 5 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+C10 7 gnd 2.080806f
+R8 6 7 2.224404
+C11 8 gnd 2.080806f
+R9 7 8 2.224404
+C12 9 gnd 2.080806f
+R10 8 9 2.224404
+C13 10 gnd 2.080806f
+R11 9 10 2.224404
+C14 11 gnd 2.080806f
+R12 10 11 2.224404
+C15 12 gnd 2.080806f
+R13 11 12 2.224404
+C16 13 gnd 2.080806f
+R14 12 13 2.224404
+C17 14 gnd 2.080806f
+R15 13 14 2.224404
+R16 14 g6784_2 2.224404
+.ends
+
+.subckt netg7436 g7436_1 g7436_0 gnd
+C1  g7436_1 gnd 2.080806f
+C2  g7436_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7436_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+R16 g7436_1 15 2.224404
+.ends
+
+.subckt netg1807 g1807_0 g1807_1 g1807_3 g1807_2 gnd
+C1  g1807_0 gnd 2.080806f
+C2  g1807_1 gnd 2.080806f
+C3  g1807_3 gnd 2.080806f
+C4  g1807_2 gnd 2.080806f
+.ends
+
+.subckt netg72 g72_0 g72_1 g72_2 gnd
+C1  g72_0 gnd 2.080806f
+C2  g72_1 gnd 2.080806f
+C3  g72_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g72_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 6 5 2.224404
+C10 7 gnd 2.080806f
+R7 7 6 2.224404
+R8 g72_2 7 2.224404
+C11 8 gnd 2.080806f
+R9 g72_2 8 2.224404
+C12 9 gnd 2.080806f
+R10 8 9 2.224404
+C13 10 gnd 2.080806f
+R11 9 10 2.224404
+C14 11 gnd 2.080806f
+R12 10 11 2.224404
+C15 12 gnd 2.080806f
+R13 11 12 2.224404
+C16 13 gnd 2.080806f
+R14 12 13 2.224404
+C17 14 gnd 2.080806f
+R15 13 14 2.224404
+C18 15 gnd 2.080806f
+R16 14 15 2.224404
+R17 15 g72_1 2.224404
+.ends
+
+.subckt netg602 g602_4 g602_2 g602_1 g602_0 g602_5 g602_3 gnd
+C1  g602_4 gnd 2.080806f
+C2  g602_2 gnd 2.080806f
+C3  g602_1 gnd 2.080806f
+C4  g602_0 gnd 2.080806f
+C5  g602_5 gnd 2.080806f
+C6  g602_3 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g602_0 2.224404
+C8 2 gnd 2.080806f
+R2 2 1 2.224404
+C9 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g602_4 3 2.224404
+C10 4 gnd 2.080806f
+R5 4 g602_4 2.224404
+C11 5 gnd 2.080806f
+R6 5 4 2.224404
+C12 6 gnd 2.080806f
+R7 6 5 2.224404
+C13 7 gnd 2.080806f
+R8 7 6 2.224404
+C14 8 gnd 2.080806f
+R9 8 7 2.224404
+C15 9 gnd 2.080806f
+R10 9 8 2.224404
+R11 g602_1 9 2.224404
+C16 10 gnd 2.080806f
+R12 10 g602_1 2.224404
+R13 g602_3 10 2.224404
+C17 11 gnd 2.080806f
+R14 11 7 2.224404
+C18 12 gnd 2.080806f
+R15 12 11 2.224404
+R16 g602_5 12 2.224404
+R17 g602_2 g602_5 2.224404
+.ends
+
+.subckt netg6423 g6423_5 g6423_2 g6423_3 g6423_4 g6423_1 g6423_0 g6423_6 gnd
+C1  g6423_5 gnd 2.080806f
+C2  g6423_2 gnd 2.080806f
+C3  g6423_3 gnd 2.080806f
+C4  g6423_4 gnd 2.080806f
+C5  g6423_1 gnd 2.080806f
+C6  g6423_0 gnd 2.080806f
+C7  g6423_6 gnd 2.080806f
+C8 1 gnd 2.080806f
+R1 g6423_0 1 2.224404
+C9 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g6423_1 2.224404
+C10 3 gnd 2.080806f
+R4 1 3 2.224404
+C11 4 gnd 2.080806f
+R5 3 4 2.224404
+C12 5 gnd 2.080806f
+R6 4 5 2.224404
+R7 5 g6423_5 2.224404
+C13 6 gnd 2.080806f
+R8 6 g6423_5 2.224404
+C14 7 gnd 2.080806f
+R9 6 7 2.224404
+R10 7 g6423_4 2.224404
+C15 8 gnd 2.080806f
+R11 g6423_4 8 2.224404
+R12 8 g6423_3 2.224404
+C16 9 gnd 2.080806f
+R13 g6423_4 9 2.224404
+C17 10 gnd 2.080806f
+R14 9 10 2.224404
+C18 11 gnd 2.080806f
+R15 10 11 2.224404
+R16 11 g6423_2 2.224404
+C19 12 gnd 2.080806f
+R17 g6423_2 12 2.224404
+C20 13 gnd 2.080806f
+R18 12 13 2.224404
+C21 14 gnd 2.080806f
+R19 13 14 2.224404
+C22 15 gnd 2.080806f
+R20 14 15 2.224404
+R21 g6423_6 15 2.224404
+.ends
+
+.subckt netg6942 g6942_3 g6942_4 g6942_5 g6942_0 g6942_2 g6942_1 gnd
+C1  g6942_3 gnd 2.080806f
+C2  g6942_4 gnd 2.080806f
+C3  g6942_5 gnd 2.080806f
+C4  g6942_0 gnd 2.080806f
+C5  g6942_2 gnd 2.080806f
+C6  g6942_1 gnd 2.080806f
+R1 g6942_2 g6942_0 2.224404
+C7 1 gnd 2.080806f
+R2 1 g6942_2 2.224404
+C8 2 gnd 2.080806f
+R3 1 2 2.224404
+R4 2 g6942_3 2.224404
+C9 3 gnd 2.080806f
+R5 g6942_3 3 2.224404
+R6 3 g6942_4 2.224404
+C10 4 gnd 2.080806f
+R7 4 g6942_3 2.224404
+C11 5 gnd 2.080806f
+R8 5 4 2.224404
+R9 g6942_1 5 2.224404
+C12 6 gnd 2.080806f
+R10 g6942_0 6 2.224404
+C13 7 gnd 2.080806f
+R11 6 7 2.224404
+C14 8 gnd 2.080806f
+R12 7 8 2.224404
+C15 9 gnd 2.080806f
+R13 8 9 2.224404
+C16 10 gnd 2.080806f
+R14 9 10 2.224404
+C17 11 gnd 2.080806f
+R15 10 11 2.224404
+C18 12 gnd 2.080806f
+R16 11 12 2.224404
+C19 13 gnd 2.080806f
+R17 12 13 2.224404
+R18 13 g6942_5 2.224404
+.ends
+
+.subckt netg3828 g3828_10 g3828_2 g3828_5 g3828_9 g3828_8 g3828_6 g3828_1 g3828_0 g3828_7 g3828_4 g3828_3 gnd
+C1  g3828_10 gnd 2.080806f
+C2  g3828_2 gnd 2.080806f
+C3  g3828_5 gnd 2.080806f
+C4  g3828_9 gnd 2.080806f
+C5  g3828_8 gnd 2.080806f
+C6  g3828_6 gnd 2.080806f
+C7  g3828_1 gnd 2.080806f
+C8  g3828_0 gnd 2.080806f
+C9  g3828_7 gnd 2.080806f
+C10  g3828_4 gnd 2.080806f
+C11  g3828_3 gnd 2.080806f
+C12 1 gnd 2.080806f
+R1 g3828_0 1 2.224404
+R2 1 g3828_1 2.224404
+C13 2 gnd 2.080806f
+R3 g3828_0 2 2.224404
+R4 2 g3828_7 2.224404
+R5 g3828_10 1 2.224404
+C14 3 gnd 2.080806f
+R6 3 g3828_7 2.224404
+R7 3 g3828_8 2.224404
+C15 4 gnd 2.080806f
+R8 g3828_7 4 2.224404
+C16 5 gnd 2.080806f
+R9 4 5 2.224404
+R10 5 g3828_3 2.224404
+R11 g3828_3 g3828_9 2.224404
+R12 g3828_9 g3828_5 2.224404
+R13 g3828_5 g3828_2 2.224404
+C17 6 gnd 2.080806f
+R14 6 g3828_2 2.224404
+R15 6 g3828_4 2.224404
+C18 7 gnd 2.080806f
+R16 7 g3828_0 2.224404
+C19 8 gnd 2.080806f
+R17 8 7 2.224404
+C20 9 gnd 2.080806f
+R18 9 8 2.224404
+C21 10 gnd 2.080806f
+R19 10 9 2.224404
+C22 11 gnd 2.080806f
+R20 11 10 2.224404
+R21 g3828_6 11 2.224404
+.ends
+
+.subckt netg2045 g2045_3 g2045_1 g2045_0 g2045_2 gnd
+C1  g2045_3 gnd 2.080806f
+C2  g2045_1 gnd 2.080806f
+C3  g2045_0 gnd 2.080806f
+C4  g2045_2 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g2045_0 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+C7 3 gnd 2.080806f
+R3 3 2 2.224404
+C8 4 gnd 2.080806f
+R4 4 3 2.224404
+C9 5 gnd 2.080806f
+R5 5 4 2.224404
+R6 g2045_1 5 2.224404
+R7 g2045_2 g2045_1 2.224404
+C10 6 gnd 2.080806f
+R8 6 2 2.224404
+C11 7 gnd 2.080806f
+R9 7 6 2.224404
+C12 8 gnd 2.080806f
+R10 7 8 2.224404
+C13 9 gnd 2.080806f
+R11 8 9 2.224404
+C14 10 gnd 2.080806f
+R12 9 10 2.224404
+C15 11 gnd 2.080806f
+R13 10 11 2.224404
+C16 12 gnd 2.080806f
+R14 11 12 2.224404
+C17 13 gnd 2.080806f
+R15 12 13 2.224404
+C18 14 gnd 2.080806f
+R16 14 13 2.224404
+C19 15 gnd 2.080806f
+R17 14 15 2.224404
+R18 g2045_3 15 2.224404
+.ends
+
+.subckt netg103 g103_1 g103_0 gnd
+C1  g103_1 gnd 2.080806f
+C2  g103_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g103_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+R17 g103_1 16 2.224404
+.ends
+
+.subckt netg1816 g1816_3 g1816_2 g1816_1 g1816_0 gnd
+C1  g1816_3 gnd 2.080806f
+C2  g1816_2 gnd 2.080806f
+C3  g1816_1 gnd 2.080806f
+C4  g1816_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g1816_0 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+C7 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g1816_3 3 2.224404
+C8 4 gnd 2.080806f
+R5 g1816_0 4 2.224404
+C9 5 gnd 2.080806f
+R6 4 5 2.224404
+C10 6 gnd 2.080806f
+R7 5 6 2.224404
+C11 7 gnd 2.080806f
+R8 6 7 2.224404
+C12 8 gnd 2.080806f
+R9 7 8 2.224404
+C13 9 gnd 2.080806f
+R10 8 9 2.224404
+C14 10 gnd 2.080806f
+R11 9 10 2.224404
+R12 10 g1816_1 2.224404
+C15 11 gnd 2.080806f
+R13 g1816_1 11 2.224404
+C16 12 gnd 2.080806f
+R14 11 12 2.224404
+C17 13 gnd 2.080806f
+R15 12 13 2.224404
+C18 14 gnd 2.080806f
+R16 13 14 2.224404
+R17 14 g1816_2 2.224404
+.ends
+
+.subckt netg1500 g1500_0 g1500_1 gnd
+C1  g1500_0 gnd 2.080806f
+C2  g1500_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1500_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+R17 16 g1500_1 2.224404
+.ends
+
+.subckt netg125 g125_1 g125_0 gnd
+C1  g125_1 gnd 2.080806f
+C2  g125_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g125_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+R17 g125_1 16 2.224404
+.ends
+
+.subckt netg6281 g6281_2 g6281_0 g6281_1 gnd
+C1  g6281_2 gnd 2.080806f
+C2  g6281_0 gnd 2.080806f
+C3  g6281_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g6281_0 1 2.224404
+R2 1 g6281_1 2.224404
+C5 2 gnd 2.080806f
+R3 g6281_0 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+C8 5 gnd 2.080806f
+R6 4 5 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+C10 7 gnd 2.080806f
+R8 6 7 2.224404
+C11 8 gnd 2.080806f
+R9 7 8 2.224404
+C12 9 gnd 2.080806f
+R10 8 9 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 10 11 2.224404
+C15 12 gnd 2.080806f
+R13 11 12 2.224404
+C16 13 gnd 2.080806f
+R14 12 13 2.224404
+C17 14 gnd 2.080806f
+R15 14 13 2.224404
+C18 15 gnd 2.080806f
+R16 14 15 2.224404
+C19 16 gnd 2.080806f
+R17 15 16 2.224404
+R18 16 g6281_2 2.224404
+.ends
+
+.subckt netg7144 g7144_1 g7144_2 g7144_0 gnd
+C1  g7144_1 gnd 2.080806f
+C2  g7144_2 gnd 2.080806f
+C3  g7144_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g7144_0 1 2.224404
+R2 1 g7144_2 2.224404
+C5 2 gnd 2.080806f
+R3 g7144_2 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+C8 5 gnd 2.080806f
+R6 4 5 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+C10 7 gnd 2.080806f
+R8 6 7 2.224404
+C11 8 gnd 2.080806f
+R9 7 8 2.224404
+C12 9 gnd 2.080806f
+R10 8 9 2.224404
+C13 10 gnd 2.080806f
+R11 9 10 2.224404
+C14 11 gnd 2.080806f
+R12 10 11 2.224404
+C15 12 gnd 2.080806f
+R13 11 12 2.224404
+C16 13 gnd 2.080806f
+R14 12 13 2.224404
+C17 14 gnd 2.080806f
+R15 13 14 2.224404
+C18 15 gnd 2.080806f
+R16 14 15 2.224404
+R17 15 g7144_1 2.224404
+.ends
+
+.subckt netg4568 g4568_13 g4568_12 g4568_9 g4568_6 g4568_4 g4568_10 g4568_8 g4568_2 g4568_11 g4568_1 g4568_3 g4568_7 gnd
+C1  g4568_13 gnd 2.080806f
+C2  g4568_12 gnd 2.080806f
+C3  g4568_9 gnd 2.080806f
+C4  g4568_6 gnd 2.080806f
+C5  g4568_4 gnd 2.080806f
+C6  g4568_10 gnd 2.080806f
+C7  g4568_8 gnd 2.080806f
+C8  g4568_2 gnd 2.080806f
+C9  g4568_11 gnd 2.080806f
+C10  g4568_1 gnd 2.080806f
+C11  g4568_3 gnd 2.080806f
+C12  g4568_7 gnd 2.080806f
+C13 1 gnd 2.080806f
+R1 g4568_8 1 2.224404
+C14 2 gnd 2.080806f
+R2 1 2 2.224404
+C15 3 gnd 2.080806f
+R3 2 3 2.224404
+C16 4 gnd 2.080806f
+R4 3 4 2.224404
+C17 5 gnd 2.080806f
+R5 4 5 2.224404
+C18 6 gnd 2.080806f
+R6 5 6 2.224404
+R7 6 g4568_3 2.224404
+C19 7 gnd 2.080806f
+R8 g4568_3 7 2.224404
+R9 7 g4568_10 2.224404
+R10 g4568_10 g4568_12 2.224404
+R11 g4568_12 g4568_6 2.224404
+C20 8 gnd 2.080806f
+R12 g4568_6 8 2.224404
+R13 8 g4568_11 2.224404
+R14 8 g4568_13 2.224404
+C21 9 gnd 2.080806f
+R15 9 g4568_12 2.224404
+R16 g4568_1 9 2.224404
+C22 10 gnd 2.080806f
+R17 g4568_13 10 2.224404
+R18 10 g4568_4 2.224404
+R19 g4568_2 g4568_4 2.224404
+C23 11 gnd 2.080806f
+R20 g4568_11 11 2.224404
+R21 11 g4568_9 2.224404
+C24 12 gnd 2.080806f
+R22 g4568_11 12 2.224404
+R23 12 g4568_7 2.224404
+.ends
+
+.subckt netg126 g126_0 g126_1 gnd
+C1  g126_0 gnd 2.080806f
+C2  g126_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g126_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+R17 16 g126_1 2.224404
+.ends
+
+.subckt netg7511 g7511_1 g7511_0 gnd
+C1  g7511_1 gnd 2.080806f
+C2  g7511_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7511_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+R17 16 g7511_1 2.224404
+.ends
+
+.subckt netg2801 g2801_1 g2801_0 gnd
+C1  g2801_1 gnd 2.080806f
+C2  g2801_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g2801_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+R17 16 g2801_1 2.224404
+.ends
+
+.subckt netg105 g105_0 g105_1 gnd
+C1  g105_0 gnd 2.080806f
+C2  g105_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g105_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+R17 g105_1 16 2.224404
+.ends
+
+.subckt netg1282 g1282_1 g1282_0 gnd
+C1  g1282_1 gnd 2.080806f
+C2  g1282_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1282_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+R17 g1282_1 16 2.224404
+.ends
+
+.subckt netg1856 g1856_2 g1856_0 g1856_1 gnd
+C1  g1856_2 gnd 2.080806f
+C2  g1856_0 gnd 2.080806f
+C3  g1856_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g1856_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+C8 5 gnd 2.080806f
+R5 4 5 2.224404
+C9 6 gnd 2.080806f
+R6 5 6 2.224404
+C10 7 gnd 2.080806f
+R7 6 7 2.224404
+C11 8 gnd 2.080806f
+R8 7 8 2.224404
+C12 9 gnd 2.080806f
+R9 8 9 2.224404
+C13 10 gnd 2.080806f
+R10 9 10 2.224404
+C14 11 gnd 2.080806f
+R11 10 11 2.224404
+C15 12 gnd 2.080806f
+R12 11 12 2.224404
+C16 13 gnd 2.080806f
+R13 12 13 2.224404
+R14 13 g1856_2 2.224404
+C17 14 gnd 2.080806f
+R15 13 14 2.224404
+C18 15 gnd 2.080806f
+R16 14 15 2.224404
+R17 15 g1856_1 2.224404
+.ends
+
+.subckt netg6366 g6366_3 g6366_2 g6366_0 g6366_1 gnd
+C1  g6366_3 gnd 2.080806f
+C2  g6366_2 gnd 2.080806f
+C3  g6366_0 gnd 2.080806f
+C4  g6366_1 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g6366_0 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g6366_2 2 2.224404
+C7 3 gnd 2.080806f
+R4 3 g6366_2 2.224404
+R5 g6366_1 3 2.224404
+C8 4 gnd 2.080806f
+R6 g6366_0 4 2.224404
+C9 5 gnd 2.080806f
+R7 4 5 2.224404
+C10 6 gnd 2.080806f
+R8 5 6 2.224404
+C11 7 gnd 2.080806f
+R9 6 7 2.224404
+C12 8 gnd 2.080806f
+R10 7 8 2.224404
+C13 9 gnd 2.080806f
+R11 8 9 2.224404
+C14 10 gnd 2.080806f
+R12 9 10 2.224404
+C15 11 gnd 2.080806f
+R13 10 11 2.224404
+C16 12 gnd 2.080806f
+R14 11 12 2.224404
+C17 13 gnd 2.080806f
+R15 12 13 2.224404
+C18 14 gnd 2.080806f
+R16 13 14 2.224404
+R17 14 g6366_3 2.224404
+.ends
+
+.subckt netg73 g73_2 g73_1 g73_0 gnd
+C1  g73_2 gnd 2.080806f
+C2  g73_1 gnd 2.080806f
+C3  g73_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g73_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 g73_1 4 2.224404
+C8 5 gnd 2.080806f
+R6 g73_0 5 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+C10 7 gnd 2.080806f
+R8 6 7 2.224404
+C11 8 gnd 2.080806f
+R9 7 8 2.224404
+C12 9 gnd 2.080806f
+R10 8 9 2.224404
+C13 10 gnd 2.080806f
+R11 9 10 2.224404
+C14 11 gnd 2.080806f
+R12 10 11 2.224404
+C15 12 gnd 2.080806f
+R13 11 12 2.224404
+C16 13 gnd 2.080806f
+R14 12 13 2.224404
+C17 14 gnd 2.080806f
+R15 13 14 2.224404
+C18 15 gnd 2.080806f
+R16 14 15 2.224404
+R17 15 g73_2 2.224404
+.ends
+
+.subckt netg7534 g7534_1 g7534_0 gnd
+C1  g7534_1 gnd 2.080806f
+C2  g7534_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7534_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+R17 g7534_1 16 2.224404
+.ends
+
+.subckt netg81 g81_1 g81_0 gnd
+C1  g81_1 gnd 2.080806f
+C2  g81_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g81_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+R17 16 g81_1 2.224404
+.ends
+
+.subckt netg6610 g6610_1 g6610_0 gnd
+C1  g6610_1 gnd 2.080806f
+C2  g6610_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6610_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+R17 g6610_1 16 2.224404
+.ends
+
+.subckt netg1600 g1600_2 g1600_3 g1600_1 g1600_0 gnd
+C1  g1600_2 gnd 2.080806f
+C2  g1600_3 gnd 2.080806f
+C3  g1600_1 gnd 2.080806f
+C4  g1600_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g1600_0 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g1600_2 2 2.224404
+C7 3 gnd 2.080806f
+R4 g1600_0 3 2.224404
+C8 4 gnd 2.080806f
+R5 3 4 2.224404
+C9 5 gnd 2.080806f
+R6 4 5 2.224404
+C10 6 gnd 2.080806f
+R7 5 6 2.224404
+C11 7 gnd 2.080806f
+R8 6 7 2.224404
+C12 8 gnd 2.080806f
+R9 7 8 2.224404
+C13 9 gnd 2.080806f
+R10 8 9 2.224404
+C14 10 gnd 2.080806f
+R11 9 10 2.224404
+C15 11 gnd 2.080806f
+R12 10 11 2.224404
+C16 12 gnd 2.080806f
+R13 11 12 2.224404
+R14 12 g1600_1 2.224404
+C17 13 gnd 2.080806f
+R15 g1600_1 13 2.224404
+C18 14 gnd 2.080806f
+R16 13 14 2.224404
+R17 14 g1600_3 2.224404
+.ends
+
+.subckt netg6026 g6026_6 g6026_4 g6026_0 g6026_5 g6026_3 g6026_1 g6026_2 gnd
+C1  g6026_6 gnd 2.080806f
+C2  g6026_4 gnd 2.080806f
+C3  g6026_0 gnd 2.080806f
+C4  g6026_5 gnd 2.080806f
+C5  g6026_3 gnd 2.080806f
+C6  g6026_1 gnd 2.080806f
+C7  g6026_2 gnd 2.080806f
+C8 1 gnd 2.080806f
+R1 g6026_0 1 2.224404
+R2 1 g6026_6 2.224404
+R3 g6026_6 g6026_1 2.224404
+R4 g6026_6 g6026_2 2.224404
+R5 g6026_4 g6026_6 2.224404
+R6 g6026_2 g6026_3 2.224404
+C9 2 gnd 2.080806f
+R7 g6026_0 2 2.224404
+C10 3 gnd 2.080806f
+R8 2 3 2.224404
+C11 4 gnd 2.080806f
+R9 3 4 2.224404
+C12 5 gnd 2.080806f
+R10 5 4 2.224404
+C13 6 gnd 2.080806f
+R11 6 5 2.224404
+C14 7 gnd 2.080806f
+R12 7 6 2.224404
+C15 8 gnd 2.080806f
+R13 8 7 2.224404
+C16 9 gnd 2.080806f
+R14 9 8 2.224404
+C17 10 gnd 2.080806f
+R15 10 9 2.224404
+C18 11 gnd 2.080806f
+R16 11 10 2.224404
+C19 12 gnd 2.080806f
+R17 11 12 2.224404
+C20 13 gnd 2.080806f
+R18 12 13 2.224404
+R19 13 g6026_5 2.224404
+.ends
+
+.subckt netg80 g80_0 g80_1 gnd
+C1  g80_0 gnd 2.080806f
+C2  g80_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g80_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+R17 16 g80_1 2.224404
+.ends
+
+.subckt netg1350 g1350_5 g1350_4 g1350_2 g1350_0 g1350_3 g1350_1 gnd
+C1  g1350_5 gnd 2.080806f
+C2  g1350_4 gnd 2.080806f
+C3  g1350_2 gnd 2.080806f
+C4  g1350_0 gnd 2.080806f
+C5  g1350_3 gnd 2.080806f
+C6  g1350_1 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 g1350_0 1 2.224404
+C8 2 gnd 2.080806f
+R2 1 2 2.224404
+C9 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g1350_3 2.224404
+C10 4 gnd 2.080806f
+R5 4 g1350_0 2.224404
+C11 5 gnd 2.080806f
+R6 4 5 2.224404
+C12 6 gnd 2.080806f
+R7 5 6 2.224404
+C13 7 gnd 2.080806f
+R8 7 6 2.224404
+C14 8 gnd 2.080806f
+R9 7 8 2.224404
+R10 g1350_5 8 2.224404
+C15 9 gnd 2.080806f
+R11 9 4 2.224404
+C16 10 gnd 2.080806f
+R12 10 9 2.224404
+C17 11 gnd 2.080806f
+R13 11 10 2.224404
+C18 12 gnd 2.080806f
+R14 12 11 2.224404
+C19 13 gnd 2.080806f
+R15 13 12 2.224404
+R16 g1350_4 13 2.224404
+C20 14 gnd 2.080806f
+R17 14 g1350_4 2.224404
+R18 g1350_1 14 2.224404
+C21 15 gnd 2.080806f
+R19 g1350_1 15 2.224404
+C22 16 gnd 2.080806f
+R20 16 15 2.224404
+C23 17 gnd 2.080806f
+R21 16 17 2.224404
+C24 18 gnd 2.080806f
+R22 17 18 2.224404
+C25 19 gnd 2.080806f
+R23 19 18 2.224404
+C26 20 gnd 2.080806f
+R24 19 20 2.224404
+R25 g1350_2 20 2.224404
+.ends
+
+.subckt netg2049 g2049_5 g2049_0 g2049_1 g2049_4 g2049_2 g2049_3 gnd
+C1  g2049_5 gnd 2.080806f
+C2  g2049_0 gnd 2.080806f
+C3  g2049_1 gnd 2.080806f
+C4  g2049_4 gnd 2.080806f
+C5  g2049_2 gnd 2.080806f
+C6  g2049_3 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 g2049_0 1 2.224404
+C8 2 gnd 2.080806f
+R2 1 2 2.224404
+C9 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g2049_2 2.224404
+C10 4 gnd 2.080806f
+R5 4 g2049_2 2.224404
+C11 5 gnd 2.080806f
+R6 5 4 2.224404
+C12 6 gnd 2.080806f
+R7 6 5 2.224404
+C13 7 gnd 2.080806f
+R8 6 7 2.224404
+C14 8 gnd 2.080806f
+R9 8 7 2.224404
+C15 9 gnd 2.080806f
+R10 8 9 2.224404
+C16 10 gnd 2.080806f
+R11 9 10 2.224404
+R12 10 g2049_3 2.224404
+C17 11 gnd 2.080806f
+R13 11 9 2.224404
+C18 12 gnd 2.080806f
+R14 12 11 2.224404
+R15 g2049_5 12 2.224404
+C19 13 gnd 2.080806f
+R16 13 g2049_5 2.224404
+C20 14 gnd 2.080806f
+R17 14 13 2.224404
+C21 15 gnd 2.080806f
+R18 14 15 2.224404
+C22 16 gnd 2.080806f
+R19 15 16 2.224404
+R20 16 g2049_1 2.224404
+C23 17 gnd 2.080806f
+R21 17 14 2.224404
+C24 18 gnd 2.080806f
+R22 18 17 2.224404
+R23 g2049_4 18 2.224404
+.ends
+
+.subckt netg71 g71_1 g71_2 g71_0 gnd
+C1  g71_1 gnd 2.080806f
+C2  g71_2 gnd 2.080806f
+C3  g71_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g71_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g71_1 3 2.224404
+C7 4 gnd 2.080806f
+R5 4 g71_1 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 11 10 2.224404
+C15 12 gnd 2.080806f
+R13 12 11 2.224404
+C16 13 gnd 2.080806f
+R14 13 12 2.224404
+C17 14 gnd 2.080806f
+R15 14 13 2.224404
+C18 15 gnd 2.080806f
+R16 15 14 2.224404
+R17 g71_2 15 2.224404
+.ends
+
+.subckt netg4812 g4812_6 g4812_1 g4812_3 g4812_7 g4812_5 g4812_2 g4812_4 gnd
+C1  g4812_6 gnd 2.080806f
+C2  g4812_1 gnd 2.080806f
+C3  g4812_3 gnd 2.080806f
+C4  g4812_7 gnd 2.080806f
+C5  g4812_5 gnd 2.080806f
+C6  g4812_2 gnd 2.080806f
+C7  g4812_4 gnd 2.080806f
+C8 1 gnd 2.080806f
+R1 1 g4812_2 2.224404
+R2 g4812_5 1 2.224404
+R3 g4812_6 g4812_5 2.224404
+C9 2 gnd 2.080806f
+R4 2 g4812_2 2.224404
+C10 3 gnd 2.080806f
+R5 3 2 2.224404
+R6 g4812_3 3 2.224404
+C11 4 gnd 2.080806f
+R7 4 g4812_3 2.224404
+C12 5 gnd 2.080806f
+R8 5 4 2.224404
+C13 6 gnd 2.080806f
+R9 6 5 2.224404
+C14 7 gnd 2.080806f
+R10 7 6 2.224404
+C15 8 gnd 2.080806f
+R11 8 7 2.224404
+C16 9 gnd 2.080806f
+R12 9 8 2.224404
+C17 10 gnd 2.080806f
+R13 10 9 2.224404
+C18 11 gnd 2.080806f
+R14 11 10 2.224404
+R15 g4812_7 11 2.224404
+C19 12 gnd 2.080806f
+R16 12 g4812_7 2.224404
+C20 13 gnd 2.080806f
+R17 13 12 2.224404
+R18 g4812_4 13 2.224404
+C21 14 gnd 2.080806f
+R19 14 g4812_4 2.224404
+C22 15 gnd 2.080806f
+R20 15 14 2.224404
+C23 16 gnd 2.080806f
+R21 15 16 2.224404
+C24 17 gnd 2.080806f
+R22 16 17 2.224404
+R23 17 g4812_1 2.224404
+.ends
+
+.subckt netg104 g104_0 g104_1 gnd
+C1  g104_0 gnd 2.080806f
+C2  g104_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g104_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+R17 16 g104_1 2.224404
+.ends
+
+.subckt netg6703 g6703_1 g6703_0 gnd
+C1  g6703_1 gnd 2.080806f
+C2  g6703_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6703_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+R18 17 g6703_1 2.224404
+.ends
+
+.subckt netg1616 g1616_3 g1616_2 g1616_0 g1616_1 gnd
+C1  g1616_3 gnd 2.080806f
+C2  g1616_2 gnd 2.080806f
+C3  g1616_0 gnd 2.080806f
+C4  g1616_1 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g1616_0 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+C7 3 gnd 2.080806f
+R3 3 2 2.224404
+C8 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 4 g1616_1 2.224404
+C9 5 gnd 2.080806f
+R6 g1616_1 5 2.224404
+C10 6 gnd 2.080806f
+R7 5 6 2.224404
+C11 7 gnd 2.080806f
+R8 6 7 2.224404
+C12 8 gnd 2.080806f
+R9 7 8 2.224404
+C13 9 gnd 2.080806f
+R10 8 9 2.224404
+R11 9 g1616_3 2.224404
+C14 10 gnd 2.080806f
+R12 10 4 2.224404
+C15 11 gnd 2.080806f
+R13 11 10 2.224404
+C16 12 gnd 2.080806f
+R14 12 11 2.224404
+C17 13 gnd 2.080806f
+R15 13 12 2.224404
+C18 14 gnd 2.080806f
+R16 14 13 2.224404
+C19 15 gnd 2.080806f
+R17 15 14 2.224404
+C20 16 gnd 2.080806f
+R18 16 15 2.224404
+C21 17 gnd 2.080806f
+R19 17 16 2.224404
+C22 18 gnd 2.080806f
+R20 17 18 2.224404
+R21 g1616_2 18 2.224404
+.ends
+
+.subckt netg6401 g6401_0 g6401_1 gnd
+C1  g6401_0 gnd 2.080806f
+C2  g6401_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6401_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+R18 g6401_1 17 2.224404
+.ends
+
+.subckt netg3694 g3694_3 g3694_1 g3694_2 g3694_0 gnd
+C1  g3694_3 gnd 2.080806f
+C2  g3694_1 gnd 2.080806f
+C3  g3694_2 gnd 2.080806f
+C4  g3694_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g3694_0 1 2.224404
+R2 g3694_1 1 2.224404
+R3 1 g3694_2 2.224404
+C6 2 gnd 2.080806f
+R4 2 g3694_1 2.224404
+C7 3 gnd 2.080806f
+R5 3 2 2.224404
+C8 4 gnd 2.080806f
+R6 4 3 2.224404
+C9 5 gnd 2.080806f
+R7 5 4 2.224404
+C10 6 gnd 2.080806f
+R8 6 5 2.224404
+C11 7 gnd 2.080806f
+R9 7 6 2.224404
+C12 8 gnd 2.080806f
+R10 8 7 2.224404
+C13 9 gnd 2.080806f
+R11 9 8 2.224404
+C14 10 gnd 2.080806f
+R12 10 9 2.224404
+C15 11 gnd 2.080806f
+R13 11 10 2.224404
+C16 12 gnd 2.080806f
+R14 12 11 2.224404
+C17 13 gnd 2.080806f
+R15 13 12 2.224404
+C18 14 gnd 2.080806f
+R16 14 13 2.224404
+C19 15 gnd 2.080806f
+R17 15 14 2.224404
+C20 16 gnd 2.080806f
+R18 16 15 2.224404
+R19 g3694_3 16 2.224404
+.ends
+
+.subckt netg1679 g1679_0 g1679_3 g1679_2 g1679_1 gnd
+C1  g1679_0 gnd 2.080806f
+C2  g1679_3 gnd 2.080806f
+C3  g1679_2 gnd 2.080806f
+C4  g1679_1 gnd 2.080806f
+R1 g1679_0 g1679_2 2.224404
+C5 1 gnd 2.080806f
+R2 g1679_2 1 2.224404
+C6 2 gnd 2.080806f
+R3 1 2 2.224404
+C7 3 gnd 2.080806f
+R4 2 3 2.224404
+C8 4 gnd 2.080806f
+R5 3 4 2.224404
+C9 5 gnd 2.080806f
+R6 4 5 2.224404
+C10 6 gnd 2.080806f
+R7 5 6 2.224404
+R8 6 g1679_3 2.224404
+C11 7 gnd 2.080806f
+R9 7 g1679_3 2.224404
+C12 8 gnd 2.080806f
+R10 8 7 2.224404
+C13 9 gnd 2.080806f
+R11 9 8 2.224404
+C14 10 gnd 2.080806f
+R12 10 9 2.224404
+C15 11 gnd 2.080806f
+R13 11 10 2.224404
+C16 12 gnd 2.080806f
+R14 12 11 2.224404
+C17 13 gnd 2.080806f
+R15 12 13 2.224404
+C18 14 gnd 2.080806f
+R16 14 13 2.224404
+C19 15 gnd 2.080806f
+R17 15 14 2.224404
+C20 16 gnd 2.080806f
+R18 16 15 2.224404
+C21 17 gnd 2.080806f
+R19 17 16 2.224404
+C22 18 gnd 2.080806f
+R20 18 17 2.224404
+R21 g1679_1 18 2.224404
+.ends
+
+.subckt netg3024 g3024_5 g3024_1 g3024_4 g3024_2 g3024_3 g3024_0 gnd
+C1  g3024_5 gnd 2.080806f
+C2  g3024_1 gnd 2.080806f
+C3  g3024_4 gnd 2.080806f
+C4  g3024_2 gnd 2.080806f
+C5  g3024_3 gnd 2.080806f
+C6  g3024_0 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 g3024_0 1 2.224404
+C8 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g3024_4 2.224404
+C9 3 gnd 2.080806f
+R4 3 g3024_4 2.224404
+C10 4 gnd 2.080806f
+R5 3 4 2.224404
+C11 5 gnd 2.080806f
+R6 4 5 2.224404
+R7 5 g3024_3 2.224404
+C12 6 gnd 2.080806f
+R8 6 g3024_3 2.224404
+C13 7 gnd 2.080806f
+R9 7 6 2.224404
+C14 8 gnd 2.080806f
+R10 8 7 2.224404
+R11 8 g3024_2 2.224404
+C15 9 gnd 2.080806f
+R12 9 8 2.224404
+C16 10 gnd 2.080806f
+R13 10 9 2.224404
+C17 11 gnd 2.080806f
+R14 11 10 2.224404
+C18 12 gnd 2.080806f
+R15 12 11 2.224404
+C19 13 gnd 2.080806f
+R16 13 12 2.224404
+C20 14 gnd 2.080806f
+R17 14 13 2.224404
+R18 g3024_1 14 2.224404
+C21 15 gnd 2.080806f
+R19 15 g3024_1 2.224404
+C22 16 gnd 2.080806f
+R20 16 15 2.224404
+C23 17 gnd 2.080806f
+R21 17 16 2.224404
+C24 18 gnd 2.080806f
+R22 17 18 2.224404
+C25 19 gnd 2.080806f
+R23 18 19 2.224404
+R24 19 g3024_5 2.224404
+.ends
+
+.subckt netg628 g628_4 g628_2 g628_5 g628_3 g628_1 g628_0 gnd
+C1  g628_4 gnd 2.080806f
+C2  g628_2 gnd 2.080806f
+C3  g628_5 gnd 2.080806f
+C4  g628_3 gnd 2.080806f
+C5  g628_1 gnd 2.080806f
+C6  g628_0 gnd 2.080806f
+R1 g628_2 g628_0 2.224404
+R2 g628_0 g628_4 2.224404
+R3 g628_4 g628_1 2.224404
+C7 1 gnd 2.080806f
+R4 g628_1 1 2.224404
+C8 2 gnd 2.080806f
+R5 1 2 2.224404
+C9 3 gnd 2.080806f
+R6 2 3 2.224404
+C10 4 gnd 2.080806f
+R7 3 4 2.224404
+C11 5 gnd 2.080806f
+R8 4 5 2.224404
+C12 6 gnd 2.080806f
+R9 5 6 2.224404
+R10 6 g628_3 2.224404
+C13 7 gnd 2.080806f
+R11 7 g628_3 2.224404
+C14 8 gnd 2.080806f
+R12 8 7 2.224404
+C15 9 gnd 2.080806f
+R13 9 8 2.224404
+C16 10 gnd 2.080806f
+R14 10 9 2.224404
+C17 11 gnd 2.080806f
+R15 11 10 2.224404
+C18 12 gnd 2.080806f
+R16 12 11 2.224404
+C19 13 gnd 2.080806f
+R17 13 12 2.224404
+C20 14 gnd 2.080806f
+R18 14 13 2.224404
+R19 g628_5 14 2.224404
+.ends
+
+.subckt netg4711 g4711_4 g4711_7 g4711_2 g4711_1 g4711_8 g4711_6 g4711_0 g4711_3 g4711_9 g4711_5 gnd
+C1  g4711_4 gnd 2.080806f
+C2  g4711_7 gnd 2.080806f
+C3  g4711_2 gnd 2.080806f
+C4  g4711_1 gnd 2.080806f
+C5  g4711_8 gnd 2.080806f
+C6  g4711_6 gnd 2.080806f
+C7  g4711_0 gnd 2.080806f
+C8  g4711_3 gnd 2.080806f
+C9  g4711_9 gnd 2.080806f
+C10  g4711_5 gnd 2.080806f
+C11 1 gnd 2.080806f
+R1 g4711_0 1 2.224404
+R2 1 g4711_2 2.224404
+R3 g4711_2 g4711_7 2.224404
+R4 g4711_4 1 2.224404
+C12 2 gnd 2.080806f
+R5 1 2 2.224404
+R6 2 g4711_5 2.224404
+C13 3 gnd 2.080806f
+R7 3 g4711_0 2.224404
+C14 4 gnd 2.080806f
+R8 4 3 2.224404
+C15 5 gnd 2.080806f
+R9 5 4 2.224404
+R10 g4711_3 5 2.224404
+C16 6 gnd 2.080806f
+R11 g4711_3 6 2.224404
+R12 g4711_1 6 2.224404
+C17 7 gnd 2.080806f
+R13 g4711_7 7 2.224404
+C18 8 gnd 2.080806f
+R14 7 8 2.224404
+C19 9 gnd 2.080806f
+R15 8 9 2.224404
+R16 9 g4711_8 2.224404
+C20 10 gnd 2.080806f
+R17 10 g4711_1 2.224404
+C21 11 gnd 2.080806f
+R18 11 10 2.224404
+C22 12 gnd 2.080806f
+R19 12 11 2.224404
+C23 13 gnd 2.080806f
+R20 13 12 2.224404
+R21 g4711_9 13 2.224404
+C24 14 gnd 2.080806f
+R22 13 14 2.224404
+R23 14 g4711_6 2.224404
+.ends
+
+.subckt netg4463 g4463_10 g4463_5 g4463_9 g4463_4 g4463_8 g4463_2 g4463_6 g4463_0 g4463_1 g4463_7 g4463_3 gnd
+C1  g4463_10 gnd 2.080806f
+C2  g4463_5 gnd 2.080806f
+C3  g4463_9 gnd 2.080806f
+C4  g4463_4 gnd 2.080806f
+C5  g4463_8 gnd 2.080806f
+C6  g4463_2 gnd 2.080806f
+C7  g4463_6 gnd 2.080806f
+C8  g4463_0 gnd 2.080806f
+C9  g4463_1 gnd 2.080806f
+C10  g4463_7 gnd 2.080806f
+C11  g4463_3 gnd 2.080806f
+R1 g4463_2 g4463_0 2.224404
+C12 1 gnd 2.080806f
+R2 1 g4463_2 2.224404
+C13 2 gnd 2.080806f
+R3 2 1 2.224404
+R4 g4463_3 2 2.224404
+R5 g4463_5 g4463_3 2.224404
+R6 g4463_6 g4463_3 2.224404
+R7 2 g4463_10 2.224404
+R8 g4463_9 g4463_10 2.224404
+C14 3 gnd 2.080806f
+R9 g4463_9 3 2.224404
+C15 4 gnd 2.080806f
+R10 3 4 2.224404
+R11 4 g4463_7 2.224404
+C16 5 gnd 2.080806f
+R12 g4463_0 5 2.224404
+C17 6 gnd 2.080806f
+R13 5 6 2.224404
+C18 7 gnd 2.080806f
+R14 6 7 2.224404
+R15 g4463_8 7 2.224404
+C19 8 gnd 2.080806f
+R16 7 8 2.224404
+R17 8 g4463_1 2.224404
+C20 9 gnd 2.080806f
+R18 g4463_7 9 2.224404
+C21 10 gnd 2.080806f
+R19 9 10 2.224404
+C22 11 gnd 2.080806f
+R20 10 11 2.224404
+C23 12 gnd 2.080806f
+R21 11 12 2.224404
+C24 13 gnd 2.080806f
+R22 12 13 2.224404
+C25 14 gnd 2.080806f
+R23 13 14 2.224404
+R24 14 g4463_4 2.224404
+.ends
+
+.subckt netg5799 g5799_1 g5799_2 g5799_0 gnd
+C1  g5799_1 gnd 2.080806f
+C2  g5799_2 gnd 2.080806f
+C3  g5799_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5799_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g5799_1 2.224404
+C7 4 gnd 2.080806f
+R5 g5799_1 4 2.224404
+C8 5 gnd 2.080806f
+R6 4 5 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+C10 7 gnd 2.080806f
+R8 6 7 2.224404
+C11 8 gnd 2.080806f
+R9 7 8 2.224404
+C12 9 gnd 2.080806f
+R10 8 9 2.224404
+C13 10 gnd 2.080806f
+R11 9 10 2.224404
+C14 11 gnd 2.080806f
+R12 10 11 2.224404
+C15 12 gnd 2.080806f
+R13 11 12 2.224404
+C16 13 gnd 2.080806f
+R14 12 13 2.224404
+C17 14 gnd 2.080806f
+R15 13 14 2.224404
+C18 15 gnd 2.080806f
+R16 14 15 2.224404
+C19 16 gnd 2.080806f
+R17 15 16 2.224404
+R18 16 g5799_2 2.224404
+.ends
+
+.subckt netg3517 g3517_1 g3517_0 gnd
+C1  g3517_1 gnd 2.080806f
+C2  g3517_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3517_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+R20 g3517_1 19 2.224404
+.ends
+
+.subckt netg4721 g4721_5 g4721_2 g4721_8 g4721_4 g4721_0 g4721_3 g4721_9 g4721_6 g4721_1 g4721_7 g4721_10 gnd
+C1  g4721_5 gnd 2.080806f
+C2  g4721_2 gnd 2.080806f
+C3  g4721_8 gnd 2.080806f
+C4  g4721_4 gnd 2.080806f
+C5  g4721_0 gnd 2.080806f
+C6  g4721_3 gnd 2.080806f
+C7  g4721_9 gnd 2.080806f
+C8  g4721_6 gnd 2.080806f
+C9  g4721_1 gnd 2.080806f
+C10  g4721_7 gnd 2.080806f
+C11  g4721_10 gnd 2.080806f
+C12 1 gnd 2.080806f
+R1 1 g4721_0 2.224404
+C13 2 gnd 2.080806f
+R2 2 1 2.224404
+C14 3 gnd 2.080806f
+R3 3 2 2.224404
+C15 4 gnd 2.080806f
+R4 4 3 2.224404
+C16 5 gnd 2.080806f
+R5 5 4 2.224404
+R6 g4721_4 5 2.224404
+C17 6 gnd 2.080806f
+R7 5 6 2.224404
+R8 6 g4721_5 2.224404
+C18 7 gnd 2.080806f
+R9 g4721_5 7 2.224404
+R10 7 g4721_7 2.224404
+C19 8 gnd 2.080806f
+R11 8 g4721_7 2.224404
+R12 g4721_2 8 2.224404
+C20 9 gnd 2.080806f
+R13 9 g4721_2 2.224404
+R14 g4721_6 9 2.224404
+C21 10 gnd 2.080806f
+R15 10 g4721_6 2.224404
+R16 g4721_3 10 2.224404
+C22 11 gnd 2.080806f
+R17 11 g4721_3 2.224404
+R18 g4721_8 11 2.224404
+R19 g4721_1 g4721_8 2.224404
+C23 12 gnd 2.080806f
+R20 12 g4721_4 2.224404
+C24 13 gnd 2.080806f
+R21 13 12 2.224404
+R22 g4721_9 13 2.224404
+C25 14 gnd 2.080806f
+R23 14 g4721_9 2.224404
+C26 15 gnd 2.080806f
+R24 15 14 2.224404
+R25 g4721_10 15 2.224404
+.ends
+
+.subckt netg79 g79_1 g79_0 gnd
+C1  g79_1 gnd 2.080806f
+C2  g79_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g79_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+R18 17 g79_1 2.224404
+.ends
+
+.subckt netg2055 g2055_2 g2055_4 g2055_3 g2055_6 g2055_5 g2055_0 gnd
+C1  g2055_2 gnd 2.080806f
+C2  g2055_4 gnd 2.080806f
+C3  g2055_3 gnd 2.080806f
+C4  g2055_6 gnd 2.080806f
+C5  g2055_5 gnd 2.080806f
+C6  g2055_0 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 g2055_0 1 2.224404
+C8 2 gnd 2.080806f
+R2 1 2 2.224404
+C9 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g2055_4 2.224404
+C10 4 gnd 2.080806f
+R5 4 g2055_4 2.224404
+R6 4 g2055_6 2.224404
+C11 5 gnd 2.080806f
+R7 g2055_6 5 2.224404
+C12 6 gnd 2.080806f
+R8 5 6 2.224404
+C13 7 gnd 2.080806f
+R9 6 7 2.224404
+R10 7 g2055_2 2.224404
+C14 8 gnd 2.080806f
+R11 g2055_4 8 2.224404
+C15 9 gnd 2.080806f
+R12 8 9 2.224404
+C16 10 gnd 2.080806f
+R13 9 10 2.224404
+C17 11 gnd 2.080806f
+R14 11 10 2.224404
+C18 12 gnd 2.080806f
+R15 11 12 2.224404
+R16 g2055_5 12 2.224404
+C19 13 gnd 2.080806f
+R17 13 g2055_2 2.224404
+C20 14 gnd 2.080806f
+R18 14 13 2.224404
+C21 15 gnd 2.080806f
+R19 15 14 2.224404
+C22 16 gnd 2.080806f
+R20 15 16 2.224404
+C23 17 gnd 2.080806f
+R21 16 17 2.224404
+R22 17 g2055_3 2.224404
+.ends
+
+.subckt netg7499 g7499_1 g7499_0 gnd
+C1  g7499_1 gnd 2.080806f
+C2  g7499_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7499_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+R18 17 g7499_1 2.224404
+.ends
+
+.subckt netg1395 g1395_1 g1395_0 gnd
+C1  g1395_1 gnd 2.080806f
+C2  g1395_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1395_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+R20 g1395_1 19 2.224404
+.ends
+
+.subckt netg1836 g1836_0 g1836_2 g1836_1 g1836_3 gnd
+C1  g1836_0 gnd 2.080806f
+C2  g1836_2 gnd 2.080806f
+C3  g1836_1 gnd 2.080806f
+C4  g1836_3 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g1836_0 1 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g1836_3 2.224404
+C7 3 gnd 2.080806f
+R4 3 g1836_0 2.224404
+C8 4 gnd 2.080806f
+R5 4 3 2.224404
+C9 5 gnd 2.080806f
+R6 5 4 2.224404
+C10 6 gnd 2.080806f
+R7 6 5 2.224404
+C11 7 gnd 2.080806f
+R8 7 6 2.224404
+C12 8 gnd 2.080806f
+R9 8 7 2.224404
+C13 9 gnd 2.080806f
+R10 9 8 2.224404
+C14 10 gnd 2.080806f
+R11 10 9 2.224404
+C15 11 gnd 2.080806f
+R12 11 10 2.224404
+C16 12 gnd 2.080806f
+R13 12 11 2.224404
+C17 13 gnd 2.080806f
+R14 13 12 2.224404
+C18 14 gnd 2.080806f
+R15 14 13 2.224404
+R16 g1836_2 14 2.224404
+C19 15 gnd 2.080806f
+R17 g1836_2 15 2.224404
+R18 g1836_1 15 2.224404
+.ends
+
+.subckt netg614 g614_3 g614_0 g614_4 g614_1 g614_5 g614_2 gnd
+C1  g614_3 gnd 2.080806f
+C2  g614_0 gnd 2.080806f
+C3  g614_4 gnd 2.080806f
+C4  g614_1 gnd 2.080806f
+C5  g614_5 gnd 2.080806f
+C6  g614_2 gnd 2.080806f
+R1 g614_0 g614_4 2.224404
+R2 g614_2 g614_4 2.224404
+R3 g614_4 g614_3 2.224404
+C7 1 gnd 2.080806f
+R4 g614_3 1 2.224404
+C8 2 gnd 2.080806f
+R5 1 2 2.224404
+C9 3 gnd 2.080806f
+R6 2 3 2.224404
+C10 4 gnd 2.080806f
+R7 3 4 2.224404
+C11 5 gnd 2.080806f
+R8 4 5 2.224404
+C12 6 gnd 2.080806f
+R9 5 6 2.224404
+C13 7 gnd 2.080806f
+R10 6 7 2.224404
+C14 8 gnd 2.080806f
+R11 7 8 2.224404
+C15 9 gnd 2.080806f
+R12 8 9 2.224404
+C16 10 gnd 2.080806f
+R13 9 10 2.224404
+C17 11 gnd 2.080806f
+R14 10 11 2.224404
+R15 11 g614_5 2.224404
+C18 12 gnd 2.080806f
+R16 12 g614_5 2.224404
+C19 13 gnd 2.080806f
+R17 13 12 2.224404
+C20 14 gnd 2.080806f
+R18 14 13 2.224404
+C21 15 gnd 2.080806f
+R19 15 14 2.224404
+R20 g614_1 15 2.224404
+.ends
+
+.subckt netg1786 g1786_5 g1786_2 g1786_4 g1786_3 g1786_0 g1786_1 gnd
+C1  g1786_5 gnd 2.080806f
+C2  g1786_2 gnd 2.080806f
+C3  g1786_4 gnd 2.080806f
+C4  g1786_3 gnd 2.080806f
+C5  g1786_0 gnd 2.080806f
+C6  g1786_1 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g1786_0 2.224404
+R2 g1786_4 1 2.224404
+R3 g1786_2 g1786_4 2.224404
+C8 2 gnd 2.080806f
+R4 g1786_0 2 2.224404
+C9 3 gnd 2.080806f
+R5 2 3 2.224404
+C10 4 gnd 2.080806f
+R6 3 4 2.224404
+C11 5 gnd 2.080806f
+R7 4 5 2.224404
+C12 6 gnd 2.080806f
+R8 5 6 2.224404
+C13 7 gnd 2.080806f
+R9 6 7 2.224404
+R10 7 g1786_3 2.224404
+C14 8 gnd 2.080806f
+R11 g1786_4 8 2.224404
+C15 9 gnd 2.080806f
+R12 8 9 2.224404
+C16 10 gnd 2.080806f
+R13 9 10 2.224404
+C17 11 gnd 2.080806f
+R14 10 11 2.224404
+C18 12 gnd 2.080806f
+R15 11 12 2.224404
+C19 13 gnd 2.080806f
+R16 12 13 2.224404
+C20 14 gnd 2.080806f
+R17 13 14 2.224404
+R18 14 g1786_1 2.224404
+C21 15 gnd 2.080806f
+R19 15 g1786_1 2.224404
+C22 16 gnd 2.080806f
+R20 16 15 2.224404
+R21 g1786_5 16 2.224404
+.ends
+
+.subckt netg5847 g5847_1 g5847_0 gnd
+C1  g5847_1 gnd 2.080806f
+C2  g5847_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5847_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+R19 g5847_1 18 2.224404
+.ends
+
+.subckt netg5170 g5170_1 g5170_3 g5170_0 g5170_2 gnd
+C1  g5170_1 gnd 2.080806f
+C2  g5170_3 gnd 2.080806f
+C3  g5170_0 gnd 2.080806f
+C4  g5170_2 gnd 2.080806f
+R1 g5170_1 g5170_0 2.224404
+C5 1 gnd 2.080806f
+R2 1 g5170_1 2.224404
+C6 2 gnd 2.080806f
+R3 1 2 2.224404
+C7 3 gnd 2.080806f
+R4 2 3 2.224404
+C8 4 gnd 2.080806f
+R5 4 3 2.224404
+C9 5 gnd 2.080806f
+R6 4 5 2.224404
+R7 g5170_3 5 2.224404
+C10 6 gnd 2.080806f
+R8 g5170_0 6 2.224404
+C11 7 gnd 2.080806f
+R9 6 7 2.224404
+C12 8 gnd 2.080806f
+R10 7 8 2.224404
+C13 9 gnd 2.080806f
+R11 8 9 2.224404
+C14 10 gnd 2.080806f
+R12 9 10 2.224404
+C15 11 gnd 2.080806f
+R13 10 11 2.224404
+C16 12 gnd 2.080806f
+R14 11 12 2.224404
+C17 13 gnd 2.080806f
+R15 12 13 2.224404
+C18 14 gnd 2.080806f
+R16 13 14 2.224404
+C19 15 gnd 2.080806f
+R17 14 15 2.224404
+C20 16 gnd 2.080806f
+R18 15 16 2.224404
+C21 17 gnd 2.080806f
+R19 16 17 2.224404
+C22 18 gnd 2.080806f
+R20 17 18 2.224404
+C23 19 gnd 2.080806f
+R21 18 19 2.224404
+R22 19 g5170_2 2.224404
+.ends
+
+.subckt netg6071 g6071_1 g6071_0 gnd
+C1  g6071_1 gnd 2.080806f
+C2  g6071_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6071_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+R19 g6071_1 18 2.224404
+.ends
+
+.subckt netg5287 g5287_1 g5287_6 g5287_5 g5287_0 g5287_4 g5287_3 g5287_2 gnd
+C1  g5287_1 gnd 2.080806f
+C2  g5287_6 gnd 2.080806f
+C3  g5287_5 gnd 2.080806f
+C4  g5287_0 gnd 2.080806f
+C5  g5287_4 gnd 2.080806f
+C6  g5287_3 gnd 2.080806f
+C7  g5287_2 gnd 2.080806f
+R1 g5287_0 g5287_1 2.224404
+R2 g5287_2 g5287_0 2.224404
+R3 g5287_1 g5287_4 2.224404
+R4 g5287_2 g5287_5 2.224404
+R5 g5287_6 g5287_4 2.224404
+C8 1 gnd 2.080806f
+R6 1 g5287_6 2.224404
+C9 2 gnd 2.080806f
+R7 2 1 2.224404
+C10 3 gnd 2.080806f
+R8 3 2 2.224404
+C11 4 gnd 2.080806f
+R9 4 3 2.224404
+C12 5 gnd 2.080806f
+R10 5 4 2.224404
+C13 6 gnd 2.080806f
+R11 6 5 2.224404
+C14 7 gnd 2.080806f
+R12 7 6 2.224404
+C15 8 gnd 2.080806f
+R13 8 7 2.224404
+C16 9 gnd 2.080806f
+R14 9 8 2.224404
+C17 10 gnd 2.080806f
+R15 10 9 2.224404
+C18 11 gnd 2.080806f
+R16 11 10 2.224404
+C19 12 gnd 2.080806f
+R17 12 11 2.224404
+C20 13 gnd 2.080806f
+R18 13 12 2.224404
+C21 14 gnd 2.080806f
+R19 14 13 2.224404
+C22 15 gnd 2.080806f
+R20 14 15 2.224404
+R21 15 g5287_3 2.224404
+.ends
+
+.subckt netg3516 g3516_1 g3516_0 gnd
+C1  g3516_1 gnd 2.080806f
+C2  g3516_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3516_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+R21 g3516_1 20 2.224404
+.ends
+
+.subckt netg6583 g6583_1 g6583_0 gnd
+C1  g6583_1 gnd 2.080806f
+C2  g6583_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6583_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+R19 g6583_1 18 2.224404
+.ends
+
+.subckt netg1727 g1727_1 g1727_2 g1727_0 g1727_3 gnd
+C1  g1727_1 gnd 2.080806f
+C2  g1727_2 gnd 2.080806f
+C3  g1727_0 gnd 2.080806f
+C4  g1727_3 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g1727_0 2.224404
+R2 1 g1727_1 2.224404
+C6 2 gnd 2.080806f
+R3 g1727_1 2 2.224404
+C7 3 gnd 2.080806f
+R4 2 3 2.224404
+C8 4 gnd 2.080806f
+R5 3 4 2.224404
+C9 5 gnd 2.080806f
+R6 4 5 2.224404
+C10 6 gnd 2.080806f
+R7 5 6 2.224404
+C11 7 gnd 2.080806f
+R8 6 7 2.224404
+C12 8 gnd 2.080806f
+R9 8 7 2.224404
+C13 9 gnd 2.080806f
+R10 8 9 2.224404
+C14 10 gnd 2.080806f
+R11 9 10 2.224404
+C15 11 gnd 2.080806f
+R12 10 11 2.224404
+R13 11 g1727_3 2.224404
+C16 12 gnd 2.080806f
+R14 g1727_3 12 2.224404
+C17 13 gnd 2.080806f
+R15 12 13 2.224404
+C18 14 gnd 2.080806f
+R16 13 14 2.224404
+C19 15 gnd 2.080806f
+R17 14 15 2.224404
+C20 16 gnd 2.080806f
+R18 15 16 2.224404
+C21 17 gnd 2.080806f
+R19 16 17 2.224404
+R20 17 g1727_2 2.224404
+.ends
+
+.subckt netg1596 g1596_1 g1596_2 g1596_0 g1596_3 gnd
+C1  g1596_1 gnd 2.080806f
+C2  g1596_2 gnd 2.080806f
+C3  g1596_0 gnd 2.080806f
+C4  g1596_3 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g1596_0 1 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+C7 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g1596_1 2.224404
+C8 4 gnd 2.080806f
+R5 g1596_1 4 2.224404
+C9 5 gnd 2.080806f
+R6 4 5 2.224404
+C10 6 gnd 2.080806f
+R7 5 6 2.224404
+C11 7 gnd 2.080806f
+R8 6 7 2.224404
+C12 8 gnd 2.080806f
+R9 7 8 2.224404
+C13 9 gnd 2.080806f
+R10 8 9 2.224404
+C14 10 gnd 2.080806f
+R11 9 10 2.224404
+C15 11 gnd 2.080806f
+R12 10 11 2.224404
+C16 12 gnd 2.080806f
+R13 12 11 2.224404
+C17 13 gnd 2.080806f
+R14 12 13 2.224404
+R15 13 g1596_2 2.224404
+C18 14 gnd 2.080806f
+R16 g1596_2 14 2.224404
+C19 15 gnd 2.080806f
+R17 14 15 2.224404
+C20 16 gnd 2.080806f
+R18 15 16 2.224404
+C21 17 gnd 2.080806f
+R19 16 17 2.224404
+C22 18 gnd 2.080806f
+R20 17 18 2.224404
+C23 19 gnd 2.080806f
+R21 18 19 2.224404
+R22 g1596_3 19 2.224404
+.ends
+
+.subckt netg124 g124_1 g124_0 gnd
+C1  g124_1 gnd 2.080806f
+C2  g124_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g124_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+R19 18 g124_1 2.224404
+.ends
+
+.subckt netg3768 g3768_1 g3768_8 g3768_3 g3768_0 g3768_13 g3768_2 g3768_10 g3768_12 g3768_11 g3768_6 g3768_7 g3768_9 g3768_5 g3768_4 g3768_15 g3768_14 gnd
+C1  g3768_1 gnd 2.080806f
+C2  g3768_8 gnd 2.080806f
+C3  g3768_3 gnd 2.080806f
+C4  g3768_0 gnd 2.080806f
+C5  g3768_13 gnd 2.080806f
+C6  g3768_2 gnd 2.080806f
+C7  g3768_10 gnd 2.080806f
+C8  g3768_12 gnd 2.080806f
+C9  g3768_11 gnd 2.080806f
+C10  g3768_6 gnd 2.080806f
+C11  g3768_7 gnd 2.080806f
+C12  g3768_9 gnd 2.080806f
+C13  g3768_5 gnd 2.080806f
+C14  g3768_4 gnd 2.080806f
+C15  g3768_15 gnd 2.080806f
+C16  g3768_14 gnd 2.080806f
+C17 1 gnd 2.080806f
+R1 g3768_0 1 2.224404
+R2 g3768_12 1 2.224404
+C18 2 gnd 2.080806f
+R3 1 2 2.224404
+R4 2 g3768_4 2.224404
+R5 g3768_4 g3768_14 2.224404
+C19 3 gnd 2.080806f
+R6 3 g3768_0 2.224404
+C20 4 gnd 2.080806f
+R7 3 4 2.224404
+R8 4 g3768_6 2.224404
+R9 g3768_6 g3768_13 2.224404
+R10 g3768_13 g3768_15 2.224404
+C21 5 gnd 2.080806f
+R11 g3768_13 5 2.224404
+R12 5 g3768_1 2.224404
+R13 g3768_7 g3768_1 2.224404
+R14 g3768_1 g3768_8 2.224404
+R15 g3768_8 g3768_2 2.224404
+C22 6 gnd 2.080806f
+R16 6 g3768_6 2.224404
+C23 7 gnd 2.080806f
+R17 7 6 2.224404
+R18 g3768_5 7 2.224404
+C24 8 gnd 2.080806f
+R19 8 7 2.224404
+C25 9 gnd 2.080806f
+R20 9 8 2.224404
+C26 10 gnd 2.080806f
+R21 10 9 2.224404
+R22 g3768_9 10 2.224404
+C27 11 gnd 2.080806f
+R23 11 g3768_4 2.224404
+C28 12 gnd 2.080806f
+R24 12 11 2.224404
+C29 13 gnd 2.080806f
+R25 13 12 2.224404
+C30 14 gnd 2.080806f
+R26 14 13 2.224404
+C31 15 gnd 2.080806f
+R27 15 14 2.224404
+R28 g3768_10 15 2.224404
+C32 16 gnd 2.080806f
+R29 16 g3768_10 2.224404
+C33 17 gnd 2.080806f
+R30 17 16 2.224404
+R31 g3768_3 17 2.224404
+C34 18 gnd 2.080806f
+R32 18 g3768_3 2.224404
+R33 g3768_11 18 2.224404
+.ends
+
+.subckt netg1687 g1687_1 g1687_0 g1687_2 g1687_3 gnd
+C1  g1687_1 gnd 2.080806f
+C2  g1687_0 gnd 2.080806f
+C3  g1687_2 gnd 2.080806f
+C4  g1687_3 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g1687_0 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+C7 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 3 g1687_3 2.224404
+C8 4 gnd 2.080806f
+R5 4 3 2.224404
+R6 g1687_2 4 2.224404
+C9 5 gnd 2.080806f
+R7 g1687_0 5 2.224404
+C10 6 gnd 2.080806f
+R8 5 6 2.224404
+C11 7 gnd 2.080806f
+R9 6 7 2.224404
+C12 8 gnd 2.080806f
+R10 7 8 2.224404
+C13 9 gnd 2.080806f
+R11 8 9 2.224404
+C14 10 gnd 2.080806f
+R12 9 10 2.224404
+C15 11 gnd 2.080806f
+R13 10 11 2.224404
+C16 12 gnd 2.080806f
+R14 11 12 2.224404
+C17 13 gnd 2.080806f
+R15 12 13 2.224404
+C18 14 gnd 2.080806f
+R16 13 14 2.224404
+C19 15 gnd 2.080806f
+R17 14 15 2.224404
+C20 16 gnd 2.080806f
+R18 15 16 2.224404
+C21 17 gnd 2.080806f
+R19 16 17 2.224404
+R20 17 g1687_1 2.224404
+.ends
+
+.subckt netg3873 g3873_8 g3873_3 g3873_9 g3873_0 g3873_6 g3873_1 g3873_7 g3873_5 g3873_2 g3873_4 gnd
+C1  g3873_8 gnd 2.080806f
+C2  g3873_3 gnd 2.080806f
+C3  g3873_9 gnd 2.080806f
+C4  g3873_0 gnd 2.080806f
+C5  g3873_6 gnd 2.080806f
+C6  g3873_1 gnd 2.080806f
+C7  g3873_7 gnd 2.080806f
+C8  g3873_5 gnd 2.080806f
+C9  g3873_2 gnd 2.080806f
+C10  g3873_4 gnd 2.080806f
+R1 g3873_2 g3873_0 2.224404
+R2 g3873_6 g3873_2 2.224404
+C11 1 gnd 2.080806f
+R3 1 g3873_6 2.224404
+R4 g3873_9 1 2.224404
+R5 g3873_7 g3873_9 2.224404
+R6 g3873_5 g3873_7 2.224404
+C12 2 gnd 2.080806f
+R7 g3873_5 2 2.224404
+C13 3 gnd 2.080806f
+R8 2 3 2.224404
+R9 g3873_4 3 2.224404
+C14 4 gnd 2.080806f
+R10 g3873_0 4 2.224404
+C15 5 gnd 2.080806f
+R11 4 5 2.224404
+C16 6 gnd 2.080806f
+R12 5 6 2.224404
+C17 7 gnd 2.080806f
+R13 6 7 2.224404
+C18 8 gnd 2.080806f
+R14 7 8 2.224404
+R15 8 g3873_8 2.224404
+C19 9 gnd 2.080806f
+R16 g3873_0 9 2.224404
+C20 10 gnd 2.080806f
+R17 9 10 2.224404
+C21 11 gnd 2.080806f
+R18 10 11 2.224404
+C22 12 gnd 2.080806f
+R19 11 12 2.224404
+C23 13 gnd 2.080806f
+R20 12 13 2.224404
+R21 13 g3873_1 2.224404
+C24 14 gnd 2.080806f
+R22 14 g3873_1 2.224404
+C25 15 gnd 2.080806f
+R23 14 15 2.224404
+R24 15 g3873_3 2.224404
+.ends
+
+.subckt netg4791 g4791_2 g4791_3 g4791_7 g4791_9 g4791_5 g4791_10 g4791_8 g4791_0 g4791_1 g4791_4 g4791_6 gnd
+C1  g4791_2 gnd 2.080806f
+C2  g4791_3 gnd 2.080806f
+C3  g4791_7 gnd 2.080806f
+C4  g4791_9 gnd 2.080806f
+C5  g4791_5 gnd 2.080806f
+C6  g4791_10 gnd 2.080806f
+C7  g4791_8 gnd 2.080806f
+C8  g4791_0 gnd 2.080806f
+C9  g4791_1 gnd 2.080806f
+C10  g4791_4 gnd 2.080806f
+C11  g4791_6 gnd 2.080806f
+C12 1 gnd 2.080806f
+R1 g4791_0 1 2.224404
+R2 1 g4791_2 2.224404
+C13 2 gnd 2.080806f
+R3 2 g4791_0 2.224404
+R4 g4791_10 2 2.224404
+C14 3 gnd 2.080806f
+R5 g4791_2 3 2.224404
+R6 3 g4791_3 2.224404
+R7 g4791_3 g4791_1 2.224404
+R8 g4791_1 g4791_6 2.224404
+R9 g4791_6 g4791_9 2.224404
+C15 4 gnd 2.080806f
+R10 g4791_10 4 2.224404
+R11 4 g4791_8 2.224404
+C16 5 gnd 2.080806f
+R12 g4791_9 5 2.224404
+R13 5 g4791_5 2.224404
+C17 6 gnd 2.080806f
+R14 6 g4791_2 2.224404
+C18 7 gnd 2.080806f
+R15 7 6 2.224404
+C19 8 gnd 2.080806f
+R16 8 7 2.224404
+C20 9 gnd 2.080806f
+R17 9 8 2.224404
+R18 9 g4791_4 2.224404
+C21 10 gnd 2.080806f
+R19 10 g4791_4 2.224404
+C22 11 gnd 2.080806f
+R20 10 11 2.224404
+C23 12 gnd 2.080806f
+R21 11 12 2.224404
+C24 13 gnd 2.080806f
+R22 13 12 2.224404
+C25 14 gnd 2.080806f
+R23 13 14 2.224404
+C26 15 gnd 2.080806f
+R24 14 15 2.224404
+R25 15 g4791_7 2.224404
+.ends
+
+.subckt netg2123 g2123_1 g2123_3 g2123_2 g2123_0 gnd
+C1  g2123_1 gnd 2.080806f
+C2  g2123_3 gnd 2.080806f
+C3  g2123_2 gnd 2.080806f
+C4  g2123_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g2123_0 1 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g2123_3 2 2.224404
+C7 3 gnd 2.080806f
+R4 3 1 2.224404
+C8 4 gnd 2.080806f
+R5 4 3 2.224404
+C9 5 gnd 2.080806f
+R6 5 4 2.224404
+C10 6 gnd 2.080806f
+R7 6 5 2.224404
+C11 7 gnd 2.080806f
+R8 7 6 2.224404
+C12 8 gnd 2.080806f
+R9 8 7 2.224404
+C13 9 gnd 2.080806f
+R10 9 8 2.224404
+C14 10 gnd 2.080806f
+R11 10 9 2.224404
+C15 11 gnd 2.080806f
+R12 11 10 2.224404
+C16 12 gnd 2.080806f
+R13 12 11 2.224404
+C17 13 gnd 2.080806f
+R14 13 12 2.224404
+C18 14 gnd 2.080806f
+R15 14 13 2.224404
+C19 15 gnd 2.080806f
+R16 15 14 2.224404
+C20 16 gnd 2.080806f
+R17 16 15 2.224404
+R18 g2123_2 16 2.224404
+C21 17 gnd 2.080806f
+R19 17 g2123_2 2.224404
+C22 18 gnd 2.080806f
+R20 18 17 2.224404
+R21 g2123_1 18 2.224404
+.ends
+
+.subckt netg4850 g4850_9 g4850_1 g4850_4 g4850_8 g4850_6 g4850_3 g4850_10 g4850_2 g4850_12 g4850_7 g4850_11 g4850_5 gnd
+C1  g4850_9 gnd 2.080806f
+C2  g4850_1 gnd 2.080806f
+C3  g4850_4 gnd 2.080806f
+C4  g4850_8 gnd 2.080806f
+C5  g4850_6 gnd 2.080806f
+C6  g4850_3 gnd 2.080806f
+C7  g4850_10 gnd 2.080806f
+C8  g4850_2 gnd 2.080806f
+C9  g4850_12 gnd 2.080806f
+C10  g4850_7 gnd 2.080806f
+C11  g4850_11 gnd 2.080806f
+C12  g4850_5 gnd 2.080806f
+R1 g4850_11 g4850_7 2.224404
+R2 g4850_7 g4850_2 2.224404
+C13 1 gnd 2.080806f
+R3 g4850_7 1 2.224404
+R4 1 g4850_12 2.224404
+C14 2 gnd 2.080806f
+R5 g4850_2 2 2.224404
+C15 3 gnd 2.080806f
+R6 2 3 2.224404
+C16 4 gnd 2.080806f
+R7 3 4 2.224404
+C17 5 gnd 2.080806f
+R8 4 5 2.224404
+C18 6 gnd 2.080806f
+R9 5 6 2.224404
+R10 6 g4850_5 2.224404
+C19 7 gnd 2.080806f
+R11 7 g4850_5 2.224404
+C20 8 gnd 2.080806f
+R12 8 7 2.224404
+R13 8 g4850_9 2.224404
+C21 9 gnd 2.080806f
+R14 9 g4850_9 2.224404
+C22 10 gnd 2.080806f
+R15 10 9 2.224404
+R16 g4850_8 10 2.224404
+R17 g4850_8 g4850_1 2.224404
+C23 11 gnd 2.080806f
+R18 11 g4850_8 2.224404
+R19 g4850_3 11 2.224404
+R20 g4850_4 g4850_3 2.224404
+C24 12 gnd 2.080806f
+R21 12 g4850_8 2.224404
+C25 13 gnd 2.080806f
+R22 13 12 2.224404
+R23 g4850_6 13 2.224404
+C26 14 gnd 2.080806f
+R24 14 g4850_4 2.224404
+C27 15 gnd 2.080806f
+R25 15 14 2.224404
+R26 g4850_10 15 2.224404
+.ends
+
+.subckt netg3617 g3617_12 g3617_3 g3617_9 g3617_7 g3617_5 g3617_2 g3617_8 g3617_1 g3617_4 g3617_10 g3617_0 g3617_6 g3617_11 gnd
+C1  g3617_12 gnd 2.080806f
+C2  g3617_3 gnd 2.080806f
+C3  g3617_9 gnd 2.080806f
+C4  g3617_7 gnd 2.080806f
+C5  g3617_5 gnd 2.080806f
+C6  g3617_2 gnd 2.080806f
+C7  g3617_8 gnd 2.080806f
+C8  g3617_1 gnd 2.080806f
+C9  g3617_4 gnd 2.080806f
+C10  g3617_10 gnd 2.080806f
+C11  g3617_0 gnd 2.080806f
+C12  g3617_6 gnd 2.080806f
+C13  g3617_11 gnd 2.080806f
+C14 1 gnd 2.080806f
+R1 1 g3617_0 2.224404
+R2 g3617_6 1 2.224404
+C15 2 gnd 2.080806f
+R3 g3617_0 2 2.224404
+R4 2 g3617_12 2.224404
+C16 3 gnd 2.080806f
+R5 g3617_12 3 2.224404
+R6 3 g3617_5 2.224404
+C17 4 gnd 2.080806f
+R7 4 1 2.224404
+C18 5 gnd 2.080806f
+R8 5 4 2.224404
+R9 g3617_3 5 2.224404
+C19 6 gnd 2.080806f
+R10 g3617_3 6 2.224404
+R11 6 g3617_10 2.224404
+R12 g3617_1 g3617_10 2.224404
+R13 g3617_10 g3617_4 2.224404
+C20 7 gnd 2.080806f
+R14 7 g3617_3 2.224404
+C21 8 gnd 2.080806f
+R15 8 7 2.224404
+C22 9 gnd 2.080806f
+R16 9 8 2.224404
+C23 10 gnd 2.080806f
+R17 10 9 2.224404
+R18 g3617_9 10 2.224404
+C24 11 gnd 2.080806f
+R19 g3617_9 11 2.224404
+C25 12 gnd 2.080806f
+R20 12 11 2.224404
+C26 13 gnd 2.080806f
+R21 12 13 2.224404
+R22 g3617_8 13 2.224404
+C27 14 gnd 2.080806f
+R23 g3617_8 14 2.224404
+C28 15 gnd 2.080806f
+R24 14 15 2.224404
+C29 16 gnd 2.080806f
+R25 15 16 2.224404
+C30 17 gnd 2.080806f
+R26 16 17 2.224404
+R27 17 g3617_11 2.224404
+C31 18 gnd 2.080806f
+R28 18 g3617_11 2.224404
+C32 19 gnd 2.080806f
+R29 19 18 2.224404
+R30 g3617_2 19 2.224404
+R31 g3617_7 19 2.224404
+.ends
+
+.subckt netg2326 g2326_1 g2326_0 g2326_3 g2326_2 gnd
+C1  g2326_1 gnd 2.080806f
+C2  g2326_0 gnd 2.080806f
+C3  g2326_3 gnd 2.080806f
+C4  g2326_2 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g2326_0 1 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+C7 3 gnd 2.080806f
+R3 2 3 2.224404
+C8 4 gnd 2.080806f
+R4 3 4 2.224404
+C9 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 5 g2326_1 2.224404
+C10 6 gnd 2.080806f
+R7 g2326_1 6 2.224404
+R8 6 g2326_2 2.224404
+C11 7 gnd 2.080806f
+R9 7 1 2.224404
+C12 8 gnd 2.080806f
+R10 8 7 2.224404
+C13 9 gnd 2.080806f
+R11 9 8 2.224404
+C14 10 gnd 2.080806f
+R12 10 9 2.224404
+C15 11 gnd 2.080806f
+R13 11 10 2.224404
+C16 12 gnd 2.080806f
+R14 12 11 2.224404
+C17 13 gnd 2.080806f
+R15 13 12 2.224404
+C18 14 gnd 2.080806f
+R16 14 13 2.224404
+C19 15 gnd 2.080806f
+R17 15 14 2.224404
+C20 16 gnd 2.080806f
+R18 16 15 2.224404
+C21 17 gnd 2.080806f
+R19 16 17 2.224404
+R20 g2326_3 17 2.224404
+.ends
+
+.subckt netg2330 g2330_3 g2330_1 g2330_0 gnd
+C1  g2330_3 gnd 2.080806f
+C2  g2330_1 gnd 2.080806f
+C3  g2330_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g2330_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g2330_3 2 2.224404
+C6 3 gnd 2.080806f
+R4 3 g2330_0 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 11 10 2.224404
+C15 12 gnd 2.080806f
+R13 12 11 2.224404
+C16 13 gnd 2.080806f
+R14 13 12 2.224404
+C17 14 gnd 2.080806f
+R15 14 13 2.224404
+C18 15 gnd 2.080806f
+R16 15 14 2.224404
+C19 16 gnd 2.080806f
+R17 16 15 2.224404
+C20 17 gnd 2.080806f
+R18 17 16 2.224404
+C21 18 gnd 2.080806f
+R19 18 17 2.224404
+R20 g2330_1 18 2.224404
+.ends
+
+.subckt netg1098 g1098_1 g1098_0 gnd
+C1  g1098_1 gnd 2.080806f
+C2  g1098_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1098_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+R23 g1098_1 22 2.224404
+.ends
+
+.subckt netg7257 g7257_0 g7257_1 g7257_2 gnd
+C1  g7257_0 gnd 2.080806f
+C2  g7257_1 gnd 2.080806f
+C3  g7257_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g7257_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g7257_1 2 2.224404
+C6 3 gnd 2.080806f
+R4 3 g7257_1 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 11 10 2.224404
+C15 12 gnd 2.080806f
+R13 12 11 2.224404
+C16 13 gnd 2.080806f
+R14 13 12 2.224404
+C17 14 gnd 2.080806f
+R15 14 13 2.224404
+C18 15 gnd 2.080806f
+R16 15 14 2.224404
+C19 16 gnd 2.080806f
+R17 16 15 2.224404
+C20 17 gnd 2.080806f
+R18 17 16 2.224404
+R19 g7257_2 17 2.224404
+.ends
+
+.subckt netg134 g134_1 g134_0 gnd
+C1  g134_1 gnd 2.080806f
+C2  g134_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g134_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+R19 18 g134_1 2.224404
+.ends
+
+.subckt netg128 g128_1 g128_0 gnd
+C1  g128_1 gnd 2.080806f
+C2  g128_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g128_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+R20 19 g128_1 2.224404
+.ends
+
+.subckt netg1474 g1474_1 g1474_0 gnd
+C1  g1474_1 gnd 2.080806f
+C2  g1474_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1474_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+R20 g1474_1 19 2.224404
+.ends
+
+.subckt netg4869 g4869_1 g4869_6 g4869_5 g4869_2 g4869_0 g4869_4 g4869_3 gnd
+C1  g4869_1 gnd 2.080806f
+C2  g4869_6 gnd 2.080806f
+C3  g4869_5 gnd 2.080806f
+C4  g4869_2 gnd 2.080806f
+C5  g4869_0 gnd 2.080806f
+C6  g4869_4 gnd 2.080806f
+C7  g4869_3 gnd 2.080806f
+C8 1 gnd 2.080806f
+R1 g4869_0 1 2.224404
+C9 2 gnd 2.080806f
+R2 1 2 2.224404
+C10 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g4869_6 2.224404
+C11 4 gnd 2.080806f
+R5 1 4 2.224404
+C12 5 gnd 2.080806f
+R6 4 5 2.224404
+C13 6 gnd 2.080806f
+R7 5 6 2.224404
+R8 6 g4869_1 2.224404
+C14 7 gnd 2.080806f
+R9 g4869_1 7 2.224404
+C15 8 gnd 2.080806f
+R10 7 8 2.224404
+C16 9 gnd 2.080806f
+R11 8 9 2.224404
+R12 9 g4869_4 2.224404
+C17 10 gnd 2.080806f
+R13 10 g4869_1 2.224404
+C18 11 gnd 2.080806f
+R14 11 10 2.224404
+C19 12 gnd 2.080806f
+R15 11 12 2.224404
+C20 13 gnd 2.080806f
+R16 12 13 2.224404
+C21 14 gnd 2.080806f
+R17 14 13 2.224404
+C22 15 gnd 2.080806f
+R18 14 15 2.224404
+R19 g4869_2 15 2.224404
+C23 16 gnd 2.080806f
+R20 16 g4869_2 2.224404
+R21 g4869_3 16 2.224404
+C24 17 gnd 2.080806f
+R22 g4869_2 17 2.224404
+C25 18 gnd 2.080806f
+R23 17 18 2.224404
+C26 19 gnd 2.080806f
+R24 18 19 2.224404
+C27 20 gnd 2.080806f
+R25 19 20 2.224404
+R26 20 g4869_5 2.224404
+.ends
+
+.subckt netg7521 g7521_1 g7521_0 gnd
+C1  g7521_1 gnd 2.080806f
+C2  g7521_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7521_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+R20 g7521_1 19 2.224404
+.ends
+
+.subckt netg727 g727_4 g727_5 g727_6 g727_1 g727_3 gnd
+C1  g727_4 gnd 2.080806f
+C2  g727_5 gnd 2.080806f
+C3  g727_6 gnd 2.080806f
+C4  g727_1 gnd 2.080806f
+C5  g727_3 gnd 2.080806f
+R1 g727_1 g727_4 2.224404
+R2 g727_3 g727_4 2.224404
+C6 1 gnd 2.080806f
+R3 1 g727_1 2.224404
+R4 g727_5 1 2.224404
+C7 2 gnd 2.080806f
+R5 2 g727_5 2.224404
+C8 3 gnd 2.080806f
+R6 3 2 2.224404
+C9 4 gnd 2.080806f
+R7 4 3 2.224404
+C10 5 gnd 2.080806f
+R8 5 4 2.224404
+C11 6 gnd 2.080806f
+R9 6 5 2.224404
+C12 7 gnd 2.080806f
+R10 7 6 2.224404
+C13 8 gnd 2.080806f
+R11 8 7 2.224404
+C14 9 gnd 2.080806f
+R12 9 8 2.224404
+C15 10 gnd 2.080806f
+R13 10 9 2.224404
+C16 11 gnd 2.080806f
+R14 11 10 2.224404
+C17 12 gnd 2.080806f
+R15 12 11 2.224404
+C18 13 gnd 2.080806f
+R16 13 12 2.224404
+C19 14 gnd 2.080806f
+R17 14 13 2.224404
+C20 15 gnd 2.080806f
+R18 15 14 2.224404
+C21 16 gnd 2.080806f
+R19 16 15 2.224404
+C22 17 gnd 2.080806f
+R20 17 16 2.224404
+R21 g727_6 17 2.224404
+.ends
+
+.subckt netg2531 g2531_2 g2531_0 gnd
+C1  g2531_2 gnd 2.080806f
+C2  g2531_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2531_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+R22 g2531_2 21 2.224404
+.ends
+
+.subckt netg2342 g2342_3 g2342_1 g2342_0 gnd
+C1  g2342_3 gnd 2.080806f
+C2  g2342_1 gnd 2.080806f
+C3  g2342_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g2342_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+C8 5 gnd 2.080806f
+R5 4 5 2.224404
+C9 6 gnd 2.080806f
+R6 5 6 2.224404
+C10 7 gnd 2.080806f
+R7 6 7 2.224404
+C11 8 gnd 2.080806f
+R8 8 7 2.224404
+C12 9 gnd 2.080806f
+R9 8 9 2.224404
+C13 10 gnd 2.080806f
+R10 9 10 2.224404
+C14 11 gnd 2.080806f
+R11 10 11 2.224404
+R12 11 g2342_1 2.224404
+C15 12 gnd 2.080806f
+R13 g2342_1 12 2.224404
+C16 13 gnd 2.080806f
+R14 12 13 2.224404
+C17 14 gnd 2.080806f
+R15 13 14 2.224404
+C18 15 gnd 2.080806f
+R16 14 15 2.224404
+C19 16 gnd 2.080806f
+R17 15 16 2.224404
+C20 17 gnd 2.080806f
+R18 16 17 2.224404
+C21 18 gnd 2.080806f
+R19 17 18 2.224404
+R20 18 g2342_3 2.224404
+.ends
+
+.subckt netg7501 g7501_1 g7501_0 gnd
+C1  g7501_1 gnd 2.080806f
+C2  g7501_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7501_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+R20 g7501_1 19 2.224404
+.ends
+
+.subckt netg7445 g7445_1 g7445_0 gnd
+C1  g7445_1 gnd 2.080806f
+C2  g7445_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7445_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+R20 g7445_1 19 2.224404
+.ends
+
+.subckt netg3803 g3803_3 g3803_0 g3803_6 g3803_4 g3803_2 g3803_1 gnd
+C1  g3803_3 gnd 2.080806f
+C2  g3803_0 gnd 2.080806f
+C3  g3803_6 gnd 2.080806f
+C4  g3803_4 gnd 2.080806f
+C5  g3803_2 gnd 2.080806f
+C6  g3803_1 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 g3803_0 1 2.224404
+C8 2 gnd 2.080806f
+R2 1 2 2.224404
+C9 3 gnd 2.080806f
+R3 2 3 2.224404
+C10 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 4 g3803_6 2.224404
+C11 5 gnd 2.080806f
+R6 g3803_0 5 2.224404
+C12 6 gnd 2.080806f
+R7 6 5 2.224404
+C13 7 gnd 2.080806f
+R8 7 6 2.224404
+C14 8 gnd 2.080806f
+R9 8 7 2.224404
+C15 9 gnd 2.080806f
+R10 9 8 2.224404
+C16 10 gnd 2.080806f
+R11 9 10 2.224404
+R12 g3803_1 10 2.224404
+C17 11 gnd 2.080806f
+R13 11 g3803_1 2.224404
+R14 g3803_2 11 2.224404
+C18 12 gnd 2.080806f
+R15 12 g3803_2 2.224404
+C19 13 gnd 2.080806f
+R16 13 12 2.224404
+C20 14 gnd 2.080806f
+R17 14 13 2.224404
+C21 15 gnd 2.080806f
+R18 15 14 2.224404
+C22 16 gnd 2.080806f
+R19 16 15 2.224404
+C23 17 gnd 2.080806f
+R20 16 17 2.224404
+R21 g3803_3 17 2.224404
+C24 18 gnd 2.080806f
+R22 18 g3803_3 2.224404
+R23 g3803_4 18 2.224404
+.ends
+
+.subckt netg6371 g6371_1 g6371_0 gnd
+C1  g6371_1 gnd 2.080806f
+C2  g6371_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6371_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+R20 g6371_1 19 2.224404
+.ends
+
+.subckt netg7500 g7500_1 g7500_0 gnd
+C1  g7500_1 gnd 2.080806f
+C2  g7500_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7500_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+R20 19 g7500_1 2.224404
+.ends
+
+.subckt netg69 g69_0 g69_2 g69_1 gnd
+C1  g69_0 gnd 2.080806f
+C2  g69_2 gnd 2.080806f
+C3  g69_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g69_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 5 6 2.224404
+C10 7 gnd 2.080806f
+R7 6 7 2.224404
+C11 8 gnd 2.080806f
+R8 7 8 2.224404
+C12 9 gnd 2.080806f
+R9 8 9 2.224404
+C13 10 gnd 2.080806f
+R10 9 10 2.224404
+C14 11 gnd 2.080806f
+R11 10 11 2.224404
+C15 12 gnd 2.080806f
+R12 11 12 2.224404
+R13 g69_2 12 2.224404
+C16 13 gnd 2.080806f
+R14 13 2 2.224404
+C17 14 gnd 2.080806f
+R15 14 13 2.224404
+C18 15 gnd 2.080806f
+R16 15 14 2.224404
+C19 16 gnd 2.080806f
+R17 16 15 2.224404
+C20 17 gnd 2.080806f
+R18 17 16 2.224404
+C21 18 gnd 2.080806f
+R19 18 17 2.224404
+C22 19 gnd 2.080806f
+R20 19 18 2.224404
+C23 20 gnd 2.080806f
+R21 20 19 2.224404
+C24 21 gnd 2.080806f
+R22 21 20 2.224404
+R23 g69_1 21 2.224404
+.ends
+
+.subckt netg4834 g4834_8 g4834_12 g4834_5 g4834_15 g4834_9 g4834_1 g4834_3 g4834_13 g4834_4 g4834_14 g4834_0 g4834_11 g4834_10 g4834_6 g4834_2 gnd
+C1  g4834_8 gnd 2.080806f
+C2  g4834_12 gnd 2.080806f
+C3  g4834_5 gnd 2.080806f
+C4  g4834_15 gnd 2.080806f
+C5  g4834_9 gnd 2.080806f
+C6  g4834_1 gnd 2.080806f
+C7  g4834_3 gnd 2.080806f
+C8  g4834_13 gnd 2.080806f
+C9  g4834_4 gnd 2.080806f
+C10  g4834_14 gnd 2.080806f
+C11  g4834_0 gnd 2.080806f
+C12  g4834_11 gnd 2.080806f
+C13  g4834_10 gnd 2.080806f
+C14  g4834_6 gnd 2.080806f
+C15  g4834_2 gnd 2.080806f
+R1 g4834_0 g4834_4 2.224404
+R2 g4834_4 g4834_1 2.224404
+R3 g4834_1 g4834_14 2.224404
+C16 1 gnd 2.080806f
+R4 g4834_14 1 2.224404
+C17 2 gnd 2.080806f
+R5 1 2 2.224404
+C18 3 gnd 2.080806f
+R6 2 3 2.224404
+R7 3 g4834_2 2.224404
+C19 4 gnd 2.080806f
+R8 4 g4834_2 2.224404
+C20 5 gnd 2.080806f
+R9 4 5 2.224404
+R10 5 g4834_11 2.224404
+C21 6 gnd 2.080806f
+R11 g4834_11 6 2.224404
+R12 6 g4834_13 2.224404
+C22 7 gnd 2.080806f
+R13 g4834_13 7 2.224404
+R14 7 g4834_15 2.224404
+C23 8 gnd 2.080806f
+R15 8 4 2.224404
+C24 9 gnd 2.080806f
+R16 9 8 2.224404
+C25 10 gnd 2.080806f
+R17 10 9 2.224404
+C26 11 gnd 2.080806f
+R18 11 10 2.224404
+R19 g4834_12 11 2.224404
+R20 g4834_12 g4834_6 2.224404
+R21 g4834_8 g4834_12 2.224404
+C27 12 gnd 2.080806f
+R22 g4834_6 12 2.224404
+R23 12 g4834_5 2.224404
+R24 g4834_10 12 2.224404
+C28 13 gnd 2.080806f
+R25 13 g4834_5 2.224404
+R26 g4834_9 13 2.224404
+C29 14 gnd 2.080806f
+R27 14 g4834_9 2.224404
+R28 14 g4834_3 2.224404
+.ends
+
+.subckt netg428 g428_4 g428_8 g428_1 g428_5 g428_9 g428_6 g428_7 g428_2 g428_10 g428_3 gnd
+C1  g428_4 gnd 2.080806f
+C2  g428_8 gnd 2.080806f
+C3  g428_1 gnd 2.080806f
+C4  g428_5 gnd 2.080806f
+C5  g428_9 gnd 2.080806f
+C6  g428_6 gnd 2.080806f
+C7  g428_7 gnd 2.080806f
+C8  g428_2 gnd 2.080806f
+C9  g428_10 gnd 2.080806f
+C10  g428_3 gnd 2.080806f
+C11 1 gnd 2.080806f
+R1 g428_9 1 2.224404
+C12 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g428_8 2.224404
+C13 3 gnd 2.080806f
+R4 g428_8 3 2.224404
+C14 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 4 g428_10 2.224404
+R7 g428_2 g428_10 2.224404
+C15 5 gnd 2.080806f
+R8 5 g428_8 2.224404
+C16 6 gnd 2.080806f
+R9 5 6 2.224404
+C17 7 gnd 2.080806f
+R10 7 6 2.224404
+C18 8 gnd 2.080806f
+R11 7 8 2.224404
+C19 9 gnd 2.080806f
+R12 8 9 2.224404
+R13 9 g428_3 2.224404
+C20 10 gnd 2.080806f
+R14 g428_3 10 2.224404
+C21 11 gnd 2.080806f
+R15 10 11 2.224404
+R16 11 g428_1 2.224404
+C22 12 gnd 2.080806f
+R17 12 g428_9 2.224404
+C23 13 gnd 2.080806f
+R18 13 12 2.224404
+C24 14 gnd 2.080806f
+R19 14 13 2.224404
+C25 15 gnd 2.080806f
+R20 15 14 2.224404
+C26 16 gnd 2.080806f
+R21 16 15 2.224404
+C27 17 gnd 2.080806f
+R22 17 16 2.224404
+R23 g428_5 17 2.224404
+R24 g428_5 g428_4 2.224404
+R25 g428_7 g428_4 2.224404
+C28 18 gnd 2.080806f
+R26 g428_7 18 2.224404
+C29 19 gnd 2.080806f
+R27 18 19 2.224404
+R28 19 g428_6 2.224404
+.ends
+
+.subckt netg7532 g7532_0 g7532_1 gnd
+C1  g7532_0 gnd 2.080806f
+C2  g7532_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7532_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+R20 g7532_1 19 2.224404
+.ends
+
+.subckt netg4820 g4820_4 g4820_1 g4820_10 g4820_7 g4820_6 g4820_0 g4820_11 g4820_13 g4820_12 g4820_9 g4820_2 g4820_8 g4820_5 gnd
+C1  g4820_4 gnd 2.080806f
+C2  g4820_1 gnd 2.080806f
+C3  g4820_10 gnd 2.080806f
+C4  g4820_7 gnd 2.080806f
+C5  g4820_6 gnd 2.080806f
+C6  g4820_0 gnd 2.080806f
+C7  g4820_11 gnd 2.080806f
+C8  g4820_13 gnd 2.080806f
+C9  g4820_12 gnd 2.080806f
+C10  g4820_9 gnd 2.080806f
+C11  g4820_2 gnd 2.080806f
+C12  g4820_8 gnd 2.080806f
+C13  g4820_5 gnd 2.080806f
+C14 1 gnd 2.080806f
+R1 g4820_0 1 2.224404
+R2 1 g4820_4 2.224404
+C15 2 gnd 2.080806f
+R3 g4820_0 2 2.224404
+R4 2 g4820_7 2.224404
+R5 g4820_7 g4820_8 2.224404
+C16 3 gnd 2.080806f
+R6 3 g4820_0 2.224404
+R7 g4820_12 3 2.224404
+R8 g4820_6 g4820_12 2.224404
+C17 4 gnd 2.080806f
+R9 g4820_8 4 2.224404
+R10 4 g4820_10 2.224404
+C18 5 gnd 2.080806f
+R11 g4820_10 5 2.224404
+C19 6 gnd 2.080806f
+R12 5 6 2.224404
+C20 7 gnd 2.080806f
+R13 6 7 2.224404
+R14 7 g4820_9 2.224404
+C21 8 gnd 2.080806f
+R15 g4820_9 8 2.224404
+R16 8 g4820_11 2.224404
+C22 9 gnd 2.080806f
+R17 9 8 2.224404
+C23 10 gnd 2.080806f
+R18 9 10 2.224404
+R19 g4820_1 10 2.224404
+R20 g4820_5 g4820_1 2.224404
+C24 11 gnd 2.080806f
+R21 11 g4820_5 2.224404
+R22 g4820_2 11 2.224404
+C25 12 gnd 2.080806f
+R23 12 g4820_2 2.224404
+C26 13 gnd 2.080806f
+R24 13 12 2.224404
+C27 14 gnd 2.080806f
+R25 14 13 2.224404
+C28 15 gnd 2.080806f
+R26 15 14 2.224404
+C29 16 gnd 2.080806f
+R27 16 15 2.224404
+C30 17 gnd 2.080806f
+R28 17 16 2.224404
+R29 g4820_13 17 2.224404
+.ends
+
+.subckt netg5986 g5986_1 g5986_0 g5986_2 gnd
+C1  g5986_1 gnd 2.080806f
+C2  g5986_0 gnd 2.080806f
+C3  g5986_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5986_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g5986_1 2 2.224404
+C6 3 gnd 2.080806f
+R4 g5986_0 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+C8 5 gnd 2.080806f
+R6 4 5 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+C10 7 gnd 2.080806f
+R8 6 7 2.224404
+C11 8 gnd 2.080806f
+R9 7 8 2.224404
+C12 9 gnd 2.080806f
+R10 8 9 2.224404
+C13 10 gnd 2.080806f
+R11 9 10 2.224404
+C14 11 gnd 2.080806f
+R12 10 11 2.224404
+C15 12 gnd 2.080806f
+R13 11 12 2.224404
+C16 13 gnd 2.080806f
+R14 12 13 2.224404
+C17 14 gnd 2.080806f
+R15 13 14 2.224404
+C18 15 gnd 2.080806f
+R16 14 15 2.224404
+C19 16 gnd 2.080806f
+R17 15 16 2.224404
+C20 17 gnd 2.080806f
+R18 16 17 2.224404
+C21 18 gnd 2.080806f
+R19 17 18 2.224404
+R20 18 g5986_2 2.224404
+.ends
+
+.subckt netg1900 g1900_0 g1900_1 gnd
+C1  g1900_0 gnd 2.080806f
+C2  g1900_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1900_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+R24 23 g1900_1 2.224404
+.ends
+
+.subckt netg576 g576_1 g576_3 g576_5 g576_2 g576_0 g576_4 gnd
+C1  g576_1 gnd 2.080806f
+C2  g576_3 gnd 2.080806f
+C3  g576_5 gnd 2.080806f
+C4  g576_2 gnd 2.080806f
+C5  g576_0 gnd 2.080806f
+C6  g576_4 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 g576_0 1 2.224404
+C8 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g576_3 2.224404
+C9 3 gnd 2.080806f
+R4 g576_0 3 2.224404
+C10 4 gnd 2.080806f
+R5 3 4 2.224404
+C11 5 gnd 2.080806f
+R6 4 5 2.224404
+C12 6 gnd 2.080806f
+R7 5 6 2.224404
+C13 7 gnd 2.080806f
+R8 6 7 2.224404
+R9 7 g576_2 2.224404
+C14 8 gnd 2.080806f
+R10 g576_2 8 2.224404
+C15 9 gnd 2.080806f
+R11 8 9 2.224404
+C16 10 gnd 2.080806f
+R12 9 10 2.224404
+C17 11 gnd 2.080806f
+R13 10 11 2.224404
+C18 12 gnd 2.080806f
+R14 11 12 2.224404
+C19 13 gnd 2.080806f
+R15 12 13 2.224404
+R16 13 g576_4 2.224404
+C20 14 gnd 2.080806f
+R17 14 g576_4 2.224404
+C21 15 gnd 2.080806f
+R18 15 14 2.224404
+C22 16 gnd 2.080806f
+R19 15 16 2.224404
+R20 g576_1 16 2.224404
+C23 17 gnd 2.080806f
+R21 g576_4 17 2.224404
+C24 18 gnd 2.080806f
+R22 17 18 2.224404
+C25 19 gnd 2.080806f
+R23 18 19 2.224404
+C26 20 gnd 2.080806f
+R24 19 20 2.224404
+C27 21 gnd 2.080806f
+R25 20 21 2.224404
+C28 22 gnd 2.080806f
+R26 21 22 2.224404
+R27 22 g576_5 2.224404
+.ends
+
+.subckt netg1664 g1664_0 g1664_3 g1664_2 g1664_5 g1664_4 g1664_1 gnd
+C1  g1664_0 gnd 2.080806f
+C2  g1664_3 gnd 2.080806f
+C3  g1664_2 gnd 2.080806f
+C4  g1664_5 gnd 2.080806f
+C5  g1664_4 gnd 2.080806f
+C6  g1664_1 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g1664_0 2.224404
+R2 g1664_1 1 2.224404
+C8 2 gnd 2.080806f
+R3 g1664_0 2 2.224404
+C9 3 gnd 2.080806f
+R4 2 3 2.224404
+C10 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 4 g1664_3 2.224404
+C11 5 gnd 2.080806f
+R7 4 5 2.224404
+C12 6 gnd 2.080806f
+R8 5 6 2.224404
+R9 6 g1664_4 2.224404
+C13 7 gnd 2.080806f
+R10 7 g1664_3 2.224404
+C14 8 gnd 2.080806f
+R11 7 8 2.224404
+C15 9 gnd 2.080806f
+R12 8 9 2.224404
+C16 10 gnd 2.080806f
+R13 9 10 2.224404
+R14 10 g1664_5 2.224404
+C17 11 gnd 2.080806f
+R15 g1664_5 11 2.224404
+C18 12 gnd 2.080806f
+R16 11 12 2.224404
+C19 13 gnd 2.080806f
+R17 12 13 2.224404
+C20 14 gnd 2.080806f
+R18 13 14 2.224404
+C21 15 gnd 2.080806f
+R19 14 15 2.224404
+C22 16 gnd 2.080806f
+R20 15 16 2.224404
+C23 17 gnd 2.080806f
+R21 16 17 2.224404
+C24 18 gnd 2.080806f
+R22 17 18 2.224404
+C25 19 gnd 2.080806f
+R23 18 19 2.224404
+C26 20 gnd 2.080806f
+R24 19 20 2.224404
+R25 20 g1664_2 2.224404
+.ends
+
+.subckt netg3030 g3030_5 g3030_4 g3030_1 g3030_3 g3030_0 g3030_6 g3030_2 gnd
+C1  g3030_5 gnd 2.080806f
+C2  g3030_4 gnd 2.080806f
+C3  g3030_1 gnd 2.080806f
+C4  g3030_3 gnd 2.080806f
+C5  g3030_0 gnd 2.080806f
+C6  g3030_6 gnd 2.080806f
+C7  g3030_2 gnd 2.080806f
+C8 1 gnd 2.080806f
+R1 1 g3030_0 2.224404
+C9 2 gnd 2.080806f
+R2 2 1 2.224404
+C10 3 gnd 2.080806f
+R3 3 2 2.224404
+C11 4 gnd 2.080806f
+R4 3 4 2.224404
+C12 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 5 g3030_3 2.224404
+C13 6 gnd 2.080806f
+R7 g3030_3 6 2.224404
+C14 7 gnd 2.080806f
+R8 6 7 2.224404
+C15 8 gnd 2.080806f
+R9 7 8 2.224404
+C16 9 gnd 2.080806f
+R10 8 9 2.224404
+R11 9 g3030_5 2.224404
+C17 10 gnd 2.080806f
+R12 10 g3030_5 2.224404
+C18 11 gnd 2.080806f
+R13 10 11 2.224404
+C19 12 gnd 2.080806f
+R14 12 11 2.224404
+C20 13 gnd 2.080806f
+R15 12 13 2.224404
+C21 14 gnd 2.080806f
+R16 13 14 2.224404
+R17 14 g3030_4 2.224404
+C22 15 gnd 2.080806f
+R18 15 g3030_4 2.224404
+C23 16 gnd 2.080806f
+R19 16 15 2.224404
+C24 17 gnd 2.080806f
+R20 17 16 2.224404
+C25 18 gnd 2.080806f
+R21 18 17 2.224404
+C26 19 gnd 2.080806f
+R22 19 18 2.224404
+C27 20 gnd 2.080806f
+R23 20 19 2.224404
+R24 g3030_1 20 2.224404
+R25 g3030_6 g3030_1 2.224404
+C28 21 gnd 2.080806f
+R26 21 19 2.224404
+C29 22 gnd 2.080806f
+R27 22 21 2.224404
+R28 g3030_2 22 2.224404
+.ends
+
+.subckt netx171 x171_0 x171_1 gnd
+C1  x171_0 gnd 2.080806f
+C2  x171_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 x171_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+R23 22 x171_1 2.224404
+.ends
+
+.subckt netg666 g666_4 g666_3 g666_2 g666_5 g666_1 g666_0 gnd
+C1  g666_4 gnd 2.080806f
+C2  g666_3 gnd 2.080806f
+C3  g666_2 gnd 2.080806f
+C4  g666_5 gnd 2.080806f
+C5  g666_1 gnd 2.080806f
+C6  g666_0 gnd 2.080806f
+R1 g666_0 g666_1 2.224404
+C7 1 gnd 2.080806f
+R2 1 g666_1 2.224404
+C8 2 gnd 2.080806f
+R3 1 2 2.224404
+R4 2 g666_5 2.224404
+C9 3 gnd 2.080806f
+R5 3 g666_0 2.224404
+C10 4 gnd 2.080806f
+R6 4 3 2.224404
+C11 5 gnd 2.080806f
+R7 5 4 2.224404
+C12 6 gnd 2.080806f
+R8 6 5 2.224404
+C13 7 gnd 2.080806f
+R9 7 6 2.224404
+R10 g666_3 7 2.224404
+C14 8 gnd 2.080806f
+R11 8 g666_3 2.224404
+C15 9 gnd 2.080806f
+R12 9 8 2.224404
+C16 10 gnd 2.080806f
+R13 10 9 2.224404
+C17 11 gnd 2.080806f
+R14 11 10 2.224404
+C18 12 gnd 2.080806f
+R15 12 11 2.224404
+C19 13 gnd 2.080806f
+R16 13 12 2.224404
+C20 14 gnd 2.080806f
+R17 14 13 2.224404
+C21 15 gnd 2.080806f
+R18 15 14 2.224404
+C22 16 gnd 2.080806f
+R19 16 15 2.224404
+R20 g666_2 16 2.224404
+C23 17 gnd 2.080806f
+R21 17 g666_2 2.224404
+R22 g666_4 17 2.224404
+.ends
+
+.subckt netg4560 g4560_6 g4560_5 g4560_4 g4560_3 g4560_0 g4560_7 g4560_2 g4560_1 gnd
+C1  g4560_6 gnd 2.080806f
+C2  g4560_5 gnd 2.080806f
+C3  g4560_4 gnd 2.080806f
+C4  g4560_3 gnd 2.080806f
+C5  g4560_0 gnd 2.080806f
+C6  g4560_7 gnd 2.080806f
+C7  g4560_2 gnd 2.080806f
+C8  g4560_1 gnd 2.080806f
+C9 1 gnd 2.080806f
+R1 g4560_0 1 2.224404
+R2 1 g4560_4 2.224404
+R3 g4560_4 g4560_5 2.224404
+R4 g4560_7 g4560_5 2.224404
+C10 2 gnd 2.080806f
+R5 2 g4560_0 2.224404
+C11 3 gnd 2.080806f
+R6 3 2 2.224404
+C12 4 gnd 2.080806f
+R7 4 3 2.224404
+R8 g4560_1 4 2.224404
+C13 5 gnd 2.080806f
+R9 5 g4560_1 2.224404
+C14 6 gnd 2.080806f
+R10 6 5 2.224404
+C15 7 gnd 2.080806f
+R11 7 6 2.224404
+R12 g4560_2 7 2.224404
+C16 8 gnd 2.080806f
+R13 8 g4560_2 2.224404
+C17 9 gnd 2.080806f
+R14 9 8 2.224404
+R15 g4560_3 9 2.224404
+C18 10 gnd 2.080806f
+R16 g4560_5 10 2.224404
+C19 11 gnd 2.080806f
+R17 10 11 2.224404
+C20 12 gnd 2.080806f
+R18 11 12 2.224404
+C21 13 gnd 2.080806f
+R19 12 13 2.224404
+C22 14 gnd 2.080806f
+R20 13 14 2.224404
+C23 15 gnd 2.080806f
+R21 14 15 2.224404
+R22 15 g4560_6 2.224404
+.ends
+
+.subckt netg2334 g2334_3 g2334_1 g2334_2 g2334_0 gnd
+C1  g2334_3 gnd 2.080806f
+C2  g2334_1 gnd 2.080806f
+C3  g2334_2 gnd 2.080806f
+C4  g2334_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g2334_0 1 2.224404
+R2 1 g2334_1 2.224404
+C6 2 gnd 2.080806f
+R3 2 1 2.224404
+C7 3 gnd 2.080806f
+R4 3 2 2.224404
+C8 4 gnd 2.080806f
+R5 4 3 2.224404
+C9 5 gnd 2.080806f
+R6 5 4 2.224404
+R7 g2334_3 5 2.224404
+C10 6 gnd 2.080806f
+R8 6 g2334_3 2.224404
+C11 7 gnd 2.080806f
+R9 7 6 2.224404
+C12 8 gnd 2.080806f
+R10 8 7 2.224404
+C13 9 gnd 2.080806f
+R11 9 8 2.224404
+C14 10 gnd 2.080806f
+R12 10 9 2.224404
+C15 11 gnd 2.080806f
+R13 11 10 2.224404
+C16 12 gnd 2.080806f
+R14 12 11 2.224404
+C17 13 gnd 2.080806f
+R15 13 12 2.224404
+C18 14 gnd 2.080806f
+R16 14 13 2.224404
+C19 15 gnd 2.080806f
+R17 15 14 2.224404
+C20 16 gnd 2.080806f
+R18 16 15 2.224404
+C21 17 gnd 2.080806f
+R19 17 16 2.224404
+C22 18 gnd 2.080806f
+R20 18 17 2.224404
+C23 19 gnd 2.080806f
+R21 19 18 2.224404
+R22 g2334_2 19 2.224404
+.ends
+
+.subckt netg120 g120_1 g120_0 gnd
+C1  g120_1 gnd 2.080806f
+C2  g120_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g120_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+R21 20 g120_1 2.224404
+.ends
+
+.subckt netg2683 g2683_2 g2683_1 g2683_0 gnd
+C1  g2683_2 gnd 2.080806f
+C2  g2683_1 gnd 2.080806f
+C3  g2683_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g2683_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+C8 5 gnd 2.080806f
+R5 4 5 2.224404
+C9 6 gnd 2.080806f
+R6 5 6 2.224404
+C10 7 gnd 2.080806f
+R7 6 7 2.224404
+C11 8 gnd 2.080806f
+R8 7 8 2.224404
+C12 9 gnd 2.080806f
+R9 8 9 2.224404
+C13 10 gnd 2.080806f
+R10 9 10 2.224404
+C14 11 gnd 2.080806f
+R11 10 11 2.224404
+C15 12 gnd 2.080806f
+R12 11 12 2.224404
+C16 13 gnd 2.080806f
+R13 12 13 2.224404
+C17 14 gnd 2.080806f
+R14 13 14 2.224404
+C18 15 gnd 2.080806f
+R15 14 15 2.224404
+C19 16 gnd 2.080806f
+R16 15 16 2.224404
+C20 17 gnd 2.080806f
+R17 16 17 2.224404
+C21 18 gnd 2.080806f
+R18 17 18 2.224404
+C22 19 gnd 2.080806f
+R19 18 19 2.224404
+R20 19 g2683_2 2.224404
+R21 g2683_2 g2683_1 2.224404
+.ends
+
+.subckt netg3862 g3862_8 g3862_0 g3862_7 g3862_6 g3862_9 g3862_2 g3862_10 g3862_3 g3862_1 g3862_5 g3862_4 gnd
+C1  g3862_8 gnd 2.080806f
+C2  g3862_0 gnd 2.080806f
+C3  g3862_7 gnd 2.080806f
+C4  g3862_6 gnd 2.080806f
+C5  g3862_9 gnd 2.080806f
+C6  g3862_2 gnd 2.080806f
+C7  g3862_10 gnd 2.080806f
+C8  g3862_3 gnd 2.080806f
+C9  g3862_1 gnd 2.080806f
+C10  g3862_5 gnd 2.080806f
+C11  g3862_4 gnd 2.080806f
+C12 1 gnd 2.080806f
+R1 1 g3862_0 2.224404
+R2 g3862_1 1 2.224404
+R3 g3862_1 g3862_5 2.224404
+R4 g3862_5 g3862_7 2.224404
+R5 g3862_7 g3862_3 2.224404
+C13 2 gnd 2.080806f
+R6 g3862_7 2 2.224404
+R7 2 g3862_2 2.224404
+C14 3 gnd 2.080806f
+R8 g3862_3 3 2.224404
+R9 3 g3862_9 2.224404
+C15 4 gnd 2.080806f
+R10 g3862_9 4 2.224404
+C16 5 gnd 2.080806f
+R11 4 5 2.224404
+R12 5 g3862_4 2.224404
+C17 6 gnd 2.080806f
+R13 6 g3862_1 2.224404
+C18 7 gnd 2.080806f
+R14 7 6 2.224404
+R15 g3862_10 7 2.224404
+C19 8 gnd 2.080806f
+R16 8 g3862_10 2.224404
+C20 9 gnd 2.080806f
+R17 9 8 2.224404
+C21 10 gnd 2.080806f
+R18 10 9 2.224404
+R19 g3862_8 10 2.224404
+C22 11 gnd 2.080806f
+R20 11 g3862_4 2.224404
+C23 12 gnd 2.080806f
+R21 11 12 2.224404
+C24 13 gnd 2.080806f
+R22 12 13 2.224404
+C25 14 gnd 2.080806f
+R23 13 14 2.224404
+C26 15 gnd 2.080806f
+R24 15 14 2.224404
+C27 16 gnd 2.080806f
+R25 15 16 2.224404
+C28 17 gnd 2.080806f
+R26 16 17 2.224404
+R27 17 g3862_6 2.224404
+.ends
+
+.subckt netg2853 g2853_5 g2853_2 g2853_3 g2853_4 g2853_1 gnd
+C1  g2853_5 gnd 2.080806f
+C2  g2853_2 gnd 2.080806f
+C3  g2853_3 gnd 2.080806f
+C4  g2853_4 gnd 2.080806f
+C5  g2853_1 gnd 2.080806f
+R1 g2853_1 g2853_4 2.224404
+C6 1 gnd 2.080806f
+R2 1 g2853_4 2.224404
+C7 2 gnd 2.080806f
+R3 2 1 2.224404
+R4 g2853_5 2 2.224404
+C8 3 gnd 2.080806f
+R5 3 g2853_5 2.224404
+C9 4 gnd 2.080806f
+R6 4 3 2.224404
+R7 g2853_3 4 2.224404
+C10 5 gnd 2.080806f
+R8 g2853_4 5 2.224404
+C11 6 gnd 2.080806f
+R9 5 6 2.224404
+C12 7 gnd 2.080806f
+R10 6 7 2.224404
+C13 8 gnd 2.080806f
+R11 7 8 2.224404
+C14 9 gnd 2.080806f
+R12 8 9 2.224404
+C15 10 gnd 2.080806f
+R13 9 10 2.224404
+C16 11 gnd 2.080806f
+R14 10 11 2.224404
+C17 12 gnd 2.080806f
+R15 11 12 2.224404
+C18 13 gnd 2.080806f
+R16 12 13 2.224404
+C19 14 gnd 2.080806f
+R17 13 14 2.224404
+C20 15 gnd 2.080806f
+R18 14 15 2.224404
+C21 16 gnd 2.080806f
+R19 15 16 2.224404
+C22 17 gnd 2.080806f
+R20 16 17 2.224404
+C23 18 gnd 2.080806f
+R21 17 18 2.224404
+R22 18 g2853_2 2.224404
+.ends
+
+.subckt netg102 g102_0 g102_1 gnd
+C1  g102_0 gnd 2.080806f
+C2  g102_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g102_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+R21 20 g102_1 2.224404
+.ends
+
+.subckt netg89 g89_0 g89_1 gnd
+C1  g89_0 gnd 2.080806f
+C2  g89_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g89_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+R21 20 g89_1 2.224404
+.ends
+
+.subckt netg44 g44_0 g44_1 gnd
+C1  g44_0 gnd 2.080806f
+C2  g44_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g44_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+R21 20 g44_1 2.224404
+.ends
+
+.subckt netg634 g634_3 g634_1 g634_0 g634_2 g634_5 g634_4 gnd
+C1  g634_3 gnd 2.080806f
+C2  g634_1 gnd 2.080806f
+C3  g634_0 gnd 2.080806f
+C4  g634_2 gnd 2.080806f
+C5  g634_5 gnd 2.080806f
+C6  g634_4 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g634_0 2.224404
+C8 2 gnd 2.080806f
+R2 2 1 2.224404
+C9 3 gnd 2.080806f
+R3 3 2 2.224404
+C10 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 g634_3 4 2.224404
+C11 5 gnd 2.080806f
+R6 g634_3 5 2.224404
+C12 6 gnd 2.080806f
+R7 5 6 2.224404
+C13 7 gnd 2.080806f
+R8 6 7 2.224404
+C14 8 gnd 2.080806f
+R9 8 7 2.224404
+C15 9 gnd 2.080806f
+R10 8 9 2.224404
+R11 g634_1 9 2.224404
+C16 10 gnd 2.080806f
+R12 10 g634_0 2.224404
+C17 11 gnd 2.080806f
+R13 11 10 2.224404
+C18 12 gnd 2.080806f
+R14 12 11 2.224404
+C19 13 gnd 2.080806f
+R15 13 12 2.224404
+C20 14 gnd 2.080806f
+R16 14 13 2.224404
+C21 15 gnd 2.080806f
+R17 15 14 2.224404
+C22 16 gnd 2.080806f
+R18 15 16 2.224404
+R19 16 g634_4 2.224404
+R20 g634_2 g634_4 2.224404
+R21 g634_2 g634_5 2.224404
+.ends
+
+.subckt netg821 g821_0 g821_6 g821_3 g821_1 g821_4 g821_2 g821_5 gnd
+C1  g821_0 gnd 2.080806f
+C2  g821_6 gnd 2.080806f
+C3  g821_3 gnd 2.080806f
+C4  g821_1 gnd 2.080806f
+C5  g821_4 gnd 2.080806f
+C6  g821_2 gnd 2.080806f
+C7  g821_5 gnd 2.080806f
+R1 g821_0 g821_1 2.224404
+R2 g821_5 g821_0 2.224404
+C8 1 gnd 2.080806f
+R3 g821_1 1 2.224404
+C9 2 gnd 2.080806f
+R4 1 2 2.224404
+C10 3 gnd 2.080806f
+R5 2 3 2.224404
+C11 4 gnd 2.080806f
+R6 3 4 2.224404
+C12 5 gnd 2.080806f
+R7 4 5 2.224404
+R8 5 g821_6 2.224404
+C13 6 gnd 2.080806f
+R9 6 g821_6 2.224404
+C14 7 gnd 2.080806f
+R10 7 6 2.224404
+C15 8 gnd 2.080806f
+R11 8 7 2.224404
+C16 9 gnd 2.080806f
+R12 9 8 2.224404
+C17 10 gnd 2.080806f
+R13 9 10 2.224404
+R14 10 g821_2 2.224404
+C18 11 gnd 2.080806f
+R15 11 g821_2 2.224404
+C19 12 gnd 2.080806f
+R16 12 11 2.224404
+C20 13 gnd 2.080806f
+R17 13 12 2.224404
+C21 14 gnd 2.080806f
+R18 14 13 2.224404
+C22 15 gnd 2.080806f
+R19 14 15 2.224404
+C23 16 gnd 2.080806f
+R20 15 16 2.224404
+R21 16 g821_3 2.224404
+R22 g821_3 g821_4 2.224404
+.ends
+
+.subckt netg1459 g1459_1 g1459_0 gnd
+C1  g1459_1 gnd 2.080806f
+C2  g1459_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1459_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+R21 g1459_1 20 2.224404
+.ends
+
+.subckt netg3784 g3784_3 g3784_2 g3784_0 g3784_9 g3784_12 g3784_8 g3784_7 g3784_6 g3784_4 g3784_1 g3784_11 g3784_10 g3784_5 gnd
+C1  g3784_3 gnd 2.080806f
+C2  g3784_2 gnd 2.080806f
+C3  g3784_0 gnd 2.080806f
+C4  g3784_9 gnd 2.080806f
+C5  g3784_12 gnd 2.080806f
+C6  g3784_8 gnd 2.080806f
+C7  g3784_7 gnd 2.080806f
+C8  g3784_6 gnd 2.080806f
+C9  g3784_4 gnd 2.080806f
+C10  g3784_1 gnd 2.080806f
+C11  g3784_11 gnd 2.080806f
+C12  g3784_10 gnd 2.080806f
+C13  g3784_5 gnd 2.080806f
+C14 1 gnd 2.080806f
+R1 g3784_0 1 2.224404
+R2 1 g3784_10 2.224404
+C15 2 gnd 2.080806f
+R3 g3784_0 2 2.224404
+C16 3 gnd 2.080806f
+R4 2 3 2.224404
+C17 4 gnd 2.080806f
+R5 3 4 2.224404
+C18 5 gnd 2.080806f
+R6 4 5 2.224404
+R7 5 g3784_6 2.224404
+C19 6 gnd 2.080806f
+R8 g3784_6 6 2.224404
+C20 7 gnd 2.080806f
+R9 6 7 2.224404
+C21 8 gnd 2.080806f
+R10 7 8 2.224404
+C22 9 gnd 2.080806f
+R11 8 9 2.224404
+R12 9 g3784_2 2.224404
+R13 g3784_2 g3784_5 2.224404
+C23 10 gnd 2.080806f
+R14 g3784_5 10 2.224404
+R15 10 g3784_7 2.224404
+R16 g3784_7 g3784_3 2.224404
+R17 g3784_3 g3784_9 2.224404
+R18 g3784_9 g3784_4 2.224404
+R19 g3784_4 g3784_1 2.224404
+C24 11 gnd 2.080806f
+R20 11 g3784_7 2.224404
+C25 12 gnd 2.080806f
+R21 12 11 2.224404
+R22 g3784_11 12 2.224404
+C26 13 gnd 2.080806f
+R23 13 g3784_1 2.224404
+C27 14 gnd 2.080806f
+R24 14 13 2.224404
+R25 14 g3784_8 2.224404
+C28 15 gnd 2.080806f
+R26 g3784_8 15 2.224404
+C29 16 gnd 2.080806f
+R27 15 16 2.224404
+C30 17 gnd 2.080806f
+R28 16 17 2.224404
+R29 17 g3784_12 2.224404
+.ends
+
+.subckt netg3579 g3579_2 g3579_5 g3579_0 g3579_4 g3579_1 g3579_6 g3579_3 g3579_7 gnd
+C1  g3579_2 gnd 2.080806f
+C2  g3579_5 gnd 2.080806f
+C3  g3579_0 gnd 2.080806f
+C4  g3579_4 gnd 2.080806f
+C5  g3579_1 gnd 2.080806f
+C6  g3579_6 gnd 2.080806f
+C7  g3579_3 gnd 2.080806f
+C8  g3579_7 gnd 2.080806f
+R1 g3579_5 g3579_0 2.224404
+C9 1 gnd 2.080806f
+R2 g3579_0 1 2.224404
+C10 2 gnd 2.080806f
+R3 2 1 2.224404
+C11 3 gnd 2.080806f
+R4 2 3 2.224404
+C12 4 gnd 2.080806f
+R5 3 4 2.224404
+C13 5 gnd 2.080806f
+R6 4 5 2.224404
+R7 5 g3579_4 2.224404
+C14 6 gnd 2.080806f
+R8 6 4 2.224404
+C15 7 gnd 2.080806f
+R9 7 6 2.224404
+C16 8 gnd 2.080806f
+R10 8 7 2.224404
+R11 g3579_7 8 2.224404
+C17 9 gnd 2.080806f
+R12 9 g3579_7 2.224404
+C18 10 gnd 2.080806f
+R13 9 10 2.224404
+C19 11 gnd 2.080806f
+R14 10 11 2.224404
+C20 12 gnd 2.080806f
+R15 12 11 2.224404
+C21 13 gnd 2.080806f
+R16 12 13 2.224404
+C22 14 gnd 2.080806f
+R17 13 14 2.224404
+R18 14 g3579_2 2.224404
+C23 15 gnd 2.080806f
+R19 g3579_2 15 2.224404
+C24 16 gnd 2.080806f
+R20 15 16 2.224404
+R21 16 g3579_6 2.224404
+R22 g3579_1 g3579_6 2.224404
+R23 g3579_1 g3579_3 2.224404
+.ends
+
+.subckt netg5977 g5977_2 g5977_0 g5977_1 gnd
+C1  g5977_2 gnd 2.080806f
+C2  g5977_0 gnd 2.080806f
+C3  g5977_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5977_0 2.224404
+R2 g5977_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 11 10 2.224404
+C15 12 gnd 2.080806f
+R13 12 11 2.224404
+C16 13 gnd 2.080806f
+R14 13 12 2.224404
+C17 14 gnd 2.080806f
+R15 14 13 2.224404
+C18 15 gnd 2.080806f
+R16 15 14 2.224404
+C19 16 gnd 2.080806f
+R17 16 15 2.224404
+C20 17 gnd 2.080806f
+R18 17 16 2.224404
+C21 18 gnd 2.080806f
+R19 17 18 2.224404
+C22 19 gnd 2.080806f
+R20 18 19 2.224404
+R21 19 g5977_2 2.224404
+.ends
+
+.subckt netg5502 g5502_2 g5502_1 g5502_0 gnd
+C1  g5502_2 gnd 2.080806f
+C2  g5502_1 gnd 2.080806f
+C3  g5502_0 gnd 2.080806f
+R1 g5502_2 g5502_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g5502_2 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 11 10 2.224404
+C15 12 gnd 2.080806f
+R13 12 11 2.224404
+C16 13 gnd 2.080806f
+R14 13 12 2.224404
+C17 14 gnd 2.080806f
+R15 14 13 2.224404
+C18 15 gnd 2.080806f
+R16 15 14 2.224404
+C19 16 gnd 2.080806f
+R17 16 15 2.224404
+C20 17 gnd 2.080806f
+R18 17 16 2.224404
+C21 18 gnd 2.080806f
+R19 18 17 2.224404
+C22 19 gnd 2.080806f
+R20 19 18 2.224404
+R21 g5502_1 19 2.224404
+.ends
+
+.subckt netg5839 g5839_3 g5839_1 g5839_0 g5839_2 gnd
+C1  g5839_3 gnd 2.080806f
+C2  g5839_1 gnd 2.080806f
+C3  g5839_0 gnd 2.080806f
+C4  g5839_2 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g5839_0 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+C7 3 gnd 2.080806f
+R3 3 2 2.224404
+C8 4 gnd 2.080806f
+R4 3 4 2.224404
+C9 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 5 g5839_2 2.224404
+C10 6 gnd 2.080806f
+R7 g5839_2 6 2.224404
+C11 7 gnd 2.080806f
+R8 6 7 2.224404
+C12 8 gnd 2.080806f
+R9 7 8 2.224404
+C13 9 gnd 2.080806f
+R10 8 9 2.224404
+R11 9 g5839_1 2.224404
+C14 10 gnd 2.080806f
+R12 g5839_1 10 2.224404
+C15 11 gnd 2.080806f
+R13 10 11 2.224404
+C16 12 gnd 2.080806f
+R14 11 12 2.224404
+C17 13 gnd 2.080806f
+R15 12 13 2.224404
+C18 14 gnd 2.080806f
+R16 13 14 2.224404
+C19 15 gnd 2.080806f
+R17 14 15 2.224404
+C20 16 gnd 2.080806f
+R18 15 16 2.224404
+C21 17 gnd 2.080806f
+R19 16 17 2.224404
+C22 18 gnd 2.080806f
+R20 17 18 2.224404
+C23 19 gnd 2.080806f
+R21 18 19 2.224404
+C24 20 gnd 2.080806f
+R22 19 20 2.224404
+R23 20 g5839_3 2.224404
+.ends
+
+.subckt netg2280 g2280_2 g2280_3 g2280_1 g2280_0 gnd
+C1  g2280_2 gnd 2.080806f
+C2  g2280_3 gnd 2.080806f
+C3  g2280_1 gnd 2.080806f
+C4  g2280_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g2280_0 1 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+C7 3 gnd 2.080806f
+R3 2 3 2.224404
+C8 4 gnd 2.080806f
+R4 3 4 2.224404
+C9 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 5 g2280_3 2.224404
+C10 6 gnd 2.080806f
+R7 6 g2280_0 2.224404
+C11 7 gnd 2.080806f
+R8 7 6 2.224404
+C12 8 gnd 2.080806f
+R9 8 7 2.224404
+C13 9 gnd 2.080806f
+R10 9 8 2.224404
+C14 10 gnd 2.080806f
+R11 10 9 2.224404
+C15 11 gnd 2.080806f
+R12 11 10 2.224404
+C16 12 gnd 2.080806f
+R13 12 11 2.224404
+C17 13 gnd 2.080806f
+R14 13 12 2.224404
+C18 14 gnd 2.080806f
+R15 14 13 2.224404
+R16 g2280_2 14 2.224404
+C19 15 gnd 2.080806f
+R17 15 g2280_2 2.224404
+C20 16 gnd 2.080806f
+R18 16 15 2.224404
+C21 17 gnd 2.080806f
+R19 17 16 2.224404
+C22 18 gnd 2.080806f
+R20 18 17 2.224404
+R21 g2280_1 18 2.224404
+.ends
+
+.subckt netg133 g133_0 g133_1 gnd
+C1  g133_0 gnd 2.080806f
+C2  g133_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g133_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+R21 g133_1 20 2.224404
+.ends
+
+.subckt netg6568 g6568_2 g6568_0 g6568_4 g6568_1 g6568_3 gnd
+C1  g6568_2 gnd 2.080806f
+C2  g6568_0 gnd 2.080806f
+C3  g6568_4 gnd 2.080806f
+C4  g6568_1 gnd 2.080806f
+C5  g6568_3 gnd 2.080806f
+C6 1 gnd 2.080806f
+R1 1 g6568_0 2.224404
+C7 2 gnd 2.080806f
+R2 2 1 2.224404
+C8 3 gnd 2.080806f
+R3 3 2 2.224404
+C9 4 gnd 2.080806f
+R4 4 3 2.224404
+C10 5 gnd 2.080806f
+R5 5 4 2.224404
+C11 6 gnd 2.080806f
+R6 6 5 2.224404
+C12 7 gnd 2.080806f
+R7 7 6 2.224404
+C13 8 gnd 2.080806f
+R8 8 7 2.224404
+C14 9 gnd 2.080806f
+R9 9 8 2.224404
+C15 10 gnd 2.080806f
+R10 10 9 2.224404
+C16 11 gnd 2.080806f
+R11 11 10 2.224404
+C17 12 gnd 2.080806f
+R12 12 11 2.224404
+C18 13 gnd 2.080806f
+R13 13 12 2.224404
+R14 g6568_2 13 2.224404
+C19 14 gnd 2.080806f
+R15 14 g6568_2 2.224404
+C20 15 gnd 2.080806f
+R16 15 14 2.224404
+R17 15 g6568_4 2.224404
+C21 16 gnd 2.080806f
+R18 g6568_4 16 2.224404
+C22 17 gnd 2.080806f
+R19 16 17 2.224404
+R20 17 g6568_3 2.224404
+C23 18 gnd 2.080806f
+R21 g6568_3 18 2.224404
+C24 19 gnd 2.080806f
+R22 18 19 2.224404
+C25 20 gnd 2.080806f
+R23 19 20 2.224404
+C26 21 gnd 2.080806f
+R24 20 21 2.224404
+R25 21 g6568_1 2.224404
+.ends
+
+.subckt netg652 g652_5 g652_4 g652_2 g652_0 g652_1 g652_3 g652_7 g652_6 gnd
+C1  g652_5 gnd 2.080806f
+C2  g652_4 gnd 2.080806f
+C3  g652_2 gnd 2.080806f
+C4  g652_0 gnd 2.080806f
+C5  g652_1 gnd 2.080806f
+C6  g652_3 gnd 2.080806f
+C7  g652_7 gnd 2.080806f
+C8  g652_6 gnd 2.080806f
+R1 g652_1 g652_0 2.224404
+C9 1 gnd 2.080806f
+R2 g652_0 1 2.224404
+R3 g652_2 1 2.224404
+C10 2 gnd 2.080806f
+R4 g652_2 2 2.224404
+C11 3 gnd 2.080806f
+R5 2 3 2.224404
+C12 4 gnd 2.080806f
+R6 3 4 2.224404
+C13 5 gnd 2.080806f
+R7 4 5 2.224404
+C14 6 gnd 2.080806f
+R8 5 6 2.224404
+R9 6 g652_5 2.224404
+C15 7 gnd 2.080806f
+R10 7 g652_5 2.224404
+C16 8 gnd 2.080806f
+R11 7 8 2.224404
+C17 9 gnd 2.080806f
+R12 9 8 2.224404
+C18 10 gnd 2.080806f
+R13 9 10 2.224404
+C19 11 gnd 2.080806f
+R14 10 11 2.224404
+R15 11 g652_4 2.224404
+C20 12 gnd 2.080806f
+R16 g652_4 12 2.224404
+C21 13 gnd 2.080806f
+R17 12 13 2.224404
+C22 14 gnd 2.080806f
+R18 13 14 2.224404
+C23 15 gnd 2.080806f
+R19 14 15 2.224404
+C24 16 gnd 2.080806f
+R20 15 16 2.224404
+R21 16 g652_7 2.224404
+C25 17 gnd 2.080806f
+R22 g652_7 17 2.224404
+C26 18 gnd 2.080806f
+R23 17 18 2.224404
+C27 19 gnd 2.080806f
+R24 18 19 2.224404
+C28 20 gnd 2.080806f
+R25 19 20 2.224404
+C29 21 gnd 2.080806f
+R26 20 21 2.224404
+R27 21 g652_6 2.224404
+C30 22 gnd 2.080806f
+R28 22 12 2.224404
+C31 23 gnd 2.080806f
+R29 22 23 2.224404
+C32 24 gnd 2.080806f
+R30 23 24 2.224404
+C33 25 gnd 2.080806f
+R31 25 24 2.224404
+C34 26 gnd 2.080806f
+R32 25 26 2.224404
+C35 27 gnd 2.080806f
+R33 26 27 2.224404
+R34 27 g652_3 2.224404
+.ends
+
+.subckt netg7512 g7512_0 g7512_1 gnd
+C1  g7512_0 gnd 2.080806f
+C2  g7512_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7512_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+R22 21 g7512_1 2.224404
+.ends
+
+.subckt netg3037 g3037_0 g3037_6 g3037_5 g3037_3 g3037_1 g3037_2 g3037_7 g3037_4 gnd
+C1  g3037_0 gnd 2.080806f
+C2  g3037_6 gnd 2.080806f
+C3  g3037_5 gnd 2.080806f
+C4  g3037_3 gnd 2.080806f
+C5  g3037_1 gnd 2.080806f
+C6  g3037_2 gnd 2.080806f
+C7  g3037_7 gnd 2.080806f
+C8  g3037_4 gnd 2.080806f
+R1 g3037_6 g3037_0 2.224404
+C9 1 gnd 2.080806f
+R2 1 g3037_6 2.224404
+R3 g3037_3 1 2.224404
+C10 2 gnd 2.080806f
+R4 2 g3037_6 2.224404
+C11 3 gnd 2.080806f
+R5 3 2 2.224404
+R6 g3037_5 3 2.224404
+C12 4 gnd 2.080806f
+R7 4 g3037_5 2.224404
+C13 5 gnd 2.080806f
+R8 5 4 2.224404
+C14 6 gnd 2.080806f
+R9 6 5 2.224404
+R10 g3037_4 6 2.224404
+C15 7 gnd 2.080806f
+R11 g3037_5 7 2.224404
+C16 8 gnd 2.080806f
+R12 7 8 2.224404
+C17 9 gnd 2.080806f
+R13 8 9 2.224404
+C18 10 gnd 2.080806f
+R14 9 10 2.224404
+C19 11 gnd 2.080806f
+R15 11 10 2.224404
+C20 12 gnd 2.080806f
+R16 11 12 2.224404
+R17 g3037_2 12 2.224404
+C21 13 gnd 2.080806f
+R18 g3037_2 13 2.224404
+C22 14 gnd 2.080806f
+R19 14 13 2.224404
+C23 15 gnd 2.080806f
+R20 15 14 2.224404
+R21 g3037_1 15 2.224404
+C24 16 gnd 2.080806f
+R22 15 16 2.224404
+C25 17 gnd 2.080806f
+R23 16 17 2.224404
+C26 18 gnd 2.080806f
+R24 17 18 2.224404
+R25 g3037_7 18 2.224404
+.ends
+
+.subckt netg2409 g2409_0 g2409_2 g2409_1 gnd
+C1  g2409_0 gnd 2.080806f
+C2  g2409_2 gnd 2.080806f
+C3  g2409_1 gnd 2.080806f
+R1 g2409_2 g2409_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g2409_2 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 11 10 2.224404
+C15 12 gnd 2.080806f
+R13 12 11 2.224404
+C16 13 gnd 2.080806f
+R14 13 12 2.224404
+C17 14 gnd 2.080806f
+R15 14 13 2.224404
+C18 15 gnd 2.080806f
+R16 15 14 2.224404
+C19 16 gnd 2.080806f
+R17 16 15 2.224404
+C20 17 gnd 2.080806f
+R18 17 16 2.224404
+C21 18 gnd 2.080806f
+R19 18 17 2.224404
+C22 19 gnd 2.080806f
+R20 19 18 2.224404
+C23 20 gnd 2.080806f
+R21 20 19 2.224404
+R22 g2409_1 20 2.224404
+.ends
+
+.subckt netg1683 g1683_2 g1683_3 g1683_1 gnd
+C1  g1683_2 gnd 2.080806f
+C2  g1683_3 gnd 2.080806f
+C3  g1683_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g1683_3 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 4 g1683_2 2.224404
+C8 5 gnd 2.080806f
+R6 g1683_2 5 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+C10 7 gnd 2.080806f
+R8 6 7 2.224404
+C11 8 gnd 2.080806f
+R9 7 8 2.224404
+C12 9 gnd 2.080806f
+R10 8 9 2.224404
+C13 10 gnd 2.080806f
+R11 9 10 2.224404
+C14 11 gnd 2.080806f
+R12 10 11 2.224404
+C15 12 gnd 2.080806f
+R13 11 12 2.224404
+C16 13 gnd 2.080806f
+R14 12 13 2.224404
+C17 14 gnd 2.080806f
+R15 13 14 2.224404
+C18 15 gnd 2.080806f
+R16 14 15 2.224404
+C19 16 gnd 2.080806f
+R17 15 16 2.224404
+C20 17 gnd 2.080806f
+R18 17 16 2.224404
+C21 18 gnd 2.080806f
+R19 17 18 2.224404
+C22 19 gnd 2.080806f
+R20 18 19 2.224404
+C23 20 gnd 2.080806f
+R21 19 20 2.224404
+C24 21 gnd 2.080806f
+R22 20 21 2.224404
+C25 22 gnd 2.080806f
+R23 21 22 2.224404
+R24 22 g1683_1 2.224404
+.ends
+
+.subckt netg7513 g7513_0 g7513_1 gnd
+C1  g7513_0 gnd 2.080806f
+C2  g7513_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7513_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+R22 g7513_1 21 2.224404
+.ends
+
+.subckt netg5418 g5418_1 g5418_0 g5418_2 gnd
+C1  g5418_1 gnd 2.080806f
+C2  g5418_0 gnd 2.080806f
+C3  g5418_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g5418_0 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g5418_1 2 2.224404
+C6 3 gnd 2.080806f
+R4 g5418_0 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+C8 5 gnd 2.080806f
+R6 4 5 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+C10 7 gnd 2.080806f
+R8 6 7 2.224404
+C11 8 gnd 2.080806f
+R9 7 8 2.224404
+C12 9 gnd 2.080806f
+R10 8 9 2.224404
+C13 10 gnd 2.080806f
+R11 9 10 2.224404
+C14 11 gnd 2.080806f
+R12 10 11 2.224404
+C15 12 gnd 2.080806f
+R13 11 12 2.224404
+C16 13 gnd 2.080806f
+R14 12 13 2.224404
+C17 14 gnd 2.080806f
+R15 13 14 2.224404
+C18 15 gnd 2.080806f
+R16 14 15 2.224404
+C19 16 gnd 2.080806f
+R17 15 16 2.224404
+C20 17 gnd 2.080806f
+R18 16 17 2.224404
+C21 18 gnd 2.080806f
+R19 17 18 2.224404
+C22 19 gnd 2.080806f
+R20 18 19 2.224404
+C23 20 gnd 2.080806f
+R21 19 20 2.224404
+C24 21 gnd 2.080806f
+R22 20 21 2.224404
+R23 21 g5418_2 2.224404
+.ends
+
+.subckt netg7515 g7515_0 g7515_1 gnd
+C1  g7515_0 gnd 2.080806f
+C2  g7515_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7515_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+R22 g7515_1 21 2.224404
+.ends
+
+.subckt netg45 g45_0 g45_1 gnd
+C1  g45_0 gnd 2.080806f
+C2  g45_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g45_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+R22 21 g45_1 2.224404
+.ends
+
+.subckt netg683 g683_3 g683_2 g683_0 g683_5 g683_6 g683_1 g683_4 gnd
+C1  g683_3 gnd 2.080806f
+C2  g683_2 gnd 2.080806f
+C3  g683_0 gnd 2.080806f
+C4  g683_5 gnd 2.080806f
+C5  g683_6 gnd 2.080806f
+C6  g683_1 gnd 2.080806f
+C7  g683_4 gnd 2.080806f
+R1 g683_0 g683_1 2.224404
+R2 g683_1 g683_3 2.224404
+C8 1 gnd 2.080806f
+R3 1 g683_0 2.224404
+C9 2 gnd 2.080806f
+R4 2 1 2.224404
+C10 3 gnd 2.080806f
+R5 3 2 2.224404
+C11 4 gnd 2.080806f
+R6 4 3 2.224404
+C12 5 gnd 2.080806f
+R7 5 4 2.224404
+C13 6 gnd 2.080806f
+R8 6 5 2.224404
+R9 g683_4 6 2.224404
+C14 7 gnd 2.080806f
+R10 7 g683_4 2.224404
+R11 7 g683_5 2.224404
+C15 8 gnd 2.080806f
+R12 g683_3 8 2.224404
+C16 9 gnd 2.080806f
+R13 9 8 2.224404
+C17 10 gnd 2.080806f
+R14 9 10 2.224404
+C18 11 gnd 2.080806f
+R15 10 11 2.224404
+C19 12 gnd 2.080806f
+R16 11 12 2.224404
+C20 13 gnd 2.080806f
+R17 13 12 2.224404
+C21 14 gnd 2.080806f
+R18 13 14 2.224404
+C22 15 gnd 2.080806f
+R19 14 15 2.224404
+R20 15 g683_2 2.224404
+C23 16 gnd 2.080806f
+R21 g683_2 16 2.224404
+C24 17 gnd 2.080806f
+R22 16 17 2.224404
+C25 18 gnd 2.080806f
+R23 17 18 2.224404
+C26 19 gnd 2.080806f
+R24 18 19 2.224404
+C27 20 gnd 2.080806f
+R25 19 20 2.224404
+C28 21 gnd 2.080806f
+R26 20 21 2.224404
+R27 21 g683_6 2.224404
+.ends
+
+.subckt netg3057 g3057_1 g3057_0 gnd
+C1  g3057_1 gnd 2.080806f
+C2  g3057_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g3057_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+R24 23 g3057_1 2.224404
+.ends
+
+.subckt netg588 g588_2 g588_3 g588_1 g588_4 g588_5 g588_0 gnd
+C1  g588_2 gnd 2.080806f
+C2  g588_3 gnd 2.080806f
+C3  g588_1 gnd 2.080806f
+C4  g588_4 gnd 2.080806f
+C5  g588_5 gnd 2.080806f
+C6  g588_0 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g588_0 2.224404
+R2 g588_3 1 2.224404
+C8 2 gnd 2.080806f
+R3 2 g588_3 2.224404
+C9 3 gnd 2.080806f
+R4 3 2 2.224404
+C10 4 gnd 2.080806f
+R5 4 3 2.224404
+C11 5 gnd 2.080806f
+R6 5 4 2.224404
+C12 6 gnd 2.080806f
+R7 6 5 2.224404
+C13 7 gnd 2.080806f
+R8 7 6 2.224404
+C14 8 gnd 2.080806f
+R9 8 7 2.224404
+C15 9 gnd 2.080806f
+R10 9 8 2.224404
+C16 10 gnd 2.080806f
+R11 10 9 2.224404
+C17 11 gnd 2.080806f
+R12 11 10 2.224404
+C18 12 gnd 2.080806f
+R13 12 11 2.224404
+C19 13 gnd 2.080806f
+R14 13 12 2.224404
+C20 14 gnd 2.080806f
+R15 14 13 2.224404
+C21 15 gnd 2.080806f
+R16 15 14 2.224404
+C22 16 gnd 2.080806f
+R17 16 15 2.224404
+R18 g588_4 16 2.224404
+C23 17 gnd 2.080806f
+R19 17 g588_4 2.224404
+C24 18 gnd 2.080806f
+R20 17 18 2.224404
+R21 g588_5 18 2.224404
+R22 g588_1 g588_5 2.224404
+C25 19 gnd 2.080806f
+R23 19 g588_1 2.224404
+R24 g588_2 19 2.224404
+.ends
+
+.subckt netg6590 g6590_2 g6590_1 g6590_4 g6590_0 g6590_3 g6590_6 gnd
+C1  g6590_2 gnd 2.080806f
+C2  g6590_1 gnd 2.080806f
+C3  g6590_4 gnd 2.080806f
+C4  g6590_0 gnd 2.080806f
+C5  g6590_3 gnd 2.080806f
+C6  g6590_6 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 g6590_0 1 2.224404
+C8 2 gnd 2.080806f
+R2 1 2 2.224404
+C9 3 gnd 2.080806f
+R3 2 3 2.224404
+C10 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 4 g6590_3 2.224404
+R6 g6590_3 g6590_4 2.224404
+C11 5 gnd 2.080806f
+R7 g6590_3 5 2.224404
+C12 6 gnd 2.080806f
+R8 5 6 2.224404
+R9 6 g6590_6 2.224404
+C13 7 gnd 2.080806f
+R10 g6590_6 7 2.224404
+C14 8 gnd 2.080806f
+R11 7 8 2.224404
+C15 9 gnd 2.080806f
+R12 8 9 2.224404
+C16 10 gnd 2.080806f
+R13 9 10 2.224404
+R14 10 g6590_1 2.224404
+C17 11 gnd 2.080806f
+R15 g6590_0 11 2.224404
+C18 12 gnd 2.080806f
+R16 11 12 2.224404
+C19 13 gnd 2.080806f
+R17 12 13 2.224404
+C20 14 gnd 2.080806f
+R18 13 14 2.224404
+C21 15 gnd 2.080806f
+R19 14 15 2.224404
+C22 16 gnd 2.080806f
+R20 15 16 2.224404
+C23 17 gnd 2.080806f
+R21 16 17 2.224404
+C24 18 gnd 2.080806f
+R22 17 18 2.224404
+C25 19 gnd 2.080806f
+R23 18 19 2.224404
+C26 20 gnd 2.080806f
+R24 19 20 2.224404
+C27 21 gnd 2.080806f
+R25 20 21 2.224404
+C28 22 gnd 2.080806f
+R26 21 22 2.224404
+C29 23 gnd 2.080806f
+R27 22 23 2.224404
+R28 23 g6590_2 2.224404
+.ends
+
+.subckt netg56 g56_1 g56_0 gnd
+C1  g56_1 gnd 2.080806f
+C2  g56_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g56_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+R22 g56_1 21 2.224404
+.ends
+
+.subckt netg7497 g7497_0 g7497_1 gnd
+C1  g7497_0 gnd 2.080806f
+C2  g7497_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7497_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+R22 g7497_1 21 2.224404
+.ends
+
+.subckt netg2284 g2284_1 g2284_0 g2284_3 g2284_2 gnd
+C1  g2284_1 gnd 2.080806f
+C2  g2284_0 gnd 2.080806f
+C3  g2284_3 gnd 2.080806f
+C4  g2284_2 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g2284_0 1 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+C7 3 gnd 2.080806f
+R3 3 2 2.224404
+C8 4 gnd 2.080806f
+R4 3 4 2.224404
+C9 5 gnd 2.080806f
+R5 4 5 2.224404
+C10 6 gnd 2.080806f
+R6 5 6 2.224404
+R7 6 g2284_1 2.224404
+C11 7 gnd 2.080806f
+R8 g2284_1 7 2.224404
+C12 8 gnd 2.080806f
+R9 7 8 2.224404
+C13 9 gnd 2.080806f
+R10 8 9 2.224404
+C14 10 gnd 2.080806f
+R11 9 10 2.224404
+C15 11 gnd 2.080806f
+R12 10 11 2.224404
+R13 11 g2284_2 2.224404
+C16 12 gnd 2.080806f
+R14 12 g2284_0 2.224404
+C17 13 gnd 2.080806f
+R15 13 12 2.224404
+C18 14 gnd 2.080806f
+R16 14 13 2.224404
+C19 15 gnd 2.080806f
+R17 15 14 2.224404
+C20 16 gnd 2.080806f
+R18 16 15 2.224404
+C21 17 gnd 2.080806f
+R19 17 16 2.224404
+C22 18 gnd 2.080806f
+R20 18 17 2.224404
+C23 19 gnd 2.080806f
+R21 19 18 2.224404
+C24 20 gnd 2.080806f
+R22 20 19 2.224404
+C25 21 gnd 2.080806f
+R23 21 20 2.224404
+R24 g2284_3 21 2.224404
+.ends
+
+.subckt netg3587 g3587_8 g3587_9 g3587_2 g3587_12 g3587_0 g3587_3 g3587_13 g3587_6 g3587_11 g3587_4 g3587_10 g3587_1 g3587_7 gnd
+C1  g3587_8 gnd 2.080806f
+C2  g3587_9 gnd 2.080806f
+C3  g3587_2 gnd 2.080806f
+C4  g3587_12 gnd 2.080806f
+C5  g3587_0 gnd 2.080806f
+C6  g3587_3 gnd 2.080806f
+C7  g3587_13 gnd 2.080806f
+C8  g3587_6 gnd 2.080806f
+C9  g3587_11 gnd 2.080806f
+C10  g3587_4 gnd 2.080806f
+C11  g3587_10 gnd 2.080806f
+C12  g3587_1 gnd 2.080806f
+C13  g3587_7 gnd 2.080806f
+C14 1 gnd 2.080806f
+R1 1 g3587_0 2.224404
+R2 g3587_6 1 2.224404
+R3 g3587_3 g3587_6 2.224404
+C15 2 gnd 2.080806f
+R4 g3587_3 2 2.224404
+R5 g3587_11 2 2.224404
+C16 3 gnd 2.080806f
+R6 g3587_0 3 2.224404
+R7 3 g3587_8 2.224404
+C17 4 gnd 2.080806f
+R8 4 g3587_3 2.224404
+C18 5 gnd 2.080806f
+R9 5 4 2.224404
+R10 g3587_10 5 2.224404
+R11 g3587_9 g3587_10 2.224404
+R12 g3587_9 g3587_2 2.224404
+C19 6 gnd 2.080806f
+R13 6 g3587_2 2.224404
+R14 g3587_13 6 2.224404
+C20 7 gnd 2.080806f
+R15 g3587_2 7 2.224404
+R16 7 g3587_4 2.224404
+C21 8 gnd 2.080806f
+R17 8 g3587_13 2.224404
+C22 9 gnd 2.080806f
+R18 9 8 2.224404
+C23 10 gnd 2.080806f
+R19 10 9 2.224404
+C24 11 gnd 2.080806f
+R20 11 10 2.224404
+C25 12 gnd 2.080806f
+R21 12 11 2.224404
+C26 13 gnd 2.080806f
+R22 12 13 2.224404
+R23 g3587_12 13 2.224404
+C27 14 gnd 2.080806f
+R24 14 g3587_12 2.224404
+C28 15 gnd 2.080806f
+R25 15 14 2.224404
+C29 16 gnd 2.080806f
+R26 16 15 2.224404
+R27 g3587_7 16 2.224404
+C30 17 gnd 2.080806f
+R28 17 15 2.224404
+C31 18 gnd 2.080806f
+R29 18 17 2.224404
+R30 g3587_1 18 2.224404
+.ends
+
+.subckt netg582 g582_5 g582_4 g582_2 g582_3 g582_1 g582_0 gnd
+C1  g582_5 gnd 2.080806f
+C2  g582_4 gnd 2.080806f
+C3  g582_2 gnd 2.080806f
+C4  g582_3 gnd 2.080806f
+C5  g582_1 gnd 2.080806f
+C6  g582_0 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g582_0 2.224404
+C8 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g582_2 2.224404
+R4 g582_4 2 2.224404
+C9 3 gnd 2.080806f
+R5 g582_2 3 2.224404
+C10 4 gnd 2.080806f
+R6 3 4 2.224404
+C11 5 gnd 2.080806f
+R7 4 5 2.224404
+C12 6 gnd 2.080806f
+R8 5 6 2.224404
+C13 7 gnd 2.080806f
+R9 6 7 2.224404
+C14 8 gnd 2.080806f
+R10 7 8 2.224404
+R11 8 g582_1 2.224404
+C15 9 gnd 2.080806f
+R12 g582_2 9 2.224404
+C16 10 gnd 2.080806f
+R13 9 10 2.224404
+C17 11 gnd 2.080806f
+R14 10 11 2.224404
+C18 12 gnd 2.080806f
+R15 11 12 2.224404
+C19 13 gnd 2.080806f
+R16 12 13 2.224404
+C20 14 gnd 2.080806f
+R17 13 14 2.224404
+R18 14 g582_5 2.224404
+C21 15 gnd 2.080806f
+R19 g582_1 15 2.224404
+C22 16 gnd 2.080806f
+R20 15 16 2.224404
+C23 17 gnd 2.080806f
+R21 16 17 2.224404
+C24 18 gnd 2.080806f
+R22 17 18 2.224404
+C25 19 gnd 2.080806f
+R23 18 19 2.224404
+C26 20 gnd 2.080806f
+R24 19 20 2.224404
+C27 21 gnd 2.080806f
+R25 20 21 2.224404
+C28 22 gnd 2.080806f
+R26 21 22 2.224404
+C29 23 gnd 2.080806f
+R27 22 23 2.224404
+C30 24 gnd 2.080806f
+R28 23 24 2.224404
+C31 25 gnd 2.080806f
+R29 24 25 2.224404
+R30 25 g582_3 2.224404
+.ends
+
+.subckt netg2552 g2552_1 g2552_0 g2552_2 gnd
+C1  g2552_1 gnd 2.080806f
+C2  g2552_0 gnd 2.080806f
+C3  g2552_2 gnd 2.080806f
+R1 g2552_0 g2552_1 2.224404
+C4 1 gnd 2.080806f
+R2 1 g2552_0 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 11 10 2.224404
+C15 12 gnd 2.080806f
+R13 12 11 2.224404
+C16 13 gnd 2.080806f
+R14 13 12 2.224404
+C17 14 gnd 2.080806f
+R15 13 14 2.224404
+C18 15 gnd 2.080806f
+R16 15 14 2.224404
+C19 16 gnd 2.080806f
+R17 16 15 2.224404
+C20 17 gnd 2.080806f
+R18 17 16 2.224404
+C21 18 gnd 2.080806f
+R19 18 17 2.224404
+C22 19 gnd 2.080806f
+R20 19 18 2.224404
+C23 20 gnd 2.080806f
+R21 20 19 2.224404
+C24 21 gnd 2.080806f
+R22 21 20 2.224404
+C25 22 gnd 2.080806f
+R23 22 21 2.224404
+R24 g2552_2 22 2.224404
+.ends
+
+.subckt netg1102 g1102_4 g1102_2 g1102_1 g1102_0 g1102_3 g1102_5 gnd
+C1  g1102_4 gnd 2.080806f
+C2  g1102_2 gnd 2.080806f
+C3  g1102_1 gnd 2.080806f
+C4  g1102_0 gnd 2.080806f
+C5  g1102_3 gnd 2.080806f
+C6  g1102_5 gnd 2.080806f
+R1 g1102_4 g1102_0 2.224404
+C7 1 gnd 2.080806f
+R2 g1102_0 1 2.224404
+C8 2 gnd 2.080806f
+R3 1 2 2.224404
+R4 2 g1102_3 2.224404
+C9 3 gnd 2.080806f
+R5 3 g1102_4 2.224404
+C10 4 gnd 2.080806f
+R6 4 3 2.224404
+C11 5 gnd 2.080806f
+R7 5 4 2.224404
+C12 6 gnd 2.080806f
+R8 6 5 2.224404
+C13 7 gnd 2.080806f
+R9 6 7 2.224404
+C14 8 gnd 2.080806f
+R10 8 7 2.224404
+R11 g1102_5 8 2.224404
+C15 9 gnd 2.080806f
+R12 g1102_3 9 2.224404
+C16 10 gnd 2.080806f
+R13 9 10 2.224404
+C17 11 gnd 2.080806f
+R14 10 11 2.224404
+C18 12 gnd 2.080806f
+R15 11 12 2.224404
+C19 13 gnd 2.080806f
+R16 12 13 2.224404
+C20 14 gnd 2.080806f
+R17 13 14 2.224404
+C21 15 gnd 2.080806f
+R18 14 15 2.224404
+R19 g1102_1 15 2.224404
+C22 16 gnd 2.080806f
+R20 9 16 2.224404
+C23 17 gnd 2.080806f
+R21 16 17 2.224404
+C24 18 gnd 2.080806f
+R22 17 18 2.224404
+C25 19 gnd 2.080806f
+R23 18 19 2.224404
+C26 20 gnd 2.080806f
+R24 19 20 2.224404
+C27 21 gnd 2.080806f
+R25 21 20 2.224404
+R26 21 g1102_2 2.224404
+.ends
+
+.subckt netg7498 g7498_1 g7498_0 gnd
+C1  g7498_1 gnd 2.080806f
+C2  g7498_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7498_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+R22 21 g7498_1 2.224404
+.ends
+
+.subckt netg7510 g7510_1 g7510_0 gnd
+C1  g7510_1 gnd 2.080806f
+C2  g7510_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7510_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+R22 g7510_1 21 2.224404
+.ends
+
+.subckt netg4582 g4582_6 g4582_5 g4582_3 g4582_12 g4582_10 g4582_15 g4582_9 g4582_0 g4582_11 g4582_2 g4582_7 g4582_1 g4582_8 g4582_13 g4582_4 g4582_14 gnd
+C1  g4582_6 gnd 2.080806f
+C2  g4582_5 gnd 2.080806f
+C3  g4582_3 gnd 2.080806f
+C4  g4582_12 gnd 2.080806f
+C5  g4582_10 gnd 2.080806f
+C6  g4582_15 gnd 2.080806f
+C7  g4582_9 gnd 2.080806f
+C8  g4582_0 gnd 2.080806f
+C9  g4582_11 gnd 2.080806f
+C10  g4582_2 gnd 2.080806f
+C11  g4582_7 gnd 2.080806f
+C12  g4582_1 gnd 2.080806f
+C13  g4582_8 gnd 2.080806f
+C14  g4582_13 gnd 2.080806f
+C15  g4582_4 gnd 2.080806f
+C16  g4582_14 gnd 2.080806f
+C17 1 gnd 2.080806f
+R1 g4582_0 1 2.224404
+R2 1 g4582_11 2.224404
+C18 2 gnd 2.080806f
+R3 g4582_11 2 2.224404
+R4 2 g4582_5 2.224404
+C19 3 gnd 2.080806f
+R5 g4582_5 3 2.224404
+R6 3 g4582_8 2.224404
+C20 4 gnd 2.080806f
+R7 4 2 2.224404
+R8 g4582_2 4 2.224404
+R9 g4582_3 g4582_2 2.224404
+C21 5 gnd 2.080806f
+R10 g4582_2 5 2.224404
+R11 5 g4582_9 2.224404
+C22 6 gnd 2.080806f
+R12 6 g4582_3 2.224404
+R13 g4582_7 6 2.224404
+C23 7 gnd 2.080806f
+R14 7 g4582_3 2.224404
+R15 7 g4582_10 2.224404
+R16 g4582_10 g4582_13 2.224404
+C24 8 gnd 2.080806f
+R17 8 g4582_7 2.224404
+R18 g4582_14 8 2.224404
+R19 g4582_4 g4582_14 2.224404
+R20 g4582_12 g4582_14 2.224404
+R21 g4582_14 g4582_15 2.224404
+C25 9 gnd 2.080806f
+R22 9 g4582_12 2.224404
+C26 10 gnd 2.080806f
+R23 10 9 2.224404
+C27 11 gnd 2.080806f
+R24 11 10 2.224404
+C28 12 gnd 2.080806f
+R25 12 11 2.224404
+C29 13 gnd 2.080806f
+R26 13 12 2.224404
+C30 14 gnd 2.080806f
+R27 14 13 2.224404
+C31 15 gnd 2.080806f
+R28 15 14 2.224404
+R29 g4582_6 15 2.224404
+C32 16 gnd 2.080806f
+R30 16 g4582_6 2.224404
+C33 17 gnd 2.080806f
+R31 17 16 2.224404
+C34 18 gnd 2.080806f
+R32 18 17 2.224404
+R33 g4582_1 18 2.224404
+.ends
+
+.subckt netg46 g46_1 g46_0 gnd
+C1  g46_1 gnd 2.080806f
+C2  g46_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g46_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+R23 g46_1 22 2.224404
+.ends
+
+.subckt netg7506 g7506_1 g7506_0 gnd
+C1  g7506_1 gnd 2.080806f
+C2  g7506_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7506_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+R23 g7506_1 22 2.224404
+.ends
+
+.subckt netg2680 g2680_2 g2680_0 g2680_1 gnd
+C1  g2680_2 gnd 2.080806f
+C2  g2680_0 gnd 2.080806f
+C3  g2680_1 gnd 2.080806f
+R1 g2680_2 g2680_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g2680_2 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 11 10 2.224404
+C15 12 gnd 2.080806f
+R13 12 11 2.224404
+C16 13 gnd 2.080806f
+R14 13 12 2.224404
+C17 14 gnd 2.080806f
+R15 14 13 2.224404
+C18 15 gnd 2.080806f
+R16 15 14 2.224404
+C19 16 gnd 2.080806f
+R17 16 15 2.224404
+C20 17 gnd 2.080806f
+R18 17 16 2.224404
+C21 18 gnd 2.080806f
+R19 18 17 2.224404
+C22 19 gnd 2.080806f
+R20 19 18 2.224404
+C23 20 gnd 2.080806f
+R21 20 19 2.224404
+C24 21 gnd 2.080806f
+R22 21 20 2.224404
+C25 22 gnd 2.080806f
+R23 22 21 2.224404
+C26 23 gnd 2.080806f
+R24 23 22 2.224404
+R25 g2680_1 23 2.224404
+.ends
+
+.subckt netg594 g594_3 g594_7 g594_5 g594_2 g594_6 g594_4 g594_1 gnd
+C1  g594_3 gnd 2.080806f
+C2  g594_7 gnd 2.080806f
+C3  g594_5 gnd 2.080806f
+C4  g594_2 gnd 2.080806f
+C5  g594_6 gnd 2.080806f
+C6  g594_4 gnd 2.080806f
+C7  g594_1 gnd 2.080806f
+R1 g594_1 g594_7 2.224404
+R2 g594_7 g594_3 2.224404
+C8 1 gnd 2.080806f
+R3 g594_3 1 2.224404
+C9 2 gnd 2.080806f
+R4 1 2 2.224404
+R5 2 g594_5 2.224404
+R6 g594_2 g594_5 2.224404
+C10 3 gnd 2.080806f
+R7 g594_5 3 2.224404
+C11 4 gnd 2.080806f
+R8 3 4 2.224404
+C12 5 gnd 2.080806f
+R9 4 5 2.224404
+C13 6 gnd 2.080806f
+R10 5 6 2.224404
+C14 7 gnd 2.080806f
+R11 6 7 2.224404
+C15 8 gnd 2.080806f
+R12 7 8 2.224404
+C16 9 gnd 2.080806f
+R13 8 9 2.224404
+C17 10 gnd 2.080806f
+R14 9 10 2.224404
+C18 11 gnd 2.080806f
+R15 10 11 2.224404
+C19 12 gnd 2.080806f
+R16 11 12 2.224404
+C20 13 gnd 2.080806f
+R17 12 13 2.224404
+R18 13 g594_4 2.224404
+C21 14 gnd 2.080806f
+R19 14 g594_4 2.224404
+C22 15 gnd 2.080806f
+R20 15 14 2.224404
+C23 16 gnd 2.080806f
+R21 16 15 2.224404
+C24 17 gnd 2.080806f
+R22 17 16 2.224404
+C25 18 gnd 2.080806f
+R23 18 17 2.224404
+C26 19 gnd 2.080806f
+R24 19 18 2.224404
+R25 g594_6 19 2.224404
+.ends
+
+.subckt netg3552 g3552_1 g3552_0 gnd
+C1  g3552_1 gnd 2.080806f
+C2  g3552_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3552_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+R27 g3552_1 26 2.224404
+.ends
+
+.subckt netg842 g842_6 g842_0 g842_1 g842_4 g842_3 g842_2 g842_5 gnd
+C1  g842_6 gnd 2.080806f
+C2  g842_0 gnd 2.080806f
+C3  g842_1 gnd 2.080806f
+C4  g842_4 gnd 2.080806f
+C5  g842_3 gnd 2.080806f
+C6  g842_2 gnd 2.080806f
+C7  g842_5 gnd 2.080806f
+C8 1 gnd 2.080806f
+R1 g842_0 1 2.224404
+C9 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g842_6 2 2.224404
+C10 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g842_2 2.224404
+C11 4 gnd 2.080806f
+R6 g842_2 4 2.224404
+R7 4 g842_3 2.224404
+C12 5 gnd 2.080806f
+R8 5 g842_3 2.224404
+R9 g842_5 5 2.224404
+C13 6 gnd 2.080806f
+R10 2 6 2.224404
+C14 7 gnd 2.080806f
+R11 6 7 2.224404
+C15 8 gnd 2.080806f
+R12 7 8 2.224404
+R13 8 g842_1 2.224404
+C16 9 gnd 2.080806f
+R14 9 g842_1 2.224404
+C17 10 gnd 2.080806f
+R15 10 9 2.224404
+C18 11 gnd 2.080806f
+R16 11 10 2.224404
+C19 12 gnd 2.080806f
+R17 11 12 2.224404
+C20 13 gnd 2.080806f
+R18 13 12 2.224404
+C21 14 gnd 2.080806f
+R19 13 14 2.224404
+C22 15 gnd 2.080806f
+R20 14 15 2.224404
+C23 16 gnd 2.080806f
+R21 16 15 2.224404
+C24 17 gnd 2.080806f
+R22 17 16 2.224404
+C25 18 gnd 2.080806f
+R23 17 18 2.224404
+C26 19 gnd 2.080806f
+R24 19 18 2.224404
+C27 20 gnd 2.080806f
+R25 19 20 2.224404
+R26 g842_4 20 2.224404
+.ends
+
+.subckt netg660 g660_4 g660_1 g660_2 g660_0 g660_5 g660_3 gnd
+C1  g660_4 gnd 2.080806f
+C2  g660_1 gnd 2.080806f
+C3  g660_2 gnd 2.080806f
+C4  g660_0 gnd 2.080806f
+C5  g660_5 gnd 2.080806f
+C6  g660_3 gnd 2.080806f
+R1 g660_2 g660_0 2.224404
+C7 1 gnd 2.080806f
+R2 1 g660_2 2.224404
+C8 2 gnd 2.080806f
+R3 2 1 2.224404
+R4 g660_3 2 2.224404
+C9 3 gnd 2.080806f
+R5 g660_3 3 2.224404
+C10 4 gnd 2.080806f
+R6 3 4 2.224404
+C11 5 gnd 2.080806f
+R7 4 5 2.224404
+R8 5 g660_5 2.224404
+C12 6 gnd 2.080806f
+R9 g660_0 6 2.224404
+C13 7 gnd 2.080806f
+R10 6 7 2.224404
+C14 8 gnd 2.080806f
+R11 7 8 2.224404
+C15 9 gnd 2.080806f
+R12 8 9 2.224404
+C16 10 gnd 2.080806f
+R13 9 10 2.224404
+C17 11 gnd 2.080806f
+R14 10 11 2.224404
+C18 12 gnd 2.080806f
+R15 11 12 2.224404
+C19 13 gnd 2.080806f
+R16 12 13 2.224404
+C20 14 gnd 2.080806f
+R17 13 14 2.224404
+C21 15 gnd 2.080806f
+R18 14 15 2.224404
+C22 16 gnd 2.080806f
+R19 15 16 2.224404
+C23 17 gnd 2.080806f
+R20 16 17 2.224404
+C24 18 gnd 2.080806f
+R21 17 18 2.224404
+C25 19 gnd 2.080806f
+R22 18 19 2.224404
+C26 20 gnd 2.080806f
+R23 19 20 2.224404
+R24 20 g660_1 2.224404
+C27 21 gnd 2.080806f
+R25 20 21 2.224404
+C28 22 gnd 2.080806f
+R26 21 22 2.224404
+R27 22 g660_4 2.224404
+.ends
+
+.subckt netg2314 g2314_2 g2314_3 g2314_1 gnd
+C1  g2314_2 gnd 2.080806f
+C2  g2314_3 gnd 2.080806f
+C3  g2314_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g2314_1 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 6 5 2.224404
+C10 7 gnd 2.080806f
+R7 7 6 2.224404
+C11 8 gnd 2.080806f
+R8 8 7 2.224404
+C12 9 gnd 2.080806f
+R9 9 8 2.224404
+C13 10 gnd 2.080806f
+R10 10 9 2.224404
+C14 11 gnd 2.080806f
+R11 11 10 2.224404
+C15 12 gnd 2.080806f
+R12 12 11 2.224404
+C16 13 gnd 2.080806f
+R13 13 12 2.224404
+C17 14 gnd 2.080806f
+R14 14 13 2.224404
+C18 15 gnd 2.080806f
+R15 15 14 2.224404
+R16 g2314_3 15 2.224404
+C19 16 gnd 2.080806f
+R17 16 g2314_3 2.224404
+C20 17 gnd 2.080806f
+R18 17 16 2.224404
+C21 18 gnd 2.080806f
+R19 18 17 2.224404
+C22 19 gnd 2.080806f
+R20 19 18 2.224404
+C23 20 gnd 2.080806f
+R21 20 19 2.224404
+C24 21 gnd 2.080806f
+R22 21 20 2.224404
+C25 22 gnd 2.080806f
+R23 21 22 2.224404
+R24 g2314_2 22 2.224404
+.ends
+
+.subckt netg7495 g7495_1 g7495_0 gnd
+C1  g7495_1 gnd 2.080806f
+C2  g7495_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7495_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+R23 g7495_1 22 2.224404
+.ends
+
+.subckt netg1398 g1398_1 g1398_0 gnd
+C1  g1398_1 gnd 2.080806f
+C2  g1398_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1398_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+R23 22 g1398_1 2.224404
+.ends
+
+.subckt netg1811 g1811_3 g1811_0 g1811_2 g1811_1 gnd
+C1  g1811_3 gnd 2.080806f
+C2  g1811_0 gnd 2.080806f
+C3  g1811_2 gnd 2.080806f
+C4  g1811_1 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g1811_0 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+C7 3 gnd 2.080806f
+R3 3 2 2.224404
+C8 4 gnd 2.080806f
+R4 4 3 2.224404
+C9 5 gnd 2.080806f
+R5 5 4 2.224404
+C10 6 gnd 2.080806f
+R6 6 5 2.224404
+C11 7 gnd 2.080806f
+R7 7 6 2.224404
+C12 8 gnd 2.080806f
+R8 8 7 2.224404
+C13 9 gnd 2.080806f
+R9 9 8 2.224404
+C14 10 gnd 2.080806f
+R10 10 9 2.224404
+C15 11 gnd 2.080806f
+R11 11 10 2.224404
+R12 g1811_3 11 2.224404
+C16 12 gnd 2.080806f
+R13 g1811_3 12 2.224404
+C17 13 gnd 2.080806f
+R14 13 12 2.224404
+C18 14 gnd 2.080806f
+R15 14 13 2.224404
+C19 15 gnd 2.080806f
+R16 15 14 2.224404
+C20 16 gnd 2.080806f
+R17 16 15 2.224404
+C21 17 gnd 2.080806f
+R18 17 16 2.224404
+C22 18 gnd 2.080806f
+R19 18 17 2.224404
+C23 19 gnd 2.080806f
+R20 19 18 2.224404
+C24 20 gnd 2.080806f
+R21 20 19 2.224404
+C25 21 gnd 2.080806f
+R22 21 20 2.224404
+C26 22 gnd 2.080806f
+R23 22 21 2.224404
+R24 g1811_2 22 2.224404
+C27 23 gnd 2.080806f
+R25 22 23 2.224404
+C28 24 gnd 2.080806f
+R26 23 24 2.224404
+C29 25 gnd 2.080806f
+R27 24 25 2.224404
+C30 26 gnd 2.080806f
+R28 25 26 2.224404
+C31 27 gnd 2.080806f
+R29 26 27 2.224404
+R30 27 g1811_1 2.224404
+.ends
+
+.subckt netg1620 g1620_0 g1620_3 g1620_2 g1620_1 gnd
+C1  g1620_0 gnd 2.080806f
+C2  g1620_3 gnd 2.080806f
+C3  g1620_2 gnd 2.080806f
+C4  g1620_1 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g1620_0 1 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+C7 3 gnd 2.080806f
+R3 3 2 2.224404
+C8 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 g1620_2 4 2.224404
+C9 5 gnd 2.080806f
+R6 5 4 2.224404
+C10 6 gnd 2.080806f
+R7 6 5 2.224404
+C11 7 gnd 2.080806f
+R8 7 6 2.224404
+C12 8 gnd 2.080806f
+R9 8 7 2.224404
+C13 9 gnd 2.080806f
+R10 9 8 2.224404
+C14 10 gnd 2.080806f
+R11 10 9 2.224404
+C15 11 gnd 2.080806f
+R12 11 10 2.224404
+C16 12 gnd 2.080806f
+R13 12 11 2.224404
+C17 13 gnd 2.080806f
+R14 13 12 2.224404
+C18 14 gnd 2.080806f
+R15 14 13 2.224404
+C19 15 gnd 2.080806f
+R16 15 14 2.224404
+C20 16 gnd 2.080806f
+R17 16 15 2.224404
+C21 17 gnd 2.080806f
+R18 17 16 2.224404
+C22 18 gnd 2.080806f
+R19 18 17 2.224404
+C23 19 gnd 2.080806f
+R20 19 18 2.224404
+C24 20 gnd 2.080806f
+R21 20 19 2.224404
+C25 21 gnd 2.080806f
+R22 21 20 2.224404
+R23 g1620_3 21 2.224404
+C26 22 gnd 2.080806f
+R24 22 21 2.224404
+C27 23 gnd 2.080806f
+R25 23 22 2.224404
+C28 24 gnd 2.080806f
+R26 24 23 2.224404
+R27 24 g1620_1 2.224404
+.ends
+
+.subckt netg2276 g2276_2 g2276_1 g2276_3 g2276_0 gnd
+C1  g2276_2 gnd 2.080806f
+C2  g2276_1 gnd 2.080806f
+C3  g2276_3 gnd 2.080806f
+C4  g2276_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g2276_0 2.224404
+R2 g2276_1 1 2.224404
+C6 2 gnd 2.080806f
+R3 2 g2276_1 2.224404
+C7 3 gnd 2.080806f
+R4 3 2 2.224404
+C8 4 gnd 2.080806f
+R5 4 3 2.224404
+C9 5 gnd 2.080806f
+R6 5 4 2.224404
+C10 6 gnd 2.080806f
+R7 6 5 2.224404
+C11 7 gnd 2.080806f
+R8 7 6 2.224404
+C12 8 gnd 2.080806f
+R9 8 7 2.224404
+C13 9 gnd 2.080806f
+R10 9 8 2.224404
+C14 10 gnd 2.080806f
+R11 10 9 2.224404
+C15 11 gnd 2.080806f
+R12 11 10 2.224404
+C16 12 gnd 2.080806f
+R13 12 11 2.224404
+C17 13 gnd 2.080806f
+R14 13 12 2.224404
+C18 14 gnd 2.080806f
+R15 14 13 2.224404
+C19 15 gnd 2.080806f
+R16 15 14 2.224404
+C20 16 gnd 2.080806f
+R17 16 15 2.224404
+C21 17 gnd 2.080806f
+R18 17 16 2.224404
+C22 18 gnd 2.080806f
+R19 18 17 2.224404
+C23 19 gnd 2.080806f
+R20 19 18 2.224404
+C24 20 gnd 2.080806f
+R21 20 19 2.224404
+R22 g2276_3 20 2.224404
+C25 21 gnd 2.080806f
+R23 20 21 2.224404
+R24 21 g2276_2 2.224404
+.ends
+
+.subckt netg1116 g1116_0 g1116_1 gnd
+C1  g1116_0 gnd 2.080806f
+C2  g1116_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1116_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+R23 22 g1116_1 2.224404
+.ends
+
+.subckt netg2089 g2089_0 g2089_2 g2089_1 gnd
+C1  g2089_0 gnd 2.080806f
+C2  g2089_2 gnd 2.080806f
+C3  g2089_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g2089_0 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 5 6 2.224404
+C10 7 gnd 2.080806f
+R7 7 6 2.224404
+C11 8 gnd 2.080806f
+R8 8 7 2.224404
+C12 9 gnd 2.080806f
+R9 8 9 2.224404
+C13 10 gnd 2.080806f
+R10 9 10 2.224404
+C14 11 gnd 2.080806f
+R11 11 10 2.224404
+C15 12 gnd 2.080806f
+R12 11 12 2.224404
+C16 13 gnd 2.080806f
+R13 12 13 2.224404
+R14 13 g2089_1 2.224404
+C17 14 gnd 2.080806f
+R15 14 g2089_0 2.224404
+C18 15 gnd 2.080806f
+R16 15 14 2.224404
+C19 16 gnd 2.080806f
+R17 16 15 2.224404
+C20 17 gnd 2.080806f
+R18 17 16 2.224404
+C21 18 gnd 2.080806f
+R19 18 17 2.224404
+C22 19 gnd 2.080806f
+R20 19 18 2.224404
+C23 20 gnd 2.080806f
+R21 20 19 2.224404
+C24 21 gnd 2.080806f
+R22 21 20 2.224404
+C25 22 gnd 2.080806f
+R23 22 21 2.224404
+C26 23 gnd 2.080806f
+R24 23 22 2.224404
+C27 24 gnd 2.080806f
+R25 24 23 2.224404
+C28 25 gnd 2.080806f
+R26 25 24 2.224404
+C29 26 gnd 2.080806f
+R27 26 25 2.224404
+R28 g2089_2 26 2.224404
+.ends
+
+.subckt netg123 g123_0 g123_1 gnd
+C1  g123_0 gnd 2.080806f
+C2  g123_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g123_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+R24 g123_1 23 2.224404
+.ends
+
+.subckt netg138 g138_1 g138_0 gnd
+C1  g138_1 gnd 2.080806f
+C2  g138_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g138_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+R24 23 g138_1 2.224404
+.ends
+
+.subckt netg58 g58_1 g58_0 gnd
+C1  g58_1 gnd 2.080806f
+C2  g58_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g58_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+R24 g58_1 23 2.224404
+.ends
+
+.subckt netg4662 g4662_0 g4662_2 g4662_1 gnd
+C1  g4662_0 gnd 2.080806f
+C2  g4662_2 gnd 2.080806f
+C3  g4662_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g4662_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 5 6 2.224404
+C10 7 gnd 2.080806f
+R7 6 7 2.224404
+C11 8 gnd 2.080806f
+R8 7 8 2.224404
+C12 9 gnd 2.080806f
+R9 8 9 2.224404
+C13 10 gnd 2.080806f
+R10 10 9 2.224404
+C14 11 gnd 2.080806f
+R11 11 10 2.224404
+C15 12 gnd 2.080806f
+R12 12 11 2.224404
+C16 13 gnd 2.080806f
+R13 12 13 2.224404
+C17 14 gnd 2.080806f
+R14 13 14 2.224404
+C18 15 gnd 2.080806f
+R15 15 14 2.224404
+C19 16 gnd 2.080806f
+R16 16 15 2.224404
+C20 17 gnd 2.080806f
+R17 16 17 2.224404
+C21 18 gnd 2.080806f
+R18 17 18 2.224404
+C22 19 gnd 2.080806f
+R19 19 18 2.224404
+C23 20 gnd 2.080806f
+R20 19 20 2.224404
+R21 g4662_2 20 2.224404
+C24 21 gnd 2.080806f
+R22 20 21 2.224404
+C25 22 gnd 2.080806f
+R23 21 22 2.224404
+R24 22 g4662_1 2.224404
+.ends
+
+.subckt netg2635 g2635_0 g2635_1 g2635_2 gnd
+C1  g2635_0 gnd 2.080806f
+C2  g2635_1 gnd 2.080806f
+C3  g2635_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g2635_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g2635_2 2.224404
+C6 3 gnd 2.080806f
+R4 g2635_2 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+C8 5 gnd 2.080806f
+R6 4 5 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+C10 7 gnd 2.080806f
+R8 6 7 2.224404
+C11 8 gnd 2.080806f
+R9 7 8 2.224404
+C12 9 gnd 2.080806f
+R10 8 9 2.224404
+C13 10 gnd 2.080806f
+R11 9 10 2.224404
+C14 11 gnd 2.080806f
+R12 10 11 2.224404
+C15 12 gnd 2.080806f
+R13 11 12 2.224404
+C16 13 gnd 2.080806f
+R14 12 13 2.224404
+C17 14 gnd 2.080806f
+R15 13 14 2.224404
+C18 15 gnd 2.080806f
+R16 14 15 2.224404
+C19 16 gnd 2.080806f
+R17 15 16 2.224404
+C20 17 gnd 2.080806f
+R18 16 17 2.224404
+C21 18 gnd 2.080806f
+R19 17 18 2.224404
+C22 19 gnd 2.080806f
+R20 18 19 2.224404
+C23 20 gnd 2.080806f
+R21 19 20 2.224404
+C24 21 gnd 2.080806f
+R22 20 21 2.224404
+C25 22 gnd 2.080806f
+R23 21 22 2.224404
+R24 22 g2635_1 2.224404
+.ends
+
+.subckt netg7260 g7260_2 g7260_0 g7260_1 gnd
+C1  g7260_2 gnd 2.080806f
+C2  g7260_0 gnd 2.080806f
+C3  g7260_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g7260_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 g7260_1 4 2.224404
+C8 5 gnd 2.080806f
+R6 g7260_1 5 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 11 10 2.224404
+C15 12 gnd 2.080806f
+R13 12 11 2.224404
+C16 13 gnd 2.080806f
+R14 13 12 2.224404
+C17 14 gnd 2.080806f
+R15 13 14 2.224404
+C18 15 gnd 2.080806f
+R16 14 15 2.224404
+C19 16 gnd 2.080806f
+R17 16 15 2.224404
+C20 17 gnd 2.080806f
+R18 17 16 2.224404
+C21 18 gnd 2.080806f
+R19 18 17 2.224404
+C22 19 gnd 2.080806f
+R20 19 18 2.224404
+C23 20 gnd 2.080806f
+R21 19 20 2.224404
+C24 21 gnd 2.080806f
+R22 21 20 2.224404
+C25 22 gnd 2.080806f
+R23 22 21 2.224404
+C26 23 gnd 2.080806f
+R24 23 22 2.224404
+C27 24 gnd 2.080806f
+R25 24 23 2.224404
+R26 g7260_2 24 2.224404
+.ends
+
+.subckt netg2546 g2546_0 g2546_2 g2546_1 gnd
+C1  g2546_0 gnd 2.080806f
+C2  g2546_2 gnd 2.080806f
+C3  g2546_1 gnd 2.080806f
+R1 g2546_1 g2546_0 2.224404
+C4 1 gnd 2.080806f
+R2 1 g2546_1 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 10 11 2.224404
+C15 12 gnd 2.080806f
+R13 12 11 2.224404
+C16 13 gnd 2.080806f
+R14 13 12 2.224404
+C17 14 gnd 2.080806f
+R15 14 13 2.224404
+C18 15 gnd 2.080806f
+R16 15 14 2.224404
+C19 16 gnd 2.080806f
+R17 16 15 2.224404
+C20 17 gnd 2.080806f
+R18 16 17 2.224404
+C21 18 gnd 2.080806f
+R19 17 18 2.224404
+C22 19 gnd 2.080806f
+R20 19 18 2.224404
+C23 20 gnd 2.080806f
+R21 20 19 2.224404
+C24 21 gnd 2.080806f
+R22 21 20 2.224404
+C25 22 gnd 2.080806f
+R23 22 21 2.224404
+R24 g2546_2 22 2.224404
+.ends
+
+.subckt netg712 g712_3 g712_1 g712_0 g712_2 gnd
+C1  g712_3 gnd 2.080806f
+C2  g712_1 gnd 2.080806f
+C3  g712_0 gnd 2.080806f
+C4  g712_2 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g712_0 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+C7 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g712_3 3 2.224404
+C8 4 gnd 2.080806f
+R5 4 g712_3 2.224404
+C9 5 gnd 2.080806f
+R6 5 4 2.224404
+C10 6 gnd 2.080806f
+R7 6 5 2.224404
+C11 7 gnd 2.080806f
+R8 7 6 2.224404
+C12 8 gnd 2.080806f
+R9 8 7 2.224404
+C13 9 gnd 2.080806f
+R10 9 8 2.224404
+C14 10 gnd 2.080806f
+R11 10 9 2.224404
+C15 11 gnd 2.080806f
+R12 11 10 2.224404
+C16 12 gnd 2.080806f
+R13 12 11 2.224404
+C17 13 gnd 2.080806f
+R14 13 12 2.224404
+C18 14 gnd 2.080806f
+R15 14 13 2.224404
+C19 15 gnd 2.080806f
+R16 15 14 2.224404
+C20 16 gnd 2.080806f
+R17 16 15 2.224404
+C21 17 gnd 2.080806f
+R18 17 16 2.224404
+C22 18 gnd 2.080806f
+R19 18 17 2.224404
+C23 19 gnd 2.080806f
+R20 19 18 2.224404
+C24 20 gnd 2.080806f
+R21 20 19 2.224404
+C25 21 gnd 2.080806f
+R22 21 20 2.224404
+R23 g712_2 21 2.224404
+R24 g712_1 g712_2 2.224404
+.ends
+
+.subckt netg1905 g1905_1 g1905_0 gnd
+C1  g1905_1 gnd 2.080806f
+C2  g1905_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1905_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+R24 g1905_1 23 2.224404
+.ends
+
+.subckt netg21 g21_0 g21_1 gnd
+C1  g21_0 gnd 2.080806f
+C2  g21_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g21_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+R24 g21_1 23 2.224404
+.ends
+
+.subckt netg7493 g7493_1 g7493_0 gnd
+C1  g7493_1 gnd 2.080806f
+C2  g7493_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7493_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+R24 23 g7493_1 2.224404
+.ends
+
+.subckt netg139 g139_1 g139_0 gnd
+C1  g139_1 gnd 2.080806f
+C2  g139_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g139_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+R25 24 g139_1 2.224404
+.ends
+
+.subckt netg2107 g2107_3 g2107_1 g2107_0 g2107_2 gnd
+C1  g2107_3 gnd 2.080806f
+C2  g2107_1 gnd 2.080806f
+C3  g2107_0 gnd 2.080806f
+C4  g2107_2 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g2107_0 1 2.224404
+R2 g2107_1 1 2.224404
+C6 2 gnd 2.080806f
+R3 1 2 2.224404
+C7 3 gnd 2.080806f
+R4 2 3 2.224404
+C8 4 gnd 2.080806f
+R5 3 4 2.224404
+C9 5 gnd 2.080806f
+R6 4 5 2.224404
+C10 6 gnd 2.080806f
+R7 5 6 2.224404
+C11 7 gnd 2.080806f
+R8 6 7 2.224404
+C12 8 gnd 2.080806f
+R9 7 8 2.224404
+C13 9 gnd 2.080806f
+R10 8 9 2.224404
+C14 10 gnd 2.080806f
+R11 9 10 2.224404
+C15 11 gnd 2.080806f
+R12 10 11 2.224404
+C16 12 gnd 2.080806f
+R13 11 12 2.224404
+C17 13 gnd 2.080806f
+R14 12 13 2.224404
+C18 14 gnd 2.080806f
+R15 13 14 2.224404
+C19 15 gnd 2.080806f
+R16 14 15 2.224404
+C20 16 gnd 2.080806f
+R17 15 16 2.224404
+C21 17 gnd 2.080806f
+R18 16 17 2.224404
+C22 18 gnd 2.080806f
+R19 17 18 2.224404
+C23 19 gnd 2.080806f
+R20 18 19 2.224404
+C24 20 gnd 2.080806f
+R21 19 20 2.224404
+R22 20 g2107_2 2.224404
+C25 21 gnd 2.080806f
+R23 g2107_2 21 2.224404
+C26 22 gnd 2.080806f
+R24 21 22 2.224404
+R25 22 g2107_3 2.224404
+.ends
+
+.subckt netg1904 g1904_1 g1904_0 gnd
+C1  g1904_1 gnd 2.080806f
+C2  g1904_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1904_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+R25 g1904_1 24 2.224404
+.ends
+
+.subckt netg5968 g5968_0 g5968_1 gnd
+C1  g5968_0 gnd 2.080806f
+C2  g5968_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5968_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+R25 24 g5968_1 2.224404
+.ends
+
+.subckt netg1782 g1782_3 g1782_1 g1782_0 g1782_2 gnd
+C1  g1782_3 gnd 2.080806f
+C2  g1782_1 gnd 2.080806f
+C3  g1782_0 gnd 2.080806f
+C4  g1782_2 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g1782_0 1 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+C7 3 gnd 2.080806f
+R3 2 3 2.224404
+C8 4 gnd 2.080806f
+R4 3 4 2.224404
+C9 5 gnd 2.080806f
+R5 4 5 2.224404
+C10 6 gnd 2.080806f
+R6 5 6 2.224404
+C11 7 gnd 2.080806f
+R7 6 7 2.224404
+C12 8 gnd 2.080806f
+R8 7 8 2.224404
+C13 9 gnd 2.080806f
+R9 8 9 2.224404
+C14 10 gnd 2.080806f
+R10 9 10 2.224404
+C15 11 gnd 2.080806f
+R11 10 11 2.224404
+C16 12 gnd 2.080806f
+R12 11 12 2.224404
+C17 13 gnd 2.080806f
+R13 12 13 2.224404
+C18 14 gnd 2.080806f
+R14 13 14 2.224404
+C19 15 gnd 2.080806f
+R15 15 14 2.224404
+C20 16 gnd 2.080806f
+R16 15 16 2.224404
+C21 17 gnd 2.080806f
+R17 16 17 2.224404
+C22 18 gnd 2.080806f
+R18 17 18 2.224404
+C23 19 gnd 2.080806f
+R19 18 19 2.224404
+C24 20 gnd 2.080806f
+R20 19 20 2.224404
+C25 21 gnd 2.080806f
+R21 20 21 2.224404
+C26 22 gnd 2.080806f
+R22 21 22 2.224404
+C27 23 gnd 2.080806f
+R23 23 22 2.224404
+R24 23 g1782_3 2.224404
+C28 24 gnd 2.080806f
+R25 24 g1782_3 2.224404
+C29 25 gnd 2.080806f
+R26 25 24 2.224404
+R27 25 g1782_2 2.224404
+C30 26 gnd 2.080806f
+R28 26 g1782_2 2.224404
+R29 g1782_1 26 2.224404
+.ends
+
+.subckt netg4784 g4784_3 g4784_2 g4784_4 g4784_1 g4784_6 g4784_5 g4784_0 gnd
+C1  g4784_3 gnd 2.080806f
+C2  g4784_2 gnd 2.080806f
+C3  g4784_4 gnd 2.080806f
+C4  g4784_1 gnd 2.080806f
+C5  g4784_6 gnd 2.080806f
+C6  g4784_5 gnd 2.080806f
+C7  g4784_0 gnd 2.080806f
+C8 1 gnd 2.080806f
+R1 1 g4784_0 2.224404
+C9 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g4784_1 2 2.224404
+C10 3 gnd 2.080806f
+R4 g4784_1 3 2.224404
+R5 g4784_5 3 2.224404
+C11 4 gnd 2.080806f
+R6 4 1 2.224404
+C12 5 gnd 2.080806f
+R7 5 4 2.224404
+C13 6 gnd 2.080806f
+R8 6 5 2.224404
+R9 6 g4784_6 2.224404
+C14 7 gnd 2.080806f
+R10 7 g4784_6 2.224404
+C15 8 gnd 2.080806f
+R11 8 7 2.224404
+C16 9 gnd 2.080806f
+R12 8 9 2.224404
+R13 9 g4784_2 2.224404
+C17 10 gnd 2.080806f
+R14 10 8 2.224404
+R15 g4784_4 10 2.224404
+C18 11 gnd 2.080806f
+R16 11 g4784_5 2.224404
+C19 12 gnd 2.080806f
+R17 12 11 2.224404
+C20 13 gnd 2.080806f
+R18 13 12 2.224404
+C21 14 gnd 2.080806f
+R19 14 13 2.224404
+C22 15 gnd 2.080806f
+R20 15 14 2.224404
+C23 16 gnd 2.080806f
+R21 16 15 2.224404
+C24 17 gnd 2.080806f
+R22 17 16 2.224404
+C25 18 gnd 2.080806f
+R23 18 17 2.224404
+C26 19 gnd 2.080806f
+R24 19 18 2.224404
+C27 20 gnd 2.080806f
+R25 20 19 2.224404
+C28 21 gnd 2.080806f
+R26 21 20 2.224404
+R27 g4784_3 21 2.224404
+.ends
+
+.subckt netg7496 g7496_1 g7496_0 gnd
+C1  g7496_1 gnd 2.080806f
+C2  g7496_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7496_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+R25 g7496_1 24 2.224404
+.ends
+
+.subckt netg1628 g1628_1 g1628_0 g1628_2 g1628_3 gnd
+C1  g1628_1 gnd 2.080806f
+C2  g1628_0 gnd 2.080806f
+C3  g1628_2 gnd 2.080806f
+C4  g1628_3 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g1628_0 1 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+C7 3 gnd 2.080806f
+R3 2 3 2.224404
+C8 4 gnd 2.080806f
+R4 3 4 2.224404
+C9 5 gnd 2.080806f
+R5 5 4 2.224404
+R6 g1628_1 5 2.224404
+C10 6 gnd 2.080806f
+R7 4 6 2.224404
+C11 7 gnd 2.080806f
+R8 6 7 2.224404
+C12 8 gnd 2.080806f
+R9 7 8 2.224404
+C13 9 gnd 2.080806f
+R10 8 9 2.224404
+C14 10 gnd 2.080806f
+R11 9 10 2.224404
+C15 11 gnd 2.080806f
+R12 10 11 2.224404
+C16 12 gnd 2.080806f
+R13 11 12 2.224404
+R14 12 g1628_2 2.224404
+C17 13 gnd 2.080806f
+R15 13 1 2.224404
+C18 14 gnd 2.080806f
+R16 14 13 2.224404
+C19 15 gnd 2.080806f
+R17 15 14 2.224404
+C20 16 gnd 2.080806f
+R18 16 15 2.224404
+C21 17 gnd 2.080806f
+R19 17 16 2.224404
+C22 18 gnd 2.080806f
+R20 18 17 2.224404
+C23 19 gnd 2.080806f
+R21 19 18 2.224404
+C24 20 gnd 2.080806f
+R22 20 19 2.224404
+C25 21 gnd 2.080806f
+R23 21 20 2.224404
+C26 22 gnd 2.080806f
+R24 22 21 2.224404
+C27 23 gnd 2.080806f
+R25 23 22 2.224404
+C28 24 gnd 2.080806f
+R26 24 23 2.224404
+C29 25 gnd 2.080806f
+R27 25 24 2.224404
+C30 26 gnd 2.080806f
+R28 26 25 2.224404
+C31 27 gnd 2.080806f
+R29 27 26 2.224404
+R30 27 g1628_3 2.224404
+.ends
+
+.subckt netg1828 g1828_2 g1828_1 g1828_0 g1828_3 gnd
+C1  g1828_2 gnd 2.080806f
+C2  g1828_1 gnd 2.080806f
+C3  g1828_0 gnd 2.080806f
+C4  g1828_3 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g1828_0 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+C7 3 gnd 2.080806f
+R3 3 2 2.224404
+C8 4 gnd 2.080806f
+R4 4 3 2.224404
+C9 5 gnd 2.080806f
+R5 5 4 2.224404
+C10 6 gnd 2.080806f
+R6 6 5 2.224404
+C11 7 gnd 2.080806f
+R7 7 6 2.224404
+R8 g1828_1 7 2.224404
+C12 8 gnd 2.080806f
+R9 8 g1828_1 2.224404
+C13 9 gnd 2.080806f
+R10 9 8 2.224404
+C14 10 gnd 2.080806f
+R11 9 10 2.224404
+C15 11 gnd 2.080806f
+R12 10 11 2.224404
+C16 12 gnd 2.080806f
+R13 12 11 2.224404
+C17 13 gnd 2.080806f
+R14 12 13 2.224404
+R15 g1828_3 13 2.224404
+C18 14 gnd 2.080806f
+R16 g1828_0 14 2.224404
+C19 15 gnd 2.080806f
+R17 14 15 2.224404
+C20 16 gnd 2.080806f
+R18 15 16 2.224404
+C21 17 gnd 2.080806f
+R19 16 17 2.224404
+C22 18 gnd 2.080806f
+R20 18 17 2.224404
+C23 19 gnd 2.080806f
+R21 18 19 2.224404
+C24 20 gnd 2.080806f
+R22 19 20 2.224404
+C25 21 gnd 2.080806f
+R23 20 21 2.224404
+C26 22 gnd 2.080806f
+R24 22 21 2.224404
+C27 23 gnd 2.080806f
+R25 22 23 2.224404
+C28 24 gnd 2.080806f
+R26 23 24 2.224404
+R27 24 g1828_2 2.224404
+.ends
+
+.subckt netg6234 g6234_0 g6234_1 g6234_2 gnd
+C1  g6234_0 gnd 2.080806f
+C2  g6234_1 gnd 2.080806f
+C3  g6234_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g6234_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+C8 5 gnd 2.080806f
+R5 4 5 2.224404
+C9 6 gnd 2.080806f
+R6 6 5 2.224404
+C10 7 gnd 2.080806f
+R7 7 6 2.224404
+C11 8 gnd 2.080806f
+R8 8 7 2.224404
+C12 9 gnd 2.080806f
+R9 9 8 2.224404
+C13 10 gnd 2.080806f
+R10 10 9 2.224404
+C14 11 gnd 2.080806f
+R11 11 10 2.224404
+C15 12 gnd 2.080806f
+R12 12 11 2.224404
+C16 13 gnd 2.080806f
+R13 12 13 2.224404
+C17 14 gnd 2.080806f
+R14 14 13 2.224404
+C18 15 gnd 2.080806f
+R15 15 14 2.224404
+C19 16 gnd 2.080806f
+R16 16 15 2.224404
+C20 17 gnd 2.080806f
+R17 17 16 2.224404
+C21 18 gnd 2.080806f
+R18 18 17 2.224404
+C22 19 gnd 2.080806f
+R19 19 18 2.224404
+C23 20 gnd 2.080806f
+R20 20 19 2.224404
+R21 g6234_1 20 2.224404
+C24 21 gnd 2.080806f
+R22 g6234_1 21 2.224404
+C25 22 gnd 2.080806f
+R23 22 21 2.224404
+C26 23 gnd 2.080806f
+R24 22 23 2.224404
+R25 g6234_2 23 2.224404
+.ends
+
+.subckt netg7494 g7494_1 g7494_0 gnd
+C1  g7494_1 gnd 2.080806f
+C2  g7494_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7494_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+R25 g7494_1 24 2.224404
+.ends
+
+.subckt netg721 g721_3 g721_0 g721_5 g721_1 g721_2 g721_4 gnd
+C1  g721_3 gnd 2.080806f
+C2  g721_0 gnd 2.080806f
+C3  g721_5 gnd 2.080806f
+C4  g721_1 gnd 2.080806f
+C5  g721_2 gnd 2.080806f
+C6  g721_4 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 g721_0 1 2.224404
+C8 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g721_4 2.224404
+C9 3 gnd 2.080806f
+R4 3 g721_0 2.224404
+C10 4 gnd 2.080806f
+R5 4 3 2.224404
+C11 5 gnd 2.080806f
+R6 5 4 2.224404
+C12 6 gnd 2.080806f
+R7 6 5 2.224404
+C13 7 gnd 2.080806f
+R8 7 6 2.224404
+C14 8 gnd 2.080806f
+R9 8 7 2.224404
+C15 9 gnd 2.080806f
+R10 9 8 2.224404
+C16 10 gnd 2.080806f
+R11 10 9 2.224404
+C17 11 gnd 2.080806f
+R12 11 10 2.224404
+C18 12 gnd 2.080806f
+R13 12 11 2.224404
+C19 13 gnd 2.080806f
+R14 12 13 2.224404
+C20 14 gnd 2.080806f
+R15 14 13 2.224404
+R16 g721_2 14 2.224404
+C21 15 gnd 2.080806f
+R17 15 g721_2 2.224404
+C22 16 gnd 2.080806f
+R18 16 15 2.224404
+C23 17 gnd 2.080806f
+R19 17 16 2.224404
+C24 18 gnd 2.080806f
+R20 18 17 2.224404
+C25 19 gnd 2.080806f
+R21 19 18 2.224404
+C26 20 gnd 2.080806f
+R22 20 19 2.224404
+C27 21 gnd 2.080806f
+R23 21 20 2.224404
+C28 22 gnd 2.080806f
+R24 22 21 2.224404
+C29 23 gnd 2.080806f
+R25 23 22 2.224404
+R26 23 g721_5 2.224404
+C30 24 gnd 2.080806f
+R27 24 g721_5 2.224404
+R28 g721_3 24 2.224404
+R29 g721_1 g721_3 2.224404
+.ends
+
+.subckt netg3294 g3294_0 g3294_2 g3294_1 gnd
+C1  g3294_0 gnd 2.080806f
+C2  g3294_2 gnd 2.080806f
+C3  g3294_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g3294_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+C8 5 gnd 2.080806f
+R5 4 5 2.224404
+C9 6 gnd 2.080806f
+R6 5 6 2.224404
+C10 7 gnd 2.080806f
+R7 6 7 2.224404
+C11 8 gnd 2.080806f
+R8 7 8 2.224404
+C12 9 gnd 2.080806f
+R9 8 9 2.224404
+C13 10 gnd 2.080806f
+R10 9 10 2.224404
+C14 11 gnd 2.080806f
+R11 11 10 2.224404
+C15 12 gnd 2.080806f
+R12 11 12 2.224404
+C16 13 gnd 2.080806f
+R13 12 13 2.224404
+C17 14 gnd 2.080806f
+R14 13 14 2.224404
+C18 15 gnd 2.080806f
+R15 14 15 2.224404
+R16 15 g3294_2 2.224404
+C19 16 gnd 2.080806f
+R17 g3294_2 16 2.224404
+C20 17 gnd 2.080806f
+R18 16 17 2.224404
+C21 18 gnd 2.080806f
+R19 17 18 2.224404
+C22 19 gnd 2.080806f
+R20 18 19 2.224404
+C23 20 gnd 2.080806f
+R21 19 20 2.224404
+C24 21 gnd 2.080806f
+R22 20 21 2.224404
+C25 22 gnd 2.080806f
+R23 21 22 2.224404
+C26 23 gnd 2.080806f
+R24 23 22 2.224404
+C27 24 gnd 2.080806f
+R25 23 24 2.224404
+C28 25 gnd 2.080806f
+R26 24 25 2.224404
+C29 26 gnd 2.080806f
+R27 25 26 2.224404
+C30 27 gnd 2.080806f
+R28 26 27 2.224404
+R29 27 g3294_1 2.224404
+.ends
+
+.subckt netg43 g43_0 g43_1 gnd
+C1  g43_0 gnd 2.080806f
+C2  g43_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g43_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+R25 24 g43_1 2.224404
+.ends
+
+.subckt netg5185 g5185_2 g5185_1 g5185_0 gnd
+C1  g5185_2 gnd 2.080806f
+C2  g5185_1 gnd 2.080806f
+C3  g5185_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5185_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g5185_1 2.224404
+C6 3 gnd 2.080806f
+R4 3 g5185_0 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 7 8 2.224404
+C12 9 gnd 2.080806f
+R10 8 9 2.224404
+C13 10 gnd 2.080806f
+R11 9 10 2.224404
+C14 11 gnd 2.080806f
+R12 10 11 2.224404
+C15 12 gnd 2.080806f
+R13 11 12 2.224404
+C16 13 gnd 2.080806f
+R14 13 12 2.224404
+C17 14 gnd 2.080806f
+R15 14 13 2.224404
+C18 15 gnd 2.080806f
+R16 15 14 2.224404
+C19 16 gnd 2.080806f
+R17 15 16 2.224404
+C20 17 gnd 2.080806f
+R18 16 17 2.224404
+C21 18 gnd 2.080806f
+R19 17 18 2.224404
+C22 19 gnd 2.080806f
+R20 19 18 2.224404
+C23 20 gnd 2.080806f
+R21 20 19 2.224404
+C24 21 gnd 2.080806f
+R22 21 20 2.224404
+C25 22 gnd 2.080806f
+R23 22 21 2.224404
+C26 23 gnd 2.080806f
+R24 22 23 2.224404
+C27 24 gnd 2.080806f
+R25 23 24 2.224404
+R26 g5185_2 24 2.224404
+.ends
+
+.subckt netg3956 g3956_3 g3956_2 g3956_0 g3956_4 gnd
+C1  g3956_3 gnd 2.080806f
+C2  g3956_2 gnd 2.080806f
+C3  g3956_0 gnd 2.080806f
+C4  g3956_4 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g3956_0 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+C7 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 3 g3956_4 2.224404
+R5 g3956_3 3 2.224404
+C8 4 gnd 2.080806f
+R6 4 g3956_0 2.224404
+C9 5 gnd 2.080806f
+R7 5 4 2.224404
+C10 6 gnd 2.080806f
+R8 6 5 2.224404
+C11 7 gnd 2.080806f
+R9 7 6 2.224404
+C12 8 gnd 2.080806f
+R10 8 7 2.224404
+C13 9 gnd 2.080806f
+R11 9 8 2.224404
+C14 10 gnd 2.080806f
+R12 10 9 2.224404
+C15 11 gnd 2.080806f
+R13 11 10 2.224404
+C16 12 gnd 2.080806f
+R14 12 11 2.224404
+C17 13 gnd 2.080806f
+R15 13 12 2.224404
+C18 14 gnd 2.080806f
+R16 14 13 2.224404
+C19 15 gnd 2.080806f
+R17 15 14 2.224404
+C20 16 gnd 2.080806f
+R18 15 16 2.224404
+C21 17 gnd 2.080806f
+R19 17 16 2.224404
+C22 18 gnd 2.080806f
+R20 17 18 2.224404
+C23 19 gnd 2.080806f
+R21 19 18 2.224404
+C24 20 gnd 2.080806f
+R22 20 19 2.224404
+C25 21 gnd 2.080806f
+R23 21 20 2.224404
+C26 22 gnd 2.080806f
+R24 22 21 2.224404
+C27 23 gnd 2.080806f
+R25 23 22 2.224404
+C28 24 gnd 2.080806f
+R26 24 23 2.224404
+C29 25 gnd 2.080806f
+R27 25 24 2.224404
+C30 26 gnd 2.080806f
+R28 26 25 2.224404
+C31 27 gnd 2.080806f
+R29 27 26 2.224404
+R30 g3956_2 27 2.224404
+.ends
+
+.subckt netg512 g512_4 g512_3 g512_1 g512_0 gnd
+C1  g512_4 gnd 2.080806f
+C2  g512_3 gnd 2.080806f
+C3  g512_1 gnd 2.080806f
+C4  g512_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g512_0 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g512_1 2.224404
+C7 3 gnd 2.080806f
+R4 3 1 2.224404
+C8 4 gnd 2.080806f
+R5 4 3 2.224404
+C9 5 gnd 2.080806f
+R6 5 4 2.224404
+C10 6 gnd 2.080806f
+R7 6 5 2.224404
+C11 7 gnd 2.080806f
+R8 7 6 2.224404
+C12 8 gnd 2.080806f
+R9 8 7 2.224404
+C13 9 gnd 2.080806f
+R10 9 8 2.224404
+C14 10 gnd 2.080806f
+R11 10 9 2.224404
+C15 11 gnd 2.080806f
+R12 11 10 2.224404
+R13 g512_3 11 2.224404
+C16 12 gnd 2.080806f
+R14 g512_1 12 2.224404
+C17 13 gnd 2.080806f
+R15 12 13 2.224404
+C18 14 gnd 2.080806f
+R16 13 14 2.224404
+C19 15 gnd 2.080806f
+R17 14 15 2.224404
+C20 16 gnd 2.080806f
+R18 15 16 2.224404
+C21 17 gnd 2.080806f
+R19 16 17 2.224404
+C22 18 gnd 2.080806f
+R20 17 18 2.224404
+C23 19 gnd 2.080806f
+R21 18 19 2.224404
+C24 20 gnd 2.080806f
+R22 19 20 2.224404
+C25 21 gnd 2.080806f
+R23 20 21 2.224404
+C26 22 gnd 2.080806f
+R24 21 22 2.224404
+C27 23 gnd 2.080806f
+R25 22 23 2.224404
+R26 23 g512_4 2.224404
+.ends
+
+.subckt netg7507 g7507_1 g7507_0 gnd
+C1  g7507_1 gnd 2.080806f
+C2  g7507_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7507_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+R25 24 g7507_1 2.224404
+.ends
+
+.subckt netg42 g42_1 g42_0 gnd
+C1  g42_1 gnd 2.080806f
+C2  g42_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g42_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+R26 g42_1 25 2.224404
+.ends
+
+.subckt netg7548 g7548_0 g7548_1 gnd
+C1  g7548_0 gnd 2.080806f
+C2  g7548_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7548_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+R26 25 g7548_1 2.224404
+.ends
+
+.subckt netg2111 g2111_3 g2111_0 g2111_2 g2111_1 gnd
+C1  g2111_3 gnd 2.080806f
+C2  g2111_0 gnd 2.080806f
+C3  g2111_2 gnd 2.080806f
+C4  g2111_1 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g2111_0 1 2.224404
+R2 g2111_2 1 2.224404
+C6 2 gnd 2.080806f
+R3 2 g2111_0 2.224404
+C7 3 gnd 2.080806f
+R4 3 2 2.224404
+R5 3 g2111_3 2.224404
+C8 4 gnd 2.080806f
+R6 1 4 2.224404
+C9 5 gnd 2.080806f
+R7 4 5 2.224404
+C10 6 gnd 2.080806f
+R8 5 6 2.224404
+C11 7 gnd 2.080806f
+R9 6 7 2.224404
+C12 8 gnd 2.080806f
+R10 7 8 2.224404
+C13 9 gnd 2.080806f
+R11 8 9 2.224404
+C14 10 gnd 2.080806f
+R12 9 10 2.224404
+C15 11 gnd 2.080806f
+R13 10 11 2.224404
+C16 12 gnd 2.080806f
+R14 11 12 2.224404
+C17 13 gnd 2.080806f
+R15 12 13 2.224404
+C18 14 gnd 2.080806f
+R16 13 14 2.224404
+C19 15 gnd 2.080806f
+R17 14 15 2.224404
+C20 16 gnd 2.080806f
+R18 15 16 2.224404
+C21 17 gnd 2.080806f
+R19 16 17 2.224404
+C22 18 gnd 2.080806f
+R20 17 18 2.224404
+C23 19 gnd 2.080806f
+R21 18 19 2.224404
+C24 20 gnd 2.080806f
+R22 19 20 2.224404
+C25 21 gnd 2.080806f
+R23 20 21 2.224404
+C26 22 gnd 2.080806f
+R24 21 22 2.224404
+C27 23 gnd 2.080806f
+R25 22 23 2.224404
+C28 24 gnd 2.080806f
+R26 23 24 2.224404
+R27 24 g2111_1 2.224404
+.ends
+
+.subckt netg55 g55_1 g55_0 gnd
+C1  g55_1 gnd 2.080806f
+C2  g55_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g55_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+R26 g55_1 25 2.224404
+.ends
+
+.subckt netg1862 g1862_2 g1862_1 g1862_0 gnd
+C1  g1862_2 gnd 2.080806f
+C2  g1862_1 gnd 2.080806f
+C3  g1862_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g1862_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+C8 5 gnd 2.080806f
+R5 4 5 2.224404
+C9 6 gnd 2.080806f
+R6 5 6 2.224404
+C10 7 gnd 2.080806f
+R7 6 7 2.224404
+C11 8 gnd 2.080806f
+R8 7 8 2.224404
+C12 9 gnd 2.080806f
+R9 8 9 2.224404
+C13 10 gnd 2.080806f
+R10 9 10 2.224404
+C14 11 gnd 2.080806f
+R11 10 11 2.224404
+C15 12 gnd 2.080806f
+R12 11 12 2.224404
+C16 13 gnd 2.080806f
+R13 12 13 2.224404
+C17 14 gnd 2.080806f
+R14 13 14 2.224404
+C18 15 gnd 2.080806f
+R15 14 15 2.224404
+C19 16 gnd 2.080806f
+R16 15 16 2.224404
+C20 17 gnd 2.080806f
+R17 16 17 2.224404
+C21 18 gnd 2.080806f
+R18 17 18 2.224404
+C22 19 gnd 2.080806f
+R19 18 19 2.224404
+C23 20 gnd 2.080806f
+R20 19 20 2.224404
+C24 21 gnd 2.080806f
+R21 20 21 2.224404
+C25 22 gnd 2.080806f
+R22 21 22 2.224404
+C26 23 gnd 2.080806f
+R23 22 23 2.224404
+C27 24 gnd 2.080806f
+R24 23 24 2.224404
+R25 24 g1862_1 2.224404
+R26 g1862_1 g1862_2 2.224404
+.ends
+
+.subckt netg101 g101_0 g101_1 gnd
+C1  g101_0 gnd 2.080806f
+C2  g101_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g101_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+R26 g101_1 25 2.224404
+.ends
+
+.subckt netg3950 g3950_5 g3950_1 g3950_4 g3950_2 g3950_3 g3950_0 gnd
+C1  g3950_5 gnd 2.080806f
+C2  g3950_1 gnd 2.080806f
+C3  g3950_4 gnd 2.080806f
+C4  g3950_2 gnd 2.080806f
+C5  g3950_3 gnd 2.080806f
+C6  g3950_0 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g3950_0 2.224404
+R2 g3950_5 1 2.224404
+C8 2 gnd 2.080806f
+R3 g3950_5 2 2.224404
+R4 2 g3950_2 2.224404
+C9 3 gnd 2.080806f
+R5 3 g3950_5 2.224404
+C10 4 gnd 2.080806f
+R6 4 3 2.224404
+C11 5 gnd 2.080806f
+R7 5 4 2.224404
+C12 6 gnd 2.080806f
+R8 6 5 2.224404
+C13 7 gnd 2.080806f
+R9 7 6 2.224404
+C14 8 gnd 2.080806f
+R10 8 7 2.224404
+C15 9 gnd 2.080806f
+R11 9 8 2.224404
+C16 10 gnd 2.080806f
+R12 10 9 2.224404
+C17 11 gnd 2.080806f
+R13 11 10 2.224404
+R14 g3950_1 11 2.224404
+R15 g3950_3 g3950_1 2.224404
+C18 12 gnd 2.080806f
+R16 12 g3950_3 2.224404
+C19 13 gnd 2.080806f
+R17 12 13 2.224404
+C20 14 gnd 2.080806f
+R18 13 14 2.224404
+C21 15 gnd 2.080806f
+R19 15 14 2.224404
+C22 16 gnd 2.080806f
+R20 16 15 2.224404
+C23 17 gnd 2.080806f
+R21 17 16 2.224404
+C24 18 gnd 2.080806f
+R22 18 17 2.224404
+C25 19 gnd 2.080806f
+R23 18 19 2.224404
+C26 20 gnd 2.080806f
+R24 19 20 2.224404
+C27 21 gnd 2.080806f
+R25 21 20 2.224404
+C28 22 gnd 2.080806f
+R26 22 21 2.224404
+C29 23 gnd 2.080806f
+R27 23 22 2.224404
+C30 24 gnd 2.080806f
+R28 24 23 2.224404
+R29 g3950_4 24 2.224404
+.ends
+
+.subckt netg1118 g1118_0 g1118_1 gnd
+C1  g1118_0 gnd 2.080806f
+C2  g1118_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g1118_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+R26 g1118_1 25 2.224404
+.ends
+
+.subckt netg640 g640_0 g640_3 g640_5 g640_1 g640_2 g640_4 gnd
+C1  g640_0 gnd 2.080806f
+C2  g640_3 gnd 2.080806f
+C3  g640_5 gnd 2.080806f
+C4  g640_1 gnd 2.080806f
+C5  g640_2 gnd 2.080806f
+C6  g640_4 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 g640_0 1 2.224404
+C8 2 gnd 2.080806f
+R2 1 2 2.224404
+C9 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g640_1 2.224404
+C10 4 gnd 2.080806f
+R5 1 4 2.224404
+C11 5 gnd 2.080806f
+R6 4 5 2.224404
+R7 5 g640_3 2.224404
+C12 6 gnd 2.080806f
+R8 g640_3 6 2.224404
+C13 7 gnd 2.080806f
+R9 6 7 2.224404
+C14 8 gnd 2.080806f
+R10 8 7 2.224404
+C15 9 gnd 2.080806f
+R11 8 9 2.224404
+R12 g640_2 9 2.224404
+C16 10 gnd 2.080806f
+R13 10 g640_2 2.224404
+C17 11 gnd 2.080806f
+R14 11 10 2.224404
+C18 12 gnd 2.080806f
+R15 11 12 2.224404
+C19 13 gnd 2.080806f
+R16 13 12 2.224404
+C20 14 gnd 2.080806f
+R17 14 13 2.224404
+C21 15 gnd 2.080806f
+R18 14 15 2.224404
+C22 16 gnd 2.080806f
+R19 16 15 2.224404
+C23 17 gnd 2.080806f
+R20 16 17 2.224404
+C24 18 gnd 2.080806f
+R21 17 18 2.224404
+C25 19 gnd 2.080806f
+R22 19 18 2.224404
+C26 20 gnd 2.080806f
+R23 19 20 2.224404
+R24 g640_5 20 2.224404
+C27 21 gnd 2.080806f
+R25 g640_5 21 2.224404
+C28 22 gnd 2.080806f
+R26 21 22 2.224404
+R27 22 g640_4 2.224404
+.ends
+
+.subckt netg7552 g7552_1 g7552_0 gnd
+C1  g7552_1 gnd 2.080806f
+C2  g7552_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7552_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+R26 25 g7552_1 2.224404
+.ends
+
+.subckt netg48 g48_0 g48_1 gnd
+C1  g48_0 gnd 2.080806f
+C2  g48_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g48_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+R26 25 g48_1 2.224404
+.ends
+
+.subckt netg111 g111_0 g111_1 gnd
+C1  g111_0 gnd 2.080806f
+C2  g111_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g111_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+R26 25 g111_1 2.224404
+.ends
+
+.subckt netg1178 g1178_6 g1178_3 g1178_4 g1178_0 g1178_5 g1178_2 g1178_1 gnd
+C1  g1178_6 gnd 2.080806f
+C2  g1178_3 gnd 2.080806f
+C3  g1178_4 gnd 2.080806f
+C4  g1178_0 gnd 2.080806f
+C5  g1178_5 gnd 2.080806f
+C6  g1178_2 gnd 2.080806f
+C7  g1178_1 gnd 2.080806f
+C8 1 gnd 2.080806f
+R1 1 g1178_0 2.224404
+C9 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g1178_1 2 2.224404
+C10 3 gnd 2.080806f
+R4 3 1 2.224404
+C11 4 gnd 2.080806f
+R5 4 3 2.224404
+R6 g1178_4 4 2.224404
+C12 5 gnd 2.080806f
+R7 g1178_1 5 2.224404
+C13 6 gnd 2.080806f
+R8 6 5 2.224404
+C14 7 gnd 2.080806f
+R9 6 7 2.224404
+R10 g1178_6 7 2.224404
+C15 8 gnd 2.080806f
+R11 5 8 2.224404
+C16 9 gnd 2.080806f
+R12 8 9 2.224404
+C17 10 gnd 2.080806f
+R13 9 10 2.224404
+R14 10 g1178_3 2.224404
+C18 11 gnd 2.080806f
+R15 g1178_6 11 2.224404
+C19 12 gnd 2.080806f
+R16 12 11 2.224404
+C20 13 gnd 2.080806f
+R17 12 13 2.224404
+C21 14 gnd 2.080806f
+R18 13 14 2.224404
+C22 15 gnd 2.080806f
+R19 14 15 2.224404
+C23 16 gnd 2.080806f
+R20 16 15 2.224404
+C24 17 gnd 2.080806f
+R21 16 17 2.224404
+R22 g1178_2 17 2.224404
+C25 18 gnd 2.080806f
+R23 18 g1178_6 2.224404
+C26 19 gnd 2.080806f
+R24 19 18 2.224404
+C27 20 gnd 2.080806f
+R25 20 19 2.224404
+C28 21 gnd 2.080806f
+R26 21 20 2.224404
+C29 22 gnd 2.080806f
+R27 22 21 2.224404
+C30 23 gnd 2.080806f
+R28 22 23 2.224404
+C31 24 gnd 2.080806f
+R29 24 23 2.224404
+C32 25 gnd 2.080806f
+R30 25 24 2.224404
+C33 26 gnd 2.080806f
+R31 26 25 2.224404
+C34 27 gnd 2.080806f
+R32 27 26 2.224404
+C35 28 gnd 2.080806f
+R33 28 27 2.224404
+C36 29 gnd 2.080806f
+R34 29 28 2.224404
+C37 30 gnd 2.080806f
+R35 30 29 2.224404
+R36 30 g1178_5 2.224404
+.ends
+
+.subckt netg96 g96_0 g96_1 gnd
+C1  g96_0 gnd 2.080806f
+C2  g96_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g96_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+R26 25 g96_1 2.224404
+.ends
+
+.subckt netg2389 g2389_2 g2389_1 g2389_0 gnd
+C1  g2389_2 gnd 2.080806f
+C2  g2389_1 gnd 2.080806f
+C3  g2389_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g2389_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g2389_2 2 2.224404
+C6 3 gnd 2.080806f
+R4 g2389_2 3 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 11 10 2.224404
+C15 12 gnd 2.080806f
+R13 12 11 2.224404
+C16 13 gnd 2.080806f
+R14 13 12 2.224404
+C17 14 gnd 2.080806f
+R15 14 13 2.224404
+C18 15 gnd 2.080806f
+R16 15 14 2.224404
+C19 16 gnd 2.080806f
+R17 16 15 2.224404
+C20 17 gnd 2.080806f
+R18 17 16 2.224404
+C21 18 gnd 2.080806f
+R19 18 17 2.224404
+C22 19 gnd 2.080806f
+R20 19 18 2.224404
+C23 20 gnd 2.080806f
+R21 20 19 2.224404
+C24 21 gnd 2.080806f
+R22 21 20 2.224404
+C25 22 gnd 2.080806f
+R23 22 21 2.224404
+C26 23 gnd 2.080806f
+R24 23 22 2.224404
+C27 24 gnd 2.080806f
+R25 23 24 2.224404
+R26 g2389_1 24 2.224404
+.ends
+
+.subckt netg2288 g2288_1 g2288_3 g2288_0 g2288_2 gnd
+C1  g2288_1 gnd 2.080806f
+C2  g2288_3 gnd 2.080806f
+C3  g2288_0 gnd 2.080806f
+C4  g2288_2 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g2288_0 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+C7 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g2288_3 2.224404
+C8 4 gnd 2.080806f
+R5 4 g2288_0 2.224404
+C9 5 gnd 2.080806f
+R6 5 4 2.224404
+C10 6 gnd 2.080806f
+R7 6 5 2.224404
+C11 7 gnd 2.080806f
+R8 7 6 2.224404
+C12 8 gnd 2.080806f
+R9 8 7 2.224404
+C13 9 gnd 2.080806f
+R10 9 8 2.224404
+C14 10 gnd 2.080806f
+R11 10 9 2.224404
+C15 11 gnd 2.080806f
+R12 11 10 2.224404
+R13 g2288_1 11 2.224404
+C16 12 gnd 2.080806f
+R14 12 g2288_1 2.224404
+C17 13 gnd 2.080806f
+R15 13 12 2.224404
+C18 14 gnd 2.080806f
+R16 14 13 2.224404
+C19 15 gnd 2.080806f
+R17 15 14 2.224404
+C20 16 gnd 2.080806f
+R18 16 15 2.224404
+C21 17 gnd 2.080806f
+R19 17 16 2.224404
+C22 18 gnd 2.080806f
+R20 18 17 2.224404
+C23 19 gnd 2.080806f
+R21 19 18 2.224404
+C24 20 gnd 2.080806f
+R22 20 19 2.224404
+C25 21 gnd 2.080806f
+R23 21 20 2.224404
+C26 22 gnd 2.080806f
+R24 22 21 2.224404
+C27 23 gnd 2.080806f
+R25 23 22 2.224404
+R26 g2288_2 23 2.224404
+.ends
+
+.subckt netg1824 g1824_0 g1824_1 g1824_2 g1824_3 gnd
+C1  g1824_0 gnd 2.080806f
+C2  g1824_1 gnd 2.080806f
+C3  g1824_2 gnd 2.080806f
+C4  g1824_3 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g1824_0 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+C7 3 gnd 2.080806f
+R3 2 3 2.224404
+C8 4 gnd 2.080806f
+R4 4 3 2.224404
+C9 5 gnd 2.080806f
+R5 4 5 2.224404
+C10 6 gnd 2.080806f
+R6 5 6 2.224404
+R7 6 g1824_2 2.224404
+C11 7 gnd 2.080806f
+R8 g1824_2 7 2.224404
+C12 8 gnd 2.080806f
+R9 7 8 2.224404
+C13 9 gnd 2.080806f
+R10 8 9 2.224404
+C14 10 gnd 2.080806f
+R11 9 10 2.224404
+C15 11 gnd 2.080806f
+R12 10 11 2.224404
+C16 12 gnd 2.080806f
+R13 12 11 2.224404
+C17 13 gnd 2.080806f
+R14 12 13 2.224404
+C18 14 gnd 2.080806f
+R15 13 14 2.224404
+C19 15 gnd 2.080806f
+R16 14 15 2.224404
+R17 15 g1824_3 2.224404
+C20 16 gnd 2.080806f
+R18 g1824_3 16 2.224404
+C21 17 gnd 2.080806f
+R19 16 17 2.224404
+C22 18 gnd 2.080806f
+R20 17 18 2.224404
+C23 19 gnd 2.080806f
+R21 18 19 2.224404
+C24 20 gnd 2.080806f
+R22 19 20 2.224404
+C25 21 gnd 2.080806f
+R23 20 21 2.224404
+C26 22 gnd 2.080806f
+R24 21 22 2.224404
+C27 23 gnd 2.080806f
+R25 22 23 2.224404
+C28 24 gnd 2.080806f
+R26 23 24 2.224404
+C29 25 gnd 2.080806f
+R27 24 25 2.224404
+C30 26 gnd 2.080806f
+R28 25 26 2.224404
+R29 26 g1824_1 2.224404
+.ends
+
+.subckt netg135 g135_0 g135_1 gnd
+C1  g135_0 gnd 2.080806f
+C2  g135_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g135_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+R27 26 g135_1 2.224404
+.ends
+
+.subckt netg5830 g5830_0 g5830_2 g5830_1 gnd
+C1  g5830_0 gnd 2.080806f
+C2  g5830_2 gnd 2.080806f
+C3  g5830_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5830_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g5830_2 2.224404
+C6 3 gnd 2.080806f
+R4 g5830_2 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+C8 5 gnd 2.080806f
+R6 4 5 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+C10 7 gnd 2.080806f
+R8 6 7 2.224404
+C11 8 gnd 2.080806f
+R9 7 8 2.224404
+C12 9 gnd 2.080806f
+R10 8 9 2.224404
+C13 10 gnd 2.080806f
+R11 9 10 2.224404
+C14 11 gnd 2.080806f
+R12 10 11 2.224404
+C15 12 gnd 2.080806f
+R13 11 12 2.224404
+C16 13 gnd 2.080806f
+R14 12 13 2.224404
+C17 14 gnd 2.080806f
+R15 13 14 2.224404
+C18 15 gnd 2.080806f
+R16 14 15 2.224404
+C19 16 gnd 2.080806f
+R17 15 16 2.224404
+C20 17 gnd 2.080806f
+R18 16 17 2.224404
+C21 18 gnd 2.080806f
+R19 17 18 2.224404
+C22 19 gnd 2.080806f
+R20 18 19 2.224404
+C23 20 gnd 2.080806f
+R21 19 20 2.224404
+C24 21 gnd 2.080806f
+R22 20 21 2.224404
+C25 22 gnd 2.080806f
+R23 21 22 2.224404
+C26 23 gnd 2.080806f
+R24 22 23 2.224404
+C27 24 gnd 2.080806f
+R25 23 24 2.224404
+C28 25 gnd 2.080806f
+R26 24 25 2.224404
+R27 25 g5830_1 2.224404
+.ends
+
+.subckt netg88 g88_1 g88_0 gnd
+C1  g88_1 gnd 2.080806f
+C2  g88_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g88_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+R27 g88_1 26 2.224404
+.ends
+
+.subckt netg2641 g2641_2 g2641_0 g2641_1 gnd
+C1  g2641_2 gnd 2.080806f
+C2  g2641_0 gnd 2.080806f
+C3  g2641_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g2641_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g2641_2 2 2.224404
+C6 3 gnd 2.080806f
+R4 3 g2641_2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 11 10 2.224404
+C15 12 gnd 2.080806f
+R13 12 11 2.224404
+C16 13 gnd 2.080806f
+R14 13 12 2.224404
+C17 14 gnd 2.080806f
+R15 14 13 2.224404
+C18 15 gnd 2.080806f
+R16 15 14 2.224404
+C19 16 gnd 2.080806f
+R17 16 15 2.224404
+C20 17 gnd 2.080806f
+R18 17 16 2.224404
+C21 18 gnd 2.080806f
+R19 18 17 2.224404
+C22 19 gnd 2.080806f
+R20 19 18 2.224404
+C23 20 gnd 2.080806f
+R21 20 19 2.224404
+C24 21 gnd 2.080806f
+R22 21 20 2.224404
+C25 22 gnd 2.080806f
+R23 22 21 2.224404
+C26 23 gnd 2.080806f
+R24 23 22 2.224404
+C27 24 gnd 2.080806f
+R25 24 23 2.224404
+C28 25 gnd 2.080806f
+R26 25 24 2.224404
+R27 g2641_1 25 2.224404
+.ends
+
+.subckt netg5302 g5302_5 g5302_3 g5302_6 g5302_4 g5302_2 g5302_1 g5302_0 gnd
+C1  g5302_5 gnd 2.080806f
+C2  g5302_3 gnd 2.080806f
+C3  g5302_6 gnd 2.080806f
+C4  g5302_4 gnd 2.080806f
+C5  g5302_2 gnd 2.080806f
+C6  g5302_1 gnd 2.080806f
+C7  g5302_0 gnd 2.080806f
+R1 g5302_4 g5302_0 2.224404
+R2 g5302_3 g5302_4 2.224404
+C8 1 gnd 2.080806f
+R3 1 g5302_3 2.224404
+C9 2 gnd 2.080806f
+R4 2 1 2.224404
+R5 g5302_5 2 2.224404
+C10 3 gnd 2.080806f
+R6 3 g5302_5 2.224404
+C11 4 gnd 2.080806f
+R7 4 3 2.224404
+R8 g5302_6 4 2.224404
+C12 5 gnd 2.080806f
+R9 5 g5302_6 2.224404
+R10 g5302_1 5 2.224404
+C13 6 gnd 2.080806f
+R11 6 g5302_1 2.224404
+C14 7 gnd 2.080806f
+R12 7 6 2.224404
+C15 8 gnd 2.080806f
+R13 8 7 2.224404
+C16 9 gnd 2.080806f
+R14 8 9 2.224404
+C17 10 gnd 2.080806f
+R15 10 9 2.224404
+C18 11 gnd 2.080806f
+R16 11 10 2.224404
+C19 12 gnd 2.080806f
+R17 11 12 2.224404
+C20 13 gnd 2.080806f
+R18 13 12 2.224404
+C21 14 gnd 2.080806f
+R19 14 13 2.224404
+C22 15 gnd 2.080806f
+R20 14 15 2.224404
+C23 16 gnd 2.080806f
+R21 16 15 2.224404
+C24 17 gnd 2.080806f
+R22 17 16 2.224404
+C25 18 gnd 2.080806f
+R23 17 18 2.224404
+C26 19 gnd 2.080806f
+R24 19 18 2.224404
+C27 20 gnd 2.080806f
+R25 20 19 2.224404
+C28 21 gnd 2.080806f
+R26 21 20 2.224404
+C29 22 gnd 2.080806f
+R27 22 21 2.224404
+R28 g5302_2 22 2.224404
+.ends
+
+.subckt netg136 g136_0 g136_1 gnd
+C1  g136_0 gnd 2.080806f
+C2  g136_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g136_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+R27 g136_1 26 2.224404
+.ends
+
+.subckt netg2692 g2692_1 g2692_2 gnd
+C1  g2692_1 gnd 2.080806f
+C2  g2692_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2692_2 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+R29 g2692_1 28 2.224404
+.ends
+
+.subckt netg3366 g3366_0 g3366_1 gnd
+C1  g3366_0 gnd 2.080806f
+C2  g3366_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g3366_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+R29 g3366_1 28 2.224404
+.ends
+
+.subckt netg7545 g7545_1 g7545_0 gnd
+C1  g7545_1 gnd 2.080806f
+C2  g7545_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7545_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+R27 26 g7545_1 2.224404
+.ends
+
+.subckt netg140 g140_1 g140_0 gnd
+C1  g140_1 gnd 2.080806f
+C2  g140_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g140_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+R27 26 g140_1 2.224404
+.ends
+
+.subckt netg1954 g1954_2 g1954_0 g1954_1 gnd
+C1  g1954_2 gnd 2.080806f
+C2  g1954_0 gnd 2.080806f
+C3  g1954_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g1954_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 6 5 2.224404
+C10 7 gnd 2.080806f
+R7 7 6 2.224404
+C11 8 gnd 2.080806f
+R8 8 7 2.224404
+C12 9 gnd 2.080806f
+R9 9 8 2.224404
+C13 10 gnd 2.080806f
+R10 10 9 2.224404
+C14 11 gnd 2.080806f
+R11 11 10 2.224404
+C15 12 gnd 2.080806f
+R12 12 11 2.224404
+C16 13 gnd 2.080806f
+R13 12 13 2.224404
+C17 14 gnd 2.080806f
+R14 14 13 2.224404
+C18 15 gnd 2.080806f
+R15 15 14 2.224404
+C19 16 gnd 2.080806f
+R16 15 16 2.224404
+C20 17 gnd 2.080806f
+R17 17 16 2.224404
+C21 18 gnd 2.080806f
+R18 18 17 2.224404
+C22 19 gnd 2.080806f
+R19 18 19 2.224404
+C23 20 gnd 2.080806f
+R20 20 19 2.224404
+C24 21 gnd 2.080806f
+R21 21 20 2.224404
+C25 22 gnd 2.080806f
+R22 21 22 2.224404
+C26 23 gnd 2.080806f
+R23 23 22 2.224404
+C27 24 gnd 2.080806f
+R24 24 23 2.224404
+C28 25 gnd 2.080806f
+R25 25 24 2.224404
+C29 26 gnd 2.080806f
+R26 26 25 2.224404
+R27 g1954_2 26 2.224404
+R28 g1954_1 g1954_2 2.224404
+.ends
+
+.subckt netg6564 g6564_0 g6564_1 gnd
+C1  g6564_0 gnd 2.080806f
+C2  g6564_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6564_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+R28 g6564_1 27 2.224404
+.ends
+
+.subckt netg7547 g7547_1 g7547_0 gnd
+C1  g7547_1 gnd 2.080806f
+C2  g7547_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7547_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+R28 27 g7547_1 2.224404
+.ends
+
+.subckt netg7546 g7546_1 g7546_0 gnd
+C1  g7546_1 gnd 2.080806f
+C2  g7546_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7546_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+R28 g7546_1 27 2.224404
+.ends
+
+.subckt netg142 g142_1 g142_0 gnd
+C1  g142_1 gnd 2.080806f
+C2  g142_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g142_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+R28 27 g142_1 2.224404
+.ends
+
+.subckt netg5569 g5569_1 g5569_0 g5569_2 gnd
+C1  g5569_1 gnd 2.080806f
+C2  g5569_0 gnd 2.080806f
+C3  g5569_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5569_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+C8 5 gnd 2.080806f
+R5 4 5 2.224404
+C9 6 gnd 2.080806f
+R6 5 6 2.224404
+C10 7 gnd 2.080806f
+R7 6 7 2.224404
+C11 8 gnd 2.080806f
+R8 7 8 2.224404
+C12 9 gnd 2.080806f
+R9 8 9 2.224404
+C13 10 gnd 2.080806f
+R10 9 10 2.224404
+C14 11 gnd 2.080806f
+R11 10 11 2.224404
+C15 12 gnd 2.080806f
+R12 11 12 2.224404
+C16 13 gnd 2.080806f
+R13 12 13 2.224404
+C17 14 gnd 2.080806f
+R14 13 14 2.224404
+C18 15 gnd 2.080806f
+R15 14 15 2.224404
+C19 16 gnd 2.080806f
+R16 15 16 2.224404
+C20 17 gnd 2.080806f
+R17 16 17 2.224404
+C21 18 gnd 2.080806f
+R18 17 18 2.224404
+C22 19 gnd 2.080806f
+R19 18 19 2.224404
+C23 20 gnd 2.080806f
+R20 19 20 2.224404
+C24 21 gnd 2.080806f
+R21 20 21 2.224404
+C25 22 gnd 2.080806f
+R22 21 22 2.224404
+C26 23 gnd 2.080806f
+R23 22 23 2.224404
+C27 24 gnd 2.080806f
+R24 23 24 2.224404
+C28 25 gnd 2.080806f
+R25 24 25 2.224404
+C29 26 gnd 2.080806f
+R26 25 26 2.224404
+R27 26 g5569_1 2.224404
+R28 g5569_1 g5569_2 2.224404
+.ends
+
+.subckt netg501 g501_2 g501_4 g501_1 g501_3 g501_5 gnd
+C1  g501_2 gnd 2.080806f
+C2  g501_4 gnd 2.080806f
+C3  g501_1 gnd 2.080806f
+C4  g501_3 gnd 2.080806f
+C5  g501_5 gnd 2.080806f
+C6 1 gnd 2.080806f
+R1 1 g501_5 2.224404
+C7 2 gnd 2.080806f
+R2 2 1 2.224404
+C8 3 gnd 2.080806f
+R3 3 2 2.224404
+C9 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 g501_2 4 2.224404
+C10 5 gnd 2.080806f
+R6 g501_5 5 2.224404
+C11 6 gnd 2.080806f
+R7 5 6 2.224404
+C12 7 gnd 2.080806f
+R8 6 7 2.224404
+C13 8 gnd 2.080806f
+R9 7 8 2.224404
+C14 9 gnd 2.080806f
+R10 8 9 2.224404
+C15 10 gnd 2.080806f
+R11 9 10 2.224404
+C16 11 gnd 2.080806f
+R12 10 11 2.224404
+C17 12 gnd 2.080806f
+R13 11 12 2.224404
+C18 13 gnd 2.080806f
+R14 12 13 2.224404
+C19 14 gnd 2.080806f
+R15 13 14 2.224404
+C20 15 gnd 2.080806f
+R16 14 15 2.224404
+C21 16 gnd 2.080806f
+R17 15 16 2.224404
+R18 16 g501_1 2.224404
+C22 17 gnd 2.080806f
+R19 17 16 2.224404
+C23 18 gnd 2.080806f
+R20 18 17 2.224404
+C24 19 gnd 2.080806f
+R21 19 18 2.224404
+C25 20 gnd 2.080806f
+R22 20 19 2.224404
+C26 21 gnd 2.080806f
+R23 21 20 2.224404
+C27 22 gnd 2.080806f
+R24 22 21 2.224404
+C28 23 gnd 2.080806f
+R25 23 22 2.224404
+C29 24 gnd 2.080806f
+R26 24 23 2.224404
+C30 25 gnd 2.080806f
+R27 25 24 2.224404
+C31 26 gnd 2.080806f
+R28 26 25 2.224404
+C32 27 gnd 2.080806f
+R29 27 26 2.224404
+R30 g501_3 27 2.224404
+C33 28 gnd 2.080806f
+R31 28 27 2.224404
+C34 29 gnd 2.080806f
+R32 29 28 2.224404
+C35 30 gnd 2.080806f
+R33 29 30 2.224404
+C36 31 gnd 2.080806f
+R34 30 31 2.224404
+C37 32 gnd 2.080806f
+R35 31 32 2.224404
+C38 33 gnd 2.080806f
+R36 32 33 2.224404
+C39 34 gnd 2.080806f
+R37 33 34 2.224404
+C40 35 gnd 2.080806f
+R38 34 35 2.224404
+R39 35 g501_4 2.224404
+.ends
+
+.subckt netg33 g33_1 g33_0 gnd
+C1  g33_1 gnd 2.080806f
+C2  g33_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g33_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+R28 27 g33_1 2.224404
+.ends
+
+.subckt netg39 g39_0 g39_1 gnd
+C1  g39_0 gnd 2.080806f
+C2  g39_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g39_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+R28 27 g39_1 2.224404
+.ends
+
+.subckt netg137 g137_0 g137_1 gnd
+C1  g137_0 gnd 2.080806f
+C2  g137_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g137_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+R28 g137_1 27 2.224404
+.ends
+
+.subckt netg2292 g2292_3 g2292_1 g2292_2 g2292_0 gnd
+C1  g2292_3 gnd 2.080806f
+C2  g2292_1 gnd 2.080806f
+C3  g2292_2 gnd 2.080806f
+C4  g2292_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g2292_0 1 2.224404
+R2 1 g2292_1 2.224404
+C6 2 gnd 2.080806f
+R3 2 g2292_0 2.224404
+C7 3 gnd 2.080806f
+R4 3 2 2.224404
+C8 4 gnd 2.080806f
+R5 4 3 2.224404
+C9 5 gnd 2.080806f
+R6 5 4 2.224404
+C10 6 gnd 2.080806f
+R7 6 5 2.224404
+C11 7 gnd 2.080806f
+R8 7 6 2.224404
+C12 8 gnd 2.080806f
+R9 8 7 2.224404
+C13 9 gnd 2.080806f
+R10 9 8 2.224404
+R11 g2292_3 9 2.224404
+C14 10 gnd 2.080806f
+R12 10 g2292_3 2.224404
+C15 11 gnd 2.080806f
+R13 11 10 2.224404
+C16 12 gnd 2.080806f
+R14 12 11 2.224404
+C17 13 gnd 2.080806f
+R15 13 12 2.224404
+C18 14 gnd 2.080806f
+R16 14 13 2.224404
+C19 15 gnd 2.080806f
+R17 15 14 2.224404
+C20 16 gnd 2.080806f
+R18 16 15 2.224404
+C21 17 gnd 2.080806f
+R19 17 16 2.224404
+C22 18 gnd 2.080806f
+R20 18 17 2.224404
+C23 19 gnd 2.080806f
+R21 19 18 2.224404
+C24 20 gnd 2.080806f
+R22 20 19 2.224404
+C25 21 gnd 2.080806f
+R23 21 20 2.224404
+C26 22 gnd 2.080806f
+R24 22 21 2.224404
+C27 23 gnd 2.080806f
+R25 23 22 2.224404
+C28 24 gnd 2.080806f
+R26 24 23 2.224404
+C29 25 gnd 2.080806f
+R27 25 24 2.224404
+R28 g2292_2 25 2.224404
+.ends
+
+.subckt netg6214 g6214_1 g6214_2 g6214_0 gnd
+C1  g6214_1 gnd 2.080806f
+C2  g6214_2 gnd 2.080806f
+C3  g6214_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g6214_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 3 g6214_2 2.224404
+C7 4 gnd 2.080806f
+R5 4 1 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 11 10 2.224404
+C15 12 gnd 2.080806f
+R13 12 11 2.224404
+C16 13 gnd 2.080806f
+R14 13 12 2.224404
+C17 14 gnd 2.080806f
+R15 14 13 2.224404
+C18 15 gnd 2.080806f
+R16 15 14 2.224404
+C19 16 gnd 2.080806f
+R17 16 15 2.224404
+C20 17 gnd 2.080806f
+R18 17 16 2.224404
+C21 18 gnd 2.080806f
+R19 18 17 2.224404
+C22 19 gnd 2.080806f
+R20 19 18 2.224404
+C23 20 gnd 2.080806f
+R21 20 19 2.224404
+C24 21 gnd 2.080806f
+R22 21 20 2.224404
+C25 22 gnd 2.080806f
+R23 22 21 2.224404
+C26 23 gnd 2.080806f
+R24 23 22 2.224404
+C27 24 gnd 2.080806f
+R25 24 23 2.224404
+C28 25 gnd 2.080806f
+R26 25 24 2.224404
+C29 26 gnd 2.080806f
+R27 26 25 2.224404
+R28 g6214_1 26 2.224404
+.ends
+
+.subckt netg60 g60_1 g60_0 gnd
+C1  g60_1 gnd 2.080806f
+C2  g60_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g60_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+R28 g60_1 27 2.224404
+.ends
+
+.subckt netg538 g538_4 g538_2 g538_1 g538_3 g538_5 gnd
+C1  g538_4 gnd 2.080806f
+C2  g538_2 gnd 2.080806f
+C3  g538_1 gnd 2.080806f
+C4  g538_3 gnd 2.080806f
+C5  g538_5 gnd 2.080806f
+C6 1 gnd 2.080806f
+R1 g538_3 1 2.224404
+C7 2 gnd 2.080806f
+R2 1 2 2.224404
+C8 3 gnd 2.080806f
+R3 2 3 2.224404
+C9 4 gnd 2.080806f
+R4 3 4 2.224404
+C10 5 gnd 2.080806f
+R5 4 5 2.224404
+C11 6 gnd 2.080806f
+R6 5 6 2.224404
+C12 7 gnd 2.080806f
+R7 6 7 2.224404
+C13 8 gnd 2.080806f
+R8 7 8 2.224404
+R9 8 g538_4 2.224404
+C14 9 gnd 2.080806f
+R10 9 g538_4 2.224404
+C15 10 gnd 2.080806f
+R11 10 9 2.224404
+C16 11 gnd 2.080806f
+R12 10 11 2.224404
+C17 12 gnd 2.080806f
+R13 11 12 2.224404
+R14 12 g538_2 2.224404
+C18 13 gnd 2.080806f
+R15 g538_2 13 2.224404
+C19 14 gnd 2.080806f
+R16 13 14 2.224404
+C20 15 gnd 2.080806f
+R17 14 15 2.224404
+C21 16 gnd 2.080806f
+R18 15 16 2.224404
+C22 17 gnd 2.080806f
+R19 16 17 2.224404
+C23 18 gnd 2.080806f
+R20 17 18 2.224404
+C24 19 gnd 2.080806f
+R21 18 19 2.224404
+C25 20 gnd 2.080806f
+R22 19 20 2.224404
+C26 21 gnd 2.080806f
+R23 20 21 2.224404
+C27 22 gnd 2.080806f
+R24 21 22 2.224404
+C28 23 gnd 2.080806f
+R25 22 23 2.224404
+C29 24 gnd 2.080806f
+R26 23 24 2.224404
+C30 25 gnd 2.080806f
+R27 24 25 2.224404
+R28 25 g538_5 2.224404
+C31 26 gnd 2.080806f
+R29 g538_5 26 2.224404
+C32 27 gnd 2.080806f
+R30 26 27 2.224404
+C33 28 gnd 2.080806f
+R31 27 28 2.224404
+C34 29 gnd 2.080806f
+R32 28 29 2.224404
+C35 30 gnd 2.080806f
+R33 29 30 2.224404
+C36 31 gnd 2.080806f
+R34 31 30 2.224404
+R35 g538_1 31 2.224404
+.ends
+
+.subckt netg3601 g3601_9 g3601_8 g3601_7 g3601_15 g3601_4 g3601_14 g3601_12 g3601_2 g3601_5 g3601_11 g3601_10 g3601_0 g3601_3 g3601_1 g3601_13 g3601_6 gnd
+C1  g3601_9 gnd 2.080806f
+C2  g3601_8 gnd 2.080806f
+C3  g3601_7 gnd 2.080806f
+C4  g3601_15 gnd 2.080806f
+C5  g3601_4 gnd 2.080806f
+C6  g3601_14 gnd 2.080806f
+C7  g3601_12 gnd 2.080806f
+C8  g3601_2 gnd 2.080806f
+C9  g3601_5 gnd 2.080806f
+C10  g3601_11 gnd 2.080806f
+C11  g3601_10 gnd 2.080806f
+C12  g3601_0 gnd 2.080806f
+C13  g3601_3 gnd 2.080806f
+C14  g3601_1 gnd 2.080806f
+C15  g3601_13 gnd 2.080806f
+C16  g3601_6 gnd 2.080806f
+C17 1 gnd 2.080806f
+R1 g3601_0 1 2.224404
+C18 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g3601_8 2.224404
+R4 g3601_8 g3601_13 2.224404
+C19 3 gnd 2.080806f
+R5 3 g3601_8 2.224404
+R6 g3601_11 3 2.224404
+R7 g3601_11 g3601_3 2.224404
+C20 4 gnd 2.080806f
+R8 4 g3601_11 2.224404
+R9 g3601_6 4 2.224404
+C21 5 gnd 2.080806f
+R10 5 g3601_13 2.224404
+C22 6 gnd 2.080806f
+R11 5 6 2.224404
+R12 6 g3601_4 2.224404
+C23 7 gnd 2.080806f
+R13 7 g3601_4 2.224404
+R14 7 g3601_10 2.224404
+C24 8 gnd 2.080806f
+R15 8 g3601_0 2.224404
+C25 9 gnd 2.080806f
+R16 9 8 2.224404
+C26 10 gnd 2.080806f
+R17 10 9 2.224404
+R18 g3601_7 10 2.224404
+C27 11 gnd 2.080806f
+R19 g3601_8 11 2.224404
+C28 12 gnd 2.080806f
+R20 11 12 2.224404
+C29 13 gnd 2.080806f
+R21 12 13 2.224404
+R22 13 g3601_2 2.224404
+R23 g3601_9 g3601_2 2.224404
+R24 g3601_2 g3601_14 2.224404
+C30 14 gnd 2.080806f
+R25 14 g3601_7 2.224404
+C31 15 gnd 2.080806f
+R26 14 15 2.224404
+C32 16 gnd 2.080806f
+R27 16 15 2.224404
+C33 17 gnd 2.080806f
+R28 16 17 2.224404
+R29 g3601_5 17 2.224404
+C34 18 gnd 2.080806f
+R30 18 g3601_5 2.224404
+C35 19 gnd 2.080806f
+R31 19 18 2.224404
+C36 20 gnd 2.080806f
+R32 20 19 2.224404
+C37 21 gnd 2.080806f
+R33 21 20 2.224404
+C38 22 gnd 2.080806f
+R34 21 22 2.224404
+R35 g3601_12 22 2.224404
+C39 23 gnd 2.080806f
+R36 g3601_12 23 2.224404
+C40 24 gnd 2.080806f
+R37 23 24 2.224404
+C41 25 gnd 2.080806f
+R38 24 25 2.224404
+R39 g3601_15 25 2.224404
+C42 26 gnd 2.080806f
+R40 18 26 2.224404
+C43 27 gnd 2.080806f
+R41 26 27 2.224404
+C44 28 gnd 2.080806f
+R42 27 28 2.224404
+C45 29 gnd 2.080806f
+R43 28 29 2.224404
+C46 30 gnd 2.080806f
+R44 29 30 2.224404
+C47 31 gnd 2.080806f
+R45 30 31 2.224404
+R46 31 g3601_1 2.224404
+.ends
+
+.subckt netg2412 g2412_2 g2412_1 g2412_0 gnd
+C1  g2412_2 gnd 2.080806f
+C2  g2412_1 gnd 2.080806f
+C3  g2412_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g2412_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g2412_1 2.224404
+C6 3 gnd 2.080806f
+R4 3 g2412_1 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+C10 7 gnd 2.080806f
+R8 6 7 2.224404
+C11 8 gnd 2.080806f
+R9 7 8 2.224404
+C12 9 gnd 2.080806f
+R10 8 9 2.224404
+C13 10 gnd 2.080806f
+R11 9 10 2.224404
+C14 11 gnd 2.080806f
+R12 10 11 2.224404
+C15 12 gnd 2.080806f
+R13 11 12 2.224404
+C16 13 gnd 2.080806f
+R14 12 13 2.224404
+C17 14 gnd 2.080806f
+R15 13 14 2.224404
+C18 15 gnd 2.080806f
+R16 14 15 2.224404
+C19 16 gnd 2.080806f
+R17 15 16 2.224404
+C20 17 gnd 2.080806f
+R18 17 16 2.224404
+C21 18 gnd 2.080806f
+R19 17 18 2.224404
+C22 19 gnd 2.080806f
+R20 18 19 2.224404
+C23 20 gnd 2.080806f
+R21 19 20 2.224404
+C24 21 gnd 2.080806f
+R22 20 21 2.224404
+C25 22 gnd 2.080806f
+R23 21 22 2.224404
+C26 23 gnd 2.080806f
+R24 22 23 2.224404
+C27 24 gnd 2.080806f
+R25 23 24 2.224404
+C28 25 gnd 2.080806f
+R26 25 24 2.224404
+C29 26 gnd 2.080806f
+R27 25 26 2.224404
+C30 27 gnd 2.080806f
+R28 26 27 2.224404
+C31 28 gnd 2.080806f
+R29 27 28 2.224404
+C32 29 gnd 2.080806f
+R30 28 29 2.224404
+C33 30 gnd 2.080806f
+R31 29 30 2.224404
+C34 31 gnd 2.080806f
+R32 30 31 2.224404
+C35 32 gnd 2.080806f
+R33 31 32 2.224404
+C36 33 gnd 2.080806f
+R34 32 33 2.224404
+C37 34 gnd 2.080806f
+R35 33 34 2.224404
+R36 34 g2412_2 2.224404
+.ends
+
+.subckt netg7491 g7491_1 g7491_0 gnd
+C1  g7491_1 gnd 2.080806f
+C2  g7491_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7491_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+R28 g7491_1 27 2.224404
+.ends
+
+.subckt netg3361 g3361_2 g3361_1 g3361_0 gnd
+C1  g3361_2 gnd 2.080806f
+C2  g3361_1 gnd 2.080806f
+C3  g3361_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g3361_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+C8 5 gnd 2.080806f
+R5 4 5 2.224404
+C9 6 gnd 2.080806f
+R6 5 6 2.224404
+C10 7 gnd 2.080806f
+R7 6 7 2.224404
+C11 8 gnd 2.080806f
+R8 7 8 2.224404
+C12 9 gnd 2.080806f
+R9 8 9 2.224404
+C13 10 gnd 2.080806f
+R10 9 10 2.224404
+C14 11 gnd 2.080806f
+R11 10 11 2.224404
+C15 12 gnd 2.080806f
+R12 11 12 2.224404
+C16 13 gnd 2.080806f
+R13 12 13 2.224404
+C17 14 gnd 2.080806f
+R14 13 14 2.224404
+C18 15 gnd 2.080806f
+R15 14 15 2.224404
+C19 16 gnd 2.080806f
+R16 15 16 2.224404
+C20 17 gnd 2.080806f
+R17 16 17 2.224404
+C21 18 gnd 2.080806f
+R18 17 18 2.224404
+C22 19 gnd 2.080806f
+R19 18 19 2.224404
+C23 20 gnd 2.080806f
+R20 19 20 2.224404
+R21 g3361_2 20 2.224404
+C24 21 gnd 2.080806f
+R22 20 21 2.224404
+C25 22 gnd 2.080806f
+R23 21 22 2.224404
+C26 23 gnd 2.080806f
+R24 22 23 2.224404
+C27 24 gnd 2.080806f
+R25 24 23 2.224404
+C28 25 gnd 2.080806f
+R26 25 24 2.224404
+C29 26 gnd 2.080806f
+R27 26 25 2.224404
+C30 27 gnd 2.080806f
+R28 26 27 2.224404
+C31 28 gnd 2.080806f
+R29 27 28 2.224404
+C32 29 gnd 2.080806f
+R30 28 29 2.224404
+C33 30 gnd 2.080806f
+R31 29 30 2.224404
+C34 31 gnd 2.080806f
+R32 30 31 2.224404
+C35 32 gnd 2.080806f
+R33 31 32 2.224404
+C36 33 gnd 2.080806f
+R34 32 33 2.224404
+R35 33 g3361_1 2.224404
+.ends
+
+.subckt netg2188 g2188_0 g2188_2 g2188_1 g2188_3 g2188_5 g2188_4 gnd
+C1  g2188_0 gnd 2.080806f
+C2  g2188_2 gnd 2.080806f
+C3  g2188_1 gnd 2.080806f
+C4  g2188_3 gnd 2.080806f
+C5  g2188_5 gnd 2.080806f
+C6  g2188_4 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g2188_0 2.224404
+C8 2 gnd 2.080806f
+R2 2 1 2.224404
+C9 3 gnd 2.080806f
+R3 3 2 2.224404
+C10 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 g2188_3 4 2.224404
+C11 5 gnd 2.080806f
+R6 3 5 2.224404
+C12 6 gnd 2.080806f
+R7 5 6 2.224404
+R8 6 g2188_5 2.224404
+C13 7 gnd 2.080806f
+R9 g2188_5 7 2.224404
+C14 8 gnd 2.080806f
+R10 7 8 2.224404
+C15 9 gnd 2.080806f
+R11 8 9 2.224404
+C16 10 gnd 2.080806f
+R12 9 10 2.224404
+C17 11 gnd 2.080806f
+R13 10 11 2.224404
+R14 11 g2188_2 2.224404
+C18 12 gnd 2.080806f
+R15 12 g2188_0 2.224404
+C19 13 gnd 2.080806f
+R16 12 13 2.224404
+C20 14 gnd 2.080806f
+R17 14 13 2.224404
+C21 15 gnd 2.080806f
+R18 14 15 2.224404
+C22 16 gnd 2.080806f
+R19 15 16 2.224404
+C23 17 gnd 2.080806f
+R20 17 16 2.224404
+C24 18 gnd 2.080806f
+R21 17 18 2.224404
+R22 g2188_1 18 2.224404
+C25 19 gnd 2.080806f
+R23 g2188_2 19 2.224404
+C26 20 gnd 2.080806f
+R24 19 20 2.224404
+C27 21 gnd 2.080806f
+R25 20 21 2.224404
+C28 22 gnd 2.080806f
+R26 21 22 2.224404
+C29 23 gnd 2.080806f
+R27 22 23 2.224404
+C30 24 gnd 2.080806f
+R28 23 24 2.224404
+C31 25 gnd 2.080806f
+R29 24 25 2.224404
+C32 26 gnd 2.080806f
+R30 25 26 2.224404
+C33 27 gnd 2.080806f
+R31 26 27 2.224404
+C34 28 gnd 2.080806f
+R32 27 28 2.224404
+C35 29 gnd 2.080806f
+R33 28 29 2.224404
+C36 30 gnd 2.080806f
+R34 29 30 2.224404
+C37 31 gnd 2.080806f
+R35 30 31 2.224404
+C38 32 gnd 2.080806f
+R36 31 32 2.224404
+R37 32 g2188_4 2.224404
+.ends
+
+.subckt netg4880 g4880_1 g4880_0 g4880_2 g4880_3 gnd
+C1  g4880_1 gnd 2.080806f
+C2  g4880_0 gnd 2.080806f
+C3  g4880_2 gnd 2.080806f
+C4  g4880_3 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g4880_0 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+C7 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g4880_3 3 2.224404
+R5 g4880_3 g4880_2 2.224404
+C8 4 gnd 2.080806f
+R6 g4880_0 4 2.224404
+C9 5 gnd 2.080806f
+R7 4 5 2.224404
+C10 6 gnd 2.080806f
+R8 5 6 2.224404
+C11 7 gnd 2.080806f
+R9 6 7 2.224404
+C12 8 gnd 2.080806f
+R10 7 8 2.224404
+C13 9 gnd 2.080806f
+R11 8 9 2.224404
+C14 10 gnd 2.080806f
+R12 9 10 2.224404
+C15 11 gnd 2.080806f
+R13 10 11 2.224404
+C16 12 gnd 2.080806f
+R14 11 12 2.224404
+C17 13 gnd 2.080806f
+R15 12 13 2.224404
+C18 14 gnd 2.080806f
+R16 13 14 2.224404
+C19 15 gnd 2.080806f
+R17 14 15 2.224404
+C20 16 gnd 2.080806f
+R18 15 16 2.224404
+C21 17 gnd 2.080806f
+R19 16 17 2.224404
+C22 18 gnd 2.080806f
+R20 17 18 2.224404
+C23 19 gnd 2.080806f
+R21 18 19 2.224404
+C24 20 gnd 2.080806f
+R22 19 20 2.224404
+C25 21 gnd 2.080806f
+R23 20 21 2.224404
+C26 22 gnd 2.080806f
+R24 21 22 2.224404
+C27 23 gnd 2.080806f
+R25 22 23 2.224404
+C28 24 gnd 2.080806f
+R26 23 24 2.224404
+C29 25 gnd 2.080806f
+R27 24 25 2.224404
+C30 26 gnd 2.080806f
+R28 25 26 2.224404
+R29 26 g4880_1 2.224404
+.ends
+
+.subckt netg6067 g6067_0 g6067_1 gnd
+C1  g6067_0 gnd 2.080806f
+C2  g6067_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6067_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+R32 g6067_1 31 2.224404
+.ends
+
+.subckt netg1502 g1502_0 g1502_1 gnd
+C1  g1502_0 gnd 2.080806f
+C2  g1502_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g1502_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+R29 28 g1502_1 2.224404
+.ends
+
+.subckt netg40 g40_0 g40_1 gnd
+C1  g40_0 gnd 2.080806f
+C2  g40_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g40_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+R29 28 g40_1 2.224404
+.ends
+
+.subckt netg6406 g6406_0 g6406_1 gnd
+C1  g6406_0 gnd 2.080806f
+C2  g6406_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6406_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+R29 28 g6406_1 2.224404
+.ends
+
+.subckt netg4474 g4474_5 g4474_8 g4474_6 g4474_10 g4474_1 g4474_4 g4474_0 g4474_7 g4474_9 g4474_2 g4474_3 gnd
+C1  g4474_5 gnd 2.080806f
+C2  g4474_8 gnd 2.080806f
+C3  g4474_6 gnd 2.080806f
+C4  g4474_10 gnd 2.080806f
+C5  g4474_1 gnd 2.080806f
+C6  g4474_4 gnd 2.080806f
+C7  g4474_0 gnd 2.080806f
+C8  g4474_7 gnd 2.080806f
+C9  g4474_9 gnd 2.080806f
+C10  g4474_2 gnd 2.080806f
+C11  g4474_3 gnd 2.080806f
+C12 1 gnd 2.080806f
+R1 1 g4474_0 2.224404
+C13 2 gnd 2.080806f
+R2 2 1 2.224404
+C14 3 gnd 2.080806f
+R3 3 2 2.224404
+C15 4 gnd 2.080806f
+R4 4 3 2.224404
+C16 5 gnd 2.080806f
+R5 5 4 2.224404
+C17 6 gnd 2.080806f
+R6 6 5 2.224404
+C18 7 gnd 2.080806f
+R7 7 6 2.224404
+C19 8 gnd 2.080806f
+R8 8 7 2.224404
+C20 9 gnd 2.080806f
+R9 9 8 2.224404
+C21 10 gnd 2.080806f
+R10 10 9 2.224404
+C22 11 gnd 2.080806f
+R11 11 10 2.224404
+C23 12 gnd 2.080806f
+R12 12 11 2.224404
+C24 13 gnd 2.080806f
+R13 13 12 2.224404
+C25 14 gnd 2.080806f
+R14 14 13 2.224404
+C26 15 gnd 2.080806f
+R15 15 14 2.224404
+R16 g4474_3 15 2.224404
+C27 16 gnd 2.080806f
+R17 16 g4474_3 2.224404
+C28 17 gnd 2.080806f
+R18 17 16 2.224404
+R19 g4474_5 17 2.224404
+R20 g4474_8 g4474_5 2.224404
+R21 g4474_9 g4474_8 2.224404
+R22 g4474_1 g4474_9 2.224404
+C29 18 gnd 2.080806f
+R23 18 g4474_9 2.224404
+C30 19 gnd 2.080806f
+R24 19 18 2.224404
+R25 g4474_10 19 2.224404
+C31 20 gnd 2.080806f
+R26 20 g4474_1 2.224404
+C32 21 gnd 2.080806f
+R27 21 20 2.224404
+R28 g4474_2 21 2.224404
+C33 22 gnd 2.080806f
+R29 g4474_2 22 2.224404
+R30 g4474_4 22 2.224404
+C34 23 gnd 2.080806f
+R31 23 g4474_4 2.224404
+C35 24 gnd 2.080806f
+R32 23 24 2.224404
+R33 g4474_6 24 2.224404
+C36 25 gnd 2.080806f
+R34 25 g4474_10 2.224404
+C37 26 gnd 2.080806f
+R35 25 26 2.224404
+C38 27 gnd 2.080806f
+R36 26 27 2.224404
+C39 28 gnd 2.080806f
+R37 27 28 2.224404
+R38 28 g4474_7 2.224404
+.ends
+
+.subckt netg621 g621_2 g621_4 g621_6 g621_3 g621_1 g621_5 gnd
+C1  g621_2 gnd 2.080806f
+C2  g621_4 gnd 2.080806f
+C3  g621_6 gnd 2.080806f
+C4  g621_3 gnd 2.080806f
+C5  g621_1 gnd 2.080806f
+C6  g621_5 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g621_1 2.224404
+R2 g621_4 1 2.224404
+C8 2 gnd 2.080806f
+R3 2 g621_4 2.224404
+R4 g621_5 2 2.224404
+C9 3 gnd 2.080806f
+R5 3 g621_5 2.224404
+C10 4 gnd 2.080806f
+R6 4 3 2.224404
+R7 g621_2 4 2.224404
+C11 5 gnd 2.080806f
+R8 3 5 2.224404
+C12 6 gnd 2.080806f
+R9 5 6 2.224404
+C13 7 gnd 2.080806f
+R10 6 7 2.224404
+C14 8 gnd 2.080806f
+R11 7 8 2.224404
+C15 9 gnd 2.080806f
+R12 8 9 2.224404
+C16 10 gnd 2.080806f
+R13 9 10 2.224404
+R14 10 g621_6 2.224404
+C17 11 gnd 2.080806f
+R15 g621_6 11 2.224404
+C18 12 gnd 2.080806f
+R16 11 12 2.224404
+C19 13 gnd 2.080806f
+R17 12 13 2.224404
+C20 14 gnd 2.080806f
+R18 13 14 2.224404
+C21 15 gnd 2.080806f
+R19 14 15 2.224404
+C22 16 gnd 2.080806f
+R20 15 16 2.224404
+C23 17 gnd 2.080806f
+R21 16 17 2.224404
+C24 18 gnd 2.080806f
+R22 17 18 2.224404
+C25 19 gnd 2.080806f
+R23 18 19 2.224404
+C26 20 gnd 2.080806f
+R24 19 20 2.224404
+C27 21 gnd 2.080806f
+R25 20 21 2.224404
+C28 22 gnd 2.080806f
+R26 21 22 2.224404
+C29 23 gnd 2.080806f
+R27 22 23 2.224404
+C30 24 gnd 2.080806f
+R28 23 24 2.224404
+C31 25 gnd 2.080806f
+R29 25 24 2.224404
+C32 26 gnd 2.080806f
+R30 25 26 2.224404
+R31 g621_3 26 2.224404
+.ends
+
+.subckt netg57 g57_1 g57_0 gnd
+C1  g57_1 gnd 2.080806f
+C2  g57_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g57_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+R29 g57_1 28 2.224404
+.ends
+
+.subckt netg122 g122_1 g122_0 gnd
+C1  g122_1 gnd 2.080806f
+C2  g122_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g122_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+R30 g122_1 29 2.224404
+.ends
+
+.subckt netg7492 g7492_0 g7492_1 gnd
+C1  g7492_0 gnd 2.080806f
+C2  g7492_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7492_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+R30 g7492_1 29 2.224404
+.ends
+
+.subckt netg1185 g1185_6 g1185_5 g1185_1 g1185_4 g1185_2 g1185_3 g1185_0 gnd
+C1  g1185_6 gnd 2.080806f
+C2  g1185_5 gnd 2.080806f
+C3  g1185_1 gnd 2.080806f
+C4  g1185_4 gnd 2.080806f
+C5  g1185_2 gnd 2.080806f
+C6  g1185_3 gnd 2.080806f
+C7  g1185_0 gnd 2.080806f
+C8 1 gnd 2.080806f
+R1 1 g1185_0 2.224404
+R2 g1185_2 1 2.224404
+C9 2 gnd 2.080806f
+R3 g1185_0 2 2.224404
+C10 3 gnd 2.080806f
+R4 2 3 2.224404
+C11 4 gnd 2.080806f
+R5 3 4 2.224404
+C12 5 gnd 2.080806f
+R6 4 5 2.224404
+C13 6 gnd 2.080806f
+R7 5 6 2.224404
+C14 7 gnd 2.080806f
+R8 6 7 2.224404
+C15 8 gnd 2.080806f
+R9 7 8 2.224404
+R10 8 g1185_4 2.224404
+C16 9 gnd 2.080806f
+R11 g1185_4 9 2.224404
+C17 10 gnd 2.080806f
+R12 9 10 2.224404
+C18 11 gnd 2.080806f
+R13 10 11 2.224404
+C19 12 gnd 2.080806f
+R14 11 12 2.224404
+C20 13 gnd 2.080806f
+R15 12 13 2.224404
+C21 14 gnd 2.080806f
+R16 13 14 2.224404
+C22 15 gnd 2.080806f
+R17 14 15 2.224404
+C23 16 gnd 2.080806f
+R18 15 16 2.224404
+C24 17 gnd 2.080806f
+R19 16 17 2.224404
+C25 18 gnd 2.080806f
+R20 17 18 2.224404
+R21 18 g1185_6 2.224404
+C26 19 gnd 2.080806f
+R22 g1185_6 19 2.224404
+C27 20 gnd 2.080806f
+R23 19 20 2.224404
+C28 21 gnd 2.080806f
+R24 20 21 2.224404
+R25 21 g1185_5 2.224404
+C29 22 gnd 2.080806f
+R26 22 g1185_5 2.224404
+C30 23 gnd 2.080806f
+R27 23 22 2.224404
+C31 24 gnd 2.080806f
+R28 23 24 2.224404
+R29 g1185_3 24 2.224404
+C32 25 gnd 2.080806f
+R30 21 25 2.224404
+C33 26 gnd 2.080806f
+R31 25 26 2.224404
+C34 27 gnd 2.080806f
+R32 26 27 2.224404
+R33 27 g1185_1 2.224404
+.ends
+
+.subckt netg6064 g6064_1 g6064_0 gnd
+C1  g6064_1 gnd 2.080806f
+C2  g6064_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6064_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+R34 g6064_1 33 2.224404
+.ends
+
+.subckt netg3754 g3754_5 g3754_2 g3754_12 g3754_10 g3754_4 g3754_9 g3754_6 g3754_13 g3754_3 g3754_7 g3754_11 g3754_8 g3754_0 g3754_1 gnd
+C1  g3754_5 gnd 2.080806f
+C2  g3754_2 gnd 2.080806f
+C3  g3754_12 gnd 2.080806f
+C4  g3754_10 gnd 2.080806f
+C5  g3754_4 gnd 2.080806f
+C6  g3754_9 gnd 2.080806f
+C7  g3754_6 gnd 2.080806f
+C8  g3754_13 gnd 2.080806f
+C9  g3754_3 gnd 2.080806f
+C10  g3754_7 gnd 2.080806f
+C11  g3754_11 gnd 2.080806f
+C12  g3754_8 gnd 2.080806f
+C13  g3754_0 gnd 2.080806f
+C14  g3754_1 gnd 2.080806f
+C15 1 gnd 2.080806f
+R1 1 g3754_0 2.224404
+R2 g3754_5 1 2.224404
+C16 2 gnd 2.080806f
+R3 g3754_0 2 2.224404
+C17 3 gnd 2.080806f
+R4 2 3 2.224404
+C18 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 4 g3754_11 2.224404
+C19 5 gnd 2.080806f
+R7 g3754_11 5 2.224404
+C20 6 gnd 2.080806f
+R8 5 6 2.224404
+C21 7 gnd 2.080806f
+R9 6 7 2.224404
+C22 8 gnd 2.080806f
+R10 7 8 2.224404
+C23 9 gnd 2.080806f
+R11 8 9 2.224404
+C24 10 gnd 2.080806f
+R12 9 10 2.224404
+C25 11 gnd 2.080806f
+R13 10 11 2.224404
+R14 11 g3754_9 2.224404
+C26 12 gnd 2.080806f
+R15 g3754_9 12 2.224404
+R16 12 g3754_7 2.224404
+C27 13 gnd 2.080806f
+R17 13 g3754_7 2.224404
+R18 g3754_2 13 2.224404
+R19 g3754_2 g3754_10 2.224404
+C28 14 gnd 2.080806f
+R20 14 g3754_2 2.224404
+C29 15 gnd 2.080806f
+R21 15 14 2.224404
+R22 g3754_1 15 2.224404
+C30 16 gnd 2.080806f
+R23 g3754_10 16 2.224404
+C31 17 gnd 2.080806f
+R24 16 17 2.224404
+C32 18 gnd 2.080806f
+R25 17 18 2.224404
+R26 18 g3754_4 2.224404
+C33 19 gnd 2.080806f
+R27 19 g3754_4 2.224404
+R28 g3754_6 19 2.224404
+C34 20 gnd 2.080806f
+R29 20 g3754_6 2.224404
+R30 g3754_13 20 2.224404
+C35 21 gnd 2.080806f
+R31 21 g3754_13 2.224404
+C36 22 gnd 2.080806f
+R32 22 21 2.224404
+C37 23 gnd 2.080806f
+R33 23 22 2.224404
+R34 g3754_8 23 2.224404
+C38 24 gnd 2.080806f
+R35 24 g3754_8 2.224404
+C39 25 gnd 2.080806f
+R36 25 24 2.224404
+R37 g3754_12 25 2.224404
+C40 26 gnd 2.080806f
+R38 26 g3754_6 2.224404
+C41 27 gnd 2.080806f
+R39 27 26 2.224404
+C42 28 gnd 2.080806f
+R40 28 27 2.224404
+C43 29 gnd 2.080806f
+R41 28 29 2.224404
+C44 30 gnd 2.080806f
+R42 29 30 2.224404
+C45 31 gnd 2.080806f
+R43 31 30 2.224404
+C46 32 gnd 2.080806f
+R44 31 32 2.224404
+C47 33 gnd 2.080806f
+R45 32 33 2.224404
+R46 33 g3754_3 2.224404
+.ends
+
+.subckt netg6056 g6056_4 g6056_0 g6056_2 g6056_5 g6056_1 g6056_6 g6056_3 gnd
+C1  g6056_4 gnd 2.080806f
+C2  g6056_0 gnd 2.080806f
+C3  g6056_2 gnd 2.080806f
+C4  g6056_5 gnd 2.080806f
+C5  g6056_1 gnd 2.080806f
+C6  g6056_6 gnd 2.080806f
+C7  g6056_3 gnd 2.080806f
+R1 g6056_1 g6056_0 2.224404
+R2 g6056_0 g6056_3 2.224404
+R3 g6056_0 g6056_6 2.224404
+R4 g6056_3 g6056_2 2.224404
+C8 1 gnd 2.080806f
+R5 g6056_6 1 2.224404
+R6 1 g6056_4 2.224404
+C9 2 gnd 2.080806f
+R7 g6056_4 2 2.224404
+C10 3 gnd 2.080806f
+R8 2 3 2.224404
+C11 4 gnd 2.080806f
+R9 3 4 2.224404
+C12 5 gnd 2.080806f
+R10 4 5 2.224404
+C13 6 gnd 2.080806f
+R11 5 6 2.224404
+C14 7 gnd 2.080806f
+R12 6 7 2.224404
+C15 8 gnd 2.080806f
+R13 7 8 2.224404
+C16 9 gnd 2.080806f
+R14 9 8 2.224404
+C17 10 gnd 2.080806f
+R15 10 9 2.224404
+C18 11 gnd 2.080806f
+R16 10 11 2.224404
+C19 12 gnd 2.080806f
+R17 11 12 2.224404
+C20 13 gnd 2.080806f
+R18 12 13 2.224404
+C21 14 gnd 2.080806f
+R19 13 14 2.224404
+C22 15 gnd 2.080806f
+R20 15 14 2.224404
+C23 16 gnd 2.080806f
+R21 16 15 2.224404
+C24 17 gnd 2.080806f
+R22 16 17 2.224404
+C25 18 gnd 2.080806f
+R23 18 17 2.224404
+C26 19 gnd 2.080806f
+R24 19 18 2.224404
+C27 20 gnd 2.080806f
+R25 20 19 2.224404
+C28 21 gnd 2.080806f
+R26 20 21 2.224404
+C29 22 gnd 2.080806f
+R27 21 22 2.224404
+C30 23 gnd 2.080806f
+R28 23 22 2.224404
+C31 24 gnd 2.080806f
+R29 23 24 2.224404
+C32 25 gnd 2.080806f
+R30 24 25 2.224404
+R31 25 g6056_5 2.224404
+.ends
+
+.subckt netg391 g391_1 g391_0 g391_2 gnd
+C1  g391_1 gnd 2.080806f
+C2  g391_0 gnd 2.080806f
+C3  g391_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g391_0 2.224404
+R2 g391_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 g391_1 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+C8 5 gnd 2.080806f
+R6 4 5 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+C10 7 gnd 2.080806f
+R8 6 7 2.224404
+C11 8 gnd 2.080806f
+R9 7 8 2.224404
+C12 9 gnd 2.080806f
+R10 8 9 2.224404
+C13 10 gnd 2.080806f
+R11 9 10 2.224404
+C14 11 gnd 2.080806f
+R12 10 11 2.224404
+C15 12 gnd 2.080806f
+R13 11 12 2.224404
+C16 13 gnd 2.080806f
+R14 12 13 2.224404
+C17 14 gnd 2.080806f
+R15 13 14 2.224404
+C18 15 gnd 2.080806f
+R16 14 15 2.224404
+C19 16 gnd 2.080806f
+R17 15 16 2.224404
+C20 17 gnd 2.080806f
+R18 16 17 2.224404
+C21 18 gnd 2.080806f
+R19 17 18 2.224404
+C22 19 gnd 2.080806f
+R20 18 19 2.224404
+C23 20 gnd 2.080806f
+R21 19 20 2.224404
+C24 21 gnd 2.080806f
+R22 20 21 2.224404
+C25 22 gnd 2.080806f
+R23 21 22 2.224404
+C26 23 gnd 2.080806f
+R24 22 23 2.224404
+C27 24 gnd 2.080806f
+R25 23 24 2.224404
+C28 25 gnd 2.080806f
+R26 24 25 2.224404
+C29 26 gnd 2.080806f
+R27 25 26 2.224404
+C30 27 gnd 2.080806f
+R28 27 26 2.224404
+C31 28 gnd 2.080806f
+R29 28 27 2.224404
+R30 g391_2 28 2.224404
+.ends
+
+.subckt netg2802 g2802_0 g2802_1 gnd
+C1  g2802_0 gnd 2.080806f
+C2  g2802_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2802_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+R36 g2802_1 35 2.224404
+.ends
+
+.subckt netg2794 g2794_1 g2794_0 gnd
+C1  g2794_1 gnd 2.080806f
+C2  g2794_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2794_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+R30 g2794_1 29 2.224404
+.ends
+
+.subckt netg5499 g5499_0 g5499_1 g5499_2 gnd
+C1  g5499_0 gnd 2.080806f
+C2  g5499_1 gnd 2.080806f
+C3  g5499_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g5499_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g5499_2 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+C8 5 gnd 2.080806f
+R6 4 5 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+C10 7 gnd 2.080806f
+R8 6 7 2.224404
+C11 8 gnd 2.080806f
+R9 7 8 2.224404
+C12 9 gnd 2.080806f
+R10 8 9 2.224404
+C13 10 gnd 2.080806f
+R11 9 10 2.224404
+C14 11 gnd 2.080806f
+R12 10 11 2.224404
+C15 12 gnd 2.080806f
+R13 11 12 2.224404
+C16 13 gnd 2.080806f
+R14 12 13 2.224404
+C17 14 gnd 2.080806f
+R15 13 14 2.224404
+C18 15 gnd 2.080806f
+R16 14 15 2.224404
+C19 16 gnd 2.080806f
+R17 15 16 2.224404
+C20 17 gnd 2.080806f
+R18 16 17 2.224404
+C21 18 gnd 2.080806f
+R19 17 18 2.224404
+C22 19 gnd 2.080806f
+R20 18 19 2.224404
+C23 20 gnd 2.080806f
+R21 19 20 2.224404
+C24 21 gnd 2.080806f
+R22 21 20 2.224404
+C25 22 gnd 2.080806f
+R23 21 22 2.224404
+C26 23 gnd 2.080806f
+R24 22 23 2.224404
+C27 24 gnd 2.080806f
+R25 23 24 2.224404
+C28 25 gnd 2.080806f
+R26 24 25 2.224404
+C29 26 gnd 2.080806f
+R27 25 26 2.224404
+C30 27 gnd 2.080806f
+R28 26 27 2.224404
+C31 28 gnd 2.080806f
+R29 27 28 2.224404
+C32 29 gnd 2.080806f
+R30 28 29 2.224404
+C33 30 gnd 2.080806f
+R31 30 29 2.224404
+C34 31 gnd 2.080806f
+R32 30 31 2.224404
+C35 32 gnd 2.080806f
+R33 31 32 2.224404
+R34 32 g5499_1 2.224404
+.ends
+
+.subckt netg4359 g4359_1 g4359_2 g4359_0 gnd
+C1  g4359_1 gnd 2.080806f
+C2  g4359_2 gnd 2.080806f
+C3  g4359_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g4359_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 6 5 2.224404
+C10 7 gnd 2.080806f
+R7 6 7 2.224404
+R8 g4359_1 7 2.224404
+C11 8 gnd 2.080806f
+R9 8 1 2.224404
+C12 9 gnd 2.080806f
+R10 8 9 2.224404
+C13 10 gnd 2.080806f
+R11 9 10 2.224404
+C14 11 gnd 2.080806f
+R12 10 11 2.224404
+C15 12 gnd 2.080806f
+R13 11 12 2.224404
+C16 13 gnd 2.080806f
+R14 12 13 2.224404
+C17 14 gnd 2.080806f
+R15 13 14 2.224404
+C18 15 gnd 2.080806f
+R16 14 15 2.224404
+C19 16 gnd 2.080806f
+R17 15 16 2.224404
+C20 17 gnd 2.080806f
+R18 16 17 2.224404
+C21 18 gnd 2.080806f
+R19 18 17 2.224404
+C22 19 gnd 2.080806f
+R20 18 19 2.224404
+C23 20 gnd 2.080806f
+R21 19 20 2.224404
+C24 21 gnd 2.080806f
+R22 20 21 2.224404
+C25 22 gnd 2.080806f
+R23 21 22 2.224404
+C26 23 gnd 2.080806f
+R24 23 22 2.224404
+C27 24 gnd 2.080806f
+R25 24 23 2.224404
+C28 25 gnd 2.080806f
+R26 24 25 2.224404
+C29 26 gnd 2.080806f
+R27 25 26 2.224404
+C30 27 gnd 2.080806f
+R28 27 26 2.224404
+C31 28 gnd 2.080806f
+R29 27 28 2.224404
+C32 29 gnd 2.080806f
+R30 28 29 2.224404
+R31 29 g4359_2 2.224404
+.ends
+
+.subckt netg646 g646_3 g646_4 g646_0 g646_5 g646_2 g646_1 gnd
+C1  g646_3 gnd 2.080806f
+C2  g646_4 gnd 2.080806f
+C3  g646_0 gnd 2.080806f
+C4  g646_5 gnd 2.080806f
+C5  g646_2 gnd 2.080806f
+C6  g646_1 gnd 2.080806f
+R1 g646_1 g646_0 2.224404
+C7 1 gnd 2.080806f
+R2 1 g646_1 2.224404
+C8 2 gnd 2.080806f
+R3 2 1 2.224404
+C9 3 gnd 2.080806f
+R4 3 2 2.224404
+C10 4 gnd 2.080806f
+R5 3 4 2.224404
+C11 5 gnd 2.080806f
+R6 4 5 2.224404
+C12 6 gnd 2.080806f
+R7 6 5 2.224404
+C13 7 gnd 2.080806f
+R8 6 7 2.224404
+R9 g646_3 7 2.224404
+C14 8 gnd 2.080806f
+R10 7 8 2.224404
+C15 9 gnd 2.080806f
+R11 8 9 2.224404
+C16 10 gnd 2.080806f
+R12 9 10 2.224404
+C17 11 gnd 2.080806f
+R13 10 11 2.224404
+R14 11 g646_4 2.224404
+C18 12 gnd 2.080806f
+R15 12 9 2.224404
+C19 13 gnd 2.080806f
+R16 12 13 2.224404
+C20 14 gnd 2.080806f
+R17 14 13 2.224404
+C21 15 gnd 2.080806f
+R18 15 14 2.224404
+C22 16 gnd 2.080806f
+R19 16 15 2.224404
+C23 17 gnd 2.080806f
+R20 17 16 2.224404
+C24 18 gnd 2.080806f
+R21 18 17 2.224404
+C25 19 gnd 2.080806f
+R22 18 19 2.224404
+R23 g646_5 19 2.224404
+C26 20 gnd 2.080806f
+R24 g646_5 20 2.224404
+C27 21 gnd 2.080806f
+R25 20 21 2.224404
+C28 22 gnd 2.080806f
+R26 22 21 2.224404
+C29 23 gnd 2.080806f
+R27 23 22 2.224404
+C30 24 gnd 2.080806f
+R28 23 24 2.224404
+C31 25 gnd 2.080806f
+R29 25 24 2.224404
+C32 26 gnd 2.080806f
+R30 25 26 2.224404
+C33 27 gnd 2.080806f
+R31 26 27 2.224404
+C34 28 gnd 2.080806f
+R32 28 27 2.224404
+C35 29 gnd 2.080806f
+R33 28 29 2.224404
+R34 g646_2 29 2.224404
+.ends
+
+.subckt netg2300 g2300_0 g2300_2 g2300_3 g2300_1 gnd
+C1  g2300_0 gnd 2.080806f
+C2  g2300_2 gnd 2.080806f
+C3  g2300_3 gnd 2.080806f
+C4  g2300_1 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g2300_0 2.224404
+R2 1 g2300_2 2.224404
+C6 2 gnd 2.080806f
+R3 2 1 2.224404
+C7 3 gnd 2.080806f
+R4 3 2 2.224404
+C8 4 gnd 2.080806f
+R5 4 3 2.224404
+C9 5 gnd 2.080806f
+R6 5 4 2.224404
+C10 6 gnd 2.080806f
+R7 6 5 2.224404
+C11 7 gnd 2.080806f
+R8 7 6 2.224404
+C12 8 gnd 2.080806f
+R9 8 7 2.224404
+C13 9 gnd 2.080806f
+R10 9 8 2.224404
+C14 10 gnd 2.080806f
+R11 10 9 2.224404
+C15 11 gnd 2.080806f
+R12 11 10 2.224404
+C16 12 gnd 2.080806f
+R13 12 11 2.224404
+C17 13 gnd 2.080806f
+R14 13 12 2.224404
+C18 14 gnd 2.080806f
+R15 14 13 2.224404
+C19 15 gnd 2.080806f
+R16 15 14 2.224404
+C20 16 gnd 2.080806f
+R17 16 15 2.224404
+R18 g2300_3 16 2.224404
+C21 17 gnd 2.080806f
+R19 17 16 2.224404
+C22 18 gnd 2.080806f
+R20 18 17 2.224404
+C23 19 gnd 2.080806f
+R21 19 18 2.224404
+C24 20 gnd 2.080806f
+R22 20 19 2.224404
+C25 21 gnd 2.080806f
+R23 21 20 2.224404
+C26 22 gnd 2.080806f
+R24 22 21 2.224404
+C27 23 gnd 2.080806f
+R25 23 22 2.224404
+C28 24 gnd 2.080806f
+R26 24 23 2.224404
+C29 25 gnd 2.080806f
+R27 25 24 2.224404
+C30 26 gnd 2.080806f
+R28 26 25 2.224404
+C31 27 gnd 2.080806f
+R29 27 26 2.224404
+C32 28 gnd 2.080806f
+R30 28 27 2.224404
+C33 29 gnd 2.080806f
+R31 29 28 2.224404
+R32 g2300_1 29 2.224404
+.ends
+
+.subckt netg4876 g4876_3 g4876_1 g4876_0 g4876_2 gnd
+C1  g4876_3 gnd 2.080806f
+C2  g4876_1 gnd 2.080806f
+C3  g4876_0 gnd 2.080806f
+C4  g4876_2 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g4876_0 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+C7 3 gnd 2.080806f
+R3 3 2 2.224404
+C8 4 gnd 2.080806f
+R4 4 3 2.224404
+C9 5 gnd 2.080806f
+R5 5 4 2.224404
+C10 6 gnd 2.080806f
+R6 6 5 2.224404
+C11 7 gnd 2.080806f
+R7 7 6 2.224404
+C12 8 gnd 2.080806f
+R8 8 7 2.224404
+C13 9 gnd 2.080806f
+R9 9 8 2.224404
+C14 10 gnd 2.080806f
+R10 10 9 2.224404
+C15 11 gnd 2.080806f
+R11 11 10 2.224404
+C16 12 gnd 2.080806f
+R12 12 11 2.224404
+C17 13 gnd 2.080806f
+R13 13 12 2.224404
+C18 14 gnd 2.080806f
+R14 14 13 2.224404
+C19 15 gnd 2.080806f
+R15 15 14 2.224404
+C20 16 gnd 2.080806f
+R16 16 15 2.224404
+C21 17 gnd 2.080806f
+R17 17 16 2.224404
+C22 18 gnd 2.080806f
+R18 18 17 2.224404
+C23 19 gnd 2.080806f
+R19 19 18 2.224404
+C24 20 gnd 2.080806f
+R20 20 19 2.224404
+C25 21 gnd 2.080806f
+R21 21 20 2.224404
+C26 22 gnd 2.080806f
+R22 22 21 2.224404
+C27 23 gnd 2.080806f
+R23 23 22 2.224404
+R24 g4876_2 23 2.224404
+C28 24 gnd 2.080806f
+R25 24 21 2.224404
+C29 25 gnd 2.080806f
+R26 25 24 2.224404
+C30 26 gnd 2.080806f
+R27 26 25 2.224404
+C31 27 gnd 2.080806f
+R28 27 26 2.224404
+C32 28 gnd 2.080806f
+R29 28 27 2.224404
+C33 29 gnd 2.080806f
+R30 29 28 2.224404
+C34 30 gnd 2.080806f
+R31 30 29 2.224404
+C35 31 gnd 2.080806f
+R32 31 30 2.224404
+R33 g4876_3 31 2.224404
+C36 32 gnd 2.080806f
+R34 31 32 2.224404
+R35 g4876_1 32 2.224404
+.ends
+
+.subckt netg450 g450_4 g450_0 g450_3 g450_1 g450_2 gnd
+C1  g450_4 gnd 2.080806f
+C2  g450_0 gnd 2.080806f
+C3  g450_3 gnd 2.080806f
+C4  g450_1 gnd 2.080806f
+C5  g450_2 gnd 2.080806f
+C6 1 gnd 2.080806f
+R1 g450_0 1 2.224404
+C7 2 gnd 2.080806f
+R2 1 2 2.224404
+C8 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g450_4 2.224404
+C9 4 gnd 2.080806f
+R5 g450_0 4 2.224404
+C10 5 gnd 2.080806f
+R6 4 5 2.224404
+C11 6 gnd 2.080806f
+R7 5 6 2.224404
+C12 7 gnd 2.080806f
+R8 6 7 2.224404
+R9 7 g450_2 2.224404
+C13 8 gnd 2.080806f
+R10 g450_2 8 2.224404
+C14 9 gnd 2.080806f
+R11 8 9 2.224404
+C15 10 gnd 2.080806f
+R12 9 10 2.224404
+C16 11 gnd 2.080806f
+R13 10 11 2.224404
+R14 11 g450_3 2.224404
+C17 12 gnd 2.080806f
+R15 12 g450_0 2.224404
+C18 13 gnd 2.080806f
+R16 13 12 2.224404
+C19 14 gnd 2.080806f
+R17 14 13 2.224404
+C20 15 gnd 2.080806f
+R18 15 14 2.224404
+C21 16 gnd 2.080806f
+R19 16 15 2.224404
+C22 17 gnd 2.080806f
+R20 17 16 2.224404
+C23 18 gnd 2.080806f
+R21 18 17 2.224404
+C24 19 gnd 2.080806f
+R22 19 18 2.224404
+C25 20 gnd 2.080806f
+R23 20 19 2.224404
+C26 21 gnd 2.080806f
+R24 21 20 2.224404
+C27 22 gnd 2.080806f
+R25 22 21 2.224404
+C28 23 gnd 2.080806f
+R26 23 22 2.224404
+C29 24 gnd 2.080806f
+R27 24 23 2.224404
+C30 25 gnd 2.080806f
+R28 25 24 2.224404
+C31 26 gnd 2.080806f
+R29 26 25 2.224404
+C32 27 gnd 2.080806f
+R30 27 26 2.224404
+C33 28 gnd 2.080806f
+R31 28 27 2.224404
+C34 29 gnd 2.080806f
+R32 29 28 2.224404
+C35 30 gnd 2.080806f
+R33 30 29 2.224404
+C36 31 gnd 2.080806f
+R34 31 30 2.224404
+R35 g450_1 31 2.224404
+.ends
+
+.subckt netg2296 g2296_3 g2296_2 g2296_1 g2296_0 gnd
+C1  g2296_3 gnd 2.080806f
+C2  g2296_2 gnd 2.080806f
+C3  g2296_1 gnd 2.080806f
+C4  g2296_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g2296_0 1 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+C7 3 gnd 2.080806f
+R3 2 3 2.224404
+C8 4 gnd 2.080806f
+R4 3 4 2.224404
+C9 5 gnd 2.080806f
+R5 5 4 2.224404
+C10 6 gnd 2.080806f
+R6 5 6 2.224404
+C11 7 gnd 2.080806f
+R7 6 7 2.224404
+C12 8 gnd 2.080806f
+R8 8 7 2.224404
+R9 8 g2296_1 2.224404
+C13 9 gnd 2.080806f
+R10 g2296_1 9 2.224404
+C14 10 gnd 2.080806f
+R11 9 10 2.224404
+C15 11 gnd 2.080806f
+R12 10 11 2.224404
+C16 12 gnd 2.080806f
+R13 11 12 2.224404
+C17 13 gnd 2.080806f
+R14 12 13 2.224404
+C18 14 gnd 2.080806f
+R15 13 14 2.224404
+C19 15 gnd 2.080806f
+R16 14 15 2.224404
+C20 16 gnd 2.080806f
+R17 15 16 2.224404
+C21 17 gnd 2.080806f
+R18 16 17 2.224404
+C22 18 gnd 2.080806f
+R19 17 18 2.224404
+C23 19 gnd 2.080806f
+R20 18 19 2.224404
+C24 20 gnd 2.080806f
+R21 19 20 2.224404
+C25 21 gnd 2.080806f
+R22 20 21 2.224404
+C26 22 gnd 2.080806f
+R23 21 22 2.224404
+C27 23 gnd 2.080806f
+R24 22 23 2.224404
+C28 24 gnd 2.080806f
+R25 23 24 2.224404
+C29 25 gnd 2.080806f
+R26 24 25 2.224404
+C30 26 gnd 2.080806f
+R27 25 26 2.224404
+C31 27 gnd 2.080806f
+R28 26 27 2.224404
+C32 28 gnd 2.080806f
+R29 27 28 2.224404
+C33 29 gnd 2.080806f
+R30 28 29 2.224404
+C34 30 gnd 2.080806f
+R31 29 30 2.224404
+R32 30 g2296_2 2.224404
+C35 31 gnd 2.080806f
+R33 31 g2296_2 2.224404
+R34 31 g2296_3 2.224404
+.ends
+
+.subckt netg1832 g1832_1 g1832_3 g1832_0 g1832_2 gnd
+C1  g1832_1 gnd 2.080806f
+C2  g1832_3 gnd 2.080806f
+C3  g1832_0 gnd 2.080806f
+C4  g1832_2 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g1832_0 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+C7 3 gnd 2.080806f
+R3 3 2 2.224404
+C8 4 gnd 2.080806f
+R4 4 3 2.224404
+C9 5 gnd 2.080806f
+R5 5 4 2.224404
+C10 6 gnd 2.080806f
+R6 6 5 2.224404
+C11 7 gnd 2.080806f
+R7 7 6 2.224404
+R8 g1832_1 7 2.224404
+C12 8 gnd 2.080806f
+R9 g1832_1 8 2.224404
+C13 9 gnd 2.080806f
+R10 8 9 2.224404
+C14 10 gnd 2.080806f
+R11 10 9 2.224404
+C15 11 gnd 2.080806f
+R12 10 11 2.224404
+C16 12 gnd 2.080806f
+R13 11 12 2.224404
+C17 13 gnd 2.080806f
+R14 13 12 2.224404
+C18 14 gnd 2.080806f
+R15 13 14 2.224404
+C19 15 gnd 2.080806f
+R16 14 15 2.224404
+C20 16 gnd 2.080806f
+R17 15 16 2.224404
+R18 g1832_2 16 2.224404
+C21 17 gnd 2.080806f
+R19 17 g1832_2 2.224404
+C22 18 gnd 2.080806f
+R20 18 17 2.224404
+C23 19 gnd 2.080806f
+R21 19 18 2.224404
+C24 20 gnd 2.080806f
+R22 20 19 2.224404
+C25 21 gnd 2.080806f
+R23 21 20 2.224404
+C26 22 gnd 2.080806f
+R24 22 21 2.224404
+C27 23 gnd 2.080806f
+R25 23 22 2.224404
+C28 24 gnd 2.080806f
+R26 24 23 2.224404
+C29 25 gnd 2.080806f
+R27 25 24 2.224404
+C30 26 gnd 2.080806f
+R28 26 25 2.224404
+C31 27 gnd 2.080806f
+R29 27 26 2.224404
+C32 28 gnd 2.080806f
+R30 28 27 2.224404
+C33 29 gnd 2.080806f
+R31 29 28 2.224404
+C34 30 gnd 2.080806f
+R32 30 29 2.224404
+C35 31 gnd 2.080806f
+R33 31 30 2.224404
+C36 32 gnd 2.080806f
+R34 32 31 2.224404
+C37 33 gnd 2.080806f
+R35 33 32 2.224404
+C38 34 gnd 2.080806f
+R36 34 33 2.224404
+R37 g1832_3 34 2.224404
+.ends
+
+.subckt netg3852 g3852_3 g3852_2 g3852_8 g3852_9 g3852_0 g3852_5 g3852_7 g3852_1 g3852_6 g3852_4 gnd
+C1  g3852_3 gnd 2.080806f
+C2  g3852_2 gnd 2.080806f
+C3  g3852_8 gnd 2.080806f
+C4  g3852_9 gnd 2.080806f
+C5  g3852_0 gnd 2.080806f
+C6  g3852_5 gnd 2.080806f
+C7  g3852_7 gnd 2.080806f
+C8  g3852_1 gnd 2.080806f
+C9  g3852_6 gnd 2.080806f
+C10  g3852_4 gnd 2.080806f
+C11 1 gnd 2.080806f
+R1 1 g3852_0 2.224404
+R2 1 g3852_1 2.224404
+C12 2 gnd 2.080806f
+R3 g3852_0 2 2.224404
+R4 2 g3852_2 2.224404
+C13 3 gnd 2.080806f
+R5 g3852_1 3 2.224404
+R6 3 g3852_8 2.224404
+C14 4 gnd 2.080806f
+R7 g3852_8 4 2.224404
+C15 5 gnd 2.080806f
+R8 4 5 2.224404
+R9 5 g3852_4 2.224404
+C16 6 gnd 2.080806f
+R10 6 2 2.224404
+C17 7 gnd 2.080806f
+R11 7 6 2.224404
+R12 g3852_3 7 2.224404
+C18 8 gnd 2.080806f
+R13 8 g3852_3 2.224404
+R14 g3852_7 8 2.224404
+C19 9 gnd 2.080806f
+R15 9 g3852_7 2.224404
+C20 10 gnd 2.080806f
+R16 10 9 2.224404
+C21 11 gnd 2.080806f
+R17 10 11 2.224404
+R18 g3852_9 11 2.224404
+C22 12 gnd 2.080806f
+R19 g3852_4 12 2.224404
+C23 13 gnd 2.080806f
+R20 12 13 2.224404
+C24 14 gnd 2.080806f
+R21 14 13 2.224404
+C25 15 gnd 2.080806f
+R22 14 15 2.224404
+C26 16 gnd 2.080806f
+R23 15 16 2.224404
+C27 17 gnd 2.080806f
+R24 16 17 2.224404
+R25 17 g3852_5 2.224404
+C28 18 gnd 2.080806f
+R26 g3852_5 18 2.224404
+C29 19 gnd 2.080806f
+R27 18 19 2.224404
+C30 20 gnd 2.080806f
+R28 19 20 2.224404
+C31 21 gnd 2.080806f
+R29 20 21 2.224404
+C32 22 gnd 2.080806f
+R30 21 22 2.224404
+C33 23 gnd 2.080806f
+R31 22 23 2.224404
+C34 24 gnd 2.080806f
+R32 23 24 2.224404
+C35 25 gnd 2.080806f
+R33 24 25 2.224404
+C36 26 gnd 2.080806f
+R34 25 26 2.224404
+C37 27 gnd 2.080806f
+R35 26 27 2.224404
+C38 28 gnd 2.080806f
+R36 28 27 2.224404
+C39 29 gnd 2.080806f
+R37 28 29 2.224404
+C40 30 gnd 2.080806f
+R38 29 30 2.224404
+C41 31 gnd 2.080806f
+R39 30 31 2.224404
+R40 31 g3852_6 2.224404
+.ends
+
+.subckt netg494 g494_5 g494_4 g494_3 g494_1 g494_2 g494_0 gnd
+C1  g494_5 gnd 2.080806f
+C2  g494_4 gnd 2.080806f
+C3  g494_3 gnd 2.080806f
+C4  g494_1 gnd 2.080806f
+C5  g494_2 gnd 2.080806f
+C6  g494_0 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 g494_0 1 2.224404
+C8 2 gnd 2.080806f
+R2 1 2 2.224404
+C9 3 gnd 2.080806f
+R3 2 3 2.224404
+C10 4 gnd 2.080806f
+R4 3 4 2.224404
+C11 5 gnd 2.080806f
+R5 4 5 2.224404
+C12 6 gnd 2.080806f
+R6 5 6 2.224404
+C13 7 gnd 2.080806f
+R7 6 7 2.224404
+C14 8 gnd 2.080806f
+R8 7 8 2.224404
+C15 9 gnd 2.080806f
+R9 8 9 2.224404
+C16 10 gnd 2.080806f
+R10 9 10 2.224404
+R11 10 g494_1 2.224404
+C17 11 gnd 2.080806f
+R12 g494_1 11 2.224404
+C18 12 gnd 2.080806f
+R13 11 12 2.224404
+C19 13 gnd 2.080806f
+R14 12 13 2.224404
+R15 13 g494_4 2.224404
+C20 14 gnd 2.080806f
+R16 13 14 2.224404
+C21 15 gnd 2.080806f
+R17 14 15 2.224404
+C22 16 gnd 2.080806f
+R18 15 16 2.224404
+C23 17 gnd 2.080806f
+R19 16 17 2.224404
+R20 17 g494_2 2.224404
+C24 18 gnd 2.080806f
+R21 18 8 2.224404
+C25 19 gnd 2.080806f
+R22 19 18 2.224404
+C26 20 gnd 2.080806f
+R23 20 19 2.224404
+C27 21 gnd 2.080806f
+R24 21 20 2.224404
+C28 22 gnd 2.080806f
+R25 22 21 2.224404
+C29 23 gnd 2.080806f
+R26 22 23 2.224404
+R27 23 g494_5 2.224404
+C30 24 gnd 2.080806f
+R28 g494_2 24 2.224404
+C31 25 gnd 2.080806f
+R29 24 25 2.224404
+C32 26 gnd 2.080806f
+R30 25 26 2.224404
+C33 27 gnd 2.080806f
+R31 26 27 2.224404
+C34 28 gnd 2.080806f
+R32 27 28 2.224404
+C35 29 gnd 2.080806f
+R33 28 29 2.224404
+C36 30 gnd 2.080806f
+R34 29 30 2.224404
+C37 31 gnd 2.080806f
+R35 30 31 2.224404
+R36 31 g494_3 2.224404
+.ends
+
+.subckt netg4377 g4377_0 g4377_2 g4377_1 gnd
+C1  g4377_0 gnd 2.080806f
+C2  g4377_2 gnd 2.080806f
+C3  g4377_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g4377_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 6 5 2.224404
+C10 7 gnd 2.080806f
+R7 7 6 2.224404
+C11 8 gnd 2.080806f
+R8 8 7 2.224404
+C12 9 gnd 2.080806f
+R9 9 8 2.224404
+C13 10 gnd 2.080806f
+R10 10 9 2.224404
+C14 11 gnd 2.080806f
+R11 11 10 2.224404
+C15 12 gnd 2.080806f
+R12 12 11 2.224404
+C16 13 gnd 2.080806f
+R13 12 13 2.224404
+C17 14 gnd 2.080806f
+R14 14 13 2.224404
+C18 15 gnd 2.080806f
+R15 15 14 2.224404
+C19 16 gnd 2.080806f
+R16 16 15 2.224404
+R17 g4377_1 16 2.224404
+C20 17 gnd 2.080806f
+R18 1 17 2.224404
+C21 18 gnd 2.080806f
+R19 17 18 2.224404
+C22 19 gnd 2.080806f
+R20 18 19 2.224404
+C23 20 gnd 2.080806f
+R21 20 19 2.224404
+C24 21 gnd 2.080806f
+R22 21 20 2.224404
+C25 22 gnd 2.080806f
+R23 22 21 2.224404
+C26 23 gnd 2.080806f
+R24 22 23 2.224404
+C27 24 gnd 2.080806f
+R25 23 24 2.224404
+C28 25 gnd 2.080806f
+R26 24 25 2.224404
+C29 26 gnd 2.080806f
+R27 25 26 2.224404
+C30 27 gnd 2.080806f
+R28 26 27 2.224404
+C31 28 gnd 2.080806f
+R29 27 28 2.224404
+C32 29 gnd 2.080806f
+R30 28 29 2.224404
+C33 30 gnd 2.080806f
+R31 30 29 2.224404
+C34 31 gnd 2.080806f
+R32 30 31 2.224404
+C35 32 gnd 2.080806f
+R33 31 32 2.224404
+R34 32 g4377_2 2.224404
+.ends
+
+.subckt netg6203 g6203_0 g6203_1 gnd
+C1  g6203_0 gnd 2.080806f
+C2  g6203_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g6203_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+R35 g6203_1 34 2.224404
+.ends
+
+.subckt netg1612 g1612_2 g1612_1 g1612_0 g1612_3 gnd
+C1  g1612_2 gnd 2.080806f
+C2  g1612_1 gnd 2.080806f
+C3  g1612_0 gnd 2.080806f
+C4  g1612_3 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g1612_0 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+C7 3 gnd 2.080806f
+R3 3 2 2.224404
+C8 4 gnd 2.080806f
+R4 4 3 2.224404
+C9 5 gnd 2.080806f
+R5 5 4 2.224404
+C10 6 gnd 2.080806f
+R6 6 5 2.224404
+R7 g1612_3 6 2.224404
+C11 7 gnd 2.080806f
+R8 7 g1612_3 2.224404
+R9 7 g1612_1 2.224404
+C12 8 gnd 2.080806f
+R10 1 8 2.224404
+C13 9 gnd 2.080806f
+R11 8 9 2.224404
+C14 10 gnd 2.080806f
+R12 9 10 2.224404
+C15 11 gnd 2.080806f
+R13 10 11 2.224404
+C16 12 gnd 2.080806f
+R14 11 12 2.224404
+C17 13 gnd 2.080806f
+R15 13 12 2.224404
+C18 14 gnd 2.080806f
+R16 13 14 2.224404
+C19 15 gnd 2.080806f
+R17 14 15 2.224404
+C20 16 gnd 2.080806f
+R18 15 16 2.224404
+C21 17 gnd 2.080806f
+R19 16 17 2.224404
+C22 18 gnd 2.080806f
+R20 17 18 2.224404
+C23 19 gnd 2.080806f
+R21 18 19 2.224404
+C24 20 gnd 2.080806f
+R22 19 20 2.224404
+C25 21 gnd 2.080806f
+R23 20 21 2.224404
+C26 22 gnd 2.080806f
+R24 21 22 2.224404
+C27 23 gnd 2.080806f
+R25 22 23 2.224404
+C28 24 gnd 2.080806f
+R26 23 24 2.224404
+C29 25 gnd 2.080806f
+R27 24 25 2.224404
+C30 26 gnd 2.080806f
+R28 25 26 2.224404
+C31 27 gnd 2.080806f
+R29 26 27 2.224404
+C32 28 gnd 2.080806f
+R30 27 28 2.224404
+C33 29 gnd 2.080806f
+R31 28 29 2.224404
+C34 30 gnd 2.080806f
+R32 29 30 2.224404
+C35 31 gnd 2.080806f
+R33 30 31 2.224404
+C36 32 gnd 2.080806f
+R34 31 32 2.224404
+R35 32 g1612_2 2.224404
+.ends
+
+.subckt netg1604 g1604_3 g1604_0 g1604_2 g1604_1 gnd
+C1  g1604_3 gnd 2.080806f
+C2  g1604_0 gnd 2.080806f
+C3  g1604_2 gnd 2.080806f
+C4  g1604_1 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g1604_0 1 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+C7 3 gnd 2.080806f
+R3 2 3 2.224404
+C8 4 gnd 2.080806f
+R4 3 4 2.224404
+C9 5 gnd 2.080806f
+R5 4 5 2.224404
+C10 6 gnd 2.080806f
+R6 5 6 2.224404
+C11 7 gnd 2.080806f
+R7 6 7 2.224404
+C12 8 gnd 2.080806f
+R8 7 8 2.224404
+C13 9 gnd 2.080806f
+R9 8 9 2.224404
+C14 10 gnd 2.080806f
+R10 9 10 2.224404
+C15 11 gnd 2.080806f
+R11 10 11 2.224404
+C16 12 gnd 2.080806f
+R12 11 12 2.224404
+C17 13 gnd 2.080806f
+R13 12 13 2.224404
+C18 14 gnd 2.080806f
+R14 13 14 2.224404
+C19 15 gnd 2.080806f
+R15 14 15 2.224404
+C20 16 gnd 2.080806f
+R16 15 16 2.224404
+C21 17 gnd 2.080806f
+R17 16 17 2.224404
+C22 18 gnd 2.080806f
+R18 17 18 2.224404
+C23 19 gnd 2.080806f
+R19 18 19 2.224404
+C24 20 gnd 2.080806f
+R20 19 20 2.224404
+C25 21 gnd 2.080806f
+R21 20 21 2.224404
+C26 22 gnd 2.080806f
+R22 21 22 2.224404
+C27 23 gnd 2.080806f
+R23 22 23 2.224404
+C28 24 gnd 2.080806f
+R24 23 24 2.224404
+R25 24 g1604_1 2.224404
+C29 25 gnd 2.080806f
+R26 g1604_1 25 2.224404
+C30 26 gnd 2.080806f
+R27 26 25 2.224404
+C31 27 gnd 2.080806f
+R28 27 26 2.224404
+C32 28 gnd 2.080806f
+R29 28 27 2.224404
+C33 29 gnd 2.080806f
+R30 28 29 2.224404
+C34 30 gnd 2.080806f
+R31 29 30 2.224404
+R32 30 g1604_3 2.224404
+C35 31 gnd 2.080806f
+R33 g1604_3 31 2.224404
+R34 31 g1604_2 2.224404
+.ends
+
+.subckt netg2115 g2115_2 g2115_3 g2115_1 gnd
+C1  g2115_2 gnd 2.080806f
+C2  g2115_3 gnd 2.080806f
+C3  g2115_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g2115_3 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 6 5 2.224404
+C10 7 gnd 2.080806f
+R7 7 6 2.224404
+C11 8 gnd 2.080806f
+R8 7 8 2.224404
+C12 9 gnd 2.080806f
+R9 9 8 2.224404
+C13 10 gnd 2.080806f
+R10 10 9 2.224404
+C14 11 gnd 2.080806f
+R11 11 10 2.224404
+C15 12 gnd 2.080806f
+R12 12 11 2.224404
+C16 13 gnd 2.080806f
+R13 13 12 2.224404
+C17 14 gnd 2.080806f
+R14 14 13 2.224404
+C18 15 gnd 2.080806f
+R15 15 14 2.224404
+C19 16 gnd 2.080806f
+R16 16 15 2.224404
+C20 17 gnd 2.080806f
+R17 17 16 2.224404
+C21 18 gnd 2.080806f
+R18 18 17 2.224404
+C22 19 gnd 2.080806f
+R19 19 18 2.224404
+C23 20 gnd 2.080806f
+R20 20 19 2.224404
+C24 21 gnd 2.080806f
+R21 21 20 2.224404
+C25 22 gnd 2.080806f
+R22 22 21 2.224404
+C26 23 gnd 2.080806f
+R23 23 22 2.224404
+C27 24 gnd 2.080806f
+R24 24 23 2.224404
+C28 25 gnd 2.080806f
+R25 25 24 2.224404
+C29 26 gnd 2.080806f
+R26 26 25 2.224404
+C30 27 gnd 2.080806f
+R27 27 26 2.224404
+C31 28 gnd 2.080806f
+R28 28 27 2.224404
+R29 g2115_1 28 2.224404
+C32 29 gnd 2.080806f
+R30 29 g2115_1 2.224404
+C33 30 gnd 2.080806f
+R31 30 29 2.224404
+C34 31 gnd 2.080806f
+R32 31 30 2.224404
+C35 32 gnd 2.080806f
+R33 32 31 2.224404
+R34 g2115_2 32 2.224404
+.ends
+
+.subckt netg3355 g3355_2 g3355_1 g3355_0 gnd
+C1  g3355_2 gnd 2.080806f
+C2  g3355_1 gnd 2.080806f
+C3  g3355_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g3355_0 2.224404
+R2 g3355_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g3355_1 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 11 10 2.224404
+C15 12 gnd 2.080806f
+R13 11 12 2.224404
+C16 13 gnd 2.080806f
+R14 12 13 2.224404
+C17 14 gnd 2.080806f
+R15 13 14 2.224404
+C18 15 gnd 2.080806f
+R16 15 14 2.224404
+C19 16 gnd 2.080806f
+R17 16 15 2.224404
+C20 17 gnd 2.080806f
+R18 17 16 2.224404
+C21 18 gnd 2.080806f
+R19 18 17 2.224404
+C22 19 gnd 2.080806f
+R20 19 18 2.224404
+C23 20 gnd 2.080806f
+R21 20 19 2.224404
+C24 21 gnd 2.080806f
+R22 21 20 2.224404
+C25 22 gnd 2.080806f
+R23 22 21 2.224404
+C26 23 gnd 2.080806f
+R24 23 22 2.224404
+C27 24 gnd 2.080806f
+R25 24 23 2.224404
+C28 25 gnd 2.080806f
+R26 25 24 2.224404
+C29 26 gnd 2.080806f
+R27 26 25 2.224404
+C30 27 gnd 2.080806f
+R28 27 26 2.224404
+C31 28 gnd 2.080806f
+R29 28 27 2.224404
+C32 29 gnd 2.080806f
+R30 29 28 2.224404
+C33 30 gnd 2.080806f
+R31 30 29 2.224404
+C34 31 gnd 2.080806f
+R32 31 30 2.224404
+C35 32 gnd 2.080806f
+R33 32 31 2.224404
+C36 33 gnd 2.080806f
+R34 33 32 2.224404
+C37 34 gnd 2.080806f
+R35 33 34 2.224404
+R36 g3355_2 34 2.224404
+.ends
+
+.subckt netg2194 g2194_0 g2194_2 g2194_5 g2194_1 g2194_4 g2194_3 gnd
+C1  g2194_0 gnd 2.080806f
+C2  g2194_2 gnd 2.080806f
+C3  g2194_5 gnd 2.080806f
+C4  g2194_1 gnd 2.080806f
+C5  g2194_4 gnd 2.080806f
+C6  g2194_3 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 g2194_0 1 2.224404
+C8 2 gnd 2.080806f
+R2 1 2 2.224404
+C9 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g2194_1 2.224404
+C10 4 gnd 2.080806f
+R5 2 4 2.224404
+C11 5 gnd 2.080806f
+R6 4 5 2.224404
+R7 5 g2194_2 2.224404
+C12 6 gnd 2.080806f
+R8 g2194_2 6 2.224404
+R9 6 g2194_3 2.224404
+C13 7 gnd 2.080806f
+R10 g2194_1 7 2.224404
+C14 8 gnd 2.080806f
+R11 7 8 2.224404
+C15 9 gnd 2.080806f
+R12 9 8 2.224404
+C16 10 gnd 2.080806f
+R13 9 10 2.224404
+R14 g2194_4 10 2.224404
+C17 11 gnd 2.080806f
+R15 g2194_3 11 2.224404
+C18 12 gnd 2.080806f
+R16 11 12 2.224404
+C19 13 gnd 2.080806f
+R17 12 13 2.224404
+C20 14 gnd 2.080806f
+R18 13 14 2.224404
+C21 15 gnd 2.080806f
+R19 15 14 2.224404
+C22 16 gnd 2.080806f
+R20 15 16 2.224404
+C23 17 gnd 2.080806f
+R21 16 17 2.224404
+C24 18 gnd 2.080806f
+R22 17 18 2.224404
+C25 19 gnd 2.080806f
+R23 18 19 2.224404
+C26 20 gnd 2.080806f
+R24 19 20 2.224404
+C27 21 gnd 2.080806f
+R25 20 21 2.224404
+C28 22 gnd 2.080806f
+R26 21 22 2.224404
+C29 23 gnd 2.080806f
+R27 22 23 2.224404
+C30 24 gnd 2.080806f
+R28 23 24 2.224404
+C31 25 gnd 2.080806f
+R29 24 25 2.224404
+C32 26 gnd 2.080806f
+R30 25 26 2.224404
+C33 27 gnd 2.080806f
+R31 26 27 2.224404
+C34 28 gnd 2.080806f
+R32 27 28 2.224404
+C35 29 gnd 2.080806f
+R33 28 29 2.224404
+C36 30 gnd 2.080806f
+R34 29 30 2.224404
+C37 31 gnd 2.080806f
+R35 30 31 2.224404
+C38 32 gnd 2.080806f
+R36 31 32 2.224404
+C39 33 gnd 2.080806f
+R37 32 33 2.224404
+C40 34 gnd 2.080806f
+R38 33 34 2.224404
+R39 34 g2194_5 2.224404
+.ends
+
+.subckt netg59 g59_1 g59_0 gnd
+C1  g59_1 gnd 2.080806f
+C2  g59_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g59_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+R32 g59_1 31 2.224404
+.ends
+
+.subckt netg532 g532_1 g532_0 g532_5 g532_4 g532_3 gnd
+C1  g532_1 gnd 2.080806f
+C2  g532_0 gnd 2.080806f
+C3  g532_5 gnd 2.080806f
+C4  g532_4 gnd 2.080806f
+C5  g532_3 gnd 2.080806f
+C6 1 gnd 2.080806f
+R1 1 g532_0 2.224404
+C7 2 gnd 2.080806f
+R2 2 1 2.224404
+C8 3 gnd 2.080806f
+R3 3 2 2.224404
+C9 4 gnd 2.080806f
+R4 4 3 2.224404
+C10 5 gnd 2.080806f
+R5 5 4 2.224404
+C11 6 gnd 2.080806f
+R6 6 5 2.224404
+R7 g532_5 6 2.224404
+C12 7 gnd 2.080806f
+R8 g532_5 7 2.224404
+C13 8 gnd 2.080806f
+R9 8 7 2.224404
+C14 9 gnd 2.080806f
+R10 9 8 2.224404
+C15 10 gnd 2.080806f
+R11 10 9 2.224404
+C16 11 gnd 2.080806f
+R12 10 11 2.224404
+R13 g532_3 11 2.224404
+C17 12 gnd 2.080806f
+R14 g532_0 12 2.224404
+C18 13 gnd 2.080806f
+R15 12 13 2.224404
+C19 14 gnd 2.080806f
+R16 13 14 2.224404
+C20 15 gnd 2.080806f
+R17 14 15 2.224404
+C21 16 gnd 2.080806f
+R18 15 16 2.224404
+C22 17 gnd 2.080806f
+R19 16 17 2.224404
+C23 18 gnd 2.080806f
+R20 17 18 2.224404
+C24 19 gnd 2.080806f
+R21 18 19 2.224404
+C25 20 gnd 2.080806f
+R22 19 20 2.224404
+C26 21 gnd 2.080806f
+R23 20 21 2.224404
+C27 22 gnd 2.080806f
+R24 21 22 2.224404
+C28 23 gnd 2.080806f
+R25 22 23 2.224404
+C29 24 gnd 2.080806f
+R26 23 24 2.224404
+C30 25 gnd 2.080806f
+R27 24 25 2.224404
+C31 26 gnd 2.080806f
+R28 25 26 2.224404
+C32 27 gnd 2.080806f
+R29 26 27 2.224404
+C33 28 gnd 2.080806f
+R30 27 28 2.224404
+R31 28 g532_1 2.224404
+C34 29 gnd 2.080806f
+R32 28 29 2.224404
+C35 30 gnd 2.080806f
+R33 29 30 2.224404
+R34 30 g532_4 2.224404
+.ends
+
+.subckt netg41 g41_1 g41_0 gnd
+C1  g41_1 gnd 2.080806f
+C2  g41_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g41_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+R32 31 g41_1 2.224404
+.ends
+
+.subckt netg6520 g6520_0 g6520_1 gnd
+C1  g6520_0 gnd 2.080806f
+C2  g6520_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6520_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+R32 31 g6520_1 2.224404
+.ends
+
+.subckt netg36 g36_1 g36_0 gnd
+C1  g36_1 gnd 2.080806f
+C2  g36_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g36_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+R32 g36_1 31 2.224404
+.ends
+
+.subckt netg6597 g6597_3 g6597_0 g6597_6 g6597_2 g6597_1 g6597_4 g6597_5 gnd
+C1  g6597_3 gnd 2.080806f
+C2  g6597_0 gnd 2.080806f
+C3  g6597_6 gnd 2.080806f
+C4  g6597_2 gnd 2.080806f
+C5  g6597_1 gnd 2.080806f
+C6  g6597_4 gnd 2.080806f
+C7  g6597_5 gnd 2.080806f
+R1 g6597_1 g6597_0 2.224404
+C8 1 gnd 2.080806f
+R2 1 g6597_0 2.224404
+C9 2 gnd 2.080806f
+R3 2 1 2.224404
+C10 3 gnd 2.080806f
+R4 3 2 2.224404
+C11 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 g6597_5 4 2.224404
+C12 5 gnd 2.080806f
+R7 g6597_5 5 2.224404
+C13 6 gnd 2.080806f
+R8 5 6 2.224404
+R9 g6597_4 6 2.224404
+C14 7 gnd 2.080806f
+R10 7 g6597_5 2.224404
+C15 8 gnd 2.080806f
+R11 8 7 2.224404
+R12 g6597_6 8 2.224404
+C16 9 gnd 2.080806f
+R13 6 9 2.224404
+C17 10 gnd 2.080806f
+R14 9 10 2.224404
+C18 11 gnd 2.080806f
+R15 10 11 2.224404
+C19 12 gnd 2.080806f
+R16 11 12 2.224404
+C20 13 gnd 2.080806f
+R17 12 13 2.224404
+C21 14 gnd 2.080806f
+R18 13 14 2.224404
+C22 15 gnd 2.080806f
+R19 14 15 2.224404
+C23 16 gnd 2.080806f
+R20 15 16 2.224404
+C24 17 gnd 2.080806f
+R21 16 17 2.224404
+C25 18 gnd 2.080806f
+R22 17 18 2.224404
+C26 19 gnd 2.080806f
+R23 18 19 2.224404
+R24 19 g6597_3 2.224404
+C27 20 gnd 2.080806f
+R25 g6597_3 20 2.224404
+C28 21 gnd 2.080806f
+R26 20 21 2.224404
+C29 22 gnd 2.080806f
+R27 21 22 2.224404
+C30 23 gnd 2.080806f
+R28 22 23 2.224404
+C31 24 gnd 2.080806f
+R29 23 24 2.224404
+C32 25 gnd 2.080806f
+R30 24 25 2.224404
+C33 26 gnd 2.080806f
+R31 25 26 2.224404
+C34 27 gnd 2.080806f
+R32 26 27 2.224404
+C35 28 gnd 2.080806f
+R33 27 28 2.224404
+C36 29 gnd 2.080806f
+R34 28 29 2.224404
+C37 30 gnd 2.080806f
+R35 29 30 2.224404
+C38 31 gnd 2.080806f
+R36 30 31 2.224404
+C39 32 gnd 2.080806f
+R37 31 32 2.224404
+C40 33 gnd 2.080806f
+R38 33 32 2.224404
+C41 34 gnd 2.080806f
+R39 33 34 2.224404
+R40 g6597_2 34 2.224404
+.ends
+
+.subckt netg3845 g3845_4 g3845_2 g3845_3 g3845_1 g3845_6 g3845_5 g3845_0 gnd
+C1  g3845_4 gnd 2.080806f
+C2  g3845_2 gnd 2.080806f
+C3  g3845_3 gnd 2.080806f
+C4  g3845_1 gnd 2.080806f
+C5  g3845_6 gnd 2.080806f
+C6  g3845_5 gnd 2.080806f
+C7  g3845_0 gnd 2.080806f
+C8 1 gnd 2.080806f
+R1 1 g3845_0 2.224404
+R2 g3845_1 1 2.224404
+C9 2 gnd 2.080806f
+R3 g3845_1 2 2.224404
+C10 3 gnd 2.080806f
+R4 3 2 2.224404
+C11 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 g3845_5 4 2.224404
+C12 5 gnd 2.080806f
+R7 g3845_0 5 2.224404
+C13 6 gnd 2.080806f
+R8 5 6 2.224404
+C14 7 gnd 2.080806f
+R9 6 7 2.224404
+C15 8 gnd 2.080806f
+R10 7 8 2.224404
+C16 9 gnd 2.080806f
+R11 8 9 2.224404
+R12 9 g3845_6 2.224404
+C17 10 gnd 2.080806f
+R13 9 10 2.224404
+R14 10 g3845_2 2.224404
+C18 11 gnd 2.080806f
+R15 g3845_2 11 2.224404
+C19 12 gnd 2.080806f
+R16 11 12 2.224404
+C20 13 gnd 2.080806f
+R17 12 13 2.224404
+R18 13 g3845_4 2.224404
+C21 14 gnd 2.080806f
+R19 14 g3845_1 2.224404
+C22 15 gnd 2.080806f
+R20 15 14 2.224404
+C23 16 gnd 2.080806f
+R21 16 15 2.224404
+C24 17 gnd 2.080806f
+R22 17 16 2.224404
+C25 18 gnd 2.080806f
+R23 18 17 2.224404
+C26 19 gnd 2.080806f
+R24 19 18 2.224404
+C27 20 gnd 2.080806f
+R25 20 19 2.224404
+C28 21 gnd 2.080806f
+R26 21 20 2.224404
+C29 22 gnd 2.080806f
+R27 22 21 2.224404
+C30 23 gnd 2.080806f
+R28 23 22 2.224404
+C31 24 gnd 2.080806f
+R29 24 23 2.224404
+C32 25 gnd 2.080806f
+R30 25 24 2.224404
+C33 26 gnd 2.080806f
+R31 26 25 2.224404
+C34 27 gnd 2.080806f
+R32 27 26 2.224404
+C35 28 gnd 2.080806f
+R33 28 27 2.224404
+C36 29 gnd 2.080806f
+R34 29 28 2.224404
+C37 30 gnd 2.080806f
+R35 30 29 2.224404
+C38 31 gnd 2.080806f
+R36 31 30 2.224404
+C39 32 gnd 2.080806f
+R37 32 31 2.224404
+R38 g3845_3 32 2.224404
+.ends
+
+.subckt netg2203 g2203_1 g2203_5 g2203_3 g2203_4 g2203_2 gnd
+C1  g2203_1 gnd 2.080806f
+C2  g2203_5 gnd 2.080806f
+C3  g2203_3 gnd 2.080806f
+C4  g2203_4 gnd 2.080806f
+C5  g2203_2 gnd 2.080806f
+C6 1 gnd 2.080806f
+R1 g2203_4 1 2.224404
+C7 2 gnd 2.080806f
+R2 1 2 2.224404
+C8 3 gnd 2.080806f
+R3 2 3 2.224404
+C9 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 4 g2203_1 2.224404
+C10 5 gnd 2.080806f
+R6 g2203_1 5 2.224404
+C11 6 gnd 2.080806f
+R7 5 6 2.224404
+C12 7 gnd 2.080806f
+R8 6 7 2.224404
+C13 8 gnd 2.080806f
+R9 7 8 2.224404
+R10 8 g2203_5 2.224404
+C14 9 gnd 2.080806f
+R11 g2203_5 9 2.224404
+C15 10 gnd 2.080806f
+R12 9 10 2.224404
+C16 11 gnd 2.080806f
+R13 10 11 2.224404
+C17 12 gnd 2.080806f
+R14 11 12 2.224404
+C18 13 gnd 2.080806f
+R15 12 13 2.224404
+C19 14 gnd 2.080806f
+R16 13 14 2.224404
+C20 15 gnd 2.080806f
+R17 14 15 2.224404
+C21 16 gnd 2.080806f
+R18 15 16 2.224404
+C22 17 gnd 2.080806f
+R19 16 17 2.224404
+C23 18 gnd 2.080806f
+R20 17 18 2.224404
+C24 19 gnd 2.080806f
+R21 18 19 2.224404
+C25 20 gnd 2.080806f
+R22 19 20 2.224404
+C26 21 gnd 2.080806f
+R23 20 21 2.224404
+C27 22 gnd 2.080806f
+R24 21 22 2.224404
+C28 23 gnd 2.080806f
+R25 23 22 2.224404
+C29 24 gnd 2.080806f
+R26 23 24 2.224404
+C30 25 gnd 2.080806f
+R27 24 25 2.224404
+C31 26 gnd 2.080806f
+R28 25 26 2.224404
+C32 27 gnd 2.080806f
+R29 26 27 2.224404
+C33 28 gnd 2.080806f
+R30 27 28 2.224404
+C34 29 gnd 2.080806f
+R31 28 29 2.224404
+C35 30 gnd 2.080806f
+R32 29 30 2.224404
+C36 31 gnd 2.080806f
+R33 31 30 2.224404
+C37 32 gnd 2.080806f
+R34 32 31 2.224404
+C38 33 gnd 2.080806f
+R35 32 33 2.224404
+C39 34 gnd 2.080806f
+R36 33 34 2.224404
+C40 35 gnd 2.080806f
+R37 34 35 2.224404
+C41 36 gnd 2.080806f
+R38 35 36 2.224404
+R39 36 g2203_2 2.224404
+C42 37 gnd 2.080806f
+R40 37 36 2.224404
+C43 38 gnd 2.080806f
+R41 38 37 2.224404
+R42 g2203_3 38 2.224404
+.ends
+
+.subckt netg2421 g2421_1 g2421_0 gnd
+C1  g2421_1 gnd 2.080806f
+C2  g2421_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g2421_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+R35 g2421_1 34 2.224404
+.ends
+
+.subckt netg6408 g6408_1 g6408_0 gnd
+C1  g6408_1 gnd 2.080806f
+C2  g6408_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g6408_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+R33 32 g6408_1 2.224404
+.ends
+
+.subckt netg3687 g3687_0 g3687_2 g3687_1 g3687_3 gnd
+C1  g3687_0 gnd 2.080806f
+C2  g3687_2 gnd 2.080806f
+C3  g3687_1 gnd 2.080806f
+C4  g3687_3 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g3687_0 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+C7 3 gnd 2.080806f
+R3 3 2 2.224404
+C8 4 gnd 2.080806f
+R4 4 3 2.224404
+C9 5 gnd 2.080806f
+R5 5 4 2.224404
+C10 6 gnd 2.080806f
+R6 6 5 2.224404
+C11 7 gnd 2.080806f
+R7 6 7 2.224404
+C12 8 gnd 2.080806f
+R8 8 7 2.224404
+R9 g3687_2 8 2.224404
+C13 9 gnd 2.080806f
+R10 9 1 2.224404
+C14 10 gnd 2.080806f
+R11 9 10 2.224404
+C15 11 gnd 2.080806f
+R12 10 11 2.224404
+C16 12 gnd 2.080806f
+R13 11 12 2.224404
+C17 13 gnd 2.080806f
+R14 12 13 2.224404
+C18 14 gnd 2.080806f
+R15 13 14 2.224404
+C19 15 gnd 2.080806f
+R16 14 15 2.224404
+C20 16 gnd 2.080806f
+R17 15 16 2.224404
+C21 17 gnd 2.080806f
+R18 17 16 2.224404
+C22 18 gnd 2.080806f
+R19 17 18 2.224404
+C23 19 gnd 2.080806f
+R20 18 19 2.224404
+C24 20 gnd 2.080806f
+R21 19 20 2.224404
+C25 21 gnd 2.080806f
+R22 21 20 2.224404
+C26 22 gnd 2.080806f
+R23 21 22 2.224404
+C27 23 gnd 2.080806f
+R24 22 23 2.224404
+C28 24 gnd 2.080806f
+R25 23 24 2.224404
+C29 25 gnd 2.080806f
+R26 24 25 2.224404
+C30 26 gnd 2.080806f
+R27 25 26 2.224404
+C31 27 gnd 2.080806f
+R28 26 27 2.224404
+C32 28 gnd 2.080806f
+R29 27 28 2.224404
+C33 29 gnd 2.080806f
+R30 28 29 2.224404
+C34 30 gnd 2.080806f
+R31 30 29 2.224404
+C35 31 gnd 2.080806f
+R32 30 31 2.224404
+C36 32 gnd 2.080806f
+R33 31 32 2.224404
+R34 32 g3687_1 2.224404
+C37 33 gnd 2.080806f
+R35 33 g3687_1 2.224404
+R36 g3687_3 33 2.224404
+.ends
+
+.subckt netg5816 g5816_3 g5816_2 g5816_1 g5816_0 gnd
+C1  g5816_3 gnd 2.080806f
+C2  g5816_2 gnd 2.080806f
+C3  g5816_1 gnd 2.080806f
+C4  g5816_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g5816_0 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g5816_3 2 2.224404
+R4 g5816_2 g5816_3 2.224404
+C7 3 gnd 2.080806f
+R5 3 g5816_0 2.224404
+C8 4 gnd 2.080806f
+R6 4 3 2.224404
+C9 5 gnd 2.080806f
+R7 5 4 2.224404
+C10 6 gnd 2.080806f
+R8 6 5 2.224404
+C11 7 gnd 2.080806f
+R9 7 6 2.224404
+C12 8 gnd 2.080806f
+R10 8 7 2.224404
+C13 9 gnd 2.080806f
+R11 9 8 2.224404
+C14 10 gnd 2.080806f
+R12 10 9 2.224404
+C15 11 gnd 2.080806f
+R13 10 11 2.224404
+C16 12 gnd 2.080806f
+R14 12 11 2.224404
+C17 13 gnd 2.080806f
+R15 13 12 2.224404
+C18 14 gnd 2.080806f
+R16 14 13 2.224404
+C19 15 gnd 2.080806f
+R17 15 14 2.224404
+C20 16 gnd 2.080806f
+R18 16 15 2.224404
+C21 17 gnd 2.080806f
+R19 17 16 2.224404
+C22 18 gnd 2.080806f
+R20 18 17 2.224404
+C23 19 gnd 2.080806f
+R21 19 18 2.224404
+C24 20 gnd 2.080806f
+R22 20 19 2.224404
+C25 21 gnd 2.080806f
+R23 21 20 2.224404
+C26 22 gnd 2.080806f
+R24 21 22 2.224404
+C27 23 gnd 2.080806f
+R25 22 23 2.224404
+C28 24 gnd 2.080806f
+R26 23 24 2.224404
+C29 25 gnd 2.080806f
+R27 25 24 2.224404
+C30 26 gnd 2.080806f
+R28 26 25 2.224404
+C31 27 gnd 2.080806f
+R29 26 27 2.224404
+C32 28 gnd 2.080806f
+R30 28 27 2.224404
+C33 29 gnd 2.080806f
+R31 28 29 2.224404
+C34 30 gnd 2.080806f
+R32 29 30 2.224404
+R33 30 g5816_1 2.224404
+.ends
+
+.subckt netg37 g37_1 g37_0 gnd
+C1  g37_1 gnd 2.080806f
+C2  g37_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g37_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+R33 32 g37_1 2.224404
+.ends
+
+.subckt netg699 g699_3 g699_2 g699_4 g699_1 g699_5 g699_0 gnd
+C1  g699_3 gnd 2.080806f
+C2  g699_2 gnd 2.080806f
+C3  g699_4 gnd 2.080806f
+C4  g699_1 gnd 2.080806f
+C5  g699_5 gnd 2.080806f
+C6  g699_0 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g699_0 2.224404
+C8 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g699_4 2 2.224404
+C9 3 gnd 2.080806f
+R4 g699_0 3 2.224404
+C10 4 gnd 2.080806f
+R5 3 4 2.224404
+C11 5 gnd 2.080806f
+R6 4 5 2.224404
+C12 6 gnd 2.080806f
+R7 5 6 2.224404
+C13 7 gnd 2.080806f
+R8 6 7 2.224404
+R9 7 g699_2 2.224404
+C14 8 gnd 2.080806f
+R10 g699_2 8 2.224404
+C15 9 gnd 2.080806f
+R11 8 9 2.224404
+C16 10 gnd 2.080806f
+R12 9 10 2.224404
+C17 11 gnd 2.080806f
+R13 10 11 2.224404
+C18 12 gnd 2.080806f
+R14 11 12 2.224404
+C19 13 gnd 2.080806f
+R15 12 13 2.224404
+C20 14 gnd 2.080806f
+R16 13 14 2.224404
+C21 15 gnd 2.080806f
+R17 14 15 2.224404
+C22 16 gnd 2.080806f
+R18 15 16 2.224404
+C23 17 gnd 2.080806f
+R19 16 17 2.224404
+C24 18 gnd 2.080806f
+R20 17 18 2.224404
+C25 19 gnd 2.080806f
+R21 18 19 2.224404
+C26 20 gnd 2.080806f
+R22 19 20 2.224404
+C27 21 gnd 2.080806f
+R23 20 21 2.224404
+C28 22 gnd 2.080806f
+R24 21 22 2.224404
+C29 23 gnd 2.080806f
+R25 22 23 2.224404
+C30 24 gnd 2.080806f
+R26 24 23 2.224404
+C31 25 gnd 2.080806f
+R27 24 25 2.224404
+C32 26 gnd 2.080806f
+R28 25 26 2.224404
+C33 27 gnd 2.080806f
+R29 27 26 2.224404
+C34 28 gnd 2.080806f
+R30 28 27 2.224404
+C35 29 gnd 2.080806f
+R31 28 29 2.224404
+C36 30 gnd 2.080806f
+R32 30 29 2.224404
+C37 31 gnd 2.080806f
+R33 31 30 2.224404
+C38 32 gnd 2.080806f
+R34 31 32 2.224404
+C39 33 gnd 2.080806f
+R35 33 32 2.224404
+R36 33 g699_3 2.224404
+C40 34 gnd 2.080806f
+R37 34 g699_3 2.224404
+C41 35 gnd 2.080806f
+R38 34 35 2.224404
+C42 36 gnd 2.080806f
+R39 35 36 2.224404
+R40 36 g699_5 2.224404
+C43 37 gnd 2.080806f
+R41 g699_5 37 2.224404
+C44 38 gnd 2.080806f
+R42 37 38 2.224404
+C45 39 gnd 2.080806f
+R43 38 39 2.224404
+C46 40 gnd 2.080806f
+R44 39 40 2.224404
+C47 41 gnd 2.080806f
+R45 40 41 2.224404
+C48 42 gnd 2.080806f
+R46 42 41 2.224404
+C49 43 gnd 2.080806f
+R47 42 43 2.224404
+R48 43 g699_1 2.224404
+.ends
+
+.subckt netg47 g47_0 g47_1 gnd
+C1  g47_0 gnd 2.080806f
+C2  g47_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g47_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+R33 g47_1 32 2.224404
+.ends
+
+.subckt netg799 g799_3 g799_1 g799_0 g799_2 g799_5 g799_4 gnd
+C1  g799_3 gnd 2.080806f
+C2  g799_1 gnd 2.080806f
+C3  g799_0 gnd 2.080806f
+C4  g799_2 gnd 2.080806f
+C5  g799_5 gnd 2.080806f
+C6  g799_4 gnd 2.080806f
+R1 g799_0 g799_2 2.224404
+C7 1 gnd 2.080806f
+R2 g799_0 1 2.224404
+C8 2 gnd 2.080806f
+R3 1 2 2.224404
+C9 3 gnd 2.080806f
+R4 3 2 2.224404
+C10 4 gnd 2.080806f
+R5 3 4 2.224404
+C11 5 gnd 2.080806f
+R6 4 5 2.224404
+C12 6 gnd 2.080806f
+R7 6 5 2.224404
+C13 7 gnd 2.080806f
+R8 6 7 2.224404
+R9 g799_5 7 2.224404
+C14 8 gnd 2.080806f
+R10 8 g799_5 2.224404
+C15 9 gnd 2.080806f
+R11 9 8 2.224404
+C16 10 gnd 2.080806f
+R12 10 9 2.224404
+C17 11 gnd 2.080806f
+R13 11 10 2.224404
+C18 12 gnd 2.080806f
+R14 12 11 2.224404
+C19 13 gnd 2.080806f
+R15 13 12 2.224404
+R16 g799_4 13 2.224404
+C20 14 gnd 2.080806f
+R17 14 g799_4 2.224404
+C21 15 gnd 2.080806f
+R18 15 14 2.224404
+C22 16 gnd 2.080806f
+R19 16 15 2.224404
+C23 17 gnd 2.080806f
+R20 17 16 2.224404
+C24 18 gnd 2.080806f
+R21 18 17 2.224404
+C25 19 gnd 2.080806f
+R22 19 18 2.224404
+C26 20 gnd 2.080806f
+R23 20 19 2.224404
+C27 21 gnd 2.080806f
+R24 21 20 2.224404
+C28 22 gnd 2.080806f
+R25 22 21 2.224404
+C29 23 gnd 2.080806f
+R26 23 22 2.224404
+C30 24 gnd 2.080806f
+R27 24 23 2.224404
+C31 25 gnd 2.080806f
+R28 25 24 2.224404
+C32 26 gnd 2.080806f
+R29 26 25 2.224404
+C33 27 gnd 2.080806f
+R30 27 26 2.224404
+C34 28 gnd 2.080806f
+R31 28 27 2.224404
+C35 29 gnd 2.080806f
+R32 29 28 2.224404
+C36 30 gnd 2.080806f
+R33 30 29 2.224404
+C37 31 gnd 2.080806f
+R34 31 30 2.224404
+C38 32 gnd 2.080806f
+R35 32 31 2.224404
+R36 g799_3 32 2.224404
+C39 33 gnd 2.080806f
+R37 33 g799_3 2.224404
+C40 34 gnd 2.080806f
+R38 33 34 2.224404
+C41 35 gnd 2.080806f
+R39 34 35 2.224404
+C42 36 gnd 2.080806f
+R40 36 35 2.224404
+C43 37 gnd 2.080806f
+R41 37 36 2.224404
+R42 g799_1 37 2.224404
+.ends
+
+.subckt netg1462 g1462_3 g1462_1 g1462_2 g1462_5 g1462_4 g1462_0 gnd
+C1  g1462_3 gnd 2.080806f
+C2  g1462_1 gnd 2.080806f
+C3  g1462_2 gnd 2.080806f
+C4  g1462_5 gnd 2.080806f
+C5  g1462_4 gnd 2.080806f
+C6  g1462_0 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 g1462_0 1 2.224404
+C8 2 gnd 2.080806f
+R2 2 1 2.224404
+C9 3 gnd 2.080806f
+R3 3 2 2.224404
+C10 4 gnd 2.080806f
+R4 3 4 2.224404
+C11 5 gnd 2.080806f
+R5 5 4 2.224404
+R6 g1462_4 5 2.224404
+C12 6 gnd 2.080806f
+R7 6 g1462_4 2.224404
+C13 7 gnd 2.080806f
+R8 7 6 2.224404
+R9 g1462_1 7 2.224404
+C14 8 gnd 2.080806f
+R10 8 g1462_0 2.224404
+C15 9 gnd 2.080806f
+R11 9 8 2.224404
+C16 10 gnd 2.080806f
+R12 10 9 2.224404
+C17 11 gnd 2.080806f
+R13 10 11 2.224404
+C18 12 gnd 2.080806f
+R14 11 12 2.224404
+C19 13 gnd 2.080806f
+R15 12 13 2.224404
+C20 14 gnd 2.080806f
+R16 13 14 2.224404
+C21 15 gnd 2.080806f
+R17 14 15 2.224404
+C22 16 gnd 2.080806f
+R18 15 16 2.224404
+C23 17 gnd 2.080806f
+R19 16 17 2.224404
+C24 18 gnd 2.080806f
+R20 17 18 2.224404
+C25 19 gnd 2.080806f
+R21 18 19 2.224404
+C26 20 gnd 2.080806f
+R22 19 20 2.224404
+C27 21 gnd 2.080806f
+R23 20 21 2.224404
+C28 22 gnd 2.080806f
+R24 21 22 2.224404
+C29 23 gnd 2.080806f
+R25 22 23 2.224404
+R26 23 g1462_3 2.224404
+C30 24 gnd 2.080806f
+R27 g1462_3 24 2.224404
+C31 25 gnd 2.080806f
+R28 24 25 2.224404
+C32 26 gnd 2.080806f
+R29 25 26 2.224404
+C33 27 gnd 2.080806f
+R30 26 27 2.224404
+C34 28 gnd 2.080806f
+R31 27 28 2.224404
+C35 29 gnd 2.080806f
+R32 28 29 2.224404
+C36 30 gnd 2.080806f
+R33 29 30 2.224404
+C37 31 gnd 2.080806f
+R34 30 31 2.224404
+C38 32 gnd 2.080806f
+R35 31 32 2.224404
+C39 33 gnd 2.080806f
+R36 32 33 2.224404
+C40 34 gnd 2.080806f
+R37 33 34 2.224404
+C41 35 gnd 2.080806f
+R38 34 35 2.224404
+C42 36 gnd 2.080806f
+R39 35 36 2.224404
+C43 37 gnd 2.080806f
+R40 36 37 2.224404
+R41 37 g1462_2 2.224404
+R42 g1462_2 g1462_5 2.224404
+.ends
+
+.subckt netg672 g672_1 g672_3 g672_2 g672_4 g672_0 g672_5 gnd
+C1  g672_1 gnd 2.080806f
+C2  g672_3 gnd 2.080806f
+C3  g672_2 gnd 2.080806f
+C4  g672_4 gnd 2.080806f
+C5  g672_0 gnd 2.080806f
+C6  g672_5 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g672_0 2.224404
+R2 g672_3 1 2.224404
+C8 2 gnd 2.080806f
+R3 g672_3 2 2.224404
+C9 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 3 g672_5 2.224404
+C10 4 gnd 2.080806f
+R6 g672_5 4 2.224404
+C11 5 gnd 2.080806f
+R7 4 5 2.224404
+C12 6 gnd 2.080806f
+R8 5 6 2.224404
+C13 7 gnd 2.080806f
+R9 6 7 2.224404
+C14 8 gnd 2.080806f
+R10 7 8 2.224404
+C15 9 gnd 2.080806f
+R11 8 9 2.224404
+C16 10 gnd 2.080806f
+R12 9 10 2.224404
+C17 11 gnd 2.080806f
+R13 10 11 2.224404
+R14 11 g672_1 2.224404
+C18 12 gnd 2.080806f
+R15 g672_1 12 2.224404
+C19 13 gnd 2.080806f
+R16 12 13 2.224404
+C20 14 gnd 2.080806f
+R17 13 14 2.224404
+C21 15 gnd 2.080806f
+R18 14 15 2.224404
+C22 16 gnd 2.080806f
+R19 15 16 2.224404
+C23 17 gnd 2.080806f
+R20 16 17 2.224404
+C24 18 gnd 2.080806f
+R21 17 18 2.224404
+C25 19 gnd 2.080806f
+R22 18 19 2.224404
+C26 20 gnd 2.080806f
+R23 19 20 2.224404
+C27 21 gnd 2.080806f
+R24 20 21 2.224404
+C28 22 gnd 2.080806f
+R25 21 22 2.224404
+R26 22 g672_2 2.224404
+C29 23 gnd 2.080806f
+R27 12 23 2.224404
+C30 24 gnd 2.080806f
+R28 23 24 2.224404
+C31 25 gnd 2.080806f
+R29 24 25 2.224404
+C32 26 gnd 2.080806f
+R30 25 26 2.224404
+C33 27 gnd 2.080806f
+R31 26 27 2.224404
+C34 28 gnd 2.080806f
+R32 27 28 2.224404
+C35 29 gnd 2.080806f
+R33 28 29 2.224404
+C36 30 gnd 2.080806f
+R34 29 30 2.224404
+C37 31 gnd 2.080806f
+R35 30 31 2.224404
+C38 32 gnd 2.080806f
+R36 31 32 2.224404
+R37 32 g672_4 2.224404
+.ends
+
+.subckt netg38 g38_0 g38_1 gnd
+C1  g38_0 gnd 2.080806f
+C2  g38_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g38_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+R34 g38_1 33 2.224404
+.ends
+
+.subckt netg6778 g6778_0 g6778_1 g6778_2 gnd
+C1  g6778_0 gnd 2.080806f
+C2  g6778_1 gnd 2.080806f
+C3  g6778_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g6778_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g6778_2 2.224404
+C6 3 gnd 2.080806f
+R4 g6778_0 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+C8 5 gnd 2.080806f
+R6 4 5 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+C10 7 gnd 2.080806f
+R8 6 7 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 8 9 2.224404
+C13 10 gnd 2.080806f
+R11 9 10 2.224404
+C14 11 gnd 2.080806f
+R12 10 11 2.224404
+C15 12 gnd 2.080806f
+R13 11 12 2.224404
+C16 13 gnd 2.080806f
+R14 12 13 2.224404
+C17 14 gnd 2.080806f
+R15 13 14 2.224404
+C18 15 gnd 2.080806f
+R16 14 15 2.224404
+C19 16 gnd 2.080806f
+R17 15 16 2.224404
+C20 17 gnd 2.080806f
+R18 16 17 2.224404
+C21 18 gnd 2.080806f
+R19 18 17 2.224404
+C22 19 gnd 2.080806f
+R20 19 18 2.224404
+C23 20 gnd 2.080806f
+R21 20 19 2.224404
+C24 21 gnd 2.080806f
+R22 20 21 2.224404
+C25 22 gnd 2.080806f
+R23 21 22 2.224404
+C26 23 gnd 2.080806f
+R24 22 23 2.224404
+C27 24 gnd 2.080806f
+R25 23 24 2.224404
+C28 25 gnd 2.080806f
+R26 25 24 2.224404
+C29 26 gnd 2.080806f
+R27 25 26 2.224404
+C30 27 gnd 2.080806f
+R28 26 27 2.224404
+C31 28 gnd 2.080806f
+R29 27 28 2.224404
+C32 29 gnd 2.080806f
+R30 29 28 2.224404
+C33 30 gnd 2.080806f
+R31 29 30 2.224404
+C34 31 gnd 2.080806f
+R32 30 31 2.224404
+C35 32 gnd 2.080806f
+R33 32 31 2.224404
+C36 33 gnd 2.080806f
+R34 32 33 2.224404
+C37 34 gnd 2.080806f
+R35 33 34 2.224404
+R36 34 g6778_1 2.224404
+.ends
+
+.subckt netg34 g34_1 g34_0 gnd
+C1  g34_1 gnd 2.080806f
+C2  g34_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g34_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+R34 33 g34_1 2.224404
+.ends
+
+.subckt netg5269 g5269_1 g5269_0 gnd
+C1  g5269_1 gnd 2.080806f
+C2  g5269_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g5269_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+R35 g5269_1 34 2.224404
+.ends
+
+.subckt netg3071 g3071_2 g3071_0 g3071_5 g3071_4 g3071_3 g3071_1 gnd
+C1  g3071_2 gnd 2.080806f
+C2  g3071_0 gnd 2.080806f
+C3  g3071_5 gnd 2.080806f
+C4  g3071_4 gnd 2.080806f
+C5  g3071_3 gnd 2.080806f
+C6  g3071_1 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g3071_0 2.224404
+C8 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g3071_4 2 2.224404
+C9 3 gnd 2.080806f
+R4 3 g3071_0 2.224404
+C10 4 gnd 2.080806f
+R5 4 3 2.224404
+C11 5 gnd 2.080806f
+R6 5 4 2.224404
+C12 6 gnd 2.080806f
+R7 6 5 2.224404
+C13 7 gnd 2.080806f
+R8 7 6 2.224404
+C14 8 gnd 2.080806f
+R9 8 7 2.224404
+C15 9 gnd 2.080806f
+R10 9 8 2.224404
+R11 g3071_1 9 2.224404
+R12 g3071_5 g3071_1 2.224404
+R13 g3071_2 g3071_5 2.224404
+C16 10 gnd 2.080806f
+R14 9 10 2.224404
+C17 11 gnd 2.080806f
+R15 10 11 2.224404
+C18 12 gnd 2.080806f
+R16 11 12 2.224404
+C19 13 gnd 2.080806f
+R17 12 13 2.224404
+C20 14 gnd 2.080806f
+R18 13 14 2.224404
+C21 15 gnd 2.080806f
+R19 14 15 2.224404
+C22 16 gnd 2.080806f
+R20 15 16 2.224404
+C23 17 gnd 2.080806f
+R21 16 17 2.224404
+C24 18 gnd 2.080806f
+R22 17 18 2.224404
+C25 19 gnd 2.080806f
+R23 18 19 2.224404
+C26 20 gnd 2.080806f
+R24 19 20 2.224404
+C27 21 gnd 2.080806f
+R25 20 21 2.224404
+C28 22 gnd 2.080806f
+R26 21 22 2.224404
+C29 23 gnd 2.080806f
+R27 22 23 2.224404
+C30 24 gnd 2.080806f
+R28 23 24 2.224404
+C31 25 gnd 2.080806f
+R29 24 25 2.224404
+C32 26 gnd 2.080806f
+R30 25 26 2.224404
+C33 27 gnd 2.080806f
+R31 26 27 2.224404
+C34 28 gnd 2.080806f
+R32 27 28 2.224404
+C35 29 gnd 2.080806f
+R33 28 29 2.224404
+C36 30 gnd 2.080806f
+R34 29 30 2.224404
+C37 31 gnd 2.080806f
+R35 30 31 2.224404
+C38 32 gnd 2.080806f
+R36 31 32 2.224404
+R37 32 g3071_3 2.224404
+.ends
+
+.subckt netg54 g54_1 g54_0 g54_2 gnd
+C1  g54_1 gnd 2.080806f
+C2  g54_0 gnd 2.080806f
+C3  g54_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g54_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+C8 5 gnd 2.080806f
+R5 4 5 2.224404
+C9 6 gnd 2.080806f
+R6 5 6 2.224404
+C10 7 gnd 2.080806f
+R7 6 7 2.224404
+C11 8 gnd 2.080806f
+R8 7 8 2.224404
+C12 9 gnd 2.080806f
+R9 8 9 2.224404
+C13 10 gnd 2.080806f
+R10 9 10 2.224404
+C14 11 gnd 2.080806f
+R11 10 11 2.224404
+C15 12 gnd 2.080806f
+R12 11 12 2.224404
+C16 13 gnd 2.080806f
+R13 13 12 2.224404
+C17 14 gnd 2.080806f
+R14 13 14 2.224404
+C18 15 gnd 2.080806f
+R15 14 15 2.224404
+C19 16 gnd 2.080806f
+R16 15 16 2.224404
+C20 17 gnd 2.080806f
+R17 16 17 2.224404
+C21 18 gnd 2.080806f
+R18 17 18 2.224404
+C22 19 gnd 2.080806f
+R19 18 19 2.224404
+C23 20 gnd 2.080806f
+R20 20 19 2.224404
+C24 21 gnd 2.080806f
+R21 20 21 2.224404
+R22 g54_1 21 2.224404
+C25 22 gnd 2.080806f
+R23 19 22 2.224404
+C26 23 gnd 2.080806f
+R24 22 23 2.224404
+C27 24 gnd 2.080806f
+R25 23 24 2.224404
+C28 25 gnd 2.080806f
+R26 24 25 2.224404
+C29 26 gnd 2.080806f
+R27 25 26 2.224404
+C30 27 gnd 2.080806f
+R28 26 27 2.224404
+C31 28 gnd 2.080806f
+R29 27 28 2.224404
+C32 29 gnd 2.080806f
+R30 28 29 2.224404
+C33 30 gnd 2.080806f
+R31 29 30 2.224404
+C34 31 gnd 2.080806f
+R32 30 31 2.224404
+C35 32 gnd 2.080806f
+R33 31 32 2.224404
+C36 33 gnd 2.080806f
+R34 32 33 2.224404
+C37 34 gnd 2.080806f
+R35 33 34 2.224404
+C38 35 gnd 2.080806f
+R36 34 35 2.224404
+C39 36 gnd 2.080806f
+R37 35 36 2.224404
+C40 37 gnd 2.080806f
+R38 36 37 2.224404
+R39 37 g54_2 2.224404
+.ends
+
+.subckt netg2182 g2182_5 g2182_2 g2182_1 g2182_4 g2182_3 g2182_0 gnd
+C1  g2182_5 gnd 2.080806f
+C2  g2182_2 gnd 2.080806f
+C3  g2182_1 gnd 2.080806f
+C4  g2182_4 gnd 2.080806f
+C5  g2182_3 gnd 2.080806f
+C6  g2182_0 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g2182_0 2.224404
+R2 g2182_5 1 2.224404
+R3 g2182_5 g2182_1 2.224404
+C8 2 gnd 2.080806f
+R4 g2182_1 2 2.224404
+C9 3 gnd 2.080806f
+R5 2 3 2.224404
+R6 3 g2182_2 2.224404
+C10 4 gnd 2.080806f
+R7 g2182_0 4 2.224404
+C11 5 gnd 2.080806f
+R8 4 5 2.224404
+C12 6 gnd 2.080806f
+R9 5 6 2.224404
+C13 7 gnd 2.080806f
+R10 6 7 2.224404
+C14 8 gnd 2.080806f
+R11 7 8 2.224404
+C15 9 gnd 2.080806f
+R12 8 9 2.224404
+C16 10 gnd 2.080806f
+R13 9 10 2.224404
+C17 11 gnd 2.080806f
+R14 10 11 2.224404
+C18 12 gnd 2.080806f
+R15 11 12 2.224404
+C19 13 gnd 2.080806f
+R16 12 13 2.224404
+C20 14 gnd 2.080806f
+R17 13 14 2.224404
+C21 15 gnd 2.080806f
+R18 14 15 2.224404
+C22 16 gnd 2.080806f
+R19 15 16 2.224404
+C23 17 gnd 2.080806f
+R20 16 17 2.224404
+C24 18 gnd 2.080806f
+R21 17 18 2.224404
+R22 g2182_4 18 2.224404
+C25 19 gnd 2.080806f
+R23 19 g2182_4 2.224404
+C26 20 gnd 2.080806f
+R24 19 20 2.224404
+C27 21 gnd 2.080806f
+R25 20 21 2.224404
+C28 22 gnd 2.080806f
+R26 21 22 2.224404
+C29 23 gnd 2.080806f
+R27 22 23 2.224404
+C30 24 gnd 2.080806f
+R28 23 24 2.224404
+C31 25 gnd 2.080806f
+R29 24 25 2.224404
+C32 26 gnd 2.080806f
+R30 25 26 2.224404
+C33 27 gnd 2.080806f
+R31 26 27 2.224404
+C34 28 gnd 2.080806f
+R32 27 28 2.224404
+C35 29 gnd 2.080806f
+R33 28 29 2.224404
+C36 30 gnd 2.080806f
+R34 29 30 2.224404
+C37 31 gnd 2.080806f
+R35 30 31 2.224404
+C38 32 gnd 2.080806f
+R36 31 32 2.224404
+C39 33 gnd 2.080806f
+R37 32 33 2.224404
+C40 34 gnd 2.080806f
+R38 33 34 2.224404
+C41 35 gnd 2.080806f
+R39 34 35 2.224404
+C42 36 gnd 2.080806f
+R40 35 36 2.224404
+C43 37 gnd 2.080806f
+R41 36 37 2.224404
+C44 38 gnd 2.080806f
+R42 37 38 2.224404
+R43 38 g2182_3 2.224404
+.ends
+
+.subckt netg442 g442_0 g442_2 g442_1 g442_3 gnd
+C1  g442_0 gnd 2.080806f
+C2  g442_2 gnd 2.080806f
+C3  g442_1 gnd 2.080806f
+C4  g442_3 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g442_0 2.224404
+R2 g442_2 1 2.224404
+C6 2 gnd 2.080806f
+R3 g442_0 2 2.224404
+C7 3 gnd 2.080806f
+R4 3 2 2.224404
+C8 4 gnd 2.080806f
+R5 4 3 2.224404
+C9 5 gnd 2.080806f
+R6 5 4 2.224404
+C10 6 gnd 2.080806f
+R7 6 5 2.224404
+C11 7 gnd 2.080806f
+R8 7 6 2.224404
+C12 8 gnd 2.080806f
+R9 8 7 2.224404
+C13 9 gnd 2.080806f
+R10 9 8 2.224404
+C14 10 gnd 2.080806f
+R11 10 9 2.224404
+C15 11 gnd 2.080806f
+R12 11 10 2.224404
+C16 12 gnd 2.080806f
+R13 12 11 2.224404
+C17 13 gnd 2.080806f
+R14 13 12 2.224404
+C18 14 gnd 2.080806f
+R15 14 13 2.224404
+C19 15 gnd 2.080806f
+R16 15 14 2.224404
+C20 16 gnd 2.080806f
+R17 16 15 2.224404
+C21 17 gnd 2.080806f
+R18 17 16 2.224404
+C22 18 gnd 2.080806f
+R19 18 17 2.224404
+C23 19 gnd 2.080806f
+R20 18 19 2.224404
+C24 20 gnd 2.080806f
+R21 19 20 2.224404
+C25 21 gnd 2.080806f
+R22 20 21 2.224404
+C26 22 gnd 2.080806f
+R23 22 21 2.224404
+C27 23 gnd 2.080806f
+R24 23 22 2.224404
+C28 24 gnd 2.080806f
+R25 23 24 2.224404
+C29 25 gnd 2.080806f
+R26 24 25 2.224404
+C30 26 gnd 2.080806f
+R27 26 25 2.224404
+C31 27 gnd 2.080806f
+R28 27 26 2.224404
+C32 28 gnd 2.080806f
+R29 28 27 2.224404
+C33 29 gnd 2.080806f
+R30 29 28 2.224404
+R31 g442_3 29 2.224404
+C34 30 gnd 2.080806f
+R32 30 g442_3 2.224404
+C35 31 gnd 2.080806f
+R33 31 30 2.224404
+C36 32 gnd 2.080806f
+R34 32 31 2.224404
+C37 33 gnd 2.080806f
+R35 33 32 2.224404
+C38 34 gnd 2.080806f
+R36 34 33 2.224404
+C39 35 gnd 2.080806f
+R37 34 35 2.224404
+C40 36 gnd 2.080806f
+R38 36 35 2.224404
+C41 37 gnd 2.080806f
+R39 36 37 2.224404
+C42 38 gnd 2.080806f
+R40 37 38 2.224404
+C43 39 gnd 2.080806f
+R41 39 38 2.224404
+C44 40 gnd 2.080806f
+R42 40 39 2.224404
+C45 41 gnd 2.080806f
+R43 41 40 2.224404
+C46 42 gnd 2.080806f
+R44 41 42 2.224404
+C47 43 gnd 2.080806f
+R45 43 42 2.224404
+C48 44 gnd 2.080806f
+R46 44 43 2.224404
+C49 45 gnd 2.080806f
+R47 45 44 2.224404
+C50 46 gnd 2.080806f
+R48 46 45 2.224404
+R49 g442_1 46 2.224404
+.ends
+
+.subckt netg1859 g1859_0 g1859_1 g1859_2 gnd
+C1  g1859_0 gnd 2.080806f
+C2  g1859_1 gnd 2.080806f
+C3  g1859_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g1859_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 6 5 2.224404
+C10 7 gnd 2.080806f
+R7 7 6 2.224404
+C11 8 gnd 2.080806f
+R8 8 7 2.224404
+C12 9 gnd 2.080806f
+R9 9 8 2.224404
+C13 10 gnd 2.080806f
+R10 10 9 2.224404
+C14 11 gnd 2.080806f
+R11 11 10 2.224404
+C15 12 gnd 2.080806f
+R12 12 11 2.224404
+C16 13 gnd 2.080806f
+R13 13 12 2.224404
+C17 14 gnd 2.080806f
+R14 14 13 2.224404
+C18 15 gnd 2.080806f
+R15 15 14 2.224404
+C19 16 gnd 2.080806f
+R16 16 15 2.224404
+C20 17 gnd 2.080806f
+R17 17 16 2.224404
+C21 18 gnd 2.080806f
+R18 18 17 2.224404
+C22 19 gnd 2.080806f
+R19 18 19 2.224404
+C23 20 gnd 2.080806f
+R20 19 20 2.224404
+C24 21 gnd 2.080806f
+R21 20 21 2.224404
+C25 22 gnd 2.080806f
+R22 22 21 2.224404
+C26 23 gnd 2.080806f
+R23 23 22 2.224404
+C27 24 gnd 2.080806f
+R24 24 23 2.224404
+C28 25 gnd 2.080806f
+R25 24 25 2.224404
+C29 26 gnd 2.080806f
+R26 26 25 2.224404
+C30 27 gnd 2.080806f
+R27 26 27 2.224404
+C31 28 gnd 2.080806f
+R28 28 27 2.224404
+C32 29 gnd 2.080806f
+R29 29 28 2.224404
+C33 30 gnd 2.080806f
+R30 30 29 2.224404
+C34 31 gnd 2.080806f
+R31 31 30 2.224404
+C35 32 gnd 2.080806f
+R32 32 31 2.224404
+C36 33 gnd 2.080806f
+R33 33 32 2.224404
+C37 34 gnd 2.080806f
+R34 34 33 2.224404
+C38 35 gnd 2.080806f
+R35 35 34 2.224404
+C39 36 gnd 2.080806f
+R36 36 35 2.224404
+R37 g1859_1 36 2.224404
+C40 37 gnd 2.080806f
+R38 37 g1859_1 2.224404
+C41 38 gnd 2.080806f
+R39 38 37 2.224404
+C42 39 gnd 2.080806f
+R40 38 39 2.224404
+C43 40 gnd 2.080806f
+R41 40 39 2.224404
+C44 41 gnd 2.080806f
+R42 41 40 2.224404
+C45 42 gnd 2.080806f
+R43 42 41 2.224404
+C46 43 gnd 2.080806f
+R44 42 43 2.224404
+C47 44 gnd 2.080806f
+R45 43 44 2.224404
+C48 45 gnd 2.080806f
+R46 45 44 2.224404
+C49 46 gnd 2.080806f
+R47 46 45 2.224404
+C50 47 gnd 2.080806f
+R48 47 46 2.224404
+C51 48 gnd 2.080806f
+R49 48 47 2.224404
+R50 g1859_2 48 2.224404
+.ends
+
+.subckt netg488 g488_3 g488_4 g488_2 g488_0 g488_1 g488_5 gnd
+C1  g488_3 gnd 2.080806f
+C2  g488_4 gnd 2.080806f
+C3  g488_2 gnd 2.080806f
+C4  g488_0 gnd 2.080806f
+C5  g488_1 gnd 2.080806f
+C6  g488_5 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g488_0 2.224404
+C8 2 gnd 2.080806f
+R2 2 1 2.224404
+C9 3 gnd 2.080806f
+R3 3 2 2.224404
+C10 4 gnd 2.080806f
+R4 4 3 2.224404
+C11 5 gnd 2.080806f
+R5 5 4 2.224404
+R6 g488_1 5 2.224404
+R7 g488_2 g488_1 2.224404
+C12 6 gnd 2.080806f
+R8 6 g488_0 2.224404
+C13 7 gnd 2.080806f
+R9 6 7 2.224404
+C14 8 gnd 2.080806f
+R10 7 8 2.224404
+C15 9 gnd 2.080806f
+R11 8 9 2.224404
+C16 10 gnd 2.080806f
+R12 9 10 2.224404
+C17 11 gnd 2.080806f
+R13 10 11 2.224404
+C18 12 gnd 2.080806f
+R14 11 12 2.224404
+C19 13 gnd 2.080806f
+R15 12 13 2.224404
+C20 14 gnd 2.080806f
+R16 13 14 2.224404
+C21 15 gnd 2.080806f
+R17 14 15 2.224404
+C22 16 gnd 2.080806f
+R18 15 16 2.224404
+C23 17 gnd 2.080806f
+R19 16 17 2.224404
+C24 18 gnd 2.080806f
+R20 17 18 2.224404
+C25 19 gnd 2.080806f
+R21 18 19 2.224404
+R22 19 g488_5 2.224404
+C26 20 gnd 2.080806f
+R23 g488_5 20 2.224404
+C27 21 gnd 2.080806f
+R24 20 21 2.224404
+C28 22 gnd 2.080806f
+R25 21 22 2.224404
+C29 23 gnd 2.080806f
+R26 22 23 2.224404
+C30 24 gnd 2.080806f
+R27 23 24 2.224404
+C31 25 gnd 2.080806f
+R28 24 25 2.224404
+C32 26 gnd 2.080806f
+R29 25 26 2.224404
+C33 27 gnd 2.080806f
+R30 26 27 2.224404
+C34 28 gnd 2.080806f
+R31 27 28 2.224404
+C35 29 gnd 2.080806f
+R32 28 29 2.224404
+R33 29 g488_4 2.224404
+C36 30 gnd 2.080806f
+R34 30 g488_4 2.224404
+C37 31 gnd 2.080806f
+R35 31 30 2.224404
+R36 g488_3 31 2.224404
+.ends
+
+.subckt netg35 g35_0 g35_1 gnd
+C1  g35_0 gnd 2.080806f
+C2  g35_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g35_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+R36 g35_1 35 2.224404
+.ends
+
+.subckt netg31 g31_1 g31_0 gnd
+C1  g31_1 gnd 2.080806f
+C2  g31_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g31_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+R36 g31_1 35 2.224404
+.ends
+
+.subckt netg64 g64_1 g64_0 g64_2 gnd
+C1  g64_1 gnd 2.080806f
+C2  g64_0 gnd 2.080806f
+C3  g64_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g64_0 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g64_2 2.224404
+C7 4 gnd 2.080806f
+R5 4 g64_2 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 11 10 2.224404
+C15 12 gnd 2.080806f
+R13 12 11 2.224404
+C16 13 gnd 2.080806f
+R14 13 12 2.224404
+C17 14 gnd 2.080806f
+R15 14 13 2.224404
+C18 15 gnd 2.080806f
+R16 15 14 2.224404
+C19 16 gnd 2.080806f
+R17 16 15 2.224404
+C20 17 gnd 2.080806f
+R18 17 16 2.224404
+C21 18 gnd 2.080806f
+R19 18 17 2.224404
+C22 19 gnd 2.080806f
+R20 19 18 2.224404
+C23 20 gnd 2.080806f
+R21 20 19 2.224404
+C24 21 gnd 2.080806f
+R22 21 20 2.224404
+C25 22 gnd 2.080806f
+R23 22 21 2.224404
+C26 23 gnd 2.080806f
+R24 23 22 2.224404
+C27 24 gnd 2.080806f
+R25 24 23 2.224404
+C28 25 gnd 2.080806f
+R26 25 24 2.224404
+C29 26 gnd 2.080806f
+R27 26 25 2.224404
+C30 27 gnd 2.080806f
+R28 27 26 2.224404
+C31 28 gnd 2.080806f
+R29 28 27 2.224404
+C32 29 gnd 2.080806f
+R30 29 28 2.224404
+C33 30 gnd 2.080806f
+R31 29 30 2.224404
+C34 31 gnd 2.080806f
+R32 31 30 2.224404
+C35 32 gnd 2.080806f
+R33 32 31 2.224404
+C36 33 gnd 2.080806f
+R34 33 32 2.224404
+C37 34 gnd 2.080806f
+R35 34 33 2.224404
+C38 35 gnd 2.080806f
+R36 35 34 2.224404
+C39 36 gnd 2.080806f
+R37 36 35 2.224404
+C40 37 gnd 2.080806f
+R38 37 36 2.224404
+C41 38 gnd 2.080806f
+R39 38 37 2.224404
+R40 g64_1 38 2.224404
+.ends
+
+.subckt netg143 g143_0 g143_1 gnd
+C1  g143_0 gnd 2.080806f
+C2  g143_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g143_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+R36 g143_1 35 2.224404
+.ends
+
+.subckt netg145 g145_1 g145_0 gnd
+C1  g145_1 gnd 2.080806f
+C2  g145_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g145_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+R37 36 g145_1 2.224404
+.ends
+
+.subckt netg2209 g2209_4 g2209_3 g2209_0 g2209_5 g2209_1 g2209_2 gnd
+C1  g2209_4 gnd 2.080806f
+C2  g2209_3 gnd 2.080806f
+C3  g2209_0 gnd 2.080806f
+C4  g2209_5 gnd 2.080806f
+C5  g2209_1 gnd 2.080806f
+C6  g2209_2 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 g2209_0 1 2.224404
+C8 2 gnd 2.080806f
+R2 1 2 2.224404
+C9 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 g2209_5 3 2.224404
+C10 4 gnd 2.080806f
+R5 4 g2209_5 2.224404
+C11 5 gnd 2.080806f
+R6 5 4 2.224404
+C12 6 gnd 2.080806f
+R7 6 5 2.224404
+C13 7 gnd 2.080806f
+R8 7 6 2.224404
+C14 8 gnd 2.080806f
+R9 8 7 2.224404
+C15 9 gnd 2.080806f
+R10 9 8 2.224404
+C16 10 gnd 2.080806f
+R11 10 9 2.224404
+C17 11 gnd 2.080806f
+R12 11 10 2.224404
+C18 12 gnd 2.080806f
+R13 12 11 2.224404
+C19 13 gnd 2.080806f
+R14 13 12 2.224404
+C20 14 gnd 2.080806f
+R15 14 13 2.224404
+C21 15 gnd 2.080806f
+R16 15 14 2.224404
+C22 16 gnd 2.080806f
+R17 16 15 2.224404
+C23 17 gnd 2.080806f
+R18 17 16 2.224404
+C24 18 gnd 2.080806f
+R19 18 17 2.224404
+C25 19 gnd 2.080806f
+R20 19 18 2.224404
+C26 20 gnd 2.080806f
+R21 20 19 2.224404
+C27 21 gnd 2.080806f
+R22 21 20 2.224404
+C28 22 gnd 2.080806f
+R23 22 21 2.224404
+C29 23 gnd 2.080806f
+R24 23 22 2.224404
+C30 24 gnd 2.080806f
+R25 24 23 2.224404
+C31 25 gnd 2.080806f
+R26 25 24 2.224404
+C32 26 gnd 2.080806f
+R27 26 25 2.224404
+C33 27 gnd 2.080806f
+R28 27 26 2.224404
+R29 g2209_3 27 2.224404
+C34 28 gnd 2.080806f
+R30 28 g2209_3 2.224404
+C35 29 gnd 2.080806f
+R31 29 28 2.224404
+C36 30 gnd 2.080806f
+R32 29 30 2.224404
+R33 g2209_2 30 2.224404
+C37 31 gnd 2.080806f
+R34 31 g2209_2 2.224404
+C38 32 gnd 2.080806f
+R35 32 31 2.224404
+C39 33 gnd 2.080806f
+R36 33 32 2.224404
+C40 34 gnd 2.080806f
+R37 34 33 2.224404
+C41 35 gnd 2.080806f
+R38 35 34 2.224404
+C42 36 gnd 2.080806f
+R39 36 35 2.224404
+C43 37 gnd 2.080806f
+R40 37 36 2.224404
+R41 g2209_1 37 2.224404
+R42 g2209_4 g2209_1 2.224404
+.ends
+
+.subckt netg2119 g2119_1 g2119_2 g2119_3 g2119_0 gnd
+C1  g2119_1 gnd 2.080806f
+C2  g2119_2 gnd 2.080806f
+C3  g2119_3 gnd 2.080806f
+C4  g2119_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g2119_0 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+C7 3 gnd 2.080806f
+R3 3 2 2.224404
+C8 4 gnd 2.080806f
+R4 4 3 2.224404
+C9 5 gnd 2.080806f
+R5 5 4 2.224404
+R6 g2119_1 5 2.224404
+R7 g2119_3 5 2.224404
+C10 6 gnd 2.080806f
+R8 g2119_0 6 2.224404
+C11 7 gnd 2.080806f
+R9 6 7 2.224404
+C12 8 gnd 2.080806f
+R10 7 8 2.224404
+C13 9 gnd 2.080806f
+R11 8 9 2.224404
+C14 10 gnd 2.080806f
+R12 9 10 2.224404
+C15 11 gnd 2.080806f
+R13 10 11 2.224404
+C16 12 gnd 2.080806f
+R14 11 12 2.224404
+C17 13 gnd 2.080806f
+R15 12 13 2.224404
+C18 14 gnd 2.080806f
+R16 13 14 2.224404
+C19 15 gnd 2.080806f
+R17 14 15 2.224404
+C20 16 gnd 2.080806f
+R18 15 16 2.224404
+C21 17 gnd 2.080806f
+R19 16 17 2.224404
+C22 18 gnd 2.080806f
+R20 17 18 2.224404
+C23 19 gnd 2.080806f
+R21 18 19 2.224404
+C24 20 gnd 2.080806f
+R22 19 20 2.224404
+C25 21 gnd 2.080806f
+R23 20 21 2.224404
+C26 22 gnd 2.080806f
+R24 22 21 2.224404
+C27 23 gnd 2.080806f
+R25 22 23 2.224404
+C28 24 gnd 2.080806f
+R26 23 24 2.224404
+C29 25 gnd 2.080806f
+R27 24 25 2.224404
+C30 26 gnd 2.080806f
+R28 25 26 2.224404
+C31 27 gnd 2.080806f
+R29 26 27 2.224404
+C32 28 gnd 2.080806f
+R30 27 28 2.224404
+C33 29 gnd 2.080806f
+R31 28 29 2.224404
+C34 30 gnd 2.080806f
+R32 29 30 2.224404
+C35 31 gnd 2.080806f
+R33 30 31 2.224404
+C36 32 gnd 2.080806f
+R34 31 32 2.224404
+C37 33 gnd 2.080806f
+R35 32 33 2.224404
+C38 34 gnd 2.080806f
+R36 34 33 2.224404
+C39 35 gnd 2.080806f
+R37 35 34 2.224404
+C40 36 gnd 2.080806f
+R38 36 35 2.224404
+C41 37 gnd 2.080806f
+R39 36 37 2.224404
+C42 38 gnd 2.080806f
+R40 38 37 2.224404
+C43 39 gnd 2.080806f
+R41 38 39 2.224404
+C44 40 gnd 2.080806f
+R42 39 40 2.224404
+C45 41 gnd 2.080806f
+R43 40 41 2.224404
+C46 42 gnd 2.080806f
+R44 41 42 2.224404
+C47 43 gnd 2.080806f
+R45 42 43 2.224404
+C48 44 gnd 2.080806f
+R46 43 44 2.224404
+R47 44 g2119_2 2.224404
+.ends
+
+.subckt netg6705 g6705_0 g6705_3 g6705_2 g6705_4 g6705_1 gnd
+C1  g6705_0 gnd 2.080806f
+C2  g6705_3 gnd 2.080806f
+C3  g6705_2 gnd 2.080806f
+C4  g6705_4 gnd 2.080806f
+C5  g6705_1 gnd 2.080806f
+C6 1 gnd 2.080806f
+R1 1 g6705_0 2.224404
+C7 2 gnd 2.080806f
+R2 1 2 2.224404
+C8 3 gnd 2.080806f
+R3 3 2 2.224404
+C9 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 g6705_2 4 2.224404
+R6 g6705_2 g6705_3 2.224404
+R7 g6705_4 g6705_2 2.224404
+C10 5 gnd 2.080806f
+R8 g6705_3 5 2.224404
+C11 6 gnd 2.080806f
+R9 5 6 2.224404
+C12 7 gnd 2.080806f
+R10 6 7 2.224404
+C13 8 gnd 2.080806f
+R11 8 7 2.224404
+C14 9 gnd 2.080806f
+R12 9 8 2.224404
+C15 10 gnd 2.080806f
+R13 9 10 2.224404
+C16 11 gnd 2.080806f
+R14 11 10 2.224404
+C17 12 gnd 2.080806f
+R15 12 11 2.224404
+C18 13 gnd 2.080806f
+R16 12 13 2.224404
+C19 14 gnd 2.080806f
+R17 13 14 2.224404
+C20 15 gnd 2.080806f
+R18 14 15 2.224404
+C21 16 gnd 2.080806f
+R19 15 16 2.224404
+C22 17 gnd 2.080806f
+R20 17 16 2.224404
+C23 18 gnd 2.080806f
+R21 17 18 2.224404
+C24 19 gnd 2.080806f
+R22 19 18 2.224404
+C25 20 gnd 2.080806f
+R23 19 20 2.224404
+C26 21 gnd 2.080806f
+R24 21 20 2.224404
+C27 22 gnd 2.080806f
+R25 22 21 2.224404
+C28 23 gnd 2.080806f
+R26 23 22 2.224404
+C29 24 gnd 2.080806f
+R27 24 23 2.224404
+C30 25 gnd 2.080806f
+R28 24 25 2.224404
+C31 26 gnd 2.080806f
+R29 26 25 2.224404
+C32 27 gnd 2.080806f
+R30 27 26 2.224404
+C33 28 gnd 2.080806f
+R31 28 27 2.224404
+C34 29 gnd 2.080806f
+R32 28 29 2.224404
+C35 30 gnd 2.080806f
+R33 29 30 2.224404
+C36 31 gnd 2.080806f
+R34 31 30 2.224404
+C37 32 gnd 2.080806f
+R35 32 31 2.224404
+C38 33 gnd 2.080806f
+R36 33 32 2.224404
+C39 34 gnd 2.080806f
+R37 34 33 2.224404
+R38 g6705_1 34 2.224404
+.ends
+
+.subckt netg86 g86_0 g86_1 gnd
+C1  g86_0 gnd 2.080806f
+C2  g86_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g86_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+R37 36 g86_1 2.224404
+.ends
+
+.subckt netg147 g147_1 g147_0 gnd
+C1  g147_1 gnd 2.080806f
+C2  g147_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g147_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+R37 36 g147_1 2.224404
+.ends
+
+.subckt netg2304 g2304_0 g2304_3 g2304_2 g2304_1 gnd
+C1  g2304_0 gnd 2.080806f
+C2  g2304_3 gnd 2.080806f
+C3  g2304_2 gnd 2.080806f
+C4  g2304_1 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g2304_0 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+C7 3 gnd 2.080806f
+R3 3 2 2.224404
+C8 4 gnd 2.080806f
+R4 4 3 2.224404
+C9 5 gnd 2.080806f
+R5 5 4 2.224404
+C10 6 gnd 2.080806f
+R6 6 5 2.224404
+C11 7 gnd 2.080806f
+R7 7 6 2.224404
+C12 8 gnd 2.080806f
+R8 8 7 2.224404
+C13 9 gnd 2.080806f
+R9 9 8 2.224404
+R10 g2304_2 9 2.224404
+C14 10 gnd 2.080806f
+R11 g2304_0 10 2.224404
+C15 11 gnd 2.080806f
+R12 10 11 2.224404
+C16 12 gnd 2.080806f
+R13 11 12 2.224404
+C17 13 gnd 2.080806f
+R14 12 13 2.224404
+C18 14 gnd 2.080806f
+R15 13 14 2.224404
+C19 15 gnd 2.080806f
+R16 14 15 2.224404
+C20 16 gnd 2.080806f
+R17 15 16 2.224404
+C21 17 gnd 2.080806f
+R18 16 17 2.224404
+C22 18 gnd 2.080806f
+R19 17 18 2.224404
+C23 19 gnd 2.080806f
+R20 18 19 2.224404
+C24 20 gnd 2.080806f
+R21 19 20 2.224404
+C25 21 gnd 2.080806f
+R22 20 21 2.224404
+C26 22 gnd 2.080806f
+R23 21 22 2.224404
+C27 23 gnd 2.080806f
+R24 22 23 2.224404
+C28 24 gnd 2.080806f
+R25 23 24 2.224404
+C29 25 gnd 2.080806f
+R26 24 25 2.224404
+C30 26 gnd 2.080806f
+R27 25 26 2.224404
+C31 27 gnd 2.080806f
+R28 26 27 2.224404
+C32 28 gnd 2.080806f
+R29 27 28 2.224404
+C33 29 gnd 2.080806f
+R30 28 29 2.224404
+C34 30 gnd 2.080806f
+R31 29 30 2.224404
+C35 31 gnd 2.080806f
+R32 30 31 2.224404
+C36 32 gnd 2.080806f
+R33 31 32 2.224404
+C37 33 gnd 2.080806f
+R34 32 33 2.224404
+C38 34 gnd 2.080806f
+R35 33 34 2.224404
+R36 34 g2304_3 2.224404
+R37 g2304_3 g2304_1 2.224404
+.ends
+
+.subckt netg74 g74_1 g74_0 gnd
+C1  g74_1 gnd 2.080806f
+C2  g74_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g74_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+R38 37 g74_1 2.224404
+.ends
+
+.subckt netg20 g20_1 g20_0 gnd
+C1  g20_1 gnd 2.080806f
+C2  g20_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g20_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+R38 g20_1 37 2.224404
+.ends
+
+.subckt netg2308 g2308_2 g2308_3 g2308_1 g2308_0 gnd
+C1  g2308_2 gnd 2.080806f
+C2  g2308_3 gnd 2.080806f
+C3  g2308_1 gnd 2.080806f
+C4  g2308_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g2308_0 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+C7 3 gnd 2.080806f
+R3 3 2 2.224404
+C8 4 gnd 2.080806f
+R4 4 3 2.224404
+C9 5 gnd 2.080806f
+R5 5 4 2.224404
+C10 6 gnd 2.080806f
+R6 6 5 2.224404
+C11 7 gnd 2.080806f
+R7 7 6 2.224404
+C12 8 gnd 2.080806f
+R8 8 7 2.224404
+C13 9 gnd 2.080806f
+R9 9 8 2.224404
+C14 10 gnd 2.080806f
+R10 10 9 2.224404
+C15 11 gnd 2.080806f
+R11 11 10 2.224404
+C16 12 gnd 2.080806f
+R12 12 11 2.224404
+C17 13 gnd 2.080806f
+R13 13 12 2.224404
+R14 g2308_3 13 2.224404
+C18 14 gnd 2.080806f
+R15 g2308_0 14 2.224404
+C19 15 gnd 2.080806f
+R16 14 15 2.224404
+C20 16 gnd 2.080806f
+R17 15 16 2.224404
+C21 17 gnd 2.080806f
+R18 16 17 2.224404
+C22 18 gnd 2.080806f
+R19 17 18 2.224404
+C23 19 gnd 2.080806f
+R20 18 19 2.224404
+C24 20 gnd 2.080806f
+R21 19 20 2.224404
+C25 21 gnd 2.080806f
+R22 20 21 2.224404
+C26 22 gnd 2.080806f
+R23 21 22 2.224404
+C27 23 gnd 2.080806f
+R24 22 23 2.224404
+C28 24 gnd 2.080806f
+R25 23 24 2.224404
+C29 25 gnd 2.080806f
+R26 24 25 2.224404
+C30 26 gnd 2.080806f
+R27 25 26 2.224404
+C31 27 gnd 2.080806f
+R28 26 27 2.224404
+C32 28 gnd 2.080806f
+R29 27 28 2.224404
+C33 29 gnd 2.080806f
+R30 28 29 2.224404
+C34 30 gnd 2.080806f
+R31 29 30 2.224404
+C35 31 gnd 2.080806f
+R32 30 31 2.224404
+C36 32 gnd 2.080806f
+R33 31 32 2.224404
+C37 33 gnd 2.080806f
+R34 32 33 2.224404
+C38 34 gnd 2.080806f
+R35 33 34 2.224404
+C39 35 gnd 2.080806f
+R36 34 35 2.224404
+R37 35 g2308_2 2.224404
+R38 g2308_2 g2308_1 2.224404
+.ends
+
+.subckt netg18 g18_1 g18_0 gnd
+C1  g18_1 gnd 2.080806f
+C2  g18_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g18_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+R38 g18_1 37 2.224404
+.ends
+
+.subckt netg146 g146_0 g146_1 gnd
+C1  g146_0 gnd 2.080806f
+C2  g146_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g146_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+R38 37 g146_1 2.224404
+.ends
+
+.subckt netg29 g29_0 g29_1 gnd
+C1  g29_0 gnd 2.080806f
+C2  g29_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g29_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+R39 g29_1 38 2.224404
+.ends
+
+.subckt netg26 g26_1 g26_0 gnd
+C1  g26_1 gnd 2.080806f
+C2  g26_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g26_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+R39 g26_1 38 2.224404
+.ends
+
+.subckt netg144 g144_0 g144_1 gnd
+C1  g144_0 gnd 2.080806f
+C2  g144_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g144_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+R39 38 g144_1 2.224404
+.ends
+
+.subckt netg2147 g2147_2 g2147_3 g2147_4 g2147_1 g2147_0 g2147_5 gnd
+C1  g2147_2 gnd 2.080806f
+C2  g2147_3 gnd 2.080806f
+C3  g2147_4 gnd 2.080806f
+C4  g2147_1 gnd 2.080806f
+C5  g2147_0 gnd 2.080806f
+C6  g2147_5 gnd 2.080806f
+R1 g2147_0 g2147_2 2.224404
+C7 1 gnd 2.080806f
+R2 g2147_2 1 2.224404
+R3 1 g2147_5 2.224404
+C8 2 gnd 2.080806f
+R4 g2147_5 2 2.224404
+C9 3 gnd 2.080806f
+R5 2 3 2.224404
+R6 3 g2147_4 2.224404
+C10 4 gnd 2.080806f
+R7 g2147_4 4 2.224404
+C11 5 gnd 2.080806f
+R8 4 5 2.224404
+C12 6 gnd 2.080806f
+R9 5 6 2.224404
+C13 7 gnd 2.080806f
+R10 6 7 2.224404
+C14 8 gnd 2.080806f
+R11 7 8 2.224404
+C15 9 gnd 2.080806f
+R12 8 9 2.224404
+C16 10 gnd 2.080806f
+R13 9 10 2.224404
+C17 11 gnd 2.080806f
+R14 10 11 2.224404
+C18 12 gnd 2.080806f
+R15 11 12 2.224404
+C19 13 gnd 2.080806f
+R16 12 13 2.224404
+C20 14 gnd 2.080806f
+R17 13 14 2.224404
+C21 15 gnd 2.080806f
+R18 14 15 2.224404
+C22 16 gnd 2.080806f
+R19 15 16 2.224404
+C23 17 gnd 2.080806f
+R20 16 17 2.224404
+C24 18 gnd 2.080806f
+R21 17 18 2.224404
+C25 19 gnd 2.080806f
+R22 18 19 2.224404
+C26 20 gnd 2.080806f
+R23 19 20 2.224404
+C27 21 gnd 2.080806f
+R24 20 21 2.224404
+C28 22 gnd 2.080806f
+R25 21 22 2.224404
+C29 23 gnd 2.080806f
+R26 23 22 2.224404
+C30 24 gnd 2.080806f
+R27 23 24 2.224404
+C31 25 gnd 2.080806f
+R28 24 25 2.224404
+C32 26 gnd 2.080806f
+R29 25 26 2.224404
+C33 27 gnd 2.080806f
+R30 26 27 2.224404
+R31 27 g2147_3 2.224404
+C34 28 gnd 2.080806f
+R32 28 g2147_3 2.224404
+C35 29 gnd 2.080806f
+R33 29 28 2.224404
+C36 30 gnd 2.080806f
+R34 30 29 2.224404
+C37 31 gnd 2.080806f
+R35 30 31 2.224404
+C38 32 gnd 2.080806f
+R36 31 32 2.224404
+C39 33 gnd 2.080806f
+R37 32 33 2.224404
+C40 34 gnd 2.080806f
+R38 33 34 2.224404
+C41 35 gnd 2.080806f
+R39 34 35 2.224404
+C42 36 gnd 2.080806f
+R40 35 36 2.224404
+C43 37 gnd 2.080806f
+R41 36 37 2.224404
+C44 38 gnd 2.080806f
+R42 37 38 2.224404
+C45 39 gnd 2.080806f
+R43 38 39 2.224404
+C46 40 gnd 2.080806f
+R44 39 40 2.224404
+R45 40 g2147_1 2.224404
+.ends
+
+.subckt netg1710 g1710_4 g1710_2 g1710_3 g1710_5 g1710_1 g1710_0 gnd
+C1  g1710_4 gnd 2.080806f
+C2  g1710_2 gnd 2.080806f
+C3  g1710_3 gnd 2.080806f
+C4  g1710_5 gnd 2.080806f
+C5  g1710_1 gnd 2.080806f
+C6  g1710_0 gnd 2.080806f
+R1 g1710_3 g1710_0 2.224404
+C7 1 gnd 2.080806f
+R2 1 g1710_0 2.224404
+C8 2 gnd 2.080806f
+R3 1 2 2.224404
+C9 3 gnd 2.080806f
+R4 2 3 2.224404
+C10 4 gnd 2.080806f
+R5 3 4 2.224404
+C11 5 gnd 2.080806f
+R6 4 5 2.224404
+C12 6 gnd 2.080806f
+R7 5 6 2.224404
+C13 7 gnd 2.080806f
+R8 6 7 2.224404
+R9 7 g1710_2 2.224404
+C14 8 gnd 2.080806f
+R10 8 g1710_2 2.224404
+C15 9 gnd 2.080806f
+R11 8 9 2.224404
+C16 10 gnd 2.080806f
+R12 9 10 2.224404
+C17 11 gnd 2.080806f
+R13 10 11 2.224404
+C18 12 gnd 2.080806f
+R14 11 12 2.224404
+R15 12 g1710_1 2.224404
+C19 13 gnd 2.080806f
+R16 13 g1710_1 2.224404
+C20 14 gnd 2.080806f
+R17 13 14 2.224404
+C21 15 gnd 2.080806f
+R18 14 15 2.224404
+C22 16 gnd 2.080806f
+R19 15 16 2.224404
+C23 17 gnd 2.080806f
+R20 16 17 2.224404
+C24 18 gnd 2.080806f
+R21 17 18 2.224404
+C25 19 gnd 2.080806f
+R22 18 19 2.224404
+C26 20 gnd 2.080806f
+R23 19 20 2.224404
+C27 21 gnd 2.080806f
+R24 20 21 2.224404
+C28 22 gnd 2.080806f
+R25 21 22 2.224404
+C29 23 gnd 2.080806f
+R26 22 23 2.224404
+C30 24 gnd 2.080806f
+R27 23 24 2.224404
+C31 25 gnd 2.080806f
+R28 24 25 2.224404
+C32 26 gnd 2.080806f
+R29 25 26 2.224404
+C33 27 gnd 2.080806f
+R30 26 27 2.224404
+C34 28 gnd 2.080806f
+R31 27 28 2.224404
+C35 29 gnd 2.080806f
+R32 28 29 2.224404
+C36 30 gnd 2.080806f
+R33 29 30 2.224404
+C37 31 gnd 2.080806f
+R34 30 31 2.224404
+C38 32 gnd 2.080806f
+R35 31 32 2.224404
+C39 33 gnd 2.080806f
+R36 32 33 2.224404
+C40 34 gnd 2.080806f
+R37 33 34 2.224404
+C41 35 gnd 2.080806f
+R38 34 35 2.224404
+C42 36 gnd 2.080806f
+R39 36 35 2.224404
+C43 37 gnd 2.080806f
+R40 36 37 2.224404
+C44 38 gnd 2.080806f
+R41 37 38 2.224404
+C45 39 gnd 2.080806f
+R42 38 39 2.224404
+R43 39 g1710_5 2.224404
+C46 40 gnd 2.080806f
+R44 g1710_5 40 2.224404
+R45 40 g1710_4 2.224404
+.ends
+
+.subckt netg132 g132_0 g132_1 gnd
+C1  g132_0 gnd 2.080806f
+C2  g132_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g132_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+R40 39 g132_1 2.224404
+.ends
+
+.subckt netg7525 g7525_1 g7525_0 gnd
+C1  g7525_1 gnd 2.080806f
+C2  g7525_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7525_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+R40 g7525_1 39 2.224404
+.ends
+
+.subckt netg519 g519_5 g519_3 g519_6 g519_4 g519_1 g519_0 g519_2 gnd
+C1  g519_5 gnd 2.080806f
+C2  g519_3 gnd 2.080806f
+C3  g519_6 gnd 2.080806f
+C4  g519_4 gnd 2.080806f
+C5  g519_1 gnd 2.080806f
+C6  g519_0 gnd 2.080806f
+C7  g519_2 gnd 2.080806f
+C8 1 gnd 2.080806f
+R1 g519_0 1 2.224404
+C9 2 gnd 2.080806f
+R2 1 2 2.224404
+C10 3 gnd 2.080806f
+R3 2 3 2.224404
+C11 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 4 g519_3 2.224404
+C12 5 gnd 2.080806f
+R6 5 g519_0 2.224404
+C13 6 gnd 2.080806f
+R7 6 5 2.224404
+C14 7 gnd 2.080806f
+R8 7 6 2.224404
+C15 8 gnd 2.080806f
+R9 8 7 2.224404
+C16 9 gnd 2.080806f
+R10 9 8 2.224404
+C17 10 gnd 2.080806f
+R11 10 9 2.224404
+C18 11 gnd 2.080806f
+R12 11 10 2.224404
+C19 12 gnd 2.080806f
+R13 12 11 2.224404
+C20 13 gnd 2.080806f
+R14 13 12 2.224404
+C21 14 gnd 2.080806f
+R15 14 13 2.224404
+C22 15 gnd 2.080806f
+R16 15 14 2.224404
+C23 16 gnd 2.080806f
+R17 16 15 2.224404
+R18 g519_1 16 2.224404
+C24 17 gnd 2.080806f
+R19 17 g519_1 2.224404
+C25 18 gnd 2.080806f
+R20 18 17 2.224404
+C26 19 gnd 2.080806f
+R21 19 18 2.224404
+C27 20 gnd 2.080806f
+R22 20 19 2.224404
+C28 21 gnd 2.080806f
+R23 21 20 2.224404
+R24 g519_4 21 2.224404
+C29 22 gnd 2.080806f
+R25 22 g519_4 2.224404
+R26 g519_6 22 2.224404
+C30 23 gnd 2.080806f
+R27 g519_3 23 2.224404
+C31 24 gnd 2.080806f
+R28 23 24 2.224404
+C32 25 gnd 2.080806f
+R29 24 25 2.224404
+C33 26 gnd 2.080806f
+R30 25 26 2.224404
+C34 27 gnd 2.080806f
+R31 26 27 2.224404
+C35 28 gnd 2.080806f
+R32 27 28 2.224404
+C36 29 gnd 2.080806f
+R33 28 29 2.224404
+C37 30 gnd 2.080806f
+R34 29 30 2.224404
+C38 31 gnd 2.080806f
+R35 30 31 2.224404
+C39 32 gnd 2.080806f
+R36 31 32 2.224404
+C40 33 gnd 2.080806f
+R37 32 33 2.224404
+C41 34 gnd 2.080806f
+R38 33 34 2.224404
+R39 34 g519_2 2.224404
+C42 35 gnd 2.080806f
+R40 35 g519_2 2.224404
+C43 36 gnd 2.080806f
+R41 36 35 2.224404
+C44 37 gnd 2.080806f
+R42 37 36 2.224404
+R43 37 g519_5 2.224404
+.ends
+
+.subckt netg2175 g2175_4 g2175_6 g2175_5 g2175_3 g2175_2 g2175_1 g2175_0 gnd
+C1  g2175_4 gnd 2.080806f
+C2  g2175_6 gnd 2.080806f
+C3  g2175_5 gnd 2.080806f
+C4  g2175_3 gnd 2.080806f
+C5  g2175_2 gnd 2.080806f
+C6  g2175_1 gnd 2.080806f
+C7  g2175_0 gnd 2.080806f
+C8 1 gnd 2.080806f
+R1 1 g2175_0 2.224404
+C9 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g2175_1 2 2.224404
+C10 3 gnd 2.080806f
+R4 g2175_1 3 2.224404
+R5 g2175_4 3 2.224404
+C11 4 gnd 2.080806f
+R6 4 g2175_4 2.224404
+R7 g2175_6 4 2.224404
+C12 5 gnd 2.080806f
+R8 5 g2175_1 2.224404
+C13 6 gnd 2.080806f
+R9 6 5 2.224404
+R10 g2175_2 6 2.224404
+C14 7 gnd 2.080806f
+R11 g2175_0 7 2.224404
+C15 8 gnd 2.080806f
+R12 7 8 2.224404
+C16 9 gnd 2.080806f
+R13 8 9 2.224404
+C17 10 gnd 2.080806f
+R14 9 10 2.224404
+C18 11 gnd 2.080806f
+R15 10 11 2.224404
+C19 12 gnd 2.080806f
+R16 11 12 2.224404
+C20 13 gnd 2.080806f
+R17 12 13 2.224404
+C21 14 gnd 2.080806f
+R18 13 14 2.224404
+C22 15 gnd 2.080806f
+R19 14 15 2.224404
+C23 16 gnd 2.080806f
+R20 15 16 2.224404
+R21 16 g2175_3 2.224404
+C24 17 gnd 2.080806f
+R22 16 17 2.224404
+C25 18 gnd 2.080806f
+R23 17 18 2.224404
+C26 19 gnd 2.080806f
+R24 18 19 2.224404
+C27 20 gnd 2.080806f
+R25 19 20 2.224404
+C28 21 gnd 2.080806f
+R26 20 21 2.224404
+C29 22 gnd 2.080806f
+R27 21 22 2.224404
+C30 23 gnd 2.080806f
+R28 22 23 2.224404
+C31 24 gnd 2.080806f
+R29 23 24 2.224404
+C32 25 gnd 2.080806f
+R30 24 25 2.224404
+C33 26 gnd 2.080806f
+R31 25 26 2.224404
+C34 27 gnd 2.080806f
+R32 26 27 2.224404
+C35 28 gnd 2.080806f
+R33 27 28 2.224404
+C36 29 gnd 2.080806f
+R34 28 29 2.224404
+C37 30 gnd 2.080806f
+R35 30 29 2.224404
+C38 31 gnd 2.080806f
+R36 30 31 2.224404
+C39 32 gnd 2.080806f
+R37 31 32 2.224404
+C40 33 gnd 2.080806f
+R38 32 33 2.224404
+C41 34 gnd 2.080806f
+R39 33 34 2.224404
+C42 35 gnd 2.080806f
+R40 34 35 2.224404
+C43 36 gnd 2.080806f
+R41 35 36 2.224404
+C44 37 gnd 2.080806f
+R42 36 37 2.224404
+C45 38 gnd 2.080806f
+R43 37 38 2.224404
+C46 39 gnd 2.080806f
+R44 38 39 2.224404
+C47 40 gnd 2.080806f
+R45 39 40 2.224404
+R46 40 g2175_5 2.224404
+.ends
+
+.subckt netg1632 g1632_2 g1632_4 g1632_1 g1632_5 g1632_3 g1632_0 gnd
+C1  g1632_2 gnd 2.080806f
+C2  g1632_4 gnd 2.080806f
+C3  g1632_1 gnd 2.080806f
+C4  g1632_5 gnd 2.080806f
+C5  g1632_3 gnd 2.080806f
+C6  g1632_0 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g1632_0 2.224404
+C8 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 2 g1632_2 2.224404
+R4 g1632_2 g1632_1 2.224404
+C9 3 gnd 2.080806f
+R5 g1632_0 3 2.224404
+C10 4 gnd 2.080806f
+R6 3 4 2.224404
+R7 4 g1632_5 2.224404
+C11 5 gnd 2.080806f
+R8 g1632_1 5 2.224404
+C12 6 gnd 2.080806f
+R9 5 6 2.224404
+C13 7 gnd 2.080806f
+R10 6 7 2.224404
+C14 8 gnd 2.080806f
+R11 7 8 2.224404
+C15 9 gnd 2.080806f
+R12 8 9 2.224404
+C16 10 gnd 2.080806f
+R13 9 10 2.224404
+C17 11 gnd 2.080806f
+R14 10 11 2.224404
+C18 12 gnd 2.080806f
+R15 11 12 2.224404
+C19 13 gnd 2.080806f
+R16 12 13 2.224404
+C20 14 gnd 2.080806f
+R17 13 14 2.224404
+C21 15 gnd 2.080806f
+R18 14 15 2.224404
+C22 16 gnd 2.080806f
+R19 15 16 2.224404
+C23 17 gnd 2.080806f
+R20 16 17 2.224404
+C24 18 gnd 2.080806f
+R21 17 18 2.224404
+C25 19 gnd 2.080806f
+R22 18 19 2.224404
+C26 20 gnd 2.080806f
+R23 19 20 2.224404
+C27 21 gnd 2.080806f
+R24 20 21 2.224404
+C28 22 gnd 2.080806f
+R25 21 22 2.224404
+C29 23 gnd 2.080806f
+R26 22 23 2.224404
+C30 24 gnd 2.080806f
+R27 23 24 2.224404
+C31 25 gnd 2.080806f
+R28 24 25 2.224404
+C32 26 gnd 2.080806f
+R29 25 26 2.224404
+C33 27 gnd 2.080806f
+R30 26 27 2.224404
+C34 28 gnd 2.080806f
+R31 27 28 2.224404
+C35 29 gnd 2.080806f
+R32 28 29 2.224404
+C36 30 gnd 2.080806f
+R33 30 29 2.224404
+C37 31 gnd 2.080806f
+R34 30 31 2.224404
+C38 32 gnd 2.080806f
+R35 31 32 2.224404
+C39 33 gnd 2.080806f
+R36 32 33 2.224404
+C40 34 gnd 2.080806f
+R37 33 34 2.224404
+C41 35 gnd 2.080806f
+R38 34 35 2.224404
+C42 36 gnd 2.080806f
+R39 35 36 2.224404
+C43 37 gnd 2.080806f
+R40 36 37 2.224404
+C44 38 gnd 2.080806f
+R41 37 38 2.224404
+C45 39 gnd 2.080806f
+R42 38 39 2.224404
+R43 39 g1632_4 2.224404
+C46 40 gnd 2.080806f
+R44 g1632_4 40 2.224404
+R45 40 g1632_3 2.224404
+.ends
+
+.subckt netg32 g32_0 g32_1 g32_2 gnd
+C1  g32_0 gnd 2.080806f
+C2  g32_1 gnd 2.080806f
+C3  g32_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g32_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g32_1 2.224404
+C6 3 gnd 2.080806f
+R4 3 g32_0 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 11 10 2.224404
+C15 12 gnd 2.080806f
+R13 12 11 2.224404
+C16 13 gnd 2.080806f
+R14 13 12 2.224404
+C17 14 gnd 2.080806f
+R15 14 13 2.224404
+C18 15 gnd 2.080806f
+R16 15 14 2.224404
+C19 16 gnd 2.080806f
+R17 16 15 2.224404
+C20 17 gnd 2.080806f
+R18 17 16 2.224404
+C21 18 gnd 2.080806f
+R19 18 17 2.224404
+C22 19 gnd 2.080806f
+R20 19 18 2.224404
+C23 20 gnd 2.080806f
+R21 20 19 2.224404
+C24 21 gnd 2.080806f
+R22 21 20 2.224404
+C25 22 gnd 2.080806f
+R23 22 21 2.224404
+C26 23 gnd 2.080806f
+R24 23 22 2.224404
+C27 24 gnd 2.080806f
+R25 24 23 2.224404
+C28 25 gnd 2.080806f
+R26 25 24 2.224404
+C29 26 gnd 2.080806f
+R27 26 25 2.224404
+C30 27 gnd 2.080806f
+R28 27 26 2.224404
+C31 28 gnd 2.080806f
+R29 28 27 2.224404
+C32 29 gnd 2.080806f
+R30 29 28 2.224404
+C33 30 gnd 2.080806f
+R31 30 29 2.224404
+C34 31 gnd 2.080806f
+R32 31 30 2.224404
+C35 32 gnd 2.080806f
+R33 32 31 2.224404
+C36 33 gnd 2.080806f
+R34 33 32 2.224404
+C37 34 gnd 2.080806f
+R35 34 33 2.224404
+C38 35 gnd 2.080806f
+R36 35 34 2.224404
+C39 36 gnd 2.080806f
+R37 36 35 2.224404
+C40 37 gnd 2.080806f
+R38 37 36 2.224404
+C41 38 gnd 2.080806f
+R39 38 37 2.224404
+R40 g32_2 38 2.224404
+.ends
+
+.subckt netg7502 g7502_0 g7502_1 gnd
+C1  g7502_0 gnd 2.080806f
+C2  g7502_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7502_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+R40 g7502_1 39 2.224404
+.ends
+
+.subckt netg7522 g7522_0 g7522_1 gnd
+C1  g7522_0 gnd 2.080806f
+C2  g7522_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7522_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+R41 40 g7522_1 2.224404
+.ends
+
+.subckt netg7482 g7482_0 g7482_1 gnd
+C1  g7482_0 gnd 2.080806f
+C2  g7482_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7482_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+R41 40 g7482_1 2.224404
+.ends
+
+.subckt netg446 g446_1 g446_3 g446_0 g446_2 gnd
+C1  g446_1 gnd 2.080806f
+C2  g446_3 gnd 2.080806f
+C3  g446_0 gnd 2.080806f
+C4  g446_2 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g446_0 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+C7 3 gnd 2.080806f
+R3 3 2 2.224404
+C8 4 gnd 2.080806f
+R4 4 3 2.224404
+C9 5 gnd 2.080806f
+R5 5 4 2.224404
+C10 6 gnd 2.080806f
+R6 6 5 2.224404
+C11 7 gnd 2.080806f
+R7 7 6 2.224404
+C12 8 gnd 2.080806f
+R8 8 7 2.224404
+C13 9 gnd 2.080806f
+R9 8 9 2.224404
+C14 10 gnd 2.080806f
+R10 9 10 2.224404
+C15 11 gnd 2.080806f
+R11 11 10 2.224404
+C16 12 gnd 2.080806f
+R12 11 12 2.224404
+C17 13 gnd 2.080806f
+R13 12 13 2.224404
+C18 14 gnd 2.080806f
+R14 13 14 2.224404
+C19 15 gnd 2.080806f
+R15 14 15 2.224404
+C20 16 gnd 2.080806f
+R16 15 16 2.224404
+C21 17 gnd 2.080806f
+R17 16 17 2.224404
+C22 18 gnd 2.080806f
+R18 17 18 2.224404
+C23 19 gnd 2.080806f
+R19 18 19 2.224404
+C24 20 gnd 2.080806f
+R20 19 20 2.224404
+C25 21 gnd 2.080806f
+R21 20 21 2.224404
+C26 22 gnd 2.080806f
+R22 21 22 2.224404
+C27 23 gnd 2.080806f
+R23 22 23 2.224404
+C28 24 gnd 2.080806f
+R24 23 24 2.224404
+C29 25 gnd 2.080806f
+R25 24 25 2.224404
+C30 26 gnd 2.080806f
+R26 25 26 2.224404
+C31 27 gnd 2.080806f
+R27 26 27 2.224404
+C32 28 gnd 2.080806f
+R28 27 28 2.224404
+R29 g446_3 28 2.224404
+C33 29 gnd 2.080806f
+R30 28 29 2.224404
+C34 30 gnd 2.080806f
+R31 29 30 2.224404
+C35 31 gnd 2.080806f
+R32 30 31 2.224404
+C36 32 gnd 2.080806f
+R33 31 32 2.224404
+C37 33 gnd 2.080806f
+R34 32 33 2.224404
+C38 34 gnd 2.080806f
+R35 33 34 2.224404
+C39 35 gnd 2.080806f
+R36 34 35 2.224404
+C40 36 gnd 2.080806f
+R37 35 36 2.224404
+C41 37 gnd 2.080806f
+R38 36 37 2.224404
+C42 38 gnd 2.080806f
+R39 37 38 2.224404
+C43 39 gnd 2.080806f
+R40 38 39 2.224404
+C44 40 gnd 2.080806f
+R41 39 40 2.224404
+C45 41 gnd 2.080806f
+R42 40 41 2.224404
+C46 42 gnd 2.080806f
+R43 41 42 2.224404
+C47 43 gnd 2.080806f
+R44 42 43 2.224404
+C48 44 gnd 2.080806f
+R45 43 44 2.224404
+C49 45 gnd 2.080806f
+R46 44 45 2.224404
+C50 46 gnd 2.080806f
+R47 45 46 2.224404
+C51 47 gnd 2.080806f
+R48 46 47 2.224404
+C52 48 gnd 2.080806f
+R49 47 48 2.224404
+C53 49 gnd 2.080806f
+R50 48 49 2.224404
+C54 50 gnd 2.080806f
+R51 49 50 2.224404
+C55 51 gnd 2.080806f
+R52 50 51 2.224404
+C56 52 gnd 2.080806f
+R53 51 52 2.224404
+C57 53 gnd 2.080806f
+R54 52 53 2.224404
+C58 54 gnd 2.080806f
+R55 53 54 2.224404
+C59 55 gnd 2.080806f
+R56 54 55 2.224404
+C60 56 gnd 2.080806f
+R57 55 56 2.224404
+R58 56 g446_1 2.224404
+C61 57 gnd 2.080806f
+R59 g446_1 57 2.224404
+R60 57 g446_2 2.224404
+.ends
+
+.subckt netg62 g62_1 g62_2 g62_0 gnd
+C1  g62_1 gnd 2.080806f
+C2  g62_2 gnd 2.080806f
+C3  g62_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g62_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+C8 5 gnd 2.080806f
+R5 4 5 2.224404
+C9 6 gnd 2.080806f
+R6 5 6 2.224404
+C10 7 gnd 2.080806f
+R7 6 7 2.224404
+C11 8 gnd 2.080806f
+R8 7 8 2.224404
+C12 9 gnd 2.080806f
+R9 8 9 2.224404
+C13 10 gnd 2.080806f
+R10 9 10 2.224404
+C14 11 gnd 2.080806f
+R11 10 11 2.224404
+C15 12 gnd 2.080806f
+R12 11 12 2.224404
+C16 13 gnd 2.080806f
+R13 12 13 2.224404
+C17 14 gnd 2.080806f
+R14 13 14 2.224404
+C18 15 gnd 2.080806f
+R15 14 15 2.224404
+C19 16 gnd 2.080806f
+R16 15 16 2.224404
+C20 17 gnd 2.080806f
+R17 16 17 2.224404
+C21 18 gnd 2.080806f
+R18 17 18 2.224404
+C22 19 gnd 2.080806f
+R19 18 19 2.224404
+C23 20 gnd 2.080806f
+R20 19 20 2.224404
+C24 21 gnd 2.080806f
+R21 20 21 2.224404
+C25 22 gnd 2.080806f
+R22 21 22 2.224404
+C26 23 gnd 2.080806f
+R23 22 23 2.224404
+C27 24 gnd 2.080806f
+R24 23 24 2.224404
+C28 25 gnd 2.080806f
+R25 24 25 2.224404
+C29 26 gnd 2.080806f
+R26 25 26 2.224404
+C30 27 gnd 2.080806f
+R27 26 27 2.224404
+C31 28 gnd 2.080806f
+R28 27 28 2.224404
+C32 29 gnd 2.080806f
+R29 28 29 2.224404
+C33 30 gnd 2.080806f
+R30 29 30 2.224404
+C34 31 gnd 2.080806f
+R31 30 31 2.224404
+C35 32 gnd 2.080806f
+R32 31 32 2.224404
+C36 33 gnd 2.080806f
+R33 32 33 2.224404
+C37 34 gnd 2.080806f
+R34 33 34 2.224404
+C38 35 gnd 2.080806f
+R35 34 35 2.224404
+C39 36 gnd 2.080806f
+R36 35 36 2.224404
+C40 37 gnd 2.080806f
+R37 36 37 2.224404
+C41 38 gnd 2.080806f
+R38 37 38 2.224404
+C42 39 gnd 2.080806f
+R39 38 39 2.224404
+R40 39 g62_1 2.224404
+R41 g62_1 g62_2 2.224404
+.ends
+
+.subckt netg24 g24_0 g24_1 gnd
+C1  g24_0 gnd 2.080806f
+C2  g24_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g24_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+R41 g24_1 40 2.224404
+.ends
+
+.subckt netg129 g129_0 g129_1 gnd
+C1  g129_0 gnd 2.080806f
+C2  g129_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g129_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+R41 40 g129_1 2.224404
+.ends
+
+.subckt netg130 g130_1 g130_0 gnd
+C1  g130_1 gnd 2.080806f
+C2  g130_0 gnd 2.080806f
+.ends
+
+.subckt netg154 g154_1 g154_0 gnd
+C1  g154_1 gnd 2.080806f
+C2  g154_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g154_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+R41 40 g154_1 2.224404
+.ends
+
+.subckt netg2215 g2215_1 g2215_4 g2215_2 g2215_5 g2215_0 g2215_3 gnd
+C1  g2215_1 gnd 2.080806f
+C2  g2215_4 gnd 2.080806f
+C3  g2215_2 gnd 2.080806f
+C4  g2215_5 gnd 2.080806f
+C5  g2215_0 gnd 2.080806f
+C6  g2215_3 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g2215_0 2.224404
+R2 g2215_3 1 2.224404
+C8 2 gnd 2.080806f
+R3 2 g2215_3 2.224404
+C9 3 gnd 2.080806f
+R4 3 2 2.224404
+C10 4 gnd 2.080806f
+R5 4 3 2.224404
+C11 5 gnd 2.080806f
+R6 5 4 2.224404
+R7 g2215_1 5 2.224404
+R8 g2215_5 g2215_1 2.224404
+C12 6 gnd 2.080806f
+R9 g2215_0 6 2.224404
+C13 7 gnd 2.080806f
+R10 6 7 2.224404
+C14 8 gnd 2.080806f
+R11 7 8 2.224404
+C15 9 gnd 2.080806f
+R12 8 9 2.224404
+C16 10 gnd 2.080806f
+R13 9 10 2.224404
+C17 11 gnd 2.080806f
+R14 10 11 2.224404
+C18 12 gnd 2.080806f
+R15 11 12 2.224404
+C19 13 gnd 2.080806f
+R16 12 13 2.224404
+C20 14 gnd 2.080806f
+R17 13 14 2.224404
+C21 15 gnd 2.080806f
+R18 14 15 2.224404
+C22 16 gnd 2.080806f
+R19 15 16 2.224404
+C23 17 gnd 2.080806f
+R20 16 17 2.224404
+C24 18 gnd 2.080806f
+R21 17 18 2.224404
+C25 19 gnd 2.080806f
+R22 18 19 2.224404
+C26 20 gnd 2.080806f
+R23 19 20 2.224404
+C27 21 gnd 2.080806f
+R24 20 21 2.224404
+C28 22 gnd 2.080806f
+R25 21 22 2.224404
+C29 23 gnd 2.080806f
+R26 22 23 2.224404
+C30 24 gnd 2.080806f
+R27 23 24 2.224404
+C31 25 gnd 2.080806f
+R28 24 25 2.224404
+C32 26 gnd 2.080806f
+R29 25 26 2.224404
+C33 27 gnd 2.080806f
+R30 26 27 2.224404
+C34 28 gnd 2.080806f
+R31 27 28 2.224404
+C35 29 gnd 2.080806f
+R32 28 29 2.224404
+C36 30 gnd 2.080806f
+R33 29 30 2.224404
+C37 31 gnd 2.080806f
+R34 30 31 2.224404
+C38 32 gnd 2.080806f
+R35 32 31 2.224404
+C39 33 gnd 2.080806f
+R36 32 33 2.224404
+C40 34 gnd 2.080806f
+R37 33 34 2.224404
+C41 35 gnd 2.080806f
+R38 35 34 2.224404
+C42 36 gnd 2.080806f
+R39 35 36 2.224404
+C43 37 gnd 2.080806f
+R40 36 37 2.224404
+C44 38 gnd 2.080806f
+R41 37 38 2.224404
+C45 39 gnd 2.080806f
+R42 38 39 2.224404
+R43 g2215_4 39 2.224404
+C46 40 gnd 2.080806f
+R44 39 40 2.224404
+C47 41 gnd 2.080806f
+R45 40 41 2.224404
+C48 42 gnd 2.080806f
+R46 41 42 2.224404
+C49 43 gnd 2.080806f
+R47 42 43 2.224404
+C50 44 gnd 2.080806f
+R48 43 44 2.224404
+C51 45 gnd 2.080806f
+R49 44 45 2.224404
+C52 46 gnd 2.080806f
+R50 45 46 2.224404
+C53 47 gnd 2.080806f
+R51 47 46 2.224404
+C54 48 gnd 2.080806f
+R52 48 47 2.224404
+R53 g2215_2 48 2.224404
+.ends
+
+.subckt netg63 g63_0 g63_2 g63_1 gnd
+C1  g63_0 gnd 2.080806f
+C2  g63_2 gnd 2.080806f
+C3  g63_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g63_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g63_2 3 2.224404
+C7 4 gnd 2.080806f
+R5 4 g63_2 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 11 10 2.224404
+C15 12 gnd 2.080806f
+R13 12 11 2.224404
+C16 13 gnd 2.080806f
+R14 13 12 2.224404
+C17 14 gnd 2.080806f
+R15 14 13 2.224404
+C18 15 gnd 2.080806f
+R16 15 14 2.224404
+C19 16 gnd 2.080806f
+R17 16 15 2.224404
+C20 17 gnd 2.080806f
+R18 17 16 2.224404
+C21 18 gnd 2.080806f
+R19 18 17 2.224404
+C22 19 gnd 2.080806f
+R20 19 18 2.224404
+C23 20 gnd 2.080806f
+R21 20 19 2.224404
+C24 21 gnd 2.080806f
+R22 21 20 2.224404
+C25 22 gnd 2.080806f
+R23 22 21 2.224404
+C26 23 gnd 2.080806f
+R24 23 22 2.224404
+C27 24 gnd 2.080806f
+R25 24 23 2.224404
+C28 25 gnd 2.080806f
+R26 25 24 2.224404
+C29 26 gnd 2.080806f
+R27 26 25 2.224404
+C30 27 gnd 2.080806f
+R28 27 26 2.224404
+C31 28 gnd 2.080806f
+R29 28 27 2.224404
+C32 29 gnd 2.080806f
+R30 29 28 2.224404
+C33 30 gnd 2.080806f
+R31 30 29 2.224404
+C34 31 gnd 2.080806f
+R32 31 30 2.224404
+C35 32 gnd 2.080806f
+R33 32 31 2.224404
+C36 33 gnd 2.080806f
+R34 33 32 2.224404
+C37 34 gnd 2.080806f
+R35 34 33 2.224404
+C38 35 gnd 2.080806f
+R36 35 34 2.224404
+C39 36 gnd 2.080806f
+R37 36 35 2.224404
+C40 37 gnd 2.080806f
+R38 37 36 2.224404
+C41 38 gnd 2.080806f
+R39 38 37 2.224404
+C42 39 gnd 2.080806f
+R40 39 38 2.224404
+C43 40 gnd 2.080806f
+R41 40 39 2.224404
+R42 g63_1 40 2.224404
+.ends
+
+.subckt netg131 g131_0 g131_1 gnd
+C1  g131_0 gnd 2.080806f
+C2  g131_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g131_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+R42 g131_1 41 2.224404
+.ends
+
+.subckt netg7524 g7524_0 g7524_1 gnd
+C1  g7524_0 gnd 2.080806f
+C2  g7524_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7524_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+R43 g7524_1 42 2.224404
+.ends
+
+.subckt netg61 g61_1 g61_2 g61_0 gnd
+C1  g61_1 gnd 2.080806f
+C2  g61_2 gnd 2.080806f
+C3  g61_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g61_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g61_2 2.224404
+C6 3 gnd 2.080806f
+R4 3 g61_0 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 11 10 2.224404
+C15 12 gnd 2.080806f
+R13 12 11 2.224404
+C16 13 gnd 2.080806f
+R14 13 12 2.224404
+C17 14 gnd 2.080806f
+R15 14 13 2.224404
+C18 15 gnd 2.080806f
+R16 15 14 2.224404
+C19 16 gnd 2.080806f
+R17 16 15 2.224404
+C20 17 gnd 2.080806f
+R18 17 16 2.224404
+C21 18 gnd 2.080806f
+R19 18 17 2.224404
+C22 19 gnd 2.080806f
+R20 19 18 2.224404
+C23 20 gnd 2.080806f
+R21 20 19 2.224404
+C24 21 gnd 2.080806f
+R22 21 20 2.224404
+C25 22 gnd 2.080806f
+R23 22 21 2.224404
+C26 23 gnd 2.080806f
+R24 23 22 2.224404
+C27 24 gnd 2.080806f
+R25 24 23 2.224404
+C28 25 gnd 2.080806f
+R26 25 24 2.224404
+C29 26 gnd 2.080806f
+R27 26 25 2.224404
+C30 27 gnd 2.080806f
+R28 27 26 2.224404
+C31 28 gnd 2.080806f
+R29 28 27 2.224404
+C32 29 gnd 2.080806f
+R30 29 28 2.224404
+C33 30 gnd 2.080806f
+R31 30 29 2.224404
+C34 31 gnd 2.080806f
+R32 31 30 2.224404
+C35 32 gnd 2.080806f
+R33 32 31 2.224404
+C36 33 gnd 2.080806f
+R34 33 32 2.224404
+C37 34 gnd 2.080806f
+R35 34 33 2.224404
+C38 35 gnd 2.080806f
+R36 35 34 2.224404
+C39 36 gnd 2.080806f
+R37 36 35 2.224404
+C40 37 gnd 2.080806f
+R38 37 36 2.224404
+C41 38 gnd 2.080806f
+R39 38 37 2.224404
+C42 39 gnd 2.080806f
+R40 39 38 2.224404
+C43 40 gnd 2.080806f
+R41 40 39 2.224404
+C44 41 gnd 2.080806f
+R42 41 40 2.224404
+R43 g61_1 41 2.224404
+.ends
+
+.subckt netg25 g25_0 g25_1 gnd
+C1  g25_0 gnd 2.080806f
+C2  g25_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g25_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+R43 42 g25_1 2.224404
+.ends
+
+.subckt netg2127 g2127_2 g2127_5 g2127_3 g2127_4 g2127_0 g2127_1 gnd
+C1  g2127_2 gnd 2.080806f
+C2  g2127_5 gnd 2.080806f
+C3  g2127_3 gnd 2.080806f
+C4  g2127_4 gnd 2.080806f
+C5  g2127_0 gnd 2.080806f
+C6  g2127_1 gnd 2.080806f
+R1 g2127_0 g2127_3 2.224404
+C7 1 gnd 2.080806f
+R2 1 g2127_3 2.224404
+R3 1 g2127_1 2.224404
+C8 2 gnd 2.080806f
+R4 g2127_3 2 2.224404
+C9 3 gnd 2.080806f
+R5 2 3 2.224404
+C10 4 gnd 2.080806f
+R6 3 4 2.224404
+C11 5 gnd 2.080806f
+R7 4 5 2.224404
+C12 6 gnd 2.080806f
+R8 5 6 2.224404
+C13 7 gnd 2.080806f
+R9 6 7 2.224404
+C14 8 gnd 2.080806f
+R10 7 8 2.224404
+C15 9 gnd 2.080806f
+R11 8 9 2.224404
+C16 10 gnd 2.080806f
+R12 9 10 2.224404
+C17 11 gnd 2.080806f
+R13 10 11 2.224404
+R14 11 g2127_2 2.224404
+C18 12 gnd 2.080806f
+R15 g2127_2 12 2.224404
+C19 13 gnd 2.080806f
+R16 12 13 2.224404
+C20 14 gnd 2.080806f
+R17 13 14 2.224404
+C21 15 gnd 2.080806f
+R18 14 15 2.224404
+C22 16 gnd 2.080806f
+R19 15 16 2.224404
+C23 17 gnd 2.080806f
+R20 16 17 2.224404
+C24 18 gnd 2.080806f
+R21 17 18 2.224404
+C25 19 gnd 2.080806f
+R22 18 19 2.224404
+C26 20 gnd 2.080806f
+R23 19 20 2.224404
+C27 21 gnd 2.080806f
+R24 20 21 2.224404
+C28 22 gnd 2.080806f
+R25 21 22 2.224404
+C29 23 gnd 2.080806f
+R26 22 23 2.224404
+C30 24 gnd 2.080806f
+R27 23 24 2.224404
+C31 25 gnd 2.080806f
+R28 24 25 2.224404
+C32 26 gnd 2.080806f
+R29 25 26 2.224404
+C33 27 gnd 2.080806f
+R30 26 27 2.224404
+C34 28 gnd 2.080806f
+R31 27 28 2.224404
+C35 29 gnd 2.080806f
+R32 28 29 2.224404
+C36 30 gnd 2.080806f
+R33 29 30 2.224404
+C37 31 gnd 2.080806f
+R34 30 31 2.224404
+C38 32 gnd 2.080806f
+R35 31 32 2.224404
+C39 33 gnd 2.080806f
+R36 32 33 2.224404
+C40 34 gnd 2.080806f
+R37 33 34 2.224404
+C41 35 gnd 2.080806f
+R38 34 35 2.224404
+C42 36 gnd 2.080806f
+R39 35 36 2.224404
+C43 37 gnd 2.080806f
+R40 36 37 2.224404
+C44 38 gnd 2.080806f
+R41 37 38 2.224404
+C45 39 gnd 2.080806f
+R42 38 39 2.224404
+C46 40 gnd 2.080806f
+R43 39 40 2.224404
+C47 41 gnd 2.080806f
+R44 41 40 2.224404
+C48 42 gnd 2.080806f
+R45 41 42 2.224404
+C49 43 gnd 2.080806f
+R46 42 43 2.224404
+C50 44 gnd 2.080806f
+R47 43 44 2.224404
+C51 45 gnd 2.080806f
+R48 45 44 2.224404
+C52 46 gnd 2.080806f
+R49 46 45 2.224404
+C53 47 gnd 2.080806f
+R50 46 47 2.224404
+R51 47 g2127_5 2.224404
+C54 48 gnd 2.080806f
+R52 48 g2127_5 2.224404
+C55 49 gnd 2.080806f
+R53 49 48 2.224404
+C56 50 gnd 2.080806f
+R54 50 49 2.224404
+R55 g2127_4 50 2.224404
+.ends
+
+.subckt netg28 g28_1 g28_0 gnd
+C1  g28_1 gnd 2.080806f
+C2  g28_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g28_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+R44 43 g28_1 2.224404
+.ends
+
+.subckt netg2 g2_1 g2_3 g2_2 g2_0 gnd
+C1  g2_1 gnd 2.080806f
+C2  g2_3 gnd 2.080806f
+C3  g2_2 gnd 2.080806f
+C4  g2_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g2_0 1 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+C7 3 gnd 2.080806f
+R3 2 3 2.224404
+C8 4 gnd 2.080806f
+R4 3 4 2.224404
+R5 4 g2_2 2.224404
+C9 5 gnd 2.080806f
+R6 g2_2 5 2.224404
+C10 6 gnd 2.080806f
+R7 5 6 2.224404
+C11 7 gnd 2.080806f
+R8 6 7 2.224404
+C12 8 gnd 2.080806f
+R9 7 8 2.224404
+C13 9 gnd 2.080806f
+R10 8 9 2.224404
+C14 10 gnd 2.080806f
+R11 9 10 2.224404
+C15 11 gnd 2.080806f
+R12 10 11 2.224404
+C16 12 gnd 2.080806f
+R13 11 12 2.224404
+C17 13 gnd 2.080806f
+R14 12 13 2.224404
+C18 14 gnd 2.080806f
+R15 13 14 2.224404
+C19 15 gnd 2.080806f
+R16 14 15 2.224404
+C20 16 gnd 2.080806f
+R17 15 16 2.224404
+C21 17 gnd 2.080806f
+R18 16 17 2.224404
+C22 18 gnd 2.080806f
+R19 17 18 2.224404
+C23 19 gnd 2.080806f
+R20 18 19 2.224404
+C24 20 gnd 2.080806f
+R21 19 20 2.224404
+C25 21 gnd 2.080806f
+R22 20 21 2.224404
+C26 22 gnd 2.080806f
+R23 21 22 2.224404
+C27 23 gnd 2.080806f
+R24 22 23 2.224404
+C28 24 gnd 2.080806f
+R25 23 24 2.224404
+C29 25 gnd 2.080806f
+R26 24 25 2.224404
+C30 26 gnd 2.080806f
+R27 25 26 2.224404
+C31 27 gnd 2.080806f
+R28 26 27 2.224404
+C32 28 gnd 2.080806f
+R29 27 28 2.224404
+C33 29 gnd 2.080806f
+R30 28 29 2.224404
+C34 30 gnd 2.080806f
+R31 29 30 2.224404
+C35 31 gnd 2.080806f
+R32 30 31 2.224404
+C36 32 gnd 2.080806f
+R33 31 32 2.224404
+C37 33 gnd 2.080806f
+R34 32 33 2.224404
+C38 34 gnd 2.080806f
+R35 33 34 2.224404
+C39 35 gnd 2.080806f
+R36 34 35 2.224404
+C40 36 gnd 2.080806f
+R37 35 36 2.224404
+C41 37 gnd 2.080806f
+R38 36 37 2.224404
+C42 38 gnd 2.080806f
+R39 37 38 2.224404
+C43 39 gnd 2.080806f
+R40 38 39 2.224404
+C44 40 gnd 2.080806f
+R41 39 40 2.224404
+C45 41 gnd 2.080806f
+R42 40 41 2.224404
+R43 41 g2_1 2.224404
+R44 41 g2_3 2.224404
+.ends
+
+.subckt netg19 g19_0 g19_1 gnd
+C1  g19_0 gnd 2.080806f
+C2  g19_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g19_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+R44 g19_1 43 2.224404
+.ends
+
+.subckt netg141 g141_1 g141_0 gnd
+C1  g141_1 gnd 2.080806f
+C2  g141_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g141_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+R44 g141_1 43 2.224404
+.ends
+
+.subckt netg7518 g7518_1 g7518_0 gnd
+C1  g7518_1 gnd 2.080806f
+C2  g7518_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7518_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+R44 g7518_1 43 2.224404
+.ends
+
+.subckt netg5 g5_0 g5_2 g5_1 gnd
+C1  g5_0 gnd 2.080806f
+C2  g5_2 gnd 2.080806f
+C3  g5_1 gnd 2.080806f
+R1 g5_0 g5_2 2.224404
+C4 1 gnd 2.080806f
+R2 1 g5_2 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 11 10 2.224404
+C15 12 gnd 2.080806f
+R13 12 11 2.224404
+C16 13 gnd 2.080806f
+R14 13 12 2.224404
+C17 14 gnd 2.080806f
+R15 14 13 2.224404
+C18 15 gnd 2.080806f
+R16 15 14 2.224404
+C19 16 gnd 2.080806f
+R17 16 15 2.224404
+C20 17 gnd 2.080806f
+R18 17 16 2.224404
+C21 18 gnd 2.080806f
+R19 18 17 2.224404
+C22 19 gnd 2.080806f
+R20 19 18 2.224404
+C23 20 gnd 2.080806f
+R21 20 19 2.224404
+C24 21 gnd 2.080806f
+R22 21 20 2.224404
+C25 22 gnd 2.080806f
+R23 22 21 2.224404
+C26 23 gnd 2.080806f
+R24 23 22 2.224404
+C27 24 gnd 2.080806f
+R25 24 23 2.224404
+C28 25 gnd 2.080806f
+R26 25 24 2.224404
+C29 26 gnd 2.080806f
+R27 26 25 2.224404
+C30 27 gnd 2.080806f
+R28 27 26 2.224404
+C31 28 gnd 2.080806f
+R29 28 27 2.224404
+C32 29 gnd 2.080806f
+R30 29 28 2.224404
+C33 30 gnd 2.080806f
+R31 30 29 2.224404
+C34 31 gnd 2.080806f
+R32 31 30 2.224404
+C35 32 gnd 2.080806f
+R33 32 31 2.224404
+C36 33 gnd 2.080806f
+R34 33 32 2.224404
+C37 34 gnd 2.080806f
+R35 34 33 2.224404
+C38 35 gnd 2.080806f
+R36 35 34 2.224404
+C39 36 gnd 2.080806f
+R37 36 35 2.224404
+C40 37 gnd 2.080806f
+R38 37 36 2.224404
+C41 38 gnd 2.080806f
+R39 38 37 2.224404
+C42 39 gnd 2.080806f
+R40 39 38 2.224404
+C43 40 gnd 2.080806f
+R41 40 39 2.224404
+C44 41 gnd 2.080806f
+R42 41 40 2.224404
+C45 42 gnd 2.080806f
+R43 42 41 2.224404
+R44 g5_1 42 2.224404
+.ends
+
+.subckt netg66 g66_2 g66_0 g66_1 gnd
+C1  g66_2 gnd 2.080806f
+C2  g66_0 gnd 2.080806f
+C3  g66_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g66_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 6 5 2.224404
+R7 g66_1 6 2.224404
+C10 7 gnd 2.080806f
+R8 7 g66_0 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 8 9 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 11 10 2.224404
+C15 12 gnd 2.080806f
+R13 12 11 2.224404
+C16 13 gnd 2.080806f
+R14 13 12 2.224404
+C17 14 gnd 2.080806f
+R15 14 13 2.224404
+C18 15 gnd 2.080806f
+R16 15 14 2.224404
+C19 16 gnd 2.080806f
+R17 16 15 2.224404
+C20 17 gnd 2.080806f
+R18 17 16 2.224404
+C21 18 gnd 2.080806f
+R19 18 17 2.224404
+C22 19 gnd 2.080806f
+R20 19 18 2.224404
+C23 20 gnd 2.080806f
+R21 20 19 2.224404
+C24 21 gnd 2.080806f
+R22 21 20 2.224404
+C25 22 gnd 2.080806f
+R23 22 21 2.224404
+C26 23 gnd 2.080806f
+R24 23 22 2.224404
+C27 24 gnd 2.080806f
+R25 24 23 2.224404
+C28 25 gnd 2.080806f
+R26 25 24 2.224404
+C29 26 gnd 2.080806f
+R27 26 25 2.224404
+C30 27 gnd 2.080806f
+R28 27 26 2.224404
+C31 28 gnd 2.080806f
+R29 28 27 2.224404
+C32 29 gnd 2.080806f
+R30 29 28 2.224404
+C33 30 gnd 2.080806f
+R31 30 29 2.224404
+C34 31 gnd 2.080806f
+R32 31 30 2.224404
+C35 32 gnd 2.080806f
+R33 32 31 2.224404
+C36 33 gnd 2.080806f
+R34 33 32 2.224404
+C37 34 gnd 2.080806f
+R35 34 33 2.224404
+C38 35 gnd 2.080806f
+R36 35 34 2.224404
+C39 36 gnd 2.080806f
+R37 36 35 2.224404
+C40 37 gnd 2.080806f
+R38 37 36 2.224404
+C41 38 gnd 2.080806f
+R39 38 37 2.224404
+C42 39 gnd 2.080806f
+R40 39 38 2.224404
+C43 40 gnd 2.080806f
+R41 40 39 2.224404
+C44 41 gnd 2.080806f
+R42 41 40 2.224404
+C45 42 gnd 2.080806f
+R43 42 41 2.224404
+C46 43 gnd 2.080806f
+R44 43 42 2.224404
+C47 44 gnd 2.080806f
+R45 44 43 2.224404
+C48 45 gnd 2.080806f
+R46 45 44 2.224404
+C49 46 gnd 2.080806f
+R47 46 45 2.224404
+C50 47 gnd 2.080806f
+R48 47 46 2.224404
+C51 48 gnd 2.080806f
+R49 48 47 2.224404
+C52 49 gnd 2.080806f
+R50 49 48 2.224404
+C53 50 gnd 2.080806f
+R51 50 49 2.224404
+C54 51 gnd 2.080806f
+R52 51 50 2.224404
+R53 g66_2 51 2.224404
+.ends
+
+.subckt netg7457 g7457_0 g7457_1 gnd
+C1  g7457_0 gnd 2.080806f
+C2  g7457_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7457_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+R44 43 g7457_1 2.224404
+.ends
+
+.subckt netg27 g27_1 g27_0 gnd
+C1  g27_1 gnd 2.080806f
+C2  g27_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g27_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+R45 g27_1 44 2.224404
+.ends
+
+.subckt netg6787 g6787_1 g6787_2 g6787_0 gnd
+C1  g6787_1 gnd 2.080806f
+C2  g6787_2 gnd 2.080806f
+C3  g6787_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g6787_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 6 5 2.224404
+C10 7 gnd 2.080806f
+R7 7 6 2.224404
+C11 8 gnd 2.080806f
+R8 8 7 2.224404
+C12 9 gnd 2.080806f
+R9 9 8 2.224404
+C13 10 gnd 2.080806f
+R10 10 9 2.224404
+R11 10 g6787_2 2.224404
+C14 11 gnd 2.080806f
+R12 11 g6787_0 2.224404
+C15 12 gnd 2.080806f
+R13 12 11 2.224404
+C16 13 gnd 2.080806f
+R14 13 12 2.224404
+C17 14 gnd 2.080806f
+R15 14 13 2.224404
+C18 15 gnd 2.080806f
+R16 15 14 2.224404
+C19 16 gnd 2.080806f
+R17 16 15 2.224404
+C20 17 gnd 2.080806f
+R18 17 16 2.224404
+C21 18 gnd 2.080806f
+R19 18 17 2.224404
+C22 19 gnd 2.080806f
+R20 19 18 2.224404
+C23 20 gnd 2.080806f
+R21 20 19 2.224404
+C24 21 gnd 2.080806f
+R22 21 20 2.224404
+C25 22 gnd 2.080806f
+R23 21 22 2.224404
+C26 23 gnd 2.080806f
+R24 23 22 2.224404
+C27 24 gnd 2.080806f
+R25 24 23 2.224404
+C28 25 gnd 2.080806f
+R26 25 24 2.224404
+C29 26 gnd 2.080806f
+R27 26 25 2.224404
+C30 27 gnd 2.080806f
+R28 27 26 2.224404
+C31 28 gnd 2.080806f
+R29 28 27 2.224404
+C32 29 gnd 2.080806f
+R30 29 28 2.224404
+C33 30 gnd 2.080806f
+R31 30 29 2.224404
+C34 31 gnd 2.080806f
+R32 31 30 2.224404
+C35 32 gnd 2.080806f
+R33 32 31 2.224404
+C36 33 gnd 2.080806f
+R34 33 32 2.224404
+C37 34 gnd 2.080806f
+R35 34 33 2.224404
+C38 35 gnd 2.080806f
+R36 35 34 2.224404
+C39 36 gnd 2.080806f
+R37 36 35 2.224404
+C40 37 gnd 2.080806f
+R38 37 36 2.224404
+C41 38 gnd 2.080806f
+R39 38 37 2.224404
+C42 39 gnd 2.080806f
+R40 39 38 2.224404
+C43 40 gnd 2.080806f
+R41 40 39 2.224404
+C44 41 gnd 2.080806f
+R42 41 40 2.224404
+C45 42 gnd 2.080806f
+R43 42 41 2.224404
+C46 43 gnd 2.080806f
+R44 42 43 2.224404
+R45 g6787_1 43 2.224404
+.ends
+
+.subckt netg49 g49_4 g49_0 g49_2 g49_3 g49_1 gnd
+C1  g49_4 gnd 2.080806f
+C2  g49_0 gnd 2.080806f
+C3  g49_2 gnd 2.080806f
+C4  g49_3 gnd 2.080806f
+C5  g49_1 gnd 2.080806f
+C6 1 gnd 2.080806f
+R1 g49_0 1 2.224404
+R2 1 g49_4 2.224404
+C7 2 gnd 2.080806f
+R3 2 g49_4 2.224404
+C8 3 gnd 2.080806f
+R4 2 3 2.224404
+C9 4 gnd 2.080806f
+R5 3 4 2.224404
+R6 4 g49_3 2.224404
+R7 g49_3 g49_2 2.224404
+C10 5 gnd 2.080806f
+R8 5 g49_0 2.224404
+C11 6 gnd 2.080806f
+R9 6 5 2.224404
+C12 7 gnd 2.080806f
+R10 7 6 2.224404
+C13 8 gnd 2.080806f
+R11 8 7 2.224404
+C14 9 gnd 2.080806f
+R12 9 8 2.224404
+C15 10 gnd 2.080806f
+R13 10 9 2.224404
+C16 11 gnd 2.080806f
+R14 11 10 2.224404
+C17 12 gnd 2.080806f
+R15 12 11 2.224404
+C18 13 gnd 2.080806f
+R16 13 12 2.224404
+C19 14 gnd 2.080806f
+R17 14 13 2.224404
+C20 15 gnd 2.080806f
+R18 15 14 2.224404
+C21 16 gnd 2.080806f
+R19 16 15 2.224404
+C22 17 gnd 2.080806f
+R20 17 16 2.224404
+C23 18 gnd 2.080806f
+R21 18 17 2.224404
+C24 19 gnd 2.080806f
+R22 19 18 2.224404
+C25 20 gnd 2.080806f
+R23 20 19 2.224404
+C26 21 gnd 2.080806f
+R24 21 20 2.224404
+C27 22 gnd 2.080806f
+R25 22 21 2.224404
+C28 23 gnd 2.080806f
+R26 23 22 2.224404
+C29 24 gnd 2.080806f
+R27 24 23 2.224404
+C30 25 gnd 2.080806f
+R28 25 24 2.224404
+C31 26 gnd 2.080806f
+R29 26 25 2.224404
+C32 27 gnd 2.080806f
+R30 27 26 2.224404
+C33 28 gnd 2.080806f
+R31 28 27 2.224404
+C34 29 gnd 2.080806f
+R32 29 28 2.224404
+C35 30 gnd 2.080806f
+R33 30 29 2.224404
+C36 31 gnd 2.080806f
+R34 31 30 2.224404
+C37 32 gnd 2.080806f
+R35 32 31 2.224404
+C38 33 gnd 2.080806f
+R36 33 32 2.224404
+C39 34 gnd 2.080806f
+R37 34 33 2.224404
+C40 35 gnd 2.080806f
+R38 35 34 2.224404
+C41 36 gnd 2.080806f
+R39 36 35 2.224404
+C42 37 gnd 2.080806f
+R40 37 36 2.224404
+C43 38 gnd 2.080806f
+R41 38 37 2.224404
+C44 39 gnd 2.080806f
+R42 39 38 2.224404
+C45 40 gnd 2.080806f
+R43 40 39 2.224404
+C46 41 gnd 2.080806f
+R44 41 40 2.224404
+C47 42 gnd 2.080806f
+R45 42 41 2.224404
+C48 43 gnd 2.080806f
+R46 43 42 2.224404
+R47 g49_1 43 2.224404
+.ends
+
+.subckt netg17 g17_0 g17_1 gnd
+C1  g17_0 gnd 2.080806f
+C2  g17_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g17_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+R45 44 g17_1 2.224404
+.ends
+
+.subckt netg76 g76_0 g76_1 gnd
+C1  g76_0 gnd 2.080806f
+C2  g76_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g76_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+R45 44 g76_1 2.224404
+.ends
+
+.subckt netg7536 g7536_0 g7536_1 gnd
+C1  g7536_0 gnd 2.080806f
+C2  g7536_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7536_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+R45 44 g7536_1 2.224404
+.ends
+
+.subckt netg7464 g7464_1 g7464_0 gnd
+C1  g7464_1 gnd 2.080806f
+C2  g7464_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7464_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+R46 g7464_1 45 2.224404
+.ends
+
+.subckt netg7468 g7468_1 g7468_0 gnd
+C1  g7468_1 gnd 2.080806f
+C2  g7468_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7468_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+R46 45 g7468_1 2.224404
+.ends
+
+.subckt netg7509 g7509_1 g7509_0 gnd
+C1  g7509_1 gnd 2.080806f
+C2  g7509_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7509_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+R47 46 g7509_1 2.224404
+.ends
+
+.subckt netg6771 g6771_4 g6771_6 g6771_5 g6771_0 g6771_3 g6771_1 g6771_2 gnd
+C1  g6771_4 gnd 2.080806f
+C2  g6771_6 gnd 2.080806f
+C3  g6771_5 gnd 2.080806f
+C4  g6771_0 gnd 2.080806f
+C5  g6771_3 gnd 2.080806f
+C6  g6771_1 gnd 2.080806f
+C7  g6771_2 gnd 2.080806f
+C8 1 gnd 2.080806f
+R1 g6771_0 1 2.224404
+C9 2 gnd 2.080806f
+R2 2 1 2.224404
+C10 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 g6771_5 3 2.224404
+C11 4 gnd 2.080806f
+R5 4 g6771_5 2.224404
+R6 g6771_3 4 2.224404
+R7 g6771_6 g6771_3 2.224404
+C12 5 gnd 2.080806f
+R8 g6771_3 5 2.224404
+R9 5 g6771_2 2.224404
+C13 6 gnd 2.080806f
+R10 6 g6771_6 2.224404
+C14 7 gnd 2.080806f
+R11 7 6 2.224404
+C15 8 gnd 2.080806f
+R12 8 7 2.224404
+C16 9 gnd 2.080806f
+R13 9 8 2.224404
+C17 10 gnd 2.080806f
+R14 10 9 2.224404
+C18 11 gnd 2.080806f
+R15 11 10 2.224404
+C19 12 gnd 2.080806f
+R16 12 11 2.224404
+C20 13 gnd 2.080806f
+R17 13 12 2.224404
+C21 14 gnd 2.080806f
+R18 14 13 2.224404
+C22 15 gnd 2.080806f
+R19 14 15 2.224404
+C23 16 gnd 2.080806f
+R20 16 15 2.224404
+C24 17 gnd 2.080806f
+R21 17 16 2.224404
+C25 18 gnd 2.080806f
+R22 18 17 2.224404
+C26 19 gnd 2.080806f
+R23 19 18 2.224404
+C27 20 gnd 2.080806f
+R24 20 19 2.224404
+C28 21 gnd 2.080806f
+R25 21 20 2.224404
+C29 22 gnd 2.080806f
+R26 22 21 2.224404
+C30 23 gnd 2.080806f
+R27 23 22 2.224404
+C31 24 gnd 2.080806f
+R28 23 24 2.224404
+R29 g6771_4 24 2.224404
+C32 25 gnd 2.080806f
+R30 g6771_4 25 2.224404
+C33 26 gnd 2.080806f
+R31 26 25 2.224404
+C34 27 gnd 2.080806f
+R32 27 26 2.224404
+C35 28 gnd 2.080806f
+R33 28 27 2.224404
+C36 29 gnd 2.080806f
+R34 29 28 2.224404
+C37 30 gnd 2.080806f
+R35 29 30 2.224404
+C38 31 gnd 2.080806f
+R36 30 31 2.224404
+C39 32 gnd 2.080806f
+R37 31 32 2.224404
+C40 33 gnd 2.080806f
+R38 32 33 2.224404
+C41 34 gnd 2.080806f
+R39 33 34 2.224404
+C42 35 gnd 2.080806f
+R40 35 34 2.224404
+C43 36 gnd 2.080806f
+R41 36 35 2.224404
+C44 37 gnd 2.080806f
+R42 37 36 2.224404
+C45 38 gnd 2.080806f
+R43 37 38 2.224404
+C46 39 gnd 2.080806f
+R44 38 39 2.224404
+C47 40 gnd 2.080806f
+R45 39 40 2.224404
+C48 41 gnd 2.080806f
+R46 40 41 2.224404
+C49 42 gnd 2.080806f
+R47 41 42 2.224404
+C50 43 gnd 2.080806f
+R48 42 43 2.224404
+C51 44 gnd 2.080806f
+R49 44 43 2.224404
+C52 45 gnd 2.080806f
+R50 44 45 2.224404
+R51 g6771_1 45 2.224404
+.ends
+
+.subckt netg7505 g7505_1 g7505_0 gnd
+C1  g7505_1 gnd 2.080806f
+C2  g7505_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7505_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+R47 g7505_1 46 2.224404
+.ends
+
+.subckt netg118 g118_0 g118_1 gnd
+C1  g118_0 gnd 2.080806f
+C2  g118_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g118_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+R47 46 g118_1 2.224404
+.ends
+
+.subckt netg7463 g7463_0 g7463_1 gnd
+C1  g7463_0 gnd 2.080806f
+C2  g7463_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7463_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+R47 g7463_1 46 2.224404
+.ends
+
+.subckt netg7469 g7469_0 g7469_1 gnd
+C1  g7469_0 gnd 2.080806f
+C2  g7469_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7469_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+R48 47 g7469_1 2.224404
+.ends
+
+.subckt netg7508 g7508_1 g7508_0 gnd
+C1  g7508_1 gnd 2.080806f
+C2  g7508_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7508_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+R48 47 g7508_1 2.224404
+.ends
+
+.subckt netg7544 g7544_1 g7544_0 gnd
+C1  g7544_1 gnd 2.080806f
+C2  g7544_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7544_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+R48 g7544_1 47 2.224404
+.ends
+
+.subckt netg5370 g5370_3 g5370_2 g5370_9 g5370_8 g5370_7 g5370_6 g5370_0 g5370_1 g5370_4 g5370_5 gnd
+C1  g5370_3 gnd 2.080806f
+C2  g5370_2 gnd 2.080806f
+C3  g5370_9 gnd 2.080806f
+C4  g5370_8 gnd 2.080806f
+C5  g5370_7 gnd 2.080806f
+C6  g5370_6 gnd 2.080806f
+C7  g5370_0 gnd 2.080806f
+C8  g5370_1 gnd 2.080806f
+C9  g5370_4 gnd 2.080806f
+C10  g5370_5 gnd 2.080806f
+C11 1 gnd 2.080806f
+R1 g5370_0 1 2.224404
+C12 2 gnd 2.080806f
+R2 1 2 2.224404
+C13 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 g5370_7 3 2.224404
+C14 4 gnd 2.080806f
+R5 4 g5370_0 2.224404
+C15 5 gnd 2.080806f
+R6 4 5 2.224404
+R7 g5370_3 5 2.224404
+C16 6 gnd 2.080806f
+R8 6 g5370_3 2.224404
+C17 7 gnd 2.080806f
+R9 7 6 2.224404
+C18 8 gnd 2.080806f
+R10 7 8 2.224404
+C19 9 gnd 2.080806f
+R11 8 9 2.224404
+C20 10 gnd 2.080806f
+R12 9 10 2.224404
+R13 10 g5370_5 2.224404
+C21 11 gnd 2.080806f
+R14 9 11 2.224404
+C22 12 gnd 2.080806f
+R15 11 12 2.224404
+R16 12 g5370_8 2.224404
+C23 13 gnd 2.080806f
+R17 g5370_8 13 2.224404
+C24 14 gnd 2.080806f
+R18 13 14 2.224404
+C25 15 gnd 2.080806f
+R19 14 15 2.224404
+C26 16 gnd 2.080806f
+R20 15 16 2.224404
+R21 g5370_2 16 2.224404
+C27 17 gnd 2.080806f
+R22 g5370_2 17 2.224404
+R23 g5370_4 17 2.224404
+R24 g5370_9 7 2.224404
+R25 g5370_6 8 2.224404
+C28 18 gnd 2.080806f
+R26 g5370_4 18 2.224404
+C29 19 gnd 2.080806f
+R27 18 19 2.224404
+C30 20 gnd 2.080806f
+R28 19 20 2.224404
+C31 21 gnd 2.080806f
+R29 21 20 2.224404
+C32 22 gnd 2.080806f
+R30 22 21 2.224404
+C33 23 gnd 2.080806f
+R31 23 22 2.224404
+C34 24 gnd 2.080806f
+R32 24 23 2.224404
+C35 25 gnd 2.080806f
+R33 24 25 2.224404
+C36 26 gnd 2.080806f
+R34 26 25 2.224404
+C37 27 gnd 2.080806f
+R35 27 26 2.224404
+C38 28 gnd 2.080806f
+R36 28 27 2.224404
+C39 29 gnd 2.080806f
+R37 28 29 2.224404
+C40 30 gnd 2.080806f
+R38 29 30 2.224404
+C41 31 gnd 2.080806f
+R39 30 31 2.224404
+C42 32 gnd 2.080806f
+R40 32 31 2.224404
+C43 33 gnd 2.080806f
+R41 33 32 2.224404
+C44 34 gnd 2.080806f
+R42 34 33 2.224404
+C45 35 gnd 2.080806f
+R43 35 34 2.224404
+C46 36 gnd 2.080806f
+R44 36 35 2.224404
+C47 37 gnd 2.080806f
+R45 37 36 2.224404
+C48 38 gnd 2.080806f
+R46 38 37 2.224404
+C49 39 gnd 2.080806f
+R47 39 38 2.224404
+C50 40 gnd 2.080806f
+R48 40 39 2.224404
+C51 41 gnd 2.080806f
+R49 41 40 2.224404
+C52 42 gnd 2.080806f
+R50 42 41 2.224404
+C53 43 gnd 2.080806f
+R51 43 42 2.224404
+C54 44 gnd 2.080806f
+R52 43 44 2.224404
+C55 45 gnd 2.080806f
+R53 44 45 2.224404
+C56 46 gnd 2.080806f
+R54 46 45 2.224404
+C57 47 gnd 2.080806f
+R55 47 46 2.224404
+C58 48 gnd 2.080806f
+R56 48 47 2.224404
+C59 49 gnd 2.080806f
+R57 49 48 2.224404
+C60 50 gnd 2.080806f
+R58 50 49 2.224404
+C61 51 gnd 2.080806f
+R59 51 50 2.224404
+C62 52 gnd 2.080806f
+R60 52 51 2.224404
+C63 53 gnd 2.080806f
+R61 53 52 2.224404
+C64 54 gnd 2.080806f
+R62 54 53 2.224404
+C65 55 gnd 2.080806f
+R63 55 54 2.224404
+C66 56 gnd 2.080806f
+R64 55 56 2.224404
+C67 57 gnd 2.080806f
+R65 57 56 2.224404
+R66 57 g5370_1 2.224404
+.ends
+
+.subckt netg1698 g1698_2 g1698_5 g1698_1 g1698_3 g1698_0 g1698_4 gnd
+C1  g1698_2 gnd 2.080806f
+C2  g1698_5 gnd 2.080806f
+C3  g1698_1 gnd 2.080806f
+C4  g1698_3 gnd 2.080806f
+C5  g1698_0 gnd 2.080806f
+C6  g1698_4 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 g1698_0 1 2.224404
+C8 2 gnd 2.080806f
+R2 1 2 2.224404
+C9 3 gnd 2.080806f
+R3 2 3 2.224404
+C10 4 gnd 2.080806f
+R4 3 4 2.224404
+C11 5 gnd 2.080806f
+R5 4 5 2.224404
+C12 6 gnd 2.080806f
+R6 5 6 2.224404
+C13 7 gnd 2.080806f
+R7 6 7 2.224404
+C14 8 gnd 2.080806f
+R8 7 8 2.224404
+C15 9 gnd 2.080806f
+R9 8 9 2.224404
+C16 10 gnd 2.080806f
+R10 9 10 2.224404
+R11 10 g1698_2 2.224404
+C17 11 gnd 2.080806f
+R12 11 g1698_0 2.224404
+C18 12 gnd 2.080806f
+R13 12 11 2.224404
+C19 13 gnd 2.080806f
+R14 13 12 2.224404
+C20 14 gnd 2.080806f
+R15 14 13 2.224404
+C21 15 gnd 2.080806f
+R16 15 14 2.224404
+C22 16 gnd 2.080806f
+R17 16 15 2.224404
+C23 17 gnd 2.080806f
+R18 17 16 2.224404
+C24 18 gnd 2.080806f
+R19 18 17 2.224404
+C25 19 gnd 2.080806f
+R20 19 18 2.224404
+C26 20 gnd 2.080806f
+R21 20 19 2.224404
+C27 21 gnd 2.080806f
+R22 21 20 2.224404
+C28 22 gnd 2.080806f
+R23 22 21 2.224404
+C29 23 gnd 2.080806f
+R24 23 22 2.224404
+C30 24 gnd 2.080806f
+R25 24 23 2.224404
+R26 g1698_3 24 2.224404
+C31 25 gnd 2.080806f
+R27 25 g1698_3 2.224404
+C32 26 gnd 2.080806f
+R28 26 25 2.224404
+C33 27 gnd 2.080806f
+R29 27 26 2.224404
+C34 28 gnd 2.080806f
+R30 28 27 2.224404
+C35 29 gnd 2.080806f
+R31 29 28 2.224404
+C36 30 gnd 2.080806f
+R32 30 29 2.224404
+C37 31 gnd 2.080806f
+R33 31 30 2.224404
+C38 32 gnd 2.080806f
+R34 32 31 2.224404
+C39 33 gnd 2.080806f
+R35 33 32 2.224404
+C40 34 gnd 2.080806f
+R36 34 33 2.224404
+C41 35 gnd 2.080806f
+R37 35 34 2.224404
+C42 36 gnd 2.080806f
+R38 36 35 2.224404
+C43 37 gnd 2.080806f
+R39 37 36 2.224404
+C44 38 gnd 2.080806f
+R40 38 37 2.224404
+C45 39 gnd 2.080806f
+R41 39 38 2.224404
+C46 40 gnd 2.080806f
+R42 40 39 2.224404
+R43 g1698_4 40 2.224404
+C47 41 gnd 2.080806f
+R44 41 g1698_4 2.224404
+R45 g1698_1 41 2.224404
+C48 42 gnd 2.080806f
+R46 42 g1698_1 2.224404
+C49 43 gnd 2.080806f
+R47 43 42 2.224404
+R48 g1698_5 43 2.224404
+.ends
+
+.subckt netg23 g23_1 g23_0 gnd
+C1  g23_1 gnd 2.080806f
+C2  g23_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g23_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+R48 g23_1 47 2.224404
+.ends
+
+.subckt netg7489 g7489_1 g7489_0 gnd
+C1  g7489_1 gnd 2.080806f
+C2  g7489_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7489_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+R48 g7489_1 47 2.224404
+.ends
+
+.subckt netg121 g121_1 g121_0 gnd
+C1  g121_1 gnd 2.080806f
+C2  g121_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g121_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+R48 47 g121_1 2.224404
+.ends
+
+.subckt netg7461 g7461_0 g7461_1 gnd
+C1  g7461_0 gnd 2.080806f
+C2  g7461_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7461_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+R48 g7461_1 47 2.224404
+.ends
+
+.subckt netg7459 g7459_1 g7459_0 gnd
+C1  g7459_1 gnd 2.080806f
+C2  g7459_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7459_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+R48 g7459_1 47 2.224404
+.ends
+
+.subckt netg7481 g7481_1 g7481_0 gnd
+C1  g7481_1 gnd 2.080806f
+C2  g7481_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7481_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+R48 47 g7481_1 2.224404
+.ends
+
+.subckt netg7447 g7447_1 g7447_0 gnd
+C1  g7447_1 gnd 2.080806f
+C2  g7447_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7447_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+C50 48 gnd 2.080806f
+R48 47 48 2.224404
+R49 48 g7447_1 2.224404
+.ends
+
+.subckt netg7523 g7523_1 g7523_0 gnd
+C1  g7523_1 gnd 2.080806f
+C2  g7523_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7523_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+C50 48 gnd 2.080806f
+R48 48 47 2.224404
+R49 g7523_1 48 2.224404
+.ends
+
+.subckt netg7446 g7446_0 g7446_1 gnd
+C1  g7446_0 gnd 2.080806f
+C2  g7446_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7446_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+C50 48 gnd 2.080806f
+R48 48 47 2.224404
+R49 g7446_1 48 2.224404
+.ends
+
+.subckt netg22 g22_1 g22_0 gnd
+C1  g22_1 gnd 2.080806f
+C2  g22_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g22_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+C50 48 gnd 2.080806f
+R48 48 47 2.224404
+R49 g22_1 48 2.224404
+.ends
+
+.subckt netg50 g50_1 g50_0 g50_2 gnd
+C1  g50_1 gnd 2.080806f
+C2  g50_0 gnd 2.080806f
+C3  g50_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g50_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+C8 5 gnd 2.080806f
+R5 4 5 2.224404
+C9 6 gnd 2.080806f
+R6 5 6 2.224404
+C10 7 gnd 2.080806f
+R7 6 7 2.224404
+C11 8 gnd 2.080806f
+R8 7 8 2.224404
+C12 9 gnd 2.080806f
+R9 8 9 2.224404
+C13 10 gnd 2.080806f
+R10 9 10 2.224404
+C14 11 gnd 2.080806f
+R11 10 11 2.224404
+C15 12 gnd 2.080806f
+R12 11 12 2.224404
+C16 13 gnd 2.080806f
+R13 12 13 2.224404
+C17 14 gnd 2.080806f
+R14 13 14 2.224404
+C18 15 gnd 2.080806f
+R15 14 15 2.224404
+C19 16 gnd 2.080806f
+R16 15 16 2.224404
+C20 17 gnd 2.080806f
+R17 16 17 2.224404
+C21 18 gnd 2.080806f
+R18 17 18 2.224404
+C22 19 gnd 2.080806f
+R19 18 19 2.224404
+C23 20 gnd 2.080806f
+R20 19 20 2.224404
+C24 21 gnd 2.080806f
+R21 20 21 2.224404
+C25 22 gnd 2.080806f
+R22 21 22 2.224404
+C26 23 gnd 2.080806f
+R23 22 23 2.224404
+C27 24 gnd 2.080806f
+R24 23 24 2.224404
+C28 25 gnd 2.080806f
+R25 24 25 2.224404
+C29 26 gnd 2.080806f
+R26 25 26 2.224404
+C30 27 gnd 2.080806f
+R27 26 27 2.224404
+C31 28 gnd 2.080806f
+R28 27 28 2.224404
+C32 29 gnd 2.080806f
+R29 28 29 2.224404
+C33 30 gnd 2.080806f
+R30 29 30 2.224404
+C34 31 gnd 2.080806f
+R31 30 31 2.224404
+C35 32 gnd 2.080806f
+R32 31 32 2.224404
+C36 33 gnd 2.080806f
+R33 32 33 2.224404
+C37 34 gnd 2.080806f
+R34 33 34 2.224404
+C38 35 gnd 2.080806f
+R35 34 35 2.224404
+C39 36 gnd 2.080806f
+R36 35 36 2.224404
+C40 37 gnd 2.080806f
+R37 36 37 2.224404
+C41 38 gnd 2.080806f
+R38 37 38 2.224404
+C42 39 gnd 2.080806f
+R39 38 39 2.224404
+C43 40 gnd 2.080806f
+R40 39 40 2.224404
+C44 41 gnd 2.080806f
+R41 40 41 2.224404
+C45 42 gnd 2.080806f
+R42 41 42 2.224404
+C46 43 gnd 2.080806f
+R43 42 43 2.224404
+C47 44 gnd 2.080806f
+R44 43 44 2.224404
+C48 45 gnd 2.080806f
+R45 44 45 2.224404
+C49 46 gnd 2.080806f
+R46 45 46 2.224404
+C50 47 gnd 2.080806f
+R47 46 47 2.224404
+R48 47 g50_1 2.224404
+R49 g50_1 g50_2 2.224404
+.ends
+
+.subckt netg157 g157_1 g157_0 gnd
+C1  g157_1 gnd 2.080806f
+C2  g157_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g157_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+C50 48 gnd 2.080806f
+R48 48 47 2.224404
+R49 g157_1 48 2.224404
+.ends
+
+.subckt netg7452 g7452_1 g7452_0 gnd
+C1  g7452_1 gnd 2.080806f
+C2  g7452_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7452_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+C50 48 gnd 2.080806f
+R48 48 47 2.224404
+R49 g7452_1 48 2.224404
+.ends
+
+.subckt netg7543 g7543_1 g7543_0 gnd
+C1  g7543_1 gnd 2.080806f
+C2  g7543_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7543_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+C50 48 gnd 2.080806f
+R48 48 47 2.224404
+R49 g7543_1 48 2.224404
+.ends
+
+.subckt netg148 g148_0 g148_1 gnd
+C1  g148_0 gnd 2.080806f
+C2  g148_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g148_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+C50 48 gnd 2.080806f
+R48 48 47 2.224404
+R49 g148_1 48 2.224404
+.ends
+
+.subckt netg2244 g2244_4 g2244_2 g2244_1 g2244_0 g2244_5 g2244_3 gnd
+C1  g2244_4 gnd 2.080806f
+C2  g2244_2 gnd 2.080806f
+C3  g2244_1 gnd 2.080806f
+C4  g2244_0 gnd 2.080806f
+C5  g2244_5 gnd 2.080806f
+C6  g2244_3 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g2244_0 2.224404
+R2 g2244_5 1 2.224404
+C8 2 gnd 2.080806f
+R3 2 g2244_5 2.224404
+C9 3 gnd 2.080806f
+R4 2 3 2.224404
+R5 g2244_2 3 2.224404
+C10 4 gnd 2.080806f
+R6 g2244_5 4 2.224404
+C11 5 gnd 2.080806f
+R7 4 5 2.224404
+C12 6 gnd 2.080806f
+R8 5 6 2.224404
+C13 7 gnd 2.080806f
+R9 6 7 2.224404
+C14 8 gnd 2.080806f
+R10 7 8 2.224404
+R11 8 g2244_1 2.224404
+C15 9 gnd 2.080806f
+R12 9 g2244_2 2.224404
+C16 10 gnd 2.080806f
+R13 10 9 2.224404
+C17 11 gnd 2.080806f
+R14 11 10 2.224404
+C18 12 gnd 2.080806f
+R15 12 11 2.224404
+C19 13 gnd 2.080806f
+R16 12 13 2.224404
+C20 14 gnd 2.080806f
+R17 13 14 2.224404
+R18 g2244_4 14 2.224404
+C21 15 gnd 2.080806f
+R19 g2244_1 15 2.224404
+C22 16 gnd 2.080806f
+R20 15 16 2.224404
+C23 17 gnd 2.080806f
+R21 16 17 2.224404
+C24 18 gnd 2.080806f
+R22 17 18 2.224404
+C25 19 gnd 2.080806f
+R23 18 19 2.224404
+C26 20 gnd 2.080806f
+R24 19 20 2.224404
+C27 21 gnd 2.080806f
+R25 20 21 2.224404
+C28 22 gnd 2.080806f
+R26 21 22 2.224404
+C29 23 gnd 2.080806f
+R27 22 23 2.224404
+C30 24 gnd 2.080806f
+R28 23 24 2.224404
+C31 25 gnd 2.080806f
+R29 24 25 2.224404
+C32 26 gnd 2.080806f
+R30 25 26 2.224404
+C33 27 gnd 2.080806f
+R31 26 27 2.224404
+C34 28 gnd 2.080806f
+R32 27 28 2.224404
+C35 29 gnd 2.080806f
+R33 28 29 2.224404
+C36 30 gnd 2.080806f
+R34 29 30 2.224404
+C37 31 gnd 2.080806f
+R35 30 31 2.224404
+C38 32 gnd 2.080806f
+R36 31 32 2.224404
+C39 33 gnd 2.080806f
+R37 32 33 2.224404
+C40 34 gnd 2.080806f
+R38 33 34 2.224404
+C41 35 gnd 2.080806f
+R39 34 35 2.224404
+C42 36 gnd 2.080806f
+R40 35 36 2.224404
+C43 37 gnd 2.080806f
+R41 36 37 2.224404
+C44 38 gnd 2.080806f
+R42 37 38 2.224404
+C45 39 gnd 2.080806f
+R43 38 39 2.224404
+C46 40 gnd 2.080806f
+R44 39 40 2.224404
+C47 41 gnd 2.080806f
+R45 40 41 2.224404
+C48 42 gnd 2.080806f
+R46 41 42 2.224404
+C49 43 gnd 2.080806f
+R47 42 43 2.224404
+C50 44 gnd 2.080806f
+R48 43 44 2.224404
+C51 45 gnd 2.080806f
+R49 44 45 2.224404
+C52 46 gnd 2.080806f
+R50 45 46 2.224404
+C53 47 gnd 2.080806f
+R51 46 47 2.224404
+C54 48 gnd 2.080806f
+R52 47 48 2.224404
+C55 49 gnd 2.080806f
+R53 48 49 2.224404
+R54 49 g2244_3 2.224404
+.ends
+
+.subckt netg7443 g7443_1 g7443_0 gnd
+C1  g7443_1 gnd 2.080806f
+C2  g7443_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7443_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+C50 48 gnd 2.080806f
+R48 47 48 2.224404
+C51 49 gnd 2.080806f
+R49 48 49 2.224404
+R50 49 g7443_1 2.224404
+.ends
+
+.subckt netg158 g158_1 g158_0 gnd
+C1  g158_1 gnd 2.080806f
+C2  g158_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g158_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+C50 48 gnd 2.080806f
+R48 48 47 2.224404
+C51 49 gnd 2.080806f
+R49 49 48 2.224404
+R50 g158_1 49 2.224404
+.ends
+
+.subckt netg7453 g7453_0 g7453_1 gnd
+C1  g7453_0 gnd 2.080806f
+C2  g7453_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7453_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+C50 48 gnd 2.080806f
+R48 47 48 2.224404
+C51 49 gnd 2.080806f
+R49 48 49 2.224404
+R50 49 g7453_1 2.224404
+.ends
+
+.subckt netg190 g190_1 g190_2 g190_0 gnd
+C1  g190_1 gnd 2.080806f
+C2  g190_2 gnd 2.080806f
+C3  g190_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g190_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 6 5 2.224404
+C10 7 gnd 2.080806f
+R7 7 6 2.224404
+C11 8 gnd 2.080806f
+R8 8 7 2.224404
+C12 9 gnd 2.080806f
+R9 9 8 2.224404
+C13 10 gnd 2.080806f
+R10 10 9 2.224404
+C14 11 gnd 2.080806f
+R11 11 10 2.224404
+C15 12 gnd 2.080806f
+R12 12 11 2.224404
+C16 13 gnd 2.080806f
+R13 13 12 2.224404
+C17 14 gnd 2.080806f
+R14 14 13 2.224404
+C18 15 gnd 2.080806f
+R15 15 14 2.224404
+C19 16 gnd 2.080806f
+R16 16 15 2.224404
+C20 17 gnd 2.080806f
+R17 17 16 2.224404
+C21 18 gnd 2.080806f
+R18 18 17 2.224404
+C22 19 gnd 2.080806f
+R19 19 18 2.224404
+C23 20 gnd 2.080806f
+R20 20 19 2.224404
+C24 21 gnd 2.080806f
+R21 21 20 2.224404
+C25 22 gnd 2.080806f
+R22 22 21 2.224404
+C26 23 gnd 2.080806f
+R23 23 22 2.224404
+C27 24 gnd 2.080806f
+R24 24 23 2.224404
+C28 25 gnd 2.080806f
+R25 25 24 2.224404
+C29 26 gnd 2.080806f
+R26 26 25 2.224404
+C30 27 gnd 2.080806f
+R27 27 26 2.224404
+C31 28 gnd 2.080806f
+R28 28 27 2.224404
+C32 29 gnd 2.080806f
+R29 29 28 2.224404
+C33 30 gnd 2.080806f
+R30 30 29 2.224404
+C34 31 gnd 2.080806f
+R31 31 30 2.224404
+C35 32 gnd 2.080806f
+R32 32 31 2.224404
+C36 33 gnd 2.080806f
+R33 33 32 2.224404
+C37 34 gnd 2.080806f
+R34 34 33 2.224404
+C38 35 gnd 2.080806f
+R35 35 34 2.224404
+C39 36 gnd 2.080806f
+R36 36 35 2.224404
+C40 37 gnd 2.080806f
+R37 37 36 2.224404
+C41 38 gnd 2.080806f
+R38 38 37 2.224404
+C42 39 gnd 2.080806f
+R39 39 38 2.224404
+C43 40 gnd 2.080806f
+R40 40 39 2.224404
+C44 41 gnd 2.080806f
+R41 41 40 2.224404
+C45 42 gnd 2.080806f
+R42 42 41 2.224404
+C46 43 gnd 2.080806f
+R43 43 42 2.224404
+C47 44 gnd 2.080806f
+R44 44 43 2.224404
+C48 45 gnd 2.080806f
+R45 45 44 2.224404
+R46 g190_2 45 2.224404
+C49 46 gnd 2.080806f
+R47 46 g190_2 2.224404
+C50 47 gnd 2.080806f
+R48 47 46 2.224404
+C51 48 gnd 2.080806f
+R49 48 47 2.224404
+C52 49 gnd 2.080806f
+R50 49 48 2.224404
+R51 49 g190_1 2.224404
+.ends
+
+.subckt netg1704 g1704_5 g1704_1 g1704_2 g1704_0 g1704_4 g1704_3 gnd
+C1  g1704_5 gnd 2.080806f
+C2  g1704_1 gnd 2.080806f
+C3  g1704_2 gnd 2.080806f
+C4  g1704_0 gnd 2.080806f
+C5  g1704_4 gnd 2.080806f
+C6  g1704_3 gnd 2.080806f
+R1 g1704_1 g1704_0 2.224404
+C7 1 gnd 2.080806f
+R2 g1704_0 1 2.224404
+R3 1 g1704_3 2.224404
+C8 2 gnd 2.080806f
+R4 g1704_0 2 2.224404
+C9 3 gnd 2.080806f
+R5 3 2 2.224404
+C10 4 gnd 2.080806f
+R6 3 4 2.224404
+C11 5 gnd 2.080806f
+R7 4 5 2.224404
+C12 6 gnd 2.080806f
+R8 5 6 2.224404
+C13 7 gnd 2.080806f
+R9 6 7 2.224404
+C14 8 gnd 2.080806f
+R10 7 8 2.224404
+C15 9 gnd 2.080806f
+R11 8 9 2.224404
+C16 10 gnd 2.080806f
+R12 9 10 2.224404
+C17 11 gnd 2.080806f
+R13 10 11 2.224404
+C18 12 gnd 2.080806f
+R14 11 12 2.224404
+R15 12 g1704_2 2.224404
+C19 13 gnd 2.080806f
+R16 13 g1704_2 2.224404
+C20 14 gnd 2.080806f
+R17 13 14 2.224404
+C21 15 gnd 2.080806f
+R18 14 15 2.224404
+C22 16 gnd 2.080806f
+R19 15 16 2.224404
+C23 17 gnd 2.080806f
+R20 16 17 2.224404
+C24 18 gnd 2.080806f
+R21 17 18 2.224404
+C25 19 gnd 2.080806f
+R22 19 18 2.224404
+C26 20 gnd 2.080806f
+R23 19 20 2.224404
+C27 21 gnd 2.080806f
+R24 20 21 2.224404
+C28 22 gnd 2.080806f
+R25 21 22 2.224404
+C29 23 gnd 2.080806f
+R26 22 23 2.224404
+C30 24 gnd 2.080806f
+R27 23 24 2.224404
+C31 25 gnd 2.080806f
+R28 24 25 2.224404
+C32 26 gnd 2.080806f
+R29 25 26 2.224404
+C33 27 gnd 2.080806f
+R30 26 27 2.224404
+C34 28 gnd 2.080806f
+R31 27 28 2.224404
+C35 29 gnd 2.080806f
+R32 28 29 2.224404
+C36 30 gnd 2.080806f
+R33 29 30 2.224404
+C37 31 gnd 2.080806f
+R34 30 31 2.224404
+C38 32 gnd 2.080806f
+R35 31 32 2.224404
+C39 33 gnd 2.080806f
+R36 32 33 2.224404
+C40 34 gnd 2.080806f
+R37 33 34 2.224404
+C41 35 gnd 2.080806f
+R38 34 35 2.224404
+C42 36 gnd 2.080806f
+R39 35 36 2.224404
+C43 37 gnd 2.080806f
+R40 36 37 2.224404
+C44 38 gnd 2.080806f
+R41 37 38 2.224404
+C45 39 gnd 2.080806f
+R42 38 39 2.224404
+C46 40 gnd 2.080806f
+R43 39 40 2.224404
+C47 41 gnd 2.080806f
+R44 40 41 2.224404
+C48 42 gnd 2.080806f
+R45 41 42 2.224404
+C49 43 gnd 2.080806f
+R46 42 43 2.224404
+C50 44 gnd 2.080806f
+R47 44 43 2.224404
+C51 45 gnd 2.080806f
+R48 44 45 2.224404
+C52 46 gnd 2.080806f
+R49 46 45 2.224404
+R50 46 g1704_4 2.224404
+C53 47 gnd 2.080806f
+R51 g1704_4 47 2.224404
+C54 48 gnd 2.080806f
+R52 47 48 2.224404
+C55 49 gnd 2.080806f
+R53 48 49 2.224404
+C56 50 gnd 2.080806f
+R54 49 50 2.224404
+C57 51 gnd 2.080806f
+R55 50 51 2.224404
+C58 52 gnd 2.080806f
+R56 51 52 2.224404
+C59 53 gnd 2.080806f
+R57 52 53 2.224404
+C60 54 gnd 2.080806f
+R58 53 54 2.224404
+C61 55 gnd 2.080806f
+R59 54 55 2.224404
+C62 56 gnd 2.080806f
+R60 55 56 2.224404
+C63 57 gnd 2.080806f
+R61 56 57 2.224404
+R62 57 g1704_5 2.224404
+.ends
+
+.subckt netg7530 g7530_1 g7530_0 gnd
+C1  g7530_1 gnd 2.080806f
+C2  g7530_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7530_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+C50 48 gnd 2.080806f
+R48 47 48 2.224404
+C51 49 gnd 2.080806f
+R49 48 49 2.224404
+C52 50 gnd 2.080806f
+R50 49 50 2.224404
+R51 50 g7530_1 2.224404
+.ends
+
+.subckt netg149 g149_1 g149_0 gnd
+C1  g149_1 gnd 2.080806f
+C2  g149_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g149_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+C50 48 gnd 2.080806f
+R48 47 48 2.224404
+C51 49 gnd 2.080806f
+R49 48 49 2.224404
+C52 50 gnd 2.080806f
+R50 49 50 2.224404
+R51 50 g149_1 2.224404
+.ends
+
+.subckt netg7542 g7542_1 g7542_0 gnd
+C1  g7542_1 gnd 2.080806f
+C2  g7542_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7542_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+C50 48 gnd 2.080806f
+R48 47 48 2.224404
+C51 49 gnd 2.080806f
+R49 48 49 2.224404
+C52 50 gnd 2.080806f
+R50 49 50 2.224404
+R51 50 g7542_1 2.224404
+.ends
+
+.subckt netg189 g189_0 g189_2 g189_1 gnd
+C1  g189_0 gnd 2.080806f
+C2  g189_2 gnd 2.080806f
+C3  g189_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g189_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g189_2 3 2.224404
+C7 4 gnd 2.080806f
+R5 g189_0 4 2.224404
+C8 5 gnd 2.080806f
+R6 4 5 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+C10 7 gnd 2.080806f
+R8 6 7 2.224404
+C11 8 gnd 2.080806f
+R9 7 8 2.224404
+C12 9 gnd 2.080806f
+R10 8 9 2.224404
+C13 10 gnd 2.080806f
+R11 9 10 2.224404
+C14 11 gnd 2.080806f
+R12 10 11 2.224404
+C15 12 gnd 2.080806f
+R13 11 12 2.224404
+C16 13 gnd 2.080806f
+R14 12 13 2.224404
+C17 14 gnd 2.080806f
+R15 13 14 2.224404
+C18 15 gnd 2.080806f
+R16 14 15 2.224404
+C19 16 gnd 2.080806f
+R17 15 16 2.224404
+C20 17 gnd 2.080806f
+R18 16 17 2.224404
+C21 18 gnd 2.080806f
+R19 17 18 2.224404
+C22 19 gnd 2.080806f
+R20 18 19 2.224404
+C23 20 gnd 2.080806f
+R21 19 20 2.224404
+C24 21 gnd 2.080806f
+R22 20 21 2.224404
+C25 22 gnd 2.080806f
+R23 21 22 2.224404
+C26 23 gnd 2.080806f
+R24 22 23 2.224404
+C27 24 gnd 2.080806f
+R25 23 24 2.224404
+C28 25 gnd 2.080806f
+R26 24 25 2.224404
+C29 26 gnd 2.080806f
+R27 25 26 2.224404
+C30 27 gnd 2.080806f
+R28 26 27 2.224404
+C31 28 gnd 2.080806f
+R29 27 28 2.224404
+C32 29 gnd 2.080806f
+R30 28 29 2.224404
+C33 30 gnd 2.080806f
+R31 29 30 2.224404
+C34 31 gnd 2.080806f
+R32 30 31 2.224404
+C35 32 gnd 2.080806f
+R33 31 32 2.224404
+C36 33 gnd 2.080806f
+R34 32 33 2.224404
+C37 34 gnd 2.080806f
+R35 33 34 2.224404
+C38 35 gnd 2.080806f
+R36 34 35 2.224404
+C39 36 gnd 2.080806f
+R37 35 36 2.224404
+C40 37 gnd 2.080806f
+R38 36 37 2.224404
+C41 38 gnd 2.080806f
+R39 37 38 2.224404
+C42 39 gnd 2.080806f
+R40 38 39 2.224404
+C43 40 gnd 2.080806f
+R41 39 40 2.224404
+C44 41 gnd 2.080806f
+R42 40 41 2.224404
+C45 42 gnd 2.080806f
+R43 41 42 2.224404
+C46 43 gnd 2.080806f
+R44 42 43 2.224404
+C47 44 gnd 2.080806f
+R45 43 44 2.224404
+C48 45 gnd 2.080806f
+R46 44 45 2.224404
+C49 46 gnd 2.080806f
+R47 45 46 2.224404
+C50 47 gnd 2.080806f
+R48 46 47 2.224404
+C51 48 gnd 2.080806f
+R49 47 48 2.224404
+C52 49 gnd 2.080806f
+R50 48 49 2.224404
+R51 49 g189_1 2.224404
+.ends
+
+.subckt netg7462 g7462_0 g7462_1 gnd
+C1  g7462_0 gnd 2.080806f
+C2  g7462_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7462_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+C50 48 gnd 2.080806f
+R48 47 48 2.224404
+C51 49 gnd 2.080806f
+R49 48 49 2.224404
+C52 50 gnd 2.080806f
+R50 50 49 2.224404
+R51 g7462_1 50 2.224404
+.ends
+
+.subckt netg119 g119_1 g119_0 gnd
+C1  g119_1 gnd 2.080806f
+C2  g119_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g119_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+C50 48 gnd 2.080806f
+R48 47 48 2.224404
+C51 49 gnd 2.080806f
+R49 48 49 2.224404
+C52 50 gnd 2.080806f
+R50 49 50 2.224404
+R51 50 g119_1 2.224404
+.ends
+
+.subckt netg7487 g7487_1 g7487_0 gnd
+C1  g7487_1 gnd 2.080806f
+C2  g7487_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7487_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+C50 48 gnd 2.080806f
+R48 47 48 2.224404
+C51 49 gnd 2.080806f
+R49 49 48 2.224404
+C52 50 gnd 2.080806f
+R50 49 50 2.224404
+C53 51 gnd 2.080806f
+R51 51 50 2.224404
+R52 g7487_1 51 2.224404
+.ends
+
+.subckt netg159 g159_0 g159_1 gnd
+C1  g159_0 gnd 2.080806f
+C2  g159_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g159_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+C50 48 gnd 2.080806f
+R48 48 47 2.224404
+C51 49 gnd 2.080806f
+R49 49 48 2.224404
+C52 50 gnd 2.080806f
+R50 50 49 2.224404
+C53 51 gnd 2.080806f
+R51 51 50 2.224404
+R52 g159_1 51 2.224404
+.ends
+
+.subckt netg163 g163_0 g163_1 gnd
+C1  g163_0 gnd 2.080806f
+C2  g163_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g163_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+C50 48 gnd 2.080806f
+R48 47 48 2.224404
+C51 49 gnd 2.080806f
+R49 48 49 2.224404
+C52 50 gnd 2.080806f
+R50 49 50 2.224404
+C53 51 gnd 2.080806f
+R51 50 51 2.224404
+R52 51 g163_1 2.224404
+.ends
+
+.subckt netg170 g170_1 g170_2 gnd
+C1  g170_1 gnd 2.080806f
+C2  g170_2 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g170_2 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+C50 48 gnd 2.080806f
+R48 47 48 2.224404
+C51 49 gnd 2.080806f
+R49 48 49 2.224404
+C52 50 gnd 2.080806f
+R50 49 50 2.224404
+C53 51 gnd 2.080806f
+R51 50 51 2.224404
+C54 52 gnd 2.080806f
+R52 51 52 2.224404
+R53 52 g170_1 2.224404
+.ends
+
+.subckt netg7485 g7485_0 g7485_1 gnd
+C1  g7485_0 gnd 2.080806f
+C2  g7485_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7485_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+C50 48 gnd 2.080806f
+R48 47 48 2.224404
+C51 49 gnd 2.080806f
+R49 48 49 2.224404
+C52 50 gnd 2.080806f
+R50 50 49 2.224404
+C53 51 gnd 2.080806f
+R51 50 51 2.224404
+C54 52 gnd 2.080806f
+R52 52 51 2.224404
+R53 g7485_1 52 2.224404
+.ends
+
+.subckt netg7472 g7472_1 g7472_0 gnd
+C1  g7472_1 gnd 2.080806f
+C2  g7472_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7472_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+C50 48 gnd 2.080806f
+R48 48 47 2.224404
+C51 49 gnd 2.080806f
+R49 48 49 2.224404
+C52 50 gnd 2.080806f
+R50 50 49 2.224404
+C53 51 gnd 2.080806f
+R51 50 51 2.224404
+C54 52 gnd 2.080806f
+R52 52 51 2.224404
+R53 g7472_1 52 2.224404
+.ends
+
+.subckt netg7488 g7488_1 g7488_0 gnd
+C1  g7488_1 gnd 2.080806f
+C2  g7488_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7488_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+C50 48 gnd 2.080806f
+R48 47 48 2.224404
+C51 49 gnd 2.080806f
+R49 48 49 2.224404
+C52 50 gnd 2.080806f
+R50 50 49 2.224404
+C53 51 gnd 2.080806f
+R51 50 51 2.224404
+C54 52 gnd 2.080806f
+R52 52 51 2.224404
+R53 g7488_1 52 2.224404
+.ends
+
+.subckt netg7480 g7480_0 g7480_1 gnd
+C1  g7480_0 gnd 2.080806f
+C2  g7480_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7480_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+C50 48 gnd 2.080806f
+R48 47 48 2.224404
+C51 49 gnd 2.080806f
+R49 48 49 2.224404
+C52 50 gnd 2.080806f
+R50 50 49 2.224404
+C53 51 gnd 2.080806f
+R51 50 51 2.224404
+C54 52 gnd 2.080806f
+R52 52 51 2.224404
+R53 g7480_1 52 2.224404
+.ends
+
+.subckt netg51 g51_2 g51_1 g51_0 gnd
+C1  g51_2 gnd 2.080806f
+C2  g51_1 gnd 2.080806f
+C3  g51_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g51_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g51_1 2 2.224404
+C6 3 gnd 2.080806f
+R4 3 g51_0 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 11 10 2.224404
+C15 12 gnd 2.080806f
+R13 12 11 2.224404
+C16 13 gnd 2.080806f
+R14 13 12 2.224404
+C17 14 gnd 2.080806f
+R15 14 13 2.224404
+C18 15 gnd 2.080806f
+R16 15 14 2.224404
+C19 16 gnd 2.080806f
+R17 16 15 2.224404
+C20 17 gnd 2.080806f
+R18 17 16 2.224404
+C21 18 gnd 2.080806f
+R19 18 17 2.224404
+C22 19 gnd 2.080806f
+R20 19 18 2.224404
+C23 20 gnd 2.080806f
+R21 20 19 2.224404
+C24 21 gnd 2.080806f
+R22 21 20 2.224404
+C25 22 gnd 2.080806f
+R23 22 21 2.224404
+C26 23 gnd 2.080806f
+R24 23 22 2.224404
+C27 24 gnd 2.080806f
+R25 24 23 2.224404
+C28 25 gnd 2.080806f
+R26 25 24 2.224404
+C29 26 gnd 2.080806f
+R27 26 25 2.224404
+C30 27 gnd 2.080806f
+R28 27 26 2.224404
+C31 28 gnd 2.080806f
+R29 28 27 2.224404
+C32 29 gnd 2.080806f
+R30 29 28 2.224404
+C33 30 gnd 2.080806f
+R31 30 29 2.224404
+C34 31 gnd 2.080806f
+R32 31 30 2.224404
+C35 32 gnd 2.080806f
+R33 32 31 2.224404
+C36 33 gnd 2.080806f
+R34 33 32 2.224404
+C37 34 gnd 2.080806f
+R35 34 33 2.224404
+C38 35 gnd 2.080806f
+R36 35 34 2.224404
+C39 36 gnd 2.080806f
+R37 36 35 2.224404
+C40 37 gnd 2.080806f
+R38 37 36 2.224404
+C41 38 gnd 2.080806f
+R39 38 37 2.224404
+C42 39 gnd 2.080806f
+R40 39 38 2.224404
+C43 40 gnd 2.080806f
+R41 40 39 2.224404
+C44 41 gnd 2.080806f
+R42 41 40 2.224404
+C45 42 gnd 2.080806f
+R43 42 41 2.224404
+C46 43 gnd 2.080806f
+R44 43 42 2.224404
+C47 44 gnd 2.080806f
+R45 44 43 2.224404
+C48 45 gnd 2.080806f
+R46 45 44 2.224404
+C49 46 gnd 2.080806f
+R47 46 45 2.224404
+C50 47 gnd 2.080806f
+R48 47 46 2.224404
+C51 48 gnd 2.080806f
+R49 48 47 2.224404
+C52 49 gnd 2.080806f
+R50 49 48 2.224404
+C53 50 gnd 2.080806f
+R51 50 49 2.224404
+C54 51 gnd 2.080806f
+R52 51 50 2.224404
+C55 52 gnd 2.080806f
+R53 52 51 2.224404
+R54 g51_2 52 2.224404
+.ends
+
+.subckt netg7477 g7477_0 g7477_1 gnd
+C1  g7477_0 gnd 2.080806f
+C2  g7477_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7477_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+C50 48 gnd 2.080806f
+R48 47 48 2.224404
+C51 49 gnd 2.080806f
+R49 48 49 2.224404
+C52 50 gnd 2.080806f
+R50 50 49 2.224404
+C53 51 gnd 2.080806f
+R51 50 51 2.224404
+C54 52 gnd 2.080806f
+R52 52 51 2.224404
+R53 g7477_1 52 2.224404
+.ends
+
+.subckt netg2141 g2141_3 g2141_2 g2141_0 g2141_1 g2141_4 g2141_5 gnd
+C1  g2141_3 gnd 2.080806f
+C2  g2141_2 gnd 2.080806f
+C3  g2141_0 gnd 2.080806f
+C4  g2141_1 gnd 2.080806f
+C5  g2141_4 gnd 2.080806f
+C6  g2141_5 gnd 2.080806f
+R1 g2141_4 g2141_0 2.224404
+C7 1 gnd 2.080806f
+R2 1 g2141_4 2.224404
+C8 2 gnd 2.080806f
+R3 2 1 2.224404
+C9 3 gnd 2.080806f
+R4 3 2 2.224404
+C10 4 gnd 2.080806f
+R5 4 3 2.224404
+C11 5 gnd 2.080806f
+R6 5 4 2.224404
+R7 g2141_5 5 2.224404
+R8 g2141_3 g2141_5 2.224404
+C12 6 gnd 2.080806f
+R9 g2141_0 6 2.224404
+C13 7 gnd 2.080806f
+R10 6 7 2.224404
+C14 8 gnd 2.080806f
+R11 7 8 2.224404
+C15 9 gnd 2.080806f
+R12 8 9 2.224404
+C16 10 gnd 2.080806f
+R13 9 10 2.224404
+C17 11 gnd 2.080806f
+R14 10 11 2.224404
+C18 12 gnd 2.080806f
+R15 12 11 2.224404
+C19 13 gnd 2.080806f
+R16 12 13 2.224404
+C20 14 gnd 2.080806f
+R17 13 14 2.224404
+C21 15 gnd 2.080806f
+R18 14 15 2.224404
+C22 16 gnd 2.080806f
+R19 15 16 2.224404
+C23 17 gnd 2.080806f
+R20 16 17 2.224404
+C24 18 gnd 2.080806f
+R21 17 18 2.224404
+C25 19 gnd 2.080806f
+R22 18 19 2.224404
+C26 20 gnd 2.080806f
+R23 19 20 2.224404
+C27 21 gnd 2.080806f
+R24 20 21 2.224404
+C28 22 gnd 2.080806f
+R25 21 22 2.224404
+C29 23 gnd 2.080806f
+R26 22 23 2.224404
+C30 24 gnd 2.080806f
+R27 23 24 2.224404
+C31 25 gnd 2.080806f
+R28 24 25 2.224404
+C32 26 gnd 2.080806f
+R29 25 26 2.224404
+C33 27 gnd 2.080806f
+R30 26 27 2.224404
+C34 28 gnd 2.080806f
+R31 27 28 2.224404
+C35 29 gnd 2.080806f
+R32 28 29 2.224404
+C36 30 gnd 2.080806f
+R33 29 30 2.224404
+C37 31 gnd 2.080806f
+R34 30 31 2.224404
+C38 32 gnd 2.080806f
+R35 31 32 2.224404
+C39 33 gnd 2.080806f
+R36 32 33 2.224404
+C40 34 gnd 2.080806f
+R37 33 34 2.224404
+C41 35 gnd 2.080806f
+R38 34 35 2.224404
+C42 36 gnd 2.080806f
+R39 36 35 2.224404
+C43 37 gnd 2.080806f
+R40 36 37 2.224404
+C44 38 gnd 2.080806f
+R41 37 38 2.224404
+C45 39 gnd 2.080806f
+R42 38 39 2.224404
+C46 40 gnd 2.080806f
+R43 40 39 2.224404
+C47 41 gnd 2.080806f
+R44 40 41 2.224404
+C48 42 gnd 2.080806f
+R45 41 42 2.224404
+R46 42 g2141_1 2.224404
+C49 43 gnd 2.080806f
+R47 43 g2141_1 2.224404
+C50 44 gnd 2.080806f
+R48 43 44 2.224404
+C51 45 gnd 2.080806f
+R49 44 45 2.224404
+C52 46 gnd 2.080806f
+R50 45 46 2.224404
+C53 47 gnd 2.080806f
+R51 46 47 2.224404
+C54 48 gnd 2.080806f
+R52 47 48 2.224404
+C55 49 gnd 2.080806f
+R53 48 49 2.224404
+C56 50 gnd 2.080806f
+R54 49 50 2.224404
+C57 51 gnd 2.080806f
+R55 51 50 2.224404
+C58 52 gnd 2.080806f
+R56 51 52 2.224404
+C59 53 gnd 2.080806f
+R57 52 53 2.224404
+C60 54 gnd 2.080806f
+R58 53 54 2.224404
+C61 55 gnd 2.080806f
+R59 54 55 2.224404
+C62 56 gnd 2.080806f
+R60 55 56 2.224404
+R61 g2141_2 56 2.224404
+.ends
+
+.subckt netg162 g162_1 g162_0 gnd
+C1  g162_1 gnd 2.080806f
+C2  g162_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g162_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+C50 48 gnd 2.080806f
+R48 48 47 2.224404
+C51 49 gnd 2.080806f
+R49 49 48 2.224404
+C52 50 gnd 2.080806f
+R50 50 49 2.224404
+C53 51 gnd 2.080806f
+R51 51 50 2.224404
+C54 52 gnd 2.080806f
+R52 52 51 2.224404
+R53 g162_1 52 2.224404
+.ends
+
+.subckt netg193 g193_1 g193_2 g193_0 gnd
+C1  g193_1 gnd 2.080806f
+C2  g193_2 gnd 2.080806f
+C3  g193_0 gnd 2.080806f
+R1 g193_1 g193_0 2.224404
+C4 1 gnd 2.080806f
+R2 g193_0 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+C8 5 gnd 2.080806f
+R6 4 5 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+C10 7 gnd 2.080806f
+R8 6 7 2.224404
+C11 8 gnd 2.080806f
+R9 7 8 2.224404
+C12 9 gnd 2.080806f
+R10 8 9 2.224404
+C13 10 gnd 2.080806f
+R11 9 10 2.224404
+C14 11 gnd 2.080806f
+R12 10 11 2.224404
+C15 12 gnd 2.080806f
+R13 11 12 2.224404
+C16 13 gnd 2.080806f
+R14 12 13 2.224404
+C17 14 gnd 2.080806f
+R15 13 14 2.224404
+C18 15 gnd 2.080806f
+R16 14 15 2.224404
+C19 16 gnd 2.080806f
+R17 15 16 2.224404
+C20 17 gnd 2.080806f
+R18 16 17 2.224404
+C21 18 gnd 2.080806f
+R19 17 18 2.224404
+C22 19 gnd 2.080806f
+R20 18 19 2.224404
+C23 20 gnd 2.080806f
+R21 19 20 2.224404
+C24 21 gnd 2.080806f
+R22 20 21 2.224404
+C25 22 gnd 2.080806f
+R23 21 22 2.224404
+C26 23 gnd 2.080806f
+R24 22 23 2.224404
+C27 24 gnd 2.080806f
+R25 23 24 2.224404
+C28 25 gnd 2.080806f
+R26 24 25 2.224404
+C29 26 gnd 2.080806f
+R27 25 26 2.224404
+C30 27 gnd 2.080806f
+R28 26 27 2.224404
+C31 28 gnd 2.080806f
+R29 27 28 2.224404
+C32 29 gnd 2.080806f
+R30 28 29 2.224404
+C33 30 gnd 2.080806f
+R31 29 30 2.224404
+C34 31 gnd 2.080806f
+R32 30 31 2.224404
+C35 32 gnd 2.080806f
+R33 31 32 2.224404
+C36 33 gnd 2.080806f
+R34 32 33 2.224404
+C37 34 gnd 2.080806f
+R35 33 34 2.224404
+C38 35 gnd 2.080806f
+R36 34 35 2.224404
+C39 36 gnd 2.080806f
+R37 35 36 2.224404
+C40 37 gnd 2.080806f
+R38 36 37 2.224404
+C41 38 gnd 2.080806f
+R39 37 38 2.224404
+C42 39 gnd 2.080806f
+R40 38 39 2.224404
+C43 40 gnd 2.080806f
+R41 39 40 2.224404
+C44 41 gnd 2.080806f
+R42 40 41 2.224404
+C45 42 gnd 2.080806f
+R43 41 42 2.224404
+C46 43 gnd 2.080806f
+R44 42 43 2.224404
+C47 44 gnd 2.080806f
+R45 43 44 2.224404
+C48 45 gnd 2.080806f
+R46 44 45 2.224404
+C49 46 gnd 2.080806f
+R47 45 46 2.224404
+C50 47 gnd 2.080806f
+R48 46 47 2.224404
+C51 48 gnd 2.080806f
+R49 47 48 2.224404
+C52 49 gnd 2.080806f
+R50 48 49 2.224404
+C53 50 gnd 2.080806f
+R51 49 50 2.224404
+C54 51 gnd 2.080806f
+R52 50 51 2.224404
+C55 52 gnd 2.080806f
+R53 51 52 2.224404
+R54 52 g193_2 2.224404
+.ends
+
+.subckt netg151 g151_0 g151_1 gnd
+C1  g151_0 gnd 2.080806f
+C2  g151_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g151_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+C50 48 gnd 2.080806f
+R48 48 47 2.224404
+C51 49 gnd 2.080806f
+R49 49 48 2.224404
+C52 50 gnd 2.080806f
+R50 50 49 2.224404
+C53 51 gnd 2.080806f
+R51 51 50 2.224404
+C54 52 gnd 2.080806f
+R52 52 51 2.224404
+C55 53 gnd 2.080806f
+R53 53 52 2.224404
+R54 g151_1 53 2.224404
+.ends
+
+.subckt netg161 g161_0 g161_1 gnd
+C1  g161_0 gnd 2.080806f
+C2  g161_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g161_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+C50 48 gnd 2.080806f
+R48 47 48 2.224404
+C51 49 gnd 2.080806f
+R49 48 49 2.224404
+C52 50 gnd 2.080806f
+R50 49 50 2.224404
+C53 51 gnd 2.080806f
+R51 50 51 2.224404
+C54 52 gnd 2.080806f
+R52 51 52 2.224404
+C55 53 gnd 2.080806f
+R53 52 53 2.224404
+R54 53 g161_1 2.224404
+.ends
+
+.subckt netg155 g155_1 g155_0 gnd
+C1  g155_1 gnd 2.080806f
+C2  g155_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g155_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+C50 48 gnd 2.080806f
+R48 48 47 2.224404
+C51 49 gnd 2.080806f
+R49 49 48 2.224404
+C52 50 gnd 2.080806f
+R50 50 49 2.224404
+C53 51 gnd 2.080806f
+R51 51 50 2.224404
+C54 52 gnd 2.080806f
+R52 52 51 2.224404
+C55 53 gnd 2.080806f
+R53 53 52 2.224404
+C56 54 gnd 2.080806f
+R54 54 53 2.224404
+C57 55 gnd 2.080806f
+R55 55 54 2.224404
+R56 g155_1 55 2.224404
+.ends
+
+.subckt netg171 g171_2 g171_0 g171_1 gnd
+C1  g171_2 gnd 2.080806f
+C2  g171_0 gnd 2.080806f
+C3  g171_1 gnd 2.080806f
+R1 g171_0 g171_1 2.224404
+C4 1 gnd 2.080806f
+R2 g171_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+C8 5 gnd 2.080806f
+R6 4 5 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+C10 7 gnd 2.080806f
+R8 6 7 2.224404
+C11 8 gnd 2.080806f
+R9 7 8 2.224404
+C12 9 gnd 2.080806f
+R10 8 9 2.224404
+C13 10 gnd 2.080806f
+R11 9 10 2.224404
+C14 11 gnd 2.080806f
+R12 10 11 2.224404
+C15 12 gnd 2.080806f
+R13 11 12 2.224404
+C16 13 gnd 2.080806f
+R14 12 13 2.224404
+C17 14 gnd 2.080806f
+R15 13 14 2.224404
+C18 15 gnd 2.080806f
+R16 14 15 2.224404
+C19 16 gnd 2.080806f
+R17 15 16 2.224404
+C20 17 gnd 2.080806f
+R18 16 17 2.224404
+C21 18 gnd 2.080806f
+R19 17 18 2.224404
+C22 19 gnd 2.080806f
+R20 18 19 2.224404
+C23 20 gnd 2.080806f
+R21 19 20 2.224404
+C24 21 gnd 2.080806f
+R22 20 21 2.224404
+C25 22 gnd 2.080806f
+R23 21 22 2.224404
+C26 23 gnd 2.080806f
+R24 22 23 2.224404
+C27 24 gnd 2.080806f
+R25 23 24 2.224404
+C28 25 gnd 2.080806f
+R26 24 25 2.224404
+C29 26 gnd 2.080806f
+R27 25 26 2.224404
+C30 27 gnd 2.080806f
+R28 26 27 2.224404
+C31 28 gnd 2.080806f
+R29 27 28 2.224404
+C32 29 gnd 2.080806f
+R30 28 29 2.224404
+C33 30 gnd 2.080806f
+R31 29 30 2.224404
+C34 31 gnd 2.080806f
+R32 30 31 2.224404
+C35 32 gnd 2.080806f
+R33 31 32 2.224404
+C36 33 gnd 2.080806f
+R34 32 33 2.224404
+C37 34 gnd 2.080806f
+R35 33 34 2.224404
+C38 35 gnd 2.080806f
+R36 34 35 2.224404
+C39 36 gnd 2.080806f
+R37 35 36 2.224404
+C40 37 gnd 2.080806f
+R38 36 37 2.224404
+C41 38 gnd 2.080806f
+R39 37 38 2.224404
+C42 39 gnd 2.080806f
+R40 38 39 2.224404
+C43 40 gnd 2.080806f
+R41 39 40 2.224404
+C44 41 gnd 2.080806f
+R42 40 41 2.224404
+C45 42 gnd 2.080806f
+R43 41 42 2.224404
+C46 43 gnd 2.080806f
+R44 42 43 2.224404
+C47 44 gnd 2.080806f
+R45 43 44 2.224404
+C48 45 gnd 2.080806f
+R46 44 45 2.224404
+C49 46 gnd 2.080806f
+R47 45 46 2.224404
+C50 47 gnd 2.080806f
+R48 46 47 2.224404
+C51 48 gnd 2.080806f
+R49 47 48 2.224404
+C52 49 gnd 2.080806f
+R50 48 49 2.224404
+C53 50 gnd 2.080806f
+R51 49 50 2.224404
+C54 51 gnd 2.080806f
+R52 50 51 2.224404
+C55 52 gnd 2.080806f
+R53 51 52 2.224404
+R54 52 g171_2 2.224404
+.ends
+
+.subckt netg153 g153_1 g153_0 gnd
+C1  g153_1 gnd 2.080806f
+C2  g153_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g153_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+C50 48 gnd 2.080806f
+R48 47 48 2.224404
+C51 49 gnd 2.080806f
+R49 48 49 2.224404
+C52 50 gnd 2.080806f
+R50 49 50 2.224404
+C53 51 gnd 2.080806f
+R51 50 51 2.224404
+C54 52 gnd 2.080806f
+R52 51 52 2.224404
+C55 53 gnd 2.080806f
+R53 52 53 2.224404
+R54 53 g153_1 2.224404
+.ends
+
+.subckt netg150 g150_1 g150_0 gnd
+C1  g150_1 gnd 2.080806f
+C2  g150_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g150_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+C50 48 gnd 2.080806f
+R48 47 48 2.224404
+C51 49 gnd 2.080806f
+R49 48 49 2.224404
+C52 50 gnd 2.080806f
+R50 49 50 2.224404
+C53 51 gnd 2.080806f
+R51 50 51 2.224404
+C54 52 gnd 2.080806f
+R52 51 52 2.224404
+C55 53 gnd 2.080806f
+R53 52 53 2.224404
+C56 54 gnd 2.080806f
+R54 53 54 2.224404
+C57 55 gnd 2.080806f
+R55 54 55 2.224404
+R56 55 g150_1 2.224404
+.ends
+
+.subckt netg7516 g7516_1 g7516_0 gnd
+C1  g7516_1 gnd 2.080806f
+C2  g7516_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7516_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+C50 48 gnd 2.080806f
+R48 48 47 2.224404
+C51 49 gnd 2.080806f
+R49 49 48 2.224404
+C52 50 gnd 2.080806f
+R50 50 49 2.224404
+C53 51 gnd 2.080806f
+R51 51 50 2.224404
+C54 52 gnd 2.080806f
+R52 52 51 2.224404
+C55 53 gnd 2.080806f
+R53 53 52 2.224404
+R54 g7516_1 53 2.224404
+.ends
+
+.subckt netg7479 g7479_0 g7479_1 gnd
+C1  g7479_0 gnd 2.080806f
+C2  g7479_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7479_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+C50 48 gnd 2.080806f
+R48 47 48 2.224404
+C51 49 gnd 2.080806f
+R49 48 49 2.224404
+C52 50 gnd 2.080806f
+R50 49 50 2.224404
+C53 51 gnd 2.080806f
+R51 50 51 2.224404
+C54 52 gnd 2.080806f
+R52 52 51 2.224404
+C55 53 gnd 2.080806f
+R53 52 53 2.224404
+C56 54 gnd 2.080806f
+R54 54 53 2.224404
+R55 g7479_1 54 2.224404
+.ends
+
+.subckt netg188 g188_1 g188_0 g188_2 gnd
+C1  g188_1 gnd 2.080806f
+C2  g188_0 gnd 2.080806f
+C3  g188_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g188_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 g188_1 4 2.224404
+C8 5 gnd 2.080806f
+R6 g188_0 5 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+C10 7 gnd 2.080806f
+R8 6 7 2.224404
+C11 8 gnd 2.080806f
+R9 7 8 2.224404
+C12 9 gnd 2.080806f
+R10 8 9 2.224404
+C13 10 gnd 2.080806f
+R11 9 10 2.224404
+C14 11 gnd 2.080806f
+R12 10 11 2.224404
+C15 12 gnd 2.080806f
+R13 11 12 2.224404
+C16 13 gnd 2.080806f
+R14 12 13 2.224404
+C17 14 gnd 2.080806f
+R15 13 14 2.224404
+C18 15 gnd 2.080806f
+R16 14 15 2.224404
+C19 16 gnd 2.080806f
+R17 15 16 2.224404
+C20 17 gnd 2.080806f
+R18 16 17 2.224404
+C21 18 gnd 2.080806f
+R19 17 18 2.224404
+C22 19 gnd 2.080806f
+R20 18 19 2.224404
+C23 20 gnd 2.080806f
+R21 19 20 2.224404
+C24 21 gnd 2.080806f
+R22 20 21 2.224404
+C25 22 gnd 2.080806f
+R23 21 22 2.224404
+C26 23 gnd 2.080806f
+R24 22 23 2.224404
+C27 24 gnd 2.080806f
+R25 23 24 2.224404
+C28 25 gnd 2.080806f
+R26 24 25 2.224404
+C29 26 gnd 2.080806f
+R27 25 26 2.224404
+C30 27 gnd 2.080806f
+R28 26 27 2.224404
+C31 28 gnd 2.080806f
+R29 28 27 2.224404
+C32 29 gnd 2.080806f
+R30 28 29 2.224404
+C33 30 gnd 2.080806f
+R31 29 30 2.224404
+C34 31 gnd 2.080806f
+R32 30 31 2.224404
+C35 32 gnd 2.080806f
+R33 31 32 2.224404
+C36 33 gnd 2.080806f
+R34 32 33 2.224404
+C37 34 gnd 2.080806f
+R35 33 34 2.224404
+C38 35 gnd 2.080806f
+R36 34 35 2.224404
+C39 36 gnd 2.080806f
+R37 35 36 2.224404
+C40 37 gnd 2.080806f
+R38 36 37 2.224404
+C41 38 gnd 2.080806f
+R39 37 38 2.224404
+C42 39 gnd 2.080806f
+R40 38 39 2.224404
+C43 40 gnd 2.080806f
+R41 39 40 2.224404
+C44 41 gnd 2.080806f
+R42 40 41 2.224404
+C45 42 gnd 2.080806f
+R43 41 42 2.224404
+C46 43 gnd 2.080806f
+R44 42 43 2.224404
+C47 44 gnd 2.080806f
+R45 43 44 2.224404
+C48 45 gnd 2.080806f
+R46 44 45 2.224404
+C49 46 gnd 2.080806f
+R47 45 46 2.224404
+C50 47 gnd 2.080806f
+R48 46 47 2.224404
+C51 48 gnd 2.080806f
+R49 47 48 2.224404
+C52 49 gnd 2.080806f
+R50 48 49 2.224404
+C53 50 gnd 2.080806f
+R51 49 50 2.224404
+C54 51 gnd 2.080806f
+R52 50 51 2.224404
+C55 52 gnd 2.080806f
+R53 51 52 2.224404
+C56 53 gnd 2.080806f
+R54 52 53 2.224404
+C57 54 gnd 2.080806f
+R55 53 54 2.224404
+C58 55 gnd 2.080806f
+R56 54 55 2.224404
+R57 55 g188_2 2.224404
+.ends
+
+.subckt netg526 g526_5 g526_3 g526_0 g526_4 g526_1 g526_2 gnd
+C1  g526_5 gnd 2.080806f
+C2  g526_3 gnd 2.080806f
+C3  g526_0 gnd 2.080806f
+C4  g526_4 gnd 2.080806f
+C5  g526_1 gnd 2.080806f
+C6  g526_2 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g526_0 2.224404
+C8 2 gnd 2.080806f
+R2 2 1 2.224404
+C9 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g526_3 3 2.224404
+C10 4 gnd 2.080806f
+R5 g526_3 4 2.224404
+R6 4 g526_5 2.224404
+C11 5 gnd 2.080806f
+R7 g526_0 5 2.224404
+C12 6 gnd 2.080806f
+R8 5 6 2.224404
+C13 7 gnd 2.080806f
+R9 6 7 2.224404
+C14 8 gnd 2.080806f
+R10 7 8 2.224404
+C15 9 gnd 2.080806f
+R11 8 9 2.224404
+C16 10 gnd 2.080806f
+R12 9 10 2.224404
+C17 11 gnd 2.080806f
+R13 10 11 2.224404
+C18 12 gnd 2.080806f
+R14 11 12 2.224404
+C19 13 gnd 2.080806f
+R15 12 13 2.224404
+C20 14 gnd 2.080806f
+R16 13 14 2.224404
+C21 15 gnd 2.080806f
+R17 14 15 2.224404
+C22 16 gnd 2.080806f
+R18 15 16 2.224404
+C23 17 gnd 2.080806f
+R19 16 17 2.224404
+C24 18 gnd 2.080806f
+R20 17 18 2.224404
+C25 19 gnd 2.080806f
+R21 18 19 2.224404
+C26 20 gnd 2.080806f
+R22 19 20 2.224404
+C27 21 gnd 2.080806f
+R23 20 21 2.224404
+R24 21 g526_1 2.224404
+C28 22 gnd 2.080806f
+R25 22 g526_1 2.224404
+C29 23 gnd 2.080806f
+R26 22 23 2.224404
+C30 24 gnd 2.080806f
+R27 23 24 2.224404
+C31 25 gnd 2.080806f
+R28 24 25 2.224404
+C32 26 gnd 2.080806f
+R29 25 26 2.224404
+C33 27 gnd 2.080806f
+R30 26 27 2.224404
+C34 28 gnd 2.080806f
+R31 27 28 2.224404
+C35 29 gnd 2.080806f
+R32 28 29 2.224404
+C36 30 gnd 2.080806f
+R33 29 30 2.224404
+C37 31 gnd 2.080806f
+R34 30 31 2.224404
+C38 32 gnd 2.080806f
+R35 31 32 2.224404
+C39 33 gnd 2.080806f
+R36 32 33 2.224404
+C40 34 gnd 2.080806f
+R37 33 34 2.224404
+C41 35 gnd 2.080806f
+R38 34 35 2.224404
+C42 36 gnd 2.080806f
+R39 35 36 2.224404
+C43 37 gnd 2.080806f
+R40 36 37 2.224404
+C44 38 gnd 2.080806f
+R41 37 38 2.224404
+C45 39 gnd 2.080806f
+R42 39 38 2.224404
+C46 40 gnd 2.080806f
+R43 39 40 2.224404
+C47 41 gnd 2.080806f
+R44 40 41 2.224404
+R45 41 g526_2 2.224404
+C48 42 gnd 2.080806f
+R46 g526_1 42 2.224404
+C49 43 gnd 2.080806f
+R47 42 43 2.224404
+C50 44 gnd 2.080806f
+R48 43 44 2.224404
+C51 45 gnd 2.080806f
+R49 44 45 2.224404
+C52 46 gnd 2.080806f
+R50 45 46 2.224404
+C53 47 gnd 2.080806f
+R51 46 47 2.224404
+C54 48 gnd 2.080806f
+R52 47 48 2.224404
+C55 49 gnd 2.080806f
+R53 48 49 2.224404
+C56 50 gnd 2.080806f
+R54 49 50 2.224404
+C57 51 gnd 2.080806f
+R55 50 51 2.224404
+C58 52 gnd 2.080806f
+R56 51 52 2.224404
+C59 53 gnd 2.080806f
+R57 52 53 2.224404
+C60 54 gnd 2.080806f
+R58 53 54 2.224404
+C61 55 gnd 2.080806f
+R59 54 55 2.224404
+C62 56 gnd 2.080806f
+R60 55 56 2.224404
+C63 57 gnd 2.080806f
+R61 56 57 2.224404
+C64 58 gnd 2.080806f
+R62 57 58 2.224404
+C65 59 gnd 2.080806f
+R63 58 59 2.224404
+C66 60 gnd 2.080806f
+R64 59 60 2.224404
+C67 61 gnd 2.080806f
+R65 60 61 2.224404
+C68 62 gnd 2.080806f
+R66 61 62 2.224404
+C69 63 gnd 2.080806f
+R67 62 63 2.224404
+C70 64 gnd 2.080806f
+R68 63 64 2.224404
+R69 64 g526_4 2.224404
+.ends
+
+.subckt netg7473 g7473_0 g7473_1 gnd
+C1  g7473_0 gnd 2.080806f
+C2  g7473_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7473_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+C50 48 gnd 2.080806f
+R48 48 47 2.224404
+C51 49 gnd 2.080806f
+R49 49 48 2.224404
+C52 50 gnd 2.080806f
+R50 50 49 2.224404
+C53 51 gnd 2.080806f
+R51 50 51 2.224404
+C54 52 gnd 2.080806f
+R52 51 52 2.224404
+C55 53 gnd 2.080806f
+R53 53 52 2.224404
+C56 54 gnd 2.080806f
+R54 53 54 2.224404
+C57 55 gnd 2.080806f
+R55 54 55 2.224404
+R56 55 g7473_1 2.224404
+.ends
+
+.subckt netg7476 g7476_1 g7476_0 gnd
+C1  g7476_1 gnd 2.080806f
+C2  g7476_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7476_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+C50 48 gnd 2.080806f
+R48 48 47 2.224404
+C51 49 gnd 2.080806f
+R49 49 48 2.224404
+C52 50 gnd 2.080806f
+R50 50 49 2.224404
+C53 51 gnd 2.080806f
+R51 51 50 2.224404
+C54 52 gnd 2.080806f
+R52 52 51 2.224404
+C55 53 gnd 2.080806f
+R53 53 52 2.224404
+C56 54 gnd 2.080806f
+R54 54 53 2.224404
+C57 55 gnd 2.080806f
+R55 55 54 2.224404
+R56 g7476_1 55 2.224404
+.ends
+
+.subckt netg7517 g7517_0 g7517_1 gnd
+C1  g7517_0 gnd 2.080806f
+C2  g7517_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7517_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+C50 48 gnd 2.080806f
+R48 48 47 2.224404
+C51 49 gnd 2.080806f
+R49 49 48 2.224404
+C52 50 gnd 2.080806f
+R50 50 49 2.224404
+C53 51 gnd 2.080806f
+R51 51 50 2.224404
+C54 52 gnd 2.080806f
+R52 51 52 2.224404
+C55 53 gnd 2.080806f
+R53 53 52 2.224404
+C56 54 gnd 2.080806f
+R54 54 53 2.224404
+C57 55 gnd 2.080806f
+R55 55 54 2.224404
+C58 56 gnd 2.080806f
+R56 56 55 2.224404
+C59 57 gnd 2.080806f
+R57 57 56 2.224404
+R58 g7517_1 57 2.224404
+.ends
+
+.subckt netg1691 g1691_6 g1691_3 g1691_5 g1691_2 g1691_1 g1691_4 g1691_0 gnd
+C1  g1691_6 gnd 2.080806f
+C2  g1691_3 gnd 2.080806f
+C3  g1691_5 gnd 2.080806f
+C4  g1691_2 gnd 2.080806f
+C5  g1691_1 gnd 2.080806f
+C6  g1691_4 gnd 2.080806f
+C7  g1691_0 gnd 2.080806f
+C8 1 gnd 2.080806f
+R1 g1691_0 1 2.224404
+C9 2 gnd 2.080806f
+R2 2 1 2.224404
+C10 3 gnd 2.080806f
+R3 2 3 2.224404
+C11 4 gnd 2.080806f
+R4 3 4 2.224404
+C12 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 5 g1691_3 2.224404
+C13 6 gnd 2.080806f
+R7 6 g1691_0 2.224404
+C14 7 gnd 2.080806f
+R8 7 6 2.224404
+C15 8 gnd 2.080806f
+R9 8 7 2.224404
+C16 9 gnd 2.080806f
+R10 9 8 2.224404
+C17 10 gnd 2.080806f
+R11 10 9 2.224404
+C18 11 gnd 2.080806f
+R12 11 10 2.224404
+C19 12 gnd 2.080806f
+R13 12 11 2.224404
+C20 13 gnd 2.080806f
+R14 13 12 2.224404
+C21 14 gnd 2.080806f
+R15 14 13 2.224404
+C22 15 gnd 2.080806f
+R16 15 14 2.224404
+C23 16 gnd 2.080806f
+R17 16 15 2.224404
+C24 17 gnd 2.080806f
+R18 17 16 2.224404
+C25 18 gnd 2.080806f
+R19 18 17 2.224404
+C26 19 gnd 2.080806f
+R20 19 18 2.224404
+R21 g1691_4 19 2.224404
+C27 20 gnd 2.080806f
+R22 20 g1691_4 2.224404
+C28 21 gnd 2.080806f
+R23 21 20 2.224404
+C29 22 gnd 2.080806f
+R24 22 21 2.224404
+C30 23 gnd 2.080806f
+R25 23 22 2.224404
+R26 g1691_5 23 2.224404
+C31 24 gnd 2.080806f
+R27 24 g1691_5 2.224404
+R28 g1691_2 24 2.224404
+C32 25 gnd 2.080806f
+R29 g1691_3 25 2.224404
+C33 26 gnd 2.080806f
+R30 25 26 2.224404
+C34 27 gnd 2.080806f
+R31 26 27 2.224404
+C35 28 gnd 2.080806f
+R32 27 28 2.224404
+C36 29 gnd 2.080806f
+R33 28 29 2.224404
+C37 30 gnd 2.080806f
+R34 29 30 2.224404
+C38 31 gnd 2.080806f
+R35 30 31 2.224404
+C39 32 gnd 2.080806f
+R36 31 32 2.224404
+C40 33 gnd 2.080806f
+R37 32 33 2.224404
+C41 34 gnd 2.080806f
+R38 33 34 2.224404
+C42 35 gnd 2.080806f
+R39 34 35 2.224404
+C43 36 gnd 2.080806f
+R40 35 36 2.224404
+C44 37 gnd 2.080806f
+R41 36 37 2.224404
+C45 38 gnd 2.080806f
+R42 37 38 2.224404
+C46 39 gnd 2.080806f
+R43 38 39 2.224404
+C47 40 gnd 2.080806f
+R44 39 40 2.224404
+C48 41 gnd 2.080806f
+R45 40 41 2.224404
+C49 42 gnd 2.080806f
+R46 41 42 2.224404
+C50 43 gnd 2.080806f
+R47 43 42 2.224404
+C51 44 gnd 2.080806f
+R48 44 43 2.224404
+C52 45 gnd 2.080806f
+R49 44 45 2.224404
+C53 46 gnd 2.080806f
+R50 45 46 2.224404
+C54 47 gnd 2.080806f
+R51 46 47 2.224404
+C55 48 gnd 2.080806f
+R52 47 48 2.224404
+C56 49 gnd 2.080806f
+R53 48 49 2.224404
+C57 50 gnd 2.080806f
+R54 49 50 2.224404
+C58 51 gnd 2.080806f
+R55 50 51 2.224404
+C59 52 gnd 2.080806f
+R56 51 52 2.224404
+R57 g1691_6 52 2.224404
+C60 53 gnd 2.080806f
+R58 53 g1691_6 2.224404
+C61 54 gnd 2.080806f
+R59 54 53 2.224404
+C62 55 gnd 2.080806f
+R60 55 54 2.224404
+C63 56 gnd 2.080806f
+R61 55 56 2.224404
+C64 57 gnd 2.080806f
+R62 57 56 2.224404
+C65 58 gnd 2.080806f
+R63 57 58 2.224404
+C66 59 gnd 2.080806f
+R64 58 59 2.224404
+R65 59 g1691_1 2.224404
+.ends
+
+.subckt netg7458 g7458_0 g7458_1 gnd
+C1  g7458_0 gnd 2.080806f
+C2  g7458_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7458_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+C50 48 gnd 2.080806f
+R48 47 48 2.224404
+C51 49 gnd 2.080806f
+R49 48 49 2.224404
+C52 50 gnd 2.080806f
+R50 49 50 2.224404
+C53 51 gnd 2.080806f
+R51 50 51 2.224404
+C54 52 gnd 2.080806f
+R52 52 51 2.224404
+C55 53 gnd 2.080806f
+R53 53 52 2.224404
+C56 54 gnd 2.080806f
+R54 53 54 2.224404
+C57 55 gnd 2.080806f
+R55 55 54 2.224404
+R56 g7458_1 55 2.224404
+.ends
+
+.subckt netg7541 g7541_0 g7541_1 gnd
+C1  g7541_0 gnd 2.080806f
+C2  g7541_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7541_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+C50 48 gnd 2.080806f
+R48 47 48 2.224404
+C51 49 gnd 2.080806f
+R49 48 49 2.224404
+C52 50 gnd 2.080806f
+R50 49 50 2.224404
+C53 51 gnd 2.080806f
+R51 50 51 2.224404
+C54 52 gnd 2.080806f
+R52 51 52 2.224404
+C55 53 gnd 2.080806f
+R53 52 53 2.224404
+C56 54 gnd 2.080806f
+R54 53 54 2.224404
+C57 55 gnd 2.080806f
+R55 54 55 2.224404
+C58 56 gnd 2.080806f
+R56 55 56 2.224404
+R57 56 g7541_1 2.224404
+.ends
+
+.subckt netg479 g479_1 g479_5 g479_3 g479_2 g479_4 g479_0 gnd
+C1  g479_1 gnd 2.080806f
+C2  g479_5 gnd 2.080806f
+C3  g479_3 gnd 2.080806f
+C4  g479_2 gnd 2.080806f
+C5  g479_4 gnd 2.080806f
+C6  g479_0 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g479_0 2.224404
+C8 2 gnd 2.080806f
+R2 2 1 2.224404
+C9 3 gnd 2.080806f
+R3 3 2 2.224404
+C10 4 gnd 2.080806f
+R4 4 3 2.224404
+C11 5 gnd 2.080806f
+R5 5 4 2.224404
+R6 g479_3 5 2.224404
+C12 6 gnd 2.080806f
+R7 6 g479_3 2.224404
+C13 7 gnd 2.080806f
+R8 7 6 2.224404
+R9 g479_1 7 2.224404
+C14 8 gnd 2.080806f
+R10 8 7 2.224404
+C15 9 gnd 2.080806f
+R11 9 8 2.224404
+C16 10 gnd 2.080806f
+R12 9 10 2.224404
+C17 11 gnd 2.080806f
+R13 11 10 2.224404
+C18 12 gnd 2.080806f
+R14 12 11 2.224404
+C19 13 gnd 2.080806f
+R15 13 12 2.224404
+R16 g479_4 13 2.224404
+C20 14 gnd 2.080806f
+R17 13 14 2.224404
+C21 15 gnd 2.080806f
+R18 14 15 2.224404
+C22 16 gnd 2.080806f
+R19 15 16 2.224404
+C23 17 gnd 2.080806f
+R20 16 17 2.224404
+C24 18 gnd 2.080806f
+R21 17 18 2.224404
+C25 19 gnd 2.080806f
+R22 18 19 2.224404
+C26 20 gnd 2.080806f
+R23 19 20 2.224404
+C27 21 gnd 2.080806f
+R24 20 21 2.224404
+C28 22 gnd 2.080806f
+R25 21 22 2.224404
+C29 23 gnd 2.080806f
+R26 22 23 2.224404
+C30 24 gnd 2.080806f
+R27 23 24 2.224404
+C31 25 gnd 2.080806f
+R28 24 25 2.224404
+C32 26 gnd 2.080806f
+R29 25 26 2.224404
+C33 27 gnd 2.080806f
+R30 26 27 2.224404
+C34 28 gnd 2.080806f
+R31 27 28 2.224404
+C35 29 gnd 2.080806f
+R32 28 29 2.224404
+C36 30 gnd 2.080806f
+R33 29 30 2.224404
+C37 31 gnd 2.080806f
+R34 30 31 2.224404
+C38 32 gnd 2.080806f
+R35 31 32 2.224404
+C39 33 gnd 2.080806f
+R36 32 33 2.224404
+C40 34 gnd 2.080806f
+R37 33 34 2.224404
+C41 35 gnd 2.080806f
+R38 34 35 2.224404
+C42 36 gnd 2.080806f
+R39 35 36 2.224404
+C43 37 gnd 2.080806f
+R40 36 37 2.224404
+C44 38 gnd 2.080806f
+R41 37 38 2.224404
+C45 39 gnd 2.080806f
+R42 38 39 2.224404
+C46 40 gnd 2.080806f
+R43 39 40 2.224404
+C47 41 gnd 2.080806f
+R44 40 41 2.224404
+C48 42 gnd 2.080806f
+R45 41 42 2.224404
+C49 43 gnd 2.080806f
+R46 42 43 2.224404
+C50 44 gnd 2.080806f
+R47 43 44 2.224404
+C51 45 gnd 2.080806f
+R48 44 45 2.224404
+C52 46 gnd 2.080806f
+R49 45 46 2.224404
+C53 47 gnd 2.080806f
+R50 46 47 2.224404
+C54 48 gnd 2.080806f
+R51 47 48 2.224404
+C55 49 gnd 2.080806f
+R52 48 49 2.224404
+C56 50 gnd 2.080806f
+R53 49 50 2.224404
+C57 51 gnd 2.080806f
+R54 50 51 2.224404
+C58 52 gnd 2.080806f
+R55 52 51 2.224404
+R56 52 g479_5 2.224404
+C59 53 gnd 2.080806f
+R57 g479_5 53 2.224404
+C60 54 gnd 2.080806f
+R58 53 54 2.224404
+C61 55 gnd 2.080806f
+R59 54 55 2.224404
+C62 56 gnd 2.080806f
+R60 55 56 2.224404
+C63 57 gnd 2.080806f
+R61 56 57 2.224404
+C64 58 gnd 2.080806f
+R62 57 58 2.224404
+C65 59 gnd 2.080806f
+R63 58 59 2.224404
+C66 60 gnd 2.080806f
+R64 59 60 2.224404
+C67 61 gnd 2.080806f
+R65 60 61 2.224404
+C68 62 gnd 2.080806f
+R66 61 62 2.224404
+C69 63 gnd 2.080806f
+R67 62 63 2.224404
+C70 64 gnd 2.080806f
+R68 63 64 2.224404
+C71 65 gnd 2.080806f
+R69 64 65 2.224404
+C72 66 gnd 2.080806f
+R70 65 66 2.224404
+C73 67 gnd 2.080806f
+R71 66 67 2.224404
+R72 67 g479_2 2.224404
+.ends
+
+.subckt netg156 g156_0 g156_1 gnd
+C1  g156_0 gnd 2.080806f
+C2  g156_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g156_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+C50 48 gnd 2.080806f
+R48 47 48 2.224404
+C51 49 gnd 2.080806f
+R49 48 49 2.224404
+C52 50 gnd 2.080806f
+R50 49 50 2.224404
+C53 51 gnd 2.080806f
+R51 50 51 2.224404
+C54 52 gnd 2.080806f
+R52 51 52 2.224404
+C55 53 gnd 2.080806f
+R53 52 53 2.224404
+C56 54 gnd 2.080806f
+R54 53 54 2.224404
+C57 55 gnd 2.080806f
+R55 54 55 2.224404
+C58 56 gnd 2.080806f
+R56 55 56 2.224404
+R57 56 g156_1 2.224404
+.ends
+
+.subckt netg164 g164_1 g164_0 gnd
+C1  g164_1 gnd 2.080806f
+C2  g164_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g164_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+C50 48 gnd 2.080806f
+R48 47 48 2.224404
+C51 49 gnd 2.080806f
+R49 48 49 2.224404
+C52 50 gnd 2.080806f
+R50 49 50 2.224404
+C53 51 gnd 2.080806f
+R51 50 51 2.224404
+C54 52 gnd 2.080806f
+R52 51 52 2.224404
+C55 53 gnd 2.080806f
+R53 52 53 2.224404
+C56 54 gnd 2.080806f
+R54 53 54 2.224404
+C57 55 gnd 2.080806f
+R55 54 55 2.224404
+C58 56 gnd 2.080806f
+R56 55 56 2.224404
+C59 57 gnd 2.080806f
+R57 56 57 2.224404
+C60 58 gnd 2.080806f
+R58 57 58 2.224404
+C61 59 gnd 2.080806f
+R59 58 59 2.224404
+C62 60 gnd 2.080806f
+R60 59 60 2.224404
+C63 61 gnd 2.080806f
+R61 60 61 2.224404
+C64 62 gnd 2.080806f
+R62 61 62 2.224404
+C65 63 gnd 2.080806f
+R63 62 63 2.224404
+C66 64 gnd 2.080806f
+R64 63 64 2.224404
+C67 65 gnd 2.080806f
+R65 64 65 2.224404
+C68 66 gnd 2.080806f
+R66 65 66 2.224404
+R67 66 g164_1 2.224404
+.ends
+
+.subckt netg7514 g7514_0 g7514_1 gnd
+C1  g7514_0 gnd 2.080806f
+C2  g7514_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7514_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+C50 48 gnd 2.080806f
+R48 47 48 2.224404
+C51 49 gnd 2.080806f
+R49 49 48 2.224404
+C52 50 gnd 2.080806f
+R50 50 49 2.224404
+C53 51 gnd 2.080806f
+R51 51 50 2.224404
+C54 52 gnd 2.080806f
+R52 51 52 2.224404
+C55 53 gnd 2.080806f
+R53 52 53 2.224404
+C56 54 gnd 2.080806f
+R54 54 53 2.224404
+C57 55 gnd 2.080806f
+R55 54 55 2.224404
+C58 56 gnd 2.080806f
+R56 55 56 2.224404
+R57 56 g7514_1 2.224404
+.ends
+
+.subckt netg160 g160_1 g160_0 gnd
+C1  g160_1 gnd 2.080806f
+C2  g160_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g160_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+C50 48 gnd 2.080806f
+R48 48 47 2.224404
+C51 49 gnd 2.080806f
+R49 49 48 2.224404
+C52 50 gnd 2.080806f
+R50 50 49 2.224404
+C53 51 gnd 2.080806f
+R51 51 50 2.224404
+C54 52 gnd 2.080806f
+R52 52 51 2.224404
+C55 53 gnd 2.080806f
+R53 53 52 2.224404
+C56 54 gnd 2.080806f
+R54 54 53 2.224404
+C57 55 gnd 2.080806f
+R55 55 54 2.224404
+C58 56 gnd 2.080806f
+R56 56 55 2.224404
+R57 g160_1 56 2.224404
+.ends
+
+.subckt netg152 g152_1 g152_0 gnd
+C1  g152_1 gnd 2.080806f
+C2  g152_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g152_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+C50 48 gnd 2.080806f
+R48 47 48 2.224404
+C51 49 gnd 2.080806f
+R49 48 49 2.224404
+C52 50 gnd 2.080806f
+R50 49 50 2.224404
+C53 51 gnd 2.080806f
+R51 50 51 2.224404
+C54 52 gnd 2.080806f
+R52 51 52 2.224404
+C55 53 gnd 2.080806f
+R53 52 53 2.224404
+C56 54 gnd 2.080806f
+R54 53 54 2.224404
+C57 55 gnd 2.080806f
+R55 54 55 2.224404
+C58 56 gnd 2.080806f
+R56 55 56 2.224404
+C59 57 gnd 2.080806f
+R57 56 57 2.224404
+C60 58 gnd 2.080806f
+R58 57 58 2.224404
+C61 59 gnd 2.080806f
+R59 58 59 2.224404
+C62 60 gnd 2.080806f
+R60 59 60 2.224404
+C63 61 gnd 2.080806f
+R61 60 61 2.224404
+C64 62 gnd 2.080806f
+R62 61 62 2.224404
+C65 63 gnd 2.080806f
+R63 62 63 2.224404
+C66 64 gnd 2.080806f
+R64 63 64 2.224404
+C67 65 gnd 2.080806f
+R65 64 65 2.224404
+C68 66 gnd 2.080806f
+R66 65 66 2.224404
+C69 67 gnd 2.080806f
+R67 66 67 2.224404
+C70 68 gnd 2.080806f
+R68 67 68 2.224404
+C71 69 gnd 2.080806f
+R69 68 69 2.224404
+C72 70 gnd 2.080806f
+R70 69 70 2.224404
+C73 71 gnd 2.080806f
+R71 70 71 2.224404
+C74 72 gnd 2.080806f
+R72 71 72 2.224404
+C75 73 gnd 2.080806f
+R73 72 73 2.224404
+C76 74 gnd 2.080806f
+R74 73 74 2.224404
+C77 75 gnd 2.080806f
+R75 74 75 2.224404
+C78 76 gnd 2.080806f
+R76 75 76 2.224404
+C79 77 gnd 2.080806f
+R77 76 77 2.224404
+C80 78 gnd 2.080806f
+R78 77 78 2.224404
+C81 79 gnd 2.080806f
+R79 78 79 2.224404
+C82 80 gnd 2.080806f
+R80 79 80 2.224404
+R81 80 g152_1 2.224404
+.ends
+
+.subckt netg169 g169_1 g169_0 g169_2 gnd
+C1  g169_1 gnd 2.080806f
+C2  g169_0 gnd 2.080806f
+C3  g169_2 gnd 2.080806f
+R1 g169_1 g169_0 2.224404
+C4 1 gnd 2.080806f
+R2 g169_0 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+C8 5 gnd 2.080806f
+R6 4 5 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+C10 7 gnd 2.080806f
+R8 6 7 2.224404
+C11 8 gnd 2.080806f
+R9 7 8 2.224404
+C12 9 gnd 2.080806f
+R10 8 9 2.224404
+C13 10 gnd 2.080806f
+R11 9 10 2.224404
+C14 11 gnd 2.080806f
+R12 10 11 2.224404
+C15 12 gnd 2.080806f
+R13 11 12 2.224404
+C16 13 gnd 2.080806f
+R14 12 13 2.224404
+C17 14 gnd 2.080806f
+R15 13 14 2.224404
+C18 15 gnd 2.080806f
+R16 14 15 2.224404
+C19 16 gnd 2.080806f
+R17 15 16 2.224404
+C20 17 gnd 2.080806f
+R18 16 17 2.224404
+C21 18 gnd 2.080806f
+R19 17 18 2.224404
+C22 19 gnd 2.080806f
+R20 18 19 2.224404
+C23 20 gnd 2.080806f
+R21 19 20 2.224404
+C24 21 gnd 2.080806f
+R22 20 21 2.224404
+C25 22 gnd 2.080806f
+R23 21 22 2.224404
+C26 23 gnd 2.080806f
+R24 22 23 2.224404
+C27 24 gnd 2.080806f
+R25 23 24 2.224404
+C28 25 gnd 2.080806f
+R26 24 25 2.224404
+C29 26 gnd 2.080806f
+R27 25 26 2.224404
+C30 27 gnd 2.080806f
+R28 26 27 2.224404
+C31 28 gnd 2.080806f
+R29 27 28 2.224404
+C32 29 gnd 2.080806f
+R30 28 29 2.224404
+C33 30 gnd 2.080806f
+R31 29 30 2.224404
+C34 31 gnd 2.080806f
+R32 30 31 2.224404
+C35 32 gnd 2.080806f
+R33 31 32 2.224404
+C36 33 gnd 2.080806f
+R34 32 33 2.224404
+C37 34 gnd 2.080806f
+R35 33 34 2.224404
+C38 35 gnd 2.080806f
+R36 34 35 2.224404
+C39 36 gnd 2.080806f
+R37 35 36 2.224404
+C40 37 gnd 2.080806f
+R38 36 37 2.224404
+C41 38 gnd 2.080806f
+R39 37 38 2.224404
+C42 39 gnd 2.080806f
+R40 38 39 2.224404
+C43 40 gnd 2.080806f
+R41 39 40 2.224404
+C44 41 gnd 2.080806f
+R42 40 41 2.224404
+C45 42 gnd 2.080806f
+R43 41 42 2.224404
+C46 43 gnd 2.080806f
+R44 42 43 2.224404
+C47 44 gnd 2.080806f
+R45 43 44 2.224404
+C48 45 gnd 2.080806f
+R46 44 45 2.224404
+C49 46 gnd 2.080806f
+R47 45 46 2.224404
+C50 47 gnd 2.080806f
+R48 46 47 2.224404
+C51 48 gnd 2.080806f
+R49 47 48 2.224404
+C52 49 gnd 2.080806f
+R50 48 49 2.224404
+C53 50 gnd 2.080806f
+R51 49 50 2.224404
+C54 51 gnd 2.080806f
+R52 50 51 2.224404
+C55 52 gnd 2.080806f
+R53 51 52 2.224404
+C56 53 gnd 2.080806f
+R54 52 53 2.224404
+C57 54 gnd 2.080806f
+R55 53 54 2.224404
+C58 55 gnd 2.080806f
+R56 54 55 2.224404
+R57 55 g169_2 2.224404
+.ends
+
+.subckt netg12 g12_0 g12_2 g12_1 gnd
+C1  g12_0 gnd 2.080806f
+C2  g12_2 gnd 2.080806f
+C3  g12_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g12_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 6 5 2.224404
+C10 7 gnd 2.080806f
+R7 7 6 2.224404
+C11 8 gnd 2.080806f
+R8 8 7 2.224404
+C12 9 gnd 2.080806f
+R9 9 8 2.224404
+C13 10 gnd 2.080806f
+R10 10 9 2.224404
+C14 11 gnd 2.080806f
+R11 11 10 2.224404
+C15 12 gnd 2.080806f
+R12 12 11 2.224404
+C16 13 gnd 2.080806f
+R13 13 12 2.224404
+C17 14 gnd 2.080806f
+R14 14 13 2.224404
+C18 15 gnd 2.080806f
+R15 15 14 2.224404
+C19 16 gnd 2.080806f
+R16 16 15 2.224404
+C20 17 gnd 2.080806f
+R17 17 16 2.224404
+C21 18 gnd 2.080806f
+R18 18 17 2.224404
+C22 19 gnd 2.080806f
+R19 19 18 2.224404
+C23 20 gnd 2.080806f
+R20 20 19 2.224404
+C24 21 gnd 2.080806f
+R21 21 20 2.224404
+C25 22 gnd 2.080806f
+R22 22 21 2.224404
+R23 g12_2 22 2.224404
+C26 23 gnd 2.080806f
+R24 g12_0 23 2.224404
+C27 24 gnd 2.080806f
+R25 23 24 2.224404
+C28 25 gnd 2.080806f
+R26 24 25 2.224404
+C29 26 gnd 2.080806f
+R27 25 26 2.224404
+C30 27 gnd 2.080806f
+R28 26 27 2.224404
+C31 28 gnd 2.080806f
+R29 27 28 2.224404
+C32 29 gnd 2.080806f
+R30 28 29 2.224404
+C33 30 gnd 2.080806f
+R31 29 30 2.224404
+C34 31 gnd 2.080806f
+R32 30 31 2.224404
+C35 32 gnd 2.080806f
+R33 31 32 2.224404
+C36 33 gnd 2.080806f
+R34 32 33 2.224404
+C37 34 gnd 2.080806f
+R35 33 34 2.224404
+C38 35 gnd 2.080806f
+R36 34 35 2.224404
+C39 36 gnd 2.080806f
+R37 35 36 2.224404
+C40 37 gnd 2.080806f
+R38 36 37 2.224404
+C41 38 gnd 2.080806f
+R39 37 38 2.224404
+C42 39 gnd 2.080806f
+R40 38 39 2.224404
+C43 40 gnd 2.080806f
+R41 39 40 2.224404
+C44 41 gnd 2.080806f
+R42 40 41 2.224404
+C45 42 gnd 2.080806f
+R43 41 42 2.224404
+C46 43 gnd 2.080806f
+R44 42 43 2.224404
+C47 44 gnd 2.080806f
+R45 43 44 2.224404
+C48 45 gnd 2.080806f
+R46 44 45 2.224404
+C49 46 gnd 2.080806f
+R47 45 46 2.224404
+C50 47 gnd 2.080806f
+R48 46 47 2.224404
+C51 48 gnd 2.080806f
+R49 47 48 2.224404
+C52 49 gnd 2.080806f
+R50 48 49 2.224404
+C53 50 gnd 2.080806f
+R51 49 50 2.224404
+C54 51 gnd 2.080806f
+R52 50 51 2.224404
+C55 52 gnd 2.080806f
+R53 51 52 2.224404
+C56 53 gnd 2.080806f
+R54 52 53 2.224404
+C57 54 gnd 2.080806f
+R55 53 54 2.224404
+C58 55 gnd 2.080806f
+R56 54 55 2.224404
+C59 56 gnd 2.080806f
+R57 55 56 2.224404
+R58 56 g12_1 2.224404
+.ends
+
+.subckt netg7474 g7474_1 g7474_0 gnd
+C1  g7474_1 gnd 2.080806f
+C2  g7474_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7474_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+C50 48 gnd 2.080806f
+R48 47 48 2.224404
+C51 49 gnd 2.080806f
+R49 49 48 2.224404
+C52 50 gnd 2.080806f
+R50 50 49 2.224404
+C53 51 gnd 2.080806f
+R51 51 50 2.224404
+C54 52 gnd 2.080806f
+R52 52 51 2.224404
+C55 53 gnd 2.080806f
+R53 53 52 2.224404
+C56 54 gnd 2.080806f
+R54 54 53 2.224404
+C57 55 gnd 2.080806f
+R55 55 54 2.224404
+C58 56 gnd 2.080806f
+R56 55 56 2.224404
+C59 57 gnd 2.080806f
+R57 56 57 2.224404
+R58 57 g7474_1 2.224404
+.ends
+
+.subckt netg53 g53_2 g53_1 g53_0 gnd
+C1  g53_2 gnd 2.080806f
+C2  g53_1 gnd 2.080806f
+C3  g53_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g53_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g53_2 2 2.224404
+C6 3 gnd 2.080806f
+R4 3 g53_2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 11 10 2.224404
+C15 12 gnd 2.080806f
+R13 12 11 2.224404
+C16 13 gnd 2.080806f
+R14 13 12 2.224404
+C17 14 gnd 2.080806f
+R15 14 13 2.224404
+C18 15 gnd 2.080806f
+R16 15 14 2.224404
+C19 16 gnd 2.080806f
+R17 16 15 2.224404
+C20 17 gnd 2.080806f
+R18 17 16 2.224404
+C21 18 gnd 2.080806f
+R19 18 17 2.224404
+C22 19 gnd 2.080806f
+R20 19 18 2.224404
+C23 20 gnd 2.080806f
+R21 20 19 2.224404
+C24 21 gnd 2.080806f
+R22 21 20 2.224404
+C25 22 gnd 2.080806f
+R23 22 21 2.224404
+C26 23 gnd 2.080806f
+R24 23 22 2.224404
+C27 24 gnd 2.080806f
+R25 24 23 2.224404
+C28 25 gnd 2.080806f
+R26 25 24 2.224404
+C29 26 gnd 2.080806f
+R27 26 25 2.224404
+C30 27 gnd 2.080806f
+R28 27 26 2.224404
+C31 28 gnd 2.080806f
+R29 28 27 2.224404
+C32 29 gnd 2.080806f
+R30 29 28 2.224404
+C33 30 gnd 2.080806f
+R31 30 29 2.224404
+C34 31 gnd 2.080806f
+R32 31 30 2.224404
+C35 32 gnd 2.080806f
+R33 32 31 2.224404
+C36 33 gnd 2.080806f
+R34 33 32 2.224404
+C37 34 gnd 2.080806f
+R35 34 33 2.224404
+C38 35 gnd 2.080806f
+R36 35 34 2.224404
+C39 36 gnd 2.080806f
+R37 36 35 2.224404
+C40 37 gnd 2.080806f
+R38 37 36 2.224404
+C41 38 gnd 2.080806f
+R39 38 37 2.224404
+C42 39 gnd 2.080806f
+R40 39 38 2.224404
+C43 40 gnd 2.080806f
+R41 40 39 2.224404
+C44 41 gnd 2.080806f
+R42 41 40 2.224404
+C45 42 gnd 2.080806f
+R43 42 41 2.224404
+C46 43 gnd 2.080806f
+R44 43 42 2.224404
+C47 44 gnd 2.080806f
+R45 44 43 2.224404
+C48 45 gnd 2.080806f
+R46 45 44 2.224404
+C49 46 gnd 2.080806f
+R47 46 45 2.224404
+C50 47 gnd 2.080806f
+R48 47 46 2.224404
+C51 48 gnd 2.080806f
+R49 48 47 2.224404
+C52 49 gnd 2.080806f
+R50 49 48 2.224404
+C53 50 gnd 2.080806f
+R51 50 49 2.224404
+C54 51 gnd 2.080806f
+R52 51 50 2.224404
+C55 52 gnd 2.080806f
+R53 52 51 2.224404
+C56 53 gnd 2.080806f
+R54 53 52 2.224404
+C57 54 gnd 2.080806f
+R55 54 53 2.224404
+C58 55 gnd 2.080806f
+R56 55 54 2.224404
+C59 56 gnd 2.080806f
+R57 56 55 2.224404
+R58 g53_1 56 2.224404
+.ends
+
+.subckt netg2258 g2258_4 g2258_3 g2258_2 g2258_1 g2258_5 gnd
+C1  g2258_4 gnd 2.080806f
+C2  g2258_3 gnd 2.080806f
+C3  g2258_2 gnd 2.080806f
+C4  g2258_1 gnd 2.080806f
+C5  g2258_5 gnd 2.080806f
+C6 1 gnd 2.080806f
+R1 1 g2258_2 2.224404
+R2 g2258_3 1 2.224404
+C7 2 gnd 2.080806f
+R3 g2258_3 2 2.224404
+R4 2 g2258_5 2.224404
+C8 3 gnd 2.080806f
+R5 g2258_2 3 2.224404
+C9 4 gnd 2.080806f
+R6 3 4 2.224404
+C10 5 gnd 2.080806f
+R7 4 5 2.224404
+C11 6 gnd 2.080806f
+R8 5 6 2.224404
+C12 7 gnd 2.080806f
+R9 6 7 2.224404
+C13 8 gnd 2.080806f
+R10 7 8 2.224404
+C14 9 gnd 2.080806f
+R11 8 9 2.224404
+C15 10 gnd 2.080806f
+R12 9 10 2.224404
+C16 11 gnd 2.080806f
+R13 10 11 2.224404
+C17 12 gnd 2.080806f
+R14 11 12 2.224404
+C18 13 gnd 2.080806f
+R15 12 13 2.224404
+C19 14 gnd 2.080806f
+R16 13 14 2.224404
+C20 15 gnd 2.080806f
+R17 14 15 2.224404
+C21 16 gnd 2.080806f
+R18 15 16 2.224404
+C22 17 gnd 2.080806f
+R19 16 17 2.224404
+C23 18 gnd 2.080806f
+R20 17 18 2.224404
+C24 19 gnd 2.080806f
+R21 18 19 2.224404
+C25 20 gnd 2.080806f
+R22 19 20 2.224404
+C26 21 gnd 2.080806f
+R23 20 21 2.224404
+C27 22 gnd 2.080806f
+R24 21 22 2.224404
+C28 23 gnd 2.080806f
+R25 22 23 2.224404
+C29 24 gnd 2.080806f
+R26 23 24 2.224404
+C30 25 gnd 2.080806f
+R27 24 25 2.224404
+C31 26 gnd 2.080806f
+R28 25 26 2.224404
+C32 27 gnd 2.080806f
+R29 26 27 2.224404
+C33 28 gnd 2.080806f
+R30 27 28 2.224404
+C34 29 gnd 2.080806f
+R31 28 29 2.224404
+C35 30 gnd 2.080806f
+R32 29 30 2.224404
+C36 31 gnd 2.080806f
+R33 30 31 2.224404
+C37 32 gnd 2.080806f
+R34 31 32 2.224404
+C38 33 gnd 2.080806f
+R35 32 33 2.224404
+C39 34 gnd 2.080806f
+R36 33 34 2.224404
+R37 34 g2258_1 2.224404
+C40 35 gnd 2.080806f
+R38 g2258_1 35 2.224404
+C41 36 gnd 2.080806f
+R39 35 36 2.224404
+C42 37 gnd 2.080806f
+R40 36 37 2.224404
+C43 38 gnd 2.080806f
+R41 37 38 2.224404
+C44 39 gnd 2.080806f
+R42 38 39 2.224404
+C45 40 gnd 2.080806f
+R43 39 40 2.224404
+C46 41 gnd 2.080806f
+R44 40 41 2.224404
+C47 42 gnd 2.080806f
+R45 41 42 2.224404
+C48 43 gnd 2.080806f
+R46 42 43 2.224404
+C49 44 gnd 2.080806f
+R47 43 44 2.224404
+C50 45 gnd 2.080806f
+R48 44 45 2.224404
+C51 46 gnd 2.080806f
+R49 45 46 2.224404
+C52 47 gnd 2.080806f
+R50 46 47 2.224404
+C53 48 gnd 2.080806f
+R51 47 48 2.224404
+C54 49 gnd 2.080806f
+R52 48 49 2.224404
+C55 50 gnd 2.080806f
+R53 49 50 2.224404
+C56 51 gnd 2.080806f
+R54 50 51 2.224404
+C57 52 gnd 2.080806f
+R55 51 52 2.224404
+C58 53 gnd 2.080806f
+R56 52 53 2.224404
+C59 54 gnd 2.080806f
+R57 53 54 2.224404
+C60 55 gnd 2.080806f
+R58 54 55 2.224404
+C61 56 gnd 2.080806f
+R59 55 56 2.224404
+R60 56 g2258_4 2.224404
+.ends
+
+.subckt netg194 g194_2 g194_0 g194_1 gnd
+C1  g194_2 gnd 2.080806f
+C2  g194_0 gnd 2.080806f
+C3  g194_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g194_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+R5 g194_2 4 2.224404
+C8 5 gnd 2.080806f
+R6 g194_0 5 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+C10 7 gnd 2.080806f
+R8 6 7 2.224404
+C11 8 gnd 2.080806f
+R9 7 8 2.224404
+C12 9 gnd 2.080806f
+R10 8 9 2.224404
+C13 10 gnd 2.080806f
+R11 9 10 2.224404
+C14 11 gnd 2.080806f
+R12 10 11 2.224404
+C15 12 gnd 2.080806f
+R13 11 12 2.224404
+C16 13 gnd 2.080806f
+R14 12 13 2.224404
+C17 14 gnd 2.080806f
+R15 13 14 2.224404
+C18 15 gnd 2.080806f
+R16 14 15 2.224404
+C19 16 gnd 2.080806f
+R17 15 16 2.224404
+C20 17 gnd 2.080806f
+R18 16 17 2.224404
+C21 18 gnd 2.080806f
+R19 17 18 2.224404
+C22 19 gnd 2.080806f
+R20 18 19 2.224404
+C23 20 gnd 2.080806f
+R21 19 20 2.224404
+C24 21 gnd 2.080806f
+R22 20 21 2.224404
+C25 22 gnd 2.080806f
+R23 21 22 2.224404
+C26 23 gnd 2.080806f
+R24 22 23 2.224404
+C27 24 gnd 2.080806f
+R25 23 24 2.224404
+C28 25 gnd 2.080806f
+R26 24 25 2.224404
+C29 26 gnd 2.080806f
+R27 25 26 2.224404
+C30 27 gnd 2.080806f
+R28 26 27 2.224404
+C31 28 gnd 2.080806f
+R29 27 28 2.224404
+C32 29 gnd 2.080806f
+R30 28 29 2.224404
+C33 30 gnd 2.080806f
+R31 29 30 2.224404
+C34 31 gnd 2.080806f
+R32 30 31 2.224404
+C35 32 gnd 2.080806f
+R33 31 32 2.224404
+C36 33 gnd 2.080806f
+R34 32 33 2.224404
+C37 34 gnd 2.080806f
+R35 33 34 2.224404
+C38 35 gnd 2.080806f
+R36 34 35 2.224404
+C39 36 gnd 2.080806f
+R37 35 36 2.224404
+C40 37 gnd 2.080806f
+R38 36 37 2.224404
+C41 38 gnd 2.080806f
+R39 37 38 2.224404
+C42 39 gnd 2.080806f
+R40 38 39 2.224404
+C43 40 gnd 2.080806f
+R41 39 40 2.224404
+C44 41 gnd 2.080806f
+R42 40 41 2.224404
+C45 42 gnd 2.080806f
+R43 41 42 2.224404
+C46 43 gnd 2.080806f
+R44 42 43 2.224404
+C47 44 gnd 2.080806f
+R45 43 44 2.224404
+C48 45 gnd 2.080806f
+R46 44 45 2.224404
+C49 46 gnd 2.080806f
+R47 45 46 2.224404
+C50 47 gnd 2.080806f
+R48 46 47 2.224404
+C51 48 gnd 2.080806f
+R49 47 48 2.224404
+C52 49 gnd 2.080806f
+R50 48 49 2.224404
+C53 50 gnd 2.080806f
+R51 49 50 2.224404
+C54 51 gnd 2.080806f
+R52 50 51 2.224404
+C55 52 gnd 2.080806f
+R53 51 52 2.224404
+C56 53 gnd 2.080806f
+R54 52 53 2.224404
+C57 54 gnd 2.080806f
+R55 53 54 2.224404
+C58 55 gnd 2.080806f
+R56 54 55 2.224404
+C59 56 gnd 2.080806f
+R57 55 56 2.224404
+C60 57 gnd 2.080806f
+R58 56 57 2.224404
+R59 57 g194_1 2.224404
+.ends
+
+.subckt netg7478 g7478_1 g7478_0 gnd
+C1  g7478_1 gnd 2.080806f
+C2  g7478_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7478_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+C50 48 gnd 2.080806f
+R48 47 48 2.224404
+C51 49 gnd 2.080806f
+R49 48 49 2.224404
+C52 50 gnd 2.080806f
+R50 49 50 2.224404
+C53 51 gnd 2.080806f
+R51 50 51 2.224404
+C54 52 gnd 2.080806f
+R52 51 52 2.224404
+C55 53 gnd 2.080806f
+R53 52 53 2.224404
+C56 54 gnd 2.080806f
+R54 53 54 2.224404
+C57 55 gnd 2.080806f
+R55 54 55 2.224404
+C58 56 gnd 2.080806f
+R56 56 55 2.224404
+C59 57 gnd 2.080806f
+R57 56 57 2.224404
+C60 58 gnd 2.080806f
+R58 58 57 2.224404
+R59 g7478_1 58 2.224404
+.ends
+
+.subckt netg2250 g2250_1 g2250_4 g2250_2 g2250_6 g2250_7 g2250_5 g2250_3 gnd
+C1  g2250_1 gnd 2.080806f
+C2  g2250_4 gnd 2.080806f
+C3  g2250_2 gnd 2.080806f
+C4  g2250_6 gnd 2.080806f
+C5  g2250_7 gnd 2.080806f
+C6  g2250_5 gnd 2.080806f
+C7  g2250_3 gnd 2.080806f
+C8 1 gnd 2.080806f
+R1 1 g2250_1 2.224404
+R2 g2250_5 1 2.224404
+C9 2 gnd 2.080806f
+R3 g2250_1 2 2.224404
+C10 3 gnd 2.080806f
+R4 2 3 2.224404
+C11 4 gnd 2.080806f
+R5 3 4 2.224404
+C12 5 gnd 2.080806f
+R6 4 5 2.224404
+C13 6 gnd 2.080806f
+R7 5 6 2.224404
+C14 7 gnd 2.080806f
+R8 6 7 2.224404
+C15 8 gnd 2.080806f
+R9 7 8 2.224404
+C16 9 gnd 2.080806f
+R10 8 9 2.224404
+C17 10 gnd 2.080806f
+R11 9 10 2.224404
+R12 10 g2250_6 2.224404
+C18 11 gnd 2.080806f
+R13 11 g2250_6 2.224404
+C19 12 gnd 2.080806f
+R14 11 12 2.224404
+R15 12 g2250_3 2.224404
+C20 13 gnd 2.080806f
+R16 13 g2250_3 2.224404
+C21 14 gnd 2.080806f
+R17 14 13 2.224404
+C22 15 gnd 2.080806f
+R18 14 15 2.224404
+C23 16 gnd 2.080806f
+R19 15 16 2.224404
+C24 17 gnd 2.080806f
+R20 16 17 2.224404
+C25 18 gnd 2.080806f
+R21 18 17 2.224404
+C26 19 gnd 2.080806f
+R22 18 19 2.224404
+R23 19 g2250_2 2.224404
+C27 20 gnd 2.080806f
+R24 20 g2250_2 2.224404
+C28 21 gnd 2.080806f
+R25 20 21 2.224404
+C29 22 gnd 2.080806f
+R26 21 22 2.224404
+C30 23 gnd 2.080806f
+R27 22 23 2.224404
+C31 24 gnd 2.080806f
+R28 23 24 2.224404
+C32 25 gnd 2.080806f
+R29 24 25 2.224404
+C33 26 gnd 2.080806f
+R30 25 26 2.224404
+C34 27 gnd 2.080806f
+R31 26 27 2.224404
+C35 28 gnd 2.080806f
+R32 27 28 2.224404
+C36 29 gnd 2.080806f
+R33 28 29 2.224404
+C37 30 gnd 2.080806f
+R34 29 30 2.224404
+C38 31 gnd 2.080806f
+R35 30 31 2.224404
+C39 32 gnd 2.080806f
+R36 31 32 2.224404
+C40 33 gnd 2.080806f
+R37 32 33 2.224404
+C41 34 gnd 2.080806f
+R38 33 34 2.224404
+C42 35 gnd 2.080806f
+R39 34 35 2.224404
+C43 36 gnd 2.080806f
+R40 35 36 2.224404
+C44 37 gnd 2.080806f
+R41 36 37 2.224404
+C45 38 gnd 2.080806f
+R42 37 38 2.224404
+C46 39 gnd 2.080806f
+R43 38 39 2.224404
+C47 40 gnd 2.080806f
+R44 39 40 2.224404
+C48 41 gnd 2.080806f
+R45 40 41 2.224404
+C49 42 gnd 2.080806f
+R46 41 42 2.224404
+C50 43 gnd 2.080806f
+R47 42 43 2.224404
+C51 44 gnd 2.080806f
+R48 43 44 2.224404
+C52 45 gnd 2.080806f
+R49 44 45 2.224404
+R50 45 g2250_7 2.224404
+C53 46 gnd 2.080806f
+R51 g2250_7 46 2.224404
+C54 47 gnd 2.080806f
+R52 46 47 2.224404
+C55 48 gnd 2.080806f
+R53 47 48 2.224404
+C56 49 gnd 2.080806f
+R54 48 49 2.224404
+C57 50 gnd 2.080806f
+R55 49 50 2.224404
+C58 51 gnd 2.080806f
+R56 50 51 2.224404
+C59 52 gnd 2.080806f
+R57 51 52 2.224404
+C60 53 gnd 2.080806f
+R58 52 53 2.224404
+C61 54 gnd 2.080806f
+R59 53 54 2.224404
+C62 55 gnd 2.080806f
+R60 54 55 2.224404
+C63 56 gnd 2.080806f
+R61 55 56 2.224404
+C64 57 gnd 2.080806f
+R62 56 57 2.224404
+C65 58 gnd 2.080806f
+R63 57 58 2.224404
+C66 59 gnd 2.080806f
+R64 58 59 2.224404
+C67 60 gnd 2.080806f
+R65 59 60 2.224404
+C68 61 gnd 2.080806f
+R66 60 61 2.224404
+C69 62 gnd 2.080806f
+R67 61 62 2.224404
+C70 63 gnd 2.080806f
+R68 62 63 2.224404
+R69 63 g2250_4 2.224404
+.ends
+
+.subckt netg2133 g2133_7 g2133_0 g2133_6 g2133_4 g2133_3 g2133_2 g2133_1 gnd
+C1  g2133_7 gnd 2.080806f
+C2  g2133_0 gnd 2.080806f
+C3  g2133_6 gnd 2.080806f
+C4  g2133_4 gnd 2.080806f
+C5  g2133_3 gnd 2.080806f
+C6  g2133_2 gnd 2.080806f
+C7  g2133_1 gnd 2.080806f
+R1 g2133_2 g2133_0 2.224404
+R2 g2133_0 g2133_7 2.224404
+R3 g2133_7 g2133_4 2.224404
+C8 1 gnd 2.080806f
+R4 g2133_4 1 2.224404
+R5 1 g2133_3 2.224404
+C9 2 gnd 2.080806f
+R6 g2133_3 2 2.224404
+C10 3 gnd 2.080806f
+R7 2 3 2.224404
+C11 4 gnd 2.080806f
+R8 3 4 2.224404
+C12 5 gnd 2.080806f
+R9 4 5 2.224404
+C13 6 gnd 2.080806f
+R10 5 6 2.224404
+C14 7 gnd 2.080806f
+R11 6 7 2.224404
+C15 8 gnd 2.080806f
+R12 7 8 2.224404
+C16 9 gnd 2.080806f
+R13 8 9 2.224404
+C17 10 gnd 2.080806f
+R14 9 10 2.224404
+C18 11 gnd 2.080806f
+R15 10 11 2.224404
+C19 12 gnd 2.080806f
+R16 11 12 2.224404
+C20 13 gnd 2.080806f
+R17 12 13 2.224404
+C21 14 gnd 2.080806f
+R18 13 14 2.224404
+C22 15 gnd 2.080806f
+R19 14 15 2.224404
+C23 16 gnd 2.080806f
+R20 15 16 2.224404
+C24 17 gnd 2.080806f
+R21 16 17 2.224404
+C25 18 gnd 2.080806f
+R22 17 18 2.224404
+C26 19 gnd 2.080806f
+R23 18 19 2.224404
+C27 20 gnd 2.080806f
+R24 19 20 2.224404
+C28 21 gnd 2.080806f
+R25 20 21 2.224404
+C29 22 gnd 2.080806f
+R26 21 22 2.224404
+C30 23 gnd 2.080806f
+R27 22 23 2.224404
+C31 24 gnd 2.080806f
+R28 23 24 2.224404
+C32 25 gnd 2.080806f
+R29 24 25 2.224404
+C33 26 gnd 2.080806f
+R30 25 26 2.224404
+C34 27 gnd 2.080806f
+R31 26 27 2.224404
+C35 28 gnd 2.080806f
+R32 27 28 2.224404
+C36 29 gnd 2.080806f
+R33 28 29 2.224404
+C37 30 gnd 2.080806f
+R34 29 30 2.224404
+C38 31 gnd 2.080806f
+R35 30 31 2.224404
+C39 32 gnd 2.080806f
+R36 31 32 2.224404
+C40 33 gnd 2.080806f
+R37 32 33 2.224404
+C41 34 gnd 2.080806f
+R38 33 34 2.224404
+C42 35 gnd 2.080806f
+R39 34 35 2.224404
+C43 36 gnd 2.080806f
+R40 35 36 2.224404
+C44 37 gnd 2.080806f
+R41 36 37 2.224404
+C45 38 gnd 2.080806f
+R42 37 38 2.224404
+C46 39 gnd 2.080806f
+R43 38 39 2.224404
+C47 40 gnd 2.080806f
+R44 39 40 2.224404
+C48 41 gnd 2.080806f
+R45 40 41 2.224404
+C49 42 gnd 2.080806f
+R46 41 42 2.224404
+C50 43 gnd 2.080806f
+R47 42 43 2.224404
+C51 44 gnd 2.080806f
+R48 43 44 2.224404
+C52 45 gnd 2.080806f
+R49 44 45 2.224404
+C53 46 gnd 2.080806f
+R50 45 46 2.224404
+C54 47 gnd 2.080806f
+R51 46 47 2.224404
+C55 48 gnd 2.080806f
+R52 47 48 2.224404
+C56 49 gnd 2.080806f
+R53 48 49 2.224404
+C57 50 gnd 2.080806f
+R54 49 50 2.224404
+C58 51 gnd 2.080806f
+R55 50 51 2.224404
+C59 52 gnd 2.080806f
+R56 51 52 2.224404
+C60 53 gnd 2.080806f
+R57 52 53 2.224404
+C61 54 gnd 2.080806f
+R58 54 53 2.224404
+C62 55 gnd 2.080806f
+R59 55 54 2.224404
+R60 55 g2133_1 2.224404
+C63 56 gnd 2.080806f
+R61 g2133_1 56 2.224404
+C64 57 gnd 2.080806f
+R62 56 57 2.224404
+C65 58 gnd 2.080806f
+R63 58 57 2.224404
+C66 59 gnd 2.080806f
+R64 58 59 2.224404
+C67 60 gnd 2.080806f
+R65 59 60 2.224404
+C68 61 gnd 2.080806f
+R66 60 61 2.224404
+R67 g2133_6 61 2.224404
+.ends
+
+.subckt netg52 g52_2 g52_1 g52_0 gnd
+C1  g52_2 gnd 2.080806f
+C2  g52_1 gnd 2.080806f
+C3  g52_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g52_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 5 6 2.224404
+C10 7 gnd 2.080806f
+R7 6 7 2.224404
+C11 8 gnd 2.080806f
+R8 7 8 2.224404
+C12 9 gnd 2.080806f
+R9 8 9 2.224404
+C13 10 gnd 2.080806f
+R10 9 10 2.224404
+C14 11 gnd 2.080806f
+R11 10 11 2.224404
+C15 12 gnd 2.080806f
+R12 11 12 2.224404
+C16 13 gnd 2.080806f
+R13 13 12 2.224404
+C17 14 gnd 2.080806f
+R14 14 13 2.224404
+C18 15 gnd 2.080806f
+R15 14 15 2.224404
+C19 16 gnd 2.080806f
+R16 15 16 2.224404
+C20 17 gnd 2.080806f
+R17 16 17 2.224404
+C21 18 gnd 2.080806f
+R18 17 18 2.224404
+C22 19 gnd 2.080806f
+R19 18 19 2.224404
+C23 20 gnd 2.080806f
+R20 19 20 2.224404
+C24 21 gnd 2.080806f
+R21 20 21 2.224404
+C25 22 gnd 2.080806f
+R22 21 22 2.224404
+C26 23 gnd 2.080806f
+R23 22 23 2.224404
+C27 24 gnd 2.080806f
+R24 23 24 2.224404
+C28 25 gnd 2.080806f
+R25 24 25 2.224404
+C29 26 gnd 2.080806f
+R26 25 26 2.224404
+C30 27 gnd 2.080806f
+R27 26 27 2.224404
+C31 28 gnd 2.080806f
+R28 27 28 2.224404
+C32 29 gnd 2.080806f
+R29 28 29 2.224404
+C33 30 gnd 2.080806f
+R30 29 30 2.224404
+C34 31 gnd 2.080806f
+R31 30 31 2.224404
+C35 32 gnd 2.080806f
+R32 32 31 2.224404
+C36 33 gnd 2.080806f
+R33 32 33 2.224404
+C37 34 gnd 2.080806f
+R34 33 34 2.224404
+R35 34 g52_1 2.224404
+C38 35 gnd 2.080806f
+R36 35 5 2.224404
+C39 36 gnd 2.080806f
+R37 36 35 2.224404
+C40 37 gnd 2.080806f
+R38 37 36 2.224404
+C41 38 gnd 2.080806f
+R39 38 37 2.224404
+C42 39 gnd 2.080806f
+R40 39 38 2.224404
+C43 40 gnd 2.080806f
+R41 40 39 2.224404
+C44 41 gnd 2.080806f
+R42 41 40 2.224404
+C45 42 gnd 2.080806f
+R43 42 41 2.224404
+C46 43 gnd 2.080806f
+R44 43 42 2.224404
+C47 44 gnd 2.080806f
+R45 44 43 2.224404
+C48 45 gnd 2.080806f
+R46 45 44 2.224404
+C49 46 gnd 2.080806f
+R47 46 45 2.224404
+C50 47 gnd 2.080806f
+R48 47 46 2.224404
+C51 48 gnd 2.080806f
+R49 48 47 2.224404
+C52 49 gnd 2.080806f
+R50 49 48 2.224404
+C53 50 gnd 2.080806f
+R51 50 49 2.224404
+C54 51 gnd 2.080806f
+R52 51 50 2.224404
+C55 52 gnd 2.080806f
+R53 52 51 2.224404
+C56 53 gnd 2.080806f
+R54 53 52 2.224404
+C57 54 gnd 2.080806f
+R55 54 53 2.224404
+C58 55 gnd 2.080806f
+R56 55 54 2.224404
+C59 56 gnd 2.080806f
+R57 56 55 2.224404
+C60 57 gnd 2.080806f
+R58 57 56 2.224404
+C61 58 gnd 2.080806f
+R59 58 57 2.224404
+C62 59 gnd 2.080806f
+R60 59 58 2.224404
+C63 60 gnd 2.080806f
+R61 60 59 2.224404
+C64 61 gnd 2.080806f
+R62 61 60 2.224404
+C65 62 gnd 2.080806f
+R63 62 61 2.224404
+C66 63 gnd 2.080806f
+R64 63 62 2.224404
+C67 64 gnd 2.080806f
+R65 64 63 2.224404
+C68 65 gnd 2.080806f
+R66 65 64 2.224404
+C69 66 gnd 2.080806f
+R67 66 65 2.224404
+R68 g52_2 66 2.224404
+.ends
+
+.subckt netg2264 g2264_4 g2264_3 g2264_5 g2264_2 g2264_1 g2264_0 gnd
+C1  g2264_4 gnd 2.080806f
+C2  g2264_3 gnd 2.080806f
+C3  g2264_5 gnd 2.080806f
+C4  g2264_2 gnd 2.080806f
+C5  g2264_1 gnd 2.080806f
+C6  g2264_0 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g2264_0 2.224404
+C8 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g2264_3 2 2.224404
+C9 3 gnd 2.080806f
+R4 3 g2264_3 2.224404
+C10 4 gnd 2.080806f
+R5 4 3 2.224404
+C11 5 gnd 2.080806f
+R6 5 4 2.224404
+C12 6 gnd 2.080806f
+R7 6 5 2.224404
+C13 7 gnd 2.080806f
+R8 7 6 2.224404
+C14 8 gnd 2.080806f
+R9 8 7 2.224404
+C15 9 gnd 2.080806f
+R10 9 8 2.224404
+C16 10 gnd 2.080806f
+R11 10 9 2.224404
+C17 11 gnd 2.080806f
+R12 11 10 2.224404
+C18 12 gnd 2.080806f
+R13 12 11 2.224404
+R14 g2264_5 12 2.224404
+C19 13 gnd 2.080806f
+R15 g2264_5 13 2.224404
+C20 14 gnd 2.080806f
+R16 13 14 2.224404
+R17 g2264_2 14 2.224404
+C21 15 gnd 2.080806f
+R18 g2264_0 15 2.224404
+C22 16 gnd 2.080806f
+R19 15 16 2.224404
+C23 17 gnd 2.080806f
+R20 16 17 2.224404
+C24 18 gnd 2.080806f
+R21 17 18 2.224404
+C25 19 gnd 2.080806f
+R22 18 19 2.224404
+C26 20 gnd 2.080806f
+R23 19 20 2.224404
+C27 21 gnd 2.080806f
+R24 20 21 2.224404
+C28 22 gnd 2.080806f
+R25 21 22 2.224404
+C29 23 gnd 2.080806f
+R26 22 23 2.224404
+C30 24 gnd 2.080806f
+R27 23 24 2.224404
+C31 25 gnd 2.080806f
+R28 24 25 2.224404
+C32 26 gnd 2.080806f
+R29 25 26 2.224404
+C33 27 gnd 2.080806f
+R30 26 27 2.224404
+C34 28 gnd 2.080806f
+R31 27 28 2.224404
+C35 29 gnd 2.080806f
+R32 28 29 2.224404
+C36 30 gnd 2.080806f
+R33 29 30 2.224404
+C37 31 gnd 2.080806f
+R34 30 31 2.224404
+C38 32 gnd 2.080806f
+R35 31 32 2.224404
+C39 33 gnd 2.080806f
+R36 32 33 2.224404
+C40 34 gnd 2.080806f
+R37 33 34 2.224404
+C41 35 gnd 2.080806f
+R38 34 35 2.224404
+C42 36 gnd 2.080806f
+R39 35 36 2.224404
+C43 37 gnd 2.080806f
+R40 36 37 2.224404
+C44 38 gnd 2.080806f
+R41 38 37 2.224404
+C45 39 gnd 2.080806f
+R42 39 38 2.224404
+C46 40 gnd 2.080806f
+R43 40 39 2.224404
+R44 g2264_1 40 2.224404
+C47 41 gnd 2.080806f
+R45 37 41 2.224404
+C48 42 gnd 2.080806f
+R46 41 42 2.224404
+C49 43 gnd 2.080806f
+R47 42 43 2.224404
+C50 44 gnd 2.080806f
+R48 43 44 2.224404
+C51 45 gnd 2.080806f
+R49 44 45 2.224404
+C52 46 gnd 2.080806f
+R50 45 46 2.224404
+C53 47 gnd 2.080806f
+R51 46 47 2.224404
+C54 48 gnd 2.080806f
+R52 47 48 2.224404
+C55 49 gnd 2.080806f
+R53 48 49 2.224404
+C56 50 gnd 2.080806f
+R54 49 50 2.224404
+C57 51 gnd 2.080806f
+R55 50 51 2.224404
+C58 52 gnd 2.080806f
+R56 51 52 2.224404
+C59 53 gnd 2.080806f
+R57 52 53 2.224404
+C60 54 gnd 2.080806f
+R58 53 54 2.224404
+C61 55 gnd 2.080806f
+R59 54 55 2.224404
+C62 56 gnd 2.080806f
+R60 55 56 2.224404
+C63 57 gnd 2.080806f
+R61 56 57 2.224404
+C64 58 gnd 2.080806f
+R62 57 58 2.224404
+C65 59 gnd 2.080806f
+R63 58 59 2.224404
+C66 60 gnd 2.080806f
+R64 59 60 2.224404
+C67 61 gnd 2.080806f
+R65 60 61 2.224404
+R66 61 g2264_4 2.224404
+.ends
+
+.subckt netg2153 g2153_1 g2153_3 g2153_2 g2153_5 g2153_4 g2153_0 gnd
+C1  g2153_1 gnd 2.080806f
+C2  g2153_3 gnd 2.080806f
+C3  g2153_2 gnd 2.080806f
+C4  g2153_5 gnd 2.080806f
+C5  g2153_4 gnd 2.080806f
+C6  g2153_0 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 g2153_0 1 2.224404
+R2 1 g2153_3 2.224404
+R3 g2153_3 g2153_1 2.224404
+C8 2 gnd 2.080806f
+R4 2 g2153_0 2.224404
+R5 2 g2153_5 2.224404
+C9 3 gnd 2.080806f
+R6 g2153_5 3 2.224404
+C10 4 gnd 2.080806f
+R7 3 4 2.224404
+C11 5 gnd 2.080806f
+R8 4 5 2.224404
+C12 6 gnd 2.080806f
+R9 5 6 2.224404
+C13 7 gnd 2.080806f
+R10 6 7 2.224404
+C14 8 gnd 2.080806f
+R11 7 8 2.224404
+C15 9 gnd 2.080806f
+R12 8 9 2.224404
+C16 10 gnd 2.080806f
+R13 9 10 2.224404
+C17 11 gnd 2.080806f
+R14 10 11 2.224404
+C18 12 gnd 2.080806f
+R15 11 12 2.224404
+C19 13 gnd 2.080806f
+R16 12 13 2.224404
+C20 14 gnd 2.080806f
+R17 13 14 2.224404
+C21 15 gnd 2.080806f
+R18 14 15 2.224404
+C22 16 gnd 2.080806f
+R19 15 16 2.224404
+C23 17 gnd 2.080806f
+R20 16 17 2.224404
+C24 18 gnd 2.080806f
+R21 17 18 2.224404
+C25 19 gnd 2.080806f
+R22 18 19 2.224404
+C26 20 gnd 2.080806f
+R23 19 20 2.224404
+C27 21 gnd 2.080806f
+R24 20 21 2.224404
+C28 22 gnd 2.080806f
+R25 21 22 2.224404
+C29 23 gnd 2.080806f
+R26 22 23 2.224404
+C30 24 gnd 2.080806f
+R27 23 24 2.224404
+C31 25 gnd 2.080806f
+R28 24 25 2.224404
+C32 26 gnd 2.080806f
+R29 25 26 2.224404
+C33 27 gnd 2.080806f
+R30 26 27 2.224404
+C34 28 gnd 2.080806f
+R31 27 28 2.224404
+C35 29 gnd 2.080806f
+R32 28 29 2.224404
+C36 30 gnd 2.080806f
+R33 29 30 2.224404
+C37 31 gnd 2.080806f
+R34 30 31 2.224404
+C38 32 gnd 2.080806f
+R35 31 32 2.224404
+C39 33 gnd 2.080806f
+R36 32 33 2.224404
+C40 34 gnd 2.080806f
+R37 33 34 2.224404
+C41 35 gnd 2.080806f
+R38 34 35 2.224404
+C42 36 gnd 2.080806f
+R39 35 36 2.224404
+C43 37 gnd 2.080806f
+R40 36 37 2.224404
+C44 38 gnd 2.080806f
+R41 37 38 2.224404
+C45 39 gnd 2.080806f
+R42 38 39 2.224404
+C46 40 gnd 2.080806f
+R43 40 39 2.224404
+C47 41 gnd 2.080806f
+R44 40 41 2.224404
+R45 g2153_2 41 2.224404
+C48 42 gnd 2.080806f
+R46 42 g2153_2 2.224404
+C49 43 gnd 2.080806f
+R47 43 42 2.224404
+C50 44 gnd 2.080806f
+R48 44 43 2.224404
+C51 45 gnd 2.080806f
+R49 44 45 2.224404
+C52 46 gnd 2.080806f
+R50 46 45 2.224404
+C53 47 gnd 2.080806f
+R51 46 47 2.224404
+C54 48 gnd 2.080806f
+R52 47 48 2.224404
+C55 49 gnd 2.080806f
+R53 48 49 2.224404
+C56 50 gnd 2.080806f
+R54 49 50 2.224404
+C57 51 gnd 2.080806f
+R55 50 51 2.224404
+C58 52 gnd 2.080806f
+R56 52 51 2.224404
+C59 53 gnd 2.080806f
+R57 52 53 2.224404
+C60 54 gnd 2.080806f
+R58 53 54 2.224404
+C61 55 gnd 2.080806f
+R59 54 55 2.224404
+C62 56 gnd 2.080806f
+R60 55 56 2.224404
+C63 57 gnd 2.080806f
+R61 56 57 2.224404
+C64 58 gnd 2.080806f
+R62 57 58 2.224404
+C65 59 gnd 2.080806f
+R63 58 59 2.224404
+C66 60 gnd 2.080806f
+R64 59 60 2.224404
+C67 61 gnd 2.080806f
+R65 60 61 2.224404
+C68 62 gnd 2.080806f
+R66 61 62 2.224404
+C69 63 gnd 2.080806f
+R67 62 63 2.224404
+C70 64 gnd 2.080806f
+R68 63 64 2.224404
+C71 65 gnd 2.080806f
+R69 64 65 2.224404
+C72 66 gnd 2.080806f
+R70 65 66 2.224404
+C73 67 gnd 2.080806f
+R71 66 67 2.224404
+C74 68 gnd 2.080806f
+R72 67 68 2.224404
+C75 69 gnd 2.080806f
+R73 68 69 2.224404
+C76 70 gnd 2.080806f
+R74 69 70 2.224404
+C77 71 gnd 2.080806f
+R75 70 71 2.224404
+C78 72 gnd 2.080806f
+R76 71 72 2.224404
+R77 72 g2153_4 2.224404
+.ends
+
+.subckt netg65 g65_2 g65_0 g65_1 gnd
+C1  g65_2 gnd 2.080806f
+C2  g65_0 gnd 2.080806f
+C3  g65_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g65_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 6 5 2.224404
+C10 7 gnd 2.080806f
+R7 7 6 2.224404
+C11 8 gnd 2.080806f
+R8 8 7 2.224404
+C12 9 gnd 2.080806f
+R9 9 8 2.224404
+C13 10 gnd 2.080806f
+R10 10 9 2.224404
+C14 11 gnd 2.080806f
+R11 11 10 2.224404
+C15 12 gnd 2.080806f
+R12 12 11 2.224404
+C16 13 gnd 2.080806f
+R13 13 12 2.224404
+C17 14 gnd 2.080806f
+R14 14 13 2.224404
+C18 15 gnd 2.080806f
+R15 14 15 2.224404
+C19 16 gnd 2.080806f
+R16 16 15 2.224404
+C20 17 gnd 2.080806f
+R17 17 16 2.224404
+C21 18 gnd 2.080806f
+R18 18 17 2.224404
+C22 19 gnd 2.080806f
+R19 19 18 2.224404
+C23 20 gnd 2.080806f
+R20 20 19 2.224404
+C24 21 gnd 2.080806f
+R21 21 20 2.224404
+C25 22 gnd 2.080806f
+R22 22 21 2.224404
+C26 23 gnd 2.080806f
+R23 23 22 2.224404
+C27 24 gnd 2.080806f
+R24 24 23 2.224404
+C28 25 gnd 2.080806f
+R25 24 25 2.224404
+C29 26 gnd 2.080806f
+R26 26 25 2.224404
+C30 27 gnd 2.080806f
+R27 27 26 2.224404
+C31 28 gnd 2.080806f
+R28 27 28 2.224404
+C32 29 gnd 2.080806f
+R29 28 29 2.224404
+C33 30 gnd 2.080806f
+R30 30 29 2.224404
+C34 31 gnd 2.080806f
+R31 31 30 2.224404
+C35 32 gnd 2.080806f
+R32 32 31 2.224404
+C36 33 gnd 2.080806f
+R33 32 33 2.224404
+C37 34 gnd 2.080806f
+R34 34 33 2.224404
+C38 35 gnd 2.080806f
+R35 35 34 2.224404
+R36 35 g65_1 2.224404
+C39 36 gnd 2.080806f
+R37 36 7 2.224404
+C40 37 gnd 2.080806f
+R38 37 36 2.224404
+C41 38 gnd 2.080806f
+R39 38 37 2.224404
+C42 39 gnd 2.080806f
+R40 39 38 2.224404
+C43 40 gnd 2.080806f
+R41 40 39 2.224404
+C44 41 gnd 2.080806f
+R42 41 40 2.224404
+C45 42 gnd 2.080806f
+R43 42 41 2.224404
+C46 43 gnd 2.080806f
+R44 43 42 2.224404
+C47 44 gnd 2.080806f
+R45 44 43 2.224404
+C48 45 gnd 2.080806f
+R46 45 44 2.224404
+C49 46 gnd 2.080806f
+R47 46 45 2.224404
+C50 47 gnd 2.080806f
+R48 47 46 2.224404
+C51 48 gnd 2.080806f
+R49 48 47 2.224404
+C52 49 gnd 2.080806f
+R50 49 48 2.224404
+C53 50 gnd 2.080806f
+R51 50 49 2.224404
+C54 51 gnd 2.080806f
+R52 51 50 2.224404
+C55 52 gnd 2.080806f
+R53 52 51 2.224404
+C56 53 gnd 2.080806f
+R54 53 52 2.224404
+C57 54 gnd 2.080806f
+R55 54 53 2.224404
+C58 55 gnd 2.080806f
+R56 55 54 2.224404
+C59 56 gnd 2.080806f
+R57 56 55 2.224404
+C60 57 gnd 2.080806f
+R58 57 56 2.224404
+C61 58 gnd 2.080806f
+R59 58 57 2.224404
+C62 59 gnd 2.080806f
+R60 59 58 2.224404
+C63 60 gnd 2.080806f
+R61 60 59 2.224404
+C64 61 gnd 2.080806f
+R62 61 60 2.224404
+C65 62 gnd 2.080806f
+R63 62 61 2.224404
+C66 63 gnd 2.080806f
+R64 63 62 2.224404
+C67 64 gnd 2.080806f
+R65 64 63 2.224404
+C68 65 gnd 2.080806f
+R66 65 64 2.224404
+C69 66 gnd 2.080806f
+R67 66 65 2.224404
+C70 67 gnd 2.080806f
+R68 67 66 2.224404
+C71 68 gnd 2.080806f
+R69 68 67 2.224404
+C72 69 gnd 2.080806f
+R70 69 68 2.224404
+C73 70 gnd 2.080806f
+R71 70 69 2.224404
+C74 71 gnd 2.080806f
+R72 71 70 2.224404
+C75 72 gnd 2.080806f
+R73 72 71 2.224404
+C76 73 gnd 2.080806f
+R74 73 72 2.224404
+R75 g65_2 73 2.224404
+.ends
+
+.subckt netg394 g394_1 g394_0 g394_2 gnd
+C1  g394_1 gnd 2.080806f
+C2  g394_0 gnd 2.080806f
+C3  g394_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g394_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 6 5 2.224404
+C10 7 gnd 2.080806f
+R7 6 7 2.224404
+C11 8 gnd 2.080806f
+R8 7 8 2.224404
+C12 9 gnd 2.080806f
+R9 8 9 2.224404
+C13 10 gnd 2.080806f
+R10 9 10 2.224404
+C14 11 gnd 2.080806f
+R11 11 10 2.224404
+C15 12 gnd 2.080806f
+R12 11 12 2.224404
+C16 13 gnd 2.080806f
+R13 12 13 2.224404
+C17 14 gnd 2.080806f
+R14 13 14 2.224404
+C18 15 gnd 2.080806f
+R15 14 15 2.224404
+C19 16 gnd 2.080806f
+R16 15 16 2.224404
+C20 17 gnd 2.080806f
+R17 17 16 2.224404
+C21 18 gnd 2.080806f
+R18 18 17 2.224404
+C22 19 gnd 2.080806f
+R19 19 18 2.224404
+C23 20 gnd 2.080806f
+R20 20 19 2.224404
+C24 21 gnd 2.080806f
+R21 21 20 2.224404
+C25 22 gnd 2.080806f
+R22 22 21 2.224404
+C26 23 gnd 2.080806f
+R23 23 22 2.224404
+C27 24 gnd 2.080806f
+R24 24 23 2.224404
+C28 25 gnd 2.080806f
+R25 25 24 2.224404
+C29 26 gnd 2.080806f
+R26 26 25 2.224404
+C30 27 gnd 2.080806f
+R27 27 26 2.224404
+C31 28 gnd 2.080806f
+R28 28 27 2.224404
+C32 29 gnd 2.080806f
+R29 29 28 2.224404
+C33 30 gnd 2.080806f
+R30 30 29 2.224404
+C34 31 gnd 2.080806f
+R31 31 30 2.224404
+C35 32 gnd 2.080806f
+R32 32 31 2.224404
+C36 33 gnd 2.080806f
+R33 32 33 2.224404
+C37 34 gnd 2.080806f
+R34 34 33 2.224404
+C38 35 gnd 2.080806f
+R35 35 34 2.224404
+C39 36 gnd 2.080806f
+R36 36 35 2.224404
+C40 37 gnd 2.080806f
+R37 37 36 2.224404
+R38 g394_1 37 2.224404
+C41 38 gnd 2.080806f
+R39 g394_1 38 2.224404
+C42 39 gnd 2.080806f
+R40 39 38 2.224404
+C43 40 gnd 2.080806f
+R41 40 39 2.224404
+C44 41 gnd 2.080806f
+R42 41 40 2.224404
+C45 42 gnd 2.080806f
+R43 42 41 2.224404
+C46 43 gnd 2.080806f
+R44 43 42 2.224404
+C47 44 gnd 2.080806f
+R45 44 43 2.224404
+C48 45 gnd 2.080806f
+R46 45 44 2.224404
+C49 46 gnd 2.080806f
+R47 46 45 2.224404
+C50 47 gnd 2.080806f
+R48 47 46 2.224404
+C51 48 gnd 2.080806f
+R49 48 47 2.224404
+C52 49 gnd 2.080806f
+R50 49 48 2.224404
+C53 50 gnd 2.080806f
+R51 50 49 2.224404
+C54 51 gnd 2.080806f
+R52 51 50 2.224404
+C55 52 gnd 2.080806f
+R53 52 51 2.224404
+C56 53 gnd 2.080806f
+R54 52 53 2.224404
+C57 54 gnd 2.080806f
+R55 54 53 2.224404
+C58 55 gnd 2.080806f
+R56 55 54 2.224404
+C59 56 gnd 2.080806f
+R57 56 55 2.224404
+C60 57 gnd 2.080806f
+R58 57 56 2.224404
+C61 58 gnd 2.080806f
+R59 58 57 2.224404
+C62 59 gnd 2.080806f
+R60 59 58 2.224404
+C63 60 gnd 2.080806f
+R61 60 59 2.224404
+C64 61 gnd 2.080806f
+R62 61 60 2.224404
+C65 62 gnd 2.080806f
+R63 62 61 2.224404
+C66 63 gnd 2.080806f
+R64 63 62 2.224404
+C67 64 gnd 2.080806f
+R65 64 63 2.224404
+C68 65 gnd 2.080806f
+R66 64 65 2.224404
+C69 66 gnd 2.080806f
+R67 66 65 2.224404
+C70 67 gnd 2.080806f
+R68 67 66 2.224404
+C71 68 gnd 2.080806f
+R69 68 67 2.224404
+C72 69 gnd 2.080806f
+R70 69 68 2.224404
+R71 g394_2 69 2.224404
+.ends
+
+.subckt netg1652 g1652_0 g1652_5 g1652_2 g1652_3 g1652_4 g1652_1 gnd
+C1  g1652_0 gnd 2.080806f
+C2  g1652_5 gnd 2.080806f
+C3  g1652_2 gnd 2.080806f
+C4  g1652_3 gnd 2.080806f
+C5  g1652_4 gnd 2.080806f
+C6  g1652_1 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g1652_0 2.224404
+C8 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g1652_1 2 2.224404
+C9 3 gnd 2.080806f
+R4 g1652_0 3 2.224404
+C10 4 gnd 2.080806f
+R5 4 3 2.224404
+C11 5 gnd 2.080806f
+R6 5 4 2.224404
+C12 6 gnd 2.080806f
+R7 6 5 2.224404
+C13 7 gnd 2.080806f
+R8 7 6 2.224404
+C14 8 gnd 2.080806f
+R9 8 7 2.224404
+C15 9 gnd 2.080806f
+R10 9 8 2.224404
+C16 10 gnd 2.080806f
+R11 10 9 2.224404
+C17 11 gnd 2.080806f
+R12 11 10 2.224404
+C18 12 gnd 2.080806f
+R13 12 11 2.224404
+C19 13 gnd 2.080806f
+R14 13 12 2.224404
+C20 14 gnd 2.080806f
+R15 14 13 2.224404
+C21 15 gnd 2.080806f
+R16 15 14 2.224404
+C22 16 gnd 2.080806f
+R17 16 15 2.224404
+C23 17 gnd 2.080806f
+R18 17 16 2.224404
+C24 18 gnd 2.080806f
+R19 18 17 2.224404
+C25 19 gnd 2.080806f
+R20 19 18 2.224404
+C26 20 gnd 2.080806f
+R21 20 19 2.224404
+C27 21 gnd 2.080806f
+R22 21 20 2.224404
+C28 22 gnd 2.080806f
+R23 22 21 2.224404
+C29 23 gnd 2.080806f
+R24 23 22 2.224404
+C30 24 gnd 2.080806f
+R25 24 23 2.224404
+C31 25 gnd 2.080806f
+R26 25 24 2.224404
+C32 26 gnd 2.080806f
+R27 26 25 2.224404
+C33 27 gnd 2.080806f
+R28 27 26 2.224404
+C34 28 gnd 2.080806f
+R29 28 27 2.224404
+C35 29 gnd 2.080806f
+R30 29 28 2.224404
+C36 30 gnd 2.080806f
+R31 30 29 2.224404
+C37 31 gnd 2.080806f
+R32 31 30 2.224404
+C38 32 gnd 2.080806f
+R33 32 31 2.224404
+C39 33 gnd 2.080806f
+R34 33 32 2.224404
+C40 34 gnd 2.080806f
+R35 34 33 2.224404
+C41 35 gnd 2.080806f
+R36 35 34 2.224404
+C42 36 gnd 2.080806f
+R37 36 35 2.224404
+C43 37 gnd 2.080806f
+R38 37 36 2.224404
+C44 38 gnd 2.080806f
+R39 38 37 2.224404
+C45 39 gnd 2.080806f
+R40 39 38 2.224404
+C46 40 gnd 2.080806f
+R41 40 39 2.224404
+C47 41 gnd 2.080806f
+R42 41 40 2.224404
+C48 42 gnd 2.080806f
+R43 42 41 2.224404
+C49 43 gnd 2.080806f
+R44 43 42 2.224404
+C50 44 gnd 2.080806f
+R45 44 43 2.224404
+C51 45 gnd 2.080806f
+R46 45 44 2.224404
+C52 46 gnd 2.080806f
+R47 46 45 2.224404
+C53 47 gnd 2.080806f
+R48 47 46 2.224404
+C54 48 gnd 2.080806f
+R49 48 47 2.224404
+C55 49 gnd 2.080806f
+R50 49 48 2.224404
+C56 50 gnd 2.080806f
+R51 50 49 2.224404
+C57 51 gnd 2.080806f
+R52 51 50 2.224404
+C58 52 gnd 2.080806f
+R53 52 51 2.224404
+C59 53 gnd 2.080806f
+R54 53 52 2.224404
+C60 54 gnd 2.080806f
+R55 54 53 2.224404
+C61 55 gnd 2.080806f
+R56 55 54 2.224404
+C62 56 gnd 2.080806f
+R57 56 55 2.224404
+C63 57 gnd 2.080806f
+R58 57 56 2.224404
+C64 58 gnd 2.080806f
+R59 58 57 2.224404
+C65 59 gnd 2.080806f
+R60 58 59 2.224404
+R61 g1652_4 59 2.224404
+R62 g1652_4 g1652_2 2.224404
+C66 60 gnd 2.080806f
+R63 60 g1652_2 2.224404
+C67 61 gnd 2.080806f
+R64 61 60 2.224404
+R65 g1652_5 61 2.224404
+C68 62 gnd 2.080806f
+R66 62 g1652_4 2.224404
+C69 63 gnd 2.080806f
+R67 63 62 2.224404
+C70 64 gnd 2.080806f
+R68 64 63 2.224404
+C71 65 gnd 2.080806f
+R69 65 64 2.224404
+C72 66 gnd 2.080806f
+R70 66 65 2.224404
+R71 g1652_3 66 2.224404
+.ends
+
+.subckt netg400 g400_1 g400_0 g400_2 gnd
+C1  g400_1 gnd 2.080806f
+C2  g400_0 gnd 2.080806f
+C3  g400_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g400_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 5 6 2.224404
+C10 7 gnd 2.080806f
+R7 6 7 2.224404
+C11 8 gnd 2.080806f
+R8 7 8 2.224404
+C12 9 gnd 2.080806f
+R9 8 9 2.224404
+C13 10 gnd 2.080806f
+R10 9 10 2.224404
+C14 11 gnd 2.080806f
+R11 10 11 2.224404
+C15 12 gnd 2.080806f
+R12 11 12 2.224404
+C16 13 gnd 2.080806f
+R13 12 13 2.224404
+C17 14 gnd 2.080806f
+R14 13 14 2.224404
+C18 15 gnd 2.080806f
+R15 14 15 2.224404
+C19 16 gnd 2.080806f
+R16 15 16 2.224404
+C20 17 gnd 2.080806f
+R17 16 17 2.224404
+C21 18 gnd 2.080806f
+R18 17 18 2.224404
+C22 19 gnd 2.080806f
+R19 18 19 2.224404
+C23 20 gnd 2.080806f
+R20 19 20 2.224404
+C24 21 gnd 2.080806f
+R21 20 21 2.224404
+C25 22 gnd 2.080806f
+R22 21 22 2.224404
+C26 23 gnd 2.080806f
+R23 22 23 2.224404
+C27 24 gnd 2.080806f
+R24 23 24 2.224404
+C28 25 gnd 2.080806f
+R25 25 24 2.224404
+C29 26 gnd 2.080806f
+R26 25 26 2.224404
+C30 27 gnd 2.080806f
+R27 26 27 2.224404
+C31 28 gnd 2.080806f
+R28 28 27 2.224404
+C32 29 gnd 2.080806f
+R29 28 29 2.224404
+C33 30 gnd 2.080806f
+R30 29 30 2.224404
+R31 30 g400_1 2.224404
+C34 31 gnd 2.080806f
+R32 g400_1 31 2.224404
+C35 32 gnd 2.080806f
+R33 31 32 2.224404
+C36 33 gnd 2.080806f
+R34 32 33 2.224404
+C37 34 gnd 2.080806f
+R35 33 34 2.224404
+C38 35 gnd 2.080806f
+R36 34 35 2.224404
+C39 36 gnd 2.080806f
+R37 35 36 2.224404
+C40 37 gnd 2.080806f
+R38 36 37 2.224404
+C41 38 gnd 2.080806f
+R39 37 38 2.224404
+C42 39 gnd 2.080806f
+R40 38 39 2.224404
+C43 40 gnd 2.080806f
+R41 39 40 2.224404
+C44 41 gnd 2.080806f
+R42 40 41 2.224404
+C45 42 gnd 2.080806f
+R43 41 42 2.224404
+C46 43 gnd 2.080806f
+R44 42 43 2.224404
+C47 44 gnd 2.080806f
+R45 43 44 2.224404
+C48 45 gnd 2.080806f
+R46 44 45 2.224404
+C49 46 gnd 2.080806f
+R47 45 46 2.224404
+C50 47 gnd 2.080806f
+R48 46 47 2.224404
+C51 48 gnd 2.080806f
+R49 47 48 2.224404
+C52 49 gnd 2.080806f
+R50 48 49 2.224404
+C53 50 gnd 2.080806f
+R51 49 50 2.224404
+C54 51 gnd 2.080806f
+R52 50 51 2.224404
+C55 52 gnd 2.080806f
+R53 51 52 2.224404
+C56 53 gnd 2.080806f
+R54 52 53 2.224404
+C57 54 gnd 2.080806f
+R55 53 54 2.224404
+C58 55 gnd 2.080806f
+R56 54 55 2.224404
+C59 56 gnd 2.080806f
+R57 55 56 2.224404
+C60 57 gnd 2.080806f
+R58 56 57 2.224404
+C61 58 gnd 2.080806f
+R59 57 58 2.224404
+C62 59 gnd 2.080806f
+R60 58 59 2.224404
+C63 60 gnd 2.080806f
+R61 59 60 2.224404
+C64 61 gnd 2.080806f
+R62 60 61 2.224404
+C65 62 gnd 2.080806f
+R63 61 62 2.224404
+C66 63 gnd 2.080806f
+R64 62 63 2.224404
+C67 64 gnd 2.080806f
+R65 63 64 2.224404
+C68 65 gnd 2.080806f
+R66 64 65 2.224404
+R67 65 g400_2 2.224404
+.ends
+
+.subckt netg7520 g7520_0 g7520_1 gnd
+C1  g7520_0 gnd 2.080806f
+C2  g7520_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7520_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+C50 48 gnd 2.080806f
+R48 48 47 2.224404
+C51 49 gnd 2.080806f
+R49 49 48 2.224404
+C52 50 gnd 2.080806f
+R50 50 49 2.224404
+C53 51 gnd 2.080806f
+R51 51 50 2.224404
+C54 52 gnd 2.080806f
+R52 52 51 2.224404
+C55 53 gnd 2.080806f
+R53 53 52 2.224404
+C56 54 gnd 2.080806f
+R54 54 53 2.224404
+C57 55 gnd 2.080806f
+R55 55 54 2.224404
+C58 56 gnd 2.080806f
+R56 56 55 2.224404
+C59 57 gnd 2.080806f
+R57 57 56 2.224404
+C60 58 gnd 2.080806f
+R58 58 57 2.224404
+C61 59 gnd 2.080806f
+R59 59 58 2.224404
+C62 60 gnd 2.080806f
+R60 60 59 2.224404
+C63 61 gnd 2.080806f
+R61 61 60 2.224404
+C64 62 gnd 2.080806f
+R62 62 61 2.224404
+C65 63 gnd 2.080806f
+R63 63 62 2.224404
+C66 64 gnd 2.080806f
+R64 64 63 2.224404
+C67 65 gnd 2.080806f
+R65 65 64 2.224404
+C68 66 gnd 2.080806f
+R66 66 65 2.224404
+C69 67 gnd 2.080806f
+R67 67 66 2.224404
+C70 68 gnd 2.080806f
+R68 68 67 2.224404
+R69 g7520_1 68 2.224404
+.ends
+
+.subckt netg7475 g7475_1 g7475_0 gnd
+C1  g7475_1 gnd 2.080806f
+C2  g7475_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7475_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+C50 48 gnd 2.080806f
+R48 47 48 2.224404
+C51 49 gnd 2.080806f
+R49 49 48 2.224404
+C52 50 gnd 2.080806f
+R50 50 49 2.224404
+C53 51 gnd 2.080806f
+R51 51 50 2.224404
+C54 52 gnd 2.080806f
+R52 52 51 2.224404
+C55 53 gnd 2.080806f
+R53 53 52 2.224404
+C56 54 gnd 2.080806f
+R54 54 53 2.224404
+C57 55 gnd 2.080806f
+R55 54 55 2.224404
+C58 56 gnd 2.080806f
+R56 55 56 2.224404
+C59 57 gnd 2.080806f
+R57 57 56 2.224404
+C60 58 gnd 2.080806f
+R58 58 57 2.224404
+C61 59 gnd 2.080806f
+R59 59 58 2.224404
+C62 60 gnd 2.080806f
+R60 60 59 2.224404
+C63 61 gnd 2.080806f
+R61 61 60 2.224404
+C64 62 gnd 2.080806f
+R62 62 61 2.224404
+C65 63 gnd 2.080806f
+R63 63 62 2.224404
+C66 64 gnd 2.080806f
+R64 63 64 2.224404
+C67 65 gnd 2.080806f
+R65 64 65 2.224404
+R66 65 g7475_1 2.224404
+.ends
+
+.subckt netg7451 g7451_1 g7451_0 gnd
+C1  g7451_1 gnd 2.080806f
+C2  g7451_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7451_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+C50 48 gnd 2.080806f
+R48 47 48 2.224404
+C51 49 gnd 2.080806f
+R49 49 48 2.224404
+C52 50 gnd 2.080806f
+R50 50 49 2.224404
+C53 51 gnd 2.080806f
+R51 51 50 2.224404
+C54 52 gnd 2.080806f
+R52 52 51 2.224404
+C55 53 gnd 2.080806f
+R53 53 52 2.224404
+C56 54 gnd 2.080806f
+R54 54 53 2.224404
+C57 55 gnd 2.080806f
+R55 55 54 2.224404
+C58 56 gnd 2.080806f
+R56 55 56 2.224404
+C59 57 gnd 2.080806f
+R57 56 57 2.224404
+C60 58 gnd 2.080806f
+R58 58 57 2.224404
+C61 59 gnd 2.080806f
+R59 59 58 2.224404
+C62 60 gnd 2.080806f
+R60 60 59 2.224404
+C63 61 gnd 2.080806f
+R61 61 60 2.224404
+C64 62 gnd 2.080806f
+R62 62 61 2.224404
+C65 63 gnd 2.080806f
+R63 63 62 2.224404
+C66 64 gnd 2.080806f
+R64 64 63 2.224404
+C67 65 gnd 2.080806f
+R65 64 65 2.224404
+C68 66 gnd 2.080806f
+R66 65 66 2.224404
+R67 66 g7451_1 2.224404
+.ends
+
+.subckt netg553 g553_5 g553_1 g553_4 g553_0 g553_3 g553_2 gnd
+C1  g553_5 gnd 2.080806f
+C2  g553_1 gnd 2.080806f
+C3  g553_4 gnd 2.080806f
+C4  g553_0 gnd 2.080806f
+C5  g553_3 gnd 2.080806f
+C6  g553_2 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g553_0 2.224404
+C8 2 gnd 2.080806f
+R2 1 2 2.224404
+C9 3 gnd 2.080806f
+R3 2 3 2.224404
+C10 4 gnd 2.080806f
+R4 3 4 2.224404
+C11 5 gnd 2.080806f
+R5 5 4 2.224404
+C12 6 gnd 2.080806f
+R6 6 5 2.224404
+C13 7 gnd 2.080806f
+R7 7 6 2.224404
+C14 8 gnd 2.080806f
+R8 7 8 2.224404
+C15 9 gnd 2.080806f
+R9 8 9 2.224404
+C16 10 gnd 2.080806f
+R10 9 10 2.224404
+C17 11 gnd 2.080806f
+R11 10 11 2.224404
+C18 12 gnd 2.080806f
+R12 11 12 2.224404
+C19 13 gnd 2.080806f
+R13 12 13 2.224404
+C20 14 gnd 2.080806f
+R14 14 13 2.224404
+C21 15 gnd 2.080806f
+R15 14 15 2.224404
+R16 g553_5 15 2.224404
+C22 16 gnd 2.080806f
+R17 16 g553_5 2.224404
+C23 17 gnd 2.080806f
+R18 17 16 2.224404
+C24 18 gnd 2.080806f
+R19 18 17 2.224404
+C25 19 gnd 2.080806f
+R20 19 18 2.224404
+C26 20 gnd 2.080806f
+R21 20 19 2.224404
+C27 21 gnd 2.080806f
+R22 21 20 2.224404
+C28 22 gnd 2.080806f
+R23 22 21 2.224404
+C29 23 gnd 2.080806f
+R24 23 22 2.224404
+C30 24 gnd 2.080806f
+R25 24 23 2.224404
+C31 25 gnd 2.080806f
+R26 25 24 2.224404
+C32 26 gnd 2.080806f
+R27 26 25 2.224404
+C33 27 gnd 2.080806f
+R28 27 26 2.224404
+C34 28 gnd 2.080806f
+R29 28 27 2.224404
+C35 29 gnd 2.080806f
+R30 29 28 2.224404
+C36 30 gnd 2.080806f
+R31 30 29 2.224404
+C37 31 gnd 2.080806f
+R32 31 30 2.224404
+C38 32 gnd 2.080806f
+R33 32 31 2.224404
+C39 33 gnd 2.080806f
+R34 33 32 2.224404
+C40 34 gnd 2.080806f
+R35 34 33 2.224404
+C41 35 gnd 2.080806f
+R36 35 34 2.224404
+C42 36 gnd 2.080806f
+R37 36 35 2.224404
+C43 37 gnd 2.080806f
+R38 37 36 2.224404
+C44 38 gnd 2.080806f
+R39 38 37 2.224404
+C45 39 gnd 2.080806f
+R40 39 38 2.224404
+C46 40 gnd 2.080806f
+R41 40 39 2.224404
+C47 41 gnd 2.080806f
+R42 41 40 2.224404
+C48 42 gnd 2.080806f
+R43 42 41 2.224404
+C49 43 gnd 2.080806f
+R44 43 42 2.224404
+C50 44 gnd 2.080806f
+R45 44 43 2.224404
+C51 45 gnd 2.080806f
+R46 45 44 2.224404
+C52 46 gnd 2.080806f
+R47 46 45 2.224404
+C53 47 gnd 2.080806f
+R48 47 46 2.224404
+C54 48 gnd 2.080806f
+R49 48 47 2.224404
+C55 49 gnd 2.080806f
+R50 49 48 2.224404
+C56 50 gnd 2.080806f
+R51 50 49 2.224404
+C57 51 gnd 2.080806f
+R52 51 50 2.224404
+C58 52 gnd 2.080806f
+R53 52 51 2.224404
+C59 53 gnd 2.080806f
+R54 53 52 2.224404
+C60 54 gnd 2.080806f
+R55 54 53 2.224404
+R56 g553_2 54 2.224404
+C61 55 gnd 2.080806f
+R57 55 g553_2 2.224404
+C62 56 gnd 2.080806f
+R58 56 55 2.224404
+C63 57 gnd 2.080806f
+R59 57 56 2.224404
+C64 58 gnd 2.080806f
+R60 58 57 2.224404
+C65 59 gnd 2.080806f
+R61 59 58 2.224404
+C66 60 gnd 2.080806f
+R62 60 59 2.224404
+C67 61 gnd 2.080806f
+R63 61 60 2.224404
+C68 62 gnd 2.080806f
+R64 62 61 2.224404
+C69 63 gnd 2.080806f
+R65 63 62 2.224404
+R66 g553_3 63 2.224404
+C70 64 gnd 2.080806f
+R67 64 g553_3 2.224404
+C71 65 gnd 2.080806f
+R68 65 64 2.224404
+C72 66 gnd 2.080806f
+R69 66 65 2.224404
+C73 67 gnd 2.080806f
+R70 66 67 2.224404
+C74 68 gnd 2.080806f
+R71 68 67 2.224404
+C75 69 gnd 2.080806f
+R72 69 68 2.224404
+C76 70 gnd 2.080806f
+R73 70 69 2.224404
+R74 g553_1 70 2.224404
+C77 71 gnd 2.080806f
+R75 71 g553_1 2.224404
+C78 72 gnd 2.080806f
+R76 72 71 2.224404
+C79 73 gnd 2.080806f
+R77 73 72 2.224404
+C80 74 gnd 2.080806f
+R78 74 73 2.224404
+C81 75 gnd 2.080806f
+R79 75 74 2.224404
+R80 g553_4 75 2.224404
+.ends
+
+.subckt netg172 g172_1 g172_2 g172_0 gnd
+C1  g172_1 gnd 2.080806f
+C2  g172_2 gnd 2.080806f
+C3  g172_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g172_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 4 5 2.224404
+R6 g172_1 5 2.224404
+C9 6 gnd 2.080806f
+R7 g172_1 6 2.224404
+C10 7 gnd 2.080806f
+R8 6 7 2.224404
+C11 8 gnd 2.080806f
+R9 7 8 2.224404
+C12 9 gnd 2.080806f
+R10 8 9 2.224404
+C13 10 gnd 2.080806f
+R11 9 10 2.224404
+C14 11 gnd 2.080806f
+R12 10 11 2.224404
+C15 12 gnd 2.080806f
+R13 11 12 2.224404
+C16 13 gnd 2.080806f
+R14 12 13 2.224404
+C17 14 gnd 2.080806f
+R15 13 14 2.224404
+C18 15 gnd 2.080806f
+R16 14 15 2.224404
+C19 16 gnd 2.080806f
+R17 15 16 2.224404
+C20 17 gnd 2.080806f
+R18 16 17 2.224404
+C21 18 gnd 2.080806f
+R19 17 18 2.224404
+C22 19 gnd 2.080806f
+R20 18 19 2.224404
+C23 20 gnd 2.080806f
+R21 19 20 2.224404
+C24 21 gnd 2.080806f
+R22 20 21 2.224404
+C25 22 gnd 2.080806f
+R23 21 22 2.224404
+C26 23 gnd 2.080806f
+R24 22 23 2.224404
+C27 24 gnd 2.080806f
+R25 23 24 2.224404
+C28 25 gnd 2.080806f
+R26 24 25 2.224404
+C29 26 gnd 2.080806f
+R27 25 26 2.224404
+C30 27 gnd 2.080806f
+R28 26 27 2.224404
+C31 28 gnd 2.080806f
+R29 27 28 2.224404
+C32 29 gnd 2.080806f
+R30 28 29 2.224404
+C33 30 gnd 2.080806f
+R31 29 30 2.224404
+C34 31 gnd 2.080806f
+R32 30 31 2.224404
+C35 32 gnd 2.080806f
+R33 31 32 2.224404
+C36 33 gnd 2.080806f
+R34 32 33 2.224404
+C37 34 gnd 2.080806f
+R35 33 34 2.224404
+C38 35 gnd 2.080806f
+R36 34 35 2.224404
+C39 36 gnd 2.080806f
+R37 35 36 2.224404
+C40 37 gnd 2.080806f
+R38 36 37 2.224404
+C41 38 gnd 2.080806f
+R39 37 38 2.224404
+C42 39 gnd 2.080806f
+R40 38 39 2.224404
+C43 40 gnd 2.080806f
+R41 39 40 2.224404
+C44 41 gnd 2.080806f
+R42 40 41 2.224404
+C45 42 gnd 2.080806f
+R43 41 42 2.224404
+C46 43 gnd 2.080806f
+R44 42 43 2.224404
+C47 44 gnd 2.080806f
+R45 43 44 2.224404
+C48 45 gnd 2.080806f
+R46 44 45 2.224404
+C49 46 gnd 2.080806f
+R47 45 46 2.224404
+C50 47 gnd 2.080806f
+R48 46 47 2.224404
+C51 48 gnd 2.080806f
+R49 47 48 2.224404
+C52 49 gnd 2.080806f
+R50 48 49 2.224404
+C53 50 gnd 2.080806f
+R51 49 50 2.224404
+C54 51 gnd 2.080806f
+R52 50 51 2.224404
+C55 52 gnd 2.080806f
+R53 51 52 2.224404
+C56 53 gnd 2.080806f
+R54 52 53 2.224404
+C57 54 gnd 2.080806f
+R55 53 54 2.224404
+C58 55 gnd 2.080806f
+R56 54 55 2.224404
+C59 56 gnd 2.080806f
+R57 55 56 2.224404
+C60 57 gnd 2.080806f
+R58 56 57 2.224404
+C61 58 gnd 2.080806f
+R59 57 58 2.224404
+C62 59 gnd 2.080806f
+R60 58 59 2.224404
+C63 60 gnd 2.080806f
+R61 59 60 2.224404
+C64 61 gnd 2.080806f
+R62 60 61 2.224404
+C65 62 gnd 2.080806f
+R63 61 62 2.224404
+C66 63 gnd 2.080806f
+R64 62 63 2.224404
+C67 64 gnd 2.080806f
+R65 63 64 2.224404
+C68 65 gnd 2.080806f
+R66 64 65 2.224404
+C69 66 gnd 2.080806f
+R67 65 66 2.224404
+C70 67 gnd 2.080806f
+R68 66 67 2.224404
+C71 68 gnd 2.080806f
+R69 67 68 2.224404
+R70 68 g172_2 2.224404
+.ends
+
+.subckt netg397 g397_1 g397_0 g397_2 gnd
+C1  g397_1 gnd 2.080806f
+C2  g397_0 gnd 2.080806f
+C3  g397_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g397_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+C8 5 gnd 2.080806f
+R5 4 5 2.224404
+C9 6 gnd 2.080806f
+R6 5 6 2.224404
+C10 7 gnd 2.080806f
+R7 6 7 2.224404
+C11 8 gnd 2.080806f
+R8 7 8 2.224404
+C12 9 gnd 2.080806f
+R9 9 8 2.224404
+C13 10 gnd 2.080806f
+R10 10 9 2.224404
+C14 11 gnd 2.080806f
+R11 11 10 2.224404
+C15 12 gnd 2.080806f
+R12 12 11 2.224404
+C16 13 gnd 2.080806f
+R13 13 12 2.224404
+C17 14 gnd 2.080806f
+R14 14 13 2.224404
+C18 15 gnd 2.080806f
+R15 15 14 2.224404
+C19 16 gnd 2.080806f
+R16 16 15 2.224404
+C20 17 gnd 2.080806f
+R17 17 16 2.224404
+C21 18 gnd 2.080806f
+R18 18 17 2.224404
+C22 19 gnd 2.080806f
+R19 19 18 2.224404
+C23 20 gnd 2.080806f
+R20 20 19 2.224404
+C24 21 gnd 2.080806f
+R21 21 20 2.224404
+C25 22 gnd 2.080806f
+R22 22 21 2.224404
+C26 23 gnd 2.080806f
+R23 23 22 2.224404
+C27 24 gnd 2.080806f
+R24 24 23 2.224404
+C28 25 gnd 2.080806f
+R25 25 24 2.224404
+C29 26 gnd 2.080806f
+R26 26 25 2.224404
+C30 27 gnd 2.080806f
+R27 27 26 2.224404
+C31 28 gnd 2.080806f
+R28 28 27 2.224404
+C32 29 gnd 2.080806f
+R29 29 28 2.224404
+C33 30 gnd 2.080806f
+R30 30 29 2.224404
+C34 31 gnd 2.080806f
+R31 31 30 2.224404
+C35 32 gnd 2.080806f
+R32 32 31 2.224404
+C36 33 gnd 2.080806f
+R33 33 32 2.224404
+C37 34 gnd 2.080806f
+R34 34 33 2.224404
+C38 35 gnd 2.080806f
+R35 35 34 2.224404
+C39 36 gnd 2.080806f
+R36 36 35 2.224404
+C40 37 gnd 2.080806f
+R37 37 36 2.224404
+C41 38 gnd 2.080806f
+R38 38 37 2.224404
+C42 39 gnd 2.080806f
+R39 39 38 2.224404
+C43 40 gnd 2.080806f
+R40 40 39 2.224404
+C44 41 gnd 2.080806f
+R41 41 40 2.224404
+C45 42 gnd 2.080806f
+R42 42 41 2.224404
+C46 43 gnd 2.080806f
+R43 43 42 2.224404
+R44 g397_1 43 2.224404
+C47 44 gnd 2.080806f
+R45 44 g397_1 2.224404
+C48 45 gnd 2.080806f
+R46 45 44 2.224404
+C49 46 gnd 2.080806f
+R47 46 45 2.224404
+C50 47 gnd 2.080806f
+R48 47 46 2.224404
+C51 48 gnd 2.080806f
+R49 48 47 2.224404
+C52 49 gnd 2.080806f
+R50 49 48 2.224404
+C53 50 gnd 2.080806f
+R51 50 49 2.224404
+C54 51 gnd 2.080806f
+R52 51 50 2.224404
+C55 52 gnd 2.080806f
+R53 52 51 2.224404
+C56 53 gnd 2.080806f
+R54 53 52 2.224404
+C57 54 gnd 2.080806f
+R55 54 53 2.224404
+C58 55 gnd 2.080806f
+R56 55 54 2.224404
+C59 56 gnd 2.080806f
+R57 56 55 2.224404
+C60 57 gnd 2.080806f
+R58 57 56 2.224404
+C61 58 gnd 2.080806f
+R59 58 57 2.224404
+C62 59 gnd 2.080806f
+R60 59 58 2.224404
+C63 60 gnd 2.080806f
+R61 60 59 2.224404
+C64 61 gnd 2.080806f
+R62 61 60 2.224404
+C65 62 gnd 2.080806f
+R63 62 61 2.224404
+C66 63 gnd 2.080806f
+R64 62 63 2.224404
+C67 64 gnd 2.080806f
+R65 63 64 2.224404
+C68 65 gnd 2.080806f
+R66 65 64 2.224404
+C69 66 gnd 2.080806f
+R67 66 65 2.224404
+C70 67 gnd 2.080806f
+R68 66 67 2.224404
+C71 68 gnd 2.080806f
+R69 67 68 2.224404
+C72 69 gnd 2.080806f
+R70 69 68 2.224404
+C73 70 gnd 2.080806f
+R71 70 69 2.224404
+C74 71 gnd 2.080806f
+R72 70 71 2.224404
+C75 72 gnd 2.080806f
+R73 72 71 2.224404
+C76 73 gnd 2.080806f
+R74 73 72 2.224404
+C77 74 gnd 2.080806f
+R75 74 73 2.224404
+C78 75 gnd 2.080806f
+R76 74 75 2.224404
+C79 76 gnd 2.080806f
+R77 76 75 2.224404
+C80 77 gnd 2.080806f
+R78 77 76 2.224404
+C81 78 gnd 2.080806f
+R79 78 77 2.224404
+C82 79 gnd 2.080806f
+R80 79 78 2.224404
+R81 g397_2 79 2.224404
+.ends
+
+.subckt netg545 g545_5 g545_0 g545_6 g545_4 g545_7 g545_1 g545_2 g545_3 gnd
+C1  g545_5 gnd 2.080806f
+C2  g545_0 gnd 2.080806f
+C3  g545_6 gnd 2.080806f
+C4  g545_4 gnd 2.080806f
+C5  g545_7 gnd 2.080806f
+C6  g545_1 gnd 2.080806f
+C7  g545_2 gnd 2.080806f
+C8  g545_3 gnd 2.080806f
+C9 1 gnd 2.080806f
+R1 1 g545_0 2.224404
+R2 g545_6 1 2.224404
+C10 2 gnd 2.080806f
+R3 g545_0 2 2.224404
+C11 3 gnd 2.080806f
+R4 2 3 2.224404
+C12 4 gnd 2.080806f
+R5 3 4 2.224404
+C13 5 gnd 2.080806f
+R6 4 5 2.224404
+C14 6 gnd 2.080806f
+R7 5 6 2.224404
+R8 6 g545_7 2.224404
+C15 7 gnd 2.080806f
+R9 7 g545_6 2.224404
+C16 8 gnd 2.080806f
+R10 8 7 2.224404
+C17 9 gnd 2.080806f
+R11 9 8 2.224404
+C18 10 gnd 2.080806f
+R12 10 9 2.224404
+C19 11 gnd 2.080806f
+R13 11 10 2.224404
+C20 12 gnd 2.080806f
+R14 12 11 2.224404
+C21 13 gnd 2.080806f
+R15 13 12 2.224404
+C22 14 gnd 2.080806f
+R16 14 13 2.224404
+C23 15 gnd 2.080806f
+R17 15 14 2.224404
+C24 16 gnd 2.080806f
+R18 16 15 2.224404
+C25 17 gnd 2.080806f
+R19 17 16 2.224404
+C26 18 gnd 2.080806f
+R20 18 17 2.224404
+R21 g545_4 18 2.224404
+R22 g545_5 g545_4 2.224404
+R23 g545_2 g545_5 2.224404
+C27 19 gnd 2.080806f
+R24 g545_7 19 2.224404
+C28 20 gnd 2.080806f
+R25 19 20 2.224404
+C29 21 gnd 2.080806f
+R26 20 21 2.224404
+C30 22 gnd 2.080806f
+R27 21 22 2.224404
+C31 23 gnd 2.080806f
+R28 22 23 2.224404
+C32 24 gnd 2.080806f
+R29 23 24 2.224404
+C33 25 gnd 2.080806f
+R30 24 25 2.224404
+C34 26 gnd 2.080806f
+R31 25 26 2.224404
+C35 27 gnd 2.080806f
+R32 26 27 2.224404
+C36 28 gnd 2.080806f
+R33 27 28 2.224404
+C37 29 gnd 2.080806f
+R34 28 29 2.224404
+C38 30 gnd 2.080806f
+R35 29 30 2.224404
+C39 31 gnd 2.080806f
+R36 30 31 2.224404
+C40 32 gnd 2.080806f
+R37 31 32 2.224404
+C41 33 gnd 2.080806f
+R38 32 33 2.224404
+C42 34 gnd 2.080806f
+R39 33 34 2.224404
+C43 35 gnd 2.080806f
+R40 34 35 2.224404
+C44 36 gnd 2.080806f
+R41 35 36 2.224404
+C45 37 gnd 2.080806f
+R42 36 37 2.224404
+C46 38 gnd 2.080806f
+R43 37 38 2.224404
+C47 39 gnd 2.080806f
+R44 38 39 2.224404
+C48 40 gnd 2.080806f
+R45 39 40 2.224404
+C49 41 gnd 2.080806f
+R46 40 41 2.224404
+C50 42 gnd 2.080806f
+R47 41 42 2.224404
+C51 43 gnd 2.080806f
+R48 42 43 2.224404
+C52 44 gnd 2.080806f
+R49 43 44 2.224404
+C53 45 gnd 2.080806f
+R50 44 45 2.224404
+C54 46 gnd 2.080806f
+R51 45 46 2.224404
+C55 47 gnd 2.080806f
+R52 46 47 2.224404
+C56 48 gnd 2.080806f
+R53 47 48 2.224404
+C57 49 gnd 2.080806f
+R54 48 49 2.224404
+C58 50 gnd 2.080806f
+R55 49 50 2.224404
+R56 50 g545_1 2.224404
+C59 51 gnd 2.080806f
+R57 g545_1 51 2.224404
+C60 52 gnd 2.080806f
+R58 51 52 2.224404
+C61 53 gnd 2.080806f
+R59 53 52 2.224404
+C62 54 gnd 2.080806f
+R60 54 53 2.224404
+C63 55 gnd 2.080806f
+R61 55 54 2.224404
+C64 56 gnd 2.080806f
+R62 55 56 2.224404
+C65 57 gnd 2.080806f
+R63 56 57 2.224404
+C66 58 gnd 2.080806f
+R64 57 58 2.224404
+C67 59 gnd 2.080806f
+R65 58 59 2.224404
+C68 60 gnd 2.080806f
+R66 60 59 2.224404
+C69 61 gnd 2.080806f
+R67 61 60 2.224404
+C70 62 gnd 2.080806f
+R68 62 61 2.224404
+C71 63 gnd 2.080806f
+R69 62 63 2.224404
+C72 64 gnd 2.080806f
+R70 63 64 2.224404
+C73 65 gnd 2.080806f
+R71 64 65 2.224404
+C74 66 gnd 2.080806f
+R72 66 65 2.224404
+C75 67 gnd 2.080806f
+R73 67 66 2.224404
+C76 68 gnd 2.080806f
+R74 68 67 2.224404
+C77 69 gnd 2.080806f
+R75 69 68 2.224404
+C78 70 gnd 2.080806f
+R76 69 70 2.224404
+C79 71 gnd 2.080806f
+R77 70 71 2.224404
+C80 72 gnd 2.080806f
+R78 71 72 2.224404
+R79 72 g545_3 2.224404
+.ends
+
+.subckt netg175 g175_1 g175_0 g175_2 gnd
+C1  g175_1 gnd 2.080806f
+C2  g175_0 gnd 2.080806f
+C3  g175_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g175_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+C8 5 gnd 2.080806f
+R5 4 5 2.224404
+C9 6 gnd 2.080806f
+R6 5 6 2.224404
+C10 7 gnd 2.080806f
+R7 6 7 2.224404
+C11 8 gnd 2.080806f
+R8 7 8 2.224404
+C12 9 gnd 2.080806f
+R9 8 9 2.224404
+C13 10 gnd 2.080806f
+R10 9 10 2.224404
+C14 11 gnd 2.080806f
+R11 10 11 2.224404
+C15 12 gnd 2.080806f
+R12 11 12 2.224404
+C16 13 gnd 2.080806f
+R13 12 13 2.224404
+C17 14 gnd 2.080806f
+R14 13 14 2.224404
+C18 15 gnd 2.080806f
+R15 14 15 2.224404
+C19 16 gnd 2.080806f
+R16 15 16 2.224404
+R17 16 g175_1 2.224404
+C20 17 gnd 2.080806f
+R18 g175_1 17 2.224404
+C21 18 gnd 2.080806f
+R19 17 18 2.224404
+C22 19 gnd 2.080806f
+R20 18 19 2.224404
+C23 20 gnd 2.080806f
+R21 19 20 2.224404
+C24 21 gnd 2.080806f
+R22 20 21 2.224404
+C25 22 gnd 2.080806f
+R23 21 22 2.224404
+C26 23 gnd 2.080806f
+R24 22 23 2.224404
+C27 24 gnd 2.080806f
+R25 23 24 2.224404
+C28 25 gnd 2.080806f
+R26 24 25 2.224404
+C29 26 gnd 2.080806f
+R27 25 26 2.224404
+C30 27 gnd 2.080806f
+R28 26 27 2.224404
+C31 28 gnd 2.080806f
+R29 27 28 2.224404
+C32 29 gnd 2.080806f
+R30 28 29 2.224404
+C33 30 gnd 2.080806f
+R31 29 30 2.224404
+C34 31 gnd 2.080806f
+R32 30 31 2.224404
+C35 32 gnd 2.080806f
+R33 31 32 2.224404
+C36 33 gnd 2.080806f
+R34 32 33 2.224404
+C37 34 gnd 2.080806f
+R35 33 34 2.224404
+C38 35 gnd 2.080806f
+R36 34 35 2.224404
+C39 36 gnd 2.080806f
+R37 35 36 2.224404
+C40 37 gnd 2.080806f
+R38 36 37 2.224404
+C41 38 gnd 2.080806f
+R39 37 38 2.224404
+C42 39 gnd 2.080806f
+R40 38 39 2.224404
+C43 40 gnd 2.080806f
+R41 39 40 2.224404
+C44 41 gnd 2.080806f
+R42 40 41 2.224404
+C45 42 gnd 2.080806f
+R43 41 42 2.224404
+C46 43 gnd 2.080806f
+R44 42 43 2.224404
+C47 44 gnd 2.080806f
+R45 43 44 2.224404
+C48 45 gnd 2.080806f
+R46 44 45 2.224404
+C49 46 gnd 2.080806f
+R47 45 46 2.224404
+C50 47 gnd 2.080806f
+R48 46 47 2.224404
+C51 48 gnd 2.080806f
+R49 47 48 2.224404
+C52 49 gnd 2.080806f
+R50 48 49 2.224404
+C53 50 gnd 2.080806f
+R51 49 50 2.224404
+C54 51 gnd 2.080806f
+R52 50 51 2.224404
+C55 52 gnd 2.080806f
+R53 51 52 2.224404
+C56 53 gnd 2.080806f
+R54 52 53 2.224404
+C57 54 gnd 2.080806f
+R55 53 54 2.224404
+C58 55 gnd 2.080806f
+R56 54 55 2.224404
+C59 56 gnd 2.080806f
+R57 55 56 2.224404
+C60 57 gnd 2.080806f
+R58 56 57 2.224404
+C61 58 gnd 2.080806f
+R59 57 58 2.224404
+C62 59 gnd 2.080806f
+R60 58 59 2.224404
+C63 60 gnd 2.080806f
+R61 59 60 2.224404
+C64 61 gnd 2.080806f
+R62 60 61 2.224404
+C65 62 gnd 2.080806f
+R63 61 62 2.224404
+C66 63 gnd 2.080806f
+R64 62 63 2.224404
+C67 64 gnd 2.080806f
+R65 63 64 2.224404
+C68 65 gnd 2.080806f
+R66 64 65 2.224404
+C69 66 gnd 2.080806f
+R67 65 66 2.224404
+C70 67 gnd 2.080806f
+R68 66 67 2.224404
+C71 68 gnd 2.080806f
+R69 67 68 2.224404
+R70 68 g175_2 2.224404
+.ends
+
+.subckt netg1658 g1658_4 g1658_1 g1658_2 g1658_5 g1658_3 g1658_0 gnd
+C1  g1658_4 gnd 2.080806f
+C2  g1658_1 gnd 2.080806f
+C3  g1658_2 gnd 2.080806f
+C4  g1658_5 gnd 2.080806f
+C5  g1658_3 gnd 2.080806f
+C6  g1658_0 gnd 2.080806f
+R1 g1658_3 g1658_0 2.224404
+C7 1 gnd 2.080806f
+R2 g1658_3 1 2.224404
+C8 2 gnd 2.080806f
+R3 1 2 2.224404
+C9 3 gnd 2.080806f
+R4 3 2 2.224404
+C10 4 gnd 2.080806f
+R5 4 3 2.224404
+C11 5 gnd 2.080806f
+R6 4 5 2.224404
+C12 6 gnd 2.080806f
+R7 6 5 2.224404
+C13 7 gnd 2.080806f
+R8 7 6 2.224404
+C14 8 gnd 2.080806f
+R9 8 7 2.224404
+R10 g1658_1 8 2.224404
+C15 9 gnd 2.080806f
+R11 9 g1658_1 2.224404
+C16 10 gnd 2.080806f
+R12 10 9 2.224404
+C17 11 gnd 2.080806f
+R13 11 10 2.224404
+R14 g1658_2 11 2.224404
+C18 12 gnd 2.080806f
+R15 g1658_0 12 2.224404
+C19 13 gnd 2.080806f
+R16 12 13 2.224404
+C20 14 gnd 2.080806f
+R17 13 14 2.224404
+C21 15 gnd 2.080806f
+R18 14 15 2.224404
+C22 16 gnd 2.080806f
+R19 15 16 2.224404
+C23 17 gnd 2.080806f
+R20 16 17 2.224404
+C24 18 gnd 2.080806f
+R21 17 18 2.224404
+C25 19 gnd 2.080806f
+R22 18 19 2.224404
+C26 20 gnd 2.080806f
+R23 19 20 2.224404
+C27 21 gnd 2.080806f
+R24 20 21 2.224404
+C28 22 gnd 2.080806f
+R25 21 22 2.224404
+C29 23 gnd 2.080806f
+R26 22 23 2.224404
+C30 24 gnd 2.080806f
+R27 23 24 2.224404
+C31 25 gnd 2.080806f
+R28 24 25 2.224404
+C32 26 gnd 2.080806f
+R29 25 26 2.224404
+C33 27 gnd 2.080806f
+R30 26 27 2.224404
+C34 28 gnd 2.080806f
+R31 27 28 2.224404
+C35 29 gnd 2.080806f
+R32 28 29 2.224404
+C36 30 gnd 2.080806f
+R33 29 30 2.224404
+C37 31 gnd 2.080806f
+R34 30 31 2.224404
+C38 32 gnd 2.080806f
+R35 31 32 2.224404
+C39 33 gnd 2.080806f
+R36 32 33 2.224404
+C40 34 gnd 2.080806f
+R37 33 34 2.224404
+C41 35 gnd 2.080806f
+R38 34 35 2.224404
+C42 36 gnd 2.080806f
+R39 35 36 2.224404
+C43 37 gnd 2.080806f
+R40 36 37 2.224404
+C44 38 gnd 2.080806f
+R41 37 38 2.224404
+C45 39 gnd 2.080806f
+R42 38 39 2.224404
+C46 40 gnd 2.080806f
+R43 39 40 2.224404
+C47 41 gnd 2.080806f
+R44 40 41 2.224404
+C48 42 gnd 2.080806f
+R45 41 42 2.224404
+C49 43 gnd 2.080806f
+R46 42 43 2.224404
+C50 44 gnd 2.080806f
+R47 43 44 2.224404
+C51 45 gnd 2.080806f
+R48 44 45 2.224404
+C52 46 gnd 2.080806f
+R49 45 46 2.224404
+C53 47 gnd 2.080806f
+R50 46 47 2.224404
+C54 48 gnd 2.080806f
+R51 47 48 2.224404
+C55 49 gnd 2.080806f
+R52 48 49 2.224404
+C56 50 gnd 2.080806f
+R53 49 50 2.224404
+C57 51 gnd 2.080806f
+R54 50 51 2.224404
+C58 52 gnd 2.080806f
+R55 51 52 2.224404
+C59 53 gnd 2.080806f
+R56 52 53 2.224404
+C60 54 gnd 2.080806f
+R57 53 54 2.224404
+C61 55 gnd 2.080806f
+R58 54 55 2.224404
+C62 56 gnd 2.080806f
+R59 55 56 2.224404
+C63 57 gnd 2.080806f
+R60 56 57 2.224404
+C64 58 gnd 2.080806f
+R61 57 58 2.224404
+C65 59 gnd 2.080806f
+R62 58 59 2.224404
+C66 60 gnd 2.080806f
+R63 59 60 2.224404
+C67 61 gnd 2.080806f
+R64 60 61 2.224404
+C68 62 gnd 2.080806f
+R65 61 62 2.224404
+C69 63 gnd 2.080806f
+R66 62 63 2.224404
+C70 64 gnd 2.080806f
+R67 63 64 2.224404
+C71 65 gnd 2.080806f
+R68 65 64 2.224404
+C72 66 gnd 2.080806f
+R69 66 65 2.224404
+C73 67 gnd 2.080806f
+R70 66 67 2.224404
+R71 67 g1658_4 2.224404
+C74 68 gnd 2.080806f
+R72 g1658_4 68 2.224404
+C75 69 gnd 2.080806f
+R73 68 69 2.224404
+C76 70 gnd 2.080806f
+R74 69 70 2.224404
+C77 71 gnd 2.080806f
+R75 70 71 2.224404
+C78 72 gnd 2.080806f
+R76 71 72 2.224404
+C79 73 gnd 2.080806f
+R77 72 73 2.224404
+C80 74 gnd 2.080806f
+R78 73 74 2.224404
+R79 74 g1658_5 2.224404
+.ends
+
+.subckt netg7454 g7454_0 g7454_1 gnd
+C1  g7454_0 gnd 2.080806f
+C2  g7454_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7454_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+C50 48 gnd 2.080806f
+R48 47 48 2.224404
+C51 49 gnd 2.080806f
+R49 49 48 2.224404
+C52 50 gnd 2.080806f
+R50 50 49 2.224404
+C53 51 gnd 2.080806f
+R51 51 50 2.224404
+C54 52 gnd 2.080806f
+R52 52 51 2.224404
+C55 53 gnd 2.080806f
+R53 52 53 2.224404
+C56 54 gnd 2.080806f
+R54 53 54 2.224404
+C57 55 gnd 2.080806f
+R55 54 55 2.224404
+C58 56 gnd 2.080806f
+R56 55 56 2.224404
+C59 57 gnd 2.080806f
+R57 56 57 2.224404
+C60 58 gnd 2.080806f
+R58 58 57 2.224404
+C61 59 gnd 2.080806f
+R59 59 58 2.224404
+C62 60 gnd 2.080806f
+R60 60 59 2.224404
+C63 61 gnd 2.080806f
+R61 60 61 2.224404
+C64 62 gnd 2.080806f
+R62 61 62 2.224404
+C65 63 gnd 2.080806f
+R63 62 63 2.224404
+C66 64 gnd 2.080806f
+R64 63 64 2.224404
+C67 65 gnd 2.080806f
+R65 64 65 2.224404
+C68 66 gnd 2.080806f
+R66 65 66 2.224404
+C69 67 gnd 2.080806f
+R67 67 66 2.224404
+C70 68 gnd 2.080806f
+R68 68 67 2.224404
+C71 69 gnd 2.080806f
+R69 68 69 2.224404
+C72 70 gnd 2.080806f
+R70 70 69 2.224404
+R71 g7454_1 70 2.224404
+.ends
+
+.subckt netg168 g168_2 g168_1 g168_0 gnd
+C1  g168_2 gnd 2.080806f
+C2  g168_1 gnd 2.080806f
+C3  g168_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g168_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 6 5 2.224404
+C10 7 gnd 2.080806f
+R7 7 6 2.224404
+C11 8 gnd 2.080806f
+R8 8 7 2.224404
+C12 9 gnd 2.080806f
+R9 9 8 2.224404
+C13 10 gnd 2.080806f
+R10 10 9 2.224404
+C14 11 gnd 2.080806f
+R11 11 10 2.224404
+C15 12 gnd 2.080806f
+R12 12 11 2.224404
+C16 13 gnd 2.080806f
+R13 13 12 2.224404
+C17 14 gnd 2.080806f
+R14 14 13 2.224404
+C18 15 gnd 2.080806f
+R15 15 14 2.224404
+C19 16 gnd 2.080806f
+R16 16 15 2.224404
+C20 17 gnd 2.080806f
+R17 17 16 2.224404
+C21 18 gnd 2.080806f
+R18 18 17 2.224404
+C22 19 gnd 2.080806f
+R19 19 18 2.224404
+C23 20 gnd 2.080806f
+R20 20 19 2.224404
+C24 21 gnd 2.080806f
+R21 21 20 2.224404
+C25 22 gnd 2.080806f
+R22 22 21 2.224404
+C26 23 gnd 2.080806f
+R23 23 22 2.224404
+C27 24 gnd 2.080806f
+R24 24 23 2.224404
+C28 25 gnd 2.080806f
+R25 25 24 2.224404
+C29 26 gnd 2.080806f
+R26 26 25 2.224404
+C30 27 gnd 2.080806f
+R27 27 26 2.224404
+C31 28 gnd 2.080806f
+R28 28 27 2.224404
+C32 29 gnd 2.080806f
+R29 29 28 2.224404
+C33 30 gnd 2.080806f
+R30 30 29 2.224404
+C34 31 gnd 2.080806f
+R31 31 30 2.224404
+C35 32 gnd 2.080806f
+R32 32 31 2.224404
+C36 33 gnd 2.080806f
+R33 33 32 2.224404
+C37 34 gnd 2.080806f
+R34 34 33 2.224404
+C38 35 gnd 2.080806f
+R35 35 34 2.224404
+C39 36 gnd 2.080806f
+R36 36 35 2.224404
+C40 37 gnd 2.080806f
+R37 37 36 2.224404
+C41 38 gnd 2.080806f
+R38 38 37 2.224404
+C42 39 gnd 2.080806f
+R39 39 38 2.224404
+C43 40 gnd 2.080806f
+R40 40 39 2.224404
+C44 41 gnd 2.080806f
+R41 41 40 2.224404
+C45 42 gnd 2.080806f
+R42 42 41 2.224404
+C46 43 gnd 2.080806f
+R43 43 42 2.224404
+C47 44 gnd 2.080806f
+R44 44 43 2.224404
+C48 45 gnd 2.080806f
+R45 45 44 2.224404
+C49 46 gnd 2.080806f
+R46 46 45 2.224404
+C50 47 gnd 2.080806f
+R47 47 46 2.224404
+C51 48 gnd 2.080806f
+R48 48 47 2.224404
+C52 49 gnd 2.080806f
+R49 49 48 2.224404
+C53 50 gnd 2.080806f
+R50 50 49 2.224404
+R51 g168_1 50 2.224404
+C54 51 gnd 2.080806f
+R52 51 g168_1 2.224404
+C55 52 gnd 2.080806f
+R53 52 51 2.224404
+C56 53 gnd 2.080806f
+R54 53 52 2.224404
+C57 54 gnd 2.080806f
+R55 54 53 2.224404
+C58 55 gnd 2.080806f
+R56 55 54 2.224404
+C59 56 gnd 2.080806f
+R57 56 55 2.224404
+C60 57 gnd 2.080806f
+R58 57 56 2.224404
+C61 58 gnd 2.080806f
+R59 58 57 2.224404
+C62 59 gnd 2.080806f
+R60 59 58 2.224404
+C63 60 gnd 2.080806f
+R61 60 59 2.224404
+C64 61 gnd 2.080806f
+R62 61 60 2.224404
+C65 62 gnd 2.080806f
+R63 62 61 2.224404
+C66 63 gnd 2.080806f
+R64 63 62 2.224404
+C67 64 gnd 2.080806f
+R65 64 63 2.224404
+C68 65 gnd 2.080806f
+R66 65 64 2.224404
+C69 66 gnd 2.080806f
+R67 66 65 2.224404
+C70 67 gnd 2.080806f
+R68 67 66 2.224404
+C71 68 gnd 2.080806f
+R69 68 67 2.224404
+C72 69 gnd 2.080806f
+R70 69 68 2.224404
+R71 g168_2 69 2.224404
+.ends
+
+.subckt netg1646 g1646_2 g1646_0 g1646_4 g1646_5 g1646_3 g1646_1 gnd
+C1  g1646_2 gnd 2.080806f
+C2  g1646_0 gnd 2.080806f
+C3  g1646_4 gnd 2.080806f
+C4  g1646_5 gnd 2.080806f
+C5  g1646_3 gnd 2.080806f
+C6  g1646_1 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 g1646_0 1 2.224404
+C8 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g1646_2 2.224404
+C9 3 gnd 2.080806f
+R4 3 g1646_2 2.224404
+C10 4 gnd 2.080806f
+R5 3 4 2.224404
+C11 5 gnd 2.080806f
+R6 4 5 2.224404
+C12 6 gnd 2.080806f
+R7 5 6 2.224404
+C13 7 gnd 2.080806f
+R8 6 7 2.224404
+C14 8 gnd 2.080806f
+R9 7 8 2.224404
+R10 8 g1646_1 2.224404
+C15 9 gnd 2.080806f
+R11 g1646_1 9 2.224404
+C16 10 gnd 2.080806f
+R12 9 10 2.224404
+C17 11 gnd 2.080806f
+R13 10 11 2.224404
+C18 12 gnd 2.080806f
+R14 11 12 2.224404
+C19 13 gnd 2.080806f
+R15 12 13 2.224404
+C20 14 gnd 2.080806f
+R16 13 14 2.224404
+C21 15 gnd 2.080806f
+R17 14 15 2.224404
+C22 16 gnd 2.080806f
+R18 15 16 2.224404
+C23 17 gnd 2.080806f
+R19 16 17 2.224404
+R20 17 g1646_3 2.224404
+C24 18 gnd 2.080806f
+R21 g1646_3 18 2.224404
+C25 19 gnd 2.080806f
+R22 18 19 2.224404
+C26 20 gnd 2.080806f
+R23 19 20 2.224404
+C27 21 gnd 2.080806f
+R24 20 21 2.224404
+C28 22 gnd 2.080806f
+R25 21 22 2.224404
+C29 23 gnd 2.080806f
+R26 22 23 2.224404
+C30 24 gnd 2.080806f
+R27 23 24 2.224404
+C31 25 gnd 2.080806f
+R28 24 25 2.224404
+C32 26 gnd 2.080806f
+R29 25 26 2.224404
+C33 27 gnd 2.080806f
+R30 26 27 2.224404
+C34 28 gnd 2.080806f
+R31 27 28 2.224404
+C35 29 gnd 2.080806f
+R32 28 29 2.224404
+C36 30 gnd 2.080806f
+R33 29 30 2.224404
+C37 31 gnd 2.080806f
+R34 30 31 2.224404
+C38 32 gnd 2.080806f
+R35 31 32 2.224404
+C39 33 gnd 2.080806f
+R36 32 33 2.224404
+C40 34 gnd 2.080806f
+R37 33 34 2.224404
+C41 35 gnd 2.080806f
+R38 34 35 2.224404
+C42 36 gnd 2.080806f
+R39 35 36 2.224404
+C43 37 gnd 2.080806f
+R40 36 37 2.224404
+C44 38 gnd 2.080806f
+R41 37 38 2.224404
+C45 39 gnd 2.080806f
+R42 38 39 2.224404
+C46 40 gnd 2.080806f
+R43 39 40 2.224404
+C47 41 gnd 2.080806f
+R44 40 41 2.224404
+C48 42 gnd 2.080806f
+R45 41 42 2.224404
+C49 43 gnd 2.080806f
+R46 42 43 2.224404
+C50 44 gnd 2.080806f
+R47 43 44 2.224404
+C51 45 gnd 2.080806f
+R48 44 45 2.224404
+C52 46 gnd 2.080806f
+R49 45 46 2.224404
+C53 47 gnd 2.080806f
+R50 46 47 2.224404
+C54 48 gnd 2.080806f
+R51 47 48 2.224404
+C55 49 gnd 2.080806f
+R52 48 49 2.224404
+C56 50 gnd 2.080806f
+R53 49 50 2.224404
+C57 51 gnd 2.080806f
+R54 50 51 2.224404
+C58 52 gnd 2.080806f
+R55 51 52 2.224404
+C59 53 gnd 2.080806f
+R56 52 53 2.224404
+C60 54 gnd 2.080806f
+R57 53 54 2.224404
+C61 55 gnd 2.080806f
+R58 54 55 2.224404
+C62 56 gnd 2.080806f
+R59 55 56 2.224404
+C63 57 gnd 2.080806f
+R60 56 57 2.224404
+C64 58 gnd 2.080806f
+R61 57 58 2.224404
+C65 59 gnd 2.080806f
+R62 58 59 2.224404
+C66 60 gnd 2.080806f
+R63 59 60 2.224404
+C67 61 gnd 2.080806f
+R64 60 61 2.224404
+C68 62 gnd 2.080806f
+R65 61 62 2.224404
+C69 63 gnd 2.080806f
+R66 62 63 2.224404
+C70 64 gnd 2.080806f
+R67 63 64 2.224404
+C71 65 gnd 2.080806f
+R68 65 64 2.224404
+C72 66 gnd 2.080806f
+R69 66 65 2.224404
+C73 67 gnd 2.080806f
+R70 66 67 2.224404
+C74 68 gnd 2.080806f
+R71 68 67 2.224404
+C75 69 gnd 2.080806f
+R72 68 69 2.224404
+C76 70 gnd 2.080806f
+R73 69 70 2.224404
+C77 71 gnd 2.080806f
+R74 70 71 2.224404
+R75 g1646_5 71 2.224404
+C78 72 gnd 2.080806f
+R76 g1646_5 72 2.224404
+C79 73 gnd 2.080806f
+R77 72 73 2.224404
+C80 74 gnd 2.080806f
+R78 73 74 2.224404
+C81 75 gnd 2.080806f
+R79 74 75 2.224404
+R80 75 g1646_4 2.224404
+.ends
+
+.subckt netg7486 g7486_1 g7486_0 gnd
+C1  g7486_1 gnd 2.080806f
+C2  g7486_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7486_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+C50 48 gnd 2.080806f
+R48 48 47 2.224404
+C51 49 gnd 2.080806f
+R49 49 48 2.224404
+C52 50 gnd 2.080806f
+R50 50 49 2.224404
+C53 51 gnd 2.080806f
+R51 51 50 2.224404
+C54 52 gnd 2.080806f
+R52 52 51 2.224404
+C55 53 gnd 2.080806f
+R53 53 52 2.224404
+C56 54 gnd 2.080806f
+R54 54 53 2.224404
+C57 55 gnd 2.080806f
+R55 55 54 2.224404
+C58 56 gnd 2.080806f
+R56 56 55 2.224404
+C59 57 gnd 2.080806f
+R57 57 56 2.224404
+C60 58 gnd 2.080806f
+R58 58 57 2.224404
+C61 59 gnd 2.080806f
+R59 59 58 2.224404
+C62 60 gnd 2.080806f
+R60 60 59 2.224404
+C63 61 gnd 2.080806f
+R61 61 60 2.224404
+C64 62 gnd 2.080806f
+R62 62 61 2.224404
+C65 63 gnd 2.080806f
+R63 63 62 2.224404
+C66 64 gnd 2.080806f
+R64 64 63 2.224404
+C67 65 gnd 2.080806f
+R65 65 64 2.224404
+C68 66 gnd 2.080806f
+R66 66 65 2.224404
+C69 67 gnd 2.080806f
+R67 67 66 2.224404
+C70 68 gnd 2.080806f
+R68 68 67 2.224404
+C71 69 gnd 2.080806f
+R69 69 68 2.224404
+C72 70 gnd 2.080806f
+R70 70 69 2.224404
+C73 71 gnd 2.080806f
+R71 71 70 2.224404
+R72 g7486_1 71 2.224404
+.ends
+
+.subckt netg470 g470_1 g470_0 g470_2 gnd
+C1  g470_1 gnd 2.080806f
+C2  g470_0 gnd 2.080806f
+C3  g470_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g470_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 5 6 2.224404
+R7 g470_1 6 2.224404
+C10 7 gnd 2.080806f
+R8 g470_0 7 2.224404
+C11 8 gnd 2.080806f
+R9 7 8 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 11 10 2.224404
+C15 12 gnd 2.080806f
+R13 12 11 2.224404
+C16 13 gnd 2.080806f
+R14 12 13 2.224404
+C17 14 gnd 2.080806f
+R15 13 14 2.224404
+C18 15 gnd 2.080806f
+R16 14 15 2.224404
+C19 16 gnd 2.080806f
+R17 15 16 2.224404
+C20 17 gnd 2.080806f
+R18 16 17 2.224404
+C21 18 gnd 2.080806f
+R19 18 17 2.224404
+C22 19 gnd 2.080806f
+R20 18 19 2.224404
+C23 20 gnd 2.080806f
+R21 19 20 2.224404
+C24 21 gnd 2.080806f
+R22 21 20 2.224404
+C25 22 gnd 2.080806f
+R23 21 22 2.224404
+C26 23 gnd 2.080806f
+R24 22 23 2.224404
+C27 24 gnd 2.080806f
+R25 23 24 2.224404
+C28 25 gnd 2.080806f
+R26 24 25 2.224404
+C29 26 gnd 2.080806f
+R27 25 26 2.224404
+C30 27 gnd 2.080806f
+R28 27 26 2.224404
+C31 28 gnd 2.080806f
+R29 28 27 2.224404
+C32 29 gnd 2.080806f
+R30 29 28 2.224404
+C33 30 gnd 2.080806f
+R31 30 29 2.224404
+C34 31 gnd 2.080806f
+R32 31 30 2.224404
+C35 32 gnd 2.080806f
+R33 32 31 2.224404
+C36 33 gnd 2.080806f
+R34 33 32 2.224404
+C37 34 gnd 2.080806f
+R35 34 33 2.224404
+C38 35 gnd 2.080806f
+R36 34 35 2.224404
+C39 36 gnd 2.080806f
+R37 35 36 2.224404
+C40 37 gnd 2.080806f
+R38 36 37 2.224404
+C41 38 gnd 2.080806f
+R39 37 38 2.224404
+C42 39 gnd 2.080806f
+R40 38 39 2.224404
+C43 40 gnd 2.080806f
+R41 39 40 2.224404
+C44 41 gnd 2.080806f
+R42 40 41 2.224404
+C45 42 gnd 2.080806f
+R43 41 42 2.224404
+C46 43 gnd 2.080806f
+R44 42 43 2.224404
+C47 44 gnd 2.080806f
+R45 43 44 2.224404
+C48 45 gnd 2.080806f
+R46 44 45 2.224404
+C49 46 gnd 2.080806f
+R47 45 46 2.224404
+C50 47 gnd 2.080806f
+R48 46 47 2.224404
+C51 48 gnd 2.080806f
+R49 47 48 2.224404
+C52 49 gnd 2.080806f
+R50 48 49 2.224404
+C53 50 gnd 2.080806f
+R51 50 49 2.224404
+C54 51 gnd 2.080806f
+R52 50 51 2.224404
+C55 52 gnd 2.080806f
+R53 51 52 2.224404
+C56 53 gnd 2.080806f
+R54 53 52 2.224404
+C57 54 gnd 2.080806f
+R55 53 54 2.224404
+C58 55 gnd 2.080806f
+R56 55 54 2.224404
+C59 56 gnd 2.080806f
+R57 56 55 2.224404
+C60 57 gnd 2.080806f
+R58 56 57 2.224404
+C61 58 gnd 2.080806f
+R59 57 58 2.224404
+C62 59 gnd 2.080806f
+R60 58 59 2.224404
+C63 60 gnd 2.080806f
+R61 59 60 2.224404
+C64 61 gnd 2.080806f
+R62 61 60 2.224404
+C65 62 gnd 2.080806f
+R63 61 62 2.224404
+C66 63 gnd 2.080806f
+R64 62 63 2.224404
+C67 64 gnd 2.080806f
+R65 63 64 2.224404
+C68 65 gnd 2.080806f
+R66 65 64 2.224404
+C69 66 gnd 2.080806f
+R67 65 66 2.224404
+C70 67 gnd 2.080806f
+R68 66 67 2.224404
+C71 68 gnd 2.080806f
+R69 68 67 2.224404
+C72 69 gnd 2.080806f
+R70 68 69 2.224404
+C73 70 gnd 2.080806f
+R71 69 70 2.224404
+R72 70 g470_2 2.224404
+.ends
+
+.subckt netg7455 g7455_0 g7455_1 gnd
+C1  g7455_0 gnd 2.080806f
+C2  g7455_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7455_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+C50 48 gnd 2.080806f
+R48 48 47 2.224404
+C51 49 gnd 2.080806f
+R49 49 48 2.224404
+C52 50 gnd 2.080806f
+R50 50 49 2.224404
+C53 51 gnd 2.080806f
+R51 51 50 2.224404
+C54 52 gnd 2.080806f
+R52 52 51 2.224404
+C55 53 gnd 2.080806f
+R53 53 52 2.224404
+C56 54 gnd 2.080806f
+R54 54 53 2.224404
+C57 55 gnd 2.080806f
+R55 55 54 2.224404
+C58 56 gnd 2.080806f
+R56 56 55 2.224404
+C59 57 gnd 2.080806f
+R57 57 56 2.224404
+C60 58 gnd 2.080806f
+R58 58 57 2.224404
+C61 59 gnd 2.080806f
+R59 59 58 2.224404
+C62 60 gnd 2.080806f
+R60 60 59 2.224404
+C63 61 gnd 2.080806f
+R61 61 60 2.224404
+C64 62 gnd 2.080806f
+R62 61 62 2.224404
+C65 63 gnd 2.080806f
+R63 62 63 2.224404
+C66 64 gnd 2.080806f
+R64 64 63 2.224404
+C67 65 gnd 2.080806f
+R65 65 64 2.224404
+C68 66 gnd 2.080806f
+R66 66 65 2.224404
+C69 67 gnd 2.080806f
+R67 67 66 2.224404
+C70 68 gnd 2.080806f
+R68 68 67 2.224404
+C71 69 gnd 2.080806f
+R69 69 68 2.224404
+C72 70 gnd 2.080806f
+R70 70 69 2.224404
+C73 71 gnd 2.080806f
+R71 70 71 2.224404
+C74 72 gnd 2.080806f
+R72 71 72 2.224404
+R73 72 g7455_1 2.224404
+.ends
+
+.subckt netg473 g473_4 g473_3 g473_0 g473_5 g473_2 g473_1 gnd
+C1  g473_4 gnd 2.080806f
+C2  g473_3 gnd 2.080806f
+C3  g473_0 gnd 2.080806f
+C4  g473_5 gnd 2.080806f
+C5  g473_2 gnd 2.080806f
+C6  g473_1 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 g473_0 1 2.224404
+C8 2 gnd 2.080806f
+R2 1 2 2.224404
+C9 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g473_4 2.224404
+C10 4 gnd 2.080806f
+R5 g473_4 4 2.224404
+C11 5 gnd 2.080806f
+R6 4 5 2.224404
+C12 6 gnd 2.080806f
+R7 5 6 2.224404
+C13 7 gnd 2.080806f
+R8 6 7 2.224404
+C14 8 gnd 2.080806f
+R9 7 8 2.224404
+C15 9 gnd 2.080806f
+R10 8 9 2.224404
+C16 10 gnd 2.080806f
+R11 9 10 2.224404
+C17 11 gnd 2.080806f
+R12 10 11 2.224404
+C18 12 gnd 2.080806f
+R13 11 12 2.224404
+R14 12 g473_3 2.224404
+C19 13 gnd 2.080806f
+R15 13 12 2.224404
+C20 14 gnd 2.080806f
+R16 13 14 2.224404
+C21 15 gnd 2.080806f
+R17 15 14 2.224404
+C22 16 gnd 2.080806f
+R18 16 15 2.224404
+C23 17 gnd 2.080806f
+R19 17 16 2.224404
+C24 18 gnd 2.080806f
+R20 18 17 2.224404
+C25 19 gnd 2.080806f
+R21 19 18 2.224404
+C26 20 gnd 2.080806f
+R22 19 20 2.224404
+C27 21 gnd 2.080806f
+R23 21 20 2.224404
+C28 22 gnd 2.080806f
+R24 21 22 2.224404
+C29 23 gnd 2.080806f
+R25 22 23 2.224404
+C30 24 gnd 2.080806f
+R26 24 23 2.224404
+C31 25 gnd 2.080806f
+R27 24 25 2.224404
+C32 26 gnd 2.080806f
+R28 25 26 2.224404
+C33 27 gnd 2.080806f
+R29 27 26 2.224404
+C34 28 gnd 2.080806f
+R30 27 28 2.224404
+R31 g473_2 28 2.224404
+C35 29 gnd 2.080806f
+R32 29 g473_4 2.224404
+C36 30 gnd 2.080806f
+R33 29 30 2.224404
+C37 31 gnd 2.080806f
+R34 30 31 2.224404
+C38 32 gnd 2.080806f
+R35 31 32 2.224404
+C39 33 gnd 2.080806f
+R36 32 33 2.224404
+C40 34 gnd 2.080806f
+R37 33 34 2.224404
+C41 35 gnd 2.080806f
+R38 35 34 2.224404
+C42 36 gnd 2.080806f
+R39 35 36 2.224404
+C43 37 gnd 2.080806f
+R40 36 37 2.224404
+C44 38 gnd 2.080806f
+R41 37 38 2.224404
+C45 39 gnd 2.080806f
+R42 38 39 2.224404
+C46 40 gnd 2.080806f
+R43 39 40 2.224404
+C47 41 gnd 2.080806f
+R44 40 41 2.224404
+C48 42 gnd 2.080806f
+R45 41 42 2.224404
+C49 43 gnd 2.080806f
+R46 42 43 2.224404
+C50 44 gnd 2.080806f
+R47 43 44 2.224404
+C51 45 gnd 2.080806f
+R48 44 45 2.224404
+C52 46 gnd 2.080806f
+R49 45 46 2.224404
+C53 47 gnd 2.080806f
+R50 46 47 2.224404
+C54 48 gnd 2.080806f
+R51 47 48 2.224404
+C55 49 gnd 2.080806f
+R52 48 49 2.224404
+C56 50 gnd 2.080806f
+R53 49 50 2.224404
+C57 51 gnd 2.080806f
+R54 50 51 2.224404
+C58 52 gnd 2.080806f
+R55 51 52 2.224404
+C59 53 gnd 2.080806f
+R56 52 53 2.224404
+C60 54 gnd 2.080806f
+R57 53 54 2.224404
+C61 55 gnd 2.080806f
+R58 54 55 2.224404
+C62 56 gnd 2.080806f
+R59 55 56 2.224404
+C63 57 gnd 2.080806f
+R60 56 57 2.224404
+C64 58 gnd 2.080806f
+R61 57 58 2.224404
+C65 59 gnd 2.080806f
+R62 58 59 2.224404
+C66 60 gnd 2.080806f
+R63 59 60 2.224404
+C67 61 gnd 2.080806f
+R64 60 61 2.224404
+C68 62 gnd 2.080806f
+R65 61 62 2.224404
+C69 63 gnd 2.080806f
+R66 62 63 2.224404
+C70 64 gnd 2.080806f
+R67 63 64 2.224404
+C71 65 gnd 2.080806f
+R68 64 65 2.224404
+C72 66 gnd 2.080806f
+R69 65 66 2.224404
+C73 67 gnd 2.080806f
+R70 66 67 2.224404
+C74 68 gnd 2.080806f
+R71 68 67 2.224404
+C75 69 gnd 2.080806f
+R72 69 68 2.224404
+C76 70 gnd 2.080806f
+R73 69 70 2.224404
+C77 71 gnd 2.080806f
+R74 71 70 2.224404
+C78 72 gnd 2.080806f
+R75 71 72 2.224404
+C79 73 gnd 2.080806f
+R76 72 73 2.224404
+R77 g473_1 73 2.224404
+C80 74 gnd 2.080806f
+R78 73 74 2.224404
+C81 75 gnd 2.080806f
+R79 74 75 2.224404
+C82 76 gnd 2.080806f
+R80 75 76 2.224404
+C83 77 gnd 2.080806f
+R81 76 77 2.224404
+C84 78 gnd 2.080806f
+R82 77 78 2.224404
+C85 79 gnd 2.080806f
+R83 78 79 2.224404
+C86 80 gnd 2.080806f
+R84 79 80 2.224404
+C87 81 gnd 2.080806f
+R85 80 81 2.224404
+C88 82 gnd 2.080806f
+R86 81 82 2.224404
+C89 83 gnd 2.080806f
+R87 82 83 2.224404
+C90 84 gnd 2.080806f
+R88 83 84 2.224404
+C91 85 gnd 2.080806f
+R89 84 85 2.224404
+C92 86 gnd 2.080806f
+R90 85 86 2.224404
+C93 87 gnd 2.080806f
+R91 86 87 2.224404
+C94 88 gnd 2.080806f
+R92 87 88 2.224404
+C95 89 gnd 2.080806f
+R93 88 89 2.224404
+C96 90 gnd 2.080806f
+R94 89 90 2.224404
+C97 91 gnd 2.080806f
+R95 90 91 2.224404
+C98 92 gnd 2.080806f
+R96 91 92 2.224404
+C99 93 gnd 2.080806f
+R97 92 93 2.224404
+C100 94 gnd 2.080806f
+R98 93 94 2.224404
+C101 95 gnd 2.080806f
+R99 94 95 2.224404
+C102 96 gnd 2.080806f
+R100 95 96 2.224404
+R101 96 g473_5 2.224404
+.ends
+
+.subckt netg1638 g1638_4 g1638_2 g1638_0 g1638_7 g1638_1 g1638_5 g1638_3 gnd
+C1  g1638_4 gnd 2.080806f
+C2  g1638_2 gnd 2.080806f
+C3  g1638_0 gnd 2.080806f
+C4  g1638_7 gnd 2.080806f
+C5  g1638_1 gnd 2.080806f
+C6  g1638_5 gnd 2.080806f
+C7  g1638_3 gnd 2.080806f
+C8 1 gnd 2.080806f
+R1 g1638_0 1 2.224404
+C9 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g1638_4 2.224404
+C10 3 gnd 2.080806f
+R4 g1638_4 3 2.224404
+C11 4 gnd 2.080806f
+R5 3 4 2.224404
+C12 5 gnd 2.080806f
+R6 4 5 2.224404
+R7 5 g1638_3 2.224404
+C13 6 gnd 2.080806f
+R8 6 g1638_0 2.224404
+C14 7 gnd 2.080806f
+R9 7 6 2.224404
+C15 8 gnd 2.080806f
+R10 8 7 2.224404
+C16 9 gnd 2.080806f
+R11 9 8 2.224404
+C17 10 gnd 2.080806f
+R12 10 9 2.224404
+C18 11 gnd 2.080806f
+R13 11 10 2.224404
+C19 12 gnd 2.080806f
+R14 12 11 2.224404
+C20 13 gnd 2.080806f
+R15 13 12 2.224404
+C21 14 gnd 2.080806f
+R16 14 13 2.224404
+C22 15 gnd 2.080806f
+R17 15 14 2.224404
+C23 16 gnd 2.080806f
+R18 16 15 2.224404
+C24 17 gnd 2.080806f
+R19 17 16 2.224404
+C25 18 gnd 2.080806f
+R20 18 17 2.224404
+C26 19 gnd 2.080806f
+R21 19 18 2.224404
+R22 g1638_7 19 2.224404
+R23 g1638_5 g1638_7 2.224404
+C27 20 gnd 2.080806f
+R24 g1638_3 20 2.224404
+C28 21 gnd 2.080806f
+R25 20 21 2.224404
+C29 22 gnd 2.080806f
+R26 21 22 2.224404
+C30 23 gnd 2.080806f
+R27 22 23 2.224404
+C31 24 gnd 2.080806f
+R28 23 24 2.224404
+C32 25 gnd 2.080806f
+R29 24 25 2.224404
+C33 26 gnd 2.080806f
+R30 25 26 2.224404
+C34 27 gnd 2.080806f
+R31 26 27 2.224404
+C35 28 gnd 2.080806f
+R32 27 28 2.224404
+C36 29 gnd 2.080806f
+R33 28 29 2.224404
+C37 30 gnd 2.080806f
+R34 29 30 2.224404
+C38 31 gnd 2.080806f
+R35 30 31 2.224404
+C39 32 gnd 2.080806f
+R36 31 32 2.224404
+C40 33 gnd 2.080806f
+R37 32 33 2.224404
+C41 34 gnd 2.080806f
+R38 33 34 2.224404
+C42 35 gnd 2.080806f
+R39 34 35 2.224404
+C43 36 gnd 2.080806f
+R40 35 36 2.224404
+C44 37 gnd 2.080806f
+R41 36 37 2.224404
+C45 38 gnd 2.080806f
+R42 37 38 2.224404
+C46 39 gnd 2.080806f
+R43 38 39 2.224404
+C47 40 gnd 2.080806f
+R44 39 40 2.224404
+C48 41 gnd 2.080806f
+R45 40 41 2.224404
+C49 42 gnd 2.080806f
+R46 41 42 2.224404
+C50 43 gnd 2.080806f
+R47 43 42 2.224404
+C51 44 gnd 2.080806f
+R48 43 44 2.224404
+C52 45 gnd 2.080806f
+R49 44 45 2.224404
+C53 46 gnd 2.080806f
+R50 46 45 2.224404
+C54 47 gnd 2.080806f
+R51 46 47 2.224404
+C55 48 gnd 2.080806f
+R52 47 48 2.224404
+C56 49 gnd 2.080806f
+R53 48 49 2.224404
+C57 50 gnd 2.080806f
+R54 49 50 2.224404
+C58 51 gnd 2.080806f
+R55 50 51 2.224404
+C59 52 gnd 2.080806f
+R56 51 52 2.224404
+C60 53 gnd 2.080806f
+R57 52 53 2.224404
+C61 54 gnd 2.080806f
+R58 53 54 2.224404
+C62 55 gnd 2.080806f
+R59 54 55 2.224404
+C63 56 gnd 2.080806f
+R60 55 56 2.224404
+C64 57 gnd 2.080806f
+R61 56 57 2.224404
+C65 58 gnd 2.080806f
+R62 57 58 2.224404
+C66 59 gnd 2.080806f
+R63 58 59 2.224404
+C67 60 gnd 2.080806f
+R64 59 60 2.224404
+C68 61 gnd 2.080806f
+R65 60 61 2.224404
+C69 62 gnd 2.080806f
+R66 61 62 2.224404
+C70 63 gnd 2.080806f
+R67 62 63 2.224404
+C71 64 gnd 2.080806f
+R68 63 64 2.224404
+C72 65 gnd 2.080806f
+R69 64 65 2.224404
+C73 66 gnd 2.080806f
+R70 65 66 2.224404
+C74 67 gnd 2.080806f
+R71 67 66 2.224404
+C75 68 gnd 2.080806f
+R72 68 67 2.224404
+C76 69 gnd 2.080806f
+R73 68 69 2.224404
+C77 70 gnd 2.080806f
+R74 69 70 2.224404
+C78 71 gnd 2.080806f
+R75 70 71 2.224404
+C79 72 gnd 2.080806f
+R76 71 72 2.224404
+C80 73 gnd 2.080806f
+R77 72 73 2.224404
+C81 74 gnd 2.080806f
+R78 73 74 2.224404
+C82 75 gnd 2.080806f
+R79 74 75 2.224404
+C83 76 gnd 2.080806f
+R80 76 75 2.224404
+C84 77 gnd 2.080806f
+R81 77 76 2.224404
+C85 78 gnd 2.080806f
+R82 78 77 2.224404
+C86 79 gnd 2.080806f
+R83 79 78 2.224404
+R84 79 g1638_1 2.224404
+C87 80 gnd 2.080806f
+R85 80 g1638_1 2.224404
+C88 81 gnd 2.080806f
+R86 80 81 2.224404
+C89 82 gnd 2.080806f
+R87 81 82 2.224404
+C90 83 gnd 2.080806f
+R88 83 82 2.224404
+C91 84 gnd 2.080806f
+R89 84 83 2.224404
+R90 g1638_2 84 2.224404
+.ends
+
+.subckt netg7470 g7470_1 g7470_0 gnd
+C1  g7470_1 gnd 2.080806f
+C2  g7470_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7470_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+C50 48 gnd 2.080806f
+R48 48 47 2.224404
+C51 49 gnd 2.080806f
+R49 48 49 2.224404
+C52 50 gnd 2.080806f
+R50 49 50 2.224404
+C53 51 gnd 2.080806f
+R51 50 51 2.224404
+C54 52 gnd 2.080806f
+R52 51 52 2.224404
+C55 53 gnd 2.080806f
+R53 52 53 2.224404
+C56 54 gnd 2.080806f
+R54 53 54 2.224404
+C57 55 gnd 2.080806f
+R55 54 55 2.224404
+C58 56 gnd 2.080806f
+R56 56 55 2.224404
+C59 57 gnd 2.080806f
+R57 56 57 2.224404
+C60 58 gnd 2.080806f
+R58 58 57 2.224404
+C61 59 gnd 2.080806f
+R59 59 58 2.224404
+C62 60 gnd 2.080806f
+R60 60 59 2.224404
+C63 61 gnd 2.080806f
+R61 61 60 2.224404
+C64 62 gnd 2.080806f
+R62 62 61 2.224404
+C65 63 gnd 2.080806f
+R63 63 62 2.224404
+C66 64 gnd 2.080806f
+R64 63 64 2.224404
+C67 65 gnd 2.080806f
+R65 64 65 2.224404
+C68 66 gnd 2.080806f
+R66 66 65 2.224404
+C69 67 gnd 2.080806f
+R67 67 66 2.224404
+C70 68 gnd 2.080806f
+R68 68 67 2.224404
+C71 69 gnd 2.080806f
+R69 69 68 2.224404
+C72 70 gnd 2.080806f
+R70 70 69 2.224404
+C73 71 gnd 2.080806f
+R71 71 70 2.224404
+C74 72 gnd 2.080806f
+R72 72 71 2.224404
+C75 73 gnd 2.080806f
+R73 72 73 2.224404
+C76 74 gnd 2.080806f
+R74 73 74 2.224404
+R75 74 g7470_1 2.224404
+.ends
+
+.subckt netg7471 g7471_1 g7471_0 gnd
+C1  g7471_1 gnd 2.080806f
+C2  g7471_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7471_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+C50 48 gnd 2.080806f
+R48 48 47 2.224404
+C51 49 gnd 2.080806f
+R49 49 48 2.224404
+C52 50 gnd 2.080806f
+R50 49 50 2.224404
+C53 51 gnd 2.080806f
+R51 50 51 2.224404
+C54 52 gnd 2.080806f
+R52 52 51 2.224404
+C55 53 gnd 2.080806f
+R53 52 53 2.224404
+C56 54 gnd 2.080806f
+R54 53 54 2.224404
+C57 55 gnd 2.080806f
+R55 55 54 2.224404
+C58 56 gnd 2.080806f
+R56 55 56 2.224404
+C59 57 gnd 2.080806f
+R57 57 56 2.224404
+C60 58 gnd 2.080806f
+R58 58 57 2.224404
+C61 59 gnd 2.080806f
+R59 59 58 2.224404
+C62 60 gnd 2.080806f
+R60 60 59 2.224404
+C63 61 gnd 2.080806f
+R61 61 60 2.224404
+C64 62 gnd 2.080806f
+R62 62 61 2.224404
+C65 63 gnd 2.080806f
+R63 63 62 2.224404
+C66 64 gnd 2.080806f
+R64 63 64 2.224404
+C67 65 gnd 2.080806f
+R65 64 65 2.224404
+C68 66 gnd 2.080806f
+R66 66 65 2.224404
+C69 67 gnd 2.080806f
+R67 67 66 2.224404
+C70 68 gnd 2.080806f
+R68 68 67 2.224404
+C71 69 gnd 2.080806f
+R69 69 68 2.224404
+C72 70 gnd 2.080806f
+R70 70 69 2.224404
+C73 71 gnd 2.080806f
+R71 71 70 2.224404
+C74 72 gnd 2.080806f
+R72 72 71 2.224404
+C75 73 gnd 2.080806f
+R73 72 73 2.224404
+C76 74 gnd 2.080806f
+R74 73 74 2.224404
+R75 74 g7471_1 2.224404
+.ends
+
+.subckt netg205 g205_2 g205_0 g205_1 gnd
+C1  g205_2 gnd 2.080806f
+C2  g205_0 gnd 2.080806f
+C3  g205_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g205_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 5 6 2.224404
+C10 7 gnd 2.080806f
+R7 6 7 2.224404
+C11 8 gnd 2.080806f
+R8 7 8 2.224404
+C12 9 gnd 2.080806f
+R9 8 9 2.224404
+C13 10 gnd 2.080806f
+R10 9 10 2.224404
+C14 11 gnd 2.080806f
+R11 10 11 2.224404
+C15 12 gnd 2.080806f
+R12 11 12 2.224404
+C16 13 gnd 2.080806f
+R13 12 13 2.224404
+C17 14 gnd 2.080806f
+R14 14 13 2.224404
+C18 15 gnd 2.080806f
+R15 14 15 2.224404
+C19 16 gnd 2.080806f
+R16 16 15 2.224404
+C20 17 gnd 2.080806f
+R17 16 17 2.224404
+C21 18 gnd 2.080806f
+R18 17 18 2.224404
+C22 19 gnd 2.080806f
+R19 18 19 2.224404
+C23 20 gnd 2.080806f
+R20 19 20 2.224404
+C24 21 gnd 2.080806f
+R21 20 21 2.224404
+C25 22 gnd 2.080806f
+R22 21 22 2.224404
+C26 23 gnd 2.080806f
+R23 23 22 2.224404
+C27 24 gnd 2.080806f
+R24 23 24 2.224404
+C28 25 gnd 2.080806f
+R25 25 24 2.224404
+C29 26 gnd 2.080806f
+R26 26 25 2.224404
+C30 27 gnd 2.080806f
+R27 26 27 2.224404
+C31 28 gnd 2.080806f
+R28 28 27 2.224404
+C32 29 gnd 2.080806f
+R29 28 29 2.224404
+C33 30 gnd 2.080806f
+R30 29 30 2.224404
+R31 30 g205_2 2.224404
+C34 31 gnd 2.080806f
+R32 g205_2 31 2.224404
+C35 32 gnd 2.080806f
+R33 31 32 2.224404
+C36 33 gnd 2.080806f
+R34 32 33 2.224404
+C37 34 gnd 2.080806f
+R35 33 34 2.224404
+C38 35 gnd 2.080806f
+R36 34 35 2.224404
+C39 36 gnd 2.080806f
+R37 35 36 2.224404
+C40 37 gnd 2.080806f
+R38 36 37 2.224404
+C41 38 gnd 2.080806f
+R39 37 38 2.224404
+C42 39 gnd 2.080806f
+R40 38 39 2.224404
+C43 40 gnd 2.080806f
+R41 39 40 2.224404
+C44 41 gnd 2.080806f
+R42 40 41 2.224404
+C45 42 gnd 2.080806f
+R43 41 42 2.224404
+C46 43 gnd 2.080806f
+R44 42 43 2.224404
+C47 44 gnd 2.080806f
+R45 43 44 2.224404
+C48 45 gnd 2.080806f
+R46 44 45 2.224404
+C49 46 gnd 2.080806f
+R47 45 46 2.224404
+C50 47 gnd 2.080806f
+R48 46 47 2.224404
+C51 48 gnd 2.080806f
+R49 47 48 2.224404
+C52 49 gnd 2.080806f
+R50 48 49 2.224404
+C53 50 gnd 2.080806f
+R51 49 50 2.224404
+C54 51 gnd 2.080806f
+R52 50 51 2.224404
+C55 52 gnd 2.080806f
+R53 51 52 2.224404
+C56 53 gnd 2.080806f
+R54 52 53 2.224404
+C57 54 gnd 2.080806f
+R55 53 54 2.224404
+C58 55 gnd 2.080806f
+R56 54 55 2.224404
+C59 56 gnd 2.080806f
+R57 55 56 2.224404
+C60 57 gnd 2.080806f
+R58 56 57 2.224404
+C61 58 gnd 2.080806f
+R59 57 58 2.224404
+C62 59 gnd 2.080806f
+R60 58 59 2.224404
+C63 60 gnd 2.080806f
+R61 59 60 2.224404
+C64 61 gnd 2.080806f
+R62 60 61 2.224404
+C65 62 gnd 2.080806f
+R63 61 62 2.224404
+C66 63 gnd 2.080806f
+R64 62 63 2.224404
+C67 64 gnd 2.080806f
+R65 63 64 2.224404
+C68 65 gnd 2.080806f
+R66 64 65 2.224404
+C69 66 gnd 2.080806f
+R67 65 66 2.224404
+C70 67 gnd 2.080806f
+R68 66 67 2.224404
+C71 68 gnd 2.080806f
+R69 67 68 2.224404
+C72 69 gnd 2.080806f
+R70 68 69 2.224404
+C73 70 gnd 2.080806f
+R71 69 70 2.224404
+C74 71 gnd 2.080806f
+R72 70 71 2.224404
+C75 72 gnd 2.080806f
+R73 71 72 2.224404
+C76 73 gnd 2.080806f
+R74 72 73 2.224404
+C77 74 gnd 2.080806f
+R75 73 74 2.224404
+C78 75 gnd 2.080806f
+R76 74 75 2.224404
+C79 76 gnd 2.080806f
+R77 75 76 2.224404
+C80 77 gnd 2.080806f
+R78 76 77 2.224404
+C81 78 gnd 2.080806f
+R79 77 78 2.224404
+C82 79 gnd 2.080806f
+R80 78 79 2.224404
+C83 80 gnd 2.080806f
+R81 79 80 2.224404
+C84 81 gnd 2.080806f
+R82 80 81 2.224404
+C85 82 gnd 2.080806f
+R83 81 82 2.224404
+R84 82 g205_1 2.224404
+.ends
+
+.subckt netg7460 g7460_1 g7460_0 gnd
+C1  g7460_1 gnd 2.080806f
+C2  g7460_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7460_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+C50 48 gnd 2.080806f
+R48 47 48 2.224404
+C51 49 gnd 2.080806f
+R49 48 49 2.224404
+C52 50 gnd 2.080806f
+R50 50 49 2.224404
+C53 51 gnd 2.080806f
+R51 51 50 2.224404
+C54 52 gnd 2.080806f
+R52 52 51 2.224404
+C55 53 gnd 2.080806f
+R53 53 52 2.224404
+C56 54 gnd 2.080806f
+R54 53 54 2.224404
+C57 55 gnd 2.080806f
+R55 54 55 2.224404
+C58 56 gnd 2.080806f
+R56 56 55 2.224404
+C59 57 gnd 2.080806f
+R57 57 56 2.224404
+C60 58 gnd 2.080806f
+R58 57 58 2.224404
+C61 59 gnd 2.080806f
+R59 59 58 2.224404
+C62 60 gnd 2.080806f
+R60 60 59 2.224404
+C63 61 gnd 2.080806f
+R61 61 60 2.224404
+C64 62 gnd 2.080806f
+R62 62 61 2.224404
+C65 63 gnd 2.080806f
+R63 63 62 2.224404
+C66 64 gnd 2.080806f
+R64 64 63 2.224404
+C67 65 gnd 2.080806f
+R65 64 65 2.224404
+C68 66 gnd 2.080806f
+R66 65 66 2.224404
+C69 67 gnd 2.080806f
+R67 67 66 2.224404
+C70 68 gnd 2.080806f
+R68 68 67 2.224404
+C71 69 gnd 2.080806f
+R69 69 68 2.224404
+C72 70 gnd 2.080806f
+R70 70 69 2.224404
+C73 71 gnd 2.080806f
+R71 71 70 2.224404
+C74 72 gnd 2.080806f
+R72 72 71 2.224404
+C75 73 gnd 2.080806f
+R73 73 72 2.224404
+C76 74 gnd 2.080806f
+R74 73 74 2.224404
+C77 75 gnd 2.080806f
+R75 74 75 2.224404
+R76 75 g7460_1 2.224404
+.ends
+
+.subckt netg2270 g2270_0 g2270_3 g2270_4 g2270_5 g2270_2 g2270_1 gnd
+C1  g2270_0 gnd 2.080806f
+C2  g2270_3 gnd 2.080806f
+C3  g2270_4 gnd 2.080806f
+C4  g2270_5 gnd 2.080806f
+C5  g2270_2 gnd 2.080806f
+C6  g2270_1 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g2270_0 2.224404
+C8 2 gnd 2.080806f
+R2 2 1 2.224404
+C9 3 gnd 2.080806f
+R3 3 2 2.224404
+C10 4 gnd 2.080806f
+R4 4 3 2.224404
+C11 5 gnd 2.080806f
+R5 5 4 2.224404
+C12 6 gnd 2.080806f
+R6 6 5 2.224404
+C13 7 gnd 2.080806f
+R7 7 6 2.224404
+R8 g2270_4 7 2.224404
+C14 8 gnd 2.080806f
+R9 8 g2270_4 2.224404
+C15 9 gnd 2.080806f
+R10 9 8 2.224404
+C16 10 gnd 2.080806f
+R11 10 9 2.224404
+R12 g2270_3 10 2.224404
+C17 11 gnd 2.080806f
+R13 11 g2270_3 2.224404
+R14 g2270_5 11 2.224404
+C18 12 gnd 2.080806f
+R15 g2270_0 12 2.224404
+C19 13 gnd 2.080806f
+R16 12 13 2.224404
+C20 14 gnd 2.080806f
+R17 13 14 2.224404
+C21 15 gnd 2.080806f
+R18 14 15 2.224404
+C22 16 gnd 2.080806f
+R19 15 16 2.224404
+C23 17 gnd 2.080806f
+R20 16 17 2.224404
+C24 18 gnd 2.080806f
+R21 17 18 2.224404
+C25 19 gnd 2.080806f
+R22 18 19 2.224404
+C26 20 gnd 2.080806f
+R23 20 19 2.224404
+C27 21 gnd 2.080806f
+R24 20 21 2.224404
+C28 22 gnd 2.080806f
+R25 21 22 2.224404
+C29 23 gnd 2.080806f
+R26 22 23 2.224404
+C30 24 gnd 2.080806f
+R27 23 24 2.224404
+C31 25 gnd 2.080806f
+R28 24 25 2.224404
+C32 26 gnd 2.080806f
+R29 25 26 2.224404
+C33 27 gnd 2.080806f
+R30 26 27 2.224404
+C34 28 gnd 2.080806f
+R31 27 28 2.224404
+C35 29 gnd 2.080806f
+R32 28 29 2.224404
+C36 30 gnd 2.080806f
+R33 29 30 2.224404
+C37 31 gnd 2.080806f
+R34 31 30 2.224404
+C38 32 gnd 2.080806f
+R35 31 32 2.224404
+C39 33 gnd 2.080806f
+R36 32 33 2.224404
+C40 34 gnd 2.080806f
+R37 33 34 2.224404
+C41 35 gnd 2.080806f
+R38 34 35 2.224404
+C42 36 gnd 2.080806f
+R39 35 36 2.224404
+C43 37 gnd 2.080806f
+R40 36 37 2.224404
+C44 38 gnd 2.080806f
+R41 37 38 2.224404
+C45 39 gnd 2.080806f
+R42 38 39 2.224404
+C46 40 gnd 2.080806f
+R43 39 40 2.224404
+C47 41 gnd 2.080806f
+R44 40 41 2.224404
+C48 42 gnd 2.080806f
+R45 41 42 2.224404
+C49 43 gnd 2.080806f
+R46 42 43 2.224404
+C50 44 gnd 2.080806f
+R47 43 44 2.224404
+C51 45 gnd 2.080806f
+R48 44 45 2.224404
+C52 46 gnd 2.080806f
+R49 45 46 2.224404
+C53 47 gnd 2.080806f
+R50 47 46 2.224404
+R51 g2270_2 47 2.224404
+C54 48 gnd 2.080806f
+R52 46 48 2.224404
+C55 49 gnd 2.080806f
+R53 48 49 2.224404
+C56 50 gnd 2.080806f
+R54 49 50 2.224404
+C57 51 gnd 2.080806f
+R55 50 51 2.224404
+C58 52 gnd 2.080806f
+R56 51 52 2.224404
+C59 53 gnd 2.080806f
+R57 52 53 2.224404
+C60 54 gnd 2.080806f
+R58 53 54 2.224404
+C61 55 gnd 2.080806f
+R59 54 55 2.224404
+C62 56 gnd 2.080806f
+R60 55 56 2.224404
+C63 57 gnd 2.080806f
+R61 56 57 2.224404
+C64 58 gnd 2.080806f
+R62 57 58 2.224404
+C65 59 gnd 2.080806f
+R63 58 59 2.224404
+C66 60 gnd 2.080806f
+R64 59 60 2.224404
+C67 61 gnd 2.080806f
+R65 60 61 2.224404
+C68 62 gnd 2.080806f
+R66 61 62 2.224404
+C69 63 gnd 2.080806f
+R67 62 63 2.224404
+C70 64 gnd 2.080806f
+R68 63 64 2.224404
+C71 65 gnd 2.080806f
+R69 64 65 2.224404
+C72 66 gnd 2.080806f
+R70 65 66 2.224404
+C73 67 gnd 2.080806f
+R71 66 67 2.224404
+C74 68 gnd 2.080806f
+R72 67 68 2.224404
+C75 69 gnd 2.080806f
+R73 68 69 2.224404
+C76 70 gnd 2.080806f
+R74 69 70 2.224404
+C77 71 gnd 2.080806f
+R75 70 71 2.224404
+C78 72 gnd 2.080806f
+R76 71 72 2.224404
+C79 73 gnd 2.080806f
+R77 72 73 2.224404
+C80 74 gnd 2.080806f
+R78 73 74 2.224404
+C81 75 gnd 2.080806f
+R79 74 75 2.224404
+C82 76 gnd 2.080806f
+R80 75 76 2.224404
+C83 77 gnd 2.080806f
+R81 76 77 2.224404
+R82 77 g2270_1 2.224404
+.ends
+
+.subckt netg7450 g7450_0 g7450_1 gnd
+C1  g7450_0 gnd 2.080806f
+C2  g7450_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7450_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+C50 48 gnd 2.080806f
+R48 48 47 2.224404
+C51 49 gnd 2.080806f
+R49 49 48 2.224404
+C52 50 gnd 2.080806f
+R50 49 50 2.224404
+C53 51 gnd 2.080806f
+R51 50 51 2.224404
+C54 52 gnd 2.080806f
+R52 52 51 2.224404
+C55 53 gnd 2.080806f
+R53 53 52 2.224404
+C56 54 gnd 2.080806f
+R54 54 53 2.224404
+C57 55 gnd 2.080806f
+R55 54 55 2.224404
+C58 56 gnd 2.080806f
+R56 56 55 2.224404
+C59 57 gnd 2.080806f
+R57 57 56 2.224404
+C60 58 gnd 2.080806f
+R58 57 58 2.224404
+C61 59 gnd 2.080806f
+R59 58 59 2.224404
+C62 60 gnd 2.080806f
+R60 59 60 2.224404
+C63 61 gnd 2.080806f
+R61 60 61 2.224404
+C64 62 gnd 2.080806f
+R62 61 62 2.224404
+C65 63 gnd 2.080806f
+R63 63 62 2.224404
+C66 64 gnd 2.080806f
+R64 64 63 2.224404
+C67 65 gnd 2.080806f
+R65 65 64 2.224404
+C68 66 gnd 2.080806f
+R66 66 65 2.224404
+C69 67 gnd 2.080806f
+R67 66 67 2.224404
+C70 68 gnd 2.080806f
+R68 67 68 2.224404
+C71 69 gnd 2.080806f
+R69 69 68 2.224404
+C72 70 gnd 2.080806f
+R70 70 69 2.224404
+C73 71 gnd 2.080806f
+R71 70 71 2.224404
+C74 72 gnd 2.080806f
+R72 72 71 2.224404
+C75 73 gnd 2.080806f
+R73 73 72 2.224404
+C76 74 gnd 2.080806f
+R74 74 73 2.224404
+C77 75 gnd 2.080806f
+R75 75 74 2.224404
+C78 76 gnd 2.080806f
+R76 76 75 2.224404
+R77 g7450_1 76 2.224404
+.ends
+
+.subckt netg7504 g7504_0 g7504_1 gnd
+C1  g7504_0 gnd 2.080806f
+C2  g7504_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7504_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+C50 48 gnd 2.080806f
+R48 48 47 2.224404
+C51 49 gnd 2.080806f
+R49 49 48 2.224404
+C52 50 gnd 2.080806f
+R50 50 49 2.224404
+C53 51 gnd 2.080806f
+R51 50 51 2.224404
+C54 52 gnd 2.080806f
+R52 51 52 2.224404
+C55 53 gnd 2.080806f
+R53 53 52 2.224404
+C56 54 gnd 2.080806f
+R54 54 53 2.224404
+C57 55 gnd 2.080806f
+R55 54 55 2.224404
+C58 56 gnd 2.080806f
+R56 55 56 2.224404
+C59 57 gnd 2.080806f
+R57 56 57 2.224404
+C60 58 gnd 2.080806f
+R58 58 57 2.224404
+C61 59 gnd 2.080806f
+R59 59 58 2.224404
+C62 60 gnd 2.080806f
+R60 59 60 2.224404
+C63 61 gnd 2.080806f
+R61 61 60 2.224404
+C64 62 gnd 2.080806f
+R62 62 61 2.224404
+C65 63 gnd 2.080806f
+R63 63 62 2.224404
+C66 64 gnd 2.080806f
+R64 64 63 2.224404
+C67 65 gnd 2.080806f
+R65 64 65 2.224404
+C68 66 gnd 2.080806f
+R66 66 65 2.224404
+C69 67 gnd 2.080806f
+R67 67 66 2.224404
+C70 68 gnd 2.080806f
+R68 68 67 2.224404
+C71 69 gnd 2.080806f
+R69 69 68 2.224404
+C72 70 gnd 2.080806f
+R70 70 69 2.224404
+C73 71 gnd 2.080806f
+R71 71 70 2.224404
+C74 72 gnd 2.080806f
+R72 71 72 2.224404
+C75 73 gnd 2.080806f
+R73 72 73 2.224404
+C76 74 gnd 2.080806f
+R74 74 73 2.224404
+C77 75 gnd 2.080806f
+R75 74 75 2.224404
+C78 76 gnd 2.080806f
+R76 76 75 2.224404
+R77 g7504_1 76 2.224404
+.ends
+
+.subckt netg7449 g7449_1 g7449_0 gnd
+C1  g7449_1 gnd 2.080806f
+C2  g7449_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7449_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+C50 48 gnd 2.080806f
+R48 48 47 2.224404
+C51 49 gnd 2.080806f
+R49 49 48 2.224404
+C52 50 gnd 2.080806f
+R50 49 50 2.224404
+C53 51 gnd 2.080806f
+R51 50 51 2.224404
+C54 52 gnd 2.080806f
+R52 52 51 2.224404
+C55 53 gnd 2.080806f
+R53 52 53 2.224404
+C56 54 gnd 2.080806f
+R54 53 54 2.224404
+C57 55 gnd 2.080806f
+R55 54 55 2.224404
+C58 56 gnd 2.080806f
+R56 55 56 2.224404
+C59 57 gnd 2.080806f
+R57 56 57 2.224404
+C60 58 gnd 2.080806f
+R58 58 57 2.224404
+C61 59 gnd 2.080806f
+R59 58 59 2.224404
+C62 60 gnd 2.080806f
+R60 60 59 2.224404
+C63 61 gnd 2.080806f
+R61 61 60 2.224404
+C64 62 gnd 2.080806f
+R62 62 61 2.224404
+C65 63 gnd 2.080806f
+R63 63 62 2.224404
+C66 64 gnd 2.080806f
+R64 64 63 2.224404
+C67 65 gnd 2.080806f
+R65 65 64 2.224404
+C68 66 gnd 2.080806f
+R66 65 66 2.224404
+C69 67 gnd 2.080806f
+R67 66 67 2.224404
+C70 68 gnd 2.080806f
+R68 68 67 2.224404
+C71 69 gnd 2.080806f
+R69 69 68 2.224404
+C72 70 gnd 2.080806f
+R70 70 69 2.224404
+C73 71 gnd 2.080806f
+R71 71 70 2.224404
+C74 72 gnd 2.080806f
+R72 72 71 2.224404
+C75 73 gnd 2.080806f
+R73 73 72 2.224404
+C76 74 gnd 2.080806f
+R74 74 73 2.224404
+C77 75 gnd 2.080806f
+R75 74 75 2.224404
+C78 76 gnd 2.080806f
+R76 75 76 2.224404
+R77 76 g7449_1 2.224404
+.ends
+
+.subckt netg7503 g7503_0 g7503_1 gnd
+C1  g7503_0 gnd 2.080806f
+C2  g7503_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7503_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+C50 48 gnd 2.080806f
+R48 48 47 2.224404
+C51 49 gnd 2.080806f
+R49 48 49 2.224404
+C52 50 gnd 2.080806f
+R50 50 49 2.224404
+C53 51 gnd 2.080806f
+R51 50 51 2.224404
+C54 52 gnd 2.080806f
+R52 52 51 2.224404
+C55 53 gnd 2.080806f
+R53 53 52 2.224404
+C56 54 gnd 2.080806f
+R54 53 54 2.224404
+C57 55 gnd 2.080806f
+R55 55 54 2.224404
+C58 56 gnd 2.080806f
+R56 55 56 2.224404
+C59 57 gnd 2.080806f
+R57 57 56 2.224404
+C60 58 gnd 2.080806f
+R58 58 57 2.224404
+C61 59 gnd 2.080806f
+R59 59 58 2.224404
+C62 60 gnd 2.080806f
+R60 60 59 2.224404
+C63 61 gnd 2.080806f
+R61 61 60 2.224404
+C64 62 gnd 2.080806f
+R62 62 61 2.224404
+C65 63 gnd 2.080806f
+R63 63 62 2.224404
+C66 64 gnd 2.080806f
+R64 64 63 2.224404
+C67 65 gnd 2.080806f
+R65 65 64 2.224404
+C68 66 gnd 2.080806f
+R66 66 65 2.224404
+C69 67 gnd 2.080806f
+R67 67 66 2.224404
+C70 68 gnd 2.080806f
+R68 68 67 2.224404
+C71 69 gnd 2.080806f
+R69 69 68 2.224404
+C72 70 gnd 2.080806f
+R70 70 69 2.224404
+C73 71 gnd 2.080806f
+R71 71 70 2.224404
+C74 72 gnd 2.080806f
+R72 71 72 2.224404
+C75 73 gnd 2.080806f
+R73 73 72 2.224404
+C76 74 gnd 2.080806f
+R74 74 73 2.224404
+C77 75 gnd 2.080806f
+R75 75 74 2.224404
+C78 76 gnd 2.080806f
+R76 76 75 2.224404
+R77 g7503_1 76 2.224404
+.ends
+
+.subckt netg197 g197_0 g197_1 g197_2 gnd
+C1  g197_0 gnd 2.080806f
+C2  g197_1 gnd 2.080806f
+C3  g197_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g197_0 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+C8 5 gnd 2.080806f
+R5 4 5 2.224404
+C9 6 gnd 2.080806f
+R6 5 6 2.224404
+C10 7 gnd 2.080806f
+R7 6 7 2.224404
+C11 8 gnd 2.080806f
+R8 7 8 2.224404
+C12 9 gnd 2.080806f
+R9 8 9 2.224404
+C13 10 gnd 2.080806f
+R10 9 10 2.224404
+C14 11 gnd 2.080806f
+R11 10 11 2.224404
+C15 12 gnd 2.080806f
+R12 11 12 2.224404
+C16 13 gnd 2.080806f
+R13 12 13 2.224404
+C17 14 gnd 2.080806f
+R14 13 14 2.224404
+C18 15 gnd 2.080806f
+R15 14 15 2.224404
+C19 16 gnd 2.080806f
+R16 15 16 2.224404
+C20 17 gnd 2.080806f
+R17 16 17 2.224404
+C21 18 gnd 2.080806f
+R18 17 18 2.224404
+C22 19 gnd 2.080806f
+R19 18 19 2.224404
+C23 20 gnd 2.080806f
+R20 19 20 2.224404
+C24 21 gnd 2.080806f
+R21 20 21 2.224404
+C25 22 gnd 2.080806f
+R22 21 22 2.224404
+C26 23 gnd 2.080806f
+R23 22 23 2.224404
+C27 24 gnd 2.080806f
+R24 23 24 2.224404
+C28 25 gnd 2.080806f
+R25 24 25 2.224404
+C29 26 gnd 2.080806f
+R26 25 26 2.224404
+C30 27 gnd 2.080806f
+R27 26 27 2.224404
+C31 28 gnd 2.080806f
+R28 27 28 2.224404
+C32 29 gnd 2.080806f
+R29 29 28 2.224404
+C33 30 gnd 2.080806f
+R30 29 30 2.224404
+C34 31 gnd 2.080806f
+R31 30 31 2.224404
+R32 g197_1 31 2.224404
+C35 32 gnd 2.080806f
+R33 27 32 2.224404
+C36 33 gnd 2.080806f
+R34 32 33 2.224404
+C37 34 gnd 2.080806f
+R35 33 34 2.224404
+C38 35 gnd 2.080806f
+R36 34 35 2.224404
+C39 36 gnd 2.080806f
+R37 35 36 2.224404
+C40 37 gnd 2.080806f
+R38 36 37 2.224404
+C41 38 gnd 2.080806f
+R39 37 38 2.224404
+C42 39 gnd 2.080806f
+R40 38 39 2.224404
+C43 40 gnd 2.080806f
+R41 39 40 2.224404
+C44 41 gnd 2.080806f
+R42 40 41 2.224404
+C45 42 gnd 2.080806f
+R43 41 42 2.224404
+C46 43 gnd 2.080806f
+R44 42 43 2.224404
+C47 44 gnd 2.080806f
+R45 43 44 2.224404
+C48 45 gnd 2.080806f
+R46 44 45 2.224404
+C49 46 gnd 2.080806f
+R47 45 46 2.224404
+C50 47 gnd 2.080806f
+R48 46 47 2.224404
+C51 48 gnd 2.080806f
+R49 47 48 2.224404
+C52 49 gnd 2.080806f
+R50 48 49 2.224404
+C53 50 gnd 2.080806f
+R51 49 50 2.224404
+C54 51 gnd 2.080806f
+R52 50 51 2.224404
+C55 52 gnd 2.080806f
+R53 51 52 2.224404
+C56 53 gnd 2.080806f
+R54 52 53 2.224404
+C57 54 gnd 2.080806f
+R55 53 54 2.224404
+C58 55 gnd 2.080806f
+R56 54 55 2.224404
+C59 56 gnd 2.080806f
+R57 55 56 2.224404
+C60 57 gnd 2.080806f
+R58 56 57 2.224404
+C61 58 gnd 2.080806f
+R59 57 58 2.224404
+C62 59 gnd 2.080806f
+R60 58 59 2.224404
+C63 60 gnd 2.080806f
+R61 59 60 2.224404
+C64 61 gnd 2.080806f
+R62 60 61 2.224404
+C65 62 gnd 2.080806f
+R63 61 62 2.224404
+C66 63 gnd 2.080806f
+R64 62 63 2.224404
+C67 64 gnd 2.080806f
+R65 63 64 2.224404
+C68 65 gnd 2.080806f
+R66 64 65 2.224404
+C69 66 gnd 2.080806f
+R67 65 66 2.224404
+C70 67 gnd 2.080806f
+R68 66 67 2.224404
+C71 68 gnd 2.080806f
+R69 67 68 2.224404
+C72 69 gnd 2.080806f
+R70 68 69 2.224404
+C73 70 gnd 2.080806f
+R71 69 70 2.224404
+C74 71 gnd 2.080806f
+R72 70 71 2.224404
+C75 72 gnd 2.080806f
+R73 71 72 2.224404
+C76 73 gnd 2.080806f
+R74 72 73 2.224404
+C77 74 gnd 2.080806f
+R75 73 74 2.224404
+C78 75 gnd 2.080806f
+R76 74 75 2.224404
+C79 76 gnd 2.080806f
+R77 75 76 2.224404
+C80 77 gnd 2.080806f
+R78 76 77 2.224404
+C81 78 gnd 2.080806f
+R79 78 77 2.224404
+R80 g197_2 78 2.224404
+.ends
+
+.subckt netg4 g4_2 g4_1 g4_0 gnd
+C1  g4_2 gnd 2.080806f
+C2  g4_1 gnd 2.080806f
+C3  g4_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g4_0 1 2.224404
+R2 1 g4_2 2.224404
+C5 2 gnd 2.080806f
+R3 2 g4_0 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 11 10 2.224404
+C15 12 gnd 2.080806f
+R13 12 11 2.224404
+C16 13 gnd 2.080806f
+R14 13 12 2.224404
+C17 14 gnd 2.080806f
+R15 14 13 2.224404
+C18 15 gnd 2.080806f
+R16 15 14 2.224404
+C19 16 gnd 2.080806f
+R17 16 15 2.224404
+C20 17 gnd 2.080806f
+R18 17 16 2.224404
+C21 18 gnd 2.080806f
+R19 18 17 2.224404
+C22 19 gnd 2.080806f
+R20 19 18 2.224404
+C23 20 gnd 2.080806f
+R21 20 19 2.224404
+C24 21 gnd 2.080806f
+R22 21 20 2.224404
+C25 22 gnd 2.080806f
+R23 22 21 2.224404
+C26 23 gnd 2.080806f
+R24 23 22 2.224404
+C27 24 gnd 2.080806f
+R25 24 23 2.224404
+C28 25 gnd 2.080806f
+R26 25 24 2.224404
+C29 26 gnd 2.080806f
+R27 26 25 2.224404
+C30 27 gnd 2.080806f
+R28 27 26 2.224404
+C31 28 gnd 2.080806f
+R29 28 27 2.224404
+C32 29 gnd 2.080806f
+R30 29 28 2.224404
+C33 30 gnd 2.080806f
+R31 30 29 2.224404
+C34 31 gnd 2.080806f
+R32 31 30 2.224404
+C35 32 gnd 2.080806f
+R33 32 31 2.224404
+C36 33 gnd 2.080806f
+R34 33 32 2.224404
+C37 34 gnd 2.080806f
+R35 34 33 2.224404
+C38 35 gnd 2.080806f
+R36 35 34 2.224404
+C39 36 gnd 2.080806f
+R37 36 35 2.224404
+C40 37 gnd 2.080806f
+R38 37 36 2.224404
+C41 38 gnd 2.080806f
+R39 38 37 2.224404
+C42 39 gnd 2.080806f
+R40 39 38 2.224404
+C43 40 gnd 2.080806f
+R41 40 39 2.224404
+C44 41 gnd 2.080806f
+R42 41 40 2.224404
+C45 42 gnd 2.080806f
+R43 42 41 2.224404
+C46 43 gnd 2.080806f
+R44 43 42 2.224404
+C47 44 gnd 2.080806f
+R45 44 43 2.224404
+C48 45 gnd 2.080806f
+R46 45 44 2.224404
+C49 46 gnd 2.080806f
+R47 46 45 2.224404
+C50 47 gnd 2.080806f
+R48 47 46 2.224404
+C51 48 gnd 2.080806f
+R49 48 47 2.224404
+C52 49 gnd 2.080806f
+R50 49 48 2.224404
+C53 50 gnd 2.080806f
+R51 50 49 2.224404
+C54 51 gnd 2.080806f
+R52 51 50 2.224404
+C55 52 gnd 2.080806f
+R53 52 51 2.224404
+C56 53 gnd 2.080806f
+R54 53 52 2.224404
+C57 54 gnd 2.080806f
+R55 54 53 2.224404
+C58 55 gnd 2.080806f
+R56 55 54 2.224404
+C59 56 gnd 2.080806f
+R57 56 55 2.224404
+C60 57 gnd 2.080806f
+R58 57 56 2.224404
+C61 58 gnd 2.080806f
+R59 58 57 2.224404
+C62 59 gnd 2.080806f
+R60 59 58 2.224404
+C63 60 gnd 2.080806f
+R61 60 59 2.224404
+C64 61 gnd 2.080806f
+R62 61 60 2.224404
+C65 62 gnd 2.080806f
+R63 62 61 2.224404
+C66 63 gnd 2.080806f
+R64 63 62 2.224404
+C67 64 gnd 2.080806f
+R65 64 63 2.224404
+C68 65 gnd 2.080806f
+R66 65 64 2.224404
+C69 66 gnd 2.080806f
+R67 66 65 2.224404
+C70 67 gnd 2.080806f
+R68 67 66 2.224404
+C71 68 gnd 2.080806f
+R69 68 67 2.224404
+C72 69 gnd 2.080806f
+R70 69 68 2.224404
+C73 70 gnd 2.080806f
+R71 70 69 2.224404
+C74 71 gnd 2.080806f
+R72 71 70 2.224404
+C75 72 gnd 2.080806f
+R73 72 71 2.224404
+C76 73 gnd 2.080806f
+R74 73 72 2.224404
+C77 74 gnd 2.080806f
+R75 74 73 2.224404
+C78 75 gnd 2.080806f
+R76 75 74 2.224404
+C79 76 gnd 2.080806f
+R77 76 75 2.224404
+R78 g4_1 76 2.224404
+.ends
+
+.subckt netg1750 g1750_4 g1750_0 g1750_2 g1750_5 g1750_3 g1750_1 gnd
+C1  g1750_4 gnd 2.080806f
+C2  g1750_0 gnd 2.080806f
+C3  g1750_2 gnd 2.080806f
+C4  g1750_5 gnd 2.080806f
+C5  g1750_3 gnd 2.080806f
+C6  g1750_1 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g1750_0 2.224404
+C8 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 g1750_4 2 2.224404
+C9 3 gnd 2.080806f
+R4 g1750_0 3 2.224404
+C10 4 gnd 2.080806f
+R5 3 4 2.224404
+C11 5 gnd 2.080806f
+R6 4 5 2.224404
+C12 6 gnd 2.080806f
+R7 5 6 2.224404
+C13 7 gnd 2.080806f
+R8 6 7 2.224404
+C14 8 gnd 2.080806f
+R9 7 8 2.224404
+C15 9 gnd 2.080806f
+R10 8 9 2.224404
+C16 10 gnd 2.080806f
+R11 9 10 2.224404
+C17 11 gnd 2.080806f
+R12 10 11 2.224404
+C18 12 gnd 2.080806f
+R13 11 12 2.224404
+C19 13 gnd 2.080806f
+R14 12 13 2.224404
+R15 13 g1750_2 2.224404
+C20 14 gnd 2.080806f
+R16 14 13 2.224404
+C21 15 gnd 2.080806f
+R17 14 15 2.224404
+C22 16 gnd 2.080806f
+R18 16 15 2.224404
+C23 17 gnd 2.080806f
+R19 17 16 2.224404
+C24 18 gnd 2.080806f
+R20 18 17 2.224404
+C25 19 gnd 2.080806f
+R21 19 18 2.224404
+C26 20 gnd 2.080806f
+R22 20 19 2.224404
+C27 21 gnd 2.080806f
+R23 20 21 2.224404
+C28 22 gnd 2.080806f
+R24 22 21 2.224404
+C29 23 gnd 2.080806f
+R25 22 23 2.224404
+C30 24 gnd 2.080806f
+R26 23 24 2.224404
+C31 25 gnd 2.080806f
+R27 25 24 2.224404
+C32 26 gnd 2.080806f
+R28 25 26 2.224404
+C33 27 gnd 2.080806f
+R29 26 27 2.224404
+C34 28 gnd 2.080806f
+R30 28 27 2.224404
+C35 29 gnd 2.080806f
+R31 28 29 2.224404
+R32 g1750_1 29 2.224404
+C36 30 gnd 2.080806f
+R33 g1750_2 30 2.224404
+C37 31 gnd 2.080806f
+R34 30 31 2.224404
+C38 32 gnd 2.080806f
+R35 31 32 2.224404
+C39 33 gnd 2.080806f
+R36 33 32 2.224404
+C40 34 gnd 2.080806f
+R37 33 34 2.224404
+C41 35 gnd 2.080806f
+R38 34 35 2.224404
+C42 36 gnd 2.080806f
+R39 35 36 2.224404
+C43 37 gnd 2.080806f
+R40 36 37 2.224404
+C44 38 gnd 2.080806f
+R41 37 38 2.224404
+C45 39 gnd 2.080806f
+R42 38 39 2.224404
+C46 40 gnd 2.080806f
+R43 39 40 2.224404
+C47 41 gnd 2.080806f
+R44 40 41 2.224404
+C48 42 gnd 2.080806f
+R45 41 42 2.224404
+C49 43 gnd 2.080806f
+R46 42 43 2.224404
+C50 44 gnd 2.080806f
+R47 43 44 2.224404
+C51 45 gnd 2.080806f
+R48 44 45 2.224404
+C52 46 gnd 2.080806f
+R49 45 46 2.224404
+C53 47 gnd 2.080806f
+R50 46 47 2.224404
+C54 48 gnd 2.080806f
+R51 47 48 2.224404
+C55 49 gnd 2.080806f
+R52 48 49 2.224404
+C56 50 gnd 2.080806f
+R53 49 50 2.224404
+C57 51 gnd 2.080806f
+R54 50 51 2.224404
+C58 52 gnd 2.080806f
+R55 51 52 2.224404
+C59 53 gnd 2.080806f
+R56 52 53 2.224404
+C60 54 gnd 2.080806f
+R57 53 54 2.224404
+C61 55 gnd 2.080806f
+R58 54 55 2.224404
+C62 56 gnd 2.080806f
+R59 55 56 2.224404
+C63 57 gnd 2.080806f
+R60 56 57 2.224404
+C64 58 gnd 2.080806f
+R61 57 58 2.224404
+C65 59 gnd 2.080806f
+R62 58 59 2.224404
+C66 60 gnd 2.080806f
+R63 59 60 2.224404
+C67 61 gnd 2.080806f
+R64 60 61 2.224404
+C68 62 gnd 2.080806f
+R65 61 62 2.224404
+C69 63 gnd 2.080806f
+R66 62 63 2.224404
+C70 64 gnd 2.080806f
+R67 63 64 2.224404
+C71 65 gnd 2.080806f
+R68 64 65 2.224404
+C72 66 gnd 2.080806f
+R69 65 66 2.224404
+C73 67 gnd 2.080806f
+R70 66 67 2.224404
+C74 68 gnd 2.080806f
+R71 67 68 2.224404
+C75 69 gnd 2.080806f
+R72 68 69 2.224404
+C76 70 gnd 2.080806f
+R73 69 70 2.224404
+C77 71 gnd 2.080806f
+R74 70 71 2.224404
+C78 72 gnd 2.080806f
+R75 71 72 2.224404
+C79 73 gnd 2.080806f
+R76 72 73 2.224404
+C80 74 gnd 2.080806f
+R77 73 74 2.224404
+C81 75 gnd 2.080806f
+R78 74 75 2.224404
+C82 76 gnd 2.080806f
+R79 75 76 2.224404
+C83 77 gnd 2.080806f
+R80 76 77 2.224404
+C84 78 gnd 2.080806f
+R81 77 78 2.224404
+C85 79 gnd 2.080806f
+R82 79 78 2.224404
+C86 80 gnd 2.080806f
+R83 80 79 2.224404
+C87 81 gnd 2.080806f
+R84 80 81 2.224404
+C88 82 gnd 2.080806f
+R85 82 81 2.224404
+C89 83 gnd 2.080806f
+R86 83 82 2.224404
+C90 84 gnd 2.080806f
+R87 84 83 2.224404
+R88 g1750_5 84 2.224404
+C91 85 gnd 2.080806f
+R89 81 85 2.224404
+C92 86 gnd 2.080806f
+R90 85 86 2.224404
+C93 87 gnd 2.080806f
+R91 86 87 2.224404
+C94 88 gnd 2.080806f
+R92 87 88 2.224404
+C95 89 gnd 2.080806f
+R93 88 89 2.224404
+C96 90 gnd 2.080806f
+R94 89 90 2.224404
+C97 91 gnd 2.080806f
+R95 90 91 2.224404
+C98 92 gnd 2.080806f
+R96 91 92 2.224404
+C99 93 gnd 2.080806f
+R97 92 93 2.224404
+C100 94 gnd 2.080806f
+R98 93 94 2.224404
+C101 95 gnd 2.080806f
+R99 94 95 2.224404
+C102 96 gnd 2.080806f
+R100 95 96 2.224404
+C103 97 gnd 2.080806f
+R101 96 97 2.224404
+C104 98 gnd 2.080806f
+R102 98 97 2.224404
+C105 99 gnd 2.080806f
+R103 99 98 2.224404
+R104 g1750_3 99 2.224404
+.ends
+
+.subckt netg457 g457_6 g457_2 g457_5 g457_1 g457_4 g457_3 g457_0 gnd
+C1  g457_6 gnd 2.080806f
+C2  g457_2 gnd 2.080806f
+C3  g457_5 gnd 2.080806f
+C4  g457_1 gnd 2.080806f
+C5  g457_4 gnd 2.080806f
+C6  g457_3 gnd 2.080806f
+C7  g457_0 gnd 2.080806f
+C8 1 gnd 2.080806f
+R1 g457_0 1 2.224404
+C9 2 gnd 2.080806f
+R2 1 2 2.224404
+C10 3 gnd 2.080806f
+R3 3 2 2.224404
+C11 4 gnd 2.080806f
+R4 4 3 2.224404
+C12 5 gnd 2.080806f
+R5 4 5 2.224404
+C13 6 gnd 2.080806f
+R6 6 5 2.224404
+C14 7 gnd 2.080806f
+R7 6 7 2.224404
+C15 8 gnd 2.080806f
+R8 7 8 2.224404
+R9 8 g457_1 2.224404
+C16 9 gnd 2.080806f
+R10 9 g457_0 2.224404
+C17 10 gnd 2.080806f
+R11 10 9 2.224404
+C18 11 gnd 2.080806f
+R12 11 10 2.224404
+C19 12 gnd 2.080806f
+R13 12 11 2.224404
+C20 13 gnd 2.080806f
+R14 13 12 2.224404
+C21 14 gnd 2.080806f
+R15 14 13 2.224404
+C22 15 gnd 2.080806f
+R16 15 14 2.224404
+C23 16 gnd 2.080806f
+R17 16 15 2.224404
+C24 17 gnd 2.080806f
+R18 17 16 2.224404
+R19 g457_3 17 2.224404
+C25 18 gnd 2.080806f
+R20 g457_3 18 2.224404
+C26 19 gnd 2.080806f
+R21 18 19 2.224404
+C27 20 gnd 2.080806f
+R22 19 20 2.224404
+C28 21 gnd 2.080806f
+R23 20 21 2.224404
+C29 22 gnd 2.080806f
+R24 21 22 2.224404
+C30 23 gnd 2.080806f
+R25 22 23 2.224404
+C31 24 gnd 2.080806f
+R26 23 24 2.224404
+C32 25 gnd 2.080806f
+R27 24 25 2.224404
+C33 26 gnd 2.080806f
+R28 25 26 2.224404
+C34 27 gnd 2.080806f
+R29 26 27 2.224404
+C35 28 gnd 2.080806f
+R30 27 28 2.224404
+C36 29 gnd 2.080806f
+R31 28 29 2.224404
+R32 29 g457_2 2.224404
+C37 30 gnd 2.080806f
+R33 g457_2 30 2.224404
+C38 31 gnd 2.080806f
+R34 30 31 2.224404
+C39 32 gnd 2.080806f
+R35 31 32 2.224404
+C40 33 gnd 2.080806f
+R36 32 33 2.224404
+R37 33 g457_5 2.224404
+C41 34 gnd 2.080806f
+R38 g457_1 34 2.224404
+C42 35 gnd 2.080806f
+R39 34 35 2.224404
+C43 36 gnd 2.080806f
+R40 35 36 2.224404
+C44 37 gnd 2.080806f
+R41 36 37 2.224404
+C45 38 gnd 2.080806f
+R42 37 38 2.224404
+C46 39 gnd 2.080806f
+R43 38 39 2.224404
+C47 40 gnd 2.080806f
+R44 39 40 2.224404
+C48 41 gnd 2.080806f
+R45 40 41 2.224404
+C49 42 gnd 2.080806f
+R46 41 42 2.224404
+C50 43 gnd 2.080806f
+R47 42 43 2.224404
+C51 44 gnd 2.080806f
+R48 43 44 2.224404
+C52 45 gnd 2.080806f
+R49 44 45 2.224404
+C53 46 gnd 2.080806f
+R50 45 46 2.224404
+C54 47 gnd 2.080806f
+R51 46 47 2.224404
+C55 48 gnd 2.080806f
+R52 47 48 2.224404
+C56 49 gnd 2.080806f
+R53 48 49 2.224404
+C57 50 gnd 2.080806f
+R54 49 50 2.224404
+C58 51 gnd 2.080806f
+R55 50 51 2.224404
+C59 52 gnd 2.080806f
+R56 51 52 2.224404
+C60 53 gnd 2.080806f
+R57 52 53 2.224404
+C61 54 gnd 2.080806f
+R58 53 54 2.224404
+C62 55 gnd 2.080806f
+R59 54 55 2.224404
+C63 56 gnd 2.080806f
+R60 55 56 2.224404
+C64 57 gnd 2.080806f
+R61 56 57 2.224404
+C65 58 gnd 2.080806f
+R62 57 58 2.224404
+C66 59 gnd 2.080806f
+R63 58 59 2.224404
+C67 60 gnd 2.080806f
+R64 59 60 2.224404
+C68 61 gnd 2.080806f
+R65 60 61 2.224404
+C69 62 gnd 2.080806f
+R66 61 62 2.224404
+C70 63 gnd 2.080806f
+R67 62 63 2.224404
+C71 64 gnd 2.080806f
+R68 63 64 2.224404
+C72 65 gnd 2.080806f
+R69 64 65 2.224404
+C73 66 gnd 2.080806f
+R70 65 66 2.224404
+C74 67 gnd 2.080806f
+R71 66 67 2.224404
+C75 68 gnd 2.080806f
+R72 68 67 2.224404
+C76 69 gnd 2.080806f
+R73 68 69 2.224404
+C77 70 gnd 2.080806f
+R74 69 70 2.224404
+C78 71 gnd 2.080806f
+R75 70 71 2.224404
+C79 72 gnd 2.080806f
+R76 72 71 2.224404
+C80 73 gnd 2.080806f
+R77 72 73 2.224404
+C81 74 gnd 2.080806f
+R78 73 74 2.224404
+C82 75 gnd 2.080806f
+R79 75 74 2.224404
+C83 76 gnd 2.080806f
+R80 76 75 2.224404
+C84 77 gnd 2.080806f
+R81 76 77 2.224404
+C85 78 gnd 2.080806f
+R82 78 77 2.224404
+C86 79 gnd 2.080806f
+R83 79 78 2.224404
+C87 80 gnd 2.080806f
+R84 79 80 2.224404
+R85 g457_6 80 2.224404
+C88 81 gnd 2.080806f
+R86 80 81 2.224404
+C89 82 gnd 2.080806f
+R87 81 82 2.224404
+C90 83 gnd 2.080806f
+R88 82 83 2.224404
+C91 84 gnd 2.080806f
+R89 83 84 2.224404
+C92 85 gnd 2.080806f
+R90 84 85 2.224404
+C93 86 gnd 2.080806f
+R91 85 86 2.224404
+C94 87 gnd 2.080806f
+R92 86 87 2.224404
+C95 88 gnd 2.080806f
+R93 87 88 2.224404
+C96 89 gnd 2.080806f
+R94 88 89 2.224404
+C97 90 gnd 2.080806f
+R95 89 90 2.224404
+C98 91 gnd 2.080806f
+R96 90 91 2.224404
+C99 92 gnd 2.080806f
+R97 91 92 2.224404
+C100 93 gnd 2.080806f
+R98 92 93 2.224404
+C101 94 gnd 2.080806f
+R99 93 94 2.224404
+C102 95 gnd 2.080806f
+R100 94 95 2.224404
+C103 96 gnd 2.080806f
+R101 95 96 2.224404
+C104 97 gnd 2.080806f
+R102 96 97 2.224404
+C105 98 gnd 2.080806f
+R103 97 98 2.224404
+C106 99 gnd 2.080806f
+R104 98 99 2.224404
+C107 100 gnd 2.080806f
+R105 99 100 2.224404
+C108 101 gnd 2.080806f
+R106 100 101 2.224404
+C109 102 gnd 2.080806f
+R107 101 102 2.224404
+R108 102 g457_4 2.224404
+.ends
+
+.subckt netg1738 g1738_5 g1738_2 g1738_1 g1738_4 g1738_3 g1738_0 gnd
+C1  g1738_5 gnd 2.080806f
+C2  g1738_2 gnd 2.080806f
+C3  g1738_1 gnd 2.080806f
+C4  g1738_4 gnd 2.080806f
+C5  g1738_3 gnd 2.080806f
+C6  g1738_0 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 g1738_0 1 2.224404
+C8 2 gnd 2.080806f
+R2 2 1 2.224404
+C9 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 g1738_3 3 2.224404
+C10 4 gnd 2.080806f
+R5 4 g1738_0 2.224404
+C11 5 gnd 2.080806f
+R6 5 4 2.224404
+C12 6 gnd 2.080806f
+R7 6 5 2.224404
+C13 7 gnd 2.080806f
+R8 7 6 2.224404
+R9 g1738_4 7 2.224404
+C14 8 gnd 2.080806f
+R10 g1738_3 8 2.224404
+C15 9 gnd 2.080806f
+R11 8 9 2.224404
+C16 10 gnd 2.080806f
+R12 9 10 2.224404
+C17 11 gnd 2.080806f
+R13 10 11 2.224404
+R14 g1738_5 11 2.224404
+C18 12 gnd 2.080806f
+R15 1 12 2.224404
+C19 13 gnd 2.080806f
+R16 12 13 2.224404
+C20 14 gnd 2.080806f
+R17 13 14 2.224404
+C21 15 gnd 2.080806f
+R18 14 15 2.224404
+C22 16 gnd 2.080806f
+R19 15 16 2.224404
+C23 17 gnd 2.080806f
+R20 16 17 2.224404
+C24 18 gnd 2.080806f
+R21 17 18 2.224404
+C25 19 gnd 2.080806f
+R22 18 19 2.224404
+C26 20 gnd 2.080806f
+R23 19 20 2.224404
+C27 21 gnd 2.080806f
+R24 20 21 2.224404
+C28 22 gnd 2.080806f
+R25 21 22 2.224404
+C29 23 gnd 2.080806f
+R26 22 23 2.224404
+C30 24 gnd 2.080806f
+R27 23 24 2.224404
+C31 25 gnd 2.080806f
+R28 24 25 2.224404
+C32 26 gnd 2.080806f
+R29 25 26 2.224404
+C33 27 gnd 2.080806f
+R30 26 27 2.224404
+C34 28 gnd 2.080806f
+R31 27 28 2.224404
+C35 29 gnd 2.080806f
+R32 28 29 2.224404
+C36 30 gnd 2.080806f
+R33 29 30 2.224404
+C37 31 gnd 2.080806f
+R34 30 31 2.224404
+C38 32 gnd 2.080806f
+R35 31 32 2.224404
+C39 33 gnd 2.080806f
+R36 32 33 2.224404
+C40 34 gnd 2.080806f
+R37 33 34 2.224404
+C41 35 gnd 2.080806f
+R38 34 35 2.224404
+C42 36 gnd 2.080806f
+R39 35 36 2.224404
+C43 37 gnd 2.080806f
+R40 36 37 2.224404
+C44 38 gnd 2.080806f
+R41 37 38 2.224404
+C45 39 gnd 2.080806f
+R42 38 39 2.224404
+C46 40 gnd 2.080806f
+R43 39 40 2.224404
+C47 41 gnd 2.080806f
+R44 40 41 2.224404
+C48 42 gnd 2.080806f
+R45 41 42 2.224404
+C49 43 gnd 2.080806f
+R46 42 43 2.224404
+C50 44 gnd 2.080806f
+R47 43 44 2.224404
+C51 45 gnd 2.080806f
+R48 44 45 2.224404
+C52 46 gnd 2.080806f
+R49 45 46 2.224404
+C53 47 gnd 2.080806f
+R50 46 47 2.224404
+C54 48 gnd 2.080806f
+R51 47 48 2.224404
+C55 49 gnd 2.080806f
+R52 48 49 2.224404
+C56 50 gnd 2.080806f
+R53 49 50 2.224404
+C57 51 gnd 2.080806f
+R54 50 51 2.224404
+C58 52 gnd 2.080806f
+R55 51 52 2.224404
+C59 53 gnd 2.080806f
+R56 52 53 2.224404
+C60 54 gnd 2.080806f
+R57 53 54 2.224404
+C61 55 gnd 2.080806f
+R58 54 55 2.224404
+R59 55 g1738_1 2.224404
+C62 56 gnd 2.080806f
+R60 56 55 2.224404
+C63 57 gnd 2.080806f
+R61 57 56 2.224404
+C64 58 gnd 2.080806f
+R62 58 57 2.224404
+C65 59 gnd 2.080806f
+R63 59 58 2.224404
+C66 60 gnd 2.080806f
+R64 60 59 2.224404
+C67 61 gnd 2.080806f
+R65 61 60 2.224404
+C68 62 gnd 2.080806f
+R66 61 62 2.224404
+C69 63 gnd 2.080806f
+R67 62 63 2.224404
+C70 64 gnd 2.080806f
+R68 63 64 2.224404
+C71 65 gnd 2.080806f
+R69 64 65 2.224404
+C72 66 gnd 2.080806f
+R70 65 66 2.224404
+C73 67 gnd 2.080806f
+R71 66 67 2.224404
+C74 68 gnd 2.080806f
+R72 67 68 2.224404
+C75 69 gnd 2.080806f
+R73 68 69 2.224404
+C76 70 gnd 2.080806f
+R74 69 70 2.224404
+C77 71 gnd 2.080806f
+R75 70 71 2.224404
+C78 72 gnd 2.080806f
+R76 71 72 2.224404
+C79 73 gnd 2.080806f
+R77 72 73 2.224404
+C80 74 gnd 2.080806f
+R78 73 74 2.224404
+C81 75 gnd 2.080806f
+R79 74 75 2.224404
+C82 76 gnd 2.080806f
+R80 75 76 2.224404
+C83 77 gnd 2.080806f
+R81 76 77 2.224404
+C84 78 gnd 2.080806f
+R82 77 78 2.224404
+C85 79 gnd 2.080806f
+R83 78 79 2.224404
+C86 80 gnd 2.080806f
+R84 79 80 2.224404
+C87 81 gnd 2.080806f
+R85 80 81 2.224404
+C88 82 gnd 2.080806f
+R86 81 82 2.224404
+C89 83 gnd 2.080806f
+R87 82 83 2.224404
+C90 84 gnd 2.080806f
+R88 83 84 2.224404
+C91 85 gnd 2.080806f
+R89 84 85 2.224404
+C92 86 gnd 2.080806f
+R90 85 86 2.224404
+C93 87 gnd 2.080806f
+R91 86 87 2.224404
+C94 88 gnd 2.080806f
+R92 88 87 2.224404
+R93 88 g1738_2 2.224404
+.ends
+
+.subckt netg183 g183_0 g183_1 g183_2 gnd
+C1  g183_0 gnd 2.080806f
+C2  g183_1 gnd 2.080806f
+C3  g183_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g183_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 6 5 2.224404
+C10 7 gnd 2.080806f
+R7 7 6 2.224404
+C11 8 gnd 2.080806f
+R8 8 7 2.224404
+C12 9 gnd 2.080806f
+R9 9 8 2.224404
+C13 10 gnd 2.080806f
+R10 10 9 2.224404
+C14 11 gnd 2.080806f
+R11 11 10 2.224404
+C15 12 gnd 2.080806f
+R12 12 11 2.224404
+C16 13 gnd 2.080806f
+R13 13 12 2.224404
+C17 14 gnd 2.080806f
+R14 14 13 2.224404
+C18 15 gnd 2.080806f
+R15 15 14 2.224404
+C19 16 gnd 2.080806f
+R16 16 15 2.224404
+C20 17 gnd 2.080806f
+R17 16 17 2.224404
+C21 18 gnd 2.080806f
+R18 18 17 2.224404
+C22 19 gnd 2.080806f
+R19 18 19 2.224404
+C23 20 gnd 2.080806f
+R20 20 19 2.224404
+C24 21 gnd 2.080806f
+R21 21 20 2.224404
+C25 22 gnd 2.080806f
+R22 22 21 2.224404
+C26 23 gnd 2.080806f
+R23 22 23 2.224404
+C27 24 gnd 2.080806f
+R24 24 23 2.224404
+C28 25 gnd 2.080806f
+R25 25 24 2.224404
+C29 26 gnd 2.080806f
+R26 26 25 2.224404
+C30 27 gnd 2.080806f
+R27 27 26 2.224404
+C31 28 gnd 2.080806f
+R28 28 27 2.224404
+C32 29 gnd 2.080806f
+R29 29 28 2.224404
+C33 30 gnd 2.080806f
+R30 30 29 2.224404
+C34 31 gnd 2.080806f
+R31 30 31 2.224404
+C35 32 gnd 2.080806f
+R32 31 32 2.224404
+R33 32 g183_2 2.224404
+C36 33 gnd 2.080806f
+R34 g183_0 33 2.224404
+C37 34 gnd 2.080806f
+R35 33 34 2.224404
+C38 35 gnd 2.080806f
+R36 34 35 2.224404
+C39 36 gnd 2.080806f
+R37 35 36 2.224404
+C40 37 gnd 2.080806f
+R38 36 37 2.224404
+C41 38 gnd 2.080806f
+R39 37 38 2.224404
+C42 39 gnd 2.080806f
+R40 38 39 2.224404
+C43 40 gnd 2.080806f
+R41 39 40 2.224404
+C44 41 gnd 2.080806f
+R42 40 41 2.224404
+C45 42 gnd 2.080806f
+R43 41 42 2.224404
+C46 43 gnd 2.080806f
+R44 42 43 2.224404
+C47 44 gnd 2.080806f
+R45 43 44 2.224404
+C48 45 gnd 2.080806f
+R46 44 45 2.224404
+C49 46 gnd 2.080806f
+R47 45 46 2.224404
+C50 47 gnd 2.080806f
+R48 46 47 2.224404
+C51 48 gnd 2.080806f
+R49 47 48 2.224404
+C52 49 gnd 2.080806f
+R50 48 49 2.224404
+C53 50 gnd 2.080806f
+R51 49 50 2.224404
+C54 51 gnd 2.080806f
+R52 50 51 2.224404
+C55 52 gnd 2.080806f
+R53 51 52 2.224404
+C56 53 gnd 2.080806f
+R54 52 53 2.224404
+C57 54 gnd 2.080806f
+R55 53 54 2.224404
+C58 55 gnd 2.080806f
+R56 54 55 2.224404
+C59 56 gnd 2.080806f
+R57 55 56 2.224404
+C60 57 gnd 2.080806f
+R58 56 57 2.224404
+C61 58 gnd 2.080806f
+R59 57 58 2.224404
+C62 59 gnd 2.080806f
+R60 58 59 2.224404
+C63 60 gnd 2.080806f
+R61 59 60 2.224404
+C64 61 gnd 2.080806f
+R62 60 61 2.224404
+C65 62 gnd 2.080806f
+R63 61 62 2.224404
+C66 63 gnd 2.080806f
+R64 62 63 2.224404
+C67 64 gnd 2.080806f
+R65 63 64 2.224404
+C68 65 gnd 2.080806f
+R66 64 65 2.224404
+C69 66 gnd 2.080806f
+R67 65 66 2.224404
+C70 67 gnd 2.080806f
+R68 66 67 2.224404
+C71 68 gnd 2.080806f
+R69 67 68 2.224404
+C72 69 gnd 2.080806f
+R70 68 69 2.224404
+C73 70 gnd 2.080806f
+R71 69 70 2.224404
+C74 71 gnd 2.080806f
+R72 70 71 2.224404
+C75 72 gnd 2.080806f
+R73 71 72 2.224404
+C76 73 gnd 2.080806f
+R74 72 73 2.224404
+C77 74 gnd 2.080806f
+R75 73 74 2.224404
+C78 75 gnd 2.080806f
+R76 74 75 2.224404
+C79 76 gnd 2.080806f
+R77 75 76 2.224404
+C80 77 gnd 2.080806f
+R78 76 77 2.224404
+C81 78 gnd 2.080806f
+R79 77 78 2.224404
+C82 79 gnd 2.080806f
+R80 78 79 2.224404
+C83 80 gnd 2.080806f
+R81 79 80 2.224404
+C84 81 gnd 2.080806f
+R82 80 81 2.224404
+C85 82 gnd 2.080806f
+R83 81 82 2.224404
+C86 83 gnd 2.080806f
+R84 82 83 2.224404
+R85 83 g183_1 2.224404
+.ends
+
+.subckt netg7465 g7465_1 g7465_0 gnd
+C1  g7465_1 gnd 2.080806f
+C2  g7465_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7465_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+C50 48 gnd 2.080806f
+R48 48 47 2.224404
+C51 49 gnd 2.080806f
+R49 49 48 2.224404
+C52 50 gnd 2.080806f
+R50 49 50 2.224404
+C53 51 gnd 2.080806f
+R51 50 51 2.224404
+C54 52 gnd 2.080806f
+R52 51 52 2.224404
+C55 53 gnd 2.080806f
+R53 52 53 2.224404
+C56 54 gnd 2.080806f
+R54 54 53 2.224404
+C57 55 gnd 2.080806f
+R55 55 54 2.224404
+C58 56 gnd 2.080806f
+R56 55 56 2.224404
+C59 57 gnd 2.080806f
+R57 57 56 2.224404
+C60 58 gnd 2.080806f
+R58 58 57 2.224404
+C61 59 gnd 2.080806f
+R59 59 58 2.224404
+C62 60 gnd 2.080806f
+R60 60 59 2.224404
+C63 61 gnd 2.080806f
+R61 60 61 2.224404
+C64 62 gnd 2.080806f
+R62 62 61 2.224404
+C65 63 gnd 2.080806f
+R63 63 62 2.224404
+C66 64 gnd 2.080806f
+R64 63 64 2.224404
+C67 65 gnd 2.080806f
+R65 65 64 2.224404
+C68 66 gnd 2.080806f
+R66 66 65 2.224404
+C69 67 gnd 2.080806f
+R67 66 67 2.224404
+C70 68 gnd 2.080806f
+R68 67 68 2.224404
+C71 69 gnd 2.080806f
+R69 68 69 2.224404
+C72 70 gnd 2.080806f
+R70 69 70 2.224404
+C73 71 gnd 2.080806f
+R71 71 70 2.224404
+C74 72 gnd 2.080806f
+R72 71 72 2.224404
+C75 73 gnd 2.080806f
+R73 73 72 2.224404
+C76 74 gnd 2.080806f
+R74 74 73 2.224404
+C77 75 gnd 2.080806f
+R75 75 74 2.224404
+C78 76 gnd 2.080806f
+R76 76 75 2.224404
+C79 77 gnd 2.080806f
+R77 77 76 2.224404
+C80 78 gnd 2.080806f
+R78 78 77 2.224404
+R79 g7465_1 78 2.224404
+.ends
+
+.subckt netg3 g3_2 g3_1 g3_0 gnd
+C1  g3_2 gnd 2.080806f
+C2  g3_1 gnd 2.080806f
+C3  g3_0 gnd 2.080806f
+R1 g3_0 g3_2 2.224404
+C4 1 gnd 2.080806f
+R2 1 g3_0 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 6 7 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 11 10 2.224404
+C15 12 gnd 2.080806f
+R13 12 11 2.224404
+C16 13 gnd 2.080806f
+R14 13 12 2.224404
+C17 14 gnd 2.080806f
+R15 14 13 2.224404
+C18 15 gnd 2.080806f
+R16 15 14 2.224404
+C19 16 gnd 2.080806f
+R17 16 15 2.224404
+C20 17 gnd 2.080806f
+R18 17 16 2.224404
+C21 18 gnd 2.080806f
+R19 18 17 2.224404
+C22 19 gnd 2.080806f
+R20 19 18 2.224404
+C23 20 gnd 2.080806f
+R21 20 19 2.224404
+C24 21 gnd 2.080806f
+R22 21 20 2.224404
+C25 22 gnd 2.080806f
+R23 22 21 2.224404
+C26 23 gnd 2.080806f
+R24 23 22 2.224404
+C27 24 gnd 2.080806f
+R25 24 23 2.224404
+C28 25 gnd 2.080806f
+R26 25 24 2.224404
+C29 26 gnd 2.080806f
+R27 26 25 2.224404
+C30 27 gnd 2.080806f
+R28 27 26 2.224404
+C31 28 gnd 2.080806f
+R29 28 27 2.224404
+C32 29 gnd 2.080806f
+R30 29 28 2.224404
+C33 30 gnd 2.080806f
+R31 30 29 2.224404
+C34 31 gnd 2.080806f
+R32 31 30 2.224404
+C35 32 gnd 2.080806f
+R33 32 31 2.224404
+C36 33 gnd 2.080806f
+R34 33 32 2.224404
+C37 34 gnd 2.080806f
+R35 34 33 2.224404
+C38 35 gnd 2.080806f
+R36 35 34 2.224404
+C39 36 gnd 2.080806f
+R37 36 35 2.224404
+C40 37 gnd 2.080806f
+R38 37 36 2.224404
+C41 38 gnd 2.080806f
+R39 38 37 2.224404
+C42 39 gnd 2.080806f
+R40 39 38 2.224404
+C43 40 gnd 2.080806f
+R41 40 39 2.224404
+C44 41 gnd 2.080806f
+R42 41 40 2.224404
+C45 42 gnd 2.080806f
+R43 42 41 2.224404
+C46 43 gnd 2.080806f
+R44 43 42 2.224404
+C47 44 gnd 2.080806f
+R45 44 43 2.224404
+C48 45 gnd 2.080806f
+R46 45 44 2.224404
+C49 46 gnd 2.080806f
+R47 46 45 2.224404
+C50 47 gnd 2.080806f
+R48 47 46 2.224404
+C51 48 gnd 2.080806f
+R49 48 47 2.224404
+C52 49 gnd 2.080806f
+R50 49 48 2.224404
+C53 50 gnd 2.080806f
+R51 50 49 2.224404
+C54 51 gnd 2.080806f
+R52 51 50 2.224404
+C55 52 gnd 2.080806f
+R53 52 51 2.224404
+C56 53 gnd 2.080806f
+R54 53 52 2.224404
+C57 54 gnd 2.080806f
+R55 54 53 2.224404
+C58 55 gnd 2.080806f
+R56 55 54 2.224404
+C59 56 gnd 2.080806f
+R57 56 55 2.224404
+C60 57 gnd 2.080806f
+R58 57 56 2.224404
+C61 58 gnd 2.080806f
+R59 58 57 2.224404
+C62 59 gnd 2.080806f
+R60 59 58 2.224404
+C63 60 gnd 2.080806f
+R61 60 59 2.224404
+C64 61 gnd 2.080806f
+R62 61 60 2.224404
+C65 62 gnd 2.080806f
+R63 62 61 2.224404
+C66 63 gnd 2.080806f
+R64 63 62 2.224404
+C67 64 gnd 2.080806f
+R65 64 63 2.224404
+C68 65 gnd 2.080806f
+R66 65 64 2.224404
+C69 66 gnd 2.080806f
+R67 66 65 2.224404
+C70 67 gnd 2.080806f
+R68 67 66 2.224404
+C71 68 gnd 2.080806f
+R69 68 67 2.224404
+C72 69 gnd 2.080806f
+R70 69 68 2.224404
+C73 70 gnd 2.080806f
+R71 70 69 2.224404
+C74 71 gnd 2.080806f
+R72 71 70 2.224404
+C75 72 gnd 2.080806f
+R73 72 71 2.224404
+C76 73 gnd 2.080806f
+R74 73 72 2.224404
+C77 74 gnd 2.080806f
+R75 74 73 2.224404
+C78 75 gnd 2.080806f
+R76 75 74 2.224404
+C79 76 gnd 2.080806f
+R77 76 75 2.224404
+C80 77 gnd 2.080806f
+R78 77 76 2.224404
+C81 78 gnd 2.080806f
+R79 78 77 2.224404
+C82 79 gnd 2.080806f
+R80 79 78 2.224404
+R81 g3_1 79 2.224404
+.ends
+
+.subckt netg1 g1_3 g1_1 g1_0 g1_2 gnd
+C1  g1_3 gnd 2.080806f
+C2  g1_1 gnd 2.080806f
+C3  g1_0 gnd 2.080806f
+C4  g1_2 gnd 2.080806f
+R1 g1_0 g1_1 2.224404
+C5 1 gnd 2.080806f
+R2 1 g1_0 2.224404
+C6 2 gnd 2.080806f
+R3 2 1 2.224404
+C7 3 gnd 2.080806f
+R4 3 2 2.224404
+C8 4 gnd 2.080806f
+R5 4 3 2.224404
+C9 5 gnd 2.080806f
+R6 4 5 2.224404
+C10 6 gnd 2.080806f
+R7 6 5 2.224404
+C11 7 gnd 2.080806f
+R8 7 6 2.224404
+C12 8 gnd 2.080806f
+R9 8 7 2.224404
+C13 9 gnd 2.080806f
+R10 9 8 2.224404
+C14 10 gnd 2.080806f
+R11 10 9 2.224404
+C15 11 gnd 2.080806f
+R12 11 10 2.224404
+C16 12 gnd 2.080806f
+R13 12 11 2.224404
+C17 13 gnd 2.080806f
+R14 13 12 2.224404
+C18 14 gnd 2.080806f
+R15 14 13 2.224404
+C19 15 gnd 2.080806f
+R16 15 14 2.224404
+C20 16 gnd 2.080806f
+R17 16 15 2.224404
+C21 17 gnd 2.080806f
+R18 17 16 2.224404
+C22 18 gnd 2.080806f
+R19 18 17 2.224404
+C23 19 gnd 2.080806f
+R20 19 18 2.224404
+C24 20 gnd 2.080806f
+R21 20 19 2.224404
+C25 21 gnd 2.080806f
+R22 21 20 2.224404
+C26 22 gnd 2.080806f
+R23 22 21 2.224404
+C27 23 gnd 2.080806f
+R24 23 22 2.224404
+C28 24 gnd 2.080806f
+R25 24 23 2.224404
+C29 25 gnd 2.080806f
+R26 25 24 2.224404
+C30 26 gnd 2.080806f
+R27 26 25 2.224404
+C31 27 gnd 2.080806f
+R28 27 26 2.224404
+C32 28 gnd 2.080806f
+R29 28 27 2.224404
+C33 29 gnd 2.080806f
+R30 29 28 2.224404
+C34 30 gnd 2.080806f
+R31 30 29 2.224404
+C35 31 gnd 2.080806f
+R32 31 30 2.224404
+C36 32 gnd 2.080806f
+R33 32 31 2.224404
+C37 33 gnd 2.080806f
+R34 33 32 2.224404
+C38 34 gnd 2.080806f
+R35 34 33 2.224404
+C39 35 gnd 2.080806f
+R36 35 34 2.224404
+C40 36 gnd 2.080806f
+R37 36 35 2.224404
+C41 37 gnd 2.080806f
+R38 37 36 2.224404
+C42 38 gnd 2.080806f
+R39 38 37 2.224404
+R40 g1_3 38 2.224404
+C43 39 gnd 2.080806f
+R41 39 g1_3 2.224404
+C44 40 gnd 2.080806f
+R42 40 39 2.224404
+C45 41 gnd 2.080806f
+R43 41 40 2.224404
+C46 42 gnd 2.080806f
+R44 42 41 2.224404
+C47 43 gnd 2.080806f
+R45 43 42 2.224404
+C48 44 gnd 2.080806f
+R46 44 43 2.224404
+C49 45 gnd 2.080806f
+R47 45 44 2.224404
+C50 46 gnd 2.080806f
+R48 46 45 2.224404
+C51 47 gnd 2.080806f
+R49 47 46 2.224404
+C52 48 gnd 2.080806f
+R50 48 47 2.224404
+C53 49 gnd 2.080806f
+R51 49 48 2.224404
+C54 50 gnd 2.080806f
+R52 50 49 2.224404
+C55 51 gnd 2.080806f
+R53 51 50 2.224404
+C56 52 gnd 2.080806f
+R54 52 51 2.224404
+C57 53 gnd 2.080806f
+R55 53 52 2.224404
+C58 54 gnd 2.080806f
+R56 54 53 2.224404
+C59 55 gnd 2.080806f
+R57 55 54 2.224404
+C60 56 gnd 2.080806f
+R58 56 55 2.224404
+C61 57 gnd 2.080806f
+R59 57 56 2.224404
+C62 58 gnd 2.080806f
+R60 58 57 2.224404
+C63 59 gnd 2.080806f
+R61 59 58 2.224404
+C64 60 gnd 2.080806f
+R62 60 59 2.224404
+C65 61 gnd 2.080806f
+R63 61 60 2.224404
+C66 62 gnd 2.080806f
+R64 62 61 2.224404
+C67 63 gnd 2.080806f
+R65 63 62 2.224404
+C68 64 gnd 2.080806f
+R66 64 63 2.224404
+C69 65 gnd 2.080806f
+R67 65 64 2.224404
+C70 66 gnd 2.080806f
+R68 66 65 2.224404
+C71 67 gnd 2.080806f
+R69 67 66 2.224404
+C72 68 gnd 2.080806f
+R70 68 67 2.224404
+C73 69 gnd 2.080806f
+R71 69 68 2.224404
+C74 70 gnd 2.080806f
+R72 70 69 2.224404
+C75 71 gnd 2.080806f
+R73 71 70 2.224404
+C76 72 gnd 2.080806f
+R74 72 71 2.224404
+C77 73 gnd 2.080806f
+R75 73 72 2.224404
+C78 74 gnd 2.080806f
+R76 74 73 2.224404
+C79 75 gnd 2.080806f
+R77 75 74 2.224404
+C80 76 gnd 2.080806f
+R78 76 75 2.224404
+C81 77 gnd 2.080806f
+R79 77 76 2.224404
+C82 78 gnd 2.080806f
+R80 78 77 2.224404
+C83 79 gnd 2.080806f
+R81 79 78 2.224404
+R82 g1_2 79 2.224404
+.ends
+
+.subckt netg167 g167_1 g167_2 g167_0 gnd
+C1  g167_1 gnd 2.080806f
+C2  g167_2 gnd 2.080806f
+C3  g167_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g167_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 6 5 2.224404
+C10 7 gnd 2.080806f
+R7 7 6 2.224404
+C11 8 gnd 2.080806f
+R8 8 7 2.224404
+C12 9 gnd 2.080806f
+R9 9 8 2.224404
+C13 10 gnd 2.080806f
+R10 10 9 2.224404
+C14 11 gnd 2.080806f
+R11 11 10 2.224404
+C15 12 gnd 2.080806f
+R12 12 11 2.224404
+C16 13 gnd 2.080806f
+R13 13 12 2.224404
+C17 14 gnd 2.080806f
+R14 14 13 2.224404
+C18 15 gnd 2.080806f
+R15 15 14 2.224404
+C19 16 gnd 2.080806f
+R16 16 15 2.224404
+C20 17 gnd 2.080806f
+R17 17 16 2.224404
+C21 18 gnd 2.080806f
+R18 18 17 2.224404
+C22 19 gnd 2.080806f
+R19 19 18 2.224404
+C23 20 gnd 2.080806f
+R20 20 19 2.224404
+R21 g167_2 20 2.224404
+C24 21 gnd 2.080806f
+R22 g167_0 21 2.224404
+C25 22 gnd 2.080806f
+R23 21 22 2.224404
+C26 23 gnd 2.080806f
+R24 22 23 2.224404
+C27 24 gnd 2.080806f
+R25 23 24 2.224404
+C28 25 gnd 2.080806f
+R26 24 25 2.224404
+C29 26 gnd 2.080806f
+R27 25 26 2.224404
+C30 27 gnd 2.080806f
+R28 26 27 2.224404
+C31 28 gnd 2.080806f
+R29 27 28 2.224404
+C32 29 gnd 2.080806f
+R30 28 29 2.224404
+C33 30 gnd 2.080806f
+R31 29 30 2.224404
+C34 31 gnd 2.080806f
+R32 30 31 2.224404
+C35 32 gnd 2.080806f
+R33 31 32 2.224404
+C36 33 gnd 2.080806f
+R34 32 33 2.224404
+C37 34 gnd 2.080806f
+R35 33 34 2.224404
+C38 35 gnd 2.080806f
+R36 34 35 2.224404
+C39 36 gnd 2.080806f
+R37 35 36 2.224404
+C40 37 gnd 2.080806f
+R38 36 37 2.224404
+C41 38 gnd 2.080806f
+R39 37 38 2.224404
+C42 39 gnd 2.080806f
+R40 38 39 2.224404
+C43 40 gnd 2.080806f
+R41 39 40 2.224404
+C44 41 gnd 2.080806f
+R42 40 41 2.224404
+C45 42 gnd 2.080806f
+R43 41 42 2.224404
+C46 43 gnd 2.080806f
+R44 42 43 2.224404
+C47 44 gnd 2.080806f
+R45 43 44 2.224404
+C48 45 gnd 2.080806f
+R46 44 45 2.224404
+C49 46 gnd 2.080806f
+R47 45 46 2.224404
+C50 47 gnd 2.080806f
+R48 46 47 2.224404
+C51 48 gnd 2.080806f
+R49 47 48 2.224404
+C52 49 gnd 2.080806f
+R50 48 49 2.224404
+C53 50 gnd 2.080806f
+R51 49 50 2.224404
+C54 51 gnd 2.080806f
+R52 50 51 2.224404
+C55 52 gnd 2.080806f
+R53 51 52 2.224404
+C56 53 gnd 2.080806f
+R54 52 53 2.224404
+C57 54 gnd 2.080806f
+R55 53 54 2.224404
+C58 55 gnd 2.080806f
+R56 54 55 2.224404
+C59 56 gnd 2.080806f
+R57 55 56 2.224404
+C60 57 gnd 2.080806f
+R58 56 57 2.224404
+C61 58 gnd 2.080806f
+R59 57 58 2.224404
+C62 59 gnd 2.080806f
+R60 58 59 2.224404
+C63 60 gnd 2.080806f
+R61 59 60 2.224404
+C64 61 gnd 2.080806f
+R62 60 61 2.224404
+C65 62 gnd 2.080806f
+R63 61 62 2.224404
+C66 63 gnd 2.080806f
+R64 62 63 2.224404
+C67 64 gnd 2.080806f
+R65 63 64 2.224404
+C68 65 gnd 2.080806f
+R66 64 65 2.224404
+C69 66 gnd 2.080806f
+R67 65 66 2.224404
+C70 67 gnd 2.080806f
+R68 66 67 2.224404
+C71 68 gnd 2.080806f
+R69 67 68 2.224404
+C72 69 gnd 2.080806f
+R70 68 69 2.224404
+C73 70 gnd 2.080806f
+R71 69 70 2.224404
+C74 71 gnd 2.080806f
+R72 70 71 2.224404
+C75 72 gnd 2.080806f
+R73 71 72 2.224404
+C76 73 gnd 2.080806f
+R74 72 73 2.224404
+C77 74 gnd 2.080806f
+R75 73 74 2.224404
+C78 75 gnd 2.080806f
+R76 74 75 2.224404
+C79 76 gnd 2.080806f
+R77 75 76 2.224404
+C80 77 gnd 2.080806f
+R78 76 77 2.224404
+C81 78 gnd 2.080806f
+R79 77 78 2.224404
+R80 78 g167_1 2.224404
+.ends
+
+.subckt netg7448 g7448_0 g7448_1 gnd
+C1  g7448_0 gnd 2.080806f
+C2  g7448_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7448_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+C50 48 gnd 2.080806f
+R48 48 47 2.224404
+C51 49 gnd 2.080806f
+R49 48 49 2.224404
+C52 50 gnd 2.080806f
+R50 49 50 2.224404
+C53 51 gnd 2.080806f
+R51 51 50 2.224404
+C54 52 gnd 2.080806f
+R52 52 51 2.224404
+C55 53 gnd 2.080806f
+R53 53 52 2.224404
+C56 54 gnd 2.080806f
+R54 53 54 2.224404
+C57 55 gnd 2.080806f
+R55 54 55 2.224404
+C58 56 gnd 2.080806f
+R56 56 55 2.224404
+C59 57 gnd 2.080806f
+R57 57 56 2.224404
+C60 58 gnd 2.080806f
+R58 58 57 2.224404
+C61 59 gnd 2.080806f
+R59 59 58 2.224404
+C62 60 gnd 2.080806f
+R60 60 59 2.224404
+C63 61 gnd 2.080806f
+R61 61 60 2.224404
+C64 62 gnd 2.080806f
+R62 62 61 2.224404
+C65 63 gnd 2.080806f
+R63 63 62 2.224404
+C66 64 gnd 2.080806f
+R64 63 64 2.224404
+C67 65 gnd 2.080806f
+R65 64 65 2.224404
+C68 66 gnd 2.080806f
+R66 65 66 2.224404
+C69 67 gnd 2.080806f
+R67 67 66 2.224404
+C70 68 gnd 2.080806f
+R68 68 67 2.224404
+C71 69 gnd 2.080806f
+R69 69 68 2.224404
+C72 70 gnd 2.080806f
+R70 69 70 2.224404
+C73 71 gnd 2.080806f
+R71 70 71 2.224404
+C74 72 gnd 2.080806f
+R72 71 72 2.224404
+C75 73 gnd 2.080806f
+R73 72 73 2.224404
+C76 74 gnd 2.080806f
+R74 73 74 2.224404
+C77 75 gnd 2.080806f
+R75 74 75 2.224404
+C78 76 gnd 2.080806f
+R76 76 75 2.224404
+C79 77 gnd 2.080806f
+R77 77 76 2.224404
+C80 78 gnd 2.080806f
+R78 77 78 2.224404
+C81 79 gnd 2.080806f
+R79 79 78 2.224404
+R80 g7448_1 79 2.224404
+.ends
+
+.subckt netg7490 g7490_1 g7490_0 gnd
+C1  g7490_1 gnd 2.080806f
+C2  g7490_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7490_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+C50 48 gnd 2.080806f
+R48 48 47 2.224404
+C51 49 gnd 2.080806f
+R49 49 48 2.224404
+C52 50 gnd 2.080806f
+R50 49 50 2.224404
+C53 51 gnd 2.080806f
+R51 51 50 2.224404
+C54 52 gnd 2.080806f
+R52 52 51 2.224404
+C55 53 gnd 2.080806f
+R53 53 52 2.224404
+C56 54 gnd 2.080806f
+R54 53 54 2.224404
+C57 55 gnd 2.080806f
+R55 55 54 2.224404
+C58 56 gnd 2.080806f
+R56 56 55 2.224404
+C59 57 gnd 2.080806f
+R57 57 56 2.224404
+C60 58 gnd 2.080806f
+R58 58 57 2.224404
+C61 59 gnd 2.080806f
+R59 58 59 2.224404
+C62 60 gnd 2.080806f
+R60 60 59 2.224404
+C63 61 gnd 2.080806f
+R61 61 60 2.224404
+C64 62 gnd 2.080806f
+R62 62 61 2.224404
+C65 63 gnd 2.080806f
+R63 63 62 2.224404
+C66 64 gnd 2.080806f
+R64 64 63 2.224404
+C67 65 gnd 2.080806f
+R65 64 65 2.224404
+C68 66 gnd 2.080806f
+R66 66 65 2.224404
+C69 67 gnd 2.080806f
+R67 67 66 2.224404
+C70 68 gnd 2.080806f
+R68 68 67 2.224404
+C71 69 gnd 2.080806f
+R69 69 68 2.224404
+C72 70 gnd 2.080806f
+R70 70 69 2.224404
+C73 71 gnd 2.080806f
+R71 70 71 2.224404
+C74 72 gnd 2.080806f
+R72 71 72 2.224404
+C75 73 gnd 2.080806f
+R73 72 73 2.224404
+C76 74 gnd 2.080806f
+R74 73 74 2.224404
+C77 75 gnd 2.080806f
+R75 75 74 2.224404
+C78 76 gnd 2.080806f
+R76 75 76 2.224404
+C79 77 gnd 2.080806f
+R77 76 77 2.224404
+C80 78 gnd 2.080806f
+R78 78 77 2.224404
+C81 79 gnd 2.080806f
+R79 78 79 2.224404
+C82 80 gnd 2.080806f
+R80 80 79 2.224404
+R81 g7490_1 80 2.224404
+.ends
+
+.subckt netg1744 g1744_1 g1744_0 g1744_4 g1744_3 g1744_2 g1744_5 gnd
+C1  g1744_1 gnd 2.080806f
+C2  g1744_0 gnd 2.080806f
+C3  g1744_4 gnd 2.080806f
+C4  g1744_3 gnd 2.080806f
+C5  g1744_2 gnd 2.080806f
+C6  g1744_5 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 g1744_0 1 2.224404
+C8 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g1744_1 2.224404
+C9 3 gnd 2.080806f
+R4 1 3 2.224404
+R5 3 g1744_4 2.224404
+C10 4 gnd 2.080806f
+R6 g1744_1 4 2.224404
+C11 5 gnd 2.080806f
+R7 4 5 2.224404
+C12 6 gnd 2.080806f
+R8 5 6 2.224404
+R9 6 g1744_3 2.224404
+C13 7 gnd 2.080806f
+R10 g1744_4 7 2.224404
+C14 8 gnd 2.080806f
+R11 7 8 2.224404
+C15 9 gnd 2.080806f
+R12 8 9 2.224404
+C16 10 gnd 2.080806f
+R13 9 10 2.224404
+C17 11 gnd 2.080806f
+R14 10 11 2.224404
+C18 12 gnd 2.080806f
+R15 11 12 2.224404
+C19 13 gnd 2.080806f
+R16 12 13 2.224404
+C20 14 gnd 2.080806f
+R17 13 14 2.224404
+C21 15 gnd 2.080806f
+R18 14 15 2.224404
+C22 16 gnd 2.080806f
+R19 15 16 2.224404
+C23 17 gnd 2.080806f
+R20 16 17 2.224404
+C24 18 gnd 2.080806f
+R21 17 18 2.224404
+C25 19 gnd 2.080806f
+R22 18 19 2.224404
+C26 20 gnd 2.080806f
+R23 19 20 2.224404
+C27 21 gnd 2.080806f
+R24 21 20 2.224404
+C28 22 gnd 2.080806f
+R25 21 22 2.224404
+C29 23 gnd 2.080806f
+R26 22 23 2.224404
+C30 24 gnd 2.080806f
+R27 23 24 2.224404
+C31 25 gnd 2.080806f
+R28 24 25 2.224404
+C32 26 gnd 2.080806f
+R29 25 26 2.224404
+C33 27 gnd 2.080806f
+R30 26 27 2.224404
+C34 28 gnd 2.080806f
+R31 27 28 2.224404
+C35 29 gnd 2.080806f
+R32 28 29 2.224404
+C36 30 gnd 2.080806f
+R33 29 30 2.224404
+C37 31 gnd 2.080806f
+R34 30 31 2.224404
+C38 32 gnd 2.080806f
+R35 31 32 2.224404
+C39 33 gnd 2.080806f
+R36 32 33 2.224404
+C40 34 gnd 2.080806f
+R37 33 34 2.224404
+C41 35 gnd 2.080806f
+R38 34 35 2.224404
+C42 36 gnd 2.080806f
+R39 35 36 2.224404
+C43 37 gnd 2.080806f
+R40 36 37 2.224404
+C44 38 gnd 2.080806f
+R41 37 38 2.224404
+C45 39 gnd 2.080806f
+R42 38 39 2.224404
+C46 40 gnd 2.080806f
+R43 40 39 2.224404
+C47 41 gnd 2.080806f
+R44 40 41 2.224404
+C48 42 gnd 2.080806f
+R45 41 42 2.224404
+C49 43 gnd 2.080806f
+R46 42 43 2.224404
+C50 44 gnd 2.080806f
+R47 43 44 2.224404
+C51 45 gnd 2.080806f
+R48 44 45 2.224404
+C52 46 gnd 2.080806f
+R49 45 46 2.224404
+C53 47 gnd 2.080806f
+R50 46 47 2.224404
+C54 48 gnd 2.080806f
+R51 47 48 2.224404
+C55 49 gnd 2.080806f
+R52 48 49 2.224404
+C56 50 gnd 2.080806f
+R53 49 50 2.224404
+C57 51 gnd 2.080806f
+R54 50 51 2.224404
+C58 52 gnd 2.080806f
+R55 51 52 2.224404
+C59 53 gnd 2.080806f
+R56 52 53 2.224404
+C60 54 gnd 2.080806f
+R57 53 54 2.224404
+C61 55 gnd 2.080806f
+R58 54 55 2.224404
+C62 56 gnd 2.080806f
+R59 55 56 2.224404
+C63 57 gnd 2.080806f
+R60 57 56 2.224404
+C64 58 gnd 2.080806f
+R61 58 57 2.224404
+C65 59 gnd 2.080806f
+R62 59 58 2.224404
+C66 60 gnd 2.080806f
+R63 59 60 2.224404
+C67 61 gnd 2.080806f
+R64 60 61 2.224404
+C68 62 gnd 2.080806f
+R65 61 62 2.224404
+C69 63 gnd 2.080806f
+R66 62 63 2.224404
+C70 64 gnd 2.080806f
+R67 63 64 2.224404
+C71 65 gnd 2.080806f
+R68 64 65 2.224404
+C72 66 gnd 2.080806f
+R69 65 66 2.224404
+C73 67 gnd 2.080806f
+R70 66 67 2.224404
+C74 68 gnd 2.080806f
+R71 67 68 2.224404
+C75 69 gnd 2.080806f
+R72 68 69 2.224404
+C76 70 gnd 2.080806f
+R73 70 69 2.224404
+C77 71 gnd 2.080806f
+R74 70 71 2.224404
+C78 72 gnd 2.080806f
+R75 71 72 2.224404
+C79 73 gnd 2.080806f
+R76 73 72 2.224404
+C80 74 gnd 2.080806f
+R77 73 74 2.224404
+C81 75 gnd 2.080806f
+R78 74 75 2.224404
+C82 76 gnd 2.080806f
+R79 75 76 2.224404
+C83 77 gnd 2.080806f
+R80 77 76 2.224404
+C84 78 gnd 2.080806f
+R81 77 78 2.224404
+C85 79 gnd 2.080806f
+R82 78 79 2.224404
+C86 80 gnd 2.080806f
+R83 79 80 2.224404
+C87 81 gnd 2.080806f
+R84 80 81 2.224404
+C88 82 gnd 2.080806f
+R85 81 82 2.224404
+C89 83 gnd 2.080806f
+R86 82 83 2.224404
+C90 84 gnd 2.080806f
+R87 83 84 2.224404
+C91 85 gnd 2.080806f
+R88 84 85 2.224404
+C92 86 gnd 2.080806f
+R89 85 86 2.224404
+C93 87 gnd 2.080806f
+R90 86 87 2.224404
+C94 88 gnd 2.080806f
+R91 87 88 2.224404
+C95 89 gnd 2.080806f
+R92 88 89 2.224404
+C96 90 gnd 2.080806f
+R93 89 90 2.224404
+C97 91 gnd 2.080806f
+R94 90 91 2.224404
+C98 92 gnd 2.080806f
+R95 91 92 2.224404
+R96 92 g1744_5 2.224404
+C99 93 gnd 2.080806f
+R97 g1744_5 93 2.224404
+C100 94 gnd 2.080806f
+R98 93 94 2.224404
+C101 95 gnd 2.080806f
+R99 94 95 2.224404
+R100 95 g1744_2 2.224404
+.ends
+
+.subckt netg7466 g7466_1 g7466_0 gnd
+C1  g7466_1 gnd 2.080806f
+C2  g7466_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7466_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+C50 48 gnd 2.080806f
+R48 48 47 2.224404
+C51 49 gnd 2.080806f
+R49 49 48 2.224404
+C52 50 gnd 2.080806f
+R50 50 49 2.224404
+C53 51 gnd 2.080806f
+R51 51 50 2.224404
+C54 52 gnd 2.080806f
+R52 52 51 2.224404
+C55 53 gnd 2.080806f
+R53 52 53 2.224404
+C56 54 gnd 2.080806f
+R54 53 54 2.224404
+C57 55 gnd 2.080806f
+R55 54 55 2.224404
+C58 56 gnd 2.080806f
+R56 55 56 2.224404
+C59 57 gnd 2.080806f
+R57 57 56 2.224404
+C60 58 gnd 2.080806f
+R58 58 57 2.224404
+C61 59 gnd 2.080806f
+R59 58 59 2.224404
+C62 60 gnd 2.080806f
+R60 59 60 2.224404
+C63 61 gnd 2.080806f
+R61 61 60 2.224404
+C64 62 gnd 2.080806f
+R62 62 61 2.224404
+C65 63 gnd 2.080806f
+R63 62 63 2.224404
+C66 64 gnd 2.080806f
+R64 64 63 2.224404
+C67 65 gnd 2.080806f
+R65 65 64 2.224404
+C68 66 gnd 2.080806f
+R66 65 66 2.224404
+C69 67 gnd 2.080806f
+R67 66 67 2.224404
+C70 68 gnd 2.080806f
+R68 67 68 2.224404
+C71 69 gnd 2.080806f
+R69 69 68 2.224404
+C72 70 gnd 2.080806f
+R70 70 69 2.224404
+C73 71 gnd 2.080806f
+R71 71 70 2.224404
+C74 72 gnd 2.080806f
+R72 71 72 2.224404
+C75 73 gnd 2.080806f
+R73 72 73 2.224404
+C76 74 gnd 2.080806f
+R74 73 74 2.224404
+C77 75 gnd 2.080806f
+R75 74 75 2.224404
+C78 76 gnd 2.080806f
+R76 75 76 2.224404
+C79 77 gnd 2.080806f
+R77 76 77 2.224404
+C80 78 gnd 2.080806f
+R78 78 77 2.224404
+C81 79 gnd 2.080806f
+R79 79 78 2.224404
+C82 80 gnd 2.080806f
+R80 79 80 2.224404
+C83 81 gnd 2.080806f
+R81 81 80 2.224404
+R82 g7466_1 81 2.224404
+.ends
+
+.subckt netg178 g178_2 g178_1 g178_0 gnd
+C1  g178_2 gnd 2.080806f
+C2  g178_1 gnd 2.080806f
+C3  g178_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g178_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 6 5 2.224404
+C10 7 gnd 2.080806f
+R7 6 7 2.224404
+C11 8 gnd 2.080806f
+R8 7 8 2.224404
+C12 9 gnd 2.080806f
+R9 9 8 2.224404
+C13 10 gnd 2.080806f
+R10 10 9 2.224404
+C14 11 gnd 2.080806f
+R11 11 10 2.224404
+C15 12 gnd 2.080806f
+R12 12 11 2.224404
+C16 13 gnd 2.080806f
+R13 13 12 2.224404
+C17 14 gnd 2.080806f
+R14 14 13 2.224404
+C18 15 gnd 2.080806f
+R15 15 14 2.224404
+C19 16 gnd 2.080806f
+R16 16 15 2.224404
+C20 17 gnd 2.080806f
+R17 17 16 2.224404
+C21 18 gnd 2.080806f
+R18 18 17 2.224404
+C22 19 gnd 2.080806f
+R19 19 18 2.224404
+C23 20 gnd 2.080806f
+R20 20 19 2.224404
+C24 21 gnd 2.080806f
+R21 21 20 2.224404
+C25 22 gnd 2.080806f
+R22 21 22 2.224404
+C26 23 gnd 2.080806f
+R23 23 22 2.224404
+C27 24 gnd 2.080806f
+R24 24 23 2.224404
+C28 25 gnd 2.080806f
+R25 25 24 2.224404
+C29 26 gnd 2.080806f
+R26 25 26 2.224404
+C30 27 gnd 2.080806f
+R27 27 26 2.224404
+C31 28 gnd 2.080806f
+R28 28 27 2.224404
+C32 29 gnd 2.080806f
+R29 29 28 2.224404
+C33 30 gnd 2.080806f
+R30 29 30 2.224404
+C34 31 gnd 2.080806f
+R31 31 30 2.224404
+C35 32 gnd 2.080806f
+R32 31 32 2.224404
+C36 33 gnd 2.080806f
+R33 32 33 2.224404
+R34 33 g178_1 2.224404
+C37 34 gnd 2.080806f
+R35 g178_0 34 2.224404
+C38 35 gnd 2.080806f
+R36 34 35 2.224404
+C39 36 gnd 2.080806f
+R37 35 36 2.224404
+C40 37 gnd 2.080806f
+R38 36 37 2.224404
+C41 38 gnd 2.080806f
+R39 37 38 2.224404
+C42 39 gnd 2.080806f
+R40 38 39 2.224404
+C43 40 gnd 2.080806f
+R41 39 40 2.224404
+C44 41 gnd 2.080806f
+R42 40 41 2.224404
+C45 42 gnd 2.080806f
+R43 41 42 2.224404
+C46 43 gnd 2.080806f
+R44 42 43 2.224404
+C47 44 gnd 2.080806f
+R45 43 44 2.224404
+C48 45 gnd 2.080806f
+R46 44 45 2.224404
+C49 46 gnd 2.080806f
+R47 45 46 2.224404
+C50 47 gnd 2.080806f
+R48 46 47 2.224404
+C51 48 gnd 2.080806f
+R49 47 48 2.224404
+C52 49 gnd 2.080806f
+R50 48 49 2.224404
+C53 50 gnd 2.080806f
+R51 49 50 2.224404
+C54 51 gnd 2.080806f
+R52 50 51 2.224404
+C55 52 gnd 2.080806f
+R53 51 52 2.224404
+C56 53 gnd 2.080806f
+R54 52 53 2.224404
+C57 54 gnd 2.080806f
+R55 53 54 2.224404
+C58 55 gnd 2.080806f
+R56 54 55 2.224404
+C59 56 gnd 2.080806f
+R57 55 56 2.224404
+C60 57 gnd 2.080806f
+R58 56 57 2.224404
+C61 58 gnd 2.080806f
+R59 57 58 2.224404
+C62 59 gnd 2.080806f
+R60 58 59 2.224404
+C63 60 gnd 2.080806f
+R61 59 60 2.224404
+C64 61 gnd 2.080806f
+R62 60 61 2.224404
+C65 62 gnd 2.080806f
+R63 61 62 2.224404
+C66 63 gnd 2.080806f
+R64 62 63 2.224404
+C67 64 gnd 2.080806f
+R65 63 64 2.224404
+C68 65 gnd 2.080806f
+R66 64 65 2.224404
+C69 66 gnd 2.080806f
+R67 65 66 2.224404
+C70 67 gnd 2.080806f
+R68 66 67 2.224404
+C71 68 gnd 2.080806f
+R69 67 68 2.224404
+C72 69 gnd 2.080806f
+R70 68 69 2.224404
+C73 70 gnd 2.080806f
+R71 69 70 2.224404
+C74 71 gnd 2.080806f
+R72 70 71 2.224404
+C75 72 gnd 2.080806f
+R73 71 72 2.224404
+C76 73 gnd 2.080806f
+R74 72 73 2.224404
+C77 74 gnd 2.080806f
+R75 73 74 2.224404
+C78 75 gnd 2.080806f
+R76 74 75 2.224404
+C79 76 gnd 2.080806f
+R77 75 76 2.224404
+C80 77 gnd 2.080806f
+R78 76 77 2.224404
+C81 78 gnd 2.080806f
+R79 77 78 2.224404
+C82 79 gnd 2.080806f
+R80 78 79 2.224404
+C83 80 gnd 2.080806f
+R81 79 80 2.224404
+C84 81 gnd 2.080806f
+R82 80 81 2.224404
+C85 82 gnd 2.080806f
+R83 81 82 2.224404
+C86 83 gnd 2.080806f
+R84 82 83 2.224404
+C87 84 gnd 2.080806f
+R85 83 84 2.224404
+C88 85 gnd 2.080806f
+R86 84 85 2.224404
+C89 86 gnd 2.080806f
+R87 85 86 2.224404
+C90 87 gnd 2.080806f
+R88 86 87 2.224404
+C91 88 gnd 2.080806f
+R89 87 88 2.224404
+R90 88 g178_2 2.224404
+.ends
+
+.subckt netg30 g30_0 g30_2 g30_1 gnd
+C1  g30_0 gnd 2.080806f
+C2  g30_2 gnd 2.080806f
+C3  g30_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g30_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+C8 5 gnd 2.080806f
+R5 4 5 2.224404
+C9 6 gnd 2.080806f
+R6 5 6 2.224404
+C10 7 gnd 2.080806f
+R7 6 7 2.224404
+C11 8 gnd 2.080806f
+R8 7 8 2.224404
+C12 9 gnd 2.080806f
+R9 8 9 2.224404
+C13 10 gnd 2.080806f
+R10 9 10 2.224404
+C14 11 gnd 2.080806f
+R11 10 11 2.224404
+C15 12 gnd 2.080806f
+R12 11 12 2.224404
+C16 13 gnd 2.080806f
+R13 12 13 2.224404
+C17 14 gnd 2.080806f
+R14 13 14 2.224404
+C18 15 gnd 2.080806f
+R15 14 15 2.224404
+C19 16 gnd 2.080806f
+R16 15 16 2.224404
+C20 17 gnd 2.080806f
+R17 16 17 2.224404
+C21 18 gnd 2.080806f
+R18 17 18 2.224404
+C22 19 gnd 2.080806f
+R19 18 19 2.224404
+C23 20 gnd 2.080806f
+R20 19 20 2.224404
+C24 21 gnd 2.080806f
+R21 20 21 2.224404
+C25 22 gnd 2.080806f
+R22 21 22 2.224404
+C26 23 gnd 2.080806f
+R23 22 23 2.224404
+C27 24 gnd 2.080806f
+R24 23 24 2.224404
+C28 25 gnd 2.080806f
+R25 24 25 2.224404
+C29 26 gnd 2.080806f
+R26 25 26 2.224404
+C30 27 gnd 2.080806f
+R27 26 27 2.224404
+C31 28 gnd 2.080806f
+R28 27 28 2.224404
+C32 29 gnd 2.080806f
+R29 28 29 2.224404
+C33 30 gnd 2.080806f
+R30 29 30 2.224404
+C34 31 gnd 2.080806f
+R31 30 31 2.224404
+C35 32 gnd 2.080806f
+R32 31 32 2.224404
+C36 33 gnd 2.080806f
+R33 32 33 2.224404
+C37 34 gnd 2.080806f
+R34 33 34 2.224404
+C38 35 gnd 2.080806f
+R35 34 35 2.224404
+C39 36 gnd 2.080806f
+R36 35 36 2.224404
+C40 37 gnd 2.080806f
+R37 36 37 2.224404
+C41 38 gnd 2.080806f
+R38 37 38 2.224404
+C42 39 gnd 2.080806f
+R39 38 39 2.224404
+C43 40 gnd 2.080806f
+R40 39 40 2.224404
+C44 41 gnd 2.080806f
+R41 40 41 2.224404
+C45 42 gnd 2.080806f
+R42 42 41 2.224404
+C46 43 gnd 2.080806f
+R43 42 43 2.224404
+C47 44 gnd 2.080806f
+R44 43 44 2.224404
+C48 45 gnd 2.080806f
+R45 44 45 2.224404
+C49 46 gnd 2.080806f
+R46 45 46 2.224404
+C50 47 gnd 2.080806f
+R47 46 47 2.224404
+C51 48 gnd 2.080806f
+R48 47 48 2.224404
+C52 49 gnd 2.080806f
+R49 48 49 2.224404
+C53 50 gnd 2.080806f
+R50 49 50 2.224404
+C54 51 gnd 2.080806f
+R51 50 51 2.224404
+C55 52 gnd 2.080806f
+R52 51 52 2.224404
+C56 53 gnd 2.080806f
+R53 52 53 2.224404
+C57 54 gnd 2.080806f
+R54 53 54 2.224404
+C58 55 gnd 2.080806f
+R55 54 55 2.224404
+C59 56 gnd 2.080806f
+R56 55 56 2.224404
+C60 57 gnd 2.080806f
+R57 56 57 2.224404
+C61 58 gnd 2.080806f
+R58 57 58 2.224404
+C62 59 gnd 2.080806f
+R59 58 59 2.224404
+C63 60 gnd 2.080806f
+R60 59 60 2.224404
+C64 61 gnd 2.080806f
+R61 60 61 2.224404
+C65 62 gnd 2.080806f
+R62 61 62 2.224404
+C66 63 gnd 2.080806f
+R63 62 63 2.224404
+C67 64 gnd 2.080806f
+R64 63 64 2.224404
+C68 65 gnd 2.080806f
+R65 64 65 2.224404
+C69 66 gnd 2.080806f
+R66 65 66 2.224404
+C70 67 gnd 2.080806f
+R67 66 67 2.224404
+C71 68 gnd 2.080806f
+R68 67 68 2.224404
+C72 69 gnd 2.080806f
+R69 68 69 2.224404
+C73 70 gnd 2.080806f
+R70 69 70 2.224404
+C74 71 gnd 2.080806f
+R71 70 71 2.224404
+C75 72 gnd 2.080806f
+R72 71 72 2.224404
+C76 73 gnd 2.080806f
+R73 72 73 2.224404
+C77 74 gnd 2.080806f
+R74 73 74 2.224404
+C78 75 gnd 2.080806f
+R75 74 75 2.224404
+C79 76 gnd 2.080806f
+R76 75 76 2.224404
+C80 77 gnd 2.080806f
+R77 76 77 2.224404
+C81 78 gnd 2.080806f
+R78 77 78 2.224404
+C82 79 gnd 2.080806f
+R79 78 79 2.224404
+C83 80 gnd 2.080806f
+R80 79 80 2.224404
+C84 81 gnd 2.080806f
+R81 80 81 2.224404
+C85 82 gnd 2.080806f
+R82 81 82 2.224404
+C86 83 gnd 2.080806f
+R83 82 83 2.224404
+C87 84 gnd 2.080806f
+R84 83 84 2.224404
+C88 85 gnd 2.080806f
+R85 84 85 2.224404
+C89 86 gnd 2.080806f
+R86 85 86 2.224404
+R87 g30_1 86 2.224404
+C90 87 gnd 2.080806f
+R88 87 g30_1 2.224404
+C91 88 gnd 2.080806f
+R89 88 87 2.224404
+R90 g30_2 88 2.224404
+.ends
+
+.subckt netg7467 g7467_0 g7467_1 gnd
+C1  g7467_0 gnd 2.080806f
+C2  g7467_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7467_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+C50 48 gnd 2.080806f
+R48 47 48 2.224404
+C51 49 gnd 2.080806f
+R49 48 49 2.224404
+C52 50 gnd 2.080806f
+R50 49 50 2.224404
+C53 51 gnd 2.080806f
+R51 50 51 2.224404
+C54 52 gnd 2.080806f
+R52 52 51 2.224404
+C55 53 gnd 2.080806f
+R53 53 52 2.224404
+C56 54 gnd 2.080806f
+R54 54 53 2.224404
+C57 55 gnd 2.080806f
+R55 55 54 2.224404
+C58 56 gnd 2.080806f
+R56 55 56 2.224404
+C59 57 gnd 2.080806f
+R57 57 56 2.224404
+C60 58 gnd 2.080806f
+R58 58 57 2.224404
+C61 59 gnd 2.080806f
+R59 58 59 2.224404
+C62 60 gnd 2.080806f
+R60 60 59 2.224404
+C63 61 gnd 2.080806f
+R61 60 61 2.224404
+C64 62 gnd 2.080806f
+R62 62 61 2.224404
+C65 63 gnd 2.080806f
+R63 62 63 2.224404
+C66 64 gnd 2.080806f
+R64 63 64 2.224404
+C67 65 gnd 2.080806f
+R65 64 65 2.224404
+C68 66 gnd 2.080806f
+R66 65 66 2.224404
+C69 67 gnd 2.080806f
+R67 66 67 2.224404
+C70 68 gnd 2.080806f
+R68 67 68 2.224404
+C71 69 gnd 2.080806f
+R69 68 69 2.224404
+C72 70 gnd 2.080806f
+R70 69 70 2.224404
+C73 71 gnd 2.080806f
+R71 70 71 2.224404
+C74 72 gnd 2.080806f
+R72 71 72 2.224404
+C75 73 gnd 2.080806f
+R73 72 73 2.224404
+C76 74 gnd 2.080806f
+R74 73 74 2.224404
+C77 75 gnd 2.080806f
+R75 75 74 2.224404
+C78 76 gnd 2.080806f
+R76 76 75 2.224404
+C79 77 gnd 2.080806f
+R77 77 76 2.224404
+C80 78 gnd 2.080806f
+R78 77 78 2.224404
+C81 79 gnd 2.080806f
+R79 78 79 2.224404
+C82 80 gnd 2.080806f
+R80 80 79 2.224404
+C83 81 gnd 2.080806f
+R81 80 81 2.224404
+C84 82 gnd 2.080806f
+R82 81 82 2.224404
+R83 82 g7467_1 2.224404
+.ends
+
+.subckt netg191 g191_2 g191_1 g191_0 gnd
+C1  g191_2 gnd 2.080806f
+C2  g191_1 gnd 2.080806f
+C3  g191_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g191_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 6 5 2.224404
+C10 7 gnd 2.080806f
+R7 7 6 2.224404
+C11 8 gnd 2.080806f
+R8 8 7 2.224404
+C12 9 gnd 2.080806f
+R9 9 8 2.224404
+C13 10 gnd 2.080806f
+R10 10 9 2.224404
+C14 11 gnd 2.080806f
+R11 11 10 2.224404
+C15 12 gnd 2.080806f
+R12 12 11 2.224404
+C16 13 gnd 2.080806f
+R13 13 12 2.224404
+C17 14 gnd 2.080806f
+R14 14 13 2.224404
+C18 15 gnd 2.080806f
+R15 15 14 2.224404
+C19 16 gnd 2.080806f
+R16 16 15 2.224404
+C20 17 gnd 2.080806f
+R17 17 16 2.224404
+C21 18 gnd 2.080806f
+R18 18 17 2.224404
+C22 19 gnd 2.080806f
+R19 19 18 2.224404
+C23 20 gnd 2.080806f
+R20 20 19 2.224404
+C24 21 gnd 2.080806f
+R21 21 20 2.224404
+C25 22 gnd 2.080806f
+R22 22 21 2.224404
+C26 23 gnd 2.080806f
+R23 23 22 2.224404
+C27 24 gnd 2.080806f
+R24 24 23 2.224404
+C28 25 gnd 2.080806f
+R25 25 24 2.224404
+C29 26 gnd 2.080806f
+R26 25 26 2.224404
+C30 27 gnd 2.080806f
+R27 27 26 2.224404
+C31 28 gnd 2.080806f
+R28 28 27 2.224404
+C32 29 gnd 2.080806f
+R29 29 28 2.224404
+C33 30 gnd 2.080806f
+R30 30 29 2.224404
+C34 31 gnd 2.080806f
+R31 31 30 2.224404
+C35 32 gnd 2.080806f
+R32 32 31 2.224404
+C36 33 gnd 2.080806f
+R33 33 32 2.224404
+C37 34 gnd 2.080806f
+R34 34 33 2.224404
+C38 35 gnd 2.080806f
+R35 35 34 2.224404
+C39 36 gnd 2.080806f
+R36 36 35 2.224404
+C40 37 gnd 2.080806f
+R37 37 36 2.224404
+C41 38 gnd 2.080806f
+R38 38 37 2.224404
+R39 g191_1 38 2.224404
+C42 39 gnd 2.080806f
+R40 g191_0 39 2.224404
+C43 40 gnd 2.080806f
+R41 39 40 2.224404
+C44 41 gnd 2.080806f
+R42 40 41 2.224404
+C45 42 gnd 2.080806f
+R43 41 42 2.224404
+C46 43 gnd 2.080806f
+R44 42 43 2.224404
+C47 44 gnd 2.080806f
+R45 43 44 2.224404
+C48 45 gnd 2.080806f
+R46 44 45 2.224404
+C49 46 gnd 2.080806f
+R47 45 46 2.224404
+C50 47 gnd 2.080806f
+R48 46 47 2.224404
+C51 48 gnd 2.080806f
+R49 47 48 2.224404
+C52 49 gnd 2.080806f
+R50 48 49 2.224404
+C53 50 gnd 2.080806f
+R51 49 50 2.224404
+C54 51 gnd 2.080806f
+R52 50 51 2.224404
+C55 52 gnd 2.080806f
+R53 51 52 2.224404
+C56 53 gnd 2.080806f
+R54 52 53 2.224404
+C57 54 gnd 2.080806f
+R55 53 54 2.224404
+C58 55 gnd 2.080806f
+R56 54 55 2.224404
+C59 56 gnd 2.080806f
+R57 55 56 2.224404
+C60 57 gnd 2.080806f
+R58 56 57 2.224404
+C61 58 gnd 2.080806f
+R59 57 58 2.224404
+C62 59 gnd 2.080806f
+R60 58 59 2.224404
+C63 60 gnd 2.080806f
+R61 59 60 2.224404
+C64 61 gnd 2.080806f
+R62 60 61 2.224404
+C65 62 gnd 2.080806f
+R63 61 62 2.224404
+C66 63 gnd 2.080806f
+R64 62 63 2.224404
+C67 64 gnd 2.080806f
+R65 63 64 2.224404
+C68 65 gnd 2.080806f
+R66 64 65 2.224404
+C69 66 gnd 2.080806f
+R67 65 66 2.224404
+C70 67 gnd 2.080806f
+R68 66 67 2.224404
+C71 68 gnd 2.080806f
+R69 67 68 2.224404
+C72 69 gnd 2.080806f
+R70 68 69 2.224404
+C73 70 gnd 2.080806f
+R71 69 70 2.224404
+C74 71 gnd 2.080806f
+R72 70 71 2.224404
+C75 72 gnd 2.080806f
+R73 71 72 2.224404
+C76 73 gnd 2.080806f
+R74 72 73 2.224404
+C77 74 gnd 2.080806f
+R75 73 74 2.224404
+C78 75 gnd 2.080806f
+R76 74 75 2.224404
+C79 76 gnd 2.080806f
+R77 75 76 2.224404
+C80 77 gnd 2.080806f
+R78 76 77 2.224404
+C81 78 gnd 2.080806f
+R79 77 78 2.224404
+C82 79 gnd 2.080806f
+R80 78 79 2.224404
+C83 80 gnd 2.080806f
+R81 79 80 2.224404
+C84 81 gnd 2.080806f
+R82 80 81 2.224404
+C85 82 gnd 2.080806f
+R83 81 82 2.224404
+C86 83 gnd 2.080806f
+R84 82 83 2.224404
+R85 83 g191_2 2.224404
+.ends
+
+.subckt netg464 g464_0 g464_4 g464_3 g464_2 g464_1 g464_5 gnd
+C1  g464_0 gnd 2.080806f
+C2  g464_4 gnd 2.080806f
+C3  g464_3 gnd 2.080806f
+C4  g464_2 gnd 2.080806f
+C5  g464_1 gnd 2.080806f
+C6  g464_5 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 1 g464_0 2.224404
+C8 2 gnd 2.080806f
+R2 2 1 2.224404
+C9 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g464_4 3 2.224404
+C10 4 gnd 2.080806f
+R5 g464_4 4 2.224404
+C11 5 gnd 2.080806f
+R6 4 5 2.224404
+C12 6 gnd 2.080806f
+R7 5 6 2.224404
+R8 6 g464_2 2.224404
+C13 7 gnd 2.080806f
+R9 g464_2 7 2.224404
+C14 8 gnd 2.080806f
+R10 7 8 2.224404
+C15 9 gnd 2.080806f
+R11 8 9 2.224404
+C16 10 gnd 2.080806f
+R12 9 10 2.224404
+C17 11 gnd 2.080806f
+R13 10 11 2.224404
+C18 12 gnd 2.080806f
+R14 11 12 2.224404
+R15 12 g464_5 2.224404
+C19 13 gnd 2.080806f
+R16 12 13 2.224404
+C20 14 gnd 2.080806f
+R17 13 14 2.224404
+C21 15 gnd 2.080806f
+R18 14 15 2.224404
+C22 16 gnd 2.080806f
+R19 15 16 2.224404
+C23 17 gnd 2.080806f
+R20 16 17 2.224404
+C24 18 gnd 2.080806f
+R21 17 18 2.224404
+C25 19 gnd 2.080806f
+R22 18 19 2.224404
+C26 20 gnd 2.080806f
+R23 19 20 2.224404
+C27 21 gnd 2.080806f
+R24 20 21 2.224404
+C28 22 gnd 2.080806f
+R25 21 22 2.224404
+C29 23 gnd 2.080806f
+R26 22 23 2.224404
+C30 24 gnd 2.080806f
+R27 23 24 2.224404
+C31 25 gnd 2.080806f
+R28 24 25 2.224404
+C32 26 gnd 2.080806f
+R29 25 26 2.224404
+C33 27 gnd 2.080806f
+R30 26 27 2.224404
+C34 28 gnd 2.080806f
+R31 27 28 2.224404
+C35 29 gnd 2.080806f
+R32 28 29 2.224404
+C36 30 gnd 2.080806f
+R33 29 30 2.224404
+C37 31 gnd 2.080806f
+R34 30 31 2.224404
+C38 32 gnd 2.080806f
+R35 31 32 2.224404
+C39 33 gnd 2.080806f
+R36 32 33 2.224404
+C40 34 gnd 2.080806f
+R37 33 34 2.224404
+C41 35 gnd 2.080806f
+R38 34 35 2.224404
+C42 36 gnd 2.080806f
+R39 35 36 2.224404
+C43 37 gnd 2.080806f
+R40 36 37 2.224404
+C44 38 gnd 2.080806f
+R41 37 38 2.224404
+C45 39 gnd 2.080806f
+R42 38 39 2.224404
+C46 40 gnd 2.080806f
+R43 39 40 2.224404
+C47 41 gnd 2.080806f
+R44 40 41 2.224404
+C48 42 gnd 2.080806f
+R45 41 42 2.224404
+C49 43 gnd 2.080806f
+R46 42 43 2.224404
+C50 44 gnd 2.080806f
+R47 43 44 2.224404
+C51 45 gnd 2.080806f
+R48 44 45 2.224404
+C52 46 gnd 2.080806f
+R49 45 46 2.224404
+C53 47 gnd 2.080806f
+R50 46 47 2.224404
+C54 48 gnd 2.080806f
+R51 47 48 2.224404
+C55 49 gnd 2.080806f
+R52 48 49 2.224404
+C56 50 gnd 2.080806f
+R53 49 50 2.224404
+C57 51 gnd 2.080806f
+R54 50 51 2.224404
+C58 52 gnd 2.080806f
+R55 51 52 2.224404
+C59 53 gnd 2.080806f
+R56 52 53 2.224404
+C60 54 gnd 2.080806f
+R57 53 54 2.224404
+C61 55 gnd 2.080806f
+R58 54 55 2.224404
+C62 56 gnd 2.080806f
+R59 55 56 2.224404
+C63 57 gnd 2.080806f
+R60 56 57 2.224404
+C64 58 gnd 2.080806f
+R61 57 58 2.224404
+C65 59 gnd 2.080806f
+R62 58 59 2.224404
+C66 60 gnd 2.080806f
+R63 59 60 2.224404
+C67 61 gnd 2.080806f
+R64 60 61 2.224404
+C68 62 gnd 2.080806f
+R65 61 62 2.224404
+C69 63 gnd 2.080806f
+R66 62 63 2.224404
+C70 64 gnd 2.080806f
+R67 63 64 2.224404
+C71 65 gnd 2.080806f
+R68 64 65 2.224404
+C72 66 gnd 2.080806f
+R69 65 66 2.224404
+C73 67 gnd 2.080806f
+R70 66 67 2.224404
+R71 67 g464_1 2.224404
+C74 68 gnd 2.080806f
+R72 68 g464_1 2.224404
+C75 69 gnd 2.080806f
+R73 69 68 2.224404
+C76 70 gnd 2.080806f
+R74 70 69 2.224404
+C77 71 gnd 2.080806f
+R75 71 70 2.224404
+C78 72 gnd 2.080806f
+R76 71 72 2.224404
+C79 73 gnd 2.080806f
+R77 73 72 2.224404
+C80 74 gnd 2.080806f
+R78 74 73 2.224404
+C81 75 gnd 2.080806f
+R79 75 74 2.224404
+C82 76 gnd 2.080806f
+R80 76 75 2.224404
+C83 77 gnd 2.080806f
+R81 77 76 2.224404
+C84 78 gnd 2.080806f
+R82 78 77 2.224404
+C85 79 gnd 2.080806f
+R83 79 78 2.224404
+C86 80 gnd 2.080806f
+R84 80 79 2.224404
+C87 81 gnd 2.080806f
+R85 81 80 2.224404
+C88 82 gnd 2.080806f
+R86 82 81 2.224404
+C89 83 gnd 2.080806f
+R87 83 82 2.224404
+C90 84 gnd 2.080806f
+R88 84 83 2.224404
+C91 85 gnd 2.080806f
+R89 85 84 2.224404
+C92 86 gnd 2.080806f
+R90 86 85 2.224404
+C93 87 gnd 2.080806f
+R91 87 86 2.224404
+C94 88 gnd 2.080806f
+R92 88 87 2.224404
+C95 89 gnd 2.080806f
+R93 88 89 2.224404
+C96 90 gnd 2.080806f
+R94 90 89 2.224404
+C97 91 gnd 2.080806f
+R95 91 90 2.224404
+C98 92 gnd 2.080806f
+R96 91 92 2.224404
+C99 93 gnd 2.080806f
+R97 93 92 2.224404
+C100 94 gnd 2.080806f
+R98 94 93 2.224404
+C101 95 gnd 2.080806f
+R99 95 94 2.224404
+C102 96 gnd 2.080806f
+R100 95 96 2.224404
+R101 96 g464_3 2.224404
+.ends
+
+.subckt netg179 g179_2 g179_1 g179_0 gnd
+C1  g179_2 gnd 2.080806f
+C2  g179_1 gnd 2.080806f
+C3  g179_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g179_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 6 5 2.224404
+C10 7 gnd 2.080806f
+R7 7 6 2.224404
+C11 8 gnd 2.080806f
+R8 8 7 2.224404
+C12 9 gnd 2.080806f
+R9 9 8 2.224404
+C13 10 gnd 2.080806f
+R10 10 9 2.224404
+C14 11 gnd 2.080806f
+R11 11 10 2.224404
+C15 12 gnd 2.080806f
+R12 12 11 2.224404
+C16 13 gnd 2.080806f
+R13 13 12 2.224404
+C17 14 gnd 2.080806f
+R14 14 13 2.224404
+C18 15 gnd 2.080806f
+R15 15 14 2.224404
+C19 16 gnd 2.080806f
+R16 16 15 2.224404
+C20 17 gnd 2.080806f
+R17 17 16 2.224404
+C21 18 gnd 2.080806f
+R18 18 17 2.224404
+C22 19 gnd 2.080806f
+R19 19 18 2.224404
+C23 20 gnd 2.080806f
+R20 20 19 2.224404
+C24 21 gnd 2.080806f
+R21 21 20 2.224404
+C25 22 gnd 2.080806f
+R22 22 21 2.224404
+C26 23 gnd 2.080806f
+R23 23 22 2.224404
+C27 24 gnd 2.080806f
+R24 24 23 2.224404
+C28 25 gnd 2.080806f
+R25 25 24 2.224404
+C29 26 gnd 2.080806f
+R26 26 25 2.224404
+C30 27 gnd 2.080806f
+R27 27 26 2.224404
+C31 28 gnd 2.080806f
+R28 28 27 2.224404
+C32 29 gnd 2.080806f
+R29 29 28 2.224404
+C33 30 gnd 2.080806f
+R30 30 29 2.224404
+C34 31 gnd 2.080806f
+R31 31 30 2.224404
+C35 32 gnd 2.080806f
+R32 32 31 2.224404
+C36 33 gnd 2.080806f
+R33 33 32 2.224404
+C37 34 gnd 2.080806f
+R34 34 33 2.224404
+C38 35 gnd 2.080806f
+R35 35 34 2.224404
+C39 36 gnd 2.080806f
+R36 36 35 2.224404
+C40 37 gnd 2.080806f
+R37 37 36 2.224404
+C41 38 gnd 2.080806f
+R38 38 37 2.224404
+C42 39 gnd 2.080806f
+R39 39 38 2.224404
+C43 40 gnd 2.080806f
+R40 40 39 2.224404
+C44 41 gnd 2.080806f
+R41 41 40 2.224404
+C45 42 gnd 2.080806f
+R42 42 41 2.224404
+C46 43 gnd 2.080806f
+R43 43 42 2.224404
+R44 g179_2 43 2.224404
+C47 44 gnd 2.080806f
+R45 44 g179_2 2.224404
+C48 45 gnd 2.080806f
+R46 45 44 2.224404
+C49 46 gnd 2.080806f
+R47 46 45 2.224404
+C50 47 gnd 2.080806f
+R48 47 46 2.224404
+C51 48 gnd 2.080806f
+R49 48 47 2.224404
+C52 49 gnd 2.080806f
+R50 49 48 2.224404
+C53 50 gnd 2.080806f
+R51 50 49 2.224404
+C54 51 gnd 2.080806f
+R52 51 50 2.224404
+C55 52 gnd 2.080806f
+R53 52 51 2.224404
+C56 53 gnd 2.080806f
+R54 53 52 2.224404
+C57 54 gnd 2.080806f
+R55 54 53 2.224404
+C58 55 gnd 2.080806f
+R56 55 54 2.224404
+C59 56 gnd 2.080806f
+R57 56 55 2.224404
+C60 57 gnd 2.080806f
+R58 57 56 2.224404
+C61 58 gnd 2.080806f
+R59 58 57 2.224404
+C62 59 gnd 2.080806f
+R60 59 58 2.224404
+C63 60 gnd 2.080806f
+R61 60 59 2.224404
+C64 61 gnd 2.080806f
+R62 61 60 2.224404
+C65 62 gnd 2.080806f
+R63 62 61 2.224404
+C66 63 gnd 2.080806f
+R64 63 62 2.224404
+C67 64 gnd 2.080806f
+R65 64 63 2.224404
+C68 65 gnd 2.080806f
+R66 65 64 2.224404
+C69 66 gnd 2.080806f
+R67 66 65 2.224404
+C70 67 gnd 2.080806f
+R68 67 66 2.224404
+C71 68 gnd 2.080806f
+R69 68 67 2.224404
+C72 69 gnd 2.080806f
+R70 69 68 2.224404
+C73 70 gnd 2.080806f
+R71 70 69 2.224404
+C74 71 gnd 2.080806f
+R72 71 70 2.224404
+C75 72 gnd 2.080806f
+R73 72 71 2.224404
+C76 73 gnd 2.080806f
+R74 72 73 2.224404
+C77 74 gnd 2.080806f
+R75 74 73 2.224404
+C78 75 gnd 2.080806f
+R76 75 74 2.224404
+C79 76 gnd 2.080806f
+R77 76 75 2.224404
+C80 77 gnd 2.080806f
+R78 77 76 2.224404
+C81 78 gnd 2.080806f
+R79 78 77 2.224404
+C82 79 gnd 2.080806f
+R80 78 79 2.224404
+C83 80 gnd 2.080806f
+R81 80 79 2.224404
+C84 81 gnd 2.080806f
+R82 81 80 2.224404
+C85 82 gnd 2.080806f
+R83 82 81 2.224404
+R84 g179_1 82 2.224404
+.ends
+
+.subckt netg195 g195_0 g195_2 g195_1 gnd
+C1  g195_0 gnd 2.080806f
+C2  g195_2 gnd 2.080806f
+C3  g195_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g195_0 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+C8 5 gnd 2.080806f
+R5 4 5 2.224404
+C9 6 gnd 2.080806f
+R6 5 6 2.224404
+C10 7 gnd 2.080806f
+R7 7 6 2.224404
+C11 8 gnd 2.080806f
+R8 7 8 2.224404
+C12 9 gnd 2.080806f
+R9 8 9 2.224404
+C13 10 gnd 2.080806f
+R10 9 10 2.224404
+C14 11 gnd 2.080806f
+R11 10 11 2.224404
+C15 12 gnd 2.080806f
+R12 11 12 2.224404
+C16 13 gnd 2.080806f
+R13 13 12 2.224404
+C17 14 gnd 2.080806f
+R14 14 13 2.224404
+C18 15 gnd 2.080806f
+R15 14 15 2.224404
+C19 16 gnd 2.080806f
+R16 15 16 2.224404
+C20 17 gnd 2.080806f
+R17 16 17 2.224404
+C21 18 gnd 2.080806f
+R18 17 18 2.224404
+C22 19 gnd 2.080806f
+R19 18 19 2.224404
+C23 20 gnd 2.080806f
+R20 20 19 2.224404
+C24 21 gnd 2.080806f
+R21 20 21 2.224404
+C25 22 gnd 2.080806f
+R22 21 22 2.224404
+C26 23 gnd 2.080806f
+R23 22 23 2.224404
+C27 24 gnd 2.080806f
+R24 23 24 2.224404
+C28 25 gnd 2.080806f
+R25 24 25 2.224404
+C29 26 gnd 2.080806f
+R26 26 25 2.224404
+C30 27 gnd 2.080806f
+R27 26 27 2.224404
+C31 28 gnd 2.080806f
+R28 27 28 2.224404
+R29 28 g195_1 2.224404
+C32 29 gnd 2.080806f
+R30 g195_1 29 2.224404
+C33 30 gnd 2.080806f
+R31 29 30 2.224404
+C34 31 gnd 2.080806f
+R32 30 31 2.224404
+C35 32 gnd 2.080806f
+R33 31 32 2.224404
+C36 33 gnd 2.080806f
+R34 32 33 2.224404
+C37 34 gnd 2.080806f
+R35 33 34 2.224404
+C38 35 gnd 2.080806f
+R36 34 35 2.224404
+C39 36 gnd 2.080806f
+R37 35 36 2.224404
+C40 37 gnd 2.080806f
+R38 36 37 2.224404
+C41 38 gnd 2.080806f
+R39 37 38 2.224404
+C42 39 gnd 2.080806f
+R40 38 39 2.224404
+C43 40 gnd 2.080806f
+R41 39 40 2.224404
+C44 41 gnd 2.080806f
+R42 40 41 2.224404
+C45 42 gnd 2.080806f
+R43 41 42 2.224404
+C46 43 gnd 2.080806f
+R44 42 43 2.224404
+C47 44 gnd 2.080806f
+R45 43 44 2.224404
+C48 45 gnd 2.080806f
+R46 44 45 2.224404
+C49 46 gnd 2.080806f
+R47 45 46 2.224404
+C50 47 gnd 2.080806f
+R48 46 47 2.224404
+C51 48 gnd 2.080806f
+R49 47 48 2.224404
+C52 49 gnd 2.080806f
+R50 48 49 2.224404
+C53 50 gnd 2.080806f
+R51 49 50 2.224404
+C54 51 gnd 2.080806f
+R52 50 51 2.224404
+C55 52 gnd 2.080806f
+R53 51 52 2.224404
+C56 53 gnd 2.080806f
+R54 52 53 2.224404
+C57 54 gnd 2.080806f
+R55 53 54 2.224404
+C58 55 gnd 2.080806f
+R56 54 55 2.224404
+C59 56 gnd 2.080806f
+R57 55 56 2.224404
+C60 57 gnd 2.080806f
+R58 56 57 2.224404
+C61 58 gnd 2.080806f
+R59 57 58 2.224404
+C62 59 gnd 2.080806f
+R60 58 59 2.224404
+C63 60 gnd 2.080806f
+R61 59 60 2.224404
+C64 61 gnd 2.080806f
+R62 60 61 2.224404
+C65 62 gnd 2.080806f
+R63 61 62 2.224404
+C66 63 gnd 2.080806f
+R64 62 63 2.224404
+C67 64 gnd 2.080806f
+R65 63 64 2.224404
+C68 65 gnd 2.080806f
+R66 64 65 2.224404
+C69 66 gnd 2.080806f
+R67 65 66 2.224404
+C70 67 gnd 2.080806f
+R68 66 67 2.224404
+C71 68 gnd 2.080806f
+R69 67 68 2.224404
+C72 69 gnd 2.080806f
+R70 68 69 2.224404
+C73 70 gnd 2.080806f
+R71 69 70 2.224404
+C74 71 gnd 2.080806f
+R72 70 71 2.224404
+C75 72 gnd 2.080806f
+R73 71 72 2.224404
+C76 73 gnd 2.080806f
+R74 72 73 2.224404
+C77 74 gnd 2.080806f
+R75 73 74 2.224404
+C78 75 gnd 2.080806f
+R76 74 75 2.224404
+C79 76 gnd 2.080806f
+R77 75 76 2.224404
+C80 77 gnd 2.080806f
+R78 76 77 2.224404
+C81 78 gnd 2.080806f
+R79 77 78 2.224404
+C82 79 gnd 2.080806f
+R80 78 79 2.224404
+C83 80 gnd 2.080806f
+R81 79 80 2.224404
+C84 81 gnd 2.080806f
+R82 80 81 2.224404
+C85 82 gnd 2.080806f
+R83 81 82 2.224404
+C86 83 gnd 2.080806f
+R84 82 83 2.224404
+C87 84 gnd 2.080806f
+R85 83 84 2.224404
+C88 85 gnd 2.080806f
+R86 84 85 2.224404
+C89 86 gnd 2.080806f
+R87 85 86 2.224404
+C90 87 gnd 2.080806f
+R88 86 87 2.224404
+C91 88 gnd 2.080806f
+R89 87 88 2.224404
+R90 88 g195_2 2.224404
+.ends
+
+.subckt netg7456 g7456_0 g7456_1 gnd
+C1  g7456_0 gnd 2.080806f
+C2  g7456_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7456_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 26 27 2.224404
+C30 28 gnd 2.080806f
+R28 27 28 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+C50 48 gnd 2.080806f
+R48 47 48 2.224404
+C51 49 gnd 2.080806f
+R49 49 48 2.224404
+C52 50 gnd 2.080806f
+R50 50 49 2.224404
+C53 51 gnd 2.080806f
+R51 51 50 2.224404
+C54 52 gnd 2.080806f
+R52 52 51 2.224404
+C55 53 gnd 2.080806f
+R53 53 52 2.224404
+C56 54 gnd 2.080806f
+R54 53 54 2.224404
+C57 55 gnd 2.080806f
+R55 54 55 2.224404
+C58 56 gnd 2.080806f
+R56 55 56 2.224404
+C59 57 gnd 2.080806f
+R57 56 57 2.224404
+C60 58 gnd 2.080806f
+R58 58 57 2.224404
+C61 59 gnd 2.080806f
+R59 58 59 2.224404
+C62 60 gnd 2.080806f
+R60 59 60 2.224404
+C63 61 gnd 2.080806f
+R61 60 61 2.224404
+C64 62 gnd 2.080806f
+R62 62 61 2.224404
+C65 63 gnd 2.080806f
+R63 63 62 2.224404
+C66 64 gnd 2.080806f
+R64 64 63 2.224404
+C67 65 gnd 2.080806f
+R65 64 65 2.224404
+C68 66 gnd 2.080806f
+R66 65 66 2.224404
+C69 67 gnd 2.080806f
+R67 67 66 2.224404
+C70 68 gnd 2.080806f
+R68 68 67 2.224404
+C71 69 gnd 2.080806f
+R69 69 68 2.224404
+C72 70 gnd 2.080806f
+R70 69 70 2.224404
+C73 71 gnd 2.080806f
+R71 71 70 2.224404
+C74 72 gnd 2.080806f
+R72 71 72 2.224404
+C75 73 gnd 2.080806f
+R73 73 72 2.224404
+C76 74 gnd 2.080806f
+R74 74 73 2.224404
+C77 75 gnd 2.080806f
+R75 74 75 2.224404
+C78 76 gnd 2.080806f
+R76 76 75 2.224404
+C79 77 gnd 2.080806f
+R77 77 76 2.224404
+C80 78 gnd 2.080806f
+R78 78 77 2.224404
+C81 79 gnd 2.080806f
+R79 78 79 2.224404
+C82 80 gnd 2.080806f
+R80 79 80 2.224404
+C83 81 gnd 2.080806f
+R81 81 80 2.224404
+C84 82 gnd 2.080806f
+R82 81 82 2.224404
+C85 83 gnd 2.080806f
+R83 82 83 2.224404
+R84 83 g7456_1 2.224404
+.ends
+
+.subckt netg7484 g7484_0 g7484_1 gnd
+C1  g7484_0 gnd 2.080806f
+C2  g7484_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g7484_0 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 35 36 2.224404
+C39 37 gnd 2.080806f
+R37 36 37 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 39 40 2.224404
+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
+R42 41 42 2.224404
+C45 43 gnd 2.080806f
+R43 42 43 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 44 45 2.224404
+C48 46 gnd 2.080806f
+R46 45 46 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+C50 48 gnd 2.080806f
+R48 48 47 2.224404
+C51 49 gnd 2.080806f
+R49 48 49 2.224404
+C52 50 gnd 2.080806f
+R50 50 49 2.224404
+C53 51 gnd 2.080806f
+R51 51 50 2.224404
+C54 52 gnd 2.080806f
+R52 52 51 2.224404
+C55 53 gnd 2.080806f
+R53 53 52 2.224404
+C56 54 gnd 2.080806f
+R54 54 53 2.224404
+C57 55 gnd 2.080806f
+R55 55 54 2.224404
+C58 56 gnd 2.080806f
+R56 56 55 2.224404
+C59 57 gnd 2.080806f
+R57 57 56 2.224404
+C60 58 gnd 2.080806f
+R58 58 57 2.224404
+C61 59 gnd 2.080806f
+R59 59 58 2.224404
+C62 60 gnd 2.080806f
+R60 60 59 2.224404
+C63 61 gnd 2.080806f
+R61 61 60 2.224404
+C64 62 gnd 2.080806f
+R62 62 61 2.224404
+C65 63 gnd 2.080806f
+R63 63 62 2.224404
+C66 64 gnd 2.080806f
+R64 64 63 2.224404
+C67 65 gnd 2.080806f
+R65 64 65 2.224404
+C68 66 gnd 2.080806f
+R66 66 65 2.224404
+C69 67 gnd 2.080806f
+R67 67 66 2.224404
+C70 68 gnd 2.080806f
+R68 67 68 2.224404
+C71 69 gnd 2.080806f
+R69 69 68 2.224404
+C72 70 gnd 2.080806f
+R70 70 69 2.224404
+C73 71 gnd 2.080806f
+R71 71 70 2.224404
+C74 72 gnd 2.080806f
+R72 71 72 2.224404
+C75 73 gnd 2.080806f
+R73 72 73 2.224404
+C76 74 gnd 2.080806f
+R74 73 74 2.224404
+C77 75 gnd 2.080806f
+R75 74 75 2.224404
+C78 76 gnd 2.080806f
+R76 75 76 2.224404
+C79 77 gnd 2.080806f
+R77 76 77 2.224404
+C80 78 gnd 2.080806f
+R78 78 77 2.224404
+C81 79 gnd 2.080806f
+R79 78 79 2.224404
+C82 80 gnd 2.080806f
+R80 79 80 2.224404
+C83 81 gnd 2.080806f
+R81 81 80 2.224404
+C84 82 gnd 2.080806f
+R82 81 82 2.224404
+C85 83 gnd 2.080806f
+R83 83 82 2.224404
+R84 g7484_1 83 2.224404
+.ends
+
+.subckt netg192 g192_2 g192_1 g192_0 gnd
+C1  g192_2 gnd 2.080806f
+C2  g192_1 gnd 2.080806f
+C3  g192_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g192_0 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+C8 5 gnd 2.080806f
+R5 4 5 2.224404
+C9 6 gnd 2.080806f
+R6 5 6 2.224404
+C10 7 gnd 2.080806f
+R7 6 7 2.224404
+C11 8 gnd 2.080806f
+R8 7 8 2.224404
+C12 9 gnd 2.080806f
+R9 8 9 2.224404
+C13 10 gnd 2.080806f
+R10 9 10 2.224404
+C14 11 gnd 2.080806f
+R11 10 11 2.224404
+C15 12 gnd 2.080806f
+R12 11 12 2.224404
+C16 13 gnd 2.080806f
+R13 12 13 2.224404
+C17 14 gnd 2.080806f
+R14 13 14 2.224404
+C18 15 gnd 2.080806f
+R15 14 15 2.224404
+C19 16 gnd 2.080806f
+R16 15 16 2.224404
+C20 17 gnd 2.080806f
+R17 16 17 2.224404
+C21 18 gnd 2.080806f
+R18 17 18 2.224404
+C22 19 gnd 2.080806f
+R19 18 19 2.224404
+C23 20 gnd 2.080806f
+R20 19 20 2.224404
+C24 21 gnd 2.080806f
+R21 20 21 2.224404
+C25 22 gnd 2.080806f
+R22 21 22 2.224404
+C26 23 gnd 2.080806f
+R23 22 23 2.224404
+C27 24 gnd 2.080806f
+R24 23 24 2.224404
+C28 25 gnd 2.080806f
+R25 25 24 2.224404
+C29 26 gnd 2.080806f
+R26 25 26 2.224404
+C30 27 gnd 2.080806f
+R27 27 26 2.224404
+C31 28 gnd 2.080806f
+R28 27 28 2.224404
+C32 29 gnd 2.080806f
+R29 28 29 2.224404
+C33 30 gnd 2.080806f
+R30 30 29 2.224404
+C34 31 gnd 2.080806f
+R31 30 31 2.224404
+C35 32 gnd 2.080806f
+R32 31 32 2.224404
+R33 32 g192_2 2.224404
+C36 33 gnd 2.080806f
+R34 g192_2 33 2.224404
+C37 34 gnd 2.080806f
+R35 33 34 2.224404
+C38 35 gnd 2.080806f
+R36 34 35 2.224404
+C39 36 gnd 2.080806f
+R37 35 36 2.224404
+C40 37 gnd 2.080806f
+R38 36 37 2.224404
+C41 38 gnd 2.080806f
+R39 37 38 2.224404
+C42 39 gnd 2.080806f
+R40 38 39 2.224404
+C43 40 gnd 2.080806f
+R41 39 40 2.224404
+C44 41 gnd 2.080806f
+R42 40 41 2.224404
+C45 42 gnd 2.080806f
+R43 41 42 2.224404
+C46 43 gnd 2.080806f
+R44 42 43 2.224404
+C47 44 gnd 2.080806f
+R45 43 44 2.224404
+C48 45 gnd 2.080806f
+R46 44 45 2.224404
+C49 46 gnd 2.080806f
+R47 45 46 2.224404
+C50 47 gnd 2.080806f
+R48 46 47 2.224404
+C51 48 gnd 2.080806f
+R49 47 48 2.224404
+C52 49 gnd 2.080806f
+R50 48 49 2.224404
+C53 50 gnd 2.080806f
+R51 49 50 2.224404
+C54 51 gnd 2.080806f
+R52 50 51 2.224404
+C55 52 gnd 2.080806f
+R53 51 52 2.224404
+C56 53 gnd 2.080806f
+R54 52 53 2.224404
+C57 54 gnd 2.080806f
+R55 53 54 2.224404
+C58 55 gnd 2.080806f
+R56 54 55 2.224404
+C59 56 gnd 2.080806f
+R57 55 56 2.224404
+C60 57 gnd 2.080806f
+R58 56 57 2.224404
+C61 58 gnd 2.080806f
+R59 57 58 2.224404
+C62 59 gnd 2.080806f
+R60 58 59 2.224404
+C63 60 gnd 2.080806f
+R61 59 60 2.224404
+C64 61 gnd 2.080806f
+R62 60 61 2.224404
+C65 62 gnd 2.080806f
+R63 61 62 2.224404
+C66 63 gnd 2.080806f
+R64 62 63 2.224404
+C67 64 gnd 2.080806f
+R65 63 64 2.224404
+C68 65 gnd 2.080806f
+R66 64 65 2.224404
+C69 66 gnd 2.080806f
+R67 65 66 2.224404
+C70 67 gnd 2.080806f
+R68 66 67 2.224404
+C71 68 gnd 2.080806f
+R69 67 68 2.224404
+C72 69 gnd 2.080806f
+R70 68 69 2.224404
+C73 70 gnd 2.080806f
+R71 69 70 2.224404
+C74 71 gnd 2.080806f
+R72 70 71 2.224404
+C75 72 gnd 2.080806f
+R73 71 72 2.224404
+C76 73 gnd 2.080806f
+R74 72 73 2.224404
+C77 74 gnd 2.080806f
+R75 73 74 2.224404
+C78 75 gnd 2.080806f
+R76 74 75 2.224404
+C79 76 gnd 2.080806f
+R77 75 76 2.224404
+C80 77 gnd 2.080806f
+R78 76 77 2.224404
+C81 78 gnd 2.080806f
+R79 77 78 2.224404
+C82 79 gnd 2.080806f
+R80 78 79 2.224404
+C83 80 gnd 2.080806f
+R81 79 80 2.224404
+C84 81 gnd 2.080806f
+R82 80 81 2.224404
+C85 82 gnd 2.080806f
+R83 81 82 2.224404
+C86 83 gnd 2.080806f
+R84 82 83 2.224404
+C87 84 gnd 2.080806f
+R85 83 84 2.224404
+C88 85 gnd 2.080806f
+R86 84 85 2.224404
+C89 86 gnd 2.080806f
+R87 85 86 2.224404
+C90 87 gnd 2.080806f
+R88 86 87 2.224404
+C91 88 gnd 2.080806f
+R89 87 88 2.224404
+C92 89 gnd 2.080806f
+R90 88 89 2.224404
+R91 89 g192_1 2.224404
+.ends
+
+.subckt netg199 g199_0 g199_1 g199_2 gnd
+C1  g199_0 gnd 2.080806f
+C2  g199_1 gnd 2.080806f
+C3  g199_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g199_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 6 5 2.224404
+C10 7 gnd 2.080806f
+R7 7 6 2.224404
+C11 8 gnd 2.080806f
+R8 8 7 2.224404
+C12 9 gnd 2.080806f
+R9 9 8 2.224404
+C13 10 gnd 2.080806f
+R10 10 9 2.224404
+C14 11 gnd 2.080806f
+R11 11 10 2.224404
+C15 12 gnd 2.080806f
+R12 12 11 2.224404
+C16 13 gnd 2.080806f
+R13 13 12 2.224404
+C17 14 gnd 2.080806f
+R14 14 13 2.224404
+C18 15 gnd 2.080806f
+R15 15 14 2.224404
+C19 16 gnd 2.080806f
+R16 16 15 2.224404
+C20 17 gnd 2.080806f
+R17 17 16 2.224404
+C21 18 gnd 2.080806f
+R18 18 17 2.224404
+C22 19 gnd 2.080806f
+R19 19 18 2.224404
+C23 20 gnd 2.080806f
+R20 20 19 2.224404
+C24 21 gnd 2.080806f
+R21 21 20 2.224404
+C25 22 gnd 2.080806f
+R22 22 21 2.224404
+C26 23 gnd 2.080806f
+R23 23 22 2.224404
+C27 24 gnd 2.080806f
+R24 24 23 2.224404
+C28 25 gnd 2.080806f
+R25 25 24 2.224404
+C29 26 gnd 2.080806f
+R26 26 25 2.224404
+C30 27 gnd 2.080806f
+R27 27 26 2.224404
+C31 28 gnd 2.080806f
+R28 28 27 2.224404
+C32 29 gnd 2.080806f
+R29 29 28 2.224404
+C33 30 gnd 2.080806f
+R30 30 29 2.224404
+C34 31 gnd 2.080806f
+R31 31 30 2.224404
+C35 32 gnd 2.080806f
+R32 32 31 2.224404
+C36 33 gnd 2.080806f
+R33 33 32 2.224404
+C37 34 gnd 2.080806f
+R34 34 33 2.224404
+C38 35 gnd 2.080806f
+R35 35 34 2.224404
+C39 36 gnd 2.080806f
+R36 36 35 2.224404
+C40 37 gnd 2.080806f
+R37 37 36 2.224404
+C41 38 gnd 2.080806f
+R38 38 37 2.224404
+C42 39 gnd 2.080806f
+R39 39 38 2.224404
+C43 40 gnd 2.080806f
+R40 40 39 2.224404
+C44 41 gnd 2.080806f
+R41 41 40 2.224404
+C45 42 gnd 2.080806f
+R42 42 41 2.224404
+C46 43 gnd 2.080806f
+R43 43 42 2.224404
+C47 44 gnd 2.080806f
+R44 44 43 2.224404
+C48 45 gnd 2.080806f
+R45 45 44 2.224404
+C49 46 gnd 2.080806f
+R46 46 45 2.224404
+C50 47 gnd 2.080806f
+R47 47 46 2.224404
+C51 48 gnd 2.080806f
+R48 48 47 2.224404
+C52 49 gnd 2.080806f
+R49 49 48 2.224404
+C53 50 gnd 2.080806f
+R50 50 49 2.224404
+C54 51 gnd 2.080806f
+R51 51 50 2.224404
+C55 52 gnd 2.080806f
+R52 52 51 2.224404
+C56 53 gnd 2.080806f
+R53 53 52 2.224404
+C57 54 gnd 2.080806f
+R54 54 53 2.224404
+C58 55 gnd 2.080806f
+R55 55 54 2.224404
+C59 56 gnd 2.080806f
+R56 56 55 2.224404
+C60 57 gnd 2.080806f
+R57 57 56 2.224404
+C61 58 gnd 2.080806f
+R58 58 57 2.224404
+C62 59 gnd 2.080806f
+R59 59 58 2.224404
+C63 60 gnd 2.080806f
+R60 60 59 2.224404
+R61 g199_2 60 2.224404
+C64 61 gnd 2.080806f
+R62 61 g199_2 2.224404
+C65 62 gnd 2.080806f
+R63 62 61 2.224404
+C66 63 gnd 2.080806f
+R64 63 62 2.224404
+C67 64 gnd 2.080806f
+R65 63 64 2.224404
+C68 65 gnd 2.080806f
+R66 64 65 2.224404
+C69 66 gnd 2.080806f
+R67 65 66 2.224404
+C70 67 gnd 2.080806f
+R68 66 67 2.224404
+C71 68 gnd 2.080806f
+R69 67 68 2.224404
+C72 69 gnd 2.080806f
+R70 68 69 2.224404
+C73 70 gnd 2.080806f
+R71 69 70 2.224404
+C74 71 gnd 2.080806f
+R72 70 71 2.224404
+C75 72 gnd 2.080806f
+R73 72 71 2.224404
+C76 73 gnd 2.080806f
+R74 72 73 2.224404
+C77 74 gnd 2.080806f
+R75 73 74 2.224404
+C78 75 gnd 2.080806f
+R76 74 75 2.224404
+C79 76 gnd 2.080806f
+R77 76 75 2.224404
+C80 77 gnd 2.080806f
+R78 76 77 2.224404
+C81 78 gnd 2.080806f
+R79 77 78 2.224404
+C82 79 gnd 2.080806f
+R80 78 79 2.224404
+C83 80 gnd 2.080806f
+R81 79 80 2.224404
+C84 81 gnd 2.080806f
+R82 80 81 2.224404
+C85 82 gnd 2.080806f
+R83 81 82 2.224404
+C86 83 gnd 2.080806f
+R84 83 82 2.224404
+C87 84 gnd 2.080806f
+R85 84 83 2.224404
+C88 85 gnd 2.080806f
+R86 85 84 2.224404
+C89 86 gnd 2.080806f
+R87 86 85 2.224404
+C90 87 gnd 2.080806f
+R88 86 87 2.224404
+C91 88 gnd 2.080806f
+R89 88 87 2.224404
+C92 89 gnd 2.080806f
+R90 88 89 2.224404
+C93 90 gnd 2.080806f
+R91 89 90 2.224404
+C94 91 gnd 2.080806f
+R92 91 90 2.224404
+C95 92 gnd 2.080806f
+R93 91 92 2.224404
+C96 93 gnd 2.080806f
+R94 93 92 2.224404
+C97 94 gnd 2.080806f
+R95 94 93 2.224404
+C98 95 gnd 2.080806f
+R96 95 94 2.224404
+C99 96 gnd 2.080806f
+R97 95 96 2.224404
+C100 97 gnd 2.080806f
+R98 96 97 2.224404
+C101 98 gnd 2.080806f
+R99 98 97 2.224404
+C102 99 gnd 2.080806f
+R100 98 99 2.224404
+C103 100 gnd 2.080806f
+R101 99 100 2.224404
+R102 100 g199_1 2.224404
+.ends
+
+.subckt netg202 g202_0 g202_2 g202_1 gnd
+C1  g202_0 gnd 2.080806f
+C2  g202_2 gnd 2.080806f
+C3  g202_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g202_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 6 5 2.224404
+C10 7 gnd 2.080806f
+R7 7 6 2.224404
+C11 8 gnd 2.080806f
+R8 8 7 2.224404
+C12 9 gnd 2.080806f
+R9 9 8 2.224404
+C13 10 gnd 2.080806f
+R10 10 9 2.224404
+C14 11 gnd 2.080806f
+R11 11 10 2.224404
+C15 12 gnd 2.080806f
+R12 12 11 2.224404
+C16 13 gnd 2.080806f
+R13 13 12 2.224404
+C17 14 gnd 2.080806f
+R14 14 13 2.224404
+C18 15 gnd 2.080806f
+R15 15 14 2.224404
+C19 16 gnd 2.080806f
+R16 16 15 2.224404
+C20 17 gnd 2.080806f
+R17 17 16 2.224404
+C21 18 gnd 2.080806f
+R18 18 17 2.224404
+C22 19 gnd 2.080806f
+R19 19 18 2.224404
+C23 20 gnd 2.080806f
+R20 20 19 2.224404
+C24 21 gnd 2.080806f
+R21 21 20 2.224404
+C25 22 gnd 2.080806f
+R22 22 21 2.224404
+C26 23 gnd 2.080806f
+R23 23 22 2.224404
+C27 24 gnd 2.080806f
+R24 24 23 2.224404
+C28 25 gnd 2.080806f
+R25 25 24 2.224404
+C29 26 gnd 2.080806f
+R26 26 25 2.224404
+C30 27 gnd 2.080806f
+R27 27 26 2.224404
+C31 28 gnd 2.080806f
+R28 28 27 2.224404
+C32 29 gnd 2.080806f
+R29 29 28 2.224404
+C33 30 gnd 2.080806f
+R30 30 29 2.224404
+C34 31 gnd 2.080806f
+R31 31 30 2.224404
+C35 32 gnd 2.080806f
+R32 32 31 2.224404
+C36 33 gnd 2.080806f
+R33 33 32 2.224404
+C37 34 gnd 2.080806f
+R34 34 33 2.224404
+C38 35 gnd 2.080806f
+R35 35 34 2.224404
+C39 36 gnd 2.080806f
+R36 36 35 2.224404
+C40 37 gnd 2.080806f
+R37 37 36 2.224404
+C41 38 gnd 2.080806f
+R38 38 37 2.224404
+C42 39 gnd 2.080806f
+R39 39 38 2.224404
+C43 40 gnd 2.080806f
+R40 40 39 2.224404
+C44 41 gnd 2.080806f
+R41 41 40 2.224404
+C45 42 gnd 2.080806f
+R42 42 41 2.224404
+C46 43 gnd 2.080806f
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+C47 44 gnd 2.080806f
+R44 44 43 2.224404
+C48 45 gnd 2.080806f
+R45 45 44 2.224404
+C49 46 gnd 2.080806f
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+R47 47 46 2.224404
+C51 48 gnd 2.080806f
+R48 48 47 2.224404
+C52 49 gnd 2.080806f
+R49 49 48 2.224404
+C53 50 gnd 2.080806f
+R50 50 49 2.224404
+C54 51 gnd 2.080806f
+R51 51 50 2.224404
+C55 52 gnd 2.080806f
+R52 52 51 2.224404
+C56 53 gnd 2.080806f
+R53 53 52 2.224404
+C57 54 gnd 2.080806f
+R54 54 53 2.224404
+C58 55 gnd 2.080806f
+R55 55 54 2.224404
+C59 56 gnd 2.080806f
+R56 56 55 2.224404
+C60 57 gnd 2.080806f
+R57 57 56 2.224404
+C61 58 gnd 2.080806f
+R58 58 57 2.224404
+C62 59 gnd 2.080806f
+R59 59 58 2.224404
+C63 60 gnd 2.080806f
+R60 60 59 2.224404
+C64 61 gnd 2.080806f
+R61 61 60 2.224404
+C65 62 gnd 2.080806f
+R62 62 61 2.224404
+C66 63 gnd 2.080806f
+R63 63 62 2.224404
+C67 64 gnd 2.080806f
+R64 64 63 2.224404
+C68 65 gnd 2.080806f
+R65 65 64 2.224404
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+C69 66 gnd 2.080806f
+R67 66 g202_1 2.224404
+C70 67 gnd 2.080806f
+R68 66 67 2.224404
+C71 68 gnd 2.080806f
+R69 67 68 2.224404
+C72 69 gnd 2.080806f
+R70 68 69 2.224404
+C73 70 gnd 2.080806f
+R71 70 69 2.224404
+C74 71 gnd 2.080806f
+R72 71 70 2.224404
+C75 72 gnd 2.080806f
+R73 72 71 2.224404
+C76 73 gnd 2.080806f
+R74 73 72 2.224404
+C77 74 gnd 2.080806f
+R75 74 73 2.224404
+C78 75 gnd 2.080806f
+R76 74 75 2.224404
+C79 76 gnd 2.080806f
+R77 76 75 2.224404
+C80 77 gnd 2.080806f
+R78 77 76 2.224404
+C81 78 gnd 2.080806f
+R79 78 77 2.224404
+C82 79 gnd 2.080806f
+R80 79 78 2.224404
+C83 80 gnd 2.080806f
+R81 80 79 2.224404
+C84 81 gnd 2.080806f
+R82 80 81 2.224404
+C85 82 gnd 2.080806f
+R83 81 82 2.224404
+C86 83 gnd 2.080806f
+R84 82 83 2.224404
+C87 84 gnd 2.080806f
+R85 84 83 2.224404
+C88 85 gnd 2.080806f
+R86 84 85 2.224404
+C89 86 gnd 2.080806f
+R87 85 86 2.224404
+C90 87 gnd 2.080806f
+R88 86 87 2.224404
+C91 88 gnd 2.080806f
+R89 87 88 2.224404
+C92 89 gnd 2.080806f
+R90 88 89 2.224404
+C93 90 gnd 2.080806f
+R91 89 90 2.224404
+C94 91 gnd 2.080806f
+R92 90 91 2.224404
+C95 92 gnd 2.080806f
+R93 91 92 2.224404
+C96 93 gnd 2.080806f
+R94 92 93 2.224404
+C97 94 gnd 2.080806f
+R95 93 94 2.224404
+C98 95 gnd 2.080806f
+R96 94 95 2.224404
+C99 96 gnd 2.080806f
+R97 96 95 2.224404
+C100 97 gnd 2.080806f
+R98 96 97 2.224404
+C101 98 gnd 2.080806f
+R99 98 97 2.224404
+C102 99 gnd 2.080806f
+R100 98 99 2.224404
+C103 100 gnd 2.080806f
+R101 99 100 2.224404
+C104 101 gnd 2.080806f
+R102 100 101 2.224404
+C105 102 gnd 2.080806f
+R103 102 101 2.224404
+C106 103 gnd 2.080806f
+R104 103 102 2.224404
+C107 104 gnd 2.080806f
+R105 104 103 2.224404
+C108 105 gnd 2.080806f
+R106 104 105 2.224404
+C109 106 gnd 2.080806f
+R107 106 105 2.224404
+R108 106 g202_2 2.224404
+.ends
+
+.subckt netg14 g14_0 g14_2 g14_1 gnd
+C1  g14_0 gnd 2.080806f
+C2  g14_2 gnd 2.080806f
+C3  g14_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g14_0 2.224404
+R2 g14_1 1 2.224404
+C5 2 gnd 2.080806f
+R3 2 g14_1 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 11 10 2.224404
+C15 12 gnd 2.080806f
+R13 12 11 2.224404
+C16 13 gnd 2.080806f
+R14 13 12 2.224404
+C17 14 gnd 2.080806f
+R15 14 13 2.224404
+C18 15 gnd 2.080806f
+R16 15 14 2.224404
+C19 16 gnd 2.080806f
+R17 16 15 2.224404
+C20 17 gnd 2.080806f
+R18 17 16 2.224404
+C21 18 gnd 2.080806f
+R19 18 17 2.224404
+C22 19 gnd 2.080806f
+R20 19 18 2.224404
+C23 20 gnd 2.080806f
+R21 20 19 2.224404
+C24 21 gnd 2.080806f
+R22 21 20 2.224404
+C25 22 gnd 2.080806f
+R23 22 21 2.224404
+C26 23 gnd 2.080806f
+R24 23 22 2.224404
+C27 24 gnd 2.080806f
+R25 24 23 2.224404
+C28 25 gnd 2.080806f
+R26 25 24 2.224404
+C29 26 gnd 2.080806f
+R27 26 25 2.224404
+C30 27 gnd 2.080806f
+R28 27 26 2.224404
+C31 28 gnd 2.080806f
+R29 28 27 2.224404
+C32 29 gnd 2.080806f
+R30 29 28 2.224404
+C33 30 gnd 2.080806f
+R31 30 29 2.224404
+C34 31 gnd 2.080806f
+R32 31 30 2.224404
+C35 32 gnd 2.080806f
+R33 32 31 2.224404
+C36 33 gnd 2.080806f
+R34 33 32 2.224404
+C37 34 gnd 2.080806f
+R35 34 33 2.224404
+C38 35 gnd 2.080806f
+R36 35 34 2.224404
+C39 36 gnd 2.080806f
+R37 36 35 2.224404
+C40 37 gnd 2.080806f
+R38 37 36 2.224404
+C41 38 gnd 2.080806f
+R39 38 37 2.224404
+C42 39 gnd 2.080806f
+R40 39 38 2.224404
+C43 40 gnd 2.080806f
+R41 40 39 2.224404
+C44 41 gnd 2.080806f
+R42 41 40 2.224404
+C45 42 gnd 2.080806f
+R43 42 41 2.224404
+C46 43 gnd 2.080806f
+R44 43 42 2.224404
+C47 44 gnd 2.080806f
+R45 44 43 2.224404
+C48 45 gnd 2.080806f
+R46 45 44 2.224404
+C49 46 gnd 2.080806f
+R47 46 45 2.224404
+C50 47 gnd 2.080806f
+R48 47 46 2.224404
+C51 48 gnd 2.080806f
+R49 48 47 2.224404
+C52 49 gnd 2.080806f
+R50 49 48 2.224404
+C53 50 gnd 2.080806f
+R51 50 49 2.224404
+C54 51 gnd 2.080806f
+R52 51 50 2.224404
+C55 52 gnd 2.080806f
+R53 52 51 2.224404
+C56 53 gnd 2.080806f
+R54 53 52 2.224404
+C57 54 gnd 2.080806f
+R55 54 53 2.224404
+C58 55 gnd 2.080806f
+R56 55 54 2.224404
+C59 56 gnd 2.080806f
+R57 56 55 2.224404
+C60 57 gnd 2.080806f
+R58 57 56 2.224404
+C61 58 gnd 2.080806f
+R59 58 57 2.224404
+C62 59 gnd 2.080806f
+R60 59 58 2.224404
+C63 60 gnd 2.080806f
+R61 60 59 2.224404
+C64 61 gnd 2.080806f
+R62 61 60 2.224404
+C65 62 gnd 2.080806f
+R63 62 61 2.224404
+C66 63 gnd 2.080806f
+R64 63 62 2.224404
+C67 64 gnd 2.080806f
+R65 64 63 2.224404
+C68 65 gnd 2.080806f
+R66 65 64 2.224404
+C69 66 gnd 2.080806f
+R67 66 65 2.224404
+C70 67 gnd 2.080806f
+R68 67 66 2.224404
+C71 68 gnd 2.080806f
+R69 68 67 2.224404
+C72 69 gnd 2.080806f
+R70 69 68 2.224404
+C73 70 gnd 2.080806f
+R71 70 69 2.224404
+C74 71 gnd 2.080806f
+R72 71 70 2.224404
+C75 72 gnd 2.080806f
+R73 72 71 2.224404
+C76 73 gnd 2.080806f
+R74 73 72 2.224404
+C77 74 gnd 2.080806f
+R75 74 73 2.224404
+C78 75 gnd 2.080806f
+R76 75 74 2.224404
+C79 76 gnd 2.080806f
+R77 76 75 2.224404
+C80 77 gnd 2.080806f
+R78 77 76 2.224404
+C81 78 gnd 2.080806f
+R79 78 77 2.224404
+C82 79 gnd 2.080806f
+R80 79 78 2.224404
+C83 80 gnd 2.080806f
+R81 80 79 2.224404
+C84 81 gnd 2.080806f
+R82 81 80 2.224404
+C85 82 gnd 2.080806f
+R83 82 81 2.224404
+C86 83 gnd 2.080806f
+R84 83 82 2.224404
+C87 84 gnd 2.080806f
+R85 84 83 2.224404
+C88 85 gnd 2.080806f
+R86 85 84 2.224404
+R87 g14_2 85 2.224404
+.ends
+
+.subckt netg176 g176_2 g176_1 g176_0 gnd
+C1  g176_2 gnd 2.080806f
+C2  g176_1 gnd 2.080806f
+C3  g176_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g176_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 4 5 2.224404
+C9 6 gnd 2.080806f
+R6 5 6 2.224404
+C10 7 gnd 2.080806f
+R7 6 7 2.224404
+C11 8 gnd 2.080806f
+R8 7 8 2.224404
+C12 9 gnd 2.080806f
+R9 8 9 2.224404
+C13 10 gnd 2.080806f
+R10 10 9 2.224404
+C14 11 gnd 2.080806f
+R11 11 10 2.224404
+C15 12 gnd 2.080806f
+R12 12 11 2.224404
+C16 13 gnd 2.080806f
+R13 13 12 2.224404
+C17 14 gnd 2.080806f
+R14 14 13 2.224404
+C18 15 gnd 2.080806f
+R15 15 14 2.224404
+C19 16 gnd 2.080806f
+R16 16 15 2.224404
+C20 17 gnd 2.080806f
+R17 17 16 2.224404
+C21 18 gnd 2.080806f
+R18 18 17 2.224404
+C22 19 gnd 2.080806f
+R19 19 18 2.224404
+C23 20 gnd 2.080806f
+R20 20 19 2.224404
+C24 21 gnd 2.080806f
+R21 21 20 2.224404
+C25 22 gnd 2.080806f
+R22 22 21 2.224404
+C26 23 gnd 2.080806f
+R23 23 22 2.224404
+C27 24 gnd 2.080806f
+R24 23 24 2.224404
+C28 25 gnd 2.080806f
+R25 24 25 2.224404
+C29 26 gnd 2.080806f
+R26 25 26 2.224404
+C30 27 gnd 2.080806f
+R27 26 27 2.224404
+C31 28 gnd 2.080806f
+R28 27 28 2.224404
+C32 29 gnd 2.080806f
+R29 28 29 2.224404
+C33 30 gnd 2.080806f
+R30 30 29 2.224404
+C34 31 gnd 2.080806f
+R31 31 30 2.224404
+C35 32 gnd 2.080806f
+R32 32 31 2.224404
+C36 33 gnd 2.080806f
+R33 33 32 2.224404
+C37 34 gnd 2.080806f
+R34 34 33 2.224404
+C38 35 gnd 2.080806f
+R35 35 34 2.224404
+C39 36 gnd 2.080806f
+R36 36 35 2.224404
+C40 37 gnd 2.080806f
+R37 37 36 2.224404
+C41 38 gnd 2.080806f
+R38 37 38 2.224404
+C42 39 gnd 2.080806f
+R39 39 38 2.224404
+C43 40 gnd 2.080806f
+R40 40 39 2.224404
+R41 40 g176_2 2.224404
+C44 41 gnd 2.080806f
+R42 g176_0 41 2.224404
+C45 42 gnd 2.080806f
+R43 41 42 2.224404
+C46 43 gnd 2.080806f
+R44 42 43 2.224404
+C47 44 gnd 2.080806f
+R45 43 44 2.224404
+C48 45 gnd 2.080806f
+R46 44 45 2.224404
+C49 46 gnd 2.080806f
+R47 45 46 2.224404
+C50 47 gnd 2.080806f
+R48 46 47 2.224404
+C51 48 gnd 2.080806f
+R49 47 48 2.224404
+C52 49 gnd 2.080806f
+R50 48 49 2.224404
+C53 50 gnd 2.080806f
+R51 49 50 2.224404
+C54 51 gnd 2.080806f
+R52 50 51 2.224404
+C55 52 gnd 2.080806f
+R53 51 52 2.224404
+C56 53 gnd 2.080806f
+R54 52 53 2.224404
+C57 54 gnd 2.080806f
+R55 53 54 2.224404
+C58 55 gnd 2.080806f
+R56 54 55 2.224404
+C59 56 gnd 2.080806f
+R57 55 56 2.224404
+C60 57 gnd 2.080806f
+R58 56 57 2.224404
+C61 58 gnd 2.080806f
+R59 57 58 2.224404
+C62 59 gnd 2.080806f
+R60 58 59 2.224404
+C63 60 gnd 2.080806f
+R61 59 60 2.224404
+C64 61 gnd 2.080806f
+R62 60 61 2.224404
+C65 62 gnd 2.080806f
+R63 61 62 2.224404
+C66 63 gnd 2.080806f
+R64 62 63 2.224404
+C67 64 gnd 2.080806f
+R65 63 64 2.224404
+C68 65 gnd 2.080806f
+R66 64 65 2.224404
+C69 66 gnd 2.080806f
+R67 65 66 2.224404
+C70 67 gnd 2.080806f
+R68 66 67 2.224404
+C71 68 gnd 2.080806f
+R69 67 68 2.224404
+C72 69 gnd 2.080806f
+R70 68 69 2.224404
+C73 70 gnd 2.080806f
+R71 69 70 2.224404
+C74 71 gnd 2.080806f
+R72 70 71 2.224404
+C75 72 gnd 2.080806f
+R73 71 72 2.224404
+C76 73 gnd 2.080806f
+R74 72 73 2.224404
+C77 74 gnd 2.080806f
+R75 73 74 2.224404
+C78 75 gnd 2.080806f
+R76 74 75 2.224404
+C79 76 gnd 2.080806f
+R77 75 76 2.224404
+C80 77 gnd 2.080806f
+R78 76 77 2.224404
+C81 78 gnd 2.080806f
+R79 77 78 2.224404
+C82 79 gnd 2.080806f
+R80 78 79 2.224404
+C83 80 gnd 2.080806f
+R81 79 80 2.224404
+C84 81 gnd 2.080806f
+R82 80 81 2.224404
+C85 82 gnd 2.080806f
+R83 81 82 2.224404
+C86 83 gnd 2.080806f
+R84 82 83 2.224404
+C87 84 gnd 2.080806f
+R85 83 84 2.224404
+C88 85 gnd 2.080806f
+R86 84 85 2.224404
+C89 86 gnd 2.080806f
+R87 85 86 2.224404
+C90 87 gnd 2.080806f
+R88 86 87 2.224404
+C91 88 gnd 2.080806f
+R89 87 88 2.224404
+C92 89 gnd 2.080806f
+R90 88 89 2.224404
+C93 90 gnd 2.080806f
+R91 89 90 2.224404
+C94 91 gnd 2.080806f
+R92 90 91 2.224404
+C95 92 gnd 2.080806f
+R93 91 92 2.224404
+C96 93 gnd 2.080806f
+R94 92 93 2.224404
+C97 94 gnd 2.080806f
+R95 93 94 2.224404
+C98 95 gnd 2.080806f
+R96 94 95 2.224404
+C99 96 gnd 2.080806f
+R97 95 96 2.224404
+C100 97 gnd 2.080806f
+R98 96 97 2.224404
+C101 98 gnd 2.080806f
+R99 97 98 2.224404
+R100 98 g176_1 2.224404
+.ends
+
+.subckt netg13 g13_2 g13_1 g13_0 gnd
+C1  g13_2 gnd 2.080806f
+C2  g13_1 gnd 2.080806f
+C3  g13_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g13_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+R3 2 g13_1 2.224404
+C6 3 gnd 2.080806f
+R4 3 g13_0 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 11 10 2.224404
+C15 12 gnd 2.080806f
+R13 12 11 2.224404
+C16 13 gnd 2.080806f
+R14 13 12 2.224404
+C17 14 gnd 2.080806f
+R15 14 13 2.224404
+C18 15 gnd 2.080806f
+R16 15 14 2.224404
+C19 16 gnd 2.080806f
+R17 16 15 2.224404
+C20 17 gnd 2.080806f
+R18 17 16 2.224404
+C21 18 gnd 2.080806f
+R19 18 17 2.224404
+C22 19 gnd 2.080806f
+R20 19 18 2.224404
+C23 20 gnd 2.080806f
+R21 20 19 2.224404
+C24 21 gnd 2.080806f
+R22 21 20 2.224404
+C25 22 gnd 2.080806f
+R23 22 21 2.224404
+C26 23 gnd 2.080806f
+R24 23 22 2.224404
+C27 24 gnd 2.080806f
+R25 24 23 2.224404
+C28 25 gnd 2.080806f
+R26 25 24 2.224404
+C29 26 gnd 2.080806f
+R27 26 25 2.224404
+C30 27 gnd 2.080806f
+R28 27 26 2.224404
+C31 28 gnd 2.080806f
+R29 28 27 2.224404
+C32 29 gnd 2.080806f
+R30 29 28 2.224404
+C33 30 gnd 2.080806f
+R31 30 29 2.224404
+C34 31 gnd 2.080806f
+R32 31 30 2.224404
+C35 32 gnd 2.080806f
+R33 32 31 2.224404
+C36 33 gnd 2.080806f
+R34 33 32 2.224404
+C37 34 gnd 2.080806f
+R35 34 33 2.224404
+C38 35 gnd 2.080806f
+R36 35 34 2.224404
+C39 36 gnd 2.080806f
+R37 36 35 2.224404
+C40 37 gnd 2.080806f
+R38 37 36 2.224404
+C41 38 gnd 2.080806f
+R39 38 37 2.224404
+C42 39 gnd 2.080806f
+R40 39 38 2.224404
+C43 40 gnd 2.080806f
+R41 40 39 2.224404
+C44 41 gnd 2.080806f
+R42 41 40 2.224404
+C45 42 gnd 2.080806f
+R43 42 41 2.224404
+C46 43 gnd 2.080806f
+R44 43 42 2.224404
+C47 44 gnd 2.080806f
+R45 44 43 2.224404
+C48 45 gnd 2.080806f
+R46 45 44 2.224404
+C49 46 gnd 2.080806f
+R47 46 45 2.224404
+C50 47 gnd 2.080806f
+R48 47 46 2.224404
+C51 48 gnd 2.080806f
+R49 48 47 2.224404
+C52 49 gnd 2.080806f
+R50 49 48 2.224404
+C53 50 gnd 2.080806f
+R51 50 49 2.224404
+C54 51 gnd 2.080806f
+R52 51 50 2.224404
+C55 52 gnd 2.080806f
+R53 52 51 2.224404
+C56 53 gnd 2.080806f
+R54 53 52 2.224404
+C57 54 gnd 2.080806f
+R55 54 53 2.224404
+C58 55 gnd 2.080806f
+R56 55 54 2.224404
+C59 56 gnd 2.080806f
+R57 56 55 2.224404
+C60 57 gnd 2.080806f
+R58 57 56 2.224404
+C61 58 gnd 2.080806f
+R59 58 57 2.224404
+C62 59 gnd 2.080806f
+R60 59 58 2.224404
+C63 60 gnd 2.080806f
+R61 60 59 2.224404
+C64 61 gnd 2.080806f
+R62 61 60 2.224404
+C65 62 gnd 2.080806f
+R63 62 61 2.224404
+C66 63 gnd 2.080806f
+R64 63 62 2.224404
+C67 64 gnd 2.080806f
+R65 64 63 2.224404
+C68 65 gnd 2.080806f
+R66 65 64 2.224404
+C69 66 gnd 2.080806f
+R67 66 65 2.224404
+C70 67 gnd 2.080806f
+R68 67 66 2.224404
+C71 68 gnd 2.080806f
+R69 68 67 2.224404
+C72 69 gnd 2.080806f
+R70 69 68 2.224404
+C73 70 gnd 2.080806f
+R71 70 69 2.224404
+C74 71 gnd 2.080806f
+R72 71 70 2.224404
+C75 72 gnd 2.080806f
+R73 72 71 2.224404
+C76 73 gnd 2.080806f
+R74 73 72 2.224404
+C77 74 gnd 2.080806f
+R75 74 73 2.224404
+C78 75 gnd 2.080806f
+R76 75 74 2.224404
+C79 76 gnd 2.080806f
+R77 76 75 2.224404
+C80 77 gnd 2.080806f
+R78 77 76 2.224404
+C81 78 gnd 2.080806f
+R79 78 77 2.224404
+C82 79 gnd 2.080806f
+R80 79 78 2.224404
+C83 80 gnd 2.080806f
+R81 80 79 2.224404
+C84 81 gnd 2.080806f
+R82 81 80 2.224404
+C85 82 gnd 2.080806f
+R83 82 81 2.224404
+C86 83 gnd 2.080806f
+R84 83 82 2.224404
+C87 84 gnd 2.080806f
+R85 84 83 2.224404
+C88 85 gnd 2.080806f
+R86 85 84 2.224404
+R87 g13_2 85 2.224404
+.ends
+
+.subckt netg1731 g1731_5 g1731_4 g1731_0 g1731_3 g1731_1 g1731_2 g1731_6 gnd
+C1  g1731_5 gnd 2.080806f
+C2  g1731_4 gnd 2.080806f
+C3  g1731_0 gnd 2.080806f
+C4  g1731_3 gnd 2.080806f
+C5  g1731_1 gnd 2.080806f
+C6  g1731_2 gnd 2.080806f
+C7  g1731_6 gnd 2.080806f
+R1 g1731_4 g1731_0 2.224404
+C8 1 gnd 2.080806f
+R2 g1731_4 1 2.224404
+C9 2 gnd 2.080806f
+R3 2 1 2.224404
+C10 3 gnd 2.080806f
+R4 3 2 2.224404
+C11 4 gnd 2.080806f
+R5 4 3 2.224404
+C12 5 gnd 2.080806f
+R6 5 4 2.224404
+C13 6 gnd 2.080806f
+R7 6 5 2.224404
+C14 7 gnd 2.080806f
+R8 7 6 2.224404
+C15 8 gnd 2.080806f
+R9 8 7 2.224404
+C16 9 gnd 2.080806f
+R10 9 8 2.224404
+C17 10 gnd 2.080806f
+R11 10 9 2.224404
+C18 11 gnd 2.080806f
+R12 11 10 2.224404
+C19 12 gnd 2.080806f
+R13 12 11 2.224404
+C20 13 gnd 2.080806f
+R14 12 13 2.224404
+C21 14 gnd 2.080806f
+R15 13 14 2.224404
+C22 15 gnd 2.080806f
+R16 15 14 2.224404
+R17 g1731_1 15 2.224404
+C23 16 gnd 2.080806f
+R18 14 16 2.224404
+C24 17 gnd 2.080806f
+R19 16 17 2.224404
+C25 18 gnd 2.080806f
+R20 17 18 2.224404
+C26 19 gnd 2.080806f
+R21 18 19 2.224404
+R22 19 g1731_2 2.224404
+C27 20 gnd 2.080806f
+R23 20 g1731_2 2.224404
+C28 21 gnd 2.080806f
+R24 20 21 2.224404
+C29 22 gnd 2.080806f
+R25 22 21 2.224404
+C30 23 gnd 2.080806f
+R26 22 23 2.224404
+C31 24 gnd 2.080806f
+R27 23 24 2.224404
+C32 25 gnd 2.080806f
+R28 25 24 2.224404
+C33 26 gnd 2.080806f
+R29 25 26 2.224404
+C34 27 gnd 2.080806f
+R30 26 27 2.224404
+R31 27 g1731_3 2.224404
+C35 28 gnd 2.080806f
+R32 g1731_3 28 2.224404
+C36 29 gnd 2.080806f
+R33 28 29 2.224404
+C37 30 gnd 2.080806f
+R34 29 30 2.224404
+C38 31 gnd 2.080806f
+R35 30 31 2.224404
+C39 32 gnd 2.080806f
+R36 31 32 2.224404
+C40 33 gnd 2.080806f
+R37 32 33 2.224404
+C41 34 gnd 2.080806f
+R38 33 34 2.224404
+C42 35 gnd 2.080806f
+R39 34 35 2.224404
+C43 36 gnd 2.080806f
+R40 35 36 2.224404
+C44 37 gnd 2.080806f
+R41 36 37 2.224404
+C45 38 gnd 2.080806f
+R42 37 38 2.224404
+C46 39 gnd 2.080806f
+R43 38 39 2.224404
+C47 40 gnd 2.080806f
+R44 39 40 2.224404
+C48 41 gnd 2.080806f
+R45 40 41 2.224404
+C49 42 gnd 2.080806f
+R46 41 42 2.224404
+C50 43 gnd 2.080806f
+R47 42 43 2.224404
+C51 44 gnd 2.080806f
+R48 43 44 2.224404
+C52 45 gnd 2.080806f
+R49 44 45 2.224404
+C53 46 gnd 2.080806f
+R50 45 46 2.224404
+C54 47 gnd 2.080806f
+R51 46 47 2.224404
+C55 48 gnd 2.080806f
+R52 47 48 2.224404
+C56 49 gnd 2.080806f
+R53 48 49 2.224404
+C57 50 gnd 2.080806f
+R54 49 50 2.224404
+C58 51 gnd 2.080806f
+R55 50 51 2.224404
+C59 52 gnd 2.080806f
+R56 51 52 2.224404
+C60 53 gnd 2.080806f
+R57 52 53 2.224404
+C61 54 gnd 2.080806f
+R58 53 54 2.224404
+C62 55 gnd 2.080806f
+R59 54 55 2.224404
+C63 56 gnd 2.080806f
+R60 55 56 2.224404
+C64 57 gnd 2.080806f
+R61 56 57 2.224404
+C65 58 gnd 2.080806f
+R62 57 58 2.224404
+C66 59 gnd 2.080806f
+R63 58 59 2.224404
+C67 60 gnd 2.080806f
+R64 59 60 2.224404
+C68 61 gnd 2.080806f
+R65 60 61 2.224404
+C69 62 gnd 2.080806f
+R66 61 62 2.224404
+C70 63 gnd 2.080806f
+R67 62 63 2.224404
+C71 64 gnd 2.080806f
+R68 63 64 2.224404
+C72 65 gnd 2.080806f
+R69 64 65 2.224404
+C73 66 gnd 2.080806f
+R70 65 66 2.224404
+C74 67 gnd 2.080806f
+R71 66 67 2.224404
+C75 68 gnd 2.080806f
+R72 67 68 2.224404
+C76 69 gnd 2.080806f
+R73 68 69 2.224404
+C77 70 gnd 2.080806f
+R74 69 70 2.224404
+C78 71 gnd 2.080806f
+R75 70 71 2.224404
+C79 72 gnd 2.080806f
+R76 71 72 2.224404
+C80 73 gnd 2.080806f
+R77 72 73 2.224404
+C81 74 gnd 2.080806f
+R78 73 74 2.224404
+C82 75 gnd 2.080806f
+R79 74 75 2.224404
+C83 76 gnd 2.080806f
+R80 75 76 2.224404
+C84 77 gnd 2.080806f
+R81 76 77 2.224404
+C85 78 gnd 2.080806f
+R82 77 78 2.224404
+C86 79 gnd 2.080806f
+R83 78 79 2.224404
+C87 80 gnd 2.080806f
+R84 79 80 2.224404
+C88 81 gnd 2.080806f
+R85 81 80 2.224404
+C89 82 gnd 2.080806f
+R86 81 82 2.224404
+C90 83 gnd 2.080806f
+R87 82 83 2.224404
+C91 84 gnd 2.080806f
+R88 84 83 2.224404
+C92 85 gnd 2.080806f
+R89 85 84 2.224404
+C93 86 gnd 2.080806f
+R90 85 86 2.224404
+C94 87 gnd 2.080806f
+R91 86 87 2.224404
+C95 88 gnd 2.080806f
+R92 87 88 2.224404
+C96 89 gnd 2.080806f
+R93 88 89 2.224404
+C97 90 gnd 2.080806f
+R94 89 90 2.224404
+C98 91 gnd 2.080806f
+R95 90 91 2.224404
+C99 92 gnd 2.080806f
+R96 91 92 2.224404
+C100 93 gnd 2.080806f
+R97 92 93 2.224404
+C101 94 gnd 2.080806f
+R98 93 94 2.224404
+C102 95 gnd 2.080806f
+R99 94 95 2.224404
+R100 95 g1731_5 2.224404
+C103 96 gnd 2.080806f
+R101 95 96 2.224404
+C104 97 gnd 2.080806f
+R102 96 97 2.224404
+C105 98 gnd 2.080806f
+R103 97 98 2.224404
+C106 99 gnd 2.080806f
+R104 98 99 2.224404
+C107 100 gnd 2.080806f
+R105 99 100 2.224404
+C108 101 gnd 2.080806f
+R106 100 101 2.224404
+C109 102 gnd 2.080806f
+R107 101 102 2.224404
+C110 103 gnd 2.080806f
+R108 102 103 2.224404
+C111 104 gnd 2.080806f
+R109 103 104 2.224404
+C112 105 gnd 2.080806f
+R110 105 104 2.224404
+C113 106 gnd 2.080806f
+R111 105 106 2.224404
+C114 107 gnd 2.080806f
+R112 106 107 2.224404
+C115 108 gnd 2.080806f
+R113 107 108 2.224404
+C116 109 gnd 2.080806f
+R114 108 109 2.224404
+R115 109 g1731_6 2.224404
+.ends
+
+.subckt netg1756 g1756_5 g1756_3 g1756_1 g1756_4 g1756_2 g1756_0 gnd
+C1  g1756_5 gnd 2.080806f
+C2  g1756_3 gnd 2.080806f
+C3  g1756_1 gnd 2.080806f
+C4  g1756_4 gnd 2.080806f
+C5  g1756_2 gnd 2.080806f
+C6  g1756_0 gnd 2.080806f
+C7 1 gnd 2.080806f
+R1 g1756_0 1 2.224404
+C8 2 gnd 2.080806f
+R2 1 2 2.224404
+C9 3 gnd 2.080806f
+R3 2 3 2.224404
+C10 4 gnd 2.080806f
+R4 3 4 2.224404
+C11 5 gnd 2.080806f
+R5 4 5 2.224404
+C12 6 gnd 2.080806f
+R6 5 6 2.224404
+C13 7 gnd 2.080806f
+R7 6 7 2.224404
+C14 8 gnd 2.080806f
+R8 7 8 2.224404
+R9 8 g1756_5 2.224404
+C15 9 gnd 2.080806f
+R10 9 g1756_0 2.224404
+C16 10 gnd 2.080806f
+R11 9 10 2.224404
+C17 11 gnd 2.080806f
+R12 10 11 2.224404
+C18 12 gnd 2.080806f
+R13 11 12 2.224404
+C19 13 gnd 2.080806f
+R14 12 13 2.224404
+C20 14 gnd 2.080806f
+R15 14 13 2.224404
+C21 15 gnd 2.080806f
+R16 15 14 2.224404
+C22 16 gnd 2.080806f
+R17 15 16 2.224404
+C23 17 gnd 2.080806f
+R18 16 17 2.224404
+C24 18 gnd 2.080806f
+R19 17 18 2.224404
+C25 19 gnd 2.080806f
+R20 18 19 2.224404
+C26 20 gnd 2.080806f
+R21 19 20 2.224404
+C27 21 gnd 2.080806f
+R22 20 21 2.224404
+C28 22 gnd 2.080806f
+R23 22 21 2.224404
+C29 23 gnd 2.080806f
+R24 23 22 2.224404
+C30 24 gnd 2.080806f
+R25 24 23 2.224404
+C31 25 gnd 2.080806f
+R26 25 24 2.224404
+C32 26 gnd 2.080806f
+R27 26 25 2.224404
+C33 27 gnd 2.080806f
+R28 27 26 2.224404
+C34 28 gnd 2.080806f
+R29 28 27 2.224404
+C35 29 gnd 2.080806f
+R30 29 28 2.224404
+C36 30 gnd 2.080806f
+R31 30 29 2.224404
+C37 31 gnd 2.080806f
+R32 31 30 2.224404
+C38 32 gnd 2.080806f
+R33 32 31 2.224404
+C39 33 gnd 2.080806f
+R34 33 32 2.224404
+C40 34 gnd 2.080806f
+R35 34 33 2.224404
+C41 35 gnd 2.080806f
+R36 35 34 2.224404
+C42 36 gnd 2.080806f
+R37 36 35 2.224404
+C43 37 gnd 2.080806f
+R38 37 36 2.224404
+C44 38 gnd 2.080806f
+R39 38 37 2.224404
+C45 39 gnd 2.080806f
+R40 39 38 2.224404
+C46 40 gnd 2.080806f
+R41 40 39 2.224404
+C47 41 gnd 2.080806f
+R42 41 40 2.224404
+C48 42 gnd 2.080806f
+R43 42 41 2.224404
+C49 43 gnd 2.080806f
+R44 43 42 2.224404
+C50 44 gnd 2.080806f
+R45 44 43 2.224404
+C51 45 gnd 2.080806f
+R46 45 44 2.224404
+C52 46 gnd 2.080806f
+R47 46 45 2.224404
+C53 47 gnd 2.080806f
+R48 47 46 2.224404
+C54 48 gnd 2.080806f
+R49 48 47 2.224404
+C55 49 gnd 2.080806f
+R50 49 48 2.224404
+C56 50 gnd 2.080806f
+R51 50 49 2.224404
+C57 51 gnd 2.080806f
+R52 51 50 2.224404
+C58 52 gnd 2.080806f
+R53 52 51 2.224404
+C59 53 gnd 2.080806f
+R54 53 52 2.224404
+C60 54 gnd 2.080806f
+R55 54 53 2.224404
+C61 55 gnd 2.080806f
+R56 55 54 2.224404
+C62 56 gnd 2.080806f
+R57 56 55 2.224404
+C63 57 gnd 2.080806f
+R58 57 56 2.224404
+C64 58 gnd 2.080806f
+R59 58 57 2.224404
+C65 59 gnd 2.080806f
+R60 59 58 2.224404
+C66 60 gnd 2.080806f
+R61 60 59 2.224404
+C67 61 gnd 2.080806f
+R62 61 60 2.224404
+C68 62 gnd 2.080806f
+R63 62 61 2.224404
+C69 63 gnd 2.080806f
+R64 63 62 2.224404
+C70 64 gnd 2.080806f
+R65 64 63 2.224404
+C71 65 gnd 2.080806f
+R66 65 64 2.224404
+C72 66 gnd 2.080806f
+R67 66 65 2.224404
+C73 67 gnd 2.080806f
+R68 67 66 2.224404
+C74 68 gnd 2.080806f
+R69 68 67 2.224404
+C75 69 gnd 2.080806f
+R70 69 68 2.224404
+C76 70 gnd 2.080806f
+R71 70 69 2.224404
+C77 71 gnd 2.080806f
+R72 71 70 2.224404
+C78 72 gnd 2.080806f
+R73 72 71 2.224404
+C79 73 gnd 2.080806f
+R74 73 72 2.224404
+C80 74 gnd 2.080806f
+R75 74 73 2.224404
+C81 75 gnd 2.080806f
+R76 75 74 2.224404
+C82 76 gnd 2.080806f
+R77 76 75 2.224404
+C83 77 gnd 2.080806f
+R78 77 76 2.224404
+C84 78 gnd 2.080806f
+R79 78 77 2.224404
+C85 79 gnd 2.080806f
+R80 79 78 2.224404
+C86 80 gnd 2.080806f
+R81 80 79 2.224404
+C87 81 gnd 2.080806f
+R82 81 80 2.224404
+C88 82 gnd 2.080806f
+R83 82 81 2.224404
+C89 83 gnd 2.080806f
+R84 83 82 2.224404
+C90 84 gnd 2.080806f
+R85 84 83 2.224404
+C91 85 gnd 2.080806f
+R86 85 84 2.224404
+C92 86 gnd 2.080806f
+R87 86 85 2.224404
+C93 87 gnd 2.080806f
+R88 87 86 2.224404
+C94 88 gnd 2.080806f
+R89 88 87 2.224404
+C95 89 gnd 2.080806f
+R90 89 88 2.224404
+C96 90 gnd 2.080806f
+R91 90 89 2.224404
+C97 91 gnd 2.080806f
+R92 91 90 2.224404
+C98 92 gnd 2.080806f
+R93 92 91 2.224404
+C99 93 gnd 2.080806f
+R94 93 92 2.224404
+C100 94 gnd 2.080806f
+R95 94 93 2.224404
+C101 95 gnd 2.080806f
+R96 95 94 2.224404
+C102 96 gnd 2.080806f
+R97 96 95 2.224404
+C103 97 gnd 2.080806f
+R98 96 97 2.224404
+R99 g1756_1 97 2.224404
+C104 98 gnd 2.080806f
+R100 g1756_1 98 2.224404
+C105 99 gnd 2.080806f
+R101 98 99 2.224404
+C106 100 gnd 2.080806f
+R102 99 100 2.224404
+R103 g1756_3 100 2.224404
+C107 101 gnd 2.080806f
+R104 101 g1756_1 2.224404
+C108 102 gnd 2.080806f
+R105 102 101 2.224404
+C109 103 gnd 2.080806f
+R106 103 102 2.224404
+C110 104 gnd 2.080806f
+R107 104 103 2.224404
+C111 105 gnd 2.080806f
+R108 105 104 2.224404
+C112 106 gnd 2.080806f
+R109 106 105 2.224404
+R110 g1756_4 106 2.224404
+C113 107 gnd 2.080806f
+R111 107 g1756_4 2.224404
+C114 108 gnd 2.080806f
+R112 108 107 2.224404
+C115 109 gnd 2.080806f
+R113 109 108 2.224404
+C116 110 gnd 2.080806f
+R114 110 109 2.224404
+C117 111 gnd 2.080806f
+R115 110 111 2.224404
+C118 112 gnd 2.080806f
+R116 111 112 2.224404
+R117 112 g1756_2 2.224404
+.ends
+
+.subckt netg201 g201_1 g201_2 g201_0 gnd
+C1  g201_1 gnd 2.080806f
+C2  g201_2 gnd 2.080806f
+C3  g201_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g201_0 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 5 6 2.224404
+C10 7 gnd 2.080806f
+R7 6 7 2.224404
+C11 8 gnd 2.080806f
+R8 7 8 2.224404
+C12 9 gnd 2.080806f
+R9 9 8 2.224404
+C13 10 gnd 2.080806f
+R10 9 10 2.224404
+C14 11 gnd 2.080806f
+R11 11 10 2.224404
+C15 12 gnd 2.080806f
+R12 12 11 2.224404
+C16 13 gnd 2.080806f
+R13 13 12 2.224404
+C17 14 gnd 2.080806f
+R14 14 13 2.224404
+C18 15 gnd 2.080806f
+R15 15 14 2.224404
+C19 16 gnd 2.080806f
+R16 15 16 2.224404
+C20 17 gnd 2.080806f
+R17 17 16 2.224404
+C21 18 gnd 2.080806f
+R18 18 17 2.224404
+C22 19 gnd 2.080806f
+R19 19 18 2.224404
+C23 20 gnd 2.080806f
+R20 20 19 2.224404
+C24 21 gnd 2.080806f
+R21 21 20 2.224404
+C25 22 gnd 2.080806f
+R22 22 21 2.224404
+C26 23 gnd 2.080806f
+R23 23 22 2.224404
+C27 24 gnd 2.080806f
+R24 24 23 2.224404
+C28 25 gnd 2.080806f
+R25 25 24 2.224404
+C29 26 gnd 2.080806f
+R26 26 25 2.224404
+C30 27 gnd 2.080806f
+R27 26 27 2.224404
+C31 28 gnd 2.080806f
+R28 28 27 2.224404
+C32 29 gnd 2.080806f
+R29 29 28 2.224404
+C33 30 gnd 2.080806f
+R30 29 30 2.224404
+C34 31 gnd 2.080806f
+R31 30 31 2.224404
+C35 32 gnd 2.080806f
+R32 32 31 2.224404
+C36 33 gnd 2.080806f
+R33 32 33 2.224404
+C37 34 gnd 2.080806f
+R34 34 33 2.224404
+C38 35 gnd 2.080806f
+R35 35 34 2.224404
+C39 36 gnd 2.080806f
+R36 36 35 2.224404
+C40 37 gnd 2.080806f
+R37 37 36 2.224404
+C41 38 gnd 2.080806f
+R38 38 37 2.224404
+C42 39 gnd 2.080806f
+R39 39 38 2.224404
+C43 40 gnd 2.080806f
+R40 39 40 2.224404
+C44 41 gnd 2.080806f
+R41 41 40 2.224404
+C45 42 gnd 2.080806f
+R42 41 42 2.224404
+C46 43 gnd 2.080806f
+R43 43 42 2.224404
+R44 g201_1 43 2.224404
+C47 44 gnd 2.080806f
+R45 4 44 2.224404
+C48 45 gnd 2.080806f
+R46 44 45 2.224404
+C49 46 gnd 2.080806f
+R47 45 46 2.224404
+C50 47 gnd 2.080806f
+R48 46 47 2.224404
+C51 48 gnd 2.080806f
+R49 47 48 2.224404
+C52 49 gnd 2.080806f
+R50 48 49 2.224404
+C53 50 gnd 2.080806f
+R51 49 50 2.224404
+C54 51 gnd 2.080806f
+R52 50 51 2.224404
+C55 52 gnd 2.080806f
+R53 51 52 2.224404
+C56 53 gnd 2.080806f
+R54 52 53 2.224404
+C57 54 gnd 2.080806f
+R55 53 54 2.224404
+C58 55 gnd 2.080806f
+R56 54 55 2.224404
+C59 56 gnd 2.080806f
+R57 55 56 2.224404
+C60 57 gnd 2.080806f
+R58 56 57 2.224404
+C61 58 gnd 2.080806f
+R59 57 58 2.224404
+C62 59 gnd 2.080806f
+R60 58 59 2.224404
+C63 60 gnd 2.080806f
+R61 59 60 2.224404
+C64 61 gnd 2.080806f
+R62 60 61 2.224404
+C65 62 gnd 2.080806f
+R63 61 62 2.224404
+C66 63 gnd 2.080806f
+R64 62 63 2.224404
+C67 64 gnd 2.080806f
+R65 63 64 2.224404
+C68 65 gnd 2.080806f
+R66 64 65 2.224404
+C69 66 gnd 2.080806f
+R67 65 66 2.224404
+C70 67 gnd 2.080806f
+R68 66 67 2.224404
+C71 68 gnd 2.080806f
+R69 67 68 2.224404
+C72 69 gnd 2.080806f
+R70 68 69 2.224404
+C73 70 gnd 2.080806f
+R71 69 70 2.224404
+C74 71 gnd 2.080806f
+R72 70 71 2.224404
+C75 72 gnd 2.080806f
+R73 71 72 2.224404
+C76 73 gnd 2.080806f
+R74 72 73 2.224404
+C77 74 gnd 2.080806f
+R75 73 74 2.224404
+C78 75 gnd 2.080806f
+R76 74 75 2.224404
+C79 76 gnd 2.080806f
+R77 75 76 2.224404
+C80 77 gnd 2.080806f
+R78 76 77 2.224404
+C81 78 gnd 2.080806f
+R79 77 78 2.224404
+C82 79 gnd 2.080806f
+R80 78 79 2.224404
+C83 80 gnd 2.080806f
+R81 79 80 2.224404
+C84 81 gnd 2.080806f
+R82 80 81 2.224404
+C85 82 gnd 2.080806f
+R83 81 82 2.224404
+C86 83 gnd 2.080806f
+R84 82 83 2.224404
+C87 84 gnd 2.080806f
+R85 83 84 2.224404
+C88 85 gnd 2.080806f
+R86 84 85 2.224404
+C89 86 gnd 2.080806f
+R87 85 86 2.224404
+C90 87 gnd 2.080806f
+R88 86 87 2.224404
+C91 88 gnd 2.080806f
+R89 87 88 2.224404
+C92 89 gnd 2.080806f
+R90 88 89 2.224404
+C93 90 gnd 2.080806f
+R91 89 90 2.224404
+C94 91 gnd 2.080806f
+R92 90 91 2.224404
+C95 92 gnd 2.080806f
+R93 91 92 2.224404
+C96 93 gnd 2.080806f
+R94 92 93 2.224404
+C97 94 gnd 2.080806f
+R95 93 94 2.224404
+C98 95 gnd 2.080806f
+R96 94 95 2.224404
+C99 96 gnd 2.080806f
+R97 95 96 2.224404
+C100 97 gnd 2.080806f
+R98 96 97 2.224404
+C101 98 gnd 2.080806f
+R99 97 98 2.224404
+C102 99 gnd 2.080806f
+R100 99 98 2.224404
+R101 g201_2 99 2.224404
+.ends
+
+.subckt netg203 g203_0 g203_2 g203_1 gnd
+C1  g203_0 gnd 2.080806f
+C2  g203_2 gnd 2.080806f
+C3  g203_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g203_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+C8 5 gnd 2.080806f
+R5 4 5 2.224404
+C9 6 gnd 2.080806f
+R6 5 6 2.224404
+C10 7 gnd 2.080806f
+R7 6 7 2.224404
+C11 8 gnd 2.080806f
+R8 7 8 2.224404
+C12 9 gnd 2.080806f
+R9 8 9 2.224404
+C13 10 gnd 2.080806f
+R10 9 10 2.224404
+C14 11 gnd 2.080806f
+R11 10 11 2.224404
+C15 12 gnd 2.080806f
+R12 11 12 2.224404
+C16 13 gnd 2.080806f
+R13 12 13 2.224404
+C17 14 gnd 2.080806f
+R14 13 14 2.224404
+C18 15 gnd 2.080806f
+R15 14 15 2.224404
+C19 16 gnd 2.080806f
+R16 15 16 2.224404
+C20 17 gnd 2.080806f
+R17 16 17 2.224404
+C21 18 gnd 2.080806f
+R18 17 18 2.224404
+C22 19 gnd 2.080806f
+R19 18 19 2.224404
+C23 20 gnd 2.080806f
+R20 19 20 2.224404
+C24 21 gnd 2.080806f
+R21 20 21 2.224404
+C25 22 gnd 2.080806f
+R22 21 22 2.224404
+C26 23 gnd 2.080806f
+R23 22 23 2.224404
+C27 24 gnd 2.080806f
+R24 23 24 2.224404
+C28 25 gnd 2.080806f
+R25 24 25 2.224404
+C29 26 gnd 2.080806f
+R26 25 26 2.224404
+C30 27 gnd 2.080806f
+R27 27 26 2.224404
+C31 28 gnd 2.080806f
+R28 28 27 2.224404
+C32 29 gnd 2.080806f
+R29 29 28 2.224404
+C33 30 gnd 2.080806f
+R30 30 29 2.224404
+C34 31 gnd 2.080806f
+R31 31 30 2.224404
+C35 32 gnd 2.080806f
+R32 32 31 2.224404
+C36 33 gnd 2.080806f
+R33 32 33 2.224404
+C37 34 gnd 2.080806f
+R34 33 34 2.224404
+C38 35 gnd 2.080806f
+R35 35 34 2.224404
+C39 36 gnd 2.080806f
+R36 36 35 2.224404
+C40 37 gnd 2.080806f
+R37 37 36 2.224404
+C41 38 gnd 2.080806f
+R38 38 37 2.224404
+C42 39 gnd 2.080806f
+R39 39 38 2.224404
+C43 40 gnd 2.080806f
+R40 40 39 2.224404
+C44 41 gnd 2.080806f
+R41 41 40 2.224404
+C45 42 gnd 2.080806f
+R42 41 42 2.224404
+C46 43 gnd 2.080806f
+R43 42 43 2.224404
+R44 43 g203_1 2.224404
+C47 44 gnd 2.080806f
+R45 26 44 2.224404
+C48 45 gnd 2.080806f
+R46 44 45 2.224404
+C49 46 gnd 2.080806f
+R47 45 46 2.224404
+C50 47 gnd 2.080806f
+R48 46 47 2.224404
+C51 48 gnd 2.080806f
+R49 47 48 2.224404
+C52 49 gnd 2.080806f
+R50 48 49 2.224404
+C53 50 gnd 2.080806f
+R51 49 50 2.224404
+C54 51 gnd 2.080806f
+R52 50 51 2.224404
+C55 52 gnd 2.080806f
+R53 51 52 2.224404
+C56 53 gnd 2.080806f
+R54 52 53 2.224404
+C57 54 gnd 2.080806f
+R55 53 54 2.224404
+C58 55 gnd 2.080806f
+R56 54 55 2.224404
+C59 56 gnd 2.080806f
+R57 55 56 2.224404
+C60 57 gnd 2.080806f
+R58 56 57 2.224404
+C61 58 gnd 2.080806f
+R59 57 58 2.224404
+C62 59 gnd 2.080806f
+R60 58 59 2.224404
+C63 60 gnd 2.080806f
+R61 59 60 2.224404
+C64 61 gnd 2.080806f
+R62 60 61 2.224404
+C65 62 gnd 2.080806f
+R63 61 62 2.224404
+C66 63 gnd 2.080806f
+R64 62 63 2.224404
+C67 64 gnd 2.080806f
+R65 63 64 2.224404
+C68 65 gnd 2.080806f
+R66 64 65 2.224404
+C69 66 gnd 2.080806f
+R67 65 66 2.224404
+C70 67 gnd 2.080806f
+R68 66 67 2.224404
+C71 68 gnd 2.080806f
+R69 67 68 2.224404
+C72 69 gnd 2.080806f
+R70 68 69 2.224404
+C73 70 gnd 2.080806f
+R71 69 70 2.224404
+C74 71 gnd 2.080806f
+R72 70 71 2.224404
+C75 72 gnd 2.080806f
+R73 72 71 2.224404
+C76 73 gnd 2.080806f
+R74 72 73 2.224404
+C77 74 gnd 2.080806f
+R75 73 74 2.224404
+C78 75 gnd 2.080806f
+R76 74 75 2.224404
+C79 76 gnd 2.080806f
+R77 75 76 2.224404
+C80 77 gnd 2.080806f
+R78 76 77 2.224404
+C81 78 gnd 2.080806f
+R79 77 78 2.224404
+C82 79 gnd 2.080806f
+R80 78 79 2.224404
+C83 80 gnd 2.080806f
+R81 79 80 2.224404
+C84 81 gnd 2.080806f
+R82 80 81 2.224404
+C85 82 gnd 2.080806f
+R83 81 82 2.224404
+C86 83 gnd 2.080806f
+R84 82 83 2.224404
+C87 84 gnd 2.080806f
+R85 83 84 2.224404
+C88 85 gnd 2.080806f
+R86 84 85 2.224404
+C89 86 gnd 2.080806f
+R87 85 86 2.224404
+C90 87 gnd 2.080806f
+R88 86 87 2.224404
+C91 88 gnd 2.080806f
+R89 87 88 2.224404
+C92 89 gnd 2.080806f
+R90 88 89 2.224404
+C93 90 gnd 2.080806f
+R91 89 90 2.224404
+R92 90 g203_2 2.224404
+.ends
+
+.subckt netg204 g204_1 g204_2 g204_0 gnd
+C1  g204_1 gnd 2.080806f
+C2  g204_2 gnd 2.080806f
+C3  g204_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g204_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 6 5 2.224404
+C10 7 gnd 2.080806f
+R7 7 6 2.224404
+C11 8 gnd 2.080806f
+R8 8 7 2.224404
+C12 9 gnd 2.080806f
+R9 8 9 2.224404
+C13 10 gnd 2.080806f
+R10 10 9 2.224404
+C14 11 gnd 2.080806f
+R11 10 11 2.224404
+C15 12 gnd 2.080806f
+R12 12 11 2.224404
+C16 13 gnd 2.080806f
+R13 13 12 2.224404
+C17 14 gnd 2.080806f
+R14 14 13 2.224404
+C18 15 gnd 2.080806f
+R15 15 14 2.224404
+C19 16 gnd 2.080806f
+R16 16 15 2.224404
+C20 17 gnd 2.080806f
+R17 17 16 2.224404
+C21 18 gnd 2.080806f
+R18 18 17 2.224404
+C22 19 gnd 2.080806f
+R19 19 18 2.224404
+C23 20 gnd 2.080806f
+R20 20 19 2.224404
+C24 21 gnd 2.080806f
+R21 20 21 2.224404
+C25 22 gnd 2.080806f
+R22 22 21 2.224404
+C26 23 gnd 2.080806f
+R23 23 22 2.224404
+C27 24 gnd 2.080806f
+R24 24 23 2.224404
+C28 25 gnd 2.080806f
+R25 25 24 2.224404
+C29 26 gnd 2.080806f
+R26 26 25 2.224404
+C30 27 gnd 2.080806f
+R27 27 26 2.224404
+C31 28 gnd 2.080806f
+R28 27 28 2.224404
+C32 29 gnd 2.080806f
+R29 28 29 2.224404
+C33 30 gnd 2.080806f
+R30 29 30 2.224404
+C34 31 gnd 2.080806f
+R31 30 31 2.224404
+C35 32 gnd 2.080806f
+R32 32 31 2.224404
+C36 33 gnd 2.080806f
+R33 32 33 2.224404
+C37 34 gnd 2.080806f
+R34 34 33 2.224404
+C38 35 gnd 2.080806f
+R35 35 34 2.224404
+C39 36 gnd 2.080806f
+R36 35 36 2.224404
+C40 37 gnd 2.080806f
+R37 37 36 2.224404
+C41 38 gnd 2.080806f
+R38 37 38 2.224404
+C42 39 gnd 2.080806f
+R39 38 39 2.224404
+C43 40 gnd 2.080806f
+R40 40 39 2.224404
+C44 41 gnd 2.080806f
+R41 41 40 2.224404
+C45 42 gnd 2.080806f
+R42 41 42 2.224404
+C46 43 gnd 2.080806f
+R43 43 42 2.224404
+C47 44 gnd 2.080806f
+R44 44 43 2.224404
+R45 44 g204_2 2.224404
+C48 45 gnd 2.080806f
+R46 5 45 2.224404
+C49 46 gnd 2.080806f
+R47 45 46 2.224404
+C50 47 gnd 2.080806f
+R48 46 47 2.224404
+C51 48 gnd 2.080806f
+R49 47 48 2.224404
+C52 49 gnd 2.080806f
+R50 48 49 2.224404
+C53 50 gnd 2.080806f
+R51 49 50 2.224404
+C54 51 gnd 2.080806f
+R52 50 51 2.224404
+C55 52 gnd 2.080806f
+R53 51 52 2.224404
+C56 53 gnd 2.080806f
+R54 52 53 2.224404
+C57 54 gnd 2.080806f
+R55 53 54 2.224404
+C58 55 gnd 2.080806f
+R56 54 55 2.224404
+C59 56 gnd 2.080806f
+R57 55 56 2.224404
+C60 57 gnd 2.080806f
+R58 56 57 2.224404
+C61 58 gnd 2.080806f
+R59 57 58 2.224404
+C62 59 gnd 2.080806f
+R60 58 59 2.224404
+C63 60 gnd 2.080806f
+R61 59 60 2.224404
+C64 61 gnd 2.080806f
+R62 60 61 2.224404
+C65 62 gnd 2.080806f
+R63 61 62 2.224404
+C66 63 gnd 2.080806f
+R64 62 63 2.224404
+C67 64 gnd 2.080806f
+R65 63 64 2.224404
+C68 65 gnd 2.080806f
+R66 64 65 2.224404
+C69 66 gnd 2.080806f
+R67 65 66 2.224404
+C70 67 gnd 2.080806f
+R68 66 67 2.224404
+C71 68 gnd 2.080806f
+R69 67 68 2.224404
+C72 69 gnd 2.080806f
+R70 68 69 2.224404
+C73 70 gnd 2.080806f
+R71 69 70 2.224404
+C74 71 gnd 2.080806f
+R72 70 71 2.224404
+C75 72 gnd 2.080806f
+R73 71 72 2.224404
+C76 73 gnd 2.080806f
+R74 72 73 2.224404
+C77 74 gnd 2.080806f
+R75 73 74 2.224404
+C78 75 gnd 2.080806f
+R76 74 75 2.224404
+C79 76 gnd 2.080806f
+R77 75 76 2.224404
+C80 77 gnd 2.080806f
+R78 76 77 2.224404
+C81 78 gnd 2.080806f
+R79 77 78 2.224404
+C82 79 gnd 2.080806f
+R80 78 79 2.224404
+C83 80 gnd 2.080806f
+R81 79 80 2.224404
+C84 81 gnd 2.080806f
+R82 80 81 2.224404
+C85 82 gnd 2.080806f
+R83 81 82 2.224404
+C86 83 gnd 2.080806f
+R84 82 83 2.224404
+C87 84 gnd 2.080806f
+R85 83 84 2.224404
+C88 85 gnd 2.080806f
+R86 85 84 2.224404
+C89 86 gnd 2.080806f
+R87 86 85 2.224404
+C90 87 gnd 2.080806f
+R88 86 87 2.224404
+C91 88 gnd 2.080806f
+R89 87 88 2.224404
+C92 89 gnd 2.080806f
+R90 88 89 2.224404
+C93 90 gnd 2.080806f
+R91 89 90 2.224404
+C94 91 gnd 2.080806f
+R92 90 91 2.224404
+C95 92 gnd 2.080806f
+R93 91 92 2.224404
+C96 93 gnd 2.080806f
+R94 92 93 2.224404
+C97 94 gnd 2.080806f
+R95 93 94 2.224404
+C98 95 gnd 2.080806f
+R96 94 95 2.224404
+C99 96 gnd 2.080806f
+R97 95 96 2.224404
+C100 97 gnd 2.080806f
+R98 96 97 2.224404
+C101 98 gnd 2.080806f
+R99 97 98 2.224404
+C102 99 gnd 2.080806f
+R100 98 99 2.224404
+C103 100 gnd 2.080806f
+R101 99 100 2.224404
+C104 101 gnd 2.080806f
+R102 100 101 2.224404
+C105 102 gnd 2.080806f
+R103 101 102 2.224404
+C106 103 gnd 2.080806f
+R104 102 103 2.224404
+C107 104 gnd 2.080806f
+R105 103 104 2.224404
+C108 105 gnd 2.080806f
+R106 105 104 2.224404
+R107 g204_1 105 2.224404
+.ends
+
+.subckt netg198 g198_0 g198_2 g198_1 gnd
+C1  g198_0 gnd 2.080806f
+C2  g198_2 gnd 2.080806f
+C3  g198_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g198_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 6 5 2.224404
+C10 7 gnd 2.080806f
+R7 6 7 2.224404
+C11 8 gnd 2.080806f
+R8 7 8 2.224404
+C12 9 gnd 2.080806f
+R9 9 8 2.224404
+C13 10 gnd 2.080806f
+R10 10 9 2.224404
+C14 11 gnd 2.080806f
+R11 10 11 2.224404
+C15 12 gnd 2.080806f
+R12 12 11 2.224404
+C16 13 gnd 2.080806f
+R13 12 13 2.224404
+C17 14 gnd 2.080806f
+R14 14 13 2.224404
+C18 15 gnd 2.080806f
+R15 15 14 2.224404
+C19 16 gnd 2.080806f
+R16 15 16 2.224404
+C20 17 gnd 2.080806f
+R17 17 16 2.224404
+C21 18 gnd 2.080806f
+R18 18 17 2.224404
+C22 19 gnd 2.080806f
+R19 18 19 2.224404
+C23 20 gnd 2.080806f
+R20 19 20 2.224404
+C24 21 gnd 2.080806f
+R21 20 21 2.224404
+C25 22 gnd 2.080806f
+R22 22 21 2.224404
+C26 23 gnd 2.080806f
+R23 22 23 2.224404
+C27 24 gnd 2.080806f
+R24 23 24 2.224404
+C28 25 gnd 2.080806f
+R25 24 25 2.224404
+C29 26 gnd 2.080806f
+R26 25 26 2.224404
+C30 27 gnd 2.080806f
+R27 26 27 2.224404
+C31 28 gnd 2.080806f
+R28 27 28 2.224404
+C32 29 gnd 2.080806f
+R29 28 29 2.224404
+C33 30 gnd 2.080806f
+R30 29 30 2.224404
+C34 31 gnd 2.080806f
+R31 30 31 2.224404
+C35 32 gnd 2.080806f
+R32 31 32 2.224404
+C36 33 gnd 2.080806f
+R33 32 33 2.224404
+C37 34 gnd 2.080806f
+R34 33 34 2.224404
+C38 35 gnd 2.080806f
+R35 34 35 2.224404
+C39 36 gnd 2.080806f
+R36 36 35 2.224404
+C40 37 gnd 2.080806f
+R37 36 37 2.224404
+C41 38 gnd 2.080806f
+R38 37 38 2.224404
+C42 39 gnd 2.080806f
+R39 39 38 2.224404
+C43 40 gnd 2.080806f
+R40 39 40 2.224404
+C44 41 gnd 2.080806f
+R41 41 40 2.224404
+C45 42 gnd 2.080806f
+R42 42 41 2.224404
+C46 43 gnd 2.080806f
+R43 42 43 2.224404
+C47 44 gnd 2.080806f
+R44 44 43 2.224404
+C48 45 gnd 2.080806f
+R45 44 45 2.224404
+R46 45 g198_2 2.224404
+C49 46 gnd 2.080806f
+R47 40 46 2.224404
+C50 47 gnd 2.080806f
+R48 46 47 2.224404
+C51 48 gnd 2.080806f
+R49 47 48 2.224404
+C52 49 gnd 2.080806f
+R50 48 49 2.224404
+C53 50 gnd 2.080806f
+R51 49 50 2.224404
+C54 51 gnd 2.080806f
+R52 50 51 2.224404
+C55 52 gnd 2.080806f
+R53 51 52 2.224404
+C56 53 gnd 2.080806f
+R54 52 53 2.224404
+C57 54 gnd 2.080806f
+R55 53 54 2.224404
+C58 55 gnd 2.080806f
+R56 54 55 2.224404
+C59 56 gnd 2.080806f
+R57 55 56 2.224404
+C60 57 gnd 2.080806f
+R58 56 57 2.224404
+C61 58 gnd 2.080806f
+R59 57 58 2.224404
+C62 59 gnd 2.080806f
+R60 58 59 2.224404
+C63 60 gnd 2.080806f
+R61 59 60 2.224404
+C64 61 gnd 2.080806f
+R62 60 61 2.224404
+C65 62 gnd 2.080806f
+R63 61 62 2.224404
+C66 63 gnd 2.080806f
+R64 62 63 2.224404
+C67 64 gnd 2.080806f
+R65 63 64 2.224404
+C68 65 gnd 2.080806f
+R66 64 65 2.224404
+C69 66 gnd 2.080806f
+R67 65 66 2.224404
+C70 67 gnd 2.080806f
+R68 66 67 2.224404
+C71 68 gnd 2.080806f
+R69 67 68 2.224404
+C72 69 gnd 2.080806f
+R70 68 69 2.224404
+C73 70 gnd 2.080806f
+R71 69 70 2.224404
+C74 71 gnd 2.080806f
+R72 70 71 2.224404
+C75 72 gnd 2.080806f
+R73 71 72 2.224404
+C76 73 gnd 2.080806f
+R74 72 73 2.224404
+C77 74 gnd 2.080806f
+R75 73 74 2.224404
+C78 75 gnd 2.080806f
+R76 74 75 2.224404
+C79 76 gnd 2.080806f
+R77 75 76 2.224404
+C80 77 gnd 2.080806f
+R78 76 77 2.224404
+C81 78 gnd 2.080806f
+R79 77 78 2.224404
+C82 79 gnd 2.080806f
+R80 78 79 2.224404
+C83 80 gnd 2.080806f
+R81 79 80 2.224404
+C84 81 gnd 2.080806f
+R82 80 81 2.224404
+C85 82 gnd 2.080806f
+R83 81 82 2.224404
+C86 83 gnd 2.080806f
+R84 82 83 2.224404
+C87 84 gnd 2.080806f
+R85 83 84 2.224404
+C88 85 gnd 2.080806f
+R86 84 85 2.224404
+C89 86 gnd 2.080806f
+R87 85 86 2.224404
+C90 87 gnd 2.080806f
+R88 86 87 2.224404
+C91 88 gnd 2.080806f
+R89 87 88 2.224404
+C92 89 gnd 2.080806f
+R90 88 89 2.224404
+C93 90 gnd 2.080806f
+R91 89 90 2.224404
+C94 91 gnd 2.080806f
+R92 90 91 2.224404
+C95 92 gnd 2.080806f
+R93 91 92 2.224404
+C96 93 gnd 2.080806f
+R94 92 93 2.224404
+C97 94 gnd 2.080806f
+R95 93 94 2.224404
+C98 95 gnd 2.080806f
+R96 94 95 2.224404
+C99 96 gnd 2.080806f
+R97 95 96 2.224404
+C100 97 gnd 2.080806f
+R98 96 97 2.224404
+C101 98 gnd 2.080806f
+R99 97 98 2.224404
+C102 99 gnd 2.080806f
+R100 98 99 2.224404
+C103 100 gnd 2.080806f
+R101 99 100 2.224404
+C104 101 gnd 2.080806f
+R102 100 101 2.224404
+C105 102 gnd 2.080806f
+R103 101 102 2.224404
+C106 103 gnd 2.080806f
+R104 102 103 2.224404
+C107 104 gnd 2.080806f
+R105 103 104 2.224404
+C108 105 gnd 2.080806f
+R106 104 105 2.224404
+R107 105 g198_1 2.224404
+.ends
+
+.subckt netg7 g7_2 g7_0 g7_1 gnd
+C1  g7_2 gnd 2.080806f
+C2  g7_0 gnd 2.080806f
+C3  g7_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g7_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+R3 g7_2 2 2.224404
+C6 3 gnd 2.080806f
+R4 3 g7_2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 11 10 2.224404
+C15 12 gnd 2.080806f
+R13 12 11 2.224404
+C16 13 gnd 2.080806f
+R14 13 12 2.224404
+C17 14 gnd 2.080806f
+R15 14 13 2.224404
+C18 15 gnd 2.080806f
+R16 15 14 2.224404
+C19 16 gnd 2.080806f
+R17 16 15 2.224404
+C20 17 gnd 2.080806f
+R18 17 16 2.224404
+C21 18 gnd 2.080806f
+R19 18 17 2.224404
+C22 19 gnd 2.080806f
+R20 19 18 2.224404
+C23 20 gnd 2.080806f
+R21 20 19 2.224404
+C24 21 gnd 2.080806f
+R22 21 20 2.224404
+C25 22 gnd 2.080806f
+R23 22 21 2.224404
+C26 23 gnd 2.080806f
+R24 23 22 2.224404
+C27 24 gnd 2.080806f
+R25 24 23 2.224404
+C28 25 gnd 2.080806f
+R26 25 24 2.224404
+C29 26 gnd 2.080806f
+R27 26 25 2.224404
+C30 27 gnd 2.080806f
+R28 27 26 2.224404
+C31 28 gnd 2.080806f
+R29 28 27 2.224404
+C32 29 gnd 2.080806f
+R30 29 28 2.224404
+C33 30 gnd 2.080806f
+R31 30 29 2.224404
+C34 31 gnd 2.080806f
+R32 31 30 2.224404
+C35 32 gnd 2.080806f
+R33 32 31 2.224404
+C36 33 gnd 2.080806f
+R34 33 32 2.224404
+C37 34 gnd 2.080806f
+R35 34 33 2.224404
+C38 35 gnd 2.080806f
+R36 35 34 2.224404
+C39 36 gnd 2.080806f
+R37 36 35 2.224404
+C40 37 gnd 2.080806f
+R38 37 36 2.224404
+C41 38 gnd 2.080806f
+R39 38 37 2.224404
+C42 39 gnd 2.080806f
+R40 39 38 2.224404
+C43 40 gnd 2.080806f
+R41 40 39 2.224404
+C44 41 gnd 2.080806f
+R42 41 40 2.224404
+C45 42 gnd 2.080806f
+R43 42 41 2.224404
+C46 43 gnd 2.080806f
+R44 43 42 2.224404
+C47 44 gnd 2.080806f
+R45 44 43 2.224404
+C48 45 gnd 2.080806f
+R46 45 44 2.224404
+C49 46 gnd 2.080806f
+R47 46 45 2.224404
+C50 47 gnd 2.080806f
+R48 47 46 2.224404
+C51 48 gnd 2.080806f
+R49 48 47 2.224404
+C52 49 gnd 2.080806f
+R50 49 48 2.224404
+C53 50 gnd 2.080806f
+R51 50 49 2.224404
+C54 51 gnd 2.080806f
+R52 51 50 2.224404
+C55 52 gnd 2.080806f
+R53 51 52 2.224404
+C56 53 gnd 2.080806f
+R54 53 52 2.224404
+C57 54 gnd 2.080806f
+R55 54 53 2.224404
+C58 55 gnd 2.080806f
+R56 55 54 2.224404
+C59 56 gnd 2.080806f
+R57 56 55 2.224404
+C60 57 gnd 2.080806f
+R58 57 56 2.224404
+C61 58 gnd 2.080806f
+R59 58 57 2.224404
+C62 59 gnd 2.080806f
+R60 59 58 2.224404
+C63 60 gnd 2.080806f
+R61 60 59 2.224404
+C64 61 gnd 2.080806f
+R62 61 60 2.224404
+C65 62 gnd 2.080806f
+R63 62 61 2.224404
+C66 63 gnd 2.080806f
+R64 63 62 2.224404
+C67 64 gnd 2.080806f
+R65 64 63 2.224404
+C68 65 gnd 2.080806f
+R66 65 64 2.224404
+C69 66 gnd 2.080806f
+R67 66 65 2.224404
+C70 67 gnd 2.080806f
+R68 67 66 2.224404
+C71 68 gnd 2.080806f
+R69 68 67 2.224404
+C72 69 gnd 2.080806f
+R70 69 68 2.224404
+C73 70 gnd 2.080806f
+R71 70 69 2.224404
+C74 71 gnd 2.080806f
+R72 71 70 2.224404
+C75 72 gnd 2.080806f
+R73 72 71 2.224404
+C76 73 gnd 2.080806f
+R74 73 72 2.224404
+C77 74 gnd 2.080806f
+R75 74 73 2.224404
+C78 75 gnd 2.080806f
+R76 75 74 2.224404
+C79 76 gnd 2.080806f
+R77 76 75 2.224404
+C80 77 gnd 2.080806f
+R78 77 76 2.224404
+C81 78 gnd 2.080806f
+R79 78 77 2.224404
+C82 79 gnd 2.080806f
+R80 79 78 2.224404
+C83 80 gnd 2.080806f
+R81 80 79 2.224404
+C84 81 gnd 2.080806f
+R82 81 80 2.224404
+C85 82 gnd 2.080806f
+R83 82 81 2.224404
+C86 83 gnd 2.080806f
+R84 83 82 2.224404
+C87 84 gnd 2.080806f
+R85 84 83 2.224404
+C88 85 gnd 2.080806f
+R86 85 84 2.224404
+C89 86 gnd 2.080806f
+R87 86 85 2.224404
+C90 87 gnd 2.080806f
+R88 87 86 2.224404
+C91 88 gnd 2.080806f
+R89 88 87 2.224404
+C92 89 gnd 2.080806f
+R90 89 88 2.224404
+C93 90 gnd 2.080806f
+R91 90 89 2.224404
+C94 91 gnd 2.080806f
+R92 91 90 2.224404
+C95 92 gnd 2.080806f
+R93 92 91 2.224404
+R94 g7_1 92 2.224404
+.ends
+
+.subckt netg186 g186_1 g186_2 g186_0 gnd
+C1  g186_1 gnd 2.080806f
+C2  g186_2 gnd 2.080806f
+C3  g186_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g186_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+C8 5 gnd 2.080806f
+R5 4 5 2.224404
+C9 6 gnd 2.080806f
+R6 5 6 2.224404
+C10 7 gnd 2.080806f
+R7 6 7 2.224404
+C11 8 gnd 2.080806f
+R8 7 8 2.224404
+C12 9 gnd 2.080806f
+R9 8 9 2.224404
+C13 10 gnd 2.080806f
+R10 9 10 2.224404
+C14 11 gnd 2.080806f
+R11 11 10 2.224404
+C15 12 gnd 2.080806f
+R12 11 12 2.224404
+C16 13 gnd 2.080806f
+R13 12 13 2.224404
+C17 14 gnd 2.080806f
+R14 13 14 2.224404
+C18 15 gnd 2.080806f
+R15 14 15 2.224404
+C19 16 gnd 2.080806f
+R16 15 16 2.224404
+C20 17 gnd 2.080806f
+R17 16 17 2.224404
+C21 18 gnd 2.080806f
+R18 17 18 2.224404
+C22 19 gnd 2.080806f
+R19 18 19 2.224404
+C23 20 gnd 2.080806f
+R20 19 20 2.224404
+C24 21 gnd 2.080806f
+R21 21 20 2.224404
+C25 22 gnd 2.080806f
+R22 22 21 2.224404
+C26 23 gnd 2.080806f
+R23 22 23 2.224404
+C27 24 gnd 2.080806f
+R24 23 24 2.224404
+C28 25 gnd 2.080806f
+R25 25 24 2.224404
+C29 26 gnd 2.080806f
+R26 25 26 2.224404
+C30 27 gnd 2.080806f
+R27 26 27 2.224404
+C31 28 gnd 2.080806f
+R28 28 27 2.224404
+C32 29 gnd 2.080806f
+R29 28 29 2.224404
+C33 30 gnd 2.080806f
+R30 29 30 2.224404
+C34 31 gnd 2.080806f
+R31 31 30 2.224404
+C35 32 gnd 2.080806f
+R32 32 31 2.224404
+C36 33 gnd 2.080806f
+R33 33 32 2.224404
+C37 34 gnd 2.080806f
+R34 33 34 2.224404
+C38 35 gnd 2.080806f
+R35 35 34 2.224404
+C39 36 gnd 2.080806f
+R36 35 36 2.224404
+R37 36 g186_1 2.224404
+C40 37 gnd 2.080806f
+R38 g186_1 37 2.224404
+C41 38 gnd 2.080806f
+R39 37 38 2.224404
+C42 39 gnd 2.080806f
+R40 38 39 2.224404
+C43 40 gnd 2.080806f
+R41 39 40 2.224404
+C44 41 gnd 2.080806f
+R42 40 41 2.224404
+C45 42 gnd 2.080806f
+R43 41 42 2.224404
+C46 43 gnd 2.080806f
+R44 42 43 2.224404
+C47 44 gnd 2.080806f
+R45 43 44 2.224404
+C48 45 gnd 2.080806f
+R46 44 45 2.224404
+C49 46 gnd 2.080806f
+R47 45 46 2.224404
+C50 47 gnd 2.080806f
+R48 46 47 2.224404
+C51 48 gnd 2.080806f
+R49 47 48 2.224404
+C52 49 gnd 2.080806f
+R50 48 49 2.224404
+C53 50 gnd 2.080806f
+R51 49 50 2.224404
+C54 51 gnd 2.080806f
+R52 50 51 2.224404
+C55 52 gnd 2.080806f
+R53 51 52 2.224404
+C56 53 gnd 2.080806f
+R54 52 53 2.224404
+C57 54 gnd 2.080806f
+R55 53 54 2.224404
+C58 55 gnd 2.080806f
+R56 54 55 2.224404
+C59 56 gnd 2.080806f
+R57 55 56 2.224404
+C60 57 gnd 2.080806f
+R58 56 57 2.224404
+C61 58 gnd 2.080806f
+R59 57 58 2.224404
+C62 59 gnd 2.080806f
+R60 58 59 2.224404
+C63 60 gnd 2.080806f
+R61 59 60 2.224404
+C64 61 gnd 2.080806f
+R62 60 61 2.224404
+C65 62 gnd 2.080806f
+R63 61 62 2.224404
+C66 63 gnd 2.080806f
+R64 62 63 2.224404
+C67 64 gnd 2.080806f
+R65 63 64 2.224404
+C68 65 gnd 2.080806f
+R66 64 65 2.224404
+C69 66 gnd 2.080806f
+R67 65 66 2.224404
+C70 67 gnd 2.080806f
+R68 66 67 2.224404
+C71 68 gnd 2.080806f
+R69 67 68 2.224404
+C72 69 gnd 2.080806f
+R70 68 69 2.224404
+C73 70 gnd 2.080806f
+R71 69 70 2.224404
+C74 71 gnd 2.080806f
+R72 70 71 2.224404
+C75 72 gnd 2.080806f
+R73 71 72 2.224404
+C76 73 gnd 2.080806f
+R74 72 73 2.224404
+C77 74 gnd 2.080806f
+R75 73 74 2.224404
+C78 75 gnd 2.080806f
+R76 74 75 2.224404
+C79 76 gnd 2.080806f
+R77 75 76 2.224404
+C80 77 gnd 2.080806f
+R78 76 77 2.224404
+C81 78 gnd 2.080806f
+R79 77 78 2.224404
+C82 79 gnd 2.080806f
+R80 78 79 2.224404
+C83 80 gnd 2.080806f
+R81 79 80 2.224404
+C84 81 gnd 2.080806f
+R82 80 81 2.224404
+C85 82 gnd 2.080806f
+R83 81 82 2.224404
+C86 83 gnd 2.080806f
+R84 82 83 2.224404
+C87 84 gnd 2.080806f
+R85 83 84 2.224404
+C88 85 gnd 2.080806f
+R86 84 85 2.224404
+C89 86 gnd 2.080806f
+R87 85 86 2.224404
+C90 87 gnd 2.080806f
+R88 86 87 2.224404
+C91 88 gnd 2.080806f
+R89 87 88 2.224404
+C92 89 gnd 2.080806f
+R90 88 89 2.224404
+C93 90 gnd 2.080806f
+R91 89 90 2.224404
+C94 91 gnd 2.080806f
+R92 90 91 2.224404
+C95 92 gnd 2.080806f
+R93 91 92 2.224404
+C96 93 gnd 2.080806f
+R94 92 93 2.224404
+C97 94 gnd 2.080806f
+R95 93 94 2.224404
+C98 95 gnd 2.080806f
+R96 94 95 2.224404
+C99 96 gnd 2.080806f
+R97 95 96 2.224404
+C100 97 gnd 2.080806f
+R98 96 97 2.224404
+C101 98 gnd 2.080806f
+R99 97 98 2.224404
+C102 99 gnd 2.080806f
+R100 98 99 2.224404
+C103 100 gnd 2.080806f
+R101 99 100 2.224404
+C104 101 gnd 2.080806f
+R102 100 101 2.224404
+R103 101 g186_2 2.224404
+.ends
+
+.subckt netg9 g9_1 g9_2 g9_0 gnd
+C1  g9_1 gnd 2.080806f
+C2  g9_2 gnd 2.080806f
+C3  g9_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g9_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+R4 g9_1 3 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 8 7 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 10 9 2.224404
+C14 11 gnd 2.080806f
+R12 11 10 2.224404
+C15 12 gnd 2.080806f
+R13 12 11 2.224404
+C16 13 gnd 2.080806f
+R14 13 12 2.224404
+C17 14 gnd 2.080806f
+R15 14 13 2.224404
+C18 15 gnd 2.080806f
+R16 15 14 2.224404
+C19 16 gnd 2.080806f
+R17 16 15 2.224404
+C20 17 gnd 2.080806f
+R18 17 16 2.224404
+C21 18 gnd 2.080806f
+R19 18 17 2.224404
+C22 19 gnd 2.080806f
+R20 19 18 2.224404
+C23 20 gnd 2.080806f
+R21 20 19 2.224404
+C24 21 gnd 2.080806f
+R22 21 20 2.224404
+C25 22 gnd 2.080806f
+R23 22 21 2.224404
+C26 23 gnd 2.080806f
+R24 23 22 2.224404
+C27 24 gnd 2.080806f
+R25 24 23 2.224404
+C28 25 gnd 2.080806f
+R26 25 24 2.224404
+C29 26 gnd 2.080806f
+R27 26 25 2.224404
+C30 27 gnd 2.080806f
+R28 27 26 2.224404
+C31 28 gnd 2.080806f
+R29 28 27 2.224404
+C32 29 gnd 2.080806f
+R30 29 28 2.224404
+C33 30 gnd 2.080806f
+R31 30 29 2.224404
+C34 31 gnd 2.080806f
+R32 31 30 2.224404
+C35 32 gnd 2.080806f
+R33 32 31 2.224404
+C36 33 gnd 2.080806f
+R34 33 32 2.224404
+C37 34 gnd 2.080806f
+R35 34 33 2.224404
+C38 35 gnd 2.080806f
+R36 35 34 2.224404
+C39 36 gnd 2.080806f
+R37 36 35 2.224404
+C40 37 gnd 2.080806f
+R38 37 36 2.224404
+C41 38 gnd 2.080806f
+R39 38 37 2.224404
+C42 39 gnd 2.080806f
+R40 39 38 2.224404
+C43 40 gnd 2.080806f
+R41 40 39 2.224404
+C44 41 gnd 2.080806f
+R42 41 40 2.224404
+C45 42 gnd 2.080806f
+R43 42 41 2.224404
+C46 43 gnd 2.080806f
+R44 43 42 2.224404
+C47 44 gnd 2.080806f
+R45 44 43 2.224404
+C48 45 gnd 2.080806f
+R46 45 44 2.224404
+C49 46 gnd 2.080806f
+R47 46 45 2.224404
+C50 47 gnd 2.080806f
+R48 47 46 2.224404
+C51 48 gnd 2.080806f
+R49 48 47 2.224404
+C52 49 gnd 2.080806f
+R50 49 48 2.224404
+C53 50 gnd 2.080806f
+R51 50 49 2.224404
+C54 51 gnd 2.080806f
+R52 51 50 2.224404
+C55 52 gnd 2.080806f
+R53 52 51 2.224404
+C56 53 gnd 2.080806f
+R54 53 52 2.224404
+C57 54 gnd 2.080806f
+R55 54 53 2.224404
+C58 55 gnd 2.080806f
+R56 55 54 2.224404
+C59 56 gnd 2.080806f
+R57 56 55 2.224404
+C60 57 gnd 2.080806f
+R58 57 56 2.224404
+C61 58 gnd 2.080806f
+R59 58 57 2.224404
+C62 59 gnd 2.080806f
+R60 59 58 2.224404
+C63 60 gnd 2.080806f
+R61 60 59 2.224404
+C64 61 gnd 2.080806f
+R62 61 60 2.224404
+C65 62 gnd 2.080806f
+R63 62 61 2.224404
+C66 63 gnd 2.080806f
+R64 63 62 2.224404
+C67 64 gnd 2.080806f
+R65 64 63 2.224404
+C68 65 gnd 2.080806f
+R66 65 64 2.224404
+C69 66 gnd 2.080806f
+R67 66 65 2.224404
+C70 67 gnd 2.080806f
+R68 67 66 2.224404
+C71 68 gnd 2.080806f
+R69 68 67 2.224404
+C72 69 gnd 2.080806f
+R70 69 68 2.224404
+C73 70 gnd 2.080806f
+R71 70 69 2.224404
+C74 71 gnd 2.080806f
+R72 71 70 2.224404
+C75 72 gnd 2.080806f
+R73 72 71 2.224404
+C76 73 gnd 2.080806f
+R74 73 72 2.224404
+C77 74 gnd 2.080806f
+R75 74 73 2.224404
+C78 75 gnd 2.080806f
+R76 75 74 2.224404
+C79 76 gnd 2.080806f
+R77 76 75 2.224404
+C80 77 gnd 2.080806f
+R78 77 76 2.224404
+C81 78 gnd 2.080806f
+R79 78 77 2.224404
+C82 79 gnd 2.080806f
+R80 79 78 2.224404
+C83 80 gnd 2.080806f
+R81 80 79 2.224404
+C84 81 gnd 2.080806f
+R82 81 80 2.224404
+C85 82 gnd 2.080806f
+R83 82 81 2.224404
+C86 83 gnd 2.080806f
+R84 83 82 2.224404
+C87 84 gnd 2.080806f
+R85 84 83 2.224404
+C88 85 gnd 2.080806f
+R86 85 84 2.224404
+C89 86 gnd 2.080806f
+R87 86 85 2.224404
+C90 87 gnd 2.080806f
+R88 87 86 2.224404
+C91 88 gnd 2.080806f
+R89 88 87 2.224404
+C92 89 gnd 2.080806f
+R90 89 88 2.224404
+C93 90 gnd 2.080806f
+R91 90 89 2.224404
+C94 91 gnd 2.080806f
+R92 91 90 2.224404
+R93 g9_2 91 2.224404
+.ends
+
+.subckt netg196 g196_2 g196_1 g196_0 gnd
+C1  g196_2 gnd 2.080806f
+C2  g196_1 gnd 2.080806f
+C3  g196_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g196_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 6 5 2.224404
+C10 7 gnd 2.080806f
+R7 7 6 2.224404
+C11 8 gnd 2.080806f
+R8 8 7 2.224404
+C12 9 gnd 2.080806f
+R9 9 8 2.224404
+C13 10 gnd 2.080806f
+R10 10 9 2.224404
+C14 11 gnd 2.080806f
+R11 11 10 2.224404
+C15 12 gnd 2.080806f
+R12 12 11 2.224404
+C16 13 gnd 2.080806f
+R13 13 12 2.224404
+C17 14 gnd 2.080806f
+R14 14 13 2.224404
+C18 15 gnd 2.080806f
+R15 15 14 2.224404
+C19 16 gnd 2.080806f
+R16 16 15 2.224404
+C20 17 gnd 2.080806f
+R17 17 16 2.224404
+C21 18 gnd 2.080806f
+R18 17 18 2.224404
+C22 19 gnd 2.080806f
+R19 19 18 2.224404
+C23 20 gnd 2.080806f
+R20 20 19 2.224404
+C24 21 gnd 2.080806f
+R21 21 20 2.224404
+C25 22 gnd 2.080806f
+R22 22 21 2.224404
+C26 23 gnd 2.080806f
+R23 23 22 2.224404
+C27 24 gnd 2.080806f
+R24 24 23 2.224404
+C28 25 gnd 2.080806f
+R25 25 24 2.224404
+C29 26 gnd 2.080806f
+R26 26 25 2.224404
+C30 27 gnd 2.080806f
+R27 27 26 2.224404
+C31 28 gnd 2.080806f
+R28 28 27 2.224404
+C32 29 gnd 2.080806f
+R29 29 28 2.224404
+C33 30 gnd 2.080806f
+R30 30 29 2.224404
+C34 31 gnd 2.080806f
+R31 31 30 2.224404
+C35 32 gnd 2.080806f
+R32 32 31 2.224404
+C36 33 gnd 2.080806f
+R33 33 32 2.224404
+C37 34 gnd 2.080806f
+R34 34 33 2.224404
+C38 35 gnd 2.080806f
+R35 35 34 2.224404
+C39 36 gnd 2.080806f
+R36 36 35 2.224404
+C40 37 gnd 2.080806f
+R37 37 36 2.224404
+C41 38 gnd 2.080806f
+R38 38 37 2.224404
+C42 39 gnd 2.080806f
+R39 39 38 2.224404
+C43 40 gnd 2.080806f
+R40 40 39 2.224404
+C44 41 gnd 2.080806f
+R41 41 40 2.224404
+C45 42 gnd 2.080806f
+R42 42 41 2.224404
+C46 43 gnd 2.080806f
+R43 43 42 2.224404
+C47 44 gnd 2.080806f
+R44 44 43 2.224404
+C48 45 gnd 2.080806f
+R45 45 44 2.224404
+C49 46 gnd 2.080806f
+R46 45 46 2.224404
+C50 47 gnd 2.080806f
+R47 47 46 2.224404
+C51 48 gnd 2.080806f
+R48 48 47 2.224404
+C52 49 gnd 2.080806f
+R49 49 48 2.224404
+C53 50 gnd 2.080806f
+R50 50 49 2.224404
+C54 51 gnd 2.080806f
+R51 51 50 2.224404
+C55 52 gnd 2.080806f
+R52 52 51 2.224404
+C56 53 gnd 2.080806f
+R53 53 52 2.224404
+C57 54 gnd 2.080806f
+R54 54 53 2.224404
+C58 55 gnd 2.080806f
+R55 55 54 2.224404
+C59 56 gnd 2.080806f
+R56 56 55 2.224404
+C60 57 gnd 2.080806f
+R57 57 56 2.224404
+C61 58 gnd 2.080806f
+R58 58 57 2.224404
+C62 59 gnd 2.080806f
+R59 59 58 2.224404
+C63 60 gnd 2.080806f
+R60 60 59 2.224404
+C64 61 gnd 2.080806f
+R61 61 60 2.224404
+C65 62 gnd 2.080806f
+R62 62 61 2.224404
+C66 63 gnd 2.080806f
+R63 62 63 2.224404
+C67 64 gnd 2.080806f
+R64 64 63 2.224404
+R65 64 g196_2 2.224404
+C68 65 gnd 2.080806f
+R66 65 61 2.224404
+C69 66 gnd 2.080806f
+R67 65 66 2.224404
+C70 67 gnd 2.080806f
+R68 66 67 2.224404
+C71 68 gnd 2.080806f
+R69 68 67 2.224404
+C72 69 gnd 2.080806f
+R70 69 68 2.224404
+C73 70 gnd 2.080806f
+R71 70 69 2.224404
+C74 71 gnd 2.080806f
+R72 71 70 2.224404
+C75 72 gnd 2.080806f
+R73 72 71 2.224404
+C76 73 gnd 2.080806f
+R74 73 72 2.224404
+C77 74 gnd 2.080806f
+R75 74 73 2.224404
+C78 75 gnd 2.080806f
+R76 75 74 2.224404
+C79 76 gnd 2.080806f
+R77 76 75 2.224404
+C80 77 gnd 2.080806f
+R78 77 76 2.224404
+C81 78 gnd 2.080806f
+R79 77 78 2.224404
+C82 79 gnd 2.080806f
+R80 79 78 2.224404
+C83 80 gnd 2.080806f
+R81 80 79 2.224404
+C84 81 gnd 2.080806f
+R82 81 80 2.224404
+C85 82 gnd 2.080806f
+R83 82 81 2.224404
+C86 83 gnd 2.080806f
+R84 83 82 2.224404
+C87 84 gnd 2.080806f
+R85 84 83 2.224404
+C88 85 gnd 2.080806f
+R86 84 85 2.224404
+C89 86 gnd 2.080806f
+R87 86 85 2.224404
+C90 87 gnd 2.080806f
+R88 87 86 2.224404
+C91 88 gnd 2.080806f
+R89 87 88 2.224404
+C92 89 gnd 2.080806f
+R90 89 88 2.224404
+C93 90 gnd 2.080806f
+R91 90 89 2.224404
+C94 91 gnd 2.080806f
+R92 90 91 2.224404
+C95 92 gnd 2.080806f
+R93 91 92 2.224404
+C96 93 gnd 2.080806f
+R94 92 93 2.224404
+C97 94 gnd 2.080806f
+R95 93 94 2.224404
+C98 95 gnd 2.080806f
+R96 95 94 2.224404
+C99 96 gnd 2.080806f
+R97 96 95 2.224404
+C100 97 gnd 2.080806f
+R98 97 96 2.224404
+C101 98 gnd 2.080806f
+R99 97 98 2.224404
+C102 99 gnd 2.080806f
+R100 99 98 2.224404
+C103 100 gnd 2.080806f
+R101 100 99 2.224404
+C104 101 gnd 2.080806f
+R102 100 101 2.224404
+C105 102 gnd 2.080806f
+R103 101 102 2.224404
+C106 103 gnd 2.080806f
+R104 103 102 2.224404
+C107 104 gnd 2.080806f
+R105 104 103 2.224404
+C108 105 gnd 2.080806f
+R106 104 105 2.224404
+C109 106 gnd 2.080806f
+R107 106 105 2.224404
+C110 107 gnd 2.080806f
+R108 106 107 2.224404
+C111 108 gnd 2.080806f
+R109 107 108 2.224404
+R110 g196_1 108 2.224404
+.ends
+
+.subckt netg206 g206_10 g206_5 g206_8 g206_7 g206_4 g206_14 g206_3 g206_1 g206_6 g206_13 g206_12 g206_2 g206_0 g206_11 g206_9 gnd
+C1  g206_10 gnd 2.080806f
+C2  g206_5 gnd 2.080806f
+C3  g206_8 gnd 2.080806f
+C4  g206_7 gnd 2.080806f
+C5  g206_4 gnd 2.080806f
+C6  g206_14 gnd 2.080806f
+C7  g206_3 gnd 2.080806f
+C8  g206_1 gnd 2.080806f
+C9  g206_6 gnd 2.080806f
+C10  g206_13 gnd 2.080806f
+C11  g206_12 gnd 2.080806f
+C12  g206_2 gnd 2.080806f
+C13  g206_0 gnd 2.080806f
+C14  g206_11 gnd 2.080806f
+C15  g206_9 gnd 2.080806f
+C16 1 gnd 2.080806f
+R1 g206_0 1 2.224404
+R2 1 g206_4 2.224404
+R3 g206_4 g206_8 2.224404
+C17 2 gnd 2.080806f
+R4 g206_8 2 2.224404
+C18 3 gnd 2.080806f
+R5 2 3 2.224404
+C19 4 gnd 2.080806f
+R6 3 4 2.224404
+C20 5 gnd 2.080806f
+R7 4 5 2.224404
+C21 6 gnd 2.080806f
+R8 5 6 2.224404
+C22 7 gnd 2.080806f
+R9 6 7 2.224404
+C23 8 gnd 2.080806f
+R10 7 8 2.224404
+R11 8 g206_5 2.224404
+R12 g206_5 g206_12 2.224404
+R13 g206_11 g206_12 2.224404
+C24 9 gnd 2.080806f
+R14 g206_12 9 2.224404
+C25 10 gnd 2.080806f
+R15 9 10 2.224404
+C26 11 gnd 2.080806f
+R16 10 11 2.224404
+C27 12 gnd 2.080806f
+R17 11 12 2.224404
+C28 13 gnd 2.080806f
+R18 12 13 2.224404
+R19 13 g206_2 2.224404
+C29 14 gnd 2.080806f
+R20 14 g206_5 2.224404
+C30 15 gnd 2.080806f
+R21 14 15 2.224404
+C31 16 gnd 2.080806f
+R22 15 16 2.224404
+C32 17 gnd 2.080806f
+R23 17 16 2.224404
+C33 18 gnd 2.080806f
+R24 17 18 2.224404
+C34 19 gnd 2.080806f
+R25 18 19 2.224404
+R26 19 g206_13 2.224404
+C35 20 gnd 2.080806f
+R27 20 g206_13 2.224404
+C36 21 gnd 2.080806f
+R28 20 21 2.224404
+C37 22 gnd 2.080806f
+R29 21 22 2.224404
+C38 23 gnd 2.080806f
+R30 22 23 2.224404
+C39 24 gnd 2.080806f
+R31 23 24 2.224404
+R32 24 g206_1 2.224404
+C40 25 gnd 2.080806f
+R33 13 25 2.224404
+C41 26 gnd 2.080806f
+R34 25 26 2.224404
+C42 27 gnd 2.080806f
+R35 26 27 2.224404
+C43 28 gnd 2.080806f
+R36 27 28 2.224404
+C44 29 gnd 2.080806f
+R37 28 29 2.224404
+C45 30 gnd 2.080806f
+R38 29 30 2.224404
+R39 30 g206_9 2.224404
+C46 31 gnd 2.080806f
+R40 g206_1 31 2.224404
+C47 32 gnd 2.080806f
+R41 31 32 2.224404
+C48 33 gnd 2.080806f
+R42 32 33 2.224404
+C49 34 gnd 2.080806f
+R43 33 34 2.224404
+C50 35 gnd 2.080806f
+R44 34 35 2.224404
+C51 36 gnd 2.080806f
+R45 35 36 2.224404
+C52 37 gnd 2.080806f
+R46 36 37 2.224404
+C53 38 gnd 2.080806f
+R47 37 38 2.224404
+C54 39 gnd 2.080806f
+R48 38 39 2.224404
+C55 40 gnd 2.080806f
+R49 39 40 2.224404
+C56 41 gnd 2.080806f
+R50 40 41 2.224404
+C57 42 gnd 2.080806f
+R51 41 42 2.224404
+C58 43 gnd 2.080806f
+R52 42 43 2.224404
+C59 44 gnd 2.080806f
+R53 43 44 2.224404
+C60 45 gnd 2.080806f
+R54 44 45 2.224404
+C61 46 gnd 2.080806f
+R55 45 46 2.224404
+C62 47 gnd 2.080806f
+R56 46 47 2.224404
+C63 48 gnd 2.080806f
+R57 47 48 2.224404
+C64 49 gnd 2.080806f
+R58 48 49 2.224404
+C65 50 gnd 2.080806f
+R59 49 50 2.224404
+C66 51 gnd 2.080806f
+R60 50 51 2.224404
+R61 51 g206_14 2.224404
+C67 52 gnd 2.080806f
+R62 g206_14 52 2.224404
+C68 53 gnd 2.080806f
+R63 52 53 2.224404
+R64 53 g206_3 2.224404
+R65 g206_3 g206_10 2.224404
+R66 g206_10 g206_7 2.224404
+C69 54 gnd 2.080806f
+R67 54 g206_14 2.224404
+C70 55 gnd 2.080806f
+R68 54 55 2.224404
+C71 56 gnd 2.080806f
+R69 55 56 2.224404
+C72 57 gnd 2.080806f
+R70 56 57 2.224404
+C73 58 gnd 2.080806f
+R71 57 58 2.224404
+C74 59 gnd 2.080806f
+R72 58 59 2.224404
+C75 60 gnd 2.080806f
+R73 59 60 2.224404
+C76 61 gnd 2.080806f
+R74 60 61 2.224404
+C77 62 gnd 2.080806f
+R75 61 62 2.224404
+C78 63 gnd 2.080806f
+R76 62 63 2.224404
+C79 64 gnd 2.080806f
+R77 63 64 2.224404
+C80 65 gnd 2.080806f
+R78 64 65 2.224404
+C81 66 gnd 2.080806f
+R79 65 66 2.224404
+C82 67 gnd 2.080806f
+R80 66 67 2.224404
+C83 68 gnd 2.080806f
+R81 67 68 2.224404
+C84 69 gnd 2.080806f
+R82 68 69 2.224404
+C85 70 gnd 2.080806f
+R83 69 70 2.224404
+C86 71 gnd 2.080806f
+R84 71 70 2.224404
+C87 72 gnd 2.080806f
+R85 72 71 2.224404
+C88 73 gnd 2.080806f
+R86 72 73 2.224404
+C89 74 gnd 2.080806f
+R87 73 74 2.224404
+C90 75 gnd 2.080806f
+R88 74 75 2.224404
+C91 76 gnd 2.080806f
+R89 75 76 2.224404
+C92 77 gnd 2.080806f
+R90 76 77 2.224404
+C93 78 gnd 2.080806f
+R91 77 78 2.224404
+C94 79 gnd 2.080806f
+R92 78 79 2.224404
+C95 80 gnd 2.080806f
+R93 79 80 2.224404
+C96 81 gnd 2.080806f
+R94 80 81 2.224404
+C97 82 gnd 2.080806f
+R95 81 82 2.224404
+C98 83 gnd 2.080806f
+R96 82 83 2.224404
+C99 84 gnd 2.080806f
+R97 83 84 2.224404
+C100 85 gnd 2.080806f
+R98 84 85 2.224404
+C101 86 gnd 2.080806f
+R99 85 86 2.224404
+C102 87 gnd 2.080806f
+R100 86 87 2.224404
+C103 88 gnd 2.080806f
+R101 87 88 2.224404
+C104 89 gnd 2.080806f
+R102 89 88 2.224404
+C105 90 gnd 2.080806f
+R103 90 89 2.224404
+C106 91 gnd 2.080806f
+R104 90 91 2.224404
+C107 92 gnd 2.080806f
+R105 91 92 2.224404
+C108 93 gnd 2.080806f
+R106 92 93 2.224404
+C109 94 gnd 2.080806f
+R107 93 94 2.224404
+C110 95 gnd 2.080806f
+R108 94 95 2.224404
+C111 96 gnd 2.080806f
+R109 95 96 2.224404
+C112 97 gnd 2.080806f
+R110 96 97 2.224404
+C113 98 gnd 2.080806f
+R111 97 98 2.224404
+C114 99 gnd 2.080806f
+R112 98 99 2.224404
+C115 100 gnd 2.080806f
+R113 99 100 2.224404
+C116 101 gnd 2.080806f
+R114 100 101 2.224404
+C117 102 gnd 2.080806f
+R115 101 102 2.224404
+C118 103 gnd 2.080806f
+R116 102 103 2.224404
+C119 104 gnd 2.080806f
+R117 103 104 2.224404
+C120 105 gnd 2.080806f
+R118 104 105 2.224404
+C121 106 gnd 2.080806f
+R119 105 106 2.224404
+C122 107 gnd 2.080806f
+R120 106 107 2.224404
+C123 108 gnd 2.080806f
+R121 108 107 2.224404
+R122 g206_6 108 2.224404
+.ends
+
+.subckt netg16 g16_1 g16_2 g16_0 gnd
+C1  g16_1 gnd 2.080806f
+C2  g16_2 gnd 2.080806f
+C3  g16_0 gnd 2.080806f
+R1 g16_0 g16_2 2.224404
+C4 1 gnd 2.080806f
+R2 1 g16_0 2.224404
+C5 2 gnd 2.080806f
+R3 2 1 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 4 3 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 6 5 2.224404
+C10 7 gnd 2.080806f
+R8 6 7 2.224404
+C11 8 gnd 2.080806f
+R9 7 8 2.224404
+C12 9 gnd 2.080806f
+R10 8 9 2.224404
+C13 10 gnd 2.080806f
+R11 9 10 2.224404
+C14 11 gnd 2.080806f
+R12 10 11 2.224404
+C15 12 gnd 2.080806f
+R13 12 11 2.224404
+C16 13 gnd 2.080806f
+R14 13 12 2.224404
+C17 14 gnd 2.080806f
+R15 14 13 2.224404
+C18 15 gnd 2.080806f
+R16 15 14 2.224404
+C19 16 gnd 2.080806f
+R17 16 15 2.224404
+C20 17 gnd 2.080806f
+R18 16 17 2.224404
+C21 18 gnd 2.080806f
+R19 18 17 2.224404
+C22 19 gnd 2.080806f
+R20 19 18 2.224404
+C23 20 gnd 2.080806f
+R21 20 19 2.224404
+C24 21 gnd 2.080806f
+R22 21 20 2.224404
+C25 22 gnd 2.080806f
+R23 22 21 2.224404
+C26 23 gnd 2.080806f
+R24 23 22 2.224404
+C27 24 gnd 2.080806f
+R25 24 23 2.224404
+C28 25 gnd 2.080806f
+R26 25 24 2.224404
+C29 26 gnd 2.080806f
+R27 26 25 2.224404
+C30 27 gnd 2.080806f
+R28 27 26 2.224404
+C31 28 gnd 2.080806f
+R29 28 27 2.224404
+C32 29 gnd 2.080806f
+R30 29 28 2.224404
+C33 30 gnd 2.080806f
+R31 30 29 2.224404
+C34 31 gnd 2.080806f
+R32 31 30 2.224404
+C35 32 gnd 2.080806f
+R33 32 31 2.224404
+C36 33 gnd 2.080806f
+R34 33 32 2.224404
+C37 34 gnd 2.080806f
+R35 34 33 2.224404
+C38 35 gnd 2.080806f
+R36 35 34 2.224404
+C39 36 gnd 2.080806f
+R37 36 35 2.224404
+C40 37 gnd 2.080806f
+R38 37 36 2.224404
+C41 38 gnd 2.080806f
+R39 38 37 2.224404
+C42 39 gnd 2.080806f
+R40 39 38 2.224404
+C43 40 gnd 2.080806f
+R41 40 39 2.224404
+C44 41 gnd 2.080806f
+R42 41 40 2.224404
+C45 42 gnd 2.080806f
+R43 42 41 2.224404
+C46 43 gnd 2.080806f
+R44 43 42 2.224404
+C47 44 gnd 2.080806f
+R45 44 43 2.224404
+C48 45 gnd 2.080806f
+R46 45 44 2.224404
+C49 46 gnd 2.080806f
+R47 46 45 2.224404
+C50 47 gnd 2.080806f
+R48 47 46 2.224404
+C51 48 gnd 2.080806f
+R49 48 47 2.224404
+C52 49 gnd 2.080806f
+R50 49 48 2.224404
+C53 50 gnd 2.080806f
+R51 50 49 2.224404
+C54 51 gnd 2.080806f
+R52 50 51 2.224404
+C55 52 gnd 2.080806f
+R53 52 51 2.224404
+C56 53 gnd 2.080806f
+R54 53 52 2.224404
+C57 54 gnd 2.080806f
+R55 54 53 2.224404
+C58 55 gnd 2.080806f
+R56 55 54 2.224404
+C59 56 gnd 2.080806f
+R57 56 55 2.224404
+C60 57 gnd 2.080806f
+R58 57 56 2.224404
+C61 58 gnd 2.080806f
+R59 58 57 2.224404
+C62 59 gnd 2.080806f
+R60 59 58 2.224404
+C63 60 gnd 2.080806f
+R61 60 59 2.224404
+C64 61 gnd 2.080806f
+R62 61 60 2.224404
+C65 62 gnd 2.080806f
+R63 62 61 2.224404
+C66 63 gnd 2.080806f
+R64 63 62 2.224404
+C67 64 gnd 2.080806f
+R65 64 63 2.224404
+C68 65 gnd 2.080806f
+R66 65 64 2.224404
+C69 66 gnd 2.080806f
+R67 66 65 2.224404
+C70 67 gnd 2.080806f
+R68 67 66 2.224404
+C71 68 gnd 2.080806f
+R69 68 67 2.224404
+C72 69 gnd 2.080806f
+R70 69 68 2.224404
+C73 70 gnd 2.080806f
+R71 70 69 2.224404
+C74 71 gnd 2.080806f
+R72 71 70 2.224404
+C75 72 gnd 2.080806f
+R73 72 71 2.224404
+C76 73 gnd 2.080806f
+R74 73 72 2.224404
+C77 74 gnd 2.080806f
+R75 74 73 2.224404
+C78 75 gnd 2.080806f
+R76 75 74 2.224404
+C79 76 gnd 2.080806f
+R77 76 75 2.224404
+C80 77 gnd 2.080806f
+R78 77 76 2.224404
+C81 78 gnd 2.080806f
+R79 78 77 2.224404
+C82 79 gnd 2.080806f
+R80 79 78 2.224404
+C83 80 gnd 2.080806f
+R81 80 79 2.224404
+C84 81 gnd 2.080806f
+R82 81 80 2.224404
+C85 82 gnd 2.080806f
+R83 82 81 2.224404
+C86 83 gnd 2.080806f
+R84 83 82 2.224404
+C87 84 gnd 2.080806f
+R85 84 83 2.224404
+C88 85 gnd 2.080806f
+R86 85 84 2.224404
+C89 86 gnd 2.080806f
+R87 86 85 2.224404
+C90 87 gnd 2.080806f
+R88 87 86 2.224404
+C91 88 gnd 2.080806f
+R89 88 87 2.224404
+C92 89 gnd 2.080806f
+R90 89 88 2.224404
+C93 90 gnd 2.080806f
+R91 90 89 2.224404
+C94 91 gnd 2.080806f
+R92 91 90 2.224404
+C95 92 gnd 2.080806f
+R93 92 91 2.224404
+C96 93 gnd 2.080806f
+R94 93 92 2.224404
+C97 94 gnd 2.080806f
+R95 94 93 2.224404
+C98 95 gnd 2.080806f
+R96 95 94 2.224404
+C99 96 gnd 2.080806f
+R97 96 95 2.224404
+C100 97 gnd 2.080806f
+R98 97 96 2.224404
+C101 98 gnd 2.080806f
+R99 98 97 2.224404
+C102 99 gnd 2.080806f
+R100 99 98 2.224404
+C103 100 gnd 2.080806f
+R101 100 99 2.224404
+C104 101 gnd 2.080806f
+R102 101 100 2.224404
+C105 102 gnd 2.080806f
+R103 102 101 2.224404
+C106 103 gnd 2.080806f
+R104 103 102 2.224404
+C107 104 gnd 2.080806f
+R105 104 103 2.224404
+C108 105 gnd 2.080806f
+R106 105 104 2.224404
+C109 106 gnd 2.080806f
+R107 106 105 2.224404
+R108 g16_1 106 2.224404
+.ends
+
+.subckt netg177 g177_1 g177_0 g177_2 gnd
+C1  g177_1 gnd 2.080806f
+C2  g177_0 gnd 2.080806f
+C3  g177_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g177_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 5 6 2.224404
+C10 7 gnd 2.080806f
+R7 6 7 2.224404
+C11 8 gnd 2.080806f
+R8 7 8 2.224404
+C12 9 gnd 2.080806f
+R9 8 9 2.224404
+C13 10 gnd 2.080806f
+R10 9 10 2.224404
+C14 11 gnd 2.080806f
+R11 10 11 2.224404
+C15 12 gnd 2.080806f
+R12 11 12 2.224404
+C16 13 gnd 2.080806f
+R13 12 13 2.224404
+C17 14 gnd 2.080806f
+R14 13 14 2.224404
+C18 15 gnd 2.080806f
+R15 15 14 2.224404
+C19 16 gnd 2.080806f
+R16 15 16 2.224404
+C20 17 gnd 2.080806f
+R17 17 16 2.224404
+C21 18 gnd 2.080806f
+R18 17 18 2.224404
+C22 19 gnd 2.080806f
+R19 19 18 2.224404
+C23 20 gnd 2.080806f
+R20 20 19 2.224404
+C24 21 gnd 2.080806f
+R21 21 20 2.224404
+C25 22 gnd 2.080806f
+R22 21 22 2.224404
+C26 23 gnd 2.080806f
+R23 22 23 2.224404
+C27 24 gnd 2.080806f
+R24 23 24 2.224404
+C28 25 gnd 2.080806f
+R25 24 25 2.224404
+C29 26 gnd 2.080806f
+R26 25 26 2.224404
+C30 27 gnd 2.080806f
+R27 26 27 2.224404
+C31 28 gnd 2.080806f
+R28 27 28 2.224404
+C32 29 gnd 2.080806f
+R29 28 29 2.224404
+C33 30 gnd 2.080806f
+R30 29 30 2.224404
+C34 31 gnd 2.080806f
+R31 30 31 2.224404
+C35 32 gnd 2.080806f
+R32 31 32 2.224404
+C36 33 gnd 2.080806f
+R33 32 33 2.224404
+C37 34 gnd 2.080806f
+R34 33 34 2.224404
+C38 35 gnd 2.080806f
+R35 34 35 2.224404
+C39 36 gnd 2.080806f
+R36 35 36 2.224404
+C40 37 gnd 2.080806f
+R37 36 37 2.224404
+C41 38 gnd 2.080806f
+R38 37 38 2.224404
+C42 39 gnd 2.080806f
+R39 38 39 2.224404
+C43 40 gnd 2.080806f
+R40 40 39 2.224404
+C44 41 gnd 2.080806f
+R41 40 41 2.224404
+C45 42 gnd 2.080806f
+R42 41 42 2.224404
+C46 43 gnd 2.080806f
+R43 42 43 2.224404
+C47 44 gnd 2.080806f
+R44 43 44 2.224404
+C48 45 gnd 2.080806f
+R45 44 45 2.224404
+C49 46 gnd 2.080806f
+R46 45 46 2.224404
+C50 47 gnd 2.080806f
+R47 47 46 2.224404
+C51 48 gnd 2.080806f
+R48 47 48 2.224404
+R49 g177_1 48 2.224404
+C52 49 gnd 2.080806f
+R50 48 49 2.224404
+C53 50 gnd 2.080806f
+R51 49 50 2.224404
+C54 51 gnd 2.080806f
+R52 50 51 2.224404
+C55 52 gnd 2.080806f
+R53 51 52 2.224404
+C56 53 gnd 2.080806f
+R54 52 53 2.224404
+C57 54 gnd 2.080806f
+R55 53 54 2.224404
+C58 55 gnd 2.080806f
+R56 54 55 2.224404
+C59 56 gnd 2.080806f
+R57 55 56 2.224404
+C60 57 gnd 2.080806f
+R58 56 57 2.224404
+C61 58 gnd 2.080806f
+R59 57 58 2.224404
+C62 59 gnd 2.080806f
+R60 58 59 2.224404
+C63 60 gnd 2.080806f
+R61 59 60 2.224404
+C64 61 gnd 2.080806f
+R62 60 61 2.224404
+C65 62 gnd 2.080806f
+R63 61 62 2.224404
+C66 63 gnd 2.080806f
+R64 62 63 2.224404
+C67 64 gnd 2.080806f
+R65 63 64 2.224404
+C68 65 gnd 2.080806f
+R66 64 65 2.224404
+C69 66 gnd 2.080806f
+R67 65 66 2.224404
+C70 67 gnd 2.080806f
+R68 66 67 2.224404
+C71 68 gnd 2.080806f
+R69 67 68 2.224404
+C72 69 gnd 2.080806f
+R70 68 69 2.224404
+C73 70 gnd 2.080806f
+R71 69 70 2.224404
+C74 71 gnd 2.080806f
+R72 70 71 2.224404
+C75 72 gnd 2.080806f
+R73 71 72 2.224404
+C76 73 gnd 2.080806f
+R74 72 73 2.224404
+C77 74 gnd 2.080806f
+R75 73 74 2.224404
+C78 75 gnd 2.080806f
+R76 74 75 2.224404
+C79 76 gnd 2.080806f
+R77 75 76 2.224404
+C80 77 gnd 2.080806f
+R78 76 77 2.224404
+C81 78 gnd 2.080806f
+R79 77 78 2.224404
+C82 79 gnd 2.080806f
+R80 78 79 2.224404
+C83 80 gnd 2.080806f
+R81 79 80 2.224404
+C84 81 gnd 2.080806f
+R82 80 81 2.224404
+C85 82 gnd 2.080806f
+R83 81 82 2.224404
+C86 83 gnd 2.080806f
+R84 82 83 2.224404
+C87 84 gnd 2.080806f
+R85 83 84 2.224404
+C88 85 gnd 2.080806f
+R86 84 85 2.224404
+C89 86 gnd 2.080806f
+R87 85 86 2.224404
+C90 87 gnd 2.080806f
+R88 86 87 2.224404
+C91 88 gnd 2.080806f
+R89 87 88 2.224404
+C92 89 gnd 2.080806f
+R90 88 89 2.224404
+C93 90 gnd 2.080806f
+R91 89 90 2.224404
+C94 91 gnd 2.080806f
+R92 90 91 2.224404
+C95 92 gnd 2.080806f
+R93 91 92 2.224404
+C96 93 gnd 2.080806f
+R94 92 93 2.224404
+C97 94 gnd 2.080806f
+R95 93 94 2.224404
+C98 95 gnd 2.080806f
+R96 94 95 2.224404
+C99 96 gnd 2.080806f
+R97 95 96 2.224404
+C100 97 gnd 2.080806f
+R98 96 97 2.224404
+C101 98 gnd 2.080806f
+R99 97 98 2.224404
+C102 99 gnd 2.080806f
+R100 98 99 2.224404
+C103 100 gnd 2.080806f
+R101 99 100 2.224404
+C104 101 gnd 2.080806f
+R102 100 101 2.224404
+C105 102 gnd 2.080806f
+R103 101 102 2.224404
+C106 103 gnd 2.080806f
+R104 102 103 2.224404
+C107 104 gnd 2.080806f
+R105 103 104 2.224404
+R106 104 g177_2 2.224404
+.ends
+
+.subckt netg7483 g7483_1 g7483_0 gnd
+C1  g7483_1 gnd 2.080806f
+C2  g7483_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g7483_0 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 25 26 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 28 29 2.224404
+C32 30 gnd 2.080806f
+R30 29 30 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 37 38 2.224404
+C41 39 gnd 2.080806f
+R39 38 39 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 43 44 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 46 47 2.224404
+C50 48 gnd 2.080806f
+R48 48 47 2.224404
+C51 49 gnd 2.080806f
+R49 49 48 2.224404
+C52 50 gnd 2.080806f
+R50 50 49 2.224404
+C53 51 gnd 2.080806f
+R51 51 50 2.224404
+C54 52 gnd 2.080806f
+R52 52 51 2.224404
+C55 53 gnd 2.080806f
+R53 53 52 2.224404
+C56 54 gnd 2.080806f
+R54 54 53 2.224404
+C57 55 gnd 2.080806f
+R55 55 54 2.224404
+C58 56 gnd 2.080806f
+R56 55 56 2.224404
+C59 57 gnd 2.080806f
+R57 57 56 2.224404
+C60 58 gnd 2.080806f
+R58 58 57 2.224404
+C61 59 gnd 2.080806f
+R59 59 58 2.224404
+C62 60 gnd 2.080806f
+R60 59 60 2.224404
+C63 61 gnd 2.080806f
+R61 61 60 2.224404
+C64 62 gnd 2.080806f
+R62 62 61 2.224404
+C65 63 gnd 2.080806f
+R63 62 63 2.224404
+C66 64 gnd 2.080806f
+R64 63 64 2.224404
+C67 65 gnd 2.080806f
+R65 64 65 2.224404
+C68 66 gnd 2.080806f
+R66 65 66 2.224404
+C69 67 gnd 2.080806f
+R67 67 66 2.224404
+C70 68 gnd 2.080806f
+R68 67 68 2.224404
+C71 69 gnd 2.080806f
+R69 69 68 2.224404
+C72 70 gnd 2.080806f
+R70 70 69 2.224404
+C73 71 gnd 2.080806f
+R71 70 71 2.224404
+C74 72 gnd 2.080806f
+R72 72 71 2.224404
+C75 73 gnd 2.080806f
+R73 73 72 2.224404
+C76 74 gnd 2.080806f
+R74 74 73 2.224404
+C77 75 gnd 2.080806f
+R75 75 74 2.224404
+C78 76 gnd 2.080806f
+R76 75 76 2.224404
+C79 77 gnd 2.080806f
+R77 77 76 2.224404
+C80 78 gnd 2.080806f
+R78 78 77 2.224404
+C81 79 gnd 2.080806f
+R79 79 78 2.224404
+C82 80 gnd 2.080806f
+R80 79 80 2.224404
+C83 81 gnd 2.080806f
+R81 81 80 2.224404
+C84 82 gnd 2.080806f
+R82 82 81 2.224404
+C85 83 gnd 2.080806f
+R83 82 83 2.224404
+C86 84 gnd 2.080806f
+R84 84 83 2.224404
+C87 85 gnd 2.080806f
+R85 85 84 2.224404
+C88 86 gnd 2.080806f
+R86 85 86 2.224404
+C89 87 gnd 2.080806f
+R87 87 86 2.224404
+C90 88 gnd 2.080806f
+R88 88 87 2.224404
+C91 89 gnd 2.080806f
+R89 89 88 2.224404
+C92 90 gnd 2.080806f
+R90 89 90 2.224404
+C93 91 gnd 2.080806f
+R91 90 91 2.224404
+C94 92 gnd 2.080806f
+R92 92 91 2.224404
+C95 93 gnd 2.080806f
+R93 92 93 2.224404
+C96 94 gnd 2.080806f
+R94 94 93 2.224404
+R95 g7483_1 94 2.224404
+.ends
+
+.subckt netg200 g200_0 g200_2 g200_1 gnd
+C1  g200_0 gnd 2.080806f
+C2  g200_2 gnd 2.080806f
+C3  g200_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g200_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 6 5 2.224404
+C10 7 gnd 2.080806f
+R7 7 6 2.224404
+C11 8 gnd 2.080806f
+R8 8 7 2.224404
+C12 9 gnd 2.080806f
+R9 9 8 2.224404
+C13 10 gnd 2.080806f
+R10 10 9 2.224404
+C14 11 gnd 2.080806f
+R11 11 10 2.224404
+C15 12 gnd 2.080806f
+R12 12 11 2.224404
+C16 13 gnd 2.080806f
+R13 13 12 2.224404
+C17 14 gnd 2.080806f
+R14 14 13 2.224404
+C18 15 gnd 2.080806f
+R15 15 14 2.224404
+C19 16 gnd 2.080806f
+R16 16 15 2.224404
+C20 17 gnd 2.080806f
+R17 17 16 2.224404
+C21 18 gnd 2.080806f
+R18 18 17 2.224404
+C22 19 gnd 2.080806f
+R19 19 18 2.224404
+C23 20 gnd 2.080806f
+R20 20 19 2.224404
+C24 21 gnd 2.080806f
+R21 21 20 2.224404
+C25 22 gnd 2.080806f
+R22 22 21 2.224404
+C26 23 gnd 2.080806f
+R23 23 22 2.224404
+C27 24 gnd 2.080806f
+R24 24 23 2.224404
+C28 25 gnd 2.080806f
+R25 25 24 2.224404
+C29 26 gnd 2.080806f
+R26 26 25 2.224404
+C30 27 gnd 2.080806f
+R27 27 26 2.224404
+C31 28 gnd 2.080806f
+R28 28 27 2.224404
+C32 29 gnd 2.080806f
+R29 29 28 2.224404
+C33 30 gnd 2.080806f
+R30 30 29 2.224404
+C34 31 gnd 2.080806f
+R31 31 30 2.224404
+C35 32 gnd 2.080806f
+R32 32 31 2.224404
+C36 33 gnd 2.080806f
+R33 33 32 2.224404
+C37 34 gnd 2.080806f
+R34 34 33 2.224404
+C38 35 gnd 2.080806f
+R35 35 34 2.224404
+C39 36 gnd 2.080806f
+R36 36 35 2.224404
+C40 37 gnd 2.080806f
+R37 37 36 2.224404
+C41 38 gnd 2.080806f
+R38 38 37 2.224404
+C42 39 gnd 2.080806f
+R39 39 38 2.224404
+C43 40 gnd 2.080806f
+R40 40 39 2.224404
+C44 41 gnd 2.080806f
+R41 41 40 2.224404
+C45 42 gnd 2.080806f
+R42 42 41 2.224404
+C46 43 gnd 2.080806f
+R43 43 42 2.224404
+C47 44 gnd 2.080806f
+R44 44 43 2.224404
+C48 45 gnd 2.080806f
+R45 45 44 2.224404
+C49 46 gnd 2.080806f
+R46 46 45 2.224404
+C50 47 gnd 2.080806f
+R47 47 46 2.224404
+C51 48 gnd 2.080806f
+R48 48 47 2.224404
+C52 49 gnd 2.080806f
+R49 49 48 2.224404
+C53 50 gnd 2.080806f
+R50 50 49 2.224404
+C54 51 gnd 2.080806f
+R51 51 50 2.224404
+C55 52 gnd 2.080806f
+R52 52 51 2.224404
+C56 53 gnd 2.080806f
+R53 53 52 2.224404
+C57 54 gnd 2.080806f
+R54 54 53 2.224404
+C58 55 gnd 2.080806f
+R55 55 54 2.224404
+C59 56 gnd 2.080806f
+R56 56 55 2.224404
+C60 57 gnd 2.080806f
+R57 57 56 2.224404
+C61 58 gnd 2.080806f
+R58 58 57 2.224404
+C62 59 gnd 2.080806f
+R59 59 58 2.224404
+C63 60 gnd 2.080806f
+R60 60 59 2.224404
+C64 61 gnd 2.080806f
+R61 61 60 2.224404
+C65 62 gnd 2.080806f
+R62 62 61 2.224404
+C66 63 gnd 2.080806f
+R63 63 62 2.224404
+C67 64 gnd 2.080806f
+R64 64 63 2.224404
+C68 65 gnd 2.080806f
+R65 65 64 2.224404
+C69 66 gnd 2.080806f
+R66 66 65 2.224404
+C70 67 gnd 2.080806f
+R67 67 66 2.224404
+C71 68 gnd 2.080806f
+R68 68 67 2.224404
+R69 g200_2 68 2.224404
+C72 69 gnd 2.080806f
+R70 69 g200_2 2.224404
+C73 70 gnd 2.080806f
+R71 70 69 2.224404
+C74 71 gnd 2.080806f
+R72 71 70 2.224404
+C75 72 gnd 2.080806f
+R73 72 71 2.224404
+C76 73 gnd 2.080806f
+R74 72 73 2.224404
+C77 74 gnd 2.080806f
+R75 73 74 2.224404
+C78 75 gnd 2.080806f
+R76 74 75 2.224404
+C79 76 gnd 2.080806f
+R77 75 76 2.224404
+C80 77 gnd 2.080806f
+R78 76 77 2.224404
+C81 78 gnd 2.080806f
+R79 77 78 2.224404
+C82 79 gnd 2.080806f
+R80 79 78 2.224404
+C83 80 gnd 2.080806f
+R81 80 79 2.224404
+C84 81 gnd 2.080806f
+R82 81 80 2.224404
+C85 82 gnd 2.080806f
+R83 82 81 2.224404
+C86 83 gnd 2.080806f
+R84 82 83 2.224404
+C87 84 gnd 2.080806f
+R85 84 83 2.224404
+C88 85 gnd 2.080806f
+R86 84 85 2.224404
+C89 86 gnd 2.080806f
+R87 86 85 2.224404
+C90 87 gnd 2.080806f
+R88 86 87 2.224404
+C91 88 gnd 2.080806f
+R89 87 88 2.224404
+C92 89 gnd 2.080806f
+R90 88 89 2.224404
+C93 90 gnd 2.080806f
+R91 89 90 2.224404
+C94 91 gnd 2.080806f
+R92 91 90 2.224404
+C95 92 gnd 2.080806f
+R93 92 91 2.224404
+C96 93 gnd 2.080806f
+R94 92 93 2.224404
+C97 94 gnd 2.080806f
+R95 93 94 2.224404
+C98 95 gnd 2.080806f
+R96 94 95 2.224404
+C99 96 gnd 2.080806f
+R97 95 96 2.224404
+C100 97 gnd 2.080806f
+R98 96 97 2.224404
+C101 98 gnd 2.080806f
+R99 97 98 2.224404
+C102 99 gnd 2.080806f
+R100 98 99 2.224404
+C103 100 gnd 2.080806f
+R101 100 99 2.224404
+C104 101 gnd 2.080806f
+R102 100 101 2.224404
+C105 102 gnd 2.080806f
+R103 101 102 2.224404
+C106 103 gnd 2.080806f
+R104 102 103 2.224404
+C107 104 gnd 2.080806f
+R105 103 104 2.224404
+C108 105 gnd 2.080806f
+R106 104 105 2.224404
+C109 106 gnd 2.080806f
+R107 105 106 2.224404
+C110 107 gnd 2.080806f
+R108 107 106 2.224404
+C111 108 gnd 2.080806f
+R109 107 108 2.224404
+C112 109 gnd 2.080806f
+R110 108 109 2.224404
+C113 110 gnd 2.080806f
+R111 109 110 2.224404
+C114 111 gnd 2.080806f
+R112 110 111 2.224404
+C115 112 gnd 2.080806f
+R113 111 112 2.224404
+C116 113 gnd 2.080806f
+R114 112 113 2.224404
+C117 114 gnd 2.080806f
+R115 113 114 2.224404
+C118 115 gnd 2.080806f
+R116 114 115 2.224404
+C119 116 gnd 2.080806f
+R117 115 116 2.224404
+C120 117 gnd 2.080806f
+R118 117 116 2.224404
+C121 118 gnd 2.080806f
+R119 117 118 2.224404
+C122 119 gnd 2.080806f
+R120 118 119 2.224404
+R121 119 g200_1 2.224404
+.ends
+
+.subckt netg8 g8_1 g8_2 g8_0 gnd
+C1  g8_1 gnd 2.080806f
+C2  g8_2 gnd 2.080806f
+C3  g8_0 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g8_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+C8 5 gnd 2.080806f
+R5 4 5 2.224404
+C9 6 gnd 2.080806f
+R6 5 6 2.224404
+C10 7 gnd 2.080806f
+R7 6 7 2.224404
+C11 8 gnd 2.080806f
+R8 7 8 2.224404
+C12 9 gnd 2.080806f
+R9 8 9 2.224404
+C13 10 gnd 2.080806f
+R10 9 10 2.224404
+C14 11 gnd 2.080806f
+R11 10 11 2.224404
+C15 12 gnd 2.080806f
+R12 11 12 2.224404
+C16 13 gnd 2.080806f
+R13 12 13 2.224404
+C17 14 gnd 2.080806f
+R14 13 14 2.224404
+C18 15 gnd 2.080806f
+R15 14 15 2.224404
+C19 16 gnd 2.080806f
+R16 15 16 2.224404
+C20 17 gnd 2.080806f
+R17 16 17 2.224404
+C21 18 gnd 2.080806f
+R18 17 18 2.224404
+C22 19 gnd 2.080806f
+R19 18 19 2.224404
+C23 20 gnd 2.080806f
+R20 19 20 2.224404
+C24 21 gnd 2.080806f
+R21 20 21 2.224404
+C25 22 gnd 2.080806f
+R22 21 22 2.224404
+C26 23 gnd 2.080806f
+R23 22 23 2.224404
+C27 24 gnd 2.080806f
+R24 23 24 2.224404
+C28 25 gnd 2.080806f
+R25 24 25 2.224404
+C29 26 gnd 2.080806f
+R26 25 26 2.224404
+C30 27 gnd 2.080806f
+R27 26 27 2.224404
+C31 28 gnd 2.080806f
+R28 27 28 2.224404
+C32 29 gnd 2.080806f
+R29 28 29 2.224404
+C33 30 gnd 2.080806f
+R30 29 30 2.224404
+C34 31 gnd 2.080806f
+R31 30 31 2.224404
+C35 32 gnd 2.080806f
+R32 31 32 2.224404
+C36 33 gnd 2.080806f
+R33 32 33 2.224404
+C37 34 gnd 2.080806f
+R34 33 34 2.224404
+C38 35 gnd 2.080806f
+R35 34 35 2.224404
+C39 36 gnd 2.080806f
+R36 35 36 2.224404
+C40 37 gnd 2.080806f
+R37 36 37 2.224404
+C41 38 gnd 2.080806f
+R38 37 38 2.224404
+C42 39 gnd 2.080806f
+R39 38 39 2.224404
+C43 40 gnd 2.080806f
+R40 39 40 2.224404
+C44 41 gnd 2.080806f
+R41 40 41 2.224404
+C45 42 gnd 2.080806f
+R42 41 42 2.224404
+C46 43 gnd 2.080806f
+R43 42 43 2.224404
+C47 44 gnd 2.080806f
+R44 43 44 2.224404
+C48 45 gnd 2.080806f
+R45 44 45 2.224404
+C49 46 gnd 2.080806f
+R46 45 46 2.224404
+C50 47 gnd 2.080806f
+R47 46 47 2.224404
+C51 48 gnd 2.080806f
+R48 47 48 2.224404
+C52 49 gnd 2.080806f
+R49 48 49 2.224404
+C53 50 gnd 2.080806f
+R50 49 50 2.224404
+C54 51 gnd 2.080806f
+R51 50 51 2.224404
+C55 52 gnd 2.080806f
+R52 51 52 2.224404
+C56 53 gnd 2.080806f
+R53 52 53 2.224404
+C57 54 gnd 2.080806f
+R54 53 54 2.224404
+C58 55 gnd 2.080806f
+R55 54 55 2.224404
+C59 56 gnd 2.080806f
+R56 55 56 2.224404
+C60 57 gnd 2.080806f
+R57 56 57 2.224404
+C61 58 gnd 2.080806f
+R58 57 58 2.224404
+C62 59 gnd 2.080806f
+R59 58 59 2.224404
+C63 60 gnd 2.080806f
+R60 59 60 2.224404
+C64 61 gnd 2.080806f
+R61 60 61 2.224404
+C65 62 gnd 2.080806f
+R62 61 62 2.224404
+C66 63 gnd 2.080806f
+R63 62 63 2.224404
+C67 64 gnd 2.080806f
+R64 63 64 2.224404
+C68 65 gnd 2.080806f
+R65 64 65 2.224404
+C69 66 gnd 2.080806f
+R66 65 66 2.224404
+C70 67 gnd 2.080806f
+R67 66 67 2.224404
+C71 68 gnd 2.080806f
+R68 67 68 2.224404
+C72 69 gnd 2.080806f
+R69 68 69 2.224404
+C73 70 gnd 2.080806f
+R70 69 70 2.224404
+C74 71 gnd 2.080806f
+R71 70 71 2.224404
+C75 72 gnd 2.080806f
+R72 71 72 2.224404
+C76 73 gnd 2.080806f
+R73 72 73 2.224404
+C77 74 gnd 2.080806f
+R74 73 74 2.224404
+C78 75 gnd 2.080806f
+R75 74 75 2.224404
+C79 76 gnd 2.080806f
+R76 75 76 2.224404
+C80 77 gnd 2.080806f
+R77 76 77 2.224404
+C81 78 gnd 2.080806f
+R78 77 78 2.224404
+C82 79 gnd 2.080806f
+R79 78 79 2.224404
+C83 80 gnd 2.080806f
+R80 79 80 2.224404
+C84 81 gnd 2.080806f
+R81 80 81 2.224404
+C85 82 gnd 2.080806f
+R82 81 82 2.224404
+C86 83 gnd 2.080806f
+R83 82 83 2.224404
+C87 84 gnd 2.080806f
+R84 83 84 2.224404
+C88 85 gnd 2.080806f
+R85 84 85 2.224404
+R86 85 g8_1 2.224404
+C89 86 gnd 2.080806f
+R87 g8_1 86 2.224404
+C90 87 gnd 2.080806f
+R88 87 86 2.224404
+C91 88 gnd 2.080806f
+R89 88 87 2.224404
+C92 89 gnd 2.080806f
+R90 89 88 2.224404
+C93 90 gnd 2.080806f
+R91 90 89 2.224404
+C94 91 gnd 2.080806f
+R92 90 91 2.224404
+C95 92 gnd 2.080806f
+R93 92 91 2.224404
+C96 93 gnd 2.080806f
+R94 93 92 2.224404
+C97 94 gnd 2.080806f
+R95 93 94 2.224404
+C98 95 gnd 2.080806f
+R96 94 95 2.224404
+C99 96 gnd 2.080806f
+R97 95 96 2.224404
+C100 97 gnd 2.080806f
+R98 96 97 2.224404
+C101 98 gnd 2.080806f
+R99 97 98 2.224404
+C102 99 gnd 2.080806f
+R100 98 99 2.224404
+C103 100 gnd 2.080806f
+R101 99 100 2.224404
+C104 101 gnd 2.080806f
+R102 100 101 2.224404
+C105 102 gnd 2.080806f
+R103 101 102 2.224404
+C106 103 gnd 2.080806f
+R104 102 103 2.224404
+C107 104 gnd 2.080806f
+R105 103 104 2.224404
+C108 105 gnd 2.080806f
+R106 104 105 2.224404
+C109 106 gnd 2.080806f
+R107 105 106 2.224404
+C110 107 gnd 2.080806f
+R108 106 107 2.224404
+C111 108 gnd 2.080806f
+R109 107 108 2.224404
+C112 109 gnd 2.080806f
+R110 108 109 2.224404
+C113 110 gnd 2.080806f
+R111 109 110 2.224404
+C114 111 gnd 2.080806f
+R112 110 111 2.224404
+C115 112 gnd 2.080806f
+R113 111 112 2.224404
+C116 113 gnd 2.080806f
+R114 113 112 2.224404
+C117 114 gnd 2.080806f
+R115 114 113 2.224404
+C118 115 gnd 2.080806f
+R116 115 114 2.224404
+C119 116 gnd 2.080806f
+R117 115 116 2.224404
+C120 117 gnd 2.080806f
+R118 117 116 2.224404
+C121 118 gnd 2.080806f
+R119 118 117 2.224404
+C122 119 gnd 2.080806f
+R120 119 118 2.224404
+C123 120 gnd 2.080806f
+R121 120 119 2.224404
+C124 121 gnd 2.080806f
+R122 120 121 2.224404
+C125 122 gnd 2.080806f
+R123 121 122 2.224404
+C126 123 gnd 2.080806f
+R124 122 123 2.224404
+C127 124 gnd 2.080806f
+R125 123 124 2.224404
+C128 125 gnd 2.080806f
+R126 125 124 2.224404
+C129 126 gnd 2.080806f
+R127 126 125 2.224404
+C130 127 gnd 2.080806f
+R128 127 126 2.224404
+R129 127 g8_2 2.224404
+.ends
+
+.subckt netg207 g207_3 g207_2 g207_0 g207_4 g207_1 gnd
+C1  g207_3 gnd 2.080806f
+C2  g207_2 gnd 2.080806f
+C3  g207_0 gnd 2.080806f
+C4  g207_4 gnd 2.080806f
+C5  g207_1 gnd 2.080806f
+R1 g207_2 g207_0 2.224404
+C6 1 gnd 2.080806f
+R2 1 g207_2 2.224404
+C7 2 gnd 2.080806f
+R3 2 1 2.224404
+C8 3 gnd 2.080806f
+R4 3 2 2.224404
+C9 4 gnd 2.080806f
+R5 4 3 2.224404
+C10 5 gnd 2.080806f
+R6 5 4 2.224404
+C11 6 gnd 2.080806f
+R7 6 5 2.224404
+C12 7 gnd 2.080806f
+R8 7 6 2.224404
+C13 8 gnd 2.080806f
+R9 8 7 2.224404
+C14 9 gnd 2.080806f
+R10 9 8 2.224404
+C15 10 gnd 2.080806f
+R11 10 9 2.224404
+C16 11 gnd 2.080806f
+R12 11 10 2.224404
+C17 12 gnd 2.080806f
+R13 12 11 2.224404
+C18 13 gnd 2.080806f
+R14 13 12 2.224404
+C19 14 gnd 2.080806f
+R15 14 13 2.224404
+C20 15 gnd 2.080806f
+R16 15 14 2.224404
+C21 16 gnd 2.080806f
+R17 16 15 2.224404
+C22 17 gnd 2.080806f
+R18 17 16 2.224404
+C23 18 gnd 2.080806f
+R19 18 17 2.224404
+C24 19 gnd 2.080806f
+R20 19 18 2.224404
+C25 20 gnd 2.080806f
+R21 20 19 2.224404
+C26 21 gnd 2.080806f
+R22 21 20 2.224404
+C27 22 gnd 2.080806f
+R23 22 21 2.224404
+C28 23 gnd 2.080806f
+R24 23 22 2.224404
+C29 24 gnd 2.080806f
+R25 24 23 2.224404
+C30 25 gnd 2.080806f
+R26 25 24 2.224404
+C31 26 gnd 2.080806f
+R27 26 25 2.224404
+C32 27 gnd 2.080806f
+R28 27 26 2.224404
+C33 28 gnd 2.080806f
+R29 28 27 2.224404
+C34 29 gnd 2.080806f
+R30 29 28 2.224404
+C35 30 gnd 2.080806f
+R31 30 29 2.224404
+C36 31 gnd 2.080806f
+R32 31 30 2.224404
+C37 32 gnd 2.080806f
+R33 32 31 2.224404
+C38 33 gnd 2.080806f
+R34 33 32 2.224404
+C39 34 gnd 2.080806f
+R35 34 33 2.224404
+C40 35 gnd 2.080806f
+R36 35 34 2.224404
+C41 36 gnd 2.080806f
+R37 36 35 2.224404
+C42 37 gnd 2.080806f
+R38 37 36 2.224404
+C43 38 gnd 2.080806f
+R39 38 37 2.224404
+C44 39 gnd 2.080806f
+R40 39 38 2.224404
+C45 40 gnd 2.080806f
+R41 40 39 2.224404
+C46 41 gnd 2.080806f
+R42 41 40 2.224404
+C47 42 gnd 2.080806f
+R43 42 41 2.224404
+C48 43 gnd 2.080806f
+R44 43 42 2.224404
+C49 44 gnd 2.080806f
+R45 44 43 2.224404
+C50 45 gnd 2.080806f
+R46 45 44 2.224404
+C51 46 gnd 2.080806f
+R47 46 45 2.224404
+C52 47 gnd 2.080806f
+R48 47 46 2.224404
+C53 48 gnd 2.080806f
+R49 48 47 2.224404
+C54 49 gnd 2.080806f
+R50 49 48 2.224404
+C55 50 gnd 2.080806f
+R51 50 49 2.224404
+R52 g207_4 50 2.224404
+R53 g207_3 g207_4 2.224404
+C56 51 gnd 2.080806f
+R54 2 51 2.224404
+C57 52 gnd 2.080806f
+R55 51 52 2.224404
+C58 53 gnd 2.080806f
+R56 53 52 2.224404
+C59 54 gnd 2.080806f
+R57 54 53 2.224404
+C60 55 gnd 2.080806f
+R58 54 55 2.224404
+C61 56 gnd 2.080806f
+R59 55 56 2.224404
+C62 57 gnd 2.080806f
+R60 57 56 2.224404
+C63 58 gnd 2.080806f
+R61 58 57 2.224404
+C64 59 gnd 2.080806f
+R62 59 58 2.224404
+C65 60 gnd 2.080806f
+R63 59 60 2.224404
+C66 61 gnd 2.080806f
+R64 61 60 2.224404
+C67 62 gnd 2.080806f
+R65 62 61 2.224404
+C68 63 gnd 2.080806f
+R66 63 62 2.224404
+C69 64 gnd 2.080806f
+R67 64 63 2.224404
+C70 65 gnd 2.080806f
+R68 64 65 2.224404
+C71 66 gnd 2.080806f
+R69 65 66 2.224404
+C72 67 gnd 2.080806f
+R70 66 67 2.224404
+C73 68 gnd 2.080806f
+R71 67 68 2.224404
+C74 69 gnd 2.080806f
+R72 68 69 2.224404
+C75 70 gnd 2.080806f
+R73 69 70 2.224404
+C76 71 gnd 2.080806f
+R74 70 71 2.224404
+C77 72 gnd 2.080806f
+R75 71 72 2.224404
+C78 73 gnd 2.080806f
+R76 72 73 2.224404
+C79 74 gnd 2.080806f
+R77 73 74 2.224404
+C80 75 gnd 2.080806f
+R78 74 75 2.224404
+C81 76 gnd 2.080806f
+R79 75 76 2.224404
+C82 77 gnd 2.080806f
+R80 76 77 2.224404
+C83 78 gnd 2.080806f
+R81 77 78 2.224404
+C84 79 gnd 2.080806f
+R82 78 79 2.224404
+C85 80 gnd 2.080806f
+R83 79 80 2.224404
+C86 81 gnd 2.080806f
+R84 81 80 2.224404
+C87 82 gnd 2.080806f
+R85 81 82 2.224404
+C88 83 gnd 2.080806f
+R86 83 82 2.224404
+C89 84 gnd 2.080806f
+R87 83 84 2.224404
+C90 85 gnd 2.080806f
+R88 85 84 2.224404
+C91 86 gnd 2.080806f
+R89 86 85 2.224404
+C92 87 gnd 2.080806f
+R90 87 86 2.224404
+C93 88 gnd 2.080806f
+R91 87 88 2.224404
+C94 89 gnd 2.080806f
+R92 89 88 2.224404
+C95 90 gnd 2.080806f
+R93 89 90 2.224404
+C96 91 gnd 2.080806f
+R94 90 91 2.224404
+C97 92 gnd 2.080806f
+R95 92 91 2.224404
+C98 93 gnd 2.080806f
+R96 92 93 2.224404
+C99 94 gnd 2.080806f
+R97 93 94 2.224404
+C100 95 gnd 2.080806f
+R98 94 95 2.224404
+C101 96 gnd 2.080806f
+R99 95 96 2.224404
+C102 97 gnd 2.080806f
+R100 96 97 2.224404
+C103 98 gnd 2.080806f
+R101 97 98 2.224404
+C104 99 gnd 2.080806f
+R102 98 99 2.224404
+C105 100 gnd 2.080806f
+R103 99 100 2.224404
+C106 101 gnd 2.080806f
+R104 100 101 2.224404
+C107 102 gnd 2.080806f
+R105 101 102 2.224404
+C108 103 gnd 2.080806f
+R106 102 103 2.224404
+C109 104 gnd 2.080806f
+R107 104 103 2.224404
+C110 105 gnd 2.080806f
+R108 105 104 2.224404
+C111 106 gnd 2.080806f
+R109 106 105 2.224404
+C112 107 gnd 2.080806f
+R110 106 107 2.224404
+C113 108 gnd 2.080806f
+R111 107 108 2.224404
+C114 109 gnd 2.080806f
+R112 108 109 2.224404
+C115 110 gnd 2.080806f
+R113 109 110 2.224404
+C116 111 gnd 2.080806f
+R114 110 111 2.224404
+C117 112 gnd 2.080806f
+R115 111 112 2.224404
+C118 113 gnd 2.080806f
+R116 113 112 2.224404
+C119 114 gnd 2.080806f
+R117 114 113 2.224404
+C120 115 gnd 2.080806f
+R118 114 115 2.224404
+C121 116 gnd 2.080806f
+R119 116 115 2.224404
+R120 g207_1 116 2.224404
+.ends
+
+.subckt netg11 g11_2 g11_1 gnd
+C1  g11_2 gnd 2.080806f
+C2  g11_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g11_2 1 2.224404
+C4 2 gnd 2.080806f
+R2 1 2 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+C50 48 gnd 2.080806f
+R48 48 47 2.224404
+C51 49 gnd 2.080806f
+R49 49 48 2.224404
+C52 50 gnd 2.080806f
+R50 50 49 2.224404
+C53 51 gnd 2.080806f
+R51 51 50 2.224404
+C54 52 gnd 2.080806f
+R52 52 51 2.224404
+C55 53 gnd 2.080806f
+R53 53 52 2.224404
+C56 54 gnd 2.080806f
+R54 54 53 2.224404
+C57 55 gnd 2.080806f
+R55 55 54 2.224404
+C58 56 gnd 2.080806f
+R56 56 55 2.224404
+C59 57 gnd 2.080806f
+R57 57 56 2.224404
+C60 58 gnd 2.080806f
+R58 58 57 2.224404
+C61 59 gnd 2.080806f
+R59 59 58 2.224404
+C62 60 gnd 2.080806f
+R60 60 59 2.224404
+C63 61 gnd 2.080806f
+R61 61 60 2.224404
+C64 62 gnd 2.080806f
+R62 62 61 2.224404
+C65 63 gnd 2.080806f
+R63 63 62 2.224404
+C66 64 gnd 2.080806f
+R64 64 63 2.224404
+C67 65 gnd 2.080806f
+R65 65 64 2.224404
+C68 66 gnd 2.080806f
+R66 66 65 2.224404
+C69 67 gnd 2.080806f
+R67 67 66 2.224404
+C70 68 gnd 2.080806f
+R68 68 67 2.224404
+C71 69 gnd 2.080806f
+R69 69 68 2.224404
+C72 70 gnd 2.080806f
+R70 70 69 2.224404
+C73 71 gnd 2.080806f
+R71 71 70 2.224404
+C74 72 gnd 2.080806f
+R72 72 71 2.224404
+C75 73 gnd 2.080806f
+R73 73 72 2.224404
+C76 74 gnd 2.080806f
+R74 74 73 2.224404
+C77 75 gnd 2.080806f
+R75 75 74 2.224404
+C78 76 gnd 2.080806f
+R76 76 75 2.224404
+C79 77 gnd 2.080806f
+R77 77 76 2.224404
+C80 78 gnd 2.080806f
+R78 78 77 2.224404
+C81 79 gnd 2.080806f
+R79 79 78 2.224404
+C82 80 gnd 2.080806f
+R80 80 79 2.224404
+C83 81 gnd 2.080806f
+R81 81 80 2.224404
+C84 82 gnd 2.080806f
+R82 82 81 2.224404
+C85 83 gnd 2.080806f
+R83 83 82 2.224404
+C86 84 gnd 2.080806f
+R84 84 83 2.224404
+C87 85 gnd 2.080806f
+R85 85 84 2.224404
+C88 86 gnd 2.080806f
+R86 86 85 2.224404
+C89 87 gnd 2.080806f
+R87 87 86 2.224404
+C90 88 gnd 2.080806f
+R88 88 87 2.224404
+C91 89 gnd 2.080806f
+R89 89 88 2.224404
+C92 90 gnd 2.080806f
+R90 90 89 2.224404
+C93 91 gnd 2.080806f
+R91 91 90 2.224404
+C94 92 gnd 2.080806f
+R92 92 91 2.224404
+C95 93 gnd 2.080806f
+R93 93 92 2.224404
+C96 94 gnd 2.080806f
+R94 94 93 2.224404
+C97 95 gnd 2.080806f
+R95 95 94 2.224404
+C98 96 gnd 2.080806f
+R96 96 95 2.224404
+C99 97 gnd 2.080806f
+R97 97 96 2.224404
+C100 98 gnd 2.080806f
+R98 98 97 2.224404
+C101 99 gnd 2.080806f
+R99 99 98 2.224404
+C102 100 gnd 2.080806f
+R100 100 99 2.224404
+R101 g11_1 100 2.224404
+.ends
+
+.subckt netg6 g6_0 g6_2 g6_1 g6_4 g6_3 gnd
+C1  g6_0 gnd 2.080806f
+C2  g6_2 gnd 2.080806f
+C3  g6_1 gnd 2.080806f
+C4  g6_4 gnd 2.080806f
+C5  g6_3 gnd 2.080806f
+C6 1 gnd 2.080806f
+R1 g6_0 1 2.224404
+C7 2 gnd 2.080806f
+R2 1 2 2.224404
+C8 3 gnd 2.080806f
+R3 2 3 2.224404
+R4 3 g6_1 2.224404
+C9 4 gnd 2.080806f
+R5 4 3 2.224404
+C10 5 gnd 2.080806f
+R6 5 4 2.224404
+C11 6 gnd 2.080806f
+R7 6 5 2.224404
+C12 7 gnd 2.080806f
+R8 6 7 2.224404
+C13 8 gnd 2.080806f
+R9 7 8 2.224404
+C14 9 gnd 2.080806f
+R10 9 8 2.224404
+C15 10 gnd 2.080806f
+R11 9 10 2.224404
+C16 11 gnd 2.080806f
+R12 10 11 2.224404
+C17 12 gnd 2.080806f
+R13 11 12 2.224404
+C18 13 gnd 2.080806f
+R14 13 12 2.224404
+C19 14 gnd 2.080806f
+R15 13 14 2.224404
+C20 15 gnd 2.080806f
+R16 14 15 2.224404
+C21 16 gnd 2.080806f
+R17 15 16 2.224404
+C22 17 gnd 2.080806f
+R18 16 17 2.224404
+C23 18 gnd 2.080806f
+R19 17 18 2.224404
+C24 19 gnd 2.080806f
+R20 18 19 2.224404
+C25 20 gnd 2.080806f
+R21 20 19 2.224404
+C26 21 gnd 2.080806f
+R22 21 20 2.224404
+C27 22 gnd 2.080806f
+R23 22 21 2.224404
+C28 23 gnd 2.080806f
+R24 23 22 2.224404
+C29 24 gnd 2.080806f
+R25 24 23 2.224404
+C30 25 gnd 2.080806f
+R26 24 25 2.224404
+C31 26 gnd 2.080806f
+R27 26 25 2.224404
+C32 27 gnd 2.080806f
+R28 27 26 2.224404
+C33 28 gnd 2.080806f
+R29 28 27 2.224404
+C34 29 gnd 2.080806f
+R30 29 28 2.224404
+C35 30 gnd 2.080806f
+R31 30 29 2.224404
+R32 g6_2 30 2.224404
+C36 31 gnd 2.080806f
+R33 31 g6_2 2.224404
+C37 32 gnd 2.080806f
+R34 32 31 2.224404
+C38 33 gnd 2.080806f
+R35 33 32 2.224404
+C39 34 gnd 2.080806f
+R36 33 34 2.224404
+C40 35 gnd 2.080806f
+R37 35 34 2.224404
+C41 36 gnd 2.080806f
+R38 36 35 2.224404
+C42 37 gnd 2.080806f
+R39 37 36 2.224404
+C43 38 gnd 2.080806f
+R40 38 37 2.224404
+C44 39 gnd 2.080806f
+R41 39 38 2.224404
+C45 40 gnd 2.080806f
+R42 40 39 2.224404
+C46 41 gnd 2.080806f
+R43 41 40 2.224404
+C47 42 gnd 2.080806f
+R44 42 41 2.224404
+C48 43 gnd 2.080806f
+R45 43 42 2.224404
+C49 44 gnd 2.080806f
+R46 44 43 2.224404
+C50 45 gnd 2.080806f
+R47 45 44 2.224404
+C51 46 gnd 2.080806f
+R48 46 45 2.224404
+C52 47 gnd 2.080806f
+R49 47 46 2.224404
+C53 48 gnd 2.080806f
+R50 48 47 2.224404
+C54 49 gnd 2.080806f
+R51 49 48 2.224404
+C55 50 gnd 2.080806f
+R52 50 49 2.224404
+C56 51 gnd 2.080806f
+R53 51 50 2.224404
+C57 52 gnd 2.080806f
+R54 52 51 2.224404
+C58 53 gnd 2.080806f
+R55 53 52 2.224404
+C59 54 gnd 2.080806f
+R56 54 53 2.224404
+C60 55 gnd 2.080806f
+R57 55 54 2.224404
+C61 56 gnd 2.080806f
+R58 56 55 2.224404
+C62 57 gnd 2.080806f
+R59 57 56 2.224404
+C63 58 gnd 2.080806f
+R60 58 57 2.224404
+R61 g6_3 58 2.224404
+C64 59 gnd 2.080806f
+R62 59 g6_3 2.224404
+C65 60 gnd 2.080806f
+R63 60 59 2.224404
+C66 61 gnd 2.080806f
+R64 61 60 2.224404
+C67 62 gnd 2.080806f
+R65 62 61 2.224404
+C68 63 gnd 2.080806f
+R66 63 62 2.224404
+C69 64 gnd 2.080806f
+R67 64 63 2.224404
+C70 65 gnd 2.080806f
+R68 65 64 2.224404
+C71 66 gnd 2.080806f
+R69 66 65 2.224404
+C72 67 gnd 2.080806f
+R70 67 66 2.224404
+C73 68 gnd 2.080806f
+R71 68 67 2.224404
+C74 69 gnd 2.080806f
+R72 69 68 2.224404
+C75 70 gnd 2.080806f
+R73 70 69 2.224404
+C76 71 gnd 2.080806f
+R74 71 70 2.224404
+C77 72 gnd 2.080806f
+R75 72 71 2.224404
+C78 73 gnd 2.080806f
+R76 73 72 2.224404
+C79 74 gnd 2.080806f
+R77 74 73 2.224404
+C80 75 gnd 2.080806f
+R78 75 74 2.224404
+C81 76 gnd 2.080806f
+R79 76 75 2.224404
+C82 77 gnd 2.080806f
+R80 77 76 2.224404
+C83 78 gnd 2.080806f
+R81 78 77 2.224404
+C84 79 gnd 2.080806f
+R82 79 78 2.224404
+C85 80 gnd 2.080806f
+R83 80 79 2.224404
+C86 81 gnd 2.080806f
+R84 81 80 2.224404
+C87 82 gnd 2.080806f
+R85 82 81 2.224404
+C88 83 gnd 2.080806f
+R86 83 82 2.224404
+C89 84 gnd 2.080806f
+R87 84 83 2.224404
+C90 85 gnd 2.080806f
+R88 85 84 2.224404
+C91 86 gnd 2.080806f
+R89 86 85 2.224404
+C92 87 gnd 2.080806f
+R90 87 86 2.224404
+C93 88 gnd 2.080806f
+R91 88 87 2.224404
+C94 89 gnd 2.080806f
+R92 89 88 2.224404
+C95 90 gnd 2.080806f
+R93 90 89 2.224404
+C96 91 gnd 2.080806f
+R94 91 90 2.224404
+C97 92 gnd 2.080806f
+R95 92 91 2.224404
+C98 93 gnd 2.080806f
+R96 93 92 2.224404
+C99 94 gnd 2.080806f
+R97 94 93 2.224404
+C100 95 gnd 2.080806f
+R98 95 94 2.224404
+C101 96 gnd 2.080806f
+R99 96 95 2.224404
+C102 97 gnd 2.080806f
+R100 97 96 2.224404
+C103 98 gnd 2.080806f
+R101 98 97 2.224404
+C104 99 gnd 2.080806f
+R102 99 98 2.224404
+C105 100 gnd 2.080806f
+R103 100 99 2.224404
+C106 101 gnd 2.080806f
+R104 101 100 2.224404
+C107 102 gnd 2.080806f
+R105 102 101 2.224404
+C108 103 gnd 2.080806f
+R106 103 102 2.224404
+C109 104 gnd 2.080806f
+R107 104 103 2.224404
+C110 105 gnd 2.080806f
+R108 105 104 2.224404
+C111 106 gnd 2.080806f
+R109 106 105 2.224404
+C112 107 gnd 2.080806f
+R110 107 106 2.224404
+C113 108 gnd 2.080806f
+R111 108 107 2.224404
+C114 109 gnd 2.080806f
+R112 109 108 2.224404
+C115 110 gnd 2.080806f
+R113 110 109 2.224404
+C116 111 gnd 2.080806f
+R114 111 110 2.224404
+C117 112 gnd 2.080806f
+R115 112 111 2.224404
+C118 113 gnd 2.080806f
+R116 113 112 2.224404
+C119 114 gnd 2.080806f
+R117 114 113 2.224404
+C120 115 gnd 2.080806f
+R118 115 114 2.224404
+R119 g6_4 115 2.224404
+.ends
+
+.subckt netg15 g15_0 g15_2 g15_1 gnd
+C1  g15_0 gnd 2.080806f
+C2  g15_2 gnd 2.080806f
+C3  g15_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 g15_0 1 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+C8 5 gnd 2.080806f
+R5 4 5 2.224404
+C9 6 gnd 2.080806f
+R6 5 6 2.224404
+C10 7 gnd 2.080806f
+R7 6 7 2.224404
+C11 8 gnd 2.080806f
+R8 7 8 2.224404
+C12 9 gnd 2.080806f
+R9 8 9 2.224404
+C13 10 gnd 2.080806f
+R10 9 10 2.224404
+C14 11 gnd 2.080806f
+R11 10 11 2.224404
+C15 12 gnd 2.080806f
+R12 11 12 2.224404
+C16 13 gnd 2.080806f
+R13 12 13 2.224404
+C17 14 gnd 2.080806f
+R14 13 14 2.224404
+C18 15 gnd 2.080806f
+R15 14 15 2.224404
+C19 16 gnd 2.080806f
+R16 15 16 2.224404
+C20 17 gnd 2.080806f
+R17 16 17 2.224404
+C21 18 gnd 2.080806f
+R18 17 18 2.224404
+C22 19 gnd 2.080806f
+R19 18 19 2.224404
+C23 20 gnd 2.080806f
+R20 19 20 2.224404
+C24 21 gnd 2.080806f
+R21 20 21 2.224404
+C25 22 gnd 2.080806f
+R22 21 22 2.224404
+C26 23 gnd 2.080806f
+R23 22 23 2.224404
+C27 24 gnd 2.080806f
+R24 23 24 2.224404
+C28 25 gnd 2.080806f
+R25 24 25 2.224404
+C29 26 gnd 2.080806f
+R26 25 26 2.224404
+C30 27 gnd 2.080806f
+R27 26 27 2.224404
+C31 28 gnd 2.080806f
+R28 27 28 2.224404
+C32 29 gnd 2.080806f
+R29 28 29 2.224404
+C33 30 gnd 2.080806f
+R30 29 30 2.224404
+C34 31 gnd 2.080806f
+R31 30 31 2.224404
+C35 32 gnd 2.080806f
+R32 31 32 2.224404
+C36 33 gnd 2.080806f
+R33 32 33 2.224404
+C37 34 gnd 2.080806f
+R34 33 34 2.224404
+C38 35 gnd 2.080806f
+R35 34 35 2.224404
+C39 36 gnd 2.080806f
+R36 35 36 2.224404
+C40 37 gnd 2.080806f
+R37 36 37 2.224404
+C41 38 gnd 2.080806f
+R38 37 38 2.224404
+C42 39 gnd 2.080806f
+R39 38 39 2.224404
+C43 40 gnd 2.080806f
+R40 39 40 2.224404
+C44 41 gnd 2.080806f
+R41 40 41 2.224404
+C45 42 gnd 2.080806f
+R42 41 42 2.224404
+C46 43 gnd 2.080806f
+R43 42 43 2.224404
+C47 44 gnd 2.080806f
+R44 43 44 2.224404
+C48 45 gnd 2.080806f
+R45 44 45 2.224404
+C49 46 gnd 2.080806f
+R46 45 46 2.224404
+C50 47 gnd 2.080806f
+R47 46 47 2.224404
+C51 48 gnd 2.080806f
+R48 47 48 2.224404
+C52 49 gnd 2.080806f
+R49 48 49 2.224404
+C53 50 gnd 2.080806f
+R50 50 49 2.224404
+C54 51 gnd 2.080806f
+R51 50 51 2.224404
+C55 52 gnd 2.080806f
+R52 52 51 2.224404
+C56 53 gnd 2.080806f
+R53 52 53 2.224404
+C57 54 gnd 2.080806f
+R54 53 54 2.224404
+C58 55 gnd 2.080806f
+R55 54 55 2.224404
+C59 56 gnd 2.080806f
+R56 55 56 2.224404
+C60 57 gnd 2.080806f
+R57 56 57 2.224404
+C61 58 gnd 2.080806f
+R58 57 58 2.224404
+C62 59 gnd 2.080806f
+R59 58 59 2.224404
+C63 60 gnd 2.080806f
+R60 59 60 2.224404
+C64 61 gnd 2.080806f
+R61 60 61 2.224404
+C65 62 gnd 2.080806f
+R62 61 62 2.224404
+C66 63 gnd 2.080806f
+R63 62 63 2.224404
+C67 64 gnd 2.080806f
+R64 63 64 2.224404
+C68 65 gnd 2.080806f
+R65 64 65 2.224404
+C69 66 gnd 2.080806f
+R66 65 66 2.224404
+C70 67 gnd 2.080806f
+R67 66 67 2.224404
+C71 68 gnd 2.080806f
+R68 67 68 2.224404
+C72 69 gnd 2.080806f
+R69 68 69 2.224404
+C73 70 gnd 2.080806f
+R70 69 70 2.224404
+C74 71 gnd 2.080806f
+R71 70 71 2.224404
+C75 72 gnd 2.080806f
+R72 71 72 2.224404
+C76 73 gnd 2.080806f
+R73 72 73 2.224404
+C77 74 gnd 2.080806f
+R74 73 74 2.224404
+C78 75 gnd 2.080806f
+R75 74 75 2.224404
+C79 76 gnd 2.080806f
+R76 75 76 2.224404
+C80 77 gnd 2.080806f
+R77 76 77 2.224404
+C81 78 gnd 2.080806f
+R78 77 78 2.224404
+C82 79 gnd 2.080806f
+R79 78 79 2.224404
+C83 80 gnd 2.080806f
+R80 79 80 2.224404
+C84 81 gnd 2.080806f
+R81 80 81 2.224404
+C85 82 gnd 2.080806f
+R82 81 82 2.224404
+C86 83 gnd 2.080806f
+R83 82 83 2.224404
+C87 84 gnd 2.080806f
+R84 83 84 2.224404
+C88 85 gnd 2.080806f
+R85 84 85 2.224404
+C89 86 gnd 2.080806f
+R86 85 86 2.224404
+C90 87 gnd 2.080806f
+R87 86 87 2.224404
+C91 88 gnd 2.080806f
+R88 87 88 2.224404
+C92 89 gnd 2.080806f
+R89 89 88 2.224404
+C93 90 gnd 2.080806f
+R90 90 89 2.224404
+C94 91 gnd 2.080806f
+R91 90 91 2.224404
+C95 92 gnd 2.080806f
+R92 92 91 2.224404
+C96 93 gnd 2.080806f
+R93 92 93 2.224404
+C97 94 gnd 2.080806f
+R94 93 94 2.224404
+C98 95 gnd 2.080806f
+R95 94 95 2.224404
+C99 96 gnd 2.080806f
+R96 95 96 2.224404
+C100 97 gnd 2.080806f
+R97 97 96 2.224404
+C101 98 gnd 2.080806f
+R98 98 97 2.224404
+C102 99 gnd 2.080806f
+R99 99 98 2.224404
+C103 100 gnd 2.080806f
+R100 100 99 2.224404
+C104 101 gnd 2.080806f
+R101 101 100 2.224404
+C105 102 gnd 2.080806f
+R102 101 102 2.224404
+C106 103 gnd 2.080806f
+R103 102 103 2.224404
+C107 104 gnd 2.080806f
+R104 104 103 2.224404
+C108 105 gnd 2.080806f
+R105 104 105 2.224404
+C109 106 gnd 2.080806f
+R106 105 106 2.224404
+C110 107 gnd 2.080806f
+R107 106 107 2.224404
+C111 108 gnd 2.080806f
+R108 108 107 2.224404
+C112 109 gnd 2.080806f
+R109 109 108 2.224404
+C113 110 gnd 2.080806f
+R110 109 110 2.224404
+C114 111 gnd 2.080806f
+R111 110 111 2.224404
+C115 112 gnd 2.080806f
+R112 111 112 2.224404
+C116 113 gnd 2.080806f
+R113 112 113 2.224404
+C117 114 gnd 2.080806f
+R114 113 114 2.224404
+C118 115 gnd 2.080806f
+R115 114 115 2.224404
+C119 116 gnd 2.080806f
+R116 115 116 2.224404
+C120 117 gnd 2.080806f
+R117 116 117 2.224404
+R118 117 g15_2 2.224404
+C121 118 gnd 2.080806f
+R119 98 118 2.224404
+C122 119 gnd 2.080806f
+R120 118 119 2.224404
+C123 120 gnd 2.080806f
+R121 119 120 2.224404
+C124 121 gnd 2.080806f
+R122 120 121 2.224404
+C125 122 gnd 2.080806f
+R123 121 122 2.224404
+C126 123 gnd 2.080806f
+R124 122 123 2.224404
+C127 124 gnd 2.080806f
+R125 123 124 2.224404
+C128 125 gnd 2.080806f
+R126 124 125 2.224404
+C129 126 gnd 2.080806f
+R127 125 126 2.224404
+C130 127 gnd 2.080806f
+R128 126 127 2.224404
+C131 128 gnd 2.080806f
+R129 127 128 2.224404
+C132 129 gnd 2.080806f
+R130 128 129 2.224404
+C133 130 gnd 2.080806f
+R131 130 129 2.224404
+C134 131 gnd 2.080806f
+R132 130 131 2.224404
+C135 132 gnd 2.080806f
+R133 131 132 2.224404
+C136 133 gnd 2.080806f
+R134 132 133 2.224404
+C137 134 gnd 2.080806f
+R135 133 134 2.224404
+C138 135 gnd 2.080806f
+R136 134 135 2.224404
+C139 136 gnd 2.080806f
+R137 135 136 2.224404
+C140 137 gnd 2.080806f
+R138 136 137 2.224404
+C141 138 gnd 2.080806f
+R139 137 138 2.224404
+C142 139 gnd 2.080806f
+R140 139 138 2.224404
+C143 140 gnd 2.080806f
+R141 140 139 2.224404
+C144 141 gnd 2.080806f
+R142 141 140 2.224404
+C145 142 gnd 2.080806f
+R143 141 142 2.224404
+C146 143 gnd 2.080806f
+R144 143 142 2.224404
+C147 144 gnd 2.080806f
+R145 144 143 2.224404
+R146 g15_1 144 2.224404
+.ends
+
+.subckt netg187 g187_2 g187_0 g187_1 gnd
+C1  g187_2 gnd 2.080806f
+C2  g187_0 gnd 2.080806f
+C3  g187_1 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g187_0 2.224404
+C5 2 gnd 2.080806f
+R2 1 2 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 3 4 2.224404
+C8 5 gnd 2.080806f
+R5 4 5 2.224404
+C9 6 gnd 2.080806f
+R6 5 6 2.224404
+C10 7 gnd 2.080806f
+R7 6 7 2.224404
+C11 8 gnd 2.080806f
+R8 7 8 2.224404
+C12 9 gnd 2.080806f
+R9 8 9 2.224404
+C13 10 gnd 2.080806f
+R10 9 10 2.224404
+C14 11 gnd 2.080806f
+R11 11 10 2.224404
+C15 12 gnd 2.080806f
+R12 12 11 2.224404
+C16 13 gnd 2.080806f
+R13 12 13 2.224404
+C17 14 gnd 2.080806f
+R14 14 13 2.224404
+C18 15 gnd 2.080806f
+R15 14 15 2.224404
+C19 16 gnd 2.080806f
+R16 15 16 2.224404
+C20 17 gnd 2.080806f
+R17 16 17 2.224404
+C21 18 gnd 2.080806f
+R18 17 18 2.224404
+C22 19 gnd 2.080806f
+R19 18 19 2.224404
+C23 20 gnd 2.080806f
+R20 19 20 2.224404
+C24 21 gnd 2.080806f
+R21 20 21 2.224404
+C25 22 gnd 2.080806f
+R22 21 22 2.224404
+C26 23 gnd 2.080806f
+R23 22 23 2.224404
+C27 24 gnd 2.080806f
+R24 23 24 2.224404
+C28 25 gnd 2.080806f
+R25 24 25 2.224404
+C29 26 gnd 2.080806f
+R26 25 26 2.224404
+C30 27 gnd 2.080806f
+R27 26 27 2.224404
+C31 28 gnd 2.080806f
+R28 27 28 2.224404
+C32 29 gnd 2.080806f
+R29 28 29 2.224404
+C33 30 gnd 2.080806f
+R30 29 30 2.224404
+C34 31 gnd 2.080806f
+R31 30 31 2.224404
+C35 32 gnd 2.080806f
+R32 32 31 2.224404
+C36 33 gnd 2.080806f
+R33 32 33 2.224404
+C37 34 gnd 2.080806f
+R34 33 34 2.224404
+C38 35 gnd 2.080806f
+R35 34 35 2.224404
+C39 36 gnd 2.080806f
+R36 36 35 2.224404
+C40 37 gnd 2.080806f
+R37 36 37 2.224404
+C41 38 gnd 2.080806f
+R38 38 37 2.224404
+C42 39 gnd 2.080806f
+R39 39 38 2.224404
+C43 40 gnd 2.080806f
+R40 40 39 2.224404
+C44 41 gnd 2.080806f
+R41 41 40 2.224404
+C45 42 gnd 2.080806f
+R42 42 41 2.224404
+C46 43 gnd 2.080806f
+R43 42 43 2.224404
+C47 44 gnd 2.080806f
+R44 43 44 2.224404
+R45 44 g187_2 2.224404
+C48 45 gnd 2.080806f
+R46 g187_2 45 2.224404
+C49 46 gnd 2.080806f
+R47 45 46 2.224404
+C50 47 gnd 2.080806f
+R48 46 47 2.224404
+C51 48 gnd 2.080806f
+R49 47 48 2.224404
+C52 49 gnd 2.080806f
+R50 48 49 2.224404
+C53 50 gnd 2.080806f
+R51 49 50 2.224404
+C54 51 gnd 2.080806f
+R52 50 51 2.224404
+C55 52 gnd 2.080806f
+R53 51 52 2.224404
+C56 53 gnd 2.080806f
+R54 52 53 2.224404
+C57 54 gnd 2.080806f
+R55 53 54 2.224404
+C58 55 gnd 2.080806f
+R56 54 55 2.224404
+C59 56 gnd 2.080806f
+R57 55 56 2.224404
+C60 57 gnd 2.080806f
+R58 56 57 2.224404
+C61 58 gnd 2.080806f
+R59 57 58 2.224404
+C62 59 gnd 2.080806f
+R60 58 59 2.224404
+C63 60 gnd 2.080806f
+R61 59 60 2.224404
+C64 61 gnd 2.080806f
+R62 60 61 2.224404
+C65 62 gnd 2.080806f
+R63 61 62 2.224404
+C66 63 gnd 2.080806f
+R64 62 63 2.224404
+C67 64 gnd 2.080806f
+R65 63 64 2.224404
+C68 65 gnd 2.080806f
+R66 64 65 2.224404
+C69 66 gnd 2.080806f
+R67 65 66 2.224404
+C70 67 gnd 2.080806f
+R68 66 67 2.224404
+C71 68 gnd 2.080806f
+R69 67 68 2.224404
+C72 69 gnd 2.080806f
+R70 68 69 2.224404
+C73 70 gnd 2.080806f
+R71 69 70 2.224404
+C74 71 gnd 2.080806f
+R72 70 71 2.224404
+C75 72 gnd 2.080806f
+R73 71 72 2.224404
+C76 73 gnd 2.080806f
+R74 72 73 2.224404
+C77 74 gnd 2.080806f
+R75 73 74 2.224404
+C78 75 gnd 2.080806f
+R76 74 75 2.224404
+C79 76 gnd 2.080806f
+R77 75 76 2.224404
+C80 77 gnd 2.080806f
+R78 76 77 2.224404
+C81 78 gnd 2.080806f
+R79 77 78 2.224404
+C82 79 gnd 2.080806f
+R80 78 79 2.224404
+C83 80 gnd 2.080806f
+R81 79 80 2.224404
+C84 81 gnd 2.080806f
+R82 80 81 2.224404
+C85 82 gnd 2.080806f
+R83 81 82 2.224404
+C86 83 gnd 2.080806f
+R84 82 83 2.224404
+C87 84 gnd 2.080806f
+R85 83 84 2.224404
+C88 85 gnd 2.080806f
+R86 84 85 2.224404
+C89 86 gnd 2.080806f
+R87 85 86 2.224404
+C90 87 gnd 2.080806f
+R88 86 87 2.224404
+C91 88 gnd 2.080806f
+R89 87 88 2.224404
+C92 89 gnd 2.080806f
+R90 88 89 2.224404
+C93 90 gnd 2.080806f
+R91 89 90 2.224404
+C94 91 gnd 2.080806f
+R92 90 91 2.224404
+C95 92 gnd 2.080806f
+R93 91 92 2.224404
+C96 93 gnd 2.080806f
+R94 92 93 2.224404
+C97 94 gnd 2.080806f
+R95 93 94 2.224404
+C98 95 gnd 2.080806f
+R96 94 95 2.224404
+C99 96 gnd 2.080806f
+R97 95 96 2.224404
+C100 97 gnd 2.080806f
+R98 96 97 2.224404
+C101 98 gnd 2.080806f
+R99 97 98 2.224404
+C102 99 gnd 2.080806f
+R100 98 99 2.224404
+C103 100 gnd 2.080806f
+R101 99 100 2.224404
+C104 101 gnd 2.080806f
+R102 100 101 2.224404
+C105 102 gnd 2.080806f
+R103 101 102 2.224404
+C106 103 gnd 2.080806f
+R104 102 103 2.224404
+C107 104 gnd 2.080806f
+R105 103 104 2.224404
+C108 105 gnd 2.080806f
+R106 104 105 2.224404
+C109 106 gnd 2.080806f
+R107 105 106 2.224404
+C110 107 gnd 2.080806f
+R108 106 107 2.224404
+C111 108 gnd 2.080806f
+R109 107 108 2.224404
+R110 108 g187_1 2.224404
+.ends
+
+.subckt netg10 g10_1 g10_0 g10_2 gnd
+C1  g10_1 gnd 2.080806f
+C2  g10_0 gnd 2.080806f
+C3  g10_2 gnd 2.080806f
+.ends
+
+.subckt netg182 g182_1 g182_0 g182_2 gnd
+C1  g182_1 gnd 2.080806f
+C2  g182_0 gnd 2.080806f
+C3  g182_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g182_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 2 3 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 4 5 2.224404
+C9 6 gnd 2.080806f
+R6 5 6 2.224404
+C10 7 gnd 2.080806f
+R7 6 7 2.224404
+C11 8 gnd 2.080806f
+R8 7 8 2.224404
+C12 9 gnd 2.080806f
+R9 8 9 2.224404
+C13 10 gnd 2.080806f
+R10 9 10 2.224404
+C14 11 gnd 2.080806f
+R11 11 10 2.224404
+C15 12 gnd 2.080806f
+R12 11 12 2.224404
+C16 13 gnd 2.080806f
+R13 13 12 2.224404
+C17 14 gnd 2.080806f
+R14 14 13 2.224404
+C18 15 gnd 2.080806f
+R15 15 14 2.224404
+C19 16 gnd 2.080806f
+R16 15 16 2.224404
+C20 17 gnd 2.080806f
+R17 17 16 2.224404
+C21 18 gnd 2.080806f
+R18 17 18 2.224404
+C22 19 gnd 2.080806f
+R19 19 18 2.224404
+C23 20 gnd 2.080806f
+R20 20 19 2.224404
+C24 21 gnd 2.080806f
+R21 20 21 2.224404
+C25 22 gnd 2.080806f
+R22 22 21 2.224404
+C26 23 gnd 2.080806f
+R23 22 23 2.224404
+C27 24 gnd 2.080806f
+R24 24 23 2.224404
+C28 25 gnd 2.080806f
+R25 25 24 2.224404
+C29 26 gnd 2.080806f
+R26 26 25 2.224404
+C30 27 gnd 2.080806f
+R27 27 26 2.224404
+C31 28 gnd 2.080806f
+R28 27 28 2.224404
+C32 29 gnd 2.080806f
+R29 29 28 2.224404
+C33 30 gnd 2.080806f
+R30 30 29 2.224404
+C34 31 gnd 2.080806f
+R31 31 30 2.224404
+C35 32 gnd 2.080806f
+R32 32 31 2.224404
+C36 33 gnd 2.080806f
+R33 33 32 2.224404
+C37 34 gnd 2.080806f
+R34 33 34 2.224404
+C38 35 gnd 2.080806f
+R35 35 34 2.224404
+C39 36 gnd 2.080806f
+R36 36 35 2.224404
+C40 37 gnd 2.080806f
+R37 36 37 2.224404
+C41 38 gnd 2.080806f
+R38 38 37 2.224404
+C42 39 gnd 2.080806f
+R39 39 38 2.224404
+C43 40 gnd 2.080806f
+R40 39 40 2.224404
+C44 41 gnd 2.080806f
+R41 40 41 2.224404
+C45 42 gnd 2.080806f
+R42 41 42 2.224404
+C46 43 gnd 2.080806f
+R43 43 42 2.224404
+C47 44 gnd 2.080806f
+R44 44 43 2.224404
+C48 45 gnd 2.080806f
+R45 44 45 2.224404
+C49 46 gnd 2.080806f
+R46 45 46 2.224404
+C50 47 gnd 2.080806f
+R47 47 46 2.224404
+C51 48 gnd 2.080806f
+R48 47 48 2.224404
+C52 49 gnd 2.080806f
+R49 49 48 2.224404
+C53 50 gnd 2.080806f
+R50 49 50 2.224404
+C54 51 gnd 2.080806f
+R51 50 51 2.224404
+R52 g182_2 51 2.224404
+C55 52 gnd 2.080806f
+R53 g182_0 52 2.224404
+C56 53 gnd 2.080806f
+R54 52 53 2.224404
+C57 54 gnd 2.080806f
+R55 53 54 2.224404
+C58 55 gnd 2.080806f
+R56 54 55 2.224404
+C59 56 gnd 2.080806f
+R57 55 56 2.224404
+C60 57 gnd 2.080806f
+R58 56 57 2.224404
+C61 58 gnd 2.080806f
+R59 57 58 2.224404
+C62 59 gnd 2.080806f
+R60 58 59 2.224404
+C63 60 gnd 2.080806f
+R61 59 60 2.224404
+C64 61 gnd 2.080806f
+R62 60 61 2.224404
+C65 62 gnd 2.080806f
+R63 61 62 2.224404
+C66 63 gnd 2.080806f
+R64 62 63 2.224404
+C67 64 gnd 2.080806f
+R65 63 64 2.224404
+C68 65 gnd 2.080806f
+R66 64 65 2.224404
+C69 66 gnd 2.080806f
+R67 65 66 2.224404
+C70 67 gnd 2.080806f
+R68 66 67 2.224404
+C71 68 gnd 2.080806f
+R69 67 68 2.224404
+C72 69 gnd 2.080806f
+R70 68 69 2.224404
+C73 70 gnd 2.080806f
+R71 69 70 2.224404
+C74 71 gnd 2.080806f
+R72 70 71 2.224404
+C75 72 gnd 2.080806f
+R73 71 72 2.224404
+C76 73 gnd 2.080806f
+R74 72 73 2.224404
+C77 74 gnd 2.080806f
+R75 73 74 2.224404
+C78 75 gnd 2.080806f
+R76 74 75 2.224404
+C79 76 gnd 2.080806f
+R77 75 76 2.224404
+C80 77 gnd 2.080806f
+R78 76 77 2.224404
+C81 78 gnd 2.080806f
+R79 77 78 2.224404
+C82 79 gnd 2.080806f
+R80 78 79 2.224404
+C83 80 gnd 2.080806f
+R81 79 80 2.224404
+C84 81 gnd 2.080806f
+R82 80 81 2.224404
+C85 82 gnd 2.080806f
+R83 81 82 2.224404
+C86 83 gnd 2.080806f
+R84 82 83 2.224404
+C87 84 gnd 2.080806f
+R85 83 84 2.224404
+C88 85 gnd 2.080806f
+R86 84 85 2.224404
+C89 86 gnd 2.080806f
+R87 85 86 2.224404
+C90 87 gnd 2.080806f
+R88 86 87 2.224404
+C91 88 gnd 2.080806f
+R89 87 88 2.224404
+C92 89 gnd 2.080806f
+R90 88 89 2.224404
+C93 90 gnd 2.080806f
+R91 89 90 2.224404
+C94 91 gnd 2.080806f
+R92 90 91 2.224404
+C95 92 gnd 2.080806f
+R93 91 92 2.224404
+C96 93 gnd 2.080806f
+R94 92 93 2.224404
+C97 94 gnd 2.080806f
+R95 93 94 2.224404
+C98 95 gnd 2.080806f
+R96 94 95 2.224404
+C99 96 gnd 2.080806f
+R97 95 96 2.224404
+C100 97 gnd 2.080806f
+R98 96 97 2.224404
+C101 98 gnd 2.080806f
+R99 97 98 2.224404
+C102 99 gnd 2.080806f
+R100 98 99 2.224404
+C103 100 gnd 2.080806f
+R101 99 100 2.224404
+C104 101 gnd 2.080806f
+R102 100 101 2.224404
+C105 102 gnd 2.080806f
+R103 101 102 2.224404
+C106 103 gnd 2.080806f
+R104 102 103 2.224404
+C107 104 gnd 2.080806f
+R105 103 104 2.224404
+C108 105 gnd 2.080806f
+R106 104 105 2.224404
+C109 106 gnd 2.080806f
+R107 105 106 2.224404
+C110 107 gnd 2.080806f
+R108 106 107 2.224404
+C111 108 gnd 2.080806f
+R109 107 108 2.224404
+C112 109 gnd 2.080806f
+R110 108 109 2.224404
+C113 110 gnd 2.080806f
+R111 109 110 2.224404
+C114 111 gnd 2.080806f
+R112 110 111 2.224404
+C115 112 gnd 2.080806f
+R113 111 112 2.224404
+C116 113 gnd 2.080806f
+R114 112 113 2.224404
+C117 114 gnd 2.080806f
+R115 113 114 2.224404
+C118 115 gnd 2.080806f
+R116 114 115 2.224404
+C119 116 gnd 2.080806f
+R117 115 116 2.224404
+C120 117 gnd 2.080806f
+R118 116 117 2.224404
+C121 118 gnd 2.080806f
+R119 117 118 2.224404
+C122 119 gnd 2.080806f
+R120 118 119 2.224404
+C123 120 gnd 2.080806f
+R121 119 120 2.224404
+C124 121 gnd 2.080806f
+R122 120 121 2.224404
+C125 122 gnd 2.080806f
+R123 121 122 2.224404
+C126 123 gnd 2.080806f
+R124 122 123 2.224404
+C127 124 gnd 2.080806f
+R125 123 124 2.224404
+R126 124 g182_1 2.224404
+.ends
+
+.subckt netg173 g173_2 g173_0 g173_3 g173_1 gnd
+C1  g173_2 gnd 2.080806f
+C2  g173_0 gnd 2.080806f
+C3  g173_3 gnd 2.080806f
+C4  g173_1 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g173_0 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+C7 3 gnd 2.080806f
+R3 3 2 2.224404
+C8 4 gnd 2.080806f
+R4 4 3 2.224404
+C9 5 gnd 2.080806f
+R5 5 4 2.224404
+C10 6 gnd 2.080806f
+R6 6 5 2.224404
+C11 7 gnd 2.080806f
+R7 7 6 2.224404
+C12 8 gnd 2.080806f
+R8 8 7 2.224404
+C13 9 gnd 2.080806f
+R9 9 8 2.224404
+C14 10 gnd 2.080806f
+R10 10 9 2.224404
+C15 11 gnd 2.080806f
+R11 11 10 2.224404
+C16 12 gnd 2.080806f
+R12 12 11 2.224404
+C17 13 gnd 2.080806f
+R13 13 12 2.224404
+C18 14 gnd 2.080806f
+R14 14 13 2.224404
+C19 15 gnd 2.080806f
+R15 15 14 2.224404
+C20 16 gnd 2.080806f
+R16 16 15 2.224404
+C21 17 gnd 2.080806f
+R17 17 16 2.224404
+C22 18 gnd 2.080806f
+R18 18 17 2.224404
+C23 19 gnd 2.080806f
+R19 19 18 2.224404
+C24 20 gnd 2.080806f
+R20 20 19 2.224404
+C25 21 gnd 2.080806f
+R21 21 20 2.224404
+C26 22 gnd 2.080806f
+R22 22 21 2.224404
+C27 23 gnd 2.080806f
+R23 23 22 2.224404
+C28 24 gnd 2.080806f
+R24 24 23 2.224404
+C29 25 gnd 2.080806f
+R25 25 24 2.224404
+C30 26 gnd 2.080806f
+R26 26 25 2.224404
+C31 27 gnd 2.080806f
+R27 27 26 2.224404
+C32 28 gnd 2.080806f
+R28 28 27 2.224404
+C33 29 gnd 2.080806f
+R29 29 28 2.224404
+C34 30 gnd 2.080806f
+R30 30 29 2.224404
+C35 31 gnd 2.080806f
+R31 31 30 2.224404
+C36 32 gnd 2.080806f
+R32 32 31 2.224404
+C37 33 gnd 2.080806f
+R33 33 32 2.224404
+C38 34 gnd 2.080806f
+R34 34 33 2.224404
+C39 35 gnd 2.080806f
+R35 35 34 2.224404
+C40 36 gnd 2.080806f
+R36 36 35 2.224404
+C41 37 gnd 2.080806f
+R37 37 36 2.224404
+C42 38 gnd 2.080806f
+R38 38 37 2.224404
+C43 39 gnd 2.080806f
+R39 39 38 2.224404
+C44 40 gnd 2.080806f
+R40 40 39 2.224404
+C45 41 gnd 2.080806f
+R41 41 40 2.224404
+C46 42 gnd 2.080806f
+R42 42 41 2.224404
+C47 43 gnd 2.080806f
+R43 43 42 2.224404
+C48 44 gnd 2.080806f
+R44 44 43 2.224404
+C49 45 gnd 2.080806f
+R45 45 44 2.224404
+C50 46 gnd 2.080806f
+R46 46 45 2.224404
+C51 47 gnd 2.080806f
+R47 47 46 2.224404
+C52 48 gnd 2.080806f
+R48 48 47 2.224404
+C53 49 gnd 2.080806f
+R49 49 48 2.224404
+C54 50 gnd 2.080806f
+R50 50 49 2.224404
+C55 51 gnd 2.080806f
+R51 51 50 2.224404
+C56 52 gnd 2.080806f
+R52 52 51 2.224404
+C57 53 gnd 2.080806f
+R53 53 52 2.224404
+C58 54 gnd 2.080806f
+R54 54 53 2.224404
+C59 55 gnd 2.080806f
+R55 55 54 2.224404
+C60 56 gnd 2.080806f
+R56 56 55 2.224404
+C61 57 gnd 2.080806f
+R57 57 56 2.224404
+C62 58 gnd 2.080806f
+R58 58 57 2.224404
+C63 59 gnd 2.080806f
+R59 59 58 2.224404
+C64 60 gnd 2.080806f
+R60 60 59 2.224404
+C65 61 gnd 2.080806f
+R61 61 60 2.224404
+C66 62 gnd 2.080806f
+R62 62 61 2.224404
+C67 63 gnd 2.080806f
+R63 63 62 2.224404
+C68 64 gnd 2.080806f
+R64 64 63 2.224404
+C69 65 gnd 2.080806f
+R65 65 64 2.224404
+C70 66 gnd 2.080806f
+R66 66 65 2.224404
+C71 67 gnd 2.080806f
+R67 67 66 2.224404
+C72 68 gnd 2.080806f
+R68 68 67 2.224404
+C73 69 gnd 2.080806f
+R69 69 68 2.224404
+C74 70 gnd 2.080806f
+R70 70 69 2.224404
+C75 71 gnd 2.080806f
+R71 71 70 2.224404
+C76 72 gnd 2.080806f
+R72 72 71 2.224404
+C77 73 gnd 2.080806f
+R73 73 72 2.224404
+C78 74 gnd 2.080806f
+R74 74 73 2.224404
+C79 75 gnd 2.080806f
+R75 75 74 2.224404
+C80 76 gnd 2.080806f
+R76 76 75 2.224404
+C81 77 gnd 2.080806f
+R77 77 76 2.224404
+C82 78 gnd 2.080806f
+R78 78 77 2.224404
+R79 g173_1 78 2.224404
+C83 79 gnd 2.080806f
+R80 79 g173_1 2.224404
+C84 80 gnd 2.080806f
+R81 80 79 2.224404
+C85 81 gnd 2.080806f
+R82 81 80 2.224404
+C86 82 gnd 2.080806f
+R83 82 81 2.224404
+C87 83 gnd 2.080806f
+R84 82 83 2.224404
+C88 84 gnd 2.080806f
+R85 84 83 2.224404
+C89 85 gnd 2.080806f
+R86 85 84 2.224404
+C90 86 gnd 2.080806f
+R87 86 85 2.224404
+C91 87 gnd 2.080806f
+R88 87 86 2.224404
+C92 88 gnd 2.080806f
+R89 88 87 2.224404
+C93 89 gnd 2.080806f
+R90 89 88 2.224404
+C94 90 gnd 2.080806f
+R91 90 89 2.224404
+C95 91 gnd 2.080806f
+R92 91 90 2.224404
+C96 92 gnd 2.080806f
+R93 92 91 2.224404
+C97 93 gnd 2.080806f
+R94 93 92 2.224404
+C98 94 gnd 2.080806f
+R95 94 93 2.224404
+C99 95 gnd 2.080806f
+R96 95 94 2.224404
+C100 96 gnd 2.080806f
+R97 96 95 2.224404
+C101 97 gnd 2.080806f
+R98 97 96 2.224404
+C102 98 gnd 2.080806f
+R99 98 97 2.224404
+C103 99 gnd 2.080806f
+R100 99 98 2.224404
+C104 100 gnd 2.080806f
+R101 100 99 2.224404
+C105 101 gnd 2.080806f
+R102 100 101 2.224404
+C106 102 gnd 2.080806f
+R103 102 101 2.224404
+C107 103 gnd 2.080806f
+R104 103 102 2.224404
+C108 104 gnd 2.080806f
+R105 104 103 2.224404
+C109 105 gnd 2.080806f
+R106 105 104 2.224404
+C110 106 gnd 2.080806f
+R107 106 105 2.224404
+C111 107 gnd 2.080806f
+R108 107 106 2.224404
+C112 108 gnd 2.080806f
+R109 108 107 2.224404
+C113 109 gnd 2.080806f
+R110 109 108 2.224404
+C114 110 gnd 2.080806f
+R111 109 110 2.224404
+R112 g173_3 110 2.224404
+C115 111 gnd 2.080806f
+R113 103 111 2.224404
+C116 112 gnd 2.080806f
+R114 111 112 2.224404
+C117 113 gnd 2.080806f
+R115 112 113 2.224404
+C118 114 gnd 2.080806f
+R116 113 114 2.224404
+C119 115 gnd 2.080806f
+R117 114 115 2.224404
+C120 116 gnd 2.080806f
+R118 115 116 2.224404
+C121 117 gnd 2.080806f
+R119 116 117 2.224404
+C122 118 gnd 2.080806f
+R120 117 118 2.224404
+C123 119 gnd 2.080806f
+R121 118 119 2.224404
+C124 120 gnd 2.080806f
+R122 119 120 2.224404
+C125 121 gnd 2.080806f
+R123 120 121 2.224404
+C126 122 gnd 2.080806f
+R124 121 122 2.224404
+C127 123 gnd 2.080806f
+R125 122 123 2.224404
+C128 124 gnd 2.080806f
+R126 123 124 2.224404
+C129 125 gnd 2.080806f
+R127 124 125 2.224404
+C130 126 gnd 2.080806f
+R128 125 126 2.224404
+C131 127 gnd 2.080806f
+R129 126 127 2.224404
+C132 128 gnd 2.080806f
+R130 127 128 2.224404
+R131 128 g173_2 2.224404
+.ends
+
+.subckt netg174 g174_2 g174_3 g174_1 g174_0 gnd
+C1  g174_2 gnd 2.080806f
+C2  g174_3 gnd 2.080806f
+C3  g174_1 gnd 2.080806f
+C4  g174_0 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g174_0 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+C7 3 gnd 2.080806f
+R3 3 2 2.224404
+C8 4 gnd 2.080806f
+R4 4 3 2.224404
+C9 5 gnd 2.080806f
+R5 5 4 2.224404
+C10 6 gnd 2.080806f
+R6 6 5 2.224404
+C11 7 gnd 2.080806f
+R7 7 6 2.224404
+C12 8 gnd 2.080806f
+R8 8 7 2.224404
+C13 9 gnd 2.080806f
+R9 9 8 2.224404
+C14 10 gnd 2.080806f
+R10 10 9 2.224404
+C15 11 gnd 2.080806f
+R11 11 10 2.224404
+C16 12 gnd 2.080806f
+R12 12 11 2.224404
+C17 13 gnd 2.080806f
+R13 13 12 2.224404
+C18 14 gnd 2.080806f
+R14 14 13 2.224404
+C19 15 gnd 2.080806f
+R15 15 14 2.224404
+C20 16 gnd 2.080806f
+R16 16 15 2.224404
+C21 17 gnd 2.080806f
+R17 17 16 2.224404
+C22 18 gnd 2.080806f
+R18 18 17 2.224404
+C23 19 gnd 2.080806f
+R19 19 18 2.224404
+C24 20 gnd 2.080806f
+R20 20 19 2.224404
+C25 21 gnd 2.080806f
+R21 21 20 2.224404
+C26 22 gnd 2.080806f
+R22 22 21 2.224404
+C27 23 gnd 2.080806f
+R23 23 22 2.224404
+C28 24 gnd 2.080806f
+R24 24 23 2.224404
+C29 25 gnd 2.080806f
+R25 25 24 2.224404
+C30 26 gnd 2.080806f
+R26 26 25 2.224404
+C31 27 gnd 2.080806f
+R27 27 26 2.224404
+C32 28 gnd 2.080806f
+R28 28 27 2.224404
+C33 29 gnd 2.080806f
+R29 29 28 2.224404
+C34 30 gnd 2.080806f
+R30 30 29 2.224404
+C35 31 gnd 2.080806f
+R31 31 30 2.224404
+C36 32 gnd 2.080806f
+R32 32 31 2.224404
+C37 33 gnd 2.080806f
+R33 33 32 2.224404
+C38 34 gnd 2.080806f
+R34 34 33 2.224404
+C39 35 gnd 2.080806f
+R35 35 34 2.224404
+C40 36 gnd 2.080806f
+R36 36 35 2.224404
+C41 37 gnd 2.080806f
+R37 37 36 2.224404
+C42 38 gnd 2.080806f
+R38 38 37 2.224404
+C43 39 gnd 2.080806f
+R39 39 38 2.224404
+C44 40 gnd 2.080806f
+R40 40 39 2.224404
+C45 41 gnd 2.080806f
+R41 41 40 2.224404
+C46 42 gnd 2.080806f
+R42 42 41 2.224404
+C47 43 gnd 2.080806f
+R43 43 42 2.224404
+C48 44 gnd 2.080806f
+R44 44 43 2.224404
+C49 45 gnd 2.080806f
+R45 45 44 2.224404
+C50 46 gnd 2.080806f
+R46 46 45 2.224404
+C51 47 gnd 2.080806f
+R47 47 46 2.224404
+C52 48 gnd 2.080806f
+R48 48 47 2.224404
+C53 49 gnd 2.080806f
+R49 49 48 2.224404
+C54 50 gnd 2.080806f
+R50 50 49 2.224404
+C55 51 gnd 2.080806f
+R51 51 50 2.224404
+C56 52 gnd 2.080806f
+R52 52 51 2.224404
+C57 53 gnd 2.080806f
+R53 53 52 2.224404
+C58 54 gnd 2.080806f
+R54 54 53 2.224404
+C59 55 gnd 2.080806f
+R55 55 54 2.224404
+C60 56 gnd 2.080806f
+R56 56 55 2.224404
+C61 57 gnd 2.080806f
+R57 57 56 2.224404
+C62 58 gnd 2.080806f
+R58 58 57 2.224404
+C63 59 gnd 2.080806f
+R59 59 58 2.224404
+C64 60 gnd 2.080806f
+R60 60 59 2.224404
+C65 61 gnd 2.080806f
+R61 61 60 2.224404
+C66 62 gnd 2.080806f
+R62 62 61 2.224404
+C67 63 gnd 2.080806f
+R63 63 62 2.224404
+C68 64 gnd 2.080806f
+R64 64 63 2.224404
+C69 65 gnd 2.080806f
+R65 65 64 2.224404
+C70 66 gnd 2.080806f
+R66 66 65 2.224404
+C71 67 gnd 2.080806f
+R67 67 66 2.224404
+C72 68 gnd 2.080806f
+R68 68 67 2.224404
+C73 69 gnd 2.080806f
+R69 69 68 2.224404
+C74 70 gnd 2.080806f
+R70 70 69 2.224404
+C75 71 gnd 2.080806f
+R71 71 70 2.224404
+C76 72 gnd 2.080806f
+R72 72 71 2.224404
+C77 73 gnd 2.080806f
+R73 73 72 2.224404
+R74 g174_3 73 2.224404
+C78 74 gnd 2.080806f
+R75 74 73 2.224404
+C79 75 gnd 2.080806f
+R76 75 74 2.224404
+C80 76 gnd 2.080806f
+R77 76 75 2.224404
+C81 77 gnd 2.080806f
+R78 77 76 2.224404
+C82 78 gnd 2.080806f
+R79 78 77 2.224404
+C83 79 gnd 2.080806f
+R80 79 78 2.224404
+C84 80 gnd 2.080806f
+R81 80 79 2.224404
+C85 81 gnd 2.080806f
+R82 81 80 2.224404
+C86 82 gnd 2.080806f
+R83 82 81 2.224404
+C87 83 gnd 2.080806f
+R84 83 82 2.224404
+C88 84 gnd 2.080806f
+R85 84 83 2.224404
+C89 85 gnd 2.080806f
+R86 85 84 2.224404
+C90 86 gnd 2.080806f
+R87 86 85 2.224404
+C91 87 gnd 2.080806f
+R88 87 86 2.224404
+C92 88 gnd 2.080806f
+R89 88 87 2.224404
+C93 89 gnd 2.080806f
+R90 89 88 2.224404
+C94 90 gnd 2.080806f
+R91 90 89 2.224404
+C95 91 gnd 2.080806f
+R92 91 90 2.224404
+C96 92 gnd 2.080806f
+R93 92 91 2.224404
+C97 93 gnd 2.080806f
+R94 93 92 2.224404
+C98 94 gnd 2.080806f
+R95 94 93 2.224404
+C99 95 gnd 2.080806f
+R96 95 94 2.224404
+C100 96 gnd 2.080806f
+R97 96 95 2.224404
+C101 97 gnd 2.080806f
+R98 97 96 2.224404
+C102 98 gnd 2.080806f
+R99 98 97 2.224404
+C103 99 gnd 2.080806f
+R100 99 98 2.224404
+C104 100 gnd 2.080806f
+R101 100 99 2.224404
+C105 101 gnd 2.080806f
+R102 101 100 2.224404
+C106 102 gnd 2.080806f
+R103 102 101 2.224404
+C107 103 gnd 2.080806f
+R104 103 102 2.224404
+C108 104 gnd 2.080806f
+R105 104 103 2.224404
+C109 105 gnd 2.080806f
+R106 105 104 2.224404
+R107 g174_2 105 2.224404
+C110 106 gnd 2.080806f
+R108 102 106 2.224404
+C111 107 gnd 2.080806f
+R109 106 107 2.224404
+C112 108 gnd 2.080806f
+R110 107 108 2.224404
+C113 109 gnd 2.080806f
+R111 108 109 2.224404
+C114 110 gnd 2.080806f
+R112 109 110 2.224404
+C115 111 gnd 2.080806f
+R113 110 111 2.224404
+C116 112 gnd 2.080806f
+R114 111 112 2.224404
+C117 113 gnd 2.080806f
+R115 112 113 2.224404
+C118 114 gnd 2.080806f
+R116 113 114 2.224404
+C119 115 gnd 2.080806f
+R117 114 115 2.224404
+C120 116 gnd 2.080806f
+R118 115 116 2.224404
+C121 117 gnd 2.080806f
+R119 116 117 2.224404
+C122 118 gnd 2.080806f
+R120 117 118 2.224404
+C123 119 gnd 2.080806f
+R121 118 119 2.224404
+C124 120 gnd 2.080806f
+R122 119 120 2.224404
+C125 121 gnd 2.080806f
+R123 120 121 2.224404
+C126 122 gnd 2.080806f
+R124 121 122 2.224404
+C127 123 gnd 2.080806f
+R125 122 123 2.224404
+C128 124 gnd 2.080806f
+R126 123 124 2.224404
+C129 125 gnd 2.080806f
+R127 124 125 2.224404
+R128 125 g174_1 2.224404
+.ends
+
+.subckt netg388 g388_2 g388_1 g388_0 gnd
+C1  g388_2 gnd 2.080806f
+C2  g388_1 gnd 2.080806f
+C3  g388_0 gnd 2.080806f
+R1 g388_2 g388_0 2.224404
+C4 1 gnd 2.080806f
+R2 g388_0 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+C6 3 gnd 2.080806f
+R4 3 2 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+C8 5 gnd 2.080806f
+R6 5 4 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+C10 7 gnd 2.080806f
+R8 7 6 2.224404
+C11 8 gnd 2.080806f
+R9 7 8 2.224404
+C12 9 gnd 2.080806f
+R10 9 8 2.224404
+C13 10 gnd 2.080806f
+R11 9 10 2.224404
+C14 11 gnd 2.080806f
+R12 10 11 2.224404
+C15 12 gnd 2.080806f
+R13 11 12 2.224404
+C16 13 gnd 2.080806f
+R14 12 13 2.224404
+C17 14 gnd 2.080806f
+R15 13 14 2.224404
+C18 15 gnd 2.080806f
+R16 14 15 2.224404
+C19 16 gnd 2.080806f
+R17 15 16 2.224404
+C20 17 gnd 2.080806f
+R18 16 17 2.224404
+C21 18 gnd 2.080806f
+R19 18 17 2.224404
+C22 19 gnd 2.080806f
+R20 18 19 2.224404
+C23 20 gnd 2.080806f
+R21 20 19 2.224404
+C24 21 gnd 2.080806f
+R22 20 21 2.224404
+C25 22 gnd 2.080806f
+R23 22 21 2.224404
+C26 23 gnd 2.080806f
+R24 23 22 2.224404
+C27 24 gnd 2.080806f
+R25 24 23 2.224404
+C28 25 gnd 2.080806f
+R26 25 24 2.224404
+C29 26 gnd 2.080806f
+R27 26 25 2.224404
+C30 27 gnd 2.080806f
+R28 26 27 2.224404
+C31 28 gnd 2.080806f
+R29 27 28 2.224404
+C32 29 gnd 2.080806f
+R30 28 29 2.224404
+C33 30 gnd 2.080806f
+R31 29 30 2.224404
+C34 31 gnd 2.080806f
+R32 31 30 2.224404
+C35 32 gnd 2.080806f
+R33 31 32 2.224404
+C36 33 gnd 2.080806f
+R34 32 33 2.224404
+C37 34 gnd 2.080806f
+R35 33 34 2.224404
+C38 35 gnd 2.080806f
+R36 34 35 2.224404
+C39 36 gnd 2.080806f
+R37 35 36 2.224404
+C40 37 gnd 2.080806f
+R38 37 36 2.224404
+C41 38 gnd 2.080806f
+R39 37 38 2.224404
+C42 39 gnd 2.080806f
+R40 38 39 2.224404
+C43 40 gnd 2.080806f
+R41 39 40 2.224404
+C44 41 gnd 2.080806f
+R42 40 41 2.224404
+C45 42 gnd 2.080806f
+R43 42 41 2.224404
+C46 43 gnd 2.080806f
+R44 42 43 2.224404
+C47 44 gnd 2.080806f
+R45 43 44 2.224404
+C48 45 gnd 2.080806f
+R46 45 44 2.224404
+C49 46 gnd 2.080806f
+R47 46 45 2.224404
+C50 47 gnd 2.080806f
+R48 47 46 2.224404
+C51 48 gnd 2.080806f
+R49 48 47 2.224404
+C52 49 gnd 2.080806f
+R50 48 49 2.224404
+C53 50 gnd 2.080806f
+R51 49 50 2.224404
+C54 51 gnd 2.080806f
+R52 50 51 2.224404
+C55 52 gnd 2.080806f
+R53 51 52 2.224404
+C56 53 gnd 2.080806f
+R54 53 52 2.224404
+C57 54 gnd 2.080806f
+R55 53 54 2.224404
+C58 55 gnd 2.080806f
+R56 55 54 2.224404
+C59 56 gnd 2.080806f
+R57 55 56 2.224404
+C60 57 gnd 2.080806f
+R58 56 57 2.224404
+C61 58 gnd 2.080806f
+R59 57 58 2.224404
+C62 59 gnd 2.080806f
+R60 58 59 2.224404
+C63 60 gnd 2.080806f
+R61 59 60 2.224404
+C64 61 gnd 2.080806f
+R62 60 61 2.224404
+C65 62 gnd 2.080806f
+R63 62 61 2.224404
+C66 63 gnd 2.080806f
+R64 63 62 2.224404
+C67 64 gnd 2.080806f
+R65 64 63 2.224404
+C68 65 gnd 2.080806f
+R66 64 65 2.224404
+C69 66 gnd 2.080806f
+R67 65 66 2.224404
+C70 67 gnd 2.080806f
+R68 66 67 2.224404
+C71 68 gnd 2.080806f
+R69 67 68 2.224404
+C72 69 gnd 2.080806f
+R70 68 69 2.224404
+C73 70 gnd 2.080806f
+R71 69 70 2.224404
+C74 71 gnd 2.080806f
+R72 70 71 2.224404
+C75 72 gnd 2.080806f
+R73 71 72 2.224404
+C76 73 gnd 2.080806f
+R74 72 73 2.224404
+C77 74 gnd 2.080806f
+R75 74 73 2.224404
+C78 75 gnd 2.080806f
+R76 74 75 2.224404
+C79 76 gnd 2.080806f
+R77 75 76 2.224404
+C80 77 gnd 2.080806f
+R78 76 77 2.224404
+C81 78 gnd 2.080806f
+R79 77 78 2.224404
+C82 79 gnd 2.080806f
+R80 78 79 2.224404
+C83 80 gnd 2.080806f
+R81 79 80 2.224404
+C84 81 gnd 2.080806f
+R82 80 81 2.224404
+C85 82 gnd 2.080806f
+R83 81 82 2.224404
+C86 83 gnd 2.080806f
+R84 83 82 2.224404
+C87 84 gnd 2.080806f
+R85 83 84 2.224404
+C88 85 gnd 2.080806f
+R86 84 85 2.224404
+C89 86 gnd 2.080806f
+R87 85 86 2.224404
+C90 87 gnd 2.080806f
+R88 87 86 2.224404
+C91 88 gnd 2.080806f
+R89 88 87 2.224404
+C92 89 gnd 2.080806f
+R90 89 88 2.224404
+C93 90 gnd 2.080806f
+R91 89 90 2.224404
+C94 91 gnd 2.080806f
+R92 90 91 2.224404
+C95 92 gnd 2.080806f
+R93 91 92 2.224404
+C96 93 gnd 2.080806f
+R94 93 92 2.224404
+C97 94 gnd 2.080806f
+R95 94 93 2.224404
+C98 95 gnd 2.080806f
+R96 94 95 2.224404
+C99 96 gnd 2.080806f
+R97 96 95 2.224404
+C100 97 gnd 2.080806f
+R98 96 97 2.224404
+C101 98 gnd 2.080806f
+R99 97 98 2.224404
+C102 99 gnd 2.080806f
+R100 98 99 2.224404
+C103 100 gnd 2.080806f
+R101 99 100 2.224404
+C104 101 gnd 2.080806f
+R102 101 100 2.224404
+C105 102 gnd 2.080806f
+R103 102 101 2.224404
+C106 103 gnd 2.080806f
+R104 102 103 2.224404
+C107 104 gnd 2.080806f
+R105 103 104 2.224404
+C108 105 gnd 2.080806f
+R106 105 104 2.224404
+C109 106 gnd 2.080806f
+R107 106 105 2.224404
+C110 107 gnd 2.080806f
+R108 107 106 2.224404
+C111 108 gnd 2.080806f
+R109 108 107 2.224404
+C112 109 gnd 2.080806f
+R110 109 108 2.224404
+C113 110 gnd 2.080806f
+R111 109 110 2.224404
+C114 111 gnd 2.080806f
+R112 110 111 2.224404
+C115 112 gnd 2.080806f
+R113 111 112 2.224404
+C116 113 gnd 2.080806f
+R114 112 113 2.224404
+C117 114 gnd 2.080806f
+R115 113 114 2.224404
+C118 115 gnd 2.080806f
+R116 114 115 2.224404
+R117 115 g388_1 2.224404
+.ends
+
+.subckt netg181 g181_0 g181_2 g181_1 g181_3 gnd
+C1  g181_0 gnd 2.080806f
+C2  g181_2 gnd 2.080806f
+C3  g181_1 gnd 2.080806f
+C4  g181_3 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 g181_0 1 2.224404
+C6 2 gnd 2.080806f
+R2 1 2 2.224404
+C7 3 gnd 2.080806f
+R3 2 3 2.224404
+C8 4 gnd 2.080806f
+R4 3 4 2.224404
+C9 5 gnd 2.080806f
+R5 4 5 2.224404
+C10 6 gnd 2.080806f
+R6 5 6 2.224404
+C11 7 gnd 2.080806f
+R7 6 7 2.224404
+C12 8 gnd 2.080806f
+R8 7 8 2.224404
+C13 9 gnd 2.080806f
+R9 9 8 2.224404
+C14 10 gnd 2.080806f
+R10 10 9 2.224404
+C15 11 gnd 2.080806f
+R11 11 10 2.224404
+C16 12 gnd 2.080806f
+R12 12 11 2.224404
+C17 13 gnd 2.080806f
+R13 13 12 2.224404
+C18 14 gnd 2.080806f
+R14 14 13 2.224404
+C19 15 gnd 2.080806f
+R15 15 14 2.224404
+C20 16 gnd 2.080806f
+R16 16 15 2.224404
+C21 17 gnd 2.080806f
+R17 17 16 2.224404
+C22 18 gnd 2.080806f
+R18 18 17 2.224404
+C23 19 gnd 2.080806f
+R19 19 18 2.224404
+C24 20 gnd 2.080806f
+R20 19 20 2.224404
+C25 21 gnd 2.080806f
+R21 21 20 2.224404
+C26 22 gnd 2.080806f
+R22 22 21 2.224404
+C27 23 gnd 2.080806f
+R23 23 22 2.224404
+C28 24 gnd 2.080806f
+R24 24 23 2.224404
+C29 25 gnd 2.080806f
+R25 25 24 2.224404
+C30 26 gnd 2.080806f
+R26 26 25 2.224404
+C31 27 gnd 2.080806f
+R27 27 26 2.224404
+C32 28 gnd 2.080806f
+R28 28 27 2.224404
+C33 29 gnd 2.080806f
+R29 29 28 2.224404
+C34 30 gnd 2.080806f
+R30 30 29 2.224404
+C35 31 gnd 2.080806f
+R31 31 30 2.224404
+C36 32 gnd 2.080806f
+R32 32 31 2.224404
+C37 33 gnd 2.080806f
+R33 33 32 2.224404
+C38 34 gnd 2.080806f
+R34 34 33 2.224404
+C39 35 gnd 2.080806f
+R35 35 34 2.224404
+C40 36 gnd 2.080806f
+R36 36 35 2.224404
+C41 37 gnd 2.080806f
+R37 37 36 2.224404
+C42 38 gnd 2.080806f
+R38 38 37 2.224404
+C43 39 gnd 2.080806f
+R39 39 38 2.224404
+C44 40 gnd 2.080806f
+R40 40 39 2.224404
+C45 41 gnd 2.080806f
+R41 41 40 2.224404
+C46 42 gnd 2.080806f
+R42 42 41 2.224404
+C47 43 gnd 2.080806f
+R43 43 42 2.224404
+C48 44 gnd 2.080806f
+R44 44 43 2.224404
+C49 45 gnd 2.080806f
+R45 45 44 2.224404
+C50 46 gnd 2.080806f
+R46 46 45 2.224404
+C51 47 gnd 2.080806f
+R47 47 46 2.224404
+C52 48 gnd 2.080806f
+R48 48 47 2.224404
+C53 49 gnd 2.080806f
+R49 48 49 2.224404
+C54 50 gnd 2.080806f
+R50 50 49 2.224404
+C55 51 gnd 2.080806f
+R51 51 50 2.224404
+R52 g181_1 51 2.224404
+C56 52 gnd 2.080806f
+R53 g181_1 52 2.224404
+C57 53 gnd 2.080806f
+R54 52 53 2.224404
+C58 54 gnd 2.080806f
+R55 53 54 2.224404
+C59 55 gnd 2.080806f
+R56 54 55 2.224404
+C60 56 gnd 2.080806f
+R57 55 56 2.224404
+C61 57 gnd 2.080806f
+R58 56 57 2.224404
+C62 58 gnd 2.080806f
+R59 57 58 2.224404
+C63 59 gnd 2.080806f
+R60 59 58 2.224404
+C64 60 gnd 2.080806f
+R61 59 60 2.224404
+C65 61 gnd 2.080806f
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+C66 62 gnd 2.080806f
+R63 61 62 2.224404
+C67 63 gnd 2.080806f
+R64 62 63 2.224404
+C68 64 gnd 2.080806f
+R65 63 64 2.224404
+C69 65 gnd 2.080806f
+R66 64 65 2.224404
+C70 66 gnd 2.080806f
+R67 65 66 2.224404
+C71 67 gnd 2.080806f
+R68 66 67 2.224404
+C72 68 gnd 2.080806f
+R69 67 68 2.224404
+C73 69 gnd 2.080806f
+R70 68 69 2.224404
+C74 70 gnd 2.080806f
+R71 69 70 2.224404
+C75 71 gnd 2.080806f
+R72 70 71 2.224404
+C76 72 gnd 2.080806f
+R73 72 71 2.224404
+C77 73 gnd 2.080806f
+R74 72 73 2.224404
+C78 74 gnd 2.080806f
+R75 73 74 2.224404
+C79 75 gnd 2.080806f
+R76 74 75 2.224404
+C80 76 gnd 2.080806f
+R77 75 76 2.224404
+C81 77 gnd 2.080806f
+R78 76 77 2.224404
+C82 78 gnd 2.080806f
+R79 77 78 2.224404
+C83 79 gnd 2.080806f
+R80 78 79 2.224404
+C84 80 gnd 2.080806f
+R81 80 79 2.224404
+C85 81 gnd 2.080806f
+R82 80 81 2.224404
+C86 82 gnd 2.080806f
+R83 81 82 2.224404
+C87 83 gnd 2.080806f
+R84 82 83 2.224404
+C88 84 gnd 2.080806f
+R85 84 83 2.224404
+C89 85 gnd 2.080806f
+R86 84 85 2.224404
+C90 86 gnd 2.080806f
+R87 85 86 2.224404
+C91 87 gnd 2.080806f
+R88 86 87 2.224404
+R89 87 g181_2 2.224404
+C92 88 gnd 2.080806f
+R90 g181_2 88 2.224404
+C93 89 gnd 2.080806f
+R91 88 89 2.224404
+C94 90 gnd 2.080806f
+R92 89 90 2.224404
+C95 91 gnd 2.080806f
+R93 90 91 2.224404
+C96 92 gnd 2.080806f
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+C97 93 gnd 2.080806f
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+C98 94 gnd 2.080806f
+R96 93 94 2.224404
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+R97 94 95 2.224404
+C100 96 gnd 2.080806f
+R98 95 96 2.224404
+C101 97 gnd 2.080806f
+R99 96 97 2.224404
+C102 98 gnd 2.080806f
+R100 97 98 2.224404
+C103 99 gnd 2.080806f
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+C104 100 gnd 2.080806f
+R102 99 100 2.224404
+C105 101 gnd 2.080806f
+R103 100 101 2.224404
+C106 102 gnd 2.080806f
+R104 101 102 2.224404
+C107 103 gnd 2.080806f
+R105 102 103 2.224404
+C108 104 gnd 2.080806f
+R106 103 104 2.224404
+C109 105 gnd 2.080806f
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+C110 106 gnd 2.080806f
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+C111 107 gnd 2.080806f
+R109 106 107 2.224404
+C112 108 gnd 2.080806f
+R110 107 108 2.224404
+C113 109 gnd 2.080806f
+R111 108 109 2.224404
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+R112 109 110 2.224404
+C115 111 gnd 2.080806f
+R113 110 111 2.224404
+C116 112 gnd 2.080806f
+R114 111 112 2.224404
+C117 113 gnd 2.080806f
+R115 112 113 2.224404
+C118 114 gnd 2.080806f
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+C119 115 gnd 2.080806f
+R117 114 115 2.224404
+C120 116 gnd 2.080806f
+R118 115 116 2.224404
+C121 117 gnd 2.080806f
+R119 116 117 2.224404
+C122 118 gnd 2.080806f
+R120 117 118 2.224404
+C123 119 gnd 2.080806f
+R121 118 119 2.224404
+C124 120 gnd 2.080806f
+R122 119 120 2.224404
+C125 121 gnd 2.080806f
+R123 120 121 2.224404
+C126 122 gnd 2.080806f
+R124 121 122 2.224404
+C127 123 gnd 2.080806f
+R125 122 123 2.224404
+C128 124 gnd 2.080806f
+R126 123 124 2.224404
+C129 125 gnd 2.080806f
+R127 124 125 2.224404
+C130 126 gnd 2.080806f
+R128 125 126 2.224404
+C131 127 gnd 2.080806f
+R129 126 127 2.224404
+C132 128 gnd 2.080806f
+R130 127 128 2.224404
+C133 129 gnd 2.080806f
+R131 128 129 2.224404
+C134 130 gnd 2.080806f
+R132 129 130 2.224404
+C135 131 gnd 2.080806f
+R133 130 131 2.224404
+C136 132 gnd 2.080806f
+R134 131 132 2.224404
+C137 133 gnd 2.080806f
+R135 132 133 2.224404
+C138 134 gnd 2.080806f
+R136 133 134 2.224404
+C139 135 gnd 2.080806f
+R137 134 135 2.224404
+C140 136 gnd 2.080806f
+R138 135 136 2.224404
+C141 137 gnd 2.080806f
+R139 136 137 2.224404
+C142 138 gnd 2.080806f
+R140 137 138 2.224404
+C143 139 gnd 2.080806f
+R141 138 139 2.224404
+C144 140 gnd 2.080806f
+R142 139 140 2.224404
+C145 141 gnd 2.080806f
+R143 140 141 2.224404
+C146 142 gnd 2.080806f
+R144 141 142 2.224404
+C147 143 gnd 2.080806f
+R145 142 143 2.224404
+C148 144 gnd 2.080806f
+R146 143 144 2.224404
+C149 145 gnd 2.080806f
+R147 144 145 2.224404
+C150 146 gnd 2.080806f
+R148 145 146 2.224404
+C151 147 gnd 2.080806f
+R149 146 147 2.224404
+C152 148 gnd 2.080806f
+R150 147 148 2.224404
+C153 149 gnd 2.080806f
+R151 148 149 2.224404
+C154 150 gnd 2.080806f
+R152 149 150 2.224404
+C155 151 gnd 2.080806f
+R153 150 151 2.224404
+C156 152 gnd 2.080806f
+R154 151 152 2.224404
+C157 153 gnd 2.080806f
+R155 152 153 2.224404
+C158 154 gnd 2.080806f
+R156 153 154 2.224404
+C159 155 gnd 2.080806f
+R157 154 155 2.224404
+C160 156 gnd 2.080806f
+R158 155 156 2.224404
+C161 157 gnd 2.080806f
+R159 156 157 2.224404
+C162 158 gnd 2.080806f
+R160 157 158 2.224404
+R161 158 g181_3 2.224404
+.ends
+
+.subckt netg87 g87_0 g87_1 gnd
+C1  g87_0 gnd 2.080806f
+C2  g87_1 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 g87_0 1 2.224404
+C4 2 gnd 2.080806f
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+C5 3 gnd 2.080806f
+R3 2 3 2.224404
+C6 4 gnd 2.080806f
+R4 3 4 2.224404
+C7 5 gnd 2.080806f
+R5 4 5 2.224404
+C8 6 gnd 2.080806f
+R6 5 6 2.224404
+C9 7 gnd 2.080806f
+R7 6 7 2.224404
+C10 8 gnd 2.080806f
+R8 7 8 2.224404
+C11 9 gnd 2.080806f
+R9 8 9 2.224404
+C12 10 gnd 2.080806f
+R10 9 10 2.224404
+C13 11 gnd 2.080806f
+R11 10 11 2.224404
+C14 12 gnd 2.080806f
+R12 11 12 2.224404
+C15 13 gnd 2.080806f
+R13 12 13 2.224404
+C16 14 gnd 2.080806f
+R14 13 14 2.224404
+C17 15 gnd 2.080806f
+R15 14 15 2.224404
+C18 16 gnd 2.080806f
+R16 15 16 2.224404
+C19 17 gnd 2.080806f
+R17 16 17 2.224404
+C20 18 gnd 2.080806f
+R18 17 18 2.224404
+C21 19 gnd 2.080806f
+R19 18 19 2.224404
+C22 20 gnd 2.080806f
+R20 19 20 2.224404
+C23 21 gnd 2.080806f
+R21 20 21 2.224404
+C24 22 gnd 2.080806f
+R22 21 22 2.224404
+C25 23 gnd 2.080806f
+R23 22 23 2.224404
+C26 24 gnd 2.080806f
+R24 23 24 2.224404
+C27 25 gnd 2.080806f
+R25 24 25 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 30 31 2.224404
+C34 32 gnd 2.080806f
+R32 31 32 2.224404
+C35 33 gnd 2.080806f
+R33 32 33 2.224404
+C36 34 gnd 2.080806f
+R34 33 34 2.224404
+C37 35 gnd 2.080806f
+R35 34 35 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
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+R38 37 38 2.224404
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+R39 38 39 2.224404
+C42 40 gnd 2.080806f
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+C43 41 gnd 2.080806f
+R41 40 41 2.224404
+C44 42 gnd 2.080806f
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+C45 43 gnd 2.080806f
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+C47 45 gnd 2.080806f
+R45 45 44 2.224404
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+R46 46 45 2.224404
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+C50 48 gnd 2.080806f
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+C51 49 gnd 2.080806f
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+C52 50 gnd 2.080806f
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+C53 51 gnd 2.080806f
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+R52 52 51 2.224404
+C55 53 gnd 2.080806f
+R53 53 52 2.224404
+C56 54 gnd 2.080806f
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+C57 55 gnd 2.080806f
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+C58 56 gnd 2.080806f
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+C59 57 gnd 2.080806f
+R57 57 56 2.224404
+C60 58 gnd 2.080806f
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+C61 59 gnd 2.080806f
+R59 59 58 2.224404
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+R60 60 59 2.224404
+C63 61 gnd 2.080806f
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+C64 62 gnd 2.080806f
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+C65 63 gnd 2.080806f
+R63 63 62 2.224404
+C66 64 gnd 2.080806f
+R64 64 63 2.224404
+C67 65 gnd 2.080806f
+R65 65 64 2.224404
+C68 66 gnd 2.080806f
+R66 66 65 2.224404
+C69 67 gnd 2.080806f
+R67 67 66 2.224404
+C70 68 gnd 2.080806f
+R68 68 67 2.224404
+C71 69 gnd 2.080806f
+R69 69 68 2.224404
+C72 70 gnd 2.080806f
+R70 70 69 2.224404
+C73 71 gnd 2.080806f
+R71 71 70 2.224404
+C74 72 gnd 2.080806f
+R72 72 71 2.224404
+C75 73 gnd 2.080806f
+R73 73 72 2.224404
+C76 74 gnd 2.080806f
+R74 74 73 2.224404
+C77 75 gnd 2.080806f
+R75 75 74 2.224404
+C78 76 gnd 2.080806f
+R76 76 75 2.224404
+C79 77 gnd 2.080806f
+R77 77 76 2.224404
+C80 78 gnd 2.080806f
+R78 78 77 2.224404
+C81 79 gnd 2.080806f
+R79 79 78 2.224404
+C82 80 gnd 2.080806f
+R80 80 79 2.224404
+C83 81 gnd 2.080806f
+R81 81 80 2.224404
+C84 82 gnd 2.080806f
+R82 82 81 2.224404
+C85 83 gnd 2.080806f
+R83 83 82 2.224404
+C86 84 gnd 2.080806f
+R84 84 83 2.224404
+C87 85 gnd 2.080806f
+R85 85 84 2.224404
+C88 86 gnd 2.080806f
+R86 86 85 2.224404
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+R87 87 86 2.224404
+C90 88 gnd 2.080806f
+R88 88 87 2.224404
+C91 89 gnd 2.080806f
+R89 89 88 2.224404
+C92 90 gnd 2.080806f
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+C93 91 gnd 2.080806f
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+R92 92 91 2.224404
+C95 93 gnd 2.080806f
+R93 93 92 2.224404
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+R94 94 93 2.224404
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+R95 95 94 2.224404
+C98 96 gnd 2.080806f
+R96 96 95 2.224404
+C99 97 gnd 2.080806f
+R97 97 96 2.224404
+C100 98 gnd 2.080806f
+R98 98 97 2.224404
+C101 99 gnd 2.080806f
+R99 99 98 2.224404
+C102 100 gnd 2.080806f
+R100 100 99 2.224404
+C103 101 gnd 2.080806f
+R101 101 100 2.224404
+C104 102 gnd 2.080806f
+R102 102 101 2.224404
+C105 103 gnd 2.080806f
+R103 103 102 2.224404
+C106 104 gnd 2.080806f
+R104 104 103 2.224404
+C107 105 gnd 2.080806f
+R105 105 104 2.224404
+C108 106 gnd 2.080806f
+R106 106 105 2.224404
+C109 107 gnd 2.080806f
+R107 107 106 2.224404
+C110 108 gnd 2.080806f
+R108 108 107 2.224404
+C111 109 gnd 2.080806f
+R109 109 108 2.224404
+C112 110 gnd 2.080806f
+R110 109 110 2.224404
+C113 111 gnd 2.080806f
+R111 111 110 2.224404
+C114 112 gnd 2.080806f
+R112 112 111 2.224404
+C115 113 gnd 2.080806f
+R113 113 112 2.224404
+C116 114 gnd 2.080806f
+R114 114 113 2.224404
+C117 115 gnd 2.080806f
+R115 114 115 2.224404
+C118 116 gnd 2.080806f
+R116 116 115 2.224404
+C119 117 gnd 2.080806f
+R117 117 116 2.224404
+C120 118 gnd 2.080806f
+R118 118 117 2.224404
+C121 119 gnd 2.080806f
+R119 119 118 2.224404
+C122 120 gnd 2.080806f
+R120 120 119 2.224404
+C123 121 gnd 2.080806f
+R121 121 120 2.224404
+C124 122 gnd 2.080806f
+R122 122 121 2.224404
+C125 123 gnd 2.080806f
+R123 123 122 2.224404
+C126 124 gnd 2.080806f
+R124 123 124 2.224404
+R125 g87_1 124 2.224404
+.ends
+
+.subckt netg166 g166_0 g166_2 g166_1 gnd
+C1  g166_0 gnd 2.080806f
+C2  g166_2 gnd 2.080806f
+C3  g166_1 gnd 2.080806f
+R1 g166_1 g166_0 2.224404
+C4 1 gnd 2.080806f
+R2 g166_0 1 2.224404
+C5 2 gnd 2.080806f
+R3 1 2 2.224404
+C6 3 gnd 2.080806f
+R4 2 3 2.224404
+C7 4 gnd 2.080806f
+R5 3 4 2.224404
+C8 5 gnd 2.080806f
+R6 4 5 2.224404
+C9 6 gnd 2.080806f
+R7 5 6 2.224404
+C10 7 gnd 2.080806f
+R8 6 7 2.224404
+C11 8 gnd 2.080806f
+R9 7 8 2.224404
+C12 9 gnd 2.080806f
+R10 8 9 2.224404
+C13 10 gnd 2.080806f
+R11 9 10 2.224404
+C14 11 gnd 2.080806f
+R12 10 11 2.224404
+C15 12 gnd 2.080806f
+R13 11 12 2.224404
+C16 13 gnd 2.080806f
+R14 12 13 2.224404
+C17 14 gnd 2.080806f
+R15 13 14 2.224404
+C18 15 gnd 2.080806f
+R16 14 15 2.224404
+C19 16 gnd 2.080806f
+R17 15 16 2.224404
+C20 17 gnd 2.080806f
+R18 16 17 2.224404
+C21 18 gnd 2.080806f
+R19 17 18 2.224404
+C22 19 gnd 2.080806f
+R20 18 19 2.224404
+C23 20 gnd 2.080806f
+R21 19 20 2.224404
+C24 21 gnd 2.080806f
+R22 20 21 2.224404
+C25 22 gnd 2.080806f
+R23 21 22 2.224404
+C26 23 gnd 2.080806f
+R24 22 23 2.224404
+C27 24 gnd 2.080806f
+R25 23 24 2.224404
+C28 25 gnd 2.080806f
+R26 24 25 2.224404
+C29 26 gnd 2.080806f
+R27 25 26 2.224404
+C30 27 gnd 2.080806f
+R28 26 27 2.224404
+C31 28 gnd 2.080806f
+R29 27 28 2.224404
+C32 29 gnd 2.080806f
+R30 28 29 2.224404
+C33 30 gnd 2.080806f
+R31 29 30 2.224404
+C34 31 gnd 2.080806f
+R32 30 31 2.224404
+C35 32 gnd 2.080806f
+R33 31 32 2.224404
+C36 33 gnd 2.080806f
+R34 32 33 2.224404
+C37 34 gnd 2.080806f
+R35 33 34 2.224404
+C38 35 gnd 2.080806f
+R36 34 35 2.224404
+C39 36 gnd 2.080806f
+R37 35 36 2.224404
+C40 37 gnd 2.080806f
+R38 36 37 2.224404
+C41 38 gnd 2.080806f
+R39 37 38 2.224404
+C42 39 gnd 2.080806f
+R40 38 39 2.224404
+C43 40 gnd 2.080806f
+R41 39 40 2.224404
+C44 41 gnd 2.080806f
+R42 40 41 2.224404
+C45 42 gnd 2.080806f
+R43 41 42 2.224404
+C46 43 gnd 2.080806f
+R44 42 43 2.224404
+C47 44 gnd 2.080806f
+R45 43 44 2.224404
+C48 45 gnd 2.080806f
+R46 44 45 2.224404
+C49 46 gnd 2.080806f
+R47 45 46 2.224404
+C50 47 gnd 2.080806f
+R48 46 47 2.224404
+C51 48 gnd 2.080806f
+R49 47 48 2.224404
+C52 49 gnd 2.080806f
+R50 48 49 2.224404
+C53 50 gnd 2.080806f
+R51 49 50 2.224404
+C54 51 gnd 2.080806f
+R52 50 51 2.224404
+C55 52 gnd 2.080806f
+R53 51 52 2.224404
+C56 53 gnd 2.080806f
+R54 52 53 2.224404
+C57 54 gnd 2.080806f
+R55 53 54 2.224404
+C58 55 gnd 2.080806f
+R56 54 55 2.224404
+C59 56 gnd 2.080806f
+R57 55 56 2.224404
+C60 57 gnd 2.080806f
+R58 56 57 2.224404
+C61 58 gnd 2.080806f
+R59 57 58 2.224404
+C62 59 gnd 2.080806f
+R60 58 59 2.224404
+C63 60 gnd 2.080806f
+R61 59 60 2.224404
+C64 61 gnd 2.080806f
+R62 60 61 2.224404
+C65 62 gnd 2.080806f
+R63 61 62 2.224404
+C66 63 gnd 2.080806f
+R64 62 63 2.224404
+C67 64 gnd 2.080806f
+R65 63 64 2.224404
+C68 65 gnd 2.080806f
+R66 64 65 2.224404
+C69 66 gnd 2.080806f
+R67 65 66 2.224404
+C70 67 gnd 2.080806f
+R68 66 67 2.224404
+C71 68 gnd 2.080806f
+R69 67 68 2.224404
+C72 69 gnd 2.080806f
+R70 68 69 2.224404
+C73 70 gnd 2.080806f
+R71 69 70 2.224404
+C74 71 gnd 2.080806f
+R72 70 71 2.224404
+C75 72 gnd 2.080806f
+R73 71 72 2.224404
+C76 73 gnd 2.080806f
+R74 72 73 2.224404
+C77 74 gnd 2.080806f
+R75 73 74 2.224404
+C78 75 gnd 2.080806f
+R76 74 75 2.224404
+C79 76 gnd 2.080806f
+R77 75 76 2.224404
+C80 77 gnd 2.080806f
+R78 76 77 2.224404
+C81 78 gnd 2.080806f
+R79 77 78 2.224404
+C82 79 gnd 2.080806f
+R80 78 79 2.224404
+C83 80 gnd 2.080806f
+R81 79 80 2.224404
+C84 81 gnd 2.080806f
+R82 80 81 2.224404
+C85 82 gnd 2.080806f
+R83 81 82 2.224404
+C86 83 gnd 2.080806f
+R84 82 83 2.224404
+C87 84 gnd 2.080806f
+R85 83 84 2.224404
+C88 85 gnd 2.080806f
+R86 84 85 2.224404
+C89 86 gnd 2.080806f
+R87 85 86 2.224404
+C90 87 gnd 2.080806f
+R88 86 87 2.224404
+C91 88 gnd 2.080806f
+R89 87 88 2.224404
+C92 89 gnd 2.080806f
+R90 88 89 2.224404
+C93 90 gnd 2.080806f
+R91 89 90 2.224404
+C94 91 gnd 2.080806f
+R92 90 91 2.224404
+C95 92 gnd 2.080806f
+R93 91 92 2.224404
+C96 93 gnd 2.080806f
+R94 92 93 2.224404
+C97 94 gnd 2.080806f
+R95 93 94 2.224404
+C98 95 gnd 2.080806f
+R96 94 95 2.224404
+C99 96 gnd 2.080806f
+R97 95 96 2.224404
+C100 97 gnd 2.080806f
+R98 96 97 2.224404
+C101 98 gnd 2.080806f
+R99 97 98 2.224404
+C102 99 gnd 2.080806f
+R100 98 99 2.224404
+C103 100 gnd 2.080806f
+R101 99 100 2.224404
+C104 101 gnd 2.080806f
+R102 100 101 2.224404
+C105 102 gnd 2.080806f
+R103 101 102 2.224404
+C106 103 gnd 2.080806f
+R104 102 103 2.224404
+C107 104 gnd 2.080806f
+R105 103 104 2.224404
+C108 105 gnd 2.080806f
+R106 104 105 2.224404
+C109 106 gnd 2.080806f
+R107 105 106 2.224404
+C110 107 gnd 2.080806f
+R108 106 107 2.224404
+C111 108 gnd 2.080806f
+R109 107 108 2.224404
+C112 109 gnd 2.080806f
+R110 108 109 2.224404
+C113 110 gnd 2.080806f
+R111 109 110 2.224404
+C114 111 gnd 2.080806f
+R112 110 111 2.224404
+C115 112 gnd 2.080806f
+R113 111 112 2.224404
+C116 113 gnd 2.080806f
+R114 112 113 2.224404
+C117 114 gnd 2.080806f
+R115 113 114 2.224404
+C118 115 gnd 2.080806f
+R116 114 115 2.224404
+C119 116 gnd 2.080806f
+R117 115 116 2.224404
+C120 117 gnd 2.080806f
+R118 116 117 2.224404
+R119 117 g166_2 2.224404
+.ends
+
+.subckt netg180 g180_0 g180_1 g180_2 gnd
+C1  g180_0 gnd 2.080806f
+C2  g180_1 gnd 2.080806f
+C3  g180_2 gnd 2.080806f
+C4 1 gnd 2.080806f
+R1 1 g180_0 2.224404
+C5 2 gnd 2.080806f
+R2 2 1 2.224404
+C6 3 gnd 2.080806f
+R3 3 2 2.224404
+C7 4 gnd 2.080806f
+R4 4 3 2.224404
+C8 5 gnd 2.080806f
+R5 5 4 2.224404
+C9 6 gnd 2.080806f
+R6 6 5 2.224404
+C10 7 gnd 2.080806f
+R7 7 6 2.224404
+C11 8 gnd 2.080806f
+R8 8 7 2.224404
+C12 9 gnd 2.080806f
+R9 9 8 2.224404
+C13 10 gnd 2.080806f
+R10 10 9 2.224404
+C14 11 gnd 2.080806f
+R11 11 10 2.224404
+C15 12 gnd 2.080806f
+R12 12 11 2.224404
+C16 13 gnd 2.080806f
+R13 13 12 2.224404
+C17 14 gnd 2.080806f
+R14 14 13 2.224404
+C18 15 gnd 2.080806f
+R15 15 14 2.224404
+C19 16 gnd 2.080806f
+R16 16 15 2.224404
+C20 17 gnd 2.080806f
+R17 17 16 2.224404
+C21 18 gnd 2.080806f
+R18 18 17 2.224404
+C22 19 gnd 2.080806f
+R19 19 18 2.224404
+C23 20 gnd 2.080806f
+R20 20 19 2.224404
+C24 21 gnd 2.080806f
+R21 21 20 2.224404
+C25 22 gnd 2.080806f
+R22 22 21 2.224404
+C26 23 gnd 2.080806f
+R23 23 22 2.224404
+C27 24 gnd 2.080806f
+R24 24 23 2.224404
+C28 25 gnd 2.080806f
+R25 25 24 2.224404
+C29 26 gnd 2.080806f
+R26 26 25 2.224404
+C30 27 gnd 2.080806f
+R27 27 26 2.224404
+C31 28 gnd 2.080806f
+R28 28 27 2.224404
+C32 29 gnd 2.080806f
+R29 29 28 2.224404
+C33 30 gnd 2.080806f
+R30 30 29 2.224404
+C34 31 gnd 2.080806f
+R31 31 30 2.224404
+C35 32 gnd 2.080806f
+R32 32 31 2.224404
+C36 33 gnd 2.080806f
+R33 33 32 2.224404
+C37 34 gnd 2.080806f
+R34 34 33 2.224404
+C38 35 gnd 2.080806f
+R35 35 34 2.224404
+C39 36 gnd 2.080806f
+R36 36 35 2.224404
+C40 37 gnd 2.080806f
+R37 37 36 2.224404
+C41 38 gnd 2.080806f
+R38 38 37 2.224404
+C42 39 gnd 2.080806f
+R39 39 38 2.224404
+C43 40 gnd 2.080806f
+R40 40 39 2.224404
+C44 41 gnd 2.080806f
+R41 41 40 2.224404
+C45 42 gnd 2.080806f
+R42 42 41 2.224404
+C46 43 gnd 2.080806f
+R43 43 42 2.224404
+C47 44 gnd 2.080806f
+R44 44 43 2.224404
+C48 45 gnd 2.080806f
+R45 45 44 2.224404
+C49 46 gnd 2.080806f
+R46 46 45 2.224404
+C50 47 gnd 2.080806f
+R47 47 46 2.224404
+C51 48 gnd 2.080806f
+R48 48 47 2.224404
+C52 49 gnd 2.080806f
+R49 49 48 2.224404
+C53 50 gnd 2.080806f
+R50 50 49 2.224404
+C54 51 gnd 2.080806f
+R51 51 50 2.224404
+C55 52 gnd 2.080806f
+R52 52 51 2.224404
+C56 53 gnd 2.080806f
+R53 53 52 2.224404
+C57 54 gnd 2.080806f
+R54 54 53 2.224404
+C58 55 gnd 2.080806f
+R55 55 54 2.224404
+C59 56 gnd 2.080806f
+R56 56 55 2.224404
+C60 57 gnd 2.080806f
+R57 57 56 2.224404
+C61 58 gnd 2.080806f
+R58 58 57 2.224404
+C62 59 gnd 2.080806f
+R59 59 58 2.224404
+C63 60 gnd 2.080806f
+R60 60 59 2.224404
+C64 61 gnd 2.080806f
+R61 61 60 2.224404
+C65 62 gnd 2.080806f
+R62 62 61 2.224404
+C66 63 gnd 2.080806f
+R63 63 62 2.224404
+C67 64 gnd 2.080806f
+R64 64 63 2.224404
+C68 65 gnd 2.080806f
+R65 65 64 2.224404
+C69 66 gnd 2.080806f
+R66 66 65 2.224404
+C70 67 gnd 2.080806f
+R67 67 66 2.224404
+C71 68 gnd 2.080806f
+R68 68 67 2.224404
+C72 69 gnd 2.080806f
+R69 68 69 2.224404
+C73 70 gnd 2.080806f
+R70 70 69 2.224404
+C74 71 gnd 2.080806f
+R71 71 70 2.224404
+C75 72 gnd 2.080806f
+R72 71 72 2.224404
+C76 73 gnd 2.080806f
+R73 72 73 2.224404
+C77 74 gnd 2.080806f
+R74 74 73 2.224404
+C78 75 gnd 2.080806f
+R75 75 74 2.224404
+C79 76 gnd 2.080806f
+R76 76 75 2.224404
+C80 77 gnd 2.080806f
+R77 77 76 2.224404
+C81 78 gnd 2.080806f
+R78 78 77 2.224404
+C82 79 gnd 2.080806f
+R79 79 78 2.224404
+C83 80 gnd 2.080806f
+R80 80 79 2.224404
+C84 81 gnd 2.080806f
+R81 81 80 2.224404
+C85 82 gnd 2.080806f
+R82 82 81 2.224404
+C86 83 gnd 2.080806f
+R83 83 82 2.224404
+C87 84 gnd 2.080806f
+R84 84 83 2.224404
+C88 85 gnd 2.080806f
+R85 85 84 2.224404
+R86 g180_1 85 2.224404
+C89 86 gnd 2.080806f
+R87 86 85 2.224404
+C90 87 gnd 2.080806f
+R88 87 86 2.224404
+C91 88 gnd 2.080806f
+R89 88 87 2.224404
+C92 89 gnd 2.080806f
+R90 89 88 2.224404
+C93 90 gnd 2.080806f
+R91 89 90 2.224404
+C94 91 gnd 2.080806f
+R92 91 90 2.224404
+C95 92 gnd 2.080806f
+R93 91 92 2.224404
+C96 93 gnd 2.080806f
+R94 93 92 2.224404
+C97 94 gnd 2.080806f
+R95 94 93 2.224404
+C98 95 gnd 2.080806f
+R96 94 95 2.224404
+C99 96 gnd 2.080806f
+R97 96 95 2.224404
+C100 97 gnd 2.080806f
+R98 97 96 2.224404
+C101 98 gnd 2.080806f
+R99 98 97 2.224404
+C102 99 gnd 2.080806f
+R100 99 98 2.224404
+C103 100 gnd 2.080806f
+R101 100 99 2.224404
+C104 101 gnd 2.080806f
+R102 101 100 2.224404
+C105 102 gnd 2.080806f
+R103 102 101 2.224404
+C106 103 gnd 2.080806f
+R104 102 103 2.224404
+C107 104 gnd 2.080806f
+R105 104 103 2.224404
+C108 105 gnd 2.080806f
+R106 105 104 2.224404
+C109 106 gnd 2.080806f
+R107 105 106 2.224404
+C110 107 gnd 2.080806f
+R108 107 106 2.224404
+C111 108 gnd 2.080806f
+R109 108 107 2.224404
+C112 109 gnd 2.080806f
+R110 108 109 2.224404
+C113 110 gnd 2.080806f
+R111 109 110 2.224404
+C114 111 gnd 2.080806f
+R112 110 111 2.224404
+C115 112 gnd 2.080806f
+R113 111 112 2.224404
+C116 113 gnd 2.080806f
+R114 112 113 2.224404
+C117 114 gnd 2.080806f
+R115 113 114 2.224404
+C118 115 gnd 2.080806f
+R116 114 115 2.224404
+C119 116 gnd 2.080806f
+R117 115 116 2.224404
+C120 117 gnd 2.080806f
+R118 116 117 2.224404
+C121 118 gnd 2.080806f
+R119 118 117 2.224404
+C122 119 gnd 2.080806f
+R120 118 119 2.224404
+C123 120 gnd 2.080806f
+R121 120 119 2.224404
+C124 121 gnd 2.080806f
+R122 121 120 2.224404
+C125 122 gnd 2.080806f
+R123 121 122 2.224404
+C126 123 gnd 2.080806f
+R124 123 122 2.224404
+C127 124 gnd 2.080806f
+R125 124 123 2.224404
+C128 125 gnd 2.080806f
+R126 125 124 2.224404
+C129 126 gnd 2.080806f
+R127 126 125 2.224404
+C130 127 gnd 2.080806f
+R128 126 127 2.224404
+C131 128 gnd 2.080806f
+R129 128 127 2.224404
+C132 129 gnd 2.080806f
+R130 128 129 2.224404
+C133 130 gnd 2.080806f
+R131 130 129 2.224404
+C134 131 gnd 2.080806f
+R132 131 130 2.224404
+C135 132 gnd 2.080806f
+R133 132 131 2.224404
+C136 133 gnd 2.080806f
+R134 133 132 2.224404
+C137 134 gnd 2.080806f
+R135 134 133 2.224404
+C138 135 gnd 2.080806f
+R136 134 135 2.224404
+C139 136 gnd 2.080806f
+R137 135 136 2.224404
+C140 137 gnd 2.080806f
+R138 137 136 2.224404
+C141 138 gnd 2.080806f
+R139 138 137 2.224404
+C142 139 gnd 2.080806f
+R140 138 139 2.224404
+C143 140 gnd 2.080806f
+R141 139 140 2.224404
+C144 141 gnd 2.080806f
+R142 140 141 2.224404
+C145 142 gnd 2.080806f
+R143 142 141 2.224404
+C146 143 gnd 2.080806f
+R144 142 143 2.224404
+C147 144 gnd 2.080806f
+R145 143 144 2.224404
+C148 145 gnd 2.080806f
+R146 144 145 2.224404
+C149 146 gnd 2.080806f
+R147 145 146 2.224404
+C150 147 gnd 2.080806f
+R148 146 147 2.224404
+C151 148 gnd 2.080806f
+R149 147 148 2.224404
+C152 149 gnd 2.080806f
+R150 148 149 2.224404
+C153 150 gnd 2.080806f
+R151 150 149 2.224404
+C154 151 gnd 2.080806f
+R152 150 151 2.224404
+C155 152 gnd 2.080806f
+R153 151 152 2.224404
+C156 153 gnd 2.080806f
+R154 153 152 2.224404
+C157 154 gnd 2.080806f
+R155 153 154 2.224404
+C158 155 gnd 2.080806f
+R156 155 154 2.224404
+C159 156 gnd 2.080806f
+R157 156 155 2.224404
+C160 157 gnd 2.080806f
+R158 156 157 2.224404
+C161 158 gnd 2.080806f
+R159 158 157 2.224404
+C162 159 gnd 2.080806f
+R160 159 158 2.224404
+C163 160 gnd 2.080806f
+R161 160 159 2.224404
+C164 161 gnd 2.080806f
+R162 160 161 2.224404
+C165 162 gnd 2.080806f
+R163 161 162 2.224404
+C166 163 gnd 2.080806f
+R164 162 163 2.224404
+R165 g180_2 163 2.224404
+.ends
+
+.subckt netg185 g185_0 g185_2 g185_1 g185_3 gnd
+C1  g185_0 gnd 2.080806f
+C2  g185_2 gnd 2.080806f
+C3  g185_1 gnd 2.080806f
+C4  g185_3 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g185_0 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+C7 3 gnd 2.080806f
+R3 3 2 2.224404
+C8 4 gnd 2.080806f
+R4 4 3 2.224404
+C9 5 gnd 2.080806f
+R5 5 4 2.224404
+C10 6 gnd 2.080806f
+R6 6 5 2.224404
+C11 7 gnd 2.080806f
+R7 7 6 2.224404
+C12 8 gnd 2.080806f
+R8 8 7 2.224404
+C13 9 gnd 2.080806f
+R9 9 8 2.224404
+C14 10 gnd 2.080806f
+R10 10 9 2.224404
+C15 11 gnd 2.080806f
+R11 11 10 2.224404
+C16 12 gnd 2.080806f
+R12 12 11 2.224404
+C17 13 gnd 2.080806f
+R13 13 12 2.224404
+C18 14 gnd 2.080806f
+R14 14 13 2.224404
+C19 15 gnd 2.080806f
+R15 15 14 2.224404
+C20 16 gnd 2.080806f
+R16 16 15 2.224404
+C21 17 gnd 2.080806f
+R17 17 16 2.224404
+C22 18 gnd 2.080806f
+R18 18 17 2.224404
+C23 19 gnd 2.080806f
+R19 19 18 2.224404
+C24 20 gnd 2.080806f
+R20 20 19 2.224404
+C25 21 gnd 2.080806f
+R21 21 20 2.224404
+C26 22 gnd 2.080806f
+R22 22 21 2.224404
+C27 23 gnd 2.080806f
+R23 23 22 2.224404
+C28 24 gnd 2.080806f
+R24 24 23 2.224404
+C29 25 gnd 2.080806f
+R25 25 24 2.224404
+C30 26 gnd 2.080806f
+R26 26 25 2.224404
+C31 27 gnd 2.080806f
+R27 27 26 2.224404
+C32 28 gnd 2.080806f
+R28 28 27 2.224404
+C33 29 gnd 2.080806f
+R29 29 28 2.224404
+C34 30 gnd 2.080806f
+R30 30 29 2.224404
+C35 31 gnd 2.080806f
+R31 31 30 2.224404
+C36 32 gnd 2.080806f
+R32 32 31 2.224404
+C37 33 gnd 2.080806f
+R33 33 32 2.224404
+C38 34 gnd 2.080806f
+R34 34 33 2.224404
+C39 35 gnd 2.080806f
+R35 35 34 2.224404
+C40 36 gnd 2.080806f
+R36 36 35 2.224404
+C41 37 gnd 2.080806f
+R37 37 36 2.224404
+C42 38 gnd 2.080806f
+R38 38 37 2.224404
+C43 39 gnd 2.080806f
+R39 39 38 2.224404
+C44 40 gnd 2.080806f
+R40 40 39 2.224404
+C45 41 gnd 2.080806f
+R41 41 40 2.224404
+C46 42 gnd 2.080806f
+R42 42 41 2.224404
+C47 43 gnd 2.080806f
+R43 43 42 2.224404
+C48 44 gnd 2.080806f
+R44 44 43 2.224404
+C49 45 gnd 2.080806f
+R45 45 44 2.224404
+C50 46 gnd 2.080806f
+R46 46 45 2.224404
+C51 47 gnd 2.080806f
+R47 47 46 2.224404
+C52 48 gnd 2.080806f
+R48 48 47 2.224404
+C53 49 gnd 2.080806f
+R49 49 48 2.224404
+C54 50 gnd 2.080806f
+R50 50 49 2.224404
+C55 51 gnd 2.080806f
+R51 51 50 2.224404
+C56 52 gnd 2.080806f
+R52 52 51 2.224404
+C57 53 gnd 2.080806f
+R53 53 52 2.224404
+C58 54 gnd 2.080806f
+R54 54 53 2.224404
+C59 55 gnd 2.080806f
+R55 55 54 2.224404
+C60 56 gnd 2.080806f
+R56 56 55 2.224404
+C61 57 gnd 2.080806f
+R57 57 56 2.224404
+C62 58 gnd 2.080806f
+R58 58 57 2.224404
+C63 59 gnd 2.080806f
+R59 59 58 2.224404
+C64 60 gnd 2.080806f
+R60 60 59 2.224404
+C65 61 gnd 2.080806f
+R61 61 60 2.224404
+C66 62 gnd 2.080806f
+R62 62 61 2.224404
+C67 63 gnd 2.080806f
+R63 63 62 2.224404
+C68 64 gnd 2.080806f
+R64 64 63 2.224404
+C69 65 gnd 2.080806f
+R65 65 64 2.224404
+C70 66 gnd 2.080806f
+R66 66 65 2.224404
+C71 67 gnd 2.080806f
+R67 67 66 2.224404
+C72 68 gnd 2.080806f
+R68 68 67 2.224404
+C73 69 gnd 2.080806f
+R69 69 68 2.224404
+C74 70 gnd 2.080806f
+R70 70 69 2.224404
+C75 71 gnd 2.080806f
+R71 71 70 2.224404
+C76 72 gnd 2.080806f
+R72 72 71 2.224404
+C77 73 gnd 2.080806f
+R73 73 72 2.224404
+C78 74 gnd 2.080806f
+R74 74 73 2.224404
+C79 75 gnd 2.080806f
+R75 75 74 2.224404
+C80 76 gnd 2.080806f
+R76 76 75 2.224404
+R77 g185_1 76 2.224404
+C81 77 gnd 2.080806f
+R78 77 g185_1 2.224404
+C82 78 gnd 2.080806f
+R79 78 77 2.224404
+C83 79 gnd 2.080806f
+R80 79 78 2.224404
+C84 80 gnd 2.080806f
+R81 80 79 2.224404
+C85 81 gnd 2.080806f
+R82 81 80 2.224404
+C86 82 gnd 2.080806f
+R83 82 81 2.224404
+C87 83 gnd 2.080806f
+R84 83 82 2.224404
+C88 84 gnd 2.080806f
+R85 84 83 2.224404
+C89 85 gnd 2.080806f
+R86 85 84 2.224404
+C90 86 gnd 2.080806f
+R87 86 85 2.224404
+C91 87 gnd 2.080806f
+R88 87 86 2.224404
+C92 88 gnd 2.080806f
+R89 88 87 2.224404
+C93 89 gnd 2.080806f
+R90 89 88 2.224404
+C94 90 gnd 2.080806f
+R91 90 89 2.224404
+C95 91 gnd 2.080806f
+R92 91 90 2.224404
+C96 92 gnd 2.080806f
+R93 92 91 2.224404
+C97 93 gnd 2.080806f
+R94 93 92 2.224404
+C98 94 gnd 2.080806f
+R95 94 93 2.224404
+C99 95 gnd 2.080806f
+R96 95 94 2.224404
+C100 96 gnd 2.080806f
+R97 96 95 2.224404
+C101 97 gnd 2.080806f
+R98 97 96 2.224404
+C102 98 gnd 2.080806f
+R99 98 97 2.224404
+C103 99 gnd 2.080806f
+R100 99 98 2.224404
+C104 100 gnd 2.080806f
+R101 100 99 2.224404
+C105 101 gnd 2.080806f
+R102 101 100 2.224404
+C106 102 gnd 2.080806f
+R103 102 101 2.224404
+C107 103 gnd 2.080806f
+R104 103 102 2.224404
+C108 104 gnd 2.080806f
+R105 104 103 2.224404
+C109 105 gnd 2.080806f
+R106 105 104 2.224404
+C110 106 gnd 2.080806f
+R107 106 105 2.224404
+C111 107 gnd 2.080806f
+R108 107 106 2.224404
+C112 108 gnd 2.080806f
+R109 108 107 2.224404
+C113 109 gnd 2.080806f
+R110 109 108 2.224404
+R111 g185_3 109 2.224404
+C114 110 gnd 2.080806f
+R112 110 g185_3 2.224404
+C115 111 gnd 2.080806f
+R113 111 110 2.224404
+C116 112 gnd 2.080806f
+R114 112 111 2.224404
+C117 113 gnd 2.080806f
+R115 112 113 2.224404
+C118 114 gnd 2.080806f
+R116 113 114 2.224404
+C119 115 gnd 2.080806f
+R117 114 115 2.224404
+C120 116 gnd 2.080806f
+R118 115 116 2.224404
+C121 117 gnd 2.080806f
+R119 116 117 2.224404
+C122 118 gnd 2.080806f
+R120 117 118 2.224404
+C123 119 gnd 2.080806f
+R121 118 119 2.224404
+C124 120 gnd 2.080806f
+R122 119 120 2.224404
+C125 121 gnd 2.080806f
+R123 120 121 2.224404
+C126 122 gnd 2.080806f
+R124 121 122 2.224404
+C127 123 gnd 2.080806f
+R125 122 123 2.224404
+C128 124 gnd 2.080806f
+R126 123 124 2.224404
+C129 125 gnd 2.080806f
+R127 124 125 2.224404
+C130 126 gnd 2.080806f
+R128 125 126 2.224404
+C131 127 gnd 2.080806f
+R129 126 127 2.224404
+C132 128 gnd 2.080806f
+R130 127 128 2.224404
+C133 129 gnd 2.080806f
+R131 128 129 2.224404
+C134 130 gnd 2.080806f
+R132 129 130 2.224404
+C135 131 gnd 2.080806f
+R133 130 131 2.224404
+C136 132 gnd 2.080806f
+R134 131 132 2.224404
+C137 133 gnd 2.080806f
+R135 132 133 2.224404
+C138 134 gnd 2.080806f
+R136 133 134 2.224404
+C139 135 gnd 2.080806f
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+C140 136 gnd 2.080806f
+R138 135 136 2.224404
+C141 137 gnd 2.080806f
+R139 136 137 2.224404
+C142 138 gnd 2.080806f
+R140 137 138 2.224404
+C143 139 gnd 2.080806f
+R141 138 139 2.224404
+C144 140 gnd 2.080806f
+R142 139 140 2.224404
+C145 141 gnd 2.080806f
+R143 140 141 2.224404
+C146 142 gnd 2.080806f
+R144 141 142 2.224404
+C147 143 gnd 2.080806f
+R145 142 143 2.224404
+C148 144 gnd 2.080806f
+R146 143 144 2.224404
+C149 145 gnd 2.080806f
+R147 144 145 2.224404
+C150 146 gnd 2.080806f
+R148 145 146 2.224404
+C151 147 gnd 2.080806f
+R149 146 147 2.224404
+C152 148 gnd 2.080806f
+R150 147 148 2.224404
+C153 149 gnd 2.080806f
+R151 148 149 2.224404
+C154 150 gnd 2.080806f
+R152 149 150 2.224404
+C155 151 gnd 2.080806f
+R153 150 151 2.224404
+C156 152 gnd 2.080806f
+R154 151 152 2.224404
+C157 153 gnd 2.080806f
+R155 153 152 2.224404
+C158 154 gnd 2.080806f
+R156 154 153 2.224404
+C159 155 gnd 2.080806f
+R157 155 154 2.224404
+C160 156 gnd 2.080806f
+R158 156 155 2.224404
+C161 157 gnd 2.080806f
+R159 157 156 2.224404
+C162 158 gnd 2.080806f
+R160 158 157 2.224404
+C163 159 gnd 2.080806f
+R161 158 159 2.224404
+C164 160 gnd 2.080806f
+R162 159 160 2.224404
+C165 161 gnd 2.080806f
+R163 160 161 2.224404
+C166 162 gnd 2.080806f
+R164 161 162 2.224404
+C167 163 gnd 2.080806f
+R165 162 163 2.224404
+C168 164 gnd 2.080806f
+R166 163 164 2.224404
+C169 165 gnd 2.080806f
+R167 164 165 2.224404
+C170 166 gnd 2.080806f
+R168 165 166 2.224404
+C171 167 gnd 2.080806f
+R169 166 167 2.224404
+C172 168 gnd 2.080806f
+R170 167 168 2.224404
+C173 169 gnd 2.080806f
+R171 168 169 2.224404
+C174 170 gnd 2.080806f
+R172 169 170 2.224404
+C175 171 gnd 2.080806f
+R173 170 171 2.224404
+C176 172 gnd 2.080806f
+R174 171 172 2.224404
+C177 173 gnd 2.080806f
+R175 172 173 2.224404
+C178 174 gnd 2.080806f
+R176 173 174 2.224404
+C179 175 gnd 2.080806f
+R177 174 175 2.224404
+C180 176 gnd 2.080806f
+R178 175 176 2.224404
+C181 177 gnd 2.080806f
+R179 176 177 2.224404
+R180 177 g185_2 2.224404
+.ends
+
+.subckt netg184 g184_0 g184_3 g184_2 g184_1 gnd
+C1  g184_0 gnd 2.080806f
+C2  g184_3 gnd 2.080806f
+C3  g184_2 gnd 2.080806f
+C4  g184_1 gnd 2.080806f
+C5 1 gnd 2.080806f
+R1 1 g184_0 2.224404
+C6 2 gnd 2.080806f
+R2 2 1 2.224404
+C7 3 gnd 2.080806f
+R3 3 2 2.224404
+C8 4 gnd 2.080806f
+R4 4 3 2.224404
+C9 5 gnd 2.080806f
+R5 5 4 2.224404
+C10 6 gnd 2.080806f
+R6 6 5 2.224404
+C11 7 gnd 2.080806f
+R7 7 6 2.224404
+C12 8 gnd 2.080806f
+R8 8 7 2.224404
+C13 9 gnd 2.080806f
+R9 9 8 2.224404
+C14 10 gnd 2.080806f
+R10 10 9 2.224404
+C15 11 gnd 2.080806f
+R11 11 10 2.224404
+C16 12 gnd 2.080806f
+R12 12 11 2.224404
+C17 13 gnd 2.080806f
+R13 13 12 2.224404
+C18 14 gnd 2.080806f
+R14 14 13 2.224404
+C19 15 gnd 2.080806f
+R15 15 14 2.224404
+C20 16 gnd 2.080806f
+R16 16 15 2.224404
+C21 17 gnd 2.080806f
+R17 16 17 2.224404
+C22 18 gnd 2.080806f
+R18 17 18 2.224404
+C23 19 gnd 2.080806f
+R19 18 19 2.224404
+C24 20 gnd 2.080806f
+R20 20 19 2.224404
+C25 21 gnd 2.080806f
+R21 20 21 2.224404
+C26 22 gnd 2.080806f
+R22 21 22 2.224404
+C27 23 gnd 2.080806f
+R23 22 23 2.224404
+C28 24 gnd 2.080806f
+R24 24 23 2.224404
+C29 25 gnd 2.080806f
+R25 24 25 2.224404
+C30 26 gnd 2.080806f
+R26 26 25 2.224404
+C31 27 gnd 2.080806f
+R27 26 27 2.224404
+C32 28 gnd 2.080806f
+R28 28 27 2.224404
+C33 29 gnd 2.080806f
+R29 29 28 2.224404
+C34 30 gnd 2.080806f
+R30 30 29 2.224404
+C35 31 gnd 2.080806f
+R31 30 31 2.224404
+C36 32 gnd 2.080806f
+R32 32 31 2.224404
+C37 33 gnd 2.080806f
+R33 33 32 2.224404
+C38 34 gnd 2.080806f
+R34 34 33 2.224404
+C39 35 gnd 2.080806f
+R35 35 34 2.224404
+C40 36 gnd 2.080806f
+R36 36 35 2.224404
+C41 37 gnd 2.080806f
+R37 37 36 2.224404
+C42 38 gnd 2.080806f
+R38 38 37 2.224404
+C43 39 gnd 2.080806f
+R39 39 38 2.224404
+C44 40 gnd 2.080806f
+R40 40 39 2.224404
+C45 41 gnd 2.080806f
+R41 41 40 2.224404
+C46 42 gnd 2.080806f
+R42 42 41 2.224404
+C47 43 gnd 2.080806f
+R43 43 42 2.224404
+C48 44 gnd 2.080806f
+R44 44 43 2.224404
+C49 45 gnd 2.080806f
+R45 45 44 2.224404
+C50 46 gnd 2.080806f
+R46 46 45 2.224404
+C51 47 gnd 2.080806f
+R47 47 46 2.224404
+C52 48 gnd 2.080806f
+R48 48 47 2.224404
+C53 49 gnd 2.080806f
+R49 49 48 2.224404
+C54 50 gnd 2.080806f
+R50 50 49 2.224404
+C55 51 gnd 2.080806f
+R51 51 50 2.224404
+C56 52 gnd 2.080806f
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+C57 53 gnd 2.080806f
+R53 53 52 2.224404
+C58 54 gnd 2.080806f
+R54 54 53 2.224404
+C59 55 gnd 2.080806f
+R55 55 54 2.224404
+C60 56 gnd 2.080806f
+R56 56 55 2.224404
+C61 57 gnd 2.080806f
+R57 57 56 2.224404
+C62 58 gnd 2.080806f
+R58 57 58 2.224404
+C63 59 gnd 2.080806f
+R59 59 58 2.224404
+C64 60 gnd 2.080806f
+R60 60 59 2.224404
+C65 61 gnd 2.080806f
+R61 61 60 2.224404
+C66 62 gnd 2.080806f
+R62 62 61 2.224404
+C67 63 gnd 2.080806f
+R63 63 62 2.224404
+C68 64 gnd 2.080806f
+R64 64 63 2.224404
+C69 65 gnd 2.080806f
+R65 65 64 2.224404
+C70 66 gnd 2.080806f
+R66 66 65 2.224404
+C71 67 gnd 2.080806f
+R67 67 66 2.224404
+C72 68 gnd 2.080806f
+R68 68 67 2.224404
+C73 69 gnd 2.080806f
+R69 69 68 2.224404
+C74 70 gnd 2.080806f
+R70 70 69 2.224404
+C75 71 gnd 2.080806f
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+R72 g184_2 71 2.224404
+C76 72 gnd 2.080806f
+R73 g184_2 72 2.224404
+C77 73 gnd 2.080806f
+R74 72 73 2.224404
+C78 74 gnd 2.080806f
+R75 73 74 2.224404
+C79 75 gnd 2.080806f
+R76 74 75 2.224404
+C80 76 gnd 2.080806f
+R77 75 76 2.224404
+C81 77 gnd 2.080806f
+R78 76 77 2.224404
+C82 78 gnd 2.080806f
+R79 77 78 2.224404
+C83 79 gnd 2.080806f
+R80 78 79 2.224404
+C84 80 gnd 2.080806f
+R81 79 80 2.224404
+C85 81 gnd 2.080806f
+R82 80 81 2.224404
+C86 82 gnd 2.080806f
+R83 81 82 2.224404
+C87 83 gnd 2.080806f
+R84 82 83 2.224404
+C88 84 gnd 2.080806f
+R85 83 84 2.224404
+C89 85 gnd 2.080806f
+R86 84 85 2.224404
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+R87 85 86 2.224404
+C91 87 gnd 2.080806f
+R88 86 87 2.224404
+C92 88 gnd 2.080806f
+R89 87 88 2.224404
+C93 89 gnd 2.080806f
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+C94 90 gnd 2.080806f
+R91 89 90 2.224404
+C95 91 gnd 2.080806f
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+C96 92 gnd 2.080806f
+R93 91 92 2.224404
+C97 93 gnd 2.080806f
+R94 92 93 2.224404
+C98 94 gnd 2.080806f
+R95 93 94 2.224404
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+R96 94 95 2.224404
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+R97 95 96 2.224404
+C101 97 gnd 2.080806f
+R98 96 97 2.224404
+C102 98 gnd 2.080806f
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+C103 99 gnd 2.080806f
+R100 98 99 2.224404
+C104 100 gnd 2.080806f
+R101 99 100 2.224404
+C105 101 gnd 2.080806f
+R102 100 101 2.224404
+C106 102 gnd 2.080806f
+R103 101 102 2.224404
+C107 103 gnd 2.080806f
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+R105 103 g184_1 2.224404
+C108 104 gnd 2.080806f
+R106 g184_1 104 2.224404
+C109 105 gnd 2.080806f
+R107 104 105 2.224404
+C110 106 gnd 2.080806f
+R108 105 106 2.224404
+C111 107 gnd 2.080806f
+R109 106 107 2.224404
+C112 108 gnd 2.080806f
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+C113 109 gnd 2.080806f
+R111 108 109 2.224404
+C114 110 gnd 2.080806f
+R112 109 110 2.224404
+C115 111 gnd 2.080806f
+R113 110 111 2.224404
+C116 112 gnd 2.080806f
+R114 111 112 2.224404
+C117 113 gnd 2.080806f
+R115 112 113 2.224404
+C118 114 gnd 2.080806f
+R116 113 114 2.224404
+C119 115 gnd 2.080806f
+R117 114 115 2.224404
+C120 116 gnd 2.080806f
+R118 115 116 2.224404
+C121 117 gnd 2.080806f
+R119 116 117 2.224404
+C122 118 gnd 2.080806f
+R120 117 118 2.224404
+C123 119 gnd 2.080806f
+R121 118 119 2.224404
+C124 120 gnd 2.080806f
+R122 119 120 2.224404
+C125 121 gnd 2.080806f
+R123 120 121 2.224404
+C126 122 gnd 2.080806f
+R124 121 122 2.224404
+C127 123 gnd 2.080806f
+R125 122 123 2.224404
+C128 124 gnd 2.080806f
+R126 123 124 2.224404
+C129 125 gnd 2.080806f
+R127 124 125 2.224404
+C130 126 gnd 2.080806f
+R128 125 126 2.224404
+C131 127 gnd 2.080806f
+R129 126 127 2.224404
+C132 128 gnd 2.080806f
+R130 127 128 2.224404
+C133 129 gnd 2.080806f
+R131 128 129 2.224404
+C134 130 gnd 2.080806f
+R132 129 130 2.224404
+C135 131 gnd 2.080806f
+R133 130 131 2.224404
+C136 132 gnd 2.080806f
+R134 131 132 2.224404
+C137 133 gnd 2.080806f
+R135 132 133 2.224404
+C138 134 gnd 2.080806f
+R136 133 134 2.224404
+C139 135 gnd 2.080806f
+R137 134 135 2.224404
+C140 136 gnd 2.080806f
+R138 135 136 2.224404
+C141 137 gnd 2.080806f
+R139 136 137 2.224404
+C142 138 gnd 2.080806f
+R140 137 138 2.224404
+C143 139 gnd 2.080806f
+R141 138 139 2.224404
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+R142 139 140 2.224404
+C145 141 gnd 2.080806f
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+C146 142 gnd 2.080806f
+R144 141 142 2.224404
+C147 143 gnd 2.080806f
+R145 142 143 2.224404
+C148 144 gnd 2.080806f
+R146 143 144 2.224404
+C149 145 gnd 2.080806f
+R147 144 145 2.224404
+C150 146 gnd 2.080806f
+R148 145 146 2.224404
+C151 147 gnd 2.080806f
+R149 146 147 2.224404
+C152 148 gnd 2.080806f
+R150 147 148 2.224404
+C153 149 gnd 2.080806f
+R151 148 149 2.224404
+C154 150 gnd 2.080806f
+R152 149 150 2.224404
+C155 151 gnd 2.080806f
+R153 150 151 2.224404
+C156 152 gnd 2.080806f
+R154 151 152 2.224404
+C157 153 gnd 2.080806f
+R155 152 153 2.224404
+C158 154 gnd 2.080806f
+R156 153 154 2.224404
+C159 155 gnd 2.080806f
+R157 154 155 2.224404
+C160 156 gnd 2.080806f
+R158 155 156 2.224404
+C161 157 gnd 2.080806f
+R159 156 157 2.224404
+C162 158 gnd 2.080806f
+R160 157 158 2.224404
+C163 159 gnd 2.080806f
+R161 158 159 2.224404
+C164 160 gnd 2.080806f
+R162 159 160 2.224404
+C165 161 gnd 2.080806f
+R163 160 161 2.224404
+C166 162 gnd 2.080806f
+R164 161 162 2.224404
+C167 163 gnd 2.080806f
+R165 162 163 2.224404
+C168 164 gnd 2.080806f
+R166 163 164 2.224404
+C169 165 gnd 2.080806f
+R167 164 165 2.224404
+C170 166 gnd 2.080806f
+R168 165 166 2.224404
+C171 167 gnd 2.080806f
+R169 166 167 2.224404
+C172 168 gnd 2.080806f
+R170 167 168 2.224404
+C173 169 gnd 2.080806f
+R171 168 169 2.224404
+C174 170 gnd 2.080806f
+R172 169 170 2.224404
+C175 171 gnd 2.080806f
+R173 170 171 2.224404
+C176 172 gnd 2.080806f
+R174 171 172 2.224404
+C177 173 gnd 2.080806f
+R175 172 173 2.224404
+C178 174 gnd 2.080806f
+R176 173 174 2.224404
+C179 175 gnd 2.080806f
+R177 174 175 2.224404
+C180 176 gnd 2.080806f
+R178 175 176 2.224404
+C181 177 gnd 2.080806f
+R179 176 177 2.224404
+C182 178 gnd 2.080806f
+R180 177 178 2.224404
+C183 179 gnd 2.080806f
+R181 178 179 2.224404
+C184 180 gnd 2.080806f
+R182 179 180 2.224404
+C185 181 gnd 2.080806f
+R183 180 181 2.224404
+C186 182 gnd 2.080806f
+R184 181 182 2.224404
+R185 182 g184_3 2.224404
+.ends
+
+.subckt netg165 g165_1 g165_0 gnd
+C1  g165_1 gnd 2.080806f
+C2  g165_0 gnd 2.080806f
+C3 1 gnd 2.080806f
+R1 1 g165_0 2.224404
+C4 2 gnd 2.080806f
+R2 2 1 2.224404
+C5 3 gnd 2.080806f
+R3 3 2 2.224404
+C6 4 gnd 2.080806f
+R4 4 3 2.224404
+C7 5 gnd 2.080806f
+R5 5 4 2.224404
+C8 6 gnd 2.080806f
+R6 6 5 2.224404
+C9 7 gnd 2.080806f
+R7 7 6 2.224404
+C10 8 gnd 2.080806f
+R8 8 7 2.224404
+C11 9 gnd 2.080806f
+R9 9 8 2.224404
+C12 10 gnd 2.080806f
+R10 10 9 2.224404
+C13 11 gnd 2.080806f
+R11 11 10 2.224404
+C14 12 gnd 2.080806f
+R12 12 11 2.224404
+C15 13 gnd 2.080806f
+R13 13 12 2.224404
+C16 14 gnd 2.080806f
+R14 14 13 2.224404
+C17 15 gnd 2.080806f
+R15 15 14 2.224404
+C18 16 gnd 2.080806f
+R16 16 15 2.224404
+C19 17 gnd 2.080806f
+R17 17 16 2.224404
+C20 18 gnd 2.080806f
+R18 18 17 2.224404
+C21 19 gnd 2.080806f
+R19 19 18 2.224404
+C22 20 gnd 2.080806f
+R20 20 19 2.224404
+C23 21 gnd 2.080806f
+R21 21 20 2.224404
+C24 22 gnd 2.080806f
+R22 22 21 2.224404
+C25 23 gnd 2.080806f
+R23 23 22 2.224404
+C26 24 gnd 2.080806f
+R24 24 23 2.224404
+C27 25 gnd 2.080806f
+R25 25 24 2.224404
+C28 26 gnd 2.080806f
+R26 26 25 2.224404
+C29 27 gnd 2.080806f
+R27 27 26 2.224404
+C30 28 gnd 2.080806f
+R28 28 27 2.224404
+C31 29 gnd 2.080806f
+R29 29 28 2.224404
+C32 30 gnd 2.080806f
+R30 30 29 2.224404
+C33 31 gnd 2.080806f
+R31 31 30 2.224404
+C34 32 gnd 2.080806f
+R32 32 31 2.224404
+C35 33 gnd 2.080806f
+R33 33 32 2.224404
+C36 34 gnd 2.080806f
+R34 34 33 2.224404
+C37 35 gnd 2.080806f
+R35 35 34 2.224404
+C38 36 gnd 2.080806f
+R36 36 35 2.224404
+C39 37 gnd 2.080806f
+R37 37 36 2.224404
+C40 38 gnd 2.080806f
+R38 38 37 2.224404
+C41 39 gnd 2.080806f
+R39 39 38 2.224404
+C42 40 gnd 2.080806f
+R40 40 39 2.224404
+C43 41 gnd 2.080806f
+R41 41 40 2.224404
+C44 42 gnd 2.080806f
+R42 42 41 2.224404
+C45 43 gnd 2.080806f
+R43 43 42 2.224404
+C46 44 gnd 2.080806f
+R44 44 43 2.224404
+C47 45 gnd 2.080806f
+R45 45 44 2.224404
+C48 46 gnd 2.080806f
+R46 46 45 2.224404
+C49 47 gnd 2.080806f
+R47 47 46 2.224404
+C50 48 gnd 2.080806f
+R48 48 47 2.224404
+C51 49 gnd 2.080806f
+R49 49 48 2.224404
+C52 50 gnd 2.080806f
+R50 50 49 2.224404
+C53 51 gnd 2.080806f
+R51 51 50 2.224404
+C54 52 gnd 2.080806f
+R52 52 51 2.224404
+C55 53 gnd 2.080806f
+R53 53 52 2.224404
+C56 54 gnd 2.080806f
+R54 54 53 2.224404
+C57 55 gnd 2.080806f
+R55 55 54 2.224404
+C58 56 gnd 2.080806f
+R56 56 55 2.224404
+C59 57 gnd 2.080806f
+R57 57 56 2.224404
+C60 58 gnd 2.080806f
+R58 58 57 2.224404
+C61 59 gnd 2.080806f
+R59 59 58 2.224404
+C62 60 gnd 2.080806f
+R60 60 59 2.224404
+C63 61 gnd 2.080806f
+R61 61 60 2.224404
+C64 62 gnd 2.080806f
+R62 62 61 2.224404
+C65 63 gnd 2.080806f
+R63 63 62 2.224404
+C66 64 gnd 2.080806f
+R64 64 63 2.224404
+C67 65 gnd 2.080806f
+R65 65 64 2.224404
+C68 66 gnd 2.080806f
+R66 66 65 2.224404
+C69 67 gnd 2.080806f
+R67 67 66 2.224404
+C70 68 gnd 2.080806f
+R68 68 67 2.224404
+C71 69 gnd 2.080806f
+R69 69 68 2.224404
+C72 70 gnd 2.080806f
+R70 70 69 2.224404
+C73 71 gnd 2.080806f
+R71 71 70 2.224404
+C74 72 gnd 2.080806f
+R72 72 71 2.224404
+C75 73 gnd 2.080806f
+R73 73 72 2.224404
+C76 74 gnd 2.080806f
+R74 74 73 2.224404
+C77 75 gnd 2.080806f
+R75 75 74 2.224404
+C78 76 gnd 2.080806f
+R76 76 75 2.224404
+C79 77 gnd 2.080806f
+R77 77 76 2.224404
+C80 78 gnd 2.080806f
+R78 78 77 2.224404
+C81 79 gnd 2.080806f
+R79 79 78 2.224404
+C82 80 gnd 2.080806f
+R80 80 79 2.224404
+C83 81 gnd 2.080806f
+R81 81 80 2.224404
+C84 82 gnd 2.080806f
+R82 82 81 2.224404
+C85 83 gnd 2.080806f
+R83 83 82 2.224404
+C86 84 gnd 2.080806f
+R84 84 83 2.224404
+C87 85 gnd 2.080806f
+R85 85 84 2.224404
+C88 86 gnd 2.080806f
+R86 86 85 2.224404
+C89 87 gnd 2.080806f
+R87 87 86 2.224404
+C90 88 gnd 2.080806f
+R88 88 87 2.224404
+C91 89 gnd 2.080806f
+R89 89 88 2.224404
+C92 90 gnd 2.080806f
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+C93 91 gnd 2.080806f
+R91 91 90 2.224404
+C94 92 gnd 2.080806f
+R92 92 91 2.224404
+C95 93 gnd 2.080806f
+R93 93 92 2.224404
+C96 94 gnd 2.080806f
+R94 94 93 2.224404
+C97 95 gnd 2.080806f
+R95 95 94 2.224404
+C98 96 gnd 2.080806f
+R96 96 95 2.224404
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+R97 97 96 2.224404
+C100 98 gnd 2.080806f
+R98 98 97 2.224404
+C101 99 gnd 2.080806f
+R99 99 98 2.224404
+C102 100 gnd 2.080806f
+R100 100 99 2.224404
+C103 101 gnd 2.080806f
+R101 101 100 2.224404
+C104 102 gnd 2.080806f
+R102 102 101 2.224404
+C105 103 gnd 2.080806f
+R103 103 102 2.224404
+C106 104 gnd 2.080806f
+R104 104 103 2.224404
+C107 105 gnd 2.080806f
+R105 105 104 2.224404
+C108 106 gnd 2.080806f
+R106 106 105 2.224404
+C109 107 gnd 2.080806f
+R107 107 106 2.224404
+C110 108 gnd 2.080806f
+R108 108 107 2.224404
+C111 109 gnd 2.080806f
+R109 109 108 2.224404
+C112 110 gnd 2.080806f
+R110 110 109 2.224404
+C113 111 gnd 2.080806f
+R111 111 110 2.224404
+C114 112 gnd 2.080806f
+R112 112 111 2.224404
+C115 113 gnd 2.080806f
+R113 113 112 2.224404
+C116 114 gnd 2.080806f
+R114 114 113 2.224404
+C117 115 gnd 2.080806f
+R115 115 114 2.224404
+C118 116 gnd 2.080806f
+R116 116 115 2.224404
+C119 117 gnd 2.080806f
+R117 117 116 2.224404
+C120 118 gnd 2.080806f
+R118 118 117 2.224404
+C121 119 gnd 2.080806f
+R119 119 118 2.224404
+C122 120 gnd 2.080806f
+R120 120 119 2.224404
+C123 121 gnd 2.080806f
+R121 121 120 2.224404
+C124 122 gnd 2.080806f
+R122 122 121 2.224404
+C125 123 gnd 2.080806f
+R123 123 122 2.224404
+C126 124 gnd 2.080806f
+R124 124 123 2.224404
+C127 125 gnd 2.080806f
+R125 125 124 2.224404
+C128 126 gnd 2.080806f
+R126 126 125 2.224404
+C129 127 gnd 2.080806f
+R127 127 126 2.224404
+C130 128 gnd 2.080806f
+R128 128 127 2.224404
+C131 129 gnd 2.080806f
+R129 129 128 2.224404
+C132 130 gnd 2.080806f
+R130 130 129 2.224404
+C133 131 gnd 2.080806f
+R131 131 130 2.224404
+C134 132 gnd 2.080806f
+R132 132 131 2.224404
+C135 133 gnd 2.080806f
+R133 133 132 2.224404
+C136 134 gnd 2.080806f
+R134 134 133 2.224404
+C137 135 gnd 2.080806f
+R135 135 134 2.224404
+C138 136 gnd 2.080806f
+R136 136 135 2.224404
+C139 137 gnd 2.080806f
+R137 137 136 2.224404
+C140 138 gnd 2.080806f
+R138 138 137 2.224404
+C141 139 gnd 2.080806f
+R139 139 138 2.224404
+C142 140 gnd 2.080806f
+R140 140 139 2.224404
+C143 141 gnd 2.080806f
+R141 141 140 2.224404
+C144 142 gnd 2.080806f
+R142 142 141 2.224404
+C145 143 gnd 2.080806f
+R143 143 142 2.224404
+C146 144 gnd 2.080806f
+R144 144 143 2.224404
+C147 145 gnd 2.080806f
+R145 145 144 2.224404
+C148 146 gnd 2.080806f
+R146 146 145 2.224404
+C149 147 gnd 2.080806f
+R147 147 146 2.224404
+C150 148 gnd 2.080806f
+R148 148 147 2.224404
+C151 149 gnd 2.080806f
+R149 149 148 2.224404
+C152 150 gnd 2.080806f
+R150 150 149 2.224404
+C153 151 gnd 2.080806f
+R151 151 150 2.224404
+C154 152 gnd 2.080806f
+R152 152 151 2.224404
+C155 153 gnd 2.080806f
+R153 153 152 2.224404
+C156 154 gnd 2.080806f
+R154 154 153 2.224404
+C157 155 gnd 2.080806f
+R155 155 154 2.224404
+C158 156 gnd 2.080806f
+R156 156 155 2.224404
+C159 157 gnd 2.080806f
+R157 157 156 2.224404
+C160 158 gnd 2.080806f
+R158 158 157 2.224404
+C161 159 gnd 2.080806f
+R159 159 158 2.224404
+C162 160 gnd 2.080806f
+R160 160 159 2.224404
+C163 161 gnd 2.080806f
+R161 161 160 2.224404
+R162 g165_1 161 2.224404
+.ends
+
+* the call of the nets sub circuits:
+
+X1 x81_1 x81_0 0 netx81
+X2 g4055_1 g4055_0 0 netg4055
+X3 g6531_1 g6531_0 0 netg6531
+X4 g1255_0 g1255_1 0 netg1255
+X5 g5391_0 g5391_1 0 netg5391
+X6 g4749_0 g4749_1 0 netg4749
+X7 g7003_0 g7003_1 0 netg7003
+X8 x242_1 x242_0 0 netx242
+X9 g6733_0 g6733_1 0 netg6733
+X10 g404_2 g404_0 0 netg404
+X11 g2934_1 g2934_0 0 netg2934
+X12 g6397_0 g6397_1 0 netg6397
+X13 g7266_1 g7266_0 0 netg7266
+X14 g5784_0 g5784_1 0 netg5784
+X15 g6546_1 g6546_2 0 netg6546
+X16 g6937_1 g6937_0 0 netg6937
+X17 g2929_1 g2929_0 0 netg2929
+X18 g4099_1 g4099_0 0 netg4099
+X19 g3537_0 g3537_1 0 netg3537
+X20 g4245_0 g4245_1 0 netg4245
+X21 g5584_1 g5584_0 0 netg5584
+X22 g4531_1 g4531_0 0 netg4531
+X23 g3903_1 g3903_0 0 netg3903
+X24 g7164_1 g7164_0 0 netg7164
+X25 g1998_0 g1998_1 0 netg1998
+X26 x461_0 x461_1 0 netx461
+X27 g4257_0 g4257_1 0 netg4257
+X28 g961_2 g961_1 0 netg961
+X29 g2816_0 g2816_1 0 netg2816
+X30 g6439_1 g6439_0 0 netg6439
+X31 g6979_1 g6979_0 0 netg6979
+X32 g6213_0 g6213_1 0 netg6213
+X33 g7268_1 g7268_0 0 netg7268
+X34 g1933_1 g1933_0 0 netg1933
+X35 g3986_0 g3986_1 0 netg3986
+X36 g2916_1 g2916_0 0 netg2916
+X37 g6553_0 g6553_1 0 netg6553
+X38 g2788_0 g2788_1 0 netg2788
+X39 g5960_0 g5960_1 0 netg5960
+X40 g3549_0 g3549_1 0 netg3549
+X41 g6206_0 g6206_1 0 netg6206
+X42 g1874_2 g1874_1 0 netg1874
+X43 g6916_1 g6916_0 0 netg6916
+X44 g5365_0 g5365_1 0 netg5365
+X45 g1131_1 g1131_0 0 netg1131
+X46 g7189_1 g7189_0 0 netg7189
+X47 g4313_1 g4313_0 0 netg4313
+X48 g2426_0 g2426_2 0 netg2426
+X49 g7001_1 g7001_0 0 netg7001
+X50 g2952_1 g2952_0 0 netg2952
+X51 g5880_1 g5880_0 0 netg5880
+X52 g3513_1 g3513_0 0 netg3513
+X53 g2939_0 g2939_1 0 netg2939
+X54 g3524_0 g3524_1 0 netg3524
+X55 g6729_1 g6729_0 0 netg6729
+X56 g7354_1 g7354_0 0 netg7354
+X57 g2818_0 g2818_1 0 netg2818
+X58 g6447_1 g6447_0 0 netg6447
+X59 g6132_0 g6132_1 0 netg6132
+X60 g3510_0 g3510_1 0 netg3510
+X61 g3486_1 g3486_0 0 netg3486
+X62 g6042_0 g6042_1 0 netg6042
+X63 g1591_1 g1591_0 0 netg1591
+X64 g4096_1 g4096_0 0 netg4096
+X65 g4048_1 g4048_0 0 netg4048
+X66 g2813_1 g2813_0 0 netg2813
+X67 g1928_0 g1928_1 0 netg1928
+X68 g5233_0 g5233_1 0 netg5233
+X69 g5369_1 g5369_0 0 netg5369
+X70 g4451_1 g4451_0 0 netg4451
+X71 g3480_1 g3480_0 0 netg3480
+X72 g7359_0 g7359_1 0 netg7359
+X73 g4302_0 g4302_1 0 netg4302
+X74 g6047_1 g6047_0 0 netg6047
+X75 g7358_0 g7358_1 0 netg7358
+X76 g4280_1 g4280_0 0 netg4280
+X77 g5411_1 g5411_0 0 netg5411
+X78 x22_0 x22_1 0 netx22
+X79 g1128_0 g1128_1 0 netg1128
+X80 g3691_2 g3691_0 0 netg3691
+X81 g7213_1 g7213_0 0 netg7213
+X82 g2764_0 g2764_1 0 netg2764
+X83 g6382_1 g6382_0 0 netg6382
+X84 g3894_1 g3894_0 0 netg3894
+X85 g6815_1 g6815_0 0 netg6815
+X86 g2773_0 g2773_1 0 netg2773
+X87 g2228_1 g2228_0 0 netg2228
+X88 g5246_1 g5246_0 0 netg5246
+X89 g2821_0 g2821_1 0 netg2821
+X90 x312_0 x312_1 0 netx312
+X91 g3983_1 g3983_0 0 netg3983
+X92 g4329_1 g4329_0 0 netg4329
+X93 g7374_0 g7374_1 0 netg7374
+X94 g2501_2 g2501_0 0 netg2501
+X95 g4100_1 g4100_0 0 netg4100
+X96 g6013_0 g6013_1 0 netg6013
+X97 g2760_1 g2760_0 0 netg2760
+X98 g7212_0 g7212_1 0 netg7212
+X99 g3923_1 g3923_0 0 netg3923
+X100 g3414_2 g3414_1 0 netg3414
+X101 g5597_0 g5597_1 0 netg5597
+X102 g4298_0 g4298_1 0 netg4298
+X103 g7046_0 g7046_1 0 netg7046
+X104 g6452_1 g6452_0 0 netg6452
+X105 g6081_1 g6081_0 0 netg6081
+X106 g5448_2 g5448_1 0 netg5448
+X107 g3367_1 g3367_0 0 netg3367
+X108 g5353_0 g5353_1 0 netg5353
+X109 g7191_0 g7191_1 0 netg7191
+X110 g4013_0 g4013_1 0 netg4013
+X111 g6580_0 g6580_1 0 netg6580
+X112 g2350_2 g2350_0 0 netg2350
+X113 g3519_1 g3519_0 0 netg3519
+X114 g387_0 g387_1 0 netg387
+X115 g6199_2 g6199_0 0 netg6199
+X116 g7293_1 g7293_0 0 netg7293
+X117 g1432_0 g1432_1 0 netg1432
+X118 g1378_1 g1378_0 0 netg1378
+X119 x332_0 x332_1 0 netx332
+X120 g6611_1 g6611_0 0 netg6611
+X121 g3564_0 g3564_1 0 netg3564
+X122 g2774_1 g2774_0 0 netg2774
+X123 g1313_0 g1313_1 0 netg1313
+X124 g6741_1 g6741_0 0 netg6741
+X125 g4290_0 g4290_1 0 netg4290
+X126 g6931_1 g6931_0 0 netg6931
+X127 g5859_1 g5859_0 0 netg5859
+X128 g5827_0 g5827_1 0 netg5827
+X129 g4428_0 g4428_1 0 netg4428
+X130 g4220_0 g4220_1 0 netg4220
+X131 g1174_0 g1174_1 0 netg1174
+X132 g5857_0 g5857_1 0 netg5857
+X133 g4103_1 g4103_0 0 netg4103
+X134 g6102_0 g6102_1 0 netg6102
+X135 g3070_0 g3070_1 0 netg3070
+X136 g6474_1 g6474_0 0 netg6474
+X137 g2781_1 g2781_0 0 netg2781
+X138 g7397_1 g7397_0 0 netg7397
+X139 g1284_0 g1284_1 0 netg1284
+X140 g410_2 g410_0 0 netg410
+X141 g2778_0 g2778_1 0 netg2778
+X142 g4283_0 g4283_1 0 netg4283
+X143 g6345_0 g6345_1 0 netg6345
+X144 g5766_0 g5766_1 0 netg5766
+X145 g6254_0 g6254_1 0 netg6254
+X146 g3069_1 g3069_0 0 netg3069
+X147 g6640_1 g6640_0 0 netg6640
+X148 g6014_1 g6014_0 0 netg6014
+X149 g4216_1 g4216_0 0 netg4216
+X150 g1945_2 g1945_1 0 netg1945
+X151 g5527_0 g5527_1 0 netg5527
+X152 g2371_1 g2371_2 0 netg2371
+X153 x82_1 x82_0 0 netx82
+X154 g2751_0 g2751_1 0 netg2751
+X155 g4219_1 g4219_0 0 netg4219
+X156 g5998_0 g5998_1 0 netg5998
+X157 g5065_2 g5065_1 0 netg5065
+X158 g6103_0 g6103_1 0 netg6103
+X159 g7047_0 g7047_1 0 netg7047
+X160 g5316_0 g5316_1 0 netg5316
+X161 g7405_1 g7405_0 0 netg7405
+X162 g1518_1 g1518_0 0 netg1518
+X163 g5191_0 g5191_2 0 netg5191
+X164 g5996_0 g5996_1 0 netg5996
+X165 g1125_1 g1125_0 0 netg1125
+X166 g5792_1 g5792_0 0 netg5792
+X167 g2380_2 g2380_1 0 netg2380
+X168 g6084_0 g6084_1 0 netg6084
+X169 g6052_0 g6052_1 0 netg6052
+X170 g5297_1 g5297_0 0 netg5297
+X171 g4323_1 g4323_0 0 netg4323
+X172 g4628_0 g4628_1 0 netg4628
+X173 g3540_1 g3540_0 0 netg3540
+X174 g4065_1 g4065_0 0 netg4065
+X175 g4239_1 g4239_0 0 netg4239
+X176 g5350_0 g5350_1 0 netg5350
+X177 g1234_0 g1234_1 0 netg1234
+X178 g4318_1 g4318_0 0 netg4318
+X179 g6667_1 g6667_0 0 netg6667
+X180 g5737_2 g5737_1 0 netg5737
+X181 g7004_1 g7004_2 0 netg7004
+X182 g5244_1 g5244_0 0 netg5244
+X183 g6184_1 g6184_0 0 netg6184
+X184 g6862_0 g6862_1 0 netg6862
+X185 g1264_0 g1264_1 0 netg1264
+X186 g2879_1 g2879_0 0 netg2879
+X187 g3509_0 g3509_1 0 netg3509
+X188 g3411_0 g3411_1 0 netg3411
+X189 g2719_1 g2719_2 0 netg2719
+X190 g6642_1 g6642_2 0 netg6642
+X191 g5601_1 g5601_0 0 netg5601
+X192 g6287_0 g6287_1 0 netg6287
+X193 g5182_0 g5182_1 0 netg5182
+X194 g4344_1 g4344_0 0 netg4344
+X195 g7399_1 g7399_0 0 netg7399
+X196 g1461_1 g1461_0 0 netg1461
+X197 g1123_1 g1123_0 0 netg1123
+X198 g5322_1 g5322_0 0 netg5322
+X199 g4010_1 g4010_0 0 netg4010
+X200 x21_0 x21_1 0 netx21
+X201 g2847_1 g2847_0 0 netg2847
+X202 g1222_0 g1222_1 0 netg1222
+X203 g1916_1 g1916_0 0 netg1916
+X204 g5425_1 g5425_0 0 netg5425
+X205 g6385_0 g6385_1 0 netg6385
+X206 g2240_1 g2240_0 0 netg2240
+X207 g5603_1 g5603_0 0 netg5603
+X208 g4043_0 g4043_1 0 netg4043
+X209 g4404_1 g4404_0 0 netg4404
+X210 g1491_0 g1491_1 0 netg1491
+X211 g5965_0 g5965_1 0 netg5965
+X212 g6137_0 g6137_1 0 netg6137
+X213 g2945_1 g2945_0 0 netg2945
+X214 x61_0 x61_1 0 netx61
+X215 g7093_1 g7093_2 0 netg7093
+X216 g6420_0 g6420_1 0 netg6420
+X217 g874_0 g874_2 0 netg874
+X218 g7344_1 g7344_0 0 netg7344
+X219 g6243_1 g6243_0 0 netg6243
+X220 g1069_0 g1069_1 0 netg1069
+X221 g6846_1 g6846_0 0 netg6846
+X222 g4353_1 g4353_0 0 netg4353
+X223 g1250_1 g1250_0 0 netg1250
+X224 g5270_0 g5270_1 0 netg5270
+X225 g2918_0 g2918_1 0 netg2918
+X226 g5980_0 g5980_1 0 netg5980
+X227 g1307_1 g1307_0 0 netg1307
+X228 g7273_1 g7273_0 0 netg7273
+X229 g2743_2 g2743_1 0 netg2743
+X230 g3207_1 g3207_2 0 netg3207
+X231 x471_0 x471_1 0 netx471
+X232 g7275_0 g7275_1 0 netg7275
+X233 g5266_1 g5266_0 0 netg5266
+X234 g4265_0 g4265_1 0 netg4265
+X235 g4022_1 g4022_0 0 netg4022
+X236 g1360_0 g1360_1 0 netg1360
+X237 g6399_0 g6399_1 0 netg6399
+X238 g6182_0 g6182_1 0 netg6182
+X239 g6673_0 g6673_1 0 netg6673
+X240 g3082_1 g3082_0 0 netg3082
+X241 g2930_1 g2930_0 0 netg2930
+X242 g1494_0 g1494_1 0 netg1494
+X243 g5368_0 g5368_1 0 netg5368
+X244 g1422_0 g1422_1 0 netg1422
+X245 g2937_1 g2937_0 0 netg2937
+X246 g2555_1 g2555_2 0 netg2555
+X247 g3061_0 g3061_1 0 netg3061
+X248 g5394_0 g5394_1 0 netg5394
+X249 g2845_1 g2845_0 0 netg2845
+X250 g1534_1 g1534_0 0 netg1534
+X251 g3045_1 g3045_0 0 netg3045
+X252 g6887_1 g6887_0 0 netg6887
+X253 g6278_0 g6278_2 0 netg6278
+X254 g6977_0 g6977_1 0 netg6977
+X255 g3551_1 g3551_0 0 netg3551
+X256 g6751_2 g6751_0 0 netg6751
+X257 x72_1 x72_0 0 netx72
+X258 g5421_1 g5421_0 0 netg5421
+X259 x122_1 x122_0 0 netx122
+X260 g5251_1 g5251_0 0 netg5251
+X261 g2784_1 g2784_0 0 netg2784
+X262 x131_1 x131_0 0 netx131
+X263 g6814_1 g6814_0 0 netg6814
+X264 g6205_1 g6205_0 0 netg6205
+X265 g6693_1 g6693_0 0 netg6693
+X266 g6465_0 g6465_1 0 netg6465
+X267 g2995_1 g2995_0 0 netg2995
+X268 g3261_2 g3261_0 0 netg3261
+X269 g1236_0 g1236_1 0 netg1236
+X270 g5333_0 g5333_1 0 netg5333
+X271 g4098_1 g4098_0 0 netg4098
+X272 g5144_1 g5144_2 0 netg5144
+X273 g1375_0 g1375_1 0 netg1375
+X274 g5366_0 g5366_1 0 netg5366
+X275 g4131_0 g4131_1 0 netg4131
+X276 g4240_1 g4240_0 0 netg4240
+X277 g3563_0 g3563_1 0 netg3563
+X278 g1158_0 g1158_1 0 netg1158
+X279 g7002_0 g7002_1 0 netg7002
+X280 g5870_1 g5870_0 0 netg5870
+X281 g4106_0 g4106_1 0 netg4106
+X282 g4352_1 g4352_0 0 netg4352
+X283 x91_1 x91_0 0 netx91
+X284 g5932_1 g5932_0 0 netg5932
+X285 g7306_2 g7306_1 0 netg7306
+X286 g2579_1 g2579_2 0 netg2579
+X287 g2919_0 g2919_1 0 netg2919
+X288 g3429_2 g3429_0 0 netg3429
+X289 g4082_1 g4082_0 0 netg4082
+X290 g3901_0 g3901_1 0 netg3901
+X291 g5999_1 g5999_0 0 netg5999
+X292 g4309_0 g4309_1 0 netg4309
+X293 g5705_1 g5705_0 0 netg5705
+X294 g6450_1 g6450_0 0 netg6450
+X295 g7240_1 g7240_0 0 netg7240
+X296 g6392_0 g6392_1 0 netg6392
+X297 g1169_1 g1169_0 0 netg1169
+X298 g6871_1 g6871_0 0 netg6871
+X299 g4138_0 g4138_1 0 netg4138
+X300 g6363_1 g6363_0 0 netg6363
+X301 g5278_0 g5278_1 0 netg5278
+X302 g1479_1 g1479_0 0 netg1479
+X303 g6167_0 g6167_1 0 netg6167
+X304 g6131_0 g6131_1 0 netg6131
+X305 g2933_0 g2933_1 0 netg2933
+X306 g6744_1 g6744_0 0 netg6744
+X307 g7400_1 g7400_0 0 netg7400
+X308 g1852_1 g1852_0 0 netg1852
+X309 g2731_1 g2731_2 0 netg2731
+X310 g3453_2 g3453_0 0 netg3453
+X311 g1151_0 g1151_1 0 netg1151
+X312 g1421_1 g1421_0 0 netg1421
+X313 g3113_1 g3113_0 0 netg3113
+X314 g3089_1 g3089_0 0 netg3089
+X315 x192_0 x192_1 0 netx192
+X316 g6000_1 g6000_0 0 netg6000
+X317 g1573_0 g1573_1 0 netg1573
+X318 g6373_1 g6373_0 0 netg6373
+X319 g456_0 g456_1 0 netg456
+X320 g3180_2 g3180_1 0 netg3180
+X321 g5313_1 g5313_0 0 netg5313
+X322 g6413_1 g6413_0 0 netg6413
+X323 g4149_0 g4149_1 0 netg4149
+X324 g6105_1 g6105_0 0 netg6105
+X325 g6448_0 g6448_1 0 netg6448
+X326 g4247_1 g4247_0 0 netg4247
+X327 g7269_0 g7269_1 0 netg7269
+X328 g4436_0 g4436_1 0 netg4436
+X329 g7346_1 g7346_0 0 netg7346
+X330 g5134_0 g5134_1 0 netg5134
+X331 g2822_1 g2822_0 0 netg2822
+X332 g4403_0 g4403_1 0 netg4403
+X333 g3968_0 g3968_1 0 netg3968
+X334 g1308_0 g1308_1 0 netg1308
+X335 g1165_1 g1165_0 0 netg1165
+X336 g6976_0 g6976_1 0 netg6976
+X337 g3315_0 g3315_2 0 netg3315
+X338 g2749_0 g2749_1 0 netg2749
+X339 g6732_1 g6732_0 0 netg6732
+X340 g5634_2 g5634_1 0 netg5634
+X341 g1380_1 g1380_0 0 netg1380
+X342 g6326_0 g6326_1 0 netg6326
+X343 g3225_0 g3225_2 0 netg3225
+X344 g7437_1 g7437_0 0 netg7437
+X345 x162_0 x162_1 0 netx162
+X346 g6139_1 g6139_0 0 netg6139
+X347 g6106_1 g6106_0 0 netg6106
+X348 g1510_1 g1510_0 0 netg1510
+X349 g1585_0 g1585_1 0 netg1585
+X350 g4047_0 g4047_1 0 netg4047
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+X3435 g4_2 g4_1 g4_0 0 netg4
+X3436 g1750_4 g1750_0 g1750_2 g1750_5 g1750_3 g1750_1 0 netg1750
+X3437 g457_6 g457_2 g457_5 g457_1 g457_4 g457_3 g457_0 0 netg457
+X3438 g1738_5 g1738_2 g1738_1 g1738_4 g1738_3 g1738_0 0 netg1738
+X3439 g183_0 g183_1 g183_2 0 netg183
+X3440 g7465_1 g7465_0 0 netg7465
+X3441 g3_2 g3_1 g3_0 0 netg3
+X3442 g1_3 g1_1 g1_0 g1_2 0 netg1
+X3443 g167_1 g167_2 g167_0 0 netg167
+X3444 g7448_0 g7448_1 0 netg7448
+X3445 g7490_1 g7490_0 0 netg7490
+X3446 g1744_1 g1744_0 g1744_4 g1744_3 g1744_2 g1744_5 0 netg1744
+X3447 g7466_1 g7466_0 0 netg7466
+X3448 g178_2 g178_1 g178_0 0 netg178
+X3449 g30_0 g30_2 g30_1 0 netg30
+X3450 g7467_0 g7467_1 0 netg7467
+X3451 g191_2 g191_1 g191_0 0 netg191
+X3452 g464_0 g464_4 g464_3 g464_2 g464_1 g464_5 0 netg464
+X3453 g179_2 g179_1 g179_0 0 netg179
+X3454 g195_0 g195_2 g195_1 0 netg195
+X3455 g7456_0 g7456_1 0 netg7456
+X3456 g7484_0 g7484_1 0 netg7484
+X3457 g192_2 g192_1 g192_0 0 netg192
+X3458 g199_0 g199_1 g199_2 0 netg199
+X3459 g202_0 g202_2 g202_1 0 netg202
+X3460 g14_0 g14_2 g14_1 0 netg14
+X3461 g176_2 g176_1 g176_0 0 netg176
+X3462 g13_2 g13_1 g13_0 0 netg13
+X3463 g1731_5 g1731_4 g1731_0 g1731_3 g1731_1 g1731_2 g1731_6 0 netg1731
+X3464 g1756_5 g1756_3 g1756_1 g1756_4 g1756_2 g1756_0 0 netg1756
+X3465 g201_1 g201_2 g201_0 0 netg201
+X3466 g203_0 g203_2 g203_1 0 netg203
+X3467 g204_1 g204_2 g204_0 0 netg204
+X3468 g198_0 g198_2 g198_1 0 netg198
+X3469 g7_2 g7_0 g7_1 0 netg7
+X3470 g186_1 g186_2 g186_0 0 netg186
+X3471 g9_1 g9_2 g9_0 0 netg9
+X3472 g196_2 g196_1 g196_0 0 netg196
+X3473 g206_10 g206_5 g206_8 g206_7 g206_4 g206_14 g206_3 g206_1 g206_6 g206_13 g206_12 g206_2 g206_0 g206_11 g206_9 0 netg206
+X3474 g16_1 g16_2 g16_0 0 netg16
+X3475 g177_1 g177_0 g177_2 0 netg177
+X3476 g7483_1 g7483_0 0 netg7483
+X3477 g200_0 g200_2 g200_1 0 netg200
+X3478 g8_1 g8_2 g8_0 0 netg8
+X3479 g207_3 g207_2 g207_0 g207_4 g207_1 0 netg207
+X3480 g11_2 g11_1 0 netg11
+X3481 g6_0 g6_2 g6_1 g6_4 g6_3 0 netg6
+X3482 g15_0 g15_2 g15_1 0 netg15
+X3483 g187_2 g187_0 g187_1 0 netg187
+X3484 g10_1 g10_0 g10_2 0 netg10
+X3485 g182_1 g182_0 g182_2 0 netg182
+X3486 g173_2 g173_0 g173_3 g173_1 0 netg173
+X3487 g174_2 g174_3 g174_1 g174_0 0 netg174
+X3488 g388_2 g388_1 g388_0 0 netg388
+X3489 g181_0 g181_2 g181_1 g181_3 0 netg181
+X3490 g87_0 g87_1 0 netg87
+X3491 g166_0 g166_2 g166_1 0 netg166
+X3492 g180_0 g180_1 g180_2 0 netg180
+X3493 g185_0 g185_2 g185_1 g185_3 0 netg185
+X3494 g184_0 g184_3 g184_2 g184_1 0 netg184
+X3495 g165_1 g165_0 0 netg165
+
+* the calls of the component sub circuits:
+
+X3496 g2386_0 vdd 0 g2788_0 not1
+X3497 g6994_0 g6881_0 vdd 0 g7532_0 or2
+X3498 g49_2 g6075_0 g6016_0 vdd 0 x441_1 and3
+X3499 g2284_1 vdd 0 g3192_1 not1
+X3500 g3234_1 g1267_1 vdd 0 g4021_0 nand2
+X3501 g1108_3 g1120_0 vdd 0 g1407_1 or2
+X3502 g2618_2 vdd 0 g2995_1 not1
+X3503 g1600_3 vdd 0 g2409_2 not1
+X3504 g1411_3 vdd 0 g1942_2 not1
+X3505 g31_0 g1330_4 vdd 0 g1571_1 and2
+X3506 g4539_5 g2885_0 vdd 0 g5348_0 and2
+X3507 g646_1 g2244_2 vdd 0 g3019_0 and2
+X3508 g4463_8 vdd 0 g5619_2 not1
+X3509 g1929_1 g1556_1 vdd 0 g2300_1 or2
+X3510 g526_1 g1698_3 vdd 0 g2055_3 and2
+X3511 g6371_0 g6370_1 vdd 0 g6475_1 nand2
+X3512 g5086_2 g7101_0 vdd 0 g7125_1 nand2
+X3513 g4913_3 g4908_4 g3060_1 vdd 0 g5520_1 and3
+X3514 g3024_0 g5485_0 g5486_0 g5487_0 vdd 0 g5939_0 or4
+X3515 g2338_0 g2119_1 vdd 0 g3059_1 and2
+X3516 g3432_0 vdd 0 g4204_1 not1
+X3517 g8_1 g785_2 vdd 0 g1222_0 and2
+X3518 g747_1 g1889_0 vdd 0 g1995_0 or2
+X3519 g3404_2 vdd 0 g4110_0 not1
+X3520 g5535_1 g5532_1 g5549_1 vdd 0 g6089_1 and3
+X3521 x171_1 x172_0 vdd 0 g5184_1 or2
+X3522 g1756_0 vdd 0 g2398_0 not1
+X3523 g4383_0 vdd 0 g5265_1 not1
+X3524 g7008_1 g6973_0 vdd 0 g7051_0 nand2
+X3525 g4006_1 g4003_0 g3999_2 vdd 0 x111_1 and3
+X3526 g6281_1 vdd 0 g6440_1 not1
+X3527 g553_4 vdd 0 g904_1 not1
+X3528 g2650_1 g3345_0 vdd 0 g3566_0 nand2
+X3529 g6631_0 g6258_0 vdd 0 g6733_0 nand2
+X3530 g3665_1 g3644_1 vdd 0 x472_0 and2
+X3531 g4519_3 vdd 0 g5578_0 not1
+X3532 g4899_1 g4896_0 g4905_1 vdd 0 g5514_0 and3
+X3533 g1836_0 g1616_1 vdd 0 g2224_1 and2
+X3534 g4976_1 vdd 0 g5239_1 not1
+X3535 g1948_2 g1383_0 vdd 0 g2746_1 nand2
+X3536 g5139_1 vdd 0 g5684_1 not1
+X3537 g486_1 g828_0 vdd 0 g1288_0 and2
+X3538 g859_1 vdd 0 g1125_1 not1
+X3539 g4850_11 vdd 0 g5734_1 not1
+X3540 g652_5 vdd 0 g1054_1 not1
+X3541 g129_0 g1206_3 vdd 0 g1494_0 and2
+X3542 g2641_0 vdd 0 g3045_1 not1
+X3543 g3222_0 vdd 0 g4014_1 not1
+X3544 g3168_2 vdd 0 g3937_1 not1
+X3545 g4704_4 vdd 0 g5557_2 not1
+X3546 g73_2 g1138_4 vdd 0 g1431_1 and2
+X3547 g2576_0 vdd 0 g2935_0 not1
+X3548 x31_0 x32_0 vdd 0 g4346_1 and2
+X3549 g5125_0 g5703_1 vdd 0 g5929_0 nand2
+X3550 g5658_1 g7358_0 vdd 0 g7374_1 nand2
+X3551 g7041_1 g5591_1 vdd 0 g7092_0 nand2
+X3552 g4060_0 g4269_1 vdd 0 g4834_15 nand2
+X3553 g4764_2 vdd 0 g5445_2 not1
+X3554 g2989_0 g6919_0 vdd 0 g6957_0 or2
+X3555 g140_0 g805_0 vdd 0 g1251_0 and2
+X3556 g4863_0 vdd 0 g5719_1 not1
+X3557 g4653_1 g4642_0 g2944_0 g4648_0 vdd 0 g5393_1 and4
+X3558 g772_2 vdd 0 g1185_5 not1
+X3559 g3195_0 g3980_1 vdd 0 g4238_1 nand2
+X3560 g7203_2 vdd 0 g7250_1 not1
+X3561 g4630_4 g2936_1 vdd 0 g5385_1 and2
+X3562 g3572_0 g3573_0 vdd 0 g4196_1 nand2
+X3563 g865_1 g2770_0 vdd 0 g3468_1 nand2
+X3564 g518_0 g842_1 vdd 0 g1356_0 and2
+X3565 g2763_0 g2764_1 vdd 0 g3106_1 nand2
+X3566 g3086_0 g1386_1 vdd 0 g4139_1 nand2
+X3567 g2486_1 vdd 0 g2832_1 not1
+X3568 g1782_3 vdd 0 g2588_2 not1
+X3569 g7260_0 g5780_1 g6687_0 vdd 0 g7299_1 and3
+X3570 g6182_0 g6699_0 vdd 0 g6781_0 and2
+X3571 g2746_0 g2791_1 vdd 0 g3477_0 nand2
+X3572 g2215_2 vdd 0 g3282_1 not1
+X3573 g3484_0 g2800_1 vdd 0 g3694_3 nand2
+X3574 g883_1 g1381_1 vdd 0 g1428_1 nand2
+X3575 g5092_0 vdd 0 g5606_1 not1
+X3576 g3303_1 g1308_0 vdd 0 g4052_1 nand2
+X3577 g6484_1 g6365_0 vdd 0 g6608_1 nand2
+X3578 g3928_7 g4568_11 vdd 0 x222_1 and2
+X3579 g2516_2 g4618_0 vdd 0 g5182_1 nand2
+X3580 g162_1 g1484_5 vdd 0 g1913_1 and2
+X3581 g4346_0 g6590_0 vdd 0 g6686_0 and2
+X3582 g2062_2 g3754_2 vdd 0 x62_0 and2
+X3583 g7231_2 vdd 0 g7263_1 not1
+X3584 g6815_0 g6721_1 vdd 0 g6840_2 nand2
+X3585 g2683_2 vdd 0 g3057_1 not1
+X3586 g1910_0 g1483_1 vdd 0 g2194_5 or2
+X3587 g964_2 vdd 0 g1228_1 not1
+X3588 g494_5 vdd 0 g716_4 not1
+X3589 g5740_2 vdd 0 g6139_0 not1
+X3590 g7287_1 g6140_1 vdd 0 g7335_1 nand2
+X3591 g2280_0 vdd 0 g3198_2 not1
+X3592 g5875_0 g4149_0 vdd 0 g6246_1 nand2
+X3593 g2848_0 g5313_0 g5314_0 g5315_0 vdd 0 g5795_1 or4
+X3594 g3803_2 g3768_0 g3754_1 g3784_2 vdd 0 g4417_1 and4
+X3595 g5867_1 g6451_0 vdd 0 g6550_1 nand2
+X3596 g6659_1 g6606_1 vdd 0 g6703_0 nand2
+X3597 g2756_0 vdd 0 g3561_0 not1
+X3598 g2203_4 vdd 0 g3165_2 not1
+X3599 g7_0 g1212_2 vdd 0 g1499_0 and2
+X3600 g473_3 g1750_2 vdd 0 g2001_0 and2
+X3601 g7231_2 g6009_0 vdd 0 g7264_1 nand2
+X3602 g2885_2 g5353_1 vdd 0 g5806_2 or2
+X3603 g1387_2 g4140_1 vdd 0 g4302_1 nand2
+X3604 g1698_4 vdd 0 g2468_0 not1
+X3605 g6667_1 g6641_1 vdd 0 g6738_2 nand2
+X3606 g3453_2 g4207_1 vdd 0 g4320_1 nand2
+X3607 g3426_1 g4203_1 vdd 0 g4316_1 nand2
+X3608 g3159_2 vdd 0 g3923_0 not1
+X3609 g3132_1 g1228_0 vdd 0 g3899_1 nand2
+X3610 g7096_2 g5601_0 vdd 0 g7140_1 nand2
+X3611 g621_6 g1537_5 vdd 0 g1923_1 and2
+X3612 g3665_4 g2013_4 vdd 0 g4358_1 and2
+X3613 g473_0 g1750_0 vdd 0 g1961_0 and2
+X3614 g5015_2 vdd 0 g5587_1 not1
+X3615 g36_0 g1330_1 vdd 0 g1574_0 and2
+X3616 g6278_2 g6013_1 vdd 0 g6437_1 nand2
+X3617 g5613_0 g6167_0 vdd 0 g6327_1 nand2
+X3618 g494_0 vdd 0 g753_1 not1
+X3619 g4064_1 g4271_0 vdd 0 g4863_1 nand2
+X3620 g2650_2 vdd 0 g3346_1 not1
+X3621 g4997_2 g6898_0 vdd 0 g6937_1 nand2
+X3622 g5984_1 vdd 0 g6154_1 not1
+X3623 g3705_0 g4374_1 g5268_1 vdd 0 g5779_1 and3
+X3624 g2326_2 g2107_0 vdd 0 g3062_1 and2
+X3625 g690_1 vdd 0 g796_1 not1
+X3626 g3123_2 vdd 0 g3894_1 not1
+X3627 g6990_2 vdd 0 g7073_1 not1
+X3628 g5816_0 g6534_0 g6535_0 g6350_0 vdd 0 g6589_0 or4
+X3629 g6196_0 g6048_1 vdd 0 g6361_0 nor2
+X3630 g1431_0 g1151_0 vdd 0 g1675_2 or2
+X3631 g4307_1 g4308_0 vdd 0 g5131_2 nand2
+X3632 g1859_2 vdd 0 g2421_1 not1
+X3633 g1874_1 g2633_0 vdd 0 g2765_1 nand2
+X3634 g4313_0 g4314_1 vdd 0 g5136_2 nand2
+X3635 g2870_0 g5331_0 g5332_0 g5990_0 vdd 0 g6217_0 or4
+X3636 g3617_9 g3601_7 g3579_2 vdd 0 x21_1 and3
+X3637 g7309_2 g5839_1 g6833_3 vdd 0 g7355_0 and3
+X3638 g5234_1 g5235_1 vdd 0 g5680_2 nand2
+X3639 g640_5 g1537_4 vdd 0 g1926_1 and2
+X3640 g7144_2 g5609_1 vdd 0 g7186_1 nand2
+X3641 g5205_2 g6623_1 vdd 0 g6666_1 nand2
+X3642 g4935_0 g4931_0 g4920_0 vdd 0 x301_1 and3
+X3643 g2127_1 vdd 0 g3156_0 not1
+X3644 g7297_1 g7278_1 vdd 0 g7324_1 nand2
+X3645 g3862_3 g2096_1 g3852_1 vdd 0 g4451_0 and3
+X3646 g147_0 g1521_3 vdd 0 g1917_1 and2
+X3647 g2119_3 vdd 0 g3377_2 not1
+X3648 g5643_2 g7105_1 vdd 0 g7127_1 nand2
+X3649 g17_1 g1337_6 vdd 0 g1577_1 and2
+X3650 g5476_0 g5477_0 vdd 0 x352_1 or2
+X3651 g5713_0 vdd 0 g6132_0 not1
+X3652 g2859_1 vdd 0 g4154_2 not1
+X3653 g6322_0 g6026_0 vdd 0 g6539_1 and2
+X3654 g6214_1 vdd 0 g6405_1 not1
+X3655 g1295_6 vdd 0 g1521_4 not1
+X3656 g691_2 vdd 0 g1082_2 not1
+X3657 g5731_2 vdd 0 g6136_1 not1
+X3658 g6351_1 g5287_0 vdd 0 g6536_1 and2
+X3659 g6223_0 vdd 0 g6411_0 not1
+X3660 g5543_1 vdd 0 g6081_0 not1
+X3661 g3637_2 g3665_2 vdd 0 x32_1 and2
+X3662 g3438_1 g3085_0 vdd 0 g4133_0 nand2
+X3663 g3453_0 vdd 0 g4206_1 not1
+X3664 g7400_1 g7388_1 vdd 0 g7408_1 nand2
+X3665 g2092_2 g4453_1 g4454_1 g6692_1 vdd 0 g6793_2 or4
+X3666 g934_1 g2836_1 vdd 0 g3506_1 nand2
+X3667 g2365_0 vdd 0 g3093_1 not1
+X3668 g450_0 vdd 0 g1003_1 not1
+X3669 g6522_0 g6412_0 vdd 0 g7509_1 nand2
+X3670 g188_0 vdd 0 g7465_0 not1
+X3671 g494_2 vdd 0 g727_1 not1
+X3672 x541_1 x542_1 vdd 0 g7503_0 or2
+X3673 g6284_2 vdd 0 g6487_0 not1
+X3674 g6046_1 g6045_0 vdd 0 g6281_2 nand2
+X3675 g1048_1 vdd 0 g1312_0 not1
+X3676 g6335_1 g6580_1 vdd 0 g6654_1 and2
+X3677 g7122_0 g7090_0 vdd 0 g7131_2 nand2
+X3678 g52_0 g1185_0 vdd 0 g1461_0 and2
+X3679 g2507_1 g1177_1 vdd 0 g2845_1 nand2
+X3680 g1018_1 g4016_1 vdd 0 g4249_1 nand2
+X3681 g7375_1 g7442_1 vdd 0 g7444_1 nand2
+X3682 g7225_1 g5605_1 vdd 0 g7276_1 nand2
+X3683 g2258_5 vdd 0 g3306_2 not1
+X3684 g5185_0 vdd 0 g5827_0 not1
+X3685 g3839_1 g3828_5 g3817_7 vdd 0 g4437_0 and3
+X3686 g1902_0 g1475_1 vdd 0 g2159_2 or2
+X3687 g2665_1 vdd 0 g3050_0 not1
+X3688 g4568_8 vdd 0 g5661_0 not1
+X3689 g3895_0 g4218_1 vdd 0 g4474_0 nand2
+X3690 g1961_1 g4332_0 g4333_1 vdd 0 x191_0 or3
+X3691 g6942_3 g6400_0 vdd 0 g7017_0 and2
+X3692 g172_1 vdd 0 g7451_1 not1
+X3693 g2200_2 vdd 0 g3270_2 not1
+X3694 g1792_1 g2241_2 vdd 0 g3069_1 and2
+X3695 g3165_1 g1238_1 vdd 0 g3926_0 nand2
+X3696 g6705_3 vdd 0 g6833_2 not1
+X3697 g3312_2 vdd 0 g4059_1 not1
+X3698 g1500_0 g799_3 vdd 0 g1815_0 and2
+X3699 g7237_0 g6113_1 vdd 0 g7280_0 nand2
+X3700 g3725_6 vdd 0 g5062_1 not1
+X3701 g3216_1 g1261_0 vdd 0 g4009_1 nand2
+X3702 g1738_4 vdd 0 g2356_1 not1
+X3703 g3665_9 g3654_9 g3637_6 vdd 0 x41_1 and3
+X3704 g2412_2 g2801_1 vdd 0 g3485_1 nand2
+X3705 g666_5 g1543_3 vdd 0 g1930_1 and2
+X3706 g4179_2 g6489_0 vdd 0 g6557_1 nand2
+X3707 g3300_2 vdd 0 g4051_1 not1
+X3708 g6957_1 g5962_0 vdd 0 g7026_0 nand2
+X3709 g2300_0 g1803_0 vdd 0 g2938_0 and2
+X3710 g4568_1 g4560_1 vdd 0 x402_0 and2
+X3711 g119_0 g1462_1 vdd 0 g1904_1 and2
+X3712 g7078_0 g7026_1 vdd 0 g7544_0 nand2
+X3713 g2453_0 vdd 0 g2814_1 not1
+X3714 g479_0 vdd 0 g886_2 not1
+X3715 g4687_3 g2969_6 vdd 0 g5417_0 and2
+X3716 g6705_0 g7408_0 vdd 0 g7413_1 and2
+X3717 g5566_0 vdd 0 g5962_1 not1
+X3718 g7374_0 g7359_0 vdd 0 g7391_1 nand2
+X3719 g4982_2 vdd 0 g5241_1 not1
+X3720 g2456_2 vdd 0 g2816_1 not1
+X3721 g104_0 g753_6 vdd 0 g1152_0 and2
+X3722 g6340_3 g6056_6 g5280_4 vdd 0 g6527_1 and3
+X3723 g7445_1 vdd 0 g7552_1 not1
+X3724 g5448_1 vdd 0 g6042_0 not1
+X3725 g907_0 vdd 0 g1163_1 not1
+X3726 g5731_1 g7071_1 vdd 0 g7083_0 nand2
+X3727 g6802_1 g5244_1 vdd 0 g6895_1 nand2
+X3728 g61_0 g1192_3 vdd 0 g1474_0 and2
+X3729 g3687_2 g3683_3 g4377_1 vdd 0 g5269_1 and3
+X3730 g4284_1 g4285_0 vdd 0 g4920_1 nand2
+X3731 g1840_2 vdd 0 g2725_0 not1
+X3732 g4756_1 g5434_1 g6042_1 vdd 0 g6196_1 and3
+X3733 g538_4 vdd 0 g940_2 not1
+X3734 g5334_6 g4582_10 g4598_12 vdd 0 g6007_1 and3
+X3735 g2627_1 g3000_0 vdd 0 g3545_0 nand2
+X3736 g5986_0 g206_2 vdd 0 g6331_1 and2
+X3737 g1670_1 vdd 0 g1999_1 not1
+X3738 g4167_0 g6040_0 vdd 0 g6194_1 nand2
+X3739 g6645_1 g6291_0 vdd 0 g6744_1 nand2
+X3740 g3617_5 g3601_14 g1978_5 vdd 0 g4340_1 and3
+X3741 g94_1 g705_4 vdd 0 g1085_1 and2
+X3742 g3330_2 vdd 0 g4182_1 not1
+X3743 g3144_0 g5998_0 vdd 0 g6173_0 nand2
+X3744 g181_0 vdd 0 g544_0 not1
+X3745 g2686_1 vdd 0 g3364_1 not1
+X3746 g1423_4 vdd 0 g1951_1 not1
+X3747 x251_1 x252_0 vdd 0 g5418_2 and2
+X3748 g2244_5 vdd 0 g3309_2 not1
+X3749 g1807_0 vdd 0 g2576_2 not1
+X3750 g4519_4 g4508_0 g3907_4 vdd 0 g5332_1 and3
+X3751 g456_1 g821_6 vdd 0 g1281_1 and2
+X3752 g185_3 vdd 0 g423_4 not1
+X3753 g2959_0 g5413_0 g5414_0 vdd 0 g5920_2 nor3
+X3754 g177_0 vdd 0 g519_2 not1
+X3755 g1916_0 g1762_0 vdd 0 g2235_0 and2
+X3756 g1435_0 g1155_1 vdd 0 g1865_1 or2
+X3757 g473_4 vdd 0 g865_1 not1
+X3758 g4282_1 g4283_0 vdd 0 g4917_2 nand2
+X3759 g614_4 g2153_3 vdd 0 g2848_1 and2
+X3760 g4812_6 g3020_3 vdd 0 g5474_1 and2
+X3761 g4617_1 g5182_0 vdd 0 g5334_5 nand2
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+X7068 g3852_2 g2092_1 vdd 0 g4450_0 and2
+X7069 g1592_0 vdd 0 g2406_2 not1
+X7070 g2778_0 g2777_0 vdd 0 g3466_1 nand2
+X7071 g6625_0 g5884_1 vdd 0 g6729_1 nand2
+X7072 g7141_0 g5604_0 vdd 0 g7184_0 nand2
+X7073 g181_1 vdd 0 g413_2 not1
+X7074 g6357_1 g6190_0 vdd 0 g6399_1 nand2
+X7075 g3276_2 vdd 0 g4046_1 not1
+X7076 x561_1 x562_1 vdd 0 g7505_0 or2
+X7077 g5298_1 g5793_1 vdd 0 g5984_0 nand2
+X7078 g1060_1 vdd 0 g1387_1 not1
+X7079 g6932_0 g6888_0 vdd 0 g7523_0 nand2
+X7080 g37_1 g1316_2 vdd 0 g1550_0 and2
+X7081 g3114_0 vdd 0 g4150_1 not1
+X7082 g7339_0 g7331_1 vdd 0 g7360_1 nand2
+X7083 g3754_6 g2049_3 vdd 0 g4418_1 and2
+X7084 g3516_0 g3517_0 vdd 0 g3947_0 nand2
+X7085 g634_0 g2188_1 vdd 0 g2980_0 and2
+X7086 g7203_1 g6143_1 vdd 0 g7251_1 nand2
+X7087 g3294_1 g4176_1 vdd 0 g4309_1 nand2
+X7088 g2817_1 g3497_1 vdd 0 g3746_6 nand2
+X7089 x291_0 x292_0 vdd 0 g5522_1 and2
+X7090 g1092_0 g1099_0 vdd 0 g1398_0 or2
+X7091 g7394_0 g6829_1 vdd 0 g7403_1 and2
+X7092 g166_1 g407_2 vdd 0 g7493_0 nand2
+X7093 g5115_2 vdd 0 g5667_1 not1
+X7094 g6329_1 g6172_1 vdd 0 g6422_1 nand2
+X7095 g5163_2 g2019_3 vdd 0 g5768_1 and2
+X7096 g2525_0 vdd 0 g2917_1 not1
+X7097 g2141_0 vdd 0 g3153_0 not1
+X7098 g7370_0 g7345_0 vdd 0 g7382_1 nand2
+X7099 g5752_0 vdd 0 g6142_1 not1
+X7100 g3261_2 vdd 0 g4171_1 not1
+X7101 g2588_2 vdd 0 g2947_1 not1
+X7102 g907_1 g2818_1 vdd 0 g3497_0 nand2
+X7103 g994_2 g3927_1 vdd 0 g4230_1 nand2
+X7104 g5830_0 g5404_0 vdd 0 g6184_0 and2
+X7105 x121_0 x122_0 vdd 0 g4668_0 and2
+X7106 g910_1 g2820_0 vdd 0 g3498_1 nand2
+X7107 g7168_1 g7138_1 vdd 0 g7177_1 nand2
+X7108 g4598_2 vdd 0 g5652_0 not1
+X7109 g2322_2 g1727_0 vdd 0 g3064_1 and2
+X7110 g2969_5 vdd 0 g4167_1 not1
+X7111 g43_1 g1344_4 vdd 0 g1583_1 and2
+X7112 g6954_2 vdd 0 g7023_0 not1
+X7113 g512_3 vdd 0 g856_2 not1
+X7114 g14_0 g1212_4 vdd 0 g1495_0 and2
+X7115 g394_2 vdd 0 g7487_0 not1
+X7116 g1102_2 g1115_1 vdd 0 g1402_0 or2
+X7117 g1951_0 vdd 0 g2749_1 not1
+X7118 g5300_0 g5794_0 vdd 0 g5957_1 nand2
+X7119 g3086_1 vdd 0 g4138_0 not1
+
+* the components sub circuits:
+
+.subckt or4 a b c d vdd vss z
+xm01 sig8  a     vdd   vdd sg13_lv_pmos  l=0.13u  w=0.99u  as=0.26235p  ad=0.26235p  ps=2.51u   pd=2.51u
+xm02 vdd   a     05    vdd sg13_lv_pmos  l=0.13u  w=0.99u  as=0.26235p  ad=0.26235p  ps=2.51u   pd=2.51u
+xm03 sig1  a     vss   vss sg13_lv_nmos  l=0.13u  w=0.33u  as=0.08745p  ad=0.08745p  ps=1.19u   pd=1.19u
+xm04 n2    b     sig8  vdd sg13_lv_pmos  l=0.13u  w=0.99u  as=0.26235p  ad=0.26235p  ps=2.51u   pd=2.51u
+xm05 05    b     08    vdd sg13_lv_pmos  l=0.13u  w=0.99u  as=0.26235p  ad=0.26235p  ps=2.51u   pd=2.51u
+xm06 vss   b     sig1  vss sg13_lv_nmos  l=0.13u  w=0.33u  as=0.08745p  ad=0.08745p  ps=1.19u   pd=1.19u
+xm07 10    c     n2    vdd sg13_lv_pmos  l=0.13u  w=0.99u  as=0.26235p  ad=0.26235p  ps=2.51u   pd=2.51u
+xm08 08    c     11    vdd sg13_lv_pmos  l=0.13u  w=0.99u  as=0.26235p  ad=0.26235p  ps=2.51u   pd=2.51u
+xm09 sig1  c     vss   vss sg13_lv_nmos  l=0.13u  w=0.33u  as=0.08745p  ad=0.08745p  ps=1.19u   pd=1.19u
+xm10 sig1  d     10    vdd sg13_lv_pmos  l=0.13u  w=0.99u  as=0.26235p  ad=0.26235p  ps=2.51u   pd=2.51u
+xm11 11    d     sig1  vdd sg13_lv_pmos  l=0.13u  w=0.99u  as=0.26235p  ad=0.26235p  ps=2.51u   pd=2.51u
+xm12 vss   d     sig1  vss sg13_lv_nmos  l=0.13u  w=0.33u  as=0.08745p  ad=0.08745p  ps=1.19u   pd=1.19u
+xm13 vdd   sig1  z     vdd sg13_lv_pmos  l=0.13u  w=0.99u  as=0.26235p  ad=0.26235p  ps=2.51u   pd=2.51u
+xm14 vss   sig1  z     vss sg13_lv_nmos  l=0.13u  w=0.495u as=0.131175p ad=0.131175p ps=1.52u   pd=1.52u
+c4  a     vss   1.356f
+c5  b     vss   1.229f
+c6  c     vss   1.043f
+c7  d     vss   0.797f
+c1  sig1  vss   1.003f
+c3  z     vss   0.701f
+.ends
+.subckt xnr2v0x1 a b vdd vss z
+xm01 z     b     sig3  vdd sg13_lv_pmos  l=0.13u  w=0.99u  as=0.26235p  ad=0.26235p  ps=2.51u   pd=2.51u
+xm02 bn    sig3  z     vss sg13_lv_nmos  l=0.13u  w=0.495u as=0.131175p ad=0.131175p ps=1.52u   pd=1.52u
+xm03 sig3  a     vdd   vdd sg13_lv_pmos  l=0.13u  w=0.99u  as=0.26235p  ad=0.26235p  ps=2.51u   pd=2.51u
+xm04 vdd   b     bn    vdd sg13_lv_pmos  l=0.13u  w=0.99u  as=0.26235p  ad=0.26235p  ps=2.51u   pd=2.51u
+xm05 z     bn    sig3  vss sg13_lv_nmos  l=0.13u  w=0.495u as=0.131175p ad=0.131175p ps=1.52u   pd=1.52u
+xm06 vdd   sig3  n1    vdd sg13_lv_pmos  l=0.13u  w=1.54u  as=0.4081p   ad=0.4081p   ps=3.61u   pd=3.61u
+xm07 sig3  a     vss   vss sg13_lv_nmos  l=0.13u  w=0.495u as=0.131175p ad=0.131175p ps=1.52u   pd=1.52u
+xm08 n1    bn    z     vdd sg13_lv_pmos  l=0.13u  w=1.54u  as=0.4081p   ad=0.4081p   ps=3.61u   pd=3.61u
+xm09 vss   b     bn    vss sg13_lv_nmos  l=0.13u  w=0.495u as=0.131175p ad=0.131175p ps=1.52u   pd=1.52u
+c4  a     vss   0.389f
+c2  bn    vss   1.593f
+c5  b     vss   0.840f
+c3  sig3  vss   0.618f
+c6  z     vss   0.627f
+.ends
+.subckt nor2 a b vdd vss z
+xm01 vdd   a     01    vdd sg13_lv_pmos  l=0.13u  w=1.54u  as=0.4081p   ad=0.4081p   ps=3.61u   pd=3.61u
+xm02 vss   a     z     vss sg13_lv_nmos  l=0.13u  w=0.44u  as=0.1166p   ad=0.1166p   ps=1.41u   pd=1.41u
+xm03 01    b     z     vdd sg13_lv_pmos  l=0.13u  w=1.54u  as=0.4081p   ad=0.4081p   ps=3.61u   pd=3.61u
+xm04 z     b     vss   vss sg13_lv_nmos  l=0.13u  w=0.44u  as=0.1166p   ad=0.1166p   ps=1.41u   pd=1.41u
+c4  a     vss   0.341f
+c3  b     vss   0.433f
+c2  z     vss   0.677f
+.ends
+.subckt or2 a b vdd vss z
+xm01 03    a     vdd   vdd sg13_lv_pmos  l=0.13u  w=1.155u as=0.306075p ad=0.306075p ps=2.84u   pd=2.84u
+xm02 sig1  a     vss   vss sg13_lv_nmos  l=0.13u  w=0.33u  as=0.08745p  ad=0.08745p  ps=1.19u   pd=1.19u
+xm03 sig1  b     03    vdd sg13_lv_pmos  l=0.13u  w=1.155u as=0.306075p ad=0.306075p ps=2.84u   pd=2.84u
+xm04 vss   b     sig1  vss sg13_lv_nmos  l=0.13u  w=0.33u  as=0.08745p  ad=0.08745p  ps=1.19u   pd=1.19u
+xm5  vdd   sig1  z     vdd sg13_lv_pmos  l=0.13u  w=0.99u  as=0.26235p  ad=0.26235p  ps=2.51u   pd=2.51u
+xm6  vss   sig1  z     vss sg13_lv_nmos  l=0.13u  w=0.495u as=0.131175p ad=0.131175p ps=1.52u   pd=1.52u
+c4  a     vss   0.464f
+c5  b     vss   0.507f
+c1  sig1  vss   0.619f
+c3  z     vss   0.593f
+.ends
+.subckt and4 a b c d vdd vss z
+xm01 10    a     vdd   vdd sg13_lv_pmos  l=0.13u  w=0.715u as=0.189475p ad=0.189475p ps=1.96u   pd=1.96u
+xm02 n1    a     vss   vss sg13_lv_nmos  l=0.13u  w=0.88u  as=0.2332p   ad=0.2332p   ps=2.29u   pd=2.29u
+xm03 vdd   b     10    vdd sg13_lv_pmos  l=0.13u  w=0.715u as=0.189475p ad=0.189475p ps=1.96u   pd=1.96u
+xm04 sig7  b     n1    vss sg13_lv_nmos  l=0.13u  w=0.88u  as=0.2332p   ad=0.2332p   ps=2.29u   pd=2.29u
+xm05 10    c     vdd   vdd sg13_lv_pmos  l=0.13u  w=0.715u as=0.189475p ad=0.189475p ps=1.96u   pd=1.96u
+xm06 n3    c     sig7  vss sg13_lv_nmos  l=0.13u  w=0.88u  as=0.2332p   ad=0.2332p   ps=2.29u   pd=2.29u
+xm07 vdd   d     10    vdd sg13_lv_pmos  l=0.13u  w=0.715u as=0.189475p ad=0.189475p ps=1.96u   pd=1.96u
+xm08 10    d     n3    vss sg13_lv_nmos  l=0.13u  w=0.88u  as=0.2332p   ad=0.2332p   ps=2.29u   pd=2.29u
+xm09 vdd   10    z     vdd sg13_lv_pmos  l=0.13u  w=0.99u  as=0.26235p  ad=0.26235p  ps=2.51u   pd=2.51u
+xm10 vss   10    z     vss sg13_lv_nmos  l=0.13u  w=0.495u as=0.131175p ad=0.131175p ps=1.52u   pd=1.52u
+c4  10    vss   0.940f
+c5  a     vss   0.674f
+c8  b     vss   0.541f
+c9  c     vss   0.622f
+c10 d     vss   0.791f
+c3  z     vss   0.765f
+.ends
+.subckt nor4 a b c d vdd vss z
+xm1a 1b    a     vdd   vdd sg13_lv_pmos  l=0.13u  w=1.375u as=0.364375p ad=0.364375p ps=3.28u   pd=3.28u
+xm1b sig8  b     1b    vdd sg13_lv_pmos  l=0.13u  w=1.375u as=0.364375p ad=0.364375p ps=3.28u   pd=3.28u
+xm1c 1d    c     sig8  vdd sg13_lv_pmos  l=0.13u  w=1.375u as=0.364375p ad=0.364375p ps=3.28u   pd=3.28u
+xm1d z     d     1d    vdd sg13_lv_pmos  l=0.13u  w=1.375u as=0.364375p ad=0.364375p ps=3.28u   pd=3.28u
+xm2a vdd   a     2a    vdd sg13_lv_pmos  l=0.13u  w=0.99u  as=0.26235p  ad=0.26235p  ps=2.51u   pd=2.51u
+xm2b 2a    b     sig11 vdd sg13_lv_pmos  l=0.13u  w=0.99u  as=0.26235p  ad=0.26235p  ps=2.51u   pd=2.51u
+xm2c sig11 c     2c    vdd sg13_lv_pmos  l=0.13u  w=0.99u  as=0.26235p  ad=0.26235p  ps=2.51u   pd=2.51u
+xm2d 2c    d     z     vdd sg13_lv_pmos  l=0.13u  w=0.99u  as=0.26235p  ad=0.26235p  ps=2.51u   pd=2.51u
+xm3a z     a     vss   vss sg13_lv_nmos  l=0.13u  w=0.33u  as=0.08745p  ad=0.08745p  ps=1.19u   pd=1.19u
+xm3b vss   b     z     vss sg13_lv_nmos  l=0.13u  w=0.33u  as=0.08745p  ad=0.08745p  ps=1.19u   pd=1.19u
+xm3c z     c     vss   vss sg13_lv_nmos  l=0.13u  w=0.33u  as=0.08745p  ad=0.08745p  ps=1.19u   pd=1.19u
+xm3d vss   d     z     vss sg13_lv_nmos  l=0.13u  w=0.33u  as=0.08745p  ad=0.08745p  ps=1.19u   pd=1.19u
+c4  a     vss   1.510f
+c3  b     vss   1.102f
+c6  c     vss   0.817f
+c5  d     vss   0.806f
+c2  z     vss   0.935f
+.ends
+.subckt not1 a vdd vss z
+xm01 vdd   a     z     vdd sg13_lv_pmos  l=0.13u  w=0.99u  as=0.26235p  ad=0.26235p  ps=2.51u   pd=2.51u
+xm02 vss   a     z     vss sg13_lv_nmos  l=0.13u  w=0.495u as=0.131175p ad=0.131175p ps=1.52u   pd=1.52u
+c3  a     vss   0.384f
+c2  z     vss   0.576f
+.ends
+.subckt and3 a b c vdd vss z
+xm01 08    a     vdd   vdd sg13_lv_pmos  l=0.13u  w=0.715u as=0.189475p ad=0.189475p ps=1.96u   pd=1.96u
+xm02 n1    a     vss   vss sg13_lv_nmos  l=0.13u  w=0.715u as=0.189475p ad=0.189475p ps=1.96u   pd=1.96u
+xm03 vdd   b     08    vdd sg13_lv_pmos  l=0.13u  w=0.715u as=0.189475p ad=0.189475p ps=1.96u   pd=1.96u
+xm04 sig6  b     n1    vss sg13_lv_nmos  l=0.13u  w=0.715u as=0.189475p ad=0.189475p ps=1.96u   pd=1.96u
+xm05 08    c     vdd   vdd sg13_lv_pmos  l=0.13u  w=0.715u as=0.189475p ad=0.189475p ps=1.96u   pd=1.96u
+xm06 08    c     sig6  vss sg13_lv_nmos  l=0.13u  w=0.715u as=0.189475p ad=0.189475p ps=1.96u   pd=1.96u
+xm07 vdd   08    z     vdd sg13_lv_pmos  l=0.13u  w=0.99u  as=0.26235p  ad=0.26235p  ps=2.51u   pd=2.51u
+xm08 vss   08    z     vss sg13_lv_nmos  l=0.13u  w=0.495u as=0.131175p ad=0.131175p ps=1.52u   pd=1.52u
+c4  08    vss   1.142f
+c5  a     vss   0.539f
+c7  b     vss   0.609f
+c8  c     vss   0.651f
+c3  z     vss   0.745f
+.ends
+.subckt or3 a b c vdd vss z
+xm01 01    a     vdd   vdd sg13_lv_pmos  l=0.13u  w=1.54u  as=0.4081p   ad=0.4081p   ps=3.61u   pd=3.61u
+xm02 sig1  a     vss   vss sg13_lv_nmos  l=0.13u  w=0.33u  as=0.08745p  ad=0.08745p  ps=1.19u   pd=1.19u
+xm03 03    b     01    vdd sg13_lv_pmos  l=0.13u  w=1.54u  as=0.4081p   ad=0.4081p   ps=3.61u   pd=3.61u
+xm04 vss   b     sig1  vss sg13_lv_nmos  l=0.13u  w=0.33u  as=0.08745p  ad=0.08745p  ps=1.19u   pd=1.19u
+xm05 sig1  c     03    vdd sg13_lv_pmos  l=0.13u  w=1.54u  as=0.4081p   ad=0.4081p   ps=3.61u   pd=3.61u
+xm06 sig1  c     vss   vss sg13_lv_nmos  l=0.13u  w=0.33u  as=0.08745p  ad=0.08745p  ps=1.19u   pd=1.19u
+xm07 vdd   sig1  z     vdd sg13_lv_pmos  l=0.13u  w=1.045u as=0.276925p ad=0.276925p ps=2.62u   pd=2.62u
+xm08 vss   sig1  z     vss sg13_lv_nmos  l=0.13u  w=0.495u as=0.131175p ad=0.131175p ps=1.52u   pd=1.52u
+c4  a     vss   0.544f
+c5  b     vss   0.535f
+c6  c     vss   0.625f
+c1  sig1  vss   0.995f
+c3  z     vss   0.544f
+.ends
+.subckt nand2 a b vdd vss z
+xm01 vdd   a     z     vdd sg13_lv_pmos  l=0.13u  w=0.77u  as=0.20405p  ad=0.20405p  ps=2.07u   pd=2.07u
+xm02 vss   a     sig3  vss sg13_lv_nmos  l=0.13u  w=0.66u  as=0.1749p   ad=0.1749p   ps=1.85u   pd=1.85u
+xm03 z     b     vdd   vdd sg13_lv_pmos  l=0.13u  w=0.77u  as=0.20405p  ad=0.20405p  ps=2.07u   pd=2.07u
+xm04 sig3  b     z     vss sg13_lv_nmos  l=0.13u  w=0.66u  as=0.1749p   ad=0.1749p   ps=1.85u   pd=1.85u
+c4  a     vss   0.549f
+c5  b     vss   0.578f
+c1  z     vss   0.609f
+.ends
+.subckt and2 a b vdd vss z
+xm01 06    a     vdd   vdd sg13_lv_pmos  l=0.13u  w=0.715u as=0.189475p ad=0.189475p ps=1.96u   pd=1.96u
+xm02 n1    a     vss   vss sg13_lv_nmos  l=0.13u  w=0.605u as=0.160325p ad=0.160325p ps=1.74u   pd=1.74u
+xm03 vdd   b     06    vdd sg13_lv_pmos  l=0.13u  w=0.715u as=0.189475p ad=0.189475p ps=1.96u   pd=1.96u
+xm04 06    b     n1    vss sg13_lv_nmos  l=0.13u  w=0.605u as=0.160325p ad=0.160325p ps=1.74u   pd=1.74u
+xm05 vdd   06    z     vdd sg13_lv_pmos  l=0.13u  w=0.99u  as=0.26235p  ad=0.26235p  ps=2.51u   pd=2.51u
+xm06 vss   06    z     vss sg13_lv_nmos  l=0.13u  w=0.495u as=0.131175p ad=0.131175p ps=1.52u   pd=1.52u
+c4  06    vss   0.724f
+c5  a     vss   0.663f
+c6  b     vss   0.538f
+c3  z     vss   0.595f
+.ends
+.subckt nor3 a b c vdd vss z
+xm01 sig6  a     vdd   vdd sg13_lv_pmos  l=0.13u  w=1.54u  as=0.4081p   ad=0.4081p   ps=3.61u   pd=3.61u
+xm02 vdd   a     02    vdd sg13_lv_pmos  l=0.13u  w=1.54u  as=0.4081p   ad=0.4081p   ps=3.61u   pd=3.61u
+xm03 vss   a     z     vss sg13_lv_nmos  l=0.13u  w=0.55u  as=0.14575p  ad=0.14575p  ps=1.63u   pd=1.63u
+xm04 04    b     sig6  vdd sg13_lv_pmos  l=0.13u  w=1.54u  as=0.4081p   ad=0.4081p   ps=3.61u   pd=3.61u
+xm05 02    b     08    vdd sg13_lv_pmos  l=0.13u  w=1.54u  as=0.4081p   ad=0.4081p   ps=3.61u   pd=3.61u
+xm06 z     b     vss   vss sg13_lv_nmos  l=0.13u  w=0.55u  as=0.14575p  ad=0.14575p  ps=1.63u   pd=1.63u
+xm07 z     c     04    vdd sg13_lv_pmos  l=0.13u  w=1.54u  as=0.4081p   ad=0.4081p   ps=3.61u   pd=3.61u
+xm08 08    c     z     vdd sg13_lv_pmos  l=0.13u  w=1.54u  as=0.4081p   ad=0.4081p   ps=3.61u   pd=3.61u
+xm09 vss   c     z     vss sg13_lv_nmos  l=0.13u  w=0.55u  as=0.14575p  ad=0.14575p  ps=1.63u   pd=1.63u
+c3  a     vss   0.957f
+c4  b     vss   0.895f
+c5  c     vss   0.693f
+c2  z     vss   0.834f
+.ends
+
+*.options noopiter ; gminsteps=500 srcsteps=0 noinit
+* simulation command:
+
+*.save V(g7529_1) V(g7509_0) V(g7484_1) V(g7477_1) V(g7460_0) V(g7503_1) V(g7522_0) V(g7485_1) V(g7453_0) V(g7474_0) V(g7500_0) V(g7514_0) V(g7546_1) V(g7549_0) V(g7467_0) V(g7491_0) V(g7456_0) V(g7495_1) V(g7545_0) V(g7473_0) V(g7541_0) V(g7448_1) V(g7525_1) V(g7550_1) V(g165_1) V(g7510_1) V(g7535_1) V(g7534_1) V(g7469_1) V(g7476_0) V(g7517_1) V(g7537_0) V(g7489_1) V(g7521_1) V(g7486_0) V(g7533_1) V(g7449_0) V(g7447_0) V(g7528_0) V(g7513_1) V(g7548_0) V(g7544_1) V(g7552_0) V(g7540_1) V(g7507_0) V(g7481_0) V(g7455_0) V(g7502_1) V(g7446_1) V(g7478_1) V(g7470_0) V(g7526_0) V(g7494_1) V(g7452_1) V(g7463_0) V(g7532_1) V(g7512_0) V(g7527_0) V(g7451_0) V(g7472_0) V(g7498_1) V(g7475_0) V(g7536_0) V(g7488_1) V(g7493_1) V(g7551_1) V(g7482_0) V(g7487_1) V(g7501_1) V(g7520_1) V(g7516_1) V(g7450_1) V(g7508_0) V(g7458_1) V(g7479_1) V(g7506_1) V(g7499_0) V(g7471_0) V(g7465_1) V(g7464_1) V(g7543_1) V(g7524_0) V(g7539_1) V(g7468_1) V(g7459_0) V(g7504_1) V(g7515_1) V(g7492_1) V(g7511_0) V(g7462_1) V(g7530_0) V(g7497_1) V(g7454_1) V(g7519_1) V(g7531_0) V(g7547_0) V(g7483_1) V(g7466_1) V(g7480_1) V(g7523_1) V(g7496_0) V(g7538_0) V(g7490_1) V(g7518_1) V(g7461_0) V(g7542_0) V(g7457_0) V(g7505_1)
+.tran 1ps 10ns 0 20p uic
+.print tran  V(g7529_1) V(g7509_0) V(g7484_1) V(g7477_1) V(g7460_0) V(g7503_1) V(g7522_0) V(g7485_1) V(g7453_0) V(g7474_0) V(g7500_0) V(g7514_0) V(g7546_1) V(g7549_0) V(g7467_0) V(g7491_0) V(g7456_0) V(g7495_1) V(g7545_0) V(g7473_0) V(g7541_0) V(g7448_1) V(g7525_1) V(g7550_1) V(g165_1) V(g7510_1) V(g7535_1) V(g7534_1) V(g7469_1) V(g7476_0) V(g7517_1) V(g7537_0) V(g7489_1) V(g7521_1) V(g7486_0) V(g7533_1) V(g7449_0) V(g7447_0) V(g7528_0) V(g7513_1) V(g7548_0) V(g7544_1) V(g7552_0) V(g7540_1) V(g7507_0) V(g7481_0) V(g7455_0) V(g7502_1) V(g7446_1) V(g7478_1) V(g7470_0) V(g7526_0) V(g7494_1) V(g7452_1) V(g7463_0) V(g7532_1) V(g7512_0) V(g7527_0) V(g7451_0) V(g7472_0) V(g7498_1) V(g7475_0) V(g7536_0) V(g7488_1) V(g7493_1) V(g7551_1) V(g7482_0) V(g7487_1) V(g7501_1) V(g7520_1) V(g7516_1) V(g7450_1) V(g7508_0) V(g7458_1) V(g7479_1) V(g7506_1) V(g7499_0) V(g7471_0) V(g7465_1) V(g7464_1) V(g7543_1) V(g7524_0) V(g7539_1) V(g7468_1) V(g7459_0) V(g7504_1) V(g7515_1) V(g7492_1) V(g7511_0) V(g7462_1) V(g7530_0) V(g7497_1) V(g7454_1) V(g7519_1) V(g7531_0) V(g7547_0) V(g7483_1) V(g7466_1) V(g7480_1) V(g7523_1) V(g7496_0) V(g7538_0) V(g7490_1) V(g7518_1) V(g7461_0) V(g7542_0) V(g7457_0) V(g7505_1)
+
+.end
diff --git a/ihp-sg13g2/libs.tech/xyce/examples/c7552_ann_psp.plt b/ihp-sg13g2/libs.tech/xyce/examples/c7552_ann_psp.plt
new file mode 100644
index 00000000..eb45cc81
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/examples/c7552_ann_psp.plt
@@ -0,0 +1,13 @@
+#set terminal postscript eps color
+#set output "c7552_ann_psp.eps"
+
+set title "c7552 ann psp"
+
+set grid
+set key left top
+set format x "%.1s%c"
+set format y "%.1s%c"
+set xlabel "time"
+set ylabel "Voltage"
+plot 'c7552_ann_psp.cir.prn' using 2:($3) t "g7529_1" w lines,\
+     'c7552_ann_psp.cir.prn' using 2:($4) t "g7509_0" w lines
diff --git a/ihp-sg13g2/libs.tech/xyce/examples/hv_nmos_id_vd_vg.cir b/ihp-sg13g2/libs.tech/xyce/examples/hv_nmos_id_vd_vg.cir
new file mode 100644
index 00000000..038af190
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/examples/hv_nmos_id_vd_vg.cir
@@ -0,0 +1,16 @@
+psp103 nch output
+*
+vd  d 0 dc 0.05
+vg  g 0 dc 0.0
+vs  s 0 dc 0.0
+vb  b 0 dc 0.0
+X1  d g s b sg13_hv_nmos w=2u l=0.5u mult=1
+
+.option temp=27
+.step vg 0 3 0.5
+.dc vd 0 3.0 0.05
+.print dc format=gnuplot v(d) i(vs)
+
+.lib ../models/cornerMOShv.lib mos_tt
+
+.end
diff --git a/ihp-sg13g2/libs.tech/xyce/examples/hv_nmos_id_vd_vg.plt b/ihp-sg13g2/libs.tech/xyce/examples/hv_nmos_id_vd_vg.plt
new file mode 100644
index 00000000..1ab394b2
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/examples/hv_nmos_id_vd_vg.plt
@@ -0,0 +1,12 @@
+#set terminal postscript eps color
+#set output "hv_nmos_id_vd_vg.eps"
+
+set title "Id=f(Vds) Vg=0...3V Temp: 27degC"
+
+set grid
+set key left top
+set format x "%.1s%c"
+set format y "%.1s%c"
+set xlabel "Vds [V]"
+set ylabel "Id [A]"
+plot 'hv_nmos_id_vd_vg.cir.prn' using 2:($3) t "Id" w lp
diff --git a/ihp-sg13g2/libs.tech/xyce/examples/hv_nmos_id_vg_vb.cir b/ihp-sg13g2/libs.tech/xyce/examples/hv_nmos_id_vg_vb.cir
new file mode 100644
index 00000000..d3237e68
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/examples/hv_nmos_id_vg_vb.cir
@@ -0,0 +1,17 @@
+psp103 test circuit
+*
+vd  d 0 dc 0.05
+vg  g 0 dc 0.0
+vs  s 0 dc 0.0
+vb  b 0 dc 0.0
+X1  d g s b sg13_hv_nmos w=2u l=0.5u mult=1
+
+.option temp=27
+.step  vb -3 0 0.25
+.dc vg 0 3 0.02
+.print dc format=gnuplot v(g) i(vd)
+
+.lib ../models/cornerMOShv.lib mos_tt
+
+.end
+
diff --git a/ihp-sg13g2/libs.tech/xyce/examples/hv_nmos_id_vg_vb.plt b/ihp-sg13g2/libs.tech/xyce/examples/hv_nmos_id_vg_vb.plt
new file mode 100644
index 00000000..379f598c
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/examples/hv_nmos_id_vg_vb.plt
@@ -0,0 +1,13 @@
+#set terminal postscript eps color
+#set output "hv_nmos_id_vg_vb.eps"
+
+set title "Id=f(Vgs) Vd=50mV Temp: 27degC"
+
+set grid
+set key left top
+set format x "%.1s%c"
+set format y "%.1s%c"
+set xlabel "Vgs [V]"
+set ylabel "Id [A]"
+set logscale y
+plot 'hv_nmos_id_vg_vb.cir.prn' using 2:(-$3) t "Id" w lp
diff --git a/ihp-sg13g2/libs.tech/xyce/examples/hv_pmos_id_vd_vg.cir b/ihp-sg13g2/libs.tech/xyce/examples/hv_pmos_id_vd_vg.cir
new file mode 100644
index 00000000..193f30e1
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/examples/hv_pmos_id_vd_vg.cir
@@ -0,0 +1,16 @@
+psp103 pch output
+*
+vd  d 0 dc -0.05
+vg  g 0 dc 0.0
+vs  s 0 dc 0.0
+vb  b 0 dc 0.0
+X1  d g s b sg13_hv_pmos w=2u l=0.5u mult=1
+
+.option temp=27
+.step vg -3 0 0.25
+.dc vd -3.0 0.0 0.05
+.print dc format=gnuplot v(d) i(vs)
+
+.lib ../models/cornerMOShv.lib mos_tt
+
+.end
diff --git a/ihp-sg13g2/libs.tech/xyce/examples/hv_pmos_id_vd_vg.plt b/ihp-sg13g2/libs.tech/xyce/examples/hv_pmos_id_vd_vg.plt
new file mode 100644
index 00000000..d561a7e5
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/examples/hv_pmos_id_vd_vg.plt
@@ -0,0 +1,12 @@
+#set terminal postscript eps color
+#set output "hv_pmos_id_vd_vg.eps"
+
+set title "Id=f(Vds) Vg=-3...0V Temp: 27degC"
+
+set grid
+set key left top
+set format x "%.1s%c"
+set format y "%.1s%c"
+set xlabel "Vds [V]"
+set ylabel "Id [A]"
+plot 'hv_pmos_id_vd_vg.cir.prn' using 2:($3) t "Id" w lp
diff --git a/ihp-sg13g2/libs.tech/xyce/examples/hv_pmos_id_vg_vb.cir b/ihp-sg13g2/libs.tech/xyce/examples/hv_pmos_id_vg_vb.cir
new file mode 100644
index 00000000..b2f26406
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/examples/hv_pmos_id_vg_vb.cir
@@ -0,0 +1,16 @@
+psp103 pch transfer
+*
+vd  d 0 dc -0.05
+vg  g 0 dc 0.0
+vs  s 0 dc 0.0
+vb  b 0 dc 0.0
+X1  d g s b sg13_hv_pmos w=2u l=0.5u mult=1
+*
+.option temp=27
+.step vb 0 3 0.25
+.dc vg -3 0.0 0.02
+.print dc format=gnuplot v(g) i(vs)
+
+.lib ../models/cornerMOShv.lib mos_tt
+
+.end
diff --git a/ihp-sg13g2/libs.tech/xyce/examples/hv_pmos_id_vg_vb.plt b/ihp-sg13g2/libs.tech/xyce/examples/hv_pmos_id_vg_vb.plt
new file mode 100644
index 00000000..2f308c57
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/examples/hv_pmos_id_vg_vb.plt
@@ -0,0 +1,12 @@
+#set terminal postscript eps color
+#set output "hv_pmos_id_vg_vb.eps"
+
+set title "Id=f(Vgs) Vb=-3...0V Temp: 27degC"
+
+set grid
+set key left top
+set format x "%.1s%c"
+set format y "%.1s%c"
+set xlabel "Vgs [V]"
+set ylabel "Id [A]"
+plot 'hv_pmos_id_vg_vb.cir.prn' using 2:($3) t "Id" w lp
diff --git a/ihp-sg13g2/libs.tech/xyce/examples/lv_nmos_id_vd_vg.cir b/ihp-sg13g2/libs.tech/xyce/examples/lv_nmos_id_vd_vg.cir
new file mode 100644
index 00000000..5eec0329
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/examples/lv_nmos_id_vd_vg.cir
@@ -0,0 +1,16 @@
+psp103 nch output
+*
+vd  d 0 dc 0.05
+vg  g 0 dc 0.0
+vs  s 0 dc 0.0
+vb  b 0 dc 0.0
+X1  d g s b sg13_lv_nmos w=1u l=0.13u mult=1
+
+.option temp=27
+.step vg 0 1.5 0.25
+.dc vd 0 2.0 0.05
+.print dc format=gnuplot v(d) i(vs)
+
+.lib ../models/cornerMOSlv.lib mos_tt
+
+.end
diff --git a/ihp-sg13g2/libs.tech/xyce/examples/lv_nmos_id_vd_vg.plt b/ihp-sg13g2/libs.tech/xyce/examples/lv_nmos_id_vd_vg.plt
new file mode 100644
index 00000000..e2fd7748
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/examples/lv_nmos_id_vd_vg.plt
@@ -0,0 +1,12 @@
+#set terminal postscript eps color
+#set output "lv_nmos_id_vd_vg.eps"
+
+set title "Id=f(Vds) Vg=0...1.5V Temp: 27degC"
+
+set grid
+set key left top
+set format x "%.1s%c"
+set format y "%.1s%c"
+set xlabel "Vds [V]"
+set ylabel "Id [A]"
+plot 'lv_nmos_id_vd_vg.cir.prn' using 2:($3) t "Id" w lp
diff --git a/ihp-sg13g2/libs.tech/xyce/examples/lv_nmos_id_vg_vb.cir b/ihp-sg13g2/libs.tech/xyce/examples/lv_nmos_id_vg_vb.cir
new file mode 100644
index 00000000..6d49dfd3
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/examples/lv_nmos_id_vg_vb.cir
@@ -0,0 +1,17 @@
+psp103 test circuit
+*
+vd  d 0 dc 0.1
+vg  g 0 dc 0.0
+vs  s 0 dc 0.0
+vb  b 0 dc 0.0
+X1  d g s b sg13_lv_nmos w=1u l=0.13u mult=1
+
+.option temp=27
+.step  vb -1.5 0 0.25
+.dc vg 0 1.5 0.02
+.print dc format=gnuplot v(g) i(vd)
+
+.lib ../models/cornerMOSlv.lib mos_tt
+
+.end
+
diff --git a/ihp-sg13g2/libs.tech/xyce/examples/lv_nmos_id_vg_vb.plt b/ihp-sg13g2/libs.tech/xyce/examples/lv_nmos_id_vg_vb.plt
new file mode 100644
index 00000000..edfb5c25
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/examples/lv_nmos_id_vg_vb.plt
@@ -0,0 +1,13 @@
+#set terminal postscript eps color
+#set output "lv_nmos_id_vg_vb.eps"
+
+set title "Id=f(Vgs) Vd=50mV Temp: 27degC"
+
+set grid
+set key left top
+set format x "%.1s%c"
+set format y "%.1s%c"
+set xlabel "Vgs [V]"
+set ylabel "Id [A]"
+set logscale y
+plot 'lv_nmos_id_vg_vb.cir.prn' using 2:(-$3) t "Id" w lp
diff --git a/ihp-sg13g2/libs.tech/xyce/examples/lv_nmos_pmos_id_vd_vg_temp.cir b/ihp-sg13g2/libs.tech/xyce/examples/lv_nmos_pmos_id_vd_vg_temp.cir
new file mode 100644
index 00000000..63c685f1
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/examples/lv_nmos_pmos_id_vd_vg_temp.cir
@@ -0,0 +1,40 @@
+***  NMOS and PMOS transistors PSP 103.8 (Id-Vgs, Vbs) (Id-Vds, Vgs) (Id-Vgs, T)  ***
+
+X1  d g s b sg13_lv_nmos w=1u l=0.13u mult=1
+
+vgsn 1 0 3.5
+vdsn 2 0 0.1
+vssn 3 0 0
+vbsn 4 0 0
+
+X1  d g s b sg13_lv_pmos w=1u l=0.13u mult=1
+
+vgsp 11 0 -3.5
+vdsp 22 0 -0.1
+vssp 33 0 0
+vbsp 44 0 0
+
+* PSP modelparameters for PSP 103.3
+.lib ../models/cornerMOSlv.lib mos_tt
+
+* NMOS
+.dc vgsn 0 1.5 0.05 vbsn 0 -1.5 -0.3
+.print dc format=gnuplot vssn#branch ylabel 'Id vs. Vgs, Vbs 0 ... -1.5'
+.print dc format=gnuplot abs(vssn#branch) ylog ylabel 'Id vs. Vgs, Vbs 0 ... -1.5'
+*.dc vdsn 0 1.6 0.01 vgsn 0 1.6 0.2
+*.print dc format=gnuplot vssn#branch ylabel 'Id vs. Vds, Vgs 0 ... 1.6'
+*.dc vgsn 0 1.5 0.05 temp -40 160 40
+*.print dc format=gnuplot vssn#branch ylabel 'Id vs. Vds, Temp. -40 ... 160'
+*.print dc format=gnuplot abs(vssn#branch) ylog ylabel 'Id vs. Vds, Temp. -40 ... 160'
+
+* PMOS
+.dc vgsp 0 -1.5 -0.05 vbsp 0 1.5 0.3
+.print dc format=gnuplot vssp#branch ylabel 'Id vs. Vgs, Vbs 0 ... 1.5'
+.print dc format=gnuplot abs(vssp#branch) ylog ylabel 'Id vs. Vgs, Vbs 0 ... 1.5'
+*.dc vdsp 0 -1.6 -0.01 vgsp 0 -1.6 -0.2
+*.print dc format=gnuplot vssp#branch ylabel 'Id vs. Vds, Vgs 0 ... -1.6'
+*.dc vgsp 0 -1.5 -0.05 temp -40 160 40
+*.print dc format=gnuplot vssp#branch ylabel 'Id vs. Vds, Temp. -40 ... 160'
+*.print dc format=gnuplot abs(vssp#branch) ylog ylabel 'Id vs. Vds, Temp. -40 ... 160'
+
+.end
diff --git a/ihp-sg13g2/libs.tech/xyce/examples/lv_pmos_id_vd_vg.cir b/ihp-sg13g2/libs.tech/xyce/examples/lv_pmos_id_vd_vg.cir
new file mode 100644
index 00000000..ca1c5d29
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/examples/lv_pmos_id_vd_vg.cir
@@ -0,0 +1,16 @@
+psp103 pch output
+*
+vd  d 0 dc -0.1
+vg  g 0 dc 0.0
+vs  s 0 dc 0.0
+vb  b 0 dc 0.0
+X1  d g s b sg13_lv_pmos w=1u l=0.13u mult=1
+
+.option temp=27
+.step vg -1.5 0 0.25
+.dc vd -2.0 0.0 0.05
+.print dc format=gnuplot v(d) i(vs)
+
+.lib ../models/cornerMOSlv.lib mos_tt
+
+.end
diff --git a/ihp-sg13g2/libs.tech/xyce/examples/lv_pmos_id_vd_vg.plt b/ihp-sg13g2/libs.tech/xyce/examples/lv_pmos_id_vd_vg.plt
new file mode 100644
index 00000000..3010ef6e
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/examples/lv_pmos_id_vd_vg.plt
@@ -0,0 +1,12 @@
+#set terminal postscript eps color
+#set output "lv_pmos_id_vd_vg.eps"
+
+set title "Id=f(Vds) Vg=-1.5...0V Temp: 27degC"
+
+set grid
+set key left top
+set format x "%.1s%c"
+set format y "%.1s%c"
+set xlabel "Vds [V]"
+set ylabel "Id [A]"
+plot 'lv_pmos_id_vd_vg.cir.prn' using 2:($3) t "Id" w lp
diff --git a/ihp-sg13g2/libs.tech/xyce/examples/lv_pmos_id_vg_vb.cir b/ihp-sg13g2/libs.tech/xyce/examples/lv_pmos_id_vg_vb.cir
new file mode 100644
index 00000000..2107487b
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/examples/lv_pmos_id_vg_vb.cir
@@ -0,0 +1,16 @@
+psp103 pch transfer
+*
+vd  d 0 dc -0.1
+vg  g 0 dc 0.0
+vs  s 0 dc 0.0
+vb  b 0 dc 0.0
+X1  d g s b sg13_lv_pmos w=1u l=0.13u mult=1
+*
+.option temp=27
+.step vb 0 1.5 0.25
+.dc vg -1.5 0.0 0.02
+.print dc format=gnuplot v(g) i(vs)
+
+.lib ../models/cornerMOSlv.lib mos_tt
+
+.end
diff --git a/ihp-sg13g2/libs.tech/xyce/examples/lv_pmos_id_vg_vb.plt b/ihp-sg13g2/libs.tech/xyce/examples/lv_pmos_id_vg_vb.plt
new file mode 100644
index 00000000..33976f1f
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/examples/lv_pmos_id_vg_vb.plt
@@ -0,0 +1,12 @@
+#set terminal postscript eps color
+#set output "lv_pmos_id_vg_vb.eps"
+
+set title "Id=f(Vgs) Vb=-1.5...0V Temp: 27degC"
+
+set grid
+set key left top
+set format x "%.1s%c"
+set format y "%.1s%c"
+set xlabel "Vgs [V]"
+set ylabel "Id [A]"
+plot 'lv_pmos_id_vg_vb.cir.prn' using 2:($3) t "Id" w lp
diff --git a/ihp-sg13g2/libs.tech/xyce/examples/npn13G2_gain.cir b/ihp-sg13g2/libs.tech/xyce/examples/npn13G2_gain.cir
new file mode 100644
index 00000000..1667665f
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/examples/npn13G2_gain.cir
@@ -0,0 +1,20 @@
+VBIC AC gain Test h21 = f(Ic) Vce=1V
+
+vce 1 0 dc 1.0
+vgain 1 c dc 0.0
+f 0 2 vgain -2
+l 2 b 1g
+c 2 0 1g
+ib 0 b dc 0.0 ac 1.0
+ic 0 c 0.01
+XQ1 C B 0 S t npn13G2 nx=4
+
+.step dec ic 50u 5m 4
+*.op
+.ac dec 10 100Meg 1000g
+.print ac format=gnuplot idb(vgain)
+.measure ac FT when idb(vgain)=0
+
+.lib ../models/cornerHBT.lib hbt_typ
+
+.end
diff --git a/ihp-sg13g2/libs.tech/xyce/examples/npn13G2_gain.plt b/ihp-sg13g2/libs.tech/xyce/examples/npn13G2_gain.plt
new file mode 100644
index 00000000..188a45bf
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/examples/npn13G2_gain.plt
@@ -0,0 +1,14 @@
+#set terminal postscript eps color
+#set output "npn13G2_gain.eps"
+
+set title "vbic gain stage Ic=50u...5m"
+
+set grid
+set key left top
+set format x "%.1s%c"
+set format y "%.1s%c"
+set xlabel "frequency [Hz]"
+set ylabel "Gain [dB]"
+set yrange [0:]
+set log x
+plot 'npn13G2_gain.cir.FD.prn' using 2:($3) t "C" w lines
diff --git a/ihp-sg13g2/libs.tech/xyce/examples/npn13G2_ic_ib_is_vb.cir b/ihp-sg13g2/libs.tech/xyce/examples/npn13G2_ic_ib_is_vb.cir
new file mode 100644
index 00000000..09a3bc03
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/examples/npn13G2_ic_ib_is_vb.cir
@@ -0,0 +1,13 @@
+VBIC Gummel Test Ic=f(Vc,Vb)
+
+.lib ../models/cornerHBT.lib hbt_typ
+
+vb b 0 0.5
+vc c 0 1.0
+vs s 0 0.0
+XQ1 C B 0 S t npn13G2 nx=1
+
+.dc vb 0.2 1.2 0.01
+.print dc v(b) i(vc) i(vb) i(vs)
+
+.end
diff --git a/ihp-sg13g2/libs.tech/xyce/examples/npn13G2_ic_ib_is_vb.plt b/ihp-sg13g2/libs.tech/xyce/examples/npn13G2_ic_ib_is_vb.plt
new file mode 100644
index 00000000..73a6a012
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/examples/npn13G2_ic_ib_is_vb.plt
@@ -0,0 +1,15 @@
+#set terminal postscript eps color
+#set output "npn13G2_ic_ib_is_vb.eps"
+
+set title "Ic,b,s=f(Vbe) Ve,Vs=0V Temp: 27degC"
+
+set grid
+set key left top
+set format x "%.1s%c"
+set format y "%.1s%c"
+set xlabel "Vbe [V]"
+set ylabel "Ic [A]"
+set logscale y
+plot 'npn13G2_ic_ib_is_vb.cir.prn' using 2:(-$3) t "Ic" w lp,\
+     'npn13G2_ic_ib_is_vb.cir.prn' using 2:(-$4) t "Ib" w lp,\
+     'npn13G2_ic_ib_is_vb.cir.prn' using 2:($5) t "Is" w lp
diff --git a/ihp-sg13g2/libs.tech/xyce/examples/npn13G2_ic_vc_ib.cir b/ihp-sg13g2/libs.tech/xyce/examples/npn13G2_ic_vc_ib.cir
new file mode 100644
index 00000000..e540ff42
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/examples/npn13G2_ic_vc_ib.cir
@@ -0,0 +1,14 @@
+VBIC Test Ic=f(Vc,Ib)
+
+.lib ../models/cornerHBT.lib hbt_typ
+
+ib 0 b 10u
+vc c 0 1.0
+vs s 0 0.0
+XQ1 C B 0 S t npn13G2 nx=4
+
+.step ib 2u 10u 2u
+.dc vc 0.0 2.0 0.01
+.print dc format=gnuplot v(c) i(vc) i(vs)
+
+.end
diff --git a/ihp-sg13g2/libs.tech/xyce/examples/npn13G2_ic_vc_ib.plt b/ihp-sg13g2/libs.tech/xyce/examples/npn13G2_ic_vc_ib.plt
new file mode 100644
index 00000000..03e5f8c6
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/examples/npn13G2_ic_vc_ib.plt
@@ -0,0 +1,12 @@
+#set terminal postscript eps color
+#set output "npn13G2_ic_vc_ib.eps"
+
+set title "Ic=f(Vce,Ib) Ve,Vs=0V Temp: 27degC"
+
+set grid
+set key left top
+set format x "%.1s%c"
+set format y "%.1s%c"
+set xlabel "Vce [V]"
+set ylabel "Ic [A]"
+plot 'npn13G2_ic_vc_ib.cir.prn' using 2:(-$3) t "Ic" w l
diff --git a/ihp-sg13g2/libs.tech/xyce/examples/psp_inverter.cir b/ihp-sg13g2/libs.tech/xyce/examples/psp_inverter.cir
new file mode 100644
index 00000000..17480205
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/examples/psp_inverter.cir
@@ -0,0 +1,29 @@
+* PSP models
+* simple inverter
+
+* Path to the models
+.lib ../models/cornerMOSlv.lib mos_tt
+
+* the voltage sources: 
+Vdd vdd 0 DC 1.2
+V1 in 0 pulse(0 1.2 0p 200p 100p 1n 2n)
+Vmeas vss 0 0
+
+Xnot1 in vdd vss out not1
+Rout out 0 10k
+
+.subckt not1 a vdd vss z
+xm01   z a     vdd     vdd sg13_lv_pmos  l=0.13u  w=1u  as=0.26235p  ad=0.26235p  ps=2.51u   pd=2.51u
+xm02   z a     vss     vss sg13_lv_nmos  l=0.13u  w=0.5u as=0.131175p ad=0.131175p ps=1.52u   pd=1.52u
+c3  a     vss   0.384f
+c2  z     vss   0.576f
+.ends
+
+* simulation command: 
+.tran 10ps 10ns
+*.dc V1 0 'vcc' 'vcc/100'
+.print tran format=gnuplot v(in) v(out)
+*plot dc1.out
+*plot dc1.i(Vmeas)
+
+.end
diff --git a/ihp-sg13g2/libs.tech/xyce/examples/psp_inverter.plt b/ihp-sg13g2/libs.tech/xyce/examples/psp_inverter.plt
new file mode 100644
index 00000000..cac28336
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/examples/psp_inverter.plt
@@ -0,0 +1,13 @@
+#set terminal postscript eps color
+#set output "psp_inverter.eps"
+
+set title "psp inverter"
+
+set grid
+set key left top
+set format x "%.1s%c"
+set format y "%.1s%c"
+set xlabel "time"
+set ylabel "Voltage"
+plot 'psp_inverter.cir.prn' using 2:($3) t "in" w lines,\
+     'psp_inverter.cir.prn' using 2:($4) t "out" w lines
diff --git a/ihp-sg13g2/libs.tech/xyce/examples/psp_ro.cir b/ihp-sg13g2/libs.tech/xyce/examples/psp_ro.cir
new file mode 100644
index 00000000..50b3fd0e
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/examples/psp_ro.cir
@@ -0,0 +1,33 @@
+* PSP models
+* simple 5-stage ring oscillator
+
+* Path to the models
+.lib ../models/cornerMOSlv.lib mos_tt
+
+* the voltage sources: 
+Vdd vdd 0 DC 1.2
+*V1 in 0 pulse(0 1.2 0p 200p 100p 1n 20n)
+Vmeas vss 0 0
+
+Xnot1 in vdd vss in2 not1
+Xnot2 in2 vdd vss in3 not1
+Xnot3 in3 vdd vss in4 not1
+Xnot4 in4 vdd vss in5 not1
+Xnot5 in5 vdd vss in not1
+
+*Rout out 0 1k
+
+.subckt not1 a vdd vss z
+xm01   z a     vdd     vdd sg13_lv_pmos  l=0.13u  w=1u  as=0.26235p  ad=0.26235p  ps=2.51u   pd=2.51u
+xm02   z a     vss     vss sg13_lv_nmos  l=0.13u  w=0.5u as=0.131175p ad=0.131175p ps=1.52u   pd=1.52u
+c3  a     vss   0.384f
+c2  z     vss   0.576f
+.ends
+
+.ic v(in5)=1.2
+* simulation command: 
+.tran 1p 2n uic
+
+.print tran v(in) 
+
+.end
diff --git a/ihp-sg13g2/libs.tech/xyce/examples/psp_ro.plt b/ihp-sg13g2/libs.tech/xyce/examples/psp_ro.plt
new file mode 100644
index 00000000..695f2342
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/examples/psp_ro.plt
@@ -0,0 +1,12 @@
+#set terminal postscript eps color
+#set output "psp_ro.eps"
+
+set title "ringosc 5 stages"
+
+set grid
+set key left top
+set format x "%.1s%c"
+set format y "%.1s%c"
+set xlabel "time"
+set ylabel "Voltage"
+plot 'psp_ro.cir.prn' using 2:($3) t "in" w lines
diff --git a/ihp-sg13g2/libs.tech/xyce/models/cornerHBT.lib b/ihp-sg13g2/libs.tech/xyce/models/cornerHBT.lib
new file mode 100644
index 00000000..b90709e9
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/models/cornerHBT.lib
@@ -0,0 +1,152 @@
+*#######################################################################
+*
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+*#######################################################################
+       
+.LIB hbt_typ
+.param vbic_cje = 1.0
+.param vbic_cjc = 1.0
+.param vbic_cjcp = 1.0
+.param vbic_is = 1.0
+.param vbic_ibei = 1.0
+.param vbic_re = 1.0
+.param vbic_rcx = 1.0
+.param vbic_rbx = 1.0
+.param vbic_tf = 1.0
+
+.param sgp_mpa_cje = 1.0
+.param sgp_mpa_cjc = 1.0
+.param sgp_mpa_is = 1.0
+.param sgp_mpa_bf = 1.0
+.param sgp_mpa_re = 1.0
+.param sgp_mpa_rb = 1.0
+.param sgp_mpa_rc = 1.0
+
+.include sg13g2_hbt_mod.lib
+.ENDL hbt_typ
+       
+.LIB hbt_typ_stat
+.param vbic_cje_norm = 1.0 
+.param vbic_cjc_norm = 1.0
+.param vbic_cjcp_norm = 1.0
+.param vbic_is_norm = 1.0
+.param vbic_ibei_norm = 1.0
+.param vbic_re_norm = 1.0
+.param vbic_rcx_norm = 1.0
+.param vbic_rbx_norm = 1.0
+.param vbic_tf = 1.0
+
+.param sgp_mpa_cje_norm = 1.0
+.param sgp_mpa_cjc_norm = 1.0
+.param sgp_mpa_is_norm = 1.0
+.param sgp_mpa_bf_norm = 1.0
+.param sgp_mpa_re_norm = 1.0
+.param sgp_mpa_rb_norm = 1.0
+.param sgp_mpa_rc_norm = 1.0
+
+.include sg13g2_hbt_stat.lib
+.include sg13g2_hbt_mod.lib
+.ENDL hbt_typ_stat
+           
+.LIB hbt_bcs
+.param vbic_cje = 0.83
+.param vbic_cjc = 0.87
+.param vbic_cjcp = 0.89
+.param vbic_is = 1.26
+.param vbic_ibei = 0.67
+.param vbic_re = 0.73
+.param vbic_rcx = 0.79
+.param vbic_rbx = 0.88
+.param vbic_tf = 0.89
+
+.param sgp_mpa_cje = 0.955
+.param sgp_mpa_cjc = 0.98
+.param sgp_mpa_is = 1.13
+.param sgp_mpa_bf = 1.24
+.param sgp_mpa_re = 0.952
+.param sgp_mpa_rb = 0.975
+.param sgp_mpa_rc = 0.95
+
+.include sg13g2_hbt_mod.lib
+.ENDL hbt_bcs
+       
+.LIB hbt_bcs_stat
+.param vbic_cje_norm = 0.83 
+.param vbic_cjc_norm = 0.87
+.param vbic_cjcp_norm = 0.89
+.param vbic_is_norm = 1.26
+.param vbic_ibei_norm = 0.67
+.param vbic_re_norm = 0.73
+.param vbic_rcx_norm = 0.79
+.param vbic_rbx_norm = 0.88
+.param vbic_tf = 0.89
+
+.param sgp_mpa_cje_norm = 0.955
+.param sgp_mpa_cjc_norm = 0.98
+.param sgp_mpa_is_norm = 1.13
+.param sgp_mpa_bf_norm = 1.24
+.param sgp_mpa_re_norm = 0.952
+.param sgp_mpa_rb_norm = 0.975
+.param sgp_mpa_rc_norm = 0.95
+
+.include sg13g2_hbt_stat.lib
+.include sg13g2_hbt_mod.lib
+.ENDL hbt_bcs_stat
+           
+.LIB hbt_wcs
+.param vbic_cje = 1.17
+.param vbic_cjc = 1.13
+.param vbic_cjcp = 1.11
+.param vbic_is = 0.74
+.param vbic_ibei = 1.33
+.param vbic_re = 1.27
+.param vbic_rcx = 1.21
+.param vbic_rbx = 1.12
+.param vbic_tf = 1.11
+
+.param sgp_mpa_cje = 1.045
+.param sgp_mpa_cjc = 1.02
+.param sgp_mpa_is = 0.87
+.param sgp_mpa_bf = 0.76
+.param sgp_mpa_re = 1.048
+.param sgp_mpa_rb = 1.025
+.param sgp_mpa_rc = 1.05
+
+.include sg13g2_hbt_mod.lib
+.ENDL hbt_wcs
+       
+.LIB hbt_wcs_stat
+.param vbic_cje_norm = 1.17 
+.param vbic_cjc_norm = 1.13
+.param vbic_cjcp_norm = 1.11
+.param vbic_is_norm = 0.74
+.param vbic_ibei_norm = 1.33
+.param vbic_re_norm = 1.27
+.param vbic_rcx_norm = 1.21
+.param vbic_rbx_norm = 1.12
+.param vbic_tf = 1.11
+
+.param sgp_mpa_cje_norm = 1.045
+.param sgp_mpa_cjc_norm = 1.02
+.param sgp_mpa_is_norm = 0.87
+.param sgp_mpa_bf_norm = 0.76
+.param sgp_mpa_re_norm = 1.048
+.param sgp_mpa_rb_norm = 1.025
+.param sgp_mpa_rc_norm = 1.05
+
+.include sg13g2_hbt_stat.lib
+.include sg13g2_hbt_mod.lib
+.ENDL hbt_wcs_stat
diff --git a/ihp-sg13g2/libs.tech/xyce/models/cornerMOShv.lib b/ihp-sg13g2/libs.tech/xyce/models/cornerMOShv.lib
new file mode 100644
index 00000000..0a199dc5
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/models/cornerMOShv.lib
@@ -0,0 +1,557 @@
+******************************************************************************* 
+*                                                                             * 
+* Library:      SG13G2_dev                                                    * 
+* Technologies: SG13G2                                                        *
+* Component:    Spectre model file for Spectre 18                             *
+*                                                                             *
+* Simulator:    Spectre 20.1                                                  *
+* Model:        PSP 103.6                                                     *
+* Revision:     210511                                                        * 
+*                                                                             * 
+******************************************************************************* 
+*                                                                             * 
+* Copyright 2023 IHP PDK Authors                                              *
+*                                                                             *
+* Licensed under the Apache License, Version 2.0 (the "License");             *
+* you may not use this file except in compliance with the License.            *
+* You may obtain a copy of the License at                                     *
+*                                                                             *
+*     https://www.apache.org/licenses/LICENSE-2.0                             *
+*                                                                             *
+* Unless required by applicable law or agreed to in writing, software         *
+* distributed under the License is distributed on an "AS IS" BASIS,           *
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.    *
+* See the License for the specific language governing permissions and         *
+* limitations under the License.                                              *
+*                                                                             *
+*******************************************************************************
+******************************************************************************* 
+*                                                                             *
+*                                                                             *
+*                            M O S     C O R N E R S                          *
+*                                                                             *
+*                                                                             *
+******************************************************************************* 
+*
+* NOTE: use only typical mean file (this file) for Monte Carlo simulations of process tolerance!
+*
+* hint: using spectre, add this file as a model file in analog artist;
+*	using spectreS, add it under Environment/Include with syntax=spectre
+*
+* Corner naming scheme: typical mean=tt, worst case=ss, best case=ff, combinations sf, fs, ...
+* Digit	Devices
+ 
+
+* Monte-Carlo begin ---------------------------------------------
+*
+* NOTE: default of all  .param should be 1.0
+* NOTE: deviations from 1.0 are used to fit statistical results
+* 
+*
+*
+*
+*******************************************************************************
+*                                                                             
+* High Voltage (hv) MOS Transistors   
+*                                                 
+* Model:                                PSP 103.6
+* Date:                                 10.03.2020
+* Lot:                                  EDJ
+* WAFER:                                06
+* CHIP Nr:                              x=3, y=9
+* Device:                               SG13G2
+* Maximum drain-source voltage:         3.3
+* Measurement data:                     
+* Nom. Temperature  (TNOM):             27 grd C
+* Meas. Temperature (TEMP):             27 grd C
+* Valid range for model:                L = (0.45 - 10)um   nmos
+*                                       L = (0.40 - 10)um   pmos
+*                                       W = (0.30 - 10)um
+*                                                                             
+*******************************************************************************
+
+**************** CORNER_LIB OF sg13g2_hv TT MODEL ****************  
+* Typical without statistical     
+.LIB mos_tt
+.param sg13g2_hv_nmos_vfbo_mm= 1.0
+.param sg13g2_hv_nmos_rsgo   = 1.0000
+.param sg13g2_hv_nmos_rsw1   = 0.7886
+.param sg13g2_hv_nmos_mueo   = 1.0780
+.param sg13g2_hv_nmos_dphibo = 1.4388
+.param sg13g2_hv_nmos_dphibl = 1.5299
+.param sg13g2_hv_nmos_dphibw = 1.0000
+.param sg13g2_hv_nmos_dphiblw= 0.8712
+.param sg13g2_hv_nmos_ctl    = 1.0000
+.param sg13g2_hv_nmos_thesato= 1.0000
+.param sg13g2_hv_nmos_thesatl= 1.0350
+.param sg13g2_hv_nmos_thesatw= 1.0000
+.param sg13g2_hv_nmos_thesatlw= 1.6050
+.param sg13g2_hv_nmos_toxo   = 1.0000
+.param sg13g2_hv_nmos_toxovo = 1.0000
+.param sg13g2_hv_nmos_cjorbot= 1.0000
+.param sg13g2_hv_nmos_cjorsti= 1.0000
+.param sg13g2_hv_nmos_cjorgat= 1.0000
+
+.param sg13g2_hv_pmos_vfbo_mm= 1.0
+.param sg13g2_hv_pmos_rsgo   = 1.1110
+.param sg13g2_hv_pmos_rsw1   = 1.0000
+.param sg13g2_hv_pmos_mueo   = 0.9605
+.param sg13g2_hv_pmos_dphibo = 1.0010
+.param sg13g2_hv_pmos_dphibl = 0.9504
+.param sg13g2_hv_pmos_dphibw = 1.4080
+.param sg13g2_hv_pmos_dphiblw= -0.1693
+.param sg13g2_hv_pmos_bgidlo = 0.8409
+.param sg13g2_hv_pmos_thesato= 1.0000
+.param sg13g2_hv_pmos_thesatl= 0.4814
+.param sg13g2_hv_pmos_thesatw= 5.7745
+.param sg13g2_hv_pmos_thesatlw= 1.0000
+.param sg13g2_hv_pmos_csl    = 1.0000
+.param sg13g2_hv_pmos_toxo   = 1.0000
+.param sg13g2_hv_pmos_toxovo = 1.0000
+.param sg13g2_hv_pmos_cjorbot= 1.0000
+.param sg13g2_hv_pmos_cjorsti= 1.0000
+.param sg13g2_hv_pmos_cjorgat= 1.0000
+
+.param sg13g2_hv_svaricap_lap   = 0.8     
+.param sg13g2_hv_svaricap_toxo  = 1     
+  
+.include sg13g2_moshv_mod.lib
+.ENDL mos_tt  
+  
+* Typical with statistical     
+.LIB mos_tt_stat 
+.param sg13g2_hv_nmos_vfbo_mm_norm= 1.0
+.param sg13g2_hv_nmos_rsgo_norm   = 1.0000
+.param sg13g2_hv_nmos_rsw1_norm   = 0.7886
+.param sg13g2_hv_nmos_mueo_norm   = 1.0780
+.param sg13g2_hv_nmos_dphibo_norm = 1.4388
+.param sg13g2_hv_nmos_dphibl_norm = 1.5299
+.param sg13g2_hv_nmos_dphibw_norm = 1.0000
+.param sg13g2_hv_nmos_dphiblw_norm= 0.8712
+.param sg13g2_hv_nmos_ctl_norm    = 1.0000
+.param sg13g2_hv_nmos_thesato_norm= 1.0000
+.param sg13g2_hv_nmos_thesatl_norm= 1.0350
+.param sg13g2_hv_nmos_thesatw_norm= 1.0000
+.param sg13g2_hv_nmos_thesatlw_norm= 1.6050
+.param sg13g2_hv_nmos_toxo_norm   = 1.0000
+.param sg13g2_hv_nmos_toxovo_norm = 1.0000
+.param sg13g2_hv_nmos_cjorbot_norm= 1.0000
+.param sg13g2_hv_nmos_cjorsti_norm= 1.0000
+.param sg13g2_hv_nmos_cjorgat_norm= 1.0000
+
+.param sg13g2_hv_pmos_vfbo_mm_norm= 1.0
+.param sg13g2_hv_pmos_rsgo_norm   = 1.1110
+.param sg13g2_hv_pmos_rsw1_norm   = 1.0000
+.param sg13g2_hv_pmos_mueo_norm   = 0.9605
+.param sg13g2_hv_pmos_dphibo_norm = 1.0010
+.param sg13g2_hv_pmos_dphibl_norm = 0.9504
+.param sg13g2_hv_pmos_dphibw_norm = 1.4080
+.param sg13g2_hv_pmos_dphiblw_norm= -0.1693
+.param sg13g2_hv_pmos_bgidlo_norm = 0.8409
+.param sg13g2_hv_pmos_thesato_norm= 1.0000
+.param sg13g2_hv_pmos_thesatl_norm= 0.4814
+.param sg13g2_hv_pmos_thesatw_norm= 5.7745
+.param sg13g2_hv_pmos_thesatlw_norm= 1.0000
+.param sg13g2_hv_pmos_csl_norm    = 1.0000
+.param sg13g2_hv_pmos_toxo_norm   = 1.0000
+.param sg13g2_hv_pmos_toxovo_norm = 1.0000
+.param sg13g2_hv_pmos_cjorbot_norm= 1.0000
+.param sg13g2_hv_pmos_cjorsti_norm= 1.0000
+.param sg13g2_hv_pmos_cjorgat_norm= 1.0000
+
+.param sg13g2_hv_svaricap_lap   = 0.8     
+.param sg13g2_hv_svaricap_toxo  = 1     
+  
+.include sg13g2_moshv_stat.lib
+.include sg13g2_moshv_mod.lib
+.ENDL mos_tt_stat 
+
+**************** CORNER_LIB OF sg13g2_hv SS MODEL **************** 
+* Slow n, Slow p without statistical
+.LIB mos_ss
+.param sg13g2_hv_nmos_vfbo_mm= 1.0
+.param sg13g2_hv_nmos_rsgo   = 1.0000
+.param sg13g2_hv_nmos_rsw1   = 0.7880
+.param sg13g2_hv_nmos_mueo   = 1.1670
+.param sg13g2_hv_nmos_dphibo = 1.0117
+.param sg13g2_hv_nmos_dphibl = 0.9004
+.param sg13g2_hv_nmos_dphibw = 1.0000
+.param sg13g2_hv_nmos_dphiblw= 0.8247
+.param sg13g2_hv_nmos_ctl    = 1.0000
+.param sg13g2_hv_nmos_thesato= 1.0000
+.param sg13g2_hv_nmos_thesatl= 1.1610
+.param sg13g2_hv_nmos_thesatw= 1.0000
+.param sg13g2_hv_nmos_thesatlw= 1.4830
+.param sg13g2_hv_nmos_toxo   = 1.0400
+.param sg13g2_hv_nmos_toxovo = 1.0400
+.param sg13g2_hv_nmos_cjorbot= 1.0800
+.param sg13g2_hv_nmos_cjorsti= 1.0800
+.param sg13g2_hv_nmos_cjorgat= 1.0800
+  
+.param sg13g2_hv_pmos_vfbo_mm= 1.0
+.param sg13g2_hv_pmos_rsgo   = -0.0510
+.param sg13g2_hv_pmos_rsw1   = 1.0000
+.param sg13g2_hv_pmos_mueo   = 0.9619
+.param sg13g2_hv_pmos_dphibo = 0.8319
+.param sg13g2_hv_pmos_dphibl = 1.1490
+.param sg13g2_hv_pmos_dphibw = 1.4480
+.param sg13g2_hv_pmos_dphiblw= 2.7230
+.param sg13g2_hv_pmos_bgidlo = 1.4000
+.param sg13g2_hv_pmos_thesato= 1.0000
+.param sg13g2_hv_pmos_thesatl= 0.6000
+.param sg13g2_hv_pmos_thesatw= 3.7378
+.param sg13g2_hv_pmos_thesatlw= 1.0000
+.param sg13g2_hv_pmos_csl    = 1.0000
+.param sg13g2_hv_pmos_toxo   = 1.0400
+.param sg13g2_hv_pmos_toxovo = 1.0400
+.param sg13g2_hv_pmos_cjorbot= 1.0800
+.param sg13g2_hv_pmos_cjorsti= 1.0800
+.param sg13g2_hv_pmos_cjorgat= 1.0800
+  
+.param sg13g2_hv_svaricap_lap   = 0.6     
+.param sg13g2_hv_svaricap_toxo  = 1.04   
+  
+.include sg13g2_moshv_mod.lib
+.ENDL mos_ss  
+  
+* Slow n, Slow p with statistical
+.LIB mos_ss_stat
+.param sg13g2_hv_nmos_vfbo_mm_norm= 1.0
+.param sg13g2_hv_nmos_rsgo_norm   = 1.0000
+.param sg13g2_hv_nmos_rsw1_norm   = 0.7880
+.param sg13g2_hv_nmos_mueo_norm   = 1.1670
+.param sg13g2_hv_nmos_dphibo_norm = 1.0117
+.param sg13g2_hv_nmos_dphibl_norm = 0.9004
+.param sg13g2_hv_nmos_dphibw_norm = 1.0000
+.param sg13g2_hv_nmos_dphiblw_norm= 0.8247
+.param sg13g2_hv_nmos_ctl_norm    = 1.0000
+.param sg13g2_hv_nmos_thesato_norm= 1.0000
+.param sg13g2_hv_nmos_thesatl_norm= 1.1610
+.param sg13g2_hv_nmos_thesatw_norm= 1.0000
+.param sg13g2_hv_nmos_thesatlw_norm= 1.4830
+.param sg13g2_hv_nmos_toxo_norm   = 1.0400
+.param sg13g2_hv_nmos_toxovo_norm = 1.0400
+.param sg13g2_hv_nmos_cjorbot_norm= 1.0800
+.param sg13g2_hv_nmos_cjorsti_norm= 1.0800
+.param sg13g2_hv_nmos_cjorgat_norm= 1.0800
+  
+.param sg13g2_hv_pmos_vfbo_mm_norm= 1.0
+.param sg13g2_hv_pmos_rsgo_norm   = -0.0510
+.param sg13g2_hv_pmos_rsw1_norm   = 1.0000
+.param sg13g2_hv_pmos_mueo_norm   = 0.9619
+.param sg13g2_hv_pmos_dphibo_norm = 0.8319
+.param sg13g2_hv_pmos_dphibl_norm = 1.1490
+.param sg13g2_hv_pmos_dphibw_norm = 1.4480
+.param sg13g2_hv_pmos_dphiblw_norm= 2.7230
+.param sg13g2_hv_pmos_bgidlo_norm = 1.4000
+.param sg13g2_hv_pmos_thesato_norm= 1.0000
+.param sg13g2_hv_pmos_thesatl_norm= 0.6000
+.param sg13g2_hv_pmos_thesatw_norm= 3.7378
+.param sg13g2_hv_pmos_thesatlw_norm= 1.0000
+.param sg13g2_hv_pmos_csl_norm    = 1.0000
+.param sg13g2_hv_pmos_toxo_norm   = 1.0400
+.param sg13g2_hv_pmos_toxovo_norm = 1.0400
+.param sg13g2_hv_pmos_cjorbot_norm= 1.0800
+.param sg13g2_hv_pmos_cjorsti_norm= 1.0800
+.param sg13g2_hv_pmos_cjorgat_norm= 1.0800
+  
+.param sg13g2_hv_svaricap_lap   = 0.6     
+.param sg13g2_hv_svaricap_toxo  = 1.04   
+  
+.include sg13g2_moshv_stat.lib
+.include sg13g2_moshv_mod.lib
+.ENDL mos_ss_stat
+**************** CORNER_LIB OF sg13g2_hv FF MODEL **************** 
+* Fast n, Fast p without statistical
+.LIB mos_ff  
+  
+.param sg13g2_hv_nmos_vfbo_mm= 1.0
+.param sg13g2_hv_nmos_rsgo   = 1.0000
+.param sg13g2_hv_nmos_rsw1   = 0.7880
+.param sg13g2_hv_nmos_mueo   = 0.9662
+.param sg13g2_hv_nmos_dphibo = 1.9136
+.param sg13g2_hv_nmos_dphibl = 2.1315
+.param sg13g2_hv_nmos_dphibw = 1.0000
+.param sg13g2_hv_nmos_dphiblw= 0.9151
+.param sg13g2_hv_nmos_ctl    = 1.0000
+.param sg13g2_hv_nmos_thesato= 1.0000
+.param sg13g2_hv_nmos_thesatl= 0.9463
+.param sg13g2_hv_nmos_thesatw= 1.0000
+.param sg13g2_hv_nmos_thesatlw= 1.6950
+.param sg13g2_hv_nmos_toxo   = 0.9600
+.param sg13g2_hv_nmos_toxovo = 0.9600
+.param sg13g2_hv_nmos_cjorbot= 0.9200
+.param sg13g2_hv_nmos_cjorsti= 0.9200
+.param sg13g2_hv_nmos_cjorgat= 0.9200
+  
+.param sg13g2_hv_pmos_vfbo_mm= 1.0
+.param sg13g2_hv_pmos_rsgo   = 2.5010
+.param sg13g2_hv_pmos_rsw1   = 1.0000
+.param sg13g2_hv_pmos_mueo   = 0.9687
+.param sg13g2_hv_pmos_dphibo = 1.1750
+.param sg13g2_hv_pmos_dphibl = 0.7456
+.param sg13g2_hv_pmos_dphibw = 1.3380
+.param sg13g2_hv_pmos_dphiblw= -3.3600
+.param sg13g2_hv_pmos_bgidlo = 0.4770
+.param sg13g2_hv_pmos_thesato= 1.0000
+.param sg13g2_hv_pmos_thesatl= 0.5000
+.param sg13g2_hv_pmos_thesatw= 6.3581
+.param sg13g2_hv_pmos_thesatlw= 1.0000
+.param sg13g2_hv_pmos_csl    = 1.0000
+.param sg13g2_hv_pmos_toxo   = 0.9600
+.param sg13g2_hv_pmos_toxovo = 0.9600
+.param sg13g2_hv_pmos_cjorbot= 0.9200
+.param sg13g2_hv_pmos_cjorsti= 0.9200
+.param sg13g2_hv_pmos_cjorgat= 0.9200
+  
+.param sg13g2_hv_svaricap_lap   = 1     
+.param sg13g2_hv_svaricap_toxo  = 0.96  
+  
+.include sg13g2_moshv_mod.lib
+.ENDL mos_ff  
+  
+* Fast n, Fast p with statistical
+.LIB mos_ff_stat  
+  
+.param sg13g2_hv_nmos_vfbo_mm_norm= 1.0
+.param sg13g2_hv_nmos_rsgo_norm   = 1.0000
+.param sg13g2_hv_nmos_rsw1_norm   = 0.7880
+.param sg13g2_hv_nmos_mueo_norm   = 0.9662
+.param sg13g2_hv_nmos_dphibo_norm = 1.9136
+.param sg13g2_hv_nmos_dphibl_norm = 2.1315
+.param sg13g2_hv_nmos_dphibw_norm = 1.0000
+.param sg13g2_hv_nmos_dphiblw_norm= 0.9151
+.param sg13g2_hv_nmos_ctl_norm    = 1.0000
+.param sg13g2_hv_nmos_thesato_norm= 1.0000
+.param sg13g2_hv_nmos_thesatl_norm= 0.9463
+.param sg13g2_hv_nmos_thesatw_norm= 1.0000
+.param sg13g2_hv_nmos_thesatlw_norm= 1.6950
+.param sg13g2_hv_nmos_toxo_norm   = 0.9600
+.param sg13g2_hv_nmos_toxovo_norm = 0.9600
+.param sg13g2_hv_nmos_cjorbot_norm= 0.9200
+.param sg13g2_hv_nmos_cjorsti_norm= 0.9200
+.param sg13g2_hv_nmos_cjorgat_norm= 0.9200
+  
+.param sg13g2_hv_pmos_vfbo_mm_norm= 1.0
+.param sg13g2_hv_pmos_rsgo_norm   = 2.5010
+.param sg13g2_hv_pmos_rsw1_norm   = 1.0000
+.param sg13g2_hv_pmos_mueo_norm   = 0.9687
+.param sg13g2_hv_pmos_dphibo_norm = 1.1750
+.param sg13g2_hv_pmos_dphibl_norm = 0.7456
+.param sg13g2_hv_pmos_dphibw_norm = 1.3380
+.param sg13g2_hv_pmos_dphiblw_norm= -3.3600
+.param sg13g2_hv_pmos_bgidlo_norm = 0.4770
+.param sg13g2_hv_pmos_thesato_norm= 1.0000
+.param sg13g2_hv_pmos_thesatl_norm= 0.5000
+.param sg13g2_hv_pmos_thesatw_norm= 6.3581
+.param sg13g2_hv_pmos_thesatlw_norm= 1.0000
+.param sg13g2_hv_pmos_csl_norm    = 1.0000
+.param sg13g2_hv_pmos_toxo_norm   = 0.9600
+.param sg13g2_hv_pmos_toxovo_norm = 0.9600
+.param sg13g2_hv_pmos_cjorbot_norm= 0.9200
+.param sg13g2_hv_pmos_cjorsti_norm= 0.9200
+.param sg13g2_hv_pmos_cjorgat_norm= 0.9200
+  
+.param sg13g2_hv_svaricap_lap   = 1     
+.param sg13g2_hv_svaricap_toxo  = 0.96  
+  
+.include sg13g2_moshv_stat.lib
+.include sg13g2_moshv_mod.lib
+.ENDL mos_ff_stat
+**************** CORNER_LIB OF sg13g2_hv SF MODEL **************** 
+* Slow n, Fast p without statistical
+.LIB mos_sf  
+  
+.param sg13g2_hv_nmos_vfbo_mm= 1.0
+.param sg13g2_hv_nmos_rsgo   = 1.0000
+.param sg13g2_hv_nmos_rsw1   = 0.7883
+.param sg13g2_hv_nmos_mueo   = 1.1225
+.param sg13g2_hv_nmos_dphibo = 1.2252
+.param sg13g2_hv_nmos_dphibl = 1.2151
+.param sg13g2_hv_nmos_dphibw = 1.0000
+.param sg13g2_hv_nmos_dphiblw= 0.8479
+.param sg13g2_hv_nmos_ctl    = 1.0000
+.param sg13g2_hv_nmos_thesato= 1.0000
+.param sg13g2_hv_nmos_thesatl= 1.0980
+.param sg13g2_hv_nmos_thesatw= 1.0000
+.param sg13g2_hv_nmos_thesatlw= 1.5440
+.param sg13g2_hv_nmos_toxo   = 1.0200
+.param sg13g2_hv_nmos_toxovo = 1.0200
+.param sg13g2_hv_nmos_cjorbot= 1.0400
+.param sg13g2_hv_nmos_cjorsti= 1.0400
+.param sg13g2_hv_nmos_cjorgat= 1.0400
+  
+.param sg13g2_hv_pmos_vfbo_mm= 1.0
+.param sg13g2_hv_pmos_rsgo   = 1.8060
+.param sg13g2_hv_pmos_rsw1   = 1.0000
+.param sg13g2_hv_pmos_mueo   = 0.9646
+.param sg13g2_hv_pmos_dphibo = 1.0880
+.param sg13g2_hv_pmos_dphibl = 0.8480
+.param sg13g2_hv_pmos_dphibw = 1.3730
+.param sg13g2_hv_pmos_dphiblw= -1.7647
+.param sg13g2_hv_pmos_bgidlo = 0.6589
+.param sg13g2_hv_pmos_thesato= 1.0000
+.param sg13g2_hv_pmos_thesatl= 0.4907
+.param sg13g2_hv_pmos_thesatw= 6.0663
+.param sg13g2_hv_pmos_thesatlw= 1.0000
+.param sg13g2_hv_pmos_csl    = 1.0000
+.param sg13g2_hv_pmos_toxo   = 0.9800
+.param sg13g2_hv_pmos_toxovo = 0.9800
+.param sg13g2_hv_pmos_cjorbot= 0.9600
+.param sg13g2_hv_pmos_cjorsti= 0.9600
+.param sg13g2_hv_pmos_cjorgat= 0.9600
+  
+.param sg13g2_hv_svaricap_lap   = 0.9     
+.param sg13g2_hv_svaricap_toxo  = 0.98   
+  
+  * .include sg13g2_moshv_stat.lib
+.include sg13g2_moshv_mod.lib
+.ENDL mos_sf  
+  
+* Slow n, Fast p with statistical
+.LIB mos_sf_stat  
+  
+.param sg13g2_hv_nmos_vfbo_mm_norm= 1.0
+.param sg13g2_hv_nmos_rsgo_norm   = 1.0000
+.param sg13g2_hv_nmos_rsw1_norm   = 0.7883
+.param sg13g2_hv_nmos_mueo_norm   = 1.1225
+.param sg13g2_hv_nmos_dphibo_norm = 1.2252
+.param sg13g2_hv_nmos_dphibl_norm = 1.2151
+.param sg13g2_hv_nmos_dphibw_norm = 1.0000
+.param sg13g2_hv_nmos_dphiblw_norm= 0.8479
+.param sg13g2_hv_nmos_ctl_norm    = 1.0000
+.param sg13g2_hv_nmos_thesato_norm= 1.0000
+.param sg13g2_hv_nmos_thesatl_norm= 1.0980
+.param sg13g2_hv_nmos_thesatw_norm= 1.0000
+.param sg13g2_hv_nmos_thesatlw_norm= 1.5440
+.param sg13g2_hv_nmos_toxo_norm   = 1.0200
+.param sg13g2_hv_nmos_toxovo_norm = 1.0200
+.param sg13g2_hv_nmos_cjorbot_norm= 1.0400
+.param sg13g2_hv_nmos_cjorsti_norm= 1.0400
+.param sg13g2_hv_nmos_cjorgat_norm= 1.0400
+  
+.param sg13g2_hv_pmos_vfbo_mm_norm= 1.0
+.param sg13g2_hv_pmos_rsgo_norm   = 1.8060
+.param sg13g2_hv_pmos_rsw1_norm   = 1.0000
+.param sg13g2_hv_pmos_mueo_norm   = 0.9646
+.param sg13g2_hv_pmos_dphibo_norm = 1.0880
+.param sg13g2_hv_pmos_dphibl_norm = 0.8480
+.param sg13g2_hv_pmos_dphibw_norm = 1.3730
+.param sg13g2_hv_pmos_dphiblw_norm= -1.7647
+.param sg13g2_hv_pmos_bgidlo_norm = 0.6589
+.param sg13g2_hv_pmos_thesato_norm= 1.0000
+.param sg13g2_hv_pmos_thesatl_norm= 0.4907
+.param sg13g2_hv_pmos_thesatw_norm= 6.0663
+.param sg13g2_hv_pmos_thesatlw_norm= 1.0000
+.param sg13g2_hv_pmos_csl_norm    = 1.0000
+.param sg13g2_hv_pmos_toxo_norm   = 0.9800
+.param sg13g2_hv_pmos_toxovo_norm = 0.9800
+.param sg13g2_hv_pmos_cjorbot_norm= 0.9600
+.param sg13g2_hv_pmos_cjorsti_norm= 0.9600
+.param sg13g2_hv_pmos_cjorgat_norm= 0.9600
+  
+.param sg13g2_hv_svaricap_lap   = 0.9     
+.param sg13g2_hv_svaricap_toxo  = 0.98   
+  
+.include sg13g2_moshv_stat.lib
+.include sg13g2_moshv_mod.lib
+.ENDL mos_sf_stat
+
+**************** CORNER_LIB OF sg13g2_hv FS MODEL **************** 
+* Fast n, Slow p without statistical
+.LIB mos_fs  
+  
+.param sg13g2_hv_nmos_vfbo_mm= 1.0
+.param sg13g2_hv_nmos_rsgo   = 1.0000
+.param sg13g2_hv_nmos_rsw1   = 0.7883
+.param sg13g2_hv_nmos_mueo   = 1.0221
+.param sg13g2_hv_nmos_dphibo = 1.6762
+.param sg13g2_hv_nmos_dphibl = 1.8307
+.param sg13g2_hv_nmos_dphibw = 1.0000
+.param sg13g2_hv_nmos_dphiblw= 0.8932
+.param sg13g2_hv_nmos_ctl    = 1.0000
+.param sg13g2_hv_nmos_thesato= 1.0000
+.param sg13g2_hv_nmos_thesatl= 0.9907
+.param sg13g2_hv_nmos_thesatw= 1.0000
+.param sg13g2_hv_nmos_thesatlw= 1.6500
+.param sg13g2_hv_nmos_toxo   = 0.9800
+.param sg13g2_hv_nmos_toxovo = 0.9800
+.param sg13g2_hv_nmos_cjorbot= 0.9600
+.param sg13g2_hv_nmos_cjorsti= 0.9600
+.param sg13g2_hv_nmos_cjorgat= 0.9600
+  
+.param sg13g2_hv_pmos_vfbo_mm= 1.0
+.param sg13g2_hv_pmos_rsgo   = 0.5300
+.param sg13g2_hv_pmos_rsw1   = 1.0000
+.param sg13g2_hv_pmos_mueo   = 0.9612
+.param sg13g2_hv_pmos_dphibo = 0.9164
+.param sg13g2_hv_pmos_dphibl = 1.0497
+.param sg13g2_hv_pmos_dphibw = 1.4280
+.param sg13g2_hv_pmos_dphiblw= 1.2769
+.param sg13g2_hv_pmos_bgidlo = 1.1204
+.param sg13g2_hv_pmos_thesato= 1.0000
+.param sg13g2_hv_pmos_thesatl= 0.5407
+.param sg13g2_hv_pmos_thesatw= 4.7562
+.param sg13g2_hv_pmos_thesatlw= 1.0000
+.param sg13g2_hv_pmos_csl    = 1.0000
+.param sg13g2_hv_pmos_toxo   = 1.0200
+.param sg13g2_hv_pmos_toxovo = 1.0200
+.param sg13g2_hv_pmos_cjorbot= 1.0400
+.param sg13g2_hv_pmos_cjorsti= 1.0400
+.param sg13g2_hv_pmos_cjorgat= 1.0400
+  
+.param sg13g2_hv_svaricap_lap   = 0.7     
+.param sg13g2_hv_svaricap_toxo  = 1.02   
+  
+  * .include sg13g2_moshv_stat.lib
+.include sg13g2_moshv_mod.lib
+.ENDL mos_fs  
+  
+* Fast n, Slow p with statistical
+.LIB mos_fs_stat
+  
+.param sg13g2_hv_nmos_vfbo_mm_norm= 1.0
+.param sg13g2_hv_nmos_rsgo_norm   = 1.0000
+.param sg13g2_hv_nmos_rsw1_norm   = 0.7883
+.param sg13g2_hv_nmos_mueo_norm   = 1.0221
+.param sg13g2_hv_nmos_dphibo_norm = 1.6762
+.param sg13g2_hv_nmos_dphibl_norm = 1.8307
+.param sg13g2_hv_nmos_dphibw_norm = 1.0000
+.param sg13g2_hv_nmos_dphiblw_norm= 0.8932
+.param sg13g2_hv_nmos_ctl_norm    = 1.0000
+.param sg13g2_hv_nmos_thesato_norm= 1.0000
+.param sg13g2_hv_nmos_thesatl_norm= 0.9907
+.param sg13g2_hv_nmos_thesatw_norm= 1.0000
+.param sg13g2_hv_nmos_thesatlw_norm= 1.6500
+.param sg13g2_hv_nmos_toxo_norm   = 0.9800
+.param sg13g2_hv_nmos_toxovo_norm = 0.9800
+.param sg13g2_hv_nmos_cjorbot_norm= 0.9600
+.param sg13g2_hv_nmos_cjorsti_norm= 0.9600
+.param sg13g2_hv_nmos_cjorgat_norm= 0.9600
+  
+.param sg13g2_hv_pmos_vfbo_mm_norm= 1.0
+.param sg13g2_hv_pmos_rsgo_norm   = 0.5300
+.param sg13g2_hv_pmos_rsw1_norm   = 1.0000
+.param sg13g2_hv_pmos_mueo_norm   = 0.9612
+.param sg13g2_hv_pmos_dphibo_norm = 0.9164
+.param sg13g2_hv_pmos_dphibl_norm = 1.0497
+.param sg13g2_hv_pmos_dphibw_norm = 1.4280
+.param sg13g2_hv_pmos_dphiblw_norm= 1.2769
+.param sg13g2_hv_pmos_bgidlo_norm = 1.1204
+.param sg13g2_hv_pmos_thesato_norm= 1.0000
+.param sg13g2_hv_pmos_thesatl_norm= 0.5407
+.param sg13g2_hv_pmos_thesatw_norm= 4.7562
+.param sg13g2_hv_pmos_thesatlw_norm= 1.0000
+.param sg13g2_hv_pmos_csl_norm    = 1.0000
+.param sg13g2_hv_pmos_toxo_norm   = 1.0200
+.param sg13g2_hv_pmos_toxovo_norm = 1.0200
+.param sg13g2_hv_pmos_cjorbot_norm= 1.0400
+.param sg13g2_hv_pmos_cjorsti_norm= 1.0400
+.param sg13g2_hv_pmos_cjorgat_norm= 1.0400
+  
+.param sg13g2_hv_svaricap_lap   = 0.7     
+.param sg13g2_hv_svaricap_toxo  = 1.02   
+  
+.include sg13g2_moshv_stat.lib
+.include sg13g2_moshv_mod.lib
+.ENDL mos_fs_stat 
diff --git a/ihp-sg13g2/libs.tech/xyce/models/cornerMOSlv.lib b/ihp-sg13g2/libs.tech/xyce/models/cornerMOSlv.lib
new file mode 100644
index 00000000..9be3184c
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/models/cornerMOSlv.lib
@@ -0,0 +1,519 @@
+*******************************************************************************
+*                                                                             *
+* Library:      SG13G2_dev                                                    *
+* Technologies: SG13G2                                                        *
+* Component:    Spectre model file for Spectre 18                             *
+*                                                                             *
+* Simulator:    Spectre 20.1                                                  *
+* Model:        PSP 103.6                                                     *
+* Revision:     200310                                                        *
+*                                                                             *
+*******************************************************************************
+*                                                                             *
+* Copyright 2023 IHP PDK Authors                                              *
+*                                                                             *
+* Licensed under the Apache License, Version 2.0 (the "License");             *
+* you may not use this file except in compliance with the License.            *
+* You may obtain a copy of the License at                                     *
+*                                                                             *
+*     https://www.apache.org/licenses/LICENSE-2.0                             *
+*                                                                             *
+* Unless required by applicable law or agreed to in writing, software         *
+* distributed under the License is distributed on an "AS IS" BASIS,           *
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.    *
+* See the License for the specific language governing permissions and         *
+* limitations under the License.                                              *
+*                                                                             *
+*******************************************************************************
+*******************************************************************************
+*                                                                             *
+*                                                                             *
+*                            M O S     C O R N E R S                          *
+*                                                                             *
+*                                                                             *
+*******************************************************************************
+*
+* NOTE: use only typical mean file (this file) for Monte Carlo simulations of process tolerance!
+*
+* hint: using spectre, add this file as a model file in analog artist;
+*	using spectreS, add it under Environment/Include with syntax=spectre
+*
+* Corner naming scheme: typical mean=tt, worst case=ss, best case=ff, combinations sf, fs, ...
+* Digit	Devices
+
+
+* Monte-Carlo begin ---------------------------------------------
+*
+* NOTE: default of all   parameters should be 1.0
+* NOTE: deviations from 1.0 are used to fit statistical results
+*
+*
+*
+*
+*******************************************************************************
+*
+* Low Voltage (lv) MOS Transistors
+*
+* Model:                                PSP 103.6
+* Date:                                 10.03.2020
+* Lot:                                  EDJ809
+* WAFER:                                06
+* CHIP Nr:                              x=3, y=9
+* Device:                               SG13G2
+* Maximum drain-source voltage:         1.5
+* Measurement data:
+* Nom. Temperature  (TNOM):             27 grd C
+* Meas. Temperature (TEMP):             27 grd C
+* Valid range for model:                L = (0.13 - 10)um
+*                                       W = (0.15 - 10)um
+*
+*******************************************************************************
+
+**************** CORNER_LIB OF sg13g2_lv TT MODEL ****************
+* Typical
+.LIB mos_tt
+.param sg13g2_lv_nmos_vfbo_mm= 1.0
+.param sg13g2_lv_nmos_ctl    = 1.2080
+.param sg13g2_lv_nmos_rsw1   = 0.7200
+.param sg13g2_lv_nmos_muew   = 0.8500
+.param sg13g2_lv_nmos_dphibo = 0.9915
+.param sg13g2_lv_nmos_dphibl = 0.9693
+.param sg13g2_lv_nmos_dphibw = 0.9749
+.param sg13g2_lv_nmos_dphiblw= 0.9754
+.param sg13g2_lv_nmos_themuo = 0.8757
+.param sg13g2_lv_nmos_thesatl= 0.7850
+.param sg13g2_lv_nmos_thesatw= 1.5000
+.param sg13g2_lv_nmos_thesatlw= 0.6127
+.param sg13g2_lv_nmos_toxo   = 1.0000
+.param sg13g2_lv_nmos_toxovo = 1.0000
+.param sg13g2_lv_nmos_cjorbot= 1.0000
+.param sg13g2_lv_nmos_cjorsti= 1.0000
+.param sg13g2_lv_nmos_cjorgat= 1.0000
+
+.param sg13g2_lv_pmos_vfbo_mm   = 1.0
+.param sg13g2_lv_pmos_ctl    = 1.9570
+.param sg13g2_lv_pmos_rsw1   = 0.7720
+.param sg13g2_lv_pmos_muew   = 1.0520
+.param sg13g2_lv_pmos_dphibo = 0.9050
+.param sg13g2_lv_pmos_dphibl = 0.8550
+.param sg13g2_lv_pmos_dphibw = -1.5800
+.param sg13g2_lv_pmos_dphiblw= 1.0000
+.param sg13g2_lv_pmos_themuo = 0.9580
+.param sg13g2_lv_pmos_thesatl= 0.5510
+.param sg13g2_lv_pmos_thesatw= 1.0800
+.param sg13g2_lv_pmos_thesatlw= 1.0000
+.param sg13g2_lv_pmos_toxo   = 1.0000
+.param sg13g2_lv_pmos_toxovo = 1.0000
+.param sg13g2_lv_pmos_cjorbot= 1.0000
+.param sg13g2_lv_pmos_cjorsti= 1.0000
+.param sg13g2_lv_pmos_cjorgat= 1.0000
+
+.param sg13g2_lv_svaricap_lap   = 1.082
+.param sg13g2_lv_svaricap_toxo  = 1
+
+.include sg13g2_moslv_mod.lib
+.ENDL mos_tt
+
+* Typical with statistical modeling
+.LIB mos_tt_stat
+.param sg13g2_lv_nmos_vfbo_norm   = 1.0
+.param sg13g2_lv_nmos_ctl_norm    = 1.2080
+.param sg13g2_lv_nmos_rsw1_norm   = 0.7200
+.param sg13g2_lv_nmos_muew_norm   = 0.8500
+.param sg13g2_lv_nmos_dphibo_norm = 0.9915
+.param sg13g2_lv_nmos_dphibl_norm = 0.9693
+.param sg13g2_lv_nmos_dphibw_norm = 0.9749
+.param sg13g2_lv_nmos_dphiblw_norm= 0.9754
+.param sg13g2_lv_nmos_themuo_norm = 0.8757
+.param sg13g2_lv_nmos_thesatl_norm= 0.7850
+.param sg13g2_lv_nmos_thesatw_norm= 1.5000
+.param sg13g2_lv_nmos_thesatlw_norm= 0.6127
+.param sg13g2_lv_nmos_toxo_norm   = 1.0000
+.param sg13g2_lv_nmos_toxovo_norm = 1.0000
+.param sg13g2_lv_nmos_cjorbot_norm= 1.0000
+.param sg13g2_lv_nmos_cjorsti_norm= 1.0000
+.param sg13g2_lv_nmos_cjorgat_norm= 1.0000
+
+.param sg13g2_lv_pmos_vfbo_norm   = 1.0
+.param sg13g2_lv_pmos_ctl_norm    = 1.2080
+.param sg13g2_lv_pmos_rsw1_norm   = 0.7200
+.param sg13g2_lv_pmos_muew_norm   = 0.8500
+.param sg13g2_lv_pmos_dphibo_norm = 0.9915
+.param sg13g2_lv_pmos_dphibl_norm = 0.9693
+.param sg13g2_lv_pmos_dphibw_norm = 0.9749
+.param sg13g2_lv_pmos_dphiblw_norm= 0.9754
+.param sg13g2_lv_pmos_themuo_norm = 0.8757
+.param sg13g2_lv_pmos_thesatl_norm= 0.7850
+.param sg13g2_lv_pmos_thesatw_norm= 1.5000
+.param sg13g2_lv_pmos_thesatlw_norm= 0.6127
+.param sg13g2_lv_pmos_toxo_norm   = 1.0000
+.param sg13g2_lv_pmos_toxovo_norm = 1.0000
+.param sg13g2_lv_pmos_cjorbot_norm= 1.0000
+.param sg13g2_lv_pmos_cjorsti_norm= 1.0000
+.param sg13g2_lv_pmos_cjorgat_norm= 1.0000
+
+.param sg13g2_lv_svaricap_lap   = 1.082
+.param sg13g2_lv_svaricap_toxo  = 1
+
+.include sg13g2_moslv_stat.lib
+.include sg13g2_moslv_mod.lib
+.ENDL mos_tt_stat
+
+**************** CORNER_LIB OF sg13g2_lv SS MODEL ****************
+* Slow n, Slow p without statistical
+.LIB mos_ss
+.param sg13g2_lv_nmos_vfbo_mm   = 1.0
+.param sg13g2_lv_nmos_ctl    = 0.4939
+.param sg13g2_lv_nmos_rsw1   = 0.6560
+.param sg13g2_lv_nmos_muew   = 0.9700
+.param sg13g2_lv_nmos_dphibo = 1.2070
+.param sg13g2_lv_nmos_dphibl = 1.3360
+.param sg13g2_lv_nmos_dphibw = 1.3290
+.param sg13g2_lv_nmos_dphiblw= 1.0110
+.param sg13g2_lv_nmos_themuo = 0.8866
+.param sg13g2_lv_nmos_thesatl= 1.0960
+.param sg13g2_lv_nmos_thesatw= 1.5930
+.param sg13g2_lv_nmos_thesatlw= 0.9875
+.param sg13g2_lv_nmos_toxo   = 1.0400
+.param sg13g2_lv_nmos_toxovo = 1.0400
+.param sg13g2_lv_nmos_cjorbot= 1.0800
+.param sg13g2_lv_nmos_cjorsti= 1.0800
+.param sg13g2_lv_nmos_cjorgat= 1.0800
+
+.param sg13g2_lv_pmos_vfbo_mm= 1.0
+.param sg13g2_lv_pmos_ctl    = 1.3520
+.param sg13g2_lv_pmos_rsw1   = 0.9365
+.param sg13g2_lv_pmos_muew   = 1.1030
+.param sg13g2_lv_pmos_dphibo = 0.5883
+.param sg13g2_lv_pmos_dphibl = 1.3540
+.param sg13g2_lv_pmos_dphibw = -4.9920
+.param sg13g2_lv_pmos_dphiblw= 1.0000
+.param sg13g2_lv_pmos_themuo = 0.8720
+.param sg13g2_lv_pmos_thesatl= 1.2190
+.param sg13g2_lv_pmos_thesatw= 0.9875
+.param sg13g2_lv_pmos_thesatlw= 1.0000
+.param sg13g2_lv_pmos_toxo   = 1.0400
+.param sg13g2_lv_pmos_toxovo = 1.0400
+.param sg13g2_lv_pmos_cjorbot= 1.0800
+.param sg13g2_lv_pmos_cjorsti= 1.0800
+.param sg13g2_lv_pmos_cjorgat= 1.0800
+
+.param sg13g2_lv_svaricap_lap   = 1
+.param sg13g2_lv_svaricap_toxo  = 1.04
+
+.include sg13g2_moslv_mod.lib
+.ENDL mos_ss
+
+* Slow n, Slow p with statistical
+.LIB mos_ss_stat
+.param sg13g2_lv_nmos_vfbo_norm   = 1.0
+.param sg13g2_lv_nmos_ctl_norm    = 0.4939
+.param sg13g2_lv_nmos_rsw1_norm   = 0.6560
+.param sg13g2_lv_nmos_muew_norm   = 0.9700
+.param sg13g2_lv_nmos_dphibo_norm = 1.2070
+.param sg13g2_lv_nmos_dphibl_norm = 1.3360
+.param sg13g2_lv_nmos_dphibw_norm = 1.3290
+.param sg13g2_lv_nmos_dphiblw_norm= 1.0110
+.param sg13g2_lv_nmos_themuo_norm = 0.8866
+.param sg13g2_lv_nmos_thesatl_norm= 1.0960
+.param sg13g2_lv_nmos_thesatw_norm= 1.5930
+.param sg13g2_lv_nmos_thesatlw_norm= 0.9875
+.param sg13g2_lv_nmos_toxo_norm   = 1.0400
+.param sg13g2_lv_nmos_toxovo_norm = 1.0400
+.param sg13g2_lv_nmos_cjorbot_norm= 1.0800
+.param sg13g2_lv_nmos_cjorsti_norm= 1.0800
+.param sg13g2_lv_nmos_cjorgat_norm= 1.0800
+
+.param sg13g2_lv_pmos_vfbo_norm= 1.0
+.param sg13g2_lv_pmos_ctl_norm    = 1.3520
+.param sg13g2_lv_pmos_rsw1_norm   = 0.9365
+.param sg13g2_lv_pmos_muew_norm   = 1.1030
+.param sg13g2_lv_pmos_dphibo_norm = 0.5883
+.param sg13g2_lv_pmos_dphibl_norm = 1.3540
+.param sg13g2_lv_pmos_dphibw_norm = -4.9920
+.param sg13g2_lv_pmos_dphiblw_norm= 1.0000
+.param sg13g2_lv_pmos_themuo_norm = 0.8720
+.param sg13g2_lv_pmos_thesatl_norm= 1.2190
+.param sg13g2_lv_pmos_thesatw_norm= 0.9875
+.param sg13g2_lv_pmos_thesatlw_norm= 1.0000
+.param sg13g2_lv_pmos_toxo_norm   = 1.0400
+.param sg13g2_lv_pmos_toxovo_norm = 1.0400
+.param sg13g2_lv_pmos_cjorbot_norm= 1.0800
+.param sg13g2_lv_pmos_cjorsti_norm= 1.0800
+.param sg13g2_lv_pmos_cjorgat_norm= 1.0800
+
+.param sg13g2_lv_svaricap_lap   = 1
+.param sg13g2_lv_svaricap_toxo  = 1.04
+
+.include sg13g2_moslv_stat.lib
+.include sg13g2_moslv_mod.lib
+.ENDL mos_ss_stat
+
+**************** CORNER_LIB OF sg13g2_lv FF MODEL ****************
+* Fast n, Fast p
+.LIB mos_ff
+.param sg13g2_lv_nmos_vfbo_mm= 1.0
+.param sg13g2_lv_nmos_ctl    = 1.4310
+.param sg13g2_lv_nmos_rsw1   = 0.9000
+.param sg13g2_lv_nmos_muew   = 0.7780
+.param sg13g2_lv_nmos_dphibo = 0.8137
+.param sg13g2_lv_nmos_dphibl = 0.6550
+.param sg13g2_lv_nmos_dphibw = 0.6105
+.param sg13g2_lv_nmos_dphiblw= 0.9300
+.param sg13g2_lv_nmos_themuo = 0.8708
+.param sg13g2_lv_nmos_thesatl= 0.5510
+.param sg13g2_lv_nmos_thesatw= 1.4300
+.param sg13g2_lv_nmos_thesatlw= 0.0860
+.param sg13g2_lv_nmos_toxo   = 0.9600
+.param sg13g2_lv_nmos_toxovo = 0.9600
+.param sg13g2_lv_nmos_cjorbot= 0.9200
+.param sg13g2_lv_nmos_cjorsti= 0.9200
+.param sg13g2_lv_nmos_cjorgat= 0.9200
+
+.param sg13g2_lv_pmos_vfbo_mm= 1.0
+.param sg13g2_lv_pmos_ctl    = 2.4800
+.param sg13g2_lv_pmos_rsw1   = 0.5000
+.param sg13g2_lv_pmos_muew   = 0.9620
+.param sg13g2_lv_pmos_dphibo = 1.2350
+.param sg13g2_lv_pmos_dphibl = 0.5066
+.param sg13g2_lv_pmos_dphibw = 3.9230
+.param sg13g2_lv_pmos_dphiblw= 1.0000
+.param sg13g2_lv_pmos_themuo = 1.0200
+.param sg13g2_lv_pmos_thesatl= 0.1880
+.param sg13g2_lv_pmos_thesatw= 1.2440
+.param sg13g2_lv_pmos_thesatlw= 2.0000
+.param sg13g2_lv_pmos_toxo   = 0.9600
+.param sg13g2_lv_pmos_toxovo = 0.9600
+.param sg13g2_lv_pmos_cjorbot= 0.9200
+.param sg13g2_lv_pmos_cjorsti= 0.9200
+.param sg13g2_lv_pmos_cjorgat= 0.9200
+
+.param sg13g2_lv_svaricap_lap   = 1.24
+.param sg13g2_lv_svaricap_toxo  = 0.96
+
+.include sg13g2_moslv_mod.lib
+.ENDL mos_ff
+
+* Fast n, Fast p
+.LIB mos_ff_stat
+.param sg13g2_lv_nmos_vfbo_norm= 1.0
+.param sg13g2_lv_nmos_ctl_norm    = 1.4310
+.param sg13g2_lv_nmos_rsw1_norm   = 0.9000
+.param sg13g2_lv_nmos_muew_norm   = 0.7780
+.param sg13g2_lv_nmos_dphibo_norm = 0.8137
+.param sg13g2_lv_nmos_dphibl_norm = 0.6550
+.param sg13g2_lv_nmos_dphibw_norm = 0.6105
+.param sg13g2_lv_nmos_dphiblw_norm= 0.9300
+.param sg13g2_lv_nmos_themuo_norm = 0.8708
+.param sg13g2_lv_nmos_thesatl_norm= 0.5510
+.param sg13g2_lv_nmos_thesatw_norm= 1.4300
+.param sg13g2_lv_nmos_thesatlw_norm= 0.0860
+.param sg13g2_lv_nmos_toxo_norm   = 0.9600
+.param sg13g2_lv_nmos_toxovo_norm = 0.9600
+.param sg13g2_lv_nmos_cjorbot_norm= 0.9200
+.param sg13g2_lv_nmos_cjorsti_norm= 0.9200
+.param sg13g2_lv_nmos_cjorgat_norm= 0.9200
+
+.param sg13g2_lv_pmos_vfbo_norm= 1.0
+.param sg13g2_lv_pmos_ctl_norm    = 2.4800
+.param sg13g2_lv_pmos_rsw1_norm   = 0.5000
+.param sg13g2_lv_pmos_muew_norm   = 0.9620
+.param sg13g2_lv_pmos_dphibo_norm = 1.2350
+.param sg13g2_lv_pmos_dphibl_norm = 0.5066
+.param sg13g2_lv_pmos_dphibw_norm = 3.9230
+.param sg13g2_lv_pmos_dphiblw_norm= 1.0000
+.param sg13g2_lv_pmos_themuo_norm = 1.0200
+.param sg13g2_lv_pmos_thesatl_norm= 0.1880
+.param sg13g2_lv_pmos_thesatw_norm= 1.2440
+.param sg13g2_lv_pmos_thesatlw_norm= 2.0000
+.param sg13g2_lv_pmos_toxo_norm   = 0.9600
+.param sg13g2_lv_pmos_toxovo_norm = 0.9600
+.param sg13g2_lv_pmos_cjorbot_norm= 0.9200
+.param sg13g2_lv_pmos_cjorsti_norm= 0.9200
+.param sg13g2_lv_pmos_cjorgat_norm= 0.9200
+
+.param sg13g2_lv_svaricap_lap   = 1.24
+.param sg13g2_lv_svaricap_toxo  = 0.96
+
+.include sg13g2_moslv_stat.lib
+.include sg13g2_moslv_mod.lib
+.ENDL mos_ff_stat
+
+**************** CORNER_LIB OF sg13g2_lv SF MODEL ****************
+* Slow n, Fast p
+.LIB mos_sf
+.param sg13g2_lv_nmos_vfbo_mm= 1.0
+.param sg13g2_lv_nmos_ctl    = 0.8509
+.param sg13g2_lv_nmos_rsw1   = 0.6880
+.param sg13g2_lv_nmos_muew   = 0.9100
+.param sg13g2_lv_nmos_dphibo = 1.0993
+.param sg13g2_lv_nmos_dphibl = 1.1526
+.param sg13g2_lv_nmos_dphibw = 1.1520
+.param sg13g2_lv_nmos_dphiblw= 0.9932
+.param sg13g2_lv_nmos_themuo = 0.8812
+.param sg13g2_lv_nmos_thesatl= 0.9405
+.param sg13g2_lv_nmos_thesatw= 1.5465
+.param sg13g2_lv_nmos_thesatlw= 0.8001
+.param sg13g2_lv_nmos_toxo   = 1.0200
+.param sg13g2_lv_nmos_toxovo = 1.0200
+.param sg13g2_lv_nmos_cjorbot= 1.0400
+.param sg13g2_lv_nmos_cjorsti= 1.0400
+.param sg13g2_lv_nmos_cjorgat= 1.0400
+
+.param sg13g2_lv_pmos_vfbo_mm= 1.0
+.param sg13g2_lv_pmos_ctl    = 2.2185
+.param sg13g2_lv_pmos_rsw1   = 0.6360
+.param sg13g2_lv_pmos_muew   = 1.0070
+.param sg13g2_lv_pmos_dphibo = 1.0700
+.param sg13g2_lv_pmos_dphibl = 0.6808
+.param sg13g2_lv_pmos_dphibw = 1.1715
+.param sg13g2_lv_pmos_dphiblw= 1.0000
+.param sg13g2_lv_pmos_themuo = 0.9890
+.param sg13g2_lv_pmos_thesatl= 0.3695
+.param sg13g2_lv_pmos_thesatw= 1.1620
+.param sg13g2_lv_pmos_thesatlw= 1.5000
+.param sg13g2_lv_pmos_toxo   = 0.9800
+.param sg13g2_lv_pmos_toxovo = 0.9800
+.param sg13g2_lv_pmos_cjorbot= 0.9600
+.param sg13g2_lv_pmos_cjorsti= 0.9600
+.param sg13g2_lv_pmos_cjorgat= 0.9600
+
+.param sg13g2_lv_svaricap_lap   = 1.161
+.param sg13g2_lv_svaricap_toxo  = 0.98
+
+.include sg13g2_moslv_mod.lib
+.ENDL mos_sf
+
+* Slow n, Fast p with statistical modeling
+.LIB mos_sf_stat
+.param sg13g2_lv_nmos_vfbo_norm= 1.0
+.param sg13g2_lv_nmos_ctl_norm    = 0.8509
+.param sg13g2_lv_nmos_rsw1_norm   = 0.6880
+.param sg13g2_lv_nmos_muew_norm   = 0.9100
+.param sg13g2_lv_nmos_dphibo_norm = 1.0993
+.param sg13g2_lv_nmos_dphibl_norm = 1.1526
+.param sg13g2_lv_nmos_dphibw_norm = 1.1520
+.param sg13g2_lv_nmos_dphiblw_norm= 0.9932
+.param sg13g2_lv_nmos_themuo_norm = 0.8812
+.param sg13g2_lv_nmos_thesatl_norm= 0.9405
+.param sg13g2_lv_nmos_thesatw_norm= 1.5465
+.param sg13g2_lv_nmos_thesatlw_norm= 0.8001
+.param sg13g2_lv_nmos_toxo_norm   = 1.0200
+.param sg13g2_lv_nmos_toxovo_norm = 1.0200
+.param sg13g2_lv_nmos_cjorbot_norm= 1.0400
+.param sg13g2_lv_nmos_cjorsti_norm= 1.0400
+.param sg13g2_lv_nmos_cjorgat_norm= 1.0400
+
+.param sg13g2_lv_pmos_vfbo_norm= 1.0
+.param sg13g2_lv_pmos_ctl_norm    = 2.2185
+.param sg13g2_lv_pmos_rsw1_norm   = 0.6360
+.param sg13g2_lv_pmos_muew_norm   = 1.0070
+.param sg13g2_lv_pmos_dphibo_norm = 1.0700
+.param sg13g2_lv_pmos_dphibl_norm = 0.6808
+.param sg13g2_lv_pmos_dphibw_norm = 1.1715
+.param sg13g2_lv_pmos_dphiblw_norm= 1.0000
+.param sg13g2_lv_pmos_themuo_norm = 0.9890
+.param sg13g2_lv_pmos_thesatl_norm= 0.3695
+.param sg13g2_lv_pmos_thesatw_norm= 1.1620
+.param sg13g2_lv_pmos_thesatlw_norm= 1.5000
+.param sg13g2_lv_pmos_toxo_norm   = 0.9800
+.param sg13g2_lv_pmos_toxovo_norm = 0.9800
+.param sg13g2_lv_pmos_cjorbot_norm= 0.9600
+.param sg13g2_lv_pmos_cjorsti_norm= 0.9600
+.param sg13g2_lv_pmos_cjorgat_norm= 0.9600
+
+.param sg13g2_lv_svaricap_lap   = 1.161
+.param sg13g2_lv_svaricap_toxo  = 0.98
+
+.include sg13g2_moslv_stat.lib
+.include sg13g2_moslv_mod.lib
+.ENDL mos_sf_stat
+**************** CORNER_LIB OF sg13g2_lv FS MODEL ****************
+* Fast n, Slow p without statistical
+.LIB mos_fs
+.param sg13g2_lv_nmos_vfbo_mm= 1.0
+.param sg13g2_lv_nmos_ctl    = 1.3195
+.param sg13g2_lv_nmos_rsw1   = 0.8100
+.param sg13g2_lv_nmos_muew   = 0.8140
+.param sg13g2_lv_nmos_dphibo = 0.9026
+.param sg13g2_lv_nmos_dphibl = 0.8122
+.param sg13g2_lv_nmos_dphibw = 0.7927
+.param sg13g2_lv_nmos_dphiblw= 0.9527
+.param sg13g2_lv_nmos_themuo = 0.8733
+.param sg13g2_lv_nmos_thesatl= 0.6680
+.param sg13g2_lv_nmos_thesatw= 1.4650
+.param sg13g2_lv_nmos_thesatlw= 0.3493
+.param sg13g2_lv_nmos_toxo   = 0.9800
+.param sg13g2_lv_nmos_toxovo = 0.9800
+.param sg13g2_lv_nmos_cjorbot= 0.9600
+.param sg13g2_lv_nmos_cjorsti= 0.9600
+.param sg13g2_lv_nmos_cjorgat= 0.9600
+
+.param sg13g2_lv_pmos_vfbo_mm= 1.0
+.param sg13g2_lv_pmos_ctl    = 1.6545
+.param sg13g2_lv_pmos_rsw1   = 0.8542
+.param sg13g2_lv_pmos_muew   = 1.0775
+.param sg13g2_lv_pmos_dphibo = 0.7467
+.param sg13g2_lv_pmos_dphibl = 1.1045
+.param sg13g2_lv_pmos_dphibw = -3.2860
+.param sg13g2_lv_pmos_dphiblw= 1.0000
+.param sg13g2_lv_pmos_themuo = 0.9150
+.param sg13g2_lv_pmos_thesatl= 0.8850
+.param sg13g2_lv_pmos_thesatw= 1.0337
+.param sg13g2_lv_pmos_thesatlw= 1.0000
+.param sg13g2_lv_pmos_toxo   = 1.0200
+.param sg13g2_lv_pmos_toxovo = 1.0200
+.param sg13g2_lv_pmos_cjorbot= 1.0400
+.param sg13g2_lv_pmos_cjorsti= 1.0400
+.param sg13g2_lv_pmos_cjorgat= 1.0400
+
+.param sg13g2_lv_svaricap_lap   = 1.041
+.param sg13g2_lv_svaricap_toxo  = 1.02
+
+.include sg13g2_moslv_mod.lib
+.ENDL mos_fs
+
+* Fast n, Slow p with statistical
+.LIB mos_fs_stat
+.param sg13g2_lv_nmos_vfbo_norm= 1.0
+.param sg13g2_lv_nmos_ctl_norm    = 1.3195
+.param sg13g2_lv_nmos_rsw1_norm   = 0.8100
+.param sg13g2_lv_nmos_muew_norm   = 0.8140
+.param sg13g2_lv_nmos_dphibo_norm = 0.9026
+.param sg13g2_lv_nmos_dphibl_norm = 0.8122
+.param sg13g2_lv_nmos_dphibw_norm = 0.7927
+.param sg13g2_lv_nmos_dphiblw_norm= 0.9527
+.param sg13g2_lv_nmos_themuo_norm = 0.8733
+.param sg13g2_lv_nmos_thesatl_norm= 0.6680
+.param sg13g2_lv_nmos_thesatw_norm= 1.4650
+.param sg13g2_lv_nmos_thesatlw_norm= 0.3493
+.param sg13g2_lv_nmos_toxo_norm   = 0.9800
+.param sg13g2_lv_nmos_toxovo_norm = 0.9800
+.param sg13g2_lv_nmos_cjorbot_norm= 0.9600
+.param sg13g2_lv_nmos_cjorsti_norm= 0.9600
+.param sg13g2_lv_nmos_cjorgat_norm= 0.9600
+
+.param sg13g2_lv_pmos_vfbo_norm= 1.0
+.param sg13g2_lv_pmos_ctl_norm    = 1.6545
+.param sg13g2_lv_pmos_rsw1_norm   = 0.8542
+.param sg13g2_lv_pmos_muew_norm   = 1.0775
+.param sg13g2_lv_pmos_dphibo_norm = 0.7467
+.param sg13g2_lv_pmos_dphibl_norm = 1.1045
+.param sg13g2_lv_pmos_dphibw_norm = -3.2860
+.param sg13g2_lv_pmos_dphiblw_norm= 1.0000
+.param sg13g2_lv_pmos_themuo_norm = 0.9150
+.param sg13g2_lv_pmos_thesatl_norm= 0.8850
+.param sg13g2_lv_pmos_thesatw_norm= 1.0337
+.param sg13g2_lv_pmos_thesatlw_norm= 1.0000
+.param sg13g2_lv_pmos_toxo_norm   = 1.0200
+.param sg13g2_lv_pmos_toxovo_norm = 1.0200
+.param sg13g2_lv_pmos_cjorbot_norm= 1.0400
+.param sg13g2_lv_pmos_cjorsti_norm= 1.0400
+.param sg13g2_lv_pmos_cjorgat_norm= 1.0400
+
+.param sg13g2_lv_svaricap_lap   = 1.041
+.param sg13g2_lv_svaricap_toxo  = 1.02
+
+.include sg13g2_moslv_stat.lib
+.include sg13g2_moslv_mod.lib
+.ENDL mos_fs_stat
diff --git a/ihp-sg13g2/libs.tech/xyce/models/sg13g2_hbt_mod.lib b/ihp-sg13g2/libs.tech/xyce/models/sg13g2_hbt_mod.lib
new file mode 100644
index 00000000..7265e941
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/models/sg13g2_hbt_mod.lib
@@ -0,0 +1,464 @@
+*#######################################################################
+*
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+*#######################################################################
+      
+* SPICE-Parameter HBT-Transistor (nom.)
+*
+* Model:                                VBIC (Rev.1.15)
+* Date:                                 25.05.18
+* Lot:                                  EDJ802
+* WAFER:                                02
+* CHIP Nr:                              3.3
+* Emitter size (mask):                  Nx *(0.07 x 0.90) �m^2 with Nx = 1 - 10
+* Maximum collector-to-emitter voltage: 1.6
+* Measurement data:                     T356_EDJ802_W02_3.3
+* Meas. Range forward gummel:           vbe = (0.3 - 1.04)V
+* Meas. Range forward output:           vce = (0.4 - 2.0)V
+* Nom. Temperature  (TNOM):             27 grd C
+* Meas. Temperature (TEMP):             27 grd C
+* Valid range for model                 
+* ic: <(0.003*Nx) A  vbe :(0.65 - 0.96) V  vce :(0.4 - 2.0) V
+* Temp: -40�C - +125�C
+* Valid numbers: NX = 1 - 10
+* ________________________________________________________________________
+
+.subckt npn13G2 c b e bn t
+.param Nx=1 dtemp=0
++Ny=1 le=0.96e-6 we=0.12e-6
++El=le*1e6
++selft=1
+
+*Yvbic13_4t_va vbic1 c b e s1 npn13G2_NX_vbic
+Qnpn13G2 c b e s1 t npn13G2_NX_vbic dtemp=dtemp m=1
+
+*.model npn13G2_NX_vbic vbic13_4t_va
+.model npn13G2_NX_vbic npn
++ level = 12
+*+ vbe_max = 1.6
+*+ vbc_max = 5.1
+*+ vce_max = 1.6
++ tnom = 27
++ cbeo = '8.00E-16*(Nx*0.25)**0.975'
++ cje = '8.418E-15*(Nx*0.25)**0.975*vbic_cje'
++ pe = 0.92
++ me = 0.12
++ aje = -0.50
++ wbe = 1.00
++ cbco = '2.36E-15*(Nx*0.25)'
++ cjc = '1.53E-15*(Nx*0.25)*vbic_cjc'
++ pc = 0.558
++ mc = 0.12
++ ajc = -0.50
++ cjep = '3.56E-15*(Nx*0.25)*vbic_cjc'
++ cjcp = '4.56E-15*(Nx*0.25)**0.8*vbic_cjcp'
++ ps = 0.46
++ ms = 0.23
++ ajs = -0.50
++ fc = 0.80
++ vef = 189
++ ver = 5.3
++ is = '4.81E-17*(Nx*0.25)*vbic_is'
++ nf = 1.018
++ ibei = '1.9E-19*(Nx*0.25)*vbic_ibei'
++ nei = 1.066
++ iben = '4.00E-16*(Nx*0.25)'
++ nen = 2.00
++ ikf = '0.009*(Nx*0.25)'
++ nr = 1.01
++ ibci = '1.50E-20*(Nx*0.25)'
++ nci = 1.103
++ ibcn = '1.00E-15*(Nx*0.25)'
++ ncn = 1.96
++ ikr = '0.01*(Nx*0.25)'
++ wsp = 1
++ isp = '4.00E-20*(Nx*0.25)'
++ nfp = 1.04
++ ibcip = '2.00E-15*(Nx*0.25)**0.7'
++ ncip = 1.00
++ ibcnp = '5.00E-15*(Nx*0.25)'
++ ncnp = 1.50
++ ikp = '.00E-04*(Nx*0.25)'
++ ibeip = '4.00E-19*(Nx*0.25)'
++ ibenp = '2.00E-14*(Nx*0.25)'
++ re = '7.13E+00*(4/Nx)**1*vbic_re'
++ rcx = '1.3E+01*(4/Nx)**1*vbic_rcx'
++ rci = '1.29E+01*(4/Nx)**1'
++ qco = 1.00E-18
++ vo = 0.80
++ gamm = 2.25E-14
++ hrcf = 1000
++ rbx = '6.93E+00*(4/Nx)**0.95*vbic_rbx'
++ rbi = '2.20E+01*(4/Nx)**0.95*vbic_rbx'
++ rbp = '5.5*(4/Nx)'
++ rs = 1
++ avc1 = 2.40
++ avc2 = 10.81
++ tf = '2.08E-13*vbic_tf*((temper+273)/300)**0.7'
++ qtf = 1.00E-18
++ xtf = 10.0
++ vtf = 20.0
++ itf = '0.585*(Nx*0.25)'
++ tr = 3.50E-13
++ td = '2.80E-13*(Nx*0.25)**0'
++ cth = '1.60E-12*(Nx*0.25)**0.95'
++ rth = '1*selft*3.26E+03*(4/Nx)**0.9'
++ ea = 1.056
++ eaie = 1.056
++ eaic = 1.12
++ eais = 1.12
++ eane = 1.12
++ eanc = 1.12
++ eans = 1.12
++ xre = -0.42
++ xrb = 0.90
++ xrc = 0.245
++ xrs = 1.50
++ xvo = 1.50
++ xis = 2.30
++ xii = 3.30
++ xin = 3.30
++ tnf = 0.00015
++ tavc = -0.00188
++ kfn = '6.00E-9*(4/Nx)'
++ afn = 1.80
++ bfn = 1.00
+
+Rsub s1 bn R = '300+100*Nx'
+Rt t 0 R = 1e9
+Csub s1 bn C = '2.30E-14-(1.50E-15*Nx)'
+.ends npn13G2
+
+*--------------------npn13g2l----------------------------------------------------
+
+* Model:                                VBIC (Rev.1.15)
+* Date:                                 25.05.18
+* Lot:                                  EDJ802
+* WAFER:                                02
+* CHIP Nr:                              3.3
+* Device:                               npn13g2l_VBIC_Q118
+* Emitter size (mask):                  Nx *(0.07 x El) �m^2 with Nx = 1 - 4, El = 1 - 2.5 
+* Maximum collector-to-emitter voltage: 1.6
+* Measurement data:                     T356_EDJ802_W02_3.3
+* Meas. Range forward gummel:           vbe = (0.3 - 1.04)V
+* Meas. Range forward output:           vce = (0.4 - 2.0)V
+* Nom. Temperature  (TNOM):             27 grd C
+* Meas. Temperature (TEMP):             27 grd C
+* Valid range for model
+* ic: <(...Nx*El) A  vbe :(0.65 - 0.96) V  vce :(0.4 - 2.0) V
+* Temp: -40�C - +125�C
+* Valid numbers: Nx = 1 - 4, El = 1 - 2.5
+* model card checked with SPECTRE 10.x and ADS2009U1
+* ________________________________________________________________________
+
+.subckt npn13G2l c b e bn t
+.param Nx=1 le=2.50e-6 dtemp=0
++Ny=1 we=0.12e-6
++El=le*1e6
++selft=1
+
+*Yvbic13_4t_va vbic1 c b e s1 npn13G2l_NX_vbic
+Qnpn13G21 c b e s1 t npn13G21_NX_vbic dtemp=dtemp m=1
+
+*.model npn13G2l_NX_vbic vbic13_4t_va
+.model npn13G21_NX_vbic npn
++ level = 12
+*+ vbe_max = 1.6
+*+ vbc_max = 5.1
+*+ vce_max = 1.6
++ tnom = 27
++ cbeo = '1.92E-15*(El/2.5)**0.85*(Nx*0.25)**0.95'
++ cje = '2.166E-14*(El/2.5)**0.85*(Nx*0.25)**0.95*vbic_cje'
++ pe = 0.92
++ me = 0.12
++ aje = -0.50
++ wbe = 1.00
++ cbco = '6.33E-15*(El/2.5)**0.85*(Nx*0.25)**0.975'
++ cjc = '3.83E-15*(El/2.5)**0.85*(Nx*0.25)**0.975*vbic_cjc'
++ pc = 0.558
++ mc = 0.12
++ ajc = -0.50
++ cjep = '7.77E-15*(El/2.5)**0.85*(Nx*0.25)**0.975*vbic_cjc'
++ cjcp = '8.36E-15*(El/2.5)**0.55*(Nx*0.25)**0.8*vbic_cjcp'
++ ps = 0.46
++ ms = 0.23
++ ajs = -0.50
++ fc = 0.80
++ vef = 189
++ ver = 5.3
++ is = '7.50E-17*(El/2.5)**0.85*(Nx*0.25)*vbic_is'
++ nf = 1.004
++ ibei = '2.01E-19*(El/2.5)**0.85*(Nx*0.25)*vbic_ibei'
++ nei = 1.035
++ iben = '1.20E-15*(El/2.5)**0.85*(Nx*0.25)'
++ nen = 2.00
++ ikf = '0.032*(El/2.5)*(Nx*0.25)'
++ nr = 1.01
++ ibci = '3.00E-19*(El/2.5)*(Nx*0.25)'
++ nci = 1.050
++ ibcn = '1.00E-15*(El/2.5)*(Nx*0.25)'
++ ncn = 1.70
++ ikr = '0.01*(El/2.5)*(Nx*0.25)'
++ wsp = 1
++ isp = '4.00E-20*(El/2.5)*(Nx*0.25)'
++ nfp = 1.04
++ ibcip = '2.00E-15*(El/2.5)*(Nx*0.25)**0.7'
++ ncip = 1.00
++ ibcnp = '5.00E-15*(El/2.5)*(Nx*0.25)'
++ ncnp = 1.50
++ ikp = '1.00E-04*(El/2.5)*(Nx*0.25)'
++ ibeip = '4.00E-19*(El/2.5)*(Nx*0.25)'
++ ibenp = '2.00E-14*(El/2.5)*(Nx*0.25)'
++ re = '3.19E+00*(2.5/El)*(4/Nx)**0.88*vbic_re'
++ rcx = '3.90E+00*(2.5/El)*(4/Nx)**0.9*vbic_rcx'
++ rci = '7.50E+00*(2.5/El)**0.85*(4/Nx)**1'
++ qco = 1.00E-18
++ vo = 0.80
++ gamm = 3.00E-14
++ hrcf = 1000
++ rbx = '2.54E+00*(2.5/El)**0.7*(4/Nx)*vbic_rbx'
++ rbi = '7.26E+00*(2.5/El)**0.7*(4/Nx)*vbic_rbx'
++ rbp = '15.0*(2.5/El)**0.7*(4/Nx)'
++ rs = '1*(2.5/El)*(4/Nx)'
++ avc1 = 2.40
++ avc2 = 10.81
++ tf = '2.31E-13*(El/2.5)**0.15*vbic_tf*((temper+273)/300)**0.7'
++ qtf = 1.00E-18
++ xtf = 10.0
++ vtf = 20.0
++ itf = '1.658*(El/2.5)*(Nx*0.25)'
++ tr = 5.00E-13
++ td = '2.8e-13*(El/2.5)'
++ cth = '4.18E-12*(El/2.5)**0.8*(Nx*0.25)**0.8'
++ rth = 'selft*1.63E+03*(2.5/El)**0.85*(4/Nx)**0.8'
++ ea = 1.045
++ eaie = 1.078
++ eaic = 1.12
++ eais = 1.12
++ eane = 1.12
++ eanc = 1.12
++ eans = 1.12
++ xre = -0.42
++ xrb = 0.90
++ xrc = 0.420
++ xrs = 1.50
++ xvo = 1.50
++ xis = 2.30
++ xii = 3.30
++ xin = 3.30
++ tnf = 0.00015
++ tavc = -0.00188
++ kfn = '3.00E-9*(2.5/El)*(4/Nx)'
++ afn = 1.80
++ bfn = 1.00
+
+Rsub s1 bn R = '(300+(400*Nx))*(El/2.5)**0.5'
+Csub s1 bn C = '(1.70E-14-(2.00E-15*Nx))*(El/2.5)**0'
+Rt t 0 R = 1e9
+.ends npn13G2l
+
+*--------------------npn13g2v----------------------------------------------------
+
+* Model:                                VBIC (Rev.1.15)
+* Date:                                 25.05.18
+* Lot:                                  EDJ802
+* WAFER:                                02
+* CHIP Nr:                              3.3
+* Device:                               npn13g2v_VBIC_Q118
+* Emitter size (mask):                  Nx *(0.12 x El) �m^2 with Nx = 1 - 4, El = 1.0 - 5.0 
+* Maximum collector-to-emitter voltage: 2.5
+* Measurement data:                     T356_EDJ802_W02_3.3
+* Meas. Range forward gummel:           vbe = (0.3 - 1.0)V
+* Meas. Range forward output:           vce = (0 - 3.0)V
+* Nom. Temperature  (TNOM):             27 grd C
+* Meas. Temperature (TEMP):             27 grd C
+* Valid range for model
+* ic: <(0.50*Nx*El) A  vbe :(0.65 - 0.84) V  vce :(0.8 - 2.3) V
+* Temp: -40�C - +125�C
+* Valid numbers: Nx = 1 - 4, El = 1 - 5
+* model card checked with SPECTRE 10.x and ADS2009U1
+* ________________________________________________________________________
+
+.subckt npn13G2v c b e bn t
+.param Nx=1 le=2.50e-6 dtemp=0
++Ny=1 we=0.12e-6
++El=le*1e6
++selft=1
+
+*Yvbic13_4t_va vbic1 c b e s1 npn13G2v_NX_vbic
+Qnpn13G21 c b e s1 t npn13G2v_NX_vbic dtemp=dtemp m=1
+
+*.model npn13G2v_NX_vbic vbic13_4t_va
+.model npn13G2v_NX_vbic npn
++ level = 12
+*+ vbe_max = 1.6
+*+ vbc_max = 7.0
+*+ vce_max = 2.2
++ tnom = 27
++ cbeo = '2.28E-15*(El/2.5)**0.94*(Nx*0.25)**0.95'
++ cje = '2.594E-14*(El/2.5)**0.94*(Nx*0.25)**0.95*vbic_cje'
++ pe = 0.88
++ me = 0.13
++ aje = -0.50
++ wbe = 1.00
++ cbco = '4.37E-15*(El/2.5)**0.85*(Nx*0.25)**0.975'
++ cjc = '2.52E-15*(El/2.5)**0.85*(Nx*0.25)**0.975*vbic_cjc'
++ pc = 0.397
++ mc = 0.09
++ ajc = -0.50
++ cjep = '6.48E-15*(El/2.5)**0.85*(Nx*0.25)**0.975*vbic_cjc'
++ cjcp = '7.60E-15*(El/2.5)**0.65*(Nx*0.25)**0.5*vbic_cjcp'
++ ps = 0.31
++ ms = 0.16
++ ajs = -0.50
++ fc = 0.80
++ vef = 189
++ ver = 5.3
++ is = '1.22E-16*(El/2.5)**0.8*(Nx*0.25)*vbic_is'
++ nf = 1.016
++ ibei = '3.02E-19*(El/2.5)**0.925*(Nx*0.25)*vbic_ibei'
++ nei = 1.043
++ iben = '1.44E-15*(El/2.5)**0.925*(Nx*0.25)'
++ nen = 2.00
++ ikf = '0.022*(El/2.5)*(Nx*0.25)'
++ nr = 1.01
++ ibci = '7.50E-19*(El/2.5)*(Nx*0.25)'
++ nci = 1.050
++ ibcn = '1.00E-15*(El/2.5)*(Nx*0.25)'
++ ncn = 1.70
++ ikr = '0.01*(El/2.5)*(Nx*0.25)'
++ wsp = 1
++ isp = '4.00E-20*(El/2.5)*(Nx*0.25)'
++ nfp = 1.04
++ ibcip = '2.00E-15*(El/2.5)*(Nx*0.25)**0.7'
++ ncip = 1.00
++ ibcnp = '5.00E-15*(El/2.5)*(Nx*0.25)'
++ ncnp = 1.50
++ ikp = '1.00E-04*(El/2.5)*(Nx*0.25)'
++ ibeip = '4.00E-19*(El/2.5)*(Nx*0.25)'
++ ibenp = '2.00E-14*(El/2.5)*(Nx*0.25)'
++ re = '3.30E+00*(2.5/El)*(4/Nx)**0.88*vbic_re'
++ rcx = '1.30E+01*(2.5/El)*(4/Nx)**0.9*vbic_rcx'
++ rci = '1.53E+02*(2.5/El)**0.9*(4/Nx)'
++ qco = 1.00E-18
++ vo = 2.40
++ gamm = 3.30E-12
++ hrcf = 1000
++ rbx = '1.54E+00*(2.5/El)**0.75*(4/Nx)*vbic_rbx'
++ rbi = '6.60E+00*(2.5/El)**0.75*(4/Nx)*vbic_rbx'
++ rbp = '6.5*(2.5/El)**0.75*(4/Nx)'
++ rs = '1*(2.5/El)*(4/Nx)'
++ avc1 = 2.40
++ avc2 = 17.14
++ tf = '4.10E-13*(El/2.5)**0*vbic_tf*((temper+273)/300)**0.7'
++ qtf = 1.00E-18
++ xtf = 60.0
++ vtf = 20.0
++ itf = '0.390*(El/2.5)*(Nx*0.25)'
++ tr = 1.50E-12
++ td = '5.60E-13*(El/2.5)'
++ cth = '4.40E-12*(El/2.5)**1*(Nx*0.25)**0.8'
++ rth = 'selft*1.55E+03*(2.5/El)**1*(4/Nx)**0.88'
++ ea = 1.030
++ eaie = 1.056
++ eaic = 1.12
++ eais = 1.12
++ eane = 1.12
++ eanc = 1.12
++ eans = 1.12
++ xre = -0.35
++ xrb = 0.90
++ xrc = 0.175
++ xrs = 1.50
++ xvo = 1.50
++ xis = 2.70
++ xii = 3.00
++ xin = 3.00
++ tnf = 0.00015
++ tavc = -0.00075
++ kfn = '6.00E-7*(2.5/El)*(4/Nx)'
++ afn = 2.20
++ bfn = 1.00
+
+Rsub s1 bn R = '(300+(400*Nx))*(El/2.5)**0.85'
+Csub s1 bn C = '(1.70E-14-(2.00E-15*Nx))*(El/2.5)**0'
+Rt t 0 R = 1e9
+.ends npn13G2v
+
+*******************************************************************************
+* pnpMPA section
+*******************************************************************************
+*--------------------------------------------------
+* Testfield: T323
+* Technology: SG13
+* Lot: PQA701
+* Wafer: 17
+* DUT: diode_pp=pnpMPA
+* Temperature range: -40C ... +125C
+* Date: 21.10.2022
+* DC Measurements at T=27C, T=-40C and T=125C (2013), 2022 only T=27C
+* CV Measurements at T=27C
+*
+*--------------------------------------------------------------------------
+*
+.param ccb0 = 970e-018  isc0 = 2e-023  ikr0 = 4e-007  rc0 = 1e+003  rb0 = 700
+*
+.subckt pnpMPA e b c
+.param a=2p p=6u ac=13.33p pc=14.64u
++ dev_a=a*1e12 dev_p=p*1e6 sub_a=ac*1e12 sub_p=pc*1e6
+
+QpnpMPA e b c pnpMPA_mod area=dev_a
+
+.model pnpMPA_mod pnp
++ level = 1
++ tnom = 27
++ is = '1.660E-19*sgp_mpa_is'
++ nf = 1.015
++ ise = 1e-022
++ ne = 1
++ bf = '1.10*sgp_mpa_bf'
++ ikf = 0.0003
++ vaf = 100
++ nr = 1
++ isc = '(isc0*(sub_a))/(dev_a)'
++ nc = 1
++ br = 0.00015
++ ikr = '(ikr0*(sub_a))/(dev_a)'
++ var = 150
++ rb = 'rb0*sgp_mpa_rb'
++ irb = 1e-015
++ rbm = '0.9*rb0*sgp_mpa_rb'
++ re = '20*sgp_mpa_re'
++ rc = '(rc0/(sub_a))*(dev_a)*sgp_mpa_rc'
++ cje = '1.72e-015*sgp_mpa_cje'
++ vje = 0.46
++ mje = 0.126
++ cjc = '((ccb0*(sub_a))/(dev_a))*sgp_mpa_cjc'
++ vjc = 0.58
++ mjc = 0.3
++ cjs = 0
++ vjs = 0.95
++ mjs = 0.5
++ xtb = 2.44
++ xti = 2.54
++ eg = 1.17
++ trm1 = 0.001
++ trm2 = 0
++ trc1 = -0.01121
++ trc2 = 3.02E-005
++ tre1 = 0
++ tre2 = 0
+.ends pnpMPA
diff --git a/ihp-sg13g2/libs.tech/xyce/models/sg13g2_hbt_stat.lib b/ihp-sg13g2/libs.tech/xyce/models/sg13g2_hbt_stat.lib
new file mode 100644
index 00000000..b8206d18
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/models/sg13g2_hbt_stat.lib
@@ -0,0 +1,37 @@
+*#######################################################################
+*
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+*#######################################################################
+
+* process variation parameters
+.param  vbic_cje  = 'gauss(vbic_cje_norm, 0.058, mc_ok)'
+.param  vbic_cjc  = 'gauss(vbic_cjc_norm, 0.043, mc_ok)'
+.param  vbic_cjcp = 'gauss(vbic_cjcp_norm, 0.037, mc_ok)'
+.param  vbic_is   = 'gauss(vbic_is_norm, 0.087, mc_ok)'
+.param  vbic_ibei = 'gauss(vbic_ibei_norm, 0.11, mc_ok)'
+.param  vbic_re   = 'gauss(vbic_re_norm, 0.09, mc_ok)'
+.param  vbic_rcx  = 'gauss(vbic_rcx_norm, 0.069, mc_ok)'
+.param  vbic_rbx  = 'gauss(vbic_rbx_norm, 0.041, mc_ok)'
+*.param  vbic_tf   = 'gauss(vbic_tf_norm, 0.037, mc_ok)'
+
+* pnpMPA device
+.param sgp_mpa_cje = 'gauss(sgp_mpa_cje_norm, 0.015, mc_ok)'
+.param sgp_mpa_cjc = 'gauss(sgp_mpa_cjc_norm, 0.007, mc_ok)'
+.param sgp_mpa_is  = 'gauss(sgp_mpa_is_norm, 0.043, mc_ok)'
+.param sgp_mpa_bf  = 'gauss(sgp_mpa_bf_norm, 0.079, mc_ok)'
+.param sgp_mpa_re  = 'gauss(sgp_mpa_re_norm, 0.016, mc_ok)'
+.param sgp_mpa_rb  = 'gauss(sgp_mpa_rb_norm, 0.008, mc_ok)'
+.param sgp_mpa_rc  = 'gauss(sgp_mpa_rc_norm, 0.017, mc_ok)'
diff --git a/ihp-sg13g2/libs.tech/xyce/models/sg13g2_moshv_mod.lib b/ihp-sg13g2/libs.tech/xyce/models/sg13g2_moshv_mod.lib
new file mode 100644
index 00000000..457d0c90
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/models/sg13g2_moshv_mod.lib
@@ -0,0 +1,92 @@
+*******************************************************************************
+*                                                                             *
+* Library:      SG13G2_dev                                                    *
+* Technologies: SG13G2                                                        *
+*                                                                             *
+* Model:        PSP 103.6                                                     *
+* Revision:     210511                                                        *
+*                                                                             *
+*******************************************************************************
+*                                                                             *
+* Copyright 2023 IHP PDK Authors                                              *
+*                                                                             *
+* Licensed under the Apache License, Version 2.0 (the "License");             *
+* you may not use this file except in compliance with the License.            *
+* You may obtain a copy of the License at                                     *
+*                                                                             *
+*     https://www.apache.org/licenses/LICENSE-2.0                             *
+*                                                                             *
+* Unless required by applicable law or agreed to in writing, software         *
+* distributed under the License is distributed on an "AS IS" BASIS,           *
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.    *
+* See the License for the specific language governing permissions and         *
+* limitations under the License.                                              *
+*                                                                             *
+*******************************************************************************
+*******************************************************************************
+*                                                                             *
+*                                                                             *
+*              C O M M O N    SG 13  M O S     M O D E L S                    *
+*                                                                             *
+*                                                                             *
+*******************************************************************************
+*
+* NOTE: do not include this file directly in the netlist, use models.typ, .bcs or .wcs only
+*
+*
+*
+*******************************************************************************
+* variable C section
+*******************************************************************************
+
+
+*******************************************************************************
+* MOS transistor section
+*******************************************************************************
+
+
+
+* MOS-Subckt with D/S-overlap possibility
+*
+*       z1              z2            z1
+*   ----------------------------------------
+*   |          |   |         |   |         |
+*   |    S     | G |   D     | G |    S    |  w/ng, >=0.15u
+*   |          |   |         |   |         |
+*   ----------------------------------------
+*
+*  z1=0.34u, z2=0.38u
+*
+* Parameters as,ad,ps,pd are calculated automatically, if <= 0
+*
+*
+
+.subckt sg13_hv_nmos d g s b
++ w=0.35u l=0.34u ng=1 m=1 as=0 ad=0 pd=0 ps=0 trise=0 z1=0.34e-6 z2=0.38e-6 wmin=0.15e-6 rfmode=0 pre_layout=1
+* if as = 0, calculate value, else take it
+* if as is given externally, no adjustment for ng is done! -> must be done in the extractor
+* if ng>1 and as=0 (in schematic) recalculate!
+
+
+* include the model parameters
+.include sg13g2_moshv_parm.lib
+
+YPSP103_VA M1 d g s b sg13g2_hv_nmos_psp w='w/ng' l=l as='as/ng' ad='ad/ng' pd='pd/ng' ps='ps/ng' mult='ng*m'
++ dta=trise
++ ngcon=2
+
+.ends
+
+
+.subckt sg13_hv_pmos d g s b
++ w=0.35u l=0.28u ng=1 m=1 as=0 ad=0 pd=0 ps=0 trise=0 z1=0.34e-6 z2=0.38e-6 wmin=0.15e-6 rfmode=0 pre_layout=1
+
+* include the model parameters
+.include sg13g2_moshv_parm.lib
+
+YPSP103_VA M1 d g s b sg13g2_hv_pmos_psp w='w/ng' l=l as='as/ng' ad='ad/ng' pd='pd/ng' ps='ps/ng' mult='ng*m'
++ dta=trise
++ ngcon=2
+
+.ends
+
diff --git a/ihp-sg13g2/libs.tech/xyce/models/sg13g2_moshv_parm.lib b/ihp-sg13g2/libs.tech/xyce/models/sg13g2_moshv_parm.lib
new file mode 100644
index 00000000..511a9d6f
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/models/sg13g2_moshv_parm.lib
@@ -0,0 +1,340 @@
+******************************************************************************* 
+*                                                                             * 
+* Library:      SG13G2_dev                                                    * 
+* Technologies: SG13G2                                                        *
+*                                                                             *
+* Model:        PSP 103.6                                                     *
+* Revision:     210511                                                        * 
+*                                                                             * 
+******************************************************************************* 
+*                                                                             * 
+* Copyright 2023 IHP PDK Authors                                              *
+*                                                                             *
+* Licensed under the Apache License, Version 2.0 (the "License");             *
+* you may not use this file except in compliance with the License.            *
+* You may obtain a copy of the License at                                     *
+*                                                                             *
+*     https://www.apache.org/licenses/LICENSE-2.0                             *
+*                                                                             *
+* Unless required by applicable law or agreed to in writing, software         *
+* distributed under the License is distributed on an "AS IS" BASIS,           *
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.    *
+* See the License for the specific language governing permissions and         *
+* limitations under the License.                                              *
+*                                                                             *
+*******************************************************************************
+*
+*
+******************************************************************************* 
+*                                                                             *
+*                                                                             *
+*                      M O D E L  P A R A M E T E R S                         *
+*                                                                             *
+*                                                                             *
+******************************************************************************* 
+*
+*
+*
+*
+*
+*
+*
+*******************************************************************************
+*                                                                             
+* High Voltage (hv) MOS Transistors   
+*                                                 
+* Model:                                PSP 103.6
+* Date:                                 10.03.2020
+* Lot:                                  EDJ
+* WAFER:                                06
+* CHIP Nr:                              x=3, y=9
+* Device:                               SG13G2
+* Maximum drain-source voltage:         3.3
+* Measurement data:                     
+* Nom. Temperature  (TNOM):             27 grd C
+* Meas. Temperature (TEMP):             27 grd C
+* Valid range for model:                L = (0.45 - 10)um   nmos
+*                                       L = (0.40 - 10)um   pmos
+*                                       W = (0.30 - 10)um
+*                                                                             
+*******************************************************************************
+
+.model sg13g2_hv_nmos_psp psp103_va           type          =  +1                          
++ tr            =  27.0                        dta           =  0.0                         
++ swgeo         =  1.0                         swigate       =  1.0                         swimpact      =  1.0                         
++ swgidl        =  0.0                         swjuncap      =  3.0                         swjunasym     =  0.0                         
++ swnud         =  0.0                         swedge        =  0.0                         swdelvtac     =  0.0                         
++ swign         =  1.0                         qmc           =  1.0                         lvaro         =  3.499e-08                   
++ lvarl         = -0.09125                     lvarw         =  0.0                         lap           =  6.3866e-08                  
++ wvaro         =  0.0                         wvarl         =  0.0                         wvarw         =  0.0                         
++ wot           =  3e-08                       dlq           =  '5.2202e-08 -((1-pre_layout)*0.0 )+rfmode*(-2e-08 +(ng<3 ? 5.9558e-09 : 0) )' dwq           =  '3e-08 +rfmode*(7.1489e-08 )' 
++ vfbo          = '-0.89839*(1+(sg13g2_hv_nmos_vfbo_mm-1)/sqrt(m*l*w*1e12))'            vfbl          =  0.15096                     vfbw          =  0.0017033                   
++ vfblw         =  0.019398                    stvfbo        =  0.0008739                   stvfbl        =  0.00014864                  
++ stvfbw        = -4.6174e-05                  stvfblw       = -2.445e-06                   st2vfbo       =  0.0                         
++ toxo          =  '7.4256e-09*sg13g2_hv_nmos_toxo'                                         epsroxo       =  3.9                         nsubo         =  1.8552e+23                  
++ nsubw         = -0.0050198                   wseg          =  1.098e-10                   npck          =  3.178e+23                   
++ npckw         = -2.7604                      wsegp         =  1e-08                       lpck          =  1e-08                       
++ lpckw         =  0.0                         fol1          =  0.21033                     fol2          =  0.0026472                   
++ facneffaco    =  1.0                         facneffacl    =  0.0                         facneffacw    =  0.0                         
++ facneffaclw   =  0.0                         gfacnudo      =  1.0                         gfacnudl      =  0.0                         
++ gfacnudlexp   =  1.0                         gfacnudw      =  0.0                         gfacnudlw     =  0.0                         
++ vsbnudo       =  0.0                         dvsbnudo      =  1.0                         vnsubo        =  0.0                         
++ nslpo         =  0.05                        dnsubo        =  0.025686                    dphibo        = '-0.042228*sg13g2_hv_nmos_dphibo'                                           
++ dphibl        = '-0.0035715*sg13g2_hv_nmos_dphibl'                                        dphiblexp     =  2.3956                      dphibw        =  '0.014614*sg13g2_hv_nmos_dphibw'                                           
++ dphiblw       = '-0.02006*sg13g2_hv_nmos_dphiblw'                                         delvtaco      =  0.0                         delvtacl      =  0.0                         
++ delvtaclexp   =  1.0                         delvtacw      =  0.0                         delvtaclw     =  0.0                         
++ npo           =  3.897e+26                   npl           = -0.1215                      toxovo        =  '7.4256e-09*sg13g2_hv_nmos_toxovo'                                         
++ toxovdo       =  2e-09                       lov           =  '6.3866e-08 -((1-pre_layout)*1e-08 )'                                      lovd          =  0.0                         
++ novo          =  5.5814e+24                  novdo         =  5e+25                       cto           = -0.061658                    
++ ctl           =  '0.025*sg13g2_hv_nmos_ctl'    ctlexp        =  1.6063                      ctw         = -0.044911                    
++ ctlw          = -0.0077386                   ctgo          =  0.0                         ctbo          =  0.0                         
++ stcto         =  1.0                         cfl           =  0.0048288                   cflexp        =  1.3328                      
++ cfw           =  0.037319                    cfbo          =  0.26069                     cfdo          =  0.0                         
++ pscel         =  0.0                         pscelexp      =  2.0                         pscew         =  0.0                         
++ pscebo        =  0.0                         pscedo        =  0.0                         uo            =  0.046687                    
++ fbet1         = -0.35712                     fbet1w        = -0.14995                     lp1           =  4.5615e-08                  
++ lp1w          =  0.4189                      fbet2         = -1.0245                      lp2           =  9.42e-09                    
++ betw1         =  0.6567                      betw2         = -0.083639                    wbet          =  1.0063e-10                  
++ stbeto        =  1.6942                      stbetl        = -0.0065587                   stbetw        = -0.060053                    
++ stbetlw       =  0.00036994                  mueo          =  '0.85058*sg13g2_hv_nmos_mueo' muew          = -0.018226                    
++ stmueo        =  0.34067                     themuo        =  2.5509                      stthemuo      =  0.63756                     
++ cso           =  2.0494                      csl           = -0.97261                     cslexp        =  0.0                         
++ csw           =  0.044205                    cslw          = -1.0021                      stcso         =  2.5545                      
++ thecso        =  2.0                         stthecso      =  0.0                         xcoro         =  0.04872                     
++ xcorl         = -0.27137                     xcorw         = -0.1948                      xcorlw        =  0.0                         
++ stxcoro       =  1.1327                      fetao         =  1.0706                      rsw1          =  '407.81*sg13g2_hv_nmos_rsw1'  
++ rsw2          = -0.07                        strso         = -0.058157                    rsbo          = -0.0025425                   
++ rsgo          =  '0.10986*sg13g2_hv_nmos_rsgo' thesato       =  '0.1*sg13g2_hv_nmos_thesato'  thesatl       =  '0.4314*sg13g2_hv_nmos_thesatl'                                            
++ thesatlexp    =  1.0973                      thesatw       =  '0.082797*sg13g2_hv_nmos_thesatw'                                          thesatlw      = '-0.020497*sg13g2_hv_nmos_thesatlw'                                         
++ stthesato     =  0.48396                     stthesatl     =  0.50226                     stthesatw     =  0.049985                    
++ stthesatlw    = -0.059487                    thesatbo      =  0.06                        thesatgo      =  0.050814                    
++ axo           =  8.7694                      axl           =  2.3029                      alpl          =  0.0019702                   
++ alplexp       =  1.4003                      alpw          =  1.1052                      alp1l1        =  0.007475                    
++ alp1lexp      =  0.80983                     alp1l2        =  0.719                       alp1w         =  0.56703                     
++ alp2l1        =  5.413e-07                   alp2lexp      =  0.2541                      alp2l2        =  0.0                         
++ alp2w         = -10.0                        vpo           =  0.06567                     a1o           =  4.7288                      
++ a1l           =  0.052459                    a1w           =  0.024056                    a2o           =  22.013                      
++ sta2o         =  0.018532                    a3o           =  1.2047                      a3l           = -0.10308                     
++ a3w           =  0.0069117                   a4o           =  0.12894                     a4l           = -0.05413                     
++ a4w           = -0.06197                     gcoo          =  0.0                         iginvlw       =  '0.0 *(1+0.0 /l)*(1+0.0 /w)'  
++ igovw         =  0.0                         igovdw        =  0.0                         stigo         =  2.0                         
++ gc2o          =  0.375                       gc3o          =  0.063                       chibo         =  3.1                         
++ agidlw        =  70.0                        agidldw       =  0.0                         bgidlo        =  13.0                        
++ bgidldo       =  41.0                        stbgidlo      = -0.001067                    stbgidldo     =  0.0                         
++ cgidlo        =  0.0                         cgidldo       =  0.0                         cgbovl        =  2.522e-16                   
++ cfrdw         =  0.0                         fnto          =  1.0                         
++ fntexcl       =  0.0                         nfalw         =  1.42e+25                    nfblw         =  574300000.0                 
++ nfclw         = -3.015e-08                   efo           =  1.0                         lintnoi       = -3.158e-08                   
++ alpnoi        =  2.708                       wedge         =  1e-08                       wedgew        =  0.0                         
++ vfbedgeo      = -1.0                         stvfbedgeo    =  0.0005                      stvfbedgel    =  0.0                         
++ stvfbedgew    =  0.0                         stvfbedgelw   =  0.0                         dphibedgeo    =  0.0                         
++ dphibedgel    =  0.0                         dphibedgelexp =  1.0                         dphibedgew    =  0.0                         
++ dphibedgelw   =  0.0                         nsubedgeo     =  5e+23                       nsubedgel     =  0.0                         
++ nsubedgelexp                                               =  1.0                         nsubedgew     =  0.0                         nsubedgelw    =  0.0                         
++ ctedgeo       =  0.0                         ctedgel       =  0.0                         ctedgelexp    =  1.0                         
++ fbetedge      =  0.0                         lpedge        =  1e-08                       betedgew      =  0.0                         
++ stbetedgeo    =  1.0                         stbetedgel    =  0.0                         stbetedgew    =  0.0                         
++ stbetedgelw   =  0.0                         psceedgel     =  0.0                         psceedgelexp  =  2.0                         
++ psceedgew     =  0.0                         pscebedgeo    =  0.0                         pscededgeo    =  0.0                         
++ cfedgel       =  0.0                         cfedgelexp    =  2.0                         cfedgew       =  0.0                         
++ cfdedgeo      =  0.0                         cfbedgeo      =  0.0                         fntedgeo      =  1.0                         
++ nfaedgelw     =  8e+22                       nfbedgelw     =  30000000.0                  nfcedgelw     =  0.0                         
++ efedgeo       =  1.0                         saref         =  1e-06                       sbref         =  1e-06                       
++ wlod          =  0.0                         kuo           =  0.0                         kvsat         =  0.0                         
++ tkuo          =  0.0                         lkuo          =  0.0                         wkuo          =  0.0                         
++ pkuo          =  0.0                         llodkuo       =  0.0                         wlodkuo       =  0.0                         
++ kvtho         =  0.0                         lkvtho        =  0.0                         wkvtho        =  0.0                         
++ pkvtho        =  0.0                         llodvth       =  0.0                         wlodvth       =  0.0                         
++ stetao        =  0.0                         lodetao       =  1.0                         scref         =  1e-06                       
++ web           =  0.0                         wec           =  0.0                         kvthoweo      =  0.0                         
++ kvthowel      =  0.0                         kvthowew      =  0.0                         kvthowelw     =  0.0                         
++ kuoweo        =  0.0                         kuowel        =  0.0                         kuowew        =  0.0                         
++ kuowelw       =  0.0                         trj           =  21.0                        swjunexp      =  0.0                         
++ imax          =  0.0020128                   frev          =  1000.0                      cjorbot       =  '0.00085856*sg13g2_hv_nmos_cjorbot'                                        
++ cjorsti       =  '2.4557e-11*sg13g2_hv_nmos_cjorsti'                                        cjorgat       =  '1.3846e-11*sg13g2_hv_nmos_cjorgat'                                        vbirbot       =  0.74373                     
++ vbirsti       =  1.597                       vbirgat       =  0.6629                      pbot          =  0.27424                     
++ psti          =  0.16571                     pgat          =  0.1451                      cjorbotd      =  0.001                       
++ cjorstid      =  1e-09                       cjorgatd      =  1e-09                       vbirbotd      =  1.0                         
++ vbirstid      =  1.0                         vbirgatd      =  1.0                         pbotd         =  0.5                         
++ pstid         =  0.5                         pgatd         =  0.5                         phigbot       =  1.1984                      
++ phigsti       =  1.006                       phiggat       =  0.3                         idsatrbot     =  5.397e-08                   
++ idsatrsti     =  4.0612e-15                  idsatrgat     =  0.0                         csrhbot       =  100.0                       
++ csrhsti       =  0.0001                      csrhgat       =  0.0001                      xjunsti       =  1.61e-08                    
++ xjungat       =  6.134e-07                   phigbotd      =  1.16                        phigstid      =  1.16                        
++ phiggatd      =  1.16                        idsatrbotd    =  1e-12                       idsatrstid    =  1e-18                       
++ idsatrgatd    =  1e-18                       csrhbotd      =  100.0                       csrhstid      =  0.0001                      
++ csrhgatd      =  0.0001                      xjunstid      =  1e-07                       xjungatd      =  1e-07                       
++ ctatbot       =  100.0                       ctatsti       =  0.0001                      ctatgat       =  0.0001                      
++ mefftatbot    =  0.25                        mefftatsti    =  0.25                        mefftatgat    =  0.25                        
++ ctatbotd      =  100.0                       ctatstid      =  0.0001                      ctatgatd      =  0.0001                      
++ mefftatbotd   =  0.25                        mefftatstid   =  0.25                        mefftatgatd   =  0.25                        
++ cbbtbot       =  1e-12                       cbbtsti       =  1e-21                       cbbtgat       =  1e-18                       
++ fbbtrbot      =  1000000000.0                fbbtrsti      =  1000000000.0                fbbtrgat      =  1000000000.0                
++ stfbbtbot     = -0.001                       stfbbtsti     = -0.001                       stfbbtgat     = -0.001                       
++ cbbtbotd      =  1e-12                       cbbtstid      =  1e-18                       cbbtgatd      =  1e-18                       
++ fbbtrbotd     =  1000000000.0                fbbtrstid     =  1000000000.0                fbbtrgatd     =  1000000000.0                
++ stfbbtbotd    = -0.001                       stfbbtstid    = -0.001                       stfbbtgatd    = -0.001                       
++ vbrbot        =  10.0                        vbrsti        =  10.0                        vbrgat        =  10.0                        
++ pbrbot        =  4.0                         pbrsti        =  4.0                         pbrgat        =  4.0                         
++ vbrbotd       =  10.0                        vbrstid       =  10.0                        vbrgatd       =  10.0                        
++ pbrbotd       =  4.0                         pbrstid       =  4.0                         pbrgatd       =  4.0                         
++ vjunref       =  2.5                         fjunq         =  0.03                        vjunrefd      =  2.5                         
++ fjunqd        =  0.03                        rint          =  3.0856e-12                  
++ rvpoly        =  0.0                         dlsil         =  0.0                         
++ rsh           =  0.0                         rshd          =  0.0                         
++ munqso        =  1.0                         
++ swnqs         =  'rfmode * 5.0'                cfrw          =  '(pre_layout * (1-rfmode)*1.2e-16 + rfmode * (0.0 + pre_layout * (ng>0 ? 4.1214e-16 : 0)))/ng' 
++ rshg          =  'rfmode * 20.0'               rgo           =  'rfmode * 35.0'               
++ rbulko        =  'rfmode * 0.002 * ng/w'       rwello        =  'rfmode * 0.002 * ng/w'       
++ rjunso        =  'rfmode * 5000.0 * l/w'       rjundo        =  'rfmode * 5000.0 * l/w'       
+
+
+*******************************************************************************
+*                                                                             
+* High Voltage (hv) MOS Transistors   
+*                                                 
+* Model:                                PSP 103.6
+* Date:                                 10.03.2020
+* Lot:                                  EDJ
+* WAFER:                                06
+* CHIP Nr:                              x=3, y=9
+* Device:                               SG13G2
+* Maximum drain-source voltage:         3.3
+* Measurement data:                     
+* Nom. Temperature  (TNOM):             27 grd C
+* Meas. Temperature (TEMP):             27 grd C
+* Valid range for model:                L = (0.45 - 10)um   nmos
+*                                       L = (0.40 - 10)um   pmos
+*                                       W = (0.30 - 10)um
+*                                                                             
+*******************************************************************************
+
+.model sg13g2_hv_pmos_psp psp103_va           type          =  -1                          
++ tr            =  27.0                        dta           =  0.0                         
++ swgeo         =  1.0                         swigate       =  1.0                         swimpact      =  1.0                         
++ swgidl        =  1.0                         swjuncap      =  3.0                         swjunasym     =  0.0                         
++ swnud         =  0.0                         swedge        =  0.0                         swdelvtac     =  0.0                         
++ swign         =  1.0                         qmc           =  1.0                         lvaro         = -1.735e-09                   
++ lvarl         =  0.0                         lvarw         =  0.0                         lap           =  3.471e-08                   
++ wvaro         =  0.0                         wvarl         =  0.0                         wvarw         =  0.0                         
++ wot           =  0.0                         dlq           =  '3.537e-08 -((1-pre_layout)*1e-07 )+rfmode*(2.96e-09 +(ng<3 ? 4e-08 : 0) )' dwq           =  '3e-08 +rfmode*(2.67e-07 )'   
++ vfbo          = '-1.0717*(1+(sg13g2_hv_pmos_vfbo_mm-1)/sqrt(m*l*w*1e12))'               vfbl          = -0.03                        vfbw          =  0.0                         
++ vfblw         =  0.0                         stvfbo        =  0.00057379                  stvfbl        =  8.6794e-05                  
++ stvfbw        =  4.9309e-05                  stvfblw       = -3.6436e-05                  st2vfbo       =  0.0                         
++ toxo          =  '6.945e-09*sg13g2_hv_pmos_toxo'                                            epsroxo       =  3.9                         nsubo         =  4.2268e+23                  
++ nsubw         =  0.01112                     wseg          =  5.362e-08                   npck          =  8.0711e+23                  
++ npckw         = -0.011403                    wsegp         =  1e-06                       lpck          =  8.3733e-09                  
++ lpckw         =  0.077499                    fol1          =  0.065253                    fol2          =  0.010199                    
++ facneffaco    =  1.0                         facneffacl    =  0.0                         facneffacw    =  0.0                         
++ facneffaclw   =  0.0                         gfacnudo      =  1.0                         gfacnudl      =  0.0                         
++ gfacnudlexp   =  1.0                         gfacnudw      =  0.0                         gfacnudlw     =  0.0                         
++ vsbnudo       =  0.0                         dvsbnudo      =  1.0                         vnsubo        =  0.0                         
++ nslpo         =  0.05                        dnsubo        =  0.03585                     dphibo        = '-0.077807*sg13g2_hv_pmos_dphibo'                                           
++ dphibl        =  '0.0055386*sg13g2_hv_pmos_dphibl'                                          dphiblexp     =  2.1893                      dphibw        = '-0.007913*sg13g2_hv_pmos_dphibw '                                          
++ dphiblw       =  '0.00055473*sg13g2_hv_pmos_dphiblw'                                        delvtaco      =  0.0                         delvtacl      =  0.0                         
++ delvtaclexp   =  1.0                         delvtacw      =  0.0                         delvtaclw     =  0.0                         
++ npo           =  1.092e+26                   npl           =  0.2188                      toxovo        =  '6.945e-09*sg13g2_hv_pmos_toxovo'                                          
++ toxovdo       =  2e-09                       lov           =  '3.471e-08 -((1-pre_layout)*2.4e-08 )'                                     lovd          =  0.0                         
++ novo          =  1.99e+26                    novdo         =  5e+25                       cto           = -0.006328                    
++ ctl           =  0.0                         ctlexp        =  1.0                         ctw           =  0.3006                      
++ ctlw          = -0.01196                     ctgo          =  0.0                         ctbo          =  0.0                         
++ stcto         =  1.0                         cfl           =  0.00045884                  cflexp        =  2.2055                      
++ cfw           =  0.45909                     cfbo          =  1.0                         cfdo          =  0.0                         
++ pscel         =  0.0                         pscelexp      =  2.0                         pscew         =  0.0                         
++ pscebo        =  0.0                         pscedo        =  0.0                         uo            =  0.018428                    
++ fbet1         =  0.15952                     fbet1w        = -2.1872                      lp1           =  9.9822e-08                  
++ lp1w          = -1.0871                      fbet2         = -2.7066                      lp2           =  5.8401e-08                  
++ betw1         = -0.097534                    betw2         =  0.022314                    wbet          =  7.9844e-10                  
++ stbeto        =  1.6489                      stbetl        =  0.029528                    stbetw        =  0.037078                    
++ stbetlw       =  0.046991                    mueo          =  '1.8162*sg13g2_hv_pmos_mueo'  muew          = -0.06367                     
++ stmueo        =  1.0816                      themuo        =  1.0324                      stthemuo      =  0.26337                     
++ cso           =  0.18648                     csl           =  '0.21903*sg13g2_hv_pmos_csl'  cslexp        =  2.0917                      
++ csw           =  0.0072837                   cslw          =  0.02                        stcso         =  2.0                         
++ thecso        =  2.0                         stthecso      =  0.0                         xcoro         =  0.001363                    
++ xcorl         =  8.0                         xcorw         =  0.0060537                   xcorlw        =  0.058951                    
++ stxcoro       = -6.939e-18                   fetao         =  1.2853                      rsw1          =  '1970.0*sg13g2_hv_pmos_rsw1'  
++ rsw2          = -0.057547                    strso         = -0.24812                     rsbo          =  0.074639                    
++ rsgo          =  '0.21144*sg13g2_hv_pmos_rsgo' thesato     =  '8.4917e-05*sg13g2_hv_pmos_thesato'        thesatl       =  '0.014*sg13g2_hv_pmos_thesatl'                                             
++ thesatlexp    =  2.395                       thesatw       =  '0.2*sg13g2_hv_pmos_thesatw'  thesatlw      = '-0.01*sg13g2_hv_pmos_thesatlw'                                             
++ stthesato     =  3.0405                      stthesatl     = -0.16001                     stthesatw     = -0.96988                     
++ stthesatlw    =  0.36213                     thesatbo      =  0.1                         thesatgo      =  0.6304                      
++ axo           =  16.822                      axl           =  3.0092                      alpl          =  0.0058454                   
++ alplexp       =  0.47562                     alpw          = -0.065973                    alp1l1        =  4.4409e-16                  
++ alp1lexp      =  1.347                       alp1l2        =  1.0                         alp1w         =  2.0                         
++ alp2l1        =  3.6779e-06                  alp2lexp      =  0.2531                      alp2l2        =  2.2204e-15                  
++ alp2w         =  0.9582                      vpo           =  1.8436e-06                  a1o           =  47.788                      
++ a1l           =  0.029145                    a1w           =  0.01435                     a2o           =  38.581                      
++ sta2o         = -0.0049931                   a3o           =  1.1753                      a3l           = -0.069795                    
++ a3w           =  0.0032538                   a4o           =  0.12593                     a4l           = -0.07                        
++ a4w           = -0.04811                     gcoo          =  0.0                         iginvlw       =  '0.0 *(1+0.0 /l)*(1+0.0 /w)'  
++ igovw         =  0.0                         igovdw        =  0.0                         stigo         =  2.0                         
++ gc2o          =  0.375                       gc3o          =  0.063                       chibo         =  3.1                         
++ agidlw        =  6e-10                       agidldw       =  0.0                         bgidlo        =  '6.656*sg13g2_hv_pmos_bgidlo' 
++ bgidldo       =  41.0                        stbgidlo      = -0.0049461                   stbgidldo     =  0.0                         
++ cgidlo        =  0.23693                     cgidldo       =  0.0                         cgbovl        = -4.669e-16                   
++ cfrdw         =  0.0                         fnto          =  1.0                         
++ fntexcl       =  0.0                         nfalw         =  1.3e+25                     nfblw         =  5289000000.0                
++ nfclw         =  2e-07                       efo           =  1.152                       lintnoi       =  2.5e-08                     
++ alpnoi        =  2.0                         wedge         =  1e-08                       wedgew        =  0.0                         
++ vfbedgeo      = -1.0                         stvfbedgeo    =  0.0005                      stvfbedgel    =  0.0                         
++ stvfbedgew    =  0.0                         stvfbedgelw   =  0.0                         dphibedgeo    =  0.0                         
++ dphibedgel    =  0.0                         dphibedgelexp =  1.0                         dphibedgew    =  0.0                         
++ dphibedgelw   =  0.0                         nsubedgeo     =  5e+23                       nsubedgel     =  0.0                         
++ nsubedgelexp                                               =  1.0                         nsubedgew     =  0.0                         nsubedgelw    =  0.0                         
++ ctedgeo       =  0.0                         ctedgel       =  0.0                         ctedgelexp    =  1.0                         
++ fbetedge      =  0.0                         lpedge        =  1e-08                       betedgew      =  0.0                         
++ stbetedgeo    =  1.0                         stbetedgel    =  0.0                         stbetedgew    =  0.0                         
++ stbetedgelw   =  0.0                         psceedgel     =  0.0                         psceedgelexp  =  2.0                         
++ psceedgew     =  0.0                         pscebedgeo    =  0.0                         pscededgeo    =  0.0                         
++ cfedgel       =  0.0                         cfedgelexp    =  2.0                         cfedgew       =  0.0                         
++ cfdedgeo      =  0.0                         cfbedgeo      =  0.0                         fntedgeo      =  1.0                         
++ nfaedgelw     =  8e+22                       nfbedgelw     =  30000000.0                  nfcedgelw     =  0.0                         
++ efedgeo       =  1.0                         saref         =  1e-06                       sbref         =  1e-06                       
++ wlod          =  0.0                         kuo           =  0.0                         kvsat         =  0.0                         
++ tkuo          =  0.0                         lkuo          =  0.0                         wkuo          =  0.0                         
++ pkuo          =  0.0                         llodkuo       =  0.0                         wlodkuo       =  0.0                         
++ kvtho         =  0.0                         lkvtho        =  0.0                         wkvtho        =  0.0                         
++ pkvtho        =  0.0                         llodvth       =  0.0                         wlodvth       =  0.0                         
++ stetao        =  0.0                         lodetao       =  1.0                         scref         =  1e-06                       
++ web           =  0.0                         wec           =  0.0                         kvthoweo      =  0.0                         
++ kvthowel      =  0.0                         kvthowew      =  0.0                         kvthowelw     =  0.0                         
++ kuoweo        =  0.0                         kuowel        =  0.0                         kuowew        =  0.0                         
++ kuowelw       =  0.0                         trj           =  21.0                        swjunexp      =  0.0                         
++ imax          =  0.0024527                   frev          =  1000.0                      cjorbot       =  '0.0008095*sg13g2_hv_pmos_cjorbot'                                         
++ cjorsti       =  '4.2583e-11*sg13g2_hv_pmos_cjorsti'                                      cjorgat       =  '3.1e-11*sg13g2_hv_pmos_cjorgat'  vbirbot       =  0.72606                     
++ vbirsti       =  0.69819                     vbirgat       =  1.199                       pbot          =  0.33078                     
++ psti          =  0.22409                     pgat          =  0.4474                      cjorbotd      =  0.001                       
++ cjorstid      =  1e-09                       cjorgatd      =  1e-09                       vbirbotd      =  1.0                         
++ vbirstid      =  1.0                         vbirgatd      =  1.0                         pbotd         =  0.5                         
++ pstid         =  0.5                         pgatd         =  0.5                         phigbot       =  1.0641                      
++ phigsti       =  1.3946                      phiggat       =  1.83                        idsatrbot     =  3.0606e-08                  
++ idsatrsti     =  3.6127e-15                  idsatrgat     =  0.0                         csrhbot       =  100.0                       
++ csrhsti       =  0.0001                      csrhgat       =  0.0001                      xjunsti       =  4.93e-08                    
++ xjungat       =  7.062e-07                   phigbotd      =  1.16                        phigstid      =  1.16                        
++ phiggatd      =  1.16                        idsatrbotd    =  1e-12                       idsatrstid    =  1e-18                       
++ idsatrgatd    =  1e-18                       csrhbotd      =  100.0                       csrhstid      =  0.0001                      
++ csrhgatd      =  0.0001                      xjunstid      =  1e-07                       xjungatd      =  1e-07                       
++ ctatbot       =  100.0                       ctatsti       =  0.0001                      ctatgat       =  0.0001                      
++ mefftatbot    =  0.25                        mefftatsti    =  0.25                        mefftatgat    =  0.25                        
++ ctatbotd      =  100.0                       ctatstid      =  0.0001                      ctatgatd      =  0.0001                      
++ mefftatbotd   =  0.25                        mefftatstid   =  0.25                        mefftatgatd   =  0.25                        
++ cbbtbot       =  1e-12                       cbbtsti       =  1e-21                       cbbtgat       =  1e-18                       
++ fbbtrbot      =  1000000000.0                fbbtrsti      =  1000000000.0                fbbtrgat      =  1000000000.0                
++ stfbbtbot     = -0.001                       stfbbtsti     = -0.001                       stfbbtgat     = -0.001                       
++ cbbtbotd      =  1e-12                       cbbtstid      =  1e-18                       cbbtgatd      =  1e-18                       
++ fbbtrbotd     =  1000000000.0                fbbtrstid     =  1000000000.0                fbbtrgatd     =  1000000000.0                
++ stfbbtbotd    = -0.001                       stfbbtstid    = -0.001                       stfbbtgatd    = -0.001                       
++ vbrbot        =  10.0                        vbrsti        =  10.0                        vbrgat        =  10.0                        
++ pbrbot        =  4.0                         pbrsti        =  4.0                         pbrgat        =  4.0                         
++ vbrbotd       =  10.0                        vbrstid       =  10.0                        vbrgatd       =  10.0                        
++ pbrbotd       =  4.0                         pbrstid       =  4.0                         pbrgatd       =  4.0                         
++ vjunref       =  2.5                         fjunq         =  0.03                        vjunrefd      =  2.5                         
++ fjunqd        =  0.03                        rint          =  0.0                         
++ rvpoly        =  0.0                         dlsil         =  0.0                         
++ rsh           =  0.0                         rshd          =  0.0                         
++ munqso        =  1.0                         
++ swnqs         =  'rfmode * 5.0'                cfrw          =  '(pre_layout * 0.0 + rfmode * (2.01e-17 + pre_layout * (ng>0 ? 3.5e-17 : 0)))/ng' 
++ rshg          =  'rfmode * 40.0'               rgo           =  'rfmode * 15.0'               
++ rbulko        =  'rfmode * 0.002 * ng/w'       rwello        =  'rfmode * 0.001 * ng/w'       
++ rjunso        =  'rfmode * 5000.0 * l/w'       rjundo        =  'rfmode * 5000.0 * l/w'       
+                
diff --git a/ihp-sg13g2/libs.tech/xyce/models/sg13g2_moshv_stat.lib b/ihp-sg13g2/libs.tech/xyce/models/sg13g2_moshv_stat.lib
new file mode 100644
index 00000000..b49b1bf1
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/models/sg13g2_moshv_stat.lib
@@ -0,0 +1,57 @@
+*#######################################################################
+*
+* Copyright 2023 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+*#######################################################################
+       
+* ngspice statistical parameters
+.param sg13g2_hv_nmos_vfbo        ='gauss(sg13g2_hv_nmos_vfbo_mm_norm,   0.004,  mc_ok)'
+.param sg13g2_hv_nmos_rsgo        ='gauss(sg13g2_hv_nmos_rsgo_norm,      1e-9,   mc_ok)'
+.param sg13g2_hv_nmos_rsw1        ='gauss(sg13g2_hv_nmos_rsw1_norm,      0.0001, mc_ok)'
+.param sg13g2_hv_nmos_mueo        ='gauss(sg13g2_hv_nmos_mueo_norm,      0.0335, mc_ok)'
+.param sg13g2_hv_nmos_dphibo      ='gauss(sg13g2_hv_nmos_dphibo_norm,    0.1503, mc_ok)'
+.param sg13g2_hv_nmos_dphibl      ='gauss(sg13g2_hv_nmos_dphibl_norm,    0.2052, mc_ok)'
+.param sg13g2_hv_nmos_dphibw      ='gauss(sg13g2_hv_nmos_dphibw_norm,    1e-9,   mc_ok)'
+.param sg13g2_hv_nmos_dphiblw     ='gauss(sg13g2_hv_nmos_dphiblw_norm,   0.0151, mc_ok)'
+.param sg13g2_hv_nmos_ctl         ='gauss(sg13g2_hv_nmos_ctl_norm,       1e-9,   mc_ok)'
+.param sg13g2_hv_nmos_thesato     ='gauss(sg13g2_hv_nmos_thesato_norm,   1e-9,   mc_ok)'
+.param sg13g2_hv_nmos_thesatl     ='gauss(sg13g2_hv_nmos_thesatl_norm,   0.0358, mc_ok)'
+.param sg13g2_hv_nmos_thesatw     ='gauss(sg13g2_hv_nmos_thesatw_norm,   1e-9,   mc_ok)'
+.param sg13g2_hv_nmos_thesatlw    ='gauss( sg13g2_hv_nmos_thesatlw_norm, 0.0353, mc_ok)'
+.param sg13g2_hv_nmos_toxo        ='gauss(sg13g2_hv_nmos_toxo_norm,      0.0133, mc_ok)'
+.param sg13g2_hv_nmos_toxovo      ='gauss(sg13g2_hv_nmos_toxovo_norm,    0.0133, mc_ok)'
+.param sg13g2_hv_nmos_cjorbot     ='gauss(sg13g2_hv_nmos_cjorbot_norm,   0.0267, mc_ok)'
+.param sg13g2_hv_nmos_cjorsti     ='gauss(sg13g2_hv_nmos_cjorsti_norm,   0.0267, mc_ok)'
+.param sg13g2_hv_nmos_cjorgat     ='gauss(sg13g2_hv_nmos_cjorgat_norm,   0.0267, mc_ok)'
+
+.param sg13g2_hv_pmos_vfbo_mm     ='gauss(sg13g2_hv_pmos_vfbo_mm_norm, 0.004, mc_ok)'
+.param sg13g2_hv_pmos_rsgo        ='gauss(sg13g2_hv_pmos_rsgo_norm,    0.4253, mc_ok)'
+.param sg13g2_hv_pmos_rsw1        ='gauss(sg13g2_hv_pmos_rsw1_norm,    1e-9,   mc_ok)'
+.param sg13g2_hv_pmos_mueo        ='gauss(sg13g2_hv_pmos_mueo_norm,    0.0014, mc_ok)'
+.param sg13g2_hv_pmos_dphibo      ='gauss(sg13g2_hv_pmos_dphibo_norm,  0.0572, mc_ok)'
+.param sg13g2_hv_pmos_dphibl      ='gauss(sg13g2_hv_pmos_dphibl_norm,  0.0672, mc_ok)'
+.param sg13g2_hv_pmos_dphibw      ='gauss(sg13g2_hv_pmos_dphibw_norm,  0.0183, mc_ok)'
+.param sg13g2_hv_pmos_dphiblw     ='gauss(sg13g2_hv_pmos_dphiblw_norm, 1.0138, mc_ok)'
+.param sg13g2_hv_pmos_bgidlo      ='gauss(sg13g2_hv_pmos_bgidlo_norm,  0.1538, mc_ok)'
+.param sg13g2_hv_pmos_thesato     ='gauss(sg13g2_hv_pmos_thesato_norm, 1e-9,   mc_ok)'
+.param sg13g2_hv_pmos_thesatl     ='gauss(sg13g2_hv_pmos_thesatl_norm, 0.0198, mc_ok)'
+.param sg13g2_hv_pmos_thesatw     ='gauss(sg13g2_hv_pmos_thesatw_norm, 0.4367, mc_ok)'
+.param sg13g2_hv_pmos_thesatlw    ='gauss(sg13g2_hv_pmos_thesatlw_norm,1e-9,   mc_ok)'
+.param sg13g2_hv_pmos_csl         ='gauss(sg13g2_hv_pmos_csl_norm,     1e-9,   mc_ok)'
+.param sg13g2_hv_pmos_toxo        ='gauss(sg13g2_hv_pmos_toxo_norm,    0.0133, mc_ok)'
+.param sg13g2_hv_pmos_toxovo      ='gauss(sg13g2_hv_pmos_toxovo_norm,  0.0133, mc_ok)'
+.param sg13g2_hv_pmos_cjorbot     ='gauss(sg13g2_hv_pmos_cjorbot_norm, 0.0267, mc_ok)'
+.param sg13g2_hv_pmos_cjorsti     ='gauss(sg13g2_hv_pmos_cjorsti_norm, 0.0267, mc_ok)'
+.param sg13g2_hv_pmos_cjorgat     ='gauss(sg13g2_hv_pmos_cjorgat_norm, 0.0267, mc_ok)'
diff --git a/ihp-sg13g2/libs.tech/xyce/models/sg13g2_moslv_mod.lib b/ihp-sg13g2/libs.tech/xyce/models/sg13g2_moslv_mod.lib
new file mode 100644
index 00000000..8039dc6f
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/models/sg13g2_moslv_mod.lib
@@ -0,0 +1,89 @@
+*******************************************************************************
+*                                                                             *
+* Library:      SG13G2_dev                                                    *
+* Technologies: SG13G2                                                        *
+*                                                                             *
+* Model:        PSP 103.6                                                     *
+* Revision:     200310                                                        *
+*                                                                             *
+*******************************************************************************
+*                                                                             *
+* Copyright 2023 IHP PDK Authors                                              *
+*                                                                             *
+* Licensed under the Apache License, Version 2.0 (the "License");             *
+* you may not use this file except in compliance with the License.            *
+* You may obtain a copy of the License at                                     *
+*                                                                             *
+*     https://www.apache.org/licenses/LICENSE-2.0                             *
+*                                                                             *
+* Unless required by applicable law or agreed to in writing, software         *
+* distributed under the License is distributed on an "AS IS" BASIS,           *
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.    *
+* See the License for the specific language governing permissions and         *
+* limitations under the License.                                              *
+*                                                                             *
+*******************************************************************************
+*******************************************************************************
+*                                                                             *
+*                                                                             *
+*              C O M M O N    SG 13  M O S     M O D E L S                    *
+*                                                                             *
+*                                                                             *
+*******************************************************************************
+*
+* NOTE: do not include this file directly in the netlist, use models.typ, .bcs or .wcs only
+*
+*
+*
+*******************************************************************************
+* variable C section
+*******************************************************************************
+
+
+
+*******************************************************************************
+* MOS transistor section
+*******************************************************************************
+
+
+
+* MOS-Subckt with D/S-overlap possibility
+*
+*       z1              z2            z1
+*   ----------------------------------------
+*   |          |   |         |   |         |
+*   |    S     | G |   D     | G |    S    |  w/ng, >=0.15u
+*   |          |   |         |   |         |
+*   ----------------------------------------
+*
+*  z1=0.34u, z2=0.38u
+*
+* Parameters as,ad,ps,pd are calculated automatically, if <= 0
+*
+*
+
+.subckt sg13_lv_nmos d g s b
++ w=0.35u l=0.34u ng=1 m=1 as=0 ad=0 pd=0 ps=0 trise=0 z1=0.34e-6 z2=0.38e-6 wmin=0.15e-6 rfmode=0 pre_layout=1
+* if as = 0, calculate value, else take it
+* if as is given externally, no adjustment for ng is done! -> must be done in the extractor
+* if ng>1 and as=0 (in schematic) recalculate!
+
+* include the model parameters
+.include sg13g2_moslv_parm.lib
+
+YPSP103_VA M1 d g s b sg13g2_lv_nmos_psp w='w/ng' l=l as='as/ng' ad='ad/ng' pd='pd/ng' ps='ps/ng' mult='ng*m'
++ dta=trise
++ ngcon=2
+.ends
+
+
+.subckt sg13_lv_pmos d g s b
++ w=0.35u l=0.28u ng=1 m=1 as=0 ad=0 pd=0 ps=0 trise=0 z1=0.34e-6 z2=0.38e-6 wmin=0.15e-6 rfmode=0 pre_layout=1
+
+* include the model parameters
+.include sg13g2_moslv_parm.lib
+
+YPSP103_VA M1 d g s b sg13g2_lv_pmos_psp w='w/ng' l=l as='as/ng' ad='ad/ng' pd='pd/ng' ps='ps/ng' mult='ng*m'
++ dta=trise
++ ngcon=2
+.ends
diff --git a/ihp-sg13g2/libs.tech/xyce/models/sg13g2_moslv_parm.lib b/ihp-sg13g2/libs.tech/xyce/models/sg13g2_moslv_parm.lib
new file mode 100644
index 00000000..dc46515d
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/models/sg13g2_moslv_parm.lib
@@ -0,0 +1,340 @@
+*******************************************************************************
+*                                                                             *
+* Library:      SG13G2_dev                                                    *
+* Technologies: SG13G2                                                        *
+*                                                                             *
+* Model:        PSP 103.6                                                     *
+* Revision:     200310                                                        *
+*                                                                             *
+*******************************************************************************
+*                                                                             *
+* Copyright 2023 IHP PDK Authors                                              *
+*                                                                             *
+* Licensed under the Apache License, Version 2.0 (the "License");             *
+* you may not use this file except in compliance with the License.            *
+* You may obtain a copy of the License at                                     *
+*                                                                             *
+*     https://www.apache.org/licenses/LICENSE-2.0                             *
+*                                                                             *
+* Unless required by applicable law or agreed to in writing, software         *
+* distributed under the License is distributed on an "AS IS" BASIS,           *
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.    *
+* See the License for the specific language governing permissions and         *
+* limitations under the License.                                              *
+*                                                                             *
+*******************************************************************************
+*
+*
+*******************************************************************************
+*                                                                             *
+*                                                                             *
+*                      M O D E L  P A R A M E T E R S                         *
+*                                                                             *
+*                                                                             *
+*******************************************************************************
+*
+*
+*
+*
+*
+*
+*
+*******************************************************************************
+*
+* Low Voltage (lv) MOS Transistors
+*
+* Model:                                PSP 103.6
+* Date:                                 10.03.2020
+* Lot:                                  EDJ809
+* WAFER:                                06
+* CHIP Nr:                              x=3, y=9
+* Device:                               SG13G2
+* Maximum drain-source voltage:         1.5
+* Measurement data:
+* Nom. Temperature  (TNOM):             27 grd C
+* Meas. Temperature (TEMP):             27 grd C
+* Valid range for model:                L = (0.13 - 10)um
+*                                       W = (0.15 - 10)um
+*
+*******************************************************************************
+
+.model sg13g2_lv_nmos_psp psp103_va          type          =  +1
++ tr            =  27.0                        dta           =  0.0
++ swgeo         =  1.0                         swigate       =  1.0                         swimpact      =  1.0
++ swgidl        =  1.0                         swjuncap      =  3.0                         swjunasym     =  0.0
++ swnud         =  0.0                         swedge        =  0.0                         swdelvtac     =  0.0
++ swign         =  1.0                         qmc           =  1.0                         lvaro         =  0.0
++ lvarl         =  0.0                         lvarw         =  0.0                         lap           =  2.9423e-08
++ wvaro         =  0.0                         wvarl         =  0.0                         wvarw         =  0.0
++ wot           = -1e-08                       dlq           = '-1.3721e-08 -((1-pre_layout)*2e-08 )+rfmode*(-1.5368e-08 +(ng<3 ? 4e-08 : 0) )' dwq           = '-1e-08 +rfmode*(4.8062e-07 )'
++ vfbo          = '-0.94312*(1+(sg13g2_lv_nmos_vfbo_mm-1)/sqrt(m*l*w*1e12)) '             vfbl          =  0.013965                    vfbw          = -0.027122
++ vfblw         =  0.0044814                   stvfbo        =  0.00068785                  stvfbl        =  2.8624e-05
++ stvfbw        = -1.8689e-05                  stvfblw       =  5.1435e-07                  st2vfbo       =  0.0
++ toxo          =  '2.2404e-09*sg13g2_lv_nmos_toxo'                                           epsroxo       =  3.9                         nsubo         =  1.0483e+23
++ nsubw         =  7.5708                      wseg          =  5.3426e-06                  npck          =  1.743e+21
++ npckw         = -1.484                       wsegp         =  1e-08                       lpck          =  3.171e-07
++ lpckw         =  0.0                         fol1          = -0.0091066                   fol2          =  0.0021139
++ facneffaco    =  1.0                         facneffacl    =  0.0                         facneffacw    =  0.0
++ facneffaclw   =  0.0                         gfacnudo      =  1.0                         gfacnudl      =  0.0
++ gfacnudlexp   =  1.0                         gfacnudw      =  0.0                         gfacnudlw     =  0.0
++ vsbnudo       =  0.0                         dvsbnudo      =  1.0                         vnsubo        =  0.0
++ nslpo         =  0.05                        dnsubo        =  4.4409e-16                  dphibo        = '-0.25737*sg13g2_lv_nmos_dphibo'
++ dphibl        =  '0.24027*sg13g2_lv_nmos_dphibl'                                            dphiblexp     =  0.068979                    dphibw        =  '0.0168*sg13g2_lv_nmos_dphibw'
++ dphiblw       = '-0.0036959*sg13g2_lv_nmos_dphiblw'                                         delvtaco      =  0.0                         delvtacl      =  0.0
++ delvtaclexp   =  1.0                         delvtacw      =  0.0                         delvtaclw     =  0.0
++ npo           =  4.6457e+26                  npl           =  0.0                         toxovo        =  '2.2404e-09*sg13g2_lv_nmos_toxovo'
++ toxovdo       =  2e-09                       lov           =  '2.9423e-08 -((1-pre_layout)*9e-09 )'                                      lovd          =  0.0
++ novo          =  3.5714e+25                  novdo         =  5e+25                       cto           =  0.054556
++ ctl           =  '0.015058*sg13g2_lv_nmos_ctl' ctlexp        =  0.85719                     ctw           = -0.096878
++ ctlw          =  0.008767                    ctgo          =  0.0                         ctbo          =  0.0
++ stcto         =  1.0                         cfl           =  8.9001e-08                  cflexp        =  3.9688
++ cfw           = -0.17956                     cfbo          =  0.6952                      cfdo          =  0.0
++ pscel         =  0.0                         pscelexp      =  2.0                         pscew         =  0.0
++ pscebo        =  0.0                         pscedo        =  0.0                         uo            =  0.045582
++ fbet1         =  12.168                      fbet1w        =  0.38931                     lp1           =  5.1674e-09
++ lp1w          = -0.1544                      fbet2         = -2.302                       lp2           =  1.9441e-08
++ betw1         = -0.020925                    betw2         =  0.0087681                   wbet          =  5.9171e-08
++ stbeto        =  2.4165                      stbetl        = -0.036997                    stbetw        =  0.0046613
++ stbetlw       =  0.0062828                   mueo          =  0.77874                     muew          =  '0.030943*sg13g2_lv_nmos_muew '
++ stmueo        =  0.98971                     themuo        =  '2.0546*sg13g2_lv_nmos_themuo'                                             stthemuo      =  4.441e-15
++ cso           =  0.3164                      csl           =  0.12341                     cslexp        =  1.1398
++ csw           =  0.19805                     cslw          = -0.00044184                  stcso         =  2.9406
++ thecso        =  1.1822                      stthecso      =  0.0                         xcoro         =  0.053934
++ xcorl         = -0.11292                     xcorw         = -0.10913                     xcorlw        = -0.014959
++ stxcoro       =  2.0                         fetao         =  1.0                         rsw1          =  '130.0*sg13g2_lv_nmos_rsw1'
++ rsw2          =  0.0                         strso         = -0.49693                     rsbo          = -0.099725
++ rsgo          =  0.074518                    thesato       =  0.39843                     thesatl       =  '0.43388*sg13g2_lv_nmos_thesatl'
++ thesatlexp    =  1.0316                      thesatw       =  '0.12825*sg13g2_lv_nmos_thesatw'                                           thesatlw      = '-0.0044*sg13g2_lv_nmos_thesatlw'
++ stthesato     =  2.7784                      stthesatl     = -0.091893                    stthesatw     = -0.065908
++ stthesatlw    =  0.01292                     thesatbo      =  0.08213                     thesatgo      =  0.1146
++ axo           =  13.547                      axl           =  1.0186                      alpl          =  0.0088345
++ alplexp       =  0.68143                     alpw          =  1.0825                      alp1l1        =  0.021138
++ alp1lexp      =  0.25                        alp1l2        =  0.04044                     alp1w         = -0.077622
++ alp2l1        =  2.6817                      alp2lexp      =  0.25                        alp2l2        =  0.0
++ alp2w         = -0.13012                     vpo           =  0.32224                     a1o           =  6.239
++ a1l           =  0.052176                    a1w           = -0.052179                    a2o           =  17.75
++ sta2o         =  0.068723                    a3o           =  0.708                       a3l           = -0.045201
++ a3w           = -0.041992                    a4o           =  0.04649                     a4l           =  0.0
++ a4w           =  1.581e-16                   gcoo          =  10.0                        iginvlw       =  '121290.0 *(1+2.4761e-07 /l)*(1+-2.1167e-08 /w)'
++ igovw         =  3026.8                      igovdw        =  0.0                         stigo         =  2.9949
++ gc2o          =  0.8413                      gc3o          = -0.4698                      chibo         =  3.1
++ agidlw        =  0.001262                    agidldw       =  0.0                         bgidlo        =  19.92
++ bgidldo       =  41.0                        stbgidlo      =  0.0                         stbgidldo     =  0.0
++ cgidlo        =  0.06641                     cgidldo       =  0.0                         cgbovl        =  4.4409e-28
++ cfrdw         =  0.0                         fnto          =  1.0
++ fntexcl       =  0.0                         nfalw         =  7.616e+25                   nfblw         =  1026000000.0
++ nfclw         = -5e-08                       efo           =  1.0                         lintnoi       = -3.7e-08
++ alpnoi        =  1.869                       wedge         =  1e-08                       wedgew        =  0.0
++ vfbedgeo      = -1.0                         stvfbedgeo    =  0.0005                      stvfbedgel    =  0.0
++ stvfbedgew    =  0.0                         stvfbedgelw   =  0.0                         dphibedgeo    =  0.0
++ dphibedgel    =  0.0                         dphibedgelexp =  1.0                         dphibedgew    =  0.0
++ dphibedgelw   =  0.0                         nsubedgeo     =  5e+23                       nsubedgel     =  0.0
++ nsubedgelexp                                               =  1.0                         nsubedgew     =  0.0                         nsubedgelw    =  0.0
++ ctedgeo       =  0.0                         ctedgel       =  0.0                         ctedgelexp    =  1.0
++ fbetedge      =  0.0                         lpedge        =  1e-08                       betedgew      =  0.0
++ stbetedgeo    =  1.0                         stbetedgel    =  0.0                         stbetedgew    =  0.0
++ stbetedgelw   =  0.0                         psceedgel     =  0.0                         psceedgelexp  =  2.0
++ psceedgew     =  0.0                         pscebedgeo    =  0.0                         pscededgeo    =  0.0
++ cfedgel       =  0.0                         cfedgelexp    =  2.0                         cfedgew       =  0.0
++ cfdedgeo      =  0.0                         cfbedgeo      =  0.0                         fntedgeo      =  1.0
++ nfaedgelw     =  8e+22                       nfbedgelw     =  30000000.0                  nfcedgelw     =  0.0
++ efedgeo       =  1.0                         saref         =  1e-06                       sbref         =  1e-06
++ wlod          =  0.0                         kuo           =  0.0                         kvsat         =  0.0
++ tkuo          =  0.0                         lkuo          =  0.0                         wkuo          =  0.0
++ pkuo          =  0.0                         llodkuo       =  0.0                         wlodkuo       =  0.0
++ kvtho         =  0.0                         lkvtho        =  0.0                         wkvtho        =  0.0
++ pkvtho        =  0.0                         llodvth       =  0.0                         wlodvth       =  0.0
++ stetao        =  0.0                         lodetao       =  1.0                         scref         =  1e-06
++ web           =  0.0                         wec           =  0.0                         kvthoweo      =  0.0
++ kvthowel      =  0.0                         kvthowew      =  0.0                         kvthowelw     =  0.0
++ kuoweo        =  0.0                         kuowel        =  0.0                         kuowew        =  0.0
++ kuowelw       =  0.0                         trj           =  21.0                        swjunexp      =  0.0
++ imax          =  0.0015358                   frev          =  1000.0                      cjorbot       =  '0.00097636*sg13g2_lv_nmos_cjorbot'
++ cjorsti       =  '2.5279e-11*sg13g2_lv_nmos_cjorsti'                                        cjorgat       =  '3e-11*sg13g2_lv_nmos_cjorgat'                                             vbirbot       =  0.70829
++ vbirsti       =  0.79368                     vbirgat       =  2.0                         pbot          =  0.31309
++ psti          =  0.27362                     pgat          =  0.5424                      cjorbotd      =  0.001
++ cjorstid      =  1e-09                       cjorgatd      =  1e-09                       vbirbotd      =  1.0
++ vbirstid      =  1.0                         vbirgatd      =  1.0                         pbotd         =  0.5
++ pstid         =  0.5                         pgatd         =  0.5                         phigbot       =  1.1136
++ phigsti       =  1.3844                      phiggat       =  1.16                        idsatrbot     =  6.3087e-08
++ idsatrsti     =  1.9278e-15                  idsatrgat     =  0.0                         csrhbot       =  100.0
++ csrhsti       =  0.0001                      csrhgat       =  6.682e-06                   xjunsti       =  1.5783e-07
++ xjungat       =  0.0001                      phigbotd      =  1.16                        phigstid      =  1.16
++ phiggatd      =  1.16                        idsatrbotd    =  1e-12                       idsatrstid    =  1e-18
++ idsatrgatd    =  1e-18                       csrhbotd      =  100.0                       csrhstid      =  0.0001
++ csrhgatd      =  0.0001                      xjunstid      =  1e-07                       xjungatd      =  1e-07
++ ctatbot       =  100.0                       ctatsti       =  0.0001                      ctatgat       =  0.0001
++ mefftatbot    =  5.204                       mefftatsti    =  3.364                       mefftatgat    =  0.25
++ ctatbotd      =  100.0                       ctatstid      =  0.0001                      ctatgatd      =  0.0001
++ mefftatbotd   =  0.25                        mefftatstid   =  0.25                        mefftatgatd   =  0.25
++ cbbtbot       =  1e-12                       cbbtsti       =  1e-21                       cbbtgat       =  1e-18
++ fbbtrbot      =  1000000000.0                fbbtrsti      =  1000000000.0                fbbtrgat      =  1000000000.0
++ stfbbtbot     = -0.001                       stfbbtsti     = -0.001                       stfbbtgat     = -0.001
++ cbbtbotd      =  1e-12                       cbbtstid      =  1e-18                       cbbtgatd      =  1e-18
++ fbbtrbotd     =  1000000000.0                fbbtrstid     =  1000000000.0                fbbtrgatd     =  1000000000.0
++ stfbbtbotd    = -0.001                       stfbbtstid    = -0.001                       stfbbtgatd    = -0.001
++ vbrbot        =  10.0                        vbrsti        =  10.0                        vbrgat        =  10.0
++ pbrbot        =  4.0                         pbrsti        =  4.0                         pbrgat        =  4.0
++ vbrbotd       =  10.0                        vbrstid       =  10.0                        vbrgatd       =  10.0
++ pbrbotd       =  4.0                         pbrstid       =  4.0                         pbrgatd       =  4.0
++ vjunref       =  2.5                         fjunq         =  0.03                        vjunrefd      =  2.5
++ fjunqd        =  0.03                        rint          =  1.3025e-11
++ rvpoly        =  0.0                         dlsil         =  0.0
++ rsh           =  0.0                         rshd          =  0.0
++ munqso        =  1.0
++ swnqs         =  'rfmode * 5.0'                cfrw          =  '((1-rfmode)*2e-16 + rfmode * (1e-18 + pre_layout * (ng>0 ? 3.8525e-17 : 0)))/ng'
++ rshg          =  'rfmode * 3.0'                rgo           =  'rfmode * 40.0'
++ rbulko        =  'rfmode * 0.002 * ng/w'       rwello        =  'rfmode * 0.002 * ng/w'
++ rjunso        =  'rfmode * 5000.0 * l/w'       rjundo        =  'rfmode * 5000.0 * l/w'
+
+*******************************************************************************
+*
+* Low Voltage (lv) MOS Transistors
+*
+* Model:                                PSP 103.6
+* Date:                                 10.03.2020
+* Lot:                                  EDJ809
+* WAFER:                                06
+* CHIP Nr:                              x=3, y=9
+* Device:                               SG13G2
+* Maximum drain-source voltage:         1.5
+* Measurement data:
+* Nom. Temperature  (TNOM):             27 grd C
+* Meas. Temperature (TEMP):             27 grd C
+* Valid range for model:                L = (0.13 - 10)um
+*                                       W = (0.15 - 10)um
+*
+* semimod changes:
+* - change parameter rint from 1.3323e-26 to 1e-12
+*******************************************************************************
+
+.model sg13g2_lv_pmos_psp psp103_va             type          =  -1
++ tr            =  27.0                        dta           =  0.0
++ swgeo         =  1.0                         swigate       =  1.0                         swimpact      =  1.0
++ swgidl        =  1.0                         swjuncap      =  3.0                         swjunasym     =  0.0
++ swnud         =  0.0                         swedge        =  0.0                         swdelvtac     =  0.0
++ swign         =  1.0                         qmc           =  1.0                         lvaro         =  9.695e-08
++ lvarl         = -0.03438                     lvarw         =  0.0                         lap           =  2.5254e-08
++ wvaro         =  0.0                         wvarl         =  0.0                         wvarw         =  0.0
++ wot           =  1.5e-08                     dlq           = '-9.5922e-08 -((1-pre_layout)*3e-08 )+rfmode*(-2e-08 +(ng<3 ? 3.3917e-08 : 0) )' dwq           =  '1.5e-08 +rfmode*(4.7599e-07 )'
++ vfbo          = '-0.88703*(1+(sg13g2_lv_pmos_vfbo_mm-1)/sqrt(m*l*w*1e12))'              vfbl          =  0.0089886                   vfbw          =  0.0071805
++ vfblw         =  0.004075                    stvfbo        =  0.00075111                  stvfbl        =  2.4487e-06
++ stvfbw        =  6.217e-06                   stvfblw       =  2.2668e-07                  st2vfbo       =  0.0
++ toxo          =  '1.9704e-09*sg13g2_lv_pmos_toxo'                                           epsroxo       =  3.9                         nsubo         =  4.6011e+23
++ nsubw         = -0.013639                    wseg          =  1.058e-08                   npck          =  5.7416e+24
++ npckw         = -1.0                         wsegp         =  1e-10                       lpck          =  1.1576e-10
++ lpckw         = -0.022414                    fol1          = -0.0081173                   fol2          =  0.0081347
++ facneffaco    =  1.0                         facneffacl    =  0.0                         facneffacw    =  0.0
++ facneffaclw   =  0.0                         gfacnudo      =  1.0                         gfacnudl      =  0.0
++ gfacnudlexp   =  1.0                         gfacnudw      =  0.0                         gfacnudlw     =  0.0
++ vsbnudo       =  0.0                         dvsbnudo      =  1.0                         vnsubo        =  0.0
++ nslpo         =  0.05                        dnsubo        =  0.039707                    dphibo        = '-0.099209*sg13g2_lv_pmos_dphibo'
++ dphibl        =  '0.00020745*sg13g2_lv_pmos_dphibl'                                         dphiblexp     =  2.9957                      dphibw        = '-0.00069395*sg13g2_lv_pmos_dphibw'
++ dphiblw       = '-0.0030829*sg13g2_lv_pmos_dphiblw'                                         delvtaco      =  0.0                         delvtacl      =  0.0
++ delvtaclexp   =  1.0                         delvtacw      =  0.0                         delvtaclw     =  0.0
++ npo           =  1.2699e+26                  npl           = -0.095923                    toxovo        =  '1.9704e-09*sg13g2_lv_pmos_toxovo'
++ toxovdo       =  2e-09                       lov           =  '2.5254e-08 -((1-pre_layout)*8.85e-09 ) '                                  lovd          =  0.0
++ novo          =  3.104e+25                   novdo         =  5e+25                       cto           =  1.1814e-05
++ ctl           =  '0.0069387*sg13g2_lv_pmos_ctl'                                             ctlexp        =  1.4316                      ctw           =  0.36122
++ ctlw          = -0.014902                    ctgo          =  0.0                         ctbo          =  0.0
++ stcto         =  1.0                         cfl           =  0.00011247                  cflexp        =  3.0355
++ cfw           = -0.012199                    cfbo          =  0.57877                     cfdo          =  0.0
++ pscel         =  0.0                         pscelexp      =  2.0                         pscew         =  0.0
++ pscebo        =  0.0                         pscedo        =  0.0                         uo            =  0.017232
++ fbet1         = -0.2152                      fbet1w        = -0.065541                    lp1           =  0.00019766
++ lp1w          =  0.0                         fbet2         = -6.171                       lp2           =  1.2564e-08
++ betw1         = -0.3268                      betw2         =  0.060181                    wbet          =  5.424e-10
++ stbeto        =  1.6974                      stbetl        = -0.037605                    stbetw        = -0.0083384
++ stbetlw       =  0.0013663                   mueo          =  2.3326                      muew          = '-0.067414*sg13g2_lv_pmos_muew'
++ stmueo        =  0.84805                     themuo        =  '1.3169*sg13g2_lv_pmos_themuo'                                             stthemuo      =  4.441e-15
++ cso           =  0.94214                     csl           =  0.34682                     cslexp        =  1.5813
++ csw           = -0.11045                     cslw          =  0.014762                    stcso         =  1.0269
++ thecso        =  1.4566                      stthecso      =  0.0                         xcoro         =  0.092591
++ xcorl         =  0.11698                     xcorw         = -0.095907                    xcorlw        =  0.029574
++ stxcoro       =  2.7756e-17                  fetao         =  1.0                         rsw1          =  '697.38*sg13g2_lv_pmos_rsw1'
++ rsw2          = -0.088444                    strso         = -0.3508                      rsbo          =  0.06
++ rsgo          =  0.495                       thesato       =  0.099164                    thesatl       =  '0.010142*sg13g2_lv_pmos_thesatl'
++ thesatlexp    =  2.4434                      thesatw       = '-0.13745*sg13g2_lv_pmos_thesatw'                                           thesatlw      = '-0.103*sg13g2_lv_pmos_thesatlw'
++ stthesato     =  12.733                      stthesatl     = -1.9651                      stthesatw     = -0.047465
++ stthesatlw    =  0.07117                     thesatbo      =  0.0                         thesatgo      =  0.0
++ axo           =  8.1825                      axl           =  0.58095                     alpl          =  0.0047346
++ alplexp       =  0.8468                      alpw          = -0.21042                     alp1l1        =  0.0040221
++ alp1lexp      =  0.6408                      alp1l2        =  1.611e-08                   alp1w         = -0.057981
++ alp2l1        =  0.005286                    alp2lexp      =  0.25                        alp2l2        =  0.0
++ alp2w         =  0.063581                    vpo           =  7.3803e-06                  a1o           =  0.0001107
++ a1l           =  5.741                       a1w           =  5.78                        a2o           =  13.33
++ sta2o         =  2.0                         a3o           =  1.526                       a3l           = -0.08391
++ a3w           = -0.004911                    a4o           = -0.005545                    a4l           =  0.2771
++ a4w           =  0.7101                      gcoo          =  0.01231                     iginvlw       =  '4880.4 *(1+-5.803e-09 /l)*(1+5.1659e-08 /w)'
++ igovw         =  1327.0                      igovdw        =  0.0                         stigo         =  2.3506
++ gc2o          =  0.54762                     gc3o          = -0.29543                     chibo         =  3.1
++ agidlw        =  7.371e-05                   agidldw       =  0.0                         bgidlo        =  15.12
++ bgidldo       =  41.0                        stbgidlo      = -0.0014941                   stbgidldo     =  0.0
++ cgidlo        =  0.02068                     cgidldo       =  0.0                         cgbovl        =  2.186e-17
++ cfrdw         =  0.0                         fnto          =  1.85
++ fntexcl       =  0.0                         nfalw         =  2.209e+26                   nfblw         =  572300000.0
++ nfclw         =  5.641e-07                   efo           =  1.0                         lintnoi       =  1e-08
++ alpnoi        =  2.118                       wedge         =  1e-08                       wedgew        =  0.0
++ vfbedgeo      = -1.0                         stvfbedgeo    =  0.0005                      stvfbedgel    =  0.0
++ stvfbedgew    =  0.0                         stvfbedgelw   =  0.0                         dphibedgeo    =  0.0
++ dphibedgel    =  0.0                         dphibedgelexp =  1.0                         dphibedgew    =  0.0
++ dphibedgelw   =  0.0                         nsubedgeo     =  5e+23                       nsubedgel     =  0.0
++ nsubedgelexp                                               =  1.0                         nsubedgew     =  0.0                         nsubedgelw    =  0.0
++ ctedgeo       =  0.0                         ctedgel       =  0.0                         ctedgelexp    =  1.0
++ fbetedge      =  0.0                         lpedge        =  1e-08                       betedgew      =  0.0
++ stbetedgeo    =  1.0                         stbetedgel    =  0.0                         stbetedgew    =  0.0
++ stbetedgelw   =  0.0                         psceedgel     =  0.0                         psceedgelexp  =  2.0
++ psceedgew     =  0.0                         pscebedgeo    =  0.0                         pscededgeo    =  0.0
++ cfedgel       =  0.0                         cfedgelexp    =  2.0                         cfedgew       =  0.0
++ cfdedgeo      =  0.0                         cfbedgeo      =  0.0                         fntedgeo      =  1.0
++ nfaedgelw     =  8e+22                       nfbedgelw     =  30000000.0                  nfcedgelw     =  0.0
++ efedgeo       =  1.0                         saref         =  1e-06                       sbref         =  1e-06
++ wlod          =  0.0                         kuo           =  0.0                         kvsat         =  0.0
++ tkuo          =  0.0                         lkuo          =  0.0                         wkuo          =  0.0
++ pkuo          =  0.0                         llodkuo       =  0.0                         wlodkuo       =  0.0
++ kvtho         =  0.0                         lkvtho        =  0.0                         wkvtho        =  0.0
++ pkvtho        =  0.0                         llodvth       =  0.0                         wlodvth       =  0.0
++ stetao        =  0.0                         lodetao       =  1.0                         scref         =  1e-06
++ web           =  0.0                         wec           =  0.0                         kvthoweo      =  0.0
++ kvthowel      =  0.0                         kvthowew      =  0.0                         kvthowelw     =  0.0
++ kuoweo        =  0.0                         kuowel        =  0.0                         kuowew        =  0.0
++ kuowelw       =  0.0                         trj           =  21.0                        swjunexp      =  0.0
++ imax          =  0.0016551                   frev          =  1000.0                      cjorbot       =  '0.00086306*sg13g2_lv_pmos_cjorbot'
++ cjorsti       =  '3.1915e-11*sg13g2_lv_pmos_cjorsti'                                        cjorgat       =  '2.7474e-11*sg13g2_lv_pmos_cjorgat'                                        vbirbot       =  0.7686
++ vbirsti       =  1.7036                      vbirgat       =  1.399                       pbot          =  0.3618
++ psti          =  0.2548                      pgat          =  0.6475                      cjorbotd      =  0.001
++ cjorstid      =  1e-09                       cjorgatd      =  1e-09                       vbirbotd      =  1.0
++ vbirstid      =  1.0                         vbirgatd      =  1.0                         pbotd         =  0.5
++ pstid         =  0.5                         pgatd         =  0.5                         phigbot       =  1.204
++ phigsti       =  0.8186                      phiggat       =  1.65                        idsatrbot     =  2.6746e-08
++ idsatrsti     =  1.1115e-15                  idsatrgat     =  0.0                         csrhbot       =  100.0
++ csrhsti       =  0.0001                      csrhgat       =  0.0001                      xjunsti       =  6.292e-08
++ xjungat       =  9.105e-05                   phigbotd      =  1.16                        phigstid      =  1.16
++ phiggatd      =  1.16                        idsatrbotd    =  1e-12                       idsatrstid    =  1e-18
++ idsatrgatd    =  1e-18                       csrhbotd      =  100.0                       csrhstid      =  0.0001
++ csrhgatd      =  0.0001                      xjunstid      =  1e-07                       xjungatd      =  1e-07
++ ctatbot       =  100.0                       ctatsti       =  0.0001                      ctatgat       =  0.0001
++ mefftatbot    =  10.0                        mefftatsti    =  4.363                       mefftatgat    =  0.25
++ ctatbotd      =  100.0                       ctatstid      =  0.0001                      ctatgatd      =  0.0001
++ mefftatbotd   =  0.25                        mefftatstid   =  0.25                        mefftatgatd   =  0.25
++ cbbtbot       =  1e-12                       cbbtsti       =  1e-21                       cbbtgat       =  1e-18
++ fbbtrbot      =  1000000000.0                fbbtrsti      =  1000000000.0                fbbtrgat      =  1000000000.0
++ stfbbtbot     = -0.001                       stfbbtsti     = -0.001                       stfbbtgat     = -0.001
++ cbbtbotd      =  1e-12                       cbbtstid      =  1e-18                       cbbtgatd      =  1e-18
++ fbbtrbotd     =  1000000000.0                fbbtrstid     =  1000000000.0                fbbtrgatd     =  1000000000.0
++ stfbbtbotd    = -0.001                       stfbbtstid    = -0.001                       stfbbtgatd    = -0.001
++ vbrbot        =  10.0                        vbrsti        =  10.0                        vbrgat        =  10.0
++ pbrbot        =  4.0                         pbrsti        =  4.0                         pbrgat        =  4.0
++ vbrbotd       =  10.0                        vbrstid       =  10.0                        vbrgatd       =  10.0
++ pbrbotd       =  4.0                         pbrstid       =  4.0                         pbrgatd       =  4.0
++ vjunref       =  2.5                         fjunq         =  0.03                        vjunrefd      =  2.5
++ fjunqd        =  0.03                        rint          =  1e-12
++ rvpoly        =  0.0                         dlsil         =  0.0
++ rsh           =  0.0                         rshd          =  0.0
++ munqso        =  1.0
++ swnqs         =  'rfmode * 5.0'                cfrw          =  '(1e-16 + rfmode * (1e-18 + pre_layout * (ng>0 ? 1.2382e-16 : 0)))/ng'
++ rshg          =  'rfmode * 20.0'               rgo           =  'rfmode * 22.0'
++ rbulko        =  'rfmode * 0.002 * ng/w'       rwello        =  'rfmode * 0.001 * ng/w'
++ rjunso        =  'rfmode * 5000.0 * l/w'       rjundo        =  'rfmode * 5000.0 * l/w'
+
+
diff --git a/ihp-sg13g2/libs.tech/xyce/models/sg13g2_moslv_stat.lib b/ihp-sg13g2/libs.tech/xyce/models/sg13g2_moslv_stat.lib
new file mode 100644
index 00000000..26366748
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/xyce/models/sg13g2_moslv_stat.lib
@@ -0,0 +1,55 @@
+*#######################################################################
+*
+* Copyright 2023 IHP PDK Authors
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*    https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+*#######################################################################
+
+* ngspice statistical parameters
+.param sg13g2_lv_nmos_vfbo     ='gauss(sg13g2_lv_nmos_vfbo_norm ,    0.01,   mc_ok)'
+.param sg13g2_lv_nmos_toxo     ='gauss(sg13g2_lv_nmos_toxo_norm,     0.0133, mc_ok)'
+.param sg13g2_lv_nmos_dphibo   ='gauss(sg13g2_lv_nmos_dphibo_norm,   0.0656, mc_ok)'
+.param sg13g2_lv_nmos_dphibl   ='gauss(sg13g2_lv_nmos_dphibl_norm,   0.1135, mc_ok)'
+.param sg13g2_lv_nmos_dphibw   ='gauss(sg13g2_lv_nmos_dphibw_norm,   0.1197, mc_ok)'
+.param sg13g2_lv_nmos_dphiblw  ='gauss(sg13g2_lv_nmos_dphiblw_norm,  0.0135, mc_ok)'
+.param sg13g2_lv_nmos_toxovo   ='gauss(sg13g2_lv_nmos_toxovo_norm,   0.0133, mc_ok)'
+.param sg13g2_lv_nmos_ctl      ='gauss(sg13g2_lv_nmos_ctl_norm,      0.1562, mc_ok)'
+.param sg13g2_lv_nmos_muew     ='gauss(sg13g2_lv_nmos_muew_norm,     0.032,  mc_ok)'
+.param sg13g2_lv_nmos_themuo   ='gauss(sg13g2_lv_nmos_themuo_norm,   0.0026, mc_ok)'
+.param sg13g2_lv_nmos_rsw1     ='gauss(sg13g2_lv_nmos_rsw1_norm,     0.0407, mc_ok)'
+.param sg13g2_lv_nmos_thesatl  ='gauss(sg13g2_lv_nmos_thesatl_norm,  0.0908, mc_ok)'
+.param sg13g2_lv_nmos_thesatw  ='gauss(sg13g2_lv_nmos_thesatw_norm,  0.0272, mc_ok)'
+.param sg13g2_lv_nmos_thesatlw ='gauss(sg13g2_lv_nmos_thesatlw_norm, 0.1503, mc_ok)'
+.param sg13g2_lv_nmos_cjorbot  ='gauss(sg13g2_lv_nmos_cjorbot_norm,  0.0267, mc_ok)'
+.param sg13g2_lv_nmos_cjorsti  ='gauss(sg13g2_lv_nmos_cjorsti_norm,  0.0267, mc_ok)'
+.param sg13g2_lv_nmos_cjorgat  ='gauss(sg13g2_lv_nmos_cjorgat_norm,  0.0267, mc_ok)'
+
+.param sg13g2_lv_pmos_vfbo     ='gauss(sg13g2_lv_pmos_vfbo_norm,     0.01,   mc_ok)'
+.param sg13g2_lv_pmos_toxo     ='gauss(sg13g2_lv_pmos_toxo_norm,     0.0133, mc_ok)'
+.param sg13g2_lv_pmos_dphibo   ='gauss(sg13g2_lv_pmos_dphibo_norm,   0.0656, mc_ok)'
+.param sg13g2_lv_pmos_dphibl   ='gauss(sg13g2_lv_pmos_dphibl_norm,   0.1135, mc_ok)'
+.param sg13g2_lv_pmos_dphibw   ='gauss(sg13g2_lv_pmos_dphibw_norm,   0.1197, mc_ok)'
+.param sg13g2_lv_pmos_dphiblw  ='gauss(sg13g2_lv_pmos_dphiblw_norm,  0.0135, mc_ok)'
+.param sg13g2_lv_pmos_toxovo   ='gauss(sg13g2_lv_pmos_toxovo_norm,   0.0133, mc_ok)'
+.param sg13g2_lv_pmos_ctl      ='gauss(sg13g2_lv_pmos_ctl_norm,      0.1562, mc_ok)'
+.param sg13g2_lv_pmos_muew     ='gauss(sg13g2_lv_pmos_muew_norm,     0.032,  mc_ok)'
+.param sg13g2_lv_pmos_themuo   ='gauss(sg13g2_lv_pmos_themuo_norm,   0.0026, mc_ok)'
+.param sg13g2_lv_pmos_rsw1     ='gauss(sg13g2_lv_pmos_rsw1_norm,     0.0407, mc_ok)'
+.param sg13g2_lv_pmos_thesatl  ='gauss(sg13g2_lv_pmos_thesatl_norm,  0.0908, mc_ok)'
+.param sg13g2_lv_pmos_thesatw  ='gauss(sg13g2_lv_pmos_thesatw_norm,  0.0272, mc_ok)'
+.param sg13g2_lv_pmos_thesatlw ='gauss(sg13g2_lv_pmos_thesatlw_norm, 0.1503, mc_ok)'
+.param sg13g2_lv_pmos_cjorbot  ='gauss(sg13g2_lv_pmos_cjorbot_norm,  0.0267, mc_ok)'
+.param sg13g2_lv_pmos_cjorsti  ='gauss(sg13g2_lv_pmos_cjorsti_norm,  0.0267, mc_ok)'
+.param sg13g2_lv_pmos_cjorgat  ='gauss(sg13g2_lv_pmos_cjorgat_norm,  0.0267, mc_ok)'
+
diff --git a/versions.txt b/versions.txt
new file mode 100644
index 00000000..4fd935dd
--- /dev/null
+++ b/versions.txt
@@ -0,0 +1,8 @@
+Python 3.10.12
+openvaf 23.5.0
+ngspice 43
+Xyce 7.8-opensource
+xschem 3.4.5
+qucs-s s24.3.0 (12ddd12b)
+klayout 0.29.2
+openEMS v0.0.35-108-gc651cce