tests/psoc6/hw_ext/pwm.py: Refactor for REPL timing performance.

Signed-off-by: enriquezgarc <enriquezgarcia.external@infineon.com>
Infineon · Apr 16, 2024 · 487f6f0 · 487f6f0
1 parent 30650e6
commit 487f6f0
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/tests/psoc6/hw_ext/pwm.py b/tests/psoc6/hw_ext/pwm.py
@@ -22,7 +22,7 @@
 low_signal_start_time = 0
 high_signal_start_time = 0
 tolerance = 3.0
-duty_tolerance = 10.0
+duty_tolerance = 13.0
 debug = False