diff --git a/tests/psoc6/hw_ext/multi_blocking/i2s_tx.py b/tests/psoc6/hw_ext/multi_blocking/i2s_tx.py
index 13142ee749f5..d84ecd54b566 100644
--- a/tests/psoc6/hw_ext/multi_blocking/i2s_tx.py
+++ b/tests/psoc6/hw_ext/multi_blocking/i2s_tx.py
@@ -12,9 +12,6 @@
     ws_tx_pin = "P13_2"
     sd_tx_pin = "P13_3"
     wait_signal_pin_name = "P0_4"
-    # while extmod/refactoring
-    # print("SKIP")
-    # raise SystemExit
 elif "CY8CPROTO-063-BLE" in machine:
     # This would be the right pins for this test, but unfortunately
     # the P5_1 is allocated for the UART serial comm terminal communication.