diff --git a/ports/psoc6/machine_i2s.c b/ports/psoc6/machine_i2s.c
index e359f4d28209c..cf3db497289af 100644
--- a/ports/psoc6/machine_i2s.c
+++ b/ports/psoc6/machine_i2s.c
@@ -104,50 +104,6 @@ static int8_t get_frame_mapping_index(int8_t bits, format_t format) {
     }
 }
 
-// void i2s_audio_clock_init(uint32_t audio_clock_freq_hz) {
-//     cyhal_clock_t clock_pll;
-//     cy_rslt_t result;
-
-//     static bool clock_set = false;
-
-//     result = cyhal_clock_reserve(&clock_pll, &CYHAL_CLOCK_PLL[0]);
-//     i2s_assert_raise_val("PLL clock reserve failed with error code: %lx", result);
-
-//     uint32_t pll_source_clock_freq_hz = cyhal_clock_get_frequency(&clock_pll);
-
-//     if (audio_clock_freq_hz != pll_source_clock_freq_hz) {
-//         mp_printf(&mp_plat_print, "machine.I2S: PLL0 freq is changed from %lu to %lu. This will affect all resources clock freq sourced by PLL0.\n", pll_source_clock_freq_hz, audio_clock_freq_hz);
-//         clock_set = false;
-//         pll_source_clock_freq_hz = audio_clock_freq_hz;
-//     }
-
-//     if (!clock_set) {
-//         result = cyhal_clock_set_frequency(&clock_pll,  pll_source_clock_freq_hz, NULL);
-//         i2s_assert_raise_val("Set PLL clock frequency failed with error code: %lx", result);
-//         if (!cyhal_clock_is_enabled(&clock_pll)) {
-//             result = cyhal_clock_set_enabled(&clock_pll, true, true);
-//             i2s_assert_raise_val("PLL clock enable failed with error code: %lx", result);
-//         }
-
-//         result = cyhal_clock_reserve(&audio_clock, &CYHAL_CLOCK_HF[1]);
-//         i2s_assert_raise_val("HF1 clock reserve failed with error code: %lx", result);
-//         result = cyhal_clock_set_source(&audio_clock, &clock_pll);
-//         i2s_assert_raise_val("HF1 clock sourcing failed with error code: %lx", result);
-//         result = cyhal_clock_set_divider(&audio_clock, 2);
-//         i2s_assert_raise_val("HF1 clock set divider failed with error code: %lx", result);
-//         if (!cyhal_clock_is_enabled(&audio_clock)) {
-//             result = cyhal_clock_set_enabled(&audio_clock, true, true);
-//             i2s_assert_raise_val("HF1 clock enable failed with error code: %lx", result);
-//         }
-//         cyhal_clock_free(&audio_clock);
-
-//         clock_set = true;
-//     }
-
-//     cyhal_clock_free(&clock_pll);
-
-//     cyhal_system_delay_ms(1);
-// }
 
 static inline bool i2s_dma_is_tx_complete(cyhal_i2s_event_t event) {
     return 0u != (event & CYHAL_I2S_ASYNC_TX_COMPLETE);
@@ -367,21 +323,6 @@ static void mp_machine_i2s_init_helper(machine_i2s_obj_t *self, mp_arg_val_t *ar
         mp_raise_ValueError(MP_ERROR_TEXT("invalid format"));
     }
 
-    // // is valid clock freq?
-    // uint32_t audio_clock_freq_hz;
-    // uint32_t rate = args[ARG_rate].u_int;
-    // if (rate == 8000 ||
-    //     rate == 16000 ||
-    //     rate == 32000 ||
-    //     rate == 48000) {
-    //     audio_clock_freq_hz = AUDIO_SYS_CLOCK_98_304_000_HZ;
-    // } else if (rate == 22050 ||
-    //            rate == 44100) {
-    //     audio_clock_freq_hz = AUDIO_SYS_CLOCK_90_300_000_HZ;
-    // } else {
-    //     mp_raise_ValueError(MP_ERROR_TEXT("rate not supported"));
-    // }
-
     // is valid buf size ?
     int32_t ring_buffer_len = args[ARG_ibuf].u_int;
     if (ring_buffer_len < 0) {
@@ -402,9 +343,6 @@ static void mp_machine_i2s_init_helper(machine_i2s_obj_t *self, mp_arg_val_t *ar
     self->ring_buffer_storage = m_new(uint8_t, ring_buffer_len);
 
     ringbuf_init(&self->ring_buffer, self->ring_buffer_storage, ring_buffer_len);
-    // i2s_audio_clock_init(audio_clock_freq_hz);
-    // audio_i2s_set_frequency(audio_clock_freq_hz, &audio_clock);
-    // mp_printf(&mp_plat_print, "clock pointer: %p\n", audio_clock);
     i2s_init(self, &audio_clock);
     i2s_dma_init(self);
 }
diff --git a/ports/psoc6/modmachine.c b/ports/psoc6/modmachine.c
index 42719a8d31ff1..b57d542e474e7 100644
--- a/ports/psoc6/modmachine.c
+++ b/ports/psoc6/modmachine.c
@@ -437,9 +437,8 @@ void audio_i2s_set_frequency(uint32_t freq) {
     clock_assert_raise_val("PLL clock reserve failed with error code: %lx", result);
 
     uint32_t pll_source_clock_freq_hz = cyhal_clock_get_frequency(&clock_pll);
-
     if (freq != pll_source_clock_freq_hz) {
-        // mp_printf(&mp_plat_print, "machine.I2S: PLL0 freq is changed from %lu to %lu. This will affect all resources clock freq sourced by PLL0.\n", pll_source_clock_freq_hz, freq);
+        mp_printf(&mp_plat_print, "machine.I2S: PLL0 freq is changed from %lu to %lu. This will affect all resources clock freq sourced by PLL0.\n", pll_source_clock_freq_hz, freq);
         clock_set_i2s = false;
         pll_source_clock_freq_hz = freq;
     }
diff --git a/tests/ports/psoc6/board_ext_hw/multi/i2s_rx.py b/tests/ports/psoc6/board_ext_hw/multi/i2s_rx.py
index 89285315eb647..8c13d10e1f244 100644
--- a/tests/ports/psoc6/board_ext_hw/multi/i2s_rx.py
+++ b/tests/ports/psoc6/board_ext_hw/multi/i2s_rx.py
@@ -112,9 +112,9 @@ def print_i2s_format(raw_buf, bits):
     for _bits in test_bits:
         for _rate in test_rates:
             if _rate == 22050 or _rate == 44100:
-                freq = 98000000
-            else:
                 freq = 90000000
+            else:
+                freq = 98000000
             machine.freq(freq, machine.AUDIO_I2S)
             audio_in = I2S(
                 0,
diff --git a/tests/ports/psoc6/board_ext_hw/multi/i2s_rx.py.exp b/tests/ports/psoc6/board_ext_hw/multi/i2s_rx.py.exp
index 8317df059e31e..65a11396d51ea 100644
--- a/tests/ports/psoc6/board_ext_hw/multi/i2s_rx.py.exp
+++ b/tests/ports/psoc6/board_ext_hw/multi/i2s_rx.py.exp
@@ -1,30 +1,39 @@
 1. tx-rx data for all formats, rates and bit resolution
+machine.I2S: PLL0 freq is changed from 48000000 to 98000000. This will affect all resources clock freq sourced by PLL0.
 data received for format = 0, bits = 16, rate = 8000 : True
 data received for format = 0, bits = 16, rate = 16000 : True
 data received for format = 0, bits = 16, rate = 32000 : True
 data received for format = 0, bits = 16, rate = 48000 : True
+machine.I2S: PLL0 freq is changed from 98000000 to 90000000. This will affect all resources clock freq sourced by PLL0.
 data received for format = 0, bits = 16, rate = 22050 : True
 data received for format = 0, bits = 16, rate = 44100 : True
+machine.I2S: PLL0 freq is changed from 90000000 to 98000000. This will affect all resources clock freq sourced by PLL0.
 data received for format = 0, bits = 32, rate = 8000 : True
 data received for format = 0, bits = 32, rate = 16000 : True
 data received for format = 0, bits = 32, rate = 32000 : True
 data received for format = 0, bits = 32, rate = 48000 : True
+machine.I2S: PLL0 freq is changed from 98000000 to 90000000. This will affect all resources clock freq sourced by PLL0.
 data received for format = 0, bits = 32, rate = 22050 : True
 data received for format = 0, bits = 32, rate = 44100 : True
+machine.I2S: PLL0 freq is changed from 90000000 to 98000000. This will affect all resources clock freq sourced by PLL0.
 data received for format = 1, bits = 16, rate = 8000 : True
 data received for format = 1, bits = 16, rate = 16000 : True
 data received for format = 1, bits = 16, rate = 32000 : True
 data received for format = 1, bits = 16, rate = 48000 : True
+machine.I2S: PLL0 freq is changed from 98000000 to 90000000. This will affect all resources clock freq sourced by PLL0.
 data received for format = 1, bits = 16, rate = 22050 : True
 data received for format = 1, bits = 16, rate = 44100 : True
+machine.I2S: PLL0 freq is changed from 90000000 to 98000000. This will affect all resources clock freq sourced by PLL0.
 data received for format = 1, bits = 32, rate = 8000 : True
 data received for format = 1, bits = 32, rate = 16000 : True
 data received for format = 1, bits = 32, rate = 32000 : True
 data received for format = 1, bits = 32, rate = 48000 : True
+machine.I2S: PLL0 freq is changed from 98000000 to 90000000. This will affect all resources clock freq sourced by PLL0.
 data received for format = 1, bits = 32, rate = 22050 : True
 data received for format = 1, bits = 32, rate = 44100 : True
 
 2. irq non-blocking read implementation 
+machine.I2S: PLL0 freq is changed from 90000000 to 98000000. This will affect all resources clock freq sourced by PLL0.
 rx blocking done
 
 3. shift 
diff --git a/tests/ports/psoc6/board_ext_hw/multi/i2s_tx.py b/tests/ports/psoc6/board_ext_hw/multi/i2s_tx.py
index 97c5160414e32..c74e15fd054a7 100644
--- a/tests/ports/psoc6/board_ext_hw/multi/i2s_tx.py
+++ b/tests/ports/psoc6/board_ext_hw/multi/i2s_tx.py
@@ -122,9 +122,9 @@ def print_i2s_format(raw_buf, bits):
     for _bits in test_bits:
         for _rate in test_rates:
             if _rate == 22050 or _rate == 44100:
-                freq = 98000000
-            else:
                 freq = 90000000
+            else:
+                freq = 98000000
             machine.freq(freq, machine.AUDIO_I2S)
             audio_out = I2S(
                 0,