tests/psoc6/hw_ext/pwm.py: Refactor for REPL timing performance.

Signed-off-by: enriquezgarc <enriquezgarcia.external@infineon.com>
Infineon · Apr 16, 2024 · a0231bc · a0231bc
1 parent d620334
commit a0231bc
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/tests/psoc6/hw_ext/pwm.py b/tests/psoc6/hw_ext/pwm.py
@@ -22,6 +22,7 @@
 low_signal_start_time = 0
 high_signal_start_time = 0
 tolerance = 3.0
+duty_tolerance = 5.0
 debug = False
 
 
@@ -102,7 +103,7 @@ def validate_signal(exp_freq=0, exp_duty_u16=0, exp_duty_ns=0, exp_dutycycle=0):
 
  print(
  "Expected duty cycle(%) approx same as experimental duty cycle(%): ",
- (exp_dutycycle - tolerance) < dc < (exp_dutycycle + tolerance),
+ (exp_dutycycle - duty_tolerance) < dc < (exp_dutycycle + duty_tolerance),
  )