From a0231bcd381737e9d610812f4182607e445f4385 Mon Sep 17 00:00:00 2001 From: enriquezgarc Date: Tue, 16 Apr 2024 10:52:53 +0200 Subject: [PATCH] tests/psoc6/hw_ext/pwm.py: Refactor for REPL timing performance. Signed-off-by: enriquezgarc --- tests/psoc6/hw_ext/pwm.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/psoc6/hw_ext/pwm.py b/tests/psoc6/hw_ext/pwm.py index b2f96c1b35729..d89f4f37e22a0 100644 --- a/tests/psoc6/hw_ext/pwm.py +++ b/tests/psoc6/hw_ext/pwm.py @@ -22,6 +22,7 @@ low_signal_start_time = 0 high_signal_start_time = 0 tolerance = 3.0 +duty_tolerance = 5.0 debug = False @@ -102,7 +103,7 @@ def validate_signal(exp_freq=0, exp_duty_u16=0, exp_duty_ns=0, exp_dutycycle=0): print( "Expected duty cycle(%) approx same as experimental duty cycle(%): ", - (exp_dutycycle - tolerance) < dc < (exp_dutycycle + tolerance), + (exp_dutycycle - duty_tolerance) < dc < (exp_dutycycle + duty_tolerance), )