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tests/psoc6/bitstream: Refining bitstream tests.
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Signed-off-by: enriquezgarc <enriquezgarcia.external@infineon.com>
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jaenrig-ifx committed Apr 15, 2024
1 parent 0baeda1 commit c0b9432
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Showing 3 changed files with 52 additions and 15 deletions.
42 changes: 32 additions & 10 deletions tests/psoc6/bitstream/bitstream_rx.py
Original file line number Diff line number Diff line change
Expand Up @@ -13,25 +13,25 @@
machine = os.uname().machine
if "CY8CPROTO-062-4343W" in machine:
bitstream_in_pin_name = "P12_1"
rx_ready_signal_pin_name = "P13_7"
rx_ready_signal_pin_name = "P13_5"

elif "CY8CPROTO-063-BLE" in machine:
bitstream_in_pin_name = "P5_3"
rx_ready_signal_pin_name = "P12_6"
bitstream_in_pin_name = "P5_2"
rx_ready_signal_pin_name = "P6_2"

expected_values = [
8000,
5000,
8000,
5000,
8000,
50000,
5000,
8000,
5000,
3000,
1000,
3000,
10000,
1000,
3000,
1000,
3000,
Expand All @@ -40,16 +40,26 @@
tolerance = 100


def notify_readiness_to_tx():
rx_ready_signal_pin = Pin(
rx_ready_signal_pin_name, Pin.OUT, value=0
) # signal to inform the transmitter that receiver is read
rx_ready_signal_pin.low()
# delay
for i in range(1000):
pass
rx_ready_signal_pin.high()
rx_ready_signal_pin.deinit()


def bitstream_rx_measure():
global periods
periods = []
last_value = 0
bitstream_in_pin = Pin(bitstream_in_pin_name, Pin.IN)
rx_ready_signal_pin = Pin(
rx_ready_signal_pin_name, Pin.OUT, value=0
) # signal to inform the transmitter that receiver is ready
start_time = time.ticks_us()
current_value = 0

for i in range(17):
while current_value == last_value:
current_value = bitstream_in_pin.value()
Expand All @@ -59,15 +69,27 @@ def bitstream_rx_measure():
start_time = current_time
periods.append(time_period)

bitstream_in_pin.deinit()


def validate_bitstream():
for i in range(len(periods) - 1):
if abs((periods[i + 1] - expected_values[i]) <= tolerance):
diff = abs(periods[i + 1] - expected_values[i])
if diff <= tolerance:
print("true")
else:
print("false")
print(
"expected :"
+ str(expected_values[i])
+ " period: "
+ str(periods[i + 1])
+ " diff: "
+ str(diff)
)


print("Bitstream capture")
print("bitstream rx")
notify_readiness_to_tx()
bitstream_rx_measure()
validate_bitstream()
2 changes: 1 addition & 1 deletion tests/psoc6/bitstream/bitstream_rx.py.exp
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
bitstream capture
bitstream rx
true
true
true
Expand Down
23 changes: 19 additions & 4 deletions tests/psoc6/bitstream/bitstream_tx.py
Original file line number Diff line number Diff line change
Expand Up @@ -14,17 +14,30 @@
machine = os.uname().machine
if "CY8CPROTO-062-4343W" in machine:
bitstream_pin_name = "P12_1"
wait_signal_pin_name = "P13_7"
wait_signal_pin_name = "P13_5"
elif "CY8CPROTO-063-BLE" in machine:
bitstream_pin_name = "P5_2"
wait_signal_pin_name = "P12_7"
wait_signal_pin_name = "P6_2"

signal_received = False


def signal_irq(arg):
global signal_received
signal_received = True


def wait_for_rx_ready():
global signal_received
wait_signal_pin = Pin(wait_signal_pin_name, Pin.IN)
while wait_signal_pin.value() == 1:
wait_signal_pin.irq(handler=signal_irq, trigger=Pin.IRQ_RISING)
while not signal_received:
pass

signal_received = False
wait_signal_pin.deinit()
# print("rx ready")


def send_bitstream():
timing = [3000000, 1000000, 8000000, 5000000]
Expand All @@ -33,7 +46,9 @@ def send_bitstream():
for i in range(2):
bitstream(bitstream_pin, 0, timing, buf)

bitstream_pin.deinit()


print("bitstream tx")
# print("bitstream tx")
wait_for_rx_ready()
send_bitstream()

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