From c0b94320c11be66b718c71a34e0f60a6be6b6273 Mon Sep 17 00:00:00 2001 From: enriquezgarc Date: Mon, 15 Apr 2024 18:38:14 +0200 Subject: [PATCH] tests/psoc6/bitstream: Refining bitstream tests. Signed-off-by: enriquezgarc --- tests/psoc6/bitstream/bitstream_rx.py | 42 +++++++++++++++++------ tests/psoc6/bitstream/bitstream_rx.py.exp | 2 +- tests/psoc6/bitstream/bitstream_tx.py | 23 ++++++++++--- 3 files changed, 52 insertions(+), 15 deletions(-) diff --git a/tests/psoc6/bitstream/bitstream_rx.py b/tests/psoc6/bitstream/bitstream_rx.py index 03d21d76cd9d0..e072a880551ef 100644 --- a/tests/psoc6/bitstream/bitstream_rx.py +++ b/tests/psoc6/bitstream/bitstream_rx.py @@ -13,11 +13,11 @@ machine = os.uname().machine if "CY8CPROTO-062-4343W" in machine: bitstream_in_pin_name = "P12_1" - rx_ready_signal_pin_name = "P13_7" + rx_ready_signal_pin_name = "P13_5" elif "CY8CPROTO-063-BLE" in machine: - bitstream_in_pin_name = "P5_3" - rx_ready_signal_pin_name = "P12_6" + bitstream_in_pin_name = "P5_2" + rx_ready_signal_pin_name = "P6_2" expected_values = [ 8000, @@ -25,13 +25,13 @@ 8000, 5000, 8000, - 50000, + 5000, 8000, 5000, 3000, 1000, 3000, - 10000, + 1000, 3000, 1000, 3000, @@ -40,16 +40,26 @@ tolerance = 100 +def notify_readiness_to_tx(): + rx_ready_signal_pin = Pin( + rx_ready_signal_pin_name, Pin.OUT, value=0 + ) # signal to inform the transmitter that receiver is read + rx_ready_signal_pin.low() + # delay + for i in range(1000): + pass + rx_ready_signal_pin.high() + rx_ready_signal_pin.deinit() + + def bitstream_rx_measure(): global periods periods = [] last_value = 0 bitstream_in_pin = Pin(bitstream_in_pin_name, Pin.IN) - rx_ready_signal_pin = Pin( - rx_ready_signal_pin_name, Pin.OUT, value=0 - ) # signal to inform the transmitter that receiver is ready start_time = time.ticks_us() current_value = 0 + for i in range(17): while current_value == last_value: current_value = bitstream_in_pin.value() @@ -59,15 +69,27 @@ def bitstream_rx_measure(): start_time = current_time periods.append(time_period) + bitstream_in_pin.deinit() + def validate_bitstream(): for i in range(len(periods) - 1): - if abs((periods[i + 1] - expected_values[i]) <= tolerance): + diff = abs(periods[i + 1] - expected_values[i]) + if diff <= tolerance: print("true") else: print("false") + print( + "expected :" + + str(expected_values[i]) + + " period: " + + str(periods[i + 1]) + + " diff: " + + str(diff) + ) -print("Bitstream capture") +print("bitstream rx") +notify_readiness_to_tx() bitstream_rx_measure() validate_bitstream() diff --git a/tests/psoc6/bitstream/bitstream_rx.py.exp b/tests/psoc6/bitstream/bitstream_rx.py.exp index 459ca4bca8c00..f2e78d14b2ed1 100644 --- a/tests/psoc6/bitstream/bitstream_rx.py.exp +++ b/tests/psoc6/bitstream/bitstream_rx.py.exp @@ -1,4 +1,4 @@ -bitstream capture +bitstream rx true true true diff --git a/tests/psoc6/bitstream/bitstream_tx.py b/tests/psoc6/bitstream/bitstream_tx.py index 7b4a4c627b449..e9fe28b86ffb0 100755 --- a/tests/psoc6/bitstream/bitstream_tx.py +++ b/tests/psoc6/bitstream/bitstream_tx.py @@ -14,17 +14,30 @@ machine = os.uname().machine if "CY8CPROTO-062-4343W" in machine: bitstream_pin_name = "P12_1" - wait_signal_pin_name = "P13_7" + wait_signal_pin_name = "P13_5" elif "CY8CPROTO-063-BLE" in machine: bitstream_pin_name = "P5_2" - wait_signal_pin_name = "P12_7" + wait_signal_pin_name = "P6_2" + +signal_received = False + + +def signal_irq(arg): + global signal_received + signal_received = True def wait_for_rx_ready(): + global signal_received wait_signal_pin = Pin(wait_signal_pin_name, Pin.IN) - while wait_signal_pin.value() == 1: + wait_signal_pin.irq(handler=signal_irq, trigger=Pin.IRQ_RISING) + while not signal_received: pass + signal_received = False + wait_signal_pin.deinit() + # print("rx ready") + def send_bitstream(): timing = [3000000, 1000000, 8000000, 5000000] @@ -33,7 +46,9 @@ def send_bitstream(): for i in range(2): bitstream(bitstream_pin, 0, timing, buf) + bitstream_pin.deinit() + -print("bitstream tx") +# print("bitstream tx") wait_for_rx_ready() send_bitstream()