From ff2683a3e08fd3705c5d505b0d5f83984700fe70 Mon Sep 17 00:00:00 2001 From: enriquezgarc Date: Wed, 27 Mar 2024 17:33:08 +0100 Subject: [PATCH] ports/psoc6/machine_i2s.c: WIP for rx prepare. Signed-off-by: enriquezgarc --- ports/psoc6/machine_i2s.c | 37 ++++----- tests/psoc6/hw_ext/i2s.py | 155 ++++++++++++++++++++++++++------------ 2 files changed, 124 insertions(+), 68 deletions(-) diff --git a/ports/psoc6/machine_i2s.c b/ports/psoc6/machine_i2s.c index e88edd5a94d38..9874c3c46d65a 100644 --- a/ports/psoc6/machine_i2s.c +++ b/ports/psoc6/machine_i2s.c @@ -117,16 +117,16 @@ void i2s_audio_clock_init(uint32_t audio_clock_freq_hz) { static bool clock_set = false; static uint32_t pll_source_clock_freq_hz = AUDIO_SYS_CLOCK_HZ; + // TODO: Currently this is not working after initialization. + // Once initializing, changing the frequency blocks execution of I2S constructor call. if (audio_clock_freq_hz != pll_source_clock_freq_hz) { clock_set = false; pll_source_clock_freq_hz = audio_clock_freq_hz; - mp_printf(&mp_plat_print, "another clock configuration required\n"); } if (!clock_set) { clock_set = true; - mp_printf(&mp_plat_print, "clock will be set\n"); /* Initialize, take ownership of PLL0/PLL */ result = cyhal_clock_reserve(&clock_pll, &CYHAL_CLOCK_PLL[0]); @@ -295,7 +295,7 @@ static void i2s_init(machine_i2s_obj_t *self, cyhal_clock_t *clock) { cyhal_i2s_pins_t pins = { .sck = self->sck, .ws = self->ws, .data = self->sd, .mclk = NC }; cyhal_i2s_config_t config = { - .is_tx_slave = false, + .is_tx_slave = true, .is_rx_slave = false, .mclk_hz = 0, .channel_length = self->bits, @@ -421,6 +421,21 @@ static void mp_machine_i2s_init_helper(machine_i2s_obj_t *self, mp_arg_val_t *ar mp_raise_ValueError(MP_ERROR_TEXT("invalid format")); } + uint32_t audio_clock_freq_hz; + uint32_t rate = args[ARG_rate].u_int; + ; + if (rate == 8000 || + rate == 16000 || + rate == 32000 || + rate == 48000) { + audio_clock_freq_hz = AUDIO_SYS_CLOCK_HZ; + } else if (rate == 22050 || + rate == 44100) { + audio_clock_freq_hz = AUDIO_SYS_CLOCK_HZ_1; + } else { + mp_raise_ValueError(MP_ERROR_TEXT("rate not supported")); + } + int32_t ring_buffer_len = args[ARG_ibuf].u_int; if (ring_buffer_len > 0) { self->ring_buffer_storage = m_new(uint8_t, ring_buffer_len); @@ -436,22 +451,8 @@ static void mp_machine_i2s_init_helper(machine_i2s_obj_t *self, mp_arg_val_t *ar self->bits = i2s_bits; self->channel_resolution_bits = i2s_bits_resolution; self->format = i2s_format; - self->rate = args[ARG_rate].u_int; - uint32_t audio_clock_freq_hz; - if (self->rate == 8000 || - self->rate == 16000 || - self->rate == 32000 || - self->rate == 48000) { - audio_clock_freq_hz = AUDIO_SYS_CLOCK_HZ; - } else if (self->rate == 22050 || - self->rate == 44100) { - audio_clock_freq_hz = AUDIO_SYS_CLOCK_HZ_1; - } else { - mp_raise_ValueError(MP_ERROR_TEXT("rate not supported")); - } + self->rate = rate; self->ibuf = ring_buffer_len; - - self->callback_for_non_blocking = MP_OBJ_NULL; self->io_mode = BLOCKING; diff --git a/tests/psoc6/hw_ext/i2s.py b/tests/psoc6/hw_ext/i2s.py index 0b50c3fe43150..4cb263b48e205 100644 --- a/tests/psoc6/hw_ext/i2s.py +++ b/tests/psoc6/hw_ext/i2s.py @@ -29,45 +29,85 @@ print("SKIP") raise SystemExit -sample_num = 3600 -max_num = 0x80 -sample = bytearray( - [0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x99, 0xAA, 0xBB, 0xCC, 0xDD, 0xEE, 0xFF] -) -buf = bytearray([0] * sample_num) -j = 0 -for i in range(sample_num): - if i >= (j + 1) * max_num: - j = j + 1 - buf[i] = sample[j % len(sample)] - - -# for i in range(sample_num/max_num - 1): -# print(binascii.hexlify(buf[i*max_num: (i + 1)*max_num])) - -audio_out = I2S( - 0, - sck=sck_tx_pin, - ws=ws_tx_pin, - sd=sd_tx_pin, - mode=I2S.TX, - bits=32, - format=I2S.STEREO, - rate=22050, - ibuf=20000, -) - -# audio_in = I2S( -# 1, -# sck=sck_rx_pin, -# ws=ws_rx_pin, -# sd=sd_rx_pin, -# mode=I2S.RX, -# bits=32, -# format=I2S.STEREO, -# rate=8000, -# ibuf=20000, -# ) + +def instance0(): + audio_in = I2S( + 1, + sck=sck_rx_pin, + ws=ws_rx_pin, + sd=sd_rx_pin, + mode=I2S.RX, + bits=32, + format=I2S.STEREO, + rate=16000, + ibuf=20000, + ) + + # rx_buf = bytearray(1000) + # num_read = audio_in.readinto(rx_buf) + # print("Rx Buffer") + # print(rx_buf) + + +def instance1(): + # I2S transmitter + def make_i2s_tx_data_pattern(): + max_num = 0x80 + sample = bytearray( + [ + 0x11, + 0x22, + 0x33, + 0x44, + 0x55, + 0x66, + 0x77, + 0x88, + 0x99, + 0xAA, + 0xBB, + 0xCC, + 0xDD, + 0xEE, + 0xFF, + ] + ) + sample_num = max_num * len(sample) * 2 + buf = bytearray([0] * sample_num) + j = 0 + for i in range(sample_num): + if i >= (j + 1) * max_num: + j = j + 1 + buf[i] = sample[j % len(sample)] + + for i in range(sample_num / max_num): + print(binascii.hexlify(buf[i * max_num : (i + 1) * max_num])) + + return buf + + buf = make_i2s_tx_data_pattern() + + audio_out = I2S( + 0, + sck=sck_tx_pin, + ws=ws_tx_pin, + sd=sd_tx_pin, + mode=I2S.TX, + bits=32, + format=I2S.STEREO, + rate=16000, + ibuf=20000, + ) + + # while True: + for i in range(20): + num_written = audio_out.write(buf) + print(num_written) + + +instance0() +instance1() + # tx_done = False # def tx_complete_irq(obj): @@ -76,25 +116,40 @@ # print("tx completed") # def tx_complete_irq(obj): -# obj.write(buf) +# audio_out.write(buf) # buf = b"\x01\x00\x17\x15\x16\x44" # print("tx Buffer") # print(buf) # audio_out.irq(tx_complete_irq) -num_written = audio_out.write(buf) + # while not tx_done: # pass -print("tx blocking done") +# tx_done = False + +# print("tx blocking done") + +# print(num_written) -print(num_written) -# rx_buf = bytearray(sample_num) -# num_read = audio_in.readinto(rx_buf) -# print("Rx Buffer") -# print(rx_buf) -# audio_out.stop() -# audio_in.stop() -# time.sleep(20) +# for i in range(20): +# time.sleep(1) # audio_out.deinit() + + +# from machine import Pin +# import asyncio + +# async def blink(period_ms): +# while True: +# print("b" + str(period_ms)) +# await asyncio.sleep_ms(period_ms) + +# async def main(): +# asyncio.create_task(blink(800)) +# asyncio.create_task(blink(400)) +# await asyncio.sleep_ms(10_000) + +# # Running on a generic board +# asyncio.run(main())