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Spi slave enablement #128

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Jun 21, 2024
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cc825a0
:tools/codeformat.py: Add exclusion for external PSoC6 port libraries.
jaenrig-ifx Apr 24, 2023
1092fb9
ports/psoc6: Adding SPI Slave code.
NikhitaR-IFX Apr 1, 2024
e485704
ports/psoc6: SPI enhanvements and test.
NikhitaR-IFX Apr 12, 2024
7bb617a
tools: Codeformat script missing.
NikhitaR-IFX Apr 12, 2024
f019640
docs/psoc6: Adding right docs for SPI slave.
NikhitaR-IFX Apr 12, 2024
c84d7cf
ports/psoc6: SPI fixes.
NikhitaR-IFX Apr 29, 2024
b9ddec4
ports/psoc6: SPI refactoring and tests.
NikhitaR-IFX May 6, 2024
ac0dad9
ports/psoc6: SPI refactoring and tests.
NikhitaR-IFX May 7, 2024
b9e6e3e
tests/psoc6: Updated test files.
NikhitaR-IFX May 7, 2024
dd96c08
tests/psoc6: Adding test support for BLE board.
NikhitaR-IFX May 10, 2024
804b0ba
tests/psoc6/hw_ext/img: Added HIL v0.4.0 setup with SPI pins.
NikhitaR-IFX May 28, 2024
fa6b604
tests/psoc6/spi: WIP SPI.
NikhitaR-IFX May 29, 2024
47aa328
tests/psoc6/spi: Refactoring SPI tests. WIP.
NikhitaR-IFX May 30, 2024
41dee33
psoc6/hw_ext/img: Updated hil setup diagrams to v0.4.0.
NikhitaR-IFX May 30, 2024
56d9d08
tests/psoc6/hw_ext: Removing obsolete spi tests.
NikhitaR-IFX May 30, 2024
23cbc42
tests/psoc6/hw_ext/img: Updated hil-setup diagram.
NikhitaR-IFX Jun 5, 2024
f9427ed
tests/psoc6/spi: Reworking spi tests.
jaenrig-ifx Jun 5, 2024
782b529
tests/psoc6/../spi: WIP refactor SPI tests.
jaenrig-ifx Jun 5, 2024
91ef1a6
tests/psoc6/../spi: Refactored tests, working without synch lines.
jaenrig-ifx Jun 5, 2024
63ef3e3
tests/psoc6/hw_ext/spi.c: Using extexternal chip select.
jaenrig-ifx Jun 13, 2024
5b7e507
tests/psoc6/hw_ext/adc: Pins modification for CY8CPROTO-062-4343W HIL.
jaenrig-ifx Jun 14, 2024
a9332d0
.github/workflow/ports_psoc6.yml: Added i2c and spi sspecific tests.
jaenrig-ifx Jun 17, 2024
2b3a83f
tests/psoc6: Changes in adc, i2c, run_test script.
jaenrig-ifx Jun 17, 2024
50d2e97
tools/psoc6/ifx-mpy-hil-devs.yml: Updating boards versions.
jaenrig-ifx Jun 17, 2024
8240a33
.github/workflows/ports_psoc6.yml: Fixed removed testtypo.
jaenrig-ifx Jun 17, 2024
89aa6ae
.github/workflows/ports_psoc6.yml: Adding device depending on board.
jaenrig-ifx Jun 17, 2024
ab7318d
.github/workflows/ports_psoc6.yml: Adding device depending on board.
jaenrig-ifx Jun 17, 2024
21f9ead
.github/workflows/ports_psoc6.yml: Adding device depending on board.
jaenrig-ifx Jun 17, 2024
20fcd09
.github/workflows/ports_psoc6.yml: Adding device depending on board.
jaenrig-ifx Jun 17, 2024
5d48a95
tests/psoc6: Fixed typo in adc test.
jaenrig-ifx Jun 17, 2024
b79f5f3
ports/psoc6: Disabled SoftSPI. Removed duplicated modmachine qstr.
jaenrig-ifx Jun 18, 2024
d247020
docs/psoc6/quickref.rst: Disabled SoftSPI.
jaenrig-ifx Jun 18, 2024
b84e71c
tests/psoc6/hw_ext/img: Updated HIL connection diagram to 0.4.0.
jaenrig-ifx Jun 18, 2024
cd53e75
ports/psoc6: Adding default NC for ssel.
NikhitaR-IFX Jun 19, 2024
9206a99
ports/psoc6: WIP: SPI constructor changes.
NikhitaR-IFX Jun 20, 2024
94d28de
ports/psoc6: Source code changes to remove ssel.
NikhitaR-IFX Jun 20, 2024
46a5d0c
ports/psoc6: SPI docs and code fix.
NikhitaR-IFX Jun 20, 2024
8f50240
ports/psoc6: Remove redundant lines.
NikhitaR-IFX Jun 20, 2024
b61dcb3
ports/psoc6: SPI minor change.
NikhitaR-IFX Jun 20, 2024
5af9b82
ports/psoc6: Remove redundant code parts.
NikhitaR-IFX Jun 20, 2024
0051976
ports/psoc6: Make single init helper for spi.
NikhitaR-IFX Jun 21, 2024
b00e746
ports/psoc6: Single SPI init helper.
NikhitaR-IFX Jun 21, 2024
61a6ad2
docs/psoc6/quickref.rst: Adding spaces for readability.
NikhitaR-IFX Jun 21, 2024
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17 changes: 14 additions & 3 deletions .github/workflows/ports_psoc6.yml
Original file line number Diff line number Diff line change
Expand Up @@ -69,8 +69,8 @@ jobs:
- name: Run psoc6 tests
run: |
devs=($(python tools/psoc6/get-devs.py port -b ${{ matrix.board }} -y tools/psoc6/${{ runner.name }}-devs.yml))
devs0=($(python tools/psoc6/get-devs.py port -b ${{ matrix.board }} -y tools/psoc6/${{ runner.name }}-devs.yml --hw-ext 0.3.0.a))
devs1=($(python tools/psoc6/get-devs.py port -b ${{ matrix.board }} -y tools/psoc6/${{ runner.name }}-devs.yml --hw-ext 0.3.0.b))
devs0=($(python tools/psoc6/get-devs.py port -b ${{ matrix.board }} -y tools/psoc6/${{ runner.name }}-devs.yml --hw-ext 0.4.0.a))
devs1=($(python tools/psoc6/get-devs.py port -b ${{ matrix.board }} -y tools/psoc6/${{ runner.name }}-devs.yml --hw-ext 0.4.0.b))
cd tests
echo " >> Filesystem tests"
./psoc6/run_psoc6_tests.sh -c -v --dev0 ${devs[0]}
Expand All @@ -79,7 +79,18 @@ jobs:
echo " >> PSoC6 single board tests"
./psoc6/run_psoc6_tests.sh -c --psoc6 --dev0 ${devs[0]}
echo " >> PSoC6 extended hardware tests"
./psoc6/run_psoc6_tests.sh -c --psoc6-hwext --dev0 ${devs0[0]}
./psoc6/run_psoc6_tests.sh -c --psoc6-hwext --dev0 ${devs0[0]}
echo " >> PSoC6 i2c tests"
if [ "${{ matrix.board }}" == "CY8CPROTO-062-4343W" ]; then
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By the way, this dirty selection approach (sorry for that 😞) should be tackle in the rework of this run_psoc6_tests.sh in future. I might have the chance to start as pre-1.0.0.

i2c_dev=${devs1[0]}
else
if [ "${{ matrix.board }}" == "CY8CPROTO-063-BLE" ]; then
i2c_dev=${devs0[0]}
fi
fi
./psoc6/run_psoc6_tests.sh -c -u --dev0 ${i2c_dev}
echo " >> PSoC6 spi tests"
./psoc6/run_psoc6_tests.sh -c -r --dev0 ${devs0[0]} --dev1 ${devs1[0]}
echo " >> PSoC6 i2s tests"
./psoc6/run_psoc6_tests.sh -c -s --dev0 ${devs0[0]} --dev1 ${devs1[0]}
echo " >> PSoC6 bitstream tests"
Expand Down
129 changes: 67 additions & 62 deletions docs/psoc6/quickref.rst
Original file line number Diff line number Diff line change
Expand Up @@ -536,60 +536,19 @@ The constructor can be called by passing the required arguments. All initializat
Software SPI bus
----------------

Software SPI (using bit-banging) works on all pins, and is accessed via the
:ref:`machine.SoftSPI <machine.SoftSPI>` class::

from machine import Pin, SoftSPI

# construct a SoftSPI bus on the given pins
# polarity is the idle state of SCK
# phase=0 means sample on the first edge of SCK, phase=1 means the second edge
spi = SoftSPI(baudrate=100_000, polarity=1, phase=0, sck='P0_2', mosi='P0_0', miso='P0_1')

spi.init(baudrate=200000) # set the baudrate

spi.read(10) # read 10 bytes on MISO
spi.read(10, 0xff) # read 10 bytes while outputting 0xff on MOSI

buf = bytearray(50) # create a buffer
spi.readinto(buf) # read into the given buffer (reads 50 bytes in this case)
spi.readinto(buf, 0xff) # read into the given buffer and output 0xff on MOSI

spi.write(b'12345') # write 5 bytes on MOSI

buf = bytearray(4) # create a buffer
spi.write_readinto(b'1234', buf) # write to MOSI and read from MISO into the buffer
spi.write_readinto(buf, buf) # write buf to MOSI and read MISO back into buf

.. Warning::
Currently *all* of ``sck``, ``mosi`` and ``miso`` *must* be specified when
initialising Software SPI.
The :ref:`machine.SoftSPI <machine.SoftSPI>` class is **disabled** in this port.

Hardware SPI bus
----------------
Hardware SPI works on the following listed pair of SPI pins.

===== =========== ============ ============
\ Default
===== =========== ============ ============
MOSI P9_0 P6_0 P10_0
MISO P9_1 P6_1 P10_1
SCK P9_2 P6_2 P10_2
===== =========== ============ ============

..
TODO: This is only applicable to the CY8CPROTO-062-4343W. This does not belong here.
TODO: Define approach on how the user gets to know the pinout diagram, alternate function of each board
- From board manual?
- From datasheet?
- To create a pinout diagram?

Refer `PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet <https://www.infineon.com/dgdl/Infineon-PSOC_6_MCU_CY8C62X8_CY8C62XA-DataSheet-v18_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ee7d03a70b1>`_
for additional details regarding all the SPI capable pins. The pins ``sck``, ``mosi`` and ``miso`` *must* be specified when
initialising Software SPI.
for details regarding all the SPI capable pins. The pins ``sck``, ``mosi`` and ``miso`` *must* be specified when
initialising SPI.

The driver is accessed via :ref:`machine.SPI <machine.SPI>`

.. note::
Slave selection should be done at application end. An example of how to do so is explained :ref:`here <machine.SPI>`

The constructor
^^^^^^^^^^^^^^^
An instance of the :mod:`machine.SPI` class can be created by invoking the constructor with all the
Expand All @@ -599,28 +558,74 @@ SPI object is created with default settings or settings of previous initializati
::

from machine import SPI
spi = SPI(0, sck='P11_2', mosi='P11_0', miso='P11_1') # Default assignment: id=0, SCK=P11_2 ,MOSI=P11_0, MISO=P11_1
spi.init()
spi = SPI(baudrate=1000000, polarity=0, phase=0, bits=8, firstbit=SPI.MSB, sck='P6_2', mosi='P6_0', miso='P6_1')

Management of a CS signal should happen in user code (via machine.Pin class).
Methods
^^^^^^^
All the methods(functions) given in :ref:`machine.SPI <machine.SPI>` class have been implemented in this port.

::

from machine import Pin
cs = Pin('P9_3', mode=Pin.OUT, value=1) # Create chip-select on pin P9_3
cs(0) # select the peripheral
Hardware SPI bus slave
----------------------

Here, ``id=0`` should be passed mandatorily which selects the ``master`` mode operation.
If the constructor is called with any additional parameters then SPI object is created & initialised.
The PSoC6™ port offers an additional class to implement an SPI slave device. The SPI master node connected to the slave can exchange data over SPI.

::

spi = SPI(0, sck='P11_2', mosi='P11_0', miso='P11_1', baudrate=2000000) #object is created & initialised with baudrate=2000000 & default parameters
spi = SPI(0, baudrate=1500000, polarity=1, phase=1, bits=8, firstbit=SPI.LSB, sck='P11_2', mosi='P11_0', miso='P11_1')
.. warning::
This is not part of the core MicroPython libraries. Therefore, not mapping any existing machine class API and neither supported by other ports.

The constructor
^^^^^^^^^^^^^^^

.. class:: SPISlave(baudrate, polarity, phase, bits, firstbit, ssel, sck, mosi, miso)

Constructs and returns a new SPI slave object using the following parameters.

Required arguments:
- *ssel* should be pin name supporting SSEL functionality.
- *sck* should be a pin name supporting the SCK functionality.
- *mosi* should be a pin name supporting the MOSI functionality.
- *miso* should be a pin name supporting the MISO functionality.

Optional arguments:
- *baudrate* should be an integer which sets the clock rate. If not passed, by default is set to 1000000 Hz.
- *polarity* can be 0 or 1. Default is set to 0.
- *phase* can be 0 or 1. Default set to 0.
- *bits* is width in bits for each transfer. Only 8 is supported.
- *firstbit* can be SPI.MSB or SPI.LSB. Default is SPI.MSB.

Example:
::

from machine import SPISlave

spi_slave = spi = SPI(baudrate=1000000, polarity=0, phase=0, bits=8, firstbit=SPI.MSB, ssel="P6_3", sck='P6_2', mosi='P6_0', miso='P6_1')

Methods
^^^^^^^
All the methods(functions) given in :ref:`machine.SPI <machine.SPI>` class have been implemented in this port.

.. method:: SPISlave.deinit()

Deinitialises the SPI slave.


.. method:: SPISlave.write(buf)

Write the bytes contained in ``buf``.

Required arguments:
- *buf* should be a buffer with bytes of data to be written.

Returns ``None``.


.. method:: SPISlave.read(buf)

Reads the data in SPI bus to ``buf``.

Required arguments:
- *buf* should be a buffer where data from bus needs to be stored.

Returns ``None``.


Timers
------
Expand Down
14 changes: 13 additions & 1 deletion ports/psoc6/boards/make-pins-csv.py
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
from __future__ import print_function
from itertools import islice
import argparse
import sys
import csv
Expand Down Expand Up @@ -50,7 +51,11 @@ def generate_pins_csv(pin_package_filename, pins_csv_filename):
with open("./" + pins_csv_filename, "w", newline="") as csv_file:
csv_writer = csv.writer(csv_file)
csv_writer.writerows(
[[value, value] for value in enum_values if value.startswith("P")]
[
[value, value]
for value in enum_values
if value.startswith("P") or value.startswith("N")
]
)
print("// pins.csv generated successfully")
else:
Expand All @@ -75,11 +80,18 @@ def generate_af_pins_csv(pin_package_filename, pins_af_csv_filename):

# Extract enum values using regex
pin_name = re.findall(r"\b(?!NC\b)(\w+)\s*=", enum_content)
# pin_name = re.findall(r"\b(\w+)\s*=", enum_content)
pin_def = re.findall(r"=\s*(.*?\))", enum_content)
# pin_def.insert(0, "255")
# print(pin_def)

# Write enum values to a CSV file
with open("./" + pins_af_csv_filename, "w", newline="") as csv_file:
NC_pin = ["NC", 255, "CYHAL_GET_GPIO(CYHAL_PORT_31, 7)"] # non-existent port
csv_writer = csv.writer(csv_file)
csv_writer.writerow(NC_pin)
for pname, pdef in zip(pin_name, pin_def):
# for pname, pdef in zip(islice(pin_name, 1, None), pin_def):
# if pin_name[pname].startswith('P'):
val = get_pin_addr_helper(pdef)
csv_writer.writerow([pname, val, pdef.strip('"')])
Expand Down
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