-
Notifications
You must be signed in to change notification settings - Fork 0
/
FSM_compute.vhd
230 lines (223 loc) · 5.58 KB
/
FSM_compute.vhd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY FSM_compute IS
PORT (
clk, rst, start, finish_indexing : IN STD_LOGIC;
src_wr_en, r_wr_en, totalsum_wr_en : OUT STD_LOGIC;
index_rst, index_wr_en : OUT STD_LOGIC;
totalsum_rst : OUT STD_LOGIC;
compute_done : OUT STD_LOGIC;
mux_adder : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
state_no : OUT std_logic_vector(3 downto 0)
);
END FSM_compute;
ARCHITECTURE FSM_compute_A OF FSM_compute IS
type state_type is (do_nothing, init, inc, load_src, load_r1, compute1, load_r2, compute2, load_r3, compute3, load_r4, compute4, compute_finish, compute_finish_2);
signal state : state_type;
signal next_state : state_type;
BEGIN
PROCESS (state, start, finish_indexing)
BEGIN
CASE state is
when do_nothing =>
if start = '0' then
next_state <= do_nothing;
src_wr_en <= '0';
r_wr_en <= '0';
totalsum_wr_en <= '0';
index_wr_en <= '0';
index_rst <= '1';
totalsum_rst <= '1';
compute_done <= '0';
mux_adder <= "000";
state_no <= "0000";
else
next_state <= init;
src_wr_en <= '0';
r_wr_en <= '0';
totalsum_wr_en <= '0';
index_wr_en <= '0';
index_rst <= '1';
totalsum_rst <= '1';
compute_done <= '0';
mux_adder <= "000";
state_no <= "0000";
end if;
when init =>
next_state <= inc;
src_wr_en <= '0';
r_wr_en <= '0';
totalsum_wr_en <= '0';
index_wr_en <= '1';
index_rst <= '1';
totalsum_rst <= '1';
compute_done <= '0';
mux_adder <= "000";
state_no <= "0001";
when inc =>
next_state <= load_src;
src_wr_en <= '0';
r_wr_en <= '0';
totalsum_wr_en <= '0';
index_wr_en <= '1';
index_rst <= '0';
totalsum_rst <= '0';
compute_done <= '0';
mux_adder <= "000";
state_no <= "0010";
when load_src =>
if finish_indexing = '1' then
next_state <= compute_finish;
src_wr_en <= '0';
r_wr_en <= '0';
totalsum_wr_en <= '0';
index_wr_en <= '0';
index_rst <= '0';
totalsum_rst <= '0';
compute_done <= '0';
mux_adder <= "000";
state_no <= "0011";
else
next_state <= load_r1;
src_wr_en <= '1';
r_wr_en <= '0';
totalsum_wr_en <= '0';
index_wr_en <= '0';
index_rst <= '0';
totalsum_rst <= '0';
compute_done <= '0';
mux_adder <= "000";
state_no <= "0011";
end if;
when load_r1 =>
next_state <= compute1;
src_wr_en <= '0';
r_wr_en <= '1';
totalsum_wr_en <= '0';
index_wr_en <= '0';
index_rst <= '0';
totalsum_rst <= '0';
compute_done <= '0';
mux_adder <= "001";
state_no <= "0100";
when compute1 =>
next_state <= load_r2;
src_wr_en <= '0';
r_wr_en <= '0';
totalsum_wr_en <= '1';
index_wr_en <= '0';
index_rst <= '0';
totalsum_rst <= '0';
compute_done <= '0';
mux_adder <= "000";
state_no <= "0101";
when load_r2 =>
next_state <= compute2;
src_wr_en <= '0';
r_wr_en <= '1';
totalsum_wr_en <= '0';
index_wr_en <= '0';
index_rst <= '0';
totalsum_rst <= '0';
compute_done <= '0';
mux_adder <= "010";
state_no <= "0110";
when compute2 =>
next_state <= load_r3;
src_wr_en <= '0';
r_wr_en <= '0';
totalsum_wr_en <= '1';
index_wr_en <= '0';
index_rst <= '0';
totalsum_rst <= '0';
compute_done <= '0';
mux_adder <= "000";
state_no <= "0111";
when load_r3 =>
next_state <= compute3;
src_wr_en <= '0';
r_wr_en <= '1';
totalsum_wr_en <= '0';
index_wr_en <= '0';
index_rst <= '0';
totalsum_rst <= '0';
compute_done <= '0';
mux_adder <= "011";
state_no <= "1000";
when compute3 =>
next_state <= load_r4;
src_wr_en <= '0';
r_wr_en <= '0';
totalsum_wr_en <= '1';
index_wr_en <= '0';
index_rst <= '0';
totalsum_rst <= '0';
compute_done <= '0';
mux_adder <= "000";
state_no <= "1001";
when load_r4 =>
next_state <= compute4;
src_wr_en <= '0';
r_wr_en <= '1';
totalsum_wr_en <= '0';
index_wr_en <= '0';
index_rst <= '0';
totalsum_rst <= '0';
compute_done <= '0';
mux_adder <= "100";
state_no <= "1010";
when compute4 =>
next_state <= inc;
src_wr_en <= '0';
r_wr_en <= '0';
totalsum_wr_en <= '1';
index_wr_en <= '0';
index_rst <= '0';
totalsum_rst <= '0';
compute_done <= '0';
mux_adder <= "000";
state_no <= "1011";
when compute_finish =>
next_state <= compute_finish_2;
src_wr_en <= '0';
r_wr_en <= '0';
totalsum_wr_en <= '0';
index_wr_en <= '0';
index_rst <= '0';
totalsum_rst <= '0';
compute_done <= '1';
mux_adder <= "000";
state_no <= "1100";
when compute_finish_2 =>
next_state <= do_nothing;
src_wr_en <= '0';
r_wr_en <= '0';
totalsum_wr_en <= '0';
index_wr_en <= '0';
index_rst <= '0';
totalsum_rst <= '0';
compute_done <= '1';
mux_adder <= "000";
state_no <= "1100";
when others =>
next_state <= do_nothing;
src_wr_en <= '0';
r_wr_en <= '0';
totalsum_wr_en <= '0';
index_wr_en <= '0';
index_rst <= '1';
totalsum_rst <= '1';
compute_done <= '0';
mux_adder <= "000";
state_no <= "0000";
END CASE;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
state <= do_nothing;
ELSIF rising_edge(clk) THEN
state <= next_state;
END IF;
END PROCESS;
End FSM_compute_A;