From dbb2fc3fd989767e8a5ff5eaddcc41b03b394ed7 Mon Sep 17 00:00:00 2001 From: MattiaDif Date: Tue, 11 Jun 2024 19:22:18 +0200 Subject: [PATCH 1/2] added Tcl for simulation --- code/sim/adder_tb.vhd | 7 ++----- code/sim_prj.tcl | 11 +++++++++++ code/src/adder.vhd | 19 +++++++------------ 3 files changed, 20 insertions(+), 17 deletions(-) create mode 100644 code/sim_prj.tcl diff --git a/code/sim/adder_tb.vhd b/code/sim/adder_tb.vhd index 1130d81..249e08d 100644 --- a/code/sim/adder_tb.vhd +++ b/code/sim/adder_tb.vhd @@ -11,8 +11,7 @@ architecture Behavioral of adder_tb is port ( a : in std_logic_vector(3 downto 0); b : in std_logic_vector(3 downto 0); - sum : out std_logic_vector(3 downto 0); - carry : out std_logic + sum : out std_logic_vector(3 downto 0) ); end component; @@ -20,14 +19,12 @@ architecture Behavioral of adder_tb is signal a : std_logic_vector(3 downto 0); signal b : std_logic_vector(3 downto 0); signal sum : std_logic_vector(3 downto 0); - signal carry : std_logic; begin -- Instantiate the Adder UUT: adder port map ( a => a, b => b, - sum => sum, - carry => carry + sum => sum ); -- Test process diff --git a/code/sim_prj.tcl b/code/sim_prj.tcl new file mode 100644 index 0000000..fab8b96 --- /dev/null +++ b/code/sim_prj.tcl @@ -0,0 +1,11 @@ +# Define project variables +set selected_simulator XSim +set top_module_sim "adder_tb" + +set_property top $top_module_sim [get_filesets sim_1] + +set_property target_simulator $selected_simulator [current_project] + +launch_simulation + +puts "Simulation launched with $selected_simulator." diff --git a/code/src/adder.vhd b/code/src/adder.vhd index 1aa6953..b33bec4 100644 --- a/code/src/adder.vhd +++ b/code/src/adder.vhd @@ -6,24 +6,19 @@ entity adder is port ( a : in std_logic_vector(3 downto 0); -- 4-bit input A b : in std_logic_vector(3 downto 0); -- 4-bit input B - sum : out std_logic_vector(3 downto 0); -- 4-bit output sum - carry : out std_logic -- carry-out + sum : out std_logic_vector(3 downto 0) -- 4-bit output sum ); end entity adder; architecture Behavioral of adder is + + signal tmp_sum : unsigned(3 downto 0); + begin - process(a, b) - variable tmp_sum : unsigned(4 downto 0); -- Temporary variable to hold the sum with carry - begin - -- Perform the addition - tmp_sum := unsigned(a) + unsigned(b); - - -- Assign the result to the output ports - sum <= std_logic_vector(tmp_sum(3 downto 0)); -- Lower 4 bits for the sum - carry <= tmp_sum(4); -- 5th bit for the carry - end process; + tmp_sum <= unsigned(a) + unsigned(b); + -- Assign the result to the output ports + sum <= std_logic_vector(tmp_sum); -- Lower 4 bits for the sum end architecture Behavioral; From d05ae1a5c9540c23efa25a76485b2029724790a5 Mon Sep 17 00:00:00 2001 From: MattiaDif Date: Wed, 12 Jun 2024 15:58:41 +0200 Subject: [PATCH 2/2] add -force to init script add simulation script --- code/init_prj.tcl | 22 ++++++++++++++++++---- code/sim_prj.tcl | 4 ++++ 2 files changed, 22 insertions(+), 4 deletions(-) diff --git a/code/init_prj.tcl b/code/init_prj.tcl index 6fb4d10..71e33a5 100644 --- a/code/init_prj.tcl +++ b/code/init_prj.tcl @@ -3,16 +3,30 @@ set project_name "MyProject" set project_directory "D:/GitHub/Tcl-Vivado/pl_project/$project_name" set top_module "top_level" set target_device "XC7A100TCSG324-1" +set language "VHDL" + + +# Overwrite or not if a project with the same name is already present in the folder +set force 1 # Create the project and directory structure setting up the board of interest #create_project -force -part XC7A100TCSG324-1 D:/GitHub/Tcl-Vivado/pl_project -create_project $project_name $project_directory -part $target_device +if {$force} { + create_project -force $project_name $project_directory -part $target_device +} else { + create_project $project_name $project_directory -part $target_device +} # Add various sources (no copy) to the project: sources, testbenches, constraint/s files -add_files {D:/GitHub/Tcl-Vivado/code/src/} +# Add all file of the folder src/ +add_files {D:/GitHub/Tcl-Vivado/code/src/} + +# Add all file of the folder sim/ add_files -fileset sim_1 {D:/GitHub/Tcl-Vivado/code/sim/} + +# Add specific file add_files -fileset constrs_1 D:/GitHub/Tcl-Vivado/code/xdc/Arty-A7-100-Master.xdc @@ -22,9 +36,9 @@ set_property top $top_module [current_fileset] # Set target language of current project, VHDL or Verilog # Project language -set_property target_language VHDL [current_project] +set_property target_language $language [current_project] # Simulator language -set_property simulator_language VHDL [current_project] +set_property simulator_language $language [current_project] diff --git a/code/sim_prj.tcl b/code/sim_prj.tcl index fab8b96..2e20e3e 100644 --- a/code/sim_prj.tcl +++ b/code/sim_prj.tcl @@ -2,10 +2,14 @@ set selected_simulator XSim set top_module_sim "adder_tb" + +# Set module to simulate set_property top $top_module_sim [get_filesets sim_1] +#Set target simulator set_property target_simulator $selected_simulator [current_project] +# Lunch simulation launch_simulation puts "Simulation launched with $selected_simulator."