{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":178278729,"defaultBranch":"main","name":"zephyr","ownerLogin":"MicrochipTech","currentUserCanPush":false,"isFork":true,"isEmpty":false,"createdAt":"2019-03-28T20:38:48.000Z","ownerAvatar":"https://avatars.githubusercontent.com/u/8910143?v=4","public":true,"private":false,"isOrgOwned":true},"refInfo":{"name":"","listCacheKey":"v0:1725049197.0","currentOid":""},"activityList":{"items":[{"before":"ebf786612845270c4a639edee18ce617197643e2","after":"7318df8a3aa33fa05f09b7f64601ccf51f3eed38","ref":"refs/heads/devel_mec5_all_updates","pushedAt":"2024-09-09T19:29:34.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"scottwcpg","name":"Scott Worley","path":"/scottwcpg","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/45947961?s=80&v=4"},"commit":{"message":"drivers: i2c: microchip: MEC5 I2C-NL disable driver debug\n\nTurn off all in driver debug capture, convert some log\nmessages to log debug category, and remove a some other\nredundant log messages.\nNOTE 1: With debug disabled driver passes test in the\ni2c target sample code for MCHP MEC5 MEC1753Q-LJ EVB.\nNOTE 2: Driver is still incomplete. Stuck bus detection\nand recovery needs to be implemented.\n\nSigned-off-by: Scott Worley ","shortMessageHtmlLink":"drivers: i2c: microchip: MEC5 I2C-NL disable driver debug"}},{"before":"63a5f14bd46d26dc9ee91a7049bd7ca9e9d1fb48","after":"ebf786612845270c4a639edee18ce617197643e2","ref":"refs/heads/devel_mec5_all_updates","pushedAt":"2024-09-09T18:17:56.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"scottwcpg","name":"Scott Worley","path":"/scottwcpg","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/45947961?s=80&v=4"},"commit":{"message":"drivers: i2c: microchip: MEC5 I2C-NL disable driver debug\n\nTurn off all in driver debug capture, convert some log\nmessages to log debug category, and remove a some other\nredundant log messages.\nNOTE 1: With debug disabled driver passes test in the\ni2c target sample code for MCHP MEC5 MEC1753Q-LJ EVB.\nNOTE 2: Driver is still incomplete. Stuck bus detection\nand recovery needs to be implemented.\n\nSigned-off-by: Scott Worley ","shortMessageHtmlLink":"drivers: i2c: microchip: MEC5 I2C-NL disable driver debug"}},{"before":"386263cc668b10a2546b93a2a3e7444d75b7b05d","after":"5032f099c64753d4a4fb858079ab57dbb22bb2cb","ref":"refs/heads/main","pushedAt":"2024-09-09T18:13:02.000Z","pushType":"push","commitsCount":598,"pusher":{"login":"scottwcpg","name":"Scott Worley","path":"/scottwcpg","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/45947961?s=80&v=4"},"commit":{"message":"drivers: sensor: add apds9253 driver\n\nAdd all the necessary files to add apds9253 Avago sensor driver.\n\nSensor available at https://docs.broadcom.com/doc/APDS-9253-001-DS\n\nSigned-off-by: Margherita Milani \nSigned-off-by: Michael Trimarchi ","shortMessageHtmlLink":"drivers: sensor: add apds9253 driver"}},{"before":"3a443afa34571591fecaaa50fef586eeae1ec41a","after":"63a5f14bd46d26dc9ee91a7049bd7ca9e9d1fb48","ref":"refs/heads/devel_mec5_all_updates","pushedAt":"2024-08-31T13:11:23.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"scottwcpg","name":"Scott Worley","path":"/scottwcpg","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/45947961?s=80&v=4"},"commit":{"message":"drivers: i2c: microchip: MEC5 I2C-NL disable driver debug\n\nTurn off all in driver debug capture, convert some log\nmessages to log debug category, and remove a some other\nredundant log messages.\nNOTE 1: With debug disabled driver passes test in the\ni2c target sample code for MCHP MEC5 MEC1753Q-LJ EVB.\nNOTE 2: Driver is still incomplete. Stuck bus detection\nand recovery needs to be implemented.\n\nSigned-off-by: Scott Worley ","shortMessageHtmlLink":"drivers: i2c: microchip: MEC5 I2C-NL disable driver debug"}},{"before":"eb33e4c0b79b2cfdb7abf4da62ea0e4c662e5442","after":"3a443afa34571591fecaaa50fef586eeae1ec41a","ref":"refs/heads/devel_mec5_all_updates","pushedAt":"2024-08-31T01:10:38.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"scottwcpg","name":"Scott Worley","path":"/scottwcpg","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/45947961?s=80&v=4"},"commit":{"message":"samples: boards: mchp_mec5: I2C target sample code test updates\n\nAdd tests for I2C combined write-read and write-write. Update\napplication test buffer handling for I2C write-write multiple\nbuffer write received callbacks in one START-to-STOP transaction.\nAll tests passing using I2C_0 with the MEC5 byte-by-byte driver\nas the external controller and I2C_1 with I2C-NL driver as the\ntarget.\n\nSigned-off-by: Scott Worley ","shortMessageHtmlLink":"samples: boards: mchp_mec5: I2C target sample code test updates"}},{"before":"459b299ab1d5fdc04a221978e683bf993098bd99","after":"eb33e4c0b79b2cfdb7abf4da62ea0e4c662e5442","ref":"refs/heads/devel_mec5_all_updates","pushedAt":"2024-08-31T00:50:12.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"scottwcpg","name":"Scott Worley","path":"/scottwcpg","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/45947961?s=80&v=4"},"commit":{"message":"drivers: dma: microchip: mec5: No IRQ handlers for reserved channels\n\nSecond part of support for DMA controller channel mask DT property.\nThe driver should should not install and enable interrupt handlers\nfor reserved channels. I could not find a way to parse the bit mask\nusing DT LISTIFY or FOR_EACH macros. Microchip MEC parts only have\none instance of the central DMA controller with different number\nof channels. We used simple macro logic to install channel handlers.\n\nSigned-off-by: Scott Worley ","shortMessageHtmlLink":"drivers: dma: microchip: mec5: No IRQ handlers for reserved channels"}},{"before":null,"after":"f230ef866952a7e9c2f28d2fb0961ee11723c924","ref":"refs/heads/mchp_mec5_gpio_driver","pushedAt":"2024-08-30T20:19:57.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"scottwcpg","name":"Scott Worley","path":"/scottwcpg","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/45947961?s=80&v=4"},"commit":{"message":"drivers: gpio: mec5: Microchip MEC5 HAL based GPIO driver\n\nAdd a GPIO driver for the Microchip MEC5 HAL based chips.\nCurrent devices are: MEC174x, MEC175x, and HAL version of\nMEC172x named MECH172x.\n\nSigned-off-by: Scott Worley ","shortMessageHtmlLink":"drivers: gpio: mec5: Microchip MEC5 HAL based GPIO driver"}},{"before":"29fa0162abf58cb48651ff7ec884d8b97c08cb5d","after":"2f0b914353063cd41e4baada253764807bb6882c","ref":"refs/heads/devel_mec5_i2c_nl5","pushedAt":"2024-08-30T18:55:46.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"scottwcpg","name":"Scott Worley","path":"/scottwcpg","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/45947961?s=80&v=4"},"commit":{"message":"samples: boards: mchp_mec5: I2C target sample code test updates\n\nAdd tests for I2C combined write-read and write-write. Update\napplication test buffer handling for I2C write-write multiple\nbuffer write received callbacks in one START-to-STOP transaction.\nAll tests passing using I2C_0 with the MEC5 byte-by-byte driver\nas the external controller and I2C_1 with I2C-NL driver as the\ntarget.\n\nSigned-off-by: Scott Worley ","shortMessageHtmlLink":"samples: boards: mchp_mec5: I2C target sample code test updates"}},{"before":null,"after":"29fa0162abf58cb48651ff7ec884d8b97c08cb5d","ref":"refs/heads/devel_mec5_i2c_nl5","pushedAt":"2024-08-28T21:57:26.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"scottwcpg","name":"Scott Worley","path":"/scottwcpg","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/45947961?s=80&v=4"},"commit":{"message":"samples: boards: mchp_mec5: I2C target mode sample for testing I2C-NL\n\nI2C target sample application used to test the under development\nI2C network layer plus DMA driver.\n\nSigned-off-by: Scott Worley ","shortMessageHtmlLink":"samples: boards: mchp_mec5: I2C target mode sample for testing I2C-NL"}},{"before":"ec4e770d06be68a01f4f9163ebeea3499aab28ec","after":"459b299ab1d5fdc04a221978e683bf993098bd99","ref":"refs/heads/devel_mec5_all_updates","pushedAt":"2024-08-28T14:00:26.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"scottwcpg","name":"Scott Worley","path":"/scottwcpg","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/45947961?s=80&v=4"},"commit":{"message":"drivers: dma: microchip: mec5: No IRQ handlers for reserved channels\n\nSecond part of support for DMA controller channel mask DT property.\nThe driver should should not install and enable interrupt handlers\nfor reserved channels. I could not find a way to parse the bit mask\nusing DT LISTIFY or FOR_EACH macros. Microchip MEC parts only have\none instance of the central DMA controller with different number\nof channels. We used simple macro logic to install channel handlers.\n\nSigned-off-by: Scott Worley ","shortMessageHtmlLink":"drivers: dma: microchip: mec5: No IRQ handlers for reserved channels"}},{"before":"858a68705294a27c41392bdae88a1f95a7e8fdea","after":"386263cc668b10a2546b93a2a3e7444d75b7b05d","ref":"refs/heads/main","pushedAt":"2024-08-28T13:52:37.000Z","pushType":"push","commitsCount":819,"pusher":{"login":"scottwcpg","name":"Scott Worley","path":"/scottwcpg","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/45947961?s=80&v=4"},"commit":{"message":"manifest: Update hostap to latest\n\nUpdate hostap repo to latest in west.yml\n\nSigned-off-by: Hui Bai ","shortMessageHtmlLink":"manifest: Update hostap to latest"}},{"before":"1f01c33ecc7ced02bd90aa61f16a629e387036fb","after":"ec4e770d06be68a01f4f9163ebeea3499aab28ec","ref":"refs/heads/devel_mec5_all_updates","pushedAt":"2024-08-14T12:54:13.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"scottwcpg","name":"Scott Worley","path":"/scottwcpg","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/45947961?s=80&v=4"},"commit":{"message":"drivers: dma: microchip: mec5: No IRQ handlers for reserved channels\n\nSecond part of support for DMA controller channel mask DT property.\nThe driver should should not install and enable interrupt handlers\nfor reserved channels. I could not find a way to parse the bit mask\nusing DT LISTIFY or FOR_EACH macros. Microchip MEC parts only have\none instance of the central DMA controller with different number\nof channels. We used simple macro logic to install channel handlers.\n\nSigned-off-by: Scott Worley ","shortMessageHtmlLink":"drivers: dma: microchip: mec5: No IRQ handlers for reserved channels"}},{"before":"5305aa615b0f800508e253c3398712eca1b209b4","after":"858a68705294a27c41392bdae88a1f95a7e8fdea","ref":"refs/heads/main","pushedAt":"2024-08-14T12:45:33.000Z","pushType":"push","commitsCount":482,"pusher":{"login":"scottwcpg","name":"Scott Worley","path":"/scottwcpg","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/45947961?s=80&v=4"},"commit":{"message":"manifest: update percepio\n\nUpdate the percepio module to use TraceRecorder v4.9.2.hotfix1\n\nSigned-off-by: Erik Tamlin ","shortMessageHtmlLink":"manifest: update percepio"}},{"before":"1c0132923122993dea9d09c35a4d3f9cff261a2b","after":"1f01c33ecc7ced02bd90aa61f16a629e387036fb","ref":"refs/heads/devel_mec5_all_updates","pushedAt":"2024-08-06T14:42:30.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"scottwcpg","name":"Scott Worley","path":"/scottwcpg","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/45947961?s=80&v=4"},"commit":{"message":"drivers: dma: microchip: mec5: No IRQ handlers for reserved channels\n\nSecond part of support for DMA controller channel mask DT property.\nThe driver should should not install and enable interrupt handlers\nfor reserved channels. I could not find a way to parse the bit mask\nusing DT LISTIFY or FOR_EACH macros. Microchip MEC parts only have\none instance of the central DMA controller with different number\nof channels. We used simple macro logic to install channel handlers.\n\nSigned-off-by: Scott Worley ","shortMessageHtmlLink":"drivers: dma: microchip: mec5: No IRQ handlers for reserved channels"}},{"before":"0fc74030d690847e41b8d471c28b373eca793cc2","after":"08ef9cf263afb052cc7304b41034a5d4790a8184","ref":"refs/heads/devel_mec5_i2c_nl4","pushedAt":"2024-08-06T14:42:15.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"scottwcpg","name":"Scott Worley","path":"/scottwcpg","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/45947961?s=80&v=4"},"commit":{"message":"samples: boards: mchp_mec5: I2C target mode sample\n\nIn progress sample code to exercise I2C-NL target mode.\nDMA channels 2 and 3 are reserved for I2C-NL using i2c_smb_1\ncontroller.\n\nSigned-off-by: Scott Worley ","shortMessageHtmlLink":"samples: boards: mchp_mec5: I2C target mode sample"}},{"before":"5d502e1d0e3cce149a97771a442204a8c7ae7284","after":"1c0132923122993dea9d09c35a4d3f9cff261a2b","ref":"refs/heads/devel_mec5_all_updates","pushedAt":"2024-08-06T14:33:37.000Z","pushType":"push","commitsCount":3,"pusher":{"login":"scottwcpg","name":"Scott Worley","path":"/scottwcpg","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/45947961?s=80&v=4"},"commit":{"message":"drivers: dma: microchip: mec5: Implement DT DMA channel mask support\n\nZephyr has DMA channel mask defined in the controller common\nproperties. We implement support for channel mask allowing\nchannels to be reserved. Reserved channels may be used by\ndrivers requiring precise DMA configuration and control\nusing the HAL directly.\n\nSigned-off-by: Scott Worley ","shortMessageHtmlLink":"drivers: dma: microchip: mec5: Implement DT DMA channel mask support"}},{"before":"8c61b82b90ae8d779ba2f8f62f6954cddfd12725","after":"5d502e1d0e3cce149a97771a442204a8c7ae7284","ref":"refs/heads/devel_mec5_all_updates","pushedAt":"2024-08-05T20:07:28.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"scottwcpg","name":"Scott Worley","path":"/scottwcpg","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/45947961?s=80&v=4"},"commit":{"message":"drivers: dma: microchip: Update central DMA driver PM support\n\nThe Microchip central DMA unit implements multiple channels.\nThis creates a problem for power management as threads could\nbe using different channels. In addition there is the issue\nof the application buiding with PM=y and PM_DEVICE=n versus\nPM=y and PM_DEVICE=y. For the multiple channel issue we add\nan atomic in use flag for each channel the is set when the\nchannel is started and cleared by the ISR when the channel\nis finished processing all blocks. For PM=y and PM_DEVICE=n\nwe build support in the driver to get a pointer to the PM\nstate table. When the in use atomic flag is set on channel\nstart we set the PM lock for power states from standby to\nall lower states implemented in the build. When all channels\nare finished we clear these locks. For PM=y and PM_DEVICE=y\nthe driver has a single atomic flag in its device structure.\nWe set this flag for any channel being started. When all\nchannels are done we clear the driver PM flag. Note, PM flags\nare manipulated using PM subsystem calls.\n\nSigned-off-by: Scott Worley ","shortMessageHtmlLink":"drivers: dma: microchip: Update central DMA driver PM support"}},{"before":"3f3ff5fb0c120ca760e87f128bba52f77099d18d","after":"d6b75df4da258a05c7b3cf9d31872c4ce337430c","ref":"refs/heads/devel_mec5_all","pushedAt":"2024-08-05T20:07:09.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"scottwcpg","name":"Scott Worley","path":"/scottwcpg","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/45947961?s=80&v=4"},"commit":{"message":"boards: microchip: mec_assy6941 Enable BBRAM driver\n\nEnable the BBRAM driver for all board variants of Microchip\nassembly 6941 EVB targetting MEC5 HAL MEC1743 and MEC1753.\n\nSigned-off-by: Scott Worley ","shortMessageHtmlLink":"boards: microchip: mec_assy6941 Enable BBRAM driver"}},{"before":"f8f4c6b9673f7cf306c737b804304adc59063ec8","after":"0fc74030d690847e41b8d471c28b373eca793cc2","ref":"refs/heads/devel_mec5_i2c_nl4","pushedAt":"2024-08-05T20:06:48.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"scottwcpg","name":"Scott Worley","path":"/scottwcpg","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/45947961?s=80&v=4"},"commit":{"message":"drivers: dma: microchip: mec5: No IRQ handlers for reserved channels\n\nSecond part of support for DMA controller channel mask DT property.\nThe driver should should not install and enable interrupt handlers\nfor reserved channels. I could not find a way to parse the bit mask\nusing DT LISTIFY or FOR_EACH macros. Microchip MEC parts only have\none instance of the central DMA controller with different number\nof channels. We used simple macro logic to install channel handlers.\n\nSigned-off-by: Scott Worley ","shortMessageHtmlLink":"drivers: dma: microchip: mec5: No IRQ handlers for reserved channels"}},{"before":"ac52bd629d705811858c8bb38ca7a43e4e81182b","after":"5305aa615b0f800508e253c3398712eca1b209b4","ref":"refs/heads/main","pushedAt":"2024-08-05T14:06:01.000Z","pushType":"push","commitsCount":583,"pusher":{"login":"scottwcpg","name":"Scott Worley","path":"/scottwcpg","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/45947961?s=80&v=4"},"commit":{"message":"samples: drivers: counter: alarm: enable on s32z2xxdc2\n\nEnable alarm sample on s32z2xxdc2 boards.\n\nSigned-off-by: Manuel Argüelles ","shortMessageHtmlLink":"samples: drivers: counter: alarm: enable on s32z2xxdc2"}},{"before":null,"after":"f8f4c6b9673f7cf306c737b804304adc59063ec8","ref":"refs/heads/devel_mec5_i2c_nl4","pushedAt":"2024-07-21T19:14:38.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"scottwcpg","name":"Scott Worley","path":"/scottwcpg","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/45947961?s=80&v=4"},"commit":{"message":"drivers: dma: microchip: mec5: No IRQ handlers for reserved channels\n\nSecond part of support for DMA controller channel mask DT property.\nThe driver should should not install and enable interrupt handlers\nfor reserved channels. I could not find a way to parse the bit mask\nusing DT LISTIFY or FOR_EACH macros. Microchip MEC parts only have\none instance of the central DMA controller with different number\nof channels. We used simple macro logic to install channel handlers.\n\nSigned-off-by: Scott Worley ","shortMessageHtmlLink":"drivers: dma: microchip: mec5: No IRQ handlers for reserved channels"}},{"before":"4f424c03c118eae88a66a8b7169d3fc6488f32f7","after":"b1ac37c2188b50b502f2adb6751dab7582017367","ref":"refs/heads/devel_mec5_i2c_nl3","pushedAt":"2024-07-21T13:27:44.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"scottwcpg","name":"Scott Worley","path":"/scottwcpg","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/45947961?s=80&v=4"},"commit":{"message":"drivers: i2c: microchip: mec5: I2C-NL driver development is BROKEN\n\nBROKEN DRIVER. DO NOT USE.\nCommit is for recording current broken development state while I'm\non vacation.\nHW race conditions between I2C-NL and DMA cannot be solved with\nseparate drivers for each one.\nThis branch is DEAD.\n\nSigned-off-by: Scott Worley ","shortMessageHtmlLink":"drivers: i2c: microchip: mec5: I2C-NL driver development is BROKEN"}},{"before":"9d14f8212b282c593f6f075ece0896c4c26ace05","after":"4f424c03c118eae88a66a8b7169d3fc6488f32f7","ref":"refs/heads/devel_mec5_i2c_nl3","pushedAt":"2024-07-19T22:21:43.000Z","pushType":"push","commitsCount":5,"pusher":{"login":"scottwcpg","name":"Scott Worley","path":"/scottwcpg","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/45947961?s=80&v=4"},"commit":{"message":"samples: boards: mchp_mec5: I2C target sample code experiments\n\nMore experiments trying and failing to get I2C-NL target mode to\nwork. Using interrupt from both I2C-NL and DMA driver are not\ngoing to work. The order the interrupts occur in depends on\ndata direction, number of bytes transferred, driver buffer size,\nand the I2C protocol used.\n\nSigned-off-by: Scott Worley ","shortMessageHtmlLink":"samples: boards: mchp_mec5: I2C target sample code experiments"}},{"before":"31c575d8e072b78bb9e752c5ecf2ac7ff53696a6","after":"8c61b82b90ae8d779ba2f8f62f6954cddfd12725","ref":"refs/heads/devel_mec5_all_updates","pushedAt":"2024-07-19T02:28:06.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"scottwcpg","name":"Scott Worley","path":"/scottwcpg","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/45947961?s=80&v=4"},"commit":{"message":"drivers: dma: microchip: Update central DMA driver PM support\n\nThe Microchip central DMA unit implements multiple channels.\nThis creates a problem for power management as threads could\nbe using different channels. In addition there is the issue\nof the application buiding with PM=y and PM_DEVICE=n versus\nPM=y and PM_DEVICE=y. For the multiple channel issue we add\nan atomic in use flag for each channel the is set when the\nchannel is started and cleared by the ISR when the channel\nis finished processing all blocks. For PM=y and PM_DEVICE=n\nwe build support in the driver to get a pointer to the PM\nstate table. When the in use atomic flag is set on channel\nstart we set the PM lock for power states from standby to\nall lower states implemented in the build. When all channels\nare finished we clear these locks. For PM=y and PM_DEVICE=y\nthe driver has a single atomic flag in its device structure.\nWe set this flag for any channel being started. When all\nchannels are done we clear the driver PM flag. Note, PM flags\nare manipulated using PM subsystem calls.\n\nSigned-off-by: Scott Worley ","shortMessageHtmlLink":"drivers: dma: microchip: Update central DMA driver PM support"}},{"before":"cdf254ec8f9e77068a08342b815bee0d8d3dace0","after":"3f3ff5fb0c120ca760e87f128bba52f77099d18d","ref":"refs/heads/devel_mec5_all","pushedAt":"2024-07-19T02:27:30.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"scottwcpg","name":"Scott Worley","path":"/scottwcpg","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/45947961?s=80&v=4"},"commit":{"message":"boards: microchip: mec_assy6941 Enable BBRAM driver\n\nEnable the BBRAM driver for all board variants of Microchip\nassembly 6941 EVB targetting MEC5 HAL MEC1743 and MEC1753.\n\nSigned-off-by: Scott Worley ","shortMessageHtmlLink":"boards: microchip: mec_assy6941 Enable BBRAM driver"}},{"before":"4b7f86577301cc6f9a4b66d8d0397bd4f6aa4932","after":"9d14f8212b282c593f6f075ece0896c4c26ace05","ref":"refs/heads/devel_mec5_i2c_nl3","pushedAt":"2024-07-19T02:26:32.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"scottwcpg","name":"Scott Worley","path":"/scottwcpg","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/45947961?s=80&v=4"},"commit":{"message":"samples: boards: mchp_mec5: I2C target mode sample\n\nDNM (DO NOT MERGE). EXPERIMENTAL.\nSample application for Microchip MEC5 evaluation board demonstrating\nI2C network layer driver using DMA. Initial target mode I2C write\nhas been added.\n\nSigned-off-by: Scott Worley ","shortMessageHtmlLink":"samples: boards: mchp_mec5: I2C target mode sample"}},{"before":"768b8bbca30ab78f2fed33272b695434288727d3","after":"ac52bd629d705811858c8bb38ca7a43e4e81182b","ref":"refs/heads/main","pushedAt":"2024-07-19T02:25:06.000Z","pushType":"push","commitsCount":519,"pusher":{"login":"scottwcpg","name":"Scott Worley","path":"/scottwcpg","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/45947961?s=80&v=4"},"commit":{"message":"posix: deprecated: remove new options without deprecation\n\nA few previously deprecated Kconfig options have not yet been\npresent for 1 release cycle and can (theoretically) just be\nremoved, without deprecation (see next commit).\n\n* GETENTROPY\n* POSIX_CONFSTR\n* POSIX_ENV\n* POSIX_SYSLOG\n\nFor dependency information, please see\nhttps://docs.zephyrproject.org/3.6.0/kconfig.html#kconfig-search\n\nSigned-off-by: Chris Friedt ","shortMessageHtmlLink":"posix: deprecated: remove new options without deprecation"}},{"before":"50004e19882850453d50967779349e6de754bd08","after":"31c575d8e072b78bb9e752c5ecf2ac7ff53696a6","ref":"refs/heads/devel_mec5_all_updates","pushedAt":"2024-07-09T19:20:58.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"scottwcpg","name":"Scott Worley","path":"/scottwcpg","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/45947961?s=80&v=4"},"commit":{"message":"samples: drivers: mec5_led: Sample for Microchip MEC5 LED driver\n\nSample project demonstrating LED driver and the extended API\nfor LED HW breathing mode of the Microchip breathing-blinking\nLED peripheral.\n\nSigned-off-by: Scott Worley ","shortMessageHtmlLink":"samples: drivers: mec5_led: Sample for Microchip MEC5 LED driver"}},{"before":"7b1e0f66dbefa1af67c3a13e4ebfcf52bd1ecf1e","after":"50004e19882850453d50967779349e6de754bd08","ref":"refs/heads/devel_mec5_all_updates","pushedAt":"2024-07-09T15:55:53.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"scottwcpg","name":"Scott Worley","path":"/scottwcpg","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/45947961?s=80&v=4"},"commit":{"message":"tests: drivers: counter: Add Microchip MEC1753Q-LJ to basic API test\n\nAdd board configuration and DTS overlay for Microchip MEC5 HAL based\nMEC1753Q-LJ (176-pin) package variant to counter driver basic API test.\n\nSigned-off-by: Scott Worley ","shortMessageHtmlLink":"tests: drivers: counter: Add Microchip MEC1753Q-LJ to basic API test"}},{"before":"b830c2c91750073023d088c5c77986a134804d73","after":"7b1e0f66dbefa1af67c3a13e4ebfcf52bd1ecf1e","ref":"refs/heads/devel_mec5_all_updates","pushedAt":"2024-07-09T15:53:17.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"scottwcpg","name":"Scott Worley","path":"/scottwcpg","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/45947961?s=80&v=4"},"commit":{"message":"tests: drivers: counter: Fix misplaced endif causing MCHP MEC failures\n\nA misplaced macro endif was causing Microchip MEC5 drivers from being\nbuilt resulting in all tests failing.\n\nSigned-off-by: Scott Worley ","shortMessageHtmlLink":"tests: drivers: counter: Fix misplaced endif causing MCHP MEC failures"}}],"hasNextPage":true,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"cursor":"djE6ks8AAAAEsUhcOAA","startCursor":null,"endCursor":null}},"title":"Activity · MicrochipTech/zephyr"}